1 /************************************************************************** 2 3 Copyright (c) 2007, Chelsio Inc. 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Neither the name of the Chelsio Corporation nor the names of its 13 contributors may be used to endorse or promote products derived from 14 this software without specific prior written permission. 15 16 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 20 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 POSSIBILITY OF SUCH DAMAGE. 27 28 $FreeBSD$ 29 30 ***************************************************************************/ 31 32 /* This file is automatically generated --- do not edit */ 33 34 #ifndef _TCB_DEFS_H 35 #define _TCB_DEFS_H 36 37 #define W_TCB_T_STATE 0 38 #define S_TCB_T_STATE 0 39 #define M_TCB_T_STATE 0xfULL 40 #define V_TCB_T_STATE(x) ((x) << S_TCB_T_STATE) 41 42 #define W_TCB_TIMER 0 43 #define S_TCB_TIMER 4 44 #define M_TCB_TIMER 0x1ULL 45 #define V_TCB_TIMER(x) ((x) << S_TCB_TIMER) 46 47 #define W_TCB_DACK_TIMER 0 48 #define S_TCB_DACK_TIMER 5 49 #define M_TCB_DACK_TIMER 0x1ULL 50 #define V_TCB_DACK_TIMER(x) ((x) << S_TCB_DACK_TIMER) 51 52 #define W_TCB_DEL_FLAG 0 53 #define S_TCB_DEL_FLAG 6 54 #define M_TCB_DEL_FLAG 0x1ULL 55 #define V_TCB_DEL_FLAG(x) ((x) << S_TCB_DEL_FLAG) 56 57 #define W_TCB_L2T_IX 0 58 #define S_TCB_L2T_IX 7 59 #define M_TCB_L2T_IX 0x7ffULL 60 #define V_TCB_L2T_IX(x) ((x) << S_TCB_L2T_IX) 61 62 #define W_TCB_SMAC_SEL 0 63 #define S_TCB_SMAC_SEL 18 64 #define M_TCB_SMAC_SEL 0x3ULL 65 #define V_TCB_SMAC_SEL(x) ((x) << S_TCB_SMAC_SEL) 66 67 #define W_TCB_TOS 0 68 #define S_TCB_TOS 20 69 #define M_TCB_TOS 0x3fULL 70 #define V_TCB_TOS(x) ((x) << S_TCB_TOS) 71 72 #define W_TCB_MAX_RT 0 73 #define S_TCB_MAX_RT 26 74 #define M_TCB_MAX_RT 0xfULL 75 #define V_TCB_MAX_RT(x) ((x) << S_TCB_MAX_RT) 76 77 #define W_TCB_T_RXTSHIFT 0 78 #define S_TCB_T_RXTSHIFT 30 79 #define M_TCB_T_RXTSHIFT 0xfULL 80 #define V_TCB_T_RXTSHIFT(x) ((x) << S_TCB_T_RXTSHIFT) 81 82 #define W_TCB_T_DUPACKS 1 83 #define S_TCB_T_DUPACKS 2 84 #define M_TCB_T_DUPACKS 0xfULL 85 #define V_TCB_T_DUPACKS(x) ((x) << S_TCB_T_DUPACKS) 86 87 #define W_TCB_T_MAXSEG 1 88 #define S_TCB_T_MAXSEG 6 89 #define M_TCB_T_MAXSEG 0xfULL 90 #define V_TCB_T_MAXSEG(x) ((x) << S_TCB_T_MAXSEG) 91 92 #define W_TCB_T_FLAGS1 1 93 #define S_TCB_T_FLAGS1 10 94 #define M_TCB_T_FLAGS1 0xffffffffULL 95 #define V_TCB_T_FLAGS1(x) ((x) << S_TCB_T_FLAGS1) 96 97 #define W_TCB_T_FLAGS2 2 98 #define S_TCB_T_FLAGS2 10 99 #define M_TCB_T_FLAGS2 0x7fULL 100 #define V_TCB_T_FLAGS2(x) ((x) << S_TCB_T_FLAGS2) 101 102 #define W_TCB_SND_SCALE 2 103 #define S_TCB_SND_SCALE 17 104 #define M_TCB_SND_SCALE 0xfULL 105 #define V_TCB_SND_SCALE(x) ((x) << S_TCB_SND_SCALE) 106 107 #define W_TCB_RCV_SCALE 2 108 #define S_TCB_RCV_SCALE 21 109 #define M_TCB_RCV_SCALE 0xfULL 110 #define V_TCB_RCV_SCALE(x) ((x) << S_TCB_RCV_SCALE) 111 112 #define W_TCB_SND_UNA_RAW 2 113 #define S_TCB_SND_UNA_RAW 25 114 #define M_TCB_SND_UNA_RAW 0x7ffffffULL 115 #define V_TCB_SND_UNA_RAW(x) ((x) << S_TCB_SND_UNA_RAW) 116 117 #define W_TCB_SND_NXT_RAW 3 118 #define S_TCB_SND_NXT_RAW 20 119 #define M_TCB_SND_NXT_RAW 0x7ffffffULL 120 #define V_TCB_SND_NXT_RAW(x) ((x) << S_TCB_SND_NXT_RAW) 121 122 #define W_TCB_RCV_NXT 4 123 #define S_TCB_RCV_NXT 15 124 #define M_TCB_RCV_NXT 0xffffffffULL 125 #define V_TCB_RCV_NXT(x) ((x) << S_TCB_RCV_NXT) 126 127 #define W_TCB_RCV_ADV 5 128 #define S_TCB_RCV_ADV 15 129 #define M_TCB_RCV_ADV 0xffffULL 130 #define V_TCB_RCV_ADV(x) ((x) << S_TCB_RCV_ADV) 131 132 #define W_TCB_SND_MAX_RAW 5 133 #define S_TCB_SND_MAX_RAW 31 134 #define M_TCB_SND_MAX_RAW 0x7ffffffULL 135 #define V_TCB_SND_MAX_RAW(x) ((x) << S_TCB_SND_MAX_RAW) 136 137 #define W_TCB_SND_CWND 6 138 #define S_TCB_SND_CWND 26 139 #define M_TCB_SND_CWND 0x7ffffffULL 140 #define V_TCB_SND_CWND(x) ((x) << S_TCB_SND_CWND) 141 142 #define W_TCB_SND_SSTHRESH 7 143 #define S_TCB_SND_SSTHRESH 21 144 #define M_TCB_SND_SSTHRESH 0x7ffffffULL 145 #define V_TCB_SND_SSTHRESH(x) ((x) << S_TCB_SND_SSTHRESH) 146 147 #define W_TCB_T_RTT_TS_RECENT_AGE 8 148 #define S_TCB_T_RTT_TS_RECENT_AGE 16 149 #define M_TCB_T_RTT_TS_RECENT_AGE 0xffffffffULL 150 #define V_TCB_T_RTT_TS_RECENT_AGE(x) ((x) << S_TCB_T_RTT_TS_RECENT_AGE) 151 152 #define W_TCB_T_RTSEQ_RECENT 9 153 #define S_TCB_T_RTSEQ_RECENT 16 154 #define M_TCB_T_RTSEQ_RECENT 0xffffffffULL 155 #define V_TCB_T_RTSEQ_RECENT(x) ((x) << S_TCB_T_RTSEQ_RECENT) 156 157 #define W_TCB_T_SRTT 10 158 #define S_TCB_T_SRTT 16 159 #define M_TCB_T_SRTT 0xffffULL 160 #define V_TCB_T_SRTT(x) ((x) << S_TCB_T_SRTT) 161 162 #define W_TCB_T_RTTVAR 11 163 #define S_TCB_T_RTTVAR 0 164 #define M_TCB_T_RTTVAR 0xffffULL 165 #define V_TCB_T_RTTVAR(x) ((x) << S_TCB_T_RTTVAR) 166 167 #define W_TCB_TS_LAST_ACK_SENT_RAW 11 168 #define S_TCB_TS_LAST_ACK_SENT_RAW 16 169 #define M_TCB_TS_LAST_ACK_SENT_RAW 0x7ffffffULL 170 #define V_TCB_TS_LAST_ACK_SENT_RAW(x) ((x) << S_TCB_TS_LAST_ACK_SENT_RAW) 171 172 #define W_TCB_DIP 12 173 #define S_TCB_DIP 11 174 #define M_TCB_DIP 0xffffffffULL 175 #define V_TCB_DIP(x) ((x) << S_TCB_DIP) 176 177 #define W_TCB_SIP 13 178 #define S_TCB_SIP 11 179 #define M_TCB_SIP 0xffffffffULL 180 #define V_TCB_SIP(x) ((x) << S_TCB_SIP) 181 182 #define W_TCB_DP 14 183 #define S_TCB_DP 11 184 #define M_TCB_DP 0xffffULL 185 #define V_TCB_DP(x) ((x) << S_TCB_DP) 186 187 #define W_TCB_SP 14 188 #define S_TCB_SP 27 189 #define M_TCB_SP 0xffffULL 190 #define V_TCB_SP(x) ((x) << S_TCB_SP) 191 192 #define W_TCB_TIMESTAMP 15 193 #define S_TCB_TIMESTAMP 11 194 #define M_TCB_TIMESTAMP 0xffffffffULL 195 #define V_TCB_TIMESTAMP(x) ((x) << S_TCB_TIMESTAMP) 196 197 #define W_TCB_TIMESTAMP_OFFSET 16 198 #define S_TCB_TIMESTAMP_OFFSET 11 199 #define M_TCB_TIMESTAMP_OFFSET 0xfULL 200 #define V_TCB_TIMESTAMP_OFFSET(x) ((x) << S_TCB_TIMESTAMP_OFFSET) 201 202 #define W_TCB_TX_MAX 16 203 #define S_TCB_TX_MAX 15 204 #define M_TCB_TX_MAX 0xffffffffULL 205 #define V_TCB_TX_MAX(x) ((x) << S_TCB_TX_MAX) 206 207 #define W_TCB_TX_HDR_PTR_RAW 17 208 #define S_TCB_TX_HDR_PTR_RAW 15 209 #define M_TCB_TX_HDR_PTR_RAW 0x1ffffULL 210 #define V_TCB_TX_HDR_PTR_RAW(x) ((x) << S_TCB_TX_HDR_PTR_RAW) 211 212 #define W_TCB_TX_LAST_PTR_RAW 18 213 #define S_TCB_TX_LAST_PTR_RAW 0 214 #define M_TCB_TX_LAST_PTR_RAW 0x1ffffULL 215 #define V_TCB_TX_LAST_PTR_RAW(x) ((x) << S_TCB_TX_LAST_PTR_RAW) 216 217 #define W_TCB_TX_COMPACT 18 218 #define S_TCB_TX_COMPACT 17 219 #define M_TCB_TX_COMPACT 0x1ULL 220 #define V_TCB_TX_COMPACT(x) ((x) << S_TCB_TX_COMPACT) 221 222 #define W_TCB_RX_COMPACT 18 223 #define S_TCB_RX_COMPACT 18 224 #define M_TCB_RX_COMPACT 0x1ULL 225 #define V_TCB_RX_COMPACT(x) ((x) << S_TCB_RX_COMPACT) 226 227 #define W_TCB_RCV_WND 18 228 #define S_TCB_RCV_WND 19 229 #define M_TCB_RCV_WND 0x7ffffffULL 230 #define V_TCB_RCV_WND(x) ((x) << S_TCB_RCV_WND) 231 232 #define W_TCB_RX_HDR_OFFSET 19 233 #define S_TCB_RX_HDR_OFFSET 14 234 #define M_TCB_RX_HDR_OFFSET 0x7ffffffULL 235 #define V_TCB_RX_HDR_OFFSET(x) ((x) << S_TCB_RX_HDR_OFFSET) 236 237 #define W_TCB_RX_FRAG0_START_IDX_RAW 20 238 #define S_TCB_RX_FRAG0_START_IDX_RAW 9 239 #define M_TCB_RX_FRAG0_START_IDX_RAW 0x7ffffffULL 240 #define V_TCB_RX_FRAG0_START_IDX_RAW(x) ((x) << S_TCB_RX_FRAG0_START_IDX_RAW) 241 242 #define W_TCB_RX_FRAG1_START_IDX_OFFSET 21 243 #define S_TCB_RX_FRAG1_START_IDX_OFFSET 4 244 #define M_TCB_RX_FRAG1_START_IDX_OFFSET 0x7ffffffULL 245 #define V_TCB_RX_FRAG1_START_IDX_OFFSET(x) ((x) << S_TCB_RX_FRAG1_START_IDX_OFFSET) 246 247 #define W_TCB_RX_FRAG0_LEN 21 248 #define S_TCB_RX_FRAG0_LEN 31 249 #define M_TCB_RX_FRAG0_LEN 0x7ffffffULL 250 #define V_TCB_RX_FRAG0_LEN(x) ((x) << S_TCB_RX_FRAG0_LEN) 251 252 #define W_TCB_RX_FRAG1_LEN 22 253 #define S_TCB_RX_FRAG1_LEN 26 254 #define M_TCB_RX_FRAG1_LEN 0x7ffffffULL 255 #define V_TCB_RX_FRAG1_LEN(x) ((x) << S_TCB_RX_FRAG1_LEN) 256 257 #define W_TCB_NEWRENO_RECOVER 23 258 #define S_TCB_NEWRENO_RECOVER 21 259 #define M_TCB_NEWRENO_RECOVER 0x7ffffffULL 260 #define V_TCB_NEWRENO_RECOVER(x) ((x) << S_TCB_NEWRENO_RECOVER) 261 262 #define W_TCB_PDU_HAVE_LEN 24 263 #define S_TCB_PDU_HAVE_LEN 16 264 #define M_TCB_PDU_HAVE_LEN 0x1ULL 265 #define V_TCB_PDU_HAVE_LEN(x) ((x) << S_TCB_PDU_HAVE_LEN) 266 267 #define W_TCB_PDU_LEN 24 268 #define S_TCB_PDU_LEN 17 269 #define M_TCB_PDU_LEN 0xffffULL 270 #define V_TCB_PDU_LEN(x) ((x) << S_TCB_PDU_LEN) 271 272 #define W_TCB_RX_QUIESCE 25 273 #define S_TCB_RX_QUIESCE 1 274 #define M_TCB_RX_QUIESCE 0x1ULL 275 #define V_TCB_RX_QUIESCE(x) ((x) << S_TCB_RX_QUIESCE) 276 277 #define W_TCB_RX_PTR_RAW 25 278 #define S_TCB_RX_PTR_RAW 2 279 #define M_TCB_RX_PTR_RAW 0x1ffffULL 280 #define V_TCB_RX_PTR_RAW(x) ((x) << S_TCB_RX_PTR_RAW) 281 282 #define W_TCB_CPU_NO 25 283 #define S_TCB_CPU_NO 19 284 #define M_TCB_CPU_NO 0x7fULL 285 #define V_TCB_CPU_NO(x) ((x) << S_TCB_CPU_NO) 286 287 #define W_TCB_ULP_TYPE 25 288 #define S_TCB_ULP_TYPE 26 289 #define M_TCB_ULP_TYPE 0xfULL 290 #define V_TCB_ULP_TYPE(x) ((x) << S_TCB_ULP_TYPE) 291 292 #define W_TCB_RX_FRAG1_PTR_RAW 25 293 #define S_TCB_RX_FRAG1_PTR_RAW 30 294 #define M_TCB_RX_FRAG1_PTR_RAW 0x1ffffULL 295 #define V_TCB_RX_FRAG1_PTR_RAW(x) ((x) << S_TCB_RX_FRAG1_PTR_RAW) 296 297 #define W_TCB_RX_FRAG2_START_IDX_OFFSET_RAW 26 298 #define S_TCB_RX_FRAG2_START_IDX_OFFSET_RAW 15 299 #define M_TCB_RX_FRAG2_START_IDX_OFFSET_RAW 0x7ffffffULL 300 #define V_TCB_RX_FRAG2_START_IDX_OFFSET_RAW(x) ((x) << S_TCB_RX_FRAG2_START_IDX_OFFSET_RAW) 301 302 #define W_TCB_RX_FRAG2_PTR_RAW 27 303 #define S_TCB_RX_FRAG2_PTR_RAW 10 304 #define M_TCB_RX_FRAG2_PTR_RAW 0x1ffffULL 305 #define V_TCB_RX_FRAG2_PTR_RAW(x) ((x) << S_TCB_RX_FRAG2_PTR_RAW) 306 307 #define W_TCB_RX_FRAG2_LEN_RAW 27 308 #define S_TCB_RX_FRAG2_LEN_RAW 27 309 #define M_TCB_RX_FRAG2_LEN_RAW 0x7ffffffULL 310 #define V_TCB_RX_FRAG2_LEN_RAW(x) ((x) << S_TCB_RX_FRAG2_LEN_RAW) 311 312 #define W_TCB_RX_FRAG3_PTR_RAW 28 313 #define S_TCB_RX_FRAG3_PTR_RAW 22 314 #define M_TCB_RX_FRAG3_PTR_RAW 0x1ffffULL 315 #define V_TCB_RX_FRAG3_PTR_RAW(x) ((x) << S_TCB_RX_FRAG3_PTR_RAW) 316 317 #define W_TCB_RX_FRAG3_LEN_RAW 29 318 #define S_TCB_RX_FRAG3_LEN_RAW 7 319 #define M_TCB_RX_FRAG3_LEN_RAW 0x7ffffffULL 320 #define V_TCB_RX_FRAG3_LEN_RAW(x) ((x) << S_TCB_RX_FRAG3_LEN_RAW) 321 322 #define W_TCB_RX_FRAG3_START_IDX_OFFSET_RAW 30 323 #define S_TCB_RX_FRAG3_START_IDX_OFFSET_RAW 2 324 #define M_TCB_RX_FRAG3_START_IDX_OFFSET_RAW 0x7ffffffULL 325 #define V_TCB_RX_FRAG3_START_IDX_OFFSET_RAW(x) ((x) << S_TCB_RX_FRAG3_START_IDX_OFFSET_RAW) 326 327 #define W_TCB_PDU_HDR_LEN 30 328 #define S_TCB_PDU_HDR_LEN 29 329 #define M_TCB_PDU_HDR_LEN 0xffULL 330 #define V_TCB_PDU_HDR_LEN(x) ((x) << S_TCB_PDU_HDR_LEN) 331 332 #define W_TCB_SLUSH1 31 333 #define S_TCB_SLUSH1 5 334 #define M_TCB_SLUSH1 0x7ffffULL 335 #define V_TCB_SLUSH1(x) ((x) << S_TCB_SLUSH1) 336 337 #define W_TCB_ULP_RAW 31 338 #define S_TCB_ULP_RAW 24 339 #define M_TCB_ULP_RAW 0xffULL 340 #define V_TCB_ULP_RAW(x) ((x) << S_TCB_ULP_RAW) 341 342 #define W_TCB_DDP_RDMAP_VERSION 25 343 #define S_TCB_DDP_RDMAP_VERSION 30 344 #define M_TCB_DDP_RDMAP_VERSION 0x1ULL 345 #define V_TCB_DDP_RDMAP_VERSION(x) ((x) << S_TCB_DDP_RDMAP_VERSION) 346 347 #define W_TCB_MARKER_ENABLE_RX 25 348 #define S_TCB_MARKER_ENABLE_RX 31 349 #define M_TCB_MARKER_ENABLE_RX 0x1ULL 350 #define V_TCB_MARKER_ENABLE_RX(x) ((x) << S_TCB_MARKER_ENABLE_RX) 351 352 #define W_TCB_MARKER_ENABLE_TX 26 353 #define S_TCB_MARKER_ENABLE_TX 0 354 #define M_TCB_MARKER_ENABLE_TX 0x1ULL 355 #define V_TCB_MARKER_ENABLE_TX(x) ((x) << S_TCB_MARKER_ENABLE_TX) 356 357 #define W_TCB_CRC_ENABLE 26 358 #define S_TCB_CRC_ENABLE 1 359 #define M_TCB_CRC_ENABLE 0x1ULL 360 #define V_TCB_CRC_ENABLE(x) ((x) << S_TCB_CRC_ENABLE) 361 362 #define W_TCB_IRS_ULP 26 363 #define S_TCB_IRS_ULP 2 364 #define M_TCB_IRS_ULP 0x1ffULL 365 #define V_TCB_IRS_ULP(x) ((x) << S_TCB_IRS_ULP) 366 367 #define W_TCB_ISS_ULP 26 368 #define S_TCB_ISS_ULP 11 369 #define M_TCB_ISS_ULP 0x1ffULL 370 #define V_TCB_ISS_ULP(x) ((x) << S_TCB_ISS_ULP) 371 372 #define W_TCB_TX_PDU_LEN 26 373 #define S_TCB_TX_PDU_LEN 20 374 #define M_TCB_TX_PDU_LEN 0x3fffULL 375 #define V_TCB_TX_PDU_LEN(x) ((x) << S_TCB_TX_PDU_LEN) 376 377 #define W_TCB_TX_PDU_OUT 27 378 #define S_TCB_TX_PDU_OUT 2 379 #define M_TCB_TX_PDU_OUT 0x1ULL 380 #define V_TCB_TX_PDU_OUT(x) ((x) << S_TCB_TX_PDU_OUT) 381 382 #define W_TCB_CQ_IDX_SQ 27 383 #define S_TCB_CQ_IDX_SQ 3 384 #define M_TCB_CQ_IDX_SQ 0xffffULL 385 #define V_TCB_CQ_IDX_SQ(x) ((x) << S_TCB_CQ_IDX_SQ) 386 387 #define W_TCB_CQ_IDX_RQ 27 388 #define S_TCB_CQ_IDX_RQ 19 389 #define M_TCB_CQ_IDX_RQ 0xffffULL 390 #define V_TCB_CQ_IDX_RQ(x) ((x) << S_TCB_CQ_IDX_RQ) 391 392 #define W_TCB_QP_ID 28 393 #define S_TCB_QP_ID 3 394 #define M_TCB_QP_ID 0xffffULL 395 #define V_TCB_QP_ID(x) ((x) << S_TCB_QP_ID) 396 397 #define W_TCB_PD_ID 28 398 #define S_TCB_PD_ID 19 399 #define M_TCB_PD_ID 0xffffULL 400 #define V_TCB_PD_ID(x) ((x) << S_TCB_PD_ID) 401 402 #define W_TCB_STAG 29 403 #define S_TCB_STAG 3 404 #define M_TCB_STAG 0xffffffffULL 405 #define V_TCB_STAG(x) ((x) << S_TCB_STAG) 406 407 #define W_TCB_RQ_START 30 408 #define S_TCB_RQ_START 3 409 #define M_TCB_RQ_START 0x3ffffffULL 410 #define V_TCB_RQ_START(x) ((x) << S_TCB_RQ_START) 411 412 #define W_TCB_RQ_MSN 30 413 #define S_TCB_RQ_MSN 29 414 #define M_TCB_RQ_MSN 0x3ffULL 415 #define V_TCB_RQ_MSN(x) ((x) << S_TCB_RQ_MSN) 416 417 #define W_TCB_RQ_MAX_OFFSET 31 418 #define S_TCB_RQ_MAX_OFFSET 7 419 #define M_TCB_RQ_MAX_OFFSET 0xfULL 420 #define V_TCB_RQ_MAX_OFFSET(x) ((x) << S_TCB_RQ_MAX_OFFSET) 421 422 #define W_TCB_RQ_WRITE_PTR 31 423 #define S_TCB_RQ_WRITE_PTR 11 424 #define M_TCB_RQ_WRITE_PTR 0x3ffULL 425 #define V_TCB_RQ_WRITE_PTR(x) ((x) << S_TCB_RQ_WRITE_PTR) 426 427 #define W_TCB_INB_WRITE_PERM 31 428 #define S_TCB_INB_WRITE_PERM 21 429 #define M_TCB_INB_WRITE_PERM 0x1ULL 430 #define V_TCB_INB_WRITE_PERM(x) ((x) << S_TCB_INB_WRITE_PERM) 431 432 #define W_TCB_INB_READ_PERM 31 433 #define S_TCB_INB_READ_PERM 22 434 #define M_TCB_INB_READ_PERM 0x1ULL 435 #define V_TCB_INB_READ_PERM(x) ((x) << S_TCB_INB_READ_PERM) 436 437 #define W_TCB_ORD_L_BIT_VLD 31 438 #define S_TCB_ORD_L_BIT_VLD 23 439 #define M_TCB_ORD_L_BIT_VLD 0x1ULL 440 #define V_TCB_ORD_L_BIT_VLD(x) ((x) << S_TCB_ORD_L_BIT_VLD) 441 442 #define W_TCB_RDMAP_OPCODE 31 443 #define S_TCB_RDMAP_OPCODE 24 444 #define M_TCB_RDMAP_OPCODE 0xfULL 445 #define V_TCB_RDMAP_OPCODE(x) ((x) << S_TCB_RDMAP_OPCODE) 446 447 #define W_TCB_TX_FLUSH 31 448 #define S_TCB_TX_FLUSH 28 449 #define M_TCB_TX_FLUSH 0x1ULL 450 #define V_TCB_TX_FLUSH(x) ((x) << S_TCB_TX_FLUSH) 451 452 #define W_TCB_TX_OOS_RXMT 31 453 #define S_TCB_TX_OOS_RXMT 29 454 #define M_TCB_TX_OOS_RXMT 0x1ULL 455 #define V_TCB_TX_OOS_RXMT(x) ((x) << S_TCB_TX_OOS_RXMT) 456 457 #define W_TCB_TX_OOS_TXMT 31 458 #define S_TCB_TX_OOS_TXMT 30 459 #define M_TCB_TX_OOS_TXMT 0x1ULL 460 #define V_TCB_TX_OOS_TXMT(x) ((x) << S_TCB_TX_OOS_TXMT) 461 462 #define W_TCB_SLUSH_AUX2 31 463 #define S_TCB_SLUSH_AUX2 31 464 #define M_TCB_SLUSH_AUX2 0x1ULL 465 #define V_TCB_SLUSH_AUX2(x) ((x) << S_TCB_SLUSH_AUX2) 466 467 #define W_TCB_RX_FRAG1_PTR_RAW2 25 468 #define S_TCB_RX_FRAG1_PTR_RAW2 30 469 #define M_TCB_RX_FRAG1_PTR_RAW2 0x1ffffULL 470 #define V_TCB_RX_FRAG1_PTR_RAW2(x) ((x) << S_TCB_RX_FRAG1_PTR_RAW2) 471 472 #define W_TCB_RX_DDP_FLAGS 26 473 #define S_TCB_RX_DDP_FLAGS 15 474 #define M_TCB_RX_DDP_FLAGS 0xffffULL 475 #define V_TCB_RX_DDP_FLAGS(x) ((x) << S_TCB_RX_DDP_FLAGS) 476 477 #define W_TCB_SLUSH_AUX3 26 478 #define S_TCB_SLUSH_AUX3 31 479 #define M_TCB_SLUSH_AUX3 0x1ffULL 480 #define V_TCB_SLUSH_AUX3(x) ((x) << S_TCB_SLUSH_AUX3) 481 482 #define W_TCB_RX_DDP_BUF0_OFFSET 27 483 #define S_TCB_RX_DDP_BUF0_OFFSET 8 484 #define M_TCB_RX_DDP_BUF0_OFFSET 0x3fffffULL 485 #define V_TCB_RX_DDP_BUF0_OFFSET(x) ((x) << S_TCB_RX_DDP_BUF0_OFFSET) 486 487 #define W_TCB_RX_DDP_BUF0_LEN 27 488 #define S_TCB_RX_DDP_BUF0_LEN 30 489 #define M_TCB_RX_DDP_BUF0_LEN 0x3fffffULL 490 #define V_TCB_RX_DDP_BUF0_LEN(x) ((x) << S_TCB_RX_DDP_BUF0_LEN) 491 492 #define W_TCB_RX_DDP_BUF1_OFFSET 28 493 #define S_TCB_RX_DDP_BUF1_OFFSET 20 494 #define M_TCB_RX_DDP_BUF1_OFFSET 0x3fffffULL 495 #define V_TCB_RX_DDP_BUF1_OFFSET(x) ((x) << S_TCB_RX_DDP_BUF1_OFFSET) 496 497 #define W_TCB_RX_DDP_BUF1_LEN 29 498 #define S_TCB_RX_DDP_BUF1_LEN 10 499 #define M_TCB_RX_DDP_BUF1_LEN 0x3fffffULL 500 #define V_TCB_RX_DDP_BUF1_LEN(x) ((x) << S_TCB_RX_DDP_BUF1_LEN) 501 502 #define W_TCB_RX_DDP_BUF0_TAG 30 503 #define S_TCB_RX_DDP_BUF0_TAG 0 504 #define M_TCB_RX_DDP_BUF0_TAG 0xffffffffULL 505 #define V_TCB_RX_DDP_BUF0_TAG(x) ((x) << S_TCB_RX_DDP_BUF0_TAG) 506 507 #define W_TCB_RX_DDP_BUF1_TAG 31 508 #define S_TCB_RX_DDP_BUF1_TAG 0 509 #define M_TCB_RX_DDP_BUF1_TAG 0xffffffffULL 510 #define V_TCB_RX_DDP_BUF1_TAG(x) ((x) << S_TCB_RX_DDP_BUF1_TAG) 511 512 #define S_TF_DACK 10 513 #define V_TF_DACK(x) ((x) << S_TF_DACK) 514 515 #define S_TF_NAGLE 11 516 #define V_TF_NAGLE(x) ((x) << S_TF_NAGLE) 517 518 #define S_TF_RECV_SCALE 12 519 #define V_TF_RECV_SCALE(x) ((x) << S_TF_RECV_SCALE) 520 521 #define S_TF_RECV_TSTMP 13 522 #define V_TF_RECV_TSTMP(x) ((x) << S_TF_RECV_TSTMP) 523 524 #define S_TF_RECV_SACK 14 525 #define V_TF_RECV_SACK(x) ((x) << S_TF_RECV_SACK) 526 527 #define S_TF_TURBO 15 528 #define V_TF_TURBO(x) ((x) << S_TF_TURBO) 529 530 #define S_TF_KEEPALIVE 16 531 #define V_TF_KEEPALIVE(x) ((x) << S_TF_KEEPALIVE) 532 533 #define S_TF_TCAM_BYPASS 17 534 #define V_TF_TCAM_BYPASS(x) ((x) << S_TF_TCAM_BYPASS) 535 536 #define S_TF_CORE_FIN 18 537 #define V_TF_CORE_FIN(x) ((x) << S_TF_CORE_FIN) 538 539 #define S_TF_CORE_MORE 19 540 #define V_TF_CORE_MORE(x) ((x) << S_TF_CORE_MORE) 541 542 #define S_TF_MIGRATING 20 543 #define V_TF_MIGRATING(x) ((x) << S_TF_MIGRATING) 544 545 #define S_TF_ACTIVE_OPEN 21 546 #define V_TF_ACTIVE_OPEN(x) ((x) << S_TF_ACTIVE_OPEN) 547 548 #define S_TF_ASK_MODE 22 549 #define V_TF_ASK_MODE(x) ((x) << S_TF_ASK_MODE) 550 551 #define S_TF_NON_OFFLOAD 23 552 #define V_TF_NON_OFFLOAD(x) ((x) << S_TF_NON_OFFLOAD) 553 554 #define S_TF_MOD_SCHD 24 555 #define V_TF_MOD_SCHD(x) ((x) << S_TF_MOD_SCHD) 556 557 #define S_TF_MOD_SCHD_REASON0 25 558 #define V_TF_MOD_SCHD_REASON0(x) ((x) << S_TF_MOD_SCHD_REASON0) 559 560 #define S_TF_MOD_SCHD_REASON1 26 561 #define V_TF_MOD_SCHD_REASON1(x) ((x) << S_TF_MOD_SCHD_REASON1) 562 563 #define S_TF_MOD_SCHD_RX 27 564 #define V_TF_MOD_SCHD_RX(x) ((x) << S_TF_MOD_SCHD_RX) 565 566 #define S_TF_CORE_PUSH 28 567 #define V_TF_CORE_PUSH(x) ((x) << S_TF_CORE_PUSH) 568 569 #define S_TF_RCV_COALESCE_ENABLE 29 570 #define V_TF_RCV_COALESCE_ENABLE(x) ((x) << S_TF_RCV_COALESCE_ENABLE) 571 572 #define S_TF_RCV_COALESCE_PUSH 30 573 #define V_TF_RCV_COALESCE_PUSH(x) ((x) << S_TF_RCV_COALESCE_PUSH) 574 575 #define S_TF_RCV_COALESCE_LAST_PSH 31 576 #define V_TF_RCV_COALESCE_LAST_PSH(x) ((x) << S_TF_RCV_COALESCE_LAST_PSH) 577 578 #define S_TF_RCV_COALESCE_HEARTBEAT 32 579 #define V_TF_RCV_COALESCE_HEARTBEAT(x) ((x) << S_TF_RCV_COALESCE_HEARTBEAT) 580 581 #define S_TF_LOCK_TID 33 582 #define V_TF_LOCK_TID(x) ((x) << S_TF_LOCK_TID) 583 584 #define S_TF_DACK_MSS 34 585 #define V_TF_DACK_MSS(x) ((x) << S_TF_DACK_MSS) 586 587 #define S_TF_CCTRL_SEL0 35 588 #define V_TF_CCTRL_SEL0(x) ((x) << S_TF_CCTRL_SEL0) 589 590 #define S_TF_CCTRL_SEL1 36 591 #define V_TF_CCTRL_SEL1(x) ((x) << S_TF_CCTRL_SEL1) 592 593 #define S_TF_TCP_NEWRENO_FAST_RECOVERY 37 594 #define V_TF_TCP_NEWRENO_FAST_RECOVERY(x) ((x) << S_TF_TCP_NEWRENO_FAST_RECOVERY) 595 596 #define S_TF_TX_PACE_AUTO 38 597 #define V_TF_TX_PACE_AUTO(x) ((x) << S_TF_TX_PACE_AUTO) 598 599 #define S_TF_PEER_FIN_HELD 39 600 #define V_TF_PEER_FIN_HELD(x) ((x) << S_TF_PEER_FIN_HELD) 601 602 #define S_TF_CORE_URG 40 603 #define V_TF_CORE_URG(x) ((x) << S_TF_CORE_URG) 604 605 #define S_TF_RDMA_ERROR 41 606 #define V_TF_RDMA_ERROR(x) ((x) << S_TF_RDMA_ERROR) 607 608 #define S_TF_SSWS_DISABLED 42 609 #define V_TF_SSWS_DISABLED(x) ((x) << S_TF_SSWS_DISABLED) 610 611 #define S_TF_DUPACK_COUNT_ODD 43 612 #define V_TF_DUPACK_COUNT_ODD(x) ((x) << S_TF_DUPACK_COUNT_ODD) 613 614 #define S_TF_TX_CHANNEL 44 615 #define V_TF_TX_CHANNEL(x) ((x) << S_TF_TX_CHANNEL) 616 617 #define S_TF_RX_CHANNEL 45 618 #define V_TF_RX_CHANNEL(x) ((x) << S_TF_RX_CHANNEL) 619 620 #define S_TF_TX_PACE_FIXED 46 621 #define V_TF_TX_PACE_FIXED(x) ((x) << S_TF_TX_PACE_FIXED) 622 623 #define S_TF_RDMA_FLM_ERROR 47 624 #define V_TF_RDMA_FLM_ERROR(x) ((x) << S_TF_RDMA_FLM_ERROR) 625 626 #define S_TF_RX_FLOW_CONTROL_DISABLE 48 627 #define V_TF_RX_FLOW_CONTROL_DISABLE(x) ((x) << S_TF_RX_FLOW_CONTROL_DISABLE) 628 629 #define S_TF_DDP_INDICATE_OUT 15 630 #define V_TF_DDP_INDICATE_OUT(x) ((x) << S_TF_DDP_INDICATE_OUT) 631 632 #define S_TF_DDP_ACTIVE_BUF 16 633 #define V_TF_DDP_ACTIVE_BUF(x) ((x) << S_TF_DDP_ACTIVE_BUF) 634 635 #define S_TF_DDP_BUF0_VALID 17 636 #define V_TF_DDP_BUF0_VALID(x) ((x) << S_TF_DDP_BUF0_VALID) 637 638 #define S_TF_DDP_BUF1_VALID 18 639 #define V_TF_DDP_BUF1_VALID(x) ((x) << S_TF_DDP_BUF1_VALID) 640 641 #define S_TF_DDP_BUF0_INDICATE 19 642 #define V_TF_DDP_BUF0_INDICATE(x) ((x) << S_TF_DDP_BUF0_INDICATE) 643 644 #define S_TF_DDP_BUF1_INDICATE 20 645 #define V_TF_DDP_BUF1_INDICATE(x) ((x) << S_TF_DDP_BUF1_INDICATE) 646 647 #define S_TF_DDP_PUSH_DISABLE_0 21 648 #define V_TF_DDP_PUSH_DISABLE_0(x) ((x) << S_TF_DDP_PUSH_DISABLE_0) 649 650 #define S_TF_DDP_PUSH_DISABLE_1 22 651 #define V_TF_DDP_PUSH_DISABLE_1(x) ((x) << S_TF_DDP_PUSH_DISABLE_1) 652 653 #define S_TF_DDP_OFF 23 654 #define V_TF_DDP_OFF(x) ((x) << S_TF_DDP_OFF) 655 656 #define S_TF_DDP_WAIT_FRAG 24 657 #define V_TF_DDP_WAIT_FRAG(x) ((x) << S_TF_DDP_WAIT_FRAG) 658 659 #define S_TF_DDP_BUF_INF 25 660 #define V_TF_DDP_BUF_INF(x) ((x) << S_TF_DDP_BUF_INF) 661 662 #define S_TF_DDP_RX2TX 26 663 #define V_TF_DDP_RX2TX(x) ((x) << S_TF_DDP_RX2TX) 664 665 #define S_TF_DDP_BUF0_FLUSH 27 666 #define V_TF_DDP_BUF0_FLUSH(x) ((x) << S_TF_DDP_BUF0_FLUSH) 667 668 #define S_TF_DDP_BUF1_FLUSH 28 669 #define V_TF_DDP_BUF1_FLUSH(x) ((x) << S_TF_DDP_BUF1_FLUSH) 670 671 #define S_TF_DDP_PSH_NO_INVALIDATE 29 672 #define V_TF_DDP_PSH_NO_INVALIDATE(x) ((x) << S_TF_DDP_PSH_NO_INVALIDATE) 673 674 #endif /* _TCB_DEFS_H */ 675