xref: /freebsd/sys/dev/cxgb/common/cxgb_t3_cpl.h (revision f39bffc62c1395bde25d152c7f68fdf7cbaab414)
1 /**************************************************************************
2 SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3 
4 Copyright (c) 2007-2009 Chelsio Inc.
5 All rights reserved.
6 
7 Redistribution and use in source and binary forms, with or without
8 modification, are permitted provided that the following conditions are met:
9 
10  1. Redistributions of source code must retain the above copyright notice,
11     this list of conditions and the following disclaimer.
12 
13  2. Neither the name of the Chelsio Corporation nor the names of its
14     contributors may be used to endorse or promote products derived from
15     this software without specific prior written permission.
16 
17 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
18 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
21 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
22 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
25 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
27 POSSIBILITY OF SUCH DAMAGE.
28 
29 $FreeBSD$
30 
31 ***************************************************************************/
32 #ifndef T3_CPL_H
33 #define T3_CPL_H
34 
35 enum CPL_opcode {
36 	CPL_PASS_OPEN_REQ     = 0x1,
37 	CPL_PASS_ACCEPT_RPL   = 0x2,
38 	CPL_ACT_OPEN_REQ      = 0x3,
39 	CPL_SET_TCB           = 0x4,
40 	CPL_SET_TCB_FIELD     = 0x5,
41 	CPL_GET_TCB           = 0x6,
42 	CPL_PCMD              = 0x7,
43 	CPL_CLOSE_CON_REQ     = 0x8,
44 	CPL_CLOSE_LISTSRV_REQ = 0x9,
45 	CPL_ABORT_REQ         = 0xA,
46 	CPL_ABORT_RPL         = 0xB,
47 	CPL_TX_DATA           = 0xC,
48 	CPL_RX_DATA_ACK       = 0xD,
49 	CPL_TX_PKT            = 0xE,
50 	CPL_RTE_DELETE_REQ    = 0xF,
51 	CPL_RTE_WRITE_REQ     = 0x10,
52 	CPL_RTE_READ_REQ      = 0x11,
53 	CPL_L2T_WRITE_REQ     = 0x12,
54 	CPL_L2T_READ_REQ      = 0x13,
55 	CPL_SMT_WRITE_REQ     = 0x14,
56 	CPL_SMT_READ_REQ      = 0x15,
57 	CPL_TX_PKT_LSO        = 0x16,
58 	CPL_PCMD_READ         = 0x17,
59 	CPL_BARRIER           = 0x18,
60 	CPL_TID_RELEASE       = 0x1A,
61 
62 	CPL_CLOSE_LISTSRV_RPL = 0x20,
63 	CPL_ERROR             = 0x21,
64 	CPL_GET_TCB_RPL       = 0x22,
65 	CPL_L2T_WRITE_RPL     = 0x23,
66 	CPL_PCMD_READ_RPL     = 0x24,
67 	CPL_PCMD_RPL          = 0x25,
68 	CPL_PEER_CLOSE        = 0x26,
69 	CPL_RTE_DELETE_RPL    = 0x27,
70 	CPL_RTE_WRITE_RPL     = 0x28,
71 	CPL_RX_DDP_COMPLETE   = 0x29,
72 	CPL_RX_PHYS_ADDR      = 0x2A,
73 	CPL_RX_PKT            = 0x2B,
74 	CPL_RX_URG_NOTIFY     = 0x2C,
75 	CPL_SET_TCB_RPL       = 0x2D,
76 	CPL_SMT_WRITE_RPL     = 0x2E,
77 	CPL_TX_DATA_ACK       = 0x2F,
78 
79 	CPL_ABORT_REQ_RSS     = 0x30,
80 	CPL_ABORT_RPL_RSS     = 0x31,
81 	CPL_CLOSE_CON_RPL     = 0x32,
82 	CPL_ISCSI_HDR         = 0x33,
83 	CPL_L2T_READ_RPL      = 0x34,
84 	CPL_RDMA_CQE          = 0x35,
85 	CPL_RDMA_CQE_READ_RSP = 0x36,
86 	CPL_RDMA_CQE_ERR      = 0x37,
87 	CPL_RTE_READ_RPL      = 0x38,
88 	CPL_RX_DATA           = 0x39,
89 
90 	CPL_ACT_OPEN_RPL      = 0x40,
91 	CPL_PASS_OPEN_RPL     = 0x41,
92 	CPL_RX_DATA_DDP       = 0x42,
93 	CPL_SMT_READ_RPL      = 0x43,
94 
95 	CPL_ACT_ESTABLISH     = 0x50,
96 	CPL_PASS_ESTABLISH    = 0x51,
97 
98 	CPL_PASS_ACCEPT_REQ   = 0x70,
99 
100 	CPL_ASYNC_NOTIF       = 0x80, /* fake opcode for async notifications */
101 
102 	CPL_TX_DMA_ACK        = 0xA0,
103 	CPL_RDMA_READ_REQ     = 0xA1,
104 	CPL_RDMA_TERMINATE    = 0xA2,
105 	CPL_TRACE_PKT         = 0xA3,
106 	CPL_RDMA_EC_STATUS    = 0xA5,
107 	CPL_SGE_EC_CR_RETURN  = 0xA6,
108 
109 	NUM_CPL_CMDS    /* must be last and previous entries must be sorted */
110 };
111 
112 enum CPL_error {
113 	CPL_ERR_NONE               = 0,
114 	CPL_ERR_TCAM_PARITY        = 1,
115 	CPL_ERR_TCAM_FULL          = 3,
116 	CPL_ERR_CONN_RESET         = 20,
117 	CPL_ERR_CONN_EXIST         = 22,
118 	CPL_ERR_ARP_MISS           = 23,
119 	CPL_ERR_BAD_SYN            = 24,
120 	CPL_ERR_CONN_TIMEDOUT      = 30,
121 	CPL_ERR_XMIT_TIMEDOUT      = 31,
122 	CPL_ERR_PERSIST_TIMEDOUT   = 32,
123 	CPL_ERR_FINWAIT2_TIMEDOUT  = 33,
124 	CPL_ERR_KEEPALIVE_TIMEDOUT = 34,
125 	CPL_ERR_RTX_NEG_ADVICE     = 35,
126 	CPL_ERR_PERSIST_NEG_ADVICE = 36,
127 	CPL_ERR_ABORT_FAILED       = 42,
128 	CPL_ERR_GENERAL            = 99
129 };
130 
131 enum {
132 	CPL_CONN_POLICY_AUTO = 0,
133 	CPL_CONN_POLICY_ASK  = 1,
134 	CPL_CONN_POLICY_FILTER = 2,
135 	CPL_CONN_POLICY_DENY = 3
136 };
137 
138 enum {
139 	ULP_MODE_NONE          = 0,
140 	ULP_MODE_TCP_DDP       = 1,
141 	ULP_MODE_ISCSI         = 2,
142 	ULP_MODE_RDMA          = 4,
143 	ULP_MODE_TCPDDP        = 5
144 };
145 
146 enum {
147 	ULP_CRC_HEADER = 1 << 0,
148 	ULP_CRC_DATA   = 1 << 1
149 };
150 
151 enum {
152 	CPL_PASS_OPEN_ACCEPT,
153 	CPL_PASS_OPEN_REJECT,
154 	CPL_PASS_OPEN_ACCEPT_TNL
155 };
156 
157 enum {
158 	CPL_ABORT_SEND_RST = 0,
159 	CPL_ABORT_NO_RST,
160 	CPL_ABORT_POST_CLOSE_REQ = 2
161 };
162 
163 enum {                     /* TX_PKT_LSO ethernet types */
164 	CPL_ETH_II,
165 	CPL_ETH_II_VLAN,
166 	CPL_ETH_802_3,
167 	CPL_ETH_802_3_VLAN
168 };
169 
170 enum {                     /* TCP congestion control algorithms */
171 	CONG_ALG_RENO,
172 	CONG_ALG_TAHOE,
173 	CONG_ALG_NEWRENO,
174 	CONG_ALG_HIGHSPEED
175 };
176 
177 enum {                     /* RSS hash type */
178 	RSS_HASH_NONE = 0,
179 	RSS_HASH_2_TUPLE = 1,
180 	RSS_HASH_4_TUPLE = 2,
181 	RSS_HASH_TCPV6 = 3
182 };
183 
184 union opcode_tid {
185 	__be32 opcode_tid;
186 	__u8 opcode;
187 };
188 
189 #define S_OPCODE 24
190 #define V_OPCODE(x) ((x) << S_OPCODE)
191 #define G_OPCODE(x) (((x) >> S_OPCODE) & 0xFF)
192 #define G_TID(x)    ((x) & 0xFFFFFF)
193 
194 /* tid is assumed to be 24-bits */
195 #define MK_OPCODE_TID(opcode, tid) (V_OPCODE(opcode) | (tid))
196 
197 #define OPCODE_TID(cmd) ((cmd)->ot.opcode_tid)
198 
199 /* extract the TID from a CPL command */
200 #define GET_TID(cmd) (G_TID(ntohl(OPCODE_TID(cmd))))
201 
202 struct tcp_options {
203 	__be16 mss;
204 	__u8 wsf;
205 #if defined(__LITTLE_ENDIAN_BITFIELD)
206 	__u8 :5;
207 	__u8 ecn:1;
208 	__u8 sack:1;
209 	__u8 tstamp:1;
210 #else
211 	__u8 tstamp:1;
212 	__u8 sack:1;
213 	__u8 ecn:1;
214 	__u8 :5;
215 #endif
216 };
217 
218 struct rss_header {
219 	__u8 opcode;
220 #if defined(__LITTLE_ENDIAN_BITFIELD)
221 	__u8 cpu_idx:6;
222 	__u8 hash_type:2;
223 #else
224 	__u8 hash_type:2;
225 	__u8 cpu_idx:6;
226 #endif
227 	__be16 cq_idx;
228 	__be32 rss_hash_val;
229 };
230 
231 #define S_HASHTYPE 22
232 #define M_HASHTYPE 0x3
233 #define G_HASHTYPE(x) (((x) >> S_HASHTYPE) & M_HASHTYPE)
234 
235 #define S_QNUM 0
236 #define M_QNUM 0xFFFF
237 #define G_QNUM(x) (((x) >> S_QNUM) & M_QNUM)
238 
239 #ifndef CHELSIO_FW
240 struct work_request_hdr {
241 	union {
242 		struct {
243 			__be32 wr_hi;
244 			__be32 wr_lo;
245 		} ilp32;
246 		struct {
247 			__be64 wr_hilo;
248 		} lp64;
249 	} u;
250 };
251 
252 #define	wrh_hi		u.ilp32.wr_hi
253 #define	wrh_lo		u.ilp32.wr_lo
254 #define	wrh_hilo	u.lp64.wr_hilo
255 
256 /* wr_hi fields */
257 #define S_WR_SGE_CREDITS    0
258 #define M_WR_SGE_CREDITS    0xFF
259 #define V_WR_SGE_CREDITS(x) ((x) << S_WR_SGE_CREDITS)
260 #define G_WR_SGE_CREDITS(x) (((x) >> S_WR_SGE_CREDITS) & M_WR_SGE_CREDITS)
261 
262 #define S_WR_SGLSFLT    8
263 #define M_WR_SGLSFLT    0xFF
264 #define V_WR_SGLSFLT(x) ((x) << S_WR_SGLSFLT)
265 #define G_WR_SGLSFLT(x) (((x) >> S_WR_SGLSFLT) & M_WR_SGLSFLT)
266 
267 #define S_WR_BCNTLFLT    16
268 #define M_WR_BCNTLFLT    0xF
269 #define V_WR_BCNTLFLT(x) ((x) << S_WR_BCNTLFLT)
270 #define G_WR_BCNTLFLT(x) (((x) >> S_WR_BCNTLFLT) & M_WR_BCNTLFLT)
271 
272 /*
273  * Applicable to BYPASS WRs only: the uP will add a CPL_BARRIER before
274  * and after the BYPASS WR if the ATOMIC bit is set.
275  */
276 #define S_WR_ATOMIC	16
277 #define V_WR_ATOMIC(x)	((x) << S_WR_ATOMIC)
278 #define F_WR_ATOMIC	V_WR_ATOMIC(1U)
279 
280 /*
281  * Applicable to BYPASS WRs only: the uP will flush buffered non abort
282  * related WRs.
283  */
284 #define S_WR_FLUSH	17
285 #define V_WR_FLUSH(x)	((x) << S_WR_FLUSH)
286 #define F_WR_FLUSH	V_WR_FLUSH(1U)
287 
288 #define S_WR_CHN	18
289 #define V_WR_CHN(x)	((x) << S_WR_CHN)
290 #define F_WR_CHN	V_WR_CHN(1U)
291 
292 #define S_WR_CHN_VLD	19
293 #define V_WR_CHN_VLD(x)	((x) << S_WR_CHN_VLD)
294 #define F_WR_CHN_VLD	V_WR_CHN_VLD(1U)
295 
296 #define S_WR_DATATYPE    20
297 #define V_WR_DATATYPE(x) ((x) << S_WR_DATATYPE)
298 #define F_WR_DATATYPE    V_WR_DATATYPE(1U)
299 
300 #define S_WR_COMPL    21
301 #define V_WR_COMPL(x) ((x) << S_WR_COMPL)
302 #define F_WR_COMPL    V_WR_COMPL(1U)
303 
304 #define S_WR_EOP    22
305 #define V_WR_EOP(x) ((x) << S_WR_EOP)
306 #define F_WR_EOP    V_WR_EOP(1U)
307 
308 #define S_WR_SOP    23
309 #define V_WR_SOP(x) ((x) << S_WR_SOP)
310 #define F_WR_SOP    V_WR_SOP(1U)
311 
312 #define S_WR_OP    24
313 #define M_WR_OP    0xFF
314 #define V_WR_OP(x) ((x) << S_WR_OP)
315 #define G_WR_OP(x) (((x) >> S_WR_OP) & M_WR_OP)
316 
317 /* wr_lo fields */
318 #define S_WR_LEN    0
319 #define M_WR_LEN    0xFF
320 #define V_WR_LEN(x) ((x) << S_WR_LEN)
321 #define G_WR_LEN(x) (((x) >> S_WR_LEN) & M_WR_LEN)
322 
323 #define S_WR_TID    8
324 #define M_WR_TID    0xFFFFF
325 #define V_WR_TID(x) ((x) << S_WR_TID)
326 #define G_WR_TID(x) (((x) >> S_WR_TID) & M_WR_TID)
327 
328 #define S_WR_CR_FLUSH    30
329 #define V_WR_CR_FLUSH(x) ((x) << S_WR_CR_FLUSH)
330 #define F_WR_CR_FLUSH    V_WR_CR_FLUSH(1U)
331 
332 #define S_WR_GEN    31
333 #define V_WR_GEN(x) ((x) << S_WR_GEN)
334 #define F_WR_GEN    V_WR_GEN(1U)
335 #define G_WR_GEN(x) ((x) >> S_WR_GEN)
336 
337 # define WR_HDR struct work_request_hdr wr
338 # define RSS_HDR
339 #else
340 # define WR_HDR
341 # define RSS_HDR struct rss_header rss_hdr;
342 #endif
343 
344 /* option 0 lower-half fields */
345 #define S_CPL_STATUS    0
346 #define M_CPL_STATUS    0xFF
347 #define V_CPL_STATUS(x) ((x) << S_CPL_STATUS)
348 #define G_CPL_STATUS(x) (((x) >> S_CPL_STATUS) & M_CPL_STATUS)
349 
350 #define S_INJECT_TIMER    6
351 #define V_INJECT_TIMER(x) ((x) << S_INJECT_TIMER)
352 #define F_INJECT_TIMER    V_INJECT_TIMER(1U)
353 
354 #define S_NO_OFFLOAD    7
355 #define V_NO_OFFLOAD(x) ((x) << S_NO_OFFLOAD)
356 #define F_NO_OFFLOAD    V_NO_OFFLOAD(1U)
357 
358 #define S_ULP_MODE    8
359 #define M_ULP_MODE    0xF
360 #define V_ULP_MODE(x) ((x) << S_ULP_MODE)
361 #define G_ULP_MODE(x) (((x) >> S_ULP_MODE) & M_ULP_MODE)
362 
363 #define S_RCV_BUFSIZ    12
364 #define M_RCV_BUFSIZ    0x3FFF
365 #define V_RCV_BUFSIZ(x) ((x) << S_RCV_BUFSIZ)
366 #define G_RCV_BUFSIZ(x) (((x) >> S_RCV_BUFSIZ) & M_RCV_BUFSIZ)
367 
368 #define S_TOS    26
369 #define M_TOS    0x3F
370 #define V_TOS(x) ((x) << S_TOS)
371 #define G_TOS(x) (((x) >> S_TOS) & M_TOS)
372 
373 /* option 0 upper-half fields */
374 #define S_DELACK    0
375 #define V_DELACK(x) ((x) << S_DELACK)
376 #define F_DELACK    V_DELACK(1U)
377 
378 #define S_NO_CONG    1
379 #define V_NO_CONG(x) ((x) << S_NO_CONG)
380 #define F_NO_CONG    V_NO_CONG(1U)
381 
382 #define S_SRC_MAC_SEL    2
383 #define M_SRC_MAC_SEL    0x3
384 #define V_SRC_MAC_SEL(x) ((x) << S_SRC_MAC_SEL)
385 #define G_SRC_MAC_SEL(x) (((x) >> S_SRC_MAC_SEL) & M_SRC_MAC_SEL)
386 
387 #define S_L2T_IDX    4
388 #define M_L2T_IDX    0x7FF
389 #define V_L2T_IDX(x) ((x) << S_L2T_IDX)
390 #define G_L2T_IDX(x) (((x) >> S_L2T_IDX) & M_L2T_IDX)
391 
392 #define S_TX_CHANNEL    15
393 #define V_TX_CHANNEL(x) ((x) << S_TX_CHANNEL)
394 #define F_TX_CHANNEL    V_TX_CHANNEL(1U)
395 
396 #define S_TCAM_BYPASS    16
397 #define V_TCAM_BYPASS(x) ((x) << S_TCAM_BYPASS)
398 #define F_TCAM_BYPASS    V_TCAM_BYPASS(1U)
399 
400 #define S_NAGLE    17
401 #define V_NAGLE(x) ((x) << S_NAGLE)
402 #define F_NAGLE    V_NAGLE(1U)
403 
404 #define S_WND_SCALE    18
405 #define M_WND_SCALE    0xF
406 #define V_WND_SCALE(x) ((x) << S_WND_SCALE)
407 #define G_WND_SCALE(x) (((x) >> S_WND_SCALE) & M_WND_SCALE)
408 
409 #define S_KEEP_ALIVE    22
410 #define V_KEEP_ALIVE(x) ((x) << S_KEEP_ALIVE)
411 #define F_KEEP_ALIVE    V_KEEP_ALIVE(1U)
412 
413 #define S_MAX_RETRANS    23
414 #define M_MAX_RETRANS    0xF
415 #define V_MAX_RETRANS(x) ((x) << S_MAX_RETRANS)
416 #define G_MAX_RETRANS(x) (((x) >> S_MAX_RETRANS) & M_MAX_RETRANS)
417 
418 #define S_MAX_RETRANS_OVERRIDE    27
419 #define V_MAX_RETRANS_OVERRIDE(x) ((x) << S_MAX_RETRANS_OVERRIDE)
420 #define F_MAX_RETRANS_OVERRIDE    V_MAX_RETRANS_OVERRIDE(1U)
421 
422 #define S_MSS_IDX    28
423 #define M_MSS_IDX    0xF
424 #define V_MSS_IDX(x) ((x) << S_MSS_IDX)
425 #define G_MSS_IDX(x) (((x) >> S_MSS_IDX) & M_MSS_IDX)
426 
427 /* option 1 fields */
428 #define S_RSS_ENABLE    0
429 #define V_RSS_ENABLE(x) ((x) << S_RSS_ENABLE)
430 #define F_RSS_ENABLE    V_RSS_ENABLE(1U)
431 
432 #define S_RSS_MASK_LEN    1
433 #define M_RSS_MASK_LEN    0x7
434 #define V_RSS_MASK_LEN(x) ((x) << S_RSS_MASK_LEN)
435 #define G_RSS_MASK_LEN(x) (((x) >> S_RSS_MASK_LEN) & M_RSS_MASK_LEN)
436 
437 #define S_CPU_IDX    4
438 #define M_CPU_IDX    0x3F
439 #define V_CPU_IDX(x) ((x) << S_CPU_IDX)
440 #define G_CPU_IDX(x) (((x) >> S_CPU_IDX) & M_CPU_IDX)
441 
442 #define S_OPT1_VLAN    6
443 #define M_OPT1_VLAN    0xFFF
444 #define V_OPT1_VLAN(x) ((x) << S_OPT1_VLAN)
445 #define G_OPT1_VLAN(x) (((x) >> S_OPT1_VLAN) & M_OPT1_VLAN)
446 
447 #define S_MAC_MATCH_VALID    18
448 #define V_MAC_MATCH_VALID(x) ((x) << S_MAC_MATCH_VALID)
449 #define F_MAC_MATCH_VALID    V_MAC_MATCH_VALID(1U)
450 
451 #define S_CONN_POLICY    19
452 #define M_CONN_POLICY    0x3
453 #define V_CONN_POLICY(x) ((x) << S_CONN_POLICY)
454 #define G_CONN_POLICY(x) (((x) >> S_CONN_POLICY) & M_CONN_POLICY)
455 
456 #define S_SYN_DEFENSE    21
457 #define V_SYN_DEFENSE(x) ((x) << S_SYN_DEFENSE)
458 #define F_SYN_DEFENSE    V_SYN_DEFENSE(1U)
459 
460 #define S_VLAN_PRI    22
461 #define M_VLAN_PRI    0x3
462 #define V_VLAN_PRI(x) ((x) << S_VLAN_PRI)
463 #define G_VLAN_PRI(x) (((x) >> S_VLAN_PRI) & M_VLAN_PRI)
464 
465 #define S_VLAN_PRI_VALID    24
466 #define V_VLAN_PRI_VALID(x) ((x) << S_VLAN_PRI_VALID)
467 #define F_VLAN_PRI_VALID    V_VLAN_PRI_VALID(1U)
468 
469 #define S_PKT_TYPE    25
470 #define M_PKT_TYPE    0x3
471 #define V_PKT_TYPE(x) ((x) << S_PKT_TYPE)
472 #define G_PKT_TYPE(x) (((x) >> S_PKT_TYPE) & M_PKT_TYPE)
473 
474 #define S_MAC_MATCH    27
475 #define M_MAC_MATCH    0x1F
476 #define V_MAC_MATCH(x) ((x) << S_MAC_MATCH)
477 #define G_MAC_MATCH(x) (((x) >> S_MAC_MATCH) & M_MAC_MATCH)
478 
479 /* option 2 fields */
480 #define S_CPU_INDEX    0
481 #define M_CPU_INDEX    0x7F
482 #define V_CPU_INDEX(x) ((x) << S_CPU_INDEX)
483 #define G_CPU_INDEX(x) (((x) >> S_CPU_INDEX) & M_CPU_INDEX)
484 
485 #define S_CPU_INDEX_VALID    7
486 #define V_CPU_INDEX_VALID(x) ((x) << S_CPU_INDEX_VALID)
487 #define F_CPU_INDEX_VALID    V_CPU_INDEX_VALID(1U)
488 
489 #define S_RX_COALESCE    8
490 #define M_RX_COALESCE    0x3
491 #define V_RX_COALESCE(x) ((x) << S_RX_COALESCE)
492 #define G_RX_COALESCE(x) (((x) >> S_RX_COALESCE) & M_RX_COALESCE)
493 
494 #define S_RX_COALESCE_VALID    10
495 #define V_RX_COALESCE_VALID(x) ((x) << S_RX_COALESCE_VALID)
496 #define F_RX_COALESCE_VALID    V_RX_COALESCE_VALID(1U)
497 
498 #define S_CONG_CONTROL_FLAVOR    11
499 #define M_CONG_CONTROL_FLAVOR    0x3
500 #define V_CONG_CONTROL_FLAVOR(x) ((x) << S_CONG_CONTROL_FLAVOR)
501 #define G_CONG_CONTROL_FLAVOR(x) (((x) >> S_CONG_CONTROL_FLAVOR) & M_CONG_CONTROL_FLAVOR)
502 
503 #define S_PACING_FLAVOR    13
504 #define M_PACING_FLAVOR    0x3
505 #define V_PACING_FLAVOR(x) ((x) << S_PACING_FLAVOR)
506 #define G_PACING_FLAVOR(x) (((x) >> S_PACING_FLAVOR) & M_PACING_FLAVOR)
507 
508 #define S_FLAVORS_VALID    15
509 #define V_FLAVORS_VALID(x) ((x) << S_FLAVORS_VALID)
510 #define F_FLAVORS_VALID    V_FLAVORS_VALID(1U)
511 
512 #define S_RX_FC_DISABLE    16
513 #define V_RX_FC_DISABLE(x) ((x) << S_RX_FC_DISABLE)
514 #define F_RX_FC_DISABLE    V_RX_FC_DISABLE(1U)
515 
516 #define S_RX_FC_VALID    17
517 #define V_RX_FC_VALID(x) ((x) << S_RX_FC_VALID)
518 #define F_RX_FC_VALID    V_RX_FC_VALID(1U)
519 
520 struct cpl_pass_open_req {
521 	WR_HDR;
522 	union opcode_tid ot;
523 	__be16 local_port;
524 	__be16 peer_port;
525 	__be32 local_ip;
526 	__be32 peer_ip;
527 	__be32 opt0h;
528 	__be32 opt0l;
529 	__be32 peer_netmask;
530 	__be32 opt1;
531 };
532 
533 struct cpl_pass_open_rpl {
534 	RSS_HDR
535 	union opcode_tid ot;
536 	__be16 local_port;
537 	__be16 peer_port;
538 	__be32 local_ip;
539 	__be32 peer_ip;
540 	__u8 resvd[7];
541 	__u8 status;
542 };
543 
544 struct cpl_pass_establish {
545 	RSS_HDR
546 	union opcode_tid ot;
547 	__be16 local_port;
548 	__be16 peer_port;
549 	__be32 local_ip;
550 	__be32 peer_ip;
551 	__be32 tos_tid;
552 	__be16 l2t_idx;
553 	__be16 tcp_opt;
554 	__be32 snd_isn;
555 	__be32 rcv_isn;
556 };
557 
558 /* cpl_pass_establish.tos_tid fields */
559 #define S_PASS_OPEN_TID    0
560 #define M_PASS_OPEN_TID    0xFFFFFF
561 #define V_PASS_OPEN_TID(x) ((x) << S_PASS_OPEN_TID)
562 #define G_PASS_OPEN_TID(x) (((x) >> S_PASS_OPEN_TID) & M_PASS_OPEN_TID)
563 
564 #define S_PASS_OPEN_TOS    24
565 #define M_PASS_OPEN_TOS    0xFF
566 #define V_PASS_OPEN_TOS(x) ((x) << S_PASS_OPEN_TOS)
567 #define G_PASS_OPEN_TOS(x) (((x) >> S_PASS_OPEN_TOS) & M_PASS_OPEN_TOS)
568 
569 /* cpl_pass_establish.l2t_idx fields */
570 #define S_L2T_IDX16    5
571 #define M_L2T_IDX16    0x7FF
572 #define V_L2T_IDX16(x) ((x) << S_L2T_IDX16)
573 #define G_L2T_IDX16(x) (((x) >> S_L2T_IDX16) & M_L2T_IDX16)
574 
575 /* cpl_pass_establish.tcp_opt fields (also applies act_open_establish) */
576 #define G_TCPOPT_WSCALE_OK(x)  (((x) >> 5) & 1)
577 #define G_TCPOPT_SACK(x)       (((x) >> 6) & 1)
578 #define G_TCPOPT_TSTAMP(x)     (((x) >> 7) & 1)
579 #define G_TCPOPT_SND_WSCALE(x) (((x) >> 8) & 0xf)
580 #define G_TCPOPT_MSS(x)        (((x) >> 12) & 0xf)
581 
582 struct cpl_pass_accept_req {
583 	RSS_HDR
584 	union opcode_tid ot;
585 	__be16 local_port;
586 	__be16 peer_port;
587 	__be32 local_ip;
588 	__be32 peer_ip;
589 	__be32 tos_tid;
590 	struct tcp_options tcp_options;
591 	__u8  dst_mac[6];
592 	__be16 vlan_tag;
593 	__u8  src_mac[6];
594 #if defined(__LITTLE_ENDIAN_BITFIELD)
595 	__u8  :3;
596 	__u8  addr_idx:3;
597 	__u8  port_idx:1;
598 	__u8  exact_match:1;
599 #else
600 	__u8  exact_match:1;
601 	__u8  port_idx:1;
602 	__u8  addr_idx:3;
603 	__u8  :3;
604 #endif
605 	__u8  rsvd;
606 	__be32 rcv_isn;
607 	__be32 rsvd2;
608 };
609 
610 struct cpl_pass_accept_rpl {
611 	WR_HDR;
612 	union opcode_tid ot;
613 	__be32 opt2;
614 	__be32 rsvd;
615 	__be32 peer_ip;
616 	__be32 opt0h;
617 	__be32 opt0l_status;
618 };
619 
620 struct cpl_act_open_req {
621 	WR_HDR;
622 	union opcode_tid ot;
623 	__be16 local_port;
624 	__be16 peer_port;
625 	__be32 local_ip;
626 	__be32 peer_ip;
627 	__be32 opt0h;
628 	__be32 opt0l;
629 	__be32 params;
630 	__be32 opt2;
631 };
632 
633 /* cpl_act_open_req.params fields */
634 #define S_AOPEN_VLAN_PRI    9
635 #define M_AOPEN_VLAN_PRI    0x3
636 #define V_AOPEN_VLAN_PRI(x) ((x) << S_AOPEN_VLAN_PRI)
637 #define G_AOPEN_VLAN_PRI(x) (((x) >> S_AOPEN_VLAN_PRI) & M_AOPEN_VLAN_PRI)
638 
639 #define S_AOPEN_VLAN_PRI_VALID    11
640 #define V_AOPEN_VLAN_PRI_VALID(x) ((x) << S_AOPEN_VLAN_PRI_VALID)
641 #define F_AOPEN_VLAN_PRI_VALID    V_AOPEN_VLAN_PRI_VALID(1U)
642 
643 #define S_AOPEN_PKT_TYPE    12
644 #define M_AOPEN_PKT_TYPE    0x3
645 #define V_AOPEN_PKT_TYPE(x) ((x) << S_AOPEN_PKT_TYPE)
646 #define G_AOPEN_PKT_TYPE(x) (((x) >> S_AOPEN_PKT_TYPE) & M_AOPEN_PKT_TYPE)
647 
648 #define S_AOPEN_MAC_MATCH    14
649 #define M_AOPEN_MAC_MATCH    0x1F
650 #define V_AOPEN_MAC_MATCH(x) ((x) << S_AOPEN_MAC_MATCH)
651 #define G_AOPEN_MAC_MATCH(x) (((x) >> S_AOPEN_MAC_MATCH) & M_AOPEN_MAC_MATCH)
652 
653 #define S_AOPEN_MAC_MATCH_VALID    19
654 #define V_AOPEN_MAC_MATCH_VALID(x) ((x) << S_AOPEN_MAC_MATCH_VALID)
655 #define F_AOPEN_MAC_MATCH_VALID    V_AOPEN_MAC_MATCH_VALID(1U)
656 
657 #define S_AOPEN_IFF_VLAN    20
658 #define M_AOPEN_IFF_VLAN    0xFFF
659 #define V_AOPEN_IFF_VLAN(x) ((x) << S_AOPEN_IFF_VLAN)
660 #define G_AOPEN_IFF_VLAN(x) (((x) >> S_AOPEN_IFF_VLAN) & M_AOPEN_IFF_VLAN)
661 
662 struct cpl_act_open_rpl {
663 	RSS_HDR
664 	union opcode_tid ot;
665 	__be16 local_port;
666 	__be16 peer_port;
667 	__be32 local_ip;
668 	__be32 peer_ip;
669 	__be32 atid;
670 	__u8  rsvd[3];
671 	__u8  status;
672 };
673 
674 struct cpl_act_establish {
675 	RSS_HDR
676 	union opcode_tid ot;
677 	__be16 local_port;
678 	__be16 peer_port;
679 	__be32 local_ip;
680 	__be32 peer_ip;
681 	__be32 tos_tid;
682 	__be16 l2t_idx;
683 	__be16 tcp_opt;
684 	__be32 snd_isn;
685 	__be32 rcv_isn;
686 };
687 
688 struct cpl_get_tcb {
689 	WR_HDR;
690 	union opcode_tid ot;
691 	__be16 cpuno;
692 	__be16 rsvd;
693 };
694 
695 struct cpl_get_tcb_rpl {
696 	RSS_HDR
697 	union opcode_tid ot;
698 	__u8 rsvd;
699 	__u8 status;
700 	__be16 len;
701 };
702 
703 struct cpl_set_tcb {
704 	WR_HDR;
705 	union opcode_tid ot;
706 	__u8  reply;
707 	__u8  cpu_idx;
708 	__be16 len;
709 };
710 
711 /* cpl_set_tcb.reply fields */
712 #define S_NO_REPLY    7
713 #define V_NO_REPLY(x) ((x) << S_NO_REPLY)
714 #define F_NO_REPLY    V_NO_REPLY(1U)
715 
716 struct cpl_set_tcb_field {
717 	WR_HDR;
718 	union opcode_tid ot;
719 	__u8  reply;
720 	__u8  cpu_idx;
721 	__be16 word;
722 	__be64 mask;
723 	__be64 val;
724 };
725 
726 struct cpl_set_tcb_rpl {
727 	RSS_HDR
728 	union opcode_tid ot;
729 	__u8 rsvd[3];
730 	__u8 status;
731 };
732 
733 struct cpl_pcmd {
734 	WR_HDR;
735 	union opcode_tid ot;
736 	__u8 rsvd[3];
737 #if defined(__LITTLE_ENDIAN_BITFIELD)
738 	__u8 src:1;
739 	__u8 bundle:1;
740 	__u8 channel:1;
741 	__u8 :5;
742 #else
743 	__u8 :5;
744 	__u8 channel:1;
745 	__u8 bundle:1;
746 	__u8 src:1;
747 #endif
748 	__be32 pcmd_parm[2];
749 };
750 
751 struct cpl_pcmd_reply {
752 	RSS_HDR
753 	union opcode_tid ot;
754 	__u8  status;
755 	__u8  rsvd;
756 	__be16 len;
757 };
758 
759 struct cpl_close_con_req {
760 	WR_HDR;
761 	union opcode_tid ot;
762 	__be32 rsvd;
763 };
764 
765 struct cpl_close_con_rpl {
766 	RSS_HDR
767 	union opcode_tid ot;
768 	__u8  rsvd[3];
769 	__u8  status;
770 	__be32 snd_nxt;
771 	__be32 rcv_nxt;
772 };
773 
774 struct cpl_close_listserv_req {
775 	WR_HDR;
776 	union opcode_tid ot;
777 	__u8  rsvd0;
778 	__u8  cpu_idx;
779 	__be16 rsvd1;
780 };
781 
782 struct cpl_close_listserv_rpl {
783 	RSS_HDR
784 	union opcode_tid ot;
785 	__u8 rsvd[3];
786 	__u8 status;
787 };
788 
789 struct cpl_abort_req_rss {
790 	RSS_HDR
791 	union opcode_tid ot;
792 	__be32 rsvd0;
793 	__u8  rsvd1;
794 	__u8  status;
795 	__u8  rsvd2[6];
796 };
797 
798 struct cpl_abort_req {
799 	WR_HDR;
800 	union opcode_tid ot;
801 	__be32 rsvd0;
802 	__u8  rsvd1;
803 	__u8  cmd;
804 	__u8  rsvd2[6];
805 };
806 
807 struct cpl_abort_rpl_rss {
808 	RSS_HDR
809 	union opcode_tid ot;
810 	__be32 rsvd0;
811 	__u8  rsvd1;
812 	__u8  status;
813 	__u8  rsvd2[6];
814 };
815 
816 struct cpl_abort_rpl {
817 	WR_HDR;
818 	union opcode_tid ot;
819 	__be32 rsvd0;
820 	__u8  rsvd1;
821 	__u8  cmd;
822 	__u8  rsvd2[6];
823 };
824 
825 struct cpl_peer_close {
826 	RSS_HDR
827 	union opcode_tid ot;
828 	__be32 rcv_nxt;
829 };
830 
831 struct tx_data_wr {
832 	WR_HDR;
833 	__be32 len;
834 	__be32 flags;
835 	__be32 sndseq;
836 	__be32 param;
837 };
838 
839 /* tx_data_wr.flags fields */
840 #define S_TX_ACK_PAGES		21
841 #define M_TX_ACK_PAGES		0x7
842 #define V_TX_ACK_PAGES(x) 	((x) << S_TX_ACK_PAGES)
843 #define G_TX_ACK_PAGES(x) 	(((x) >> S_TX_ACK_PAGES) & M_TX_ACK_PAGES)
844 
845 /* tx_data_wr.param fields */
846 #define S_TX_PORT    0
847 #define M_TX_PORT    0x7
848 #define V_TX_PORT(x) ((x) << S_TX_PORT)
849 #define G_TX_PORT(x) (((x) >> S_TX_PORT) & M_TX_PORT)
850 
851 #define S_TX_MSS    4
852 #define M_TX_MSS    0xF
853 #define V_TX_MSS(x) ((x) << S_TX_MSS)
854 #define G_TX_MSS(x) (((x) >> S_TX_MSS) & M_TX_MSS)
855 
856 #define S_TX_QOS    8
857 #define M_TX_QOS    0xFF
858 #define V_TX_QOS(x) ((x) << S_TX_QOS)
859 #define G_TX_QOS(x) (((x) >> S_TX_QOS) & M_TX_QOS)
860 
861 #define S_TX_SNDBUF 16
862 #define M_TX_SNDBUF 0xFFFF
863 #define V_TX_SNDBUF(x) ((x) << S_TX_SNDBUF)
864 #define G_TX_SNDBUF(x) (((x) >> S_TX_SNDBUF) & M_TX_SNDBUF)
865 
866 struct cpl_tx_data {
867 	union opcode_tid ot;
868 	__be32 len;
869 	__be32 rsvd;
870 	__be16 urg;
871 	__be16 flags;
872 };
873 
874 /* cpl_tx_data.flags fields */
875 #define S_TX_ULP_SUBMODE    6
876 #define M_TX_ULP_SUBMODE    0xF
877 #define V_TX_ULP_SUBMODE(x) ((x) << S_TX_ULP_SUBMODE)
878 #define G_TX_ULP_SUBMODE(x) (((x) >> S_TX_ULP_SUBMODE) & M_TX_ULP_SUBMODE)
879 
880 #define S_TX_ULP_MODE    10
881 #define M_TX_ULP_MODE    0xF
882 #define V_TX_ULP_MODE(x) ((x) << S_TX_ULP_MODE)
883 #define G_TX_ULP_MODE(x) (((x) >> S_TX_ULP_MODE) & M_TX_ULP_MODE)
884 
885 #define S_TX_SHOVE    14
886 #define V_TX_SHOVE(x) ((x) << S_TX_SHOVE)
887 #define F_TX_SHOVE    V_TX_SHOVE(1U)
888 
889 #define S_TX_MORE    15
890 #define V_TX_MORE(x) ((x) << S_TX_MORE)
891 #define F_TX_MORE    V_TX_MORE(1U)
892 
893 /* additional tx_data_wr.flags fields */
894 #define S_TX_CPU_IDX    0
895 #define M_TX_CPU_IDX    0x3F
896 #define V_TX_CPU_IDX(x) ((x) << S_TX_CPU_IDX)
897 #define G_TX_CPU_IDX(x) (((x) >> S_TX_CPU_IDX) & M_TX_CPU_IDX)
898 
899 #define S_TX_URG    16
900 #define V_TX_URG(x) ((x) << S_TX_URG)
901 #define F_TX_URG    V_TX_URG(1U)
902 
903 #define S_TX_CLOSE    17
904 #define V_TX_CLOSE(x) ((x) << S_TX_CLOSE)
905 #define F_TX_CLOSE    V_TX_CLOSE(1U)
906 
907 #define S_TX_INIT    18
908 #define V_TX_INIT(x) ((x) << S_TX_INIT)
909 #define F_TX_INIT    V_TX_INIT(1U)
910 
911 #define S_TX_IMM_ACK    19
912 #define V_TX_IMM_ACK(x) ((x) << S_TX_IMM_ACK)
913 #define F_TX_IMM_ACK    V_TX_IMM_ACK(1U)
914 
915 #define S_TX_IMM_DMA    20
916 #define V_TX_IMM_DMA(x) ((x) << S_TX_IMM_DMA)
917 #define F_TX_IMM_DMA    V_TX_IMM_DMA(1U)
918 
919 struct cpl_tx_data_ack {
920 	RSS_HDR
921 	union opcode_tid ot;
922 	__be32 ack_seq;
923 };
924 
925 struct cpl_wr_ack {
926 	RSS_HDR
927 	union opcode_tid ot;
928 	__be16 credits;
929 	__be16 rsvd;
930 	__be32 snd_nxt;
931 	__be32 snd_una;
932 };
933 
934 struct cpl_sge_ec_cr_return {
935 	RSS_HDR
936 	union opcode_tid ot;
937 	__be16 sge_ec_id;
938 	__u8 cr;
939 	__u8 rsvd;
940 };
941 
942 struct cpl_rdma_ec_status {
943 	RSS_HDR
944 	union opcode_tid ot;
945 	__u8  rsvd[3];
946 	__u8  status;
947 };
948 
949 struct mngt_pktsched_wr {
950 	WR_HDR;
951 	__u8  mngt_opcode;
952 	__u8  rsvd[7];
953 	__u8  sched;
954 	__u8  idx;
955 	__u8  min;
956 	__u8  max;
957 	__u8  binding;
958 	__u8  rsvd1[3];
959 };
960 
961 struct cpl_iscsi_hdr {
962 	RSS_HDR
963 	union opcode_tid ot;
964 	__be16 pdu_len_ddp;
965 	__be16 len;
966 	__be32 seq;
967 	__be16 urg;
968 	__u8  rsvd;
969 	__u8  status;
970 };
971 
972 /* cpl_iscsi_hdr.pdu_len_ddp fields */
973 #define S_ISCSI_PDU_LEN    0
974 #define M_ISCSI_PDU_LEN    0x7FFF
975 #define V_ISCSI_PDU_LEN(x) ((x) << S_ISCSI_PDU_LEN)
976 #define G_ISCSI_PDU_LEN(x) (((x) >> S_ISCSI_PDU_LEN) & M_ISCSI_PDU_LEN)
977 
978 #define S_ISCSI_DDP    15
979 #define V_ISCSI_DDP(x) ((x) << S_ISCSI_DDP)
980 #define F_ISCSI_DDP    V_ISCSI_DDP(1U)
981 
982 struct cpl_rx_data {
983 	RSS_HDR
984 	union opcode_tid ot;
985 	__be16 rsvd;
986 	__be16 len;
987 	__be32 seq;
988 	__be16 urg;
989 #if defined(__LITTLE_ENDIAN_BITFIELD)
990 	__u8  dack_mode:2;
991 	__u8  psh:1;
992 	__u8  heartbeat:1;
993 	__u8  ddp_off:1;
994 	__u8  :3;
995 #else
996 	__u8  :3;
997 	__u8  ddp_off:1;
998 	__u8  heartbeat:1;
999 	__u8  psh:1;
1000 	__u8  dack_mode:2;
1001 #endif
1002 	__u8  status;
1003 };
1004 
1005 struct cpl_rx_data_ack {
1006 	WR_HDR;
1007 	union opcode_tid ot;
1008 	__be32 credit_dack;
1009 };
1010 
1011 /* cpl_rx_data_ack.ack_seq fields */
1012 #define S_RX_CREDITS    0
1013 #define M_RX_CREDITS    0x7FFFFFF
1014 #define V_RX_CREDITS(x) ((x) << S_RX_CREDITS)
1015 #define G_RX_CREDITS(x) (((x) >> S_RX_CREDITS) & M_RX_CREDITS)
1016 
1017 #define S_RX_MODULATE    27
1018 #define V_RX_MODULATE(x) ((x) << S_RX_MODULATE)
1019 #define F_RX_MODULATE    V_RX_MODULATE(1U)
1020 
1021 #define S_RX_FORCE_ACK    28
1022 #define V_RX_FORCE_ACK(x) ((x) << S_RX_FORCE_ACK)
1023 #define F_RX_FORCE_ACK    V_RX_FORCE_ACK(1U)
1024 
1025 #define S_RX_DACK_MODE    29
1026 #define M_RX_DACK_MODE    0x3
1027 #define V_RX_DACK_MODE(x) ((x) << S_RX_DACK_MODE)
1028 #define G_RX_DACK_MODE(x) (((x) >> S_RX_DACK_MODE) & M_RX_DACK_MODE)
1029 
1030 #define S_RX_DACK_CHANGE    31
1031 #define V_RX_DACK_CHANGE(x) ((x) << S_RX_DACK_CHANGE)
1032 #define F_RX_DACK_CHANGE    V_RX_DACK_CHANGE(1U)
1033 
1034 struct cpl_rx_urg_notify {
1035 	RSS_HDR
1036 	union opcode_tid ot;
1037 	__be32 seq;
1038 };
1039 
1040 struct cpl_rx_ddp_complete {
1041 	RSS_HDR
1042 	union opcode_tid ot;
1043 	__be32 ddp_report;
1044 };
1045 
1046 struct cpl_rx_data_ddp {
1047 	RSS_HDR
1048 	union opcode_tid ot;
1049 	__be16 urg;
1050 	__be16 len;
1051 	__be32 seq;
1052 	union {
1053 		__be32 nxt_seq;
1054 		__be32 ddp_report;
1055 	} u;
1056 	__be32 ulp_crc;
1057 	__be32 ddpvld_status;
1058 };
1059 
1060 /* cpl_rx_data_ddp.ddpvld_status fields */
1061 #define S_DDP_STATUS    0
1062 #define M_DDP_STATUS    0xFF
1063 #define V_DDP_STATUS(x) ((x) << S_DDP_STATUS)
1064 #define G_DDP_STATUS(x) (((x) >> S_DDP_STATUS) & M_DDP_STATUS)
1065 
1066 #define S_DDP_VALID    15
1067 #define M_DDP_VALID    0x1FFFF
1068 #define V_DDP_VALID(x) ((x) << S_DDP_VALID)
1069 #define G_DDP_VALID(x) (((x) >> S_DDP_VALID) & M_DDP_VALID)
1070 
1071 #define S_DDP_PPOD_MISMATCH    15
1072 #define V_DDP_PPOD_MISMATCH(x) ((x) << S_DDP_PPOD_MISMATCH)
1073 #define F_DDP_PPOD_MISMATCH    V_DDP_PPOD_MISMATCH(1U)
1074 
1075 #define S_DDP_PDU    16
1076 #define V_DDP_PDU(x) ((x) << S_DDP_PDU)
1077 #define F_DDP_PDU    V_DDP_PDU(1U)
1078 
1079 #define S_DDP_LLIMIT_ERR    17
1080 #define V_DDP_LLIMIT_ERR(x) ((x) << S_DDP_LLIMIT_ERR)
1081 #define F_DDP_LLIMIT_ERR    V_DDP_LLIMIT_ERR(1U)
1082 
1083 #define S_DDP_PPOD_PARITY_ERR    18
1084 #define V_DDP_PPOD_PARITY_ERR(x) ((x) << S_DDP_PPOD_PARITY_ERR)
1085 #define F_DDP_PPOD_PARITY_ERR    V_DDP_PPOD_PARITY_ERR(1U)
1086 
1087 #define S_DDP_PADDING_ERR    19
1088 #define V_DDP_PADDING_ERR(x) ((x) << S_DDP_PADDING_ERR)
1089 #define F_DDP_PADDING_ERR    V_DDP_PADDING_ERR(1U)
1090 
1091 #define S_DDP_HDRCRC_ERR    20
1092 #define V_DDP_HDRCRC_ERR(x) ((x) << S_DDP_HDRCRC_ERR)
1093 #define F_DDP_HDRCRC_ERR    V_DDP_HDRCRC_ERR(1U)
1094 
1095 #define S_DDP_DATACRC_ERR    21
1096 #define V_DDP_DATACRC_ERR(x) ((x) << S_DDP_DATACRC_ERR)
1097 #define F_DDP_DATACRC_ERR    V_DDP_DATACRC_ERR(1U)
1098 
1099 #define S_DDP_INVALID_TAG    22
1100 #define V_DDP_INVALID_TAG(x) ((x) << S_DDP_INVALID_TAG)
1101 #define F_DDP_INVALID_TAG    V_DDP_INVALID_TAG(1U)
1102 
1103 #define S_DDP_ULIMIT_ERR    23
1104 #define V_DDP_ULIMIT_ERR(x) ((x) << S_DDP_ULIMIT_ERR)
1105 #define F_DDP_ULIMIT_ERR    V_DDP_ULIMIT_ERR(1U)
1106 
1107 #define S_DDP_OFFSET_ERR    24
1108 #define V_DDP_OFFSET_ERR(x) ((x) << S_DDP_OFFSET_ERR)
1109 #define F_DDP_OFFSET_ERR    V_DDP_OFFSET_ERR(1U)
1110 
1111 #define S_DDP_COLOR_ERR    25
1112 #define V_DDP_COLOR_ERR(x) ((x) << S_DDP_COLOR_ERR)
1113 #define F_DDP_COLOR_ERR    V_DDP_COLOR_ERR(1U)
1114 
1115 #define S_DDP_TID_MISMATCH    26
1116 #define V_DDP_TID_MISMATCH(x) ((x) << S_DDP_TID_MISMATCH)
1117 #define F_DDP_TID_MISMATCH    V_DDP_TID_MISMATCH(1U)
1118 
1119 #define S_DDP_INVALID_PPOD    27
1120 #define V_DDP_INVALID_PPOD(x) ((x) << S_DDP_INVALID_PPOD)
1121 #define F_DDP_INVALID_PPOD    V_DDP_INVALID_PPOD(1U)
1122 
1123 #define S_DDP_ULP_MODE    28
1124 #define M_DDP_ULP_MODE    0xF
1125 #define V_DDP_ULP_MODE(x) ((x) << S_DDP_ULP_MODE)
1126 #define G_DDP_ULP_MODE(x) (((x) >> S_DDP_ULP_MODE) & M_DDP_ULP_MODE)
1127 
1128 /* cpl_rx_data_ddp.ddp_report fields */
1129 #define S_DDP_OFFSET    0
1130 #define M_DDP_OFFSET    0x3FFFFF
1131 #define V_DDP_OFFSET(x) ((x) << S_DDP_OFFSET)
1132 #define G_DDP_OFFSET(x) (((x) >> S_DDP_OFFSET) & M_DDP_OFFSET)
1133 
1134 #define S_DDP_DACK_MODE    22
1135 #define M_DDP_DACK_MODE    0x3
1136 #define V_DDP_DACK_MODE(x) ((x) << S_DDP_DACK_MODE)
1137 #define G_DDP_DACK_MODE(x) (((x) >> S_DDP_DACK_MODE) & M_DDP_DACK_MODE)
1138 
1139 #define S_DDP_URG    24
1140 #define V_DDP_URG(x) ((x) << S_DDP_URG)
1141 #define F_DDP_URG    V_DDP_URG(1U)
1142 
1143 #define S_DDP_PSH    25
1144 #define V_DDP_PSH(x) ((x) << S_DDP_PSH)
1145 #define F_DDP_PSH    V_DDP_PSH(1U)
1146 
1147 #define S_DDP_BUF_COMPLETE    26
1148 #define V_DDP_BUF_COMPLETE(x) ((x) << S_DDP_BUF_COMPLETE)
1149 #define F_DDP_BUF_COMPLETE    V_DDP_BUF_COMPLETE(1U)
1150 
1151 #define S_DDP_BUF_TIMED_OUT    27
1152 #define V_DDP_BUF_TIMED_OUT(x) ((x) << S_DDP_BUF_TIMED_OUT)
1153 #define F_DDP_BUF_TIMED_OUT    V_DDP_BUF_TIMED_OUT(1U)
1154 
1155 #define S_DDP_BUF_IDX    28
1156 #define V_DDP_BUF_IDX(x) ((x) << S_DDP_BUF_IDX)
1157 #define F_DDP_BUF_IDX    V_DDP_BUF_IDX(1U)
1158 
1159 struct cpl_tx_pkt {
1160 	WR_HDR;
1161 	__be32 cntrl;
1162 	__be32 len;
1163 };
1164 
1165 struct cpl_tx_pkt_coalesce {
1166 	__be32 cntrl;
1167 	__be32 len;
1168 	__be64 addr;
1169 };
1170 
1171 struct tx_pkt_coalesce_wr {
1172 	WR_HDR;
1173 	struct cpl_tx_pkt_coalesce cpl[0];
1174 };
1175 
1176 struct cpl_tx_pkt_lso {
1177 	WR_HDR;
1178 	__be32 cntrl;
1179 	__be32 len;
1180 
1181 	__be32 rsvd;
1182 	__be32 lso_info;
1183 };
1184 
1185 struct cpl_tx_pkt_batch_entry {
1186 	__be32 cntrl;
1187 	__be32 len;
1188 	__be64 addr;
1189 };
1190 
1191 struct cpl_tx_pkt_batch {
1192 	WR_HDR;
1193 	struct cpl_tx_pkt_batch_entry pkt_entry[7];
1194 };
1195 
1196 
1197 /* cpl_tx_pkt*.cntrl fields */
1198 #define S_TXPKT_VLAN    0
1199 #define M_TXPKT_VLAN    0xFFFF
1200 #define V_TXPKT_VLAN(x) ((x) << S_TXPKT_VLAN)
1201 #define G_TXPKT_VLAN(x) (((x) >> S_TXPKT_VLAN) & M_TXPKT_VLAN)
1202 
1203 #define S_TXPKT_INTF    16
1204 #define M_TXPKT_INTF    0xF
1205 #define V_TXPKT_INTF(x) ((x) << S_TXPKT_INTF)
1206 #define G_TXPKT_INTF(x) (((x) >> S_TXPKT_INTF) & M_TXPKT_INTF)
1207 
1208 #define S_TXPKT_IPCSUM_DIS    20
1209 #define V_TXPKT_IPCSUM_DIS(x) ((x) << S_TXPKT_IPCSUM_DIS)
1210 #define F_TXPKT_IPCSUM_DIS    V_TXPKT_IPCSUM_DIS(1U)
1211 
1212 #define S_TXPKT_L4CSUM_DIS    21
1213 #define V_TXPKT_L4CSUM_DIS(x) ((x) << S_TXPKT_L4CSUM_DIS)
1214 #define F_TXPKT_L4CSUM_DIS    V_TXPKT_L4CSUM_DIS(1U)
1215 
1216 #define S_TXPKT_VLAN_VLD    22
1217 #define V_TXPKT_VLAN_VLD(x) ((x) << S_TXPKT_VLAN_VLD)
1218 #define F_TXPKT_VLAN_VLD    V_TXPKT_VLAN_VLD(1U)
1219 
1220 #define S_TXPKT_LOOPBACK    23
1221 #define V_TXPKT_LOOPBACK(x) ((x) << S_TXPKT_LOOPBACK)
1222 #define F_TXPKT_LOOPBACK    V_TXPKT_LOOPBACK(1U)
1223 
1224 #define S_TXPKT_OPCODE    24
1225 #define M_TXPKT_OPCODE    0xFF
1226 #define V_TXPKT_OPCODE(x) ((x) << S_TXPKT_OPCODE)
1227 #define G_TXPKT_OPCODE(x) (((x) >> S_TXPKT_OPCODE) & M_TXPKT_OPCODE)
1228 
1229 /* cpl_tx_pkt_lso.lso_info fields */
1230 #define S_LSO_MSS    0
1231 #define M_LSO_MSS    0x3FFF
1232 #define V_LSO_MSS(x) ((x) << S_LSO_MSS)
1233 #define G_LSO_MSS(x) (((x) >> S_LSO_MSS) & M_LSO_MSS)
1234 
1235 #define S_LSO_ETH_TYPE    14
1236 #define M_LSO_ETH_TYPE    0x3
1237 #define V_LSO_ETH_TYPE(x) ((x) << S_LSO_ETH_TYPE)
1238 #define G_LSO_ETH_TYPE(x) (((x) >> S_LSO_ETH_TYPE) & M_LSO_ETH_TYPE)
1239 
1240 #define S_LSO_TCPHDR_WORDS    16
1241 #define M_LSO_TCPHDR_WORDS    0xF
1242 #define V_LSO_TCPHDR_WORDS(x) ((x) << S_LSO_TCPHDR_WORDS)
1243 #define G_LSO_TCPHDR_WORDS(x) (((x) >> S_LSO_TCPHDR_WORDS) & M_LSO_TCPHDR_WORDS)
1244 
1245 #define S_LSO_IPHDR_WORDS    20
1246 #define M_LSO_IPHDR_WORDS    0xF
1247 #define V_LSO_IPHDR_WORDS(x) ((x) << S_LSO_IPHDR_WORDS)
1248 #define G_LSO_IPHDR_WORDS(x) (((x) >> S_LSO_IPHDR_WORDS) & M_LSO_IPHDR_WORDS)
1249 
1250 #define S_LSO_IPV6    24
1251 #define V_LSO_IPV6(x) ((x) << S_LSO_IPV6)
1252 #define F_LSO_IPV6    V_LSO_IPV6(1U)
1253 
1254 struct cpl_trace_pkt {
1255 #ifdef CHELSIO_FW
1256 	__u8 rss_opcode;
1257 #if defined(__LITTLE_ENDIAN_BITFIELD)
1258 	__u8 err:1;
1259 	__u8 :7;
1260 #else
1261 	__u8 :7;
1262 	__u8 err:1;
1263 #endif
1264 	__u8 rsvd0;
1265 #if defined(__LITTLE_ENDIAN_BITFIELD)
1266 	__u8 qid:4;
1267 	__u8 :4;
1268 #else
1269 	__u8 :4;
1270 	__u8 qid:4;
1271 #endif
1272 	__be32 tstamp;
1273 #endif /* CHELSIO_FW */
1274 
1275 	__u8  opcode;
1276 #if defined(__LITTLE_ENDIAN_BITFIELD)
1277 	__u8  iff:4;
1278 	__u8  :4;
1279 #else
1280 	__u8  :4;
1281 	__u8  iff:4;
1282 #endif
1283 	__u8  rsvd[4];
1284 	__be16 len;
1285 };
1286 
1287 struct cpl_rx_pkt {
1288 	RSS_HDR
1289 	__u8 opcode;
1290 #if defined(__LITTLE_ENDIAN_BITFIELD)
1291 	__u8 iff:4;
1292 	__u8 csum_valid:1;
1293 	__u8 ipmi_pkt:1;
1294 	__u8 vlan_valid:1;
1295 	__u8 fragment:1;
1296 #else
1297 	__u8 fragment:1;
1298 	__u8 vlan_valid:1;
1299 	__u8 ipmi_pkt:1;
1300 	__u8 csum_valid:1;
1301 	__u8 iff:4;
1302 #endif
1303 	__be16 csum;
1304 	__be16 vlan;
1305 	__be16 len;
1306 };
1307 
1308 struct cpl_l2t_write_req {
1309 	WR_HDR;
1310 	union opcode_tid ot;
1311 	__be32 params;
1312 	__u8  rsvd;
1313 	__u8  port_idx;
1314 	__u8  dst_mac[6];
1315 };
1316 
1317 /* cpl_l2t_write_req.params fields */
1318 #define S_L2T_W_IDX    0
1319 #define M_L2T_W_IDX    0x7FF
1320 #define V_L2T_W_IDX(x) ((x) << S_L2T_W_IDX)
1321 #define G_L2T_W_IDX(x) (((x) >> S_L2T_W_IDX) & M_L2T_W_IDX)
1322 
1323 #define S_L2T_W_VLAN    11
1324 #define M_L2T_W_VLAN    0xFFF
1325 #define V_L2T_W_VLAN(x) ((x) << S_L2T_W_VLAN)
1326 #define G_L2T_W_VLAN(x) (((x) >> S_L2T_W_VLAN) & M_L2T_W_VLAN)
1327 
1328 #define S_L2T_W_IFF    23
1329 #define M_L2T_W_IFF    0xF
1330 #define V_L2T_W_IFF(x) ((x) << S_L2T_W_IFF)
1331 #define G_L2T_W_IFF(x) (((x) >> S_L2T_W_IFF) & M_L2T_W_IFF)
1332 
1333 #define S_L2T_W_PRIO    27
1334 #define M_L2T_W_PRIO    0x7
1335 #define V_L2T_W_PRIO(x) ((x) << S_L2T_W_PRIO)
1336 #define G_L2T_W_PRIO(x) (((x) >> S_L2T_W_PRIO) & M_L2T_W_PRIO)
1337 
1338 struct cpl_l2t_write_rpl {
1339 	RSS_HDR
1340 	union opcode_tid ot;
1341 	__u8 status;
1342 	__u8 rsvd[3];
1343 };
1344 
1345 struct cpl_l2t_read_req {
1346 	WR_HDR;
1347 	union opcode_tid ot;
1348 	__be16 rsvd;
1349 	__be16 l2t_idx;
1350 };
1351 
1352 struct cpl_l2t_read_rpl {
1353 	RSS_HDR
1354 	union opcode_tid ot;
1355 	__be32 params;
1356 	__u8 rsvd[2];
1357 	__u8 dst_mac[6];
1358 };
1359 
1360 /* cpl_l2t_read_rpl.params fields */
1361 #define S_L2T_R_PRIO    0
1362 #define M_L2T_R_PRIO    0x7
1363 #define V_L2T_R_PRIO(x) ((x) << S_L2T_R_PRIO)
1364 #define G_L2T_R_PRIO(x) (((x) >> S_L2T_R_PRIO) & M_L2T_R_PRIO)
1365 
1366 #define S_L2T_R_VLAN    8
1367 #define M_L2T_R_VLAN    0xFFF
1368 #define V_L2T_R_VLAN(x) ((x) << S_L2T_R_VLAN)
1369 #define G_L2T_R_VLAN(x) (((x) >> S_L2T_R_VLAN) & M_L2T_R_VLAN)
1370 
1371 #define S_L2T_R_IFF    20
1372 #define M_L2T_R_IFF    0xF
1373 #define V_L2T_R_IFF(x) ((x) << S_L2T_R_IFF)
1374 #define G_L2T_R_IFF(x) (((x) >> S_L2T_R_IFF) & M_L2T_R_IFF)
1375 
1376 #define S_L2T_STATUS    24
1377 #define M_L2T_STATUS    0xFF
1378 #define V_L2T_STATUS(x) ((x) << S_L2T_STATUS)
1379 #define G_L2T_STATUS(x) (((x) >> S_L2T_STATUS) & M_L2T_STATUS)
1380 
1381 struct cpl_smt_write_req {
1382 	WR_HDR;
1383 	union opcode_tid ot;
1384 	__u8 rsvd0;
1385 #if defined(__LITTLE_ENDIAN_BITFIELD)
1386 	__u8 mtu_idx:4;
1387 	__u8 iff:4;
1388 #else
1389 	__u8 iff:4;
1390 	__u8 mtu_idx:4;
1391 #endif
1392 	__be16 rsvd2;
1393 	__be16 rsvd3;
1394 	__u8  src_mac1[6];
1395 	__be16 rsvd4;
1396 	__u8  src_mac0[6];
1397 };
1398 
1399 struct cpl_smt_write_rpl {
1400 	RSS_HDR
1401 	union opcode_tid ot;
1402 	__u8 status;
1403 	__u8 rsvd[3];
1404 };
1405 
1406 struct cpl_smt_read_req {
1407 	WR_HDR;
1408 	union opcode_tid ot;
1409 	__u8 rsvd0;
1410 #if defined(__LITTLE_ENDIAN_BITFIELD)
1411 	__u8 :4;
1412 	__u8 iff:4;
1413 #else
1414 	__u8 iff:4;
1415 	__u8 :4;
1416 #endif
1417 	__be16 rsvd2;
1418 };
1419 
1420 struct cpl_smt_read_rpl {
1421 	RSS_HDR
1422 	union opcode_tid ot;
1423 	__u8 status;
1424 #if defined(__LITTLE_ENDIAN_BITFIELD)
1425 	__u8 mtu_idx:4;
1426 	__u8 :4;
1427 #else
1428 	__u8 :4;
1429 	__u8 mtu_idx:4;
1430 #endif
1431 	__be16 rsvd2;
1432 	__be16 rsvd3;
1433 	__u8  src_mac1[6];
1434 	__be16 rsvd4;
1435 	__u8  src_mac0[6];
1436 };
1437 
1438 struct cpl_rte_delete_req {
1439 	WR_HDR;
1440 	union opcode_tid ot;
1441 	__be32 params;
1442 };
1443 
1444 /* { cpl_rte_delete_req, cpl_rte_read_req }.params fields */
1445 #define S_RTE_REQ_LUT_IX    8
1446 #define M_RTE_REQ_LUT_IX    0x7FF
1447 #define V_RTE_REQ_LUT_IX(x) ((x) << S_RTE_REQ_LUT_IX)
1448 #define G_RTE_REQ_LUT_IX(x) (((x) >> S_RTE_REQ_LUT_IX) & M_RTE_REQ_LUT_IX)
1449 
1450 #define S_RTE_REQ_LUT_BASE    19
1451 #define M_RTE_REQ_LUT_BASE    0x7FF
1452 #define V_RTE_REQ_LUT_BASE(x) ((x) << S_RTE_REQ_LUT_BASE)
1453 #define G_RTE_REQ_LUT_BASE(x) (((x) >> S_RTE_REQ_LUT_BASE) & M_RTE_REQ_LUT_BASE)
1454 
1455 #define S_RTE_READ_REQ_SELECT    31
1456 #define V_RTE_READ_REQ_SELECT(x) ((x) << S_RTE_READ_REQ_SELECT)
1457 #define F_RTE_READ_REQ_SELECT    V_RTE_READ_REQ_SELECT(1U)
1458 
1459 struct cpl_rte_delete_rpl {
1460 	RSS_HDR
1461 	union opcode_tid ot;
1462 	__u8 status;
1463 	__u8 rsvd[3];
1464 };
1465 
1466 struct cpl_rte_write_req {
1467 	WR_HDR;
1468 	union opcode_tid ot;
1469 #if defined(__LITTLE_ENDIAN_BITFIELD)
1470 	__u8 :6;
1471 	__u8 write_tcam:1;
1472 	__u8 write_l2t_lut:1;
1473 #else
1474 	__u8 write_l2t_lut:1;
1475 	__u8 write_tcam:1;
1476 	__u8 :6;
1477 #endif
1478 	__u8 rsvd[3];
1479 	__be32 lut_params;
1480 	__be16 rsvd2;
1481 	__be16 l2t_idx;
1482 	__be32 netmask;
1483 	__be32 faddr;
1484 };
1485 
1486 /* cpl_rte_write_req.lut_params fields */
1487 #define S_RTE_WRITE_REQ_LUT_IX    10
1488 #define M_RTE_WRITE_REQ_LUT_IX    0x7FF
1489 #define V_RTE_WRITE_REQ_LUT_IX(x) ((x) << S_RTE_WRITE_REQ_LUT_IX)
1490 #define G_RTE_WRITE_REQ_LUT_IX(x) (((x) >> S_RTE_WRITE_REQ_LUT_IX) & M_RTE_WRITE_REQ_LUT_IX)
1491 
1492 #define S_RTE_WRITE_REQ_LUT_BASE    21
1493 #define M_RTE_WRITE_REQ_LUT_BASE    0x7FF
1494 #define V_RTE_WRITE_REQ_LUT_BASE(x) ((x) << S_RTE_WRITE_REQ_LUT_BASE)
1495 #define G_RTE_WRITE_REQ_LUT_BASE(x) (((x) >> S_RTE_WRITE_REQ_LUT_BASE) & M_RTE_WRITE_REQ_LUT_BASE)
1496 
1497 struct cpl_rte_write_rpl {
1498 	RSS_HDR
1499 	union opcode_tid ot;
1500 	__u8 status;
1501 	__u8 rsvd[3];
1502 };
1503 
1504 struct cpl_rte_read_req {
1505 	WR_HDR;
1506 	union opcode_tid ot;
1507 	__be32 params;
1508 };
1509 
1510 struct cpl_rte_read_rpl {
1511 	RSS_HDR
1512 	union opcode_tid ot;
1513 	__u8 status;
1514 	__u8 rsvd0;
1515 	__be16 l2t_idx;
1516 #if defined(__LITTLE_ENDIAN_BITFIELD)
1517 	__u8 :7;
1518 	__u8 select:1;
1519 #else
1520 	__u8 select:1;
1521 	__u8 :7;
1522 #endif
1523 	__u8 rsvd2[3];
1524 	__be32 addr;
1525 };
1526 
1527 struct cpl_tid_release {
1528 	WR_HDR;
1529 	union opcode_tid ot;
1530 	__be32 rsvd;
1531 };
1532 
1533 struct cpl_barrier {
1534 	WR_HDR;
1535 	__u8 opcode;
1536 	__u8 rsvd[7];
1537 };
1538 
1539 struct cpl_rdma_read_req {
1540 	__u8 opcode;
1541 	__u8 rsvd[15];
1542 };
1543 
1544 struct cpl_rdma_terminate {
1545 #ifdef CHELSIO_FW
1546 	__u8 opcode;
1547 	__u8 rsvd[2];
1548 #if defined(__LITTLE_ENDIAN_BITFIELD)
1549 	__u8 rspq:3;
1550 	__u8 :5;
1551 #else
1552 	__u8 :5;
1553 	__u8 rspq:3;
1554 #endif
1555 	__be32 tid_len;
1556 #endif
1557 	__be32 msn;
1558 	__be32 mo;
1559 	__u8  data[0];
1560 };
1561 
1562 /* cpl_rdma_terminate.tid_len fields */
1563 #define S_FLIT_CNT    0
1564 #define M_FLIT_CNT    0xFF
1565 #define V_FLIT_CNT(x) ((x) << S_FLIT_CNT)
1566 #define G_FLIT_CNT(x) (((x) >> S_FLIT_CNT) & M_FLIT_CNT)
1567 
1568 #define S_TERM_TID    8
1569 #define M_TERM_TID    0xFFFFF
1570 #define V_TERM_TID(x) ((x) << S_TERM_TID)
1571 #define G_TERM_TID(x) (((x) >> S_TERM_TID) & M_TERM_TID)
1572 
1573 /* ULP_TX opcodes */
1574 enum { ULP_MEM_READ = 2, ULP_MEM_WRITE = 3, ULP_TXPKT = 4 };
1575 
1576 #define S_ULPTX_CMD    28
1577 #define M_ULPTX_CMD    0xF
1578 #define V_ULPTX_CMD(x) ((x) << S_ULPTX_CMD)
1579 
1580 #define S_ULPTX_NFLITS    0
1581 #define M_ULPTX_NFLITS    0xFF
1582 #define V_ULPTX_NFLITS(x) ((x) << S_ULPTX_NFLITS)
1583 
1584 struct ulp_mem_io {
1585 	WR_HDR;
1586 	__be32 cmd_lock_addr;
1587 	__be32 len;
1588 };
1589 
1590 /* ulp_mem_io.cmd_lock_addr fields */
1591 #define S_ULP_MEMIO_ADDR    0
1592 #define M_ULP_MEMIO_ADDR    0x7FFFFFF
1593 #define V_ULP_MEMIO_ADDR(x) ((x) << S_ULP_MEMIO_ADDR)
1594 
1595 #define S_ULP_MEMIO_LOCK    27
1596 #define V_ULP_MEMIO_LOCK(x) ((x) << S_ULP_MEMIO_LOCK)
1597 #define F_ULP_MEMIO_LOCK    V_ULP_MEMIO_LOCK(1U)
1598 
1599 /* ulp_mem_io.len fields */
1600 #define S_ULP_MEMIO_DATA_LEN    28
1601 #define M_ULP_MEMIO_DATA_LEN    0xF
1602 #define V_ULP_MEMIO_DATA_LEN(x) ((x) << S_ULP_MEMIO_DATA_LEN)
1603 
1604 struct ulp_txpkt {
1605 	__be32 cmd_dest;
1606 	__be32 len;
1607 };
1608 
1609 /* ulp_txpkt.cmd_dest fields */
1610 #define S_ULP_TXPKT_DEST    24
1611 #define M_ULP_TXPKT_DEST    0xF
1612 #define V_ULP_TXPKT_DEST(x) ((x) << S_ULP_TXPKT_DEST)
1613 
1614 #endif  /* T3_CPL_H */
1615