1 /************************************************************************** 2 3 Copyright (c) 2007, Chelsio Inc. 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Neither the name of the Chelsio Corporation nor the names of its 13 contributors may be used to endorse or promote products derived from 14 this software without specific prior written permission. 15 16 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 20 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 POSSIBILITY OF SUCH DAMAGE. 27 28 $FreeBSD$ 29 30 ***************************************************************************/ 31 #ifndef T3_CPL_H 32 #define T3_CPL_H 33 34 enum CPL_opcode { 35 CPL_PASS_OPEN_REQ = 0x1, 36 CPL_PASS_ACCEPT_RPL = 0x2, 37 CPL_ACT_OPEN_REQ = 0x3, 38 CPL_SET_TCB = 0x4, 39 CPL_SET_TCB_FIELD = 0x5, 40 CPL_GET_TCB = 0x6, 41 CPL_PCMD = 0x7, 42 CPL_CLOSE_CON_REQ = 0x8, 43 CPL_CLOSE_LISTSRV_REQ = 0x9, 44 CPL_ABORT_REQ = 0xA, 45 CPL_ABORT_RPL = 0xB, 46 CPL_TX_DATA = 0xC, 47 CPL_RX_DATA_ACK = 0xD, 48 CPL_TX_PKT = 0xE, 49 CPL_RTE_DELETE_REQ = 0xF, 50 CPL_RTE_WRITE_REQ = 0x10, 51 CPL_RTE_READ_REQ = 0x11, 52 CPL_L2T_WRITE_REQ = 0x12, 53 CPL_L2T_READ_REQ = 0x13, 54 CPL_SMT_WRITE_REQ = 0x14, 55 CPL_SMT_READ_REQ = 0x15, 56 CPL_TX_PKT_LSO = 0x16, 57 CPL_PCMD_READ = 0x17, 58 CPL_BARRIER = 0x18, 59 CPL_TID_RELEASE = 0x1A, 60 61 CPL_CLOSE_LISTSRV_RPL = 0x20, 62 CPL_ERROR = 0x21, 63 CPL_GET_TCB_RPL = 0x22, 64 CPL_L2T_WRITE_RPL = 0x23, 65 CPL_PCMD_READ_RPL = 0x24, 66 CPL_PCMD_RPL = 0x25, 67 CPL_PEER_CLOSE = 0x26, 68 CPL_RTE_DELETE_RPL = 0x27, 69 CPL_RTE_WRITE_RPL = 0x28, 70 CPL_RX_DDP_COMPLETE = 0x29, 71 CPL_RX_PHYS_ADDR = 0x2A, 72 CPL_RX_PKT = 0x2B, 73 CPL_RX_URG_NOTIFY = 0x2C, 74 CPL_SET_TCB_RPL = 0x2D, 75 CPL_SMT_WRITE_RPL = 0x2E, 76 CPL_TX_DATA_ACK = 0x2F, 77 78 CPL_ABORT_REQ_RSS = 0x30, 79 CPL_ABORT_RPL_RSS = 0x31, 80 CPL_CLOSE_CON_RPL = 0x32, 81 CPL_ISCSI_HDR = 0x33, 82 CPL_L2T_READ_RPL = 0x34, 83 CPL_RDMA_CQE = 0x35, 84 CPL_RDMA_CQE_READ_RSP = 0x36, 85 CPL_RDMA_CQE_ERR = 0x37, 86 CPL_RTE_READ_RPL = 0x38, 87 CPL_RX_DATA = 0x39, 88 89 CPL_ACT_OPEN_RPL = 0x40, 90 CPL_PASS_OPEN_RPL = 0x41, 91 CPL_RX_DATA_DDP = 0x42, 92 CPL_SMT_READ_RPL = 0x43, 93 94 CPL_ACT_ESTABLISH = 0x50, 95 CPL_PASS_ESTABLISH = 0x51, 96 97 CPL_PASS_ACCEPT_REQ = 0x70, 98 99 CPL_ASYNC_NOTIF = 0x80, /* fake opcode for async notifications */ 100 101 CPL_TX_DMA_ACK = 0xA0, 102 CPL_RDMA_READ_REQ = 0xA1, 103 CPL_RDMA_TERMINATE = 0xA2, 104 CPL_TRACE_PKT = 0xA3, 105 CPL_RDMA_EC_STATUS = 0xA5, 106 CPL_SGE_EC_CR_RETURN = 0xA6, 107 108 NUM_CPL_CMDS /* must be last and previous entries must be sorted */ 109 }; 110 111 enum CPL_error { 112 CPL_ERR_NONE = 0, 113 CPL_ERR_TCAM_PARITY = 1, 114 CPL_ERR_TCAM_FULL = 3, 115 CPL_ERR_CONN_RESET = 20, 116 CPL_ERR_CONN_EXIST = 22, 117 CPL_ERR_ARP_MISS = 23, 118 CPL_ERR_BAD_SYN = 24, 119 CPL_ERR_CONN_TIMEDOUT = 30, 120 CPL_ERR_XMIT_TIMEDOUT = 31, 121 CPL_ERR_PERSIST_TIMEDOUT = 32, 122 CPL_ERR_FINWAIT2_TIMEDOUT = 33, 123 CPL_ERR_KEEPALIVE_TIMEDOUT = 34, 124 CPL_ERR_RTX_NEG_ADVICE = 35, 125 CPL_ERR_PERSIST_NEG_ADVICE = 36, 126 CPL_ERR_ABORT_FAILED = 42, 127 CPL_ERR_GENERAL = 99 128 }; 129 130 enum { 131 CPL_CONN_POLICY_AUTO = 0, 132 CPL_CONN_POLICY_ASK = 1, 133 CPL_CONN_POLICY_FILTER = 2, 134 CPL_CONN_POLICY_DENY = 3 135 }; 136 137 enum { 138 ULP_MODE_NONE = 0, 139 ULP_MODE_TCP_DDP = 1, 140 ULP_MODE_ISCSI = 2, 141 ULP_MODE_RDMA = 4, 142 ULP_MODE_TCPDDP = 5 143 }; 144 145 enum { 146 ULP_CRC_HEADER = 1 << 0, 147 ULP_CRC_DATA = 1 << 1 148 }; 149 150 enum { 151 CPL_PASS_OPEN_ACCEPT, 152 CPL_PASS_OPEN_REJECT, 153 CPL_PASS_OPEN_ACCEPT_TNL 154 }; 155 156 enum { 157 CPL_ABORT_SEND_RST = 0, 158 CPL_ABORT_NO_RST, 159 CPL_ABORT_POST_CLOSE_REQ = 2 160 }; 161 162 enum { /* TX_PKT_LSO ethernet types */ 163 CPL_ETH_II, 164 CPL_ETH_II_VLAN, 165 CPL_ETH_802_3, 166 CPL_ETH_802_3_VLAN 167 }; 168 169 enum { /* TCP congestion control algorithms */ 170 CONG_ALG_RENO, 171 CONG_ALG_TAHOE, 172 CONG_ALG_NEWRENO, 173 CONG_ALG_HIGHSPEED 174 }; 175 176 enum { /* RSS hash type */ 177 RSS_HASH_NONE = 0, 178 RSS_HASH_2_TUPLE = 1, 179 RSS_HASH_4_TUPLE = 2, 180 RSS_HASH_TCPV6 = 3 181 }; 182 183 union opcode_tid { 184 __be32 opcode_tid; 185 __u8 opcode; 186 }; 187 188 #define S_OPCODE 24 189 #define V_OPCODE(x) ((x) << S_OPCODE) 190 #define G_OPCODE(x) (((x) >> S_OPCODE) & 0xFF) 191 #define G_TID(x) ((x) & 0xFFFFFF) 192 193 /* tid is assumed to be 24-bits */ 194 #define MK_OPCODE_TID(opcode, tid) (V_OPCODE(opcode) | (tid)) 195 196 #define OPCODE_TID(cmd) ((cmd)->ot.opcode_tid) 197 198 /* extract the TID from a CPL command */ 199 #define GET_TID(cmd) (G_TID(ntohl(OPCODE_TID(cmd)))) 200 201 struct tcp_options { 202 __be16 mss; 203 __u8 wsf; 204 #if defined(__LITTLE_ENDIAN_BITFIELD) 205 __u8 :5; 206 __u8 ecn:1; 207 __u8 sack:1; 208 __u8 tstamp:1; 209 #else 210 __u8 tstamp:1; 211 __u8 sack:1; 212 __u8 ecn:1; 213 __u8 :5; 214 #endif 215 }; 216 217 struct rss_header { 218 __u8 opcode; 219 #if defined(__LITTLE_ENDIAN_BITFIELD) 220 __u8 cpu_idx:6; 221 __u8 hash_type:2; 222 #else 223 __u8 hash_type:2; 224 __u8 cpu_idx:6; 225 #endif 226 __be16 cq_idx; 227 __be32 rss_hash_val; 228 }; 229 230 #define S_HASHTYPE 22 231 #define M_HASHTYPE 0x3 232 #define G_HASHTYPE(x) (((x) >> S_HASHTYPE) & M_HASHTYPE) 233 234 #define S_QNUM 0 235 #define M_QNUM 0xFFFF 236 #define G_QNUM(x) (((x) >> S_QNUM) & M_QNUM) 237 238 #ifndef CHELSIO_FW 239 struct work_request_hdr { 240 __be32 wr_hi; 241 __be32 wr_lo; 242 }; 243 244 /* wr_hi fields */ 245 #define S_WR_SGE_CREDITS 0 246 #define M_WR_SGE_CREDITS 0xFF 247 #define V_WR_SGE_CREDITS(x) ((x) << S_WR_SGE_CREDITS) 248 #define G_WR_SGE_CREDITS(x) (((x) >> S_WR_SGE_CREDITS) & M_WR_SGE_CREDITS) 249 250 #define S_WR_SGLSFLT 8 251 #define M_WR_SGLSFLT 0xFF 252 #define V_WR_SGLSFLT(x) ((x) << S_WR_SGLSFLT) 253 #define G_WR_SGLSFLT(x) (((x) >> S_WR_SGLSFLT) & M_WR_SGLSFLT) 254 255 #define S_WR_BCNTLFLT 16 256 #define M_WR_BCNTLFLT 0xF 257 #define V_WR_BCNTLFLT(x) ((x) << S_WR_BCNTLFLT) 258 #define G_WR_BCNTLFLT(x) (((x) >> S_WR_BCNTLFLT) & M_WR_BCNTLFLT) 259 260 /* 261 * Applicable to BYPASS WRs only: the uP will add a CPL_BARRIER before 262 * and after the BYPASS WR if the ATOMIC bit is set. 263 */ 264 #define S_WR_ATOMIC 16 265 #define V_WR_ATOMIC(x) ((x) << S_WR_ATOMIC) 266 #define F_WR_ATOMIC V_WR_ATOMIC(1U) 267 268 /* 269 * Applicable to BYPASS WRs only: the uP will flush buffered non abort 270 * related WRs. 271 */ 272 #define S_WR_FLUSH 17 273 #define V_WR_FLUSH(x) ((x) << S_WR_FLUSH) 274 #define F_WR_FLUSH V_WR_FLUSH(1U) 275 276 #define S_WR_DATATYPE 20 277 #define V_WR_DATATYPE(x) ((x) << S_WR_DATATYPE) 278 #define F_WR_DATATYPE V_WR_DATATYPE(1U) 279 280 #define S_WR_COMPL 21 281 #define V_WR_COMPL(x) ((x) << S_WR_COMPL) 282 #define F_WR_COMPL V_WR_COMPL(1U) 283 284 #define S_WR_EOP 22 285 #define V_WR_EOP(x) ((x) << S_WR_EOP) 286 #define F_WR_EOP V_WR_EOP(1U) 287 288 #define S_WR_SOP 23 289 #define V_WR_SOP(x) ((x) << S_WR_SOP) 290 #define F_WR_SOP V_WR_SOP(1U) 291 292 #define S_WR_OP 24 293 #define M_WR_OP 0xFF 294 #define V_WR_OP(x) ((x) << S_WR_OP) 295 #define G_WR_OP(x) (((x) >> S_WR_OP) & M_WR_OP) 296 297 /* wr_lo fields */ 298 #define S_WR_LEN 0 299 #define M_WR_LEN 0xFF 300 #define V_WR_LEN(x) ((x) << S_WR_LEN) 301 #define G_WR_LEN(x) (((x) >> S_WR_LEN) & M_WR_LEN) 302 303 #define S_WR_TID 8 304 #define M_WR_TID 0xFFFFF 305 #define V_WR_TID(x) ((x) << S_WR_TID) 306 #define G_WR_TID(x) (((x) >> S_WR_TID) & M_WR_TID) 307 308 #define S_WR_CR_FLUSH 30 309 #define V_WR_CR_FLUSH(x) ((x) << S_WR_CR_FLUSH) 310 #define F_WR_CR_FLUSH V_WR_CR_FLUSH(1U) 311 312 #define S_WR_GEN 31 313 #define V_WR_GEN(x) ((x) << S_WR_GEN) 314 #define F_WR_GEN V_WR_GEN(1U) 315 #define G_WR_GEN(x) ((x) >> S_WR_GEN) 316 317 # define WR_HDR struct work_request_hdr wr 318 # define RSS_HDR 319 #else 320 # define WR_HDR 321 # define RSS_HDR struct rss_header rss_hdr; 322 #endif 323 324 /* option 0 lower-half fields */ 325 #define S_CPL_STATUS 0 326 #define M_CPL_STATUS 0xFF 327 #define V_CPL_STATUS(x) ((x) << S_CPL_STATUS) 328 #define G_CPL_STATUS(x) (((x) >> S_CPL_STATUS) & M_CPL_STATUS) 329 330 #define S_INJECT_TIMER 6 331 #define V_INJECT_TIMER(x) ((x) << S_INJECT_TIMER) 332 #define F_INJECT_TIMER V_INJECT_TIMER(1U) 333 334 #define S_NO_OFFLOAD 7 335 #define V_NO_OFFLOAD(x) ((x) << S_NO_OFFLOAD) 336 #define F_NO_OFFLOAD V_NO_OFFLOAD(1U) 337 338 #define S_ULP_MODE 8 339 #define M_ULP_MODE 0xF 340 #define V_ULP_MODE(x) ((x) << S_ULP_MODE) 341 #define G_ULP_MODE(x) (((x) >> S_ULP_MODE) & M_ULP_MODE) 342 343 #define S_RCV_BUFSIZ 12 344 #define M_RCV_BUFSIZ 0x3FFF 345 #define V_RCV_BUFSIZ(x) ((x) << S_RCV_BUFSIZ) 346 #define G_RCV_BUFSIZ(x) (((x) >> S_RCV_BUFSIZ) & M_RCV_BUFSIZ) 347 348 #define S_TOS 26 349 #define M_TOS 0x3F 350 #define V_TOS(x) ((x) << S_TOS) 351 #define G_TOS(x) (((x) >> S_TOS) & M_TOS) 352 353 /* option 0 upper-half fields */ 354 #define S_DELACK 0 355 #define V_DELACK(x) ((x) << S_DELACK) 356 #define F_DELACK V_DELACK(1U) 357 358 #define S_NO_CONG 1 359 #define V_NO_CONG(x) ((x) << S_NO_CONG) 360 #define F_NO_CONG V_NO_CONG(1U) 361 362 #define S_SRC_MAC_SEL 2 363 #define M_SRC_MAC_SEL 0x3 364 #define V_SRC_MAC_SEL(x) ((x) << S_SRC_MAC_SEL) 365 #define G_SRC_MAC_SEL(x) (((x) >> S_SRC_MAC_SEL) & M_SRC_MAC_SEL) 366 367 #define S_L2T_IDX 4 368 #define M_L2T_IDX 0x7FF 369 #define V_L2T_IDX(x) ((x) << S_L2T_IDX) 370 #define G_L2T_IDX(x) (((x) >> S_L2T_IDX) & M_L2T_IDX) 371 372 #define S_TX_CHANNEL 15 373 #define V_TX_CHANNEL(x) ((x) << S_TX_CHANNEL) 374 #define F_TX_CHANNEL V_TX_CHANNEL(1U) 375 376 #define S_TCAM_BYPASS 16 377 #define V_TCAM_BYPASS(x) ((x) << S_TCAM_BYPASS) 378 #define F_TCAM_BYPASS V_TCAM_BYPASS(1U) 379 380 #define S_NAGLE 17 381 #define V_NAGLE(x) ((x) << S_NAGLE) 382 #define F_NAGLE V_NAGLE(1U) 383 384 #define S_WND_SCALE 18 385 #define M_WND_SCALE 0xF 386 #define V_WND_SCALE(x) ((x) << S_WND_SCALE) 387 #define G_WND_SCALE(x) (((x) >> S_WND_SCALE) & M_WND_SCALE) 388 389 #define S_KEEP_ALIVE 22 390 #define V_KEEP_ALIVE(x) ((x) << S_KEEP_ALIVE) 391 #define F_KEEP_ALIVE V_KEEP_ALIVE(1U) 392 393 #define S_MAX_RETRANS 23 394 #define M_MAX_RETRANS 0xF 395 #define V_MAX_RETRANS(x) ((x) << S_MAX_RETRANS) 396 #define G_MAX_RETRANS(x) (((x) >> S_MAX_RETRANS) & M_MAX_RETRANS) 397 398 #define S_MAX_RETRANS_OVERRIDE 27 399 #define V_MAX_RETRANS_OVERRIDE(x) ((x) << S_MAX_RETRANS_OVERRIDE) 400 #define F_MAX_RETRANS_OVERRIDE V_MAX_RETRANS_OVERRIDE(1U) 401 402 #define S_MSS_IDX 28 403 #define M_MSS_IDX 0xF 404 #define V_MSS_IDX(x) ((x) << S_MSS_IDX) 405 #define G_MSS_IDX(x) (((x) >> S_MSS_IDX) & M_MSS_IDX) 406 407 /* option 1 fields */ 408 #define S_RSS_ENABLE 0 409 #define V_RSS_ENABLE(x) ((x) << S_RSS_ENABLE) 410 #define F_RSS_ENABLE V_RSS_ENABLE(1U) 411 412 #define S_RSS_MASK_LEN 1 413 #define M_RSS_MASK_LEN 0x7 414 #define V_RSS_MASK_LEN(x) ((x) << S_RSS_MASK_LEN) 415 #define G_RSS_MASK_LEN(x) (((x) >> S_RSS_MASK_LEN) & M_RSS_MASK_LEN) 416 417 #define S_CPU_IDX 4 418 #define M_CPU_IDX 0x3F 419 #define V_CPU_IDX(x) ((x) << S_CPU_IDX) 420 #define G_CPU_IDX(x) (((x) >> S_CPU_IDX) & M_CPU_IDX) 421 422 #define S_OPT1_VLAN 6 423 #define M_OPT1_VLAN 0xFFF 424 #define V_OPT1_VLAN(x) ((x) << S_OPT1_VLAN) 425 #define G_OPT1_VLAN(x) (((x) >> S_OPT1_VLAN) & M_OPT1_VLAN) 426 427 #define S_MAC_MATCH_VALID 18 428 #define V_MAC_MATCH_VALID(x) ((x) << S_MAC_MATCH_VALID) 429 #define F_MAC_MATCH_VALID V_MAC_MATCH_VALID(1U) 430 431 #define S_CONN_POLICY 19 432 #define M_CONN_POLICY 0x3 433 #define V_CONN_POLICY(x) ((x) << S_CONN_POLICY) 434 #define G_CONN_POLICY(x) (((x) >> S_CONN_POLICY) & M_CONN_POLICY) 435 436 #define S_SYN_DEFENSE 21 437 #define V_SYN_DEFENSE(x) ((x) << S_SYN_DEFENSE) 438 #define F_SYN_DEFENSE V_SYN_DEFENSE(1U) 439 440 #define S_VLAN_PRI 22 441 #define M_VLAN_PRI 0x3 442 #define V_VLAN_PRI(x) ((x) << S_VLAN_PRI) 443 #define G_VLAN_PRI(x) (((x) >> S_VLAN_PRI) & M_VLAN_PRI) 444 445 #define S_VLAN_PRI_VALID 24 446 #define V_VLAN_PRI_VALID(x) ((x) << S_VLAN_PRI_VALID) 447 #define F_VLAN_PRI_VALID V_VLAN_PRI_VALID(1U) 448 449 #define S_PKT_TYPE 25 450 #define M_PKT_TYPE 0x3 451 #define V_PKT_TYPE(x) ((x) << S_PKT_TYPE) 452 #define G_PKT_TYPE(x) (((x) >> S_PKT_TYPE) & M_PKT_TYPE) 453 454 #define S_MAC_MATCH 27 455 #define M_MAC_MATCH 0x1F 456 #define V_MAC_MATCH(x) ((x) << S_MAC_MATCH) 457 #define G_MAC_MATCH(x) (((x) >> S_MAC_MATCH) & M_MAC_MATCH) 458 459 /* option 2 fields */ 460 #define S_CPU_INDEX 0 461 #define M_CPU_INDEX 0x7F 462 #define V_CPU_INDEX(x) ((x) << S_CPU_INDEX) 463 #define G_CPU_INDEX(x) (((x) >> S_CPU_INDEX) & M_CPU_INDEX) 464 465 #define S_CPU_INDEX_VALID 7 466 #define V_CPU_INDEX_VALID(x) ((x) << S_CPU_INDEX_VALID) 467 #define F_CPU_INDEX_VALID V_CPU_INDEX_VALID(1U) 468 469 #define S_RX_COALESCE 8 470 #define M_RX_COALESCE 0x3 471 #define V_RX_COALESCE(x) ((x) << S_RX_COALESCE) 472 #define G_RX_COALESCE(x) (((x) >> S_RX_COALESCE) & M_RX_COALESCE) 473 474 #define S_RX_COALESCE_VALID 10 475 #define V_RX_COALESCE_VALID(x) ((x) << S_RX_COALESCE_VALID) 476 #define F_RX_COALESCE_VALID V_RX_COALESCE_VALID(1U) 477 478 #define S_CONG_CONTROL_FLAVOR 11 479 #define M_CONG_CONTROL_FLAVOR 0x3 480 #define V_CONG_CONTROL_FLAVOR(x) ((x) << S_CONG_CONTROL_FLAVOR) 481 #define G_CONG_CONTROL_FLAVOR(x) (((x) >> S_CONG_CONTROL_FLAVOR) & M_CONG_CONTROL_FLAVOR) 482 483 #define S_PACING_FLAVOR 13 484 #define M_PACING_FLAVOR 0x3 485 #define V_PACING_FLAVOR(x) ((x) << S_PACING_FLAVOR) 486 #define G_PACING_FLAVOR(x) (((x) >> S_PACING_FLAVOR) & M_PACING_FLAVOR) 487 488 #define S_FLAVORS_VALID 15 489 #define V_FLAVORS_VALID(x) ((x) << S_FLAVORS_VALID) 490 #define F_FLAVORS_VALID V_FLAVORS_VALID(1U) 491 492 #define S_RX_FC_DISABLE 16 493 #define V_RX_FC_DISABLE(x) ((x) << S_RX_FC_DISABLE) 494 #define F_RX_FC_DISABLE V_RX_FC_DISABLE(1U) 495 496 #define S_RX_FC_VALID 17 497 #define V_RX_FC_VALID(x) ((x) << S_RX_FC_VALID) 498 #define F_RX_FC_VALID V_RX_FC_VALID(1U) 499 500 struct cpl_pass_open_req { 501 WR_HDR; 502 union opcode_tid ot; 503 __be16 local_port; 504 __be16 peer_port; 505 __be32 local_ip; 506 __be32 peer_ip; 507 __be32 opt0h; 508 __be32 opt0l; 509 __be32 peer_netmask; 510 __be32 opt1; 511 }; 512 513 struct cpl_pass_open_rpl { 514 RSS_HDR 515 union opcode_tid ot; 516 __be16 local_port; 517 __be16 peer_port; 518 __be32 local_ip; 519 __be32 peer_ip; 520 __u8 resvd[7]; 521 __u8 status; 522 }; 523 524 struct cpl_pass_establish { 525 RSS_HDR 526 union opcode_tid ot; 527 __be16 local_port; 528 __be16 peer_port; 529 __be32 local_ip; 530 __be32 peer_ip; 531 __be32 tos_tid; 532 __be16 l2t_idx; 533 __be16 tcp_opt; 534 __be32 snd_isn; 535 __be32 rcv_isn; 536 }; 537 538 /* cpl_pass_establish.tos_tid fields */ 539 #define S_PASS_OPEN_TID 0 540 #define M_PASS_OPEN_TID 0xFFFFFF 541 #define V_PASS_OPEN_TID(x) ((x) << S_PASS_OPEN_TID) 542 #define G_PASS_OPEN_TID(x) (((x) >> S_PASS_OPEN_TID) & M_PASS_OPEN_TID) 543 544 #define S_PASS_OPEN_TOS 24 545 #define M_PASS_OPEN_TOS 0xFF 546 #define V_PASS_OPEN_TOS(x) ((x) << S_PASS_OPEN_TOS) 547 #define G_PASS_OPEN_TOS(x) (((x) >> S_PASS_OPEN_TOS) & M_PASS_OPEN_TOS) 548 549 /* cpl_pass_establish.l2t_idx fields */ 550 #define S_L2T_IDX16 5 551 #define M_L2T_IDX16 0x7FF 552 #define V_L2T_IDX16(x) ((x) << S_L2T_IDX16) 553 #define G_L2T_IDX16(x) (((x) >> S_L2T_IDX16) & M_L2T_IDX16) 554 555 /* cpl_pass_establish.tcp_opt fields (also applies act_open_establish) */ 556 #define G_TCPOPT_WSCALE_OK(x) (((x) >> 5) & 1) 557 #define G_TCPOPT_SACK(x) (((x) >> 6) & 1) 558 #define G_TCPOPT_TSTAMP(x) (((x) >> 7) & 1) 559 #define G_TCPOPT_SND_WSCALE(x) (((x) >> 8) & 0xf) 560 #define G_TCPOPT_MSS(x) (((x) >> 12) & 0xf) 561 562 struct cpl_pass_accept_req { 563 RSS_HDR 564 union opcode_tid ot; 565 __be16 local_port; 566 __be16 peer_port; 567 __be32 local_ip; 568 __be32 peer_ip; 569 __be32 tos_tid; 570 struct tcp_options tcp_options; 571 __u8 dst_mac[6]; 572 __be16 vlan_tag; 573 __u8 src_mac[6]; 574 #if defined(__LITTLE_ENDIAN_BITFIELD) 575 __u8 :3; 576 __u8 addr_idx:3; 577 __u8 port_idx:1; 578 __u8 exact_match:1; 579 #else 580 __u8 exact_match:1; 581 __u8 port_idx:1; 582 __u8 addr_idx:3; 583 __u8 :3; 584 #endif 585 __u8 rsvd; 586 __be32 rcv_isn; 587 __be32 rsvd2; 588 }; 589 590 struct cpl_pass_accept_rpl { 591 WR_HDR; 592 union opcode_tid ot; 593 __be32 opt2; 594 __be32 rsvd; 595 __be32 peer_ip; 596 __be32 opt0h; 597 __be32 opt0l_status; 598 }; 599 600 struct cpl_act_open_req { 601 WR_HDR; 602 union opcode_tid ot; 603 __be16 local_port; 604 __be16 peer_port; 605 __be32 local_ip; 606 __be32 peer_ip; 607 __be32 opt0h; 608 __be32 opt0l; 609 __be32 params; 610 __be32 opt2; 611 }; 612 613 /* cpl_act_open_req.params fields */ 614 #define S_AOPEN_VLAN_PRI 9 615 #define M_AOPEN_VLAN_PRI 0x3 616 #define V_AOPEN_VLAN_PRI(x) ((x) << S_AOPEN_VLAN_PRI) 617 #define G_AOPEN_VLAN_PRI(x) (((x) >> S_AOPEN_VLAN_PRI) & M_AOPEN_VLAN_PRI) 618 619 #define S_AOPEN_VLAN_PRI_VALID 11 620 #define V_AOPEN_VLAN_PRI_VALID(x) ((x) << S_AOPEN_VLAN_PRI_VALID) 621 #define F_AOPEN_VLAN_PRI_VALID V_AOPEN_VLAN_PRI_VALID(1U) 622 623 #define S_AOPEN_PKT_TYPE 12 624 #define M_AOPEN_PKT_TYPE 0x3 625 #define V_AOPEN_PKT_TYPE(x) ((x) << S_AOPEN_PKT_TYPE) 626 #define G_AOPEN_PKT_TYPE(x) (((x) >> S_AOPEN_PKT_TYPE) & M_AOPEN_PKT_TYPE) 627 628 #define S_AOPEN_MAC_MATCH 14 629 #define M_AOPEN_MAC_MATCH 0x1F 630 #define V_AOPEN_MAC_MATCH(x) ((x) << S_AOPEN_MAC_MATCH) 631 #define G_AOPEN_MAC_MATCH(x) (((x) >> S_AOPEN_MAC_MATCH) & M_AOPEN_MAC_MATCH) 632 633 #define S_AOPEN_MAC_MATCH_VALID 19 634 #define V_AOPEN_MAC_MATCH_VALID(x) ((x) << S_AOPEN_MAC_MATCH_VALID) 635 #define F_AOPEN_MAC_MATCH_VALID V_AOPEN_MAC_MATCH_VALID(1U) 636 637 #define S_AOPEN_IFF_VLAN 20 638 #define M_AOPEN_IFF_VLAN 0xFFF 639 #define V_AOPEN_IFF_VLAN(x) ((x) << S_AOPEN_IFF_VLAN) 640 #define G_AOPEN_IFF_VLAN(x) (((x) >> S_AOPEN_IFF_VLAN) & M_AOPEN_IFF_VLAN) 641 642 struct cpl_act_open_rpl { 643 RSS_HDR 644 union opcode_tid ot; 645 __be16 local_port; 646 __be16 peer_port; 647 __be32 local_ip; 648 __be32 peer_ip; 649 __be32 atid; 650 __u8 rsvd[3]; 651 __u8 status; 652 }; 653 654 struct cpl_act_establish { 655 RSS_HDR 656 union opcode_tid ot; 657 __be16 local_port; 658 __be16 peer_port; 659 __be32 local_ip; 660 __be32 peer_ip; 661 __be32 tos_tid; 662 __be16 l2t_idx; 663 __be16 tcp_opt; 664 __be32 snd_isn; 665 __be32 rcv_isn; 666 }; 667 668 struct cpl_get_tcb { 669 WR_HDR; 670 union opcode_tid ot; 671 __be16 cpuno; 672 __be16 rsvd; 673 }; 674 675 struct cpl_get_tcb_rpl { 676 RSS_HDR 677 union opcode_tid ot; 678 __u8 rsvd; 679 __u8 status; 680 __be16 len; 681 }; 682 683 struct cpl_set_tcb { 684 WR_HDR; 685 union opcode_tid ot; 686 __u8 reply; 687 __u8 cpu_idx; 688 __be16 len; 689 }; 690 691 /* cpl_set_tcb.reply fields */ 692 #define S_NO_REPLY 7 693 #define V_NO_REPLY(x) ((x) << S_NO_REPLY) 694 #define F_NO_REPLY V_NO_REPLY(1U) 695 696 struct cpl_set_tcb_field { 697 WR_HDR; 698 union opcode_tid ot; 699 __u8 reply; 700 __u8 cpu_idx; 701 __be16 word; 702 __be64 mask; 703 __be64 val; 704 }; 705 706 struct cpl_set_tcb_rpl { 707 RSS_HDR 708 union opcode_tid ot; 709 __u8 rsvd[3]; 710 __u8 status; 711 }; 712 713 struct cpl_pcmd { 714 WR_HDR; 715 union opcode_tid ot; 716 __u8 rsvd[3]; 717 #if defined(__LITTLE_ENDIAN_BITFIELD) 718 __u8 src:1; 719 __u8 bundle:1; 720 __u8 channel:1; 721 __u8 :5; 722 #else 723 __u8 :5; 724 __u8 channel:1; 725 __u8 bundle:1; 726 __u8 src:1; 727 #endif 728 __be32 pcmd_parm[2]; 729 }; 730 731 struct cpl_pcmd_reply { 732 RSS_HDR 733 union opcode_tid ot; 734 __u8 status; 735 __u8 rsvd; 736 __be16 len; 737 }; 738 739 struct cpl_close_con_req { 740 WR_HDR; 741 union opcode_tid ot; 742 __be32 rsvd; 743 }; 744 745 struct cpl_close_con_rpl { 746 RSS_HDR 747 union opcode_tid ot; 748 __u8 rsvd[3]; 749 __u8 status; 750 __be32 snd_nxt; 751 __be32 rcv_nxt; 752 }; 753 754 struct cpl_close_listserv_req { 755 WR_HDR; 756 union opcode_tid ot; 757 __u8 rsvd0; 758 __u8 cpu_idx; 759 __be16 rsvd1; 760 }; 761 762 struct cpl_close_listserv_rpl { 763 RSS_HDR 764 union opcode_tid ot; 765 __u8 rsvd[3]; 766 __u8 status; 767 }; 768 769 struct cpl_abort_req_rss { 770 RSS_HDR 771 union opcode_tid ot; 772 __be32 rsvd0; 773 __u8 rsvd1; 774 __u8 status; 775 __u8 rsvd2[6]; 776 }; 777 778 struct cpl_abort_req { 779 WR_HDR; 780 union opcode_tid ot; 781 __be32 rsvd0; 782 __u8 rsvd1; 783 __u8 cmd; 784 __u8 rsvd2[6]; 785 }; 786 787 struct cpl_abort_rpl_rss { 788 RSS_HDR 789 union opcode_tid ot; 790 __be32 rsvd0; 791 __u8 rsvd1; 792 __u8 status; 793 __u8 rsvd2[6]; 794 }; 795 796 struct cpl_abort_rpl { 797 WR_HDR; 798 union opcode_tid ot; 799 __be32 rsvd0; 800 __u8 rsvd1; 801 __u8 cmd; 802 __u8 rsvd2[6]; 803 }; 804 805 struct cpl_peer_close { 806 RSS_HDR 807 union opcode_tid ot; 808 __be32 rcv_nxt; 809 }; 810 811 struct tx_data_wr { 812 __be32 wr_hi; 813 __be32 wr_lo; 814 __be32 len; 815 __be32 flags; 816 __be32 sndseq; 817 __be32 param; 818 }; 819 820 /* tx_data_wr.flags fields */ 821 #define S_TX_ACK_PAGES 21 822 #define M_TX_ACK_PAGES 0x7 823 #define V_TX_ACK_PAGES(x) ((x) << S_TX_ACK_PAGES) 824 #define G_TX_ACK_PAGES(x) (((x) >> S_TX_ACK_PAGES) & M_TX_ACK_PAGES) 825 826 /* tx_data_wr.param fields */ 827 #define S_TX_PORT 0 828 #define M_TX_PORT 0x7 829 #define V_TX_PORT(x) ((x) << S_TX_PORT) 830 #define G_TX_PORT(x) (((x) >> S_TX_PORT) & M_TX_PORT) 831 832 #define S_TX_MSS 4 833 #define M_TX_MSS 0xF 834 #define V_TX_MSS(x) ((x) << S_TX_MSS) 835 #define G_TX_MSS(x) (((x) >> S_TX_MSS) & M_TX_MSS) 836 837 #define S_TX_QOS 8 838 #define M_TX_QOS 0xFF 839 #define V_TX_QOS(x) ((x) << S_TX_QOS) 840 #define G_TX_QOS(x) (((x) >> S_TX_QOS) & M_TX_QOS) 841 842 #define S_TX_SNDBUF 16 843 #define M_TX_SNDBUF 0xFFFF 844 #define V_TX_SNDBUF(x) ((x) << S_TX_SNDBUF) 845 #define G_TX_SNDBUF(x) (((x) >> S_TX_SNDBUF) & M_TX_SNDBUF) 846 847 struct cpl_tx_data { 848 union opcode_tid ot; 849 __be32 len; 850 __be32 rsvd; 851 __be16 urg; 852 __be16 flags; 853 }; 854 855 /* cpl_tx_data.flags fields */ 856 #define S_TX_ULP_SUBMODE 6 857 #define M_TX_ULP_SUBMODE 0xF 858 #define V_TX_ULP_SUBMODE(x) ((x) << S_TX_ULP_SUBMODE) 859 #define G_TX_ULP_SUBMODE(x) (((x) >> S_TX_ULP_SUBMODE) & M_TX_ULP_SUBMODE) 860 861 #define S_TX_ULP_MODE 10 862 #define M_TX_ULP_MODE 0xF 863 #define V_TX_ULP_MODE(x) ((x) << S_TX_ULP_MODE) 864 #define G_TX_ULP_MODE(x) (((x) >> S_TX_ULP_MODE) & M_TX_ULP_MODE) 865 866 #define S_TX_SHOVE 14 867 #define V_TX_SHOVE(x) ((x) << S_TX_SHOVE) 868 #define F_TX_SHOVE V_TX_SHOVE(1U) 869 870 #define S_TX_MORE 15 871 #define V_TX_MORE(x) ((x) << S_TX_MORE) 872 #define F_TX_MORE V_TX_MORE(1U) 873 874 /* additional tx_data_wr.flags fields */ 875 #define S_TX_CPU_IDX 0 876 #define M_TX_CPU_IDX 0x3F 877 #define V_TX_CPU_IDX(x) ((x) << S_TX_CPU_IDX) 878 #define G_TX_CPU_IDX(x) (((x) >> S_TX_CPU_IDX) & M_TX_CPU_IDX) 879 880 #define S_TX_URG 16 881 #define V_TX_URG(x) ((x) << S_TX_URG) 882 #define F_TX_URG V_TX_URG(1U) 883 884 #define S_TX_CLOSE 17 885 #define V_TX_CLOSE(x) ((x) << S_TX_CLOSE) 886 #define F_TX_CLOSE V_TX_CLOSE(1U) 887 888 #define S_TX_INIT 18 889 #define V_TX_INIT(x) ((x) << S_TX_INIT) 890 #define F_TX_INIT V_TX_INIT(1U) 891 892 #define S_TX_IMM_ACK 19 893 #define V_TX_IMM_ACK(x) ((x) << S_TX_IMM_ACK) 894 #define F_TX_IMM_ACK V_TX_IMM_ACK(1U) 895 896 #define S_TX_IMM_DMA 20 897 #define V_TX_IMM_DMA(x) ((x) << S_TX_IMM_DMA) 898 #define F_TX_IMM_DMA V_TX_IMM_DMA(1U) 899 900 struct cpl_tx_data_ack { 901 RSS_HDR 902 union opcode_tid ot; 903 __be32 ack_seq; 904 }; 905 906 struct cpl_wr_ack { 907 RSS_HDR 908 union opcode_tid ot; 909 __be16 credits; 910 __be16 rsvd; 911 __be32 snd_nxt; 912 __be32 snd_una; 913 }; 914 915 struct cpl_sge_ec_cr_return { 916 RSS_HDR 917 union opcode_tid ot; 918 __be16 sge_ec_id; 919 __u8 cr; 920 __u8 rsvd; 921 }; 922 923 struct cpl_rdma_ec_status { 924 RSS_HDR 925 union opcode_tid ot; 926 __u8 rsvd[3]; 927 __u8 status; 928 }; 929 930 struct mngt_pktsched_wr { 931 __be32 wr_hi; 932 __be32 wr_lo; 933 __u8 mngt_opcode; 934 __u8 rsvd[7]; 935 __u8 sched; 936 __u8 idx; 937 __u8 min; 938 __u8 max; 939 __u8 binding; 940 __u8 rsvd1[3]; 941 }; 942 943 struct cpl_iscsi_hdr { 944 RSS_HDR 945 union opcode_tid ot; 946 __be16 pdu_len_ddp; 947 __be16 len; 948 __be32 seq; 949 __be16 urg; 950 __u8 rsvd; 951 __u8 status; 952 }; 953 954 /* cpl_iscsi_hdr.pdu_len_ddp fields */ 955 #define S_ISCSI_PDU_LEN 0 956 #define M_ISCSI_PDU_LEN 0x7FFF 957 #define V_ISCSI_PDU_LEN(x) ((x) << S_ISCSI_PDU_LEN) 958 #define G_ISCSI_PDU_LEN(x) (((x) >> S_ISCSI_PDU_LEN) & M_ISCSI_PDU_LEN) 959 960 #define S_ISCSI_DDP 15 961 #define V_ISCSI_DDP(x) ((x) << S_ISCSI_DDP) 962 #define F_ISCSI_DDP V_ISCSI_DDP(1U) 963 964 struct cpl_rx_data { 965 RSS_HDR 966 union opcode_tid ot; 967 __be16 rsvd; 968 __be16 len; 969 __be32 seq; 970 __be16 urg; 971 #if defined(__LITTLE_ENDIAN_BITFIELD) 972 __u8 dack_mode:2; 973 __u8 psh:1; 974 __u8 heartbeat:1; 975 __u8 ddp_off:1; 976 __u8 :3; 977 #else 978 __u8 :3; 979 __u8 ddp_off:1; 980 __u8 heartbeat:1; 981 __u8 psh:1; 982 __u8 dack_mode:2; 983 #endif 984 __u8 status; 985 }; 986 987 struct cpl_rx_data_ack { 988 WR_HDR; 989 union opcode_tid ot; 990 __be32 credit_dack; 991 }; 992 993 /* cpl_rx_data_ack.ack_seq fields */ 994 #define S_RX_CREDITS 0 995 #define M_RX_CREDITS 0x7FFFFFF 996 #define V_RX_CREDITS(x) ((x) << S_RX_CREDITS) 997 #define G_RX_CREDITS(x) (((x) >> S_RX_CREDITS) & M_RX_CREDITS) 998 999 #define S_RX_MODULATE 27 1000 #define V_RX_MODULATE(x) ((x) << S_RX_MODULATE) 1001 #define F_RX_MODULATE V_RX_MODULATE(1U) 1002 1003 #define S_RX_FORCE_ACK 28 1004 #define V_RX_FORCE_ACK(x) ((x) << S_RX_FORCE_ACK) 1005 #define F_RX_FORCE_ACK V_RX_FORCE_ACK(1U) 1006 1007 #define S_RX_DACK_MODE 29 1008 #define M_RX_DACK_MODE 0x3 1009 #define V_RX_DACK_MODE(x) ((x) << S_RX_DACK_MODE) 1010 #define G_RX_DACK_MODE(x) (((x) >> S_RX_DACK_MODE) & M_RX_DACK_MODE) 1011 1012 #define S_RX_DACK_CHANGE 31 1013 #define V_RX_DACK_CHANGE(x) ((x) << S_RX_DACK_CHANGE) 1014 #define F_RX_DACK_CHANGE V_RX_DACK_CHANGE(1U) 1015 1016 struct cpl_rx_urg_notify { 1017 RSS_HDR 1018 union opcode_tid ot; 1019 __be32 seq; 1020 }; 1021 1022 struct cpl_rx_ddp_complete { 1023 RSS_HDR 1024 union opcode_tid ot; 1025 __be32 ddp_report; 1026 }; 1027 1028 struct cpl_rx_data_ddp { 1029 RSS_HDR 1030 union opcode_tid ot; 1031 __be16 urg; 1032 __be16 len; 1033 __be32 seq; 1034 union { 1035 __be32 nxt_seq; 1036 __be32 ddp_report; 1037 } u; 1038 __be32 ulp_crc; 1039 __be32 ddpvld_status; 1040 }; 1041 1042 /* cpl_rx_data_ddp.ddpvld_status fields */ 1043 #define S_DDP_STATUS 0 1044 #define M_DDP_STATUS 0xFF 1045 #define V_DDP_STATUS(x) ((x) << S_DDP_STATUS) 1046 #define G_DDP_STATUS(x) (((x) >> S_DDP_STATUS) & M_DDP_STATUS) 1047 1048 #define S_DDP_VALID 15 1049 #define M_DDP_VALID 0x1FFFF 1050 #define V_DDP_VALID(x) ((x) << S_DDP_VALID) 1051 #define G_DDP_VALID(x) (((x) >> S_DDP_VALID) & M_DDP_VALID) 1052 1053 #define S_DDP_PPOD_MISMATCH 15 1054 #define V_DDP_PPOD_MISMATCH(x) ((x) << S_DDP_PPOD_MISMATCH) 1055 #define F_DDP_PPOD_MISMATCH V_DDP_PPOD_MISMATCH(1U) 1056 1057 #define S_DDP_PDU 16 1058 #define V_DDP_PDU(x) ((x) << S_DDP_PDU) 1059 #define F_DDP_PDU V_DDP_PDU(1U) 1060 1061 #define S_DDP_LLIMIT_ERR 17 1062 #define V_DDP_LLIMIT_ERR(x) ((x) << S_DDP_LLIMIT_ERR) 1063 #define F_DDP_LLIMIT_ERR V_DDP_LLIMIT_ERR(1U) 1064 1065 #define S_DDP_PPOD_PARITY_ERR 18 1066 #define V_DDP_PPOD_PARITY_ERR(x) ((x) << S_DDP_PPOD_PARITY_ERR) 1067 #define F_DDP_PPOD_PARITY_ERR V_DDP_PPOD_PARITY_ERR(1U) 1068 1069 #define S_DDP_PADDING_ERR 19 1070 #define V_DDP_PADDING_ERR(x) ((x) << S_DDP_PADDING_ERR) 1071 #define F_DDP_PADDING_ERR V_DDP_PADDING_ERR(1U) 1072 1073 #define S_DDP_HDRCRC_ERR 20 1074 #define V_DDP_HDRCRC_ERR(x) ((x) << S_DDP_HDRCRC_ERR) 1075 #define F_DDP_HDRCRC_ERR V_DDP_HDRCRC_ERR(1U) 1076 1077 #define S_DDP_DATACRC_ERR 21 1078 #define V_DDP_DATACRC_ERR(x) ((x) << S_DDP_DATACRC_ERR) 1079 #define F_DDP_DATACRC_ERR V_DDP_DATACRC_ERR(1U) 1080 1081 #define S_DDP_INVALID_TAG 22 1082 #define V_DDP_INVALID_TAG(x) ((x) << S_DDP_INVALID_TAG) 1083 #define F_DDP_INVALID_TAG V_DDP_INVALID_TAG(1U) 1084 1085 #define S_DDP_ULIMIT_ERR 23 1086 #define V_DDP_ULIMIT_ERR(x) ((x) << S_DDP_ULIMIT_ERR) 1087 #define F_DDP_ULIMIT_ERR V_DDP_ULIMIT_ERR(1U) 1088 1089 #define S_DDP_OFFSET_ERR 24 1090 #define V_DDP_OFFSET_ERR(x) ((x) << S_DDP_OFFSET_ERR) 1091 #define F_DDP_OFFSET_ERR V_DDP_OFFSET_ERR(1U) 1092 1093 #define S_DDP_COLOR_ERR 25 1094 #define V_DDP_COLOR_ERR(x) ((x) << S_DDP_COLOR_ERR) 1095 #define F_DDP_COLOR_ERR V_DDP_COLOR_ERR(1U) 1096 1097 #define S_DDP_TID_MISMATCH 26 1098 #define V_DDP_TID_MISMATCH(x) ((x) << S_DDP_TID_MISMATCH) 1099 #define F_DDP_TID_MISMATCH V_DDP_TID_MISMATCH(1U) 1100 1101 #define S_DDP_INVALID_PPOD 27 1102 #define V_DDP_INVALID_PPOD(x) ((x) << S_DDP_INVALID_PPOD) 1103 #define F_DDP_INVALID_PPOD V_DDP_INVALID_PPOD(1U) 1104 1105 #define S_DDP_ULP_MODE 28 1106 #define M_DDP_ULP_MODE 0xF 1107 #define V_DDP_ULP_MODE(x) ((x) << S_DDP_ULP_MODE) 1108 #define G_DDP_ULP_MODE(x) (((x) >> S_DDP_ULP_MODE) & M_DDP_ULP_MODE) 1109 1110 /* cpl_rx_data_ddp.ddp_report fields */ 1111 #define S_DDP_OFFSET 0 1112 #define M_DDP_OFFSET 0x3FFFFF 1113 #define V_DDP_OFFSET(x) ((x) << S_DDP_OFFSET) 1114 #define G_DDP_OFFSET(x) (((x) >> S_DDP_OFFSET) & M_DDP_OFFSET) 1115 1116 #define S_DDP_DACK_MODE 22 1117 #define M_DDP_DACK_MODE 0x3 1118 #define V_DDP_DACK_MODE(x) ((x) << S_DDP_DACK_MODE) 1119 #define G_DDP_DACK_MODE(x) (((x) >> S_DDP_DACK_MODE) & M_DDP_DACK_MODE) 1120 1121 #define S_DDP_URG 24 1122 #define V_DDP_URG(x) ((x) << S_DDP_URG) 1123 #define F_DDP_URG V_DDP_URG(1U) 1124 1125 #define S_DDP_PSH 25 1126 #define V_DDP_PSH(x) ((x) << S_DDP_PSH) 1127 #define F_DDP_PSH V_DDP_PSH(1U) 1128 1129 #define S_DDP_BUF_COMPLETE 26 1130 #define V_DDP_BUF_COMPLETE(x) ((x) << S_DDP_BUF_COMPLETE) 1131 #define F_DDP_BUF_COMPLETE V_DDP_BUF_COMPLETE(1U) 1132 1133 #define S_DDP_BUF_TIMED_OUT 27 1134 #define V_DDP_BUF_TIMED_OUT(x) ((x) << S_DDP_BUF_TIMED_OUT) 1135 #define F_DDP_BUF_TIMED_OUT V_DDP_BUF_TIMED_OUT(1U) 1136 1137 #define S_DDP_BUF_IDX 28 1138 #define V_DDP_BUF_IDX(x) ((x) << S_DDP_BUF_IDX) 1139 #define F_DDP_BUF_IDX V_DDP_BUF_IDX(1U) 1140 1141 struct cpl_tx_pkt { 1142 WR_HDR; 1143 __be32 cntrl; 1144 __be32 len; 1145 }; 1146 1147 struct cpl_tx_pkt_coalesce { 1148 __be32 cntrl; 1149 __be32 len; 1150 __be64 addr; 1151 }; 1152 1153 struct tx_pkt_coalesce_wr { 1154 WR_HDR; 1155 struct cpl_tx_pkt_coalesce cpl[0]; 1156 }; 1157 1158 struct cpl_tx_pkt_lso { 1159 WR_HDR; 1160 __be32 cntrl; 1161 __be32 len; 1162 1163 __be32 rsvd; 1164 __be32 lso_info; 1165 }; 1166 1167 struct cpl_tx_pkt_batch_entry { 1168 __be32 cntrl; 1169 __be32 len; 1170 __be64 addr; 1171 }; 1172 1173 struct cpl_tx_pkt_batch { 1174 WR_HDR; 1175 struct cpl_tx_pkt_batch_entry pkt_entry[7]; 1176 }; 1177 1178 1179 /* cpl_tx_pkt*.cntrl fields */ 1180 #define S_TXPKT_VLAN 0 1181 #define M_TXPKT_VLAN 0xFFFF 1182 #define V_TXPKT_VLAN(x) ((x) << S_TXPKT_VLAN) 1183 #define G_TXPKT_VLAN(x) (((x) >> S_TXPKT_VLAN) & M_TXPKT_VLAN) 1184 1185 #define S_TXPKT_INTF 16 1186 #define M_TXPKT_INTF 0xF 1187 #define V_TXPKT_INTF(x) ((x) << S_TXPKT_INTF) 1188 #define G_TXPKT_INTF(x) (((x) >> S_TXPKT_INTF) & M_TXPKT_INTF) 1189 1190 #define S_TXPKT_IPCSUM_DIS 20 1191 #define V_TXPKT_IPCSUM_DIS(x) ((x) << S_TXPKT_IPCSUM_DIS) 1192 #define F_TXPKT_IPCSUM_DIS V_TXPKT_IPCSUM_DIS(1U) 1193 1194 #define S_TXPKT_L4CSUM_DIS 21 1195 #define V_TXPKT_L4CSUM_DIS(x) ((x) << S_TXPKT_L4CSUM_DIS) 1196 #define F_TXPKT_L4CSUM_DIS V_TXPKT_L4CSUM_DIS(1U) 1197 1198 #define S_TXPKT_VLAN_VLD 22 1199 #define V_TXPKT_VLAN_VLD(x) ((x) << S_TXPKT_VLAN_VLD) 1200 #define F_TXPKT_VLAN_VLD V_TXPKT_VLAN_VLD(1U) 1201 1202 #define S_TXPKT_LOOPBACK 23 1203 #define V_TXPKT_LOOPBACK(x) ((x) << S_TXPKT_LOOPBACK) 1204 #define F_TXPKT_LOOPBACK V_TXPKT_LOOPBACK(1U) 1205 1206 #define S_TXPKT_OPCODE 24 1207 #define M_TXPKT_OPCODE 0xFF 1208 #define V_TXPKT_OPCODE(x) ((x) << S_TXPKT_OPCODE) 1209 #define G_TXPKT_OPCODE(x) (((x) >> S_TXPKT_OPCODE) & M_TXPKT_OPCODE) 1210 1211 /* cpl_tx_pkt_lso.lso_info fields */ 1212 #define S_LSO_MSS 0 1213 #define M_LSO_MSS 0x3FFF 1214 #define V_LSO_MSS(x) ((x) << S_LSO_MSS) 1215 #define G_LSO_MSS(x) (((x) >> S_LSO_MSS) & M_LSO_MSS) 1216 1217 #define S_LSO_ETH_TYPE 14 1218 #define M_LSO_ETH_TYPE 0x3 1219 #define V_LSO_ETH_TYPE(x) ((x) << S_LSO_ETH_TYPE) 1220 #define G_LSO_ETH_TYPE(x) (((x) >> S_LSO_ETH_TYPE) & M_LSO_ETH_TYPE) 1221 1222 #define S_LSO_TCPHDR_WORDS 16 1223 #define M_LSO_TCPHDR_WORDS 0xF 1224 #define V_LSO_TCPHDR_WORDS(x) ((x) << S_LSO_TCPHDR_WORDS) 1225 #define G_LSO_TCPHDR_WORDS(x) (((x) >> S_LSO_TCPHDR_WORDS) & M_LSO_TCPHDR_WORDS) 1226 1227 #define S_LSO_IPHDR_WORDS 20 1228 #define M_LSO_IPHDR_WORDS 0xF 1229 #define V_LSO_IPHDR_WORDS(x) ((x) << S_LSO_IPHDR_WORDS) 1230 #define G_LSO_IPHDR_WORDS(x) (((x) >> S_LSO_IPHDR_WORDS) & M_LSO_IPHDR_WORDS) 1231 1232 #define S_LSO_IPV6 24 1233 #define V_LSO_IPV6(x) ((x) << S_LSO_IPV6) 1234 #define F_LSO_IPV6 V_LSO_IPV6(1U) 1235 1236 struct cpl_trace_pkt { 1237 #ifdef CHELSIO_FW 1238 __u8 rss_opcode; 1239 #if defined(__LITTLE_ENDIAN_BITFIELD) 1240 __u8 err:1; 1241 __u8 :7; 1242 #else 1243 __u8 :7; 1244 __u8 err:1; 1245 #endif 1246 __u8 rsvd0; 1247 #if defined(__LITTLE_ENDIAN_BITFIELD) 1248 __u8 qid:4; 1249 __u8 :4; 1250 #else 1251 __u8 :4; 1252 __u8 qid:4; 1253 #endif 1254 __be32 tstamp; 1255 #endif /* CHELSIO_FW */ 1256 1257 __u8 opcode; 1258 #if defined(__LITTLE_ENDIAN_BITFIELD) 1259 __u8 iff:4; 1260 __u8 :4; 1261 #else 1262 __u8 :4; 1263 __u8 iff:4; 1264 #endif 1265 __u8 rsvd[4]; 1266 __be16 len; 1267 }; 1268 1269 struct cpl_rx_pkt { 1270 RSS_HDR 1271 __u8 opcode; 1272 #if defined(__LITTLE_ENDIAN_BITFIELD) 1273 __u8 iff:4; 1274 __u8 csum_valid:1; 1275 __u8 ipmi_pkt:1; 1276 __u8 vlan_valid:1; 1277 __u8 fragment:1; 1278 #else 1279 __u8 fragment:1; 1280 __u8 vlan_valid:1; 1281 __u8 ipmi_pkt:1; 1282 __u8 csum_valid:1; 1283 __u8 iff:4; 1284 #endif 1285 __be16 csum; 1286 __be16 vlan; 1287 __be16 len; 1288 }; 1289 1290 struct cpl_l2t_write_req { 1291 WR_HDR; 1292 union opcode_tid ot; 1293 __be32 params; 1294 __u8 rsvd; 1295 __u8 port_idx; 1296 __u8 dst_mac[6]; 1297 }; 1298 1299 /* cpl_l2t_write_req.params fields */ 1300 #define S_L2T_W_IDX 0 1301 #define M_L2T_W_IDX 0x7FF 1302 #define V_L2T_W_IDX(x) ((x) << S_L2T_W_IDX) 1303 #define G_L2T_W_IDX(x) (((x) >> S_L2T_W_IDX) & M_L2T_W_IDX) 1304 1305 #define S_L2T_W_VLAN 11 1306 #define M_L2T_W_VLAN 0xFFF 1307 #define V_L2T_W_VLAN(x) ((x) << S_L2T_W_VLAN) 1308 #define G_L2T_W_VLAN(x) (((x) >> S_L2T_W_VLAN) & M_L2T_W_VLAN) 1309 1310 #define S_L2T_W_IFF 23 1311 #define M_L2T_W_IFF 0xF 1312 #define V_L2T_W_IFF(x) ((x) << S_L2T_W_IFF) 1313 #define G_L2T_W_IFF(x) (((x) >> S_L2T_W_IFF) & M_L2T_W_IFF) 1314 1315 #define S_L2T_W_PRIO 27 1316 #define M_L2T_W_PRIO 0x7 1317 #define V_L2T_W_PRIO(x) ((x) << S_L2T_W_PRIO) 1318 #define G_L2T_W_PRIO(x) (((x) >> S_L2T_W_PRIO) & M_L2T_W_PRIO) 1319 1320 struct cpl_l2t_write_rpl { 1321 RSS_HDR 1322 union opcode_tid ot; 1323 __u8 status; 1324 __u8 rsvd[3]; 1325 }; 1326 1327 struct cpl_l2t_read_req { 1328 WR_HDR; 1329 union opcode_tid ot; 1330 __be16 rsvd; 1331 __be16 l2t_idx; 1332 }; 1333 1334 struct cpl_l2t_read_rpl { 1335 RSS_HDR 1336 union opcode_tid ot; 1337 __be32 params; 1338 __u8 rsvd[2]; 1339 __u8 dst_mac[6]; 1340 }; 1341 1342 /* cpl_l2t_read_rpl.params fields */ 1343 #define S_L2T_R_PRIO 0 1344 #define M_L2T_R_PRIO 0x7 1345 #define V_L2T_R_PRIO(x) ((x) << S_L2T_R_PRIO) 1346 #define G_L2T_R_PRIO(x) (((x) >> S_L2T_R_PRIO) & M_L2T_R_PRIO) 1347 1348 #define S_L2T_R_VLAN 8 1349 #define M_L2T_R_VLAN 0xFFF 1350 #define V_L2T_R_VLAN(x) ((x) << S_L2T_R_VLAN) 1351 #define G_L2T_R_VLAN(x) (((x) >> S_L2T_R_VLAN) & M_L2T_R_VLAN) 1352 1353 #define S_L2T_R_IFF 20 1354 #define M_L2T_R_IFF 0xF 1355 #define V_L2T_R_IFF(x) ((x) << S_L2T_R_IFF) 1356 #define G_L2T_R_IFF(x) (((x) >> S_L2T_R_IFF) & M_L2T_R_IFF) 1357 1358 #define S_L2T_STATUS 24 1359 #define M_L2T_STATUS 0xFF 1360 #define V_L2T_STATUS(x) ((x) << S_L2T_STATUS) 1361 #define G_L2T_STATUS(x) (((x) >> S_L2T_STATUS) & M_L2T_STATUS) 1362 1363 struct cpl_smt_write_req { 1364 WR_HDR; 1365 union opcode_tid ot; 1366 __u8 rsvd0; 1367 #if defined(__LITTLE_ENDIAN_BITFIELD) 1368 __u8 mtu_idx:4; 1369 __u8 iff:4; 1370 #else 1371 __u8 iff:4; 1372 __u8 mtu_idx:4; 1373 #endif 1374 __be16 rsvd2; 1375 __be16 rsvd3; 1376 __u8 src_mac1[6]; 1377 __be16 rsvd4; 1378 __u8 src_mac0[6]; 1379 }; 1380 1381 struct cpl_smt_write_rpl { 1382 RSS_HDR 1383 union opcode_tid ot; 1384 __u8 status; 1385 __u8 rsvd[3]; 1386 }; 1387 1388 struct cpl_smt_read_req { 1389 WR_HDR; 1390 union opcode_tid ot; 1391 __u8 rsvd0; 1392 #if defined(__LITTLE_ENDIAN_BITFIELD) 1393 __u8 :4; 1394 __u8 iff:4; 1395 #else 1396 __u8 iff:4; 1397 __u8 :4; 1398 #endif 1399 __be16 rsvd2; 1400 }; 1401 1402 struct cpl_smt_read_rpl { 1403 RSS_HDR 1404 union opcode_tid ot; 1405 __u8 status; 1406 #if defined(__LITTLE_ENDIAN_BITFIELD) 1407 __u8 mtu_idx:4; 1408 __u8 :4; 1409 #else 1410 __u8 :4; 1411 __u8 mtu_idx:4; 1412 #endif 1413 __be16 rsvd2; 1414 __be16 rsvd3; 1415 __u8 src_mac1[6]; 1416 __be16 rsvd4; 1417 __u8 src_mac0[6]; 1418 }; 1419 1420 struct cpl_rte_delete_req { 1421 WR_HDR; 1422 union opcode_tid ot; 1423 __be32 params; 1424 }; 1425 1426 /* { cpl_rte_delete_req, cpl_rte_read_req }.params fields */ 1427 #define S_RTE_REQ_LUT_IX 8 1428 #define M_RTE_REQ_LUT_IX 0x7FF 1429 #define V_RTE_REQ_LUT_IX(x) ((x) << S_RTE_REQ_LUT_IX) 1430 #define G_RTE_REQ_LUT_IX(x) (((x) >> S_RTE_REQ_LUT_IX) & M_RTE_REQ_LUT_IX) 1431 1432 #define S_RTE_REQ_LUT_BASE 19 1433 #define M_RTE_REQ_LUT_BASE 0x7FF 1434 #define V_RTE_REQ_LUT_BASE(x) ((x) << S_RTE_REQ_LUT_BASE) 1435 #define G_RTE_REQ_LUT_BASE(x) (((x) >> S_RTE_REQ_LUT_BASE) & M_RTE_REQ_LUT_BASE) 1436 1437 #define S_RTE_READ_REQ_SELECT 31 1438 #define V_RTE_READ_REQ_SELECT(x) ((x) << S_RTE_READ_REQ_SELECT) 1439 #define F_RTE_READ_REQ_SELECT V_RTE_READ_REQ_SELECT(1U) 1440 1441 struct cpl_rte_delete_rpl { 1442 RSS_HDR 1443 union opcode_tid ot; 1444 __u8 status; 1445 __u8 rsvd[3]; 1446 }; 1447 1448 struct cpl_rte_write_req { 1449 WR_HDR; 1450 union opcode_tid ot; 1451 #if defined(__LITTLE_ENDIAN_BITFIELD) 1452 __u8 :6; 1453 __u8 write_tcam:1; 1454 __u8 write_l2t_lut:1; 1455 #else 1456 __u8 write_l2t_lut:1; 1457 __u8 write_tcam:1; 1458 __u8 :6; 1459 #endif 1460 __u8 rsvd[3]; 1461 __be32 lut_params; 1462 __be16 rsvd2; 1463 __be16 l2t_idx; 1464 __be32 netmask; 1465 __be32 faddr; 1466 }; 1467 1468 /* cpl_rte_write_req.lut_params fields */ 1469 #define S_RTE_WRITE_REQ_LUT_IX 10 1470 #define M_RTE_WRITE_REQ_LUT_IX 0x7FF 1471 #define V_RTE_WRITE_REQ_LUT_IX(x) ((x) << S_RTE_WRITE_REQ_LUT_IX) 1472 #define G_RTE_WRITE_REQ_LUT_IX(x) (((x) >> S_RTE_WRITE_REQ_LUT_IX) & M_RTE_WRITE_REQ_LUT_IX) 1473 1474 #define S_RTE_WRITE_REQ_LUT_BASE 21 1475 #define M_RTE_WRITE_REQ_LUT_BASE 0x7FF 1476 #define V_RTE_WRITE_REQ_LUT_BASE(x) ((x) << S_RTE_WRITE_REQ_LUT_BASE) 1477 #define G_RTE_WRITE_REQ_LUT_BASE(x) (((x) >> S_RTE_WRITE_REQ_LUT_BASE) & M_RTE_WRITE_REQ_LUT_BASE) 1478 1479 struct cpl_rte_write_rpl { 1480 RSS_HDR 1481 union opcode_tid ot; 1482 __u8 status; 1483 __u8 rsvd[3]; 1484 }; 1485 1486 struct cpl_rte_read_req { 1487 WR_HDR; 1488 union opcode_tid ot; 1489 __be32 params; 1490 }; 1491 1492 struct cpl_rte_read_rpl { 1493 RSS_HDR 1494 union opcode_tid ot; 1495 __u8 status; 1496 __u8 rsvd0; 1497 __be16 l2t_idx; 1498 #if defined(__LITTLE_ENDIAN_BITFIELD) 1499 __u8 :7; 1500 __u8 select:1; 1501 #else 1502 __u8 select:1; 1503 __u8 :7; 1504 #endif 1505 __u8 rsvd2[3]; 1506 __be32 addr; 1507 }; 1508 1509 struct cpl_tid_release { 1510 WR_HDR; 1511 union opcode_tid ot; 1512 __be32 rsvd; 1513 }; 1514 1515 struct cpl_barrier { 1516 WR_HDR; 1517 __u8 opcode; 1518 __u8 rsvd[7]; 1519 }; 1520 1521 struct cpl_rdma_read_req { 1522 __u8 opcode; 1523 __u8 rsvd[15]; 1524 }; 1525 1526 struct cpl_rdma_terminate { 1527 #ifdef CHELSIO_FW 1528 __u8 opcode; 1529 __u8 rsvd[2]; 1530 #if defined(__LITTLE_ENDIAN_BITFIELD) 1531 __u8 rspq:3; 1532 __u8 :5; 1533 #else 1534 __u8 :5; 1535 __u8 rspq:3; 1536 #endif 1537 __be32 tid_len; 1538 #endif 1539 __be32 msn; 1540 __be32 mo; 1541 __u8 data[0]; 1542 }; 1543 1544 /* cpl_rdma_terminate.tid_len fields */ 1545 #define S_FLIT_CNT 0 1546 #define M_FLIT_CNT 0xFF 1547 #define V_FLIT_CNT(x) ((x) << S_FLIT_CNT) 1548 #define G_FLIT_CNT(x) (((x) >> S_FLIT_CNT) & M_FLIT_CNT) 1549 1550 #define S_TERM_TID 8 1551 #define M_TERM_TID 0xFFFFF 1552 #define V_TERM_TID(x) ((x) << S_TERM_TID) 1553 #define G_TERM_TID(x) (((x) >> S_TERM_TID) & M_TERM_TID) 1554 1555 /* ULP_TX opcodes */ 1556 enum { ULP_MEM_READ = 2, ULP_MEM_WRITE = 3, ULP_TXPKT = 4 }; 1557 1558 #define S_ULPTX_CMD 28 1559 #define M_ULPTX_CMD 0xF 1560 #define V_ULPTX_CMD(x) ((x) << S_ULPTX_CMD) 1561 1562 #define S_ULPTX_NFLITS 0 1563 #define M_ULPTX_NFLITS 0xFF 1564 #define V_ULPTX_NFLITS(x) ((x) << S_ULPTX_NFLITS) 1565 1566 struct ulp_mem_io { 1567 WR_HDR; 1568 __be32 cmd_lock_addr; 1569 __be32 len; 1570 }; 1571 1572 /* ulp_mem_io.cmd_lock_addr fields */ 1573 #define S_ULP_MEMIO_ADDR 0 1574 #define M_ULP_MEMIO_ADDR 0x7FFFFFF 1575 #define V_ULP_MEMIO_ADDR(x) ((x) << S_ULP_MEMIO_ADDR) 1576 1577 #define S_ULP_MEMIO_LOCK 27 1578 #define V_ULP_MEMIO_LOCK(x) ((x) << S_ULP_MEMIO_LOCK) 1579 #define F_ULP_MEMIO_LOCK V_ULP_MEMIO_LOCK(1U) 1580 1581 /* ulp_mem_io.len fields */ 1582 #define S_ULP_MEMIO_DATA_LEN 28 1583 #define M_ULP_MEMIO_DATA_LEN 0xF 1584 #define V_ULP_MEMIO_DATA_LEN(x) ((x) << S_ULP_MEMIO_DATA_LEN) 1585 1586 struct ulp_txpkt { 1587 __be32 cmd_dest; 1588 __be32 len; 1589 }; 1590 1591 /* ulp_txpkt.cmd_dest fields */ 1592 #define S_ULP_TXPKT_DEST 24 1593 #define M_ULP_TXPKT_DEST 0xF 1594 #define V_ULP_TXPKT_DEST(x) ((x) << S_ULP_TXPKT_DEST) 1595 1596 #endif /* T3_CPL_H */ 1597