1 /************************************************************************** 2 3 Copyright (c) 2007, Chelsio Inc. 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Chelsio Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 $FreeBSD$ 33 34 ***************************************************************************/ 35 #ifndef T3_CPL_H 36 #define T3_CPL_H 37 38 #if !defined(__LITTLE_ENDIAN_BITFIELD) && !defined(__BIG_ENDIAN_BITFIELD) 39 # include <asm/byteorder.h> 40 #endif 41 42 enum CPL_opcode { 43 CPL_PASS_OPEN_REQ = 0x1, 44 CPL_PASS_ACCEPT_RPL = 0x2, 45 CPL_ACT_OPEN_REQ = 0x3, 46 CPL_SET_TCB = 0x4, 47 CPL_SET_TCB_FIELD = 0x5, 48 CPL_GET_TCB = 0x6, 49 CPL_PCMD = 0x7, 50 CPL_CLOSE_CON_REQ = 0x8, 51 CPL_CLOSE_LISTSRV_REQ = 0x9, 52 CPL_ABORT_REQ = 0xA, 53 CPL_ABORT_RPL = 0xB, 54 CPL_TX_DATA = 0xC, 55 CPL_RX_DATA_ACK = 0xD, 56 CPL_TX_PKT = 0xE, 57 CPL_RTE_DELETE_REQ = 0xF, 58 CPL_RTE_WRITE_REQ = 0x10, 59 CPL_RTE_READ_REQ = 0x11, 60 CPL_L2T_WRITE_REQ = 0x12, 61 CPL_L2T_READ_REQ = 0x13, 62 CPL_SMT_WRITE_REQ = 0x14, 63 CPL_SMT_READ_REQ = 0x15, 64 CPL_TX_PKT_LSO = 0x16, 65 CPL_PCMD_READ = 0x17, 66 CPL_BARRIER = 0x18, 67 CPL_TID_RELEASE = 0x1A, 68 69 CPL_CLOSE_LISTSRV_RPL = 0x20, 70 CPL_ERROR = 0x21, 71 CPL_GET_TCB_RPL = 0x22, 72 CPL_L2T_WRITE_RPL = 0x23, 73 CPL_PCMD_READ_RPL = 0x24, 74 CPL_PCMD_RPL = 0x25, 75 CPL_PEER_CLOSE = 0x26, 76 CPL_RTE_DELETE_RPL = 0x27, 77 CPL_RTE_WRITE_RPL = 0x28, 78 CPL_RX_DDP_COMPLETE = 0x29, 79 CPL_RX_PHYS_ADDR = 0x2A, 80 CPL_RX_PKT = 0x2B, 81 CPL_RX_URG_NOTIFY = 0x2C, 82 CPL_SET_TCB_RPL = 0x2D, 83 CPL_SMT_WRITE_RPL = 0x2E, 84 CPL_TX_DATA_ACK = 0x2F, 85 86 CPL_ABORT_REQ_RSS = 0x30, 87 CPL_ABORT_RPL_RSS = 0x31, 88 CPL_CLOSE_CON_RPL = 0x32, 89 CPL_ISCSI_HDR = 0x33, 90 CPL_L2T_READ_RPL = 0x34, 91 CPL_RDMA_CQE = 0x35, 92 CPL_RDMA_CQE_READ_RSP = 0x36, 93 CPL_RDMA_CQE_ERR = 0x37, 94 CPL_RTE_READ_RPL = 0x38, 95 CPL_RX_DATA = 0x39, 96 97 CPL_ACT_OPEN_RPL = 0x40, 98 CPL_PASS_OPEN_RPL = 0x41, 99 CPL_RX_DATA_DDP = 0x42, 100 CPL_SMT_READ_RPL = 0x43, 101 102 CPL_ACT_ESTABLISH = 0x50, 103 CPL_PASS_ESTABLISH = 0x51, 104 105 CPL_PASS_ACCEPT_REQ = 0x70, 106 107 CPL_ASYNC_NOTIF = 0x80, /* fake opcode for async notifications */ 108 109 CPL_TX_DMA_ACK = 0xA0, 110 CPL_RDMA_READ_REQ = 0xA1, 111 CPL_RDMA_TERMINATE = 0xA2, 112 CPL_TRACE_PKT = 0xA3, 113 CPL_RDMA_EC_STATUS = 0xA5, 114 115 NUM_CPL_CMDS /* must be last and previous entries must be sorted */ 116 }; 117 118 enum CPL_error { 119 CPL_ERR_NONE = 0, 120 CPL_ERR_TCAM_PARITY = 1, 121 CPL_ERR_TCAM_FULL = 3, 122 CPL_ERR_CONN_RESET = 20, 123 CPL_ERR_CONN_EXIST = 22, 124 CPL_ERR_ARP_MISS = 23, 125 CPL_ERR_BAD_SYN = 24, 126 CPL_ERR_CONN_TIMEDOUT = 30, 127 CPL_ERR_XMIT_TIMEDOUT = 31, 128 CPL_ERR_PERSIST_TIMEDOUT = 32, 129 CPL_ERR_FINWAIT2_TIMEDOUT = 33, 130 CPL_ERR_KEEPALIVE_TIMEDOUT = 34, 131 CPL_ERR_RTX_NEG_ADVICE = 35, 132 CPL_ERR_PERSIST_NEG_ADVICE = 36, 133 CPL_ERR_ABORT_FAILED = 42, 134 CPL_ERR_GENERAL = 99 135 }; 136 137 enum { 138 CPL_CONN_POLICY_AUTO = 0, 139 CPL_CONN_POLICY_ASK = 1, 140 CPL_CONN_POLICY_DENY = 3 141 }; 142 143 enum { 144 ULP_MODE_NONE = 0, 145 ULP_MODE_TCP_DDP = 1, 146 ULP_MODE_ISCSI = 2, 147 ULP_MODE_RDMA = 4, 148 ULP_MODE_TCPDDP = 5 149 }; 150 151 enum { 152 ULP_CRC_HEADER = 1 << 0, 153 ULP_CRC_DATA = 1 << 1 154 }; 155 156 enum { 157 CPL_PASS_OPEN_ACCEPT, 158 CPL_PASS_OPEN_REJECT 159 }; 160 161 enum { 162 CPL_ABORT_SEND_RST = 0, 163 CPL_ABORT_NO_RST, 164 CPL_ABORT_POST_CLOSE_REQ = 2 165 }; 166 167 enum { /* TX_PKT_LSO ethernet types */ 168 CPL_ETH_II, 169 CPL_ETH_II_VLAN, 170 CPL_ETH_802_3, 171 CPL_ETH_802_3_VLAN 172 }; 173 174 enum { /* TCP congestion control algorithms */ 175 CONG_ALG_RENO, 176 CONG_ALG_TAHOE, 177 CONG_ALG_NEWRENO, 178 CONG_ALG_HIGHSPEED 179 }; 180 181 enum { /* RSS hash type */ 182 RSS_HASH_NONE = 0, 183 RSS_HASH_2_TUPLE = 1 << 0, 184 RSS_HASH_4_TUPLE = 1 << 1 185 }; 186 187 union opcode_tid { 188 __be32 opcode_tid; 189 __u8 opcode; 190 }; 191 192 #define S_OPCODE 24 193 #define V_OPCODE(x) ((x) << S_OPCODE) 194 #define G_OPCODE(x) (((x) >> S_OPCODE) & 0xFF) 195 #define G_TID(x) ((x) & 0xFFFFFF) 196 197 #define S_HASHTYPE 22 198 #define M_HASHTYPE 0x3 199 #define G_HASHTYPE(x) (((x) >> S_HASHTYPE) & M_HASHTYPE) 200 201 #define S_QNUM 0 202 #define G_QNUM(x) (((x) >> S_QNUM) & 0xFFFF) 203 204 /* tid is assumed to be 24-bits */ 205 #define MK_OPCODE_TID(opcode, tid) (V_OPCODE(opcode) | (tid)) 206 207 #define OPCODE_TID(cmd) ((cmd)->ot.opcode_tid) 208 209 /* extract the TID from a CPL command */ 210 #define GET_TID(cmd) (G_TID(ntohl(OPCODE_TID(cmd)))) 211 212 struct tcp_options { 213 __be16 mss; 214 __u8 wsf; 215 #if defined(__LITTLE_ENDIAN_BITFIELD) 216 __u8 :5; 217 __u8 ecn:1; 218 __u8 sack:1; 219 __u8 tstamp:1; 220 #else 221 __u8 tstamp:1; 222 __u8 sack:1; 223 __u8 ecn:1; 224 __u8 :5; 225 #endif 226 }; 227 228 struct rss_header { 229 __u8 opcode; 230 #if defined(__LITTLE_ENDIAN_BITFIELD) 231 __u8 cpu_idx:6; 232 __u8 hash_type:2; 233 #else 234 __u8 hash_type:2; 235 __u8 cpu_idx:6; 236 #endif 237 __be16 cq_idx; 238 __be32 rss_hash_val; 239 }; 240 241 #ifndef CHELSIO_FW 242 struct work_request_hdr { 243 __be32 wr_hi; 244 __be32 wr_lo; 245 }; 246 247 /* wr_hi fields */ 248 #define S_WR_SGE_CREDITS 0 249 #define M_WR_SGE_CREDITS 0xFF 250 #define V_WR_SGE_CREDITS(x) ((x) << S_WR_SGE_CREDITS) 251 #define G_WR_SGE_CREDITS(x) (((x) >> S_WR_SGE_CREDITS) & M_WR_SGE_CREDITS) 252 253 #define S_WR_SGLSFLT 8 254 #define M_WR_SGLSFLT 0xFF 255 #define V_WR_SGLSFLT(x) ((x) << S_WR_SGLSFLT) 256 #define G_WR_SGLSFLT(x) (((x) >> S_WR_SGLSFLT) & M_WR_SGLSFLT) 257 258 #define S_WR_BCNTLFLT 16 259 #define M_WR_BCNTLFLT 0xF 260 #define V_WR_BCNTLFLT(x) ((x) << S_WR_BCNTLFLT) 261 #define G_WR_BCNTLFLT(x) (((x) >> S_WR_BCNTLFLT) & M_WR_BCNTLFLT) 262 263 #define S_WR_DATATYPE 20 264 #define V_WR_DATATYPE(x) ((x) << S_WR_DATATYPE) 265 #define F_WR_DATATYPE V_WR_DATATYPE(1U) 266 267 #define S_WR_COMPL 21 268 #define V_WR_COMPL(x) ((x) << S_WR_COMPL) 269 #define F_WR_COMPL V_WR_COMPL(1U) 270 271 #define S_WR_EOP 22 272 #define V_WR_EOP(x) ((x) << S_WR_EOP) 273 #define F_WR_EOP V_WR_EOP(1U) 274 275 #define S_WR_SOP 23 276 #define V_WR_SOP(x) ((x) << S_WR_SOP) 277 #define F_WR_SOP V_WR_SOP(1U) 278 279 #define S_WR_OP 24 280 #define M_WR_OP 0xFF 281 #define V_WR_OP(x) ((x) << S_WR_OP) 282 #define G_WR_OP(x) (((x) >> S_WR_OP) & M_WR_OP) 283 284 /* wr_lo fields */ 285 #define S_WR_LEN 0 286 #define M_WR_LEN 0xFF 287 #define V_WR_LEN(x) ((x) << S_WR_LEN) 288 #define G_WR_LEN(x) (((x) >> S_WR_LEN) & M_WR_LEN) 289 290 #define S_WR_TID 8 291 #define M_WR_TID 0xFFFFF 292 #define V_WR_TID(x) ((x) << S_WR_TID) 293 #define G_WR_TID(x) (((x) >> S_WR_TID) & M_WR_TID) 294 295 #define S_WR_CR_FLUSH 30 296 #define V_WR_CR_FLUSH(x) ((x) << S_WR_CR_FLUSH) 297 #define F_WR_CR_FLUSH V_WR_CR_FLUSH(1U) 298 299 #define S_WR_GEN 31 300 #define V_WR_GEN(x) ((x) << S_WR_GEN) 301 #define F_WR_GEN V_WR_GEN(1U) 302 303 # define WR_HDR struct work_request_hdr wr 304 # define RSS_HDR 305 #else 306 # define WR_HDR 307 # define RSS_HDR struct rss_header rss_hdr; 308 #endif 309 310 /* option 0 lower-half fields */ 311 #define S_CPL_STATUS 0 312 #define M_CPL_STATUS 0xFF 313 #define V_CPL_STATUS(x) ((x) << S_CPL_STATUS) 314 #define G_CPL_STATUS(x) (((x) >> S_CPL_STATUS) & M_CPL_STATUS) 315 316 #define S_INJECT_TIMER 6 317 #define V_INJECT_TIMER(x) ((x) << S_INJECT_TIMER) 318 #define F_INJECT_TIMER V_INJECT_TIMER(1U) 319 320 #define S_NO_OFFLOAD 7 321 #define V_NO_OFFLOAD(x) ((x) << S_NO_OFFLOAD) 322 #define F_NO_OFFLOAD V_NO_OFFLOAD(1U) 323 324 #define S_ULP_MODE 8 325 #define M_ULP_MODE 0xF 326 #define V_ULP_MODE(x) ((x) << S_ULP_MODE) 327 #define G_ULP_MODE(x) (((x) >> S_ULP_MODE) & M_ULP_MODE) 328 329 #define S_RCV_BUFSIZ 12 330 #define M_RCV_BUFSIZ 0x3FFF 331 #define V_RCV_BUFSIZ(x) ((x) << S_RCV_BUFSIZ) 332 #define G_RCV_BUFSIZ(x) (((x) >> S_RCV_BUFSIZ) & M_RCV_BUFSIZ) 333 334 #define S_TOS 26 335 #define M_TOS 0x3F 336 #define V_TOS(x) ((x) << S_TOS) 337 #define G_TOS(x) (((x) >> S_TOS) & M_TOS) 338 339 /* option 0 upper-half fields */ 340 #define S_DELACK 0 341 #define V_DELACK(x) ((x) << S_DELACK) 342 #define F_DELACK V_DELACK(1U) 343 344 #define S_NO_CONG 1 345 #define V_NO_CONG(x) ((x) << S_NO_CONG) 346 #define F_NO_CONG V_NO_CONG(1U) 347 348 #define S_SRC_MAC_SEL 2 349 #define M_SRC_MAC_SEL 0x3 350 #define V_SRC_MAC_SEL(x) ((x) << S_SRC_MAC_SEL) 351 #define G_SRC_MAC_SEL(x) (((x) >> S_SRC_MAC_SEL) & M_SRC_MAC_SEL) 352 353 #define S_L2T_IDX 4 354 #define M_L2T_IDX 0x7FF 355 #define V_L2T_IDX(x) ((x) << S_L2T_IDX) 356 #define G_L2T_IDX(x) (((x) >> S_L2T_IDX) & M_L2T_IDX) 357 358 #define S_TX_CHANNEL 15 359 #define V_TX_CHANNEL(x) ((x) << S_TX_CHANNEL) 360 #define F_TX_CHANNEL V_TX_CHANNEL(1U) 361 362 #define S_TCAM_BYPASS 16 363 #define V_TCAM_BYPASS(x) ((x) << S_TCAM_BYPASS) 364 #define F_TCAM_BYPASS V_TCAM_BYPASS(1U) 365 366 #define S_NAGLE 17 367 #define V_NAGLE(x) ((x) << S_NAGLE) 368 #define F_NAGLE V_NAGLE(1U) 369 370 #define S_WND_SCALE 18 371 #define M_WND_SCALE 0xF 372 #define V_WND_SCALE(x) ((x) << S_WND_SCALE) 373 #define G_WND_SCALE(x) (((x) >> S_WND_SCALE) & M_WND_SCALE) 374 375 #define S_KEEP_ALIVE 22 376 #define V_KEEP_ALIVE(x) ((x) << S_KEEP_ALIVE) 377 #define F_KEEP_ALIVE V_KEEP_ALIVE(1U) 378 379 #define S_MAX_RETRANS 23 380 #define M_MAX_RETRANS 0xF 381 #define V_MAX_RETRANS(x) ((x) << S_MAX_RETRANS) 382 #define G_MAX_RETRANS(x) (((x) >> S_MAX_RETRANS) & M_MAX_RETRANS) 383 384 #define S_MAX_RETRANS_OVERRIDE 27 385 #define V_MAX_RETRANS_OVERRIDE(x) ((x) << S_MAX_RETRANS_OVERRIDE) 386 #define F_MAX_RETRANS_OVERRIDE V_MAX_RETRANS_OVERRIDE(1U) 387 388 #define S_MSS_IDX 28 389 #define M_MSS_IDX 0xF 390 #define V_MSS_IDX(x) ((x) << S_MSS_IDX) 391 #define G_MSS_IDX(x) (((x) >> S_MSS_IDX) & M_MSS_IDX) 392 393 /* option 1 fields */ 394 #define S_RSS_ENABLE 0 395 #define V_RSS_ENABLE(x) ((x) << S_RSS_ENABLE) 396 #define F_RSS_ENABLE V_RSS_ENABLE(1U) 397 398 #define S_RSS_MASK_LEN 1 399 #define M_RSS_MASK_LEN 0x7 400 #define V_RSS_MASK_LEN(x) ((x) << S_RSS_MASK_LEN) 401 #define G_RSS_MASK_LEN(x) (((x) >> S_RSS_MASK_LEN) & M_RSS_MASK_LEN) 402 403 #define S_CPU_IDX 4 404 #define M_CPU_IDX 0x3F 405 #define V_CPU_IDX(x) ((x) << S_CPU_IDX) 406 #define G_CPU_IDX(x) (((x) >> S_CPU_IDX) & M_CPU_IDX) 407 408 #define S_MAC_MATCH_VALID 18 409 #define V_MAC_MATCH_VALID(x) ((x) << S_MAC_MATCH_VALID) 410 #define F_MAC_MATCH_VALID V_MAC_MATCH_VALID(1U) 411 412 #define S_CONN_POLICY 19 413 #define M_CONN_POLICY 0x3 414 #define V_CONN_POLICY(x) ((x) << S_CONN_POLICY) 415 #define G_CONN_POLICY(x) (((x) >> S_CONN_POLICY) & M_CONN_POLICY) 416 417 #define S_SYN_DEFENSE 21 418 #define V_SYN_DEFENSE(x) ((x) << S_SYN_DEFENSE) 419 #define F_SYN_DEFENSE V_SYN_DEFENSE(1U) 420 421 #define S_VLAN_PRI 22 422 #define M_VLAN_PRI 0x3 423 #define V_VLAN_PRI(x) ((x) << S_VLAN_PRI) 424 #define G_VLAN_PRI(x) (((x) >> S_VLAN_PRI) & M_VLAN_PRI) 425 426 #define S_VLAN_PRI_VALID 24 427 #define V_VLAN_PRI_VALID(x) ((x) << S_VLAN_PRI_VALID) 428 #define F_VLAN_PRI_VALID V_VLAN_PRI_VALID(1U) 429 430 #define S_PKT_TYPE 25 431 #define M_PKT_TYPE 0x3 432 #define V_PKT_TYPE(x) ((x) << S_PKT_TYPE) 433 #define G_PKT_TYPE(x) (((x) >> S_PKT_TYPE) & M_PKT_TYPE) 434 435 #define S_MAC_MATCH 27 436 #define M_MAC_MATCH 0x1F 437 #define V_MAC_MATCH(x) ((x) << S_MAC_MATCH) 438 #define G_MAC_MATCH(x) (((x) >> S_MAC_MATCH) & M_MAC_MATCH) 439 440 /* option 2 fields */ 441 #define S_CPU_INDEX 0 442 #define M_CPU_INDEX 0x7F 443 #define V_CPU_INDEX(x) ((x) << S_CPU_INDEX) 444 #define G_CPU_INDEX(x) (((x) >> S_CPU_INDEX) & M_CPU_INDEX) 445 446 #define S_CPU_INDEX_VALID 7 447 #define V_CPU_INDEX_VALID(x) ((x) << S_CPU_INDEX_VALID) 448 #define F_CPU_INDEX_VALID V_CPU_INDEX_VALID(1U) 449 450 #define S_RX_COALESCE 8 451 #define M_RX_COALESCE 0x3 452 #define V_RX_COALESCE(x) ((x) << S_RX_COALESCE) 453 #define G_RX_COALESCE(x) (((x) >> S_RX_COALESCE) & M_RX_COALESCE) 454 455 #define S_RX_COALESCE_VALID 10 456 #define V_RX_COALESCE_VALID(x) ((x) << S_RX_COALESCE_VALID) 457 #define F_RX_COALESCE_VALID V_RX_COALESCE_VALID(1U) 458 459 #define S_CONG_CONTROL_FLAVOR 11 460 #define M_CONG_CONTROL_FLAVOR 0x3 461 #define V_CONG_CONTROL_FLAVOR(x) ((x) << S_CONG_CONTROL_FLAVOR) 462 #define G_CONG_CONTROL_FLAVOR(x) (((x) >> S_CONG_CONTROL_FLAVOR) & M_CONG_CONTROL_FLAVOR) 463 464 #define S_PACING_FLAVOR 13 465 #define M_PACING_FLAVOR 0x3 466 #define V_PACING_FLAVOR(x) ((x) << S_PACING_FLAVOR) 467 #define G_PACING_FLAVOR(x) (((x) >> S_PACING_FLAVOR) & M_PACING_FLAVOR) 468 469 #define S_FLAVORS_VALID 15 470 #define V_FLAVORS_VALID(x) ((x) << S_FLAVORS_VALID) 471 #define F_FLAVORS_VALID V_FLAVORS_VALID(1U) 472 473 #define S_RX_FC_DISABLE 16 474 #define V_RX_FC_DISABLE(x) ((x) << S_RX_FC_DISABLE) 475 #define F_RX_FC_DISABLE V_RX_FC_DISABLE(1U) 476 477 #define S_RX_FC_VALID 17 478 #define V_RX_FC_VALID(x) ((x) << S_RX_FC_VALID) 479 #define F_RX_FC_VALID V_RX_FC_VALID(1U) 480 481 struct cpl_pass_open_req { 482 WR_HDR; 483 union opcode_tid ot; 484 __be16 local_port; 485 __be16 peer_port; 486 __be32 local_ip; 487 __be32 peer_ip; 488 __be32 opt0h; 489 __be32 opt0l; 490 __be32 peer_netmask; 491 __be32 opt1; 492 }; 493 494 struct cpl_pass_open_rpl { 495 RSS_HDR 496 union opcode_tid ot; 497 __be16 local_port; 498 __be16 peer_port; 499 __be32 local_ip; 500 __be32 peer_ip; 501 __u8 resvd[7]; 502 __u8 status; 503 }; 504 505 struct cpl_pass_establish { 506 RSS_HDR 507 union opcode_tid ot; 508 __be16 local_port; 509 __be16 peer_port; 510 __be32 local_ip; 511 __be32 peer_ip; 512 __be32 tos_tid; 513 __be16 l2t_idx; 514 __be16 tcp_opt; 515 __be32 snd_isn; 516 __be32 rcv_isn; 517 }; 518 519 /* cpl_pass_establish.tos_tid fields */ 520 #define S_PASS_OPEN_TID 0 521 #define M_PASS_OPEN_TID 0xFFFFFF 522 #define V_PASS_OPEN_TID(x) ((x) << S_PASS_OPEN_TID) 523 #define G_PASS_OPEN_TID(x) (((x) >> S_PASS_OPEN_TID) & M_PASS_OPEN_TID) 524 525 #define S_PASS_OPEN_TOS 24 526 #define M_PASS_OPEN_TOS 0xFF 527 #define V_PASS_OPEN_TOS(x) ((x) << S_PASS_OPEN_TOS) 528 #define G_PASS_OPEN_TOS(x) (((x) >> S_PASS_OPEN_TOS) & M_PASS_OPEN_TOS) 529 530 /* cpl_pass_establish.l2t_idx fields */ 531 #define S_L2T_IDX16 5 532 #define M_L2T_IDX16 0x7FF 533 #define V_L2T_IDX16(x) ((x) << S_L2T_IDX16) 534 #define G_L2T_IDX16(x) (((x) >> S_L2T_IDX16) & M_L2T_IDX16) 535 536 /* cpl_pass_establish.tcp_opt fields (also applies act_open_establish) */ 537 #define G_TCPOPT_WSCALE_OK(x) (((x) >> 5) & 1) 538 #define G_TCPOPT_SACK(x) (((x) >> 6) & 1) 539 #define G_TCPOPT_TSTAMP(x) (((x) >> 7) & 1) 540 #define G_TCPOPT_SND_WSCALE(x) (((x) >> 8) & 0xf) 541 #define G_TCPOPT_MSS(x) (((x) >> 12) & 0xf) 542 543 struct cpl_pass_accept_req { 544 RSS_HDR 545 union opcode_tid ot; 546 __be16 local_port; 547 __be16 peer_port; 548 __be32 local_ip; 549 __be32 peer_ip; 550 __be32 tos_tid; 551 struct tcp_options tcp_options; 552 __u8 dst_mac[6]; 553 __be16 vlan_tag; 554 __u8 src_mac[6]; 555 #if defined(__LITTLE_ENDIAN_BITFIELD) 556 __u8 :3; 557 __u8 addr_idx:3; 558 __u8 port_idx:1; 559 __u8 exact_match:1; 560 #else 561 __u8 exact_match:1; 562 __u8 port_idx:1; 563 __u8 addr_idx:3; 564 __u8 :3; 565 #endif 566 __u8 rsvd; 567 __be32 rcv_isn; 568 __be32 rsvd2; 569 }; 570 571 struct cpl_pass_accept_rpl { 572 WR_HDR; 573 union opcode_tid ot; 574 __be32 opt2; 575 __be32 rsvd; 576 __be32 peer_ip; 577 __be32 opt0h; 578 __be32 opt0l_status; 579 }; 580 581 struct cpl_act_open_req { 582 WR_HDR; 583 union opcode_tid ot; 584 __be16 local_port; 585 __be16 peer_port; 586 __be32 local_ip; 587 __be32 peer_ip; 588 __be32 opt0h; 589 __be32 opt0l; 590 __be32 params; 591 __be32 opt2; 592 }; 593 594 /* cpl_act_open_req.params fields */ 595 #define S_AOPEN_VLAN_PRI 9 596 #define M_AOPEN_VLAN_PRI 0x3 597 #define V_AOPEN_VLAN_PRI(x) ((x) << S_AOPEN_VLAN_PRI) 598 #define G_AOPEN_VLAN_PRI(x) (((x) >> S_AOPEN_VLAN_PRI) & M_AOPEN_VLAN_PRI) 599 600 #define S_AOPEN_VLAN_PRI_VALID 11 601 #define V_AOPEN_VLAN_PRI_VALID(x) ((x) << S_AOPEN_VLAN_PRI_VALID) 602 #define F_AOPEN_VLAN_PRI_VALID V_AOPEN_VLAN_PRI_VALID(1U) 603 604 #define S_AOPEN_PKT_TYPE 12 605 #define M_AOPEN_PKT_TYPE 0x3 606 #define V_AOPEN_PKT_TYPE(x) ((x) << S_AOPEN_PKT_TYPE) 607 #define G_AOPEN_PKT_TYPE(x) (((x) >> S_AOPEN_PKT_TYPE) & M_AOPEN_PKT_TYPE) 608 609 #define S_AOPEN_MAC_MATCH 14 610 #define M_AOPEN_MAC_MATCH 0x1F 611 #define V_AOPEN_MAC_MATCH(x) ((x) << S_AOPEN_MAC_MATCH) 612 #define G_AOPEN_MAC_MATCH(x) (((x) >> S_AOPEN_MAC_MATCH) & M_AOPEN_MAC_MATCH) 613 614 #define S_AOPEN_MAC_MATCH_VALID 19 615 #define V_AOPEN_MAC_MATCH_VALID(x) ((x) << S_AOPEN_MAC_MATCH_VALID) 616 #define F_AOPEN_MAC_MATCH_VALID V_AOPEN_MAC_MATCH_VALID(1U) 617 618 #define S_AOPEN_IFF_VLAN 20 619 #define M_AOPEN_IFF_VLAN 0xFFF 620 #define V_AOPEN_IFF_VLAN(x) ((x) << S_AOPEN_IFF_VLAN) 621 #define G_AOPEN_IFF_VLAN(x) (((x) >> S_AOPEN_IFF_VLAN) & M_AOPEN_IFF_VLAN) 622 623 struct cpl_act_open_rpl { 624 RSS_HDR 625 union opcode_tid ot; 626 __be16 local_port; 627 __be16 peer_port; 628 __be32 local_ip; 629 __be32 peer_ip; 630 __be32 atid; 631 __u8 rsvd[3]; 632 __u8 status; 633 }; 634 635 struct cpl_act_establish { 636 RSS_HDR 637 union opcode_tid ot; 638 __be16 local_port; 639 __be16 peer_port; 640 __be32 local_ip; 641 __be32 peer_ip; 642 __be32 tos_tid; 643 __be16 l2t_idx; 644 __be16 tcp_opt; 645 __be32 snd_isn; 646 __be32 rcv_isn; 647 }; 648 649 struct cpl_get_tcb { 650 WR_HDR; 651 union opcode_tid ot; 652 __be16 cpuno; 653 __be16 rsvd; 654 }; 655 656 struct cpl_get_tcb_rpl { 657 RSS_HDR 658 union opcode_tid ot; 659 __u8 rsvd; 660 __u8 status; 661 __be16 len; 662 }; 663 664 struct cpl_set_tcb { 665 WR_HDR; 666 union opcode_tid ot; 667 __u8 reply; 668 __u8 cpu_idx; 669 __be16 len; 670 }; 671 672 /* cpl_set_tcb.reply fields */ 673 #define S_NO_REPLY 7 674 #define V_NO_REPLY(x) ((x) << S_NO_REPLY) 675 #define F_NO_REPLY V_NO_REPLY(1U) 676 677 struct cpl_set_tcb_field { 678 WR_HDR; 679 union opcode_tid ot; 680 __u8 reply; 681 __u8 cpu_idx; 682 __be16 word; 683 __be64 mask; 684 __be64 val; 685 }; 686 687 struct cpl_set_tcb_rpl { 688 RSS_HDR 689 union opcode_tid ot; 690 __u8 rsvd[3]; 691 __u8 status; 692 }; 693 694 struct cpl_pcmd { 695 WR_HDR; 696 union opcode_tid ot; 697 __u8 rsvd[3]; 698 #if defined(__LITTLE_ENDIAN_BITFIELD) 699 __u8 src:1; 700 __u8 bundle:1; 701 __u8 channel:1; 702 __u8 :5; 703 #else 704 __u8 :5; 705 __u8 channel:1; 706 __u8 bundle:1; 707 __u8 src:1; 708 #endif 709 __be32 pcmd_parm[2]; 710 }; 711 712 struct cpl_pcmd_reply { 713 RSS_HDR 714 union opcode_tid ot; 715 __u8 status; 716 __u8 rsvd; 717 __be16 len; 718 }; 719 720 struct cpl_close_con_req { 721 WR_HDR; 722 union opcode_tid ot; 723 __be32 rsvd; 724 }; 725 726 struct cpl_close_con_rpl { 727 RSS_HDR 728 union opcode_tid ot; 729 __u8 rsvd[3]; 730 __u8 status; 731 __be32 snd_nxt; 732 __be32 rcv_nxt; 733 }; 734 735 struct cpl_close_listserv_req { 736 WR_HDR; 737 union opcode_tid ot; 738 __u8 rsvd0; 739 __u8 cpu_idx; 740 __be16 rsvd1; 741 }; 742 743 struct cpl_close_listserv_rpl { 744 RSS_HDR 745 union opcode_tid ot; 746 __u8 rsvd[3]; 747 __u8 status; 748 }; 749 750 struct cpl_abort_req_rss { 751 RSS_HDR 752 union opcode_tid ot; 753 __be32 rsvd0; 754 __u8 rsvd1; 755 __u8 status; 756 __u8 rsvd2[6]; 757 }; 758 759 struct cpl_abort_req { 760 WR_HDR; 761 union opcode_tid ot; 762 __be32 rsvd0; 763 __u8 rsvd1; 764 __u8 cmd; 765 __u8 rsvd2[6]; 766 }; 767 768 struct cpl_abort_rpl_rss { 769 RSS_HDR 770 union opcode_tid ot; 771 __be32 rsvd0; 772 __u8 rsvd1; 773 __u8 status; 774 __u8 rsvd2[6]; 775 }; 776 777 struct cpl_abort_rpl { 778 WR_HDR; 779 union opcode_tid ot; 780 __be32 rsvd0; 781 __u8 rsvd1; 782 __u8 cmd; 783 __u8 rsvd2[6]; 784 }; 785 786 struct cpl_peer_close { 787 RSS_HDR 788 union opcode_tid ot; 789 __be32 rcv_nxt; 790 }; 791 792 struct tx_data_wr { 793 __be32 wr_hi; 794 __be32 wr_lo; 795 __be32 len; 796 __be32 flags; 797 __be32 sndseq; 798 __be32 param; 799 }; 800 801 /* tx_data_wr.param fields */ 802 #define S_TX_PORT 0 803 #define M_TX_PORT 0x7 804 #define V_TX_PORT(x) ((x) << S_TX_PORT) 805 #define G_TX_PORT(x) (((x) >> S_TX_PORT) & M_TX_PORT) 806 807 #define S_TX_MSS 4 808 #define M_TX_MSS 0xF 809 #define V_TX_MSS(x) ((x) << S_TX_MSS) 810 #define G_TX_MSS(x) (((x) >> S_TX_MSS) & M_TX_MSS) 811 812 #define S_TX_QOS 8 813 #define M_TX_QOS 0xFF 814 #define V_TX_QOS(x) ((x) << S_TX_QOS) 815 #define G_TX_QOS(x) (((x) >> S_TX_QOS) & M_TX_QOS) 816 817 #define S_TX_SNDBUF 16 818 #define M_TX_SNDBUF 0xFFFF 819 #define V_TX_SNDBUF(x) ((x) << S_TX_SNDBUF) 820 #define G_TX_SNDBUF(x) (((x) >> S_TX_SNDBUF) & M_TX_SNDBUF) 821 822 struct cpl_tx_data { 823 union opcode_tid ot; 824 __be32 len; 825 __be32 rsvd; 826 __be16 urg; 827 __be16 flags; 828 }; 829 830 /* cpl_tx_data.flags fields */ 831 #define S_TX_ULP_SUBMODE 6 832 #define M_TX_ULP_SUBMODE 0xF 833 #define V_TX_ULP_SUBMODE(x) ((x) << S_TX_ULP_SUBMODE) 834 #define G_TX_ULP_SUBMODE(x) (((x) >> S_TX_ULP_SUBMODE) & M_TX_ULP_SUBMODE) 835 836 #define S_TX_ULP_MODE 10 837 #define M_TX_ULP_MODE 0xF 838 #define V_TX_ULP_MODE(x) ((x) << S_TX_ULP_MODE) 839 #define G_TX_ULP_MODE(x) (((x) >> S_TX_ULP_MODE) & M_TX_ULP_MODE) 840 841 #define S_TX_SHOVE 14 842 #define V_TX_SHOVE(x) ((x) << S_TX_SHOVE) 843 #define F_TX_SHOVE V_TX_SHOVE(1U) 844 845 #define S_TX_MORE 15 846 #define V_TX_MORE(x) ((x) << S_TX_MORE) 847 #define F_TX_MORE V_TX_MORE(1U) 848 849 /* additional tx_data_wr.flags fields */ 850 #define S_TX_CPU_IDX 0 851 #define M_TX_CPU_IDX 0x3F 852 #define V_TX_CPU_IDX(x) ((x) << S_TX_CPU_IDX) 853 #define G_TX_CPU_IDX(x) (((x) >> S_TX_CPU_IDX) & M_TX_CPU_IDX) 854 855 #define S_TX_URG 16 856 #define V_TX_URG(x) ((x) << S_TX_URG) 857 #define F_TX_URG V_TX_URG(1U) 858 859 #define S_TX_CLOSE 17 860 #define V_TX_CLOSE(x) ((x) << S_TX_CLOSE) 861 #define F_TX_CLOSE V_TX_CLOSE(1U) 862 863 #define S_TX_INIT 18 864 #define V_TX_INIT(x) ((x) << S_TX_INIT) 865 #define F_TX_INIT V_TX_INIT(1U) 866 867 #define S_TX_IMM_ACK 19 868 #define V_TX_IMM_ACK(x) ((x) << S_TX_IMM_ACK) 869 #define F_TX_IMM_ACK V_TX_IMM_ACK(1U) 870 871 #define S_TX_IMM_DMA 20 872 #define V_TX_IMM_DMA(x) ((x) << S_TX_IMM_DMA) 873 #define F_TX_IMM_DMA V_TX_IMM_DMA(1U) 874 875 struct cpl_tx_data_ack { 876 RSS_HDR 877 union opcode_tid ot; 878 __be32 ack_seq; 879 }; 880 881 struct cpl_wr_ack { 882 RSS_HDR 883 union opcode_tid ot; 884 __be16 credits; 885 __be16 rsvd; 886 __be32 snd_nxt; 887 __be32 snd_una; 888 }; 889 890 struct cpl_rdma_ec_status { 891 RSS_HDR 892 union opcode_tid ot; 893 __u8 rsvd[3]; 894 __u8 status; 895 }; 896 897 struct mngt_pktsched_wr { 898 __be32 wr_hi; 899 __be32 wr_lo; 900 __u8 mngt_opcode; 901 __u8 rsvd[7]; 902 __u8 sched; 903 __u8 idx; 904 __u8 min; 905 __u8 max; 906 __u8 binding; 907 __u8 rsvd1[3]; 908 }; 909 910 struct cpl_iscsi_hdr { 911 RSS_HDR 912 union opcode_tid ot; 913 __be16 pdu_len_ddp; 914 __be16 len; 915 __be32 seq; 916 __be16 urg; 917 __u8 rsvd; 918 __u8 status; 919 }; 920 921 /* cpl_iscsi_hdr.pdu_len_ddp fields */ 922 #define S_ISCSI_PDU_LEN 0 923 #define M_ISCSI_PDU_LEN 0x7FFF 924 #define V_ISCSI_PDU_LEN(x) ((x) << S_ISCSI_PDU_LEN) 925 #define G_ISCSI_PDU_LEN(x) (((x) >> S_ISCSI_PDU_LEN) & M_ISCSI_PDU_LEN) 926 927 #define S_ISCSI_DDP 15 928 #define V_ISCSI_DDP(x) ((x) << S_ISCSI_DDP) 929 #define F_ISCSI_DDP V_ISCSI_DDP(1U) 930 931 struct cpl_rx_data { 932 RSS_HDR 933 union opcode_tid ot; 934 __be16 rsvd; 935 __be16 len; 936 __be32 seq; 937 __be16 urg; 938 #if defined(__LITTLE_ENDIAN_BITFIELD) 939 __u8 dack_mode:2; 940 __u8 psh:1; 941 __u8 heartbeat:1; 942 __u8 :4; 943 #else 944 __u8 :4; 945 __u8 heartbeat:1; 946 __u8 psh:1; 947 __u8 dack_mode:2; 948 #endif 949 __u8 status; 950 }; 951 952 struct cpl_rx_data_ack { 953 WR_HDR; 954 union opcode_tid ot; 955 __be32 credit_dack; 956 }; 957 958 /* cpl_rx_data_ack.ack_seq fields */ 959 #define S_RX_CREDITS 0 960 #define M_RX_CREDITS 0x7FFFFFF 961 #define V_RX_CREDITS(x) ((x) << S_RX_CREDITS) 962 #define G_RX_CREDITS(x) (((x) >> S_RX_CREDITS) & M_RX_CREDITS) 963 964 #define S_RX_MODULATE 27 965 #define V_RX_MODULATE(x) ((x) << S_RX_MODULATE) 966 #define F_RX_MODULATE V_RX_MODULATE(1U) 967 968 #define S_RX_FORCE_ACK 28 969 #define V_RX_FORCE_ACK(x) ((x) << S_RX_FORCE_ACK) 970 #define F_RX_FORCE_ACK V_RX_FORCE_ACK(1U) 971 972 #define S_RX_DACK_MODE 29 973 #define M_RX_DACK_MODE 0x3 974 #define V_RX_DACK_MODE(x) ((x) << S_RX_DACK_MODE) 975 #define G_RX_DACK_MODE(x) (((x) >> S_RX_DACK_MODE) & M_RX_DACK_MODE) 976 977 #define S_RX_DACK_CHANGE 31 978 #define V_RX_DACK_CHANGE(x) ((x) << S_RX_DACK_CHANGE) 979 #define F_RX_DACK_CHANGE V_RX_DACK_CHANGE(1U) 980 981 struct cpl_rx_urg_notify { 982 RSS_HDR 983 union opcode_tid ot; 984 __be32 seq; 985 }; 986 987 struct cpl_rx_ddp_complete { 988 RSS_HDR 989 union opcode_tid ot; 990 __be32 ddp_report; 991 }; 992 993 struct cpl_rx_data_ddp { 994 RSS_HDR 995 union opcode_tid ot; 996 __be16 urg; 997 __be16 len; 998 __be32 seq; 999 union { 1000 __be32 nxt_seq; 1001 __be32 ddp_report; 1002 } __U; 1003 __be32 ulp_crc; 1004 __be32 ddpvld_status; 1005 }; 1006 1007 /* cpl_rx_data_ddp.ddpvld_status fields */ 1008 #define S_DDP_STATUS 0 1009 #define M_DDP_STATUS 0xFF 1010 #define V_DDP_STATUS(x) ((x) << S_DDP_STATUS) 1011 #define G_DDP_STATUS(x) (((x) >> S_DDP_STATUS) & M_DDP_STATUS) 1012 1013 #define S_DDP_VALID 15 1014 #define M_DDP_VALID 0x1FFFF 1015 #define V_DDP_VALID(x) ((x) << S_DDP_VALID) 1016 #define G_DDP_VALID(x) (((x) >> S_DDP_VALID) & M_DDP_VALID) 1017 1018 #define S_DDP_PPOD_MISMATCH 15 1019 #define V_DDP_PPOD_MISMATCH(x) ((x) << S_DDP_PPOD_MISMATCH) 1020 #define F_DDP_PPOD_MISMATCH V_DDP_PPOD_MISMATCH(1U) 1021 1022 #define S_DDP_PDU 16 1023 #define V_DDP_PDU(x) ((x) << S_DDP_PDU) 1024 #define F_DDP_PDU V_DDP_PDU(1U) 1025 1026 #define S_DDP_LLIMIT_ERR 17 1027 #define V_DDP_LLIMIT_ERR(x) ((x) << S_DDP_LLIMIT_ERR) 1028 #define F_DDP_LLIMIT_ERR V_DDP_LLIMIT_ERR(1U) 1029 1030 #define S_DDP_PPOD_PARITY_ERR 18 1031 #define V_DDP_PPOD_PARITY_ERR(x) ((x) << S_DDP_PPOD_PARITY_ERR) 1032 #define F_DDP_PPOD_PARITY_ERR V_DDP_PPOD_PARITY_ERR(1U) 1033 1034 #define S_DDP_PADDING_ERR 19 1035 #define V_DDP_PADDING_ERR(x) ((x) << S_DDP_PADDING_ERR) 1036 #define F_DDP_PADDING_ERR V_DDP_PADDING_ERR(1U) 1037 1038 #define S_DDP_HDRCRC_ERR 20 1039 #define V_DDP_HDRCRC_ERR(x) ((x) << S_DDP_HDRCRC_ERR) 1040 #define F_DDP_HDRCRC_ERR V_DDP_HDRCRC_ERR(1U) 1041 1042 #define S_DDP_DATACRC_ERR 21 1043 #define V_DDP_DATACRC_ERR(x) ((x) << S_DDP_DATACRC_ERR) 1044 #define F_DDP_DATACRC_ERR V_DDP_DATACRC_ERR(1U) 1045 1046 #define S_DDP_INVALID_TAG 22 1047 #define V_DDP_INVALID_TAG(x) ((x) << S_DDP_INVALID_TAG) 1048 #define F_DDP_INVALID_TAG V_DDP_INVALID_TAG(1U) 1049 1050 #define S_DDP_ULIMIT_ERR 23 1051 #define V_DDP_ULIMIT_ERR(x) ((x) << S_DDP_ULIMIT_ERR) 1052 #define F_DDP_ULIMIT_ERR V_DDP_ULIMIT_ERR(1U) 1053 1054 #define S_DDP_OFFSET_ERR 24 1055 #define V_DDP_OFFSET_ERR(x) ((x) << S_DDP_OFFSET_ERR) 1056 #define F_DDP_OFFSET_ERR V_DDP_OFFSET_ERR(1U) 1057 1058 #define S_DDP_COLOR_ERR 25 1059 #define V_DDP_COLOR_ERR(x) ((x) << S_DDP_COLOR_ERR) 1060 #define F_DDP_COLOR_ERR V_DDP_COLOR_ERR(1U) 1061 1062 #define S_DDP_TID_MISMATCH 26 1063 #define V_DDP_TID_MISMATCH(x) ((x) << S_DDP_TID_MISMATCH) 1064 #define F_DDP_TID_MISMATCH V_DDP_TID_MISMATCH(1U) 1065 1066 #define S_DDP_INVALID_PPOD 27 1067 #define V_DDP_INVALID_PPOD(x) ((x) << S_DDP_INVALID_PPOD) 1068 #define F_DDP_INVALID_PPOD V_DDP_INVALID_PPOD(1U) 1069 1070 #define S_DDP_ULP_MODE 28 1071 #define M_DDP_ULP_MODE 0xF 1072 #define V_DDP_ULP_MODE(x) ((x) << S_DDP_ULP_MODE) 1073 #define G_DDP_ULP_MODE(x) (((x) >> S_DDP_ULP_MODE) & M_DDP_ULP_MODE) 1074 1075 /* cpl_rx_data_ddp.ddp_report fields */ 1076 #define S_DDP_OFFSET 0 1077 #define M_DDP_OFFSET 0x3FFFFF 1078 #define V_DDP_OFFSET(x) ((x) << S_DDP_OFFSET) 1079 #define G_DDP_OFFSET(x) (((x) >> S_DDP_OFFSET) & M_DDP_OFFSET) 1080 1081 #define S_DDP_URG 24 1082 #define V_DDP_URG(x) ((x) << S_DDP_URG) 1083 #define F_DDP_URG V_DDP_URG(1U) 1084 1085 #define S_DDP_PSH 25 1086 #define V_DDP_PSH(x) ((x) << S_DDP_PSH) 1087 #define F_DDP_PSH V_DDP_PSH(1U) 1088 1089 #define S_DDP_BUF_COMPLETE 26 1090 #define V_DDP_BUF_COMPLETE(x) ((x) << S_DDP_BUF_COMPLETE) 1091 #define F_DDP_BUF_COMPLETE V_DDP_BUF_COMPLETE(1U) 1092 1093 #define S_DDP_BUF_TIMED_OUT 27 1094 #define V_DDP_BUF_TIMED_OUT(x) ((x) << S_DDP_BUF_TIMED_OUT) 1095 #define F_DDP_BUF_TIMED_OUT V_DDP_BUF_TIMED_OUT(1U) 1096 1097 #define S_DDP_BUF_IDX 28 1098 #define V_DDP_BUF_IDX(x) ((x) << S_DDP_BUF_IDX) 1099 #define F_DDP_BUF_IDX V_DDP_BUF_IDX(1U) 1100 1101 struct cpl_tx_pkt { 1102 WR_HDR; 1103 __be32 cntrl; 1104 __be32 len; 1105 }; 1106 1107 struct cpl_tx_pkt_lso { 1108 WR_HDR; 1109 __be32 cntrl; 1110 __be32 len; 1111 1112 __be32 rsvd; 1113 __be32 lso_info; 1114 }; 1115 1116 /* cpl_tx_pkt*.cntrl fields */ 1117 #define S_TXPKT_VLAN 0 1118 #define M_TXPKT_VLAN 0xFFFF 1119 #define V_TXPKT_VLAN(x) ((x) << S_TXPKT_VLAN) 1120 #define G_TXPKT_VLAN(x) (((x) >> S_TXPKT_VLAN) & M_TXPKT_VLAN) 1121 1122 #define S_TXPKT_INTF 16 1123 #define M_TXPKT_INTF 0xF 1124 #define V_TXPKT_INTF(x) ((x) << S_TXPKT_INTF) 1125 #define G_TXPKT_INTF(x) (((x) >> S_TXPKT_INTF) & M_TXPKT_INTF) 1126 1127 #define S_TXPKT_IPCSUM_DIS 20 1128 #define V_TXPKT_IPCSUM_DIS(x) ((x) << S_TXPKT_IPCSUM_DIS) 1129 #define F_TXPKT_IPCSUM_DIS V_TXPKT_IPCSUM_DIS(1U) 1130 1131 #define S_TXPKT_L4CSUM_DIS 21 1132 #define V_TXPKT_L4CSUM_DIS(x) ((x) << S_TXPKT_L4CSUM_DIS) 1133 #define F_TXPKT_L4CSUM_DIS V_TXPKT_L4CSUM_DIS(1U) 1134 1135 #define S_TXPKT_VLAN_VLD 22 1136 #define V_TXPKT_VLAN_VLD(x) ((x) << S_TXPKT_VLAN_VLD) 1137 #define F_TXPKT_VLAN_VLD V_TXPKT_VLAN_VLD(1U) 1138 1139 #define S_TXPKT_LOOPBACK 23 1140 #define V_TXPKT_LOOPBACK(x) ((x) << S_TXPKT_LOOPBACK) 1141 #define F_TXPKT_LOOPBACK V_TXPKT_LOOPBACK(1U) 1142 1143 #define S_TXPKT_OPCODE 24 1144 #define M_TXPKT_OPCODE 0xFF 1145 #define V_TXPKT_OPCODE(x) ((x) << S_TXPKT_OPCODE) 1146 #define G_TXPKT_OPCODE(x) (((x) >> S_TXPKT_OPCODE) & M_TXPKT_OPCODE) 1147 1148 /* cpl_tx_pkt_lso.lso_info fields */ 1149 #define S_LSO_MSS 0 1150 #define M_LSO_MSS 0x3FFF 1151 #define V_LSO_MSS(x) ((x) << S_LSO_MSS) 1152 #define G_LSO_MSS(x) (((x) >> S_LSO_MSS) & M_LSO_MSS) 1153 1154 #define S_LSO_ETH_TYPE 14 1155 #define M_LSO_ETH_TYPE 0x3 1156 #define V_LSO_ETH_TYPE(x) ((x) << S_LSO_ETH_TYPE) 1157 #define G_LSO_ETH_TYPE(x) (((x) >> S_LSO_ETH_TYPE) & M_LSO_ETH_TYPE) 1158 1159 #define S_LSO_TCPHDR_WORDS 16 1160 #define M_LSO_TCPHDR_WORDS 0xF 1161 #define V_LSO_TCPHDR_WORDS(x) ((x) << S_LSO_TCPHDR_WORDS) 1162 #define G_LSO_TCPHDR_WORDS(x) (((x) >> S_LSO_TCPHDR_WORDS) & M_LSO_TCPHDR_WORDS) 1163 1164 #define S_LSO_IPHDR_WORDS 20 1165 #define M_LSO_IPHDR_WORDS 0xF 1166 #define V_LSO_IPHDR_WORDS(x) ((x) << S_LSO_IPHDR_WORDS) 1167 #define G_LSO_IPHDR_WORDS(x) (((x) >> S_LSO_IPHDR_WORDS) & M_LSO_IPHDR_WORDS) 1168 1169 #define S_LSO_IPV6 24 1170 #define V_LSO_IPV6(x) ((x) << S_LSO_IPV6) 1171 #define F_LSO_IPV6 V_LSO_IPV6(1U) 1172 1173 struct cpl_trace_pkt { 1174 #ifdef CHELSIO_FW 1175 __u8 rss_opcode; 1176 #if defined(__LITTLE_ENDIAN_BITFIELD) 1177 __u8 err:1; 1178 __u8 :7; 1179 #else 1180 __u8 :7; 1181 __u8 err:1; 1182 #endif 1183 __u8 rsvd0; 1184 #if defined(__LITTLE_ENDIAN_BITFIELD) 1185 __u8 qid:4; 1186 __u8 :4; 1187 #else 1188 __u8 :4; 1189 __u8 qid:4; 1190 #endif 1191 __be32 tstamp; 1192 #endif /* CHELSIO_FW */ 1193 1194 __u8 opcode; 1195 #if defined(__LITTLE_ENDIAN_BITFIELD) 1196 __u8 iff:4; 1197 __u8 :4; 1198 #else 1199 __u8 :4; 1200 __u8 iff:4; 1201 #endif 1202 __u8 rsvd[4]; 1203 __be16 len; 1204 }; 1205 1206 struct cpl_rx_pkt { 1207 RSS_HDR 1208 __u8 opcode; 1209 #if defined(__LITTLE_ENDIAN_BITFIELD) 1210 __u8 iff:4; 1211 __u8 csum_valid:1; 1212 __u8 ipmi_pkt:1; 1213 __u8 vlan_valid:1; 1214 __u8 fragment:1; 1215 #else 1216 __u8 fragment:1; 1217 __u8 vlan_valid:1; 1218 __u8 ipmi_pkt:1; 1219 __u8 csum_valid:1; 1220 __u8 iff:4; 1221 #endif 1222 __be16 csum; 1223 __be16 vlan; 1224 __be16 len; 1225 }; 1226 1227 struct cpl_l2t_write_req { 1228 WR_HDR; 1229 union opcode_tid ot; 1230 __be32 params; 1231 __u8 rsvd[2]; 1232 __u8 dst_mac[6]; 1233 }; 1234 1235 /* cpl_l2t_write_req.params fields */ 1236 #define S_L2T_W_IDX 0 1237 #define M_L2T_W_IDX 0x7FF 1238 #define V_L2T_W_IDX(x) ((x) << S_L2T_W_IDX) 1239 #define G_L2T_W_IDX(x) (((x) >> S_L2T_W_IDX) & M_L2T_W_IDX) 1240 1241 #define S_L2T_W_VLAN 11 1242 #define M_L2T_W_VLAN 0xFFF 1243 #define V_L2T_W_VLAN(x) ((x) << S_L2T_W_VLAN) 1244 #define G_L2T_W_VLAN(x) (((x) >> S_L2T_W_VLAN) & M_L2T_W_VLAN) 1245 1246 #define S_L2T_W_IFF 23 1247 #define M_L2T_W_IFF 0xF 1248 #define V_L2T_W_IFF(x) ((x) << S_L2T_W_IFF) 1249 #define G_L2T_W_IFF(x) (((x) >> S_L2T_W_IFF) & M_L2T_W_IFF) 1250 1251 #define S_L2T_W_PRIO 27 1252 #define M_L2T_W_PRIO 0x7 1253 #define V_L2T_W_PRIO(x) ((x) << S_L2T_W_PRIO) 1254 #define G_L2T_W_PRIO(x) (((x) >> S_L2T_W_PRIO) & M_L2T_W_PRIO) 1255 1256 struct cpl_l2t_write_rpl { 1257 RSS_HDR 1258 union opcode_tid ot; 1259 __u8 status; 1260 __u8 rsvd[3]; 1261 }; 1262 1263 struct cpl_l2t_read_req { 1264 WR_HDR; 1265 union opcode_tid ot; 1266 __be16 rsvd; 1267 __be16 l2t_idx; 1268 }; 1269 1270 struct cpl_l2t_read_rpl { 1271 RSS_HDR 1272 union opcode_tid ot; 1273 __be32 params; 1274 __u8 rsvd[2]; 1275 __u8 dst_mac[6]; 1276 }; 1277 1278 /* cpl_l2t_read_rpl.params fields */ 1279 #define S_L2T_R_PRIO 0 1280 #define M_L2T_R_PRIO 0x7 1281 #define V_L2T_R_PRIO(x) ((x) << S_L2T_R_PRIO) 1282 #define G_L2T_R_PRIO(x) (((x) >> S_L2T_R_PRIO) & M_L2T_R_PRIO) 1283 1284 #define S_L2T_R_VLAN 8 1285 #define M_L2T_R_VLAN 0xFFF 1286 #define V_L2T_R_VLAN(x) ((x) << S_L2T_R_VLAN) 1287 #define G_L2T_R_VLAN(x) (((x) >> S_L2T_R_VLAN) & M_L2T_R_VLAN) 1288 1289 #define S_L2T_R_IFF 20 1290 #define M_L2T_R_IFF 0xF 1291 #define V_L2T_R_IFF(x) ((x) << S_L2T_R_IFF) 1292 #define G_L2T_R_IFF(x) (((x) >> S_L2T_R_IFF) & M_L2T_R_IFF) 1293 1294 #define S_L2T_STATUS 24 1295 #define M_L2T_STATUS 0xFF 1296 #define V_L2T_STATUS(x) ((x) << S_L2T_STATUS) 1297 #define G_L2T_STATUS(x) (((x) >> S_L2T_STATUS) & M_L2T_STATUS) 1298 1299 struct cpl_smt_write_req { 1300 WR_HDR; 1301 union opcode_tid ot; 1302 __u8 rsvd0; 1303 #if defined(__LITTLE_ENDIAN_BITFIELD) 1304 __u8 mtu_idx:4; 1305 __u8 iff:4; 1306 #else 1307 __u8 iff:4; 1308 __u8 mtu_idx:4; 1309 #endif 1310 __be16 rsvd2; 1311 __be16 rsvd3; 1312 __u8 src_mac1[6]; 1313 __be16 rsvd4; 1314 __u8 src_mac0[6]; 1315 }; 1316 1317 struct cpl_smt_write_rpl { 1318 RSS_HDR 1319 union opcode_tid ot; 1320 __u8 status; 1321 __u8 rsvd[3]; 1322 }; 1323 1324 struct cpl_smt_read_req { 1325 WR_HDR; 1326 union opcode_tid ot; 1327 __u8 rsvd0; 1328 #if defined(__LITTLE_ENDIAN_BITFIELD) 1329 __u8 :4; 1330 __u8 iff:4; 1331 #else 1332 __u8 iff:4; 1333 __u8 :4; 1334 #endif 1335 __be16 rsvd2; 1336 }; 1337 1338 struct cpl_smt_read_rpl { 1339 RSS_HDR 1340 union opcode_tid ot; 1341 __u8 status; 1342 #if defined(__LITTLE_ENDIAN_BITFIELD) 1343 __u8 mtu_idx:4; 1344 __u8 :4; 1345 #else 1346 __u8 :4; 1347 __u8 mtu_idx:4; 1348 #endif 1349 __be16 rsvd2; 1350 __be16 rsvd3; 1351 __u8 src_mac1[6]; 1352 __be16 rsvd4; 1353 __u8 src_mac0[6]; 1354 }; 1355 1356 struct cpl_rte_delete_req { 1357 WR_HDR; 1358 union opcode_tid ot; 1359 __be32 params; 1360 }; 1361 1362 /* { cpl_rte_delete_req, cpl_rte_read_req }.params fields */ 1363 #define S_RTE_REQ_LUT_IX 8 1364 #define M_RTE_REQ_LUT_IX 0x7FF 1365 #define V_RTE_REQ_LUT_IX(x) ((x) << S_RTE_REQ_LUT_IX) 1366 #define G_RTE_REQ_LUT_IX(x) (((x) >> S_RTE_REQ_LUT_IX) & M_RTE_REQ_LUT_IX) 1367 1368 #define S_RTE_REQ_LUT_BASE 19 1369 #define M_RTE_REQ_LUT_BASE 0x7FF 1370 #define V_RTE_REQ_LUT_BASE(x) ((x) << S_RTE_REQ_LUT_BASE) 1371 #define G_RTE_REQ_LUT_BASE(x) (((x) >> S_RTE_REQ_LUT_BASE) & M_RTE_REQ_LUT_BASE) 1372 1373 #define S_RTE_READ_REQ_SELECT 31 1374 #define V_RTE_READ_REQ_SELECT(x) ((x) << S_RTE_READ_REQ_SELECT) 1375 #define F_RTE_READ_REQ_SELECT V_RTE_READ_REQ_SELECT(1U) 1376 1377 struct cpl_rte_delete_rpl { 1378 RSS_HDR 1379 union opcode_tid ot; 1380 __u8 status; 1381 __u8 rsvd[3]; 1382 }; 1383 1384 struct cpl_rte_write_req { 1385 WR_HDR; 1386 union opcode_tid ot; 1387 #if defined(__LITTLE_ENDIAN_BITFIELD) 1388 __u8 :6; 1389 __u8 write_tcam:1; 1390 __u8 write_l2t_lut:1; 1391 #else 1392 __u8 write_l2t_lut:1; 1393 __u8 write_tcam:1; 1394 __u8 :6; 1395 #endif 1396 __u8 rsvd[3]; 1397 __be32 lut_params; 1398 __be16 rsvd2; 1399 __be16 l2t_idx; 1400 __be32 netmask; 1401 __be32 faddr; 1402 }; 1403 1404 /* cpl_rte_write_req.lut_params fields */ 1405 #define S_RTE_WRITE_REQ_LUT_IX 10 1406 #define M_RTE_WRITE_REQ_LUT_IX 0x7FF 1407 #define V_RTE_WRITE_REQ_LUT_IX(x) ((x) << S_RTE_WRITE_REQ_LUT_IX) 1408 #define G_RTE_WRITE_REQ_LUT_IX(x) (((x) >> S_RTE_WRITE_REQ_LUT_IX) & M_RTE_WRITE_REQ_LUT_IX) 1409 1410 #define S_RTE_WRITE_REQ_LUT_BASE 21 1411 #define M_RTE_WRITE_REQ_LUT_BASE 0x7FF 1412 #define V_RTE_WRITE_REQ_LUT_BASE(x) ((x) << S_RTE_WRITE_REQ_LUT_BASE) 1413 #define G_RTE_WRITE_REQ_LUT_BASE(x) (((x) >> S_RTE_WRITE_REQ_LUT_BASE) & M_RTE_WRITE_REQ_LUT_BASE) 1414 1415 struct cpl_rte_write_rpl { 1416 RSS_HDR 1417 union opcode_tid ot; 1418 __u8 status; 1419 __u8 rsvd[3]; 1420 }; 1421 1422 struct cpl_rte_read_req { 1423 WR_HDR; 1424 union opcode_tid ot; 1425 __be32 params; 1426 }; 1427 1428 struct cpl_rte_read_rpl { 1429 RSS_HDR 1430 union opcode_tid ot; 1431 __u8 status; 1432 __u8 rsvd0; 1433 __be16 l2t_idx; 1434 #if defined(__LITTLE_ENDIAN_BITFIELD) 1435 __u8 :7; 1436 __u8 select:1; 1437 #else 1438 __u8 select:1; 1439 __u8 :7; 1440 #endif 1441 __u8 rsvd2[3]; 1442 __be32 addr; 1443 }; 1444 1445 struct cpl_tid_release { 1446 WR_HDR; 1447 union opcode_tid ot; 1448 __be32 rsvd; 1449 }; 1450 1451 struct cpl_barrier { 1452 WR_HDR; 1453 __u8 opcode; 1454 __u8 rsvd[7]; 1455 }; 1456 1457 struct cpl_rdma_read_req { 1458 __u8 opcode; 1459 __u8 rsvd[15]; 1460 }; 1461 1462 struct cpl_rdma_terminate { 1463 #ifdef CHELSIO_FW 1464 __u8 opcode; 1465 __u8 rsvd[2]; 1466 #if defined(__LITTLE_ENDIAN_BITFIELD) 1467 __u8 rspq:3; 1468 __u8 :5; 1469 #else 1470 __u8 :5; 1471 __u8 rspq:3; 1472 #endif 1473 __be32 tid_len; 1474 #endif 1475 __be32 msn; 1476 __be32 mo; 1477 __u8 data[0]; 1478 }; 1479 1480 /* cpl_rdma_terminate.tid_len fields */ 1481 #define S_FLIT_CNT 0 1482 #define M_FLIT_CNT 0xFF 1483 #define V_FLIT_CNT(x) ((x) << S_FLIT_CNT) 1484 #define G_FLIT_CNT(x) (((x) >> S_FLIT_CNT) & M_FLIT_CNT) 1485 1486 #define S_TERM_TID 8 1487 #define M_TERM_TID 0xFFFFF 1488 #define V_TERM_TID(x) ((x) << S_TERM_TID) 1489 #define G_TERM_TID(x) (((x) >> S_TERM_TID) & M_TERM_TID) 1490 #endif /* T3_CPL_H */ 1491