1 /************************************************************************** 2 3 Copyright (c) 2007-2009 Chelsio Inc. 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Neither the name of the Chelsio Corporation nor the names of its 13 contributors may be used to endorse or promote products derived from 14 this software without specific prior written permission. 15 16 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 20 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 POSSIBILITY OF SUCH DAMAGE. 27 28 $FreeBSD$ 29 30 ***************************************************************************/ 31 #ifndef T3_CPL_H 32 #define T3_CPL_H 33 34 enum CPL_opcode { 35 CPL_PASS_OPEN_REQ = 0x1, 36 CPL_PASS_ACCEPT_RPL = 0x2, 37 CPL_ACT_OPEN_REQ = 0x3, 38 CPL_SET_TCB = 0x4, 39 CPL_SET_TCB_FIELD = 0x5, 40 CPL_GET_TCB = 0x6, 41 CPL_PCMD = 0x7, 42 CPL_CLOSE_CON_REQ = 0x8, 43 CPL_CLOSE_LISTSRV_REQ = 0x9, 44 CPL_ABORT_REQ = 0xA, 45 CPL_ABORT_RPL = 0xB, 46 CPL_TX_DATA = 0xC, 47 CPL_RX_DATA_ACK = 0xD, 48 CPL_TX_PKT = 0xE, 49 CPL_RTE_DELETE_REQ = 0xF, 50 CPL_RTE_WRITE_REQ = 0x10, 51 CPL_RTE_READ_REQ = 0x11, 52 CPL_L2T_WRITE_REQ = 0x12, 53 CPL_L2T_READ_REQ = 0x13, 54 CPL_SMT_WRITE_REQ = 0x14, 55 CPL_SMT_READ_REQ = 0x15, 56 CPL_TX_PKT_LSO = 0x16, 57 CPL_PCMD_READ = 0x17, 58 CPL_BARRIER = 0x18, 59 CPL_TID_RELEASE = 0x1A, 60 61 CPL_CLOSE_LISTSRV_RPL = 0x20, 62 CPL_ERROR = 0x21, 63 CPL_GET_TCB_RPL = 0x22, 64 CPL_L2T_WRITE_RPL = 0x23, 65 CPL_PCMD_READ_RPL = 0x24, 66 CPL_PCMD_RPL = 0x25, 67 CPL_PEER_CLOSE = 0x26, 68 CPL_RTE_DELETE_RPL = 0x27, 69 CPL_RTE_WRITE_RPL = 0x28, 70 CPL_RX_DDP_COMPLETE = 0x29, 71 CPL_RX_PHYS_ADDR = 0x2A, 72 CPL_RX_PKT = 0x2B, 73 CPL_RX_URG_NOTIFY = 0x2C, 74 CPL_SET_TCB_RPL = 0x2D, 75 CPL_SMT_WRITE_RPL = 0x2E, 76 CPL_TX_DATA_ACK = 0x2F, 77 78 CPL_ABORT_REQ_RSS = 0x30, 79 CPL_ABORT_RPL_RSS = 0x31, 80 CPL_CLOSE_CON_RPL = 0x32, 81 CPL_ISCSI_HDR = 0x33, 82 CPL_L2T_READ_RPL = 0x34, 83 CPL_RDMA_CQE = 0x35, 84 CPL_RDMA_CQE_READ_RSP = 0x36, 85 CPL_RDMA_CQE_ERR = 0x37, 86 CPL_RTE_READ_RPL = 0x38, 87 CPL_RX_DATA = 0x39, 88 89 CPL_ACT_OPEN_RPL = 0x40, 90 CPL_PASS_OPEN_RPL = 0x41, 91 CPL_RX_DATA_DDP = 0x42, 92 CPL_SMT_READ_RPL = 0x43, 93 94 CPL_ACT_ESTABLISH = 0x50, 95 CPL_PASS_ESTABLISH = 0x51, 96 97 CPL_PASS_ACCEPT_REQ = 0x70, 98 99 CPL_ASYNC_NOTIF = 0x80, /* fake opcode for async notifications */ 100 101 CPL_TX_DMA_ACK = 0xA0, 102 CPL_RDMA_READ_REQ = 0xA1, 103 CPL_RDMA_TERMINATE = 0xA2, 104 CPL_TRACE_PKT = 0xA3, 105 CPL_RDMA_EC_STATUS = 0xA5, 106 CPL_SGE_EC_CR_RETURN = 0xA6, 107 108 NUM_CPL_CMDS /* must be last and previous entries must be sorted */ 109 }; 110 111 enum CPL_error { 112 CPL_ERR_NONE = 0, 113 CPL_ERR_TCAM_PARITY = 1, 114 CPL_ERR_TCAM_FULL = 3, 115 CPL_ERR_CONN_RESET = 20, 116 CPL_ERR_CONN_EXIST = 22, 117 CPL_ERR_ARP_MISS = 23, 118 CPL_ERR_BAD_SYN = 24, 119 CPL_ERR_CONN_TIMEDOUT = 30, 120 CPL_ERR_XMIT_TIMEDOUT = 31, 121 CPL_ERR_PERSIST_TIMEDOUT = 32, 122 CPL_ERR_FINWAIT2_TIMEDOUT = 33, 123 CPL_ERR_KEEPALIVE_TIMEDOUT = 34, 124 CPL_ERR_RTX_NEG_ADVICE = 35, 125 CPL_ERR_PERSIST_NEG_ADVICE = 36, 126 CPL_ERR_ABORT_FAILED = 42, 127 CPL_ERR_GENERAL = 99 128 }; 129 130 enum { 131 CPL_CONN_POLICY_AUTO = 0, 132 CPL_CONN_POLICY_ASK = 1, 133 CPL_CONN_POLICY_FILTER = 2, 134 CPL_CONN_POLICY_DENY = 3 135 }; 136 137 enum { 138 ULP_MODE_NONE = 0, 139 ULP_MODE_TCP_DDP = 1, 140 ULP_MODE_ISCSI = 2, 141 ULP_MODE_RDMA = 4, 142 ULP_MODE_TCPDDP = 5 143 }; 144 145 enum { 146 ULP_CRC_HEADER = 1 << 0, 147 ULP_CRC_DATA = 1 << 1 148 }; 149 150 enum { 151 CPL_PASS_OPEN_ACCEPT, 152 CPL_PASS_OPEN_REJECT, 153 CPL_PASS_OPEN_ACCEPT_TNL 154 }; 155 156 enum { 157 CPL_ABORT_SEND_RST = 0, 158 CPL_ABORT_NO_RST, 159 CPL_ABORT_POST_CLOSE_REQ = 2 160 }; 161 162 enum { /* TX_PKT_LSO ethernet types */ 163 CPL_ETH_II, 164 CPL_ETH_II_VLAN, 165 CPL_ETH_802_3, 166 CPL_ETH_802_3_VLAN 167 }; 168 169 enum { /* TCP congestion control algorithms */ 170 CONG_ALG_RENO, 171 CONG_ALG_TAHOE, 172 CONG_ALG_NEWRENO, 173 CONG_ALG_HIGHSPEED 174 }; 175 176 enum { /* RSS hash type */ 177 RSS_HASH_NONE = 0, 178 RSS_HASH_2_TUPLE = 1, 179 RSS_HASH_4_TUPLE = 2, 180 RSS_HASH_TCPV6 = 3 181 }; 182 183 union opcode_tid { 184 __be32 opcode_tid; 185 __u8 opcode; 186 }; 187 188 #define S_OPCODE 24 189 #define V_OPCODE(x) ((x) << S_OPCODE) 190 #define G_OPCODE(x) (((x) >> S_OPCODE) & 0xFF) 191 #define G_TID(x) ((x) & 0xFFFFFF) 192 193 /* tid is assumed to be 24-bits */ 194 #define MK_OPCODE_TID(opcode, tid) (V_OPCODE(opcode) | (tid)) 195 196 #define OPCODE_TID(cmd) ((cmd)->ot.opcode_tid) 197 198 /* extract the TID from a CPL command */ 199 #define GET_TID(cmd) (G_TID(ntohl(OPCODE_TID(cmd)))) 200 201 struct tcp_options { 202 __be16 mss; 203 __u8 wsf; 204 #if defined(__LITTLE_ENDIAN_BITFIELD) 205 __u8 :5; 206 __u8 ecn:1; 207 __u8 sack:1; 208 __u8 tstamp:1; 209 #else 210 __u8 tstamp:1; 211 __u8 sack:1; 212 __u8 ecn:1; 213 __u8 :5; 214 #endif 215 }; 216 217 struct rss_header { 218 __u8 opcode; 219 #if defined(__LITTLE_ENDIAN_BITFIELD) 220 __u8 cpu_idx:6; 221 __u8 hash_type:2; 222 #else 223 __u8 hash_type:2; 224 __u8 cpu_idx:6; 225 #endif 226 __be16 cq_idx; 227 __be32 rss_hash_val; 228 }; 229 230 #define S_HASHTYPE 22 231 #define M_HASHTYPE 0x3 232 #define G_HASHTYPE(x) (((x) >> S_HASHTYPE) & M_HASHTYPE) 233 234 #define S_QNUM 0 235 #define M_QNUM 0xFFFF 236 #define G_QNUM(x) (((x) >> S_QNUM) & M_QNUM) 237 238 #ifndef CHELSIO_FW 239 struct work_request_hdr { 240 __be32 wr_hi; 241 __be32 wr_lo; 242 }; 243 244 /* wr_hi fields */ 245 #define S_WR_SGE_CREDITS 0 246 #define M_WR_SGE_CREDITS 0xFF 247 #define V_WR_SGE_CREDITS(x) ((x) << S_WR_SGE_CREDITS) 248 #define G_WR_SGE_CREDITS(x) (((x) >> S_WR_SGE_CREDITS) & M_WR_SGE_CREDITS) 249 250 #define S_WR_SGLSFLT 8 251 #define M_WR_SGLSFLT 0xFF 252 #define V_WR_SGLSFLT(x) ((x) << S_WR_SGLSFLT) 253 #define G_WR_SGLSFLT(x) (((x) >> S_WR_SGLSFLT) & M_WR_SGLSFLT) 254 255 #define S_WR_BCNTLFLT 16 256 #define M_WR_BCNTLFLT 0xF 257 #define V_WR_BCNTLFLT(x) ((x) << S_WR_BCNTLFLT) 258 #define G_WR_BCNTLFLT(x) (((x) >> S_WR_BCNTLFLT) & M_WR_BCNTLFLT) 259 260 /* 261 * Applicable to BYPASS WRs only: the uP will add a CPL_BARRIER before 262 * and after the BYPASS WR if the ATOMIC bit is set. 263 */ 264 #define S_WR_ATOMIC 16 265 #define V_WR_ATOMIC(x) ((x) << S_WR_ATOMIC) 266 #define F_WR_ATOMIC V_WR_ATOMIC(1U) 267 268 /* 269 * Applicable to BYPASS WRs only: the uP will flush buffered non abort 270 * related WRs. 271 */ 272 #define S_WR_FLUSH 17 273 #define V_WR_FLUSH(x) ((x) << S_WR_FLUSH) 274 #define F_WR_FLUSH V_WR_FLUSH(1U) 275 276 #define S_WR_CHN 18 277 #define V_WR_CHN(x) ((x) << S_WR_CHN) 278 #define F_WR_CHN V_WR_CHN(1U) 279 280 #define S_WR_CHN_VLD 19 281 #define V_WR_CHN_VLD(x) ((x) << S_WR_CHN_VLD) 282 #define F_WR_CHN_VLD V_WR_CHN_VLD(1U) 283 284 #define S_WR_DATATYPE 20 285 #define V_WR_DATATYPE(x) ((x) << S_WR_DATATYPE) 286 #define F_WR_DATATYPE V_WR_DATATYPE(1U) 287 288 #define S_WR_COMPL 21 289 #define V_WR_COMPL(x) ((x) << S_WR_COMPL) 290 #define F_WR_COMPL V_WR_COMPL(1U) 291 292 #define S_WR_EOP 22 293 #define V_WR_EOP(x) ((x) << S_WR_EOP) 294 #define F_WR_EOP V_WR_EOP(1U) 295 296 #define S_WR_SOP 23 297 #define V_WR_SOP(x) ((x) << S_WR_SOP) 298 #define F_WR_SOP V_WR_SOP(1U) 299 300 #define S_WR_OP 24 301 #define M_WR_OP 0xFF 302 #define V_WR_OP(x) ((x) << S_WR_OP) 303 #define G_WR_OP(x) (((x) >> S_WR_OP) & M_WR_OP) 304 305 /* wr_lo fields */ 306 #define S_WR_LEN 0 307 #define M_WR_LEN 0xFF 308 #define V_WR_LEN(x) ((x) << S_WR_LEN) 309 #define G_WR_LEN(x) (((x) >> S_WR_LEN) & M_WR_LEN) 310 311 #define S_WR_TID 8 312 #define M_WR_TID 0xFFFFF 313 #define V_WR_TID(x) ((x) << S_WR_TID) 314 #define G_WR_TID(x) (((x) >> S_WR_TID) & M_WR_TID) 315 316 #define S_WR_CR_FLUSH 30 317 #define V_WR_CR_FLUSH(x) ((x) << S_WR_CR_FLUSH) 318 #define F_WR_CR_FLUSH V_WR_CR_FLUSH(1U) 319 320 #define S_WR_GEN 31 321 #define V_WR_GEN(x) ((x) << S_WR_GEN) 322 #define F_WR_GEN V_WR_GEN(1U) 323 #define G_WR_GEN(x) ((x) >> S_WR_GEN) 324 325 # define WR_HDR struct work_request_hdr wr 326 # define RSS_HDR 327 #else 328 # define WR_HDR 329 # define RSS_HDR struct rss_header rss_hdr; 330 #endif 331 332 /* option 0 lower-half fields */ 333 #define S_CPL_STATUS 0 334 #define M_CPL_STATUS 0xFF 335 #define V_CPL_STATUS(x) ((x) << S_CPL_STATUS) 336 #define G_CPL_STATUS(x) (((x) >> S_CPL_STATUS) & M_CPL_STATUS) 337 338 #define S_INJECT_TIMER 6 339 #define V_INJECT_TIMER(x) ((x) << S_INJECT_TIMER) 340 #define F_INJECT_TIMER V_INJECT_TIMER(1U) 341 342 #define S_NO_OFFLOAD 7 343 #define V_NO_OFFLOAD(x) ((x) << S_NO_OFFLOAD) 344 #define F_NO_OFFLOAD V_NO_OFFLOAD(1U) 345 346 #define S_ULP_MODE 8 347 #define M_ULP_MODE 0xF 348 #define V_ULP_MODE(x) ((x) << S_ULP_MODE) 349 #define G_ULP_MODE(x) (((x) >> S_ULP_MODE) & M_ULP_MODE) 350 351 #define S_RCV_BUFSIZ 12 352 #define M_RCV_BUFSIZ 0x3FFF 353 #define V_RCV_BUFSIZ(x) ((x) << S_RCV_BUFSIZ) 354 #define G_RCV_BUFSIZ(x) (((x) >> S_RCV_BUFSIZ) & M_RCV_BUFSIZ) 355 356 #define S_TOS 26 357 #define M_TOS 0x3F 358 #define V_TOS(x) ((x) << S_TOS) 359 #define G_TOS(x) (((x) >> S_TOS) & M_TOS) 360 361 /* option 0 upper-half fields */ 362 #define S_DELACK 0 363 #define V_DELACK(x) ((x) << S_DELACK) 364 #define F_DELACK V_DELACK(1U) 365 366 #define S_NO_CONG 1 367 #define V_NO_CONG(x) ((x) << S_NO_CONG) 368 #define F_NO_CONG V_NO_CONG(1U) 369 370 #define S_SRC_MAC_SEL 2 371 #define M_SRC_MAC_SEL 0x3 372 #define V_SRC_MAC_SEL(x) ((x) << S_SRC_MAC_SEL) 373 #define G_SRC_MAC_SEL(x) (((x) >> S_SRC_MAC_SEL) & M_SRC_MAC_SEL) 374 375 #define S_L2T_IDX 4 376 #define M_L2T_IDX 0x7FF 377 #define V_L2T_IDX(x) ((x) << S_L2T_IDX) 378 #define G_L2T_IDX(x) (((x) >> S_L2T_IDX) & M_L2T_IDX) 379 380 #define S_TX_CHANNEL 15 381 #define V_TX_CHANNEL(x) ((x) << S_TX_CHANNEL) 382 #define F_TX_CHANNEL V_TX_CHANNEL(1U) 383 384 #define S_TCAM_BYPASS 16 385 #define V_TCAM_BYPASS(x) ((x) << S_TCAM_BYPASS) 386 #define F_TCAM_BYPASS V_TCAM_BYPASS(1U) 387 388 #define S_NAGLE 17 389 #define V_NAGLE(x) ((x) << S_NAGLE) 390 #define F_NAGLE V_NAGLE(1U) 391 392 #define S_WND_SCALE 18 393 #define M_WND_SCALE 0xF 394 #define V_WND_SCALE(x) ((x) << S_WND_SCALE) 395 #define G_WND_SCALE(x) (((x) >> S_WND_SCALE) & M_WND_SCALE) 396 397 #define S_KEEP_ALIVE 22 398 #define V_KEEP_ALIVE(x) ((x) << S_KEEP_ALIVE) 399 #define F_KEEP_ALIVE V_KEEP_ALIVE(1U) 400 401 #define S_MAX_RETRANS 23 402 #define M_MAX_RETRANS 0xF 403 #define V_MAX_RETRANS(x) ((x) << S_MAX_RETRANS) 404 #define G_MAX_RETRANS(x) (((x) >> S_MAX_RETRANS) & M_MAX_RETRANS) 405 406 #define S_MAX_RETRANS_OVERRIDE 27 407 #define V_MAX_RETRANS_OVERRIDE(x) ((x) << S_MAX_RETRANS_OVERRIDE) 408 #define F_MAX_RETRANS_OVERRIDE V_MAX_RETRANS_OVERRIDE(1U) 409 410 #define S_MSS_IDX 28 411 #define M_MSS_IDX 0xF 412 #define V_MSS_IDX(x) ((x) << S_MSS_IDX) 413 #define G_MSS_IDX(x) (((x) >> S_MSS_IDX) & M_MSS_IDX) 414 415 /* option 1 fields */ 416 #define S_RSS_ENABLE 0 417 #define V_RSS_ENABLE(x) ((x) << S_RSS_ENABLE) 418 #define F_RSS_ENABLE V_RSS_ENABLE(1U) 419 420 #define S_RSS_MASK_LEN 1 421 #define M_RSS_MASK_LEN 0x7 422 #define V_RSS_MASK_LEN(x) ((x) << S_RSS_MASK_LEN) 423 #define G_RSS_MASK_LEN(x) (((x) >> S_RSS_MASK_LEN) & M_RSS_MASK_LEN) 424 425 #define S_CPU_IDX 4 426 #define M_CPU_IDX 0x3F 427 #define V_CPU_IDX(x) ((x) << S_CPU_IDX) 428 #define G_CPU_IDX(x) (((x) >> S_CPU_IDX) & M_CPU_IDX) 429 430 #define S_OPT1_VLAN 6 431 #define M_OPT1_VLAN 0xFFF 432 #define V_OPT1_VLAN(x) ((x) << S_OPT1_VLAN) 433 #define G_OPT1_VLAN(x) (((x) >> S_OPT1_VLAN) & M_OPT1_VLAN) 434 435 #define S_MAC_MATCH_VALID 18 436 #define V_MAC_MATCH_VALID(x) ((x) << S_MAC_MATCH_VALID) 437 #define F_MAC_MATCH_VALID V_MAC_MATCH_VALID(1U) 438 439 #define S_CONN_POLICY 19 440 #define M_CONN_POLICY 0x3 441 #define V_CONN_POLICY(x) ((x) << S_CONN_POLICY) 442 #define G_CONN_POLICY(x) (((x) >> S_CONN_POLICY) & M_CONN_POLICY) 443 444 #define S_SYN_DEFENSE 21 445 #define V_SYN_DEFENSE(x) ((x) << S_SYN_DEFENSE) 446 #define F_SYN_DEFENSE V_SYN_DEFENSE(1U) 447 448 #define S_VLAN_PRI 22 449 #define M_VLAN_PRI 0x3 450 #define V_VLAN_PRI(x) ((x) << S_VLAN_PRI) 451 #define G_VLAN_PRI(x) (((x) >> S_VLAN_PRI) & M_VLAN_PRI) 452 453 #define S_VLAN_PRI_VALID 24 454 #define V_VLAN_PRI_VALID(x) ((x) << S_VLAN_PRI_VALID) 455 #define F_VLAN_PRI_VALID V_VLAN_PRI_VALID(1U) 456 457 #define S_PKT_TYPE 25 458 #define M_PKT_TYPE 0x3 459 #define V_PKT_TYPE(x) ((x) << S_PKT_TYPE) 460 #define G_PKT_TYPE(x) (((x) >> S_PKT_TYPE) & M_PKT_TYPE) 461 462 #define S_MAC_MATCH 27 463 #define M_MAC_MATCH 0x1F 464 #define V_MAC_MATCH(x) ((x) << S_MAC_MATCH) 465 #define G_MAC_MATCH(x) (((x) >> S_MAC_MATCH) & M_MAC_MATCH) 466 467 /* option 2 fields */ 468 #define S_CPU_INDEX 0 469 #define M_CPU_INDEX 0x7F 470 #define V_CPU_INDEX(x) ((x) << S_CPU_INDEX) 471 #define G_CPU_INDEX(x) (((x) >> S_CPU_INDEX) & M_CPU_INDEX) 472 473 #define S_CPU_INDEX_VALID 7 474 #define V_CPU_INDEX_VALID(x) ((x) << S_CPU_INDEX_VALID) 475 #define F_CPU_INDEX_VALID V_CPU_INDEX_VALID(1U) 476 477 #define S_RX_COALESCE 8 478 #define M_RX_COALESCE 0x3 479 #define V_RX_COALESCE(x) ((x) << S_RX_COALESCE) 480 #define G_RX_COALESCE(x) (((x) >> S_RX_COALESCE) & M_RX_COALESCE) 481 482 #define S_RX_COALESCE_VALID 10 483 #define V_RX_COALESCE_VALID(x) ((x) << S_RX_COALESCE_VALID) 484 #define F_RX_COALESCE_VALID V_RX_COALESCE_VALID(1U) 485 486 #define S_CONG_CONTROL_FLAVOR 11 487 #define M_CONG_CONTROL_FLAVOR 0x3 488 #define V_CONG_CONTROL_FLAVOR(x) ((x) << S_CONG_CONTROL_FLAVOR) 489 #define G_CONG_CONTROL_FLAVOR(x) (((x) >> S_CONG_CONTROL_FLAVOR) & M_CONG_CONTROL_FLAVOR) 490 491 #define S_PACING_FLAVOR 13 492 #define M_PACING_FLAVOR 0x3 493 #define V_PACING_FLAVOR(x) ((x) << S_PACING_FLAVOR) 494 #define G_PACING_FLAVOR(x) (((x) >> S_PACING_FLAVOR) & M_PACING_FLAVOR) 495 496 #define S_FLAVORS_VALID 15 497 #define V_FLAVORS_VALID(x) ((x) << S_FLAVORS_VALID) 498 #define F_FLAVORS_VALID V_FLAVORS_VALID(1U) 499 500 #define S_RX_FC_DISABLE 16 501 #define V_RX_FC_DISABLE(x) ((x) << S_RX_FC_DISABLE) 502 #define F_RX_FC_DISABLE V_RX_FC_DISABLE(1U) 503 504 #define S_RX_FC_VALID 17 505 #define V_RX_FC_VALID(x) ((x) << S_RX_FC_VALID) 506 #define F_RX_FC_VALID V_RX_FC_VALID(1U) 507 508 struct cpl_pass_open_req { 509 WR_HDR; 510 union opcode_tid ot; 511 __be16 local_port; 512 __be16 peer_port; 513 __be32 local_ip; 514 __be32 peer_ip; 515 __be32 opt0h; 516 __be32 opt0l; 517 __be32 peer_netmask; 518 __be32 opt1; 519 }; 520 521 struct cpl_pass_open_rpl { 522 RSS_HDR 523 union opcode_tid ot; 524 __be16 local_port; 525 __be16 peer_port; 526 __be32 local_ip; 527 __be32 peer_ip; 528 __u8 resvd[7]; 529 __u8 status; 530 }; 531 532 struct cpl_pass_establish { 533 RSS_HDR 534 union opcode_tid ot; 535 __be16 local_port; 536 __be16 peer_port; 537 __be32 local_ip; 538 __be32 peer_ip; 539 __be32 tos_tid; 540 __be16 l2t_idx; 541 __be16 tcp_opt; 542 __be32 snd_isn; 543 __be32 rcv_isn; 544 }; 545 546 /* cpl_pass_establish.tos_tid fields */ 547 #define S_PASS_OPEN_TID 0 548 #define M_PASS_OPEN_TID 0xFFFFFF 549 #define V_PASS_OPEN_TID(x) ((x) << S_PASS_OPEN_TID) 550 #define G_PASS_OPEN_TID(x) (((x) >> S_PASS_OPEN_TID) & M_PASS_OPEN_TID) 551 552 #define S_PASS_OPEN_TOS 24 553 #define M_PASS_OPEN_TOS 0xFF 554 #define V_PASS_OPEN_TOS(x) ((x) << S_PASS_OPEN_TOS) 555 #define G_PASS_OPEN_TOS(x) (((x) >> S_PASS_OPEN_TOS) & M_PASS_OPEN_TOS) 556 557 /* cpl_pass_establish.l2t_idx fields */ 558 #define S_L2T_IDX16 5 559 #define M_L2T_IDX16 0x7FF 560 #define V_L2T_IDX16(x) ((x) << S_L2T_IDX16) 561 #define G_L2T_IDX16(x) (((x) >> S_L2T_IDX16) & M_L2T_IDX16) 562 563 /* cpl_pass_establish.tcp_opt fields (also applies act_open_establish) */ 564 #define G_TCPOPT_WSCALE_OK(x) (((x) >> 5) & 1) 565 #define G_TCPOPT_SACK(x) (((x) >> 6) & 1) 566 #define G_TCPOPT_TSTAMP(x) (((x) >> 7) & 1) 567 #define G_TCPOPT_SND_WSCALE(x) (((x) >> 8) & 0xf) 568 #define G_TCPOPT_MSS(x) (((x) >> 12) & 0xf) 569 570 struct cpl_pass_accept_req { 571 RSS_HDR 572 union opcode_tid ot; 573 __be16 local_port; 574 __be16 peer_port; 575 __be32 local_ip; 576 __be32 peer_ip; 577 __be32 tos_tid; 578 struct tcp_options tcp_options; 579 __u8 dst_mac[6]; 580 __be16 vlan_tag; 581 __u8 src_mac[6]; 582 #if defined(__LITTLE_ENDIAN_BITFIELD) 583 __u8 :3; 584 __u8 addr_idx:3; 585 __u8 port_idx:1; 586 __u8 exact_match:1; 587 #else 588 __u8 exact_match:1; 589 __u8 port_idx:1; 590 __u8 addr_idx:3; 591 __u8 :3; 592 #endif 593 __u8 rsvd; 594 __be32 rcv_isn; 595 __be32 rsvd2; 596 }; 597 598 struct cpl_pass_accept_rpl { 599 WR_HDR; 600 union opcode_tid ot; 601 __be32 opt2; 602 __be32 rsvd; 603 __be32 peer_ip; 604 __be32 opt0h; 605 __be32 opt0l_status; 606 }; 607 608 struct cpl_act_open_req { 609 WR_HDR; 610 union opcode_tid ot; 611 __be16 local_port; 612 __be16 peer_port; 613 __be32 local_ip; 614 __be32 peer_ip; 615 __be32 opt0h; 616 __be32 opt0l; 617 __be32 params; 618 __be32 opt2; 619 }; 620 621 /* cpl_act_open_req.params fields */ 622 #define S_AOPEN_VLAN_PRI 9 623 #define M_AOPEN_VLAN_PRI 0x3 624 #define V_AOPEN_VLAN_PRI(x) ((x) << S_AOPEN_VLAN_PRI) 625 #define G_AOPEN_VLAN_PRI(x) (((x) >> S_AOPEN_VLAN_PRI) & M_AOPEN_VLAN_PRI) 626 627 #define S_AOPEN_VLAN_PRI_VALID 11 628 #define V_AOPEN_VLAN_PRI_VALID(x) ((x) << S_AOPEN_VLAN_PRI_VALID) 629 #define F_AOPEN_VLAN_PRI_VALID V_AOPEN_VLAN_PRI_VALID(1U) 630 631 #define S_AOPEN_PKT_TYPE 12 632 #define M_AOPEN_PKT_TYPE 0x3 633 #define V_AOPEN_PKT_TYPE(x) ((x) << S_AOPEN_PKT_TYPE) 634 #define G_AOPEN_PKT_TYPE(x) (((x) >> S_AOPEN_PKT_TYPE) & M_AOPEN_PKT_TYPE) 635 636 #define S_AOPEN_MAC_MATCH 14 637 #define M_AOPEN_MAC_MATCH 0x1F 638 #define V_AOPEN_MAC_MATCH(x) ((x) << S_AOPEN_MAC_MATCH) 639 #define G_AOPEN_MAC_MATCH(x) (((x) >> S_AOPEN_MAC_MATCH) & M_AOPEN_MAC_MATCH) 640 641 #define S_AOPEN_MAC_MATCH_VALID 19 642 #define V_AOPEN_MAC_MATCH_VALID(x) ((x) << S_AOPEN_MAC_MATCH_VALID) 643 #define F_AOPEN_MAC_MATCH_VALID V_AOPEN_MAC_MATCH_VALID(1U) 644 645 #define S_AOPEN_IFF_VLAN 20 646 #define M_AOPEN_IFF_VLAN 0xFFF 647 #define V_AOPEN_IFF_VLAN(x) ((x) << S_AOPEN_IFF_VLAN) 648 #define G_AOPEN_IFF_VLAN(x) (((x) >> S_AOPEN_IFF_VLAN) & M_AOPEN_IFF_VLAN) 649 650 struct cpl_act_open_rpl { 651 RSS_HDR 652 union opcode_tid ot; 653 __be16 local_port; 654 __be16 peer_port; 655 __be32 local_ip; 656 __be32 peer_ip; 657 __be32 atid; 658 __u8 rsvd[3]; 659 __u8 status; 660 }; 661 662 struct cpl_act_establish { 663 RSS_HDR 664 union opcode_tid ot; 665 __be16 local_port; 666 __be16 peer_port; 667 __be32 local_ip; 668 __be32 peer_ip; 669 __be32 tos_tid; 670 __be16 l2t_idx; 671 __be16 tcp_opt; 672 __be32 snd_isn; 673 __be32 rcv_isn; 674 }; 675 676 struct cpl_get_tcb { 677 WR_HDR; 678 union opcode_tid ot; 679 __be16 cpuno; 680 __be16 rsvd; 681 }; 682 683 struct cpl_get_tcb_rpl { 684 RSS_HDR 685 union opcode_tid ot; 686 __u8 rsvd; 687 __u8 status; 688 __be16 len; 689 }; 690 691 struct cpl_set_tcb { 692 WR_HDR; 693 union opcode_tid ot; 694 __u8 reply; 695 __u8 cpu_idx; 696 __be16 len; 697 }; 698 699 /* cpl_set_tcb.reply fields */ 700 #define S_NO_REPLY 7 701 #define V_NO_REPLY(x) ((x) << S_NO_REPLY) 702 #define F_NO_REPLY V_NO_REPLY(1U) 703 704 struct cpl_set_tcb_field { 705 WR_HDR; 706 union opcode_tid ot; 707 __u8 reply; 708 __u8 cpu_idx; 709 __be16 word; 710 __be64 mask; 711 __be64 val; 712 }; 713 714 struct cpl_set_tcb_rpl { 715 RSS_HDR 716 union opcode_tid ot; 717 __u8 rsvd[3]; 718 __u8 status; 719 }; 720 721 struct cpl_pcmd { 722 WR_HDR; 723 union opcode_tid ot; 724 __u8 rsvd[3]; 725 #if defined(__LITTLE_ENDIAN_BITFIELD) 726 __u8 src:1; 727 __u8 bundle:1; 728 __u8 channel:1; 729 __u8 :5; 730 #else 731 __u8 :5; 732 __u8 channel:1; 733 __u8 bundle:1; 734 __u8 src:1; 735 #endif 736 __be32 pcmd_parm[2]; 737 }; 738 739 struct cpl_pcmd_reply { 740 RSS_HDR 741 union opcode_tid ot; 742 __u8 status; 743 __u8 rsvd; 744 __be16 len; 745 }; 746 747 struct cpl_close_con_req { 748 WR_HDR; 749 union opcode_tid ot; 750 __be32 rsvd; 751 }; 752 753 struct cpl_close_con_rpl { 754 RSS_HDR 755 union opcode_tid ot; 756 __u8 rsvd[3]; 757 __u8 status; 758 __be32 snd_nxt; 759 __be32 rcv_nxt; 760 }; 761 762 struct cpl_close_listserv_req { 763 WR_HDR; 764 union opcode_tid ot; 765 __u8 rsvd0; 766 __u8 cpu_idx; 767 __be16 rsvd1; 768 }; 769 770 struct cpl_close_listserv_rpl { 771 RSS_HDR 772 union opcode_tid ot; 773 __u8 rsvd[3]; 774 __u8 status; 775 }; 776 777 struct cpl_abort_req_rss { 778 RSS_HDR 779 union opcode_tid ot; 780 __be32 rsvd0; 781 __u8 rsvd1; 782 __u8 status; 783 __u8 rsvd2[6]; 784 }; 785 786 struct cpl_abort_req { 787 WR_HDR; 788 union opcode_tid ot; 789 __be32 rsvd0; 790 __u8 rsvd1; 791 __u8 cmd; 792 __u8 rsvd2[6]; 793 }; 794 795 struct cpl_abort_rpl_rss { 796 RSS_HDR 797 union opcode_tid ot; 798 __be32 rsvd0; 799 __u8 rsvd1; 800 __u8 status; 801 __u8 rsvd2[6]; 802 }; 803 804 struct cpl_abort_rpl { 805 WR_HDR; 806 union opcode_tid ot; 807 __be32 rsvd0; 808 __u8 rsvd1; 809 __u8 cmd; 810 __u8 rsvd2[6]; 811 }; 812 813 struct cpl_peer_close { 814 RSS_HDR 815 union opcode_tid ot; 816 __be32 rcv_nxt; 817 }; 818 819 struct tx_data_wr { 820 __be32 wr_hi; 821 __be32 wr_lo; 822 __be32 len; 823 __be32 flags; 824 __be32 sndseq; 825 __be32 param; 826 }; 827 828 /* tx_data_wr.flags fields */ 829 #define S_TX_ACK_PAGES 21 830 #define M_TX_ACK_PAGES 0x7 831 #define V_TX_ACK_PAGES(x) ((x) << S_TX_ACK_PAGES) 832 #define G_TX_ACK_PAGES(x) (((x) >> S_TX_ACK_PAGES) & M_TX_ACK_PAGES) 833 834 /* tx_data_wr.param fields */ 835 #define S_TX_PORT 0 836 #define M_TX_PORT 0x7 837 #define V_TX_PORT(x) ((x) << S_TX_PORT) 838 #define G_TX_PORT(x) (((x) >> S_TX_PORT) & M_TX_PORT) 839 840 #define S_TX_MSS 4 841 #define M_TX_MSS 0xF 842 #define V_TX_MSS(x) ((x) << S_TX_MSS) 843 #define G_TX_MSS(x) (((x) >> S_TX_MSS) & M_TX_MSS) 844 845 #define S_TX_QOS 8 846 #define M_TX_QOS 0xFF 847 #define V_TX_QOS(x) ((x) << S_TX_QOS) 848 #define G_TX_QOS(x) (((x) >> S_TX_QOS) & M_TX_QOS) 849 850 #define S_TX_SNDBUF 16 851 #define M_TX_SNDBUF 0xFFFF 852 #define V_TX_SNDBUF(x) ((x) << S_TX_SNDBUF) 853 #define G_TX_SNDBUF(x) (((x) >> S_TX_SNDBUF) & M_TX_SNDBUF) 854 855 struct cpl_tx_data { 856 union opcode_tid ot; 857 __be32 len; 858 __be32 rsvd; 859 __be16 urg; 860 __be16 flags; 861 }; 862 863 /* cpl_tx_data.flags fields */ 864 #define S_TX_ULP_SUBMODE 6 865 #define M_TX_ULP_SUBMODE 0xF 866 #define V_TX_ULP_SUBMODE(x) ((x) << S_TX_ULP_SUBMODE) 867 #define G_TX_ULP_SUBMODE(x) (((x) >> S_TX_ULP_SUBMODE) & M_TX_ULP_SUBMODE) 868 869 #define S_TX_ULP_MODE 10 870 #define M_TX_ULP_MODE 0xF 871 #define V_TX_ULP_MODE(x) ((x) << S_TX_ULP_MODE) 872 #define G_TX_ULP_MODE(x) (((x) >> S_TX_ULP_MODE) & M_TX_ULP_MODE) 873 874 #define S_TX_SHOVE 14 875 #define V_TX_SHOVE(x) ((x) << S_TX_SHOVE) 876 #define F_TX_SHOVE V_TX_SHOVE(1U) 877 878 #define S_TX_MORE 15 879 #define V_TX_MORE(x) ((x) << S_TX_MORE) 880 #define F_TX_MORE V_TX_MORE(1U) 881 882 /* additional tx_data_wr.flags fields */ 883 #define S_TX_CPU_IDX 0 884 #define M_TX_CPU_IDX 0x3F 885 #define V_TX_CPU_IDX(x) ((x) << S_TX_CPU_IDX) 886 #define G_TX_CPU_IDX(x) (((x) >> S_TX_CPU_IDX) & M_TX_CPU_IDX) 887 888 #define S_TX_URG 16 889 #define V_TX_URG(x) ((x) << S_TX_URG) 890 #define F_TX_URG V_TX_URG(1U) 891 892 #define S_TX_CLOSE 17 893 #define V_TX_CLOSE(x) ((x) << S_TX_CLOSE) 894 #define F_TX_CLOSE V_TX_CLOSE(1U) 895 896 #define S_TX_INIT 18 897 #define V_TX_INIT(x) ((x) << S_TX_INIT) 898 #define F_TX_INIT V_TX_INIT(1U) 899 900 #define S_TX_IMM_ACK 19 901 #define V_TX_IMM_ACK(x) ((x) << S_TX_IMM_ACK) 902 #define F_TX_IMM_ACK V_TX_IMM_ACK(1U) 903 904 #define S_TX_IMM_DMA 20 905 #define V_TX_IMM_DMA(x) ((x) << S_TX_IMM_DMA) 906 #define F_TX_IMM_DMA V_TX_IMM_DMA(1U) 907 908 struct cpl_tx_data_ack { 909 RSS_HDR 910 union opcode_tid ot; 911 __be32 ack_seq; 912 }; 913 914 struct cpl_wr_ack { 915 RSS_HDR 916 union opcode_tid ot; 917 __be16 credits; 918 __be16 rsvd; 919 __be32 snd_nxt; 920 __be32 snd_una; 921 }; 922 923 struct cpl_sge_ec_cr_return { 924 RSS_HDR 925 union opcode_tid ot; 926 __be16 sge_ec_id; 927 __u8 cr; 928 __u8 rsvd; 929 }; 930 931 struct cpl_rdma_ec_status { 932 RSS_HDR 933 union opcode_tid ot; 934 __u8 rsvd[3]; 935 __u8 status; 936 }; 937 938 struct mngt_pktsched_wr { 939 __be32 wr_hi; 940 __be32 wr_lo; 941 __u8 mngt_opcode; 942 __u8 rsvd[7]; 943 __u8 sched; 944 __u8 idx; 945 __u8 min; 946 __u8 max; 947 __u8 binding; 948 __u8 rsvd1[3]; 949 }; 950 951 struct cpl_iscsi_hdr { 952 RSS_HDR 953 union opcode_tid ot; 954 __be16 pdu_len_ddp; 955 __be16 len; 956 __be32 seq; 957 __be16 urg; 958 __u8 rsvd; 959 __u8 status; 960 }; 961 962 /* cpl_iscsi_hdr.pdu_len_ddp fields */ 963 #define S_ISCSI_PDU_LEN 0 964 #define M_ISCSI_PDU_LEN 0x7FFF 965 #define V_ISCSI_PDU_LEN(x) ((x) << S_ISCSI_PDU_LEN) 966 #define G_ISCSI_PDU_LEN(x) (((x) >> S_ISCSI_PDU_LEN) & M_ISCSI_PDU_LEN) 967 968 #define S_ISCSI_DDP 15 969 #define V_ISCSI_DDP(x) ((x) << S_ISCSI_DDP) 970 #define F_ISCSI_DDP V_ISCSI_DDP(1U) 971 972 struct cpl_rx_data { 973 RSS_HDR 974 union opcode_tid ot; 975 __be16 rsvd; 976 __be16 len; 977 __be32 seq; 978 __be16 urg; 979 #if defined(__LITTLE_ENDIAN_BITFIELD) 980 __u8 dack_mode:2; 981 __u8 psh:1; 982 __u8 heartbeat:1; 983 __u8 ddp_off:1; 984 __u8 :3; 985 #else 986 __u8 :3; 987 __u8 ddp_off:1; 988 __u8 heartbeat:1; 989 __u8 psh:1; 990 __u8 dack_mode:2; 991 #endif 992 __u8 status; 993 }; 994 995 struct cpl_rx_data_ack { 996 WR_HDR; 997 union opcode_tid ot; 998 __be32 credit_dack; 999 }; 1000 1001 /* cpl_rx_data_ack.ack_seq fields */ 1002 #define S_RX_CREDITS 0 1003 #define M_RX_CREDITS 0x7FFFFFF 1004 #define V_RX_CREDITS(x) ((x) << S_RX_CREDITS) 1005 #define G_RX_CREDITS(x) (((x) >> S_RX_CREDITS) & M_RX_CREDITS) 1006 1007 #define S_RX_MODULATE 27 1008 #define V_RX_MODULATE(x) ((x) << S_RX_MODULATE) 1009 #define F_RX_MODULATE V_RX_MODULATE(1U) 1010 1011 #define S_RX_FORCE_ACK 28 1012 #define V_RX_FORCE_ACK(x) ((x) << S_RX_FORCE_ACK) 1013 #define F_RX_FORCE_ACK V_RX_FORCE_ACK(1U) 1014 1015 #define S_RX_DACK_MODE 29 1016 #define M_RX_DACK_MODE 0x3 1017 #define V_RX_DACK_MODE(x) ((x) << S_RX_DACK_MODE) 1018 #define G_RX_DACK_MODE(x) (((x) >> S_RX_DACK_MODE) & M_RX_DACK_MODE) 1019 1020 #define S_RX_DACK_CHANGE 31 1021 #define V_RX_DACK_CHANGE(x) ((x) << S_RX_DACK_CHANGE) 1022 #define F_RX_DACK_CHANGE V_RX_DACK_CHANGE(1U) 1023 1024 struct cpl_rx_urg_notify { 1025 RSS_HDR 1026 union opcode_tid ot; 1027 __be32 seq; 1028 }; 1029 1030 struct cpl_rx_ddp_complete { 1031 RSS_HDR 1032 union opcode_tid ot; 1033 __be32 ddp_report; 1034 }; 1035 1036 struct cpl_rx_data_ddp { 1037 RSS_HDR 1038 union opcode_tid ot; 1039 __be16 urg; 1040 __be16 len; 1041 __be32 seq; 1042 union { 1043 __be32 nxt_seq; 1044 __be32 ddp_report; 1045 } u; 1046 __be32 ulp_crc; 1047 __be32 ddpvld_status; 1048 }; 1049 1050 /* cpl_rx_data_ddp.ddpvld_status fields */ 1051 #define S_DDP_STATUS 0 1052 #define M_DDP_STATUS 0xFF 1053 #define V_DDP_STATUS(x) ((x) << S_DDP_STATUS) 1054 #define G_DDP_STATUS(x) (((x) >> S_DDP_STATUS) & M_DDP_STATUS) 1055 1056 #define S_DDP_VALID 15 1057 #define M_DDP_VALID 0x1FFFF 1058 #define V_DDP_VALID(x) ((x) << S_DDP_VALID) 1059 #define G_DDP_VALID(x) (((x) >> S_DDP_VALID) & M_DDP_VALID) 1060 1061 #define S_DDP_PPOD_MISMATCH 15 1062 #define V_DDP_PPOD_MISMATCH(x) ((x) << S_DDP_PPOD_MISMATCH) 1063 #define F_DDP_PPOD_MISMATCH V_DDP_PPOD_MISMATCH(1U) 1064 1065 #define S_DDP_PDU 16 1066 #define V_DDP_PDU(x) ((x) << S_DDP_PDU) 1067 #define F_DDP_PDU V_DDP_PDU(1U) 1068 1069 #define S_DDP_LLIMIT_ERR 17 1070 #define V_DDP_LLIMIT_ERR(x) ((x) << S_DDP_LLIMIT_ERR) 1071 #define F_DDP_LLIMIT_ERR V_DDP_LLIMIT_ERR(1U) 1072 1073 #define S_DDP_PPOD_PARITY_ERR 18 1074 #define V_DDP_PPOD_PARITY_ERR(x) ((x) << S_DDP_PPOD_PARITY_ERR) 1075 #define F_DDP_PPOD_PARITY_ERR V_DDP_PPOD_PARITY_ERR(1U) 1076 1077 #define S_DDP_PADDING_ERR 19 1078 #define V_DDP_PADDING_ERR(x) ((x) << S_DDP_PADDING_ERR) 1079 #define F_DDP_PADDING_ERR V_DDP_PADDING_ERR(1U) 1080 1081 #define S_DDP_HDRCRC_ERR 20 1082 #define V_DDP_HDRCRC_ERR(x) ((x) << S_DDP_HDRCRC_ERR) 1083 #define F_DDP_HDRCRC_ERR V_DDP_HDRCRC_ERR(1U) 1084 1085 #define S_DDP_DATACRC_ERR 21 1086 #define V_DDP_DATACRC_ERR(x) ((x) << S_DDP_DATACRC_ERR) 1087 #define F_DDP_DATACRC_ERR V_DDP_DATACRC_ERR(1U) 1088 1089 #define S_DDP_INVALID_TAG 22 1090 #define V_DDP_INVALID_TAG(x) ((x) << S_DDP_INVALID_TAG) 1091 #define F_DDP_INVALID_TAG V_DDP_INVALID_TAG(1U) 1092 1093 #define S_DDP_ULIMIT_ERR 23 1094 #define V_DDP_ULIMIT_ERR(x) ((x) << S_DDP_ULIMIT_ERR) 1095 #define F_DDP_ULIMIT_ERR V_DDP_ULIMIT_ERR(1U) 1096 1097 #define S_DDP_OFFSET_ERR 24 1098 #define V_DDP_OFFSET_ERR(x) ((x) << S_DDP_OFFSET_ERR) 1099 #define F_DDP_OFFSET_ERR V_DDP_OFFSET_ERR(1U) 1100 1101 #define S_DDP_COLOR_ERR 25 1102 #define V_DDP_COLOR_ERR(x) ((x) << S_DDP_COLOR_ERR) 1103 #define F_DDP_COLOR_ERR V_DDP_COLOR_ERR(1U) 1104 1105 #define S_DDP_TID_MISMATCH 26 1106 #define V_DDP_TID_MISMATCH(x) ((x) << S_DDP_TID_MISMATCH) 1107 #define F_DDP_TID_MISMATCH V_DDP_TID_MISMATCH(1U) 1108 1109 #define S_DDP_INVALID_PPOD 27 1110 #define V_DDP_INVALID_PPOD(x) ((x) << S_DDP_INVALID_PPOD) 1111 #define F_DDP_INVALID_PPOD V_DDP_INVALID_PPOD(1U) 1112 1113 #define S_DDP_ULP_MODE 28 1114 #define M_DDP_ULP_MODE 0xF 1115 #define V_DDP_ULP_MODE(x) ((x) << S_DDP_ULP_MODE) 1116 #define G_DDP_ULP_MODE(x) (((x) >> S_DDP_ULP_MODE) & M_DDP_ULP_MODE) 1117 1118 /* cpl_rx_data_ddp.ddp_report fields */ 1119 #define S_DDP_OFFSET 0 1120 #define M_DDP_OFFSET 0x3FFFFF 1121 #define V_DDP_OFFSET(x) ((x) << S_DDP_OFFSET) 1122 #define G_DDP_OFFSET(x) (((x) >> S_DDP_OFFSET) & M_DDP_OFFSET) 1123 1124 #define S_DDP_DACK_MODE 22 1125 #define M_DDP_DACK_MODE 0x3 1126 #define V_DDP_DACK_MODE(x) ((x) << S_DDP_DACK_MODE) 1127 #define G_DDP_DACK_MODE(x) (((x) >> S_DDP_DACK_MODE) & M_DDP_DACK_MODE) 1128 1129 #define S_DDP_URG 24 1130 #define V_DDP_URG(x) ((x) << S_DDP_URG) 1131 #define F_DDP_URG V_DDP_URG(1U) 1132 1133 #define S_DDP_PSH 25 1134 #define V_DDP_PSH(x) ((x) << S_DDP_PSH) 1135 #define F_DDP_PSH V_DDP_PSH(1U) 1136 1137 #define S_DDP_BUF_COMPLETE 26 1138 #define V_DDP_BUF_COMPLETE(x) ((x) << S_DDP_BUF_COMPLETE) 1139 #define F_DDP_BUF_COMPLETE V_DDP_BUF_COMPLETE(1U) 1140 1141 #define S_DDP_BUF_TIMED_OUT 27 1142 #define V_DDP_BUF_TIMED_OUT(x) ((x) << S_DDP_BUF_TIMED_OUT) 1143 #define F_DDP_BUF_TIMED_OUT V_DDP_BUF_TIMED_OUT(1U) 1144 1145 #define S_DDP_BUF_IDX 28 1146 #define V_DDP_BUF_IDX(x) ((x) << S_DDP_BUF_IDX) 1147 #define F_DDP_BUF_IDX V_DDP_BUF_IDX(1U) 1148 1149 struct cpl_tx_pkt { 1150 WR_HDR; 1151 __be32 cntrl; 1152 __be32 len; 1153 }; 1154 1155 struct cpl_tx_pkt_coalesce { 1156 __be32 cntrl; 1157 __be32 len; 1158 __be64 addr; 1159 }; 1160 1161 struct tx_pkt_coalesce_wr { 1162 WR_HDR; 1163 struct cpl_tx_pkt_coalesce cpl[0]; 1164 }; 1165 1166 struct cpl_tx_pkt_lso { 1167 WR_HDR; 1168 __be32 cntrl; 1169 __be32 len; 1170 1171 __be32 rsvd; 1172 __be32 lso_info; 1173 }; 1174 1175 struct cpl_tx_pkt_batch_entry { 1176 __be32 cntrl; 1177 __be32 len; 1178 __be64 addr; 1179 }; 1180 1181 struct cpl_tx_pkt_batch { 1182 WR_HDR; 1183 struct cpl_tx_pkt_batch_entry pkt_entry[7]; 1184 }; 1185 1186 1187 /* cpl_tx_pkt*.cntrl fields */ 1188 #define S_TXPKT_VLAN 0 1189 #define M_TXPKT_VLAN 0xFFFF 1190 #define V_TXPKT_VLAN(x) ((x) << S_TXPKT_VLAN) 1191 #define G_TXPKT_VLAN(x) (((x) >> S_TXPKT_VLAN) & M_TXPKT_VLAN) 1192 1193 #define S_TXPKT_INTF 16 1194 #define M_TXPKT_INTF 0xF 1195 #define V_TXPKT_INTF(x) ((x) << S_TXPKT_INTF) 1196 #define G_TXPKT_INTF(x) (((x) >> S_TXPKT_INTF) & M_TXPKT_INTF) 1197 1198 #define S_TXPKT_IPCSUM_DIS 20 1199 #define V_TXPKT_IPCSUM_DIS(x) ((x) << S_TXPKT_IPCSUM_DIS) 1200 #define F_TXPKT_IPCSUM_DIS V_TXPKT_IPCSUM_DIS(1U) 1201 1202 #define S_TXPKT_L4CSUM_DIS 21 1203 #define V_TXPKT_L4CSUM_DIS(x) ((x) << S_TXPKT_L4CSUM_DIS) 1204 #define F_TXPKT_L4CSUM_DIS V_TXPKT_L4CSUM_DIS(1U) 1205 1206 #define S_TXPKT_VLAN_VLD 22 1207 #define V_TXPKT_VLAN_VLD(x) ((x) << S_TXPKT_VLAN_VLD) 1208 #define F_TXPKT_VLAN_VLD V_TXPKT_VLAN_VLD(1U) 1209 1210 #define S_TXPKT_LOOPBACK 23 1211 #define V_TXPKT_LOOPBACK(x) ((x) << S_TXPKT_LOOPBACK) 1212 #define F_TXPKT_LOOPBACK V_TXPKT_LOOPBACK(1U) 1213 1214 #define S_TXPKT_OPCODE 24 1215 #define M_TXPKT_OPCODE 0xFF 1216 #define V_TXPKT_OPCODE(x) ((x) << S_TXPKT_OPCODE) 1217 #define G_TXPKT_OPCODE(x) (((x) >> S_TXPKT_OPCODE) & M_TXPKT_OPCODE) 1218 1219 /* cpl_tx_pkt_lso.lso_info fields */ 1220 #define S_LSO_MSS 0 1221 #define M_LSO_MSS 0x3FFF 1222 #define V_LSO_MSS(x) ((x) << S_LSO_MSS) 1223 #define G_LSO_MSS(x) (((x) >> S_LSO_MSS) & M_LSO_MSS) 1224 1225 #define S_LSO_ETH_TYPE 14 1226 #define M_LSO_ETH_TYPE 0x3 1227 #define V_LSO_ETH_TYPE(x) ((x) << S_LSO_ETH_TYPE) 1228 #define G_LSO_ETH_TYPE(x) (((x) >> S_LSO_ETH_TYPE) & M_LSO_ETH_TYPE) 1229 1230 #define S_LSO_TCPHDR_WORDS 16 1231 #define M_LSO_TCPHDR_WORDS 0xF 1232 #define V_LSO_TCPHDR_WORDS(x) ((x) << S_LSO_TCPHDR_WORDS) 1233 #define G_LSO_TCPHDR_WORDS(x) (((x) >> S_LSO_TCPHDR_WORDS) & M_LSO_TCPHDR_WORDS) 1234 1235 #define S_LSO_IPHDR_WORDS 20 1236 #define M_LSO_IPHDR_WORDS 0xF 1237 #define V_LSO_IPHDR_WORDS(x) ((x) << S_LSO_IPHDR_WORDS) 1238 #define G_LSO_IPHDR_WORDS(x) (((x) >> S_LSO_IPHDR_WORDS) & M_LSO_IPHDR_WORDS) 1239 1240 #define S_LSO_IPV6 24 1241 #define V_LSO_IPV6(x) ((x) << S_LSO_IPV6) 1242 #define F_LSO_IPV6 V_LSO_IPV6(1U) 1243 1244 struct cpl_trace_pkt { 1245 #ifdef CHELSIO_FW 1246 __u8 rss_opcode; 1247 #if defined(__LITTLE_ENDIAN_BITFIELD) 1248 __u8 err:1; 1249 __u8 :7; 1250 #else 1251 __u8 :7; 1252 __u8 err:1; 1253 #endif 1254 __u8 rsvd0; 1255 #if defined(__LITTLE_ENDIAN_BITFIELD) 1256 __u8 qid:4; 1257 __u8 :4; 1258 #else 1259 __u8 :4; 1260 __u8 qid:4; 1261 #endif 1262 __be32 tstamp; 1263 #endif /* CHELSIO_FW */ 1264 1265 __u8 opcode; 1266 #if defined(__LITTLE_ENDIAN_BITFIELD) 1267 __u8 iff:4; 1268 __u8 :4; 1269 #else 1270 __u8 :4; 1271 __u8 iff:4; 1272 #endif 1273 __u8 rsvd[4]; 1274 __be16 len; 1275 }; 1276 1277 struct cpl_rx_pkt { 1278 RSS_HDR 1279 __u8 opcode; 1280 #if defined(__LITTLE_ENDIAN_BITFIELD) 1281 __u8 iff:4; 1282 __u8 csum_valid:1; 1283 __u8 ipmi_pkt:1; 1284 __u8 vlan_valid:1; 1285 __u8 fragment:1; 1286 #else 1287 __u8 fragment:1; 1288 __u8 vlan_valid:1; 1289 __u8 ipmi_pkt:1; 1290 __u8 csum_valid:1; 1291 __u8 iff:4; 1292 #endif 1293 __be16 csum; 1294 __be16 vlan; 1295 __be16 len; 1296 }; 1297 1298 struct cpl_l2t_write_req { 1299 WR_HDR; 1300 union opcode_tid ot; 1301 __be32 params; 1302 __u8 rsvd; 1303 __u8 port_idx; 1304 __u8 dst_mac[6]; 1305 }; 1306 1307 /* cpl_l2t_write_req.params fields */ 1308 #define S_L2T_W_IDX 0 1309 #define M_L2T_W_IDX 0x7FF 1310 #define V_L2T_W_IDX(x) ((x) << S_L2T_W_IDX) 1311 #define G_L2T_W_IDX(x) (((x) >> S_L2T_W_IDX) & M_L2T_W_IDX) 1312 1313 #define S_L2T_W_VLAN 11 1314 #define M_L2T_W_VLAN 0xFFF 1315 #define V_L2T_W_VLAN(x) ((x) << S_L2T_W_VLAN) 1316 #define G_L2T_W_VLAN(x) (((x) >> S_L2T_W_VLAN) & M_L2T_W_VLAN) 1317 1318 #define S_L2T_W_IFF 23 1319 #define M_L2T_W_IFF 0xF 1320 #define V_L2T_W_IFF(x) ((x) << S_L2T_W_IFF) 1321 #define G_L2T_W_IFF(x) (((x) >> S_L2T_W_IFF) & M_L2T_W_IFF) 1322 1323 #define S_L2T_W_PRIO 27 1324 #define M_L2T_W_PRIO 0x7 1325 #define V_L2T_W_PRIO(x) ((x) << S_L2T_W_PRIO) 1326 #define G_L2T_W_PRIO(x) (((x) >> S_L2T_W_PRIO) & M_L2T_W_PRIO) 1327 1328 struct cpl_l2t_write_rpl { 1329 RSS_HDR 1330 union opcode_tid ot; 1331 __u8 status; 1332 __u8 rsvd[3]; 1333 }; 1334 1335 struct cpl_l2t_read_req { 1336 WR_HDR; 1337 union opcode_tid ot; 1338 __be16 rsvd; 1339 __be16 l2t_idx; 1340 }; 1341 1342 struct cpl_l2t_read_rpl { 1343 RSS_HDR 1344 union opcode_tid ot; 1345 __be32 params; 1346 __u8 rsvd[2]; 1347 __u8 dst_mac[6]; 1348 }; 1349 1350 /* cpl_l2t_read_rpl.params fields */ 1351 #define S_L2T_R_PRIO 0 1352 #define M_L2T_R_PRIO 0x7 1353 #define V_L2T_R_PRIO(x) ((x) << S_L2T_R_PRIO) 1354 #define G_L2T_R_PRIO(x) (((x) >> S_L2T_R_PRIO) & M_L2T_R_PRIO) 1355 1356 #define S_L2T_R_VLAN 8 1357 #define M_L2T_R_VLAN 0xFFF 1358 #define V_L2T_R_VLAN(x) ((x) << S_L2T_R_VLAN) 1359 #define G_L2T_R_VLAN(x) (((x) >> S_L2T_R_VLAN) & M_L2T_R_VLAN) 1360 1361 #define S_L2T_R_IFF 20 1362 #define M_L2T_R_IFF 0xF 1363 #define V_L2T_R_IFF(x) ((x) << S_L2T_R_IFF) 1364 #define G_L2T_R_IFF(x) (((x) >> S_L2T_R_IFF) & M_L2T_R_IFF) 1365 1366 #define S_L2T_STATUS 24 1367 #define M_L2T_STATUS 0xFF 1368 #define V_L2T_STATUS(x) ((x) << S_L2T_STATUS) 1369 #define G_L2T_STATUS(x) (((x) >> S_L2T_STATUS) & M_L2T_STATUS) 1370 1371 struct cpl_smt_write_req { 1372 WR_HDR; 1373 union opcode_tid ot; 1374 __u8 rsvd0; 1375 #if defined(__LITTLE_ENDIAN_BITFIELD) 1376 __u8 mtu_idx:4; 1377 __u8 iff:4; 1378 #else 1379 __u8 iff:4; 1380 __u8 mtu_idx:4; 1381 #endif 1382 __be16 rsvd2; 1383 __be16 rsvd3; 1384 __u8 src_mac1[6]; 1385 __be16 rsvd4; 1386 __u8 src_mac0[6]; 1387 }; 1388 1389 struct cpl_smt_write_rpl { 1390 RSS_HDR 1391 union opcode_tid ot; 1392 __u8 status; 1393 __u8 rsvd[3]; 1394 }; 1395 1396 struct cpl_smt_read_req { 1397 WR_HDR; 1398 union opcode_tid ot; 1399 __u8 rsvd0; 1400 #if defined(__LITTLE_ENDIAN_BITFIELD) 1401 __u8 :4; 1402 __u8 iff:4; 1403 #else 1404 __u8 iff:4; 1405 __u8 :4; 1406 #endif 1407 __be16 rsvd2; 1408 }; 1409 1410 struct cpl_smt_read_rpl { 1411 RSS_HDR 1412 union opcode_tid ot; 1413 __u8 status; 1414 #if defined(__LITTLE_ENDIAN_BITFIELD) 1415 __u8 mtu_idx:4; 1416 __u8 :4; 1417 #else 1418 __u8 :4; 1419 __u8 mtu_idx:4; 1420 #endif 1421 __be16 rsvd2; 1422 __be16 rsvd3; 1423 __u8 src_mac1[6]; 1424 __be16 rsvd4; 1425 __u8 src_mac0[6]; 1426 }; 1427 1428 struct cpl_rte_delete_req { 1429 WR_HDR; 1430 union opcode_tid ot; 1431 __be32 params; 1432 }; 1433 1434 /* { cpl_rte_delete_req, cpl_rte_read_req }.params fields */ 1435 #define S_RTE_REQ_LUT_IX 8 1436 #define M_RTE_REQ_LUT_IX 0x7FF 1437 #define V_RTE_REQ_LUT_IX(x) ((x) << S_RTE_REQ_LUT_IX) 1438 #define G_RTE_REQ_LUT_IX(x) (((x) >> S_RTE_REQ_LUT_IX) & M_RTE_REQ_LUT_IX) 1439 1440 #define S_RTE_REQ_LUT_BASE 19 1441 #define M_RTE_REQ_LUT_BASE 0x7FF 1442 #define V_RTE_REQ_LUT_BASE(x) ((x) << S_RTE_REQ_LUT_BASE) 1443 #define G_RTE_REQ_LUT_BASE(x) (((x) >> S_RTE_REQ_LUT_BASE) & M_RTE_REQ_LUT_BASE) 1444 1445 #define S_RTE_READ_REQ_SELECT 31 1446 #define V_RTE_READ_REQ_SELECT(x) ((x) << S_RTE_READ_REQ_SELECT) 1447 #define F_RTE_READ_REQ_SELECT V_RTE_READ_REQ_SELECT(1U) 1448 1449 struct cpl_rte_delete_rpl { 1450 RSS_HDR 1451 union opcode_tid ot; 1452 __u8 status; 1453 __u8 rsvd[3]; 1454 }; 1455 1456 struct cpl_rte_write_req { 1457 WR_HDR; 1458 union opcode_tid ot; 1459 #if defined(__LITTLE_ENDIAN_BITFIELD) 1460 __u8 :6; 1461 __u8 write_tcam:1; 1462 __u8 write_l2t_lut:1; 1463 #else 1464 __u8 write_l2t_lut:1; 1465 __u8 write_tcam:1; 1466 __u8 :6; 1467 #endif 1468 __u8 rsvd[3]; 1469 __be32 lut_params; 1470 __be16 rsvd2; 1471 __be16 l2t_idx; 1472 __be32 netmask; 1473 __be32 faddr; 1474 }; 1475 1476 /* cpl_rte_write_req.lut_params fields */ 1477 #define S_RTE_WRITE_REQ_LUT_IX 10 1478 #define M_RTE_WRITE_REQ_LUT_IX 0x7FF 1479 #define V_RTE_WRITE_REQ_LUT_IX(x) ((x) << S_RTE_WRITE_REQ_LUT_IX) 1480 #define G_RTE_WRITE_REQ_LUT_IX(x) (((x) >> S_RTE_WRITE_REQ_LUT_IX) & M_RTE_WRITE_REQ_LUT_IX) 1481 1482 #define S_RTE_WRITE_REQ_LUT_BASE 21 1483 #define M_RTE_WRITE_REQ_LUT_BASE 0x7FF 1484 #define V_RTE_WRITE_REQ_LUT_BASE(x) ((x) << S_RTE_WRITE_REQ_LUT_BASE) 1485 #define G_RTE_WRITE_REQ_LUT_BASE(x) (((x) >> S_RTE_WRITE_REQ_LUT_BASE) & M_RTE_WRITE_REQ_LUT_BASE) 1486 1487 struct cpl_rte_write_rpl { 1488 RSS_HDR 1489 union opcode_tid ot; 1490 __u8 status; 1491 __u8 rsvd[3]; 1492 }; 1493 1494 struct cpl_rte_read_req { 1495 WR_HDR; 1496 union opcode_tid ot; 1497 __be32 params; 1498 }; 1499 1500 struct cpl_rte_read_rpl { 1501 RSS_HDR 1502 union opcode_tid ot; 1503 __u8 status; 1504 __u8 rsvd0; 1505 __be16 l2t_idx; 1506 #if defined(__LITTLE_ENDIAN_BITFIELD) 1507 __u8 :7; 1508 __u8 select:1; 1509 #else 1510 __u8 select:1; 1511 __u8 :7; 1512 #endif 1513 __u8 rsvd2[3]; 1514 __be32 addr; 1515 }; 1516 1517 struct cpl_tid_release { 1518 WR_HDR; 1519 union opcode_tid ot; 1520 __be32 rsvd; 1521 }; 1522 1523 struct cpl_barrier { 1524 WR_HDR; 1525 __u8 opcode; 1526 __u8 rsvd[7]; 1527 }; 1528 1529 struct cpl_rdma_read_req { 1530 __u8 opcode; 1531 __u8 rsvd[15]; 1532 }; 1533 1534 struct cpl_rdma_terminate { 1535 #ifdef CHELSIO_FW 1536 __u8 opcode; 1537 __u8 rsvd[2]; 1538 #if defined(__LITTLE_ENDIAN_BITFIELD) 1539 __u8 rspq:3; 1540 __u8 :5; 1541 #else 1542 __u8 :5; 1543 __u8 rspq:3; 1544 #endif 1545 __be32 tid_len; 1546 #endif 1547 __be32 msn; 1548 __be32 mo; 1549 __u8 data[0]; 1550 }; 1551 1552 /* cpl_rdma_terminate.tid_len fields */ 1553 #define S_FLIT_CNT 0 1554 #define M_FLIT_CNT 0xFF 1555 #define V_FLIT_CNT(x) ((x) << S_FLIT_CNT) 1556 #define G_FLIT_CNT(x) (((x) >> S_FLIT_CNT) & M_FLIT_CNT) 1557 1558 #define S_TERM_TID 8 1559 #define M_TERM_TID 0xFFFFF 1560 #define V_TERM_TID(x) ((x) << S_TERM_TID) 1561 #define G_TERM_TID(x) (((x) >> S_TERM_TID) & M_TERM_TID) 1562 1563 /* ULP_TX opcodes */ 1564 enum { ULP_MEM_READ = 2, ULP_MEM_WRITE = 3, ULP_TXPKT = 4 }; 1565 1566 #define S_ULPTX_CMD 28 1567 #define M_ULPTX_CMD 0xF 1568 #define V_ULPTX_CMD(x) ((x) << S_ULPTX_CMD) 1569 1570 #define S_ULPTX_NFLITS 0 1571 #define M_ULPTX_NFLITS 0xFF 1572 #define V_ULPTX_NFLITS(x) ((x) << S_ULPTX_NFLITS) 1573 1574 struct ulp_mem_io { 1575 WR_HDR; 1576 __be32 cmd_lock_addr; 1577 __be32 len; 1578 }; 1579 1580 /* ulp_mem_io.cmd_lock_addr fields */ 1581 #define S_ULP_MEMIO_ADDR 0 1582 #define M_ULP_MEMIO_ADDR 0x7FFFFFF 1583 #define V_ULP_MEMIO_ADDR(x) ((x) << S_ULP_MEMIO_ADDR) 1584 1585 #define S_ULP_MEMIO_LOCK 27 1586 #define V_ULP_MEMIO_LOCK(x) ((x) << S_ULP_MEMIO_LOCK) 1587 #define F_ULP_MEMIO_LOCK V_ULP_MEMIO_LOCK(1U) 1588 1589 /* ulp_mem_io.len fields */ 1590 #define S_ULP_MEMIO_DATA_LEN 28 1591 #define M_ULP_MEMIO_DATA_LEN 0xF 1592 #define V_ULP_MEMIO_DATA_LEN(x) ((x) << S_ULP_MEMIO_DATA_LEN) 1593 1594 struct ulp_txpkt { 1595 __be32 cmd_dest; 1596 __be32 len; 1597 }; 1598 1599 /* ulp_txpkt.cmd_dest fields */ 1600 #define S_ULP_TXPKT_DEST 24 1601 #define M_ULP_TXPKT_DEST 0xF 1602 #define V_ULP_TXPKT_DEST(x) ((x) << S_ULP_TXPKT_DEST) 1603 1604 #endif /* T3_CPL_H */ 1605