1 /************************************************************************** 2 3 Copyright (c) 2007, Chelsio Inc. 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Neither the name of the Chelsio Corporation nor the names of its 13 contributors may be used to endorse or promote products derived from 14 this software without specific prior written permission. 15 16 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 20 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 POSSIBILITY OF SUCH DAMAGE. 27 28 $FreeBSD$ 29 30 ***************************************************************************/ 31 #ifndef T3_CPL_H 32 #define T3_CPL_H 33 34 enum CPL_opcode { 35 CPL_PASS_OPEN_REQ = 0x1, 36 CPL_PASS_ACCEPT_RPL = 0x2, 37 CPL_ACT_OPEN_REQ = 0x3, 38 CPL_SET_TCB = 0x4, 39 CPL_SET_TCB_FIELD = 0x5, 40 CPL_GET_TCB = 0x6, 41 CPL_PCMD = 0x7, 42 CPL_CLOSE_CON_REQ = 0x8, 43 CPL_CLOSE_LISTSRV_REQ = 0x9, 44 CPL_ABORT_REQ = 0xA, 45 CPL_ABORT_RPL = 0xB, 46 CPL_TX_DATA = 0xC, 47 CPL_RX_DATA_ACK = 0xD, 48 CPL_TX_PKT = 0xE, 49 CPL_RTE_DELETE_REQ = 0xF, 50 CPL_RTE_WRITE_REQ = 0x10, 51 CPL_RTE_READ_REQ = 0x11, 52 CPL_L2T_WRITE_REQ = 0x12, 53 CPL_L2T_READ_REQ = 0x13, 54 CPL_SMT_WRITE_REQ = 0x14, 55 CPL_SMT_READ_REQ = 0x15, 56 CPL_TX_PKT_LSO = 0x16, 57 CPL_PCMD_READ = 0x17, 58 CPL_BARRIER = 0x18, 59 CPL_TID_RELEASE = 0x1A, 60 61 CPL_CLOSE_LISTSRV_RPL = 0x20, 62 CPL_ERROR = 0x21, 63 CPL_GET_TCB_RPL = 0x22, 64 CPL_L2T_WRITE_RPL = 0x23, 65 CPL_PCMD_READ_RPL = 0x24, 66 CPL_PCMD_RPL = 0x25, 67 CPL_PEER_CLOSE = 0x26, 68 CPL_RTE_DELETE_RPL = 0x27, 69 CPL_RTE_WRITE_RPL = 0x28, 70 CPL_RX_DDP_COMPLETE = 0x29, 71 CPL_RX_PHYS_ADDR = 0x2A, 72 CPL_RX_PKT = 0x2B, 73 CPL_RX_URG_NOTIFY = 0x2C, 74 CPL_SET_TCB_RPL = 0x2D, 75 CPL_SMT_WRITE_RPL = 0x2E, 76 CPL_TX_DATA_ACK = 0x2F, 77 78 CPL_ABORT_REQ_RSS = 0x30, 79 CPL_ABORT_RPL_RSS = 0x31, 80 CPL_CLOSE_CON_RPL = 0x32, 81 CPL_ISCSI_HDR = 0x33, 82 CPL_L2T_READ_RPL = 0x34, 83 CPL_RDMA_CQE = 0x35, 84 CPL_RDMA_CQE_READ_RSP = 0x36, 85 CPL_RDMA_CQE_ERR = 0x37, 86 CPL_RTE_READ_RPL = 0x38, 87 CPL_RX_DATA = 0x39, 88 89 CPL_ACT_OPEN_RPL = 0x40, 90 CPL_PASS_OPEN_RPL = 0x41, 91 CPL_RX_DATA_DDP = 0x42, 92 CPL_SMT_READ_RPL = 0x43, 93 94 CPL_ACT_ESTABLISH = 0x50, 95 CPL_PASS_ESTABLISH = 0x51, 96 97 CPL_PASS_ACCEPT_REQ = 0x70, 98 99 CPL_ASYNC_NOTIF = 0x80, /* fake opcode for async notifications */ 100 101 CPL_TX_DMA_ACK = 0xA0, 102 CPL_RDMA_READ_REQ = 0xA1, 103 CPL_RDMA_TERMINATE = 0xA2, 104 CPL_TRACE_PKT = 0xA3, 105 CPL_RDMA_EC_STATUS = 0xA5, 106 107 NUM_CPL_CMDS /* must be last and previous entries must be sorted */ 108 }; 109 110 enum CPL_error { 111 CPL_ERR_NONE = 0, 112 CPL_ERR_TCAM_PARITY = 1, 113 CPL_ERR_TCAM_FULL = 3, 114 CPL_ERR_CONN_RESET = 20, 115 CPL_ERR_CONN_EXIST = 22, 116 CPL_ERR_ARP_MISS = 23, 117 CPL_ERR_BAD_SYN = 24, 118 CPL_ERR_CONN_TIMEDOUT = 30, 119 CPL_ERR_XMIT_TIMEDOUT = 31, 120 CPL_ERR_PERSIST_TIMEDOUT = 32, 121 CPL_ERR_FINWAIT2_TIMEDOUT = 33, 122 CPL_ERR_KEEPALIVE_TIMEDOUT = 34, 123 CPL_ERR_RTX_NEG_ADVICE = 35, 124 CPL_ERR_PERSIST_NEG_ADVICE = 36, 125 CPL_ERR_ABORT_FAILED = 42, 126 CPL_ERR_GENERAL = 99 127 }; 128 129 enum { 130 CPL_CONN_POLICY_AUTO = 0, 131 CPL_CONN_POLICY_ASK = 1, 132 CPL_CONN_POLICY_FILTER = 2, 133 CPL_CONN_POLICY_DENY = 3 134 }; 135 136 enum { 137 ULP_MODE_NONE = 0, 138 ULP_MODE_TCP_DDP = 1, 139 ULP_MODE_ISCSI = 2, 140 ULP_MODE_RDMA = 4, 141 ULP_MODE_TCPDDP = 5 142 }; 143 144 enum { 145 ULP_CRC_HEADER = 1 << 0, 146 ULP_CRC_DATA = 1 << 1 147 }; 148 149 enum { 150 CPL_PASS_OPEN_ACCEPT, 151 CPL_PASS_OPEN_REJECT 152 }; 153 154 enum { 155 CPL_ABORT_SEND_RST = 0, 156 CPL_ABORT_NO_RST, 157 CPL_ABORT_POST_CLOSE_REQ = 2 158 }; 159 160 enum { /* TX_PKT_LSO ethernet types */ 161 CPL_ETH_II, 162 CPL_ETH_II_VLAN, 163 CPL_ETH_802_3, 164 CPL_ETH_802_3_VLAN 165 }; 166 167 enum { /* TCP congestion control algorithms */ 168 CONG_ALG_RENO, 169 CONG_ALG_TAHOE, 170 CONG_ALG_NEWRENO, 171 CONG_ALG_HIGHSPEED 172 }; 173 174 enum { /* RSS hash type */ 175 RSS_HASH_NONE = 0, 176 RSS_HASH_2_TUPLE = 1 << 0, 177 RSS_HASH_4_TUPLE = 1 << 1 178 }; 179 180 union opcode_tid { 181 __be32 opcode_tid; 182 __u8 opcode; 183 }; 184 185 #define S_OPCODE 24 186 #define V_OPCODE(x) ((x) << S_OPCODE) 187 #define G_OPCODE(x) (((x) >> S_OPCODE) & 0xFF) 188 #define G_TID(x) ((x) & 0xFFFFFF) 189 190 #define S_HASHTYPE 22 191 #define M_HASHTYPE 0x3 192 #define G_HASHTYPE(x) (((x) >> S_HASHTYPE) & M_HASHTYPE) 193 194 #define S_QNUM 0 195 #define G_QNUM(x) (((x) >> S_QNUM) & 0xFFFF) 196 197 /* tid is assumed to be 24-bits */ 198 #define MK_OPCODE_TID(opcode, tid) (V_OPCODE(opcode) | (tid)) 199 200 #define OPCODE_TID(cmd) ((cmd)->ot.opcode_tid) 201 202 /* extract the TID from a CPL command */ 203 #define GET_TID(cmd) (G_TID(ntohl(OPCODE_TID(cmd)))) 204 205 struct tcp_options { 206 __be16 mss; 207 __u8 wsf; 208 #if defined(__LITTLE_ENDIAN_BITFIELD) 209 __u8 :5; 210 __u8 ecn:1; 211 __u8 sack:1; 212 __u8 tstamp:1; 213 #else 214 __u8 tstamp:1; 215 __u8 sack:1; 216 __u8 ecn:1; 217 __u8 :5; 218 #endif 219 }; 220 221 struct rss_header { 222 __u8 opcode; 223 #if defined(__LITTLE_ENDIAN_BITFIELD) 224 __u8 cpu_idx:6; 225 __u8 hash_type:2; 226 #else 227 __u8 hash_type:2; 228 __u8 cpu_idx:6; 229 #endif 230 __be16 cq_idx; 231 __be32 rss_hash_val; 232 }; 233 234 #ifndef CHELSIO_FW 235 struct work_request_hdr { 236 __be32 wr_hi; 237 __be32 wr_lo; 238 }; 239 240 /* wr_hi fields */ 241 #define S_WR_SGE_CREDITS 0 242 #define M_WR_SGE_CREDITS 0xFF 243 #define V_WR_SGE_CREDITS(x) ((x) << S_WR_SGE_CREDITS) 244 #define G_WR_SGE_CREDITS(x) (((x) >> S_WR_SGE_CREDITS) & M_WR_SGE_CREDITS) 245 246 #define S_WR_SGLSFLT 8 247 #define M_WR_SGLSFLT 0xFF 248 #define V_WR_SGLSFLT(x) ((x) << S_WR_SGLSFLT) 249 #define G_WR_SGLSFLT(x) (((x) >> S_WR_SGLSFLT) & M_WR_SGLSFLT) 250 251 #define S_WR_BCNTLFLT 16 252 #define M_WR_BCNTLFLT 0xF 253 #define V_WR_BCNTLFLT(x) ((x) << S_WR_BCNTLFLT) 254 #define G_WR_BCNTLFLT(x) (((x) >> S_WR_BCNTLFLT) & M_WR_BCNTLFLT) 255 256 /* Applicable to BYPASS WRs only: the uP will added a CPL_BARRIER before 257 * and after the BYPASS WR if the ATOMIC bit is set. 258 */ 259 #define S_WR_ATOMIC 16 260 #define V_WR_ATOMIC(x) ((x) << S_WR_ATOMIC) 261 #define F_WR_ATOMIC V_WR_ATOMIC(1U) 262 263 /* Applicable to BYPASS WRs only: the uP will flush buffered non abort 264 * related WRs. 265 */ 266 #define S_WR_FLUSH 17 267 #define V_WR_FLUSH(x) ((x) << S_WR_FLUSH) 268 #define F_WR_FLUSH V_WR_FLUSH(1U) 269 270 #define S_WR_DATATYPE 20 271 #define V_WR_DATATYPE(x) ((x) << S_WR_DATATYPE) 272 #define F_WR_DATATYPE V_WR_DATATYPE(1U) 273 274 #define S_WR_COMPL 21 275 #define V_WR_COMPL(x) ((x) << S_WR_COMPL) 276 #define F_WR_COMPL V_WR_COMPL(1U) 277 278 #define S_WR_EOP 22 279 #define V_WR_EOP(x) ((x) << S_WR_EOP) 280 #define F_WR_EOP V_WR_EOP(1U) 281 282 #define S_WR_SOP 23 283 #define V_WR_SOP(x) ((x) << S_WR_SOP) 284 #define F_WR_SOP V_WR_SOP(1U) 285 286 #define S_WR_OP 24 287 #define M_WR_OP 0xFF 288 #define V_WR_OP(x) ((x) << S_WR_OP) 289 #define G_WR_OP(x) (((x) >> S_WR_OP) & M_WR_OP) 290 291 /* wr_lo fields */ 292 #define S_WR_LEN 0 293 #define M_WR_LEN 0xFF 294 #define V_WR_LEN(x) ((x) << S_WR_LEN) 295 #define G_WR_LEN(x) (((x) >> S_WR_LEN) & M_WR_LEN) 296 297 #define S_WR_TID 8 298 #define M_WR_TID 0xFFFFF 299 #define V_WR_TID(x) ((x) << S_WR_TID) 300 #define G_WR_TID(x) (((x) >> S_WR_TID) & M_WR_TID) 301 302 #define S_WR_CR_FLUSH 30 303 #define V_WR_CR_FLUSH(x) ((x) << S_WR_CR_FLUSH) 304 #define F_WR_CR_FLUSH V_WR_CR_FLUSH(1U) 305 306 #define S_WR_GEN 31 307 #define V_WR_GEN(x) ((x) << S_WR_GEN) 308 #define F_WR_GEN V_WR_GEN(1U) 309 #define G_WR_GEN(x) ((x) >> S_WR_GEN) 310 311 # define WR_HDR struct work_request_hdr wr 312 # define RSS_HDR 313 #else 314 # define WR_HDR 315 # define RSS_HDR struct rss_header rss_hdr; 316 #endif 317 318 /* option 0 lower-half fields */ 319 #define S_CPL_STATUS 0 320 #define M_CPL_STATUS 0xFF 321 #define V_CPL_STATUS(x) ((x) << S_CPL_STATUS) 322 #define G_CPL_STATUS(x) (((x) >> S_CPL_STATUS) & M_CPL_STATUS) 323 324 #define S_INJECT_TIMER 6 325 #define V_INJECT_TIMER(x) ((x) << S_INJECT_TIMER) 326 #define F_INJECT_TIMER V_INJECT_TIMER(1U) 327 328 #define S_NO_OFFLOAD 7 329 #define V_NO_OFFLOAD(x) ((x) << S_NO_OFFLOAD) 330 #define F_NO_OFFLOAD V_NO_OFFLOAD(1U) 331 332 #define S_ULP_MODE 8 333 #define M_ULP_MODE 0xF 334 #define V_ULP_MODE(x) ((x) << S_ULP_MODE) 335 #define G_ULP_MODE(x) (((x) >> S_ULP_MODE) & M_ULP_MODE) 336 337 #define S_RCV_BUFSIZ 12 338 #define M_RCV_BUFSIZ 0x3FFF 339 #define V_RCV_BUFSIZ(x) ((x) << S_RCV_BUFSIZ) 340 #define G_RCV_BUFSIZ(x) (((x) >> S_RCV_BUFSIZ) & M_RCV_BUFSIZ) 341 342 #define S_TOS 26 343 #define M_TOS 0x3F 344 #define V_TOS(x) ((x) << S_TOS) 345 #define G_TOS(x) (((x) >> S_TOS) & M_TOS) 346 347 /* option 0 upper-half fields */ 348 #define S_DELACK 0 349 #define V_DELACK(x) ((x) << S_DELACK) 350 #define F_DELACK V_DELACK(1U) 351 352 #define S_NO_CONG 1 353 #define V_NO_CONG(x) ((x) << S_NO_CONG) 354 #define F_NO_CONG V_NO_CONG(1U) 355 356 #define S_SRC_MAC_SEL 2 357 #define M_SRC_MAC_SEL 0x3 358 #define V_SRC_MAC_SEL(x) ((x) << S_SRC_MAC_SEL) 359 #define G_SRC_MAC_SEL(x) (((x) >> S_SRC_MAC_SEL) & M_SRC_MAC_SEL) 360 361 #define S_L2T_IDX 4 362 #define M_L2T_IDX 0x7FF 363 #define V_L2T_IDX(x) ((x) << S_L2T_IDX) 364 #define G_L2T_IDX(x) (((x) >> S_L2T_IDX) & M_L2T_IDX) 365 366 #define S_TX_CHANNEL 15 367 #define V_TX_CHANNEL(x) ((x) << S_TX_CHANNEL) 368 #define F_TX_CHANNEL V_TX_CHANNEL(1U) 369 370 #define S_TCAM_BYPASS 16 371 #define V_TCAM_BYPASS(x) ((x) << S_TCAM_BYPASS) 372 #define F_TCAM_BYPASS V_TCAM_BYPASS(1U) 373 374 #define S_NAGLE 17 375 #define V_NAGLE(x) ((x) << S_NAGLE) 376 #define F_NAGLE V_NAGLE(1U) 377 378 #define S_WND_SCALE 18 379 #define M_WND_SCALE 0xF 380 #define V_WND_SCALE(x) ((x) << S_WND_SCALE) 381 #define G_WND_SCALE(x) (((x) >> S_WND_SCALE) & M_WND_SCALE) 382 383 #define S_KEEP_ALIVE 22 384 #define V_KEEP_ALIVE(x) ((x) << S_KEEP_ALIVE) 385 #define F_KEEP_ALIVE V_KEEP_ALIVE(1U) 386 387 #define S_MAX_RETRANS 23 388 #define M_MAX_RETRANS 0xF 389 #define V_MAX_RETRANS(x) ((x) << S_MAX_RETRANS) 390 #define G_MAX_RETRANS(x) (((x) >> S_MAX_RETRANS) & M_MAX_RETRANS) 391 392 #define S_MAX_RETRANS_OVERRIDE 27 393 #define V_MAX_RETRANS_OVERRIDE(x) ((x) << S_MAX_RETRANS_OVERRIDE) 394 #define F_MAX_RETRANS_OVERRIDE V_MAX_RETRANS_OVERRIDE(1U) 395 396 #define S_MSS_IDX 28 397 #define M_MSS_IDX 0xF 398 #define V_MSS_IDX(x) ((x) << S_MSS_IDX) 399 #define G_MSS_IDX(x) (((x) >> S_MSS_IDX) & M_MSS_IDX) 400 401 /* option 1 fields */ 402 #define S_RSS_ENABLE 0 403 #define V_RSS_ENABLE(x) ((x) << S_RSS_ENABLE) 404 #define F_RSS_ENABLE V_RSS_ENABLE(1U) 405 406 #define S_RSS_MASK_LEN 1 407 #define M_RSS_MASK_LEN 0x7 408 #define V_RSS_MASK_LEN(x) ((x) << S_RSS_MASK_LEN) 409 #define G_RSS_MASK_LEN(x) (((x) >> S_RSS_MASK_LEN) & M_RSS_MASK_LEN) 410 411 #define S_CPU_IDX 4 412 #define M_CPU_IDX 0x3F 413 #define V_CPU_IDX(x) ((x) << S_CPU_IDX) 414 #define G_CPU_IDX(x) (((x) >> S_CPU_IDX) & M_CPU_IDX) 415 416 #define S_OPT1_VLAN 6 417 #define M_OPT1_VLAN 0xFFF 418 #define V_OPT1_VLAN(x) ((x) << S_OPT1_VLAN) 419 #define G_OPT1_VLAN(x) (((x) >> S_OPT1_VLAN) & M_OPT1_VLAN) 420 421 #define S_MAC_MATCH_VALID 18 422 #define V_MAC_MATCH_VALID(x) ((x) << S_MAC_MATCH_VALID) 423 #define F_MAC_MATCH_VALID V_MAC_MATCH_VALID(1U) 424 425 #define S_CONN_POLICY 19 426 #define M_CONN_POLICY 0x3 427 #define V_CONN_POLICY(x) ((x) << S_CONN_POLICY) 428 #define G_CONN_POLICY(x) (((x) >> S_CONN_POLICY) & M_CONN_POLICY) 429 430 #define S_SYN_DEFENSE 21 431 #define V_SYN_DEFENSE(x) ((x) << S_SYN_DEFENSE) 432 #define F_SYN_DEFENSE V_SYN_DEFENSE(1U) 433 434 #define S_VLAN_PRI 22 435 #define M_VLAN_PRI 0x3 436 #define V_VLAN_PRI(x) ((x) << S_VLAN_PRI) 437 #define G_VLAN_PRI(x) (((x) >> S_VLAN_PRI) & M_VLAN_PRI) 438 439 #define S_VLAN_PRI_VALID 24 440 #define V_VLAN_PRI_VALID(x) ((x) << S_VLAN_PRI_VALID) 441 #define F_VLAN_PRI_VALID V_VLAN_PRI_VALID(1U) 442 443 #define S_PKT_TYPE 25 444 #define M_PKT_TYPE 0x3 445 #define V_PKT_TYPE(x) ((x) << S_PKT_TYPE) 446 #define G_PKT_TYPE(x) (((x) >> S_PKT_TYPE) & M_PKT_TYPE) 447 448 #define S_MAC_MATCH 27 449 #define M_MAC_MATCH 0x1F 450 #define V_MAC_MATCH(x) ((x) << S_MAC_MATCH) 451 #define G_MAC_MATCH(x) (((x) >> S_MAC_MATCH) & M_MAC_MATCH) 452 453 /* option 2 fields */ 454 #define S_CPU_INDEX 0 455 #define M_CPU_INDEX 0x7F 456 #define V_CPU_INDEX(x) ((x) << S_CPU_INDEX) 457 #define G_CPU_INDEX(x) (((x) >> S_CPU_INDEX) & M_CPU_INDEX) 458 459 #define S_CPU_INDEX_VALID 7 460 #define V_CPU_INDEX_VALID(x) ((x) << S_CPU_INDEX_VALID) 461 #define F_CPU_INDEX_VALID V_CPU_INDEX_VALID(1U) 462 463 #define S_RX_COALESCE 8 464 #define M_RX_COALESCE 0x3 465 #define V_RX_COALESCE(x) ((x) << S_RX_COALESCE) 466 #define G_RX_COALESCE(x) (((x) >> S_RX_COALESCE) & M_RX_COALESCE) 467 468 #define S_RX_COALESCE_VALID 10 469 #define V_RX_COALESCE_VALID(x) ((x) << S_RX_COALESCE_VALID) 470 #define F_RX_COALESCE_VALID V_RX_COALESCE_VALID(1U) 471 472 #define S_CONG_CONTROL_FLAVOR 11 473 #define M_CONG_CONTROL_FLAVOR 0x3 474 #define V_CONG_CONTROL_FLAVOR(x) ((x) << S_CONG_CONTROL_FLAVOR) 475 #define G_CONG_CONTROL_FLAVOR(x) (((x) >> S_CONG_CONTROL_FLAVOR) & M_CONG_CONTROL_FLAVOR) 476 477 #define S_PACING_FLAVOR 13 478 #define M_PACING_FLAVOR 0x3 479 #define V_PACING_FLAVOR(x) ((x) << S_PACING_FLAVOR) 480 #define G_PACING_FLAVOR(x) (((x) >> S_PACING_FLAVOR) & M_PACING_FLAVOR) 481 482 #define S_FLAVORS_VALID 15 483 #define V_FLAVORS_VALID(x) ((x) << S_FLAVORS_VALID) 484 #define F_FLAVORS_VALID V_FLAVORS_VALID(1U) 485 486 #define S_RX_FC_DISABLE 16 487 #define V_RX_FC_DISABLE(x) ((x) << S_RX_FC_DISABLE) 488 #define F_RX_FC_DISABLE V_RX_FC_DISABLE(1U) 489 490 #define S_RX_FC_VALID 17 491 #define V_RX_FC_VALID(x) ((x) << S_RX_FC_VALID) 492 #define F_RX_FC_VALID V_RX_FC_VALID(1U) 493 494 struct cpl_pass_open_req { 495 WR_HDR; 496 union opcode_tid ot; 497 __be16 local_port; 498 __be16 peer_port; 499 __be32 local_ip; 500 __be32 peer_ip; 501 __be32 opt0h; 502 __be32 opt0l; 503 __be32 peer_netmask; 504 __be32 opt1; 505 }; 506 507 struct cpl_pass_open_rpl { 508 RSS_HDR 509 union opcode_tid ot; 510 __be16 local_port; 511 __be16 peer_port; 512 __be32 local_ip; 513 __be32 peer_ip; 514 __u8 resvd[7]; 515 __u8 status; 516 }; 517 518 struct cpl_pass_establish { 519 RSS_HDR 520 union opcode_tid ot; 521 __be16 local_port; 522 __be16 peer_port; 523 __be32 local_ip; 524 __be32 peer_ip; 525 __be32 tos_tid; 526 __be16 l2t_idx; 527 __be16 tcp_opt; 528 __be32 snd_isn; 529 __be32 rcv_isn; 530 }; 531 532 /* cpl_pass_establish.tos_tid fields */ 533 #define S_PASS_OPEN_TID 0 534 #define M_PASS_OPEN_TID 0xFFFFFF 535 #define V_PASS_OPEN_TID(x) ((x) << S_PASS_OPEN_TID) 536 #define G_PASS_OPEN_TID(x) (((x) >> S_PASS_OPEN_TID) & M_PASS_OPEN_TID) 537 538 #define S_PASS_OPEN_TOS 24 539 #define M_PASS_OPEN_TOS 0xFF 540 #define V_PASS_OPEN_TOS(x) ((x) << S_PASS_OPEN_TOS) 541 #define G_PASS_OPEN_TOS(x) (((x) >> S_PASS_OPEN_TOS) & M_PASS_OPEN_TOS) 542 543 /* cpl_pass_establish.l2t_idx fields */ 544 #define S_L2T_IDX16 5 545 #define M_L2T_IDX16 0x7FF 546 #define V_L2T_IDX16(x) ((x) << S_L2T_IDX16) 547 #define G_L2T_IDX16(x) (((x) >> S_L2T_IDX16) & M_L2T_IDX16) 548 549 /* cpl_pass_establish.tcp_opt fields (also applies act_open_establish) */ 550 #define G_TCPOPT_WSCALE_OK(x) (((x) >> 5) & 1) 551 #define G_TCPOPT_SACK(x) (((x) >> 6) & 1) 552 #define G_TCPOPT_TSTAMP(x) (((x) >> 7) & 1) 553 #define G_TCPOPT_SND_WSCALE(x) (((x) >> 8) & 0xf) 554 #define G_TCPOPT_MSS(x) (((x) >> 12) & 0xf) 555 556 struct cpl_pass_accept_req { 557 RSS_HDR 558 union opcode_tid ot; 559 __be16 local_port; 560 __be16 peer_port; 561 __be32 local_ip; 562 __be32 peer_ip; 563 __be32 tos_tid; 564 struct tcp_options tcp_options; 565 __u8 dst_mac[6]; 566 __be16 vlan_tag; 567 __u8 src_mac[6]; 568 #if defined(__LITTLE_ENDIAN_BITFIELD) 569 __u8 :3; 570 __u8 addr_idx:3; 571 __u8 port_idx:1; 572 __u8 exact_match:1; 573 #else 574 __u8 exact_match:1; 575 __u8 port_idx:1; 576 __u8 addr_idx:3; 577 __u8 :3; 578 #endif 579 __u8 rsvd; 580 __be32 rcv_isn; 581 __be32 rsvd2; 582 }; 583 584 struct cpl_pass_accept_rpl { 585 WR_HDR; 586 union opcode_tid ot; 587 __be32 opt2; 588 __be32 rsvd; 589 __be32 peer_ip; 590 __be32 opt0h; 591 __be32 opt0l_status; 592 }; 593 594 struct cpl_act_open_req { 595 WR_HDR; 596 union opcode_tid ot; 597 __be16 local_port; 598 __be16 peer_port; 599 __be32 local_ip; 600 __be32 peer_ip; 601 __be32 opt0h; 602 __be32 opt0l; 603 __be32 params; 604 __be32 opt2; 605 }; 606 607 /* cpl_act_open_req.params fields */ 608 #define S_AOPEN_VLAN_PRI 9 609 #define M_AOPEN_VLAN_PRI 0x3 610 #define V_AOPEN_VLAN_PRI(x) ((x) << S_AOPEN_VLAN_PRI) 611 #define G_AOPEN_VLAN_PRI(x) (((x) >> S_AOPEN_VLAN_PRI) & M_AOPEN_VLAN_PRI) 612 613 #define S_AOPEN_VLAN_PRI_VALID 11 614 #define V_AOPEN_VLAN_PRI_VALID(x) ((x) << S_AOPEN_VLAN_PRI_VALID) 615 #define F_AOPEN_VLAN_PRI_VALID V_AOPEN_VLAN_PRI_VALID(1U) 616 617 #define S_AOPEN_PKT_TYPE 12 618 #define M_AOPEN_PKT_TYPE 0x3 619 #define V_AOPEN_PKT_TYPE(x) ((x) << S_AOPEN_PKT_TYPE) 620 #define G_AOPEN_PKT_TYPE(x) (((x) >> S_AOPEN_PKT_TYPE) & M_AOPEN_PKT_TYPE) 621 622 #define S_AOPEN_MAC_MATCH 14 623 #define M_AOPEN_MAC_MATCH 0x1F 624 #define V_AOPEN_MAC_MATCH(x) ((x) << S_AOPEN_MAC_MATCH) 625 #define G_AOPEN_MAC_MATCH(x) (((x) >> S_AOPEN_MAC_MATCH) & M_AOPEN_MAC_MATCH) 626 627 #define S_AOPEN_MAC_MATCH_VALID 19 628 #define V_AOPEN_MAC_MATCH_VALID(x) ((x) << S_AOPEN_MAC_MATCH_VALID) 629 #define F_AOPEN_MAC_MATCH_VALID V_AOPEN_MAC_MATCH_VALID(1U) 630 631 #define S_AOPEN_IFF_VLAN 20 632 #define M_AOPEN_IFF_VLAN 0xFFF 633 #define V_AOPEN_IFF_VLAN(x) ((x) << S_AOPEN_IFF_VLAN) 634 #define G_AOPEN_IFF_VLAN(x) (((x) >> S_AOPEN_IFF_VLAN) & M_AOPEN_IFF_VLAN) 635 636 struct cpl_act_open_rpl { 637 RSS_HDR 638 union opcode_tid ot; 639 __be16 local_port; 640 __be16 peer_port; 641 __be32 local_ip; 642 __be32 peer_ip; 643 __be32 atid; 644 __u8 rsvd[3]; 645 __u8 status; 646 }; 647 648 struct cpl_act_establish { 649 RSS_HDR 650 union opcode_tid ot; 651 __be16 local_port; 652 __be16 peer_port; 653 __be32 local_ip; 654 __be32 peer_ip; 655 __be32 tos_tid; 656 __be16 l2t_idx; 657 __be16 tcp_opt; 658 __be32 snd_isn; 659 __be32 rcv_isn; 660 }; 661 662 struct cpl_get_tcb { 663 WR_HDR; 664 union opcode_tid ot; 665 __be16 cpuno; 666 __be16 rsvd; 667 }; 668 669 struct cpl_get_tcb_rpl { 670 RSS_HDR 671 union opcode_tid ot; 672 __u8 rsvd; 673 __u8 status; 674 __be16 len; 675 }; 676 677 struct cpl_set_tcb { 678 WR_HDR; 679 union opcode_tid ot; 680 __u8 reply; 681 __u8 cpu_idx; 682 __be16 len; 683 }; 684 685 /* cpl_set_tcb.reply fields */ 686 #define S_NO_REPLY 7 687 #define V_NO_REPLY(x) ((x) << S_NO_REPLY) 688 #define F_NO_REPLY V_NO_REPLY(1U) 689 690 struct cpl_set_tcb_field { 691 WR_HDR; 692 union opcode_tid ot; 693 __u8 reply; 694 __u8 cpu_idx; 695 __be16 word; 696 __be64 mask; 697 __be64 val; 698 }; 699 700 struct cpl_set_tcb_rpl { 701 RSS_HDR 702 union opcode_tid ot; 703 __u8 rsvd[3]; 704 __u8 status; 705 }; 706 707 struct cpl_pcmd { 708 WR_HDR; 709 union opcode_tid ot; 710 __u8 rsvd[3]; 711 #if defined(__LITTLE_ENDIAN_BITFIELD) 712 __u8 src:1; 713 __u8 bundle:1; 714 __u8 channel:1; 715 __u8 :5; 716 #else 717 __u8 :5; 718 __u8 channel:1; 719 __u8 bundle:1; 720 __u8 src:1; 721 #endif 722 __be32 pcmd_parm[2]; 723 }; 724 725 struct cpl_pcmd_reply { 726 RSS_HDR 727 union opcode_tid ot; 728 __u8 status; 729 __u8 rsvd; 730 __be16 len; 731 }; 732 733 struct cpl_close_con_req { 734 WR_HDR; 735 union opcode_tid ot; 736 __be32 rsvd; 737 }; 738 739 struct cpl_close_con_rpl { 740 RSS_HDR 741 union opcode_tid ot; 742 __u8 rsvd[3]; 743 __u8 status; 744 __be32 snd_nxt; 745 __be32 rcv_nxt; 746 }; 747 748 struct cpl_close_listserv_req { 749 WR_HDR; 750 union opcode_tid ot; 751 __u8 rsvd0; 752 __u8 cpu_idx; 753 __be16 rsvd1; 754 }; 755 756 struct cpl_close_listserv_rpl { 757 RSS_HDR 758 union opcode_tid ot; 759 __u8 rsvd[3]; 760 __u8 status; 761 }; 762 763 struct cpl_abort_req_rss { 764 RSS_HDR 765 union opcode_tid ot; 766 __be32 rsvd0; 767 __u8 rsvd1; 768 __u8 status; 769 __u8 rsvd2[6]; 770 }; 771 772 struct cpl_abort_req { 773 WR_HDR; 774 union opcode_tid ot; 775 __be32 rsvd0; 776 __u8 rsvd1; 777 __u8 cmd; 778 __u8 rsvd2[6]; 779 }; 780 781 struct cpl_abort_rpl_rss { 782 RSS_HDR 783 union opcode_tid ot; 784 __be32 rsvd0; 785 __u8 rsvd1; 786 __u8 status; 787 __u8 rsvd2[6]; 788 }; 789 790 struct cpl_abort_rpl { 791 WR_HDR; 792 union opcode_tid ot; 793 __be32 rsvd0; 794 __u8 rsvd1; 795 __u8 cmd; 796 __u8 rsvd2[6]; 797 }; 798 799 struct cpl_peer_close { 800 RSS_HDR 801 union opcode_tid ot; 802 __be32 rcv_nxt; 803 }; 804 805 struct tx_data_wr { 806 __be32 wr_hi; 807 __be32 wr_lo; 808 __be32 len; 809 __be32 flags; 810 __be32 sndseq; 811 __be32 param; 812 }; 813 814 /* tx_data_wr.flags fields */ 815 #define S_TX_ACK_PAGES 21 816 #define M_TX_ACK_PAGES 0x7 817 #define V_TX_ACK_PAGES(x) ((x) << S_TX_ACK_PAGES) 818 #define G_TX_ACK_PAGES(x) (((x) >> S_TX_ACK_PAGES) & M_TX_ACK_PAGES) 819 820 /* tx_data_wr.param fields */ 821 #define S_TX_PORT 0 822 #define M_TX_PORT 0x7 823 #define V_TX_PORT(x) ((x) << S_TX_PORT) 824 #define G_TX_PORT(x) (((x) >> S_TX_PORT) & M_TX_PORT) 825 826 #define S_TX_MSS 4 827 #define M_TX_MSS 0xF 828 #define V_TX_MSS(x) ((x) << S_TX_MSS) 829 #define G_TX_MSS(x) (((x) >> S_TX_MSS) & M_TX_MSS) 830 831 #define S_TX_QOS 8 832 #define M_TX_QOS 0xFF 833 #define V_TX_QOS(x) ((x) << S_TX_QOS) 834 #define G_TX_QOS(x) (((x) >> S_TX_QOS) & M_TX_QOS) 835 836 #define S_TX_SNDBUF 16 837 #define M_TX_SNDBUF 0xFFFF 838 #define V_TX_SNDBUF(x) ((x) << S_TX_SNDBUF) 839 #define G_TX_SNDBUF(x) (((x) >> S_TX_SNDBUF) & M_TX_SNDBUF) 840 841 struct cpl_tx_data { 842 union opcode_tid ot; 843 __be32 len; 844 __be32 rsvd; 845 __be16 urg; 846 __be16 flags; 847 }; 848 849 /* cpl_tx_data.flags fields */ 850 #define S_TX_ULP_SUBMODE 6 851 #define M_TX_ULP_SUBMODE 0xF 852 #define V_TX_ULP_SUBMODE(x) ((x) << S_TX_ULP_SUBMODE) 853 #define G_TX_ULP_SUBMODE(x) (((x) >> S_TX_ULP_SUBMODE) & M_TX_ULP_SUBMODE) 854 855 #define S_TX_ULP_MODE 10 856 #define M_TX_ULP_MODE 0xF 857 #define V_TX_ULP_MODE(x) ((x) << S_TX_ULP_MODE) 858 #define G_TX_ULP_MODE(x) (((x) >> S_TX_ULP_MODE) & M_TX_ULP_MODE) 859 860 #define S_TX_SHOVE 14 861 #define V_TX_SHOVE(x) ((x) << S_TX_SHOVE) 862 #define F_TX_SHOVE V_TX_SHOVE(1U) 863 864 #define S_TX_MORE 15 865 #define V_TX_MORE(x) ((x) << S_TX_MORE) 866 #define F_TX_MORE V_TX_MORE(1U) 867 868 /* additional tx_data_wr.flags fields */ 869 #define S_TX_CPU_IDX 0 870 #define M_TX_CPU_IDX 0x3F 871 #define V_TX_CPU_IDX(x) ((x) << S_TX_CPU_IDX) 872 #define G_TX_CPU_IDX(x) (((x) >> S_TX_CPU_IDX) & M_TX_CPU_IDX) 873 874 #define S_TX_URG 16 875 #define V_TX_URG(x) ((x) << S_TX_URG) 876 #define F_TX_URG V_TX_URG(1U) 877 878 #define S_TX_CLOSE 17 879 #define V_TX_CLOSE(x) ((x) << S_TX_CLOSE) 880 #define F_TX_CLOSE V_TX_CLOSE(1U) 881 882 #define S_TX_INIT 18 883 #define V_TX_INIT(x) ((x) << S_TX_INIT) 884 #define F_TX_INIT V_TX_INIT(1U) 885 886 #define S_TX_IMM_ACK 19 887 #define V_TX_IMM_ACK(x) ((x) << S_TX_IMM_ACK) 888 #define F_TX_IMM_ACK V_TX_IMM_ACK(1U) 889 890 #define S_TX_IMM_DMA 20 891 #define V_TX_IMM_DMA(x) ((x) << S_TX_IMM_DMA) 892 #define F_TX_IMM_DMA V_TX_IMM_DMA(1U) 893 894 struct cpl_tx_data_ack { 895 RSS_HDR 896 union opcode_tid ot; 897 __be32 ack_seq; 898 }; 899 900 struct cpl_wr_ack { 901 RSS_HDR 902 union opcode_tid ot; 903 __be16 credits; 904 __be16 rsvd; 905 __be32 snd_nxt; 906 __be32 snd_una; 907 }; 908 909 struct cpl_rdma_ec_status { 910 RSS_HDR 911 union opcode_tid ot; 912 __u8 rsvd[3]; 913 __u8 status; 914 }; 915 916 struct mngt_pktsched_wr { 917 __be32 wr_hi; 918 __be32 wr_lo; 919 __u8 mngt_opcode; 920 __u8 rsvd[7]; 921 __u8 sched; 922 __u8 idx; 923 __u8 min; 924 __u8 max; 925 __u8 binding; 926 __u8 rsvd1[3]; 927 }; 928 929 struct cpl_iscsi_hdr { 930 RSS_HDR 931 union opcode_tid ot; 932 __be16 pdu_len_ddp; 933 __be16 len; 934 __be32 seq; 935 __be16 urg; 936 __u8 rsvd; 937 __u8 status; 938 }; 939 940 /* cpl_iscsi_hdr.pdu_len_ddp fields */ 941 #define S_ISCSI_PDU_LEN 0 942 #define M_ISCSI_PDU_LEN 0x7FFF 943 #define V_ISCSI_PDU_LEN(x) ((x) << S_ISCSI_PDU_LEN) 944 #define G_ISCSI_PDU_LEN(x) (((x) >> S_ISCSI_PDU_LEN) & M_ISCSI_PDU_LEN) 945 946 #define S_ISCSI_DDP 15 947 #define V_ISCSI_DDP(x) ((x) << S_ISCSI_DDP) 948 #define F_ISCSI_DDP V_ISCSI_DDP(1U) 949 950 struct cpl_rx_data { 951 RSS_HDR 952 union opcode_tid ot; 953 __be16 rsvd; 954 __be16 len; 955 __be32 seq; 956 __be16 urg; 957 #if defined(__LITTLE_ENDIAN_BITFIELD) 958 __u8 dack_mode:2; 959 __u8 psh:1; 960 __u8 heartbeat:1; 961 __u8 :4; 962 #else 963 __u8 :4; 964 __u8 heartbeat:1; 965 __u8 psh:1; 966 __u8 dack_mode:2; 967 #endif 968 __u8 status; 969 }; 970 971 struct cpl_rx_data_ack { 972 WR_HDR; 973 union opcode_tid ot; 974 __be32 credit_dack; 975 }; 976 977 /* cpl_rx_data_ack.ack_seq fields */ 978 #define S_RX_CREDITS 0 979 #define M_RX_CREDITS 0x7FFFFFF 980 #define V_RX_CREDITS(x) ((x) << S_RX_CREDITS) 981 #define G_RX_CREDITS(x) (((x) >> S_RX_CREDITS) & M_RX_CREDITS) 982 983 #define S_RX_MODULATE 27 984 #define V_RX_MODULATE(x) ((x) << S_RX_MODULATE) 985 #define F_RX_MODULATE V_RX_MODULATE(1U) 986 987 #define S_RX_FORCE_ACK 28 988 #define V_RX_FORCE_ACK(x) ((x) << S_RX_FORCE_ACK) 989 #define F_RX_FORCE_ACK V_RX_FORCE_ACK(1U) 990 991 #define S_RX_DACK_MODE 29 992 #define M_RX_DACK_MODE 0x3 993 #define V_RX_DACK_MODE(x) ((x) << S_RX_DACK_MODE) 994 #define G_RX_DACK_MODE(x) (((x) >> S_RX_DACK_MODE) & M_RX_DACK_MODE) 995 996 #define S_RX_DACK_CHANGE 31 997 #define V_RX_DACK_CHANGE(x) ((x) << S_RX_DACK_CHANGE) 998 #define F_RX_DACK_CHANGE V_RX_DACK_CHANGE(1U) 999 1000 struct cpl_rx_urg_notify { 1001 RSS_HDR 1002 union opcode_tid ot; 1003 __be32 seq; 1004 }; 1005 1006 struct cpl_rx_ddp_complete { 1007 RSS_HDR 1008 union opcode_tid ot; 1009 __be32 ddp_report; 1010 }; 1011 1012 struct cpl_rx_data_ddp { 1013 RSS_HDR 1014 union opcode_tid ot; 1015 __be16 urg; 1016 __be16 len; 1017 __be32 seq; 1018 union { 1019 __be32 nxt_seq; 1020 __be32 ddp_report; 1021 } u; 1022 __be32 ulp_crc; 1023 __be32 ddpvld_status; 1024 }; 1025 1026 /* cpl_rx_data_ddp.ddpvld_status fields */ 1027 #define S_DDP_STATUS 0 1028 #define M_DDP_STATUS 0xFF 1029 #define V_DDP_STATUS(x) ((x) << S_DDP_STATUS) 1030 #define G_DDP_STATUS(x) (((x) >> S_DDP_STATUS) & M_DDP_STATUS) 1031 1032 #define S_DDP_VALID 15 1033 #define M_DDP_VALID 0x1FFFF 1034 #define V_DDP_VALID(x) ((x) << S_DDP_VALID) 1035 #define G_DDP_VALID(x) (((x) >> S_DDP_VALID) & M_DDP_VALID) 1036 1037 #define S_DDP_PPOD_MISMATCH 15 1038 #define V_DDP_PPOD_MISMATCH(x) ((x) << S_DDP_PPOD_MISMATCH) 1039 #define F_DDP_PPOD_MISMATCH V_DDP_PPOD_MISMATCH(1U) 1040 1041 #define S_DDP_PDU 16 1042 #define V_DDP_PDU(x) ((x) << S_DDP_PDU) 1043 #define F_DDP_PDU V_DDP_PDU(1U) 1044 1045 #define S_DDP_LLIMIT_ERR 17 1046 #define V_DDP_LLIMIT_ERR(x) ((x) << S_DDP_LLIMIT_ERR) 1047 #define F_DDP_LLIMIT_ERR V_DDP_LLIMIT_ERR(1U) 1048 1049 #define S_DDP_PPOD_PARITY_ERR 18 1050 #define V_DDP_PPOD_PARITY_ERR(x) ((x) << S_DDP_PPOD_PARITY_ERR) 1051 #define F_DDP_PPOD_PARITY_ERR V_DDP_PPOD_PARITY_ERR(1U) 1052 1053 #define S_DDP_PADDING_ERR 19 1054 #define V_DDP_PADDING_ERR(x) ((x) << S_DDP_PADDING_ERR) 1055 #define F_DDP_PADDING_ERR V_DDP_PADDING_ERR(1U) 1056 1057 #define S_DDP_HDRCRC_ERR 20 1058 #define V_DDP_HDRCRC_ERR(x) ((x) << S_DDP_HDRCRC_ERR) 1059 #define F_DDP_HDRCRC_ERR V_DDP_HDRCRC_ERR(1U) 1060 1061 #define S_DDP_DATACRC_ERR 21 1062 #define V_DDP_DATACRC_ERR(x) ((x) << S_DDP_DATACRC_ERR) 1063 #define F_DDP_DATACRC_ERR V_DDP_DATACRC_ERR(1U) 1064 1065 #define S_DDP_INVALID_TAG 22 1066 #define V_DDP_INVALID_TAG(x) ((x) << S_DDP_INVALID_TAG) 1067 #define F_DDP_INVALID_TAG V_DDP_INVALID_TAG(1U) 1068 1069 #define S_DDP_ULIMIT_ERR 23 1070 #define V_DDP_ULIMIT_ERR(x) ((x) << S_DDP_ULIMIT_ERR) 1071 #define F_DDP_ULIMIT_ERR V_DDP_ULIMIT_ERR(1U) 1072 1073 #define S_DDP_OFFSET_ERR 24 1074 #define V_DDP_OFFSET_ERR(x) ((x) << S_DDP_OFFSET_ERR) 1075 #define F_DDP_OFFSET_ERR V_DDP_OFFSET_ERR(1U) 1076 1077 #define S_DDP_COLOR_ERR 25 1078 #define V_DDP_COLOR_ERR(x) ((x) << S_DDP_COLOR_ERR) 1079 #define F_DDP_COLOR_ERR V_DDP_COLOR_ERR(1U) 1080 1081 #define S_DDP_TID_MISMATCH 26 1082 #define V_DDP_TID_MISMATCH(x) ((x) << S_DDP_TID_MISMATCH) 1083 #define F_DDP_TID_MISMATCH V_DDP_TID_MISMATCH(1U) 1084 1085 #define S_DDP_INVALID_PPOD 27 1086 #define V_DDP_INVALID_PPOD(x) ((x) << S_DDP_INVALID_PPOD) 1087 #define F_DDP_INVALID_PPOD V_DDP_INVALID_PPOD(1U) 1088 1089 #define S_DDP_ULP_MODE 28 1090 #define M_DDP_ULP_MODE 0xF 1091 #define V_DDP_ULP_MODE(x) ((x) << S_DDP_ULP_MODE) 1092 #define G_DDP_ULP_MODE(x) (((x) >> S_DDP_ULP_MODE) & M_DDP_ULP_MODE) 1093 1094 /* cpl_rx_data_ddp.ddp_report fields */ 1095 #define S_DDP_OFFSET 0 1096 #define M_DDP_OFFSET 0x3FFFFF 1097 #define V_DDP_OFFSET(x) ((x) << S_DDP_OFFSET) 1098 #define G_DDP_OFFSET(x) (((x) >> S_DDP_OFFSET) & M_DDP_OFFSET) 1099 1100 #define S_DDP_URG 24 1101 #define V_DDP_URG(x) ((x) << S_DDP_URG) 1102 #define F_DDP_URG V_DDP_URG(1U) 1103 1104 #define S_DDP_PSH 25 1105 #define V_DDP_PSH(x) ((x) << S_DDP_PSH) 1106 #define F_DDP_PSH V_DDP_PSH(1U) 1107 1108 #define S_DDP_BUF_COMPLETE 26 1109 #define V_DDP_BUF_COMPLETE(x) ((x) << S_DDP_BUF_COMPLETE) 1110 #define F_DDP_BUF_COMPLETE V_DDP_BUF_COMPLETE(1U) 1111 1112 #define S_DDP_BUF_TIMED_OUT 27 1113 #define V_DDP_BUF_TIMED_OUT(x) ((x) << S_DDP_BUF_TIMED_OUT) 1114 #define F_DDP_BUF_TIMED_OUT V_DDP_BUF_TIMED_OUT(1U) 1115 1116 #define S_DDP_BUF_IDX 28 1117 #define V_DDP_BUF_IDX(x) ((x) << S_DDP_BUF_IDX) 1118 #define F_DDP_BUF_IDX V_DDP_BUF_IDX(1U) 1119 1120 struct cpl_tx_pkt { 1121 WR_HDR; 1122 __be32 cntrl; 1123 __be32 len; 1124 }; 1125 1126 struct cpl_tx_pkt_lso { 1127 WR_HDR; 1128 __be32 cntrl; 1129 __be32 len; 1130 1131 __be32 rsvd; 1132 __be32 lso_info; 1133 }; 1134 1135 struct cpl_tx_pkt_batch_entry { 1136 __be32 cntrl; 1137 __be32 len; 1138 __be64 addr; 1139 }; 1140 1141 struct cpl_tx_pkt_batch { 1142 WR_HDR; 1143 struct cpl_tx_pkt_batch_entry pkt_entry[7]; 1144 }; 1145 1146 1147 /* cpl_tx_pkt*.cntrl fields */ 1148 #define S_TXPKT_VLAN 0 1149 #define M_TXPKT_VLAN 0xFFFF 1150 #define V_TXPKT_VLAN(x) ((x) << S_TXPKT_VLAN) 1151 #define G_TXPKT_VLAN(x) (((x) >> S_TXPKT_VLAN) & M_TXPKT_VLAN) 1152 1153 #define S_TXPKT_INTF 16 1154 #define M_TXPKT_INTF 0xF 1155 #define V_TXPKT_INTF(x) ((x) << S_TXPKT_INTF) 1156 #define G_TXPKT_INTF(x) (((x) >> S_TXPKT_INTF) & M_TXPKT_INTF) 1157 1158 #define S_TXPKT_IPCSUM_DIS 20 1159 #define V_TXPKT_IPCSUM_DIS(x) ((x) << S_TXPKT_IPCSUM_DIS) 1160 #define F_TXPKT_IPCSUM_DIS V_TXPKT_IPCSUM_DIS(1U) 1161 1162 #define S_TXPKT_L4CSUM_DIS 21 1163 #define V_TXPKT_L4CSUM_DIS(x) ((x) << S_TXPKT_L4CSUM_DIS) 1164 #define F_TXPKT_L4CSUM_DIS V_TXPKT_L4CSUM_DIS(1U) 1165 1166 #define S_TXPKT_VLAN_VLD 22 1167 #define V_TXPKT_VLAN_VLD(x) ((x) << S_TXPKT_VLAN_VLD) 1168 #define F_TXPKT_VLAN_VLD V_TXPKT_VLAN_VLD(1U) 1169 1170 #define S_TXPKT_LOOPBACK 23 1171 #define V_TXPKT_LOOPBACK(x) ((x) << S_TXPKT_LOOPBACK) 1172 #define F_TXPKT_LOOPBACK V_TXPKT_LOOPBACK(1U) 1173 1174 #define S_TXPKT_OPCODE 24 1175 #define M_TXPKT_OPCODE 0xFF 1176 #define V_TXPKT_OPCODE(x) ((x) << S_TXPKT_OPCODE) 1177 #define G_TXPKT_OPCODE(x) (((x) >> S_TXPKT_OPCODE) & M_TXPKT_OPCODE) 1178 1179 /* cpl_tx_pkt_lso.lso_info fields */ 1180 #define S_LSO_MSS 0 1181 #define M_LSO_MSS 0x3FFF 1182 #define V_LSO_MSS(x) ((x) << S_LSO_MSS) 1183 #define G_LSO_MSS(x) (((x) >> S_LSO_MSS) & M_LSO_MSS) 1184 1185 #define S_LSO_ETH_TYPE 14 1186 #define M_LSO_ETH_TYPE 0x3 1187 #define V_LSO_ETH_TYPE(x) ((x) << S_LSO_ETH_TYPE) 1188 #define G_LSO_ETH_TYPE(x) (((x) >> S_LSO_ETH_TYPE) & M_LSO_ETH_TYPE) 1189 1190 #define S_LSO_TCPHDR_WORDS 16 1191 #define M_LSO_TCPHDR_WORDS 0xF 1192 #define V_LSO_TCPHDR_WORDS(x) ((x) << S_LSO_TCPHDR_WORDS) 1193 #define G_LSO_TCPHDR_WORDS(x) (((x) >> S_LSO_TCPHDR_WORDS) & M_LSO_TCPHDR_WORDS) 1194 1195 #define S_LSO_IPHDR_WORDS 20 1196 #define M_LSO_IPHDR_WORDS 0xF 1197 #define V_LSO_IPHDR_WORDS(x) ((x) << S_LSO_IPHDR_WORDS) 1198 #define G_LSO_IPHDR_WORDS(x) (((x) >> S_LSO_IPHDR_WORDS) & M_LSO_IPHDR_WORDS) 1199 1200 #define S_LSO_IPV6 24 1201 #define V_LSO_IPV6(x) ((x) << S_LSO_IPV6) 1202 #define F_LSO_IPV6 V_LSO_IPV6(1U) 1203 1204 struct cpl_trace_pkt { 1205 #ifdef CHELSIO_FW 1206 __u8 rss_opcode; 1207 #if defined(__LITTLE_ENDIAN_BITFIELD) 1208 __u8 err:1; 1209 __u8 :7; 1210 #else 1211 __u8 :7; 1212 __u8 err:1; 1213 #endif 1214 __u8 rsvd0; 1215 #if defined(__LITTLE_ENDIAN_BITFIELD) 1216 __u8 qid:4; 1217 __u8 :4; 1218 #else 1219 __u8 :4; 1220 __u8 qid:4; 1221 #endif 1222 __be32 tstamp; 1223 #endif /* CHELSIO_FW */ 1224 1225 __u8 opcode; 1226 #if defined(__LITTLE_ENDIAN_BITFIELD) 1227 __u8 iff:4; 1228 __u8 :4; 1229 #else 1230 __u8 :4; 1231 __u8 iff:4; 1232 #endif 1233 __u8 rsvd[4]; 1234 __be16 len; 1235 }; 1236 1237 struct cpl_rx_pkt { 1238 RSS_HDR 1239 __u8 opcode; 1240 #if defined(__LITTLE_ENDIAN_BITFIELD) 1241 __u8 iff:4; 1242 __u8 csum_valid:1; 1243 __u8 ipmi_pkt:1; 1244 __u8 vlan_valid:1; 1245 __u8 fragment:1; 1246 #else 1247 __u8 fragment:1; 1248 __u8 vlan_valid:1; 1249 __u8 ipmi_pkt:1; 1250 __u8 csum_valid:1; 1251 __u8 iff:4; 1252 #endif 1253 __be16 csum; 1254 __be16 vlan; 1255 __be16 len; 1256 }; 1257 1258 struct cpl_l2t_write_req { 1259 WR_HDR; 1260 union opcode_tid ot; 1261 __be32 params; 1262 __u8 rsvd[2]; 1263 __u8 dst_mac[6]; 1264 }; 1265 1266 /* cpl_l2t_write_req.params fields */ 1267 #define S_L2T_W_IDX 0 1268 #define M_L2T_W_IDX 0x7FF 1269 #define V_L2T_W_IDX(x) ((x) << S_L2T_W_IDX) 1270 #define G_L2T_W_IDX(x) (((x) >> S_L2T_W_IDX) & M_L2T_W_IDX) 1271 1272 #define S_L2T_W_VLAN 11 1273 #define M_L2T_W_VLAN 0xFFF 1274 #define V_L2T_W_VLAN(x) ((x) << S_L2T_W_VLAN) 1275 #define G_L2T_W_VLAN(x) (((x) >> S_L2T_W_VLAN) & M_L2T_W_VLAN) 1276 1277 #define S_L2T_W_IFF 23 1278 #define M_L2T_W_IFF 0xF 1279 #define V_L2T_W_IFF(x) ((x) << S_L2T_W_IFF) 1280 #define G_L2T_W_IFF(x) (((x) >> S_L2T_W_IFF) & M_L2T_W_IFF) 1281 1282 #define S_L2T_W_PRIO 27 1283 #define M_L2T_W_PRIO 0x7 1284 #define V_L2T_W_PRIO(x) ((x) << S_L2T_W_PRIO) 1285 #define G_L2T_W_PRIO(x) (((x) >> S_L2T_W_PRIO) & M_L2T_W_PRIO) 1286 1287 struct cpl_l2t_write_rpl { 1288 RSS_HDR 1289 union opcode_tid ot; 1290 __u8 status; 1291 __u8 rsvd[3]; 1292 }; 1293 1294 struct cpl_l2t_read_req { 1295 WR_HDR; 1296 union opcode_tid ot; 1297 __be16 rsvd; 1298 __be16 l2t_idx; 1299 }; 1300 1301 struct cpl_l2t_read_rpl { 1302 RSS_HDR 1303 union opcode_tid ot; 1304 __be32 params; 1305 __u8 rsvd[2]; 1306 __u8 dst_mac[6]; 1307 }; 1308 1309 /* cpl_l2t_read_rpl.params fields */ 1310 #define S_L2T_R_PRIO 0 1311 #define M_L2T_R_PRIO 0x7 1312 #define V_L2T_R_PRIO(x) ((x) << S_L2T_R_PRIO) 1313 #define G_L2T_R_PRIO(x) (((x) >> S_L2T_R_PRIO) & M_L2T_R_PRIO) 1314 1315 #define S_L2T_R_VLAN 8 1316 #define M_L2T_R_VLAN 0xFFF 1317 #define V_L2T_R_VLAN(x) ((x) << S_L2T_R_VLAN) 1318 #define G_L2T_R_VLAN(x) (((x) >> S_L2T_R_VLAN) & M_L2T_R_VLAN) 1319 1320 #define S_L2T_R_IFF 20 1321 #define M_L2T_R_IFF 0xF 1322 #define V_L2T_R_IFF(x) ((x) << S_L2T_R_IFF) 1323 #define G_L2T_R_IFF(x) (((x) >> S_L2T_R_IFF) & M_L2T_R_IFF) 1324 1325 #define S_L2T_STATUS 24 1326 #define M_L2T_STATUS 0xFF 1327 #define V_L2T_STATUS(x) ((x) << S_L2T_STATUS) 1328 #define G_L2T_STATUS(x) (((x) >> S_L2T_STATUS) & M_L2T_STATUS) 1329 1330 struct cpl_smt_write_req { 1331 WR_HDR; 1332 union opcode_tid ot; 1333 __u8 rsvd0; 1334 #if defined(__LITTLE_ENDIAN_BITFIELD) 1335 __u8 mtu_idx:4; 1336 __u8 iff:4; 1337 #else 1338 __u8 iff:4; 1339 __u8 mtu_idx:4; 1340 #endif 1341 __be16 rsvd2; 1342 __be16 rsvd3; 1343 __u8 src_mac1[6]; 1344 __be16 rsvd4; 1345 __u8 src_mac0[6]; 1346 }; 1347 1348 struct cpl_smt_write_rpl { 1349 RSS_HDR 1350 union opcode_tid ot; 1351 __u8 status; 1352 __u8 rsvd[3]; 1353 }; 1354 1355 struct cpl_smt_read_req { 1356 WR_HDR; 1357 union opcode_tid ot; 1358 __u8 rsvd0; 1359 #if defined(__LITTLE_ENDIAN_BITFIELD) 1360 __u8 :4; 1361 __u8 iff:4; 1362 #else 1363 __u8 iff:4; 1364 __u8 :4; 1365 #endif 1366 __be16 rsvd2; 1367 }; 1368 1369 struct cpl_smt_read_rpl { 1370 RSS_HDR 1371 union opcode_tid ot; 1372 __u8 status; 1373 #if defined(__LITTLE_ENDIAN_BITFIELD) 1374 __u8 mtu_idx:4; 1375 __u8 :4; 1376 #else 1377 __u8 :4; 1378 __u8 mtu_idx:4; 1379 #endif 1380 __be16 rsvd2; 1381 __be16 rsvd3; 1382 __u8 src_mac1[6]; 1383 __be16 rsvd4; 1384 __u8 src_mac0[6]; 1385 }; 1386 1387 struct cpl_rte_delete_req { 1388 WR_HDR; 1389 union opcode_tid ot; 1390 __be32 params; 1391 }; 1392 1393 /* { cpl_rte_delete_req, cpl_rte_read_req }.params fields */ 1394 #define S_RTE_REQ_LUT_IX 8 1395 #define M_RTE_REQ_LUT_IX 0x7FF 1396 #define V_RTE_REQ_LUT_IX(x) ((x) << S_RTE_REQ_LUT_IX) 1397 #define G_RTE_REQ_LUT_IX(x) (((x) >> S_RTE_REQ_LUT_IX) & M_RTE_REQ_LUT_IX) 1398 1399 #define S_RTE_REQ_LUT_BASE 19 1400 #define M_RTE_REQ_LUT_BASE 0x7FF 1401 #define V_RTE_REQ_LUT_BASE(x) ((x) << S_RTE_REQ_LUT_BASE) 1402 #define G_RTE_REQ_LUT_BASE(x) (((x) >> S_RTE_REQ_LUT_BASE) & M_RTE_REQ_LUT_BASE) 1403 1404 #define S_RTE_READ_REQ_SELECT 31 1405 #define V_RTE_READ_REQ_SELECT(x) ((x) << S_RTE_READ_REQ_SELECT) 1406 #define F_RTE_READ_REQ_SELECT V_RTE_READ_REQ_SELECT(1U) 1407 1408 struct cpl_rte_delete_rpl { 1409 RSS_HDR 1410 union opcode_tid ot; 1411 __u8 status; 1412 __u8 rsvd[3]; 1413 }; 1414 1415 struct cpl_rte_write_req { 1416 WR_HDR; 1417 union opcode_tid ot; 1418 #if defined(__LITTLE_ENDIAN_BITFIELD) 1419 __u8 :6; 1420 __u8 write_tcam:1; 1421 __u8 write_l2t_lut:1; 1422 #else 1423 __u8 write_l2t_lut:1; 1424 __u8 write_tcam:1; 1425 __u8 :6; 1426 #endif 1427 __u8 rsvd[3]; 1428 __be32 lut_params; 1429 __be16 rsvd2; 1430 __be16 l2t_idx; 1431 __be32 netmask; 1432 __be32 faddr; 1433 }; 1434 1435 /* cpl_rte_write_req.lut_params fields */ 1436 #define S_RTE_WRITE_REQ_LUT_IX 10 1437 #define M_RTE_WRITE_REQ_LUT_IX 0x7FF 1438 #define V_RTE_WRITE_REQ_LUT_IX(x) ((x) << S_RTE_WRITE_REQ_LUT_IX) 1439 #define G_RTE_WRITE_REQ_LUT_IX(x) (((x) >> S_RTE_WRITE_REQ_LUT_IX) & M_RTE_WRITE_REQ_LUT_IX) 1440 1441 #define S_RTE_WRITE_REQ_LUT_BASE 21 1442 #define M_RTE_WRITE_REQ_LUT_BASE 0x7FF 1443 #define V_RTE_WRITE_REQ_LUT_BASE(x) ((x) << S_RTE_WRITE_REQ_LUT_BASE) 1444 #define G_RTE_WRITE_REQ_LUT_BASE(x) (((x) >> S_RTE_WRITE_REQ_LUT_BASE) & M_RTE_WRITE_REQ_LUT_BASE) 1445 1446 struct cpl_rte_write_rpl { 1447 RSS_HDR 1448 union opcode_tid ot; 1449 __u8 status; 1450 __u8 rsvd[3]; 1451 }; 1452 1453 struct cpl_rte_read_req { 1454 WR_HDR; 1455 union opcode_tid ot; 1456 __be32 params; 1457 }; 1458 1459 struct cpl_rte_read_rpl { 1460 RSS_HDR 1461 union opcode_tid ot; 1462 __u8 status; 1463 __u8 rsvd0; 1464 __be16 l2t_idx; 1465 #if defined(__LITTLE_ENDIAN_BITFIELD) 1466 __u8 :7; 1467 __u8 select:1; 1468 #else 1469 __u8 select:1; 1470 __u8 :7; 1471 #endif 1472 __u8 rsvd2[3]; 1473 __be32 addr; 1474 }; 1475 1476 struct cpl_tid_release { 1477 WR_HDR; 1478 union opcode_tid ot; 1479 __be32 rsvd; 1480 }; 1481 1482 struct cpl_barrier { 1483 WR_HDR; 1484 __u8 opcode; 1485 __u8 rsvd[7]; 1486 }; 1487 1488 struct cpl_rdma_read_req { 1489 __u8 opcode; 1490 __u8 rsvd[15]; 1491 }; 1492 1493 struct cpl_rdma_terminate { 1494 #ifdef CHELSIO_FW 1495 __u8 opcode; 1496 __u8 rsvd[2]; 1497 #if defined(__LITTLE_ENDIAN_BITFIELD) 1498 __u8 rspq:3; 1499 __u8 :5; 1500 #else 1501 __u8 :5; 1502 __u8 rspq:3; 1503 #endif 1504 __be32 tid_len; 1505 #endif 1506 __be32 msn; 1507 __be32 mo; 1508 __u8 data[0]; 1509 }; 1510 1511 /* cpl_rdma_terminate.tid_len fields */ 1512 #define S_FLIT_CNT 0 1513 #define M_FLIT_CNT 0xFF 1514 #define V_FLIT_CNT(x) ((x) << S_FLIT_CNT) 1515 #define G_FLIT_CNT(x) (((x) >> S_FLIT_CNT) & M_FLIT_CNT) 1516 1517 #define S_TERM_TID 8 1518 #define M_TERM_TID 0xFFFFF 1519 #define V_TERM_TID(x) ((x) << S_TERM_TID) 1520 #define G_TERM_TID(x) (((x) >> S_TERM_TID) & M_TERM_TID) 1521 1522 /* ULP_TX opcodes */ 1523 enum { ULP_MEM_READ = 2, ULP_MEM_WRITE = 3, ULP_TXPKT = 4 }; 1524 1525 #define S_ULPTX_CMD 28 1526 #define M_ULPTX_CMD 0xF 1527 #define V_ULPTX_CMD(x) ((x) << S_ULPTX_CMD) 1528 1529 #define S_ULPTX_NFLITS 0 1530 #define M_ULPTX_NFLITS 0xFF 1531 #define V_ULPTX_NFLITS(x) ((x) << S_ULPTX_NFLITS) 1532 1533 struct ulp_mem_io { 1534 WR_HDR; 1535 __be32 cmd_lock_addr; 1536 __be32 len; 1537 }; 1538 1539 /* ulp_mem_io.cmd_lock_addr fields */ 1540 #define S_ULP_MEMIO_ADDR 0 1541 #define M_ULP_MEMIO_ADDR 0x7FFFFFF 1542 #define V_ULP_MEMIO_ADDR(x) ((x) << S_ULP_MEMIO_ADDR) 1543 1544 #define S_ULP_MEMIO_LOCK 27 1545 #define V_ULP_MEMIO_LOCK(x) ((x) << S_ULP_MEMIO_LOCK) 1546 #define F_ULP_MEMIO_LOCK V_ULP_MEMIO_LOCK(1U) 1547 1548 /* ulp_mem_io.len fields */ 1549 #define S_ULP_MEMIO_DATA_LEN 28 1550 #define M_ULP_MEMIO_DATA_LEN 0xF 1551 #define V_ULP_MEMIO_DATA_LEN(x) ((x) << S_ULP_MEMIO_DATA_LEN) 1552 1553 struct ulp_txpkt { 1554 __be32 cmd_dest; 1555 __be32 len; 1556 }; 1557 1558 /* ulp_txpkt.cmd_dest fields */ 1559 #define S_ULP_TXPKT_DEST 24 1560 #define M_ULP_TXPKT_DEST 0xF 1561 #define V_ULP_TXPKT_DEST(x) ((x) << S_ULP_TXPKT_DEST) 1562 1563 #endif /* T3_CPL_H */ 1564