1 /************************************************************************** 2 3 Copyright (c) 2007, Chelsio Inc. 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Neither the name of the Chelsio Corporation nor the names of its 13 contributors may be used to endorse or promote products derived from 14 this software without specific prior written permission. 15 16 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 20 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 POSSIBILITY OF SUCH DAMAGE. 27 28 $FreeBSD$ 29 30 ***************************************************************************/ 31 /* This file is automatically generated --- do not edit */ 32 33 /* registers for module SGE3 */ 34 #define SGE3_BASE_ADDR 0x0 35 36 #define A_SG_CONTROL 0x0 37 38 #define S_EGRENUPBP 21 39 #define V_EGRENUPBP(x) ((x) << S_EGRENUPBP) 40 #define F_EGRENUPBP V_EGRENUPBP(1U) 41 42 #define S_DROPPKT 20 43 #define V_DROPPKT(x) ((x) << S_DROPPKT) 44 #define F_DROPPKT V_DROPPKT(1U) 45 46 #define S_EGRGENCTRL 19 47 #define V_EGRGENCTRL(x) ((x) << S_EGRGENCTRL) 48 #define F_EGRGENCTRL V_EGRGENCTRL(1U) 49 50 #define S_USERSPACESIZE 14 51 #define M_USERSPACESIZE 0x1f 52 #define V_USERSPACESIZE(x) ((x) << S_USERSPACESIZE) 53 #define G_USERSPACESIZE(x) (((x) >> S_USERSPACESIZE) & M_USERSPACESIZE) 54 55 #define S_HOSTPAGESIZE 11 56 #define M_HOSTPAGESIZE 0x7 57 #define V_HOSTPAGESIZE(x) ((x) << S_HOSTPAGESIZE) 58 #define G_HOSTPAGESIZE(x) (((x) >> S_HOSTPAGESIZE) & M_HOSTPAGESIZE) 59 60 #define S_PCIRELAX 10 61 #define V_PCIRELAX(x) ((x) << S_PCIRELAX) 62 #define F_PCIRELAX V_PCIRELAX(1U) 63 64 #define S_FLMODE 9 65 #define V_FLMODE(x) ((x) << S_FLMODE) 66 #define F_FLMODE V_FLMODE(1U) 67 68 #define S_PKTSHIFT 6 69 #define M_PKTSHIFT 0x7 70 #define V_PKTSHIFT(x) ((x) << S_PKTSHIFT) 71 #define G_PKTSHIFT(x) (((x) >> S_PKTSHIFT) & M_PKTSHIFT) 72 73 #define S_ONEINTMULTQ 5 74 #define V_ONEINTMULTQ(x) ((x) << S_ONEINTMULTQ) 75 #define F_ONEINTMULTQ V_ONEINTMULTQ(1U) 76 77 #define S_FLPICKAVAIL 4 78 #define V_FLPICKAVAIL(x) ((x) << S_FLPICKAVAIL) 79 #define F_FLPICKAVAIL V_FLPICKAVAIL(1U) 80 81 #define S_BIGENDIANEGRESS 3 82 #define V_BIGENDIANEGRESS(x) ((x) << S_BIGENDIANEGRESS) 83 #define F_BIGENDIANEGRESS V_BIGENDIANEGRESS(1U) 84 85 #define S_BIGENDIANINGRESS 2 86 #define V_BIGENDIANINGRESS(x) ((x) << S_BIGENDIANINGRESS) 87 #define F_BIGENDIANINGRESS V_BIGENDIANINGRESS(1U) 88 89 #define S_ISCSICOALESCING 1 90 #define V_ISCSICOALESCING(x) ((x) << S_ISCSICOALESCING) 91 #define F_ISCSICOALESCING V_ISCSICOALESCING(1U) 92 93 #define S_GLOBALENABLE 0 94 #define V_GLOBALENABLE(x) ((x) << S_GLOBALENABLE) 95 #define F_GLOBALENABLE V_GLOBALENABLE(1U) 96 97 #define S_URGTNL 26 98 #define V_URGTNL(x) ((x) << S_URGTNL) 99 #define F_URGTNL V_URGTNL(1U) 100 101 #define S_NEWNOTIFY 25 102 #define V_NEWNOTIFY(x) ((x) << S_NEWNOTIFY) 103 #define F_NEWNOTIFY V_NEWNOTIFY(1U) 104 105 #define S_AVOIDCQOVFL 24 106 #define V_AVOIDCQOVFL(x) ((x) << S_AVOIDCQOVFL) 107 #define F_AVOIDCQOVFL V_AVOIDCQOVFL(1U) 108 109 #define S_OPTONEINTMULTQ 23 110 #define V_OPTONEINTMULTQ(x) ((x) << S_OPTONEINTMULTQ) 111 #define F_OPTONEINTMULTQ V_OPTONEINTMULTQ(1U) 112 113 #define S_CQCRDTCTRL 22 114 #define V_CQCRDTCTRL(x) ((x) << S_CQCRDTCTRL) 115 #define F_CQCRDTCTRL V_CQCRDTCTRL(1U) 116 117 #define A_SG_KDOORBELL 0x4 118 119 #define S_SELEGRCNTX 31 120 #define V_SELEGRCNTX(x) ((x) << S_SELEGRCNTX) 121 #define F_SELEGRCNTX V_SELEGRCNTX(1U) 122 123 #define S_EGRCNTX 0 124 #define M_EGRCNTX 0xffff 125 #define V_EGRCNTX(x) ((x) << S_EGRCNTX) 126 #define G_EGRCNTX(x) (((x) >> S_EGRCNTX) & M_EGRCNTX) 127 128 #define A_SG_GTS 0x8 129 130 #define S_RSPQ 29 131 #define M_RSPQ 0x7 132 #define V_RSPQ(x) ((x) << S_RSPQ) 133 #define G_RSPQ(x) (((x) >> S_RSPQ) & M_RSPQ) 134 135 #define S_NEWTIMER 16 136 #define M_NEWTIMER 0x1fff 137 #define V_NEWTIMER(x) ((x) << S_NEWTIMER) 138 #define G_NEWTIMER(x) (((x) >> S_NEWTIMER) & M_NEWTIMER) 139 140 #define S_NEWINDEX 0 141 #define M_NEWINDEX 0xffff 142 #define V_NEWINDEX(x) ((x) << S_NEWINDEX) 143 #define G_NEWINDEX(x) (((x) >> S_NEWINDEX) & M_NEWINDEX) 144 145 #define A_SG_CONTEXT_CMD 0xc 146 147 #define S_CONTEXT_CMD_OPCODE 28 148 #define M_CONTEXT_CMD_OPCODE 0xf 149 #define V_CONTEXT_CMD_OPCODE(x) ((x) << S_CONTEXT_CMD_OPCODE) 150 #define G_CONTEXT_CMD_OPCODE(x) (((x) >> S_CONTEXT_CMD_OPCODE) & M_CONTEXT_CMD_OPCODE) 151 152 #define S_CONTEXT_CMD_BUSY 27 153 #define V_CONTEXT_CMD_BUSY(x) ((x) << S_CONTEXT_CMD_BUSY) 154 #define F_CONTEXT_CMD_BUSY V_CONTEXT_CMD_BUSY(1U) 155 156 #define S_CQ_CREDIT 20 157 #define M_CQ_CREDIT 0x7f 158 #define V_CQ_CREDIT(x) ((x) << S_CQ_CREDIT) 159 #define G_CQ_CREDIT(x) (((x) >> S_CQ_CREDIT) & M_CQ_CREDIT) 160 161 #define S_CQ 19 162 #define V_CQ(x) ((x) << S_CQ) 163 #define F_CQ V_CQ(1U) 164 165 #define S_RESPONSEQ 18 166 #define V_RESPONSEQ(x) ((x) << S_RESPONSEQ) 167 #define F_RESPONSEQ V_RESPONSEQ(1U) 168 169 #define S_EGRESS 17 170 #define V_EGRESS(x) ((x) << S_EGRESS) 171 #define F_EGRESS V_EGRESS(1U) 172 173 #define S_FREELIST 16 174 #define V_FREELIST(x) ((x) << S_FREELIST) 175 #define F_FREELIST V_FREELIST(1U) 176 177 #define S_CONTEXT 0 178 #define M_CONTEXT 0xffff 179 #define V_CONTEXT(x) ((x) << S_CONTEXT) 180 #define G_CONTEXT(x) (((x) >> S_CONTEXT) & M_CONTEXT) 181 182 #define A_SG_CONTEXT_DATA0 0x10 183 #define A_SG_CONTEXT_DATA1 0x14 184 #define A_SG_CONTEXT_DATA2 0x18 185 #define A_SG_CONTEXT_DATA3 0x1c 186 #define A_SG_CONTEXT_MASK0 0x20 187 #define A_SG_CONTEXT_MASK1 0x24 188 #define A_SG_CONTEXT_MASK2 0x28 189 #define A_SG_CONTEXT_MASK3 0x2c 190 #define A_SG_RSPQ_CREDIT_RETURN 0x30 191 192 #define S_CREDITS 0 193 #define M_CREDITS 0xffff 194 #define V_CREDITS(x) ((x) << S_CREDITS) 195 #define G_CREDITS(x) (((x) >> S_CREDITS) & M_CREDITS) 196 197 #define A_SG_DATA_INTR 0x34 198 199 #define S_ERRINTR 31 200 #define V_ERRINTR(x) ((x) << S_ERRINTR) 201 #define F_ERRINTR V_ERRINTR(1U) 202 203 #define S_DATAINTR 0 204 #define M_DATAINTR 0xff 205 #define V_DATAINTR(x) ((x) << S_DATAINTR) 206 #define G_DATAINTR(x) (((x) >> S_DATAINTR) & M_DATAINTR) 207 208 #define A_SG_HI_DRB_HI_THRSH 0x38 209 210 #define S_HIDRBHITHRSH 0 211 #define M_HIDRBHITHRSH 0x3ff 212 #define V_HIDRBHITHRSH(x) ((x) << S_HIDRBHITHRSH) 213 #define G_HIDRBHITHRSH(x) (((x) >> S_HIDRBHITHRSH) & M_HIDRBHITHRSH) 214 215 #define A_SG_HI_DRB_LO_THRSH 0x3c 216 217 #define S_HIDRBLOTHRSH 0 218 #define M_HIDRBLOTHRSH 0x3ff 219 #define V_HIDRBLOTHRSH(x) ((x) << S_HIDRBLOTHRSH) 220 #define G_HIDRBLOTHRSH(x) (((x) >> S_HIDRBLOTHRSH) & M_HIDRBLOTHRSH) 221 222 #define A_SG_LO_DRB_HI_THRSH 0x40 223 224 #define S_LODRBHITHRSH 0 225 #define M_LODRBHITHRSH 0x3ff 226 #define V_LODRBHITHRSH(x) ((x) << S_LODRBHITHRSH) 227 #define G_LODRBHITHRSH(x) (((x) >> S_LODRBHITHRSH) & M_LODRBHITHRSH) 228 229 #define A_SG_LO_DRB_LO_THRSH 0x44 230 231 #define S_LODRBLOTHRSH 0 232 #define M_LODRBLOTHRSH 0x3ff 233 #define V_LODRBLOTHRSH(x) ((x) << S_LODRBLOTHRSH) 234 #define G_LODRBLOTHRSH(x) (((x) >> S_LODRBLOTHRSH) & M_LODRBLOTHRSH) 235 236 #define A_SG_ONE_INT_MULT_Q_COALESCING_TIMER 0x48 237 #define A_SG_RSPQ_FL_STATUS 0x4c 238 239 #define S_RSPQ0STARVED 0 240 #define V_RSPQ0STARVED(x) ((x) << S_RSPQ0STARVED) 241 #define F_RSPQ0STARVED V_RSPQ0STARVED(1U) 242 243 #define S_RSPQ1STARVED 1 244 #define V_RSPQ1STARVED(x) ((x) << S_RSPQ1STARVED) 245 #define F_RSPQ1STARVED V_RSPQ1STARVED(1U) 246 247 #define S_RSPQ2STARVED 2 248 #define V_RSPQ2STARVED(x) ((x) << S_RSPQ2STARVED) 249 #define F_RSPQ2STARVED V_RSPQ2STARVED(1U) 250 251 #define S_RSPQ3STARVED 3 252 #define V_RSPQ3STARVED(x) ((x) << S_RSPQ3STARVED) 253 #define F_RSPQ3STARVED V_RSPQ3STARVED(1U) 254 255 #define S_RSPQ4STARVED 4 256 #define V_RSPQ4STARVED(x) ((x) << S_RSPQ4STARVED) 257 #define F_RSPQ4STARVED V_RSPQ4STARVED(1U) 258 259 #define S_RSPQ5STARVED 5 260 #define V_RSPQ5STARVED(x) ((x) << S_RSPQ5STARVED) 261 #define F_RSPQ5STARVED V_RSPQ5STARVED(1U) 262 263 #define S_RSPQ6STARVED 6 264 #define V_RSPQ6STARVED(x) ((x) << S_RSPQ6STARVED) 265 #define F_RSPQ6STARVED V_RSPQ6STARVED(1U) 266 267 #define S_RSPQ7STARVED 7 268 #define V_RSPQ7STARVED(x) ((x) << S_RSPQ7STARVED) 269 #define F_RSPQ7STARVED V_RSPQ7STARVED(1U) 270 271 #define S_RSPQ0DISABLED 8 272 #define V_RSPQ0DISABLED(x) ((x) << S_RSPQ0DISABLED) 273 #define F_RSPQ0DISABLED V_RSPQ0DISABLED(1U) 274 275 #define S_RSPQ1DISABLED 9 276 #define V_RSPQ1DISABLED(x) ((x) << S_RSPQ1DISABLED) 277 #define F_RSPQ1DISABLED V_RSPQ1DISABLED(1U) 278 279 #define S_RSPQ2DISABLED 10 280 #define V_RSPQ2DISABLED(x) ((x) << S_RSPQ2DISABLED) 281 #define F_RSPQ2DISABLED V_RSPQ2DISABLED(1U) 282 283 #define S_RSPQ3DISABLED 11 284 #define V_RSPQ3DISABLED(x) ((x) << S_RSPQ3DISABLED) 285 #define F_RSPQ3DISABLED V_RSPQ3DISABLED(1U) 286 287 #define S_RSPQ4DISABLED 12 288 #define V_RSPQ4DISABLED(x) ((x) << S_RSPQ4DISABLED) 289 #define F_RSPQ4DISABLED V_RSPQ4DISABLED(1U) 290 291 #define S_RSPQ5DISABLED 13 292 #define V_RSPQ5DISABLED(x) ((x) << S_RSPQ5DISABLED) 293 #define F_RSPQ5DISABLED V_RSPQ5DISABLED(1U) 294 295 #define S_RSPQ6DISABLED 14 296 #define V_RSPQ6DISABLED(x) ((x) << S_RSPQ6DISABLED) 297 #define F_RSPQ6DISABLED V_RSPQ6DISABLED(1U) 298 299 #define S_RSPQ7DISABLED 15 300 #define V_RSPQ7DISABLED(x) ((x) << S_RSPQ7DISABLED) 301 #define F_RSPQ7DISABLED V_RSPQ7DISABLED(1U) 302 303 #define S_FL0EMPTY 16 304 #define V_FL0EMPTY(x) ((x) << S_FL0EMPTY) 305 #define F_FL0EMPTY V_FL0EMPTY(1U) 306 307 #define S_FL1EMPTY 17 308 #define V_FL1EMPTY(x) ((x) << S_FL1EMPTY) 309 #define F_FL1EMPTY V_FL1EMPTY(1U) 310 311 #define S_FL2EMPTY 18 312 #define V_FL2EMPTY(x) ((x) << S_FL2EMPTY) 313 #define F_FL2EMPTY V_FL2EMPTY(1U) 314 315 #define S_FL3EMPTY 19 316 #define V_FL3EMPTY(x) ((x) << S_FL3EMPTY) 317 #define F_FL3EMPTY V_FL3EMPTY(1U) 318 319 #define S_FL4EMPTY 20 320 #define V_FL4EMPTY(x) ((x) << S_FL4EMPTY) 321 #define F_FL4EMPTY V_FL4EMPTY(1U) 322 323 #define S_FL5EMPTY 21 324 #define V_FL5EMPTY(x) ((x) << S_FL5EMPTY) 325 #define F_FL5EMPTY V_FL5EMPTY(1U) 326 327 #define S_FL6EMPTY 22 328 #define V_FL6EMPTY(x) ((x) << S_FL6EMPTY) 329 #define F_FL6EMPTY V_FL6EMPTY(1U) 330 331 #define S_FL7EMPTY 23 332 #define V_FL7EMPTY(x) ((x) << S_FL7EMPTY) 333 #define F_FL7EMPTY V_FL7EMPTY(1U) 334 335 #define S_FL8EMPTY 24 336 #define V_FL8EMPTY(x) ((x) << S_FL8EMPTY) 337 #define F_FL8EMPTY V_FL8EMPTY(1U) 338 339 #define S_FL9EMPTY 25 340 #define V_FL9EMPTY(x) ((x) << S_FL9EMPTY) 341 #define F_FL9EMPTY V_FL9EMPTY(1U) 342 343 #define S_FL10EMPTY 26 344 #define V_FL10EMPTY(x) ((x) << S_FL10EMPTY) 345 #define F_FL10EMPTY V_FL10EMPTY(1U) 346 347 #define S_FL11EMPTY 27 348 #define V_FL11EMPTY(x) ((x) << S_FL11EMPTY) 349 #define F_FL11EMPTY V_FL11EMPTY(1U) 350 351 #define S_FL12EMPTY 28 352 #define V_FL12EMPTY(x) ((x) << S_FL12EMPTY) 353 #define F_FL12EMPTY V_FL12EMPTY(1U) 354 355 #define S_FL13EMPTY 29 356 #define V_FL13EMPTY(x) ((x) << S_FL13EMPTY) 357 #define F_FL13EMPTY V_FL13EMPTY(1U) 358 359 #define S_FL14EMPTY 30 360 #define V_FL14EMPTY(x) ((x) << S_FL14EMPTY) 361 #define F_FL14EMPTY V_FL14EMPTY(1U) 362 363 #define S_FL15EMPTY 31 364 #define V_FL15EMPTY(x) ((x) << S_FL15EMPTY) 365 #define F_FL15EMPTY V_FL15EMPTY(1U) 366 367 #define A_SG_EGR_PRI_CNT 0x50 368 369 #define S_EGRPRICNT 0 370 #define M_EGRPRICNT 0x1f 371 #define V_EGRPRICNT(x) ((x) << S_EGRPRICNT) 372 #define G_EGRPRICNT(x) (((x) >> S_EGRPRICNT) & M_EGRPRICNT) 373 374 #define S_EGRERROPCODE 24 375 #define M_EGRERROPCODE 0xff 376 #define V_EGRERROPCODE(x) ((x) << S_EGRERROPCODE) 377 #define G_EGRERROPCODE(x) (((x) >> S_EGRERROPCODE) & M_EGRERROPCODE) 378 379 #define S_EGRHIOPCODE 16 380 #define M_EGRHIOPCODE 0xff 381 #define V_EGRHIOPCODE(x) ((x) << S_EGRHIOPCODE) 382 #define G_EGRHIOPCODE(x) (((x) >> S_EGRHIOPCODE) & M_EGRHIOPCODE) 383 384 #define S_EGRLOOPCODE 8 385 #define M_EGRLOOPCODE 0xff 386 #define V_EGRLOOPCODE(x) ((x) << S_EGRLOOPCODE) 387 #define G_EGRLOOPCODE(x) (((x) >> S_EGRLOOPCODE) & M_EGRLOOPCODE) 388 389 #define A_SG_EGR_RCQ_DRB_THRSH 0x54 390 391 #define S_HIRCQDRBTHRSH 16 392 #define M_HIRCQDRBTHRSH 0x7ff 393 #define V_HIRCQDRBTHRSH(x) ((x) << S_HIRCQDRBTHRSH) 394 #define G_HIRCQDRBTHRSH(x) (((x) >> S_HIRCQDRBTHRSH) & M_HIRCQDRBTHRSH) 395 396 #define S_LORCQDRBTHRSH 0 397 #define M_LORCQDRBTHRSH 0x7ff 398 #define V_LORCQDRBTHRSH(x) ((x) << S_LORCQDRBTHRSH) 399 #define G_LORCQDRBTHRSH(x) (((x) >> S_LORCQDRBTHRSH) & M_LORCQDRBTHRSH) 400 401 #define A_SG_EGR_CNTX_BADDR 0x58 402 403 #define S_EGRCNTXBADDR 5 404 #define M_EGRCNTXBADDR 0x7ffffff 405 #define V_EGRCNTXBADDR(x) ((x) << S_EGRCNTXBADDR) 406 #define G_EGRCNTXBADDR(x) (((x) >> S_EGRCNTXBADDR) & M_EGRCNTXBADDR) 407 408 #define A_SG_INT_CAUSE 0x5c 409 410 #define S_HICTLDRBDROPERR 13 411 #define V_HICTLDRBDROPERR(x) ((x) << S_HICTLDRBDROPERR) 412 #define F_HICTLDRBDROPERR V_HICTLDRBDROPERR(1U) 413 414 #define S_LOCTLDRBDROPERR 12 415 #define V_LOCTLDRBDROPERR(x) ((x) << S_LOCTLDRBDROPERR) 416 #define F_LOCTLDRBDROPERR V_LOCTLDRBDROPERR(1U) 417 418 #define S_HIPIODRBDROPERR 11 419 #define V_HIPIODRBDROPERR(x) ((x) << S_HIPIODRBDROPERR) 420 #define F_HIPIODRBDROPERR V_HIPIODRBDROPERR(1U) 421 422 #define S_LOPIODRBDROPERR 10 423 #define V_LOPIODRBDROPERR(x) ((x) << S_LOPIODRBDROPERR) 424 #define F_LOPIODRBDROPERR V_LOPIODRBDROPERR(1U) 425 426 #define S_HICRDTUNDFLOWERR 9 427 #define V_HICRDTUNDFLOWERR(x) ((x) << S_HICRDTUNDFLOWERR) 428 #define F_HICRDTUNDFLOWERR V_HICRDTUNDFLOWERR(1U) 429 430 #define S_LOCRDTUNDFLOWERR 8 431 #define V_LOCRDTUNDFLOWERR(x) ((x) << S_LOCRDTUNDFLOWERR) 432 #define F_LOCRDTUNDFLOWERR V_LOCRDTUNDFLOWERR(1U) 433 434 #define S_HIPRIORITYDBFULL 7 435 #define V_HIPRIORITYDBFULL(x) ((x) << S_HIPRIORITYDBFULL) 436 #define F_HIPRIORITYDBFULL V_HIPRIORITYDBFULL(1U) 437 438 #define S_HIPRIORITYDBEMPTY 6 439 #define V_HIPRIORITYDBEMPTY(x) ((x) << S_HIPRIORITYDBEMPTY) 440 #define F_HIPRIORITYDBEMPTY V_HIPRIORITYDBEMPTY(1U) 441 442 #define S_LOPRIORITYDBFULL 5 443 #define V_LOPRIORITYDBFULL(x) ((x) << S_LOPRIORITYDBFULL) 444 #define F_LOPRIORITYDBFULL V_LOPRIORITYDBFULL(1U) 445 446 #define S_LOPRIORITYDBEMPTY 4 447 #define V_LOPRIORITYDBEMPTY(x) ((x) << S_LOPRIORITYDBEMPTY) 448 #define F_LOPRIORITYDBEMPTY V_LOPRIORITYDBEMPTY(1U) 449 450 #define S_RSPQDISABLED 3 451 #define V_RSPQDISABLED(x) ((x) << S_RSPQDISABLED) 452 #define F_RSPQDISABLED V_RSPQDISABLED(1U) 453 454 #define S_RSPQCREDITOVERFOW 2 455 #define V_RSPQCREDITOVERFOW(x) ((x) << S_RSPQCREDITOVERFOW) 456 #define F_RSPQCREDITOVERFOW V_RSPQCREDITOVERFOW(1U) 457 458 #define S_FLEMPTY 1 459 #define V_FLEMPTY(x) ((x) << S_FLEMPTY) 460 #define F_FLEMPTY V_FLEMPTY(1U) 461 462 #define S_RSPQSTARVE 0 463 #define V_RSPQSTARVE(x) ((x) << S_RSPQSTARVE) 464 #define F_RSPQSTARVE V_RSPQSTARVE(1U) 465 466 #define A_SG_INT_ENABLE 0x60 467 #define A_SG_CMDQ_CREDIT_TH 0x64 468 469 #define S_TIMEOUT 8 470 #define M_TIMEOUT 0xffffff 471 #define V_TIMEOUT(x) ((x) << S_TIMEOUT) 472 #define G_TIMEOUT(x) (((x) >> S_TIMEOUT) & M_TIMEOUT) 473 474 #define S_THRESHOLD 0 475 #define M_THRESHOLD 0xff 476 #define V_THRESHOLD(x) ((x) << S_THRESHOLD) 477 #define G_THRESHOLD(x) (((x) >> S_THRESHOLD) & M_THRESHOLD) 478 479 #define A_SG_TIMER_TICK 0x68 480 #define A_SG_CQ_CONTEXT_BADDR 0x6c 481 482 #define S_BASEADDR 5 483 #define M_BASEADDR 0x7ffffff 484 #define V_BASEADDR(x) ((x) << S_BASEADDR) 485 #define G_BASEADDR(x) (((x) >> S_BASEADDR) & M_BASEADDR) 486 487 #define A_SG_OCO_BASE 0x70 488 489 #define S_BASE1 16 490 #define M_BASE1 0xffff 491 #define V_BASE1(x) ((x) << S_BASE1) 492 #define G_BASE1(x) (((x) >> S_BASE1) & M_BASE1) 493 494 #define S_BASE0 0 495 #define M_BASE0 0xffff 496 #define V_BASE0(x) ((x) << S_BASE0) 497 #define G_BASE0(x) (((x) >> S_BASE0) & M_BASE0) 498 499 #define A_SG_DRB_PRI_THRESH 0x74 500 501 #define S_DRBPRITHRSH 0 502 #define M_DRBPRITHRSH 0xffff 503 #define V_DRBPRITHRSH(x) ((x) << S_DRBPRITHRSH) 504 #define G_DRBPRITHRSH(x) (((x) >> S_DRBPRITHRSH) & M_DRBPRITHRSH) 505 506 #define A_SG_DEBUG_INDEX 0x78 507 #define A_SG_DEBUG_DATA 0x7c 508 509 /* registers for module PCIX1 */ 510 #define PCIX1_BASE_ADDR 0x80 511 512 #define A_PCIX_INT_ENABLE 0x80 513 514 #define S_MSIXPARERR 22 515 #define M_MSIXPARERR 0x7 516 #define V_MSIXPARERR(x) ((x) << S_MSIXPARERR) 517 #define G_MSIXPARERR(x) (((x) >> S_MSIXPARERR) & M_MSIXPARERR) 518 519 #define S_CFPARERR 18 520 #define M_CFPARERR 0xf 521 #define V_CFPARERR(x) ((x) << S_CFPARERR) 522 #define G_CFPARERR(x) (((x) >> S_CFPARERR) & M_CFPARERR) 523 524 #define S_RFPARERR 14 525 #define M_RFPARERR 0xf 526 #define V_RFPARERR(x) ((x) << S_RFPARERR) 527 #define G_RFPARERR(x) (((x) >> S_RFPARERR) & M_RFPARERR) 528 529 #define S_WFPARERR 12 530 #define M_WFPARERR 0x3 531 #define V_WFPARERR(x) ((x) << S_WFPARERR) 532 #define G_WFPARERR(x) (((x) >> S_WFPARERR) & M_WFPARERR) 533 534 #define S_PIOPARERR 11 535 #define V_PIOPARERR(x) ((x) << S_PIOPARERR) 536 #define F_PIOPARERR V_PIOPARERR(1U) 537 538 #define S_DETUNCECCERR 10 539 #define V_DETUNCECCERR(x) ((x) << S_DETUNCECCERR) 540 #define F_DETUNCECCERR V_DETUNCECCERR(1U) 541 542 #define S_DETCORECCERR 9 543 #define V_DETCORECCERR(x) ((x) << S_DETCORECCERR) 544 #define F_DETCORECCERR V_DETCORECCERR(1U) 545 546 #define S_RCVSPLCMPERR 8 547 #define V_RCVSPLCMPERR(x) ((x) << S_RCVSPLCMPERR) 548 #define F_RCVSPLCMPERR V_RCVSPLCMPERR(1U) 549 550 #define S_UNXSPLCMP 7 551 #define V_UNXSPLCMP(x) ((x) << S_UNXSPLCMP) 552 #define F_UNXSPLCMP V_UNXSPLCMP(1U) 553 554 #define S_SPLCMPDIS 6 555 #define V_SPLCMPDIS(x) ((x) << S_SPLCMPDIS) 556 #define F_SPLCMPDIS V_SPLCMPDIS(1U) 557 558 #define S_DETPARERR 5 559 #define V_DETPARERR(x) ((x) << S_DETPARERR) 560 #define F_DETPARERR V_DETPARERR(1U) 561 562 #define S_SIGSYSERR 4 563 #define V_SIGSYSERR(x) ((x) << S_SIGSYSERR) 564 #define F_SIGSYSERR V_SIGSYSERR(1U) 565 566 #define S_RCVMSTABT 3 567 #define V_RCVMSTABT(x) ((x) << S_RCVMSTABT) 568 #define F_RCVMSTABT V_RCVMSTABT(1U) 569 570 #define S_RCVTARABT 2 571 #define V_RCVTARABT(x) ((x) << S_RCVTARABT) 572 #define F_RCVTARABT V_RCVTARABT(1U) 573 574 #define S_SIGTARABT 1 575 #define V_SIGTARABT(x) ((x) << S_SIGTARABT) 576 #define F_SIGTARABT V_SIGTARABT(1U) 577 578 #define S_MSTDETPARERR 0 579 #define V_MSTDETPARERR(x) ((x) << S_MSTDETPARERR) 580 #define F_MSTDETPARERR V_MSTDETPARERR(1U) 581 582 #define A_PCIX_INT_CAUSE 0x84 583 #define A_PCIX_CFG 0x88 584 585 #define S_CLIDECEN 18 586 #define V_CLIDECEN(x) ((x) << S_CLIDECEN) 587 #define F_CLIDECEN V_CLIDECEN(1U) 588 589 #define S_LATTMRDIS 17 590 #define V_LATTMRDIS(x) ((x) << S_LATTMRDIS) 591 #define F_LATTMRDIS V_LATTMRDIS(1U) 592 593 #define S_LOWPWREN 16 594 #define V_LOWPWREN(x) ((x) << S_LOWPWREN) 595 #define F_LOWPWREN V_LOWPWREN(1U) 596 597 #define S_ASYNCINTVEC 11 598 #define M_ASYNCINTVEC 0x1f 599 #define V_ASYNCINTVEC(x) ((x) << S_ASYNCINTVEC) 600 #define G_ASYNCINTVEC(x) (((x) >> S_ASYNCINTVEC) & M_ASYNCINTVEC) 601 602 #define S_MAXSPLTRNC 8 603 #define M_MAXSPLTRNC 0x7 604 #define V_MAXSPLTRNC(x) ((x) << S_MAXSPLTRNC) 605 #define G_MAXSPLTRNC(x) (((x) >> S_MAXSPLTRNC) & M_MAXSPLTRNC) 606 607 #define S_MAXSPLTRNR 5 608 #define M_MAXSPLTRNR 0x7 609 #define V_MAXSPLTRNR(x) ((x) << S_MAXSPLTRNR) 610 #define G_MAXSPLTRNR(x) (((x) >> S_MAXSPLTRNR) & M_MAXSPLTRNR) 611 612 #define S_MAXWRBYTECNT 3 613 #define M_MAXWRBYTECNT 0x3 614 #define V_MAXWRBYTECNT(x) ((x) << S_MAXWRBYTECNT) 615 #define G_MAXWRBYTECNT(x) (((x) >> S_MAXWRBYTECNT) & M_MAXWRBYTECNT) 616 617 #define S_WRREQATOMICEN 2 618 #define V_WRREQATOMICEN(x) ((x) << S_WRREQATOMICEN) 619 #define F_WRREQATOMICEN V_WRREQATOMICEN(1U) 620 621 #define S_RSTWRMMODE 1 622 #define V_RSTWRMMODE(x) ((x) << S_RSTWRMMODE) 623 #define F_RSTWRMMODE V_RSTWRMMODE(1U) 624 625 #define S_PIOACK64EN 0 626 #define V_PIOACK64EN(x) ((x) << S_PIOACK64EN) 627 #define F_PIOACK64EN V_PIOACK64EN(1U) 628 629 #define A_PCIX_MODE 0x8c 630 631 #define S_PCLKRANGE 6 632 #define M_PCLKRANGE 0x3 633 #define V_PCLKRANGE(x) ((x) << S_PCLKRANGE) 634 #define G_PCLKRANGE(x) (((x) >> S_PCLKRANGE) & M_PCLKRANGE) 635 636 #define S_PCIXINITPAT 2 637 #define M_PCIXINITPAT 0xf 638 #define V_PCIXINITPAT(x) ((x) << S_PCIXINITPAT) 639 #define G_PCIXINITPAT(x) (((x) >> S_PCIXINITPAT) & M_PCIXINITPAT) 640 641 #define S_66MHZ 1 642 #define V_66MHZ(x) ((x) << S_66MHZ) 643 #define F_66MHZ V_66MHZ(1U) 644 645 #define S_64BIT 0 646 #define V_64BIT(x) ((x) << S_64BIT) 647 #define F_64BIT V_64BIT(1U) 648 649 #define A_PCIX_CAL 0x90 650 651 #define S_BUSY 31 652 #define V_BUSY(x) ((x) << S_BUSY) 653 #define F_BUSY V_BUSY(1U) 654 655 #define S_PERCALDIV 22 656 #define M_PERCALDIV 0xff 657 #define V_PERCALDIV(x) ((x) << S_PERCALDIV) 658 #define G_PERCALDIV(x) (((x) >> S_PERCALDIV) & M_PERCALDIV) 659 660 #define S_PERCALEN 21 661 #define V_PERCALEN(x) ((x) << S_PERCALEN) 662 #define F_PERCALEN V_PERCALEN(1U) 663 664 #define S_SGLCALEN 20 665 #define V_SGLCALEN(x) ((x) << S_SGLCALEN) 666 #define F_SGLCALEN V_SGLCALEN(1U) 667 668 #define S_ZINUPDMODE 19 669 #define V_ZINUPDMODE(x) ((x) << S_ZINUPDMODE) 670 #define F_ZINUPDMODE V_ZINUPDMODE(1U) 671 672 #define S_ZINSEL 18 673 #define V_ZINSEL(x) ((x) << S_ZINSEL) 674 #define F_ZINSEL V_ZINSEL(1U) 675 676 #define S_ZPDMAN 15 677 #define M_ZPDMAN 0x7 678 #define V_ZPDMAN(x) ((x) << S_ZPDMAN) 679 #define G_ZPDMAN(x) (((x) >> S_ZPDMAN) & M_ZPDMAN) 680 681 #define S_ZPUMAN 12 682 #define M_ZPUMAN 0x7 683 #define V_ZPUMAN(x) ((x) << S_ZPUMAN) 684 #define G_ZPUMAN(x) (((x) >> S_ZPUMAN) & M_ZPUMAN) 685 686 #define S_ZPDOUT 9 687 #define M_ZPDOUT 0x7 688 #define V_ZPDOUT(x) ((x) << S_ZPDOUT) 689 #define G_ZPDOUT(x) (((x) >> S_ZPDOUT) & M_ZPDOUT) 690 691 #define S_ZPUOUT 6 692 #define M_ZPUOUT 0x7 693 #define V_ZPUOUT(x) ((x) << S_ZPUOUT) 694 #define G_ZPUOUT(x) (((x) >> S_ZPUOUT) & M_ZPUOUT) 695 696 #define S_ZPDIN 3 697 #define M_ZPDIN 0x7 698 #define V_ZPDIN(x) ((x) << S_ZPDIN) 699 #define G_ZPDIN(x) (((x) >> S_ZPDIN) & M_ZPDIN) 700 701 #define S_ZPUIN 0 702 #define M_ZPUIN 0x7 703 #define V_ZPUIN(x) ((x) << S_ZPUIN) 704 #define G_ZPUIN(x) (((x) >> S_ZPUIN) & M_ZPUIN) 705 706 #define A_PCIX_WOL 0x94 707 708 #define S_WAKEUP1 3 709 #define V_WAKEUP1(x) ((x) << S_WAKEUP1) 710 #define F_WAKEUP1 V_WAKEUP1(1U) 711 712 #define S_WAKEUP0 2 713 #define V_WAKEUP0(x) ((x) << S_WAKEUP0) 714 #define F_WAKEUP0 V_WAKEUP0(1U) 715 716 #define S_SLEEPMODE1 1 717 #define V_SLEEPMODE1(x) ((x) << S_SLEEPMODE1) 718 #define F_SLEEPMODE1 V_SLEEPMODE1(1U) 719 720 #define S_SLEEPMODE0 0 721 #define V_SLEEPMODE0(x) ((x) << S_SLEEPMODE0) 722 #define F_SLEEPMODE0 V_SLEEPMODE0(1U) 723 724 /* registers for module PCIE0 */ 725 #define PCIE0_BASE_ADDR 0x80 726 727 #define A_PCIE_INT_ENABLE 0x80 728 729 #define S_BISTERR 15 730 #define M_BISTERR 0xff 731 #define V_BISTERR(x) ((x) << S_BISTERR) 732 #define G_BISTERR(x) (((x) >> S_BISTERR) & M_BISTERR) 733 734 #define S_PCIE_MSIXPARERR 12 735 #define M_PCIE_MSIXPARERR 0x7 736 #define V_PCIE_MSIXPARERR(x) ((x) << S_PCIE_MSIXPARERR) 737 #define G_PCIE_MSIXPARERR(x) (((x) >> S_PCIE_MSIXPARERR) & M_PCIE_MSIXPARERR) 738 739 #define S_PCIE_CFPARERR 11 740 #define V_PCIE_CFPARERR(x) ((x) << S_PCIE_CFPARERR) 741 #define F_PCIE_CFPARERR V_PCIE_CFPARERR(1U) 742 743 #define S_PCIE_RFPARERR 10 744 #define V_PCIE_RFPARERR(x) ((x) << S_PCIE_RFPARERR) 745 #define F_PCIE_RFPARERR V_PCIE_RFPARERR(1U) 746 747 #define S_PCIE_WFPARERR 9 748 #define V_PCIE_WFPARERR(x) ((x) << S_PCIE_WFPARERR) 749 #define F_PCIE_WFPARERR V_PCIE_WFPARERR(1U) 750 751 #define S_PCIE_PIOPARERR 8 752 #define V_PCIE_PIOPARERR(x) ((x) << S_PCIE_PIOPARERR) 753 #define F_PCIE_PIOPARERR V_PCIE_PIOPARERR(1U) 754 755 #define S_UNXSPLCPLERRC 7 756 #define V_UNXSPLCPLERRC(x) ((x) << S_UNXSPLCPLERRC) 757 #define F_UNXSPLCPLERRC V_UNXSPLCPLERRC(1U) 758 759 #define S_UNXSPLCPLERRR 6 760 #define V_UNXSPLCPLERRR(x) ((x) << S_UNXSPLCPLERRR) 761 #define F_UNXSPLCPLERRR V_UNXSPLCPLERRR(1U) 762 763 #define S_VPDADDRCHNG 5 764 #define V_VPDADDRCHNG(x) ((x) << S_VPDADDRCHNG) 765 #define F_VPDADDRCHNG V_VPDADDRCHNG(1U) 766 767 #define S_BUSMSTREN 4 768 #define V_BUSMSTREN(x) ((x) << S_BUSMSTREN) 769 #define F_BUSMSTREN V_BUSMSTREN(1U) 770 771 #define S_PMSTCHNG 3 772 #define V_PMSTCHNG(x) ((x) << S_PMSTCHNG) 773 #define F_PMSTCHNG V_PMSTCHNG(1U) 774 775 #define S_PEXMSG 2 776 #define V_PEXMSG(x) ((x) << S_PEXMSG) 777 #define F_PEXMSG V_PEXMSG(1U) 778 779 #define S_ZEROLENRD 1 780 #define V_ZEROLENRD(x) ((x) << S_ZEROLENRD) 781 #define F_ZEROLENRD V_ZEROLENRD(1U) 782 783 #define S_PEXERR 0 784 #define V_PEXERR(x) ((x) << S_PEXERR) 785 #define F_PEXERR V_PEXERR(1U) 786 787 #define A_PCIE_INT_CAUSE 0x84 788 #define A_PCIE_CFG 0x88 789 790 #define S_ENABLELINKDWNDRST 21 791 #define V_ENABLELINKDWNDRST(x) ((x) << S_ENABLELINKDWNDRST) 792 #define F_ENABLELINKDWNDRST V_ENABLELINKDWNDRST(1U) 793 794 #define S_ENABLELINKDOWNRST 20 795 #define V_ENABLELINKDOWNRST(x) ((x) << S_ENABLELINKDOWNRST) 796 #define F_ENABLELINKDOWNRST V_ENABLELINKDOWNRST(1U) 797 798 #define S_ENABLEHOTRST 19 799 #define V_ENABLEHOTRST(x) ((x) << S_ENABLEHOTRST) 800 #define F_ENABLEHOTRST V_ENABLEHOTRST(1U) 801 802 #define S_INIWAITFORGNT 18 803 #define V_INIWAITFORGNT(x) ((x) << S_INIWAITFORGNT) 804 #define F_INIWAITFORGNT V_INIWAITFORGNT(1U) 805 806 #define S_INIBEDIS 17 807 #define V_INIBEDIS(x) ((x) << S_INIBEDIS) 808 #define F_INIBEDIS V_INIBEDIS(1U) 809 810 #define S_PCIE_CLIDECEN 16 811 #define V_PCIE_CLIDECEN(x) ((x) << S_PCIE_CLIDECEN) 812 #define F_PCIE_CLIDECEN V_PCIE_CLIDECEN(1U) 813 814 #define S_PCIE_MAXSPLTRNC 7 815 #define M_PCIE_MAXSPLTRNC 0xf 816 #define V_PCIE_MAXSPLTRNC(x) ((x) << S_PCIE_MAXSPLTRNC) 817 #define G_PCIE_MAXSPLTRNC(x) (((x) >> S_PCIE_MAXSPLTRNC) & M_PCIE_MAXSPLTRNC) 818 819 #define S_PCIE_MAXSPLTRNR 1 820 #define M_PCIE_MAXSPLTRNR 0x3f 821 #define V_PCIE_MAXSPLTRNR(x) ((x) << S_PCIE_MAXSPLTRNR) 822 #define G_PCIE_MAXSPLTRNR(x) (((x) >> S_PCIE_MAXSPLTRNR) & M_PCIE_MAXSPLTRNR) 823 824 #define S_CRSTWRMMODE 0 825 #define V_CRSTWRMMODE(x) ((x) << S_CRSTWRMMODE) 826 #define F_CRSTWRMMODE V_CRSTWRMMODE(1U) 827 828 #define S_PRIORITYINTA 23 829 #define V_PRIORITYINTA(x) ((x) << S_PRIORITYINTA) 830 #define F_PRIORITYINTA V_PRIORITYINTA(1U) 831 832 #define S_INIFULLPKT 22 833 #define V_INIFULLPKT(x) ((x) << S_INIFULLPKT) 834 #define F_INIFULLPKT V_INIFULLPKT(1U) 835 836 #define A_PCIE_MODE 0x8c 837 838 #define S_LNKCNTLSTATE 2 839 #define M_LNKCNTLSTATE 0xff 840 #define V_LNKCNTLSTATE(x) ((x) << S_LNKCNTLSTATE) 841 #define G_LNKCNTLSTATE(x) (((x) >> S_LNKCNTLSTATE) & M_LNKCNTLSTATE) 842 843 #define S_VC0UP 1 844 #define V_VC0UP(x) ((x) << S_VC0UP) 845 #define F_VC0UP V_VC0UP(1U) 846 847 #define S_LNKINITIAL 0 848 #define V_LNKINITIAL(x) ((x) << S_LNKINITIAL) 849 #define F_LNKINITIAL V_LNKINITIAL(1U) 850 851 #define S_NUMFSTTRNSEQRX 10 852 #define M_NUMFSTTRNSEQRX 0xff 853 #define V_NUMFSTTRNSEQRX(x) ((x) << S_NUMFSTTRNSEQRX) 854 #define G_NUMFSTTRNSEQRX(x) (((x) >> S_NUMFSTTRNSEQRX) & M_NUMFSTTRNSEQRX) 855 856 #define A_PCIE_CAL 0x90 857 858 #define S_CALBUSY 31 859 #define V_CALBUSY(x) ((x) << S_CALBUSY) 860 #define F_CALBUSY V_CALBUSY(1U) 861 862 #define S_CALFAULT 30 863 #define V_CALFAULT(x) ((x) << S_CALFAULT) 864 #define F_CALFAULT V_CALFAULT(1U) 865 866 #define S_PCIE_ZINSEL 11 867 #define V_PCIE_ZINSEL(x) ((x) << S_PCIE_ZINSEL) 868 #define F_PCIE_ZINSEL V_PCIE_ZINSEL(1U) 869 870 #define S_ZMAN 8 871 #define M_ZMAN 0x7 872 #define V_ZMAN(x) ((x) << S_ZMAN) 873 #define G_ZMAN(x) (((x) >> S_ZMAN) & M_ZMAN) 874 875 #define S_ZOUT 3 876 #define M_ZOUT 0x1f 877 #define V_ZOUT(x) ((x) << S_ZOUT) 878 #define G_ZOUT(x) (((x) >> S_ZOUT) & M_ZOUT) 879 880 #define S_ZIN 0 881 #define M_ZIN 0x7 882 #define V_ZIN(x) ((x) << S_ZIN) 883 #define G_ZIN(x) (((x) >> S_ZIN) & M_ZIN) 884 885 #define A_PCIE_WOL 0x94 886 #define A_PCIE_PEX_CTRL0 0x98 887 888 #define S_NUMFSTTRNSEQ 22 889 #define M_NUMFSTTRNSEQ 0xff 890 #define V_NUMFSTTRNSEQ(x) ((x) << S_NUMFSTTRNSEQ) 891 #define G_NUMFSTTRNSEQ(x) (((x) >> S_NUMFSTTRNSEQ) & M_NUMFSTTRNSEQ) 892 893 #define S_REPLAYLMT 2 894 #define M_REPLAYLMT 0xfffff 895 #define V_REPLAYLMT(x) ((x) << S_REPLAYLMT) 896 #define G_REPLAYLMT(x) (((x) >> S_REPLAYLMT) & M_REPLAYLMT) 897 898 #define S_TXPNDCHKEN 1 899 #define V_TXPNDCHKEN(x) ((x) << S_TXPNDCHKEN) 900 #define F_TXPNDCHKEN V_TXPNDCHKEN(1U) 901 902 #define S_CPLPNDCHKEN 0 903 #define V_CPLPNDCHKEN(x) ((x) << S_CPLPNDCHKEN) 904 #define F_CPLPNDCHKEN V_CPLPNDCHKEN(1U) 905 906 #define S_CPLTIMEOUTRETRY 31 907 #define V_CPLTIMEOUTRETRY(x) ((x) << S_CPLTIMEOUTRETRY) 908 #define F_CPLTIMEOUTRETRY V_CPLTIMEOUTRETRY(1U) 909 910 #define S_STRICTTSMN 30 911 #define V_STRICTTSMN(x) ((x) << S_STRICTTSMN) 912 #define F_STRICTTSMN V_STRICTTSMN(1U) 913 914 #define A_PCIE_PEX_CTRL1 0x9c 915 916 #define S_T3A_DLLPTIMEOUTLMT 11 917 #define M_T3A_DLLPTIMEOUTLMT 0xfffff 918 #define V_T3A_DLLPTIMEOUTLMT(x) ((x) << S_T3A_DLLPTIMEOUTLMT) 919 #define G_T3A_DLLPTIMEOUTLMT(x) (((x) >> S_T3A_DLLPTIMEOUTLMT) & M_T3A_DLLPTIMEOUTLMT) 920 921 #define S_T3A_ACKLAT 0 922 #define M_T3A_ACKLAT 0x7ff 923 #define V_T3A_ACKLAT(x) ((x) << S_T3A_ACKLAT) 924 #define G_T3A_ACKLAT(x) (((x) >> S_T3A_ACKLAT) & M_T3A_ACKLAT) 925 926 #define S_RXPHYERREN 31 927 #define V_RXPHYERREN(x) ((x) << S_RXPHYERREN) 928 #define F_RXPHYERREN V_RXPHYERREN(1U) 929 930 #define S_DLLPTIMEOUTLMT 13 931 #define M_DLLPTIMEOUTLMT 0x3ffff 932 #define V_DLLPTIMEOUTLMT(x) ((x) << S_DLLPTIMEOUTLMT) 933 #define G_DLLPTIMEOUTLMT(x) (((x) >> S_DLLPTIMEOUTLMT) & M_DLLPTIMEOUTLMT) 934 935 #define S_ACKLAT 0 936 #define M_ACKLAT 0x1fff 937 #define V_ACKLAT(x) ((x) << S_ACKLAT) 938 #define G_ACKLAT(x) (((x) >> S_ACKLAT) & M_ACKLAT) 939 940 #define A_PCIE_PEX_CTRL2 0xa0 941 942 #define S_PMEXITL1REQ 29 943 #define V_PMEXITL1REQ(x) ((x) << S_PMEXITL1REQ) 944 #define F_PMEXITL1REQ V_PMEXITL1REQ(1U) 945 946 #define S_PMTXIDLE 28 947 #define V_PMTXIDLE(x) ((x) << S_PMTXIDLE) 948 #define F_PMTXIDLE V_PMTXIDLE(1U) 949 950 #define S_PCIMODELOOP 27 951 #define V_PCIMODELOOP(x) ((x) << S_PCIMODELOOP) 952 #define F_PCIMODELOOP V_PCIMODELOOP(1U) 953 954 #define S_L1ASPMTXRXL0STIME 15 955 #define M_L1ASPMTXRXL0STIME 0xfff 956 #define V_L1ASPMTXRXL0STIME(x) ((x) << S_L1ASPMTXRXL0STIME) 957 #define G_L1ASPMTXRXL0STIME(x) (((x) >> S_L1ASPMTXRXL0STIME) & M_L1ASPMTXRXL0STIME) 958 959 #define S_L0SIDLETIME 4 960 #define M_L0SIDLETIME 0x7ff 961 #define V_L0SIDLETIME(x) ((x) << S_L0SIDLETIME) 962 #define G_L0SIDLETIME(x) (((x) >> S_L0SIDLETIME) & M_L0SIDLETIME) 963 964 #define S_ENTERL23 3 965 #define V_ENTERL23(x) ((x) << S_ENTERL23) 966 #define F_ENTERL23 V_ENTERL23(1U) 967 968 #define S_ENTERL1ASPMEN 2 969 #define V_ENTERL1ASPMEN(x) ((x) << S_ENTERL1ASPMEN) 970 #define F_ENTERL1ASPMEN V_ENTERL1ASPMEN(1U) 971 972 #define S_ENTERL1EN 1 973 #define V_ENTERL1EN(x) ((x) << S_ENTERL1EN) 974 #define F_ENTERL1EN V_ENTERL1EN(1U) 975 976 #define S_ENTERL0SEN 0 977 #define V_ENTERL0SEN(x) ((x) << S_ENTERL0SEN) 978 #define F_ENTERL0SEN V_ENTERL0SEN(1U) 979 980 #define S_LNKCNTLDETDIR 30 981 #define V_LNKCNTLDETDIR(x) ((x) << S_LNKCNTLDETDIR) 982 #define F_LNKCNTLDETDIR V_LNKCNTLDETDIR(1U) 983 984 #define S_ENTERL1REN 29 985 #define V_ENTERL1REN(x) ((x) << S_ENTERL1REN) 986 #define F_ENTERL1REN V_ENTERL1REN(1U) 987 988 #define A_PCIE_PEX_ERR 0xa4 989 990 #define S_FLOWCTLOFLOWERR 17 991 #define V_FLOWCTLOFLOWERR(x) ((x) << S_FLOWCTLOFLOWERR) 992 #define F_FLOWCTLOFLOWERR V_FLOWCTLOFLOWERR(1U) 993 994 #define S_REPLAYTIMEOUT 16 995 #define V_REPLAYTIMEOUT(x) ((x) << S_REPLAYTIMEOUT) 996 #define F_REPLAYTIMEOUT V_REPLAYTIMEOUT(1U) 997 998 #define S_REPLAYROLLOVER 15 999 #define V_REPLAYROLLOVER(x) ((x) << S_REPLAYROLLOVER) 1000 #define F_REPLAYROLLOVER V_REPLAYROLLOVER(1U) 1001 1002 #define S_BADDLLP 14 1003 #define V_BADDLLP(x) ((x) << S_BADDLLP) 1004 #define F_BADDLLP V_BADDLLP(1U) 1005 1006 #define S_DLLPERR 13 1007 #define V_DLLPERR(x) ((x) << S_DLLPERR) 1008 #define F_DLLPERR V_DLLPERR(1U) 1009 1010 #define S_FLOWCTLPROTERR 12 1011 #define V_FLOWCTLPROTERR(x) ((x) << S_FLOWCTLPROTERR) 1012 #define F_FLOWCTLPROTERR V_FLOWCTLPROTERR(1U) 1013 1014 #define S_CPLTIMEOUT 11 1015 #define V_CPLTIMEOUT(x) ((x) << S_CPLTIMEOUT) 1016 #define F_CPLTIMEOUT V_CPLTIMEOUT(1U) 1017 1018 #define S_PHYRCVERR 10 1019 #define V_PHYRCVERR(x) ((x) << S_PHYRCVERR) 1020 #define F_PHYRCVERR V_PHYRCVERR(1U) 1021 1022 #define S_DISTLP 9 1023 #define V_DISTLP(x) ((x) << S_DISTLP) 1024 #define F_DISTLP V_DISTLP(1U) 1025 1026 #define S_BADECRC 8 1027 #define V_BADECRC(x) ((x) << S_BADECRC) 1028 #define F_BADECRC V_BADECRC(1U) 1029 1030 #define S_BADTLP 7 1031 #define V_BADTLP(x) ((x) << S_BADTLP) 1032 #define F_BADTLP V_BADTLP(1U) 1033 1034 #define S_MALTLP 6 1035 #define V_MALTLP(x) ((x) << S_MALTLP) 1036 #define F_MALTLP V_MALTLP(1U) 1037 1038 #define S_UNXCPL 5 1039 #define V_UNXCPL(x) ((x) << S_UNXCPL) 1040 #define F_UNXCPL V_UNXCPL(1U) 1041 1042 #define S_UNSREQ 4 1043 #define V_UNSREQ(x) ((x) << S_UNSREQ) 1044 #define F_UNSREQ V_UNSREQ(1U) 1045 1046 #define S_PSNREQ 3 1047 #define V_PSNREQ(x) ((x) << S_PSNREQ) 1048 #define F_PSNREQ V_PSNREQ(1U) 1049 1050 #define S_UNSCPL 2 1051 #define V_UNSCPL(x) ((x) << S_UNSCPL) 1052 #define F_UNSCPL V_UNSCPL(1U) 1053 1054 #define S_CPLABT 1 1055 #define V_CPLABT(x) ((x) << S_CPLABT) 1056 #define F_CPLABT V_CPLABT(1U) 1057 1058 #define S_PSNCPL 0 1059 #define V_PSNCPL(x) ((x) << S_PSNCPL) 1060 #define F_PSNCPL V_PSNCPL(1U) 1061 1062 #define S_CPLTIMEOUTID 18 1063 #define M_CPLTIMEOUTID 0x7f 1064 #define V_CPLTIMEOUTID(x) ((x) << S_CPLTIMEOUTID) 1065 #define G_CPLTIMEOUTID(x) (((x) >> S_CPLTIMEOUTID) & M_CPLTIMEOUTID) 1066 1067 #define A_PCIE_PIPE_CTRL 0xa8 1068 1069 #define S_RECDETUSEC 19 1070 #define M_RECDETUSEC 0x7 1071 #define V_RECDETUSEC(x) ((x) << S_RECDETUSEC) 1072 #define G_RECDETUSEC(x) (((x) >> S_RECDETUSEC) & M_RECDETUSEC) 1073 1074 #define S_PLLLCKCYC 6 1075 #define M_PLLLCKCYC 0x1fff 1076 #define V_PLLLCKCYC(x) ((x) << S_PLLLCKCYC) 1077 #define G_PLLLCKCYC(x) (((x) >> S_PLLLCKCYC) & M_PLLLCKCYC) 1078 1079 #define S_ELECIDLEDETCYC 3 1080 #define M_ELECIDLEDETCYC 0x7 1081 #define V_ELECIDLEDETCYC(x) ((x) << S_ELECIDLEDETCYC) 1082 #define G_ELECIDLEDETCYC(x) (((x) >> S_ELECIDLEDETCYC) & M_ELECIDLEDETCYC) 1083 1084 #define S_USECDRLOS 2 1085 #define V_USECDRLOS(x) ((x) << S_USECDRLOS) 1086 #define F_USECDRLOS V_USECDRLOS(1U) 1087 1088 #define S_PCLKREQINP1 1 1089 #define V_PCLKREQINP1(x) ((x) << S_PCLKREQINP1) 1090 #define F_PCLKREQINP1 V_PCLKREQINP1(1U) 1091 1092 #define S_PCLKOFFINP1 0 1093 #define V_PCLKOFFINP1(x) ((x) << S_PCLKOFFINP1) 1094 #define F_PCLKOFFINP1 V_PCLKOFFINP1(1U) 1095 1096 #define S_PMASEL 3 1097 #define V_PMASEL(x) ((x) << S_PMASEL) 1098 #define F_PMASEL V_PMASEL(1U) 1099 1100 #define S_LANE 0 1101 #define M_LANE 0x7 1102 #define V_LANE(x) ((x) << S_LANE) 1103 #define G_LANE(x) (((x) >> S_LANE) & M_LANE) 1104 1105 #define A_PCIE_SERDES_CTRL 0xac 1106 1107 #define S_MANMODE 31 1108 #define V_MANMODE(x) ((x) << S_MANMODE) 1109 #define F_MANMODE V_MANMODE(1U) 1110 1111 #define S_MANLPBKEN 29 1112 #define M_MANLPBKEN 0x3 1113 #define V_MANLPBKEN(x) ((x) << S_MANLPBKEN) 1114 #define G_MANLPBKEN(x) (((x) >> S_MANLPBKEN) & M_MANLPBKEN) 1115 1116 #define S_MANTXRECDETEN 28 1117 #define V_MANTXRECDETEN(x) ((x) << S_MANTXRECDETEN) 1118 #define F_MANTXRECDETEN V_MANTXRECDETEN(1U) 1119 1120 #define S_MANTXBEACON 27 1121 #define V_MANTXBEACON(x) ((x) << S_MANTXBEACON) 1122 #define F_MANTXBEACON V_MANTXBEACON(1U) 1123 1124 #define S_MANTXEI 26 1125 #define V_MANTXEI(x) ((x) << S_MANTXEI) 1126 #define F_MANTXEI V_MANTXEI(1U) 1127 1128 #define S_MANRXPOLARITY 25 1129 #define V_MANRXPOLARITY(x) ((x) << S_MANRXPOLARITY) 1130 #define F_MANRXPOLARITY V_MANRXPOLARITY(1U) 1131 1132 #define S_MANTXRST 24 1133 #define V_MANTXRST(x) ((x) << S_MANTXRST) 1134 #define F_MANTXRST V_MANTXRST(1U) 1135 1136 #define S_MANRXRST 23 1137 #define V_MANRXRST(x) ((x) << S_MANRXRST) 1138 #define F_MANRXRST V_MANRXRST(1U) 1139 1140 #define S_MANTXEN 22 1141 #define V_MANTXEN(x) ((x) << S_MANTXEN) 1142 #define F_MANTXEN V_MANTXEN(1U) 1143 1144 #define S_MANRXEN 21 1145 #define V_MANRXEN(x) ((x) << S_MANRXEN) 1146 #define F_MANRXEN V_MANRXEN(1U) 1147 1148 #define S_MANEN 20 1149 #define V_MANEN(x) ((x) << S_MANEN) 1150 #define F_MANEN V_MANEN(1U) 1151 1152 #define S_PCIE_CMURANGE 17 1153 #define M_PCIE_CMURANGE 0x7 1154 #define V_PCIE_CMURANGE(x) ((x) << S_PCIE_CMURANGE) 1155 #define G_PCIE_CMURANGE(x) (((x) >> S_PCIE_CMURANGE) & M_PCIE_CMURANGE) 1156 1157 #define S_PCIE_BGENB 16 1158 #define V_PCIE_BGENB(x) ((x) << S_PCIE_BGENB) 1159 #define F_PCIE_BGENB V_PCIE_BGENB(1U) 1160 1161 #define S_PCIE_ENSKPDROP 15 1162 #define V_PCIE_ENSKPDROP(x) ((x) << S_PCIE_ENSKPDROP) 1163 #define F_PCIE_ENSKPDROP V_PCIE_ENSKPDROP(1U) 1164 1165 #define S_PCIE_ENCOMMA 14 1166 #define V_PCIE_ENCOMMA(x) ((x) << S_PCIE_ENCOMMA) 1167 #define F_PCIE_ENCOMMA V_PCIE_ENCOMMA(1U) 1168 1169 #define S_PCIE_EN8B10B 13 1170 #define V_PCIE_EN8B10B(x) ((x) << S_PCIE_EN8B10B) 1171 #define F_PCIE_EN8B10B V_PCIE_EN8B10B(1U) 1172 1173 #define S_PCIE_ENELBUF 12 1174 #define V_PCIE_ENELBUF(x) ((x) << S_PCIE_ENELBUF) 1175 #define F_PCIE_ENELBUF V_PCIE_ENELBUF(1U) 1176 1177 #define S_PCIE_GAIN 7 1178 #define M_PCIE_GAIN 0x1f 1179 #define V_PCIE_GAIN(x) ((x) << S_PCIE_GAIN) 1180 #define G_PCIE_GAIN(x) (((x) >> S_PCIE_GAIN) & M_PCIE_GAIN) 1181 1182 #define S_PCIE_BANDGAP 3 1183 #define M_PCIE_BANDGAP 0xf 1184 #define V_PCIE_BANDGAP(x) ((x) << S_PCIE_BANDGAP) 1185 #define G_PCIE_BANDGAP(x) (((x) >> S_PCIE_BANDGAP) & M_PCIE_BANDGAP) 1186 1187 #define S_RXCOMADJ 2 1188 #define V_RXCOMADJ(x) ((x) << S_RXCOMADJ) 1189 #define F_RXCOMADJ V_RXCOMADJ(1U) 1190 1191 #define S_PREEMPH 0 1192 #define M_PREEMPH 0x3 1193 #define V_PREEMPH(x) ((x) << S_PREEMPH) 1194 #define G_PREEMPH(x) (((x) >> S_PREEMPH) & M_PREEMPH) 1195 1196 #define A_PCIE_SERDES_QUAD_CTRL0 0xac 1197 1198 #define S_TESTSIG 10 1199 #define M_TESTSIG 0x7ffff 1200 #define V_TESTSIG(x) ((x) << S_TESTSIG) 1201 #define G_TESTSIG(x) (((x) >> S_TESTSIG) & M_TESTSIG) 1202 1203 #define S_OFFSET 2 1204 #define M_OFFSET 0xff 1205 #define V_OFFSET(x) ((x) << S_OFFSET) 1206 #define G_OFFSET(x) (((x) >> S_OFFSET) & M_OFFSET) 1207 1208 #define S_OFFSETEN 1 1209 #define V_OFFSETEN(x) ((x) << S_OFFSETEN) 1210 #define F_OFFSETEN V_OFFSETEN(1U) 1211 1212 #define S_IDDQB 0 1213 #define V_IDDQB(x) ((x) << S_IDDQB) 1214 #define F_IDDQB V_IDDQB(1U) 1215 1216 #define A_PCIE_SERDES_STATUS0 0xb0 1217 1218 #define S_RXERRLANE7 21 1219 #define M_RXERRLANE7 0x7 1220 #define V_RXERRLANE7(x) ((x) << S_RXERRLANE7) 1221 #define G_RXERRLANE7(x) (((x) >> S_RXERRLANE7) & M_RXERRLANE7) 1222 1223 #define S_RXERRLANE6 18 1224 #define M_RXERRLANE6 0x7 1225 #define V_RXERRLANE6(x) ((x) << S_RXERRLANE6) 1226 #define G_RXERRLANE6(x) (((x) >> S_RXERRLANE6) & M_RXERRLANE6) 1227 1228 #define S_RXERRLANE5 15 1229 #define M_RXERRLANE5 0x7 1230 #define V_RXERRLANE5(x) ((x) << S_RXERRLANE5) 1231 #define G_RXERRLANE5(x) (((x) >> S_RXERRLANE5) & M_RXERRLANE5) 1232 1233 #define S_RXERRLANE4 12 1234 #define M_RXERRLANE4 0x7 1235 #define V_RXERRLANE4(x) ((x) << S_RXERRLANE4) 1236 #define G_RXERRLANE4(x) (((x) >> S_RXERRLANE4) & M_RXERRLANE4) 1237 1238 #define S_PCIE_RXERRLANE3 9 1239 #define M_PCIE_RXERRLANE3 0x7 1240 #define V_PCIE_RXERRLANE3(x) ((x) << S_PCIE_RXERRLANE3) 1241 #define G_PCIE_RXERRLANE3(x) (((x) >> S_PCIE_RXERRLANE3) & M_PCIE_RXERRLANE3) 1242 1243 #define S_PCIE_RXERRLANE2 6 1244 #define M_PCIE_RXERRLANE2 0x7 1245 #define V_PCIE_RXERRLANE2(x) ((x) << S_PCIE_RXERRLANE2) 1246 #define G_PCIE_RXERRLANE2(x) (((x) >> S_PCIE_RXERRLANE2) & M_PCIE_RXERRLANE2) 1247 1248 #define S_PCIE_RXERRLANE1 3 1249 #define M_PCIE_RXERRLANE1 0x7 1250 #define V_PCIE_RXERRLANE1(x) ((x) << S_PCIE_RXERRLANE1) 1251 #define G_PCIE_RXERRLANE1(x) (((x) >> S_PCIE_RXERRLANE1) & M_PCIE_RXERRLANE1) 1252 1253 #define S_PCIE_RXERRLANE0 0 1254 #define M_PCIE_RXERRLANE0 0x7 1255 #define V_PCIE_RXERRLANE0(x) ((x) << S_PCIE_RXERRLANE0) 1256 #define G_PCIE_RXERRLANE0(x) (((x) >> S_PCIE_RXERRLANE0) & M_PCIE_RXERRLANE0) 1257 1258 #define A_PCIE_SERDES_QUAD_CTRL1 0xb0 1259 1260 #define S_FASTINIT 28 1261 #define V_FASTINIT(x) ((x) << S_FASTINIT) 1262 #define F_FASTINIT V_FASTINIT(1U) 1263 1264 #define S_CTCDISABLE 27 1265 #define V_CTCDISABLE(x) ((x) << S_CTCDISABLE) 1266 #define F_CTCDISABLE V_CTCDISABLE(1U) 1267 1268 #define S_MANRESETPLL 26 1269 #define V_MANRESETPLL(x) ((x) << S_MANRESETPLL) 1270 #define F_MANRESETPLL V_MANRESETPLL(1U) 1271 1272 #define S_MANL2PWRDN 25 1273 #define V_MANL2PWRDN(x) ((x) << S_MANL2PWRDN) 1274 #define F_MANL2PWRDN V_MANL2PWRDN(1U) 1275 1276 #define S_MANQUADEN 24 1277 #define V_MANQUADEN(x) ((x) << S_MANQUADEN) 1278 #define F_MANQUADEN V_MANQUADEN(1U) 1279 1280 #define S_RXEQCTL 22 1281 #define M_RXEQCTL 0x3 1282 #define V_RXEQCTL(x) ((x) << S_RXEQCTL) 1283 #define G_RXEQCTL(x) (((x) >> S_RXEQCTL) & M_RXEQCTL) 1284 1285 #define S_HIVMODE 21 1286 #define V_HIVMODE(x) ((x) << S_HIVMODE) 1287 #define F_HIVMODE V_HIVMODE(1U) 1288 1289 #define S_REFSEL 19 1290 #define M_REFSEL 0x3 1291 #define V_REFSEL(x) ((x) << S_REFSEL) 1292 #define G_REFSEL(x) (((x) >> S_REFSEL) & M_REFSEL) 1293 1294 #define S_RXTERMADJ 17 1295 #define M_RXTERMADJ 0x3 1296 #define V_RXTERMADJ(x) ((x) << S_RXTERMADJ) 1297 #define G_RXTERMADJ(x) (((x) >> S_RXTERMADJ) & M_RXTERMADJ) 1298 1299 #define S_TXTERMADJ 15 1300 #define M_TXTERMADJ 0x3 1301 #define V_TXTERMADJ(x) ((x) << S_TXTERMADJ) 1302 #define G_TXTERMADJ(x) (((x) >> S_TXTERMADJ) & M_TXTERMADJ) 1303 1304 #define S_DEQ 11 1305 #define M_DEQ 0xf 1306 #define V_DEQ(x) ((x) << S_DEQ) 1307 #define G_DEQ(x) (((x) >> S_DEQ) & M_DEQ) 1308 1309 #define S_DTX 7 1310 #define M_DTX 0xf 1311 #define V_DTX(x) ((x) << S_DTX) 1312 #define G_DTX(x) (((x) >> S_DTX) & M_DTX) 1313 1314 #define S_LODRV 6 1315 #define V_LODRV(x) ((x) << S_LODRV) 1316 #define F_LODRV V_LODRV(1U) 1317 1318 #define S_HIDRV 5 1319 #define V_HIDRV(x) ((x) << S_HIDRV) 1320 #define F_HIDRV V_HIDRV(1U) 1321 1322 #define S_INTPARRESET 4 1323 #define V_INTPARRESET(x) ((x) << S_INTPARRESET) 1324 #define F_INTPARRESET V_INTPARRESET(1U) 1325 1326 #define S_INTPARLPBK 3 1327 #define V_INTPARLPBK(x) ((x) << S_INTPARLPBK) 1328 #define F_INTPARLPBK V_INTPARLPBK(1U) 1329 1330 #define S_INTSERLPBKWDRV 2 1331 #define V_INTSERLPBKWDRV(x) ((x) << S_INTSERLPBKWDRV) 1332 #define F_INTSERLPBKWDRV V_INTSERLPBKWDRV(1U) 1333 1334 #define S_PW 1 1335 #define V_PW(x) ((x) << S_PW) 1336 #define F_PW V_PW(1U) 1337 1338 #define S_PCLKDETECT 0 1339 #define V_PCLKDETECT(x) ((x) << S_PCLKDETECT) 1340 #define F_PCLKDETECT V_PCLKDETECT(1U) 1341 1342 #define A_PCIE_SERDES_STATUS1 0xb4 1343 1344 #define S_CMULOCK 31 1345 #define V_CMULOCK(x) ((x) << S_CMULOCK) 1346 #define F_CMULOCK V_CMULOCK(1U) 1347 1348 #define S_RXKLOCKLANE7 23 1349 #define V_RXKLOCKLANE7(x) ((x) << S_RXKLOCKLANE7) 1350 #define F_RXKLOCKLANE7 V_RXKLOCKLANE7(1U) 1351 1352 #define S_RXKLOCKLANE6 22 1353 #define V_RXKLOCKLANE6(x) ((x) << S_RXKLOCKLANE6) 1354 #define F_RXKLOCKLANE6 V_RXKLOCKLANE6(1U) 1355 1356 #define S_RXKLOCKLANE5 21 1357 #define V_RXKLOCKLANE5(x) ((x) << S_RXKLOCKLANE5) 1358 #define F_RXKLOCKLANE5 V_RXKLOCKLANE5(1U) 1359 1360 #define S_RXKLOCKLANE4 20 1361 #define V_RXKLOCKLANE4(x) ((x) << S_RXKLOCKLANE4) 1362 #define F_RXKLOCKLANE4 V_RXKLOCKLANE4(1U) 1363 1364 #define S_PCIE_RXKLOCKLANE3 19 1365 #define V_PCIE_RXKLOCKLANE3(x) ((x) << S_PCIE_RXKLOCKLANE3) 1366 #define F_PCIE_RXKLOCKLANE3 V_PCIE_RXKLOCKLANE3(1U) 1367 1368 #define S_PCIE_RXKLOCKLANE2 18 1369 #define V_PCIE_RXKLOCKLANE2(x) ((x) << S_PCIE_RXKLOCKLANE2) 1370 #define F_PCIE_RXKLOCKLANE2 V_PCIE_RXKLOCKLANE2(1U) 1371 1372 #define S_PCIE_RXKLOCKLANE1 17 1373 #define V_PCIE_RXKLOCKLANE1(x) ((x) << S_PCIE_RXKLOCKLANE1) 1374 #define F_PCIE_RXKLOCKLANE1 V_PCIE_RXKLOCKLANE1(1U) 1375 1376 #define S_PCIE_RXKLOCKLANE0 16 1377 #define V_PCIE_RXKLOCKLANE0(x) ((x) << S_PCIE_RXKLOCKLANE0) 1378 #define F_PCIE_RXKLOCKLANE0 V_PCIE_RXKLOCKLANE0(1U) 1379 1380 #define S_RXUFLOWLANE7 15 1381 #define V_RXUFLOWLANE7(x) ((x) << S_RXUFLOWLANE7) 1382 #define F_RXUFLOWLANE7 V_RXUFLOWLANE7(1U) 1383 1384 #define S_RXUFLOWLANE6 14 1385 #define V_RXUFLOWLANE6(x) ((x) << S_RXUFLOWLANE6) 1386 #define F_RXUFLOWLANE6 V_RXUFLOWLANE6(1U) 1387 1388 #define S_RXUFLOWLANE5 13 1389 #define V_RXUFLOWLANE5(x) ((x) << S_RXUFLOWLANE5) 1390 #define F_RXUFLOWLANE5 V_RXUFLOWLANE5(1U) 1391 1392 #define S_RXUFLOWLANE4 12 1393 #define V_RXUFLOWLANE4(x) ((x) << S_RXUFLOWLANE4) 1394 #define F_RXUFLOWLANE4 V_RXUFLOWLANE4(1U) 1395 1396 #define S_PCIE_RXUFLOWLANE3 11 1397 #define V_PCIE_RXUFLOWLANE3(x) ((x) << S_PCIE_RXUFLOWLANE3) 1398 #define F_PCIE_RXUFLOWLANE3 V_PCIE_RXUFLOWLANE3(1U) 1399 1400 #define S_PCIE_RXUFLOWLANE2 10 1401 #define V_PCIE_RXUFLOWLANE2(x) ((x) << S_PCIE_RXUFLOWLANE2) 1402 #define F_PCIE_RXUFLOWLANE2 V_PCIE_RXUFLOWLANE2(1U) 1403 1404 #define S_PCIE_RXUFLOWLANE1 9 1405 #define V_PCIE_RXUFLOWLANE1(x) ((x) << S_PCIE_RXUFLOWLANE1) 1406 #define F_PCIE_RXUFLOWLANE1 V_PCIE_RXUFLOWLANE1(1U) 1407 1408 #define S_PCIE_RXUFLOWLANE0 8 1409 #define V_PCIE_RXUFLOWLANE0(x) ((x) << S_PCIE_RXUFLOWLANE0) 1410 #define F_PCIE_RXUFLOWLANE0 V_PCIE_RXUFLOWLANE0(1U) 1411 1412 #define S_RXOFLOWLANE7 7 1413 #define V_RXOFLOWLANE7(x) ((x) << S_RXOFLOWLANE7) 1414 #define F_RXOFLOWLANE7 V_RXOFLOWLANE7(1U) 1415 1416 #define S_RXOFLOWLANE6 6 1417 #define V_RXOFLOWLANE6(x) ((x) << S_RXOFLOWLANE6) 1418 #define F_RXOFLOWLANE6 V_RXOFLOWLANE6(1U) 1419 1420 #define S_RXOFLOWLANE5 5 1421 #define V_RXOFLOWLANE5(x) ((x) << S_RXOFLOWLANE5) 1422 #define F_RXOFLOWLANE5 V_RXOFLOWLANE5(1U) 1423 1424 #define S_RXOFLOWLANE4 4 1425 #define V_RXOFLOWLANE4(x) ((x) << S_RXOFLOWLANE4) 1426 #define F_RXOFLOWLANE4 V_RXOFLOWLANE4(1U) 1427 1428 #define S_PCIE_RXOFLOWLANE3 3 1429 #define V_PCIE_RXOFLOWLANE3(x) ((x) << S_PCIE_RXOFLOWLANE3) 1430 #define F_PCIE_RXOFLOWLANE3 V_PCIE_RXOFLOWLANE3(1U) 1431 1432 #define S_PCIE_RXOFLOWLANE2 2 1433 #define V_PCIE_RXOFLOWLANE2(x) ((x) << S_PCIE_RXOFLOWLANE2) 1434 #define F_PCIE_RXOFLOWLANE2 V_PCIE_RXOFLOWLANE2(1U) 1435 1436 #define S_PCIE_RXOFLOWLANE1 1 1437 #define V_PCIE_RXOFLOWLANE1(x) ((x) << S_PCIE_RXOFLOWLANE1) 1438 #define F_PCIE_RXOFLOWLANE1 V_PCIE_RXOFLOWLANE1(1U) 1439 1440 #define S_PCIE_RXOFLOWLANE0 0 1441 #define V_PCIE_RXOFLOWLANE0(x) ((x) << S_PCIE_RXOFLOWLANE0) 1442 #define F_PCIE_RXOFLOWLANE0 V_PCIE_RXOFLOWLANE0(1U) 1443 1444 #define A_PCIE_SERDES_LANE_CTRL 0xb4 1445 1446 #define S_EXTBISTCHKERRCLR 22 1447 #define V_EXTBISTCHKERRCLR(x) ((x) << S_EXTBISTCHKERRCLR) 1448 #define F_EXTBISTCHKERRCLR V_EXTBISTCHKERRCLR(1U) 1449 1450 #define S_EXTBISTCHKEN 21 1451 #define V_EXTBISTCHKEN(x) ((x) << S_EXTBISTCHKEN) 1452 #define F_EXTBISTCHKEN V_EXTBISTCHKEN(1U) 1453 1454 #define S_EXTBISTGENEN 20 1455 #define V_EXTBISTGENEN(x) ((x) << S_EXTBISTGENEN) 1456 #define F_EXTBISTGENEN V_EXTBISTGENEN(1U) 1457 1458 #define S_EXTBISTPAT 17 1459 #define M_EXTBISTPAT 0x7 1460 #define V_EXTBISTPAT(x) ((x) << S_EXTBISTPAT) 1461 #define G_EXTBISTPAT(x) (((x) >> S_EXTBISTPAT) & M_EXTBISTPAT) 1462 1463 #define S_EXTPARRESET 16 1464 #define V_EXTPARRESET(x) ((x) << S_EXTPARRESET) 1465 #define F_EXTPARRESET V_EXTPARRESET(1U) 1466 1467 #define S_EXTPARLPBK 15 1468 #define V_EXTPARLPBK(x) ((x) << S_EXTPARLPBK) 1469 #define F_EXTPARLPBK V_EXTPARLPBK(1U) 1470 1471 #define S_MANRXTERMEN 14 1472 #define V_MANRXTERMEN(x) ((x) << S_MANRXTERMEN) 1473 #define F_MANRXTERMEN V_MANRXTERMEN(1U) 1474 1475 #define S_MANBEACONTXEN 13 1476 #define V_MANBEACONTXEN(x) ((x) << S_MANBEACONTXEN) 1477 #define F_MANBEACONTXEN V_MANBEACONTXEN(1U) 1478 1479 #define S_MANRXDETECTEN 12 1480 #define V_MANRXDETECTEN(x) ((x) << S_MANRXDETECTEN) 1481 #define F_MANRXDETECTEN V_MANRXDETECTEN(1U) 1482 1483 #define S_MANTXIDLEEN 11 1484 #define V_MANTXIDLEEN(x) ((x) << S_MANTXIDLEEN) 1485 #define F_MANTXIDLEEN V_MANTXIDLEEN(1U) 1486 1487 #define S_MANRXIDLEEN 10 1488 #define V_MANRXIDLEEN(x) ((x) << S_MANRXIDLEEN) 1489 #define F_MANRXIDLEEN V_MANRXIDLEEN(1U) 1490 1491 #define S_MANL1PWRDN 9 1492 #define V_MANL1PWRDN(x) ((x) << S_MANL1PWRDN) 1493 #define F_MANL1PWRDN V_MANL1PWRDN(1U) 1494 1495 #define S_MANRESET 8 1496 #define V_MANRESET(x) ((x) << S_MANRESET) 1497 #define F_MANRESET V_MANRESET(1U) 1498 1499 #define S_MANFMOFFSET 3 1500 #define M_MANFMOFFSET 0x1f 1501 #define V_MANFMOFFSET(x) ((x) << S_MANFMOFFSET) 1502 #define G_MANFMOFFSET(x) (((x) >> S_MANFMOFFSET) & M_MANFMOFFSET) 1503 1504 #define S_MANFMOFFSETEN 2 1505 #define V_MANFMOFFSETEN(x) ((x) << S_MANFMOFFSETEN) 1506 #define F_MANFMOFFSETEN V_MANFMOFFSETEN(1U) 1507 1508 #define S_MANLANEEN 1 1509 #define V_MANLANEEN(x) ((x) << S_MANLANEEN) 1510 #define F_MANLANEEN V_MANLANEEN(1U) 1511 1512 #define S_INTSERLPBK 0 1513 #define V_INTSERLPBK(x) ((x) << S_INTSERLPBK) 1514 #define F_INTSERLPBK V_INTSERLPBK(1U) 1515 1516 #define A_PCIE_SERDES_STATUS2 0xb8 1517 1518 #define S_TXRECDETLANE7 31 1519 #define V_TXRECDETLANE7(x) ((x) << S_TXRECDETLANE7) 1520 #define F_TXRECDETLANE7 V_TXRECDETLANE7(1U) 1521 1522 #define S_TXRECDETLANE6 30 1523 #define V_TXRECDETLANE6(x) ((x) << S_TXRECDETLANE6) 1524 #define F_TXRECDETLANE6 V_TXRECDETLANE6(1U) 1525 1526 #define S_TXRECDETLANE5 29 1527 #define V_TXRECDETLANE5(x) ((x) << S_TXRECDETLANE5) 1528 #define F_TXRECDETLANE5 V_TXRECDETLANE5(1U) 1529 1530 #define S_TXRECDETLANE4 28 1531 #define V_TXRECDETLANE4(x) ((x) << S_TXRECDETLANE4) 1532 #define F_TXRECDETLANE4 V_TXRECDETLANE4(1U) 1533 1534 #define S_TXRECDETLANE3 27 1535 #define V_TXRECDETLANE3(x) ((x) << S_TXRECDETLANE3) 1536 #define F_TXRECDETLANE3 V_TXRECDETLANE3(1U) 1537 1538 #define S_TXRECDETLANE2 26 1539 #define V_TXRECDETLANE2(x) ((x) << S_TXRECDETLANE2) 1540 #define F_TXRECDETLANE2 V_TXRECDETLANE2(1U) 1541 1542 #define S_TXRECDETLANE1 25 1543 #define V_TXRECDETLANE1(x) ((x) << S_TXRECDETLANE1) 1544 #define F_TXRECDETLANE1 V_TXRECDETLANE1(1U) 1545 1546 #define S_TXRECDETLANE0 24 1547 #define V_TXRECDETLANE0(x) ((x) << S_TXRECDETLANE0) 1548 #define F_TXRECDETLANE0 V_TXRECDETLANE0(1U) 1549 1550 #define S_RXEIDLANE7 23 1551 #define V_RXEIDLANE7(x) ((x) << S_RXEIDLANE7) 1552 #define F_RXEIDLANE7 V_RXEIDLANE7(1U) 1553 1554 #define S_RXEIDLANE6 22 1555 #define V_RXEIDLANE6(x) ((x) << S_RXEIDLANE6) 1556 #define F_RXEIDLANE6 V_RXEIDLANE6(1U) 1557 1558 #define S_RXEIDLANE5 21 1559 #define V_RXEIDLANE5(x) ((x) << S_RXEIDLANE5) 1560 #define F_RXEIDLANE5 V_RXEIDLANE5(1U) 1561 1562 #define S_RXEIDLANE4 20 1563 #define V_RXEIDLANE4(x) ((x) << S_RXEIDLANE4) 1564 #define F_RXEIDLANE4 V_RXEIDLANE4(1U) 1565 1566 #define S_RXEIDLANE3 19 1567 #define V_RXEIDLANE3(x) ((x) << S_RXEIDLANE3) 1568 #define F_RXEIDLANE3 V_RXEIDLANE3(1U) 1569 1570 #define S_RXEIDLANE2 18 1571 #define V_RXEIDLANE2(x) ((x) << S_RXEIDLANE2) 1572 #define F_RXEIDLANE2 V_RXEIDLANE2(1U) 1573 1574 #define S_RXEIDLANE1 17 1575 #define V_RXEIDLANE1(x) ((x) << S_RXEIDLANE1) 1576 #define F_RXEIDLANE1 V_RXEIDLANE1(1U) 1577 1578 #define S_RXEIDLANE0 16 1579 #define V_RXEIDLANE0(x) ((x) << S_RXEIDLANE0) 1580 #define F_RXEIDLANE0 V_RXEIDLANE0(1U) 1581 1582 #define S_RXREMSKIPLANE7 15 1583 #define V_RXREMSKIPLANE7(x) ((x) << S_RXREMSKIPLANE7) 1584 #define F_RXREMSKIPLANE7 V_RXREMSKIPLANE7(1U) 1585 1586 #define S_RXREMSKIPLANE6 14 1587 #define V_RXREMSKIPLANE6(x) ((x) << S_RXREMSKIPLANE6) 1588 #define F_RXREMSKIPLANE6 V_RXREMSKIPLANE6(1U) 1589 1590 #define S_RXREMSKIPLANE5 13 1591 #define V_RXREMSKIPLANE5(x) ((x) << S_RXREMSKIPLANE5) 1592 #define F_RXREMSKIPLANE5 V_RXREMSKIPLANE5(1U) 1593 1594 #define S_RXREMSKIPLANE4 12 1595 #define V_RXREMSKIPLANE4(x) ((x) << S_RXREMSKIPLANE4) 1596 #define F_RXREMSKIPLANE4 V_RXREMSKIPLANE4(1U) 1597 1598 #define S_PCIE_RXREMSKIPLANE3 11 1599 #define V_PCIE_RXREMSKIPLANE3(x) ((x) << S_PCIE_RXREMSKIPLANE3) 1600 #define F_PCIE_RXREMSKIPLANE3 V_PCIE_RXREMSKIPLANE3(1U) 1601 1602 #define S_PCIE_RXREMSKIPLANE2 10 1603 #define V_PCIE_RXREMSKIPLANE2(x) ((x) << S_PCIE_RXREMSKIPLANE2) 1604 #define F_PCIE_RXREMSKIPLANE2 V_PCIE_RXREMSKIPLANE2(1U) 1605 1606 #define S_PCIE_RXREMSKIPLANE1 9 1607 #define V_PCIE_RXREMSKIPLANE1(x) ((x) << S_PCIE_RXREMSKIPLANE1) 1608 #define F_PCIE_RXREMSKIPLANE1 V_PCIE_RXREMSKIPLANE1(1U) 1609 1610 #define S_PCIE_RXREMSKIPLANE0 8 1611 #define V_PCIE_RXREMSKIPLANE0(x) ((x) << S_PCIE_RXREMSKIPLANE0) 1612 #define F_PCIE_RXREMSKIPLANE0 V_PCIE_RXREMSKIPLANE0(1U) 1613 1614 #define S_RXADDSKIPLANE7 7 1615 #define V_RXADDSKIPLANE7(x) ((x) << S_RXADDSKIPLANE7) 1616 #define F_RXADDSKIPLANE7 V_RXADDSKIPLANE7(1U) 1617 1618 #define S_RXADDSKIPLANE6 6 1619 #define V_RXADDSKIPLANE6(x) ((x) << S_RXADDSKIPLANE6) 1620 #define F_RXADDSKIPLANE6 V_RXADDSKIPLANE6(1U) 1621 1622 #define S_RXADDSKIPLANE5 5 1623 #define V_RXADDSKIPLANE5(x) ((x) << S_RXADDSKIPLANE5) 1624 #define F_RXADDSKIPLANE5 V_RXADDSKIPLANE5(1U) 1625 1626 #define S_RXADDSKIPLANE4 4 1627 #define V_RXADDSKIPLANE4(x) ((x) << S_RXADDSKIPLANE4) 1628 #define F_RXADDSKIPLANE4 V_RXADDSKIPLANE4(1U) 1629 1630 #define S_PCIE_RXADDSKIPLANE3 3 1631 #define V_PCIE_RXADDSKIPLANE3(x) ((x) << S_PCIE_RXADDSKIPLANE3) 1632 #define F_PCIE_RXADDSKIPLANE3 V_PCIE_RXADDSKIPLANE3(1U) 1633 1634 #define S_PCIE_RXADDSKIPLANE2 2 1635 #define V_PCIE_RXADDSKIPLANE2(x) ((x) << S_PCIE_RXADDSKIPLANE2) 1636 #define F_PCIE_RXADDSKIPLANE2 V_PCIE_RXADDSKIPLANE2(1U) 1637 1638 #define S_PCIE_RXADDSKIPLANE1 1 1639 #define V_PCIE_RXADDSKIPLANE1(x) ((x) << S_PCIE_RXADDSKIPLANE1) 1640 #define F_PCIE_RXADDSKIPLANE1 V_PCIE_RXADDSKIPLANE1(1U) 1641 1642 #define S_PCIE_RXADDSKIPLANE0 0 1643 #define V_PCIE_RXADDSKIPLANE0(x) ((x) << S_PCIE_RXADDSKIPLANE0) 1644 #define F_PCIE_RXADDSKIPLANE0 V_PCIE_RXADDSKIPLANE0(1U) 1645 1646 #define A_PCIE_SERDES_LANE_STAT 0xb8 1647 1648 #define S_EXTBISTCHKERRCNT 8 1649 #define M_EXTBISTCHKERRCNT 0xffffff 1650 #define V_EXTBISTCHKERRCNT(x) ((x) << S_EXTBISTCHKERRCNT) 1651 #define G_EXTBISTCHKERRCNT(x) (((x) >> S_EXTBISTCHKERRCNT) & M_EXTBISTCHKERRCNT) 1652 1653 #define S_EXTBISTCHKFMD 7 1654 #define V_EXTBISTCHKFMD(x) ((x) << S_EXTBISTCHKFMD) 1655 #define F_EXTBISTCHKFMD V_EXTBISTCHKFMD(1U) 1656 1657 #define S_BEACONDETECTCHG 6 1658 #define V_BEACONDETECTCHG(x) ((x) << S_BEACONDETECTCHG) 1659 #define F_BEACONDETECTCHG V_BEACONDETECTCHG(1U) 1660 1661 #define S_RXDETECTCHG 5 1662 #define V_RXDETECTCHG(x) ((x) << S_RXDETECTCHG) 1663 #define F_RXDETECTCHG V_RXDETECTCHG(1U) 1664 1665 #define S_TXIDLEDETECTCHG 4 1666 #define V_TXIDLEDETECTCHG(x) ((x) << S_TXIDLEDETECTCHG) 1667 #define F_TXIDLEDETECTCHG V_TXIDLEDETECTCHG(1U) 1668 1669 #define S_BEACONDETECT 2 1670 #define V_BEACONDETECT(x) ((x) << S_BEACONDETECT) 1671 #define F_BEACONDETECT V_BEACONDETECT(1U) 1672 1673 #define S_RXDETECT 1 1674 #define V_RXDETECT(x) ((x) << S_RXDETECT) 1675 #define F_RXDETECT V_RXDETECT(1U) 1676 1677 #define S_TXIDLEDETECT 0 1678 #define V_TXIDLEDETECT(x) ((x) << S_TXIDLEDETECT) 1679 #define F_TXIDLEDETECT V_TXIDLEDETECT(1U) 1680 1681 #define A_PCIE_SERDES_BIST 0xbc 1682 1683 #define S_PCIE_BISTDONE 24 1684 #define M_PCIE_BISTDONE 0xff 1685 #define V_PCIE_BISTDONE(x) ((x) << S_PCIE_BISTDONE) 1686 #define G_PCIE_BISTDONE(x) (((x) >> S_PCIE_BISTDONE) & M_PCIE_BISTDONE) 1687 1688 #define S_PCIE_BISTCYCLETHRESH 3 1689 #define M_PCIE_BISTCYCLETHRESH 0xffff 1690 #define V_PCIE_BISTCYCLETHRESH(x) ((x) << S_PCIE_BISTCYCLETHRESH) 1691 #define G_PCIE_BISTCYCLETHRESH(x) (((x) >> S_PCIE_BISTCYCLETHRESH) & M_PCIE_BISTCYCLETHRESH) 1692 1693 #define S_BISTMODE 0 1694 #define M_BISTMODE 0x7 1695 #define V_BISTMODE(x) ((x) << S_BISTMODE) 1696 #define G_BISTMODE(x) (((x) >> S_BISTMODE) & M_BISTMODE) 1697 1698 /* registers for module T3DBG */ 1699 #define T3DBG_BASE_ADDR 0xc0 1700 1701 #define A_T3DBG_DBG0_CFG 0xc0 1702 1703 #define S_REGSELECT 9 1704 #define M_REGSELECT 0xff 1705 #define V_REGSELECT(x) ((x) << S_REGSELECT) 1706 #define G_REGSELECT(x) (((x) >> S_REGSELECT) & M_REGSELECT) 1707 1708 #define S_MODULESELECT 4 1709 #define M_MODULESELECT 0x1f 1710 #define V_MODULESELECT(x) ((x) << S_MODULESELECT) 1711 #define G_MODULESELECT(x) (((x) >> S_MODULESELECT) & M_MODULESELECT) 1712 1713 #define S_CLKSELECT 0 1714 #define M_CLKSELECT 0xf 1715 #define V_CLKSELECT(x) ((x) << S_CLKSELECT) 1716 #define G_CLKSELECT(x) (((x) >> S_CLKSELECT) & M_CLKSELECT) 1717 1718 #define A_T3DBG_DBG0_EN 0xc4 1719 1720 #define S_SDRBYTE0 8 1721 #define V_SDRBYTE0(x) ((x) << S_SDRBYTE0) 1722 #define F_SDRBYTE0 V_SDRBYTE0(1U) 1723 1724 #define S_DDREN 4 1725 #define V_DDREN(x) ((x) << S_DDREN) 1726 #define F_DDREN V_DDREN(1U) 1727 1728 #define S_PORTEN 0 1729 #define V_PORTEN(x) ((x) << S_PORTEN) 1730 #define F_PORTEN V_PORTEN(1U) 1731 1732 #define A_T3DBG_DBG1_CFG 0xc8 1733 #define A_T3DBG_DBG1_EN 0xcc 1734 #define A_T3DBG_GPIO_EN 0xd0 1735 1736 #define S_GPIO11_OEN 27 1737 #define V_GPIO11_OEN(x) ((x) << S_GPIO11_OEN) 1738 #define F_GPIO11_OEN V_GPIO11_OEN(1U) 1739 1740 #define S_GPIO10_OEN 26 1741 #define V_GPIO10_OEN(x) ((x) << S_GPIO10_OEN) 1742 #define F_GPIO10_OEN V_GPIO10_OEN(1U) 1743 1744 #define S_GPIO9_OEN 25 1745 #define V_GPIO9_OEN(x) ((x) << S_GPIO9_OEN) 1746 #define F_GPIO9_OEN V_GPIO9_OEN(1U) 1747 1748 #define S_GPIO8_OEN 24 1749 #define V_GPIO8_OEN(x) ((x) << S_GPIO8_OEN) 1750 #define F_GPIO8_OEN V_GPIO8_OEN(1U) 1751 1752 #define S_GPIO7_OEN 23 1753 #define V_GPIO7_OEN(x) ((x) << S_GPIO7_OEN) 1754 #define F_GPIO7_OEN V_GPIO7_OEN(1U) 1755 1756 #define S_GPIO6_OEN 22 1757 #define V_GPIO6_OEN(x) ((x) << S_GPIO6_OEN) 1758 #define F_GPIO6_OEN V_GPIO6_OEN(1U) 1759 1760 #define S_GPIO5_OEN 21 1761 #define V_GPIO5_OEN(x) ((x) << S_GPIO5_OEN) 1762 #define F_GPIO5_OEN V_GPIO5_OEN(1U) 1763 1764 #define S_GPIO4_OEN 20 1765 #define V_GPIO4_OEN(x) ((x) << S_GPIO4_OEN) 1766 #define F_GPIO4_OEN V_GPIO4_OEN(1U) 1767 1768 #define S_GPIO3_OEN 19 1769 #define V_GPIO3_OEN(x) ((x) << S_GPIO3_OEN) 1770 #define F_GPIO3_OEN V_GPIO3_OEN(1U) 1771 1772 #define S_GPIO2_OEN 18 1773 #define V_GPIO2_OEN(x) ((x) << S_GPIO2_OEN) 1774 #define F_GPIO2_OEN V_GPIO2_OEN(1U) 1775 1776 #define S_GPIO1_OEN 17 1777 #define V_GPIO1_OEN(x) ((x) << S_GPIO1_OEN) 1778 #define F_GPIO1_OEN V_GPIO1_OEN(1U) 1779 1780 #define S_GPIO0_OEN 16 1781 #define V_GPIO0_OEN(x) ((x) << S_GPIO0_OEN) 1782 #define F_GPIO0_OEN V_GPIO0_OEN(1U) 1783 1784 #define S_GPIO11_OUT_VAL 11 1785 #define V_GPIO11_OUT_VAL(x) ((x) << S_GPIO11_OUT_VAL) 1786 #define F_GPIO11_OUT_VAL V_GPIO11_OUT_VAL(1U) 1787 1788 #define S_GPIO10_OUT_VAL 10 1789 #define V_GPIO10_OUT_VAL(x) ((x) << S_GPIO10_OUT_VAL) 1790 #define F_GPIO10_OUT_VAL V_GPIO10_OUT_VAL(1U) 1791 1792 #define S_GPIO9_OUT_VAL 9 1793 #define V_GPIO9_OUT_VAL(x) ((x) << S_GPIO9_OUT_VAL) 1794 #define F_GPIO9_OUT_VAL V_GPIO9_OUT_VAL(1U) 1795 1796 #define S_GPIO8_OUT_VAL 8 1797 #define V_GPIO8_OUT_VAL(x) ((x) << S_GPIO8_OUT_VAL) 1798 #define F_GPIO8_OUT_VAL V_GPIO8_OUT_VAL(1U) 1799 1800 #define S_GPIO7_OUT_VAL 7 1801 #define V_GPIO7_OUT_VAL(x) ((x) << S_GPIO7_OUT_VAL) 1802 #define F_GPIO7_OUT_VAL V_GPIO7_OUT_VAL(1U) 1803 1804 #define S_GPIO6_OUT_VAL 6 1805 #define V_GPIO6_OUT_VAL(x) ((x) << S_GPIO6_OUT_VAL) 1806 #define F_GPIO6_OUT_VAL V_GPIO6_OUT_VAL(1U) 1807 1808 #define S_GPIO5_OUT_VAL 5 1809 #define V_GPIO5_OUT_VAL(x) ((x) << S_GPIO5_OUT_VAL) 1810 #define F_GPIO5_OUT_VAL V_GPIO5_OUT_VAL(1U) 1811 1812 #define S_GPIO4_OUT_VAL 4 1813 #define V_GPIO4_OUT_VAL(x) ((x) << S_GPIO4_OUT_VAL) 1814 #define F_GPIO4_OUT_VAL V_GPIO4_OUT_VAL(1U) 1815 1816 #define S_GPIO3_OUT_VAL 3 1817 #define V_GPIO3_OUT_VAL(x) ((x) << S_GPIO3_OUT_VAL) 1818 #define F_GPIO3_OUT_VAL V_GPIO3_OUT_VAL(1U) 1819 1820 #define S_GPIO2_OUT_VAL 2 1821 #define V_GPIO2_OUT_VAL(x) ((x) << S_GPIO2_OUT_VAL) 1822 #define F_GPIO2_OUT_VAL V_GPIO2_OUT_VAL(1U) 1823 1824 #define S_GPIO1_OUT_VAL 1 1825 #define V_GPIO1_OUT_VAL(x) ((x) << S_GPIO1_OUT_VAL) 1826 #define F_GPIO1_OUT_VAL V_GPIO1_OUT_VAL(1U) 1827 1828 #define S_GPIO0_OUT_VAL 0 1829 #define V_GPIO0_OUT_VAL(x) ((x) << S_GPIO0_OUT_VAL) 1830 #define F_GPIO0_OUT_VAL V_GPIO0_OUT_VAL(1U) 1831 1832 #define A_T3DBG_GPIO_IN 0xd4 1833 1834 #define S_GPIO11_IN 11 1835 #define V_GPIO11_IN(x) ((x) << S_GPIO11_IN) 1836 #define F_GPIO11_IN V_GPIO11_IN(1U) 1837 1838 #define S_GPIO10_IN 10 1839 #define V_GPIO10_IN(x) ((x) << S_GPIO10_IN) 1840 #define F_GPIO10_IN V_GPIO10_IN(1U) 1841 1842 #define S_GPIO9_IN 9 1843 #define V_GPIO9_IN(x) ((x) << S_GPIO9_IN) 1844 #define F_GPIO9_IN V_GPIO9_IN(1U) 1845 1846 #define S_GPIO8_IN 8 1847 #define V_GPIO8_IN(x) ((x) << S_GPIO8_IN) 1848 #define F_GPIO8_IN V_GPIO8_IN(1U) 1849 1850 #define S_GPIO7_IN 7 1851 #define V_GPIO7_IN(x) ((x) << S_GPIO7_IN) 1852 #define F_GPIO7_IN V_GPIO7_IN(1U) 1853 1854 #define S_GPIO6_IN 6 1855 #define V_GPIO6_IN(x) ((x) << S_GPIO6_IN) 1856 #define F_GPIO6_IN V_GPIO6_IN(1U) 1857 1858 #define S_GPIO5_IN 5 1859 #define V_GPIO5_IN(x) ((x) << S_GPIO5_IN) 1860 #define F_GPIO5_IN V_GPIO5_IN(1U) 1861 1862 #define S_GPIO4_IN 4 1863 #define V_GPIO4_IN(x) ((x) << S_GPIO4_IN) 1864 #define F_GPIO4_IN V_GPIO4_IN(1U) 1865 1866 #define S_GPIO3_IN 3 1867 #define V_GPIO3_IN(x) ((x) << S_GPIO3_IN) 1868 #define F_GPIO3_IN V_GPIO3_IN(1U) 1869 1870 #define S_GPIO2_IN 2 1871 #define V_GPIO2_IN(x) ((x) << S_GPIO2_IN) 1872 #define F_GPIO2_IN V_GPIO2_IN(1U) 1873 1874 #define S_GPIO1_IN 1 1875 #define V_GPIO1_IN(x) ((x) << S_GPIO1_IN) 1876 #define F_GPIO1_IN V_GPIO1_IN(1U) 1877 1878 #define S_GPIO0_IN 0 1879 #define V_GPIO0_IN(x) ((x) << S_GPIO0_IN) 1880 #define F_GPIO0_IN V_GPIO0_IN(1U) 1881 1882 #define S_GPIO11_CHG_DET 27 1883 #define V_GPIO11_CHG_DET(x) ((x) << S_GPIO11_CHG_DET) 1884 #define F_GPIO11_CHG_DET V_GPIO11_CHG_DET(1U) 1885 1886 #define S_GPIO10_CHG_DET 26 1887 #define V_GPIO10_CHG_DET(x) ((x) << S_GPIO10_CHG_DET) 1888 #define F_GPIO10_CHG_DET V_GPIO10_CHG_DET(1U) 1889 1890 #define S_GPIO9_CHG_DET 25 1891 #define V_GPIO9_CHG_DET(x) ((x) << S_GPIO9_CHG_DET) 1892 #define F_GPIO9_CHG_DET V_GPIO9_CHG_DET(1U) 1893 1894 #define S_GPIO8_CHG_DET 24 1895 #define V_GPIO8_CHG_DET(x) ((x) << S_GPIO8_CHG_DET) 1896 #define F_GPIO8_CHG_DET V_GPIO8_CHG_DET(1U) 1897 1898 #define S_GPIO7_CHG_DET 23 1899 #define V_GPIO7_CHG_DET(x) ((x) << S_GPIO7_CHG_DET) 1900 #define F_GPIO7_CHG_DET V_GPIO7_CHG_DET(1U) 1901 1902 #define S_GPIO6_CHG_DET 22 1903 #define V_GPIO6_CHG_DET(x) ((x) << S_GPIO6_CHG_DET) 1904 #define F_GPIO6_CHG_DET V_GPIO6_CHG_DET(1U) 1905 1906 #define S_GPIO5_CHG_DET 21 1907 #define V_GPIO5_CHG_DET(x) ((x) << S_GPIO5_CHG_DET) 1908 #define F_GPIO5_CHG_DET V_GPIO5_CHG_DET(1U) 1909 1910 #define S_GPIO4_CHG_DET 20 1911 #define V_GPIO4_CHG_DET(x) ((x) << S_GPIO4_CHG_DET) 1912 #define F_GPIO4_CHG_DET V_GPIO4_CHG_DET(1U) 1913 1914 #define S_GPIO3_CHG_DET 19 1915 #define V_GPIO3_CHG_DET(x) ((x) << S_GPIO3_CHG_DET) 1916 #define F_GPIO3_CHG_DET V_GPIO3_CHG_DET(1U) 1917 1918 #define S_GPIO2_CHG_DET 18 1919 #define V_GPIO2_CHG_DET(x) ((x) << S_GPIO2_CHG_DET) 1920 #define F_GPIO2_CHG_DET V_GPIO2_CHG_DET(1U) 1921 1922 #define S_GPIO1_CHG_DET 17 1923 #define V_GPIO1_CHG_DET(x) ((x) << S_GPIO1_CHG_DET) 1924 #define F_GPIO1_CHG_DET V_GPIO1_CHG_DET(1U) 1925 1926 #define S_GPIO0_CHG_DET 16 1927 #define V_GPIO0_CHG_DET(x) ((x) << S_GPIO0_CHG_DET) 1928 #define F_GPIO0_CHG_DET V_GPIO0_CHG_DET(1U) 1929 1930 #define A_T3DBG_INT_ENABLE 0xd8 1931 1932 #define S_C_LOCK 21 1933 #define V_C_LOCK(x) ((x) << S_C_LOCK) 1934 #define F_C_LOCK V_C_LOCK(1U) 1935 1936 #define S_M_LOCK 20 1937 #define V_M_LOCK(x) ((x) << S_M_LOCK) 1938 #define F_M_LOCK V_M_LOCK(1U) 1939 1940 #define S_U_LOCK 19 1941 #define V_U_LOCK(x) ((x) << S_U_LOCK) 1942 #define F_U_LOCK V_U_LOCK(1U) 1943 1944 #define S_R_LOCK 18 1945 #define V_R_LOCK(x) ((x) << S_R_LOCK) 1946 #define F_R_LOCK V_R_LOCK(1U) 1947 1948 #define S_PX_LOCK 17 1949 #define V_PX_LOCK(x) ((x) << S_PX_LOCK) 1950 #define F_PX_LOCK V_PX_LOCK(1U) 1951 1952 #define S_PE_LOCK 16 1953 #define V_PE_LOCK(x) ((x) << S_PE_LOCK) 1954 #define F_PE_LOCK V_PE_LOCK(1U) 1955 1956 #define S_GPIO11 11 1957 #define V_GPIO11(x) ((x) << S_GPIO11) 1958 #define F_GPIO11 V_GPIO11(1U) 1959 1960 #define S_GPIO10 10 1961 #define V_GPIO10(x) ((x) << S_GPIO10) 1962 #define F_GPIO10 V_GPIO10(1U) 1963 1964 #define S_GPIO9 9 1965 #define V_GPIO9(x) ((x) << S_GPIO9) 1966 #define F_GPIO9 V_GPIO9(1U) 1967 1968 #define S_GPIO8 8 1969 #define V_GPIO8(x) ((x) << S_GPIO8) 1970 #define F_GPIO8 V_GPIO8(1U) 1971 1972 #define S_GPIO7 7 1973 #define V_GPIO7(x) ((x) << S_GPIO7) 1974 #define F_GPIO7 V_GPIO7(1U) 1975 1976 #define S_GPIO6 6 1977 #define V_GPIO6(x) ((x) << S_GPIO6) 1978 #define F_GPIO6 V_GPIO6(1U) 1979 1980 #define S_GPIO5 5 1981 #define V_GPIO5(x) ((x) << S_GPIO5) 1982 #define F_GPIO5 V_GPIO5(1U) 1983 1984 #define S_GPIO4 4 1985 #define V_GPIO4(x) ((x) << S_GPIO4) 1986 #define F_GPIO4 V_GPIO4(1U) 1987 1988 #define S_GPIO3 3 1989 #define V_GPIO3(x) ((x) << S_GPIO3) 1990 #define F_GPIO3 V_GPIO3(1U) 1991 1992 #define S_GPIO2 2 1993 #define V_GPIO2(x) ((x) << S_GPIO2) 1994 #define F_GPIO2 V_GPIO2(1U) 1995 1996 #define S_GPIO1 1 1997 #define V_GPIO1(x) ((x) << S_GPIO1) 1998 #define F_GPIO1 V_GPIO1(1U) 1999 2000 #define S_GPIO0 0 2001 #define V_GPIO0(x) ((x) << S_GPIO0) 2002 #define F_GPIO0 V_GPIO0(1U) 2003 2004 #define A_T3DBG_INT_CAUSE 0xdc 2005 #define A_T3DBG_DBG0_RST_VALUE 0xe0 2006 2007 #define S_DEBUGDATA 0 2008 #define V_DEBUGDATA(x) ((x) << S_DEBUGDATA) 2009 #define F_DEBUGDATA V_DEBUGDATA(1U) 2010 2011 #define A_T3DBG_PLL_OCLK_PAD_EN 0xe4 2012 2013 #define S_PCIE_OCLK_EN 20 2014 #define V_PCIE_OCLK_EN(x) ((x) << S_PCIE_OCLK_EN) 2015 #define F_PCIE_OCLK_EN V_PCIE_OCLK_EN(1U) 2016 2017 #define S_PCIX_OCLK_EN 16 2018 #define V_PCIX_OCLK_EN(x) ((x) << S_PCIX_OCLK_EN) 2019 #define F_PCIX_OCLK_EN V_PCIX_OCLK_EN(1U) 2020 2021 #define S_U_OCLK_EN 12 2022 #define V_U_OCLK_EN(x) ((x) << S_U_OCLK_EN) 2023 #define F_U_OCLK_EN V_U_OCLK_EN(1U) 2024 2025 #define S_R_OCLK_EN 8 2026 #define V_R_OCLK_EN(x) ((x) << S_R_OCLK_EN) 2027 #define F_R_OCLK_EN V_R_OCLK_EN(1U) 2028 2029 #define S_M_OCLK_EN 4 2030 #define V_M_OCLK_EN(x) ((x) << S_M_OCLK_EN) 2031 #define F_M_OCLK_EN V_M_OCLK_EN(1U) 2032 2033 #define S_C_OCLK_EN 0 2034 #define V_C_OCLK_EN(x) ((x) << S_C_OCLK_EN) 2035 #define F_C_OCLK_EN V_C_OCLK_EN(1U) 2036 2037 #define S_PCLKTREE_DBG_EN 17 2038 #define V_PCLKTREE_DBG_EN(x) ((x) << S_PCLKTREE_DBG_EN) 2039 #define F_PCLKTREE_DBG_EN V_PCLKTREE_DBG_EN(1U) 2040 2041 #define A_T3DBG_PLL_LOCK 0xe8 2042 2043 #define S_PCIE_LOCK 20 2044 #define V_PCIE_LOCK(x) ((x) << S_PCIE_LOCK) 2045 #define F_PCIE_LOCK V_PCIE_LOCK(1U) 2046 2047 #define S_PCIX_LOCK 16 2048 #define V_PCIX_LOCK(x) ((x) << S_PCIX_LOCK) 2049 #define F_PCIX_LOCK V_PCIX_LOCK(1U) 2050 2051 #define S_PLL_U_LOCK 12 2052 #define V_PLL_U_LOCK(x) ((x) << S_PLL_U_LOCK) 2053 #define F_PLL_U_LOCK V_PLL_U_LOCK(1U) 2054 2055 #define S_PLL_R_LOCK 8 2056 #define V_PLL_R_LOCK(x) ((x) << S_PLL_R_LOCK) 2057 #define F_PLL_R_LOCK V_PLL_R_LOCK(1U) 2058 2059 #define S_PLL_M_LOCK 4 2060 #define V_PLL_M_LOCK(x) ((x) << S_PLL_M_LOCK) 2061 #define F_PLL_M_LOCK V_PLL_M_LOCK(1U) 2062 2063 #define S_PLL_C_LOCK 0 2064 #define V_PLL_C_LOCK(x) ((x) << S_PLL_C_LOCK) 2065 #define F_PLL_C_LOCK V_PLL_C_LOCK(1U) 2066 2067 #define A_T3DBG_SERDES_RBC_CFG 0xec 2068 2069 #define S_X_RBC_LANE_SEL 16 2070 #define V_X_RBC_LANE_SEL(x) ((x) << S_X_RBC_LANE_SEL) 2071 #define F_X_RBC_LANE_SEL V_X_RBC_LANE_SEL(1U) 2072 2073 #define S_X_RBC_DBG_EN 12 2074 #define V_X_RBC_DBG_EN(x) ((x) << S_X_RBC_DBG_EN) 2075 #define F_X_RBC_DBG_EN V_X_RBC_DBG_EN(1U) 2076 2077 #define S_X_SERDES_SEL 8 2078 #define V_X_SERDES_SEL(x) ((x) << S_X_SERDES_SEL) 2079 #define F_X_SERDES_SEL V_X_SERDES_SEL(1U) 2080 2081 #define S_PE_RBC_LANE_SEL 4 2082 #define V_PE_RBC_LANE_SEL(x) ((x) << S_PE_RBC_LANE_SEL) 2083 #define F_PE_RBC_LANE_SEL V_PE_RBC_LANE_SEL(1U) 2084 2085 #define S_PE_RBC_DBG_EN 0 2086 #define V_PE_RBC_DBG_EN(x) ((x) << S_PE_RBC_DBG_EN) 2087 #define F_PE_RBC_DBG_EN V_PE_RBC_DBG_EN(1U) 2088 2089 #define A_T3DBG_GPIO_ACT_LOW 0xf0 2090 2091 #define S_C_LOCK_ACT_LOW 21 2092 #define V_C_LOCK_ACT_LOW(x) ((x) << S_C_LOCK_ACT_LOW) 2093 #define F_C_LOCK_ACT_LOW V_C_LOCK_ACT_LOW(1U) 2094 2095 #define S_M_LOCK_ACT_LOW 20 2096 #define V_M_LOCK_ACT_LOW(x) ((x) << S_M_LOCK_ACT_LOW) 2097 #define F_M_LOCK_ACT_LOW V_M_LOCK_ACT_LOW(1U) 2098 2099 #define S_U_LOCK_ACT_LOW 19 2100 #define V_U_LOCK_ACT_LOW(x) ((x) << S_U_LOCK_ACT_LOW) 2101 #define F_U_LOCK_ACT_LOW V_U_LOCK_ACT_LOW(1U) 2102 2103 #define S_R_LOCK_ACT_LOW 18 2104 #define V_R_LOCK_ACT_LOW(x) ((x) << S_R_LOCK_ACT_LOW) 2105 #define F_R_LOCK_ACT_LOW V_R_LOCK_ACT_LOW(1U) 2106 2107 #define S_PX_LOCK_ACT_LOW 17 2108 #define V_PX_LOCK_ACT_LOW(x) ((x) << S_PX_LOCK_ACT_LOW) 2109 #define F_PX_LOCK_ACT_LOW V_PX_LOCK_ACT_LOW(1U) 2110 2111 #define S_PE_LOCK_ACT_LOW 16 2112 #define V_PE_LOCK_ACT_LOW(x) ((x) << S_PE_LOCK_ACT_LOW) 2113 #define F_PE_LOCK_ACT_LOW V_PE_LOCK_ACT_LOW(1U) 2114 2115 #define S_GPIO11_ACT_LOW 11 2116 #define V_GPIO11_ACT_LOW(x) ((x) << S_GPIO11_ACT_LOW) 2117 #define F_GPIO11_ACT_LOW V_GPIO11_ACT_LOW(1U) 2118 2119 #define S_GPIO10_ACT_LOW 10 2120 #define V_GPIO10_ACT_LOW(x) ((x) << S_GPIO10_ACT_LOW) 2121 #define F_GPIO10_ACT_LOW V_GPIO10_ACT_LOW(1U) 2122 2123 #define S_GPIO9_ACT_LOW 9 2124 #define V_GPIO9_ACT_LOW(x) ((x) << S_GPIO9_ACT_LOW) 2125 #define F_GPIO9_ACT_LOW V_GPIO9_ACT_LOW(1U) 2126 2127 #define S_GPIO8_ACT_LOW 8 2128 #define V_GPIO8_ACT_LOW(x) ((x) << S_GPIO8_ACT_LOW) 2129 #define F_GPIO8_ACT_LOW V_GPIO8_ACT_LOW(1U) 2130 2131 #define S_GPIO7_ACT_LOW 7 2132 #define V_GPIO7_ACT_LOW(x) ((x) << S_GPIO7_ACT_LOW) 2133 #define F_GPIO7_ACT_LOW V_GPIO7_ACT_LOW(1U) 2134 2135 #define S_GPIO6_ACT_LOW 6 2136 #define V_GPIO6_ACT_LOW(x) ((x) << S_GPIO6_ACT_LOW) 2137 #define F_GPIO6_ACT_LOW V_GPIO6_ACT_LOW(1U) 2138 2139 #define S_GPIO5_ACT_LOW 5 2140 #define V_GPIO5_ACT_LOW(x) ((x) << S_GPIO5_ACT_LOW) 2141 #define F_GPIO5_ACT_LOW V_GPIO5_ACT_LOW(1U) 2142 2143 #define S_GPIO4_ACT_LOW 4 2144 #define V_GPIO4_ACT_LOW(x) ((x) << S_GPIO4_ACT_LOW) 2145 #define F_GPIO4_ACT_LOW V_GPIO4_ACT_LOW(1U) 2146 2147 #define S_GPIO3_ACT_LOW 3 2148 #define V_GPIO3_ACT_LOW(x) ((x) << S_GPIO3_ACT_LOW) 2149 #define F_GPIO3_ACT_LOW V_GPIO3_ACT_LOW(1U) 2150 2151 #define S_GPIO2_ACT_LOW 2 2152 #define V_GPIO2_ACT_LOW(x) ((x) << S_GPIO2_ACT_LOW) 2153 #define F_GPIO2_ACT_LOW V_GPIO2_ACT_LOW(1U) 2154 2155 #define S_GPIO1_ACT_LOW 1 2156 #define V_GPIO1_ACT_LOW(x) ((x) << S_GPIO1_ACT_LOW) 2157 #define F_GPIO1_ACT_LOW V_GPIO1_ACT_LOW(1U) 2158 2159 #define S_GPIO0_ACT_LOW 0 2160 #define V_GPIO0_ACT_LOW(x) ((x) << S_GPIO0_ACT_LOW) 2161 #define F_GPIO0_ACT_LOW V_GPIO0_ACT_LOW(1U) 2162 2163 #define A_T3DBG_PMON_CFG 0xf4 2164 2165 #define S_PMON_DONE 29 2166 #define V_PMON_DONE(x) ((x) << S_PMON_DONE) 2167 #define F_PMON_DONE V_PMON_DONE(1U) 2168 2169 #define S_PMON_FAIL 28 2170 #define V_PMON_FAIL(x) ((x) << S_PMON_FAIL) 2171 #define F_PMON_FAIL V_PMON_FAIL(1U) 2172 2173 #define S_PMON_FDEL_AUTO 22 2174 #define V_PMON_FDEL_AUTO(x) ((x) << S_PMON_FDEL_AUTO) 2175 #define F_PMON_FDEL_AUTO V_PMON_FDEL_AUTO(1U) 2176 2177 #define S_PMON_CDEL_AUTO 16 2178 #define V_PMON_CDEL_AUTO(x) ((x) << S_PMON_CDEL_AUTO) 2179 #define F_PMON_CDEL_AUTO V_PMON_CDEL_AUTO(1U) 2180 2181 #define S_PMON_FDEL_MANUAL 10 2182 #define V_PMON_FDEL_MANUAL(x) ((x) << S_PMON_FDEL_MANUAL) 2183 #define F_PMON_FDEL_MANUAL V_PMON_FDEL_MANUAL(1U) 2184 2185 #define S_PMON_CDEL_MANUAL 4 2186 #define V_PMON_CDEL_MANUAL(x) ((x) << S_PMON_CDEL_MANUAL) 2187 #define F_PMON_CDEL_MANUAL V_PMON_CDEL_MANUAL(1U) 2188 2189 #define S_PMON_MANUAL 1 2190 #define V_PMON_MANUAL(x) ((x) << S_PMON_MANUAL) 2191 #define F_PMON_MANUAL V_PMON_MANUAL(1U) 2192 2193 #define S_PMON_AUTO 0 2194 #define V_PMON_AUTO(x) ((x) << S_PMON_AUTO) 2195 #define F_PMON_AUTO V_PMON_AUTO(1U) 2196 2197 #define A_T3DBG_SERDES_REFCLK_CFG 0xf8 2198 2199 #define S_PE_REFCLK_DBG_EN 12 2200 #define V_PE_REFCLK_DBG_EN(x) ((x) << S_PE_REFCLK_DBG_EN) 2201 #define F_PE_REFCLK_DBG_EN V_PE_REFCLK_DBG_EN(1U) 2202 2203 #define S_X_REFCLK_DBG_EN 8 2204 #define V_X_REFCLK_DBG_EN(x) ((x) << S_X_REFCLK_DBG_EN) 2205 #define F_X_REFCLK_DBG_EN V_X_REFCLK_DBG_EN(1U) 2206 2207 #define S_PE_REFCLK_TERMADJ 5 2208 #define M_PE_REFCLK_TERMADJ 0x3 2209 #define V_PE_REFCLK_TERMADJ(x) ((x) << S_PE_REFCLK_TERMADJ) 2210 #define G_PE_REFCLK_TERMADJ(x) (((x) >> S_PE_REFCLK_TERMADJ) & M_PE_REFCLK_TERMADJ) 2211 2212 #define S_PE_REFCLK_PD 4 2213 #define V_PE_REFCLK_PD(x) ((x) << S_PE_REFCLK_PD) 2214 #define F_PE_REFCLK_PD V_PE_REFCLK_PD(1U) 2215 2216 #define S_X_REFCLK_TERMADJ 1 2217 #define M_X_REFCLK_TERMADJ 0x3 2218 #define V_X_REFCLK_TERMADJ(x) ((x) << S_X_REFCLK_TERMADJ) 2219 #define G_X_REFCLK_TERMADJ(x) (((x) >> S_X_REFCLK_TERMADJ) & M_X_REFCLK_TERMADJ) 2220 2221 #define S_X_REFCLK_PD 0 2222 #define V_X_REFCLK_PD(x) ((x) << S_X_REFCLK_PD) 2223 #define F_X_REFCLK_PD V_X_REFCLK_PD(1U) 2224 2225 #define A_T3DBG_PCIE_PMA_BSPIN_CFG 0xfc 2226 2227 #define S_BSMODEQUAD1 31 2228 #define V_BSMODEQUAD1(x) ((x) << S_BSMODEQUAD1) 2229 #define F_BSMODEQUAD1 V_BSMODEQUAD1(1U) 2230 2231 #define S_BSINSELLANE7 29 2232 #define M_BSINSELLANE7 0x3 2233 #define V_BSINSELLANE7(x) ((x) << S_BSINSELLANE7) 2234 #define G_BSINSELLANE7(x) (((x) >> S_BSINSELLANE7) & M_BSINSELLANE7) 2235 2236 #define S_BSENLANE7 28 2237 #define V_BSENLANE7(x) ((x) << S_BSENLANE7) 2238 #define F_BSENLANE7 V_BSENLANE7(1U) 2239 2240 #define S_BSINSELLANE6 25 2241 #define M_BSINSELLANE6 0x3 2242 #define V_BSINSELLANE6(x) ((x) << S_BSINSELLANE6) 2243 #define G_BSINSELLANE6(x) (((x) >> S_BSINSELLANE6) & M_BSINSELLANE6) 2244 2245 #define S_BSENLANE6 24 2246 #define V_BSENLANE6(x) ((x) << S_BSENLANE6) 2247 #define F_BSENLANE6 V_BSENLANE6(1U) 2248 2249 #define S_BSINSELLANE5 21 2250 #define M_BSINSELLANE5 0x3 2251 #define V_BSINSELLANE5(x) ((x) << S_BSINSELLANE5) 2252 #define G_BSINSELLANE5(x) (((x) >> S_BSINSELLANE5) & M_BSINSELLANE5) 2253 2254 #define S_BSENLANE5 20 2255 #define V_BSENLANE5(x) ((x) << S_BSENLANE5) 2256 #define F_BSENLANE5 V_BSENLANE5(1U) 2257 2258 #define S_BSINSELLANE4 17 2259 #define M_BSINSELLANE4 0x3 2260 #define V_BSINSELLANE4(x) ((x) << S_BSINSELLANE4) 2261 #define G_BSINSELLANE4(x) (((x) >> S_BSINSELLANE4) & M_BSINSELLANE4) 2262 2263 #define S_BSENLANE4 16 2264 #define V_BSENLANE4(x) ((x) << S_BSENLANE4) 2265 #define F_BSENLANE4 V_BSENLANE4(1U) 2266 2267 #define S_BSMODEQUAD0 15 2268 #define V_BSMODEQUAD0(x) ((x) << S_BSMODEQUAD0) 2269 #define F_BSMODEQUAD0 V_BSMODEQUAD0(1U) 2270 2271 #define S_BSINSELLANE3 13 2272 #define M_BSINSELLANE3 0x3 2273 #define V_BSINSELLANE3(x) ((x) << S_BSINSELLANE3) 2274 #define G_BSINSELLANE3(x) (((x) >> S_BSINSELLANE3) & M_BSINSELLANE3) 2275 2276 #define S_BSENLANE3 12 2277 #define V_BSENLANE3(x) ((x) << S_BSENLANE3) 2278 #define F_BSENLANE3 V_BSENLANE3(1U) 2279 2280 #define S_BSINSELLANE2 9 2281 #define M_BSINSELLANE2 0x3 2282 #define V_BSINSELLANE2(x) ((x) << S_BSINSELLANE2) 2283 #define G_BSINSELLANE2(x) (((x) >> S_BSINSELLANE2) & M_BSINSELLANE2) 2284 2285 #define S_BSENLANE2 8 2286 #define V_BSENLANE2(x) ((x) << S_BSENLANE2) 2287 #define F_BSENLANE2 V_BSENLANE2(1U) 2288 2289 #define S_BSINSELLANE1 5 2290 #define M_BSINSELLANE1 0x3 2291 #define V_BSINSELLANE1(x) ((x) << S_BSINSELLANE1) 2292 #define G_BSINSELLANE1(x) (((x) >> S_BSINSELLANE1) & M_BSINSELLANE1) 2293 2294 #define S_BSENLANE1 4 2295 #define V_BSENLANE1(x) ((x) << S_BSENLANE1) 2296 #define F_BSENLANE1 V_BSENLANE1(1U) 2297 2298 #define S_BSINSELLANE0 1 2299 #define M_BSINSELLANE0 0x3 2300 #define V_BSINSELLANE0(x) ((x) << S_BSINSELLANE0) 2301 #define G_BSINSELLANE0(x) (((x) >> S_BSINSELLANE0) & M_BSINSELLANE0) 2302 2303 #define S_BSENLANE0 0 2304 #define V_BSENLANE0(x) ((x) << S_BSENLANE0) 2305 #define F_BSENLANE0 V_BSENLANE0(1U) 2306 2307 /* registers for module MC7_PMRX */ 2308 #define MC7_PMRX_BASE_ADDR 0x100 2309 2310 #define A_MC7_CFG 0x100 2311 2312 #define S_IMPSETUPDATE 14 2313 #define V_IMPSETUPDATE(x) ((x) << S_IMPSETUPDATE) 2314 #define F_IMPSETUPDATE V_IMPSETUPDATE(1U) 2315 2316 #define S_IFEN 13 2317 #define V_IFEN(x) ((x) << S_IFEN) 2318 #define F_IFEN V_IFEN(1U) 2319 2320 #define S_TERM300 12 2321 #define V_TERM300(x) ((x) << S_TERM300) 2322 #define F_TERM300 V_TERM300(1U) 2323 2324 #define S_TERM150 11 2325 #define V_TERM150(x) ((x) << S_TERM150) 2326 #define F_TERM150 V_TERM150(1U) 2327 2328 #define S_SLOW 10 2329 #define V_SLOW(x) ((x) << S_SLOW) 2330 #define F_SLOW V_SLOW(1U) 2331 2332 #define S_WIDTH 8 2333 #define M_WIDTH 0x3 2334 #define V_WIDTH(x) ((x) << S_WIDTH) 2335 #define G_WIDTH(x) (((x) >> S_WIDTH) & M_WIDTH) 2336 2337 #define S_ODTEN 7 2338 #define V_ODTEN(x) ((x) << S_ODTEN) 2339 #define F_ODTEN V_ODTEN(1U) 2340 2341 #define S_BKS 6 2342 #define V_BKS(x) ((x) << S_BKS) 2343 #define F_BKS V_BKS(1U) 2344 2345 #define S_ORG 5 2346 #define V_ORG(x) ((x) << S_ORG) 2347 #define F_ORG V_ORG(1U) 2348 2349 #define S_DEN 2 2350 #define M_DEN 0x7 2351 #define V_DEN(x) ((x) << S_DEN) 2352 #define G_DEN(x) (((x) >> S_DEN) & M_DEN) 2353 2354 #define S_RDY 1 2355 #define V_RDY(x) ((x) << S_RDY) 2356 #define F_RDY V_RDY(1U) 2357 2358 #define S_CLKEN 0 2359 #define V_CLKEN(x) ((x) << S_CLKEN) 2360 #define F_CLKEN V_CLKEN(1U) 2361 2362 #define A_MC7_MODE 0x104 2363 2364 #define S_MODE 0 2365 #define M_MODE 0xffff 2366 #define V_MODE(x) ((x) << S_MODE) 2367 #define G_MODE(x) (((x) >> S_MODE) & M_MODE) 2368 2369 #define A_MC7_EXT_MODE1 0x108 2370 2371 #define S_OCDADJUSTMODE 20 2372 #define V_OCDADJUSTMODE(x) ((x) << S_OCDADJUSTMODE) 2373 #define F_OCDADJUSTMODE V_OCDADJUSTMODE(1U) 2374 2375 #define S_OCDCODE 16 2376 #define M_OCDCODE 0xf 2377 #define V_OCDCODE(x) ((x) << S_OCDCODE) 2378 #define G_OCDCODE(x) (((x) >> S_OCDCODE) & M_OCDCODE) 2379 2380 #define S_EXTMODE1 0 2381 #define M_EXTMODE1 0xffff 2382 #define V_EXTMODE1(x) ((x) << S_EXTMODE1) 2383 #define G_EXTMODE1(x) (((x) >> S_EXTMODE1) & M_EXTMODE1) 2384 2385 #define A_MC7_EXT_MODE2 0x10c 2386 2387 #define S_EXTMODE2 0 2388 #define M_EXTMODE2 0xffff 2389 #define V_EXTMODE2(x) ((x) << S_EXTMODE2) 2390 #define G_EXTMODE2(x) (((x) >> S_EXTMODE2) & M_EXTMODE2) 2391 2392 #define A_MC7_EXT_MODE3 0x110 2393 2394 #define S_EXTMODE3 0 2395 #define M_EXTMODE3 0xffff 2396 #define V_EXTMODE3(x) ((x) << S_EXTMODE3) 2397 #define G_EXTMODE3(x) (((x) >> S_EXTMODE3) & M_EXTMODE3) 2398 2399 #define A_MC7_PRE 0x114 2400 #define A_MC7_REF 0x118 2401 2402 #define S_PREREFDIV 1 2403 #define M_PREREFDIV 0x3fff 2404 #define V_PREREFDIV(x) ((x) << S_PREREFDIV) 2405 #define G_PREREFDIV(x) (((x) >> S_PREREFDIV) & M_PREREFDIV) 2406 2407 #define S_PERREFEN 0 2408 #define V_PERREFEN(x) ((x) << S_PERREFEN) 2409 #define F_PERREFEN V_PERREFEN(1U) 2410 2411 #define A_MC7_DLL 0x11c 2412 2413 #define S_DLLLOCK 31 2414 #define V_DLLLOCK(x) ((x) << S_DLLLOCK) 2415 #define F_DLLLOCK V_DLLLOCK(1U) 2416 2417 #define S_DLLDELTA 24 2418 #define M_DLLDELTA 0x7f 2419 #define V_DLLDELTA(x) ((x) << S_DLLDELTA) 2420 #define G_DLLDELTA(x) (((x) >> S_DLLDELTA) & M_DLLDELTA) 2421 2422 #define S_MANDELTA 3 2423 #define M_MANDELTA 0x7f 2424 #define V_MANDELTA(x) ((x) << S_MANDELTA) 2425 #define G_MANDELTA(x) (((x) >> S_MANDELTA) & M_MANDELTA) 2426 2427 #define S_DLLDELTASEL 2 2428 #define V_DLLDELTASEL(x) ((x) << S_DLLDELTASEL) 2429 #define F_DLLDELTASEL V_DLLDELTASEL(1U) 2430 2431 #define S_DLLENB 1 2432 #define V_DLLENB(x) ((x) << S_DLLENB) 2433 #define F_DLLENB V_DLLENB(1U) 2434 2435 #define S_DLLRST 0 2436 #define V_DLLRST(x) ((x) << S_DLLRST) 2437 #define F_DLLRST V_DLLRST(1U) 2438 2439 #define A_MC7_PARM 0x120 2440 2441 #define S_ACTTOPREDLY 26 2442 #define M_ACTTOPREDLY 0xf 2443 #define V_ACTTOPREDLY(x) ((x) << S_ACTTOPREDLY) 2444 #define G_ACTTOPREDLY(x) (((x) >> S_ACTTOPREDLY) & M_ACTTOPREDLY) 2445 2446 #define S_ACTTORDWRDLY 23 2447 #define M_ACTTORDWRDLY 0x7 2448 #define V_ACTTORDWRDLY(x) ((x) << S_ACTTORDWRDLY) 2449 #define G_ACTTORDWRDLY(x) (((x) >> S_ACTTORDWRDLY) & M_ACTTORDWRDLY) 2450 2451 #define S_PRECYC 20 2452 #define M_PRECYC 0x7 2453 #define V_PRECYC(x) ((x) << S_PRECYC) 2454 #define G_PRECYC(x) (((x) >> S_PRECYC) & M_PRECYC) 2455 2456 #define S_REFCYC 13 2457 #define M_REFCYC 0x7f 2458 #define V_REFCYC(x) ((x) << S_REFCYC) 2459 #define G_REFCYC(x) (((x) >> S_REFCYC) & M_REFCYC) 2460 2461 #define S_BKCYC 8 2462 #define M_BKCYC 0x1f 2463 #define V_BKCYC(x) ((x) << S_BKCYC) 2464 #define G_BKCYC(x) (((x) >> S_BKCYC) & M_BKCYC) 2465 2466 #define S_WRTORDDLY 4 2467 #define M_WRTORDDLY 0xf 2468 #define V_WRTORDDLY(x) ((x) << S_WRTORDDLY) 2469 #define G_WRTORDDLY(x) (((x) >> S_WRTORDDLY) & M_WRTORDDLY) 2470 2471 #define S_RDTOWRDLY 0 2472 #define M_RDTOWRDLY 0xf 2473 #define V_RDTOWRDLY(x) ((x) << S_RDTOWRDLY) 2474 #define G_RDTOWRDLY(x) (((x) >> S_RDTOWRDLY) & M_RDTOWRDLY) 2475 2476 #define A_MC7_HWM_WRR 0x124 2477 2478 #define S_MEM_HWM 26 2479 #define M_MEM_HWM 0x3f 2480 #define V_MEM_HWM(x) ((x) << S_MEM_HWM) 2481 #define G_MEM_HWM(x) (((x) >> S_MEM_HWM) & M_MEM_HWM) 2482 2483 #define S_ULP_HWM 22 2484 #define M_ULP_HWM 0xf 2485 #define V_ULP_HWM(x) ((x) << S_ULP_HWM) 2486 #define G_ULP_HWM(x) (((x) >> S_ULP_HWM) & M_ULP_HWM) 2487 2488 #define S_TOT_RLD_WT 14 2489 #define M_TOT_RLD_WT 0xff 2490 #define V_TOT_RLD_WT(x) ((x) << S_TOT_RLD_WT) 2491 #define G_TOT_RLD_WT(x) (((x) >> S_TOT_RLD_WT) & M_TOT_RLD_WT) 2492 2493 #define S_MEM_RLD_WT 7 2494 #define M_MEM_RLD_WT 0x7f 2495 #define V_MEM_RLD_WT(x) ((x) << S_MEM_RLD_WT) 2496 #define G_MEM_RLD_WT(x) (((x) >> S_MEM_RLD_WT) & M_MEM_RLD_WT) 2497 2498 #define S_ULP_RLD_WT 0 2499 #define M_ULP_RLD_WT 0x7f 2500 #define V_ULP_RLD_WT(x) ((x) << S_ULP_RLD_WT) 2501 #define G_ULP_RLD_WT(x) (((x) >> S_ULP_RLD_WT) & M_ULP_RLD_WT) 2502 2503 #define A_MC7_CAL 0x128 2504 2505 #define S_BUSY 31 2506 #define V_BUSY(x) ((x) << S_BUSY) 2507 #define F_BUSY V_BUSY(1U) 2508 2509 #define S_CAL_FAULT 30 2510 #define V_CAL_FAULT(x) ((x) << S_CAL_FAULT) 2511 #define F_CAL_FAULT V_CAL_FAULT(1U) 2512 2513 #define S_PER_CAL_DIV 22 2514 #define M_PER_CAL_DIV 0xff 2515 #define V_PER_CAL_DIV(x) ((x) << S_PER_CAL_DIV) 2516 #define G_PER_CAL_DIV(x) (((x) >> S_PER_CAL_DIV) & M_PER_CAL_DIV) 2517 2518 #define S_PER_CAL_EN 21 2519 #define V_PER_CAL_EN(x) ((x) << S_PER_CAL_EN) 2520 #define F_PER_CAL_EN V_PER_CAL_EN(1U) 2521 2522 #define S_SGL_CAL_EN 20 2523 #define V_SGL_CAL_EN(x) ((x) << S_SGL_CAL_EN) 2524 #define F_SGL_CAL_EN V_SGL_CAL_EN(1U) 2525 2526 #define S_IMP_UPD_MODE 19 2527 #define V_IMP_UPD_MODE(x) ((x) << S_IMP_UPD_MODE) 2528 #define F_IMP_UPD_MODE V_IMP_UPD_MODE(1U) 2529 2530 #define S_IMP_SEL 18 2531 #define V_IMP_SEL(x) ((x) << S_IMP_SEL) 2532 #define F_IMP_SEL V_IMP_SEL(1U) 2533 2534 #define S_IMP_MAN_PD 15 2535 #define M_IMP_MAN_PD 0x7 2536 #define V_IMP_MAN_PD(x) ((x) << S_IMP_MAN_PD) 2537 #define G_IMP_MAN_PD(x) (((x) >> S_IMP_MAN_PD) & M_IMP_MAN_PD) 2538 2539 #define S_IMP_MAN_PU 12 2540 #define M_IMP_MAN_PU 0x7 2541 #define V_IMP_MAN_PU(x) ((x) << S_IMP_MAN_PU) 2542 #define G_IMP_MAN_PU(x) (((x) >> S_IMP_MAN_PU) & M_IMP_MAN_PU) 2543 2544 #define S_IMP_CAL_PD 9 2545 #define M_IMP_CAL_PD 0x7 2546 #define V_IMP_CAL_PD(x) ((x) << S_IMP_CAL_PD) 2547 #define G_IMP_CAL_PD(x) (((x) >> S_IMP_CAL_PD) & M_IMP_CAL_PD) 2548 2549 #define S_IMP_CAL_PU 6 2550 #define M_IMP_CAL_PU 0x7 2551 #define V_IMP_CAL_PU(x) ((x) << S_IMP_CAL_PU) 2552 #define G_IMP_CAL_PU(x) (((x) >> S_IMP_CAL_PU) & M_IMP_CAL_PU) 2553 2554 #define S_IMP_SET_PD 3 2555 #define M_IMP_SET_PD 0x7 2556 #define V_IMP_SET_PD(x) ((x) << S_IMP_SET_PD) 2557 #define G_IMP_SET_PD(x) (((x) >> S_IMP_SET_PD) & M_IMP_SET_PD) 2558 2559 #define S_IMP_SET_PU 0 2560 #define M_IMP_SET_PU 0x7 2561 #define V_IMP_SET_PU(x) ((x) << S_IMP_SET_PU) 2562 #define G_IMP_SET_PU(x) (((x) >> S_IMP_SET_PU) & M_IMP_SET_PU) 2563 2564 #define A_MC7_ERR_ADDR 0x12c 2565 2566 #define S_ERRADDRESS 3 2567 #define M_ERRADDRESS 0x1fffffff 2568 #define V_ERRADDRESS(x) ((x) << S_ERRADDRESS) 2569 #define G_ERRADDRESS(x) (((x) >> S_ERRADDRESS) & M_ERRADDRESS) 2570 2571 #define S_ERRAGENT 1 2572 #define M_ERRAGENT 0x3 2573 #define V_ERRAGENT(x) ((x) << S_ERRAGENT) 2574 #define G_ERRAGENT(x) (((x) >> S_ERRAGENT) & M_ERRAGENT) 2575 2576 #define S_ERROP 0 2577 #define V_ERROP(x) ((x) << S_ERROP) 2578 #define F_ERROP V_ERROP(1U) 2579 2580 #define A_MC7_ECC 0x130 2581 2582 #define S_UECNT 10 2583 #define M_UECNT 0xff 2584 #define V_UECNT(x) ((x) << S_UECNT) 2585 #define G_UECNT(x) (((x) >> S_UECNT) & M_UECNT) 2586 2587 #define S_CECNT 2 2588 #define M_CECNT 0xff 2589 #define V_CECNT(x) ((x) << S_CECNT) 2590 #define G_CECNT(x) (((x) >> S_CECNT) & M_CECNT) 2591 2592 #define S_ECCCHKEN 1 2593 #define V_ECCCHKEN(x) ((x) << S_ECCCHKEN) 2594 #define F_ECCCHKEN V_ECCCHKEN(1U) 2595 2596 #define S_ECCGENEN 0 2597 #define V_ECCGENEN(x) ((x) << S_ECCGENEN) 2598 #define F_ECCGENEN V_ECCGENEN(1U) 2599 2600 #define A_MC7_CE_ADDR 0x134 2601 #define A_MC7_CE_DATA0 0x138 2602 #define A_MC7_CE_DATA1 0x13c 2603 #define A_MC7_CE_DATA2 0x140 2604 2605 #define S_DATA 0 2606 #define M_DATA 0xff 2607 #define V_DATA(x) ((x) << S_DATA) 2608 #define G_DATA(x) (((x) >> S_DATA) & M_DATA) 2609 2610 #define A_MC7_UE_ADDR 0x144 2611 #define A_MC7_UE_DATA0 0x148 2612 #define A_MC7_UE_DATA1 0x14c 2613 #define A_MC7_UE_DATA2 0x150 2614 #define A_MC7_BD_ADDR 0x154 2615 2616 #define S_ADDR 3 2617 #define M_ADDR 0x1fffffff 2618 #define V_ADDR(x) ((x) << S_ADDR) 2619 #define G_ADDR(x) (((x) >> S_ADDR) & M_ADDR) 2620 2621 #define A_MC7_BD_DATA0 0x158 2622 #define A_MC7_BD_DATA1 0x15c 2623 #define A_MC7_BD_DATA2 0x160 2624 #define A_MC7_BD_OP 0x164 2625 2626 #define S_OP 0 2627 #define V_OP(x) ((x) << S_OP) 2628 #define F_OP V_OP(1U) 2629 2630 #define A_MC7_BIST_ADDR_BEG 0x168 2631 2632 #define S_ADDRBEG 5 2633 #define M_ADDRBEG 0x7ffffff 2634 #define V_ADDRBEG(x) ((x) << S_ADDRBEG) 2635 #define G_ADDRBEG(x) (((x) >> S_ADDRBEG) & M_ADDRBEG) 2636 2637 #define A_MC7_BIST_ADDR_END 0x16c 2638 2639 #define S_ADDREND 5 2640 #define M_ADDREND 0x7ffffff 2641 #define V_ADDREND(x) ((x) << S_ADDREND) 2642 #define G_ADDREND(x) (((x) >> S_ADDREND) & M_ADDREND) 2643 2644 #define A_MC7_BIST_DATA 0x170 2645 #define A_MC7_BIST_OP 0x174 2646 2647 #define S_GAP 4 2648 #define M_GAP 0x1f 2649 #define V_GAP(x) ((x) << S_GAP) 2650 #define G_GAP(x) (((x) >> S_GAP) & M_GAP) 2651 2652 #define S_CONT 3 2653 #define V_CONT(x) ((x) << S_CONT) 2654 #define F_CONT V_CONT(1U) 2655 2656 #define S_DATAPAT 1 2657 #define M_DATAPAT 0x3 2658 #define V_DATAPAT(x) ((x) << S_DATAPAT) 2659 #define G_DATAPAT(x) (((x) >> S_DATAPAT) & M_DATAPAT) 2660 2661 #define A_MC7_INT_ENABLE 0x178 2662 2663 #define S_AE 17 2664 #define V_AE(x) ((x) << S_AE) 2665 #define F_AE V_AE(1U) 2666 2667 #define S_PE 2 2668 #define M_PE 0x7fff 2669 #define V_PE(x) ((x) << S_PE) 2670 #define G_PE(x) (((x) >> S_PE) & M_PE) 2671 2672 #define S_UE 1 2673 #define V_UE(x) ((x) << S_UE) 2674 #define F_UE V_UE(1U) 2675 2676 #define S_CE 0 2677 #define V_CE(x) ((x) << S_CE) 2678 #define F_CE V_CE(1U) 2679 2680 #define A_MC7_INT_CAUSE 0x17c 2681 2682 /* registers for module MC7_PMTX */ 2683 #define MC7_PMTX_BASE_ADDR 0x180 2684 2685 /* registers for module MC7_CM */ 2686 #define MC7_CM_BASE_ADDR 0x200 2687 2688 /* registers for module CIM */ 2689 #define CIM_BASE_ADDR 0x280 2690 2691 #define A_CIM_BOOT_CFG 0x280 2692 2693 #define S_BOOTADDR 2 2694 #define M_BOOTADDR 0x3fffffff 2695 #define V_BOOTADDR(x) ((x) << S_BOOTADDR) 2696 #define G_BOOTADDR(x) (((x) >> S_BOOTADDR) & M_BOOTADDR) 2697 2698 #define S_BOOTSDRAM 1 2699 #define V_BOOTSDRAM(x) ((x) << S_BOOTSDRAM) 2700 #define F_BOOTSDRAM V_BOOTSDRAM(1U) 2701 2702 #define S_UPCRST 0 2703 #define V_UPCRST(x) ((x) << S_UPCRST) 2704 #define F_UPCRST V_UPCRST(1U) 2705 2706 #define A_CIM_FLASH_BASE_ADDR 0x284 2707 2708 #define S_FLASHBASEADDR 2 2709 #define M_FLASHBASEADDR 0x3fffff 2710 #define V_FLASHBASEADDR(x) ((x) << S_FLASHBASEADDR) 2711 #define G_FLASHBASEADDR(x) (((x) >> S_FLASHBASEADDR) & M_FLASHBASEADDR) 2712 2713 #define A_CIM_FLASH_ADDR_SIZE 0x288 2714 2715 #define S_FLASHADDRSIZE 2 2716 #define M_FLASHADDRSIZE 0x3fffff 2717 #define V_FLASHADDRSIZE(x) ((x) << S_FLASHADDRSIZE) 2718 #define G_FLASHADDRSIZE(x) (((x) >> S_FLASHADDRSIZE) & M_FLASHADDRSIZE) 2719 2720 #define A_CIM_SDRAM_BASE_ADDR 0x28c 2721 2722 #define S_SDRAMBASEADDR 2 2723 #define M_SDRAMBASEADDR 0x3fffffff 2724 #define V_SDRAMBASEADDR(x) ((x) << S_SDRAMBASEADDR) 2725 #define G_SDRAMBASEADDR(x) (((x) >> S_SDRAMBASEADDR) & M_SDRAMBASEADDR) 2726 2727 #define A_CIM_SDRAM_ADDR_SIZE 0x290 2728 2729 #define S_SDRAMADDRSIZE 2 2730 #define M_SDRAMADDRSIZE 0x3fffffff 2731 #define V_SDRAMADDRSIZE(x) ((x) << S_SDRAMADDRSIZE) 2732 #define G_SDRAMADDRSIZE(x) (((x) >> S_SDRAMADDRSIZE) & M_SDRAMADDRSIZE) 2733 2734 #define A_CIM_UP_SPARE_INT 0x294 2735 2736 #define S_UPSPAREINT 0 2737 #define M_UPSPAREINT 0x7 2738 #define V_UPSPAREINT(x) ((x) << S_UPSPAREINT) 2739 #define G_UPSPAREINT(x) (((x) >> S_UPSPAREINT) & M_UPSPAREINT) 2740 2741 #define A_CIM_HOST_INT_ENABLE 0x298 2742 2743 #define S_TIMER1INTEN 15 2744 #define V_TIMER1INTEN(x) ((x) << S_TIMER1INTEN) 2745 #define F_TIMER1INTEN V_TIMER1INTEN(1U) 2746 2747 #define S_TIMER0INTEN 14 2748 #define V_TIMER0INTEN(x) ((x) << S_TIMER0INTEN) 2749 #define F_TIMER0INTEN V_TIMER0INTEN(1U) 2750 2751 #define S_PREFDROPINTEN 13 2752 #define V_PREFDROPINTEN(x) ((x) << S_PREFDROPINTEN) 2753 #define F_PREFDROPINTEN V_PREFDROPINTEN(1U) 2754 2755 #define S_BLKWRPLINTEN 12 2756 #define V_BLKWRPLINTEN(x) ((x) << S_BLKWRPLINTEN) 2757 #define F_BLKWRPLINTEN V_BLKWRPLINTEN(1U) 2758 2759 #define S_BLKRDPLINTEN 11 2760 #define V_BLKRDPLINTEN(x) ((x) << S_BLKRDPLINTEN) 2761 #define F_BLKRDPLINTEN V_BLKRDPLINTEN(1U) 2762 2763 #define S_BLKWRCTLINTEN 10 2764 #define V_BLKWRCTLINTEN(x) ((x) << S_BLKWRCTLINTEN) 2765 #define F_BLKWRCTLINTEN V_BLKWRCTLINTEN(1U) 2766 2767 #define S_BLKRDCTLINTEN 9 2768 #define V_BLKRDCTLINTEN(x) ((x) << S_BLKRDCTLINTEN) 2769 #define F_BLKRDCTLINTEN V_BLKRDCTLINTEN(1U) 2770 2771 #define S_BLKWRFLASHINTEN 8 2772 #define V_BLKWRFLASHINTEN(x) ((x) << S_BLKWRFLASHINTEN) 2773 #define F_BLKWRFLASHINTEN V_BLKWRFLASHINTEN(1U) 2774 2775 #define S_BLKRDFLASHINTEN 7 2776 #define V_BLKRDFLASHINTEN(x) ((x) << S_BLKRDFLASHINTEN) 2777 #define F_BLKRDFLASHINTEN V_BLKRDFLASHINTEN(1U) 2778 2779 #define S_SGLWRFLASHINTEN 6 2780 #define V_SGLWRFLASHINTEN(x) ((x) << S_SGLWRFLASHINTEN) 2781 #define F_SGLWRFLASHINTEN V_SGLWRFLASHINTEN(1U) 2782 2783 #define S_WRBLKFLASHINTEN 5 2784 #define V_WRBLKFLASHINTEN(x) ((x) << S_WRBLKFLASHINTEN) 2785 #define F_WRBLKFLASHINTEN V_WRBLKFLASHINTEN(1U) 2786 2787 #define S_BLKWRBOOTINTEN 4 2788 #define V_BLKWRBOOTINTEN(x) ((x) << S_BLKWRBOOTINTEN) 2789 #define F_BLKWRBOOTINTEN V_BLKWRBOOTINTEN(1U) 2790 2791 #define S_BLKRDBOOTINTEN 3 2792 #define V_BLKRDBOOTINTEN(x) ((x) << S_BLKRDBOOTINTEN) 2793 #define F_BLKRDBOOTINTEN V_BLKRDBOOTINTEN(1U) 2794 2795 #define S_FLASHRANGEINTEN 2 2796 #define V_FLASHRANGEINTEN(x) ((x) << S_FLASHRANGEINTEN) 2797 #define F_FLASHRANGEINTEN V_FLASHRANGEINTEN(1U) 2798 2799 #define S_SDRAMRANGEINTEN 1 2800 #define V_SDRAMRANGEINTEN(x) ((x) << S_SDRAMRANGEINTEN) 2801 #define F_SDRAMRANGEINTEN V_SDRAMRANGEINTEN(1U) 2802 2803 #define S_RSVDSPACEINTEN 0 2804 #define V_RSVDSPACEINTEN(x) ((x) << S_RSVDSPACEINTEN) 2805 #define F_RSVDSPACEINTEN V_RSVDSPACEINTEN(1U) 2806 2807 #define A_CIM_HOST_INT_CAUSE 0x29c 2808 2809 #define S_TIMER1INT 15 2810 #define V_TIMER1INT(x) ((x) << S_TIMER1INT) 2811 #define F_TIMER1INT V_TIMER1INT(1U) 2812 2813 #define S_TIMER0INT 14 2814 #define V_TIMER0INT(x) ((x) << S_TIMER0INT) 2815 #define F_TIMER0INT V_TIMER0INT(1U) 2816 2817 #define S_PREFDROPINT 13 2818 #define V_PREFDROPINT(x) ((x) << S_PREFDROPINT) 2819 #define F_PREFDROPINT V_PREFDROPINT(1U) 2820 2821 #define S_BLKWRPLINT 12 2822 #define V_BLKWRPLINT(x) ((x) << S_BLKWRPLINT) 2823 #define F_BLKWRPLINT V_BLKWRPLINT(1U) 2824 2825 #define S_BLKRDPLINT 11 2826 #define V_BLKRDPLINT(x) ((x) << S_BLKRDPLINT) 2827 #define F_BLKRDPLINT V_BLKRDPLINT(1U) 2828 2829 #define S_BLKWRCTLINT 10 2830 #define V_BLKWRCTLINT(x) ((x) << S_BLKWRCTLINT) 2831 #define F_BLKWRCTLINT V_BLKWRCTLINT(1U) 2832 2833 #define S_BLKRDCTLINT 9 2834 #define V_BLKRDCTLINT(x) ((x) << S_BLKRDCTLINT) 2835 #define F_BLKRDCTLINT V_BLKRDCTLINT(1U) 2836 2837 #define S_BLKWRFLASHINT 8 2838 #define V_BLKWRFLASHINT(x) ((x) << S_BLKWRFLASHINT) 2839 #define F_BLKWRFLASHINT V_BLKWRFLASHINT(1U) 2840 2841 #define S_BLKRDFLASHINT 7 2842 #define V_BLKRDFLASHINT(x) ((x) << S_BLKRDFLASHINT) 2843 #define F_BLKRDFLASHINT V_BLKRDFLASHINT(1U) 2844 2845 #define S_SGLWRFLASHINT 6 2846 #define V_SGLWRFLASHINT(x) ((x) << S_SGLWRFLASHINT) 2847 #define F_SGLWRFLASHINT V_SGLWRFLASHINT(1U) 2848 2849 #define S_WRBLKFLASHINT 5 2850 #define V_WRBLKFLASHINT(x) ((x) << S_WRBLKFLASHINT) 2851 #define F_WRBLKFLASHINT V_WRBLKFLASHINT(1U) 2852 2853 #define S_BLKWRBOOTINT 4 2854 #define V_BLKWRBOOTINT(x) ((x) << S_BLKWRBOOTINT) 2855 #define F_BLKWRBOOTINT V_BLKWRBOOTINT(1U) 2856 2857 #define S_BLKRDBOOTINT 3 2858 #define V_BLKRDBOOTINT(x) ((x) << S_BLKRDBOOTINT) 2859 #define F_BLKRDBOOTINT V_BLKRDBOOTINT(1U) 2860 2861 #define S_FLASHRANGEINT 2 2862 #define V_FLASHRANGEINT(x) ((x) << S_FLASHRANGEINT) 2863 #define F_FLASHRANGEINT V_FLASHRANGEINT(1U) 2864 2865 #define S_SDRAMRANGEINT 1 2866 #define V_SDRAMRANGEINT(x) ((x) << S_SDRAMRANGEINT) 2867 #define F_SDRAMRANGEINT V_SDRAMRANGEINT(1U) 2868 2869 #define S_RSVDSPACEINT 0 2870 #define V_RSVDSPACEINT(x) ((x) << S_RSVDSPACEINT) 2871 #define F_RSVDSPACEINT V_RSVDSPACEINT(1U) 2872 2873 #define A_CIM_UP_INT_ENABLE 0x2a0 2874 2875 #define S_MSTPLINTEN 16 2876 #define V_MSTPLINTEN(x) ((x) << S_MSTPLINTEN) 2877 #define F_MSTPLINTEN V_MSTPLINTEN(1U) 2878 2879 #define A_CIM_UP_INT_CAUSE 0x2a4 2880 2881 #define S_MSTPLINT 16 2882 #define V_MSTPLINT(x) ((x) << S_MSTPLINT) 2883 #define F_MSTPLINT V_MSTPLINT(1U) 2884 2885 #define A_CIM_IBQ_FULLA_THRSH 0x2a8 2886 2887 #define S_IBQ0FULLTHRSH 0 2888 #define M_IBQ0FULLTHRSH 0x1ff 2889 #define V_IBQ0FULLTHRSH(x) ((x) << S_IBQ0FULLTHRSH) 2890 #define G_IBQ0FULLTHRSH(x) (((x) >> S_IBQ0FULLTHRSH) & M_IBQ0FULLTHRSH) 2891 2892 #define S_IBQ1FULLTHRSH 16 2893 #define M_IBQ1FULLTHRSH 0x1ff 2894 #define V_IBQ1FULLTHRSH(x) ((x) << S_IBQ1FULLTHRSH) 2895 #define G_IBQ1FULLTHRSH(x) (((x) >> S_IBQ1FULLTHRSH) & M_IBQ1FULLTHRSH) 2896 2897 #define A_CIM_IBQ_FULLB_THRSH 0x2ac 2898 2899 #define S_IBQ2FULLTHRSH 0 2900 #define M_IBQ2FULLTHRSH 0x1ff 2901 #define V_IBQ2FULLTHRSH(x) ((x) << S_IBQ2FULLTHRSH) 2902 #define G_IBQ2FULLTHRSH(x) (((x) >> S_IBQ2FULLTHRSH) & M_IBQ2FULLTHRSH) 2903 2904 #define S_IBQ3FULLTHRSH 16 2905 #define M_IBQ3FULLTHRSH 0x1ff 2906 #define V_IBQ3FULLTHRSH(x) ((x) << S_IBQ3FULLTHRSH) 2907 #define G_IBQ3FULLTHRSH(x) (((x) >> S_IBQ3FULLTHRSH) & M_IBQ3FULLTHRSH) 2908 2909 #define A_CIM_HOST_ACC_CTRL 0x2b0 2910 2911 #define S_HOSTBUSY 17 2912 #define V_HOSTBUSY(x) ((x) << S_HOSTBUSY) 2913 #define F_HOSTBUSY V_HOSTBUSY(1U) 2914 2915 #define S_HOSTWRITE 16 2916 #define V_HOSTWRITE(x) ((x) << S_HOSTWRITE) 2917 #define F_HOSTWRITE V_HOSTWRITE(1U) 2918 2919 #define S_HOSTADDR 0 2920 #define M_HOSTADDR 0xffff 2921 #define V_HOSTADDR(x) ((x) << S_HOSTADDR) 2922 #define G_HOSTADDR(x) (((x) >> S_HOSTADDR) & M_HOSTADDR) 2923 2924 #define A_CIM_HOST_ACC_DATA 0x2b4 2925 #define A_CIM_IBQ_DBG_CFG 0x2c0 2926 2927 #define S_IBQDBGADDR 16 2928 #define M_IBQDBGADDR 0x1ff 2929 #define V_IBQDBGADDR(x) ((x) << S_IBQDBGADDR) 2930 #define G_IBQDBGADDR(x) (((x) >> S_IBQDBGADDR) & M_IBQDBGADDR) 2931 2932 #define S_IBQDBGQID 3 2933 #define M_IBQDBGQID 0x3 2934 #define V_IBQDBGQID(x) ((x) << S_IBQDBGQID) 2935 #define G_IBQDBGQID(x) (((x) >> S_IBQDBGQID) & M_IBQDBGQID) 2936 2937 #define S_IBQDBGWR 2 2938 #define V_IBQDBGWR(x) ((x) << S_IBQDBGWR) 2939 #define F_IBQDBGWR V_IBQDBGWR(1U) 2940 2941 #define S_IBQDBGBUSY 1 2942 #define V_IBQDBGBUSY(x) ((x) << S_IBQDBGBUSY) 2943 #define F_IBQDBGBUSY V_IBQDBGBUSY(1U) 2944 2945 #define S_IBQDBGEN 0 2946 #define V_IBQDBGEN(x) ((x) << S_IBQDBGEN) 2947 #define F_IBQDBGEN V_IBQDBGEN(1U) 2948 2949 #define A_CIM_OBQ_DBG_CFG 0x2c4 2950 2951 #define S_OBQDBGADDR 16 2952 #define M_OBQDBGADDR 0x1ff 2953 #define V_OBQDBGADDR(x) ((x) << S_OBQDBGADDR) 2954 #define G_OBQDBGADDR(x) (((x) >> S_OBQDBGADDR) & M_OBQDBGADDR) 2955 2956 #define S_OBQDBGQID 3 2957 #define M_OBQDBGQID 0x3 2958 #define V_OBQDBGQID(x) ((x) << S_OBQDBGQID) 2959 #define G_OBQDBGQID(x) (((x) >> S_OBQDBGQID) & M_OBQDBGQID) 2960 2961 #define S_OBQDBGWR 2 2962 #define V_OBQDBGWR(x) ((x) << S_OBQDBGWR) 2963 #define F_OBQDBGWR V_OBQDBGWR(1U) 2964 2965 #define S_OBQDBGBUSY 1 2966 #define V_OBQDBGBUSY(x) ((x) << S_OBQDBGBUSY) 2967 #define F_OBQDBGBUSY V_OBQDBGBUSY(1U) 2968 2969 #define S_OBQDBGEN 0 2970 #define V_OBQDBGEN(x) ((x) << S_OBQDBGEN) 2971 #define F_OBQDBGEN V_OBQDBGEN(1U) 2972 2973 #define A_CIM_IBQ_DBG_DATA 0x2c8 2974 #define A_CIM_OBQ_DBG_DATA 0x2cc 2975 #define A_CIM_CDEBUGDATA 0x2d0 2976 2977 #define S_CDEBUGDATAH 16 2978 #define M_CDEBUGDATAH 0xffff 2979 #define V_CDEBUGDATAH(x) ((x) << S_CDEBUGDATAH) 2980 #define G_CDEBUGDATAH(x) (((x) >> S_CDEBUGDATAH) & M_CDEBUGDATAH) 2981 2982 #define S_CDEBUGDATAL 0 2983 #define M_CDEBUGDATAL 0xffff 2984 #define V_CDEBUGDATAL(x) ((x) << S_CDEBUGDATAL) 2985 #define G_CDEBUGDATAL(x) (((x) >> S_CDEBUGDATAL) & M_CDEBUGDATAL) 2986 2987 #define A_CIM_DEBUGCFG 0x2e0 2988 2989 #define S_POLADBGRDPTR 23 2990 #define M_POLADBGRDPTR 0x1ff 2991 #define V_POLADBGRDPTR(x) ((x) << S_POLADBGRDPTR) 2992 #define G_POLADBGRDPTR(x) (((x) >> S_POLADBGRDPTR) & M_POLADBGRDPTR) 2993 2994 #define S_PILADBGRDPTR 14 2995 #define M_PILADBGRDPTR 0x1ff 2996 #define V_PILADBGRDPTR(x) ((x) << S_PILADBGRDPTR) 2997 #define G_PILADBGRDPTR(x) (((x) >> S_PILADBGRDPTR) & M_PILADBGRDPTR) 2998 2999 #define S_CIM_LADBGEN 12 3000 #define V_CIM_LADBGEN(x) ((x) << S_CIM_LADBGEN) 3001 #define F_CIM_LADBGEN V_CIM_LADBGEN(1U) 3002 3003 #define S_DEBUGSELHI 5 3004 #define M_DEBUGSELHI 0x1f 3005 #define V_DEBUGSELHI(x) ((x) << S_DEBUGSELHI) 3006 #define G_DEBUGSELHI(x) (((x) >> S_DEBUGSELHI) & M_DEBUGSELHI) 3007 3008 #define S_DEBUGSELLO 0 3009 #define M_DEBUGSELLO 0x1f 3010 #define V_DEBUGSELLO(x) ((x) << S_DEBUGSELLO) 3011 #define G_DEBUGSELLO(x) (((x) >> S_DEBUGSELLO) & M_DEBUGSELLO) 3012 3013 #define A_CIM_DEBUGSTS 0x2e4 3014 3015 #define S_POLADBGWRPTR 16 3016 #define M_POLADBGWRPTR 0x1ff 3017 #define V_POLADBGWRPTR(x) ((x) << S_POLADBGWRPTR) 3018 #define G_POLADBGWRPTR(x) (((x) >> S_POLADBGWRPTR) & M_POLADBGWRPTR) 3019 3020 #define S_PILADBGWRPTR 0 3021 #define M_PILADBGWRPTR 0x1ff 3022 #define V_PILADBGWRPTR(x) ((x) << S_PILADBGWRPTR) 3023 #define G_PILADBGWRPTR(x) (((x) >> S_PILADBGWRPTR) & M_PILADBGWRPTR) 3024 3025 #define A_CIM_PO_LA_DEBUGDATA 0x2e8 3026 #define A_CIM_PI_LA_DEBUGDATA 0x2ec 3027 3028 /* registers for module TP1 */ 3029 #define TP1_BASE_ADDR 0x300 3030 3031 #define A_TP_IN_CONFIG 0x300 3032 3033 #define S_RXFBARBPRIO 25 3034 #define V_RXFBARBPRIO(x) ((x) << S_RXFBARBPRIO) 3035 #define F_RXFBARBPRIO V_RXFBARBPRIO(1U) 3036 3037 #define S_TXFBARBPRIO 24 3038 #define V_TXFBARBPRIO(x) ((x) << S_TXFBARBPRIO) 3039 #define F_TXFBARBPRIO V_TXFBARBPRIO(1U) 3040 3041 #define S_DBMAXOPCNT 16 3042 #define M_DBMAXOPCNT 0xff 3043 #define V_DBMAXOPCNT(x) ((x) << S_DBMAXOPCNT) 3044 #define G_DBMAXOPCNT(x) (((x) >> S_DBMAXOPCNT) & M_DBMAXOPCNT) 3045 3046 #define S_NICMODE 14 3047 #define V_NICMODE(x) ((x) << S_NICMODE) 3048 #define F_NICMODE V_NICMODE(1U) 3049 3050 #define S_ECHECKSUMCHECKTCP 13 3051 #define V_ECHECKSUMCHECKTCP(x) ((x) << S_ECHECKSUMCHECKTCP) 3052 #define F_ECHECKSUMCHECKTCP V_ECHECKSUMCHECKTCP(1U) 3053 3054 #define S_ECHECKSUMCHECKIP 12 3055 #define V_ECHECKSUMCHECKIP(x) ((x) << S_ECHECKSUMCHECKIP) 3056 #define F_ECHECKSUMCHECKIP V_ECHECKSUMCHECKIP(1U) 3057 3058 #define S_ECPL 10 3059 #define V_ECPL(x) ((x) << S_ECPL) 3060 #define F_ECPL V_ECPL(1U) 3061 3062 #define S_EETHERNET 8 3063 #define V_EETHERNET(x) ((x) << S_EETHERNET) 3064 #define F_EETHERNET V_EETHERNET(1U) 3065 3066 #define S_ETUNNEL 7 3067 #define V_ETUNNEL(x) ((x) << S_ETUNNEL) 3068 #define F_ETUNNEL V_ETUNNEL(1U) 3069 3070 #define S_CCHECKSUMCHECKTCP 6 3071 #define V_CCHECKSUMCHECKTCP(x) ((x) << S_CCHECKSUMCHECKTCP) 3072 #define F_CCHECKSUMCHECKTCP V_CCHECKSUMCHECKTCP(1U) 3073 3074 #define S_CCHECKSUMCHECKIP 5 3075 #define V_CCHECKSUMCHECKIP(x) ((x) << S_CCHECKSUMCHECKIP) 3076 #define F_CCHECKSUMCHECKIP V_CCHECKSUMCHECKIP(1U) 3077 3078 #define S_CCPL 3 3079 #define V_CCPL(x) ((x) << S_CCPL) 3080 #define F_CCPL V_CCPL(1U) 3081 3082 #define S_CETHERNET 1 3083 #define V_CETHERNET(x) ((x) << S_CETHERNET) 3084 #define F_CETHERNET V_CETHERNET(1U) 3085 3086 #define S_CTUNNEL 0 3087 #define V_CTUNNEL(x) ((x) << S_CTUNNEL) 3088 #define F_CTUNNEL V_CTUNNEL(1U) 3089 3090 #define S_IPV6ENABLE 15 3091 #define V_IPV6ENABLE(x) ((x) << S_IPV6ENABLE) 3092 #define F_IPV6ENABLE V_IPV6ENABLE(1U) 3093 3094 #define A_TP_OUT_CONFIG 0x304 3095 3096 #define S_VLANEXTRACTIONENABLE 12 3097 #define V_VLANEXTRACTIONENABLE(x) ((x) << S_VLANEXTRACTIONENABLE) 3098 #define F_VLANEXTRACTIONENABLE V_VLANEXTRACTIONENABLE(1U) 3099 3100 #define S_ECHECKSUMGENERATETCP 11 3101 #define V_ECHECKSUMGENERATETCP(x) ((x) << S_ECHECKSUMGENERATETCP) 3102 #define F_ECHECKSUMGENERATETCP V_ECHECKSUMGENERATETCP(1U) 3103 3104 #define S_ECHECKSUMGENERATEIP 10 3105 #define V_ECHECKSUMGENERATEIP(x) ((x) << S_ECHECKSUMGENERATEIP) 3106 #define F_ECHECKSUMGENERATEIP V_ECHECKSUMGENERATEIP(1U) 3107 3108 #define S_OUT_ECPL 8 3109 #define V_OUT_ECPL(x) ((x) << S_OUT_ECPL) 3110 #define F_OUT_ECPL V_OUT_ECPL(1U) 3111 3112 #define S_OUT_EETHERNET 6 3113 #define V_OUT_EETHERNET(x) ((x) << S_OUT_EETHERNET) 3114 #define F_OUT_EETHERNET V_OUT_EETHERNET(1U) 3115 3116 #define S_CCHECKSUMGENERATETCP 5 3117 #define V_CCHECKSUMGENERATETCP(x) ((x) << S_CCHECKSUMGENERATETCP) 3118 #define F_CCHECKSUMGENERATETCP V_CCHECKSUMGENERATETCP(1U) 3119 3120 #define S_CCHECKSUMGENERATEIP 4 3121 #define V_CCHECKSUMGENERATEIP(x) ((x) << S_CCHECKSUMGENERATEIP) 3122 #define F_CCHECKSUMGENERATEIP V_CCHECKSUMGENERATEIP(1U) 3123 3124 #define S_OUT_CCPL 2 3125 #define V_OUT_CCPL(x) ((x) << S_OUT_CCPL) 3126 #define F_OUT_CCPL V_OUT_CCPL(1U) 3127 3128 #define S_OUT_CETHERNET 0 3129 #define V_OUT_CETHERNET(x) ((x) << S_OUT_CETHERNET) 3130 #define F_OUT_CETHERNET V_OUT_CETHERNET(1U) 3131 3132 #define S_IPIDSPLITMODE 16 3133 #define V_IPIDSPLITMODE(x) ((x) << S_IPIDSPLITMODE) 3134 #define F_IPIDSPLITMODE V_IPIDSPLITMODE(1U) 3135 3136 #define S_VLANEXTRACTIONENABLE2NDPORT 13 3137 #define V_VLANEXTRACTIONENABLE2NDPORT(x) ((x) << S_VLANEXTRACTIONENABLE2NDPORT) 3138 #define F_VLANEXTRACTIONENABLE2NDPORT V_VLANEXTRACTIONENABLE2NDPORT(1U) 3139 3140 #define A_TP_GLOBAL_CONFIG 0x308 3141 3142 #define S_RXFLOWCONTROLDISABLE 25 3143 #define V_RXFLOWCONTROLDISABLE(x) ((x) << S_RXFLOWCONTROLDISABLE) 3144 #define F_RXFLOWCONTROLDISABLE V_RXFLOWCONTROLDISABLE(1U) 3145 3146 #define S_TXPACINGENABLE 24 3147 #define V_TXPACINGENABLE(x) ((x) << S_TXPACINGENABLE) 3148 #define F_TXPACINGENABLE V_TXPACINGENABLE(1U) 3149 3150 #define S_ATTACKFILTERENABLE 23 3151 #define V_ATTACKFILTERENABLE(x) ((x) << S_ATTACKFILTERENABLE) 3152 #define F_ATTACKFILTERENABLE V_ATTACKFILTERENABLE(1U) 3153 3154 #define S_SYNCOOKIENOOPTIONS 22 3155 #define V_SYNCOOKIENOOPTIONS(x) ((x) << S_SYNCOOKIENOOPTIONS) 3156 #define F_SYNCOOKIENOOPTIONS V_SYNCOOKIENOOPTIONS(1U) 3157 3158 #define S_PROTECTEDMODE 21 3159 #define V_PROTECTEDMODE(x) ((x) << S_PROTECTEDMODE) 3160 #define F_PROTECTEDMODE V_PROTECTEDMODE(1U) 3161 3162 #define S_PINGDROP 20 3163 #define V_PINGDROP(x) ((x) << S_PINGDROP) 3164 #define F_PINGDROP V_PINGDROP(1U) 3165 3166 #define S_FRAGMENTDROP 19 3167 #define V_FRAGMENTDROP(x) ((x) << S_FRAGMENTDROP) 3168 #define F_FRAGMENTDROP V_FRAGMENTDROP(1U) 3169 3170 #define S_FIVETUPLELOOKUP 17 3171 #define M_FIVETUPLELOOKUP 0x3 3172 #define V_FIVETUPLELOOKUP(x) ((x) << S_FIVETUPLELOOKUP) 3173 #define G_FIVETUPLELOOKUP(x) (((x) >> S_FIVETUPLELOOKUP) & M_FIVETUPLELOOKUP) 3174 3175 #define S_PATHMTU 15 3176 #define V_PATHMTU(x) ((x) << S_PATHMTU) 3177 #define F_PATHMTU V_PATHMTU(1U) 3178 3179 #define S_IPIDENTSPLIT 14 3180 #define V_IPIDENTSPLIT(x) ((x) << S_IPIDENTSPLIT) 3181 #define F_IPIDENTSPLIT V_IPIDENTSPLIT(1U) 3182 3183 #define S_IPCHECKSUMOFFLOAD 13 3184 #define V_IPCHECKSUMOFFLOAD(x) ((x) << S_IPCHECKSUMOFFLOAD) 3185 #define F_IPCHECKSUMOFFLOAD V_IPCHECKSUMOFFLOAD(1U) 3186 3187 #define S_UDPCHECKSUMOFFLOAD 12 3188 #define V_UDPCHECKSUMOFFLOAD(x) ((x) << S_UDPCHECKSUMOFFLOAD) 3189 #define F_UDPCHECKSUMOFFLOAD V_UDPCHECKSUMOFFLOAD(1U) 3190 3191 #define S_TCPCHECKSUMOFFLOAD 11 3192 #define V_TCPCHECKSUMOFFLOAD(x) ((x) << S_TCPCHECKSUMOFFLOAD) 3193 #define F_TCPCHECKSUMOFFLOAD V_TCPCHECKSUMOFFLOAD(1U) 3194 3195 #define S_QOSMAPPING 10 3196 #define V_QOSMAPPING(x) ((x) << S_QOSMAPPING) 3197 #define F_QOSMAPPING V_QOSMAPPING(1U) 3198 3199 #define S_TCAMSERVERUSE 8 3200 #define M_TCAMSERVERUSE 0x3 3201 #define V_TCAMSERVERUSE(x) ((x) << S_TCAMSERVERUSE) 3202 #define G_TCAMSERVERUSE(x) (((x) >> S_TCAMSERVERUSE) & M_TCAMSERVERUSE) 3203 3204 #define S_IPTTL 0 3205 #define M_IPTTL 0xff 3206 #define V_IPTTL(x) ((x) << S_IPTTL) 3207 #define G_IPTTL(x) (((x) >> S_IPTTL) & M_IPTTL) 3208 3209 #define S_SYNCOOKIEPARAMS 26 3210 #define M_SYNCOOKIEPARAMS 0x3f 3211 #define V_SYNCOOKIEPARAMS(x) ((x) << S_SYNCOOKIEPARAMS) 3212 #define G_SYNCOOKIEPARAMS(x) (((x) >> S_SYNCOOKIEPARAMS) & M_SYNCOOKIEPARAMS) 3213 3214 #define A_TP_GLOBAL_RX_CREDIT 0x30c 3215 #define A_TP_CMM_SIZE 0x310 3216 3217 #define S_CMMEMMGRSIZE 0 3218 #define M_CMMEMMGRSIZE 0xfffffff 3219 #define V_CMMEMMGRSIZE(x) ((x) << S_CMMEMMGRSIZE) 3220 #define G_CMMEMMGRSIZE(x) (((x) >> S_CMMEMMGRSIZE) & M_CMMEMMGRSIZE) 3221 3222 #define A_TP_CMM_MM_BASE 0x314 3223 3224 #define S_CMMEMMGRBASE 0 3225 #define M_CMMEMMGRBASE 0xfffffff 3226 #define V_CMMEMMGRBASE(x) ((x) << S_CMMEMMGRBASE) 3227 #define G_CMMEMMGRBASE(x) (((x) >> S_CMMEMMGRBASE) & M_CMMEMMGRBASE) 3228 3229 #define A_TP_CMM_TIMER_BASE 0x318 3230 3231 #define S_CMTIMERBASE 0 3232 #define M_CMTIMERBASE 0xfffffff 3233 #define V_CMTIMERBASE(x) ((x) << S_CMTIMERBASE) 3234 #define G_CMTIMERBASE(x) (((x) >> S_CMTIMERBASE) & M_CMTIMERBASE) 3235 3236 #define S_CMTIMERMAXNUM 28 3237 #define M_CMTIMERMAXNUM 0x3 3238 #define V_CMTIMERMAXNUM(x) ((x) << S_CMTIMERMAXNUM) 3239 #define G_CMTIMERMAXNUM(x) (((x) >> S_CMTIMERMAXNUM) & M_CMTIMERMAXNUM) 3240 3241 #define A_TP_PMM_SIZE 0x31c 3242 3243 #define S_PMSIZE 0 3244 #define M_PMSIZE 0xfffffff 3245 #define V_PMSIZE(x) ((x) << S_PMSIZE) 3246 #define G_PMSIZE(x) (((x) >> S_PMSIZE) & M_PMSIZE) 3247 3248 #define A_TP_PMM_TX_BASE 0x320 3249 #define A_TP_PMM_DEFRAG_BASE 0x324 3250 #define A_TP_PMM_RX_BASE 0x328 3251 #define A_TP_PMM_RX_PAGE_SIZE 0x32c 3252 #define A_TP_PMM_RX_MAX_PAGE 0x330 3253 3254 #define S_PMRXMAXPAGE 0 3255 #define M_PMRXMAXPAGE 0x1fffff 3256 #define V_PMRXMAXPAGE(x) ((x) << S_PMRXMAXPAGE) 3257 #define G_PMRXMAXPAGE(x) (((x) >> S_PMRXMAXPAGE) & M_PMRXMAXPAGE) 3258 3259 #define A_TP_PMM_TX_PAGE_SIZE 0x334 3260 #define A_TP_PMM_TX_MAX_PAGE 0x338 3261 3262 #define S_PMTXMAXPAGE 0 3263 #define M_PMTXMAXPAGE 0x1fffff 3264 #define V_PMTXMAXPAGE(x) ((x) << S_PMTXMAXPAGE) 3265 #define G_PMTXMAXPAGE(x) (((x) >> S_PMTXMAXPAGE) & M_PMTXMAXPAGE) 3266 3267 #define A_TP_TCP_OPTIONS 0x340 3268 3269 #define S_MTUDEFAULT 16 3270 #define M_MTUDEFAULT 0xffff 3271 #define V_MTUDEFAULT(x) ((x) << S_MTUDEFAULT) 3272 #define G_MTUDEFAULT(x) (((x) >> S_MTUDEFAULT) & M_MTUDEFAULT) 3273 3274 #define S_MTUENABLE 10 3275 #define V_MTUENABLE(x) ((x) << S_MTUENABLE) 3276 #define F_MTUENABLE V_MTUENABLE(1U) 3277 3278 #define S_SACKTX 9 3279 #define V_SACKTX(x) ((x) << S_SACKTX) 3280 #define F_SACKTX V_SACKTX(1U) 3281 3282 #define S_SACKRX 8 3283 #define V_SACKRX(x) ((x) << S_SACKRX) 3284 #define F_SACKRX V_SACKRX(1U) 3285 3286 #define S_SACKMODE 4 3287 #define M_SACKMODE 0x3 3288 #define V_SACKMODE(x) ((x) << S_SACKMODE) 3289 #define G_SACKMODE(x) (((x) >> S_SACKMODE) & M_SACKMODE) 3290 3291 #define S_WINDOWSCALEMODE 2 3292 #define M_WINDOWSCALEMODE 0x3 3293 #define V_WINDOWSCALEMODE(x) ((x) << S_WINDOWSCALEMODE) 3294 #define G_WINDOWSCALEMODE(x) (((x) >> S_WINDOWSCALEMODE) & M_WINDOWSCALEMODE) 3295 3296 #define S_TIMESTAMPSMODE 0 3297 #define M_TIMESTAMPSMODE 0x3 3298 #define V_TIMESTAMPSMODE(x) ((x) << S_TIMESTAMPSMODE) 3299 #define G_TIMESTAMPSMODE(x) (((x) >> S_TIMESTAMPSMODE) & M_TIMESTAMPSMODE) 3300 3301 #define A_TP_DACK_CONFIG 0x344 3302 3303 #define S_AUTOSTATE3 30 3304 #define M_AUTOSTATE3 0x3 3305 #define V_AUTOSTATE3(x) ((x) << S_AUTOSTATE3) 3306 #define G_AUTOSTATE3(x) (((x) >> S_AUTOSTATE3) & M_AUTOSTATE3) 3307 3308 #define S_AUTOSTATE2 28 3309 #define M_AUTOSTATE2 0x3 3310 #define V_AUTOSTATE2(x) ((x) << S_AUTOSTATE2) 3311 #define G_AUTOSTATE2(x) (((x) >> S_AUTOSTATE2) & M_AUTOSTATE2) 3312 3313 #define S_AUTOSTATE1 26 3314 #define M_AUTOSTATE1 0x3 3315 #define V_AUTOSTATE1(x) ((x) << S_AUTOSTATE1) 3316 #define G_AUTOSTATE1(x) (((x) >> S_AUTOSTATE1) & M_AUTOSTATE1) 3317 3318 #define S_BYTETHRESHOLD 5 3319 #define M_BYTETHRESHOLD 0xfffff 3320 #define V_BYTETHRESHOLD(x) ((x) << S_BYTETHRESHOLD) 3321 #define G_BYTETHRESHOLD(x) (((x) >> S_BYTETHRESHOLD) & M_BYTETHRESHOLD) 3322 3323 #define S_MSSTHRESHOLD 3 3324 #define M_MSSTHRESHOLD 0x3 3325 #define V_MSSTHRESHOLD(x) ((x) << S_MSSTHRESHOLD) 3326 #define G_MSSTHRESHOLD(x) (((x) >> S_MSSTHRESHOLD) & M_MSSTHRESHOLD) 3327 3328 #define S_AUTOCAREFUL 2 3329 #define V_AUTOCAREFUL(x) ((x) << S_AUTOCAREFUL) 3330 #define F_AUTOCAREFUL V_AUTOCAREFUL(1U) 3331 3332 #define S_AUTOENABLE 1 3333 #define V_AUTOENABLE(x) ((x) << S_AUTOENABLE) 3334 #define F_AUTOENABLE V_AUTOENABLE(1U) 3335 3336 #define S_DACK_MODE 0 3337 #define V_DACK_MODE(x) ((x) << S_DACK_MODE) 3338 #define F_DACK_MODE V_DACK_MODE(1U) 3339 3340 #define A_TP_PC_CONFIG 0x348 3341 3342 #define S_TXTOSQUEUEMAPMODE 26 3343 #define V_TXTOSQUEUEMAPMODE(x) ((x) << S_TXTOSQUEUEMAPMODE) 3344 #define F_TXTOSQUEUEMAPMODE V_TXTOSQUEUEMAPMODE(1U) 3345 3346 #define S_RDDPCONGEN 25 3347 #define V_RDDPCONGEN(x) ((x) << S_RDDPCONGEN) 3348 #define F_RDDPCONGEN V_RDDPCONGEN(1U) 3349 3350 #define S_ENABLEONFLYPDU 24 3351 #define V_ENABLEONFLYPDU(x) ((x) << S_ENABLEONFLYPDU) 3352 #define F_ENABLEONFLYPDU V_ENABLEONFLYPDU(1U) 3353 3354 #define S_ENABLEEPCMDAFULL 23 3355 #define V_ENABLEEPCMDAFULL(x) ((x) << S_ENABLEEPCMDAFULL) 3356 #define F_ENABLEEPCMDAFULL V_ENABLEEPCMDAFULL(1U) 3357 3358 #define S_MODULATEUNIONMODE 22 3359 #define V_MODULATEUNIONMODE(x) ((x) << S_MODULATEUNIONMODE) 3360 #define F_MODULATEUNIONMODE V_MODULATEUNIONMODE(1U) 3361 3362 #define S_TXDATAACKRATEENABLE 21 3363 #define V_TXDATAACKRATEENABLE(x) ((x) << S_TXDATAACKRATEENABLE) 3364 #define F_TXDATAACKRATEENABLE V_TXDATAACKRATEENABLE(1U) 3365 3366 #define S_TXDEFERENABLE 20 3367 #define V_TXDEFERENABLE(x) ((x) << S_TXDEFERENABLE) 3368 #define F_TXDEFERENABLE V_TXDEFERENABLE(1U) 3369 3370 #define S_RXCONGESTIONMODE 19 3371 #define V_RXCONGESTIONMODE(x) ((x) << S_RXCONGESTIONMODE) 3372 #define F_RXCONGESTIONMODE V_RXCONGESTIONMODE(1U) 3373 3374 #define S_HEARBEATONCEDACK 18 3375 #define V_HEARBEATONCEDACK(x) ((x) << S_HEARBEATONCEDACK) 3376 #define F_HEARBEATONCEDACK V_HEARBEATONCEDACK(1U) 3377 3378 #define S_HEARBEATONCEHEAP 17 3379 #define V_HEARBEATONCEHEAP(x) ((x) << S_HEARBEATONCEHEAP) 3380 #define F_HEARBEATONCEHEAP V_HEARBEATONCEHEAP(1U) 3381 3382 #define S_HEARBEATDACK 16 3383 #define V_HEARBEATDACK(x) ((x) << S_HEARBEATDACK) 3384 #define F_HEARBEATDACK V_HEARBEATDACK(1U) 3385 3386 #define S_TXCONGESTIONMODE 15 3387 #define V_TXCONGESTIONMODE(x) ((x) << S_TXCONGESTIONMODE) 3388 #define F_TXCONGESTIONMODE V_TXCONGESTIONMODE(1U) 3389 3390 #define S_ACCEPTLATESTRCVADV 14 3391 #define V_ACCEPTLATESTRCVADV(x) ((x) << S_ACCEPTLATESTRCVADV) 3392 #define F_ACCEPTLATESTRCVADV V_ACCEPTLATESTRCVADV(1U) 3393 3394 #define S_DISABLESYNDATA 13 3395 #define V_DISABLESYNDATA(x) ((x) << S_DISABLESYNDATA) 3396 #define F_DISABLESYNDATA V_DISABLESYNDATA(1U) 3397 3398 #define S_DISABLEWINDOWPSH 12 3399 #define V_DISABLEWINDOWPSH(x) ((x) << S_DISABLEWINDOWPSH) 3400 #define F_DISABLEWINDOWPSH V_DISABLEWINDOWPSH(1U) 3401 3402 #define S_DISABLEFINOLDDATA 11 3403 #define V_DISABLEFINOLDDATA(x) ((x) << S_DISABLEFINOLDDATA) 3404 #define F_DISABLEFINOLDDATA V_DISABLEFINOLDDATA(1U) 3405 3406 #define S_ENABLEFLMERROR 10 3407 #define V_ENABLEFLMERROR(x) ((x) << S_ENABLEFLMERROR) 3408 #define F_ENABLEFLMERROR V_ENABLEFLMERROR(1U) 3409 3410 #define S_DISABLENEXTMTU 9 3411 #define V_DISABLENEXTMTU(x) ((x) << S_DISABLENEXTMTU) 3412 #define F_DISABLENEXTMTU V_DISABLENEXTMTU(1U) 3413 3414 #define S_FILTERPEERFIN 8 3415 #define V_FILTERPEERFIN(x) ((x) << S_FILTERPEERFIN) 3416 #define F_FILTERPEERFIN V_FILTERPEERFIN(1U) 3417 3418 #define S_ENABLEFEEDBACKSEND 7 3419 #define V_ENABLEFEEDBACKSEND(x) ((x) << S_ENABLEFEEDBACKSEND) 3420 #define F_ENABLEFEEDBACKSEND V_ENABLEFEEDBACKSEND(1U) 3421 3422 #define S_ENABLERDMAERROR 6 3423 #define V_ENABLERDMAERROR(x) ((x) << S_ENABLERDMAERROR) 3424 #define F_ENABLERDMAERROR V_ENABLERDMAERROR(1U) 3425 3426 #define S_ENABLEDDPFLOWCONTROL 5 3427 #define V_ENABLEDDPFLOWCONTROL(x) ((x) << S_ENABLEDDPFLOWCONTROL) 3428 #define F_ENABLEDDPFLOWCONTROL V_ENABLEDDPFLOWCONTROL(1U) 3429 3430 #define S_DISABLEHELDFIN 4 3431 #define V_DISABLEHELDFIN(x) ((x) << S_DISABLEHELDFIN) 3432 #define F_DISABLEHELDFIN V_DISABLEHELDFIN(1U) 3433 3434 #define S_TABLELATENCYDELTA 0 3435 #define M_TABLELATENCYDELTA 0xf 3436 #define V_TABLELATENCYDELTA(x) ((x) << S_TABLELATENCYDELTA) 3437 #define G_TABLELATENCYDELTA(x) (((x) >> S_TABLELATENCYDELTA) & M_TABLELATENCYDELTA) 3438 3439 #define S_CMCACHEDISABLE 31 3440 #define V_CMCACHEDISABLE(x) ((x) << S_CMCACHEDISABLE) 3441 #define F_CMCACHEDISABLE V_CMCACHEDISABLE(1U) 3442 3443 #define S_ENABLEOCSPIFULL 30 3444 #define V_ENABLEOCSPIFULL(x) ((x) << S_ENABLEOCSPIFULL) 3445 #define F_ENABLEOCSPIFULL V_ENABLEOCSPIFULL(1U) 3446 3447 #define S_ENABLEFLMERRORDDP 29 3448 #define V_ENABLEFLMERRORDDP(x) ((x) << S_ENABLEFLMERRORDDP) 3449 #define F_ENABLEFLMERRORDDP V_ENABLEFLMERRORDDP(1U) 3450 3451 #define S_LOCKTID 28 3452 #define V_LOCKTID(x) ((x) << S_LOCKTID) 3453 #define F_LOCKTID V_LOCKTID(1U) 3454 3455 #define S_FIXRCVWND 27 3456 #define V_FIXRCVWND(x) ((x) << S_FIXRCVWND) 3457 #define F_FIXRCVWND V_FIXRCVWND(1U) 3458 3459 #define A_TP_PC_CONFIG2 0x34c 3460 3461 #define S_ENABLEDROPRQEMPTYPKT 10 3462 #define V_ENABLEDROPRQEMPTYPKT(x) ((x) << S_ENABLEDROPRQEMPTYPKT) 3463 #define F_ENABLEDROPRQEMPTYPKT V_ENABLEDROPRQEMPTYPKT(1U) 3464 3465 #define S_ENABLETXPORTFROMDA2 9 3466 #define V_ENABLETXPORTFROMDA2(x) ((x) << S_ENABLETXPORTFROMDA2) 3467 #define F_ENABLETXPORTFROMDA2 V_ENABLETXPORTFROMDA2(1U) 3468 3469 #define S_ENABLERXPKTTMSTPRSS 8 3470 #define V_ENABLERXPKTTMSTPRSS(x) ((x) << S_ENABLERXPKTTMSTPRSS) 3471 #define F_ENABLERXPKTTMSTPRSS V_ENABLERXPKTTMSTPRSS(1U) 3472 3473 #define S_ENABLESNDUNAINRXDATA 7 3474 #define V_ENABLESNDUNAINRXDATA(x) ((x) << S_ENABLESNDUNAINRXDATA) 3475 #define F_ENABLESNDUNAINRXDATA V_ENABLESNDUNAINRXDATA(1U) 3476 3477 #define S_ENABLERXPORTFROMADDR 6 3478 #define V_ENABLERXPORTFROMADDR(x) ((x) << S_ENABLERXPORTFROMADDR) 3479 #define F_ENABLERXPORTFROMADDR V_ENABLERXPORTFROMADDR(1U) 3480 3481 #define S_ENABLETXPORTFROMDA 5 3482 #define V_ENABLETXPORTFROMDA(x) ((x) << S_ENABLETXPORTFROMDA) 3483 #define F_ENABLETXPORTFROMDA V_ENABLETXPORTFROMDA(1U) 3484 3485 #define S_CHDRAFULL 4 3486 #define V_CHDRAFULL(x) ((x) << S_CHDRAFULL) 3487 #define F_CHDRAFULL V_CHDRAFULL(1U) 3488 3489 #define S_ENABLENONOFDSCBBIT 3 3490 #define V_ENABLENONOFDSCBBIT(x) ((x) << S_ENABLENONOFDSCBBIT) 3491 #define F_ENABLENONOFDSCBBIT V_ENABLENONOFDSCBBIT(1U) 3492 3493 #define S_ENABLENONOFDTIDRSS 2 3494 #define V_ENABLENONOFDTIDRSS(x) ((x) << S_ENABLENONOFDTIDRSS) 3495 #define F_ENABLENONOFDTIDRSS V_ENABLENONOFDTIDRSS(1U) 3496 3497 #define S_ENABLENONOFDTCBRSS 1 3498 #define V_ENABLENONOFDTCBRSS(x) ((x) << S_ENABLENONOFDTCBRSS) 3499 #define F_ENABLENONOFDTCBRSS V_ENABLENONOFDTCBRSS(1U) 3500 3501 #define S_ENABLEOLDRXFORWARD 0 3502 #define V_ENABLEOLDRXFORWARD(x) ((x) << S_ENABLEOLDRXFORWARD) 3503 #define F_ENABLEOLDRXFORWARD V_ENABLEOLDRXFORWARD(1U) 3504 3505 #define A_TP_TCP_BACKOFF_REG0 0x350 3506 3507 #define S_TIMERBACKOFFINDEX3 24 3508 #define M_TIMERBACKOFFINDEX3 0xff 3509 #define V_TIMERBACKOFFINDEX3(x) ((x) << S_TIMERBACKOFFINDEX3) 3510 #define G_TIMERBACKOFFINDEX3(x) (((x) >> S_TIMERBACKOFFINDEX3) & M_TIMERBACKOFFINDEX3) 3511 3512 #define S_TIMERBACKOFFINDEX2 16 3513 #define M_TIMERBACKOFFINDEX2 0xff 3514 #define V_TIMERBACKOFFINDEX2(x) ((x) << S_TIMERBACKOFFINDEX2) 3515 #define G_TIMERBACKOFFINDEX2(x) (((x) >> S_TIMERBACKOFFINDEX2) & M_TIMERBACKOFFINDEX2) 3516 3517 #define S_TIMERBACKOFFINDEX1 8 3518 #define M_TIMERBACKOFFINDEX1 0xff 3519 #define V_TIMERBACKOFFINDEX1(x) ((x) << S_TIMERBACKOFFINDEX1) 3520 #define G_TIMERBACKOFFINDEX1(x) (((x) >> S_TIMERBACKOFFINDEX1) & M_TIMERBACKOFFINDEX1) 3521 3522 #define S_TIMERBACKOFFINDEX0 0 3523 #define M_TIMERBACKOFFINDEX0 0xff 3524 #define V_TIMERBACKOFFINDEX0(x) ((x) << S_TIMERBACKOFFINDEX0) 3525 #define G_TIMERBACKOFFINDEX0(x) (((x) >> S_TIMERBACKOFFINDEX0) & M_TIMERBACKOFFINDEX0) 3526 3527 #define A_TP_TCP_BACKOFF_REG1 0x354 3528 3529 #define S_TIMERBACKOFFINDEX7 24 3530 #define M_TIMERBACKOFFINDEX7 0xff 3531 #define V_TIMERBACKOFFINDEX7(x) ((x) << S_TIMERBACKOFFINDEX7) 3532 #define G_TIMERBACKOFFINDEX7(x) (((x) >> S_TIMERBACKOFFINDEX7) & M_TIMERBACKOFFINDEX7) 3533 3534 #define S_TIMERBACKOFFINDEX6 16 3535 #define M_TIMERBACKOFFINDEX6 0xff 3536 #define V_TIMERBACKOFFINDEX6(x) ((x) << S_TIMERBACKOFFINDEX6) 3537 #define G_TIMERBACKOFFINDEX6(x) (((x) >> S_TIMERBACKOFFINDEX6) & M_TIMERBACKOFFINDEX6) 3538 3539 #define S_TIMERBACKOFFINDEX5 8 3540 #define M_TIMERBACKOFFINDEX5 0xff 3541 #define V_TIMERBACKOFFINDEX5(x) ((x) << S_TIMERBACKOFFINDEX5) 3542 #define G_TIMERBACKOFFINDEX5(x) (((x) >> S_TIMERBACKOFFINDEX5) & M_TIMERBACKOFFINDEX5) 3543 3544 #define S_TIMERBACKOFFINDEX4 0 3545 #define M_TIMERBACKOFFINDEX4 0xff 3546 #define V_TIMERBACKOFFINDEX4(x) ((x) << S_TIMERBACKOFFINDEX4) 3547 #define G_TIMERBACKOFFINDEX4(x) (((x) >> S_TIMERBACKOFFINDEX4) & M_TIMERBACKOFFINDEX4) 3548 3549 #define A_TP_TCP_BACKOFF_REG2 0x358 3550 3551 #define S_TIMERBACKOFFINDEX11 24 3552 #define M_TIMERBACKOFFINDEX11 0xff 3553 #define V_TIMERBACKOFFINDEX11(x) ((x) << S_TIMERBACKOFFINDEX11) 3554 #define G_TIMERBACKOFFINDEX11(x) (((x) >> S_TIMERBACKOFFINDEX11) & M_TIMERBACKOFFINDEX11) 3555 3556 #define S_TIMERBACKOFFINDEX10 16 3557 #define M_TIMERBACKOFFINDEX10 0xff 3558 #define V_TIMERBACKOFFINDEX10(x) ((x) << S_TIMERBACKOFFINDEX10) 3559 #define G_TIMERBACKOFFINDEX10(x) (((x) >> S_TIMERBACKOFFINDEX10) & M_TIMERBACKOFFINDEX10) 3560 3561 #define S_TIMERBACKOFFINDEX9 8 3562 #define M_TIMERBACKOFFINDEX9 0xff 3563 #define V_TIMERBACKOFFINDEX9(x) ((x) << S_TIMERBACKOFFINDEX9) 3564 #define G_TIMERBACKOFFINDEX9(x) (((x) >> S_TIMERBACKOFFINDEX9) & M_TIMERBACKOFFINDEX9) 3565 3566 #define S_TIMERBACKOFFINDEX8 0 3567 #define M_TIMERBACKOFFINDEX8 0xff 3568 #define V_TIMERBACKOFFINDEX8(x) ((x) << S_TIMERBACKOFFINDEX8) 3569 #define G_TIMERBACKOFFINDEX8(x) (((x) >> S_TIMERBACKOFFINDEX8) & M_TIMERBACKOFFINDEX8) 3570 3571 #define A_TP_TCP_BACKOFF_REG3 0x35c 3572 3573 #define S_TIMERBACKOFFINDEX15 24 3574 #define M_TIMERBACKOFFINDEX15 0xff 3575 #define V_TIMERBACKOFFINDEX15(x) ((x) << S_TIMERBACKOFFINDEX15) 3576 #define G_TIMERBACKOFFINDEX15(x) (((x) >> S_TIMERBACKOFFINDEX15) & M_TIMERBACKOFFINDEX15) 3577 3578 #define S_TIMERBACKOFFINDEX14 16 3579 #define M_TIMERBACKOFFINDEX14 0xff 3580 #define V_TIMERBACKOFFINDEX14(x) ((x) << S_TIMERBACKOFFINDEX14) 3581 #define G_TIMERBACKOFFINDEX14(x) (((x) >> S_TIMERBACKOFFINDEX14) & M_TIMERBACKOFFINDEX14) 3582 3583 #define S_TIMERBACKOFFINDEX13 8 3584 #define M_TIMERBACKOFFINDEX13 0xff 3585 #define V_TIMERBACKOFFINDEX13(x) ((x) << S_TIMERBACKOFFINDEX13) 3586 #define G_TIMERBACKOFFINDEX13(x) (((x) >> S_TIMERBACKOFFINDEX13) & M_TIMERBACKOFFINDEX13) 3587 3588 #define S_TIMERBACKOFFINDEX12 0 3589 #define M_TIMERBACKOFFINDEX12 0xff 3590 #define V_TIMERBACKOFFINDEX12(x) ((x) << S_TIMERBACKOFFINDEX12) 3591 #define G_TIMERBACKOFFINDEX12(x) (((x) >> S_TIMERBACKOFFINDEX12) & M_TIMERBACKOFFINDEX12) 3592 3593 #define A_TP_PARA_REG0 0x360 3594 3595 #define S_INITCWND 24 3596 #define M_INITCWND 0x7 3597 #define V_INITCWND(x) ((x) << S_INITCWND) 3598 #define G_INITCWND(x) (((x) >> S_INITCWND) & M_INITCWND) 3599 3600 #define S_DUPACKTHRESH 20 3601 #define M_DUPACKTHRESH 0xf 3602 #define V_DUPACKTHRESH(x) ((x) << S_DUPACKTHRESH) 3603 #define G_DUPACKTHRESH(x) (((x) >> S_DUPACKTHRESH) & M_DUPACKTHRESH) 3604 3605 #define A_TP_PARA_REG1 0x364 3606 3607 #define S_INITRWND 16 3608 #define M_INITRWND 0xffff 3609 #define V_INITRWND(x) ((x) << S_INITRWND) 3610 #define G_INITRWND(x) (((x) >> S_INITRWND) & M_INITRWND) 3611 3612 #define S_INITIALSSTHRESH 0 3613 #define M_INITIALSSTHRESH 0xffff 3614 #define V_INITIALSSTHRESH(x) ((x) << S_INITIALSSTHRESH) 3615 #define G_INITIALSSTHRESH(x) (((x) >> S_INITIALSSTHRESH) & M_INITIALSSTHRESH) 3616 3617 #define A_TP_PARA_REG2 0x368 3618 3619 #define S_MAXRXDATA 16 3620 #define M_MAXRXDATA 0xffff 3621 #define V_MAXRXDATA(x) ((x) << S_MAXRXDATA) 3622 #define G_MAXRXDATA(x) (((x) >> S_MAXRXDATA) & M_MAXRXDATA) 3623 3624 #define S_RXCOALESCESIZE 0 3625 #define M_RXCOALESCESIZE 0xffff 3626 #define V_RXCOALESCESIZE(x) ((x) << S_RXCOALESCESIZE) 3627 #define G_RXCOALESCESIZE(x) (((x) >> S_RXCOALESCESIZE) & M_RXCOALESCESIZE) 3628 3629 #define A_TP_PARA_REG3 0x36c 3630 3631 #define S_TUNNELCNGDROP1 21 3632 #define V_TUNNELCNGDROP1(x) ((x) << S_TUNNELCNGDROP1) 3633 #define F_TUNNELCNGDROP1 V_TUNNELCNGDROP1(1U) 3634 3635 #define S_TUNNELCNGDROP0 20 3636 #define V_TUNNELCNGDROP0(x) ((x) << S_TUNNELCNGDROP0) 3637 #define F_TUNNELCNGDROP0 V_TUNNELCNGDROP0(1U) 3638 3639 #define S_TXDATAACKIDX 16 3640 #define M_TXDATAACKIDX 0xf 3641 #define V_TXDATAACKIDX(x) ((x) << S_TXDATAACKIDX) 3642 #define G_TXDATAACKIDX(x) (((x) >> S_TXDATAACKIDX) & M_TXDATAACKIDX) 3643 3644 #define S_RXFRAGENABLE 12 3645 #define M_RXFRAGENABLE 0x7 3646 #define V_RXFRAGENABLE(x) ((x) << S_RXFRAGENABLE) 3647 #define G_RXFRAGENABLE(x) (((x) >> S_RXFRAGENABLE) & M_RXFRAGENABLE) 3648 3649 #define S_TXPACEFIXEDSTRICT 11 3650 #define V_TXPACEFIXEDSTRICT(x) ((x) << S_TXPACEFIXEDSTRICT) 3651 #define F_TXPACEFIXEDSTRICT V_TXPACEFIXEDSTRICT(1U) 3652 3653 #define S_TXPACEAUTOSTRICT 10 3654 #define V_TXPACEAUTOSTRICT(x) ((x) << S_TXPACEAUTOSTRICT) 3655 #define F_TXPACEAUTOSTRICT V_TXPACEAUTOSTRICT(1U) 3656 3657 #define S_TXPACEFIXED 9 3658 #define V_TXPACEFIXED(x) ((x) << S_TXPACEFIXED) 3659 #define F_TXPACEFIXED V_TXPACEFIXED(1U) 3660 3661 #define S_TXPACEAUTO 8 3662 #define V_TXPACEAUTO(x) ((x) << S_TXPACEAUTO) 3663 #define F_TXPACEAUTO V_TXPACEAUTO(1U) 3664 3665 #define S_RXURGMODE 5 3666 #define V_RXURGMODE(x) ((x) << S_RXURGMODE) 3667 #define F_RXURGMODE V_RXURGMODE(1U) 3668 3669 #define S_TXURGMODE 4 3670 #define V_TXURGMODE(x) ((x) << S_TXURGMODE) 3671 #define F_TXURGMODE V_TXURGMODE(1U) 3672 3673 #define S_CNGCTRLMODE 2 3674 #define M_CNGCTRLMODE 0x3 3675 #define V_CNGCTRLMODE(x) ((x) << S_CNGCTRLMODE) 3676 #define G_CNGCTRLMODE(x) (((x) >> S_CNGCTRLMODE) & M_CNGCTRLMODE) 3677 3678 #define S_RXCOALESCEENABLE 1 3679 #define V_RXCOALESCEENABLE(x) ((x) << S_RXCOALESCEENABLE) 3680 #define F_RXCOALESCEENABLE V_RXCOALESCEENABLE(1U) 3681 3682 #define S_RXCOALESCEPSHEN 0 3683 #define V_RXCOALESCEPSHEN(x) ((x) << S_RXCOALESCEPSHEN) 3684 #define F_RXCOALESCEPSHEN V_RXCOALESCEPSHEN(1U) 3685 3686 #define S_RXURGTUNNEL 6 3687 #define V_RXURGTUNNEL(x) ((x) << S_RXURGTUNNEL) 3688 #define F_RXURGTUNNEL V_RXURGTUNNEL(1U) 3689 3690 #define A_TP_PARA_REG4 0x370 3691 3692 #define S_HIGHSPEEDCFG 24 3693 #define M_HIGHSPEEDCFG 0xff 3694 #define V_HIGHSPEEDCFG(x) ((x) << S_HIGHSPEEDCFG) 3695 #define G_HIGHSPEEDCFG(x) (((x) >> S_HIGHSPEEDCFG) & M_HIGHSPEEDCFG) 3696 3697 #define S_NEWRENOCFG 16 3698 #define M_NEWRENOCFG 0xff 3699 #define V_NEWRENOCFG(x) ((x) << S_NEWRENOCFG) 3700 #define G_NEWRENOCFG(x) (((x) >> S_NEWRENOCFG) & M_NEWRENOCFG) 3701 3702 #define S_TAHOECFG 8 3703 #define M_TAHOECFG 0xff 3704 #define V_TAHOECFG(x) ((x) << S_TAHOECFG) 3705 #define G_TAHOECFG(x) (((x) >> S_TAHOECFG) & M_TAHOECFG) 3706 3707 #define S_RENOCFG 0 3708 #define M_RENOCFG 0xff 3709 #define V_RENOCFG(x) ((x) << S_RENOCFG) 3710 #define G_RENOCFG(x) (((x) >> S_RENOCFG) & M_RENOCFG) 3711 3712 #define A_TP_PARA_REG5 0x374 3713 3714 #define S_INDICATESIZE 16 3715 #define M_INDICATESIZE 0xffff 3716 #define V_INDICATESIZE(x) ((x) << S_INDICATESIZE) 3717 #define G_INDICATESIZE(x) (((x) >> S_INDICATESIZE) & M_INDICATESIZE) 3718 3719 #define S_SCHDENABLE 8 3720 #define V_SCHDENABLE(x) ((x) << S_SCHDENABLE) 3721 #define F_SCHDENABLE V_SCHDENABLE(1U) 3722 3723 #define S_ONFLYDDPENABLE 2 3724 #define V_ONFLYDDPENABLE(x) ((x) << S_ONFLYDDPENABLE) 3725 #define F_ONFLYDDPENABLE V_ONFLYDDPENABLE(1U) 3726 3727 #define S_DACKTIMERSPIN 1 3728 #define V_DACKTIMERSPIN(x) ((x) << S_DACKTIMERSPIN) 3729 #define F_DACKTIMERSPIN V_DACKTIMERSPIN(1U) 3730 3731 #define S_PUSHTIMERENABLE 0 3732 #define V_PUSHTIMERENABLE(x) ((x) << S_PUSHTIMERENABLE) 3733 #define F_PUSHTIMERENABLE V_PUSHTIMERENABLE(1U) 3734 3735 #define A_TP_PARA_REG6 0x378 3736 3737 #define S_TXPDUSIZEADJ 16 3738 #define M_TXPDUSIZEADJ 0xff 3739 #define V_TXPDUSIZEADJ(x) ((x) << S_TXPDUSIZEADJ) 3740 #define G_TXPDUSIZEADJ(x) (((x) >> S_TXPDUSIZEADJ) & M_TXPDUSIZEADJ) 3741 3742 #define S_ENABLEEPDU 14 3743 #define V_ENABLEEPDU(x) ((x) << S_ENABLEEPDU) 3744 #define F_ENABLEEPDU V_ENABLEEPDU(1U) 3745 3746 #define S_T3A_ENABLEESND 13 3747 #define V_T3A_ENABLEESND(x) ((x) << S_T3A_ENABLEESND) 3748 #define F_T3A_ENABLEESND V_T3A_ENABLEESND(1U) 3749 3750 #define S_T3A_ENABLECSND 12 3751 #define V_T3A_ENABLECSND(x) ((x) << S_T3A_ENABLECSND) 3752 #define F_T3A_ENABLECSND V_T3A_ENABLECSND(1U) 3753 3754 #define S_T3A_ENABLEDEFERACK 9 3755 #define V_T3A_ENABLEDEFERACK(x) ((x) << S_T3A_ENABLEDEFERACK) 3756 #define F_T3A_ENABLEDEFERACK V_T3A_ENABLEDEFERACK(1U) 3757 3758 #define S_ENABLEPDUC 8 3759 #define V_ENABLEPDUC(x) ((x) << S_ENABLEPDUC) 3760 #define F_ENABLEPDUC V_ENABLEPDUC(1U) 3761 3762 #define S_ENABLEPDUI 7 3763 #define V_ENABLEPDUI(x) ((x) << S_ENABLEPDUI) 3764 #define F_ENABLEPDUI V_ENABLEPDUI(1U) 3765 3766 #define S_T3A_ENABLEPDUE 6 3767 #define V_T3A_ENABLEPDUE(x) ((x) << S_T3A_ENABLEPDUE) 3768 #define F_T3A_ENABLEPDUE V_T3A_ENABLEPDUE(1U) 3769 3770 #define S_ENABLEDEFER 5 3771 #define V_ENABLEDEFER(x) ((x) << S_ENABLEDEFER) 3772 #define F_ENABLEDEFER V_ENABLEDEFER(1U) 3773 3774 #define S_ENABLECLEARRXMTOOS 4 3775 #define V_ENABLECLEARRXMTOOS(x) ((x) << S_ENABLECLEARRXMTOOS) 3776 #define F_ENABLECLEARRXMTOOS V_ENABLECLEARRXMTOOS(1U) 3777 3778 #define S_DISABLEPDUCNG 3 3779 #define V_DISABLEPDUCNG(x) ((x) << S_DISABLEPDUCNG) 3780 #define F_DISABLEPDUCNG V_DISABLEPDUCNG(1U) 3781 3782 #define S_DISABLEPDUTIMEOUT 2 3783 #define V_DISABLEPDUTIMEOUT(x) ((x) << S_DISABLEPDUTIMEOUT) 3784 #define F_DISABLEPDUTIMEOUT V_DISABLEPDUTIMEOUT(1U) 3785 3786 #define S_DISABLEPDURXMT 1 3787 #define V_DISABLEPDURXMT(x) ((x) << S_DISABLEPDURXMT) 3788 #define F_DISABLEPDURXMT V_DISABLEPDURXMT(1U) 3789 3790 #define S_DISABLEPDUXMT 0 3791 #define V_DISABLEPDUXMT(x) ((x) << S_DISABLEPDUXMT) 3792 #define F_DISABLEPDUXMT V_DISABLEPDUXMT(1U) 3793 3794 #define S_ENABLEDEFERACK 12 3795 #define V_ENABLEDEFERACK(x) ((x) << S_ENABLEDEFERACK) 3796 #define F_ENABLEDEFERACK V_ENABLEDEFERACK(1U) 3797 3798 #define S_ENABLEESND 11 3799 #define V_ENABLEESND(x) ((x) << S_ENABLEESND) 3800 #define F_ENABLEESND V_ENABLEESND(1U) 3801 3802 #define S_ENABLECSND 10 3803 #define V_ENABLECSND(x) ((x) << S_ENABLECSND) 3804 #define F_ENABLECSND V_ENABLECSND(1U) 3805 3806 #define S_ENABLEPDUE 9 3807 #define V_ENABLEPDUE(x) ((x) << S_ENABLEPDUE) 3808 #define F_ENABLEPDUE V_ENABLEPDUE(1U) 3809 3810 #define S_ENABLEBUFI 7 3811 #define V_ENABLEBUFI(x) ((x) << S_ENABLEBUFI) 3812 #define F_ENABLEBUFI V_ENABLEBUFI(1U) 3813 3814 #define S_ENABLEBUFE 6 3815 #define V_ENABLEBUFE(x) ((x) << S_ENABLEBUFE) 3816 #define F_ENABLEBUFE V_ENABLEBUFE(1U) 3817 3818 #define A_TP_PARA_REG7 0x37c 3819 3820 #define S_PMMAXXFERLEN1 16 3821 #define M_PMMAXXFERLEN1 0xffff 3822 #define V_PMMAXXFERLEN1(x) ((x) << S_PMMAXXFERLEN1) 3823 #define G_PMMAXXFERLEN1(x) (((x) >> S_PMMAXXFERLEN1) & M_PMMAXXFERLEN1) 3824 3825 #define S_PMMAXXFERLEN0 0 3826 #define M_PMMAXXFERLEN0 0xffff 3827 #define V_PMMAXXFERLEN0(x) ((x) << S_PMMAXXFERLEN0) 3828 #define G_PMMAXXFERLEN0(x) (((x) >> S_PMMAXXFERLEN0) & M_PMMAXXFERLEN0) 3829 3830 #define A_TP_TIMER_RESOLUTION 0x390 3831 3832 #define S_TIMERRESOLUTION 16 3833 #define M_TIMERRESOLUTION 0xff 3834 #define V_TIMERRESOLUTION(x) ((x) << S_TIMERRESOLUTION) 3835 #define G_TIMERRESOLUTION(x) (((x) >> S_TIMERRESOLUTION) & M_TIMERRESOLUTION) 3836 3837 #define S_TIMESTAMPRESOLUTION 8 3838 #define M_TIMESTAMPRESOLUTION 0xff 3839 #define V_TIMESTAMPRESOLUTION(x) ((x) << S_TIMESTAMPRESOLUTION) 3840 #define G_TIMESTAMPRESOLUTION(x) (((x) >> S_TIMESTAMPRESOLUTION) & M_TIMESTAMPRESOLUTION) 3841 3842 #define S_DELAYEDACKRESOLUTION 0 3843 #define M_DELAYEDACKRESOLUTION 0xff 3844 #define V_DELAYEDACKRESOLUTION(x) ((x) << S_DELAYEDACKRESOLUTION) 3845 #define G_DELAYEDACKRESOLUTION(x) (((x) >> S_DELAYEDACKRESOLUTION) & M_DELAYEDACKRESOLUTION) 3846 3847 #define A_TP_MSL 0x394 3848 3849 #define S_MSL 0 3850 #define M_MSL 0x3fffffff 3851 #define V_MSL(x) ((x) << S_MSL) 3852 #define G_MSL(x) (((x) >> S_MSL) & M_MSL) 3853 3854 #define A_TP_RXT_MIN 0x398 3855 3856 #define S_RXTMIN 0 3857 #define M_RXTMIN 0x3fffffff 3858 #define V_RXTMIN(x) ((x) << S_RXTMIN) 3859 #define G_RXTMIN(x) (((x) >> S_RXTMIN) & M_RXTMIN) 3860 3861 #define A_TP_RXT_MAX 0x39c 3862 3863 #define S_RXTMAX 0 3864 #define M_RXTMAX 0x3fffffff 3865 #define V_RXTMAX(x) ((x) << S_RXTMAX) 3866 #define G_RXTMAX(x) (((x) >> S_RXTMAX) & M_RXTMAX) 3867 3868 #define A_TP_PERS_MIN 0x3a0 3869 3870 #define S_PERSMIN 0 3871 #define M_PERSMIN 0x3fffffff 3872 #define V_PERSMIN(x) ((x) << S_PERSMIN) 3873 #define G_PERSMIN(x) (((x) >> S_PERSMIN) & M_PERSMIN) 3874 3875 #define A_TP_PERS_MAX 0x3a4 3876 3877 #define S_PERSMAX 0 3878 #define M_PERSMAX 0x3fffffff 3879 #define V_PERSMAX(x) ((x) << S_PERSMAX) 3880 #define G_PERSMAX(x) (((x) >> S_PERSMAX) & M_PERSMAX) 3881 3882 #define A_TP_KEEP_IDLE 0x3a8 3883 3884 #define S_KEEPALIVEIDLE 0 3885 #define M_KEEPALIVEIDLE 0x3fffffff 3886 #define V_KEEPALIVEIDLE(x) ((x) << S_KEEPALIVEIDLE) 3887 #define G_KEEPALIVEIDLE(x) (((x) >> S_KEEPALIVEIDLE) & M_KEEPALIVEIDLE) 3888 3889 #define A_TP_KEEP_INTVL 0x3ac 3890 3891 #define S_KEEPALIVEINTVL 0 3892 #define M_KEEPALIVEINTVL 0x3fffffff 3893 #define V_KEEPALIVEINTVL(x) ((x) << S_KEEPALIVEINTVL) 3894 #define G_KEEPALIVEINTVL(x) (((x) >> S_KEEPALIVEINTVL) & M_KEEPALIVEINTVL) 3895 3896 #define A_TP_INIT_SRTT 0x3b0 3897 3898 #define S_INITSRTT 0 3899 #define M_INITSRTT 0xffff 3900 #define V_INITSRTT(x) ((x) << S_INITSRTT) 3901 #define G_INITSRTT(x) (((x) >> S_INITSRTT) & M_INITSRTT) 3902 3903 #define A_TP_DACK_TIMER 0x3b4 3904 3905 #define S_DACKTIME 0 3906 #define M_DACKTIME 0xfff 3907 #define V_DACKTIME(x) ((x) << S_DACKTIME) 3908 #define G_DACKTIME(x) (((x) >> S_DACKTIME) & M_DACKTIME) 3909 3910 #define A_TP_FINWAIT2_TIMER 0x3b8 3911 3912 #define S_FINWAIT2TIME 0 3913 #define M_FINWAIT2TIME 0x3fffffff 3914 #define V_FINWAIT2TIME(x) ((x) << S_FINWAIT2TIME) 3915 #define G_FINWAIT2TIME(x) (((x) >> S_FINWAIT2TIME) & M_FINWAIT2TIME) 3916 3917 #define A_TP_FAST_FINWAIT2_TIMER 0x3bc 3918 3919 #define S_FASTFINWAIT2TIME 0 3920 #define M_FASTFINWAIT2TIME 0x3fffffff 3921 #define V_FASTFINWAIT2TIME(x) ((x) << S_FASTFINWAIT2TIME) 3922 #define G_FASTFINWAIT2TIME(x) (((x) >> S_FASTFINWAIT2TIME) & M_FASTFINWAIT2TIME) 3923 3924 #define A_TP_SHIFT_CNT 0x3c0 3925 3926 #define S_SYNSHIFTMAX 24 3927 #define M_SYNSHIFTMAX 0xff 3928 #define V_SYNSHIFTMAX(x) ((x) << S_SYNSHIFTMAX) 3929 #define G_SYNSHIFTMAX(x) (((x) >> S_SYNSHIFTMAX) & M_SYNSHIFTMAX) 3930 3931 #define S_RXTSHIFTMAXR1 20 3932 #define M_RXTSHIFTMAXR1 0xf 3933 #define V_RXTSHIFTMAXR1(x) ((x) << S_RXTSHIFTMAXR1) 3934 #define G_RXTSHIFTMAXR1(x) (((x) >> S_RXTSHIFTMAXR1) & M_RXTSHIFTMAXR1) 3935 3936 #define S_RXTSHIFTMAXR2 16 3937 #define M_RXTSHIFTMAXR2 0xf 3938 #define V_RXTSHIFTMAXR2(x) ((x) << S_RXTSHIFTMAXR2) 3939 #define G_RXTSHIFTMAXR2(x) (((x) >> S_RXTSHIFTMAXR2) & M_RXTSHIFTMAXR2) 3940 3941 #define S_PERSHIFTBACKOFFMAX 12 3942 #define M_PERSHIFTBACKOFFMAX 0xf 3943 #define V_PERSHIFTBACKOFFMAX(x) ((x) << S_PERSHIFTBACKOFFMAX) 3944 #define G_PERSHIFTBACKOFFMAX(x) (((x) >> S_PERSHIFTBACKOFFMAX) & M_PERSHIFTBACKOFFMAX) 3945 3946 #define S_PERSHIFTMAX 8 3947 #define M_PERSHIFTMAX 0xf 3948 #define V_PERSHIFTMAX(x) ((x) << S_PERSHIFTMAX) 3949 #define G_PERSHIFTMAX(x) (((x) >> S_PERSHIFTMAX) & M_PERSHIFTMAX) 3950 3951 #define S_KEEPALIVEMAX 0 3952 #define M_KEEPALIVEMAX 0xff 3953 #define V_KEEPALIVEMAX(x) ((x) << S_KEEPALIVEMAX) 3954 #define G_KEEPALIVEMAX(x) (((x) >> S_KEEPALIVEMAX) & M_KEEPALIVEMAX) 3955 3956 #define A_TP_TIME_HI 0x3c8 3957 #define A_TP_TIME_LO 0x3cc 3958 #define A_TP_MTU_PORT_TABLE 0x3d0 3959 3960 #define S_PORT1MTUVALUE 16 3961 #define M_PORT1MTUVALUE 0xffff 3962 #define V_PORT1MTUVALUE(x) ((x) << S_PORT1MTUVALUE) 3963 #define G_PORT1MTUVALUE(x) (((x) >> S_PORT1MTUVALUE) & M_PORT1MTUVALUE) 3964 3965 #define S_PORT0MTUVALUE 0 3966 #define M_PORT0MTUVALUE 0xffff 3967 #define V_PORT0MTUVALUE(x) ((x) << S_PORT0MTUVALUE) 3968 #define G_PORT0MTUVALUE(x) (((x) >> S_PORT0MTUVALUE) & M_PORT0MTUVALUE) 3969 3970 #define A_TP_ULP_TABLE 0x3d4 3971 3972 #define S_ULPTYPE7FIELD 28 3973 #define M_ULPTYPE7FIELD 0xf 3974 #define V_ULPTYPE7FIELD(x) ((x) << S_ULPTYPE7FIELD) 3975 #define G_ULPTYPE7FIELD(x) (((x) >> S_ULPTYPE7FIELD) & M_ULPTYPE7FIELD) 3976 3977 #define S_ULPTYPE6FIELD 24 3978 #define M_ULPTYPE6FIELD 0xf 3979 #define V_ULPTYPE6FIELD(x) ((x) << S_ULPTYPE6FIELD) 3980 #define G_ULPTYPE6FIELD(x) (((x) >> S_ULPTYPE6FIELD) & M_ULPTYPE6FIELD) 3981 3982 #define S_ULPTYPE5FIELD 20 3983 #define M_ULPTYPE5FIELD 0xf 3984 #define V_ULPTYPE5FIELD(x) ((x) << S_ULPTYPE5FIELD) 3985 #define G_ULPTYPE5FIELD(x) (((x) >> S_ULPTYPE5FIELD) & M_ULPTYPE5FIELD) 3986 3987 #define S_ULPTYPE4FIELD 16 3988 #define M_ULPTYPE4FIELD 0xf 3989 #define V_ULPTYPE4FIELD(x) ((x) << S_ULPTYPE4FIELD) 3990 #define G_ULPTYPE4FIELD(x) (((x) >> S_ULPTYPE4FIELD) & M_ULPTYPE4FIELD) 3991 3992 #define S_ULPTYPE3FIELD 12 3993 #define M_ULPTYPE3FIELD 0xf 3994 #define V_ULPTYPE3FIELD(x) ((x) << S_ULPTYPE3FIELD) 3995 #define G_ULPTYPE3FIELD(x) (((x) >> S_ULPTYPE3FIELD) & M_ULPTYPE3FIELD) 3996 3997 #define S_ULPTYPE2FIELD 8 3998 #define M_ULPTYPE2FIELD 0xf 3999 #define V_ULPTYPE2FIELD(x) ((x) << S_ULPTYPE2FIELD) 4000 #define G_ULPTYPE2FIELD(x) (((x) >> S_ULPTYPE2FIELD) & M_ULPTYPE2FIELD) 4001 4002 #define S_ULPTYPE1FIELD 4 4003 #define M_ULPTYPE1FIELD 0xf 4004 #define V_ULPTYPE1FIELD(x) ((x) << S_ULPTYPE1FIELD) 4005 #define G_ULPTYPE1FIELD(x) (((x) >> S_ULPTYPE1FIELD) & M_ULPTYPE1FIELD) 4006 4007 #define S_ULPTYPE0FIELD 0 4008 #define M_ULPTYPE0FIELD 0xf 4009 #define V_ULPTYPE0FIELD(x) ((x) << S_ULPTYPE0FIELD) 4010 #define G_ULPTYPE0FIELD(x) (((x) >> S_ULPTYPE0FIELD) & M_ULPTYPE0FIELD) 4011 4012 #define A_TP_PACE_TABLE 0x3d8 4013 #define A_TP_CCTRL_TABLE 0x3dc 4014 #define A_TP_TOS_TABLE 0x3e0 4015 #define A_TP_MTU_TABLE 0x3e4 4016 #define A_TP_RSS_MAP_TABLE 0x3e8 4017 #define A_TP_RSS_LKP_TABLE 0x3ec 4018 #define A_TP_RSS_CONFIG 0x3f0 4019 4020 #define S_TNL4TUPEN 29 4021 #define V_TNL4TUPEN(x) ((x) << S_TNL4TUPEN) 4022 #define F_TNL4TUPEN V_TNL4TUPEN(1U) 4023 4024 #define S_TNL2TUPEN 28 4025 #define V_TNL2TUPEN(x) ((x) << S_TNL2TUPEN) 4026 #define F_TNL2TUPEN V_TNL2TUPEN(1U) 4027 4028 #define S_TNLPRTEN 26 4029 #define V_TNLPRTEN(x) ((x) << S_TNLPRTEN) 4030 #define F_TNLPRTEN V_TNLPRTEN(1U) 4031 4032 #define S_TNLMAPEN 25 4033 #define V_TNLMAPEN(x) ((x) << S_TNLMAPEN) 4034 #define F_TNLMAPEN V_TNLMAPEN(1U) 4035 4036 #define S_TNLLKPEN 24 4037 #define V_TNLLKPEN(x) ((x) << S_TNLLKPEN) 4038 #define F_TNLLKPEN V_TNLLKPEN(1U) 4039 4040 #define S_OFD4TUPEN 21 4041 #define V_OFD4TUPEN(x) ((x) << S_OFD4TUPEN) 4042 #define F_OFD4TUPEN V_OFD4TUPEN(1U) 4043 4044 #define S_OFD2TUPEN 20 4045 #define V_OFD2TUPEN(x) ((x) << S_OFD2TUPEN) 4046 #define F_OFD2TUPEN V_OFD2TUPEN(1U) 4047 4048 #define S_OFDMAPEN 17 4049 #define V_OFDMAPEN(x) ((x) << S_OFDMAPEN) 4050 #define F_OFDMAPEN V_OFDMAPEN(1U) 4051 4052 #define S_OFDLKPEN 16 4053 #define V_OFDLKPEN(x) ((x) << S_OFDLKPEN) 4054 #define F_OFDLKPEN V_OFDLKPEN(1U) 4055 4056 #define S_SYN4TUPEN 13 4057 #define V_SYN4TUPEN(x) ((x) << S_SYN4TUPEN) 4058 #define F_SYN4TUPEN V_SYN4TUPEN(1U) 4059 4060 #define S_SYN2TUPEN 12 4061 #define V_SYN2TUPEN(x) ((x) << S_SYN2TUPEN) 4062 #define F_SYN2TUPEN V_SYN2TUPEN(1U) 4063 4064 #define S_SYNMAPEN 9 4065 #define V_SYNMAPEN(x) ((x) << S_SYNMAPEN) 4066 #define F_SYNMAPEN V_SYNMAPEN(1U) 4067 4068 #define S_SYNLKPEN 8 4069 #define V_SYNLKPEN(x) ((x) << S_SYNLKPEN) 4070 #define F_SYNLKPEN V_SYNLKPEN(1U) 4071 4072 #define S_RRCPLMAPEN 7 4073 #define V_RRCPLMAPEN(x) ((x) << S_RRCPLMAPEN) 4074 #define F_RRCPLMAPEN V_RRCPLMAPEN(1U) 4075 4076 #define S_RRCPLCPUSIZE 4 4077 #define M_RRCPLCPUSIZE 0x7 4078 #define V_RRCPLCPUSIZE(x) ((x) << S_RRCPLCPUSIZE) 4079 #define G_RRCPLCPUSIZE(x) (((x) >> S_RRCPLCPUSIZE) & M_RRCPLCPUSIZE) 4080 4081 #define S_RQFEEDBACKENABLE 3 4082 #define V_RQFEEDBACKENABLE(x) ((x) << S_RQFEEDBACKENABLE) 4083 #define F_RQFEEDBACKENABLE V_RQFEEDBACKENABLE(1U) 4084 4085 #define S_HASHTOEPLITZ 2 4086 #define V_HASHTOEPLITZ(x) ((x) << S_HASHTOEPLITZ) 4087 #define F_HASHTOEPLITZ V_HASHTOEPLITZ(1U) 4088 4089 #define S_HASHSAVE 1 4090 #define V_HASHSAVE(x) ((x) << S_HASHSAVE) 4091 #define F_HASHSAVE V_HASHSAVE(1U) 4092 4093 #define S_DISABLE 0 4094 #define V_DISABLE(x) ((x) << S_DISABLE) 4095 #define F_DISABLE V_DISABLE(1U) 4096 4097 #define A_TP_RSS_CONFIG_TNL 0x3f4 4098 4099 #define S_MASKSIZE 28 4100 #define M_MASKSIZE 0x7 4101 #define V_MASKSIZE(x) ((x) << S_MASKSIZE) 4102 #define G_MASKSIZE(x) (((x) >> S_MASKSIZE) & M_MASKSIZE) 4103 4104 #define S_DEFAULTCPUBASE 22 4105 #define M_DEFAULTCPUBASE 0x3f 4106 #define V_DEFAULTCPUBASE(x) ((x) << S_DEFAULTCPUBASE) 4107 #define G_DEFAULTCPUBASE(x) (((x) >> S_DEFAULTCPUBASE) & M_DEFAULTCPUBASE) 4108 4109 #define S_DEFAULTCPU 16 4110 #define M_DEFAULTCPU 0x3f 4111 #define V_DEFAULTCPU(x) ((x) << S_DEFAULTCPU) 4112 #define G_DEFAULTCPU(x) (((x) >> S_DEFAULTCPU) & M_DEFAULTCPU) 4113 4114 #define S_DEFAULTQUEUE 0 4115 #define M_DEFAULTQUEUE 0xffff 4116 #define V_DEFAULTQUEUE(x) ((x) << S_DEFAULTQUEUE) 4117 #define G_DEFAULTQUEUE(x) (((x) >> S_DEFAULTQUEUE) & M_DEFAULTQUEUE) 4118 4119 #define A_TP_RSS_CONFIG_OFD 0x3f8 4120 #define A_TP_RSS_CONFIG_SYN 0x3fc 4121 #define A_TP_RSS_SECRET_KEY0 0x400 4122 #define A_TP_RSS_SECRET_KEY1 0x404 4123 #define A_TP_RSS_SECRET_KEY2 0x408 4124 #define A_TP_RSS_SECRET_KEY3 0x40c 4125 #define A_TP_TM_PIO_ADDR 0x418 4126 #define A_TP_TM_PIO_DATA 0x41c 4127 #define A_TP_TX_MOD_QUE_TABLE 0x420 4128 #define A_TP_TX_RESOURCE_LIMIT 0x424 4129 4130 #define S_TX_RESOURCE_LIMIT_CH1_PC 24 4131 #define M_TX_RESOURCE_LIMIT_CH1_PC 0xff 4132 #define V_TX_RESOURCE_LIMIT_CH1_PC(x) ((x) << S_TX_RESOURCE_LIMIT_CH1_PC) 4133 #define G_TX_RESOURCE_LIMIT_CH1_PC(x) (((x) >> S_TX_RESOURCE_LIMIT_CH1_PC) & M_TX_RESOURCE_LIMIT_CH1_PC) 4134 4135 #define S_TX_RESOURCE_LIMIT_CH1_NON_PC 16 4136 #define M_TX_RESOURCE_LIMIT_CH1_NON_PC 0xff 4137 #define V_TX_RESOURCE_LIMIT_CH1_NON_PC(x) ((x) << S_TX_RESOURCE_LIMIT_CH1_NON_PC) 4138 #define G_TX_RESOURCE_LIMIT_CH1_NON_PC(x) (((x) >> S_TX_RESOURCE_LIMIT_CH1_NON_PC) & M_TX_RESOURCE_LIMIT_CH1_NON_PC) 4139 4140 #define S_TX_RESOURCE_LIMIT_CH0_PC 8 4141 #define M_TX_RESOURCE_LIMIT_CH0_PC 0xff 4142 #define V_TX_RESOURCE_LIMIT_CH0_PC(x) ((x) << S_TX_RESOURCE_LIMIT_CH0_PC) 4143 #define G_TX_RESOURCE_LIMIT_CH0_PC(x) (((x) >> S_TX_RESOURCE_LIMIT_CH0_PC) & M_TX_RESOURCE_LIMIT_CH0_PC) 4144 4145 #define S_TX_RESOURCE_LIMIT_CH0_NON_PC 0 4146 #define M_TX_RESOURCE_LIMIT_CH0_NON_PC 0xff 4147 #define V_TX_RESOURCE_LIMIT_CH0_NON_PC(x) ((x) << S_TX_RESOURCE_LIMIT_CH0_NON_PC) 4148 #define G_TX_RESOURCE_LIMIT_CH0_NON_PC(x) (((x) >> S_TX_RESOURCE_LIMIT_CH0_NON_PC) & M_TX_RESOURCE_LIMIT_CH0_NON_PC) 4149 4150 #define A_TP_TX_MOD_QUEUE_REQ_MAP 0x428 4151 4152 #define S_RX_MOD_WEIGHT 24 4153 #define M_RX_MOD_WEIGHT 0xff 4154 #define V_RX_MOD_WEIGHT(x) ((x) << S_RX_MOD_WEIGHT) 4155 #define G_RX_MOD_WEIGHT(x) (((x) >> S_RX_MOD_WEIGHT) & M_RX_MOD_WEIGHT) 4156 4157 #define S_TX_MOD_WEIGHT 16 4158 #define M_TX_MOD_WEIGHT 0xff 4159 #define V_TX_MOD_WEIGHT(x) ((x) << S_TX_MOD_WEIGHT) 4160 #define G_TX_MOD_WEIGHT(x) (((x) >> S_TX_MOD_WEIGHT) & M_TX_MOD_WEIGHT) 4161 4162 #define S_TX_MOD_TIMER_MODE 8 4163 #define M_TX_MOD_TIMER_MODE 0xff 4164 #define V_TX_MOD_TIMER_MODE(x) ((x) << S_TX_MOD_TIMER_MODE) 4165 #define G_TX_MOD_TIMER_MODE(x) (((x) >> S_TX_MOD_TIMER_MODE) & M_TX_MOD_TIMER_MODE) 4166 4167 #define S_TX_MOD_QUEUE_REQ_MAP 0 4168 #define M_TX_MOD_QUEUE_REQ_MAP 0xff 4169 #define V_TX_MOD_QUEUE_REQ_MAP(x) ((x) << S_TX_MOD_QUEUE_REQ_MAP) 4170 #define G_TX_MOD_QUEUE_REQ_MAP(x) (((x) >> S_TX_MOD_QUEUE_REQ_MAP) & M_TX_MOD_QUEUE_REQ_MAP) 4171 4172 #define A_TP_TX_MOD_QUEUE_WEIGHT1 0x42c 4173 4174 #define S_TP_TX_MODQ_WGHT7 24 4175 #define M_TP_TX_MODQ_WGHT7 0xff 4176 #define V_TP_TX_MODQ_WGHT7(x) ((x) << S_TP_TX_MODQ_WGHT7) 4177 #define G_TP_TX_MODQ_WGHT7(x) (((x) >> S_TP_TX_MODQ_WGHT7) & M_TP_TX_MODQ_WGHT7) 4178 4179 #define S_TP_TX_MODQ_WGHT6 16 4180 #define M_TP_TX_MODQ_WGHT6 0xff 4181 #define V_TP_TX_MODQ_WGHT6(x) ((x) << S_TP_TX_MODQ_WGHT6) 4182 #define G_TP_TX_MODQ_WGHT6(x) (((x) >> S_TP_TX_MODQ_WGHT6) & M_TP_TX_MODQ_WGHT6) 4183 4184 #define S_TP_TX_MODQ_WGHT5 8 4185 #define M_TP_TX_MODQ_WGHT5 0xff 4186 #define V_TP_TX_MODQ_WGHT5(x) ((x) << S_TP_TX_MODQ_WGHT5) 4187 #define G_TP_TX_MODQ_WGHT5(x) (((x) >> S_TP_TX_MODQ_WGHT5) & M_TP_TX_MODQ_WGHT5) 4188 4189 #define S_TP_TX_MODQ_WGHT4 0 4190 #define M_TP_TX_MODQ_WGHT4 0xff 4191 #define V_TP_TX_MODQ_WGHT4(x) ((x) << S_TP_TX_MODQ_WGHT4) 4192 #define G_TP_TX_MODQ_WGHT4(x) (((x) >> S_TP_TX_MODQ_WGHT4) & M_TP_TX_MODQ_WGHT4) 4193 4194 #define A_TP_TX_MOD_QUEUE_WEIGHT0 0x430 4195 4196 #define S_TP_TX_MODQ_WGHT3 24 4197 #define M_TP_TX_MODQ_WGHT3 0xff 4198 #define V_TP_TX_MODQ_WGHT3(x) ((x) << S_TP_TX_MODQ_WGHT3) 4199 #define G_TP_TX_MODQ_WGHT3(x) (((x) >> S_TP_TX_MODQ_WGHT3) & M_TP_TX_MODQ_WGHT3) 4200 4201 #define S_TP_TX_MODQ_WGHT2 16 4202 #define M_TP_TX_MODQ_WGHT2 0xff 4203 #define V_TP_TX_MODQ_WGHT2(x) ((x) << S_TP_TX_MODQ_WGHT2) 4204 #define G_TP_TX_MODQ_WGHT2(x) (((x) >> S_TP_TX_MODQ_WGHT2) & M_TP_TX_MODQ_WGHT2) 4205 4206 #define S_TP_TX_MODQ_WGHT1 8 4207 #define M_TP_TX_MODQ_WGHT1 0xff 4208 #define V_TP_TX_MODQ_WGHT1(x) ((x) << S_TP_TX_MODQ_WGHT1) 4209 #define G_TP_TX_MODQ_WGHT1(x) (((x) >> S_TP_TX_MODQ_WGHT1) & M_TP_TX_MODQ_WGHT1) 4210 4211 #define S_TP_TX_MODQ_WGHT0 0 4212 #define M_TP_TX_MODQ_WGHT0 0xff 4213 #define V_TP_TX_MODQ_WGHT0(x) ((x) << S_TP_TX_MODQ_WGHT0) 4214 #define G_TP_TX_MODQ_WGHT0(x) (((x) >> S_TP_TX_MODQ_WGHT0) & M_TP_TX_MODQ_WGHT0) 4215 4216 #define A_TP_MOD_CHANNEL_WEIGHT 0x434 4217 4218 #define S_RX_MOD_CHANNEL_WEIGHT1 24 4219 #define M_RX_MOD_CHANNEL_WEIGHT1 0xff 4220 #define V_RX_MOD_CHANNEL_WEIGHT1(x) ((x) << S_RX_MOD_CHANNEL_WEIGHT1) 4221 #define G_RX_MOD_CHANNEL_WEIGHT1(x) (((x) >> S_RX_MOD_CHANNEL_WEIGHT1) & M_RX_MOD_CHANNEL_WEIGHT1) 4222 4223 #define S_RX_MOD_CHANNEL_WEIGHT0 16 4224 #define M_RX_MOD_CHANNEL_WEIGHT0 0xff 4225 #define V_RX_MOD_CHANNEL_WEIGHT0(x) ((x) << S_RX_MOD_CHANNEL_WEIGHT0) 4226 #define G_RX_MOD_CHANNEL_WEIGHT0(x) (((x) >> S_RX_MOD_CHANNEL_WEIGHT0) & M_RX_MOD_CHANNEL_WEIGHT0) 4227 4228 #define S_TX_MOD_CHANNEL_WEIGHT1 8 4229 #define M_TX_MOD_CHANNEL_WEIGHT1 0xff 4230 #define V_TX_MOD_CHANNEL_WEIGHT1(x) ((x) << S_TX_MOD_CHANNEL_WEIGHT1) 4231 #define G_TX_MOD_CHANNEL_WEIGHT1(x) (((x) >> S_TX_MOD_CHANNEL_WEIGHT1) & M_TX_MOD_CHANNEL_WEIGHT1) 4232 4233 #define S_TX_MOD_CHANNEL_WEIGHT0 0 4234 #define M_TX_MOD_CHANNEL_WEIGHT0 0xff 4235 #define V_TX_MOD_CHANNEL_WEIGHT0(x) ((x) << S_TX_MOD_CHANNEL_WEIGHT0) 4236 #define G_TX_MOD_CHANNEL_WEIGHT0(x) (((x) >> S_TX_MOD_CHANNEL_WEIGHT0) & M_TX_MOD_CHANNEL_WEIGHT0) 4237 4238 #define A_TP_MOD_RATE_LIMIT 0x438 4239 4240 #define S_RX_MOD_RATE_LIMIT_INC 24 4241 #define M_RX_MOD_RATE_LIMIT_INC 0xff 4242 #define V_RX_MOD_RATE_LIMIT_INC(x) ((x) << S_RX_MOD_RATE_LIMIT_INC) 4243 #define G_RX_MOD_RATE_LIMIT_INC(x) (((x) >> S_RX_MOD_RATE_LIMIT_INC) & M_RX_MOD_RATE_LIMIT_INC) 4244 4245 #define S_RX_MOD_RATE_LIMIT_TICK 16 4246 #define M_RX_MOD_RATE_LIMIT_TICK 0xff 4247 #define V_RX_MOD_RATE_LIMIT_TICK(x) ((x) << S_RX_MOD_RATE_LIMIT_TICK) 4248 #define G_RX_MOD_RATE_LIMIT_TICK(x) (((x) >> S_RX_MOD_RATE_LIMIT_TICK) & M_RX_MOD_RATE_LIMIT_TICK) 4249 4250 #define S_TX_MOD_RATE_LIMIT_INC 8 4251 #define M_TX_MOD_RATE_LIMIT_INC 0xff 4252 #define V_TX_MOD_RATE_LIMIT_INC(x) ((x) << S_TX_MOD_RATE_LIMIT_INC) 4253 #define G_TX_MOD_RATE_LIMIT_INC(x) (((x) >> S_TX_MOD_RATE_LIMIT_INC) & M_TX_MOD_RATE_LIMIT_INC) 4254 4255 #define S_TX_MOD_RATE_LIMIT_TICK 0 4256 #define M_TX_MOD_RATE_LIMIT_TICK 0xff 4257 #define V_TX_MOD_RATE_LIMIT_TICK(x) ((x) << S_TX_MOD_RATE_LIMIT_TICK) 4258 #define G_TX_MOD_RATE_LIMIT_TICK(x) (((x) >> S_TX_MOD_RATE_LIMIT_TICK) & M_TX_MOD_RATE_LIMIT_TICK) 4259 4260 #define A_TP_PIO_ADDR 0x440 4261 #define A_TP_PIO_DATA 0x444 4262 #define A_TP_RESET 0x44c 4263 4264 #define S_FLSTINITENABLE 1 4265 #define V_FLSTINITENABLE(x) ((x) << S_FLSTINITENABLE) 4266 #define F_FLSTINITENABLE V_FLSTINITENABLE(1U) 4267 4268 #define S_TPRESET 0 4269 #define V_TPRESET(x) ((x) << S_TPRESET) 4270 #define F_TPRESET V_TPRESET(1U) 4271 4272 #define A_TP_MIB_INDEX 0x450 4273 #define A_TP_MIB_RDATA 0x454 4274 #define A_TP_SYNC_TIME_HI 0x458 4275 #define A_TP_SYNC_TIME_LO 0x45c 4276 #define A_TP_CMM_MM_RX_FLST_BASE 0x460 4277 4278 #define S_CMRXFLSTBASE 0 4279 #define M_CMRXFLSTBASE 0xfffffff 4280 #define V_CMRXFLSTBASE(x) ((x) << S_CMRXFLSTBASE) 4281 #define G_CMRXFLSTBASE(x) (((x) >> S_CMRXFLSTBASE) & M_CMRXFLSTBASE) 4282 4283 #define A_TP_CMM_MM_TX_FLST_BASE 0x464 4284 4285 #define S_CMTXFLSTBASE 0 4286 #define M_CMTXFLSTBASE 0xfffffff 4287 #define V_CMTXFLSTBASE(x) ((x) << S_CMTXFLSTBASE) 4288 #define G_CMTXFLSTBASE(x) (((x) >> S_CMTXFLSTBASE) & M_CMTXFLSTBASE) 4289 4290 #define A_TP_CMM_MM_PS_FLST_BASE 0x468 4291 4292 #define S_CMPSFLSTBASE 0 4293 #define M_CMPSFLSTBASE 0xfffffff 4294 #define V_CMPSFLSTBASE(x) ((x) << S_CMPSFLSTBASE) 4295 #define G_CMPSFLSTBASE(x) (((x) >> S_CMPSFLSTBASE) & M_CMPSFLSTBASE) 4296 4297 #define A_TP_CMM_MM_MAX_PSTRUCT 0x46c 4298 4299 #define S_CMMAXPSTRUCT 0 4300 #define M_CMMAXPSTRUCT 0x1fffff 4301 #define V_CMMAXPSTRUCT(x) ((x) << S_CMMAXPSTRUCT) 4302 #define G_CMMAXPSTRUCT(x) (((x) >> S_CMMAXPSTRUCT) & M_CMMAXPSTRUCT) 4303 4304 #define A_TP_INT_ENABLE 0x470 4305 #define A_TP_INT_CAUSE 0x474 4306 #define A_TP_FLM_FREE_PS_CNT 0x480 4307 4308 #define S_FREEPSTRUCTCOUNT 0 4309 #define M_FREEPSTRUCTCOUNT 0x1fffff 4310 #define V_FREEPSTRUCTCOUNT(x) ((x) << S_FREEPSTRUCTCOUNT) 4311 #define G_FREEPSTRUCTCOUNT(x) (((x) >> S_FREEPSTRUCTCOUNT) & M_FREEPSTRUCTCOUNT) 4312 4313 #define A_TP_FLM_FREE_RX_CNT 0x484 4314 4315 #define S_FREERXPAGECOUNT 0 4316 #define M_FREERXPAGECOUNT 0x1fffff 4317 #define V_FREERXPAGECOUNT(x) ((x) << S_FREERXPAGECOUNT) 4318 #define G_FREERXPAGECOUNT(x) (((x) >> S_FREERXPAGECOUNT) & M_FREERXPAGECOUNT) 4319 4320 #define A_TP_FLM_FREE_TX_CNT 0x488 4321 4322 #define S_FREETXPAGECOUNT 0 4323 #define M_FREETXPAGECOUNT 0x1fffff 4324 #define V_FREETXPAGECOUNT(x) ((x) << S_FREETXPAGECOUNT) 4325 #define G_FREETXPAGECOUNT(x) (((x) >> S_FREETXPAGECOUNT) & M_FREETXPAGECOUNT) 4326 4327 #define A_TP_TM_HEAP_PUSH_CNT 0x48c 4328 #define A_TP_TM_HEAP_POP_CNT 0x490 4329 #define A_TP_TM_DACK_PUSH_CNT 0x494 4330 #define A_TP_TM_DACK_POP_CNT 0x498 4331 #define A_TP_TM_MOD_PUSH_CNT 0x49c 4332 #define A_TP_MOD_POP_CNT 0x4a0 4333 #define A_TP_TIMER_SEPARATOR 0x4a4 4334 #define A_TP_DEBUG_SEL 0x4a8 4335 #define A_TP_DEBUG_FLAGS 0x4ac 4336 4337 #define S_RXDEBUGFLAGS 16 4338 #define M_RXDEBUGFLAGS 0xffff 4339 #define V_RXDEBUGFLAGS(x) ((x) << S_RXDEBUGFLAGS) 4340 #define G_RXDEBUGFLAGS(x) (((x) >> S_RXDEBUGFLAGS) & M_RXDEBUGFLAGS) 4341 4342 #define S_TXDEBUGFLAGS 0 4343 #define M_TXDEBUGFLAGS 0xffff 4344 #define V_TXDEBUGFLAGS(x) ((x) << S_TXDEBUGFLAGS) 4345 #define G_TXDEBUGFLAGS(x) (((x) >> S_TXDEBUGFLAGS) & M_TXDEBUGFLAGS) 4346 4347 #define S_RXTIMERDACKFIRST 26 4348 #define V_RXTIMERDACKFIRST(x) ((x) << S_RXTIMERDACKFIRST) 4349 #define F_RXTIMERDACKFIRST V_RXTIMERDACKFIRST(1U) 4350 4351 #define S_RXTIMERDACK 25 4352 #define V_RXTIMERDACK(x) ((x) << S_RXTIMERDACK) 4353 #define F_RXTIMERDACK V_RXTIMERDACK(1U) 4354 4355 #define S_RXTIMERHEARTBEAT 24 4356 #define V_RXTIMERHEARTBEAT(x) ((x) << S_RXTIMERHEARTBEAT) 4357 #define F_RXTIMERHEARTBEAT V_RXTIMERHEARTBEAT(1U) 4358 4359 #define S_RXPAWSDROP 23 4360 #define V_RXPAWSDROP(x) ((x) << S_RXPAWSDROP) 4361 #define F_RXPAWSDROP V_RXPAWSDROP(1U) 4362 4363 #define S_RXURGDATADROP 22 4364 #define V_RXURGDATADROP(x) ((x) << S_RXURGDATADROP) 4365 #define F_RXURGDATADROP V_RXURGDATADROP(1U) 4366 4367 #define S_RXFUTUREDATA 21 4368 #define V_RXFUTUREDATA(x) ((x) << S_RXFUTUREDATA) 4369 #define F_RXFUTUREDATA V_RXFUTUREDATA(1U) 4370 4371 #define S_RXRCVRXMDATA 20 4372 #define V_RXRCVRXMDATA(x) ((x) << S_RXRCVRXMDATA) 4373 #define F_RXRCVRXMDATA V_RXRCVRXMDATA(1U) 4374 4375 #define S_RXRCVOOODATAFIN 19 4376 #define V_RXRCVOOODATAFIN(x) ((x) << S_RXRCVOOODATAFIN) 4377 #define F_RXRCVOOODATAFIN V_RXRCVOOODATAFIN(1U) 4378 4379 #define S_RXRCVOOODATA 18 4380 #define V_RXRCVOOODATA(x) ((x) << S_RXRCVOOODATA) 4381 #define F_RXRCVOOODATA V_RXRCVOOODATA(1U) 4382 4383 #define S_RXRCVWNDZERO 17 4384 #define V_RXRCVWNDZERO(x) ((x) << S_RXRCVWNDZERO) 4385 #define F_RXRCVWNDZERO V_RXRCVWNDZERO(1U) 4386 4387 #define S_RXRCVWNDLTMSS 16 4388 #define V_RXRCVWNDLTMSS(x) ((x) << S_RXRCVWNDLTMSS) 4389 #define F_RXRCVWNDLTMSS V_RXRCVWNDLTMSS(1U) 4390 4391 #define S_TXDUPACKINC 11 4392 #define V_TXDUPACKINC(x) ((x) << S_TXDUPACKINC) 4393 #define F_TXDUPACKINC V_TXDUPACKINC(1U) 4394 4395 #define S_TXRXMURG 10 4396 #define V_TXRXMURG(x) ((x) << S_TXRXMURG) 4397 #define F_TXRXMURG V_TXRXMURG(1U) 4398 4399 #define S_TXRXMFIN 9 4400 #define V_TXRXMFIN(x) ((x) << S_TXRXMFIN) 4401 #define F_TXRXMFIN V_TXRXMFIN(1U) 4402 4403 #define S_TXRXMSYN 8 4404 #define V_TXRXMSYN(x) ((x) << S_TXRXMSYN) 4405 #define F_TXRXMSYN V_TXRXMSYN(1U) 4406 4407 #define S_TXRXMNEWRENO 7 4408 #define V_TXRXMNEWRENO(x) ((x) << S_TXRXMNEWRENO) 4409 #define F_TXRXMNEWRENO V_TXRXMNEWRENO(1U) 4410 4411 #define S_TXRXMFAST 6 4412 #define V_TXRXMFAST(x) ((x) << S_TXRXMFAST) 4413 #define F_TXRXMFAST V_TXRXMFAST(1U) 4414 4415 #define S_TXRXMTIMER 5 4416 #define V_TXRXMTIMER(x) ((x) << S_TXRXMTIMER) 4417 #define F_TXRXMTIMER V_TXRXMTIMER(1U) 4418 4419 #define S_TXRXMTIMERKEEPALIVE 4 4420 #define V_TXRXMTIMERKEEPALIVE(x) ((x) << S_TXRXMTIMERKEEPALIVE) 4421 #define F_TXRXMTIMERKEEPALIVE V_TXRXMTIMERKEEPALIVE(1U) 4422 4423 #define S_TXRXMTIMERPERSIST 3 4424 #define V_TXRXMTIMERPERSIST(x) ((x) << S_TXRXMTIMERPERSIST) 4425 #define F_TXRXMTIMERPERSIST V_TXRXMTIMERPERSIST(1U) 4426 4427 #define S_TXRCVADVSHRUNK 2 4428 #define V_TXRCVADVSHRUNK(x) ((x) << S_TXRCVADVSHRUNK) 4429 #define F_TXRCVADVSHRUNK V_TXRCVADVSHRUNK(1U) 4430 4431 #define S_TXRCVADVZERO 1 4432 #define V_TXRCVADVZERO(x) ((x) << S_TXRCVADVZERO) 4433 #define F_TXRCVADVZERO V_TXRCVADVZERO(1U) 4434 4435 #define S_TXRCVADVLTMSS 0 4436 #define V_TXRCVADVLTMSS(x) ((x) << S_TXRCVADVLTMSS) 4437 #define F_TXRCVADVLTMSS V_TXRCVADVLTMSS(1U) 4438 4439 #define A_TP_CM_FLOW_CNTL_MODE 0x4b0 4440 4441 #define S_CMFLOWCACHEDISABLE 0 4442 #define V_CMFLOWCACHEDISABLE(x) ((x) << S_CMFLOWCACHEDISABLE) 4443 #define F_CMFLOWCACHEDISABLE V_CMFLOWCACHEDISABLE(1U) 4444 4445 #define A_TP_PROXY_FLOW_CNTL 0x4b0 4446 #define A_TP_PC_CONGESTION_CNTL 0x4b4 4447 4448 #define S_EDROPTUNNEL 19 4449 #define V_EDROPTUNNEL(x) ((x) << S_EDROPTUNNEL) 4450 #define F_EDROPTUNNEL V_EDROPTUNNEL(1U) 4451 4452 #define S_CDROPTUNNEL 18 4453 #define V_CDROPTUNNEL(x) ((x) << S_CDROPTUNNEL) 4454 #define F_CDROPTUNNEL V_CDROPTUNNEL(1U) 4455 4456 #define S_ETHRESHOLD 12 4457 #define M_ETHRESHOLD 0x3f 4458 #define V_ETHRESHOLD(x) ((x) << S_ETHRESHOLD) 4459 #define G_ETHRESHOLD(x) (((x) >> S_ETHRESHOLD) & M_ETHRESHOLD) 4460 4461 #define S_CTHRESHOLD 6 4462 #define M_CTHRESHOLD 0x3f 4463 #define V_CTHRESHOLD(x) ((x) << S_CTHRESHOLD) 4464 #define G_CTHRESHOLD(x) (((x) >> S_CTHRESHOLD) & M_CTHRESHOLD) 4465 4466 #define S_TXTHRESHOLD 0 4467 #define M_TXTHRESHOLD 0x3f 4468 #define V_TXTHRESHOLD(x) ((x) << S_TXTHRESHOLD) 4469 #define G_TXTHRESHOLD(x) (((x) >> S_TXTHRESHOLD) & M_TXTHRESHOLD) 4470 4471 #define A_TP_TX_DROP_COUNT 0x4bc 4472 #define A_TP_CLEAR_DEBUG 0x4c0 4473 4474 #define S_CLRDEBUG 0 4475 #define V_CLRDEBUG(x) ((x) << S_CLRDEBUG) 4476 #define F_CLRDEBUG V_CLRDEBUG(1U) 4477 4478 #define A_TP_DEBUG_VEC 0x4c4 4479 #define A_TP_DEBUG_VEC2 0x4c8 4480 #define A_TP_DEBUG_REG_SEL 0x4cc 4481 #define A_TP_DEBUG 0x4d0 4482 #define A_TP_DBG_LA_CONFIG 0x4d4 4483 #define A_TP_DBG_LA_DATAH 0x4d8 4484 #define A_TP_DBG_LA_DATAL 0x4dc 4485 #define A_TP_EMBED_OP_FIELD0 0x4e8 4486 #define A_TP_EMBED_OP_FIELD1 0x4ec 4487 #define A_TP_EMBED_OP_FIELD2 0x4f0 4488 #define A_TP_EMBED_OP_FIELD3 0x4f4 4489 #define A_TP_EMBED_OP_FIELD4 0x4f8 4490 #define A_TP_EMBED_OP_FIELD5 0x4fc 4491 #define A_TP_TX_MOD_Q7_Q6_TIMER_SEPARATOR 0x0 4492 #define A_TP_TX_MOD_Q5_Q4_TIMER_SEPARATOR 0x1 4493 #define A_TP_TX_MOD_Q3_Q2_TIMER_SEPARATOR 0x2 4494 #define A_TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR 0x3 4495 #define A_TP_RX_MOD_Q1_Q0_TIMER_SEPARATOR 0x4 4496 #define A_TP_TX_MOD_Q7_Q6_RATE_LIMIT 0x5 4497 #define A_TP_TX_MOD_Q5_Q4_RATE_LIMIT 0x6 4498 #define A_TP_TX_MOD_Q3_Q2_RATE_LIMIT 0x7 4499 #define A_TP_TX_MOD_Q1_Q0_RATE_LIMIT 0x8 4500 #define A_TP_RX_MOD_Q1_Q0_RATE_LIMIT 0x9 4501 #define A_TP_TX_TRC_KEY0 0x20 4502 #define A_TP_TX_TRC_MASK0 0x21 4503 #define A_TP_TX_TRC_KEY1 0x22 4504 #define A_TP_TX_TRC_MASK1 0x23 4505 #define A_TP_TX_TRC_KEY2 0x24 4506 #define A_TP_TX_TRC_MASK2 0x25 4507 #define A_TP_TX_TRC_KEY3 0x26 4508 #define A_TP_TX_TRC_MASK3 0x27 4509 #define A_TP_IPMI_CFG1 0x28 4510 4511 #define S_VLANENABLE 31 4512 #define V_VLANENABLE(x) ((x) << S_VLANENABLE) 4513 #define F_VLANENABLE V_VLANENABLE(1U) 4514 4515 #define S_PRIMARYPORTENABLE 30 4516 #define V_PRIMARYPORTENABLE(x) ((x) << S_PRIMARYPORTENABLE) 4517 #define F_PRIMARYPORTENABLE V_PRIMARYPORTENABLE(1U) 4518 4519 #define S_SECUREPORTENABLE 29 4520 #define V_SECUREPORTENABLE(x) ((x) << S_SECUREPORTENABLE) 4521 #define F_SECUREPORTENABLE V_SECUREPORTENABLE(1U) 4522 4523 #define S_ARPENABLE 28 4524 #define V_ARPENABLE(x) ((x) << S_ARPENABLE) 4525 #define F_ARPENABLE V_ARPENABLE(1U) 4526 4527 #define S_VLAN 0 4528 #define M_VLAN 0xffff 4529 #define V_VLAN(x) ((x) << S_VLAN) 4530 #define G_VLAN(x) (((x) >> S_VLAN) & M_VLAN) 4531 4532 #define A_TP_IPMI_CFG2 0x29 4533 4534 #define S_SECUREPORT 16 4535 #define M_SECUREPORT 0xffff 4536 #define V_SECUREPORT(x) ((x) << S_SECUREPORT) 4537 #define G_SECUREPORT(x) (((x) >> S_SECUREPORT) & M_SECUREPORT) 4538 4539 #define S_PRIMARYPORT 0 4540 #define M_PRIMARYPORT 0xffff 4541 #define V_PRIMARYPORT(x) ((x) << S_PRIMARYPORT) 4542 #define G_PRIMARYPORT(x) (((x) >> S_PRIMARYPORT) & M_PRIMARYPORT) 4543 4544 #define A_TP_RX_TRC_KEY0 0x120 4545 #define A_TP_RX_TRC_MASK0 0x121 4546 #define A_TP_RX_TRC_KEY1 0x122 4547 #define A_TP_RX_TRC_MASK1 0x123 4548 #define A_TP_RX_TRC_KEY2 0x124 4549 #define A_TP_RX_TRC_MASK2 0x125 4550 #define A_TP_RX_TRC_KEY3 0x126 4551 #define A_TP_RX_TRC_MASK3 0x127 4552 #define A_TP_QOS_RX_TOS_MAP_H 0x128 4553 #define A_TP_QOS_RX_TOS_MAP_L 0x129 4554 #define A_TP_QOS_RX_MAP_MODE 0x12a 4555 4556 #define S_DEFAULTCH 11 4557 #define V_DEFAULTCH(x) ((x) << S_DEFAULTCH) 4558 #define F_DEFAULTCH V_DEFAULTCH(1U) 4559 4560 #define S_RXMAPMODE 8 4561 #define M_RXMAPMODE 0x7 4562 #define V_RXMAPMODE(x) ((x) << S_RXMAPMODE) 4563 #define G_RXMAPMODE(x) (((x) >> S_RXMAPMODE) & M_RXMAPMODE) 4564 4565 #define S_RXVLANMAP 7 4566 #define V_RXVLANMAP(x) ((x) << S_RXVLANMAP) 4567 #define F_RXVLANMAP V_RXVLANMAP(1U) 4568 4569 #define A_TP_TX_DROP_CFG_CH0 0x12b 4570 4571 #define S_TIMERENABLED 31 4572 #define V_TIMERENABLED(x) ((x) << S_TIMERENABLED) 4573 #define F_TIMERENABLED V_TIMERENABLED(1U) 4574 4575 #define S_TIMERERRORENABLE 30 4576 #define V_TIMERERRORENABLE(x) ((x) << S_TIMERERRORENABLE) 4577 #define F_TIMERERRORENABLE V_TIMERERRORENABLE(1U) 4578 4579 #define S_TIMERTHRESHOLD 4 4580 #define M_TIMERTHRESHOLD 0x3ffffff 4581 #define V_TIMERTHRESHOLD(x) ((x) << S_TIMERTHRESHOLD) 4582 #define G_TIMERTHRESHOLD(x) (((x) >> S_TIMERTHRESHOLD) & M_TIMERTHRESHOLD) 4583 4584 #define S_PACKETDROPS 0 4585 #define M_PACKETDROPS 0xf 4586 #define V_PACKETDROPS(x) ((x) << S_PACKETDROPS) 4587 #define G_PACKETDROPS(x) (((x) >> S_PACKETDROPS) & M_PACKETDROPS) 4588 4589 #define A_TP_TX_DROP_CFG_CH1 0x12c 4590 #define A_TP_TX_DROP_CNT_CH0 0x12d 4591 4592 #define S_TXDROPCNTCH0SENT 16 4593 #define M_TXDROPCNTCH0SENT 0xffff 4594 #define V_TXDROPCNTCH0SENT(x) ((x) << S_TXDROPCNTCH0SENT) 4595 #define G_TXDROPCNTCH0SENT(x) (((x) >> S_TXDROPCNTCH0SENT) & M_TXDROPCNTCH0SENT) 4596 4597 #define S_TXDROPCNTCH0RCVD 0 4598 #define M_TXDROPCNTCH0RCVD 0xffff 4599 #define V_TXDROPCNTCH0RCVD(x) ((x) << S_TXDROPCNTCH0RCVD) 4600 #define G_TXDROPCNTCH0RCVD(x) (((x) >> S_TXDROPCNTCH0RCVD) & M_TXDROPCNTCH0RCVD) 4601 4602 #define A_TP_TX_DROP_CNT_CH1 0x12e 4603 4604 #define S_TXDROPCNTCH1SENT 16 4605 #define M_TXDROPCNTCH1SENT 0xffff 4606 #define V_TXDROPCNTCH1SENT(x) ((x) << S_TXDROPCNTCH1SENT) 4607 #define G_TXDROPCNTCH1SENT(x) (((x) >> S_TXDROPCNTCH1SENT) & M_TXDROPCNTCH1SENT) 4608 4609 #define S_TXDROPCNTCH1RCVD 0 4610 #define M_TXDROPCNTCH1RCVD 0xffff 4611 #define V_TXDROPCNTCH1RCVD(x) ((x) << S_TXDROPCNTCH1RCVD) 4612 #define G_TXDROPCNTCH1RCVD(x) (((x) >> S_TXDROPCNTCH1RCVD) & M_TXDROPCNTCH1RCVD) 4613 4614 #define A_TP_TX_DROP_MODE 0x12f 4615 4616 #define S_TXDROPMODECH1 1 4617 #define V_TXDROPMODECH1(x) ((x) << S_TXDROPMODECH1) 4618 #define F_TXDROPMODECH1 V_TXDROPMODECH1(1U) 4619 4620 #define S_TXDROPMODECH0 0 4621 #define V_TXDROPMODECH0(x) ((x) << S_TXDROPMODECH0) 4622 #define F_TXDROPMODECH0 V_TXDROPMODECH0(1U) 4623 4624 #define A_TP_VLAN_PRI_MAP 0x137 4625 4626 #define S_VLANPRIMAP7 14 4627 #define M_VLANPRIMAP7 0x3 4628 #define V_VLANPRIMAP7(x) ((x) << S_VLANPRIMAP7) 4629 #define G_VLANPRIMAP7(x) (((x) >> S_VLANPRIMAP7) & M_VLANPRIMAP7) 4630 4631 #define S_VLANPRIMAP6 12 4632 #define M_VLANPRIMAP6 0x3 4633 #define V_VLANPRIMAP6(x) ((x) << S_VLANPRIMAP6) 4634 #define G_VLANPRIMAP6(x) (((x) >> S_VLANPRIMAP6) & M_VLANPRIMAP6) 4635 4636 #define S_VLANPRIMAP5 10 4637 #define M_VLANPRIMAP5 0x3 4638 #define V_VLANPRIMAP5(x) ((x) << S_VLANPRIMAP5) 4639 #define G_VLANPRIMAP5(x) (((x) >> S_VLANPRIMAP5) & M_VLANPRIMAP5) 4640 4641 #define S_VLANPRIMAP4 8 4642 #define M_VLANPRIMAP4 0x3 4643 #define V_VLANPRIMAP4(x) ((x) << S_VLANPRIMAP4) 4644 #define G_VLANPRIMAP4(x) (((x) >> S_VLANPRIMAP4) & M_VLANPRIMAP4) 4645 4646 #define S_VLANPRIMAP3 6 4647 #define M_VLANPRIMAP3 0x3 4648 #define V_VLANPRIMAP3(x) ((x) << S_VLANPRIMAP3) 4649 #define G_VLANPRIMAP3(x) (((x) >> S_VLANPRIMAP3) & M_VLANPRIMAP3) 4650 4651 #define S_VLANPRIMAP2 4 4652 #define M_VLANPRIMAP2 0x3 4653 #define V_VLANPRIMAP2(x) ((x) << S_VLANPRIMAP2) 4654 #define G_VLANPRIMAP2(x) (((x) >> S_VLANPRIMAP2) & M_VLANPRIMAP2) 4655 4656 #define S_VLANPRIMAP1 2 4657 #define M_VLANPRIMAP1 0x3 4658 #define V_VLANPRIMAP1(x) ((x) << S_VLANPRIMAP1) 4659 #define G_VLANPRIMAP1(x) (((x) >> S_VLANPRIMAP1) & M_VLANPRIMAP1) 4660 4661 #define S_VLANPRIMAP0 0 4662 #define M_VLANPRIMAP0 0x3 4663 #define V_VLANPRIMAP0(x) ((x) << S_VLANPRIMAP0) 4664 #define G_VLANPRIMAP0(x) (((x) >> S_VLANPRIMAP0) & M_VLANPRIMAP0) 4665 4666 #define A_TP_MAC_MATCH_MAP0 0x138 4667 4668 #define S_MACMATCHMAP7 21 4669 #define M_MACMATCHMAP7 0x7 4670 #define V_MACMATCHMAP7(x) ((x) << S_MACMATCHMAP7) 4671 #define G_MACMATCHMAP7(x) (((x) >> S_MACMATCHMAP7) & M_MACMATCHMAP7) 4672 4673 #define S_MACMATCHMAP6 18 4674 #define M_MACMATCHMAP6 0x7 4675 #define V_MACMATCHMAP6(x) ((x) << S_MACMATCHMAP6) 4676 #define G_MACMATCHMAP6(x) (((x) >> S_MACMATCHMAP6) & M_MACMATCHMAP6) 4677 4678 #define S_MACMATCHMAP5 15 4679 #define M_MACMATCHMAP5 0x7 4680 #define V_MACMATCHMAP5(x) ((x) << S_MACMATCHMAP5) 4681 #define G_MACMATCHMAP5(x) (((x) >> S_MACMATCHMAP5) & M_MACMATCHMAP5) 4682 4683 #define S_MACMATCHMAP4 12 4684 #define M_MACMATCHMAP4 0x7 4685 #define V_MACMATCHMAP4(x) ((x) << S_MACMATCHMAP4) 4686 #define G_MACMATCHMAP4(x) (((x) >> S_MACMATCHMAP4) & M_MACMATCHMAP4) 4687 4688 #define S_MACMATCHMAP3 9 4689 #define M_MACMATCHMAP3 0x7 4690 #define V_MACMATCHMAP3(x) ((x) << S_MACMATCHMAP3) 4691 #define G_MACMATCHMAP3(x) (((x) >> S_MACMATCHMAP3) & M_MACMATCHMAP3) 4692 4693 #define S_MACMATCHMAP2 6 4694 #define M_MACMATCHMAP2 0x7 4695 #define V_MACMATCHMAP2(x) ((x) << S_MACMATCHMAP2) 4696 #define G_MACMATCHMAP2(x) (((x) >> S_MACMATCHMAP2) & M_MACMATCHMAP2) 4697 4698 #define S_MACMATCHMAP1 3 4699 #define M_MACMATCHMAP1 0x7 4700 #define V_MACMATCHMAP1(x) ((x) << S_MACMATCHMAP1) 4701 #define G_MACMATCHMAP1(x) (((x) >> S_MACMATCHMAP1) & M_MACMATCHMAP1) 4702 4703 #define S_MACMATCHMAP0 0 4704 #define M_MACMATCHMAP0 0x7 4705 #define V_MACMATCHMAP0(x) ((x) << S_MACMATCHMAP0) 4706 #define G_MACMATCHMAP0(x) (((x) >> S_MACMATCHMAP0) & M_MACMATCHMAP0) 4707 4708 #define A_TP_MAC_MATCH_MAP1 0x139 4709 #define A_TP_INGRESS_CONFIG 0x141 4710 4711 #define S_LOOKUPEVERYPKT 28 4712 #define V_LOOKUPEVERYPKT(x) ((x) << S_LOOKUPEVERYPKT) 4713 #define F_LOOKUPEVERYPKT V_LOOKUPEVERYPKT(1U) 4714 4715 #define S_ENABLEINSERTIONSFD 27 4716 #define V_ENABLEINSERTIONSFD(x) ((x) << S_ENABLEINSERTIONSFD) 4717 #define F_ENABLEINSERTIONSFD V_ENABLEINSERTIONSFD(1U) 4718 4719 #define S_ENABLEINSERTION 26 4720 #define V_ENABLEINSERTION(x) ((x) << S_ENABLEINSERTION) 4721 #define F_ENABLEINSERTION V_ENABLEINSERTION(1U) 4722 4723 #define S_ENABLEEXTRACTIONSFD 25 4724 #define V_ENABLEEXTRACTIONSFD(x) ((x) << S_ENABLEEXTRACTIONSFD) 4725 #define F_ENABLEEXTRACTIONSFD V_ENABLEEXTRACTIONSFD(1U) 4726 4727 #define S_ENABLEEXTRACT 24 4728 #define V_ENABLEEXTRACT(x) ((x) << S_ENABLEEXTRACT) 4729 #define F_ENABLEEXTRACT V_ENABLEEXTRACT(1U) 4730 4731 #define S_BITPOS3 18 4732 #define M_BITPOS3 0x3f 4733 #define V_BITPOS3(x) ((x) << S_BITPOS3) 4734 #define G_BITPOS3(x) (((x) >> S_BITPOS3) & M_BITPOS3) 4735 4736 #define S_BITPOS2 12 4737 #define M_BITPOS2 0x3f 4738 #define V_BITPOS2(x) ((x) << S_BITPOS2) 4739 #define G_BITPOS2(x) (((x) >> S_BITPOS2) & M_BITPOS2) 4740 4741 #define S_BITPOS1 6 4742 #define M_BITPOS1 0x3f 4743 #define V_BITPOS1(x) ((x) << S_BITPOS1) 4744 #define G_BITPOS1(x) (((x) >> S_BITPOS1) & M_BITPOS1) 4745 4746 #define S_BITPOS0 0 4747 #define M_BITPOS0 0x3f 4748 #define V_BITPOS0(x) ((x) << S_BITPOS0) 4749 #define G_BITPOS0(x) (((x) >> S_BITPOS0) & M_BITPOS0) 4750 4751 #define A_TP_PREAMBLE_MSB 0x142 4752 #define A_TP_PREAMBLE_LSB 0x143 4753 #define A_TP_EGRESS_CONFIG 0x145 4754 4755 #define S_REWRITEFORCETOSIZE 0 4756 #define V_REWRITEFORCETOSIZE(x) ((x) << S_REWRITEFORCETOSIZE) 4757 #define F_REWRITEFORCETOSIZE V_REWRITEFORCETOSIZE(1U) 4758 4759 #define A_TP_INTF_FROM_TX_PKT 0x244 4760 4761 #define S_INTFFROMTXPKT 0 4762 #define V_INTFFROMTXPKT(x) ((x) << S_INTFFROMTXPKT) 4763 #define F_INTFFROMTXPKT V_INTFFROMTXPKT(1U) 4764 4765 #define A_TP_FIFO_CONFIG 0x8c0 4766 4767 #define S_RXFIFOCONFIG 10 4768 #define M_RXFIFOCONFIG 0x3f 4769 #define V_RXFIFOCONFIG(x) ((x) << S_RXFIFOCONFIG) 4770 #define G_RXFIFOCONFIG(x) (((x) >> S_RXFIFOCONFIG) & M_RXFIFOCONFIG) 4771 4772 #define S_TXFIFOCONFIG 2 4773 #define M_TXFIFOCONFIG 0x3f 4774 #define V_TXFIFOCONFIG(x) ((x) << S_TXFIFOCONFIG) 4775 #define G_TXFIFOCONFIG(x) (((x) >> S_TXFIFOCONFIG) & M_TXFIFOCONFIG) 4776 4777 /* registers for module ULP2_RX */ 4778 #define ULP2_RX_BASE_ADDR 0x500 4779 4780 #define A_ULPRX_CTL 0x500 4781 4782 #define S_PCMD1THRESHOLD 24 4783 #define M_PCMD1THRESHOLD 0xff 4784 #define V_PCMD1THRESHOLD(x) ((x) << S_PCMD1THRESHOLD) 4785 #define G_PCMD1THRESHOLD(x) (((x) >> S_PCMD1THRESHOLD) & M_PCMD1THRESHOLD) 4786 4787 #define S_PCMD0THRESHOLD 16 4788 #define M_PCMD0THRESHOLD 0xff 4789 #define V_PCMD0THRESHOLD(x) ((x) << S_PCMD0THRESHOLD) 4790 #define G_PCMD0THRESHOLD(x) (((x) >> S_PCMD0THRESHOLD) & M_PCMD0THRESHOLD) 4791 4792 #define S_ROUND_ROBIN 4 4793 #define V_ROUND_ROBIN(x) ((x) << S_ROUND_ROBIN) 4794 #define F_ROUND_ROBIN V_ROUND_ROBIN(1U) 4795 4796 #define S_RDMA_PERMISSIVE_MODE 3 4797 #define V_RDMA_PERMISSIVE_MODE(x) ((x) << S_RDMA_PERMISSIVE_MODE) 4798 #define F_RDMA_PERMISSIVE_MODE V_RDMA_PERMISSIVE_MODE(1U) 4799 4800 #define S_PAGEPODME 2 4801 #define V_PAGEPODME(x) ((x) << S_PAGEPODME) 4802 #define F_PAGEPODME V_PAGEPODME(1U) 4803 4804 #define S_ISCSITAGTCB 1 4805 #define V_ISCSITAGTCB(x) ((x) << S_ISCSITAGTCB) 4806 #define F_ISCSITAGTCB V_ISCSITAGTCB(1U) 4807 4808 #define S_TDDPTAGTCB 0 4809 #define V_TDDPTAGTCB(x) ((x) << S_TDDPTAGTCB) 4810 #define F_TDDPTAGTCB V_TDDPTAGTCB(1U) 4811 4812 #define A_ULPRX_INT_ENABLE 0x504 4813 4814 #define S_PARERR 0 4815 #define V_PARERR(x) ((x) << S_PARERR) 4816 #define F_PARERR V_PARERR(1U) 4817 4818 #define A_ULPRX_INT_CAUSE 0x508 4819 #define A_ULPRX_ISCSI_LLIMIT 0x50c 4820 4821 #define S_ISCSILLIMIT 6 4822 #define M_ISCSILLIMIT 0x3ffffff 4823 #define V_ISCSILLIMIT(x) ((x) << S_ISCSILLIMIT) 4824 #define G_ISCSILLIMIT(x) (((x) >> S_ISCSILLIMIT) & M_ISCSILLIMIT) 4825 4826 #define A_ULPRX_ISCSI_ULIMIT 0x510 4827 4828 #define S_ISCSIULIMIT 6 4829 #define M_ISCSIULIMIT 0x3ffffff 4830 #define V_ISCSIULIMIT(x) ((x) << S_ISCSIULIMIT) 4831 #define G_ISCSIULIMIT(x) (((x) >> S_ISCSIULIMIT) & M_ISCSIULIMIT) 4832 4833 #define A_ULPRX_ISCSI_TAGMASK 0x514 4834 4835 #define S_ISCSITAGMASK 6 4836 #define M_ISCSITAGMASK 0x3ffffff 4837 #define V_ISCSITAGMASK(x) ((x) << S_ISCSITAGMASK) 4838 #define G_ISCSITAGMASK(x) (((x) >> S_ISCSITAGMASK) & M_ISCSITAGMASK) 4839 4840 #define A_ULPRX_ISCSI_PSZ 0x518 4841 4842 #define S_HPZ3 24 4843 #define M_HPZ3 0xf 4844 #define V_HPZ3(x) ((x) << S_HPZ3) 4845 #define G_HPZ3(x) (((x) >> S_HPZ3) & M_HPZ3) 4846 4847 #define S_HPZ2 16 4848 #define M_HPZ2 0xf 4849 #define V_HPZ2(x) ((x) << S_HPZ2) 4850 #define G_HPZ2(x) (((x) >> S_HPZ2) & M_HPZ2) 4851 4852 #define S_HPZ1 8 4853 #define M_HPZ1 0xf 4854 #define V_HPZ1(x) ((x) << S_HPZ1) 4855 #define G_HPZ1(x) (((x) >> S_HPZ1) & M_HPZ1) 4856 4857 #define S_HPZ0 0 4858 #define M_HPZ0 0xf 4859 #define V_HPZ0(x) ((x) << S_HPZ0) 4860 #define G_HPZ0(x) (((x) >> S_HPZ0) & M_HPZ0) 4861 4862 #define A_ULPRX_TDDP_LLIMIT 0x51c 4863 4864 #define S_TDDPLLIMIT 6 4865 #define M_TDDPLLIMIT 0x3ffffff 4866 #define V_TDDPLLIMIT(x) ((x) << S_TDDPLLIMIT) 4867 #define G_TDDPLLIMIT(x) (((x) >> S_TDDPLLIMIT) & M_TDDPLLIMIT) 4868 4869 #define A_ULPRX_TDDP_ULIMIT 0x520 4870 4871 #define S_TDDPULIMIT 6 4872 #define M_TDDPULIMIT 0x3ffffff 4873 #define V_TDDPULIMIT(x) ((x) << S_TDDPULIMIT) 4874 #define G_TDDPULIMIT(x) (((x) >> S_TDDPULIMIT) & M_TDDPULIMIT) 4875 4876 #define A_ULPRX_TDDP_TAGMASK 0x524 4877 4878 #define S_TDDPTAGMASK 6 4879 #define M_TDDPTAGMASK 0x3ffffff 4880 #define V_TDDPTAGMASK(x) ((x) << S_TDDPTAGMASK) 4881 #define G_TDDPTAGMASK(x) (((x) >> S_TDDPTAGMASK) & M_TDDPTAGMASK) 4882 4883 #define A_ULPRX_TDDP_PSZ 0x528 4884 #define A_ULPRX_STAG_LLIMIT 0x52c 4885 #define A_ULPRX_STAG_ULIMIT 0x530 4886 #define A_ULPRX_RQ_LLIMIT 0x534 4887 #define A_ULPRX_RQ_ULIMIT 0x538 4888 #define A_ULPRX_PBL_LLIMIT 0x53c 4889 #define A_ULPRX_PBL_ULIMIT 0x540 4890 4891 /* registers for module ULP2_TX */ 4892 #define ULP2_TX_BASE_ADDR 0x580 4893 4894 #define A_ULPTX_CONFIG 0x580 4895 4896 #define S_CFG_RR_ARB 0 4897 #define V_CFG_RR_ARB(x) ((x) << S_CFG_RR_ARB) 4898 #define F_CFG_RR_ARB V_CFG_RR_ARB(1U) 4899 4900 #define A_ULPTX_INT_ENABLE 0x584 4901 4902 #define S_PBL_BOUND_ERR_CH1 1 4903 #define V_PBL_BOUND_ERR_CH1(x) ((x) << S_PBL_BOUND_ERR_CH1) 4904 #define F_PBL_BOUND_ERR_CH1 V_PBL_BOUND_ERR_CH1(1U) 4905 4906 #define S_PBL_BOUND_ERR_CH0 0 4907 #define V_PBL_BOUND_ERR_CH0(x) ((x) << S_PBL_BOUND_ERR_CH0) 4908 #define F_PBL_BOUND_ERR_CH0 V_PBL_BOUND_ERR_CH0(1U) 4909 4910 #define A_ULPTX_INT_CAUSE 0x588 4911 #define A_ULPTX_TPT_LLIMIT 0x58c 4912 #define A_ULPTX_TPT_ULIMIT 0x590 4913 #define A_ULPTX_PBL_LLIMIT 0x594 4914 #define A_ULPTX_PBL_ULIMIT 0x598 4915 #define A_ULPTX_CPL_ERR_OFFSET 0x59c 4916 #define A_ULPTX_CPL_ERR_MASK 0x5a0 4917 #define A_ULPTX_CPL_ERR_VALUE 0x5a4 4918 #define A_ULPTX_CPL_PACK_SIZE 0x5a8 4919 4920 #define S_VALUE 24 4921 #define M_VALUE 0xff 4922 #define V_VALUE(x) ((x) << S_VALUE) 4923 #define G_VALUE(x) (((x) >> S_VALUE) & M_VALUE) 4924 4925 #define S_CH1SIZE2 24 4926 #define M_CH1SIZE2 0xff 4927 #define V_CH1SIZE2(x) ((x) << S_CH1SIZE2) 4928 #define G_CH1SIZE2(x) (((x) >> S_CH1SIZE2) & M_CH1SIZE2) 4929 4930 #define S_CH1SIZE1 16 4931 #define M_CH1SIZE1 0xff 4932 #define V_CH1SIZE1(x) ((x) << S_CH1SIZE1) 4933 #define G_CH1SIZE1(x) (((x) >> S_CH1SIZE1) & M_CH1SIZE1) 4934 4935 #define S_CH0SIZE2 8 4936 #define M_CH0SIZE2 0xff 4937 #define V_CH0SIZE2(x) ((x) << S_CH0SIZE2) 4938 #define G_CH0SIZE2(x) (((x) >> S_CH0SIZE2) & M_CH0SIZE2) 4939 4940 #define S_CH0SIZE1 0 4941 #define M_CH0SIZE1 0xff 4942 #define V_CH0SIZE1(x) ((x) << S_CH0SIZE1) 4943 #define G_CH0SIZE1(x) (((x) >> S_CH0SIZE1) & M_CH0SIZE1) 4944 4945 #define A_ULPTX_DMA_WEIGHT 0x5ac 4946 4947 #define S_D1_WEIGHT 16 4948 #define M_D1_WEIGHT 0xffff 4949 #define V_D1_WEIGHT(x) ((x) << S_D1_WEIGHT) 4950 #define G_D1_WEIGHT(x) (((x) >> S_D1_WEIGHT) & M_D1_WEIGHT) 4951 4952 #define S_D0_WEIGHT 0 4953 #define M_D0_WEIGHT 0xffff 4954 #define V_D0_WEIGHT(x) ((x) << S_D0_WEIGHT) 4955 #define G_D0_WEIGHT(x) (((x) >> S_D0_WEIGHT) & M_D0_WEIGHT) 4956 4957 /* registers for module PM1_RX */ 4958 #define PM1_RX_BASE_ADDR 0x5c0 4959 4960 #define A_PM1_RX_CFG 0x5c0 4961 #define A_PM1_RX_MODE 0x5c4 4962 4963 #define S_STAT_CHANNEL 1 4964 #define V_STAT_CHANNEL(x) ((x) << S_STAT_CHANNEL) 4965 #define F_STAT_CHANNEL V_STAT_CHANNEL(1U) 4966 4967 #define S_PRIORITY_CH 0 4968 #define V_PRIORITY_CH(x) ((x) << S_PRIORITY_CH) 4969 #define F_PRIORITY_CH V_PRIORITY_CH(1U) 4970 4971 #define A_PM1_RX_STAT_CONFIG 0x5c8 4972 #define A_PM1_RX_STAT_COUNT 0x5cc 4973 #define A_PM1_RX_STAT_MSB 0x5d0 4974 #define A_PM1_RX_STAT_LSB 0x5d4 4975 #define A_PM1_RX_INT_ENABLE 0x5d8 4976 4977 #define S_ZERO_E_CMD_ERROR 18 4978 #define V_ZERO_E_CMD_ERROR(x) ((x) << S_ZERO_E_CMD_ERROR) 4979 #define F_ZERO_E_CMD_ERROR V_ZERO_E_CMD_ERROR(1U) 4980 4981 #define S_IESPI0_FIFO2X_RX_FRAMING_ERROR 17 4982 #define V_IESPI0_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_IESPI0_FIFO2X_RX_FRAMING_ERROR) 4983 #define F_IESPI0_FIFO2X_RX_FRAMING_ERROR V_IESPI0_FIFO2X_RX_FRAMING_ERROR(1U) 4984 4985 #define S_IESPI1_FIFO2X_RX_FRAMING_ERROR 16 4986 #define V_IESPI1_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_IESPI1_FIFO2X_RX_FRAMING_ERROR) 4987 #define F_IESPI1_FIFO2X_RX_FRAMING_ERROR V_IESPI1_FIFO2X_RX_FRAMING_ERROR(1U) 4988 4989 #define S_IESPI0_RX_FRAMING_ERROR 15 4990 #define V_IESPI0_RX_FRAMING_ERROR(x) ((x) << S_IESPI0_RX_FRAMING_ERROR) 4991 #define F_IESPI0_RX_FRAMING_ERROR V_IESPI0_RX_FRAMING_ERROR(1U) 4992 4993 #define S_IESPI1_RX_FRAMING_ERROR 14 4994 #define V_IESPI1_RX_FRAMING_ERROR(x) ((x) << S_IESPI1_RX_FRAMING_ERROR) 4995 #define F_IESPI1_RX_FRAMING_ERROR V_IESPI1_RX_FRAMING_ERROR(1U) 4996 4997 #define S_IESPI0_TX_FRAMING_ERROR 13 4998 #define V_IESPI0_TX_FRAMING_ERROR(x) ((x) << S_IESPI0_TX_FRAMING_ERROR) 4999 #define F_IESPI0_TX_FRAMING_ERROR V_IESPI0_TX_FRAMING_ERROR(1U) 5000 5001 #define S_IESPI1_TX_FRAMING_ERROR 12 5002 #define V_IESPI1_TX_FRAMING_ERROR(x) ((x) << S_IESPI1_TX_FRAMING_ERROR) 5003 #define F_IESPI1_TX_FRAMING_ERROR V_IESPI1_TX_FRAMING_ERROR(1U) 5004 5005 #define S_OCSPI0_RX_FRAMING_ERROR 11 5006 #define V_OCSPI0_RX_FRAMING_ERROR(x) ((x) << S_OCSPI0_RX_FRAMING_ERROR) 5007 #define F_OCSPI0_RX_FRAMING_ERROR V_OCSPI0_RX_FRAMING_ERROR(1U) 5008 5009 #define S_OCSPI1_RX_FRAMING_ERROR 10 5010 #define V_OCSPI1_RX_FRAMING_ERROR(x) ((x) << S_OCSPI1_RX_FRAMING_ERROR) 5011 #define F_OCSPI1_RX_FRAMING_ERROR V_OCSPI1_RX_FRAMING_ERROR(1U) 5012 5013 #define S_OCSPI0_TX_FRAMING_ERROR 9 5014 #define V_OCSPI0_TX_FRAMING_ERROR(x) ((x) << S_OCSPI0_TX_FRAMING_ERROR) 5015 #define F_OCSPI0_TX_FRAMING_ERROR V_OCSPI0_TX_FRAMING_ERROR(1U) 5016 5017 #define S_OCSPI1_TX_FRAMING_ERROR 8 5018 #define V_OCSPI1_TX_FRAMING_ERROR(x) ((x) << S_OCSPI1_TX_FRAMING_ERROR) 5019 #define F_OCSPI1_TX_FRAMING_ERROR V_OCSPI1_TX_FRAMING_ERROR(1U) 5020 5021 #define S_OCSPI0_OFIFO2X_TX_FRAMING_ERROR 7 5022 #define V_OCSPI0_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OCSPI0_OFIFO2X_TX_FRAMING_ERROR) 5023 #define F_OCSPI0_OFIFO2X_TX_FRAMING_ERROR V_OCSPI0_OFIFO2X_TX_FRAMING_ERROR(1U) 5024 5025 #define S_OCSPI1_OFIFO2X_TX_FRAMING_ERROR 6 5026 #define V_OCSPI1_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OCSPI1_OFIFO2X_TX_FRAMING_ERROR) 5027 #define F_OCSPI1_OFIFO2X_TX_FRAMING_ERROR V_OCSPI1_OFIFO2X_TX_FRAMING_ERROR(1U) 5028 5029 #define S_IESPI_PAR_ERROR 3 5030 #define M_IESPI_PAR_ERROR 0x7 5031 #define V_IESPI_PAR_ERROR(x) ((x) << S_IESPI_PAR_ERROR) 5032 #define G_IESPI_PAR_ERROR(x) (((x) >> S_IESPI_PAR_ERROR) & M_IESPI_PAR_ERROR) 5033 5034 #define S_OCSPI_PAR_ERROR 0 5035 #define M_OCSPI_PAR_ERROR 0x7 5036 #define V_OCSPI_PAR_ERROR(x) ((x) << S_OCSPI_PAR_ERROR) 5037 #define G_OCSPI_PAR_ERROR(x) (((x) >> S_OCSPI_PAR_ERROR) & M_OCSPI_PAR_ERROR) 5038 5039 #define A_PM1_RX_INT_CAUSE 0x5dc 5040 5041 /* registers for module PM1_TX */ 5042 #define PM1_TX_BASE_ADDR 0x5e0 5043 5044 #define A_PM1_TX_CFG 0x5e0 5045 #define A_PM1_TX_MODE 0x5e4 5046 #define A_PM1_TX_STAT_CONFIG 0x5e8 5047 #define A_PM1_TX_STAT_COUNT 0x5ec 5048 #define A_PM1_TX_STAT_MSB 0x5f0 5049 #define A_PM1_TX_STAT_LSB 0x5f4 5050 #define A_PM1_TX_INT_ENABLE 0x5f8 5051 5052 #define S_ZERO_C_CMD_ERROR 18 5053 #define V_ZERO_C_CMD_ERROR(x) ((x) << S_ZERO_C_CMD_ERROR) 5054 #define F_ZERO_C_CMD_ERROR V_ZERO_C_CMD_ERROR(1U) 5055 5056 #define S_ICSPI0_FIFO2X_RX_FRAMING_ERROR 17 5057 #define V_ICSPI0_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_ICSPI0_FIFO2X_RX_FRAMING_ERROR) 5058 #define F_ICSPI0_FIFO2X_RX_FRAMING_ERROR V_ICSPI0_FIFO2X_RX_FRAMING_ERROR(1U) 5059 5060 #define S_ICSPI1_FIFO2X_RX_FRAMING_ERROR 16 5061 #define V_ICSPI1_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_ICSPI1_FIFO2X_RX_FRAMING_ERROR) 5062 #define F_ICSPI1_FIFO2X_RX_FRAMING_ERROR V_ICSPI1_FIFO2X_RX_FRAMING_ERROR(1U) 5063 5064 #define S_ICSPI0_RX_FRAMING_ERROR 15 5065 #define V_ICSPI0_RX_FRAMING_ERROR(x) ((x) << S_ICSPI0_RX_FRAMING_ERROR) 5066 #define F_ICSPI0_RX_FRAMING_ERROR V_ICSPI0_RX_FRAMING_ERROR(1U) 5067 5068 #define S_ICSPI1_RX_FRAMING_ERROR 14 5069 #define V_ICSPI1_RX_FRAMING_ERROR(x) ((x) << S_ICSPI1_RX_FRAMING_ERROR) 5070 #define F_ICSPI1_RX_FRAMING_ERROR V_ICSPI1_RX_FRAMING_ERROR(1U) 5071 5072 #define S_ICSPI0_TX_FRAMING_ERROR 13 5073 #define V_ICSPI0_TX_FRAMING_ERROR(x) ((x) << S_ICSPI0_TX_FRAMING_ERROR) 5074 #define F_ICSPI0_TX_FRAMING_ERROR V_ICSPI0_TX_FRAMING_ERROR(1U) 5075 5076 #define S_ICSPI1_TX_FRAMING_ERROR 12 5077 #define V_ICSPI1_TX_FRAMING_ERROR(x) ((x) << S_ICSPI1_TX_FRAMING_ERROR) 5078 #define F_ICSPI1_TX_FRAMING_ERROR V_ICSPI1_TX_FRAMING_ERROR(1U) 5079 5080 #define S_OESPI0_RX_FRAMING_ERROR 11 5081 #define V_OESPI0_RX_FRAMING_ERROR(x) ((x) << S_OESPI0_RX_FRAMING_ERROR) 5082 #define F_OESPI0_RX_FRAMING_ERROR V_OESPI0_RX_FRAMING_ERROR(1U) 5083 5084 #define S_OESPI1_RX_FRAMING_ERROR 10 5085 #define V_OESPI1_RX_FRAMING_ERROR(x) ((x) << S_OESPI1_RX_FRAMING_ERROR) 5086 #define F_OESPI1_RX_FRAMING_ERROR V_OESPI1_RX_FRAMING_ERROR(1U) 5087 5088 #define S_OESPI0_TX_FRAMING_ERROR 9 5089 #define V_OESPI0_TX_FRAMING_ERROR(x) ((x) << S_OESPI0_TX_FRAMING_ERROR) 5090 #define F_OESPI0_TX_FRAMING_ERROR V_OESPI0_TX_FRAMING_ERROR(1U) 5091 5092 #define S_OESPI1_TX_FRAMING_ERROR 8 5093 #define V_OESPI1_TX_FRAMING_ERROR(x) ((x) << S_OESPI1_TX_FRAMING_ERROR) 5094 #define F_OESPI1_TX_FRAMING_ERROR V_OESPI1_TX_FRAMING_ERROR(1U) 5095 5096 #define S_OESPI0_OFIFO2X_TX_FRAMING_ERROR 7 5097 #define V_OESPI0_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OESPI0_OFIFO2X_TX_FRAMING_ERROR) 5098 #define F_OESPI0_OFIFO2X_TX_FRAMING_ERROR V_OESPI0_OFIFO2X_TX_FRAMING_ERROR(1U) 5099 5100 #define S_OESPI1_OFIFO2X_TX_FRAMING_ERROR 6 5101 #define V_OESPI1_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OESPI1_OFIFO2X_TX_FRAMING_ERROR) 5102 #define F_OESPI1_OFIFO2X_TX_FRAMING_ERROR V_OESPI1_OFIFO2X_TX_FRAMING_ERROR(1U) 5103 5104 #define S_ICSPI_PAR_ERROR 3 5105 #define M_ICSPI_PAR_ERROR 0x7 5106 #define V_ICSPI_PAR_ERROR(x) ((x) << S_ICSPI_PAR_ERROR) 5107 #define G_ICSPI_PAR_ERROR(x) (((x) >> S_ICSPI_PAR_ERROR) & M_ICSPI_PAR_ERROR) 5108 5109 #define S_OESPI_PAR_ERROR 0 5110 #define M_OESPI_PAR_ERROR 0x7 5111 #define V_OESPI_PAR_ERROR(x) ((x) << S_OESPI_PAR_ERROR) 5112 #define G_OESPI_PAR_ERROR(x) (((x) >> S_OESPI_PAR_ERROR) & M_OESPI_PAR_ERROR) 5113 5114 #define A_PM1_TX_INT_CAUSE 0x5fc 5115 5116 /* registers for module MPS0 */ 5117 #define MPS0_BASE_ADDR 0x600 5118 5119 #define A_MPS_CFG 0x600 5120 5121 #define S_SGETPQID 8 5122 #define M_SGETPQID 0x7 5123 #define V_SGETPQID(x) ((x) << S_SGETPQID) 5124 #define G_SGETPQID(x) (((x) >> S_SGETPQID) & M_SGETPQID) 5125 5126 #define S_TPRXPORTSIZE 7 5127 #define V_TPRXPORTSIZE(x) ((x) << S_TPRXPORTSIZE) 5128 #define F_TPRXPORTSIZE V_TPRXPORTSIZE(1U) 5129 5130 #define S_TPTXPORT1SIZE 6 5131 #define V_TPTXPORT1SIZE(x) ((x) << S_TPTXPORT1SIZE) 5132 #define F_TPTXPORT1SIZE V_TPTXPORT1SIZE(1U) 5133 5134 #define S_TPTXPORT0SIZE 5 5135 #define V_TPTXPORT0SIZE(x) ((x) << S_TPTXPORT0SIZE) 5136 #define F_TPTXPORT0SIZE V_TPTXPORT0SIZE(1U) 5137 5138 #define S_TPRXPORTEN 4 5139 #define V_TPRXPORTEN(x) ((x) << S_TPRXPORTEN) 5140 #define F_TPRXPORTEN V_TPRXPORTEN(1U) 5141 5142 #define S_TPTXPORT1EN 3 5143 #define V_TPTXPORT1EN(x) ((x) << S_TPTXPORT1EN) 5144 #define F_TPTXPORT1EN V_TPTXPORT1EN(1U) 5145 5146 #define S_TPTXPORT0EN 2 5147 #define V_TPTXPORT0EN(x) ((x) << S_TPTXPORT0EN) 5148 #define F_TPTXPORT0EN V_TPTXPORT0EN(1U) 5149 5150 #define S_PORT1ACTIVE 1 5151 #define V_PORT1ACTIVE(x) ((x) << S_PORT1ACTIVE) 5152 #define F_PORT1ACTIVE V_PORT1ACTIVE(1U) 5153 5154 #define S_PORT0ACTIVE 0 5155 #define V_PORT0ACTIVE(x) ((x) << S_PORT0ACTIVE) 5156 #define F_PORT0ACTIVE V_PORT0ACTIVE(1U) 5157 5158 #define S_ENFORCEPKT 11 5159 #define V_ENFORCEPKT(x) ((x) << S_ENFORCEPKT) 5160 #define F_ENFORCEPKT V_ENFORCEPKT(1U) 5161 5162 #define A_MPS_DRR_CFG1 0x604 5163 5164 #define S_RLDWTTPD1 11 5165 #define M_RLDWTTPD1 0x7ff 5166 #define V_RLDWTTPD1(x) ((x) << S_RLDWTTPD1) 5167 #define G_RLDWTTPD1(x) (((x) >> S_RLDWTTPD1) & M_RLDWTTPD1) 5168 5169 #define S_RLDWTTPD0 0 5170 #define M_RLDWTTPD0 0x7ff 5171 #define V_RLDWTTPD0(x) ((x) << S_RLDWTTPD0) 5172 #define G_RLDWTTPD0(x) (((x) >> S_RLDWTTPD0) & M_RLDWTTPD0) 5173 5174 #define A_MPS_DRR_CFG2 0x608 5175 5176 #define S_RLDWTTOTAL 0 5177 #define M_RLDWTTOTAL 0xfff 5178 #define V_RLDWTTOTAL(x) ((x) << S_RLDWTTOTAL) 5179 #define G_RLDWTTOTAL(x) (((x) >> S_RLDWTTOTAL) & M_RLDWTTOTAL) 5180 5181 #define A_MPS_MCA_STATUS 0x60c 5182 5183 #define S_MCAPKTCNT 12 5184 #define M_MCAPKTCNT 0xfffff 5185 #define V_MCAPKTCNT(x) ((x) << S_MCAPKTCNT) 5186 #define G_MCAPKTCNT(x) (((x) >> S_MCAPKTCNT) & M_MCAPKTCNT) 5187 5188 #define S_MCADEPTH 0 5189 #define M_MCADEPTH 0xfff 5190 #define V_MCADEPTH(x) ((x) << S_MCADEPTH) 5191 #define G_MCADEPTH(x) (((x) >> S_MCADEPTH) & M_MCADEPTH) 5192 5193 #define A_MPS_TX0_TP_CNT 0x610 5194 5195 #define S_TX0TPDISCNT 24 5196 #define M_TX0TPDISCNT 0xff 5197 #define V_TX0TPDISCNT(x) ((x) << S_TX0TPDISCNT) 5198 #define G_TX0TPDISCNT(x) (((x) >> S_TX0TPDISCNT) & M_TX0TPDISCNT) 5199 5200 #define S_TX0TPCNT 0 5201 #define M_TX0TPCNT 0xffffff 5202 #define V_TX0TPCNT(x) ((x) << S_TX0TPCNT) 5203 #define G_TX0TPCNT(x) (((x) >> S_TX0TPCNT) & M_TX0TPCNT) 5204 5205 #define A_MPS_TX1_TP_CNT 0x614 5206 5207 #define S_TX1TPDISCNT 24 5208 #define M_TX1TPDISCNT 0xff 5209 #define V_TX1TPDISCNT(x) ((x) << S_TX1TPDISCNT) 5210 #define G_TX1TPDISCNT(x) (((x) >> S_TX1TPDISCNT) & M_TX1TPDISCNT) 5211 5212 #define S_TX1TPCNT 0 5213 #define M_TX1TPCNT 0xffffff 5214 #define V_TX1TPCNT(x) ((x) << S_TX1TPCNT) 5215 #define G_TX1TPCNT(x) (((x) >> S_TX1TPCNT) & M_TX1TPCNT) 5216 5217 #define A_MPS_RX_TP_CNT 0x618 5218 5219 #define S_RXTPDISCNT 24 5220 #define M_RXTPDISCNT 0xff 5221 #define V_RXTPDISCNT(x) ((x) << S_RXTPDISCNT) 5222 #define G_RXTPDISCNT(x) (((x) >> S_RXTPDISCNT) & M_RXTPDISCNT) 5223 5224 #define S_RXTPCNT 0 5225 #define M_RXTPCNT 0xffffff 5226 #define V_RXTPCNT(x) ((x) << S_RXTPCNT) 5227 #define G_RXTPCNT(x) (((x) >> S_RXTPCNT) & M_RXTPCNT) 5228 5229 #define A_MPS_INT_ENABLE 0x61c 5230 5231 #define S_MCAPARERRENB 6 5232 #define M_MCAPARERRENB 0x7 5233 #define V_MCAPARERRENB(x) ((x) << S_MCAPARERRENB) 5234 #define G_MCAPARERRENB(x) (((x) >> S_MCAPARERRENB) & M_MCAPARERRENB) 5235 5236 #define S_RXTPPARERRENB 4 5237 #define M_RXTPPARERRENB 0x3 5238 #define V_RXTPPARERRENB(x) ((x) << S_RXTPPARERRENB) 5239 #define G_RXTPPARERRENB(x) (((x) >> S_RXTPPARERRENB) & M_RXTPPARERRENB) 5240 5241 #define S_TX1TPPARERRENB 2 5242 #define M_TX1TPPARERRENB 0x3 5243 #define V_TX1TPPARERRENB(x) ((x) << S_TX1TPPARERRENB) 5244 #define G_TX1TPPARERRENB(x) (((x) >> S_TX1TPPARERRENB) & M_TX1TPPARERRENB) 5245 5246 #define S_TX0TPPARERRENB 0 5247 #define M_TX0TPPARERRENB 0x3 5248 #define V_TX0TPPARERRENB(x) ((x) << S_TX0TPPARERRENB) 5249 #define G_TX0TPPARERRENB(x) (((x) >> S_TX0TPPARERRENB) & M_TX0TPPARERRENB) 5250 5251 #define A_MPS_INT_CAUSE 0x620 5252 5253 #define S_MCAPARERR 6 5254 #define M_MCAPARERR 0x7 5255 #define V_MCAPARERR(x) ((x) << S_MCAPARERR) 5256 #define G_MCAPARERR(x) (((x) >> S_MCAPARERR) & M_MCAPARERR) 5257 5258 #define S_RXTPPARERR 4 5259 #define M_RXTPPARERR 0x3 5260 #define V_RXTPPARERR(x) ((x) << S_RXTPPARERR) 5261 #define G_RXTPPARERR(x) (((x) >> S_RXTPPARERR) & M_RXTPPARERR) 5262 5263 #define S_TX1TPPARERR 2 5264 #define M_TX1TPPARERR 0x3 5265 #define V_TX1TPPARERR(x) ((x) << S_TX1TPPARERR) 5266 #define G_TX1TPPARERR(x) (((x) >> S_TX1TPPARERR) & M_TX1TPPARERR) 5267 5268 #define S_TX0TPPARERR 0 5269 #define M_TX0TPPARERR 0x3 5270 #define V_TX0TPPARERR(x) ((x) << S_TX0TPPARERR) 5271 #define G_TX0TPPARERR(x) (((x) >> S_TX0TPPARERR) & M_TX0TPPARERR) 5272 5273 /* registers for module CPL_SWITCH */ 5274 #define CPL_SWITCH_BASE_ADDR 0x640 5275 5276 #define A_CPL_SWITCH_CNTRL 0x640 5277 5278 #define S_CPL_PKT_TID 8 5279 #define M_CPL_PKT_TID 0xffffff 5280 #define V_CPL_PKT_TID(x) ((x) << S_CPL_PKT_TID) 5281 #define G_CPL_PKT_TID(x) (((x) >> S_CPL_PKT_TID) & M_CPL_PKT_TID) 5282 5283 #define S_CPU_NO_3F_CIM_ENABLE 3 5284 #define V_CPU_NO_3F_CIM_ENABLE(x) ((x) << S_CPU_NO_3F_CIM_ENABLE) 5285 #define F_CPU_NO_3F_CIM_ENABLE V_CPU_NO_3F_CIM_ENABLE(1U) 5286 5287 #define S_SWITCH_TABLE_ENABLE 2 5288 #define V_SWITCH_TABLE_ENABLE(x) ((x) << S_SWITCH_TABLE_ENABLE) 5289 #define F_SWITCH_TABLE_ENABLE V_SWITCH_TABLE_ENABLE(1U) 5290 5291 #define S_SGE_ENABLE 1 5292 #define V_SGE_ENABLE(x) ((x) << S_SGE_ENABLE) 5293 #define F_SGE_ENABLE V_SGE_ENABLE(1U) 5294 5295 #define S_CIM_ENABLE 0 5296 #define V_CIM_ENABLE(x) ((x) << S_CIM_ENABLE) 5297 #define F_CIM_ENABLE V_CIM_ENABLE(1U) 5298 5299 #define A_CPL_SWITCH_TBL_IDX 0x644 5300 5301 #define S_SWITCH_TBL_IDX 0 5302 #define M_SWITCH_TBL_IDX 0xf 5303 #define V_SWITCH_TBL_IDX(x) ((x) << S_SWITCH_TBL_IDX) 5304 #define G_SWITCH_TBL_IDX(x) (((x) >> S_SWITCH_TBL_IDX) & M_SWITCH_TBL_IDX) 5305 5306 #define A_CPL_SWITCH_TBL_DATA 0x648 5307 #define A_CPL_SWITCH_ZERO_ERROR 0x64c 5308 5309 #define S_ZERO_CMD 0 5310 #define M_ZERO_CMD 0xff 5311 #define V_ZERO_CMD(x) ((x) << S_ZERO_CMD) 5312 #define G_ZERO_CMD(x) (((x) >> S_ZERO_CMD) & M_ZERO_CMD) 5313 5314 #define A_CPL_INTR_ENABLE 0x650 5315 5316 #define S_CIM_OVFL_ERROR 4 5317 #define V_CIM_OVFL_ERROR(x) ((x) << S_CIM_OVFL_ERROR) 5318 #define F_CIM_OVFL_ERROR V_CIM_OVFL_ERROR(1U) 5319 5320 #define S_TP_FRAMING_ERROR 3 5321 #define V_TP_FRAMING_ERROR(x) ((x) << S_TP_FRAMING_ERROR) 5322 #define F_TP_FRAMING_ERROR V_TP_FRAMING_ERROR(1U) 5323 5324 #define S_SGE_FRAMING_ERROR 2 5325 #define V_SGE_FRAMING_ERROR(x) ((x) << S_SGE_FRAMING_ERROR) 5326 #define F_SGE_FRAMING_ERROR V_SGE_FRAMING_ERROR(1U) 5327 5328 #define S_CIM_FRAMING_ERROR 1 5329 #define V_CIM_FRAMING_ERROR(x) ((x) << S_CIM_FRAMING_ERROR) 5330 #define F_CIM_FRAMING_ERROR V_CIM_FRAMING_ERROR(1U) 5331 5332 #define S_ZERO_SWITCH_ERROR 0 5333 #define V_ZERO_SWITCH_ERROR(x) ((x) << S_ZERO_SWITCH_ERROR) 5334 #define F_ZERO_SWITCH_ERROR V_ZERO_SWITCH_ERROR(1U) 5335 5336 #define A_CPL_INTR_CAUSE 0x654 5337 #define A_CPL_MAP_TBL_IDX 0x658 5338 5339 #define S_CPL_MAP_TBL_IDX 0 5340 #define M_CPL_MAP_TBL_IDX 0xff 5341 #define V_CPL_MAP_TBL_IDX(x) ((x) << S_CPL_MAP_TBL_IDX) 5342 #define G_CPL_MAP_TBL_IDX(x) (((x) >> S_CPL_MAP_TBL_IDX) & M_CPL_MAP_TBL_IDX) 5343 5344 #define A_CPL_MAP_TBL_DATA 0x65c 5345 5346 #define S_CPL_MAP_TBL_DATA 0 5347 #define M_CPL_MAP_TBL_DATA 0xff 5348 #define V_CPL_MAP_TBL_DATA(x) ((x) << S_CPL_MAP_TBL_DATA) 5349 #define G_CPL_MAP_TBL_DATA(x) (((x) >> S_CPL_MAP_TBL_DATA) & M_CPL_MAP_TBL_DATA) 5350 5351 /* registers for module SMB0 */ 5352 #define SMB0_BASE_ADDR 0x660 5353 5354 #define A_SMB_GLOBAL_TIME_CFG 0x660 5355 5356 #define S_LADBGWRPTR 24 5357 #define M_LADBGWRPTR 0xff 5358 #define V_LADBGWRPTR(x) ((x) << S_LADBGWRPTR) 5359 #define G_LADBGWRPTR(x) (((x) >> S_LADBGWRPTR) & M_LADBGWRPTR) 5360 5361 #define S_LADBGRDPTR 16 5362 #define M_LADBGRDPTR 0xff 5363 #define V_LADBGRDPTR(x) ((x) << S_LADBGRDPTR) 5364 #define G_LADBGRDPTR(x) (((x) >> S_LADBGRDPTR) & M_LADBGRDPTR) 5365 5366 #define S_LADBGEN 13 5367 #define V_LADBGEN(x) ((x) << S_LADBGEN) 5368 #define F_LADBGEN V_LADBGEN(1U) 5369 5370 #define S_MACROCNTCFG 8 5371 #define M_MACROCNTCFG 0x1f 5372 #define V_MACROCNTCFG(x) ((x) << S_MACROCNTCFG) 5373 #define G_MACROCNTCFG(x) (((x) >> S_MACROCNTCFG) & M_MACROCNTCFG) 5374 5375 #define S_MICROCNTCFG 0 5376 #define M_MICROCNTCFG 0xff 5377 #define V_MICROCNTCFG(x) ((x) << S_MICROCNTCFG) 5378 #define G_MICROCNTCFG(x) (((x) >> S_MICROCNTCFG) & M_MICROCNTCFG) 5379 5380 #define A_SMB_MST_TIMEOUT_CFG 0x664 5381 5382 #define S_DEBUGSELH 28 5383 #define M_DEBUGSELH 0xf 5384 #define V_DEBUGSELH(x) ((x) << S_DEBUGSELH) 5385 #define G_DEBUGSELH(x) (((x) >> S_DEBUGSELH) & M_DEBUGSELH) 5386 5387 #define S_DEBUGSELL 24 5388 #define M_DEBUGSELL 0xf 5389 #define V_DEBUGSELL(x) ((x) << S_DEBUGSELL) 5390 #define G_DEBUGSELL(x) (((x) >> S_DEBUGSELL) & M_DEBUGSELL) 5391 5392 #define S_MSTTIMEOUTCFG 0 5393 #define M_MSTTIMEOUTCFG 0xffffff 5394 #define V_MSTTIMEOUTCFG(x) ((x) << S_MSTTIMEOUTCFG) 5395 #define G_MSTTIMEOUTCFG(x) (((x) >> S_MSTTIMEOUTCFG) & M_MSTTIMEOUTCFG) 5396 5397 #define A_SMB_MST_CTL_CFG 0x668 5398 5399 #define S_MSTFIFODBG 31 5400 #define V_MSTFIFODBG(x) ((x) << S_MSTFIFODBG) 5401 #define F_MSTFIFODBG V_MSTFIFODBG(1U) 5402 5403 #define S_MSTFIFODBGCLR 30 5404 #define V_MSTFIFODBGCLR(x) ((x) << S_MSTFIFODBGCLR) 5405 #define F_MSTFIFODBGCLR V_MSTFIFODBGCLR(1U) 5406 5407 #define S_MSTRXBYTECFG 12 5408 #define M_MSTRXBYTECFG 0x3f 5409 #define V_MSTRXBYTECFG(x) ((x) << S_MSTRXBYTECFG) 5410 #define G_MSTRXBYTECFG(x) (((x) >> S_MSTRXBYTECFG) & M_MSTRXBYTECFG) 5411 5412 #define S_MSTTXBYTECFG 6 5413 #define M_MSTTXBYTECFG 0x3f 5414 #define V_MSTTXBYTECFG(x) ((x) << S_MSTTXBYTECFG) 5415 #define G_MSTTXBYTECFG(x) (((x) >> S_MSTTXBYTECFG) & M_MSTTXBYTECFG) 5416 5417 #define S_MSTRESET 1 5418 #define V_MSTRESET(x) ((x) << S_MSTRESET) 5419 #define F_MSTRESET V_MSTRESET(1U) 5420 5421 #define S_MSTCTLEN 0 5422 #define V_MSTCTLEN(x) ((x) << S_MSTCTLEN) 5423 #define F_MSTCTLEN V_MSTCTLEN(1U) 5424 5425 #define A_SMB_MST_CTL_STS 0x66c 5426 5427 #define S_MSTRXBYTECNT 12 5428 #define M_MSTRXBYTECNT 0x3f 5429 #define V_MSTRXBYTECNT(x) ((x) << S_MSTRXBYTECNT) 5430 #define G_MSTRXBYTECNT(x) (((x) >> S_MSTRXBYTECNT) & M_MSTRXBYTECNT) 5431 5432 #define S_MSTTXBYTECNT 6 5433 #define M_MSTTXBYTECNT 0x3f 5434 #define V_MSTTXBYTECNT(x) ((x) << S_MSTTXBYTECNT) 5435 #define G_MSTTXBYTECNT(x) (((x) >> S_MSTTXBYTECNT) & M_MSTTXBYTECNT) 5436 5437 #define S_MSTBUSYSTS 0 5438 #define V_MSTBUSYSTS(x) ((x) << S_MSTBUSYSTS) 5439 #define F_MSTBUSYSTS V_MSTBUSYSTS(1U) 5440 5441 #define A_SMB_MST_TX_FIFO_RDWR 0x670 5442 #define A_SMB_MST_RX_FIFO_RDWR 0x674 5443 #define A_SMB_SLV_TIMEOUT_CFG 0x678 5444 5445 #define S_SLVTIMEOUTCFG 0 5446 #define M_SLVTIMEOUTCFG 0xffffff 5447 #define V_SLVTIMEOUTCFG(x) ((x) << S_SLVTIMEOUTCFG) 5448 #define G_SLVTIMEOUTCFG(x) (((x) >> S_SLVTIMEOUTCFG) & M_SLVTIMEOUTCFG) 5449 5450 #define A_SMB_SLV_CTL_CFG 0x67c 5451 5452 #define S_SLVFIFODBG 31 5453 #define V_SLVFIFODBG(x) ((x) << S_SLVFIFODBG) 5454 #define F_SLVFIFODBG V_SLVFIFODBG(1U) 5455 5456 #define S_SLVFIFODBGCLR 30 5457 #define V_SLVFIFODBGCLR(x) ((x) << S_SLVFIFODBGCLR) 5458 #define F_SLVFIFODBGCLR V_SLVFIFODBGCLR(1U) 5459 5460 #define S_SLVADDRCFG 4 5461 #define M_SLVADDRCFG 0x7f 5462 #define V_SLVADDRCFG(x) ((x) << S_SLVADDRCFG) 5463 #define G_SLVADDRCFG(x) (((x) >> S_SLVADDRCFG) & M_SLVADDRCFG) 5464 5465 #define S_SLVALRTSET 2 5466 #define V_SLVALRTSET(x) ((x) << S_SLVALRTSET) 5467 #define F_SLVALRTSET V_SLVALRTSET(1U) 5468 5469 #define S_SLVRESET 1 5470 #define V_SLVRESET(x) ((x) << S_SLVRESET) 5471 #define F_SLVRESET V_SLVRESET(1U) 5472 5473 #define S_SLVCTLEN 0 5474 #define V_SLVCTLEN(x) ((x) << S_SLVCTLEN) 5475 #define F_SLVCTLEN V_SLVCTLEN(1U) 5476 5477 #define A_SMB_SLV_CTL_STS 0x680 5478 5479 #define S_SLVFIFOTXCNT 12 5480 #define M_SLVFIFOTXCNT 0x3f 5481 #define V_SLVFIFOTXCNT(x) ((x) << S_SLVFIFOTXCNT) 5482 #define G_SLVFIFOTXCNT(x) (((x) >> S_SLVFIFOTXCNT) & M_SLVFIFOTXCNT) 5483 5484 #define S_SLVFIFOCNT 6 5485 #define M_SLVFIFOCNT 0x3f 5486 #define V_SLVFIFOCNT(x) ((x) << S_SLVFIFOCNT) 5487 #define G_SLVFIFOCNT(x) (((x) >> S_SLVFIFOCNT) & M_SLVFIFOCNT) 5488 5489 #define S_SLVALRTSTS 2 5490 #define V_SLVALRTSTS(x) ((x) << S_SLVALRTSTS) 5491 #define F_SLVALRTSTS V_SLVALRTSTS(1U) 5492 5493 #define S_SLVBUSYSTS 0 5494 #define V_SLVBUSYSTS(x) ((x) << S_SLVBUSYSTS) 5495 #define F_SLVBUSYSTS V_SLVBUSYSTS(1U) 5496 5497 #define A_SMB_SLV_FIFO_RDWR 0x684 5498 #define A_SMB_SLV_CMD_FIFO_RDWR 0x688 5499 #define A_SMB_INT_ENABLE 0x68c 5500 5501 #define S_SLVTIMEOUTINTEN 7 5502 #define V_SLVTIMEOUTINTEN(x) ((x) << S_SLVTIMEOUTINTEN) 5503 #define F_SLVTIMEOUTINTEN V_SLVTIMEOUTINTEN(1U) 5504 5505 #define S_SLVERRINTEN 6 5506 #define V_SLVERRINTEN(x) ((x) << S_SLVERRINTEN) 5507 #define F_SLVERRINTEN V_SLVERRINTEN(1U) 5508 5509 #define S_SLVDONEINTEN 5 5510 #define V_SLVDONEINTEN(x) ((x) << S_SLVDONEINTEN) 5511 #define F_SLVDONEINTEN V_SLVDONEINTEN(1U) 5512 5513 #define S_SLVRXRDYINTEN 4 5514 #define V_SLVRXRDYINTEN(x) ((x) << S_SLVRXRDYINTEN) 5515 #define F_SLVRXRDYINTEN V_SLVRXRDYINTEN(1U) 5516 5517 #define S_MSTTIMEOUTINTEN 3 5518 #define V_MSTTIMEOUTINTEN(x) ((x) << S_MSTTIMEOUTINTEN) 5519 #define F_MSTTIMEOUTINTEN V_MSTTIMEOUTINTEN(1U) 5520 5521 #define S_MSTNACKINTEN 2 5522 #define V_MSTNACKINTEN(x) ((x) << S_MSTNACKINTEN) 5523 #define F_MSTNACKINTEN V_MSTNACKINTEN(1U) 5524 5525 #define S_MSTLOSTARBINTEN 1 5526 #define V_MSTLOSTARBINTEN(x) ((x) << S_MSTLOSTARBINTEN) 5527 #define F_MSTLOSTARBINTEN V_MSTLOSTARBINTEN(1U) 5528 5529 #define S_MSTDONEINTEN 0 5530 #define V_MSTDONEINTEN(x) ((x) << S_MSTDONEINTEN) 5531 #define F_MSTDONEINTEN V_MSTDONEINTEN(1U) 5532 5533 #define A_SMB_INT_CAUSE 0x690 5534 5535 #define S_SLVTIMEOUTINT 7 5536 #define V_SLVTIMEOUTINT(x) ((x) << S_SLVTIMEOUTINT) 5537 #define F_SLVTIMEOUTINT V_SLVTIMEOUTINT(1U) 5538 5539 #define S_SLVERRINT 6 5540 #define V_SLVERRINT(x) ((x) << S_SLVERRINT) 5541 #define F_SLVERRINT V_SLVERRINT(1U) 5542 5543 #define S_SLVDONEINT 5 5544 #define V_SLVDONEINT(x) ((x) << S_SLVDONEINT) 5545 #define F_SLVDONEINT V_SLVDONEINT(1U) 5546 5547 #define S_SLVRXRDYINT 4 5548 #define V_SLVRXRDYINT(x) ((x) << S_SLVRXRDYINT) 5549 #define F_SLVRXRDYINT V_SLVRXRDYINT(1U) 5550 5551 #define S_MSTTIMEOUTINT 3 5552 #define V_MSTTIMEOUTINT(x) ((x) << S_MSTTIMEOUTINT) 5553 #define F_MSTTIMEOUTINT V_MSTTIMEOUTINT(1U) 5554 5555 #define S_MSTNACKINT 2 5556 #define V_MSTNACKINT(x) ((x) << S_MSTNACKINT) 5557 #define F_MSTNACKINT V_MSTNACKINT(1U) 5558 5559 #define S_MSTLOSTARBINT 1 5560 #define V_MSTLOSTARBINT(x) ((x) << S_MSTLOSTARBINT) 5561 #define F_MSTLOSTARBINT V_MSTLOSTARBINT(1U) 5562 5563 #define S_MSTDONEINT 0 5564 #define V_MSTDONEINT(x) ((x) << S_MSTDONEINT) 5565 #define F_MSTDONEINT V_MSTDONEINT(1U) 5566 5567 #define A_SMB_DEBUG_DATA 0x694 5568 5569 #define S_DEBUGDATAH 16 5570 #define M_DEBUGDATAH 0xffff 5571 #define V_DEBUGDATAH(x) ((x) << S_DEBUGDATAH) 5572 #define G_DEBUGDATAH(x) (((x) >> S_DEBUGDATAH) & M_DEBUGDATAH) 5573 5574 #define S_DEBUGDATAL 0 5575 #define M_DEBUGDATAL 0xffff 5576 #define V_DEBUGDATAL(x) ((x) << S_DEBUGDATAL) 5577 #define G_DEBUGDATAL(x) (((x) >> S_DEBUGDATAL) & M_DEBUGDATAL) 5578 5579 #define A_SMB_DEBUG_LA 0x69c 5580 5581 #define S_DEBUGLAREQADDR 0 5582 #define M_DEBUGLAREQADDR 0x3ff 5583 #define V_DEBUGLAREQADDR(x) ((x) << S_DEBUGLAREQADDR) 5584 #define G_DEBUGLAREQADDR(x) (((x) >> S_DEBUGLAREQADDR) & M_DEBUGLAREQADDR) 5585 5586 /* registers for module I2CM0 */ 5587 #define I2CM0_BASE_ADDR 0x6a0 5588 5589 #define A_I2C_CFG 0x6a0 5590 5591 #define S_I2C_CLKDIV 0 5592 #define M_I2C_CLKDIV 0xfff 5593 #define V_I2C_CLKDIV(x) ((x) << S_I2C_CLKDIV) 5594 #define G_I2C_CLKDIV(x) (((x) >> S_I2C_CLKDIV) & M_I2C_CLKDIV) 5595 5596 #define A_I2C_DATA 0x6a4 5597 #define A_I2C_OP 0x6a8 5598 5599 #define S_ACK 30 5600 #define V_ACK(x) ((x) << S_ACK) 5601 #define F_ACK V_ACK(1U) 5602 5603 #define S_I2C_CONT 1 5604 #define V_I2C_CONT(x) ((x) << S_I2C_CONT) 5605 #define F_I2C_CONT V_I2C_CONT(1U) 5606 5607 /* registers for module MI1 */ 5608 #define MI1_BASE_ADDR 0x6b0 5609 5610 #define A_MI1_CFG 0x6b0 5611 5612 #define S_CLKDIV 5 5613 #define M_CLKDIV 0xff 5614 #define V_CLKDIV(x) ((x) << S_CLKDIV) 5615 #define G_CLKDIV(x) (((x) >> S_CLKDIV) & M_CLKDIV) 5616 5617 #define S_ST 3 5618 #define M_ST 0x3 5619 #define V_ST(x) ((x) << S_ST) 5620 #define G_ST(x) (((x) >> S_ST) & M_ST) 5621 5622 #define S_PREEN 2 5623 #define V_PREEN(x) ((x) << S_PREEN) 5624 #define F_PREEN V_PREEN(1U) 5625 5626 #define S_MDIINV 1 5627 #define V_MDIINV(x) ((x) << S_MDIINV) 5628 #define F_MDIINV V_MDIINV(1U) 5629 5630 #define S_MDIEN 0 5631 #define V_MDIEN(x) ((x) << S_MDIEN) 5632 #define F_MDIEN V_MDIEN(1U) 5633 5634 #define A_MI1_ADDR 0x6b4 5635 5636 #define S_PHYADDR 5 5637 #define M_PHYADDR 0x1f 5638 #define V_PHYADDR(x) ((x) << S_PHYADDR) 5639 #define G_PHYADDR(x) (((x) >> S_PHYADDR) & M_PHYADDR) 5640 5641 #define S_REGADDR 0 5642 #define M_REGADDR 0x1f 5643 #define V_REGADDR(x) ((x) << S_REGADDR) 5644 #define G_REGADDR(x) (((x) >> S_REGADDR) & M_REGADDR) 5645 5646 #define A_MI1_DATA 0x6b8 5647 5648 #define S_MDI_DATA 0 5649 #define M_MDI_DATA 0xffff 5650 #define V_MDI_DATA(x) ((x) << S_MDI_DATA) 5651 #define G_MDI_DATA(x) (((x) >> S_MDI_DATA) & M_MDI_DATA) 5652 5653 #define A_MI1_OP 0x6bc 5654 5655 #define S_INC 2 5656 #define V_INC(x) ((x) << S_INC) 5657 #define F_INC V_INC(1U) 5658 5659 #define S_MDI_OP 0 5660 #define M_MDI_OP 0x3 5661 #define V_MDI_OP(x) ((x) << S_MDI_OP) 5662 #define G_MDI_OP(x) (((x) >> S_MDI_OP) & M_MDI_OP) 5663 5664 /* registers for module JM1 */ 5665 #define JM1_BASE_ADDR 0x6c0 5666 5667 #define A_JM_CFG 0x6c0 5668 5669 #define S_JM_CLKDIV 2 5670 #define M_JM_CLKDIV 0xff 5671 #define V_JM_CLKDIV(x) ((x) << S_JM_CLKDIV) 5672 #define G_JM_CLKDIV(x) (((x) >> S_JM_CLKDIV) & M_JM_CLKDIV) 5673 5674 #define S_TRST 1 5675 #define V_TRST(x) ((x) << S_TRST) 5676 #define F_TRST V_TRST(1U) 5677 5678 #define S_EN 0 5679 #define V_EN(x) ((x) << S_EN) 5680 #define F_EN V_EN(1U) 5681 5682 #define A_JM_MODE 0x6c4 5683 #define A_JM_DATA 0x6c8 5684 #define A_JM_OP 0x6cc 5685 5686 #define S_CNT 0 5687 #define M_CNT 0x1f 5688 #define V_CNT(x) ((x) << S_CNT) 5689 #define G_CNT(x) (((x) >> S_CNT) & M_CNT) 5690 5691 /* registers for module SF1 */ 5692 #define SF1_BASE_ADDR 0x6d8 5693 5694 #define A_SF_DATA 0x6d8 5695 #define A_SF_OP 0x6dc 5696 5697 #define S_BYTECNT 1 5698 #define M_BYTECNT 0x3 5699 #define V_BYTECNT(x) ((x) << S_BYTECNT) 5700 #define G_BYTECNT(x) (((x) >> S_BYTECNT) & M_BYTECNT) 5701 5702 /* registers for module PL3 */ 5703 #define PL3_BASE_ADDR 0x6e0 5704 5705 #define A_PL_INT_ENABLE0 0x6e0 5706 5707 #define S_EXT 24 5708 #define V_EXT(x) ((x) << S_EXT) 5709 #define F_EXT V_EXT(1U) 5710 5711 #define S_T3DBG 23 5712 #define V_T3DBG(x) ((x) << S_T3DBG) 5713 #define F_T3DBG V_T3DBG(1U) 5714 5715 #define S_XGMAC0_1 20 5716 #define V_XGMAC0_1(x) ((x) << S_XGMAC0_1) 5717 #define F_XGMAC0_1 V_XGMAC0_1(1U) 5718 5719 #define S_XGMAC0_0 19 5720 #define V_XGMAC0_0(x) ((x) << S_XGMAC0_0) 5721 #define F_XGMAC0_0 V_XGMAC0_0(1U) 5722 5723 #define S_MC5A 18 5724 #define V_MC5A(x) ((x) << S_MC5A) 5725 #define F_MC5A V_MC5A(1U) 5726 5727 #define S_SF1 17 5728 #define V_SF1(x) ((x) << S_SF1) 5729 #define F_SF1 V_SF1(1U) 5730 5731 #define S_SMB0 15 5732 #define V_SMB0(x) ((x) << S_SMB0) 5733 #define F_SMB0 V_SMB0(1U) 5734 5735 #define S_I2CM0 14 5736 #define V_I2CM0(x) ((x) << S_I2CM0) 5737 #define F_I2CM0 V_I2CM0(1U) 5738 5739 #define S_MI1 13 5740 #define V_MI1(x) ((x) << S_MI1) 5741 #define F_MI1 V_MI1(1U) 5742 5743 #define S_CPL_SWITCH 12 5744 #define V_CPL_SWITCH(x) ((x) << S_CPL_SWITCH) 5745 #define F_CPL_SWITCH V_CPL_SWITCH(1U) 5746 5747 #define S_MPS0 11 5748 #define V_MPS0(x) ((x) << S_MPS0) 5749 #define F_MPS0 V_MPS0(1U) 5750 5751 #define S_PM1_TX 10 5752 #define V_PM1_TX(x) ((x) << S_PM1_TX) 5753 #define F_PM1_TX V_PM1_TX(1U) 5754 5755 #define S_PM1_RX 9 5756 #define V_PM1_RX(x) ((x) << S_PM1_RX) 5757 #define F_PM1_RX V_PM1_RX(1U) 5758 5759 #define S_ULP2_TX 8 5760 #define V_ULP2_TX(x) ((x) << S_ULP2_TX) 5761 #define F_ULP2_TX V_ULP2_TX(1U) 5762 5763 #define S_ULP2_RX 7 5764 #define V_ULP2_RX(x) ((x) << S_ULP2_RX) 5765 #define F_ULP2_RX V_ULP2_RX(1U) 5766 5767 #define S_TP1 6 5768 #define V_TP1(x) ((x) << S_TP1) 5769 #define F_TP1 V_TP1(1U) 5770 5771 #define S_CIM 5 5772 #define V_CIM(x) ((x) << S_CIM) 5773 #define F_CIM V_CIM(1U) 5774 5775 #define S_MC7_CM 4 5776 #define V_MC7_CM(x) ((x) << S_MC7_CM) 5777 #define F_MC7_CM V_MC7_CM(1U) 5778 5779 #define S_MC7_PMTX 3 5780 #define V_MC7_PMTX(x) ((x) << S_MC7_PMTX) 5781 #define F_MC7_PMTX V_MC7_PMTX(1U) 5782 5783 #define S_MC7_PMRX 2 5784 #define V_MC7_PMRX(x) ((x) << S_MC7_PMRX) 5785 #define F_MC7_PMRX V_MC7_PMRX(1U) 5786 5787 #define S_PCIM0 1 5788 #define V_PCIM0(x) ((x) << S_PCIM0) 5789 #define F_PCIM0 V_PCIM0(1U) 5790 5791 #define S_SGE3 0 5792 #define V_SGE3(x) ((x) << S_SGE3) 5793 #define F_SGE3 V_SGE3(1U) 5794 5795 #define S_SW 25 5796 #define V_SW(x) ((x) << S_SW) 5797 #define F_SW V_SW(1U) 5798 5799 #define A_PL_INT_CAUSE0 0x6e4 5800 #define A_PL_INT_ENABLE1 0x6e8 5801 #define A_PL_INT_CAUSE1 0x6ec 5802 #define A_PL_RST 0x6f0 5803 5804 #define S_CRSTWRM 1 5805 #define V_CRSTWRM(x) ((x) << S_CRSTWRM) 5806 #define F_CRSTWRM V_CRSTWRM(1U) 5807 5808 #define S_SWINT1 3 5809 #define V_SWINT1(x) ((x) << S_SWINT1) 5810 #define F_SWINT1 V_SWINT1(1U) 5811 5812 #define S_SWINT0 2 5813 #define V_SWINT0(x) ((x) << S_SWINT0) 5814 #define F_SWINT0 V_SWINT0(1U) 5815 5816 #define A_PL_REV 0x6f4 5817 5818 #define S_REV 0 5819 #define M_REV 0xf 5820 #define V_REV(x) ((x) << S_REV) 5821 #define G_REV(x) (((x) >> S_REV) & M_REV) 5822 5823 #define A_PL_CLI 0x6f8 5824 #define A_PL_LCK 0x6fc 5825 5826 #define S_LCK 0 5827 #define M_LCK 0x3 5828 #define V_LCK(x) ((x) << S_LCK) 5829 #define G_LCK(x) (((x) >> S_LCK) & M_LCK) 5830 5831 /* registers for module MC5A */ 5832 #define MC5A_BASE_ADDR 0x700 5833 5834 #define A_MC5_BUF_CONFIG 0x700 5835 5836 #define S_TERM300_240 31 5837 #define V_TERM300_240(x) ((x) << S_TERM300_240) 5838 #define F_TERM300_240 V_TERM300_240(1U) 5839 5840 #define S_MC5_TERM150 30 5841 #define V_MC5_TERM150(x) ((x) << S_MC5_TERM150) 5842 #define F_MC5_TERM150 V_MC5_TERM150(1U) 5843 5844 #define S_TERM60 29 5845 #define V_TERM60(x) ((x) << S_TERM60) 5846 #define F_TERM60 V_TERM60(1U) 5847 5848 #define S_GDDRIII 28 5849 #define V_GDDRIII(x) ((x) << S_GDDRIII) 5850 #define F_GDDRIII V_GDDRIII(1U) 5851 5852 #define S_GDDRII 27 5853 #define V_GDDRII(x) ((x) << S_GDDRII) 5854 #define F_GDDRII V_GDDRII(1U) 5855 5856 #define S_GDDRI 26 5857 #define V_GDDRI(x) ((x) << S_GDDRI) 5858 #define F_GDDRI V_GDDRI(1U) 5859 5860 #define S_READ 25 5861 #define V_READ(x) ((x) << S_READ) 5862 #define F_READ V_READ(1U) 5863 5864 #define S_CAL_IMP_UPD 23 5865 #define V_CAL_IMP_UPD(x) ((x) << S_CAL_IMP_UPD) 5866 #define F_CAL_IMP_UPD V_CAL_IMP_UPD(1U) 5867 5868 #define S_CAL_BUSY 22 5869 #define V_CAL_BUSY(x) ((x) << S_CAL_BUSY) 5870 #define F_CAL_BUSY V_CAL_BUSY(1U) 5871 5872 #define S_CAL_ERROR 21 5873 #define V_CAL_ERROR(x) ((x) << S_CAL_ERROR) 5874 #define F_CAL_ERROR V_CAL_ERROR(1U) 5875 5876 #define S_SGL_CAL_EN 20 5877 #define V_SGL_CAL_EN(x) ((x) << S_SGL_CAL_EN) 5878 #define F_SGL_CAL_EN V_SGL_CAL_EN(1U) 5879 5880 #define S_IMP_UPD_MODE 19 5881 #define V_IMP_UPD_MODE(x) ((x) << S_IMP_UPD_MODE) 5882 #define F_IMP_UPD_MODE V_IMP_UPD_MODE(1U) 5883 5884 #define S_IMP_SEL 18 5885 #define V_IMP_SEL(x) ((x) << S_IMP_SEL) 5886 #define F_IMP_SEL V_IMP_SEL(1U) 5887 5888 #define S_MAN_PU 15 5889 #define M_MAN_PU 0x7 5890 #define V_MAN_PU(x) ((x) << S_MAN_PU) 5891 #define G_MAN_PU(x) (((x) >> S_MAN_PU) & M_MAN_PU) 5892 5893 #define S_MAN_PD 12 5894 #define M_MAN_PD 0x7 5895 #define V_MAN_PD(x) ((x) << S_MAN_PD) 5896 #define G_MAN_PD(x) (((x) >> S_MAN_PD) & M_MAN_PD) 5897 5898 #define S_CAL_PU 9 5899 #define M_CAL_PU 0x7 5900 #define V_CAL_PU(x) ((x) << S_CAL_PU) 5901 #define G_CAL_PU(x) (((x) >> S_CAL_PU) & M_CAL_PU) 5902 5903 #define S_CAL_PD 6 5904 #define M_CAL_PD 0x7 5905 #define V_CAL_PD(x) ((x) << S_CAL_PD) 5906 #define G_CAL_PD(x) (((x) >> S_CAL_PD) & M_CAL_PD) 5907 5908 #define S_SET_PU 3 5909 #define M_SET_PU 0x7 5910 #define V_SET_PU(x) ((x) << S_SET_PU) 5911 #define G_SET_PU(x) (((x) >> S_SET_PU) & M_SET_PU) 5912 5913 #define S_SET_PD 0 5914 #define M_SET_PD 0x7 5915 #define V_SET_PD(x) ((x) << S_SET_PD) 5916 #define G_SET_PD(x) (((x) >> S_SET_PD) & M_SET_PD) 5917 5918 #define S_IMP_SET_UPDATE 24 5919 #define V_IMP_SET_UPDATE(x) ((x) << S_IMP_SET_UPDATE) 5920 #define F_IMP_SET_UPDATE V_IMP_SET_UPDATE(1U) 5921 5922 #define S_CAL_UPDATE 23 5923 #define V_CAL_UPDATE(x) ((x) << S_CAL_UPDATE) 5924 #define F_CAL_UPDATE V_CAL_UPDATE(1U) 5925 5926 #define A_MC5_DB_CONFIG 0x704 5927 5928 #define S_TMCFGWRLOCK 31 5929 #define V_TMCFGWRLOCK(x) ((x) << S_TMCFGWRLOCK) 5930 #define F_TMCFGWRLOCK V_TMCFGWRLOCK(1U) 5931 5932 #define S_TMTYPEHI 30 5933 #define V_TMTYPEHI(x) ((x) << S_TMTYPEHI) 5934 #define F_TMTYPEHI V_TMTYPEHI(1U) 5935 5936 #define S_TMPARTSIZE 28 5937 #define M_TMPARTSIZE 0x3 5938 #define V_TMPARTSIZE(x) ((x) << S_TMPARTSIZE) 5939 #define G_TMPARTSIZE(x) (((x) >> S_TMPARTSIZE) & M_TMPARTSIZE) 5940 5941 #define S_TMTYPE 26 5942 #define M_TMTYPE 0x3 5943 #define V_TMTYPE(x) ((x) << S_TMTYPE) 5944 #define G_TMTYPE(x) (((x) >> S_TMTYPE) & M_TMTYPE) 5945 5946 #define S_TMPARTCOUNT 24 5947 #define M_TMPARTCOUNT 0x3 5948 #define V_TMPARTCOUNT(x) ((x) << S_TMPARTCOUNT) 5949 #define G_TMPARTCOUNT(x) (((x) >> S_TMPARTCOUNT) & M_TMPARTCOUNT) 5950 5951 #define S_NLIP 18 5952 #define M_NLIP 0x3f 5953 #define V_NLIP(x) ((x) << S_NLIP) 5954 #define G_NLIP(x) (((x) >> S_NLIP) & M_NLIP) 5955 5956 #define S_COMPEN 17 5957 #define V_COMPEN(x) ((x) << S_COMPEN) 5958 #define F_COMPEN V_COMPEN(1U) 5959 5960 #define S_BUILD 16 5961 #define V_BUILD(x) ((x) << S_BUILD) 5962 #define F_BUILD V_BUILD(1U) 5963 5964 #define S_TM_IO_PDOWN 9 5965 #define V_TM_IO_PDOWN(x) ((x) << S_TM_IO_PDOWN) 5966 #define F_TM_IO_PDOWN V_TM_IO_PDOWN(1U) 5967 5968 #define S_SYNMODE 7 5969 #define M_SYNMODE 0x3 5970 #define V_SYNMODE(x) ((x) << S_SYNMODE) 5971 #define G_SYNMODE(x) (((x) >> S_SYNMODE) & M_SYNMODE) 5972 5973 #define S_PRTYEN 6 5974 #define V_PRTYEN(x) ((x) << S_PRTYEN) 5975 #define F_PRTYEN V_PRTYEN(1U) 5976 5977 #define S_MBUSEN 5 5978 #define V_MBUSEN(x) ((x) << S_MBUSEN) 5979 #define F_MBUSEN V_MBUSEN(1U) 5980 5981 #define S_DBGIEN 4 5982 #define V_DBGIEN(x) ((x) << S_DBGIEN) 5983 #define F_DBGIEN V_DBGIEN(1U) 5984 5985 #define S_TMRDY 2 5986 #define V_TMRDY(x) ((x) << S_TMRDY) 5987 #define F_TMRDY V_TMRDY(1U) 5988 5989 #define S_TMRST 1 5990 #define V_TMRST(x) ((x) << S_TMRST) 5991 #define F_TMRST V_TMRST(1U) 5992 5993 #define S_TMMODE 0 5994 #define V_TMMODE(x) ((x) << S_TMMODE) 5995 #define F_TMMODE V_TMMODE(1U) 5996 5997 #define S_FILTEREN 11 5998 #define V_FILTEREN(x) ((x) << S_FILTEREN) 5999 #define F_FILTEREN V_FILTEREN(1U) 6000 6001 #define S_CLIPUPDATE 10 6002 #define V_CLIPUPDATE(x) ((x) << S_CLIPUPDATE) 6003 #define F_CLIPUPDATE V_CLIPUPDATE(1U) 6004 6005 #define S_TCMCFGOVR 3 6006 #define V_TCMCFGOVR(x) ((x) << S_TCMCFGOVR) 6007 #define F_TCMCFGOVR V_TCMCFGOVR(1U) 6008 6009 #define A_MC5_MISC 0x708 6010 6011 #define S_LIP_CMP_UNAVAILABLE 0 6012 #define M_LIP_CMP_UNAVAILABLE 0xf 6013 #define V_LIP_CMP_UNAVAILABLE(x) ((x) << S_LIP_CMP_UNAVAILABLE) 6014 #define G_LIP_CMP_UNAVAILABLE(x) (((x) >> S_LIP_CMP_UNAVAILABLE) & M_LIP_CMP_UNAVAILABLE) 6015 6016 #define A_MC5_DB_ROUTING_TABLE_INDEX 0x70c 6017 6018 #define S_RTINDX 0 6019 #define M_RTINDX 0x3fffff 6020 #define V_RTINDX(x) ((x) << S_RTINDX) 6021 #define G_RTINDX(x) (((x) >> S_RTINDX) & M_RTINDX) 6022 6023 #define A_MC5_DB_FILTER_TABLE 0x710 6024 #define A_MC5_DB_SERVER_INDEX 0x714 6025 6026 #define S_SRINDX 0 6027 #define M_SRINDX 0x3fffff 6028 #define V_SRINDX(x) ((x) << S_SRINDX) 6029 #define G_SRINDX(x) (((x) >> S_SRINDX) & M_SRINDX) 6030 6031 #define A_MC5_DB_LIP_RAM_ADDR 0x718 6032 6033 #define S_RAMWR 8 6034 #define V_RAMWR(x) ((x) << S_RAMWR) 6035 #define F_RAMWR V_RAMWR(1U) 6036 6037 #define S_RAMADDR 0 6038 #define M_RAMADDR 0x3f 6039 #define V_RAMADDR(x) ((x) << S_RAMADDR) 6040 #define G_RAMADDR(x) (((x) >> S_RAMADDR) & M_RAMADDR) 6041 6042 #define A_MC5_DB_LIP_RAM_DATA 0x71c 6043 #define A_MC5_DB_RSP_LATENCY 0x720 6044 6045 #define S_RDLAT 16 6046 #define M_RDLAT 0x1f 6047 #define V_RDLAT(x) ((x) << S_RDLAT) 6048 #define G_RDLAT(x) (((x) >> S_RDLAT) & M_RDLAT) 6049 6050 #define S_LRNLAT 8 6051 #define M_LRNLAT 0x1f 6052 #define V_LRNLAT(x) ((x) << S_LRNLAT) 6053 #define G_LRNLAT(x) (((x) >> S_LRNLAT) & M_LRNLAT) 6054 6055 #define S_SRCHLAT 0 6056 #define M_SRCHLAT 0x1f 6057 #define V_SRCHLAT(x) ((x) << S_SRCHLAT) 6058 #define G_SRCHLAT(x) (((x) >> S_SRCHLAT) & M_SRCHLAT) 6059 6060 #define A_MC5_DB_PARITY_LATENCY 0x724 6061 6062 #define S_PARLAT 0 6063 #define M_PARLAT 0xf 6064 #define V_PARLAT(x) ((x) << S_PARLAT) 6065 #define G_PARLAT(x) (((x) >> S_PARLAT) & M_PARLAT) 6066 6067 #define A_MC5_DB_WR_LRN_VERIFY 0x728 6068 6069 #define S_VWVEREN 2 6070 #define V_VWVEREN(x) ((x) << S_VWVEREN) 6071 #define F_VWVEREN V_VWVEREN(1U) 6072 6073 #define S_LRNVEREN 1 6074 #define V_LRNVEREN(x) ((x) << S_LRNVEREN) 6075 #define F_LRNVEREN V_LRNVEREN(1U) 6076 6077 #define S_POVEREN 0 6078 #define V_POVEREN(x) ((x) << S_POVEREN) 6079 #define F_POVEREN V_POVEREN(1U) 6080 6081 #define A_MC5_DB_PART_ID_INDEX 0x72c 6082 6083 #define S_IDINDEX 0 6084 #define M_IDINDEX 0xf 6085 #define V_IDINDEX(x) ((x) << S_IDINDEX) 6086 #define G_IDINDEX(x) (((x) >> S_IDINDEX) & M_IDINDEX) 6087 6088 #define A_MC5_DB_RESET_MAX 0x730 6089 6090 #define S_RSTMAX 0 6091 #define M_RSTMAX 0xf 6092 #define V_RSTMAX(x) ((x) << S_RSTMAX) 6093 #define G_RSTMAX(x) (((x) >> S_RSTMAX) & M_RSTMAX) 6094 6095 #define A_MC5_DB_ACT_CNT 0x734 6096 6097 #define S_ACTCNT 0 6098 #define M_ACTCNT 0xfffff 6099 #define V_ACTCNT(x) ((x) << S_ACTCNT) 6100 #define G_ACTCNT(x) (((x) >> S_ACTCNT) & M_ACTCNT) 6101 6102 #define A_MC5_DB_CLIP_MAP 0x738 6103 6104 #define S_CLIPMAPOP 31 6105 #define V_CLIPMAPOP(x) ((x) << S_CLIPMAPOP) 6106 #define F_CLIPMAPOP V_CLIPMAPOP(1U) 6107 6108 #define S_CLIPMAPVAL 16 6109 #define M_CLIPMAPVAL 0x3f 6110 #define V_CLIPMAPVAL(x) ((x) << S_CLIPMAPVAL) 6111 #define G_CLIPMAPVAL(x) (((x) >> S_CLIPMAPVAL) & M_CLIPMAPVAL) 6112 6113 #define S_CLIPMAPADDR 0 6114 #define M_CLIPMAPADDR 0x3f 6115 #define V_CLIPMAPADDR(x) ((x) << S_CLIPMAPADDR) 6116 #define G_CLIPMAPADDR(x) (((x) >> S_CLIPMAPADDR) & M_CLIPMAPADDR) 6117 6118 #define A_MC5_DB_INT_ENABLE 0x740 6119 6120 #define S_MSGSEL 28 6121 #define M_MSGSEL 0xf 6122 #define V_MSGSEL(x) ((x) << S_MSGSEL) 6123 #define G_MSGSEL(x) (((x) >> S_MSGSEL) & M_MSGSEL) 6124 6125 #define S_DELACTEMPTY 18 6126 #define V_DELACTEMPTY(x) ((x) << S_DELACTEMPTY) 6127 #define F_DELACTEMPTY V_DELACTEMPTY(1U) 6128 6129 #define S_DISPQPARERR 17 6130 #define V_DISPQPARERR(x) ((x) << S_DISPQPARERR) 6131 #define F_DISPQPARERR V_DISPQPARERR(1U) 6132 6133 #define S_REQQPARERR 16 6134 #define V_REQQPARERR(x) ((x) << S_REQQPARERR) 6135 #define F_REQQPARERR V_REQQPARERR(1U) 6136 6137 #define S_UNKNOWNCMD 15 6138 #define V_UNKNOWNCMD(x) ((x) << S_UNKNOWNCMD) 6139 #define F_UNKNOWNCMD V_UNKNOWNCMD(1U) 6140 6141 #define S_SYNCOOKIEOFF 11 6142 #define V_SYNCOOKIEOFF(x) ((x) << S_SYNCOOKIEOFF) 6143 #define F_SYNCOOKIEOFF V_SYNCOOKIEOFF(1U) 6144 6145 #define S_SYNCOOKIEBAD 10 6146 #define V_SYNCOOKIEBAD(x) ((x) << S_SYNCOOKIEBAD) 6147 #define F_SYNCOOKIEBAD V_SYNCOOKIEBAD(1U) 6148 6149 #define S_SYNCOOKIE 9 6150 #define V_SYNCOOKIE(x) ((x) << S_SYNCOOKIE) 6151 #define F_SYNCOOKIE V_SYNCOOKIE(1U) 6152 6153 #define S_NFASRCHFAIL 8 6154 #define V_NFASRCHFAIL(x) ((x) << S_NFASRCHFAIL) 6155 #define F_NFASRCHFAIL V_NFASRCHFAIL(1U) 6156 6157 #define S_ACTRGNFULL 7 6158 #define V_ACTRGNFULL(x) ((x) << S_ACTRGNFULL) 6159 #define F_ACTRGNFULL V_ACTRGNFULL(1U) 6160 6161 #define S_PARITYERR 6 6162 #define V_PARITYERR(x) ((x) << S_PARITYERR) 6163 #define F_PARITYERR V_PARITYERR(1U) 6164 6165 #define S_LIPMISS 5 6166 #define V_LIPMISS(x) ((x) << S_LIPMISS) 6167 #define F_LIPMISS V_LIPMISS(1U) 6168 6169 #define S_LIP0 4 6170 #define V_LIP0(x) ((x) << S_LIP0) 6171 #define F_LIP0 V_LIP0(1U) 6172 6173 #define S_MISS 3 6174 #define V_MISS(x) ((x) << S_MISS) 6175 #define F_MISS V_MISS(1U) 6176 6177 #define S_ROUTINGHIT 2 6178 #define V_ROUTINGHIT(x) ((x) << S_ROUTINGHIT) 6179 #define F_ROUTINGHIT V_ROUTINGHIT(1U) 6180 6181 #define S_ACTIVEHIT 1 6182 #define V_ACTIVEHIT(x) ((x) << S_ACTIVEHIT) 6183 #define F_ACTIVEHIT V_ACTIVEHIT(1U) 6184 6185 #define S_ACTIVEOUTHIT 0 6186 #define V_ACTIVEOUTHIT(x) ((x) << S_ACTIVEOUTHIT) 6187 #define F_ACTIVEOUTHIT V_ACTIVEOUTHIT(1U) 6188 6189 #define A_MC5_DB_INT_CAUSE 0x744 6190 #define A_MC5_DB_INT_TID 0x748 6191 6192 #define S_INTTID 0 6193 #define M_INTTID 0xfffff 6194 #define V_INTTID(x) ((x) << S_INTTID) 6195 #define G_INTTID(x) (((x) >> S_INTTID) & M_INTTID) 6196 6197 #define A_MC5_DB_INT_PTID 0x74c 6198 6199 #define S_INTPTID 0 6200 #define M_INTPTID 0xfffff 6201 #define V_INTPTID(x) ((x) << S_INTPTID) 6202 #define G_INTPTID(x) (((x) >> S_INTPTID) & M_INTPTID) 6203 6204 #define A_MC5_DB_DBGI_CONFIG 0x774 6205 6206 #define S_WRREQSIZE 22 6207 #define M_WRREQSIZE 0x3ff 6208 #define V_WRREQSIZE(x) ((x) << S_WRREQSIZE) 6209 #define G_WRREQSIZE(x) (((x) >> S_WRREQSIZE) & M_WRREQSIZE) 6210 6211 #define S_SADRSEL 4 6212 #define V_SADRSEL(x) ((x) << S_SADRSEL) 6213 #define F_SADRSEL V_SADRSEL(1U) 6214 6215 #define S_CMDMODE 0 6216 #define M_CMDMODE 0x7 6217 #define V_CMDMODE(x) ((x) << S_CMDMODE) 6218 #define G_CMDMODE(x) (((x) >> S_CMDMODE) & M_CMDMODE) 6219 6220 #define A_MC5_DB_DBGI_REQ_CMD 0x778 6221 6222 #define S_MBUSCMD 0 6223 #define M_MBUSCMD 0xf 6224 #define V_MBUSCMD(x) ((x) << S_MBUSCMD) 6225 #define G_MBUSCMD(x) (((x) >> S_MBUSCMD) & M_MBUSCMD) 6226 6227 #define S_IDTCMDHI 11 6228 #define M_IDTCMDHI 0x7 6229 #define V_IDTCMDHI(x) ((x) << S_IDTCMDHI) 6230 #define G_IDTCMDHI(x) (((x) >> S_IDTCMDHI) & M_IDTCMDHI) 6231 6232 #define S_IDTCMDLO 0 6233 #define M_IDTCMDLO 0xf 6234 #define V_IDTCMDLO(x) ((x) << S_IDTCMDLO) 6235 #define G_IDTCMDLO(x) (((x) >> S_IDTCMDLO) & M_IDTCMDLO) 6236 6237 #define S_IDTCMD 0 6238 #define M_IDTCMD 0xfffff 6239 #define V_IDTCMD(x) ((x) << S_IDTCMD) 6240 #define G_IDTCMD(x) (((x) >> S_IDTCMD) & M_IDTCMD) 6241 6242 #define S_LCMDB 16 6243 #define M_LCMDB 0x7ff 6244 #define V_LCMDB(x) ((x) << S_LCMDB) 6245 #define G_LCMDB(x) (((x) >> S_LCMDB) & M_LCMDB) 6246 6247 #define S_LCMDA 0 6248 #define M_LCMDA 0x7ff 6249 #define V_LCMDA(x) ((x) << S_LCMDA) 6250 #define G_LCMDA(x) (((x) >> S_LCMDA) & M_LCMDA) 6251 6252 #define A_MC5_DB_DBGI_REQ_ADDR0 0x77c 6253 #define A_MC5_DB_DBGI_REQ_ADDR1 0x780 6254 #define A_MC5_DB_DBGI_REQ_ADDR2 0x784 6255 6256 #define S_DBGIREQADRHI 0 6257 #define M_DBGIREQADRHI 0xff 6258 #define V_DBGIREQADRHI(x) ((x) << S_DBGIREQADRHI) 6259 #define G_DBGIREQADRHI(x) (((x) >> S_DBGIREQADRHI) & M_DBGIREQADRHI) 6260 6261 #define A_MC5_DB_DBGI_REQ_DATA0 0x788 6262 #define A_MC5_DB_DBGI_REQ_DATA1 0x78c 6263 #define A_MC5_DB_DBGI_REQ_DATA2 0x790 6264 #define A_MC5_DB_DBGI_REQ_DATA3 0x794 6265 #define A_MC5_DB_DBGI_REQ_DATA4 0x798 6266 6267 #define S_DBGIREQDATA4 0 6268 #define M_DBGIREQDATA4 0xffff 6269 #define V_DBGIREQDATA4(x) ((x) << S_DBGIREQDATA4) 6270 #define G_DBGIREQDATA4(x) (((x) >> S_DBGIREQDATA4) & M_DBGIREQDATA4) 6271 6272 #define A_MC5_DB_DBGI_REQ_MASK0 0x79c 6273 #define A_MC5_DB_DBGI_REQ_MASK1 0x7a0 6274 #define A_MC5_DB_DBGI_REQ_MASK2 0x7a4 6275 #define A_MC5_DB_DBGI_REQ_MASK3 0x7a8 6276 #define A_MC5_DB_DBGI_REQ_MASK4 0x7ac 6277 6278 #define S_DBGIREQMSK4 0 6279 #define M_DBGIREQMSK4 0xffff 6280 #define V_DBGIREQMSK4(x) ((x) << S_DBGIREQMSK4) 6281 #define G_DBGIREQMSK4(x) (((x) >> S_DBGIREQMSK4) & M_DBGIREQMSK4) 6282 6283 #define A_MC5_DB_DBGI_RSP_STATUS 0x7b0 6284 6285 #define S_DBGIRSPMSG 8 6286 #define M_DBGIRSPMSG 0xf 6287 #define V_DBGIRSPMSG(x) ((x) << S_DBGIRSPMSG) 6288 #define G_DBGIRSPMSG(x) (((x) >> S_DBGIRSPMSG) & M_DBGIRSPMSG) 6289 6290 #define S_DBGIRSPMSGVLD 2 6291 #define V_DBGIRSPMSGVLD(x) ((x) << S_DBGIRSPMSGVLD) 6292 #define F_DBGIRSPMSGVLD V_DBGIRSPMSGVLD(1U) 6293 6294 #define S_DBGIRSPHIT 1 6295 #define V_DBGIRSPHIT(x) ((x) << S_DBGIRSPHIT) 6296 #define F_DBGIRSPHIT V_DBGIRSPHIT(1U) 6297 6298 #define S_DBGIRSPVALID 0 6299 #define V_DBGIRSPVALID(x) ((x) << S_DBGIRSPVALID) 6300 #define F_DBGIRSPVALID V_DBGIRSPVALID(1U) 6301 6302 #define A_MC5_DB_DBGI_RSP_DATA0 0x7b4 6303 #define A_MC5_DB_DBGI_RSP_DATA1 0x7b8 6304 #define A_MC5_DB_DBGI_RSP_DATA2 0x7bc 6305 #define A_MC5_DB_DBGI_RSP_DATA3 0x7c0 6306 #define A_MC5_DB_DBGI_RSP_DATA4 0x7c4 6307 6308 #define S_DBGIRSPDATA3 0 6309 #define M_DBGIRSPDATA3 0xffff 6310 #define V_DBGIRSPDATA3(x) ((x) << S_DBGIRSPDATA3) 6311 #define G_DBGIRSPDATA3(x) (((x) >> S_DBGIRSPDATA3) & M_DBGIRSPDATA3) 6312 6313 #define A_MC5_DB_DBGI_RSP_LAST_CMD 0x7c8 6314 6315 #define S_LASTCMDB 16 6316 #define M_LASTCMDB 0x7ff 6317 #define V_LASTCMDB(x) ((x) << S_LASTCMDB) 6318 #define G_LASTCMDB(x) (((x) >> S_LASTCMDB) & M_LASTCMDB) 6319 6320 #define S_LASTCMDA 0 6321 #define M_LASTCMDA 0x7ff 6322 #define V_LASTCMDA(x) ((x) << S_LASTCMDA) 6323 #define G_LASTCMDA(x) (((x) >> S_LASTCMDA) & M_LASTCMDA) 6324 6325 #define A_MC5_DB_POPEN_DATA_WR_CMD 0x7cc 6326 6327 #define S_PO_DWR 0 6328 #define M_PO_DWR 0xfffff 6329 #define V_PO_DWR(x) ((x) << S_PO_DWR) 6330 #define G_PO_DWR(x) (((x) >> S_PO_DWR) & M_PO_DWR) 6331 6332 #define A_MC5_DB_POPEN_MASK_WR_CMD 0x7d0 6333 6334 #define S_PO_MWR 0 6335 #define M_PO_MWR 0xfffff 6336 #define V_PO_MWR(x) ((x) << S_PO_MWR) 6337 #define G_PO_MWR(x) (((x) >> S_PO_MWR) & M_PO_MWR) 6338 6339 #define A_MC5_DB_AOPEN_SRCH_CMD 0x7d4 6340 6341 #define S_AO_SRCH 0 6342 #define M_AO_SRCH 0xfffff 6343 #define V_AO_SRCH(x) ((x) << S_AO_SRCH) 6344 #define G_AO_SRCH(x) (((x) >> S_AO_SRCH) & M_AO_SRCH) 6345 6346 #define A_MC5_DB_AOPEN_LRN_CMD 0x7d8 6347 6348 #define S_AO_LRN 0 6349 #define M_AO_LRN 0xfffff 6350 #define V_AO_LRN(x) ((x) << S_AO_LRN) 6351 #define G_AO_LRN(x) (((x) >> S_AO_LRN) & M_AO_LRN) 6352 6353 #define A_MC5_DB_SYN_SRCH_CMD 0x7dc 6354 6355 #define S_SYN_SRCH 0 6356 #define M_SYN_SRCH 0xfffff 6357 #define V_SYN_SRCH(x) ((x) << S_SYN_SRCH) 6358 #define G_SYN_SRCH(x) (((x) >> S_SYN_SRCH) & M_SYN_SRCH) 6359 6360 #define A_MC5_DB_SYN_LRN_CMD 0x7e0 6361 6362 #define S_SYN_LRN 0 6363 #define M_SYN_LRN 0xfffff 6364 #define V_SYN_LRN(x) ((x) << S_SYN_LRN) 6365 #define G_SYN_LRN(x) (((x) >> S_SYN_LRN) & M_SYN_LRN) 6366 6367 #define A_MC5_DB_ACK_SRCH_CMD 0x7e4 6368 6369 #define S_ACK_SRCH 0 6370 #define M_ACK_SRCH 0xfffff 6371 #define V_ACK_SRCH(x) ((x) << S_ACK_SRCH) 6372 #define G_ACK_SRCH(x) (((x) >> S_ACK_SRCH) & M_ACK_SRCH) 6373 6374 #define A_MC5_DB_ACK_LRN_CMD 0x7e8 6375 6376 #define S_ACK_LRN 0 6377 #define M_ACK_LRN 0xfffff 6378 #define V_ACK_LRN(x) ((x) << S_ACK_LRN) 6379 #define G_ACK_LRN(x) (((x) >> S_ACK_LRN) & M_ACK_LRN) 6380 6381 #define A_MC5_DB_ILOOKUP_CMD 0x7ec 6382 6383 #define S_I_SRCH 0 6384 #define M_I_SRCH 0xfffff 6385 #define V_I_SRCH(x) ((x) << S_I_SRCH) 6386 #define G_I_SRCH(x) (((x) >> S_I_SRCH) & M_I_SRCH) 6387 6388 #define A_MC5_DB_ELOOKUP_CMD 0x7f0 6389 6390 #define S_E_SRCH 0 6391 #define M_E_SRCH 0xfffff 6392 #define V_E_SRCH(x) ((x) << S_E_SRCH) 6393 #define G_E_SRCH(x) (((x) >> S_E_SRCH) & M_E_SRCH) 6394 6395 #define A_MC5_DB_DATA_WRITE_CMD 0x7f4 6396 6397 #define S_WRITE 0 6398 #define M_WRITE 0xfffff 6399 #define V_WRITE(x) ((x) << S_WRITE) 6400 #define G_WRITE(x) (((x) >> S_WRITE) & M_WRITE) 6401 6402 #define A_MC5_DB_DATA_READ_CMD 0x7f8 6403 6404 #define S_READCMD 0 6405 #define M_READCMD 0xfffff 6406 #define V_READCMD(x) ((x) << S_READCMD) 6407 #define G_READCMD(x) (((x) >> S_READCMD) & M_READCMD) 6408 6409 #define A_MC5_DB_MASK_WRITE_CMD 0x7fc 6410 6411 #define S_MASKWR 0 6412 #define M_MASKWR 0xffff 6413 #define V_MASKWR(x) ((x) << S_MASKWR) 6414 #define G_MASKWR(x) (((x) >> S_MASKWR) & M_MASKWR) 6415 6416 /* registers for module XGMAC0_0 */ 6417 #define XGMAC0_0_BASE_ADDR 0x800 6418 6419 #define A_XGM_TX_CTRL 0x800 6420 6421 #define S_SENDPAUSE 2 6422 #define V_SENDPAUSE(x) ((x) << S_SENDPAUSE) 6423 #define F_SENDPAUSE V_SENDPAUSE(1U) 6424 6425 #define S_SENDZEROPAUSE 1 6426 #define V_SENDZEROPAUSE(x) ((x) << S_SENDZEROPAUSE) 6427 #define F_SENDZEROPAUSE V_SENDZEROPAUSE(1U) 6428 6429 #define S_TXEN 0 6430 #define V_TXEN(x) ((x) << S_TXEN) 6431 #define F_TXEN V_TXEN(1U) 6432 6433 #define A_XGM_TX_CFG 0x804 6434 6435 #define S_CFGCLKSPEED 2 6436 #define M_CFGCLKSPEED 0x7 6437 #define V_CFGCLKSPEED(x) ((x) << S_CFGCLKSPEED) 6438 #define G_CFGCLKSPEED(x) (((x) >> S_CFGCLKSPEED) & M_CFGCLKSPEED) 6439 6440 #define S_STRETCHMODE 1 6441 #define V_STRETCHMODE(x) ((x) << S_STRETCHMODE) 6442 #define F_STRETCHMODE V_STRETCHMODE(1U) 6443 6444 #define S_TXPAUSEEN 0 6445 #define V_TXPAUSEEN(x) ((x) << S_TXPAUSEEN) 6446 #define F_TXPAUSEEN V_TXPAUSEEN(1U) 6447 6448 #define A_XGM_TX_PAUSE_QUANTA 0x808 6449 6450 #define S_TXPAUSEQUANTA 0 6451 #define M_TXPAUSEQUANTA 0xffff 6452 #define V_TXPAUSEQUANTA(x) ((x) << S_TXPAUSEQUANTA) 6453 #define G_TXPAUSEQUANTA(x) (((x) >> S_TXPAUSEQUANTA) & M_TXPAUSEQUANTA) 6454 6455 #define A_XGM_RX_CTRL 0x80c 6456 6457 #define S_RXEN 0 6458 #define V_RXEN(x) ((x) << S_RXEN) 6459 #define F_RXEN V_RXEN(1U) 6460 6461 #define A_XGM_RX_CFG 0x810 6462 6463 #define S_CON802_3PREAMBLE 12 6464 #define V_CON802_3PREAMBLE(x) ((x) << S_CON802_3PREAMBLE) 6465 #define F_CON802_3PREAMBLE V_CON802_3PREAMBLE(1U) 6466 6467 #define S_ENNON802_3PREAMBLE 11 6468 #define V_ENNON802_3PREAMBLE(x) ((x) << S_ENNON802_3PREAMBLE) 6469 #define F_ENNON802_3PREAMBLE V_ENNON802_3PREAMBLE(1U) 6470 6471 #define S_COPYPREAMBLE 10 6472 #define V_COPYPREAMBLE(x) ((x) << S_COPYPREAMBLE) 6473 #define F_COPYPREAMBLE V_COPYPREAMBLE(1U) 6474 6475 #define S_DISPAUSEFRAMES 9 6476 #define V_DISPAUSEFRAMES(x) ((x) << S_DISPAUSEFRAMES) 6477 #define F_DISPAUSEFRAMES V_DISPAUSEFRAMES(1U) 6478 6479 #define S_EN1536BFRAMES 8 6480 #define V_EN1536BFRAMES(x) ((x) << S_EN1536BFRAMES) 6481 #define F_EN1536BFRAMES V_EN1536BFRAMES(1U) 6482 6483 #define S_ENJUMBO 7 6484 #define V_ENJUMBO(x) ((x) << S_ENJUMBO) 6485 #define F_ENJUMBO V_ENJUMBO(1U) 6486 6487 #define S_RMFCS 6 6488 #define V_RMFCS(x) ((x) << S_RMFCS) 6489 #define F_RMFCS V_RMFCS(1U) 6490 6491 #define S_DISNONVLAN 5 6492 #define V_DISNONVLAN(x) ((x) << S_DISNONVLAN) 6493 #define F_DISNONVLAN V_DISNONVLAN(1U) 6494 6495 #define S_ENEXTMATCH 4 6496 #define V_ENEXTMATCH(x) ((x) << S_ENEXTMATCH) 6497 #define F_ENEXTMATCH V_ENEXTMATCH(1U) 6498 6499 #define S_ENHASHUCAST 3 6500 #define V_ENHASHUCAST(x) ((x) << S_ENHASHUCAST) 6501 #define F_ENHASHUCAST V_ENHASHUCAST(1U) 6502 6503 #define S_ENHASHMCAST 2 6504 #define V_ENHASHMCAST(x) ((x) << S_ENHASHMCAST) 6505 #define F_ENHASHMCAST V_ENHASHMCAST(1U) 6506 6507 #define S_DISBCAST 1 6508 #define V_DISBCAST(x) ((x) << S_DISBCAST) 6509 #define F_DISBCAST V_DISBCAST(1U) 6510 6511 #define S_COPYALLFRAMES 0 6512 #define V_COPYALLFRAMES(x) ((x) << S_COPYALLFRAMES) 6513 #define F_COPYALLFRAMES V_COPYALLFRAMES(1U) 6514 6515 #define A_XGM_RX_HASH_LOW 0x814 6516 #define A_XGM_RX_HASH_HIGH 0x818 6517 #define A_XGM_RX_EXACT_MATCH_LOW_1 0x81c 6518 #define A_XGM_RX_EXACT_MATCH_HIGH_1 0x820 6519 6520 #define S_ADDRESS_HIGH 0 6521 #define M_ADDRESS_HIGH 0xffff 6522 #define V_ADDRESS_HIGH(x) ((x) << S_ADDRESS_HIGH) 6523 #define G_ADDRESS_HIGH(x) (((x) >> S_ADDRESS_HIGH) & M_ADDRESS_HIGH) 6524 6525 #define A_XGM_RX_EXACT_MATCH_LOW_2 0x824 6526 #define A_XGM_RX_EXACT_MATCH_HIGH_2 0x828 6527 #define A_XGM_RX_EXACT_MATCH_LOW_3 0x82c 6528 #define A_XGM_RX_EXACT_MATCH_HIGH_3 0x830 6529 #define A_XGM_RX_EXACT_MATCH_LOW_4 0x834 6530 #define A_XGM_RX_EXACT_MATCH_HIGH_4 0x838 6531 #define A_XGM_RX_EXACT_MATCH_LOW_5 0x83c 6532 #define A_XGM_RX_EXACT_MATCH_HIGH_5 0x840 6533 #define A_XGM_RX_EXACT_MATCH_LOW_6 0x844 6534 #define A_XGM_RX_EXACT_MATCH_HIGH_6 0x848 6535 #define A_XGM_RX_EXACT_MATCH_LOW_7 0x84c 6536 #define A_XGM_RX_EXACT_MATCH_HIGH_7 0x850 6537 #define A_XGM_RX_EXACT_MATCH_LOW_8 0x854 6538 #define A_XGM_RX_EXACT_MATCH_HIGH_8 0x858 6539 #define A_XGM_RX_TYPE_MATCH_1 0x85c 6540 6541 #define S_ENTYPEMATCH 31 6542 #define V_ENTYPEMATCH(x) ((x) << S_ENTYPEMATCH) 6543 #define F_ENTYPEMATCH V_ENTYPEMATCH(1U) 6544 6545 #define S_TYPE 0 6546 #define M_TYPE 0xffff 6547 #define V_TYPE(x) ((x) << S_TYPE) 6548 #define G_TYPE(x) (((x) >> S_TYPE) & M_TYPE) 6549 6550 #define A_XGM_RX_TYPE_MATCH_2 0x860 6551 #define A_XGM_RX_TYPE_MATCH_3 0x864 6552 #define A_XGM_RX_TYPE_MATCH_4 0x868 6553 #define A_XGM_INT_STATUS 0x86c 6554 6555 #define S_XGMIIEXTINT 10 6556 #define V_XGMIIEXTINT(x) ((x) << S_XGMIIEXTINT) 6557 #define F_XGMIIEXTINT V_XGMIIEXTINT(1U) 6558 6559 #define S_LINKFAULTCHANGE 9 6560 #define V_LINKFAULTCHANGE(x) ((x) << S_LINKFAULTCHANGE) 6561 #define F_LINKFAULTCHANGE V_LINKFAULTCHANGE(1U) 6562 6563 #define S_PHYFRAMECOMPLETE 8 6564 #define V_PHYFRAMECOMPLETE(x) ((x) << S_PHYFRAMECOMPLETE) 6565 #define F_PHYFRAMECOMPLETE V_PHYFRAMECOMPLETE(1U) 6566 6567 #define S_PAUSEFRAMETXMT 7 6568 #define V_PAUSEFRAMETXMT(x) ((x) << S_PAUSEFRAMETXMT) 6569 #define F_PAUSEFRAMETXMT V_PAUSEFRAMETXMT(1U) 6570 6571 #define S_PAUSECNTRTIMEOUT 6 6572 #define V_PAUSECNTRTIMEOUT(x) ((x) << S_PAUSECNTRTIMEOUT) 6573 #define F_PAUSECNTRTIMEOUT V_PAUSECNTRTIMEOUT(1U) 6574 6575 #define S_NON0PAUSERCVD 5 6576 #define V_NON0PAUSERCVD(x) ((x) << S_NON0PAUSERCVD) 6577 #define F_NON0PAUSERCVD V_NON0PAUSERCVD(1U) 6578 6579 #define S_STATOFLOW 4 6580 #define V_STATOFLOW(x) ((x) << S_STATOFLOW) 6581 #define F_STATOFLOW V_STATOFLOW(1U) 6582 6583 #define S_TXERRFIFO 3 6584 #define V_TXERRFIFO(x) ((x) << S_TXERRFIFO) 6585 #define F_TXERRFIFO V_TXERRFIFO(1U) 6586 6587 #define S_TXUFLOW 2 6588 #define V_TXUFLOW(x) ((x) << S_TXUFLOW) 6589 #define F_TXUFLOW V_TXUFLOW(1U) 6590 6591 #define S_FRAMETXMT 1 6592 #define V_FRAMETXMT(x) ((x) << S_FRAMETXMT) 6593 #define F_FRAMETXMT V_FRAMETXMT(1U) 6594 6595 #define S_FRAMERCVD 0 6596 #define V_FRAMERCVD(x) ((x) << S_FRAMERCVD) 6597 #define F_FRAMERCVD V_FRAMERCVD(1U) 6598 6599 #define A_XGM_XGM_INT_MASK 0x870 6600 #define A_XGM_XGM_INT_ENABLE 0x874 6601 #define A_XGM_XGM_INT_DISABLE 0x878 6602 #define A_XGM_TX_PAUSE_TIMER 0x87c 6603 6604 #define S_CURPAUSETIMER 0 6605 #define M_CURPAUSETIMER 0xffff 6606 #define V_CURPAUSETIMER(x) ((x) << S_CURPAUSETIMER) 6607 #define G_CURPAUSETIMER(x) (((x) >> S_CURPAUSETIMER) & M_CURPAUSETIMER) 6608 6609 #define A_XGM_STAT_CTRL 0x880 6610 6611 #define S_READSNPSHOT 4 6612 #define V_READSNPSHOT(x) ((x) << S_READSNPSHOT) 6613 #define F_READSNPSHOT V_READSNPSHOT(1U) 6614 6615 #define S_TAKESNPSHOT 3 6616 #define V_TAKESNPSHOT(x) ((x) << S_TAKESNPSHOT) 6617 #define F_TAKESNPSHOT V_TAKESNPSHOT(1U) 6618 6619 #define S_CLRSTATS 2 6620 #define V_CLRSTATS(x) ((x) << S_CLRSTATS) 6621 #define F_CLRSTATS V_CLRSTATS(1U) 6622 6623 #define S_INCRSTATS 1 6624 #define V_INCRSTATS(x) ((x) << S_INCRSTATS) 6625 #define F_INCRSTATS V_INCRSTATS(1U) 6626 6627 #define S_ENTESTMODEWR 0 6628 #define V_ENTESTMODEWR(x) ((x) << S_ENTESTMODEWR) 6629 #define F_ENTESTMODEWR V_ENTESTMODEWR(1U) 6630 6631 #define A_XGM_RXFIFO_CFG 0x884 6632 6633 #define S_RXFIFOPAUSEHWM 17 6634 #define M_RXFIFOPAUSEHWM 0xfff 6635 #define V_RXFIFOPAUSEHWM(x) ((x) << S_RXFIFOPAUSEHWM) 6636 #define G_RXFIFOPAUSEHWM(x) (((x) >> S_RXFIFOPAUSEHWM) & M_RXFIFOPAUSEHWM) 6637 6638 #define S_RXFIFOPAUSELWM 5 6639 #define M_RXFIFOPAUSELWM 0xfff 6640 #define V_RXFIFOPAUSELWM(x) ((x) << S_RXFIFOPAUSELWM) 6641 #define G_RXFIFOPAUSELWM(x) (((x) >> S_RXFIFOPAUSELWM) & M_RXFIFOPAUSELWM) 6642 6643 #define S_FORCEDPAUSE 4 6644 #define V_FORCEDPAUSE(x) ((x) << S_FORCEDPAUSE) 6645 #define F_FORCEDPAUSE V_FORCEDPAUSE(1U) 6646 6647 #define S_EXTERNLOOPBACK 3 6648 #define V_EXTERNLOOPBACK(x) ((x) << S_EXTERNLOOPBACK) 6649 #define F_EXTERNLOOPBACK V_EXTERNLOOPBACK(1U) 6650 6651 #define S_RXBYTESWAP 2 6652 #define V_RXBYTESWAP(x) ((x) << S_RXBYTESWAP) 6653 #define F_RXBYTESWAP V_RXBYTESWAP(1U) 6654 6655 #define S_RXSTRFRWRD 1 6656 #define V_RXSTRFRWRD(x) ((x) << S_RXSTRFRWRD) 6657 #define F_RXSTRFRWRD V_RXSTRFRWRD(1U) 6658 6659 #define S_DISERRFRAMES 0 6660 #define V_DISERRFRAMES(x) ((x) << S_DISERRFRAMES) 6661 #define F_DISERRFRAMES V_DISERRFRAMES(1U) 6662 6663 #define A_XGM_TXFIFO_CFG 0x888 6664 6665 #define S_TXIPG 13 6666 #define M_TXIPG 0xff 6667 #define V_TXIPG(x) ((x) << S_TXIPG) 6668 #define G_TXIPG(x) (((x) >> S_TXIPG) & M_TXIPG) 6669 6670 #define S_TXFIFOTHRESH 4 6671 #define M_TXFIFOTHRESH 0x1ff 6672 #define V_TXFIFOTHRESH(x) ((x) << S_TXFIFOTHRESH) 6673 #define G_TXFIFOTHRESH(x) (((x) >> S_TXFIFOTHRESH) & M_TXFIFOTHRESH) 6674 6675 #define S_INTERNLOOPBACK 3 6676 #define V_INTERNLOOPBACK(x) ((x) << S_INTERNLOOPBACK) 6677 #define F_INTERNLOOPBACK V_INTERNLOOPBACK(1U) 6678 6679 #define S_TXBYTESWAP 2 6680 #define V_TXBYTESWAP(x) ((x) << S_TXBYTESWAP) 6681 #define F_TXBYTESWAP V_TXBYTESWAP(1U) 6682 6683 #define S_DISCRC 1 6684 #define V_DISCRC(x) ((x) << S_DISCRC) 6685 #define F_DISCRC V_DISCRC(1U) 6686 6687 #define S_DISPREAMBLE 0 6688 #define V_DISPREAMBLE(x) ((x) << S_DISPREAMBLE) 6689 #define F_DISPREAMBLE V_DISPREAMBLE(1U) 6690 6691 #define S_ENDROPPKT 21 6692 #define V_ENDROPPKT(x) ((x) << S_ENDROPPKT) 6693 #define F_ENDROPPKT V_ENDROPPKT(1U) 6694 6695 #define A_XGM_SLOW_TIMER 0x88c 6696 6697 #define S_PAUSESLOWTIMEREN 31 6698 #define V_PAUSESLOWTIMEREN(x) ((x) << S_PAUSESLOWTIMEREN) 6699 #define F_PAUSESLOWTIMEREN V_PAUSESLOWTIMEREN(1U) 6700 6701 #define S_PAUSESLOWTIMER 0 6702 #define M_PAUSESLOWTIMER 0xfffff 6703 #define V_PAUSESLOWTIMER(x) ((x) << S_PAUSESLOWTIMER) 6704 #define G_PAUSESLOWTIMER(x) (((x) >> S_PAUSESLOWTIMER) & M_PAUSESLOWTIMER) 6705 6706 #define A_XGM_SERDES_CTRL 0x890 6707 6708 #define S_SERDESEN 25 6709 #define V_SERDESEN(x) ((x) << S_SERDESEN) 6710 #define F_SERDESEN V_SERDESEN(1U) 6711 6712 #define S_SERDESRESET_ 24 6713 #define V_SERDESRESET_(x) ((x) << S_SERDESRESET_) 6714 #define F_SERDESRESET_ V_SERDESRESET_(1U) 6715 6716 #define S_CMURANGE 21 6717 #define M_CMURANGE 0x7 6718 #define V_CMURANGE(x) ((x) << S_CMURANGE) 6719 #define G_CMURANGE(x) (((x) >> S_CMURANGE) & M_CMURANGE) 6720 6721 #define S_BGENB 20 6722 #define V_BGENB(x) ((x) << S_BGENB) 6723 #define F_BGENB V_BGENB(1U) 6724 6725 #define S_ENSKPDROP 19 6726 #define V_ENSKPDROP(x) ((x) << S_ENSKPDROP) 6727 #define F_ENSKPDROP V_ENSKPDROP(1U) 6728 6729 #define S_ENCOMMA 18 6730 #define V_ENCOMMA(x) ((x) << S_ENCOMMA) 6731 #define F_ENCOMMA V_ENCOMMA(1U) 6732 6733 #define S_EN8B10B 17 6734 #define V_EN8B10B(x) ((x) << S_EN8B10B) 6735 #define F_EN8B10B V_EN8B10B(1U) 6736 6737 #define S_ENELBUF 16 6738 #define V_ENELBUF(x) ((x) << S_ENELBUF) 6739 #define F_ENELBUF V_ENELBUF(1U) 6740 6741 #define S_GAIN 11 6742 #define M_GAIN 0x1f 6743 #define V_GAIN(x) ((x) << S_GAIN) 6744 #define G_GAIN(x) (((x) >> S_GAIN) & M_GAIN) 6745 6746 #define S_BANDGAP 7 6747 #define M_BANDGAP 0xf 6748 #define V_BANDGAP(x) ((x) << S_BANDGAP) 6749 #define G_BANDGAP(x) (((x) >> S_BANDGAP) & M_BANDGAP) 6750 6751 #define S_LPBKEN 5 6752 #define M_LPBKEN 0x3 6753 #define V_LPBKEN(x) ((x) << S_LPBKEN) 6754 #define G_LPBKEN(x) (((x) >> S_LPBKEN) & M_LPBKEN) 6755 6756 #define S_RXENABLE 4 6757 #define V_RXENABLE(x) ((x) << S_RXENABLE) 6758 #define F_RXENABLE V_RXENABLE(1U) 6759 6760 #define S_TXENABLE 3 6761 #define V_TXENABLE(x) ((x) << S_TXENABLE) 6762 #define F_TXENABLE V_TXENABLE(1U) 6763 6764 #define A_XGM_PAUSE_TIMER 0x890 6765 6766 #define S_PAUSETIMER 0 6767 #define M_PAUSETIMER 0xfffff 6768 #define V_PAUSETIMER(x) ((x) << S_PAUSETIMER) 6769 #define G_PAUSETIMER(x) (((x) >> S_PAUSETIMER) & M_PAUSETIMER) 6770 6771 #define A_XGM_XAUI_PCS_TEST 0x894 6772 6773 #define S_TESTPATTERN 1 6774 #define M_TESTPATTERN 0x3 6775 #define V_TESTPATTERN(x) ((x) << S_TESTPATTERN) 6776 #define G_TESTPATTERN(x) (((x) >> S_TESTPATTERN) & M_TESTPATTERN) 6777 6778 #define S_ENTEST 0 6779 #define V_ENTEST(x) ((x) << S_ENTEST) 6780 #define F_ENTEST V_ENTEST(1U) 6781 6782 #define A_XGM_RGMII_CTRL 0x898 6783 6784 #define S_PHALIGNFIFOTHRESH 1 6785 #define M_PHALIGNFIFOTHRESH 0x3 6786 #define V_PHALIGNFIFOTHRESH(x) ((x) << S_PHALIGNFIFOTHRESH) 6787 #define G_PHALIGNFIFOTHRESH(x) (((x) >> S_PHALIGNFIFOTHRESH) & M_PHALIGNFIFOTHRESH) 6788 6789 #define S_TXCLK90SHIFT 0 6790 #define V_TXCLK90SHIFT(x) ((x) << S_TXCLK90SHIFT) 6791 #define F_TXCLK90SHIFT V_TXCLK90SHIFT(1U) 6792 6793 #define A_XGM_RGMII_IMP 0x89c 6794 6795 #define S_XGM_IMPSETUPDATE 6 6796 #define V_XGM_IMPSETUPDATE(x) ((x) << S_XGM_IMPSETUPDATE) 6797 #define F_XGM_IMPSETUPDATE V_XGM_IMPSETUPDATE(1U) 6798 6799 #define S_RGMIIIMPPD 3 6800 #define M_RGMIIIMPPD 0x7 6801 #define V_RGMIIIMPPD(x) ((x) << S_RGMIIIMPPD) 6802 #define G_RGMIIIMPPD(x) (((x) >> S_RGMIIIMPPD) & M_RGMIIIMPPD) 6803 6804 #define S_RGMIIIMPPU 0 6805 #define M_RGMIIIMPPU 0x7 6806 #define V_RGMIIIMPPU(x) ((x) << S_RGMIIIMPPU) 6807 #define G_RGMIIIMPPU(x) (((x) >> S_RGMIIIMPPU) & M_RGMIIIMPPU) 6808 6809 #define S_CALRESET 8 6810 #define V_CALRESET(x) ((x) << S_CALRESET) 6811 #define F_CALRESET V_CALRESET(1U) 6812 6813 #define S_CALUPDATE 7 6814 #define V_CALUPDATE(x) ((x) << S_CALUPDATE) 6815 #define F_CALUPDATE V_CALUPDATE(1U) 6816 6817 #define A_XGM_XAUI_IMP 0x8a0 6818 6819 #define S_XGM_CALFAULT 29 6820 #define V_XGM_CALFAULT(x) ((x) << S_XGM_CALFAULT) 6821 #define F_XGM_CALFAULT V_XGM_CALFAULT(1U) 6822 6823 #define S_CALIMP 24 6824 #define M_CALIMP 0x1f 6825 #define V_CALIMP(x) ((x) << S_CALIMP) 6826 #define G_CALIMP(x) (((x) >> S_CALIMP) & M_CALIMP) 6827 6828 #define S_XAUIIMP 0 6829 #define M_XAUIIMP 0x7 6830 #define V_XAUIIMP(x) ((x) << S_XAUIIMP) 6831 #define G_XAUIIMP(x) (((x) >> S_XAUIIMP) & M_XAUIIMP) 6832 6833 #define A_XGM_SERDES_BIST 0x8a4 6834 6835 #define S_BISTDONE 28 6836 #define M_BISTDONE 0xf 6837 #define V_BISTDONE(x) ((x) << S_BISTDONE) 6838 #define G_BISTDONE(x) (((x) >> S_BISTDONE) & M_BISTDONE) 6839 6840 #define S_BISTCYCLETHRESH 3 6841 #define M_BISTCYCLETHRESH 0x1ffff 6842 #define V_BISTCYCLETHRESH(x) ((x) << S_BISTCYCLETHRESH) 6843 #define G_BISTCYCLETHRESH(x) (((x) >> S_BISTCYCLETHRESH) & M_BISTCYCLETHRESH) 6844 6845 #define A_XGM_RX_MAX_PKT_SIZE 0x8a8 6846 6847 #define S_RXMAXPKTSIZE 0 6848 #define M_RXMAXPKTSIZE 0x3fff 6849 #define V_RXMAXPKTSIZE(x) ((x) << S_RXMAXPKTSIZE) 6850 #define G_RXMAXPKTSIZE(x) (((x) >> S_RXMAXPKTSIZE) & M_RXMAXPKTSIZE) 6851 6852 #define A_XGM_RESET_CTRL 0x8ac 6853 6854 #define S_XG2G_RESET_ 3 6855 #define V_XG2G_RESET_(x) ((x) << S_XG2G_RESET_) 6856 #define F_XG2G_RESET_ V_XG2G_RESET_(1U) 6857 6858 #define S_RGMII_RESET_ 2 6859 #define V_RGMII_RESET_(x) ((x) << S_RGMII_RESET_) 6860 #define F_RGMII_RESET_ V_RGMII_RESET_(1U) 6861 6862 #define S_PCS_RESET_ 1 6863 #define V_PCS_RESET_(x) ((x) << S_PCS_RESET_) 6864 #define F_PCS_RESET_ V_PCS_RESET_(1U) 6865 6866 #define S_MAC_RESET_ 0 6867 #define V_MAC_RESET_(x) ((x) << S_MAC_RESET_) 6868 #define F_MAC_RESET_ V_MAC_RESET_(1U) 6869 6870 #define A_XGM_XAUI1G_CTRL 0x8b0 6871 6872 #define S_XAUI1GLINKID 0 6873 #define M_XAUI1GLINKID 0x3 6874 #define V_XAUI1GLINKID(x) ((x) << S_XAUI1GLINKID) 6875 #define G_XAUI1GLINKID(x) (((x) >> S_XAUI1GLINKID) & M_XAUI1GLINKID) 6876 6877 #define A_XGM_SERDES_LANE_CTRL 0x8b4 6878 6879 #define S_LANEREVERSAL 8 6880 #define V_LANEREVERSAL(x) ((x) << S_LANEREVERSAL) 6881 #define F_LANEREVERSAL V_LANEREVERSAL(1U) 6882 6883 #define S_TXPOLARITY 4 6884 #define M_TXPOLARITY 0xf 6885 #define V_TXPOLARITY(x) ((x) << S_TXPOLARITY) 6886 #define G_TXPOLARITY(x) (((x) >> S_TXPOLARITY) & M_TXPOLARITY) 6887 6888 #define S_RXPOLARITY 0 6889 #define M_RXPOLARITY 0xf 6890 #define V_RXPOLARITY(x) ((x) << S_RXPOLARITY) 6891 #define G_RXPOLARITY(x) (((x) >> S_RXPOLARITY) & M_RXPOLARITY) 6892 6893 #define A_XGM_PORT_CFG 0x8b8 6894 6895 #define S_SAFESPEEDCHANGE 4 6896 #define V_SAFESPEEDCHANGE(x) ((x) << S_SAFESPEEDCHANGE) 6897 #define F_SAFESPEEDCHANGE V_SAFESPEEDCHANGE(1U) 6898 6899 #define S_CLKDIVRESET_ 3 6900 #define V_CLKDIVRESET_(x) ((x) << S_CLKDIVRESET_) 6901 #define F_CLKDIVRESET_ V_CLKDIVRESET_(1U) 6902 6903 #define S_PORTSPEED 1 6904 #define M_PORTSPEED 0x3 6905 #define V_PORTSPEED(x) ((x) << S_PORTSPEED) 6906 #define G_PORTSPEED(x) (((x) >> S_PORTSPEED) & M_PORTSPEED) 6907 6908 #define S_ENRGMII 0 6909 #define V_ENRGMII(x) ((x) << S_ENRGMII) 6910 #define F_ENRGMII V_ENRGMII(1U) 6911 6912 #define A_XGM_EPIO_DATA0 0x8c0 6913 #define A_XGM_EPIO_DATA1 0x8c4 6914 #define A_XGM_EPIO_DATA2 0x8c8 6915 #define A_XGM_EPIO_DATA3 0x8cc 6916 #define A_XGM_EPIO_OP 0x8d0 6917 6918 #define S_PIO_READY 31 6919 #define V_PIO_READY(x) ((x) << S_PIO_READY) 6920 #define F_PIO_READY V_PIO_READY(1U) 6921 6922 #define S_PIO_WRRD 24 6923 #define V_PIO_WRRD(x) ((x) << S_PIO_WRRD) 6924 #define F_PIO_WRRD V_PIO_WRRD(1U) 6925 6926 #define S_PIO_ADDRESS 0 6927 #define M_PIO_ADDRESS 0xff 6928 #define V_PIO_ADDRESS(x) ((x) << S_PIO_ADDRESS) 6929 #define G_PIO_ADDRESS(x) (((x) >> S_PIO_ADDRESS) & M_PIO_ADDRESS) 6930 6931 #define A_XGM_INT_ENABLE 0x8d4 6932 6933 #define S_SERDESCMULOCK_LOSS 24 6934 #define V_SERDESCMULOCK_LOSS(x) ((x) << S_SERDESCMULOCK_LOSS) 6935 #define F_SERDESCMULOCK_LOSS V_SERDESCMULOCK_LOSS(1U) 6936 6937 #define S_RGMIIRXFIFOOVERFLOW 23 6938 #define V_RGMIIRXFIFOOVERFLOW(x) ((x) << S_RGMIIRXFIFOOVERFLOW) 6939 #define F_RGMIIRXFIFOOVERFLOW V_RGMIIRXFIFOOVERFLOW(1U) 6940 6941 #define S_RGMIIRXFIFOUNDERFLOW 22 6942 #define V_RGMIIRXFIFOUNDERFLOW(x) ((x) << S_RGMIIRXFIFOUNDERFLOW) 6943 #define F_RGMIIRXFIFOUNDERFLOW V_RGMIIRXFIFOUNDERFLOW(1U) 6944 6945 #define S_RXPKTSIZEERROR 21 6946 #define V_RXPKTSIZEERROR(x) ((x) << S_RXPKTSIZEERROR) 6947 #define F_RXPKTSIZEERROR V_RXPKTSIZEERROR(1U) 6948 6949 #define S_WOLPATDETECTED 20 6950 #define V_WOLPATDETECTED(x) ((x) << S_WOLPATDETECTED) 6951 #define F_WOLPATDETECTED V_WOLPATDETECTED(1U) 6952 6953 #define S_TXFIFO_PRTY_ERR 17 6954 #define M_TXFIFO_PRTY_ERR 0x7 6955 #define V_TXFIFO_PRTY_ERR(x) ((x) << S_TXFIFO_PRTY_ERR) 6956 #define G_TXFIFO_PRTY_ERR(x) (((x) >> S_TXFIFO_PRTY_ERR) & M_TXFIFO_PRTY_ERR) 6957 6958 #define S_RXFIFO_PRTY_ERR 14 6959 #define M_RXFIFO_PRTY_ERR 0x7 6960 #define V_RXFIFO_PRTY_ERR(x) ((x) << S_RXFIFO_PRTY_ERR) 6961 #define G_RXFIFO_PRTY_ERR(x) (((x) >> S_RXFIFO_PRTY_ERR) & M_RXFIFO_PRTY_ERR) 6962 6963 #define S_TXFIFO_UNDERRUN 13 6964 #define V_TXFIFO_UNDERRUN(x) ((x) << S_TXFIFO_UNDERRUN) 6965 #define F_TXFIFO_UNDERRUN V_TXFIFO_UNDERRUN(1U) 6966 6967 #define S_RXFIFO_OVERFLOW 12 6968 #define V_RXFIFO_OVERFLOW(x) ((x) << S_RXFIFO_OVERFLOW) 6969 #define F_RXFIFO_OVERFLOW V_RXFIFO_OVERFLOW(1U) 6970 6971 #define S_SERDESBIST_ERR 8 6972 #define M_SERDESBIST_ERR 0xf 6973 #define V_SERDESBIST_ERR(x) ((x) << S_SERDESBIST_ERR) 6974 #define G_SERDESBIST_ERR(x) (((x) >> S_SERDESBIST_ERR) & M_SERDESBIST_ERR) 6975 6976 #define S_SERDES_LOS 4 6977 #define M_SERDES_LOS 0xf 6978 #define V_SERDES_LOS(x) ((x) << S_SERDES_LOS) 6979 #define G_SERDES_LOS(x) (((x) >> S_SERDES_LOS) & M_SERDES_LOS) 6980 6981 #define S_XAUIPCSCTCERR 3 6982 #define V_XAUIPCSCTCERR(x) ((x) << S_XAUIPCSCTCERR) 6983 #define F_XAUIPCSCTCERR V_XAUIPCSCTCERR(1U) 6984 6985 #define S_XAUIPCSALIGNCHANGE 2 6986 #define V_XAUIPCSALIGNCHANGE(x) ((x) << S_XAUIPCSALIGNCHANGE) 6987 #define F_XAUIPCSALIGNCHANGE V_XAUIPCSALIGNCHANGE(1U) 6988 6989 #define S_RGMIILINKSTSCHANGE 1 6990 #define V_RGMIILINKSTSCHANGE(x) ((x) << S_RGMIILINKSTSCHANGE) 6991 #define F_RGMIILINKSTSCHANGE V_RGMIILINKSTSCHANGE(1U) 6992 6993 #define S_XGM_INT 0 6994 #define V_XGM_INT(x) ((x) << S_XGM_INT) 6995 #define F_XGM_INT V_XGM_INT(1U) 6996 6997 #define S_SERDESBISTERR 8 6998 #define M_SERDESBISTERR 0xf 6999 #define V_SERDESBISTERR(x) ((x) << S_SERDESBISTERR) 7000 #define G_SERDESBISTERR(x) (((x) >> S_SERDESBISTERR) & M_SERDESBISTERR) 7001 7002 #define S_SERDESLOWSIGCHANGE 4 7003 #define M_SERDESLOWSIGCHANGE 0xf 7004 #define V_SERDESLOWSIGCHANGE(x) ((x) << S_SERDESLOWSIGCHANGE) 7005 #define G_SERDESLOWSIGCHANGE(x) (((x) >> S_SERDESLOWSIGCHANGE) & M_SERDESLOWSIGCHANGE) 7006 7007 #define A_XGM_INT_CAUSE 0x8d8 7008 #define A_XGM_XAUI_ACT_CTRL 0x8dc 7009 7010 #define S_TXACTENABLE 1 7011 #define V_TXACTENABLE(x) ((x) << S_TXACTENABLE) 7012 #define F_TXACTENABLE V_TXACTENABLE(1U) 7013 7014 #define A_XGM_SERDES_CTRL0 0x8e0 7015 7016 #define S_INTSERLPBK3 27 7017 #define V_INTSERLPBK3(x) ((x) << S_INTSERLPBK3) 7018 #define F_INTSERLPBK3 V_INTSERLPBK3(1U) 7019 7020 #define S_INTSERLPBK2 26 7021 #define V_INTSERLPBK2(x) ((x) << S_INTSERLPBK2) 7022 #define F_INTSERLPBK2 V_INTSERLPBK2(1U) 7023 7024 #define S_INTSERLPBK1 25 7025 #define V_INTSERLPBK1(x) ((x) << S_INTSERLPBK1) 7026 #define F_INTSERLPBK1 V_INTSERLPBK1(1U) 7027 7028 #define S_INTSERLPBK0 24 7029 #define V_INTSERLPBK0(x) ((x) << S_INTSERLPBK0) 7030 #define F_INTSERLPBK0 V_INTSERLPBK0(1U) 7031 7032 #define S_RESET3 23 7033 #define V_RESET3(x) ((x) << S_RESET3) 7034 #define F_RESET3 V_RESET3(1U) 7035 7036 #define S_RESET2 22 7037 #define V_RESET2(x) ((x) << S_RESET2) 7038 #define F_RESET2 V_RESET2(1U) 7039 7040 #define S_RESET1 21 7041 #define V_RESET1(x) ((x) << S_RESET1) 7042 #define F_RESET1 V_RESET1(1U) 7043 7044 #define S_RESET0 20 7045 #define V_RESET0(x) ((x) << S_RESET0) 7046 #define F_RESET0 V_RESET0(1U) 7047 7048 #define S_PWRDN3 19 7049 #define V_PWRDN3(x) ((x) << S_PWRDN3) 7050 #define F_PWRDN3 V_PWRDN3(1U) 7051 7052 #define S_PWRDN2 18 7053 #define V_PWRDN2(x) ((x) << S_PWRDN2) 7054 #define F_PWRDN2 V_PWRDN2(1U) 7055 7056 #define S_PWRDN1 17 7057 #define V_PWRDN1(x) ((x) << S_PWRDN1) 7058 #define F_PWRDN1 V_PWRDN1(1U) 7059 7060 #define S_PWRDN0 16 7061 #define V_PWRDN0(x) ((x) << S_PWRDN0) 7062 #define F_PWRDN0 V_PWRDN0(1U) 7063 7064 #define S_RESETPLL23 15 7065 #define V_RESETPLL23(x) ((x) << S_RESETPLL23) 7066 #define F_RESETPLL23 V_RESETPLL23(1U) 7067 7068 #define S_RESETPLL01 14 7069 #define V_RESETPLL01(x) ((x) << S_RESETPLL01) 7070 #define F_RESETPLL01 V_RESETPLL01(1U) 7071 7072 #define S_PW23 12 7073 #define M_PW23 0x3 7074 #define V_PW23(x) ((x) << S_PW23) 7075 #define G_PW23(x) (((x) >> S_PW23) & M_PW23) 7076 7077 #define S_PW01 10 7078 #define M_PW01 0x3 7079 #define V_PW01(x) ((x) << S_PW01) 7080 #define G_PW01(x) (((x) >> S_PW01) & M_PW01) 7081 7082 #define S_XGM_DEQ 6 7083 #define M_XGM_DEQ 0xf 7084 #define V_XGM_DEQ(x) ((x) << S_XGM_DEQ) 7085 #define G_XGM_DEQ(x) (((x) >> S_XGM_DEQ) & M_XGM_DEQ) 7086 7087 #define S_XGM_DTX 2 7088 #define M_XGM_DTX 0xf 7089 #define V_XGM_DTX(x) ((x) << S_XGM_DTX) 7090 #define G_XGM_DTX(x) (((x) >> S_XGM_DTX) & M_XGM_DTX) 7091 7092 #define S_XGM_LODRV 1 7093 #define V_XGM_LODRV(x) ((x) << S_XGM_LODRV) 7094 #define F_XGM_LODRV V_XGM_LODRV(1U) 7095 7096 #define S_XGM_HIDRV 0 7097 #define V_XGM_HIDRV(x) ((x) << S_XGM_HIDRV) 7098 #define F_XGM_HIDRV V_XGM_HIDRV(1U) 7099 7100 #define A_XGM_SERDES_CTRL1 0x8e4 7101 7102 #define S_FMOFFSET3 19 7103 #define M_FMOFFSET3 0x1f 7104 #define V_FMOFFSET3(x) ((x) << S_FMOFFSET3) 7105 #define G_FMOFFSET3(x) (((x) >> S_FMOFFSET3) & M_FMOFFSET3) 7106 7107 #define S_FMOFFSETEN3 18 7108 #define V_FMOFFSETEN3(x) ((x) << S_FMOFFSETEN3) 7109 #define F_FMOFFSETEN3 V_FMOFFSETEN3(1U) 7110 7111 #define S_FMOFFSET2 13 7112 #define M_FMOFFSET2 0x1f 7113 #define V_FMOFFSET2(x) ((x) << S_FMOFFSET2) 7114 #define G_FMOFFSET2(x) (((x) >> S_FMOFFSET2) & M_FMOFFSET2) 7115 7116 #define S_FMOFFSETEN2 12 7117 #define V_FMOFFSETEN2(x) ((x) << S_FMOFFSETEN2) 7118 #define F_FMOFFSETEN2 V_FMOFFSETEN2(1U) 7119 7120 #define S_FMOFFSET1 7 7121 #define M_FMOFFSET1 0x1f 7122 #define V_FMOFFSET1(x) ((x) << S_FMOFFSET1) 7123 #define G_FMOFFSET1(x) (((x) >> S_FMOFFSET1) & M_FMOFFSET1) 7124 7125 #define S_FMOFFSETEN1 6 7126 #define V_FMOFFSETEN1(x) ((x) << S_FMOFFSETEN1) 7127 #define F_FMOFFSETEN1 V_FMOFFSETEN1(1U) 7128 7129 #define S_FMOFFSET0 1 7130 #define M_FMOFFSET0 0x1f 7131 #define V_FMOFFSET0(x) ((x) << S_FMOFFSET0) 7132 #define G_FMOFFSET0(x) (((x) >> S_FMOFFSET0) & M_FMOFFSET0) 7133 7134 #define S_FMOFFSETEN0 0 7135 #define V_FMOFFSETEN0(x) ((x) << S_FMOFFSETEN0) 7136 #define F_FMOFFSETEN0 V_FMOFFSETEN0(1U) 7137 7138 #define A_XGM_SERDES_CTRL2 0x8e8 7139 7140 #define S_DNIN3 11 7141 #define V_DNIN3(x) ((x) << S_DNIN3) 7142 #define F_DNIN3 V_DNIN3(1U) 7143 7144 #define S_UPIN3 10 7145 #define V_UPIN3(x) ((x) << S_UPIN3) 7146 #define F_UPIN3 V_UPIN3(1U) 7147 7148 #define S_RXSLAVE3 9 7149 #define V_RXSLAVE3(x) ((x) << S_RXSLAVE3) 7150 #define F_RXSLAVE3 V_RXSLAVE3(1U) 7151 7152 #define S_DNIN2 8 7153 #define V_DNIN2(x) ((x) << S_DNIN2) 7154 #define F_DNIN2 V_DNIN2(1U) 7155 7156 #define S_UPIN2 7 7157 #define V_UPIN2(x) ((x) << S_UPIN2) 7158 #define F_UPIN2 V_UPIN2(1U) 7159 7160 #define S_RXSLAVE2 6 7161 #define V_RXSLAVE2(x) ((x) << S_RXSLAVE2) 7162 #define F_RXSLAVE2 V_RXSLAVE2(1U) 7163 7164 #define S_DNIN1 5 7165 #define V_DNIN1(x) ((x) << S_DNIN1) 7166 #define F_DNIN1 V_DNIN1(1U) 7167 7168 #define S_UPIN1 4 7169 #define V_UPIN1(x) ((x) << S_UPIN1) 7170 #define F_UPIN1 V_UPIN1(1U) 7171 7172 #define S_RXSLAVE1 3 7173 #define V_RXSLAVE1(x) ((x) << S_RXSLAVE1) 7174 #define F_RXSLAVE1 V_RXSLAVE1(1U) 7175 7176 #define S_DNIN0 2 7177 #define V_DNIN0(x) ((x) << S_DNIN0) 7178 #define F_DNIN0 V_DNIN0(1U) 7179 7180 #define S_UPIN0 1 7181 #define V_UPIN0(x) ((x) << S_UPIN0) 7182 #define F_UPIN0 V_UPIN0(1U) 7183 7184 #define S_RXSLAVE0 0 7185 #define V_RXSLAVE0(x) ((x) << S_RXSLAVE0) 7186 #define F_RXSLAVE0 V_RXSLAVE0(1U) 7187 7188 #define A_XGM_SERDES_CTRL3 0x8ec 7189 7190 #define S_EXTBISTCHKERRCLR3 31 7191 #define V_EXTBISTCHKERRCLR3(x) ((x) << S_EXTBISTCHKERRCLR3) 7192 #define F_EXTBISTCHKERRCLR3 V_EXTBISTCHKERRCLR3(1U) 7193 7194 #define S_EXTBISTCHKEN3 30 7195 #define V_EXTBISTCHKEN3(x) ((x) << S_EXTBISTCHKEN3) 7196 #define F_EXTBISTCHKEN3 V_EXTBISTCHKEN3(1U) 7197 7198 #define S_EXTBISTGENEN3 29 7199 #define V_EXTBISTGENEN3(x) ((x) << S_EXTBISTGENEN3) 7200 #define F_EXTBISTGENEN3 V_EXTBISTGENEN3(1U) 7201 7202 #define S_EXTBISTPAT3 26 7203 #define M_EXTBISTPAT3 0x7 7204 #define V_EXTBISTPAT3(x) ((x) << S_EXTBISTPAT3) 7205 #define G_EXTBISTPAT3(x) (((x) >> S_EXTBISTPAT3) & M_EXTBISTPAT3) 7206 7207 #define S_EXTPARRESET3 25 7208 #define V_EXTPARRESET3(x) ((x) << S_EXTPARRESET3) 7209 #define F_EXTPARRESET3 V_EXTPARRESET3(1U) 7210 7211 #define S_EXTPARLPBK3 24 7212 #define V_EXTPARLPBK3(x) ((x) << S_EXTPARLPBK3) 7213 #define F_EXTPARLPBK3 V_EXTPARLPBK3(1U) 7214 7215 #define S_EXTBISTCHKERRCLR2 23 7216 #define V_EXTBISTCHKERRCLR2(x) ((x) << S_EXTBISTCHKERRCLR2) 7217 #define F_EXTBISTCHKERRCLR2 V_EXTBISTCHKERRCLR2(1U) 7218 7219 #define S_EXTBISTCHKEN2 22 7220 #define V_EXTBISTCHKEN2(x) ((x) << S_EXTBISTCHKEN2) 7221 #define F_EXTBISTCHKEN2 V_EXTBISTCHKEN2(1U) 7222 7223 #define S_EXTBISTGENEN2 21 7224 #define V_EXTBISTGENEN2(x) ((x) << S_EXTBISTGENEN2) 7225 #define F_EXTBISTGENEN2 V_EXTBISTGENEN2(1U) 7226 7227 #define S_EXTBISTPAT2 18 7228 #define M_EXTBISTPAT2 0x7 7229 #define V_EXTBISTPAT2(x) ((x) << S_EXTBISTPAT2) 7230 #define G_EXTBISTPAT2(x) (((x) >> S_EXTBISTPAT2) & M_EXTBISTPAT2) 7231 7232 #define S_EXTPARRESET2 17 7233 #define V_EXTPARRESET2(x) ((x) << S_EXTPARRESET2) 7234 #define F_EXTPARRESET2 V_EXTPARRESET2(1U) 7235 7236 #define S_EXTPARLPBK2 16 7237 #define V_EXTPARLPBK2(x) ((x) << S_EXTPARLPBK2) 7238 #define F_EXTPARLPBK2 V_EXTPARLPBK2(1U) 7239 7240 #define S_EXTBISTCHKERRCLR1 15 7241 #define V_EXTBISTCHKERRCLR1(x) ((x) << S_EXTBISTCHKERRCLR1) 7242 #define F_EXTBISTCHKERRCLR1 V_EXTBISTCHKERRCLR1(1U) 7243 7244 #define S_EXTBISTCHKEN1 14 7245 #define V_EXTBISTCHKEN1(x) ((x) << S_EXTBISTCHKEN1) 7246 #define F_EXTBISTCHKEN1 V_EXTBISTCHKEN1(1U) 7247 7248 #define S_EXTBISTGENEN1 13 7249 #define V_EXTBISTGENEN1(x) ((x) << S_EXTBISTGENEN1) 7250 #define F_EXTBISTGENEN1 V_EXTBISTGENEN1(1U) 7251 7252 #define S_EXTBISTPAT1 10 7253 #define M_EXTBISTPAT1 0x7 7254 #define V_EXTBISTPAT1(x) ((x) << S_EXTBISTPAT1) 7255 #define G_EXTBISTPAT1(x) (((x) >> S_EXTBISTPAT1) & M_EXTBISTPAT1) 7256 7257 #define S_EXTPARRESET1 9 7258 #define V_EXTPARRESET1(x) ((x) << S_EXTPARRESET1) 7259 #define F_EXTPARRESET1 V_EXTPARRESET1(1U) 7260 7261 #define S_EXTPARLPBK1 8 7262 #define V_EXTPARLPBK1(x) ((x) << S_EXTPARLPBK1) 7263 #define F_EXTPARLPBK1 V_EXTPARLPBK1(1U) 7264 7265 #define S_EXTBISTCHKERRCLR0 7 7266 #define V_EXTBISTCHKERRCLR0(x) ((x) << S_EXTBISTCHKERRCLR0) 7267 #define F_EXTBISTCHKERRCLR0 V_EXTBISTCHKERRCLR0(1U) 7268 7269 #define S_EXTBISTCHKEN0 6 7270 #define V_EXTBISTCHKEN0(x) ((x) << S_EXTBISTCHKEN0) 7271 #define F_EXTBISTCHKEN0 V_EXTBISTCHKEN0(1U) 7272 7273 #define S_EXTBISTGENEN0 5 7274 #define V_EXTBISTGENEN0(x) ((x) << S_EXTBISTGENEN0) 7275 #define F_EXTBISTGENEN0 V_EXTBISTGENEN0(1U) 7276 7277 #define S_EXTBISTPAT0 2 7278 #define M_EXTBISTPAT0 0x7 7279 #define V_EXTBISTPAT0(x) ((x) << S_EXTBISTPAT0) 7280 #define G_EXTBISTPAT0(x) (((x) >> S_EXTBISTPAT0) & M_EXTBISTPAT0) 7281 7282 #define S_EXTPARRESET0 1 7283 #define V_EXTPARRESET0(x) ((x) << S_EXTPARRESET0) 7284 #define F_EXTPARRESET0 V_EXTPARRESET0(1U) 7285 7286 #define S_EXTPARLPBK0 0 7287 #define V_EXTPARLPBK0(x) ((x) << S_EXTPARLPBK0) 7288 #define F_EXTPARLPBK0 V_EXTPARLPBK0(1U) 7289 7290 #define A_XGM_SERDES_STAT0 0x8f0 7291 7292 #define S_EXTBISTCHKERRCNT0 4 7293 #define M_EXTBISTCHKERRCNT0 0xffffff 7294 #define V_EXTBISTCHKERRCNT0(x) ((x) << S_EXTBISTCHKERRCNT0) 7295 #define G_EXTBISTCHKERRCNT0(x) (((x) >> S_EXTBISTCHKERRCNT0) & M_EXTBISTCHKERRCNT0) 7296 7297 #define S_EXTBISTCHKFMD0 3 7298 #define V_EXTBISTCHKFMD0(x) ((x) << S_EXTBISTCHKFMD0) 7299 #define F_EXTBISTCHKFMD0 V_EXTBISTCHKFMD0(1U) 7300 7301 #define S_LOWSIG0 0 7302 #define V_LOWSIG0(x) ((x) << S_LOWSIG0) 7303 #define F_LOWSIG0 V_LOWSIG0(1U) 7304 7305 #define A_XGM_SERDES_STAT1 0x8f4 7306 7307 #define S_EXTBISTCHKERRCNT1 4 7308 #define M_EXTBISTCHKERRCNT1 0xffffff 7309 #define V_EXTBISTCHKERRCNT1(x) ((x) << S_EXTBISTCHKERRCNT1) 7310 #define G_EXTBISTCHKERRCNT1(x) (((x) >> S_EXTBISTCHKERRCNT1) & M_EXTBISTCHKERRCNT1) 7311 7312 #define S_EXTBISTCHKFMD1 3 7313 #define V_EXTBISTCHKFMD1(x) ((x) << S_EXTBISTCHKFMD1) 7314 #define F_EXTBISTCHKFMD1 V_EXTBISTCHKFMD1(1U) 7315 7316 #define S_LOWSIG1 0 7317 #define V_LOWSIG1(x) ((x) << S_LOWSIG1) 7318 #define F_LOWSIG1 V_LOWSIG1(1U) 7319 7320 #define A_XGM_SERDES_STAT2 0x8f8 7321 7322 #define S_EXTBISTCHKERRCNT2 4 7323 #define M_EXTBISTCHKERRCNT2 0xffffff 7324 #define V_EXTBISTCHKERRCNT2(x) ((x) << S_EXTBISTCHKERRCNT2) 7325 #define G_EXTBISTCHKERRCNT2(x) (((x) >> S_EXTBISTCHKERRCNT2) & M_EXTBISTCHKERRCNT2) 7326 7327 #define S_EXTBISTCHKFMD2 3 7328 #define V_EXTBISTCHKFMD2(x) ((x) << S_EXTBISTCHKFMD2) 7329 #define F_EXTBISTCHKFMD2 V_EXTBISTCHKFMD2(1U) 7330 7331 #define S_LOWSIG2 0 7332 #define V_LOWSIG2(x) ((x) << S_LOWSIG2) 7333 #define F_LOWSIG2 V_LOWSIG2(1U) 7334 7335 #define A_XGM_SERDES_STAT3 0x8fc 7336 7337 #define S_EXTBISTCHKERRCNT3 4 7338 #define M_EXTBISTCHKERRCNT3 0xffffff 7339 #define V_EXTBISTCHKERRCNT3(x) ((x) << S_EXTBISTCHKERRCNT3) 7340 #define G_EXTBISTCHKERRCNT3(x) (((x) >> S_EXTBISTCHKERRCNT3) & M_EXTBISTCHKERRCNT3) 7341 7342 #define S_EXTBISTCHKFMD3 3 7343 #define V_EXTBISTCHKFMD3(x) ((x) << S_EXTBISTCHKFMD3) 7344 #define F_EXTBISTCHKFMD3 V_EXTBISTCHKFMD3(1U) 7345 7346 #define S_LOWSIG3 0 7347 #define V_LOWSIG3(x) ((x) << S_LOWSIG3) 7348 #define F_LOWSIG3 V_LOWSIG3(1U) 7349 7350 #define A_XGM_STAT_TX_BYTE_LOW 0x900 7351 #define A_XGM_STAT_TX_BYTE_HIGH 0x904 7352 7353 #define S_TXBYTES_HIGH 0 7354 #define M_TXBYTES_HIGH 0x1fff 7355 #define V_TXBYTES_HIGH(x) ((x) << S_TXBYTES_HIGH) 7356 #define G_TXBYTES_HIGH(x) (((x) >> S_TXBYTES_HIGH) & M_TXBYTES_HIGH) 7357 7358 #define A_XGM_STAT_TX_FRAME_LOW 0x908 7359 #define A_XGM_STAT_TX_FRAME_HIGH 0x90c 7360 7361 #define S_TXFRAMES_HIGH 0 7362 #define M_TXFRAMES_HIGH 0xf 7363 #define V_TXFRAMES_HIGH(x) ((x) << S_TXFRAMES_HIGH) 7364 #define G_TXFRAMES_HIGH(x) (((x) >> S_TXFRAMES_HIGH) & M_TXFRAMES_HIGH) 7365 7366 #define A_XGM_STAT_TX_BCAST 0x910 7367 #define A_XGM_STAT_TX_MCAST 0x914 7368 #define A_XGM_STAT_TX_PAUSE 0x918 7369 #define A_XGM_STAT_TX_64B_FRAMES 0x91c 7370 #define A_XGM_STAT_TX_65_127B_FRAMES 0x920 7371 #define A_XGM_STAT_TX_128_255B_FRAMES 0x924 7372 #define A_XGM_STAT_TX_256_511B_FRAMES 0x928 7373 #define A_XGM_STAT_TX_512_1023B_FRAMES 0x92c 7374 #define A_XGM_STAT_TX_1024_1518B_FRAMES 0x930 7375 #define A_XGM_STAT_TX_1519_MAXB_FRAMES 0x934 7376 #define A_XGM_STAT_TX_ERR_FRAMES 0x938 7377 #define A_XGM_STAT_RX_BYTES_LOW 0x93c 7378 #define A_XGM_STAT_RX_BYTES_HIGH 0x940 7379 7380 #define S_RXBYTES_HIGH 0 7381 #define M_RXBYTES_HIGH 0x1fff 7382 #define V_RXBYTES_HIGH(x) ((x) << S_RXBYTES_HIGH) 7383 #define G_RXBYTES_HIGH(x) (((x) >> S_RXBYTES_HIGH) & M_RXBYTES_HIGH) 7384 7385 #define A_XGM_STAT_RX_FRAMES_LOW 0x944 7386 #define A_XGM_STAT_RX_FRAMES_HIGH 0x948 7387 7388 #define S_RXFRAMES_HIGH 0 7389 #define M_RXFRAMES_HIGH 0xf 7390 #define V_RXFRAMES_HIGH(x) ((x) << S_RXFRAMES_HIGH) 7391 #define G_RXFRAMES_HIGH(x) (((x) >> S_RXFRAMES_HIGH) & M_RXFRAMES_HIGH) 7392 7393 #define A_XGM_STAT_RX_BCAST_FRAMES 0x94c 7394 #define A_XGM_STAT_RX_MCAST_FRAMES 0x950 7395 #define A_XGM_STAT_RX_PAUSE_FRAMES 0x954 7396 7397 #define S_RXPAUSEFRAMES 0 7398 #define M_RXPAUSEFRAMES 0xffff 7399 #define V_RXPAUSEFRAMES(x) ((x) << S_RXPAUSEFRAMES) 7400 #define G_RXPAUSEFRAMES(x) (((x) >> S_RXPAUSEFRAMES) & M_RXPAUSEFRAMES) 7401 7402 #define A_XGM_STAT_RX_64B_FRAMES 0x958 7403 #define A_XGM_STAT_RX_65_127B_FRAMES 0x95c 7404 #define A_XGM_STAT_RX_128_255B_FRAMES 0x960 7405 #define A_XGM_STAT_RX_256_511B_FRAMES 0x964 7406 #define A_XGM_STAT_RX_512_1023B_FRAMES 0x968 7407 #define A_XGM_STAT_RX_1024_1518B_FRAMES 0x96c 7408 #define A_XGM_STAT_RX_1519_MAXB_FRAMES 0x970 7409 #define A_XGM_STAT_RX_SHORT_FRAMES 0x974 7410 7411 #define S_RXSHORTFRAMES 0 7412 #define M_RXSHORTFRAMES 0xffff 7413 #define V_RXSHORTFRAMES(x) ((x) << S_RXSHORTFRAMES) 7414 #define G_RXSHORTFRAMES(x) (((x) >> S_RXSHORTFRAMES) & M_RXSHORTFRAMES) 7415 7416 #define A_XGM_STAT_RX_OVERSIZE_FRAMES 0x978 7417 7418 #define S_RXOVERSIZEFRAMES 0 7419 #define M_RXOVERSIZEFRAMES 0xffff 7420 #define V_RXOVERSIZEFRAMES(x) ((x) << S_RXOVERSIZEFRAMES) 7421 #define G_RXOVERSIZEFRAMES(x) (((x) >> S_RXOVERSIZEFRAMES) & M_RXOVERSIZEFRAMES) 7422 7423 #define A_XGM_STAT_RX_JABBER_FRAMES 0x97c 7424 7425 #define S_RXJABBERFRAMES 0 7426 #define M_RXJABBERFRAMES 0xffff 7427 #define V_RXJABBERFRAMES(x) ((x) << S_RXJABBERFRAMES) 7428 #define G_RXJABBERFRAMES(x) (((x) >> S_RXJABBERFRAMES) & M_RXJABBERFRAMES) 7429 7430 #define A_XGM_STAT_RX_CRC_ERR_FRAMES 0x980 7431 7432 #define S_RXCRCERRFRAMES 0 7433 #define M_RXCRCERRFRAMES 0xffff 7434 #define V_RXCRCERRFRAMES(x) ((x) << S_RXCRCERRFRAMES) 7435 #define G_RXCRCERRFRAMES(x) (((x) >> S_RXCRCERRFRAMES) & M_RXCRCERRFRAMES) 7436 7437 #define A_XGM_STAT_RX_LENGTH_ERR_FRAMES 0x984 7438 7439 #define S_RXLENGTHERRFRAMES 0 7440 #define M_RXLENGTHERRFRAMES 0xffff 7441 #define V_RXLENGTHERRFRAMES(x) ((x) << S_RXLENGTHERRFRAMES) 7442 #define G_RXLENGTHERRFRAMES(x) (((x) >> S_RXLENGTHERRFRAMES) & M_RXLENGTHERRFRAMES) 7443 7444 #define A_XGM_STAT_RX_SYM_CODE_ERR_FRAMES 0x988 7445 7446 #define S_RXSYMCODEERRFRAMES 0 7447 #define M_RXSYMCODEERRFRAMES 0xffff 7448 #define V_RXSYMCODEERRFRAMES(x) ((x) << S_RXSYMCODEERRFRAMES) 7449 #define G_RXSYMCODEERRFRAMES(x) (((x) >> S_RXSYMCODEERRFRAMES) & M_RXSYMCODEERRFRAMES) 7450 7451 #define A_XGM_SERDES_STATUS0 0x98c 7452 7453 #define S_RXERRLANE3 9 7454 #define M_RXERRLANE3 0x7 7455 #define V_RXERRLANE3(x) ((x) << S_RXERRLANE3) 7456 #define G_RXERRLANE3(x) (((x) >> S_RXERRLANE3) & M_RXERRLANE3) 7457 7458 #define S_RXERRLANE2 6 7459 #define M_RXERRLANE2 0x7 7460 #define V_RXERRLANE2(x) ((x) << S_RXERRLANE2) 7461 #define G_RXERRLANE2(x) (((x) >> S_RXERRLANE2) & M_RXERRLANE2) 7462 7463 #define S_RXERRLANE1 3 7464 #define M_RXERRLANE1 0x7 7465 #define V_RXERRLANE1(x) ((x) << S_RXERRLANE1) 7466 #define G_RXERRLANE1(x) (((x) >> S_RXERRLANE1) & M_RXERRLANE1) 7467 7468 #define S_RXERRLANE0 0 7469 #define M_RXERRLANE0 0x7 7470 #define V_RXERRLANE0(x) ((x) << S_RXERRLANE0) 7471 #define G_RXERRLANE0(x) (((x) >> S_RXERRLANE0) & M_RXERRLANE0) 7472 7473 #define A_XGM_SERDES_STATUS1 0x990 7474 7475 #define S_RXKLOCKLANE3 11 7476 #define V_RXKLOCKLANE3(x) ((x) << S_RXKLOCKLANE3) 7477 #define F_RXKLOCKLANE3 V_RXKLOCKLANE3(1U) 7478 7479 #define S_RXKLOCKLANE2 10 7480 #define V_RXKLOCKLANE2(x) ((x) << S_RXKLOCKLANE2) 7481 #define F_RXKLOCKLANE2 V_RXKLOCKLANE2(1U) 7482 7483 #define S_RXKLOCKLANE1 9 7484 #define V_RXKLOCKLANE1(x) ((x) << S_RXKLOCKLANE1) 7485 #define F_RXKLOCKLANE1 V_RXKLOCKLANE1(1U) 7486 7487 #define S_RXKLOCKLANE0 8 7488 #define V_RXKLOCKLANE0(x) ((x) << S_RXKLOCKLANE0) 7489 #define F_RXKLOCKLANE0 V_RXKLOCKLANE0(1U) 7490 7491 #define S_RXUFLOWLANE3 7 7492 #define V_RXUFLOWLANE3(x) ((x) << S_RXUFLOWLANE3) 7493 #define F_RXUFLOWLANE3 V_RXUFLOWLANE3(1U) 7494 7495 #define S_RXUFLOWLANE2 6 7496 #define V_RXUFLOWLANE2(x) ((x) << S_RXUFLOWLANE2) 7497 #define F_RXUFLOWLANE2 V_RXUFLOWLANE2(1U) 7498 7499 #define S_RXUFLOWLANE1 5 7500 #define V_RXUFLOWLANE1(x) ((x) << S_RXUFLOWLANE1) 7501 #define F_RXUFLOWLANE1 V_RXUFLOWLANE1(1U) 7502 7503 #define S_RXUFLOWLANE0 4 7504 #define V_RXUFLOWLANE0(x) ((x) << S_RXUFLOWLANE0) 7505 #define F_RXUFLOWLANE0 V_RXUFLOWLANE0(1U) 7506 7507 #define S_RXOFLOWLANE3 3 7508 #define V_RXOFLOWLANE3(x) ((x) << S_RXOFLOWLANE3) 7509 #define F_RXOFLOWLANE3 V_RXOFLOWLANE3(1U) 7510 7511 #define S_RXOFLOWLANE2 2 7512 #define V_RXOFLOWLANE2(x) ((x) << S_RXOFLOWLANE2) 7513 #define F_RXOFLOWLANE2 V_RXOFLOWLANE2(1U) 7514 7515 #define S_RXOFLOWLANE1 1 7516 #define V_RXOFLOWLANE1(x) ((x) << S_RXOFLOWLANE1) 7517 #define F_RXOFLOWLANE1 V_RXOFLOWLANE1(1U) 7518 7519 #define S_RXOFLOWLANE0 0 7520 #define V_RXOFLOWLANE0(x) ((x) << S_RXOFLOWLANE0) 7521 #define F_RXOFLOWLANE0 V_RXOFLOWLANE0(1U) 7522 7523 #define A_XGM_SERDES_STATUS2 0x994 7524 7525 #define S_XGM_RXEIDLANE3 11 7526 #define V_XGM_RXEIDLANE3(x) ((x) << S_XGM_RXEIDLANE3) 7527 #define F_XGM_RXEIDLANE3 V_XGM_RXEIDLANE3(1U) 7528 7529 #define S_XGM_RXEIDLANE2 10 7530 #define V_XGM_RXEIDLANE2(x) ((x) << S_XGM_RXEIDLANE2) 7531 #define F_XGM_RXEIDLANE2 V_XGM_RXEIDLANE2(1U) 7532 7533 #define S_XGM_RXEIDLANE1 9 7534 #define V_XGM_RXEIDLANE1(x) ((x) << S_XGM_RXEIDLANE1) 7535 #define F_XGM_RXEIDLANE1 V_XGM_RXEIDLANE1(1U) 7536 7537 #define S_XGM_RXEIDLANE0 8 7538 #define V_XGM_RXEIDLANE0(x) ((x) << S_XGM_RXEIDLANE0) 7539 #define F_XGM_RXEIDLANE0 V_XGM_RXEIDLANE0(1U) 7540 7541 #define S_RXREMSKIPLANE3 7 7542 #define V_RXREMSKIPLANE3(x) ((x) << S_RXREMSKIPLANE3) 7543 #define F_RXREMSKIPLANE3 V_RXREMSKIPLANE3(1U) 7544 7545 #define S_RXREMSKIPLANE2 6 7546 #define V_RXREMSKIPLANE2(x) ((x) << S_RXREMSKIPLANE2) 7547 #define F_RXREMSKIPLANE2 V_RXREMSKIPLANE2(1U) 7548 7549 #define S_RXREMSKIPLANE1 5 7550 #define V_RXREMSKIPLANE1(x) ((x) << S_RXREMSKIPLANE1) 7551 #define F_RXREMSKIPLANE1 V_RXREMSKIPLANE1(1U) 7552 7553 #define S_RXREMSKIPLANE0 4 7554 #define V_RXREMSKIPLANE0(x) ((x) << S_RXREMSKIPLANE0) 7555 #define F_RXREMSKIPLANE0 V_RXREMSKIPLANE0(1U) 7556 7557 #define S_RXADDSKIPLANE3 3 7558 #define V_RXADDSKIPLANE3(x) ((x) << S_RXADDSKIPLANE3) 7559 #define F_RXADDSKIPLANE3 V_RXADDSKIPLANE3(1U) 7560 7561 #define S_RXADDSKIPLANE2 2 7562 #define V_RXADDSKIPLANE2(x) ((x) << S_RXADDSKIPLANE2) 7563 #define F_RXADDSKIPLANE2 V_RXADDSKIPLANE2(1U) 7564 7565 #define S_RXADDSKIPLANE1 1 7566 #define V_RXADDSKIPLANE1(x) ((x) << S_RXADDSKIPLANE1) 7567 #define F_RXADDSKIPLANE1 V_RXADDSKIPLANE1(1U) 7568 7569 #define S_RXADDSKIPLANE0 0 7570 #define V_RXADDSKIPLANE0(x) ((x) << S_RXADDSKIPLANE0) 7571 #define F_RXADDSKIPLANE0 V_RXADDSKIPLANE0(1U) 7572 7573 #define A_XGM_XAUI_PCS_ERR 0x998 7574 7575 #define S_PCS_SYNCSTATUS 5 7576 #define M_PCS_SYNCSTATUS 0xf 7577 #define V_PCS_SYNCSTATUS(x) ((x) << S_PCS_SYNCSTATUS) 7578 #define G_PCS_SYNCSTATUS(x) (((x) >> S_PCS_SYNCSTATUS) & M_PCS_SYNCSTATUS) 7579 7580 #define S_PCS_CTCFIFOERR 1 7581 #define M_PCS_CTCFIFOERR 0xf 7582 #define V_PCS_CTCFIFOERR(x) ((x) << S_PCS_CTCFIFOERR) 7583 #define G_PCS_CTCFIFOERR(x) (((x) >> S_PCS_CTCFIFOERR) & M_PCS_CTCFIFOERR) 7584 7585 #define S_PCS_NOTALIGNED 0 7586 #define V_PCS_NOTALIGNED(x) ((x) << S_PCS_NOTALIGNED) 7587 #define F_PCS_NOTALIGNED V_PCS_NOTALIGNED(1U) 7588 7589 #define A_XGM_RGMII_STATUS 0x99c 7590 7591 #define S_GMIIDUPLEX 3 7592 #define V_GMIIDUPLEX(x) ((x) << S_GMIIDUPLEX) 7593 #define F_GMIIDUPLEX V_GMIIDUPLEX(1U) 7594 7595 #define S_GMIISPEED 1 7596 #define M_GMIISPEED 0x3 7597 #define V_GMIISPEED(x) ((x) << S_GMIISPEED) 7598 #define G_GMIISPEED(x) (((x) >> S_GMIISPEED) & M_GMIISPEED) 7599 7600 #define S_GMIILINKSTATUS 0 7601 #define V_GMIILINKSTATUS(x) ((x) << S_GMIILINKSTATUS) 7602 #define F_GMIILINKSTATUS V_GMIILINKSTATUS(1U) 7603 7604 #define A_XGM_WOL_STATUS 0x9a0 7605 7606 #define S_PATDETECTED 31 7607 #define V_PATDETECTED(x) ((x) << S_PATDETECTED) 7608 #define F_PATDETECTED V_PATDETECTED(1U) 7609 7610 #define S_MATCHEDFILTER 0 7611 #define M_MATCHEDFILTER 0x7 7612 #define V_MATCHEDFILTER(x) ((x) << S_MATCHEDFILTER) 7613 #define G_MATCHEDFILTER(x) (((x) >> S_MATCHEDFILTER) & M_MATCHEDFILTER) 7614 7615 #define A_XGM_RX_MAX_PKT_SIZE_ERR_CNT 0x9a4 7616 #define A_XGM_TX_SPI4_SOP_EOP_CNT 0x9a8 7617 7618 #define S_TXSPI4SOPCNT 16 7619 #define M_TXSPI4SOPCNT 0xffff 7620 #define V_TXSPI4SOPCNT(x) ((x) << S_TXSPI4SOPCNT) 7621 #define G_TXSPI4SOPCNT(x) (((x) >> S_TXSPI4SOPCNT) & M_TXSPI4SOPCNT) 7622 7623 #define S_TXSPI4EOPCNT 0 7624 #define M_TXSPI4EOPCNT 0xffff 7625 #define V_TXSPI4EOPCNT(x) ((x) << S_TXSPI4EOPCNT) 7626 #define G_TXSPI4EOPCNT(x) (((x) >> S_TXSPI4EOPCNT) & M_TXSPI4EOPCNT) 7627 7628 #define A_XGM_RX_SPI4_SOP_EOP_CNT 0x9ac 7629 7630 #define S_RXSPI4SOPCNT 16 7631 #define M_RXSPI4SOPCNT 0xffff 7632 #define V_RXSPI4SOPCNT(x) ((x) << S_RXSPI4SOPCNT) 7633 #define G_RXSPI4SOPCNT(x) (((x) >> S_RXSPI4SOPCNT) & M_RXSPI4SOPCNT) 7634 7635 #define S_RXSPI4EOPCNT 0 7636 #define M_RXSPI4EOPCNT 0xffff 7637 #define V_RXSPI4EOPCNT(x) ((x) << S_RXSPI4EOPCNT) 7638 #define G_RXSPI4EOPCNT(x) (((x) >> S_RXSPI4EOPCNT) & M_RXSPI4EOPCNT) 7639 7640 /* registers for module XGMAC0_1 */ 7641 #define XGMAC0_1_BASE_ADDR 0xa00 7642