xref: /freebsd/sys/dev/cxgb/common/cxgb_regs.h (revision 2f6a179eb910129fb812c1ad1bdc300da1203dc0)
1 /**************************************************************************
2 
3 Copyright (c) 2007, Chelsio Inc.
4 All rights reserved.
5 
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8 
9  1. Redistributions of source code must retain the above copyright notice,
10     this list of conditions and the following disclaimer.
11 
12  2. Neither the name of the Chelsio Corporation nor the names of its
13     contributors may be used to endorse or promote products derived from
14     this software without specific prior written permission.
15 
16 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
20 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26 POSSIBILITY OF SUCH DAMAGE.
27 
28 $FreeBSD$
29 
30 ***************************************************************************/
31 /* This file is automatically generated --- do not edit */
32 
33 /* registers for module SGE3 */
34 #define SGE3_BASE_ADDR 0x0
35 
36 #define A_SG_CONTROL 0x0
37 
38 #define S_CONGMODE    29
39 #define V_CONGMODE(x) ((x) << S_CONGMODE)
40 #define F_CONGMODE    V_CONGMODE(1U)
41 
42 #define S_TNLFLMODE    28
43 #define V_TNLFLMODE(x) ((x) << S_TNLFLMODE)
44 #define F_TNLFLMODE    V_TNLFLMODE(1U)
45 
46 #define S_FATLPERREN    27
47 #define V_FATLPERREN(x) ((x) << S_FATLPERREN)
48 #define F_FATLPERREN    V_FATLPERREN(1U)
49 
50 #define S_URGTNL    26
51 #define V_URGTNL(x) ((x) << S_URGTNL)
52 #define F_URGTNL    V_URGTNL(1U)
53 
54 #define S_NEWNOTIFY    25
55 #define V_NEWNOTIFY(x) ((x) << S_NEWNOTIFY)
56 #define F_NEWNOTIFY    V_NEWNOTIFY(1U)
57 
58 #define S_AVOIDCQOVFL    24
59 #define V_AVOIDCQOVFL(x) ((x) << S_AVOIDCQOVFL)
60 #define F_AVOIDCQOVFL    V_AVOIDCQOVFL(1U)
61 
62 #define S_OPTONEINTMULTQ    23
63 #define V_OPTONEINTMULTQ(x) ((x) << S_OPTONEINTMULTQ)
64 #define F_OPTONEINTMULTQ    V_OPTONEINTMULTQ(1U)
65 
66 #define S_CQCRDTCTRL    22
67 #define V_CQCRDTCTRL(x) ((x) << S_CQCRDTCTRL)
68 #define F_CQCRDTCTRL    V_CQCRDTCTRL(1U)
69 
70 #define S_EGRENUPBP    21
71 #define V_EGRENUPBP(x) ((x) << S_EGRENUPBP)
72 #define F_EGRENUPBP    V_EGRENUPBP(1U)
73 
74 #define S_DROPPKT    20
75 #define V_DROPPKT(x) ((x) << S_DROPPKT)
76 #define F_DROPPKT    V_DROPPKT(1U)
77 
78 #define S_EGRGENCTRL    19
79 #define V_EGRGENCTRL(x) ((x) << S_EGRGENCTRL)
80 #define F_EGRGENCTRL    V_EGRGENCTRL(1U)
81 
82 #define S_USERSPACESIZE    14
83 #define M_USERSPACESIZE    0x1f
84 #define V_USERSPACESIZE(x) ((x) << S_USERSPACESIZE)
85 #define G_USERSPACESIZE(x) (((x) >> S_USERSPACESIZE) & M_USERSPACESIZE)
86 
87 #define S_HOSTPAGESIZE    11
88 #define M_HOSTPAGESIZE    0x7
89 #define V_HOSTPAGESIZE(x) ((x) << S_HOSTPAGESIZE)
90 #define G_HOSTPAGESIZE(x) (((x) >> S_HOSTPAGESIZE) & M_HOSTPAGESIZE)
91 
92 #define S_PCIRELAX    10
93 #define V_PCIRELAX(x) ((x) << S_PCIRELAX)
94 #define F_PCIRELAX    V_PCIRELAX(1U)
95 
96 #define S_FLMODE    9
97 #define V_FLMODE(x) ((x) << S_FLMODE)
98 #define F_FLMODE    V_FLMODE(1U)
99 
100 #define S_PKTSHIFT    6
101 #define M_PKTSHIFT    0x7
102 #define V_PKTSHIFT(x) ((x) << S_PKTSHIFT)
103 #define G_PKTSHIFT(x) (((x) >> S_PKTSHIFT) & M_PKTSHIFT)
104 
105 #define S_ONEINTMULTQ    5
106 #define V_ONEINTMULTQ(x) ((x) << S_ONEINTMULTQ)
107 #define F_ONEINTMULTQ    V_ONEINTMULTQ(1U)
108 
109 #define S_FLPICKAVAIL    4
110 #define V_FLPICKAVAIL(x) ((x) << S_FLPICKAVAIL)
111 #define F_FLPICKAVAIL    V_FLPICKAVAIL(1U)
112 
113 #define S_BIGENDIANEGRESS    3
114 #define V_BIGENDIANEGRESS(x) ((x) << S_BIGENDIANEGRESS)
115 #define F_BIGENDIANEGRESS    V_BIGENDIANEGRESS(1U)
116 
117 #define S_BIGENDIANINGRESS    2
118 #define V_BIGENDIANINGRESS(x) ((x) << S_BIGENDIANINGRESS)
119 #define F_BIGENDIANINGRESS    V_BIGENDIANINGRESS(1U)
120 
121 #define S_ISCSICOALESCING    1
122 #define V_ISCSICOALESCING(x) ((x) << S_ISCSICOALESCING)
123 #define F_ISCSICOALESCING    V_ISCSICOALESCING(1U)
124 
125 #define S_GLOBALENABLE    0
126 #define V_GLOBALENABLE(x) ((x) << S_GLOBALENABLE)
127 #define F_GLOBALENABLE    V_GLOBALENABLE(1U)
128 
129 #define A_SG_KDOORBELL 0x4
130 
131 #define S_SELEGRCNTX    31
132 #define V_SELEGRCNTX(x) ((x) << S_SELEGRCNTX)
133 #define F_SELEGRCNTX    V_SELEGRCNTX(1U)
134 
135 #define S_EGRCNTX    0
136 #define M_EGRCNTX    0xffff
137 #define V_EGRCNTX(x) ((x) << S_EGRCNTX)
138 #define G_EGRCNTX(x) (((x) >> S_EGRCNTX) & M_EGRCNTX)
139 
140 #define A_SG_GTS 0x8
141 
142 #define S_RSPQ    29
143 #define M_RSPQ    0x7
144 #define V_RSPQ(x) ((x) << S_RSPQ)
145 #define G_RSPQ(x) (((x) >> S_RSPQ) & M_RSPQ)
146 
147 #define S_NEWTIMER    16
148 #define M_NEWTIMER    0x1fff
149 #define V_NEWTIMER(x) ((x) << S_NEWTIMER)
150 #define G_NEWTIMER(x) (((x) >> S_NEWTIMER) & M_NEWTIMER)
151 
152 #define S_NEWINDEX    0
153 #define M_NEWINDEX    0xffff
154 #define V_NEWINDEX(x) ((x) << S_NEWINDEX)
155 #define G_NEWINDEX(x) (((x) >> S_NEWINDEX) & M_NEWINDEX)
156 
157 #define A_SG_CONTEXT_CMD 0xc
158 
159 #define S_CONTEXT_CMD_OPCODE    28
160 #define M_CONTEXT_CMD_OPCODE    0xf
161 #define V_CONTEXT_CMD_OPCODE(x) ((x) << S_CONTEXT_CMD_OPCODE)
162 #define G_CONTEXT_CMD_OPCODE(x) (((x) >> S_CONTEXT_CMD_OPCODE) & M_CONTEXT_CMD_OPCODE)
163 
164 #define S_CONTEXT_CMD_BUSY    27
165 #define V_CONTEXT_CMD_BUSY(x) ((x) << S_CONTEXT_CMD_BUSY)
166 #define F_CONTEXT_CMD_BUSY    V_CONTEXT_CMD_BUSY(1U)
167 
168 #define S_CQ_CREDIT    20
169 #define M_CQ_CREDIT    0x7f
170 #define V_CQ_CREDIT(x) ((x) << S_CQ_CREDIT)
171 #define G_CQ_CREDIT(x) (((x) >> S_CQ_CREDIT) & M_CQ_CREDIT)
172 
173 #define S_CQ    19
174 #define V_CQ(x) ((x) << S_CQ)
175 #define F_CQ    V_CQ(1U)
176 
177 #define S_RESPONSEQ    18
178 #define V_RESPONSEQ(x) ((x) << S_RESPONSEQ)
179 #define F_RESPONSEQ    V_RESPONSEQ(1U)
180 
181 #define S_EGRESS    17
182 #define V_EGRESS(x) ((x) << S_EGRESS)
183 #define F_EGRESS    V_EGRESS(1U)
184 
185 #define S_FREELIST    16
186 #define V_FREELIST(x) ((x) << S_FREELIST)
187 #define F_FREELIST    V_FREELIST(1U)
188 
189 #define S_CONTEXT    0
190 #define M_CONTEXT    0xffff
191 #define V_CONTEXT(x) ((x) << S_CONTEXT)
192 #define G_CONTEXT(x) (((x) >> S_CONTEXT) & M_CONTEXT)
193 
194 #define A_SG_CONTEXT_DATA0 0x10
195 #define A_SG_CONTEXT_DATA1 0x14
196 #define A_SG_CONTEXT_DATA2 0x18
197 #define A_SG_CONTEXT_DATA3 0x1c
198 #define A_SG_CONTEXT_MASK0 0x20
199 #define A_SG_CONTEXT_MASK1 0x24
200 #define A_SG_CONTEXT_MASK2 0x28
201 #define A_SG_CONTEXT_MASK3 0x2c
202 #define A_SG_RSPQ_CREDIT_RETURN 0x30
203 
204 #define S_CREDITS    0
205 #define M_CREDITS    0xffff
206 #define V_CREDITS(x) ((x) << S_CREDITS)
207 #define G_CREDITS(x) (((x) >> S_CREDITS) & M_CREDITS)
208 
209 #define A_SG_DATA_INTR 0x34
210 
211 #define S_ERRINTR    31
212 #define V_ERRINTR(x) ((x) << S_ERRINTR)
213 #define F_ERRINTR    V_ERRINTR(1U)
214 
215 #define S_DATAINTR    0
216 #define M_DATAINTR    0xff
217 #define V_DATAINTR(x) ((x) << S_DATAINTR)
218 #define G_DATAINTR(x) (((x) >> S_DATAINTR) & M_DATAINTR)
219 
220 #define A_SG_HI_DRB_HI_THRSH 0x38
221 
222 #define S_HIDRBHITHRSH    0
223 #define M_HIDRBHITHRSH    0x3ff
224 #define V_HIDRBHITHRSH(x) ((x) << S_HIDRBHITHRSH)
225 #define G_HIDRBHITHRSH(x) (((x) >> S_HIDRBHITHRSH) & M_HIDRBHITHRSH)
226 
227 #define A_SG_HI_DRB_LO_THRSH 0x3c
228 
229 #define S_HIDRBLOTHRSH    0
230 #define M_HIDRBLOTHRSH    0x3ff
231 #define V_HIDRBLOTHRSH(x) ((x) << S_HIDRBLOTHRSH)
232 #define G_HIDRBLOTHRSH(x) (((x) >> S_HIDRBLOTHRSH) & M_HIDRBLOTHRSH)
233 
234 #define A_SG_LO_DRB_HI_THRSH 0x40
235 
236 #define S_LODRBHITHRSH    0
237 #define M_LODRBHITHRSH    0x3ff
238 #define V_LODRBHITHRSH(x) ((x) << S_LODRBHITHRSH)
239 #define G_LODRBHITHRSH(x) (((x) >> S_LODRBHITHRSH) & M_LODRBHITHRSH)
240 
241 #define A_SG_LO_DRB_LO_THRSH 0x44
242 
243 #define S_LODRBLOTHRSH    0
244 #define M_LODRBLOTHRSH    0x3ff
245 #define V_LODRBLOTHRSH(x) ((x) << S_LODRBLOTHRSH)
246 #define G_LODRBLOTHRSH(x) (((x) >> S_LODRBLOTHRSH) & M_LODRBLOTHRSH)
247 
248 #define A_SG_ONE_INT_MULT_Q_COALESCING_TIMER 0x48
249 #define A_SG_RSPQ_FL_STATUS 0x4c
250 
251 #define S_RSPQ0STARVED    0
252 #define V_RSPQ0STARVED(x) ((x) << S_RSPQ0STARVED)
253 #define F_RSPQ0STARVED    V_RSPQ0STARVED(1U)
254 
255 #define S_RSPQ1STARVED    1
256 #define V_RSPQ1STARVED(x) ((x) << S_RSPQ1STARVED)
257 #define F_RSPQ1STARVED    V_RSPQ1STARVED(1U)
258 
259 #define S_RSPQ2STARVED    2
260 #define V_RSPQ2STARVED(x) ((x) << S_RSPQ2STARVED)
261 #define F_RSPQ2STARVED    V_RSPQ2STARVED(1U)
262 
263 #define S_RSPQ3STARVED    3
264 #define V_RSPQ3STARVED(x) ((x) << S_RSPQ3STARVED)
265 #define F_RSPQ3STARVED    V_RSPQ3STARVED(1U)
266 
267 #define S_RSPQ4STARVED    4
268 #define V_RSPQ4STARVED(x) ((x) << S_RSPQ4STARVED)
269 #define F_RSPQ4STARVED    V_RSPQ4STARVED(1U)
270 
271 #define S_RSPQ5STARVED    5
272 #define V_RSPQ5STARVED(x) ((x) << S_RSPQ5STARVED)
273 #define F_RSPQ5STARVED    V_RSPQ5STARVED(1U)
274 
275 #define S_RSPQ6STARVED    6
276 #define V_RSPQ6STARVED(x) ((x) << S_RSPQ6STARVED)
277 #define F_RSPQ6STARVED    V_RSPQ6STARVED(1U)
278 
279 #define S_RSPQ7STARVED    7
280 #define V_RSPQ7STARVED(x) ((x) << S_RSPQ7STARVED)
281 #define F_RSPQ7STARVED    V_RSPQ7STARVED(1U)
282 
283 #define S_RSPQ0DISABLED    8
284 #define V_RSPQ0DISABLED(x) ((x) << S_RSPQ0DISABLED)
285 #define F_RSPQ0DISABLED    V_RSPQ0DISABLED(1U)
286 
287 #define S_RSPQ1DISABLED    9
288 #define V_RSPQ1DISABLED(x) ((x) << S_RSPQ1DISABLED)
289 #define F_RSPQ1DISABLED    V_RSPQ1DISABLED(1U)
290 
291 #define S_RSPQ2DISABLED    10
292 #define V_RSPQ2DISABLED(x) ((x) << S_RSPQ2DISABLED)
293 #define F_RSPQ2DISABLED    V_RSPQ2DISABLED(1U)
294 
295 #define S_RSPQ3DISABLED    11
296 #define V_RSPQ3DISABLED(x) ((x) << S_RSPQ3DISABLED)
297 #define F_RSPQ3DISABLED    V_RSPQ3DISABLED(1U)
298 
299 #define S_RSPQ4DISABLED    12
300 #define V_RSPQ4DISABLED(x) ((x) << S_RSPQ4DISABLED)
301 #define F_RSPQ4DISABLED    V_RSPQ4DISABLED(1U)
302 
303 #define S_RSPQ5DISABLED    13
304 #define V_RSPQ5DISABLED(x) ((x) << S_RSPQ5DISABLED)
305 #define F_RSPQ5DISABLED    V_RSPQ5DISABLED(1U)
306 
307 #define S_RSPQ6DISABLED    14
308 #define V_RSPQ6DISABLED(x) ((x) << S_RSPQ6DISABLED)
309 #define F_RSPQ6DISABLED    V_RSPQ6DISABLED(1U)
310 
311 #define S_RSPQ7DISABLED    15
312 #define V_RSPQ7DISABLED(x) ((x) << S_RSPQ7DISABLED)
313 #define F_RSPQ7DISABLED    V_RSPQ7DISABLED(1U)
314 
315 #define S_FL0EMPTY    16
316 #define V_FL0EMPTY(x) ((x) << S_FL0EMPTY)
317 #define F_FL0EMPTY    V_FL0EMPTY(1U)
318 
319 #define S_FL1EMPTY    17
320 #define V_FL1EMPTY(x) ((x) << S_FL1EMPTY)
321 #define F_FL1EMPTY    V_FL1EMPTY(1U)
322 
323 #define S_FL2EMPTY    18
324 #define V_FL2EMPTY(x) ((x) << S_FL2EMPTY)
325 #define F_FL2EMPTY    V_FL2EMPTY(1U)
326 
327 #define S_FL3EMPTY    19
328 #define V_FL3EMPTY(x) ((x) << S_FL3EMPTY)
329 #define F_FL3EMPTY    V_FL3EMPTY(1U)
330 
331 #define S_FL4EMPTY    20
332 #define V_FL4EMPTY(x) ((x) << S_FL4EMPTY)
333 #define F_FL4EMPTY    V_FL4EMPTY(1U)
334 
335 #define S_FL5EMPTY    21
336 #define V_FL5EMPTY(x) ((x) << S_FL5EMPTY)
337 #define F_FL5EMPTY    V_FL5EMPTY(1U)
338 
339 #define S_FL6EMPTY    22
340 #define V_FL6EMPTY(x) ((x) << S_FL6EMPTY)
341 #define F_FL6EMPTY    V_FL6EMPTY(1U)
342 
343 #define S_FL7EMPTY    23
344 #define V_FL7EMPTY(x) ((x) << S_FL7EMPTY)
345 #define F_FL7EMPTY    V_FL7EMPTY(1U)
346 
347 #define S_FL8EMPTY    24
348 #define V_FL8EMPTY(x) ((x) << S_FL8EMPTY)
349 #define F_FL8EMPTY    V_FL8EMPTY(1U)
350 
351 #define S_FL9EMPTY    25
352 #define V_FL9EMPTY(x) ((x) << S_FL9EMPTY)
353 #define F_FL9EMPTY    V_FL9EMPTY(1U)
354 
355 #define S_FL10EMPTY    26
356 #define V_FL10EMPTY(x) ((x) << S_FL10EMPTY)
357 #define F_FL10EMPTY    V_FL10EMPTY(1U)
358 
359 #define S_FL11EMPTY    27
360 #define V_FL11EMPTY(x) ((x) << S_FL11EMPTY)
361 #define F_FL11EMPTY    V_FL11EMPTY(1U)
362 
363 #define S_FL12EMPTY    28
364 #define V_FL12EMPTY(x) ((x) << S_FL12EMPTY)
365 #define F_FL12EMPTY    V_FL12EMPTY(1U)
366 
367 #define S_FL13EMPTY    29
368 #define V_FL13EMPTY(x) ((x) << S_FL13EMPTY)
369 #define F_FL13EMPTY    V_FL13EMPTY(1U)
370 
371 #define S_FL14EMPTY    30
372 #define V_FL14EMPTY(x) ((x) << S_FL14EMPTY)
373 #define F_FL14EMPTY    V_FL14EMPTY(1U)
374 
375 #define S_FL15EMPTY    31
376 #define V_FL15EMPTY(x) ((x) << S_FL15EMPTY)
377 #define F_FL15EMPTY    V_FL15EMPTY(1U)
378 
379 #define A_SG_EGR_PRI_CNT 0x50
380 
381 #define S_EGRERROPCODE    24
382 #define M_EGRERROPCODE    0xff
383 #define V_EGRERROPCODE(x) ((x) << S_EGRERROPCODE)
384 #define G_EGRERROPCODE(x) (((x) >> S_EGRERROPCODE) & M_EGRERROPCODE)
385 
386 #define S_EGRHIOPCODE    16
387 #define M_EGRHIOPCODE    0xff
388 #define V_EGRHIOPCODE(x) ((x) << S_EGRHIOPCODE)
389 #define G_EGRHIOPCODE(x) (((x) >> S_EGRHIOPCODE) & M_EGRHIOPCODE)
390 
391 #define S_EGRLOOPCODE    8
392 #define M_EGRLOOPCODE    0xff
393 #define V_EGRLOOPCODE(x) ((x) << S_EGRLOOPCODE)
394 #define G_EGRLOOPCODE(x) (((x) >> S_EGRLOOPCODE) & M_EGRLOOPCODE)
395 
396 #define S_EGRPRICNT    0
397 #define M_EGRPRICNT    0x1f
398 #define V_EGRPRICNT(x) ((x) << S_EGRPRICNT)
399 #define G_EGRPRICNT(x) (((x) >> S_EGRPRICNT) & M_EGRPRICNT)
400 
401 #define A_SG_EGR_RCQ_DRB_THRSH 0x54
402 
403 #define S_HIRCQDRBTHRSH    16
404 #define M_HIRCQDRBTHRSH    0x7ff
405 #define V_HIRCQDRBTHRSH(x) ((x) << S_HIRCQDRBTHRSH)
406 #define G_HIRCQDRBTHRSH(x) (((x) >> S_HIRCQDRBTHRSH) & M_HIRCQDRBTHRSH)
407 
408 #define S_LORCQDRBTHRSH    0
409 #define M_LORCQDRBTHRSH    0x7ff
410 #define V_LORCQDRBTHRSH(x) ((x) << S_LORCQDRBTHRSH)
411 #define G_LORCQDRBTHRSH(x) (((x) >> S_LORCQDRBTHRSH) & M_LORCQDRBTHRSH)
412 
413 #define A_SG_EGR_CNTX_BADDR 0x58
414 
415 #define S_EGRCNTXBADDR    5
416 #define M_EGRCNTXBADDR    0x7ffffff
417 #define V_EGRCNTXBADDR(x) ((x) << S_EGRCNTXBADDR)
418 #define G_EGRCNTXBADDR(x) (((x) >> S_EGRCNTXBADDR) & M_EGRCNTXBADDR)
419 
420 #define A_SG_INT_CAUSE 0x5c
421 
422 #define S_HIRCQPARITYERROR    31
423 #define V_HIRCQPARITYERROR(x) ((x) << S_HIRCQPARITYERROR)
424 #define F_HIRCQPARITYERROR    V_HIRCQPARITYERROR(1U)
425 
426 #define S_LORCQPARITYERROR    30
427 #define V_LORCQPARITYERROR(x) ((x) << S_LORCQPARITYERROR)
428 #define F_LORCQPARITYERROR    V_LORCQPARITYERROR(1U)
429 
430 #define S_HIDRBPARITYERROR    29
431 #define V_HIDRBPARITYERROR(x) ((x) << S_HIDRBPARITYERROR)
432 #define F_HIDRBPARITYERROR    V_HIDRBPARITYERROR(1U)
433 
434 #define S_LODRBPARITYERROR    28
435 #define V_LODRBPARITYERROR(x) ((x) << S_LODRBPARITYERROR)
436 #define F_LODRBPARITYERROR    V_LODRBPARITYERROR(1U)
437 
438 #define S_FLPARITYERROR    22
439 #define M_FLPARITYERROR    0x3f
440 #define V_FLPARITYERROR(x) ((x) << S_FLPARITYERROR)
441 #define G_FLPARITYERROR(x) (((x) >> S_FLPARITYERROR) & M_FLPARITYERROR)
442 
443 #define S_ITPARITYERROR    20
444 #define M_ITPARITYERROR    0x3
445 #define V_ITPARITYERROR(x) ((x) << S_ITPARITYERROR)
446 #define G_ITPARITYERROR(x) (((x) >> S_ITPARITYERROR) & M_ITPARITYERROR)
447 
448 #define S_IRPARITYERROR    19
449 #define V_IRPARITYERROR(x) ((x) << S_IRPARITYERROR)
450 #define F_IRPARITYERROR    V_IRPARITYERROR(1U)
451 
452 #define S_RCPARITYERROR    18
453 #define V_RCPARITYERROR(x) ((x) << S_RCPARITYERROR)
454 #define F_RCPARITYERROR    V_RCPARITYERROR(1U)
455 
456 #define S_OCPARITYERROR    17
457 #define V_OCPARITYERROR(x) ((x) << S_OCPARITYERROR)
458 #define F_OCPARITYERROR    V_OCPARITYERROR(1U)
459 
460 #define S_CPPARITYERROR    16
461 #define V_CPPARITYERROR(x) ((x) << S_CPPARITYERROR)
462 #define F_CPPARITYERROR    V_CPPARITYERROR(1U)
463 
464 #define S_R_REQ_FRAMINGERROR    15
465 #define V_R_REQ_FRAMINGERROR(x) ((x) << S_R_REQ_FRAMINGERROR)
466 #define F_R_REQ_FRAMINGERROR    V_R_REQ_FRAMINGERROR(1U)
467 
468 #define S_UC_REQ_FRAMINGERROR    14
469 #define V_UC_REQ_FRAMINGERROR(x) ((x) << S_UC_REQ_FRAMINGERROR)
470 #define F_UC_REQ_FRAMINGERROR    V_UC_REQ_FRAMINGERROR(1U)
471 
472 #define S_HICTLDRBDROPERR    13
473 #define V_HICTLDRBDROPERR(x) ((x) << S_HICTLDRBDROPERR)
474 #define F_HICTLDRBDROPERR    V_HICTLDRBDROPERR(1U)
475 
476 #define S_LOCTLDRBDROPERR    12
477 #define V_LOCTLDRBDROPERR(x) ((x) << S_LOCTLDRBDROPERR)
478 #define F_LOCTLDRBDROPERR    V_LOCTLDRBDROPERR(1U)
479 
480 #define S_HIPIODRBDROPERR    11
481 #define V_HIPIODRBDROPERR(x) ((x) << S_HIPIODRBDROPERR)
482 #define F_HIPIODRBDROPERR    V_HIPIODRBDROPERR(1U)
483 
484 #define S_LOPIODRBDROPERR    10
485 #define V_LOPIODRBDROPERR(x) ((x) << S_LOPIODRBDROPERR)
486 #define F_LOPIODRBDROPERR    V_LOPIODRBDROPERR(1U)
487 
488 #define S_HICRDTUNDFLOWERR    9
489 #define V_HICRDTUNDFLOWERR(x) ((x) << S_HICRDTUNDFLOWERR)
490 #define F_HICRDTUNDFLOWERR    V_HICRDTUNDFLOWERR(1U)
491 
492 #define S_LOCRDTUNDFLOWERR    8
493 #define V_LOCRDTUNDFLOWERR(x) ((x) << S_LOCRDTUNDFLOWERR)
494 #define F_LOCRDTUNDFLOWERR    V_LOCRDTUNDFLOWERR(1U)
495 
496 #define S_HIPRIORITYDBFULL    7
497 #define V_HIPRIORITYDBFULL(x) ((x) << S_HIPRIORITYDBFULL)
498 #define F_HIPRIORITYDBFULL    V_HIPRIORITYDBFULL(1U)
499 
500 #define S_HIPRIORITYDBEMPTY    6
501 #define V_HIPRIORITYDBEMPTY(x) ((x) << S_HIPRIORITYDBEMPTY)
502 #define F_HIPRIORITYDBEMPTY    V_HIPRIORITYDBEMPTY(1U)
503 
504 #define S_LOPRIORITYDBFULL    5
505 #define V_LOPRIORITYDBFULL(x) ((x) << S_LOPRIORITYDBFULL)
506 #define F_LOPRIORITYDBFULL    V_LOPRIORITYDBFULL(1U)
507 
508 #define S_LOPRIORITYDBEMPTY    4
509 #define V_LOPRIORITYDBEMPTY(x) ((x) << S_LOPRIORITYDBEMPTY)
510 #define F_LOPRIORITYDBEMPTY    V_LOPRIORITYDBEMPTY(1U)
511 
512 #define S_RSPQDISABLED    3
513 #define V_RSPQDISABLED(x) ((x) << S_RSPQDISABLED)
514 #define F_RSPQDISABLED    V_RSPQDISABLED(1U)
515 
516 #define S_RSPQCREDITOVERFOW    2
517 #define V_RSPQCREDITOVERFOW(x) ((x) << S_RSPQCREDITOVERFOW)
518 #define F_RSPQCREDITOVERFOW    V_RSPQCREDITOVERFOW(1U)
519 
520 #define S_FLEMPTY    1
521 #define V_FLEMPTY(x) ((x) << S_FLEMPTY)
522 #define F_FLEMPTY    V_FLEMPTY(1U)
523 
524 #define S_RSPQSTARVE    0
525 #define V_RSPQSTARVE(x) ((x) << S_RSPQSTARVE)
526 #define F_RSPQSTARVE    V_RSPQSTARVE(1U)
527 
528 #define A_SG_INT_ENABLE 0x60
529 #define A_SG_CMDQ_CREDIT_TH 0x64
530 
531 #define S_TIMEOUT    8
532 #define M_TIMEOUT    0xffffff
533 #define V_TIMEOUT(x) ((x) << S_TIMEOUT)
534 #define G_TIMEOUT(x) (((x) >> S_TIMEOUT) & M_TIMEOUT)
535 
536 #define S_THRESHOLD    0
537 #define M_THRESHOLD    0xff
538 #define V_THRESHOLD(x) ((x) << S_THRESHOLD)
539 #define G_THRESHOLD(x) (((x) >> S_THRESHOLD) & M_THRESHOLD)
540 
541 #define A_SG_TIMER_TICK 0x68
542 #define A_SG_CQ_CONTEXT_BADDR 0x6c
543 
544 #define S_BASEADDR    5
545 #define M_BASEADDR    0x7ffffff
546 #define V_BASEADDR(x) ((x) << S_BASEADDR)
547 #define G_BASEADDR(x) (((x) >> S_BASEADDR) & M_BASEADDR)
548 
549 #define A_SG_OCO_BASE 0x70
550 
551 #define S_BASE1    16
552 #define M_BASE1    0xffff
553 #define V_BASE1(x) ((x) << S_BASE1)
554 #define G_BASE1(x) (((x) >> S_BASE1) & M_BASE1)
555 
556 #define S_BASE0    0
557 #define M_BASE0    0xffff
558 #define V_BASE0(x) ((x) << S_BASE0)
559 #define G_BASE0(x) (((x) >> S_BASE0) & M_BASE0)
560 
561 #define A_SG_DRB_PRI_THRESH 0x74
562 
563 #define S_DRBPRITHRSH    0
564 #define M_DRBPRITHRSH    0xffff
565 #define V_DRBPRITHRSH(x) ((x) << S_DRBPRITHRSH)
566 #define G_DRBPRITHRSH(x) (((x) >> S_DRBPRITHRSH) & M_DRBPRITHRSH)
567 
568 #define A_SG_DEBUG_INDEX 0x78
569 #define A_SG_DEBUG_DATA 0x7c
570 
571 /* registers for module PCIX1 */
572 #define PCIX1_BASE_ADDR 0x80
573 
574 #define A_PCIX_INT_ENABLE 0x80
575 
576 #define S_MSIXPARERR    22
577 #define M_MSIXPARERR    0x7
578 #define V_MSIXPARERR(x) ((x) << S_MSIXPARERR)
579 #define G_MSIXPARERR(x) (((x) >> S_MSIXPARERR) & M_MSIXPARERR)
580 
581 #define S_CFPARERR    18
582 #define M_CFPARERR    0xf
583 #define V_CFPARERR(x) ((x) << S_CFPARERR)
584 #define G_CFPARERR(x) (((x) >> S_CFPARERR) & M_CFPARERR)
585 
586 #define S_RFPARERR    14
587 #define M_RFPARERR    0xf
588 #define V_RFPARERR(x) ((x) << S_RFPARERR)
589 #define G_RFPARERR(x) (((x) >> S_RFPARERR) & M_RFPARERR)
590 
591 #define S_WFPARERR    12
592 #define M_WFPARERR    0x3
593 #define V_WFPARERR(x) ((x) << S_WFPARERR)
594 #define G_WFPARERR(x) (((x) >> S_WFPARERR) & M_WFPARERR)
595 
596 #define S_PIOPARERR    11
597 #define V_PIOPARERR(x) ((x) << S_PIOPARERR)
598 #define F_PIOPARERR    V_PIOPARERR(1U)
599 
600 #define S_DETUNCECCERR    10
601 #define V_DETUNCECCERR(x) ((x) << S_DETUNCECCERR)
602 #define F_DETUNCECCERR    V_DETUNCECCERR(1U)
603 
604 #define S_DETCORECCERR    9
605 #define V_DETCORECCERR(x) ((x) << S_DETCORECCERR)
606 #define F_DETCORECCERR    V_DETCORECCERR(1U)
607 
608 #define S_RCVSPLCMPERR    8
609 #define V_RCVSPLCMPERR(x) ((x) << S_RCVSPLCMPERR)
610 #define F_RCVSPLCMPERR    V_RCVSPLCMPERR(1U)
611 
612 #define S_UNXSPLCMP    7
613 #define V_UNXSPLCMP(x) ((x) << S_UNXSPLCMP)
614 #define F_UNXSPLCMP    V_UNXSPLCMP(1U)
615 
616 #define S_SPLCMPDIS    6
617 #define V_SPLCMPDIS(x) ((x) << S_SPLCMPDIS)
618 #define F_SPLCMPDIS    V_SPLCMPDIS(1U)
619 
620 #define S_DETPARERR    5
621 #define V_DETPARERR(x) ((x) << S_DETPARERR)
622 #define F_DETPARERR    V_DETPARERR(1U)
623 
624 #define S_SIGSYSERR    4
625 #define V_SIGSYSERR(x) ((x) << S_SIGSYSERR)
626 #define F_SIGSYSERR    V_SIGSYSERR(1U)
627 
628 #define S_RCVMSTABT    3
629 #define V_RCVMSTABT(x) ((x) << S_RCVMSTABT)
630 #define F_RCVMSTABT    V_RCVMSTABT(1U)
631 
632 #define S_RCVTARABT    2
633 #define V_RCVTARABT(x) ((x) << S_RCVTARABT)
634 #define F_RCVTARABT    V_RCVTARABT(1U)
635 
636 #define S_SIGTARABT    1
637 #define V_SIGTARABT(x) ((x) << S_SIGTARABT)
638 #define F_SIGTARABT    V_SIGTARABT(1U)
639 
640 #define S_MSTDETPARERR    0
641 #define V_MSTDETPARERR(x) ((x) << S_MSTDETPARERR)
642 #define F_MSTDETPARERR    V_MSTDETPARERR(1U)
643 
644 #define A_PCIX_INT_CAUSE 0x84
645 #define A_PCIX_CFG 0x88
646 
647 #define S_DMASTOPEN    19
648 #define V_DMASTOPEN(x) ((x) << S_DMASTOPEN)
649 #define F_DMASTOPEN    V_DMASTOPEN(1U)
650 
651 #define S_CLIDECEN    18
652 #define V_CLIDECEN(x) ((x) << S_CLIDECEN)
653 #define F_CLIDECEN    V_CLIDECEN(1U)
654 
655 #define S_LATTMRDIS    17
656 #define V_LATTMRDIS(x) ((x) << S_LATTMRDIS)
657 #define F_LATTMRDIS    V_LATTMRDIS(1U)
658 
659 #define S_LOWPWREN    16
660 #define V_LOWPWREN(x) ((x) << S_LOWPWREN)
661 #define F_LOWPWREN    V_LOWPWREN(1U)
662 
663 #define S_ASYNCINTVEC    11
664 #define M_ASYNCINTVEC    0x1f
665 #define V_ASYNCINTVEC(x) ((x) << S_ASYNCINTVEC)
666 #define G_ASYNCINTVEC(x) (((x) >> S_ASYNCINTVEC) & M_ASYNCINTVEC)
667 
668 #define S_MAXSPLTRNC    8
669 #define M_MAXSPLTRNC    0x7
670 #define V_MAXSPLTRNC(x) ((x) << S_MAXSPLTRNC)
671 #define G_MAXSPLTRNC(x) (((x) >> S_MAXSPLTRNC) & M_MAXSPLTRNC)
672 
673 #define S_MAXSPLTRNR    5
674 #define M_MAXSPLTRNR    0x7
675 #define V_MAXSPLTRNR(x) ((x) << S_MAXSPLTRNR)
676 #define G_MAXSPLTRNR(x) (((x) >> S_MAXSPLTRNR) & M_MAXSPLTRNR)
677 
678 #define S_MAXWRBYTECNT    3
679 #define M_MAXWRBYTECNT    0x3
680 #define V_MAXWRBYTECNT(x) ((x) << S_MAXWRBYTECNT)
681 #define G_MAXWRBYTECNT(x) (((x) >> S_MAXWRBYTECNT) & M_MAXWRBYTECNT)
682 
683 #define S_WRREQATOMICEN    2
684 #define V_WRREQATOMICEN(x) ((x) << S_WRREQATOMICEN)
685 #define F_WRREQATOMICEN    V_WRREQATOMICEN(1U)
686 
687 #define S_RSTWRMMODE    1
688 #define V_RSTWRMMODE(x) ((x) << S_RSTWRMMODE)
689 #define F_RSTWRMMODE    V_RSTWRMMODE(1U)
690 
691 #define S_PIOACK64EN    0
692 #define V_PIOACK64EN(x) ((x) << S_PIOACK64EN)
693 #define F_PIOACK64EN    V_PIOACK64EN(1U)
694 
695 #define A_PCIX_MODE 0x8c
696 
697 #define S_PCLKRANGE    6
698 #define M_PCLKRANGE    0x3
699 #define V_PCLKRANGE(x) ((x) << S_PCLKRANGE)
700 #define G_PCLKRANGE(x) (((x) >> S_PCLKRANGE) & M_PCLKRANGE)
701 
702 #define S_PCIXINITPAT    2
703 #define M_PCIXINITPAT    0xf
704 #define V_PCIXINITPAT(x) ((x) << S_PCIXINITPAT)
705 #define G_PCIXINITPAT(x) (((x) >> S_PCIXINITPAT) & M_PCIXINITPAT)
706 
707 #define S_66MHZ    1
708 #define V_66MHZ(x) ((x) << S_66MHZ)
709 #define F_66MHZ    V_66MHZ(1U)
710 
711 #define S_64BIT    0
712 #define V_64BIT(x) ((x) << S_64BIT)
713 #define F_64BIT    V_64BIT(1U)
714 
715 #define A_PCIX_CAL 0x90
716 
717 #define S_BUSY    31
718 #define V_BUSY(x) ((x) << S_BUSY)
719 #define F_BUSY    V_BUSY(1U)
720 
721 #define S_PERCALDIV    22
722 #define M_PERCALDIV    0xff
723 #define V_PERCALDIV(x) ((x) << S_PERCALDIV)
724 #define G_PERCALDIV(x) (((x) >> S_PERCALDIV) & M_PERCALDIV)
725 
726 #define S_PERCALEN    21
727 #define V_PERCALEN(x) ((x) << S_PERCALEN)
728 #define F_PERCALEN    V_PERCALEN(1U)
729 
730 #define S_SGLCALEN    20
731 #define V_SGLCALEN(x) ((x) << S_SGLCALEN)
732 #define F_SGLCALEN    V_SGLCALEN(1U)
733 
734 #define S_ZINUPDMODE    19
735 #define V_ZINUPDMODE(x) ((x) << S_ZINUPDMODE)
736 #define F_ZINUPDMODE    V_ZINUPDMODE(1U)
737 
738 #define S_ZINSEL    18
739 #define V_ZINSEL(x) ((x) << S_ZINSEL)
740 #define F_ZINSEL    V_ZINSEL(1U)
741 
742 #define S_ZPDMAN    15
743 #define M_ZPDMAN    0x7
744 #define V_ZPDMAN(x) ((x) << S_ZPDMAN)
745 #define G_ZPDMAN(x) (((x) >> S_ZPDMAN) & M_ZPDMAN)
746 
747 #define S_ZPUMAN    12
748 #define M_ZPUMAN    0x7
749 #define V_ZPUMAN(x) ((x) << S_ZPUMAN)
750 #define G_ZPUMAN(x) (((x) >> S_ZPUMAN) & M_ZPUMAN)
751 
752 #define S_ZPDOUT    9
753 #define M_ZPDOUT    0x7
754 #define V_ZPDOUT(x) ((x) << S_ZPDOUT)
755 #define G_ZPDOUT(x) (((x) >> S_ZPDOUT) & M_ZPDOUT)
756 
757 #define S_ZPUOUT    6
758 #define M_ZPUOUT    0x7
759 #define V_ZPUOUT(x) ((x) << S_ZPUOUT)
760 #define G_ZPUOUT(x) (((x) >> S_ZPUOUT) & M_ZPUOUT)
761 
762 #define S_ZPDIN    3
763 #define M_ZPDIN    0x7
764 #define V_ZPDIN(x) ((x) << S_ZPDIN)
765 #define G_ZPDIN(x) (((x) >> S_ZPDIN) & M_ZPDIN)
766 
767 #define S_ZPUIN    0
768 #define M_ZPUIN    0x7
769 #define V_ZPUIN(x) ((x) << S_ZPUIN)
770 #define G_ZPUIN(x) (((x) >> S_ZPUIN) & M_ZPUIN)
771 
772 #define A_PCIX_WOL 0x94
773 
774 #define S_WAKEUP1    3
775 #define V_WAKEUP1(x) ((x) << S_WAKEUP1)
776 #define F_WAKEUP1    V_WAKEUP1(1U)
777 
778 #define S_WAKEUP0    2
779 #define V_WAKEUP0(x) ((x) << S_WAKEUP0)
780 #define F_WAKEUP0    V_WAKEUP0(1U)
781 
782 #define S_SLEEPMODE1    1
783 #define V_SLEEPMODE1(x) ((x) << S_SLEEPMODE1)
784 #define F_SLEEPMODE1    V_SLEEPMODE1(1U)
785 
786 #define S_SLEEPMODE0    0
787 #define V_SLEEPMODE0(x) ((x) << S_SLEEPMODE0)
788 #define F_SLEEPMODE0    V_SLEEPMODE0(1U)
789 
790 #define A_PCIX_STAT0 0x98
791 
792 #define S_PIOREQFIFOLEVEL    26
793 #define M_PIOREQFIFOLEVEL    0x3f
794 #define V_PIOREQFIFOLEVEL(x) ((x) << S_PIOREQFIFOLEVEL)
795 #define G_PIOREQFIFOLEVEL(x) (((x) >> S_PIOREQFIFOLEVEL) & M_PIOREQFIFOLEVEL)
796 
797 #define S_RFINIST    24
798 #define M_RFINIST    0x3
799 #define V_RFINIST(x) ((x) << S_RFINIST)
800 #define G_RFINIST(x) (((x) >> S_RFINIST) & M_RFINIST)
801 
802 #define S_RFRESPRDST    22
803 #define M_RFRESPRDST    0x3
804 #define V_RFRESPRDST(x) ((x) << S_RFRESPRDST)
805 #define G_RFRESPRDST(x) (((x) >> S_RFRESPRDST) & M_RFRESPRDST)
806 
807 #define S_TARCST    19
808 #define M_TARCST    0x7
809 #define V_TARCST(x) ((x) << S_TARCST)
810 #define G_TARCST(x) (((x) >> S_TARCST) & M_TARCST)
811 
812 #define S_TARXST    16
813 #define M_TARXST    0x7
814 #define V_TARXST(x) ((x) << S_TARXST)
815 #define G_TARXST(x) (((x) >> S_TARXST) & M_TARXST)
816 
817 #define S_WFREQWRST    13
818 #define M_WFREQWRST    0x7
819 #define V_WFREQWRST(x) ((x) << S_WFREQWRST)
820 #define G_WFREQWRST(x) (((x) >> S_WFREQWRST) & M_WFREQWRST)
821 
822 #define S_WFRESPFIFOEMPTY    12
823 #define V_WFRESPFIFOEMPTY(x) ((x) << S_WFRESPFIFOEMPTY)
824 #define F_WFRESPFIFOEMPTY    V_WFRESPFIFOEMPTY(1U)
825 
826 #define S_WFREQFIFOEMPTY    11
827 #define V_WFREQFIFOEMPTY(x) ((x) << S_WFREQFIFOEMPTY)
828 #define F_WFREQFIFOEMPTY    V_WFREQFIFOEMPTY(1U)
829 
830 #define S_RFRESPFIFOEMPTY    10
831 #define V_RFRESPFIFOEMPTY(x) ((x) << S_RFRESPFIFOEMPTY)
832 #define F_RFRESPFIFOEMPTY    V_RFRESPFIFOEMPTY(1U)
833 
834 #define S_RFREQFIFOEMPTY    9
835 #define V_RFREQFIFOEMPTY(x) ((x) << S_RFREQFIFOEMPTY)
836 #define F_RFREQFIFOEMPTY    V_RFREQFIFOEMPTY(1U)
837 
838 #define S_PIORESPFIFOLEVEL    7
839 #define M_PIORESPFIFOLEVEL    0x3
840 #define V_PIORESPFIFOLEVEL(x) ((x) << S_PIORESPFIFOLEVEL)
841 #define G_PIORESPFIFOLEVEL(x) (((x) >> S_PIORESPFIFOLEVEL) & M_PIORESPFIFOLEVEL)
842 
843 #define S_CFRESPFIFOEMPTY    6
844 #define V_CFRESPFIFOEMPTY(x) ((x) << S_CFRESPFIFOEMPTY)
845 #define F_CFRESPFIFOEMPTY    V_CFRESPFIFOEMPTY(1U)
846 
847 #define S_CFREQFIFOEMPTY    5
848 #define V_CFREQFIFOEMPTY(x) ((x) << S_CFREQFIFOEMPTY)
849 #define F_CFREQFIFOEMPTY    V_CFREQFIFOEMPTY(1U)
850 
851 #define S_VPDRESPFIFOEMPTY    4
852 #define V_VPDRESPFIFOEMPTY(x) ((x) << S_VPDRESPFIFOEMPTY)
853 #define F_VPDRESPFIFOEMPTY    V_VPDRESPFIFOEMPTY(1U)
854 
855 #define S_VPDREQFIFOEMPTY    3
856 #define V_VPDREQFIFOEMPTY(x) ((x) << S_VPDREQFIFOEMPTY)
857 #define F_VPDREQFIFOEMPTY    V_VPDREQFIFOEMPTY(1U)
858 
859 #define S_PIO_RSPPND    2
860 #define V_PIO_RSPPND(x) ((x) << S_PIO_RSPPND)
861 #define F_PIO_RSPPND    V_PIO_RSPPND(1U)
862 
863 #define S_DLYTRNPND    1
864 #define V_DLYTRNPND(x) ((x) << S_DLYTRNPND)
865 #define F_DLYTRNPND    V_DLYTRNPND(1U)
866 
867 #define S_SPLTRNPND    0
868 #define V_SPLTRNPND(x) ((x) << S_SPLTRNPND)
869 #define F_SPLTRNPND    V_SPLTRNPND(1U)
870 
871 #define A_PCIX_STAT1 0x9c
872 
873 #define S_WFINIST    26
874 #define M_WFINIST    0xf
875 #define V_WFINIST(x) ((x) << S_WFINIST)
876 #define G_WFINIST(x) (((x) >> S_WFINIST) & M_WFINIST)
877 
878 #define S_ARBST    23
879 #define M_ARBST    0x7
880 #define V_ARBST(x) ((x) << S_ARBST)
881 #define G_ARBST(x) (((x) >> S_ARBST) & M_ARBST)
882 
883 #define S_PMIST    21
884 #define M_PMIST    0x3
885 #define V_PMIST(x) ((x) << S_PMIST)
886 #define G_PMIST(x) (((x) >> S_PMIST) & M_PMIST)
887 
888 #define S_CALST    19
889 #define M_CALST    0x3
890 #define V_CALST(x) ((x) << S_CALST)
891 #define G_CALST(x) (((x) >> S_CALST) & M_CALST)
892 
893 #define S_CFREQRDST    17
894 #define M_CFREQRDST    0x3
895 #define V_CFREQRDST(x) ((x) << S_CFREQRDST)
896 #define G_CFREQRDST(x) (((x) >> S_CFREQRDST) & M_CFREQRDST)
897 
898 #define S_CFINIST    15
899 #define M_CFINIST    0x3
900 #define V_CFINIST(x) ((x) << S_CFINIST)
901 #define G_CFINIST(x) (((x) >> S_CFINIST) & M_CFINIST)
902 
903 #define S_CFRESPRDST    13
904 #define M_CFRESPRDST    0x3
905 #define V_CFRESPRDST(x) ((x) << S_CFRESPRDST)
906 #define G_CFRESPRDST(x) (((x) >> S_CFRESPRDST) & M_CFRESPRDST)
907 
908 #define S_INICST    10
909 #define M_INICST    0x7
910 #define V_INICST(x) ((x) << S_INICST)
911 #define G_INICST(x) (((x) >> S_INICST) & M_INICST)
912 
913 #define S_INIXST    7
914 #define M_INIXST    0x7
915 #define V_INIXST(x) ((x) << S_INIXST)
916 #define G_INIXST(x) (((x) >> S_INIXST) & M_INIXST)
917 
918 #define S_INTST    4
919 #define M_INTST    0x7
920 #define V_INTST(x) ((x) << S_INTST)
921 #define G_INTST(x) (((x) >> S_INTST) & M_INTST)
922 
923 #define S_PIOST    2
924 #define M_PIOST    0x3
925 #define V_PIOST(x) ((x) << S_PIOST)
926 #define G_PIOST(x) (((x) >> S_PIOST) & M_PIOST)
927 
928 #define S_RFREQRDST    0
929 #define M_RFREQRDST    0x3
930 #define V_RFREQRDST(x) ((x) << S_RFREQRDST)
931 #define G_RFREQRDST(x) (((x) >> S_RFREQRDST) & M_RFREQRDST)
932 
933 /* registers for module PCIE0 */
934 #define PCIE0_BASE_ADDR 0x80
935 
936 #define A_PCIE_INT_ENABLE 0x80
937 
938 #define S_BISTERR    19
939 #define M_BISTERR    0xff
940 #define V_BISTERR(x) ((x) << S_BISTERR)
941 #define G_BISTERR(x) (((x) >> S_BISTERR) & M_BISTERR)
942 
943 #define S_TXPARERR    18
944 #define V_TXPARERR(x) ((x) << S_TXPARERR)
945 #define F_TXPARERR    V_TXPARERR(1U)
946 
947 #define S_RXPARERR    17
948 #define V_RXPARERR(x) ((x) << S_RXPARERR)
949 #define F_RXPARERR    V_RXPARERR(1U)
950 
951 #define S_RETRYLUTPARERR    16
952 #define V_RETRYLUTPARERR(x) ((x) << S_RETRYLUTPARERR)
953 #define F_RETRYLUTPARERR    V_RETRYLUTPARERR(1U)
954 
955 #define S_RETRYBUFPARERR    15
956 #define V_RETRYBUFPARERR(x) ((x) << S_RETRYBUFPARERR)
957 #define F_RETRYBUFPARERR    V_RETRYBUFPARERR(1U)
958 
959 #define S_PCIE_MSIXPARERR    12
960 #define M_PCIE_MSIXPARERR    0x7
961 #define V_PCIE_MSIXPARERR(x) ((x) << S_PCIE_MSIXPARERR)
962 #define G_PCIE_MSIXPARERR(x) (((x) >> S_PCIE_MSIXPARERR) & M_PCIE_MSIXPARERR)
963 
964 #define S_PCIE_CFPARERR    11
965 #define V_PCIE_CFPARERR(x) ((x) << S_PCIE_CFPARERR)
966 #define F_PCIE_CFPARERR    V_PCIE_CFPARERR(1U)
967 
968 #define S_PCIE_RFPARERR    10
969 #define V_PCIE_RFPARERR(x) ((x) << S_PCIE_RFPARERR)
970 #define F_PCIE_RFPARERR    V_PCIE_RFPARERR(1U)
971 
972 #define S_PCIE_WFPARERR    9
973 #define V_PCIE_WFPARERR(x) ((x) << S_PCIE_WFPARERR)
974 #define F_PCIE_WFPARERR    V_PCIE_WFPARERR(1U)
975 
976 #define S_PCIE_PIOPARERR    8
977 #define V_PCIE_PIOPARERR(x) ((x) << S_PCIE_PIOPARERR)
978 #define F_PCIE_PIOPARERR    V_PCIE_PIOPARERR(1U)
979 
980 #define S_UNXSPLCPLERRC    7
981 #define V_UNXSPLCPLERRC(x) ((x) << S_UNXSPLCPLERRC)
982 #define F_UNXSPLCPLERRC    V_UNXSPLCPLERRC(1U)
983 
984 #define S_UNXSPLCPLERRR    6
985 #define V_UNXSPLCPLERRR(x) ((x) << S_UNXSPLCPLERRR)
986 #define F_UNXSPLCPLERRR    V_UNXSPLCPLERRR(1U)
987 
988 #define S_VPDADDRCHNG    5
989 #define V_VPDADDRCHNG(x) ((x) << S_VPDADDRCHNG)
990 #define F_VPDADDRCHNG    V_VPDADDRCHNG(1U)
991 
992 #define S_BUSMSTREN    4
993 #define V_BUSMSTREN(x) ((x) << S_BUSMSTREN)
994 #define F_BUSMSTREN    V_BUSMSTREN(1U)
995 
996 #define S_PMSTCHNG    3
997 #define V_PMSTCHNG(x) ((x) << S_PMSTCHNG)
998 #define F_PMSTCHNG    V_PMSTCHNG(1U)
999 
1000 #define S_PEXMSG    2
1001 #define V_PEXMSG(x) ((x) << S_PEXMSG)
1002 #define F_PEXMSG    V_PEXMSG(1U)
1003 
1004 #define S_ZEROLENRD    1
1005 #define V_ZEROLENRD(x) ((x) << S_ZEROLENRD)
1006 #define F_ZEROLENRD    V_ZEROLENRD(1U)
1007 
1008 #define S_PEXERR    0
1009 #define V_PEXERR(x) ((x) << S_PEXERR)
1010 #define F_PEXERR    V_PEXERR(1U)
1011 
1012 #define A_PCIE_INT_CAUSE 0x84
1013 #define A_PCIE_CFG 0x88
1014 
1015 #define S_PCIE_DMASTOPEN    24
1016 #define V_PCIE_DMASTOPEN(x) ((x) << S_PCIE_DMASTOPEN)
1017 #define F_PCIE_DMASTOPEN    V_PCIE_DMASTOPEN(1U)
1018 
1019 #define S_PRIORITYINTA    23
1020 #define V_PRIORITYINTA(x) ((x) << S_PRIORITYINTA)
1021 #define F_PRIORITYINTA    V_PRIORITYINTA(1U)
1022 
1023 #define S_INIFULLPKT    22
1024 #define V_INIFULLPKT(x) ((x) << S_INIFULLPKT)
1025 #define F_INIFULLPKT    V_INIFULLPKT(1U)
1026 
1027 #define S_ENABLELINKDWNDRST    21
1028 #define V_ENABLELINKDWNDRST(x) ((x) << S_ENABLELINKDWNDRST)
1029 #define F_ENABLELINKDWNDRST    V_ENABLELINKDWNDRST(1U)
1030 
1031 #define S_ENABLELINKDOWNRST    20
1032 #define V_ENABLELINKDOWNRST(x) ((x) << S_ENABLELINKDOWNRST)
1033 #define F_ENABLELINKDOWNRST    V_ENABLELINKDOWNRST(1U)
1034 
1035 #define S_ENABLEHOTRST    19
1036 #define V_ENABLEHOTRST(x) ((x) << S_ENABLEHOTRST)
1037 #define F_ENABLEHOTRST    V_ENABLEHOTRST(1U)
1038 
1039 #define S_INIWAITFORGNT    18
1040 #define V_INIWAITFORGNT(x) ((x) << S_INIWAITFORGNT)
1041 #define F_INIWAITFORGNT    V_INIWAITFORGNT(1U)
1042 
1043 #define S_INIBEDIS    17
1044 #define V_INIBEDIS(x) ((x) << S_INIBEDIS)
1045 #define F_INIBEDIS    V_INIBEDIS(1U)
1046 
1047 #define S_PCIE_CLIDECEN    16
1048 #define V_PCIE_CLIDECEN(x) ((x) << S_PCIE_CLIDECEN)
1049 #define F_PCIE_CLIDECEN    V_PCIE_CLIDECEN(1U)
1050 
1051 #define S_PCIE_MAXSPLTRNC    7
1052 #define M_PCIE_MAXSPLTRNC    0xf
1053 #define V_PCIE_MAXSPLTRNC(x) ((x) << S_PCIE_MAXSPLTRNC)
1054 #define G_PCIE_MAXSPLTRNC(x) (((x) >> S_PCIE_MAXSPLTRNC) & M_PCIE_MAXSPLTRNC)
1055 
1056 #define S_PCIE_MAXSPLTRNR    1
1057 #define M_PCIE_MAXSPLTRNR    0x3f
1058 #define V_PCIE_MAXSPLTRNR(x) ((x) << S_PCIE_MAXSPLTRNR)
1059 #define G_PCIE_MAXSPLTRNR(x) (((x) >> S_PCIE_MAXSPLTRNR) & M_PCIE_MAXSPLTRNR)
1060 
1061 #define S_CRSTWRMMODE    0
1062 #define V_CRSTWRMMODE(x) ((x) << S_CRSTWRMMODE)
1063 #define F_CRSTWRMMODE    V_CRSTWRMMODE(1U)
1064 
1065 #define A_PCIE_MODE 0x8c
1066 
1067 #define S_TAR_STATE    29
1068 #define M_TAR_STATE    0x7
1069 #define V_TAR_STATE(x) ((x) << S_TAR_STATE)
1070 #define G_TAR_STATE(x) (((x) >> S_TAR_STATE) & M_TAR_STATE)
1071 
1072 #define S_RF_STATEINI    26
1073 #define M_RF_STATEINI    0x7
1074 #define V_RF_STATEINI(x) ((x) << S_RF_STATEINI)
1075 #define G_RF_STATEINI(x) (((x) >> S_RF_STATEINI) & M_RF_STATEINI)
1076 
1077 #define S_CF_STATEINI    23
1078 #define M_CF_STATEINI    0x7
1079 #define V_CF_STATEINI(x) ((x) << S_CF_STATEINI)
1080 #define G_CF_STATEINI(x) (((x) >> S_CF_STATEINI) & M_CF_STATEINI)
1081 
1082 #define S_PIO_STATEPL    20
1083 #define M_PIO_STATEPL    0x7
1084 #define V_PIO_STATEPL(x) ((x) << S_PIO_STATEPL)
1085 #define G_PIO_STATEPL(x) (((x) >> S_PIO_STATEPL) & M_PIO_STATEPL)
1086 
1087 #define S_PIO_STATEISC    18
1088 #define M_PIO_STATEISC    0x3
1089 #define V_PIO_STATEISC(x) ((x) << S_PIO_STATEISC)
1090 #define G_PIO_STATEISC(x) (((x) >> S_PIO_STATEISC) & M_PIO_STATEISC)
1091 
1092 #define S_NUMFSTTRNSEQRX    10
1093 #define M_NUMFSTTRNSEQRX    0xff
1094 #define V_NUMFSTTRNSEQRX(x) ((x) << S_NUMFSTTRNSEQRX)
1095 #define G_NUMFSTTRNSEQRX(x) (((x) >> S_NUMFSTTRNSEQRX) & M_NUMFSTTRNSEQRX)
1096 
1097 #define S_LNKCNTLSTATE    2
1098 #define M_LNKCNTLSTATE    0xff
1099 #define V_LNKCNTLSTATE(x) ((x) << S_LNKCNTLSTATE)
1100 #define G_LNKCNTLSTATE(x) (((x) >> S_LNKCNTLSTATE) & M_LNKCNTLSTATE)
1101 
1102 #define S_VC0UP    1
1103 #define V_VC0UP(x) ((x) << S_VC0UP)
1104 #define F_VC0UP    V_VC0UP(1U)
1105 
1106 #define S_LNKINITIAL    0
1107 #define V_LNKINITIAL(x) ((x) << S_LNKINITIAL)
1108 #define F_LNKINITIAL    V_LNKINITIAL(1U)
1109 
1110 #define A_PCIE_STAT 0x90
1111 
1112 #define S_INI_STATE    28
1113 #define M_INI_STATE    0xf
1114 #define V_INI_STATE(x) ((x) << S_INI_STATE)
1115 #define G_INI_STATE(x) (((x) >> S_INI_STATE) & M_INI_STATE)
1116 
1117 #define S_WF_STATEINI    24
1118 #define M_WF_STATEINI    0xf
1119 #define V_WF_STATEINI(x) ((x) << S_WF_STATEINI)
1120 #define G_WF_STATEINI(x) (((x) >> S_WF_STATEINI) & M_WF_STATEINI)
1121 
1122 #define S_PLM_REQFIFOCNT    22
1123 #define M_PLM_REQFIFOCNT    0x3
1124 #define V_PLM_REQFIFOCNT(x) ((x) << S_PLM_REQFIFOCNT)
1125 #define G_PLM_REQFIFOCNT(x) (((x) >> S_PLM_REQFIFOCNT) & M_PLM_REQFIFOCNT)
1126 
1127 #define S_ER_REQFIFOEMPTY    21
1128 #define V_ER_REQFIFOEMPTY(x) ((x) << S_ER_REQFIFOEMPTY)
1129 #define F_ER_REQFIFOEMPTY    V_ER_REQFIFOEMPTY(1U)
1130 
1131 #define S_WF_RSPFIFOEMPTY    20
1132 #define V_WF_RSPFIFOEMPTY(x) ((x) << S_WF_RSPFIFOEMPTY)
1133 #define F_WF_RSPFIFOEMPTY    V_WF_RSPFIFOEMPTY(1U)
1134 
1135 #define S_WF_REQFIFOEMPTY    19
1136 #define V_WF_REQFIFOEMPTY(x) ((x) << S_WF_REQFIFOEMPTY)
1137 #define F_WF_REQFIFOEMPTY    V_WF_REQFIFOEMPTY(1U)
1138 
1139 #define S_RF_RSPFIFOEMPTY    18
1140 #define V_RF_RSPFIFOEMPTY(x) ((x) << S_RF_RSPFIFOEMPTY)
1141 #define F_RF_RSPFIFOEMPTY    V_RF_RSPFIFOEMPTY(1U)
1142 
1143 #define S_RF_REQFIFOEMPTY    17
1144 #define V_RF_REQFIFOEMPTY(x) ((x) << S_RF_REQFIFOEMPTY)
1145 #define F_RF_REQFIFOEMPTY    V_RF_REQFIFOEMPTY(1U)
1146 
1147 #define S_RF_ACTEMPTY    16
1148 #define V_RF_ACTEMPTY(x) ((x) << S_RF_ACTEMPTY)
1149 #define F_RF_ACTEMPTY    V_RF_ACTEMPTY(1U)
1150 
1151 #define S_PIO_RSPFIFOCNT    11
1152 #define M_PIO_RSPFIFOCNT    0x1f
1153 #define V_PIO_RSPFIFOCNT(x) ((x) << S_PIO_RSPFIFOCNT)
1154 #define G_PIO_RSPFIFOCNT(x) (((x) >> S_PIO_RSPFIFOCNT) & M_PIO_RSPFIFOCNT)
1155 
1156 #define S_PIO_REQFIFOCNT    5
1157 #define M_PIO_REQFIFOCNT    0x3f
1158 #define V_PIO_REQFIFOCNT(x) ((x) << S_PIO_REQFIFOCNT)
1159 #define G_PIO_REQFIFOCNT(x) (((x) >> S_PIO_REQFIFOCNT) & M_PIO_REQFIFOCNT)
1160 
1161 #define S_CF_RSPFIFOEMPTY    4
1162 #define V_CF_RSPFIFOEMPTY(x) ((x) << S_CF_RSPFIFOEMPTY)
1163 #define F_CF_RSPFIFOEMPTY    V_CF_RSPFIFOEMPTY(1U)
1164 
1165 #define S_CF_REQFIFOEMPTY    3
1166 #define V_CF_REQFIFOEMPTY(x) ((x) << S_CF_REQFIFOEMPTY)
1167 #define F_CF_REQFIFOEMPTY    V_CF_REQFIFOEMPTY(1U)
1168 
1169 #define S_CF_ACTEMPTY    2
1170 #define V_CF_ACTEMPTY(x) ((x) << S_CF_ACTEMPTY)
1171 #define F_CF_ACTEMPTY    V_CF_ACTEMPTY(1U)
1172 
1173 #define S_VPD_RSPFIFOEMPTY    1
1174 #define V_VPD_RSPFIFOEMPTY(x) ((x) << S_VPD_RSPFIFOEMPTY)
1175 #define F_VPD_RSPFIFOEMPTY    V_VPD_RSPFIFOEMPTY(1U)
1176 
1177 #define S_VPD_REQFIFOEMPTY    0
1178 #define V_VPD_REQFIFOEMPTY(x) ((x) << S_VPD_REQFIFOEMPTY)
1179 #define F_VPD_REQFIFOEMPTY    V_VPD_REQFIFOEMPTY(1U)
1180 
1181 #define A_PCIE_CAL 0x90
1182 
1183 #define S_CALBUSY    31
1184 #define V_CALBUSY(x) ((x) << S_CALBUSY)
1185 #define F_CALBUSY    V_CALBUSY(1U)
1186 
1187 #define S_CALFAULT    30
1188 #define V_CALFAULT(x) ((x) << S_CALFAULT)
1189 #define F_CALFAULT    V_CALFAULT(1U)
1190 
1191 #define S_PCIE_ZINSEL    11
1192 #define V_PCIE_ZINSEL(x) ((x) << S_PCIE_ZINSEL)
1193 #define F_PCIE_ZINSEL    V_PCIE_ZINSEL(1U)
1194 
1195 #define S_ZMAN    8
1196 #define M_ZMAN    0x7
1197 #define V_ZMAN(x) ((x) << S_ZMAN)
1198 #define G_ZMAN(x) (((x) >> S_ZMAN) & M_ZMAN)
1199 
1200 #define S_ZOUT    3
1201 #define M_ZOUT    0x1f
1202 #define V_ZOUT(x) ((x) << S_ZOUT)
1203 #define G_ZOUT(x) (((x) >> S_ZOUT) & M_ZOUT)
1204 
1205 #define S_ZIN    0
1206 #define M_ZIN    0x7
1207 #define V_ZIN(x) ((x) << S_ZIN)
1208 #define G_ZIN(x) (((x) >> S_ZIN) & M_ZIN)
1209 
1210 #define A_PCIE_WOL 0x94
1211 
1212 #define S_CF_RSPSTATE    12
1213 #define M_CF_RSPSTATE    0x3
1214 #define V_CF_RSPSTATE(x) ((x) << S_CF_RSPSTATE)
1215 #define G_CF_RSPSTATE(x) (((x) >> S_CF_RSPSTATE) & M_CF_RSPSTATE)
1216 
1217 #define S_RF_RSPSTATE    10
1218 #define M_RF_RSPSTATE    0x3
1219 #define V_RF_RSPSTATE(x) ((x) << S_RF_RSPSTATE)
1220 #define G_RF_RSPSTATE(x) (((x) >> S_RF_RSPSTATE) & M_RF_RSPSTATE)
1221 
1222 #define S_PME_STATE    7
1223 #define M_PME_STATE    0x7
1224 #define V_PME_STATE(x) ((x) << S_PME_STATE)
1225 #define G_PME_STATE(x) (((x) >> S_PME_STATE) & M_PME_STATE)
1226 
1227 #define S_INT_STATE    4
1228 #define M_INT_STATE    0x7
1229 #define V_INT_STATE(x) ((x) << S_INT_STATE)
1230 #define G_INT_STATE(x) (((x) >> S_INT_STATE) & M_INT_STATE)
1231 
1232 #define A_PCIE_PEX_CTRL0 0x98
1233 
1234 #define S_CPLTIMEOUTRETRY    31
1235 #define V_CPLTIMEOUTRETRY(x) ((x) << S_CPLTIMEOUTRETRY)
1236 #define F_CPLTIMEOUTRETRY    V_CPLTIMEOUTRETRY(1U)
1237 
1238 #define S_STRICTTSMN    30
1239 #define V_STRICTTSMN(x) ((x) << S_STRICTTSMN)
1240 #define F_STRICTTSMN    V_STRICTTSMN(1U)
1241 
1242 #define S_NUMFSTTRNSEQ    22
1243 #define M_NUMFSTTRNSEQ    0xff
1244 #define V_NUMFSTTRNSEQ(x) ((x) << S_NUMFSTTRNSEQ)
1245 #define G_NUMFSTTRNSEQ(x) (((x) >> S_NUMFSTTRNSEQ) & M_NUMFSTTRNSEQ)
1246 
1247 #define S_REPLAYLMT    2
1248 #define M_REPLAYLMT    0xfffff
1249 #define V_REPLAYLMT(x) ((x) << S_REPLAYLMT)
1250 #define G_REPLAYLMT(x) (((x) >> S_REPLAYLMT) & M_REPLAYLMT)
1251 
1252 #define S_TXPNDCHKEN    1
1253 #define V_TXPNDCHKEN(x) ((x) << S_TXPNDCHKEN)
1254 #define F_TXPNDCHKEN    V_TXPNDCHKEN(1U)
1255 
1256 #define S_CPLPNDCHKEN    0
1257 #define V_CPLPNDCHKEN(x) ((x) << S_CPLPNDCHKEN)
1258 #define F_CPLPNDCHKEN    V_CPLPNDCHKEN(1U)
1259 
1260 #define A_PCIE_PEX_CTRL1 0x9c
1261 
1262 #define S_RXPHYERREN    31
1263 #define V_RXPHYERREN(x) ((x) << S_RXPHYERREN)
1264 #define F_RXPHYERREN    V_RXPHYERREN(1U)
1265 
1266 #define S_DLLPTIMEOUTLMT    13
1267 #define M_DLLPTIMEOUTLMT    0x3ffff
1268 #define V_DLLPTIMEOUTLMT(x) ((x) << S_DLLPTIMEOUTLMT)
1269 #define G_DLLPTIMEOUTLMT(x) (((x) >> S_DLLPTIMEOUTLMT) & M_DLLPTIMEOUTLMT)
1270 
1271 #define S_ACKLAT    0
1272 #define M_ACKLAT    0x1fff
1273 #define V_ACKLAT(x) ((x) << S_ACKLAT)
1274 #define G_ACKLAT(x) (((x) >> S_ACKLAT) & M_ACKLAT)
1275 
1276 #define S_T3A_DLLPTIMEOUTLMT    11
1277 #define M_T3A_DLLPTIMEOUTLMT    0xfffff
1278 #define V_T3A_DLLPTIMEOUTLMT(x) ((x) << S_T3A_DLLPTIMEOUTLMT)
1279 #define G_T3A_DLLPTIMEOUTLMT(x) (((x) >> S_T3A_DLLPTIMEOUTLMT) & M_T3A_DLLPTIMEOUTLMT)
1280 
1281 #define S_T3A_ACKLAT    0
1282 #define M_T3A_ACKLAT    0x7ff
1283 #define V_T3A_ACKLAT(x) ((x) << S_T3A_ACKLAT)
1284 #define G_T3A_ACKLAT(x) (((x) >> S_T3A_ACKLAT) & M_T3A_ACKLAT)
1285 
1286 #define A_PCIE_PEX_CTRL2 0xa0
1287 
1288 #define S_LNKCNTLDETDIR    30
1289 #define V_LNKCNTLDETDIR(x) ((x) << S_LNKCNTLDETDIR)
1290 #define F_LNKCNTLDETDIR    V_LNKCNTLDETDIR(1U)
1291 
1292 #define S_ENTERL1REN    29
1293 #define V_ENTERL1REN(x) ((x) << S_ENTERL1REN)
1294 #define F_ENTERL1REN    V_ENTERL1REN(1U)
1295 
1296 #define S_PMEXITL1REQ    28
1297 #define V_PMEXITL1REQ(x) ((x) << S_PMEXITL1REQ)
1298 #define F_PMEXITL1REQ    V_PMEXITL1REQ(1U)
1299 
1300 #define S_PMTXIDLE    27
1301 #define V_PMTXIDLE(x) ((x) << S_PMTXIDLE)
1302 #define F_PMTXIDLE    V_PMTXIDLE(1U)
1303 
1304 #define S_PCIMODELOOP    26
1305 #define V_PCIMODELOOP(x) ((x) << S_PCIMODELOOP)
1306 #define F_PCIMODELOOP    V_PCIMODELOOP(1U)
1307 
1308 #define S_L1ASPMTXRXL0STIME    14
1309 #define M_L1ASPMTXRXL0STIME    0xfff
1310 #define V_L1ASPMTXRXL0STIME(x) ((x) << S_L1ASPMTXRXL0STIME)
1311 #define G_L1ASPMTXRXL0STIME(x) (((x) >> S_L1ASPMTXRXL0STIME) & M_L1ASPMTXRXL0STIME)
1312 
1313 #define S_L0SIDLETIME    3
1314 #define M_L0SIDLETIME    0x7ff
1315 #define V_L0SIDLETIME(x) ((x) << S_L0SIDLETIME)
1316 #define G_L0SIDLETIME(x) (((x) >> S_L0SIDLETIME) & M_L0SIDLETIME)
1317 
1318 #define S_ENTERL1ASPMEN    2
1319 #define V_ENTERL1ASPMEN(x) ((x) << S_ENTERL1ASPMEN)
1320 #define F_ENTERL1ASPMEN    V_ENTERL1ASPMEN(1U)
1321 
1322 #define S_ENTERL1EN    1
1323 #define V_ENTERL1EN(x) ((x) << S_ENTERL1EN)
1324 #define F_ENTERL1EN    V_ENTERL1EN(1U)
1325 
1326 #define S_ENTERL0SEN    0
1327 #define V_ENTERL0SEN(x) ((x) << S_ENTERL0SEN)
1328 #define F_ENTERL0SEN    V_ENTERL0SEN(1U)
1329 
1330 #define S_ENTERL23    3
1331 #define V_ENTERL23(x) ((x) << S_ENTERL23)
1332 #define F_ENTERL23    V_ENTERL23(1U)
1333 
1334 #define A_PCIE_PEX_ERR 0xa4
1335 
1336 #define S_CPLTIMEOUTID    18
1337 #define M_CPLTIMEOUTID    0x7f
1338 #define V_CPLTIMEOUTID(x) ((x) << S_CPLTIMEOUTID)
1339 #define G_CPLTIMEOUTID(x) (((x) >> S_CPLTIMEOUTID) & M_CPLTIMEOUTID)
1340 
1341 #define S_FLOWCTLOFLOWERR    17
1342 #define V_FLOWCTLOFLOWERR(x) ((x) << S_FLOWCTLOFLOWERR)
1343 #define F_FLOWCTLOFLOWERR    V_FLOWCTLOFLOWERR(1U)
1344 
1345 #define S_REPLAYTIMEOUT    16
1346 #define V_REPLAYTIMEOUT(x) ((x) << S_REPLAYTIMEOUT)
1347 #define F_REPLAYTIMEOUT    V_REPLAYTIMEOUT(1U)
1348 
1349 #define S_REPLAYROLLOVER    15
1350 #define V_REPLAYROLLOVER(x) ((x) << S_REPLAYROLLOVER)
1351 #define F_REPLAYROLLOVER    V_REPLAYROLLOVER(1U)
1352 
1353 #define S_BADDLLP    14
1354 #define V_BADDLLP(x) ((x) << S_BADDLLP)
1355 #define F_BADDLLP    V_BADDLLP(1U)
1356 
1357 #define S_DLLPERR    13
1358 #define V_DLLPERR(x) ((x) << S_DLLPERR)
1359 #define F_DLLPERR    V_DLLPERR(1U)
1360 
1361 #define S_FLOWCTLPROTERR    12
1362 #define V_FLOWCTLPROTERR(x) ((x) << S_FLOWCTLPROTERR)
1363 #define F_FLOWCTLPROTERR    V_FLOWCTLPROTERR(1U)
1364 
1365 #define S_CPLTIMEOUT    11
1366 #define V_CPLTIMEOUT(x) ((x) << S_CPLTIMEOUT)
1367 #define F_CPLTIMEOUT    V_CPLTIMEOUT(1U)
1368 
1369 #define S_PHYRCVERR    10
1370 #define V_PHYRCVERR(x) ((x) << S_PHYRCVERR)
1371 #define F_PHYRCVERR    V_PHYRCVERR(1U)
1372 
1373 #define S_DISTLP    9
1374 #define V_DISTLP(x) ((x) << S_DISTLP)
1375 #define F_DISTLP    V_DISTLP(1U)
1376 
1377 #define S_BADECRC    8
1378 #define V_BADECRC(x) ((x) << S_BADECRC)
1379 #define F_BADECRC    V_BADECRC(1U)
1380 
1381 #define S_BADTLP    7
1382 #define V_BADTLP(x) ((x) << S_BADTLP)
1383 #define F_BADTLP    V_BADTLP(1U)
1384 
1385 #define S_MALTLP    6
1386 #define V_MALTLP(x) ((x) << S_MALTLP)
1387 #define F_MALTLP    V_MALTLP(1U)
1388 
1389 #define S_UNXCPL    5
1390 #define V_UNXCPL(x) ((x) << S_UNXCPL)
1391 #define F_UNXCPL    V_UNXCPL(1U)
1392 
1393 #define S_UNSREQ    4
1394 #define V_UNSREQ(x) ((x) << S_UNSREQ)
1395 #define F_UNSREQ    V_UNSREQ(1U)
1396 
1397 #define S_PSNREQ    3
1398 #define V_PSNREQ(x) ((x) << S_PSNREQ)
1399 #define F_PSNREQ    V_PSNREQ(1U)
1400 
1401 #define S_UNSCPL    2
1402 #define V_UNSCPL(x) ((x) << S_UNSCPL)
1403 #define F_UNSCPL    V_UNSCPL(1U)
1404 
1405 #define S_CPLABT    1
1406 #define V_CPLABT(x) ((x) << S_CPLABT)
1407 #define F_CPLABT    V_CPLABT(1U)
1408 
1409 #define S_PSNCPL    0
1410 #define V_PSNCPL(x) ((x) << S_PSNCPL)
1411 #define F_PSNCPL    V_PSNCPL(1U)
1412 
1413 #define A_PCIE_SERDES_CTRL 0xa8
1414 
1415 #define S_PMASEL    3
1416 #define V_PMASEL(x) ((x) << S_PMASEL)
1417 #define F_PMASEL    V_PMASEL(1U)
1418 
1419 #define S_LANE    0
1420 #define M_LANE    0x7
1421 #define V_LANE(x) ((x) << S_LANE)
1422 #define G_LANE(x) (((x) >> S_LANE) & M_LANE)
1423 
1424 #define A_PCIE_PIPE_CTRL 0xa8
1425 
1426 #define S_RECDETUSEC    19
1427 #define M_RECDETUSEC    0x7
1428 #define V_RECDETUSEC(x) ((x) << S_RECDETUSEC)
1429 #define G_RECDETUSEC(x) (((x) >> S_RECDETUSEC) & M_RECDETUSEC)
1430 
1431 #define S_PLLLCKCYC    6
1432 #define M_PLLLCKCYC    0x1fff
1433 #define V_PLLLCKCYC(x) ((x) << S_PLLLCKCYC)
1434 #define G_PLLLCKCYC(x) (((x) >> S_PLLLCKCYC) & M_PLLLCKCYC)
1435 
1436 #define S_ELECIDLEDETCYC    3
1437 #define M_ELECIDLEDETCYC    0x7
1438 #define V_ELECIDLEDETCYC(x) ((x) << S_ELECIDLEDETCYC)
1439 #define G_ELECIDLEDETCYC(x) (((x) >> S_ELECIDLEDETCYC) & M_ELECIDLEDETCYC)
1440 
1441 #define S_USECDRLOS    2
1442 #define V_USECDRLOS(x) ((x) << S_USECDRLOS)
1443 #define F_USECDRLOS    V_USECDRLOS(1U)
1444 
1445 #define S_PCLKREQINP1    1
1446 #define V_PCLKREQINP1(x) ((x) << S_PCLKREQINP1)
1447 #define F_PCLKREQINP1    V_PCLKREQINP1(1U)
1448 
1449 #define S_PCLKOFFINP1    0
1450 #define V_PCLKOFFINP1(x) ((x) << S_PCLKOFFINP1)
1451 #define F_PCLKOFFINP1    V_PCLKOFFINP1(1U)
1452 
1453 #define A_PCIE_SERDES_QUAD_CTRL0 0xac
1454 
1455 #define S_TESTSIG    10
1456 #define M_TESTSIG    0x7ffff
1457 #define V_TESTSIG(x) ((x) << S_TESTSIG)
1458 #define G_TESTSIG(x) (((x) >> S_TESTSIG) & M_TESTSIG)
1459 
1460 #define S_OFFSET    2
1461 #define M_OFFSET    0xff
1462 #define V_OFFSET(x) ((x) << S_OFFSET)
1463 #define G_OFFSET(x) (((x) >> S_OFFSET) & M_OFFSET)
1464 
1465 #define S_OFFSETEN    1
1466 #define V_OFFSETEN(x) ((x) << S_OFFSETEN)
1467 #define F_OFFSETEN    V_OFFSETEN(1U)
1468 
1469 #define S_IDDQB    0
1470 #define V_IDDQB(x) ((x) << S_IDDQB)
1471 #define F_IDDQB    V_IDDQB(1U)
1472 
1473 #define S_MANMODE    31
1474 #define V_MANMODE(x) ((x) << S_MANMODE)
1475 #define F_MANMODE    V_MANMODE(1U)
1476 
1477 #define S_MANLPBKEN    29
1478 #define M_MANLPBKEN    0x3
1479 #define V_MANLPBKEN(x) ((x) << S_MANLPBKEN)
1480 #define G_MANLPBKEN(x) (((x) >> S_MANLPBKEN) & M_MANLPBKEN)
1481 
1482 #define S_MANTXRECDETEN    28
1483 #define V_MANTXRECDETEN(x) ((x) << S_MANTXRECDETEN)
1484 #define F_MANTXRECDETEN    V_MANTXRECDETEN(1U)
1485 
1486 #define S_MANTXBEACON    27
1487 #define V_MANTXBEACON(x) ((x) << S_MANTXBEACON)
1488 #define F_MANTXBEACON    V_MANTXBEACON(1U)
1489 
1490 #define S_MANTXEI    26
1491 #define V_MANTXEI(x) ((x) << S_MANTXEI)
1492 #define F_MANTXEI    V_MANTXEI(1U)
1493 
1494 #define S_MANRXPOLARITY    25
1495 #define V_MANRXPOLARITY(x) ((x) << S_MANRXPOLARITY)
1496 #define F_MANRXPOLARITY    V_MANRXPOLARITY(1U)
1497 
1498 #define S_MANTXRST    24
1499 #define V_MANTXRST(x) ((x) << S_MANTXRST)
1500 #define F_MANTXRST    V_MANTXRST(1U)
1501 
1502 #define S_MANRXRST    23
1503 #define V_MANRXRST(x) ((x) << S_MANRXRST)
1504 #define F_MANRXRST    V_MANRXRST(1U)
1505 
1506 #define S_MANTXEN    22
1507 #define V_MANTXEN(x) ((x) << S_MANTXEN)
1508 #define F_MANTXEN    V_MANTXEN(1U)
1509 
1510 #define S_MANRXEN    21
1511 #define V_MANRXEN(x) ((x) << S_MANRXEN)
1512 #define F_MANRXEN    V_MANRXEN(1U)
1513 
1514 #define S_MANEN    20
1515 #define V_MANEN(x) ((x) << S_MANEN)
1516 #define F_MANEN    V_MANEN(1U)
1517 
1518 #define S_PCIE_CMURANGE    17
1519 #define M_PCIE_CMURANGE    0x7
1520 #define V_PCIE_CMURANGE(x) ((x) << S_PCIE_CMURANGE)
1521 #define G_PCIE_CMURANGE(x) (((x) >> S_PCIE_CMURANGE) & M_PCIE_CMURANGE)
1522 
1523 #define S_PCIE_BGENB    16
1524 #define V_PCIE_BGENB(x) ((x) << S_PCIE_BGENB)
1525 #define F_PCIE_BGENB    V_PCIE_BGENB(1U)
1526 
1527 #define S_PCIE_ENSKPDROP    15
1528 #define V_PCIE_ENSKPDROP(x) ((x) << S_PCIE_ENSKPDROP)
1529 #define F_PCIE_ENSKPDROP    V_PCIE_ENSKPDROP(1U)
1530 
1531 #define S_PCIE_ENCOMMA    14
1532 #define V_PCIE_ENCOMMA(x) ((x) << S_PCIE_ENCOMMA)
1533 #define F_PCIE_ENCOMMA    V_PCIE_ENCOMMA(1U)
1534 
1535 #define S_PCIE_EN8B10B    13
1536 #define V_PCIE_EN8B10B(x) ((x) << S_PCIE_EN8B10B)
1537 #define F_PCIE_EN8B10B    V_PCIE_EN8B10B(1U)
1538 
1539 #define S_PCIE_ENELBUF    12
1540 #define V_PCIE_ENELBUF(x) ((x) << S_PCIE_ENELBUF)
1541 #define F_PCIE_ENELBUF    V_PCIE_ENELBUF(1U)
1542 
1543 #define S_PCIE_GAIN    7
1544 #define M_PCIE_GAIN    0x1f
1545 #define V_PCIE_GAIN(x) ((x) << S_PCIE_GAIN)
1546 #define G_PCIE_GAIN(x) (((x) >> S_PCIE_GAIN) & M_PCIE_GAIN)
1547 
1548 #define S_PCIE_BANDGAP    3
1549 #define M_PCIE_BANDGAP    0xf
1550 #define V_PCIE_BANDGAP(x) ((x) << S_PCIE_BANDGAP)
1551 #define G_PCIE_BANDGAP(x) (((x) >> S_PCIE_BANDGAP) & M_PCIE_BANDGAP)
1552 
1553 #define S_RXCOMADJ    2
1554 #define V_RXCOMADJ(x) ((x) << S_RXCOMADJ)
1555 #define F_RXCOMADJ    V_RXCOMADJ(1U)
1556 
1557 #define S_PREEMPH    0
1558 #define M_PREEMPH    0x3
1559 #define V_PREEMPH(x) ((x) << S_PREEMPH)
1560 #define G_PREEMPH(x) (((x) >> S_PREEMPH) & M_PREEMPH)
1561 
1562 #define A_PCIE_SERDES_QUAD_CTRL1 0xb0
1563 
1564 #define S_FASTINIT    28
1565 #define V_FASTINIT(x) ((x) << S_FASTINIT)
1566 #define F_FASTINIT    V_FASTINIT(1U)
1567 
1568 #define S_CTCDISABLE    27
1569 #define V_CTCDISABLE(x) ((x) << S_CTCDISABLE)
1570 #define F_CTCDISABLE    V_CTCDISABLE(1U)
1571 
1572 #define S_MANRESETPLL    26
1573 #define V_MANRESETPLL(x) ((x) << S_MANRESETPLL)
1574 #define F_MANRESETPLL    V_MANRESETPLL(1U)
1575 
1576 #define S_MANL2PWRDN    25
1577 #define V_MANL2PWRDN(x) ((x) << S_MANL2PWRDN)
1578 #define F_MANL2PWRDN    V_MANL2PWRDN(1U)
1579 
1580 #define S_MANQUADEN    24
1581 #define V_MANQUADEN(x) ((x) << S_MANQUADEN)
1582 #define F_MANQUADEN    V_MANQUADEN(1U)
1583 
1584 #define S_RXEQCTL    22
1585 #define M_RXEQCTL    0x3
1586 #define V_RXEQCTL(x) ((x) << S_RXEQCTL)
1587 #define G_RXEQCTL(x) (((x) >> S_RXEQCTL) & M_RXEQCTL)
1588 
1589 #define S_HIVMODE    21
1590 #define V_HIVMODE(x) ((x) << S_HIVMODE)
1591 #define F_HIVMODE    V_HIVMODE(1U)
1592 
1593 #define S_REFSEL    19
1594 #define M_REFSEL    0x3
1595 #define V_REFSEL(x) ((x) << S_REFSEL)
1596 #define G_REFSEL(x) (((x) >> S_REFSEL) & M_REFSEL)
1597 
1598 #define S_RXTERMADJ    17
1599 #define M_RXTERMADJ    0x3
1600 #define V_RXTERMADJ(x) ((x) << S_RXTERMADJ)
1601 #define G_RXTERMADJ(x) (((x) >> S_RXTERMADJ) & M_RXTERMADJ)
1602 
1603 #define S_TXTERMADJ    15
1604 #define M_TXTERMADJ    0x3
1605 #define V_TXTERMADJ(x) ((x) << S_TXTERMADJ)
1606 #define G_TXTERMADJ(x) (((x) >> S_TXTERMADJ) & M_TXTERMADJ)
1607 
1608 #define S_DEQ    11
1609 #define M_DEQ    0xf
1610 #define V_DEQ(x) ((x) << S_DEQ)
1611 #define G_DEQ(x) (((x) >> S_DEQ) & M_DEQ)
1612 
1613 #define S_DTX    7
1614 #define M_DTX    0xf
1615 #define V_DTX(x) ((x) << S_DTX)
1616 #define G_DTX(x) (((x) >> S_DTX) & M_DTX)
1617 
1618 #define S_LODRV    6
1619 #define V_LODRV(x) ((x) << S_LODRV)
1620 #define F_LODRV    V_LODRV(1U)
1621 
1622 #define S_HIDRV    5
1623 #define V_HIDRV(x) ((x) << S_HIDRV)
1624 #define F_HIDRV    V_HIDRV(1U)
1625 
1626 #define S_INTPARRESET    4
1627 #define V_INTPARRESET(x) ((x) << S_INTPARRESET)
1628 #define F_INTPARRESET    V_INTPARRESET(1U)
1629 
1630 #define S_INTPARLPBK    3
1631 #define V_INTPARLPBK(x) ((x) << S_INTPARLPBK)
1632 #define F_INTPARLPBK    V_INTPARLPBK(1U)
1633 
1634 #define S_INTSERLPBKWDRV    2
1635 #define V_INTSERLPBKWDRV(x) ((x) << S_INTSERLPBKWDRV)
1636 #define F_INTSERLPBKWDRV    V_INTSERLPBKWDRV(1U)
1637 
1638 #define S_PW    1
1639 #define V_PW(x) ((x) << S_PW)
1640 #define F_PW    V_PW(1U)
1641 
1642 #define S_PCLKDETECT    0
1643 #define V_PCLKDETECT(x) ((x) << S_PCLKDETECT)
1644 #define F_PCLKDETECT    V_PCLKDETECT(1U)
1645 
1646 #define A_PCIE_SERDES_STATUS0 0xb0
1647 
1648 #define S_RXERRLANE7    21
1649 #define M_RXERRLANE7    0x7
1650 #define V_RXERRLANE7(x) ((x) << S_RXERRLANE7)
1651 #define G_RXERRLANE7(x) (((x) >> S_RXERRLANE7) & M_RXERRLANE7)
1652 
1653 #define S_RXERRLANE6    18
1654 #define M_RXERRLANE6    0x7
1655 #define V_RXERRLANE6(x) ((x) << S_RXERRLANE6)
1656 #define G_RXERRLANE6(x) (((x) >> S_RXERRLANE6) & M_RXERRLANE6)
1657 
1658 #define S_RXERRLANE5    15
1659 #define M_RXERRLANE5    0x7
1660 #define V_RXERRLANE5(x) ((x) << S_RXERRLANE5)
1661 #define G_RXERRLANE5(x) (((x) >> S_RXERRLANE5) & M_RXERRLANE5)
1662 
1663 #define S_RXERRLANE4    12
1664 #define M_RXERRLANE4    0x7
1665 #define V_RXERRLANE4(x) ((x) << S_RXERRLANE4)
1666 #define G_RXERRLANE4(x) (((x) >> S_RXERRLANE4) & M_RXERRLANE4)
1667 
1668 #define S_PCIE_RXERRLANE3    9
1669 #define M_PCIE_RXERRLANE3    0x7
1670 #define V_PCIE_RXERRLANE3(x) ((x) << S_PCIE_RXERRLANE3)
1671 #define G_PCIE_RXERRLANE3(x) (((x) >> S_PCIE_RXERRLANE3) & M_PCIE_RXERRLANE3)
1672 
1673 #define S_PCIE_RXERRLANE2    6
1674 #define M_PCIE_RXERRLANE2    0x7
1675 #define V_PCIE_RXERRLANE2(x) ((x) << S_PCIE_RXERRLANE2)
1676 #define G_PCIE_RXERRLANE2(x) (((x) >> S_PCIE_RXERRLANE2) & M_PCIE_RXERRLANE2)
1677 
1678 #define S_PCIE_RXERRLANE1    3
1679 #define M_PCIE_RXERRLANE1    0x7
1680 #define V_PCIE_RXERRLANE1(x) ((x) << S_PCIE_RXERRLANE1)
1681 #define G_PCIE_RXERRLANE1(x) (((x) >> S_PCIE_RXERRLANE1) & M_PCIE_RXERRLANE1)
1682 
1683 #define S_PCIE_RXERRLANE0    0
1684 #define M_PCIE_RXERRLANE0    0x7
1685 #define V_PCIE_RXERRLANE0(x) ((x) << S_PCIE_RXERRLANE0)
1686 #define G_PCIE_RXERRLANE0(x) (((x) >> S_PCIE_RXERRLANE0) & M_PCIE_RXERRLANE0)
1687 
1688 #define A_PCIE_SERDES_LANE_CTRL 0xb4
1689 
1690 #define S_EXTBISTCHKERRCLR    22
1691 #define V_EXTBISTCHKERRCLR(x) ((x) << S_EXTBISTCHKERRCLR)
1692 #define F_EXTBISTCHKERRCLR    V_EXTBISTCHKERRCLR(1U)
1693 
1694 #define S_EXTBISTCHKEN    21
1695 #define V_EXTBISTCHKEN(x) ((x) << S_EXTBISTCHKEN)
1696 #define F_EXTBISTCHKEN    V_EXTBISTCHKEN(1U)
1697 
1698 #define S_EXTBISTGENEN    20
1699 #define V_EXTBISTGENEN(x) ((x) << S_EXTBISTGENEN)
1700 #define F_EXTBISTGENEN    V_EXTBISTGENEN(1U)
1701 
1702 #define S_EXTBISTPAT    17
1703 #define M_EXTBISTPAT    0x7
1704 #define V_EXTBISTPAT(x) ((x) << S_EXTBISTPAT)
1705 #define G_EXTBISTPAT(x) (((x) >> S_EXTBISTPAT) & M_EXTBISTPAT)
1706 
1707 #define S_EXTPARRESET    16
1708 #define V_EXTPARRESET(x) ((x) << S_EXTPARRESET)
1709 #define F_EXTPARRESET    V_EXTPARRESET(1U)
1710 
1711 #define S_EXTPARLPBK    15
1712 #define V_EXTPARLPBK(x) ((x) << S_EXTPARLPBK)
1713 #define F_EXTPARLPBK    V_EXTPARLPBK(1U)
1714 
1715 #define S_MANRXTERMEN    14
1716 #define V_MANRXTERMEN(x) ((x) << S_MANRXTERMEN)
1717 #define F_MANRXTERMEN    V_MANRXTERMEN(1U)
1718 
1719 #define S_MANBEACONTXEN    13
1720 #define V_MANBEACONTXEN(x) ((x) << S_MANBEACONTXEN)
1721 #define F_MANBEACONTXEN    V_MANBEACONTXEN(1U)
1722 
1723 #define S_MANRXDETECTEN    12
1724 #define V_MANRXDETECTEN(x) ((x) << S_MANRXDETECTEN)
1725 #define F_MANRXDETECTEN    V_MANRXDETECTEN(1U)
1726 
1727 #define S_MANTXIDLEEN    11
1728 #define V_MANTXIDLEEN(x) ((x) << S_MANTXIDLEEN)
1729 #define F_MANTXIDLEEN    V_MANTXIDLEEN(1U)
1730 
1731 #define S_MANRXIDLEEN    10
1732 #define V_MANRXIDLEEN(x) ((x) << S_MANRXIDLEEN)
1733 #define F_MANRXIDLEEN    V_MANRXIDLEEN(1U)
1734 
1735 #define S_MANL1PWRDN    9
1736 #define V_MANL1PWRDN(x) ((x) << S_MANL1PWRDN)
1737 #define F_MANL1PWRDN    V_MANL1PWRDN(1U)
1738 
1739 #define S_MANRESET    8
1740 #define V_MANRESET(x) ((x) << S_MANRESET)
1741 #define F_MANRESET    V_MANRESET(1U)
1742 
1743 #define S_MANFMOFFSET    3
1744 #define M_MANFMOFFSET    0x1f
1745 #define V_MANFMOFFSET(x) ((x) << S_MANFMOFFSET)
1746 #define G_MANFMOFFSET(x) (((x) >> S_MANFMOFFSET) & M_MANFMOFFSET)
1747 
1748 #define S_MANFMOFFSETEN    2
1749 #define V_MANFMOFFSETEN(x) ((x) << S_MANFMOFFSETEN)
1750 #define F_MANFMOFFSETEN    V_MANFMOFFSETEN(1U)
1751 
1752 #define S_MANLANEEN    1
1753 #define V_MANLANEEN(x) ((x) << S_MANLANEEN)
1754 #define F_MANLANEEN    V_MANLANEEN(1U)
1755 
1756 #define S_INTSERLPBK    0
1757 #define V_INTSERLPBK(x) ((x) << S_INTSERLPBK)
1758 #define F_INTSERLPBK    V_INTSERLPBK(1U)
1759 
1760 #define A_PCIE_SERDES_STATUS1 0xb4
1761 
1762 #define S_CMULOCK    31
1763 #define V_CMULOCK(x) ((x) << S_CMULOCK)
1764 #define F_CMULOCK    V_CMULOCK(1U)
1765 
1766 #define S_RXKLOCKLANE7    23
1767 #define V_RXKLOCKLANE7(x) ((x) << S_RXKLOCKLANE7)
1768 #define F_RXKLOCKLANE7    V_RXKLOCKLANE7(1U)
1769 
1770 #define S_RXKLOCKLANE6    22
1771 #define V_RXKLOCKLANE6(x) ((x) << S_RXKLOCKLANE6)
1772 #define F_RXKLOCKLANE6    V_RXKLOCKLANE6(1U)
1773 
1774 #define S_RXKLOCKLANE5    21
1775 #define V_RXKLOCKLANE5(x) ((x) << S_RXKLOCKLANE5)
1776 #define F_RXKLOCKLANE5    V_RXKLOCKLANE5(1U)
1777 
1778 #define S_RXKLOCKLANE4    20
1779 #define V_RXKLOCKLANE4(x) ((x) << S_RXKLOCKLANE4)
1780 #define F_RXKLOCKLANE4    V_RXKLOCKLANE4(1U)
1781 
1782 #define S_PCIE_RXKLOCKLANE3    19
1783 #define V_PCIE_RXKLOCKLANE3(x) ((x) << S_PCIE_RXKLOCKLANE3)
1784 #define F_PCIE_RXKLOCKLANE3    V_PCIE_RXKLOCKLANE3(1U)
1785 
1786 #define S_PCIE_RXKLOCKLANE2    18
1787 #define V_PCIE_RXKLOCKLANE2(x) ((x) << S_PCIE_RXKLOCKLANE2)
1788 #define F_PCIE_RXKLOCKLANE2    V_PCIE_RXKLOCKLANE2(1U)
1789 
1790 #define S_PCIE_RXKLOCKLANE1    17
1791 #define V_PCIE_RXKLOCKLANE1(x) ((x) << S_PCIE_RXKLOCKLANE1)
1792 #define F_PCIE_RXKLOCKLANE1    V_PCIE_RXKLOCKLANE1(1U)
1793 
1794 #define S_PCIE_RXKLOCKLANE0    16
1795 #define V_PCIE_RXKLOCKLANE0(x) ((x) << S_PCIE_RXKLOCKLANE0)
1796 #define F_PCIE_RXKLOCKLANE0    V_PCIE_RXKLOCKLANE0(1U)
1797 
1798 #define S_RXUFLOWLANE7    15
1799 #define V_RXUFLOWLANE7(x) ((x) << S_RXUFLOWLANE7)
1800 #define F_RXUFLOWLANE7    V_RXUFLOWLANE7(1U)
1801 
1802 #define S_RXUFLOWLANE6    14
1803 #define V_RXUFLOWLANE6(x) ((x) << S_RXUFLOWLANE6)
1804 #define F_RXUFLOWLANE6    V_RXUFLOWLANE6(1U)
1805 
1806 #define S_RXUFLOWLANE5    13
1807 #define V_RXUFLOWLANE5(x) ((x) << S_RXUFLOWLANE5)
1808 #define F_RXUFLOWLANE5    V_RXUFLOWLANE5(1U)
1809 
1810 #define S_RXUFLOWLANE4    12
1811 #define V_RXUFLOWLANE4(x) ((x) << S_RXUFLOWLANE4)
1812 #define F_RXUFLOWLANE4    V_RXUFLOWLANE4(1U)
1813 
1814 #define S_PCIE_RXUFLOWLANE3    11
1815 #define V_PCIE_RXUFLOWLANE3(x) ((x) << S_PCIE_RXUFLOWLANE3)
1816 #define F_PCIE_RXUFLOWLANE3    V_PCIE_RXUFLOWLANE3(1U)
1817 
1818 #define S_PCIE_RXUFLOWLANE2    10
1819 #define V_PCIE_RXUFLOWLANE2(x) ((x) << S_PCIE_RXUFLOWLANE2)
1820 #define F_PCIE_RXUFLOWLANE2    V_PCIE_RXUFLOWLANE2(1U)
1821 
1822 #define S_PCIE_RXUFLOWLANE1    9
1823 #define V_PCIE_RXUFLOWLANE1(x) ((x) << S_PCIE_RXUFLOWLANE1)
1824 #define F_PCIE_RXUFLOWLANE1    V_PCIE_RXUFLOWLANE1(1U)
1825 
1826 #define S_PCIE_RXUFLOWLANE0    8
1827 #define V_PCIE_RXUFLOWLANE0(x) ((x) << S_PCIE_RXUFLOWLANE0)
1828 #define F_PCIE_RXUFLOWLANE0    V_PCIE_RXUFLOWLANE0(1U)
1829 
1830 #define S_RXOFLOWLANE7    7
1831 #define V_RXOFLOWLANE7(x) ((x) << S_RXOFLOWLANE7)
1832 #define F_RXOFLOWLANE7    V_RXOFLOWLANE7(1U)
1833 
1834 #define S_RXOFLOWLANE6    6
1835 #define V_RXOFLOWLANE6(x) ((x) << S_RXOFLOWLANE6)
1836 #define F_RXOFLOWLANE6    V_RXOFLOWLANE6(1U)
1837 
1838 #define S_RXOFLOWLANE5    5
1839 #define V_RXOFLOWLANE5(x) ((x) << S_RXOFLOWLANE5)
1840 #define F_RXOFLOWLANE5    V_RXOFLOWLANE5(1U)
1841 
1842 #define S_RXOFLOWLANE4    4
1843 #define V_RXOFLOWLANE4(x) ((x) << S_RXOFLOWLANE4)
1844 #define F_RXOFLOWLANE4    V_RXOFLOWLANE4(1U)
1845 
1846 #define S_PCIE_RXOFLOWLANE3    3
1847 #define V_PCIE_RXOFLOWLANE3(x) ((x) << S_PCIE_RXOFLOWLANE3)
1848 #define F_PCIE_RXOFLOWLANE3    V_PCIE_RXOFLOWLANE3(1U)
1849 
1850 #define S_PCIE_RXOFLOWLANE2    2
1851 #define V_PCIE_RXOFLOWLANE2(x) ((x) << S_PCIE_RXOFLOWLANE2)
1852 #define F_PCIE_RXOFLOWLANE2    V_PCIE_RXOFLOWLANE2(1U)
1853 
1854 #define S_PCIE_RXOFLOWLANE1    1
1855 #define V_PCIE_RXOFLOWLANE1(x) ((x) << S_PCIE_RXOFLOWLANE1)
1856 #define F_PCIE_RXOFLOWLANE1    V_PCIE_RXOFLOWLANE1(1U)
1857 
1858 #define S_PCIE_RXOFLOWLANE0    0
1859 #define V_PCIE_RXOFLOWLANE0(x) ((x) << S_PCIE_RXOFLOWLANE0)
1860 #define F_PCIE_RXOFLOWLANE0    V_PCIE_RXOFLOWLANE0(1U)
1861 
1862 #define A_PCIE_SERDES_LANE_STAT 0xb8
1863 
1864 #define S_EXTBISTCHKERRCNT    8
1865 #define M_EXTBISTCHKERRCNT    0xffffff
1866 #define V_EXTBISTCHKERRCNT(x) ((x) << S_EXTBISTCHKERRCNT)
1867 #define G_EXTBISTCHKERRCNT(x) (((x) >> S_EXTBISTCHKERRCNT) & M_EXTBISTCHKERRCNT)
1868 
1869 #define S_EXTBISTCHKFMD    7
1870 #define V_EXTBISTCHKFMD(x) ((x) << S_EXTBISTCHKFMD)
1871 #define F_EXTBISTCHKFMD    V_EXTBISTCHKFMD(1U)
1872 
1873 #define S_BEACONDETECTCHG    6
1874 #define V_BEACONDETECTCHG(x) ((x) << S_BEACONDETECTCHG)
1875 #define F_BEACONDETECTCHG    V_BEACONDETECTCHG(1U)
1876 
1877 #define S_RXDETECTCHG    5
1878 #define V_RXDETECTCHG(x) ((x) << S_RXDETECTCHG)
1879 #define F_RXDETECTCHG    V_RXDETECTCHG(1U)
1880 
1881 #define S_TXIDLEDETECTCHG    4
1882 #define V_TXIDLEDETECTCHG(x) ((x) << S_TXIDLEDETECTCHG)
1883 #define F_TXIDLEDETECTCHG    V_TXIDLEDETECTCHG(1U)
1884 
1885 #define S_BEACONDETECT    2
1886 #define V_BEACONDETECT(x) ((x) << S_BEACONDETECT)
1887 #define F_BEACONDETECT    V_BEACONDETECT(1U)
1888 
1889 #define S_RXDETECT    1
1890 #define V_RXDETECT(x) ((x) << S_RXDETECT)
1891 #define F_RXDETECT    V_RXDETECT(1U)
1892 
1893 #define S_TXIDLEDETECT    0
1894 #define V_TXIDLEDETECT(x) ((x) << S_TXIDLEDETECT)
1895 #define F_TXIDLEDETECT    V_TXIDLEDETECT(1U)
1896 
1897 #define A_PCIE_SERDES_STATUS2 0xb8
1898 
1899 #define S_TXRECDETLANE7    31
1900 #define V_TXRECDETLANE7(x) ((x) << S_TXRECDETLANE7)
1901 #define F_TXRECDETLANE7    V_TXRECDETLANE7(1U)
1902 
1903 #define S_TXRECDETLANE6    30
1904 #define V_TXRECDETLANE6(x) ((x) << S_TXRECDETLANE6)
1905 #define F_TXRECDETLANE6    V_TXRECDETLANE6(1U)
1906 
1907 #define S_TXRECDETLANE5    29
1908 #define V_TXRECDETLANE5(x) ((x) << S_TXRECDETLANE5)
1909 #define F_TXRECDETLANE5    V_TXRECDETLANE5(1U)
1910 
1911 #define S_TXRECDETLANE4    28
1912 #define V_TXRECDETLANE4(x) ((x) << S_TXRECDETLANE4)
1913 #define F_TXRECDETLANE4    V_TXRECDETLANE4(1U)
1914 
1915 #define S_TXRECDETLANE3    27
1916 #define V_TXRECDETLANE3(x) ((x) << S_TXRECDETLANE3)
1917 #define F_TXRECDETLANE3    V_TXRECDETLANE3(1U)
1918 
1919 #define S_TXRECDETLANE2    26
1920 #define V_TXRECDETLANE2(x) ((x) << S_TXRECDETLANE2)
1921 #define F_TXRECDETLANE2    V_TXRECDETLANE2(1U)
1922 
1923 #define S_TXRECDETLANE1    25
1924 #define V_TXRECDETLANE1(x) ((x) << S_TXRECDETLANE1)
1925 #define F_TXRECDETLANE1    V_TXRECDETLANE1(1U)
1926 
1927 #define S_TXRECDETLANE0    24
1928 #define V_TXRECDETLANE0(x) ((x) << S_TXRECDETLANE0)
1929 #define F_TXRECDETLANE0    V_TXRECDETLANE0(1U)
1930 
1931 #define S_RXEIDLANE7    23
1932 #define V_RXEIDLANE7(x) ((x) << S_RXEIDLANE7)
1933 #define F_RXEIDLANE7    V_RXEIDLANE7(1U)
1934 
1935 #define S_RXEIDLANE6    22
1936 #define V_RXEIDLANE6(x) ((x) << S_RXEIDLANE6)
1937 #define F_RXEIDLANE6    V_RXEIDLANE6(1U)
1938 
1939 #define S_RXEIDLANE5    21
1940 #define V_RXEIDLANE5(x) ((x) << S_RXEIDLANE5)
1941 #define F_RXEIDLANE5    V_RXEIDLANE5(1U)
1942 
1943 #define S_RXEIDLANE4    20
1944 #define V_RXEIDLANE4(x) ((x) << S_RXEIDLANE4)
1945 #define F_RXEIDLANE4    V_RXEIDLANE4(1U)
1946 
1947 #define S_RXEIDLANE3    19
1948 #define V_RXEIDLANE3(x) ((x) << S_RXEIDLANE3)
1949 #define F_RXEIDLANE3    V_RXEIDLANE3(1U)
1950 
1951 #define S_RXEIDLANE2    18
1952 #define V_RXEIDLANE2(x) ((x) << S_RXEIDLANE2)
1953 #define F_RXEIDLANE2    V_RXEIDLANE2(1U)
1954 
1955 #define S_RXEIDLANE1    17
1956 #define V_RXEIDLANE1(x) ((x) << S_RXEIDLANE1)
1957 #define F_RXEIDLANE1    V_RXEIDLANE1(1U)
1958 
1959 #define S_RXEIDLANE0    16
1960 #define V_RXEIDLANE0(x) ((x) << S_RXEIDLANE0)
1961 #define F_RXEIDLANE0    V_RXEIDLANE0(1U)
1962 
1963 #define S_RXREMSKIPLANE7    15
1964 #define V_RXREMSKIPLANE7(x) ((x) << S_RXREMSKIPLANE7)
1965 #define F_RXREMSKIPLANE7    V_RXREMSKIPLANE7(1U)
1966 
1967 #define S_RXREMSKIPLANE6    14
1968 #define V_RXREMSKIPLANE6(x) ((x) << S_RXREMSKIPLANE6)
1969 #define F_RXREMSKIPLANE6    V_RXREMSKIPLANE6(1U)
1970 
1971 #define S_RXREMSKIPLANE5    13
1972 #define V_RXREMSKIPLANE5(x) ((x) << S_RXREMSKIPLANE5)
1973 #define F_RXREMSKIPLANE5    V_RXREMSKIPLANE5(1U)
1974 
1975 #define S_RXREMSKIPLANE4    12
1976 #define V_RXREMSKIPLANE4(x) ((x) << S_RXREMSKIPLANE4)
1977 #define F_RXREMSKIPLANE4    V_RXREMSKIPLANE4(1U)
1978 
1979 #define S_PCIE_RXREMSKIPLANE3    11
1980 #define V_PCIE_RXREMSKIPLANE3(x) ((x) << S_PCIE_RXREMSKIPLANE3)
1981 #define F_PCIE_RXREMSKIPLANE3    V_PCIE_RXREMSKIPLANE3(1U)
1982 
1983 #define S_PCIE_RXREMSKIPLANE2    10
1984 #define V_PCIE_RXREMSKIPLANE2(x) ((x) << S_PCIE_RXREMSKIPLANE2)
1985 #define F_PCIE_RXREMSKIPLANE2    V_PCIE_RXREMSKIPLANE2(1U)
1986 
1987 #define S_PCIE_RXREMSKIPLANE1    9
1988 #define V_PCIE_RXREMSKIPLANE1(x) ((x) << S_PCIE_RXREMSKIPLANE1)
1989 #define F_PCIE_RXREMSKIPLANE1    V_PCIE_RXREMSKIPLANE1(1U)
1990 
1991 #define S_PCIE_RXREMSKIPLANE0    8
1992 #define V_PCIE_RXREMSKIPLANE0(x) ((x) << S_PCIE_RXREMSKIPLANE0)
1993 #define F_PCIE_RXREMSKIPLANE0    V_PCIE_RXREMSKIPLANE0(1U)
1994 
1995 #define S_RXADDSKIPLANE7    7
1996 #define V_RXADDSKIPLANE7(x) ((x) << S_RXADDSKIPLANE7)
1997 #define F_RXADDSKIPLANE7    V_RXADDSKIPLANE7(1U)
1998 
1999 #define S_RXADDSKIPLANE6    6
2000 #define V_RXADDSKIPLANE6(x) ((x) << S_RXADDSKIPLANE6)
2001 #define F_RXADDSKIPLANE6    V_RXADDSKIPLANE6(1U)
2002 
2003 #define S_RXADDSKIPLANE5    5
2004 #define V_RXADDSKIPLANE5(x) ((x) << S_RXADDSKIPLANE5)
2005 #define F_RXADDSKIPLANE5    V_RXADDSKIPLANE5(1U)
2006 
2007 #define S_RXADDSKIPLANE4    4
2008 #define V_RXADDSKIPLANE4(x) ((x) << S_RXADDSKIPLANE4)
2009 #define F_RXADDSKIPLANE4    V_RXADDSKIPLANE4(1U)
2010 
2011 #define S_PCIE_RXADDSKIPLANE3    3
2012 #define V_PCIE_RXADDSKIPLANE3(x) ((x) << S_PCIE_RXADDSKIPLANE3)
2013 #define F_PCIE_RXADDSKIPLANE3    V_PCIE_RXADDSKIPLANE3(1U)
2014 
2015 #define S_PCIE_RXADDSKIPLANE2    2
2016 #define V_PCIE_RXADDSKIPLANE2(x) ((x) << S_PCIE_RXADDSKIPLANE2)
2017 #define F_PCIE_RXADDSKIPLANE2    V_PCIE_RXADDSKIPLANE2(1U)
2018 
2019 #define S_PCIE_RXADDSKIPLANE1    1
2020 #define V_PCIE_RXADDSKIPLANE1(x) ((x) << S_PCIE_RXADDSKIPLANE1)
2021 #define F_PCIE_RXADDSKIPLANE1    V_PCIE_RXADDSKIPLANE1(1U)
2022 
2023 #define S_PCIE_RXADDSKIPLANE0    0
2024 #define V_PCIE_RXADDSKIPLANE0(x) ((x) << S_PCIE_RXADDSKIPLANE0)
2025 #define F_PCIE_RXADDSKIPLANE0    V_PCIE_RXADDSKIPLANE0(1U)
2026 
2027 #define A_PCIE_PEX_WMARK 0xbc
2028 
2029 #define S_P_WMARK    18
2030 #define M_P_WMARK    0x7ff
2031 #define V_P_WMARK(x) ((x) << S_P_WMARK)
2032 #define G_P_WMARK(x) (((x) >> S_P_WMARK) & M_P_WMARK)
2033 
2034 #define S_NP_WMARK    11
2035 #define M_NP_WMARK    0x7f
2036 #define V_NP_WMARK(x) ((x) << S_NP_WMARK)
2037 #define G_NP_WMARK(x) (((x) >> S_NP_WMARK) & M_NP_WMARK)
2038 
2039 #define S_CPL_WMARK    0
2040 #define M_CPL_WMARK    0x7ff
2041 #define V_CPL_WMARK(x) ((x) << S_CPL_WMARK)
2042 #define G_CPL_WMARK(x) (((x) >> S_CPL_WMARK) & M_CPL_WMARK)
2043 
2044 #define A_PCIE_SERDES_BIST 0xbc
2045 
2046 #define S_PCIE_BISTDONE    24
2047 #define M_PCIE_BISTDONE    0xff
2048 #define V_PCIE_BISTDONE(x) ((x) << S_PCIE_BISTDONE)
2049 #define G_PCIE_BISTDONE(x) (((x) >> S_PCIE_BISTDONE) & M_PCIE_BISTDONE)
2050 
2051 #define S_PCIE_BISTCYCLETHRESH    3
2052 #define M_PCIE_BISTCYCLETHRESH    0xffff
2053 #define V_PCIE_BISTCYCLETHRESH(x) ((x) << S_PCIE_BISTCYCLETHRESH)
2054 #define G_PCIE_BISTCYCLETHRESH(x) (((x) >> S_PCIE_BISTCYCLETHRESH) & M_PCIE_BISTCYCLETHRESH)
2055 
2056 #define S_BISTMODE    0
2057 #define M_BISTMODE    0x7
2058 #define V_BISTMODE(x) ((x) << S_BISTMODE)
2059 #define G_BISTMODE(x) (((x) >> S_BISTMODE) & M_BISTMODE)
2060 
2061 /* registers for module T3DBG */
2062 #define T3DBG_BASE_ADDR 0xc0
2063 
2064 #define A_T3DBG_DBG0_CFG 0xc0
2065 
2066 #define S_REGSELECT    9
2067 #define M_REGSELECT    0xff
2068 #define V_REGSELECT(x) ((x) << S_REGSELECT)
2069 #define G_REGSELECT(x) (((x) >> S_REGSELECT) & M_REGSELECT)
2070 
2071 #define S_MODULESELECT    4
2072 #define M_MODULESELECT    0x1f
2073 #define V_MODULESELECT(x) ((x) << S_MODULESELECT)
2074 #define G_MODULESELECT(x) (((x) >> S_MODULESELECT) & M_MODULESELECT)
2075 
2076 #define S_CLKSELECT    0
2077 #define M_CLKSELECT    0xf
2078 #define V_CLKSELECT(x) ((x) << S_CLKSELECT)
2079 #define G_CLKSELECT(x) (((x) >> S_CLKSELECT) & M_CLKSELECT)
2080 
2081 #define A_T3DBG_DBG0_EN 0xc4
2082 
2083 #define S_SDRBYTE0    8
2084 #define V_SDRBYTE0(x) ((x) << S_SDRBYTE0)
2085 #define F_SDRBYTE0    V_SDRBYTE0(1U)
2086 
2087 #define S_DDREN    4
2088 #define V_DDREN(x) ((x) << S_DDREN)
2089 #define F_DDREN    V_DDREN(1U)
2090 
2091 #define S_PORTEN    0
2092 #define V_PORTEN(x) ((x) << S_PORTEN)
2093 #define F_PORTEN    V_PORTEN(1U)
2094 
2095 #define A_T3DBG_DBG1_CFG 0xc8
2096 #define A_T3DBG_DBG1_EN 0xcc
2097 #define A_T3DBG_GPIO_EN 0xd0
2098 
2099 #define S_GPIO11_OEN    27
2100 #define V_GPIO11_OEN(x) ((x) << S_GPIO11_OEN)
2101 #define F_GPIO11_OEN    V_GPIO11_OEN(1U)
2102 
2103 #define S_GPIO10_OEN    26
2104 #define V_GPIO10_OEN(x) ((x) << S_GPIO10_OEN)
2105 #define F_GPIO10_OEN    V_GPIO10_OEN(1U)
2106 
2107 #define S_GPIO9_OEN    25
2108 #define V_GPIO9_OEN(x) ((x) << S_GPIO9_OEN)
2109 #define F_GPIO9_OEN    V_GPIO9_OEN(1U)
2110 
2111 #define S_GPIO8_OEN    24
2112 #define V_GPIO8_OEN(x) ((x) << S_GPIO8_OEN)
2113 #define F_GPIO8_OEN    V_GPIO8_OEN(1U)
2114 
2115 #define S_GPIO7_OEN    23
2116 #define V_GPIO7_OEN(x) ((x) << S_GPIO7_OEN)
2117 #define F_GPIO7_OEN    V_GPIO7_OEN(1U)
2118 
2119 #define S_GPIO6_OEN    22
2120 #define V_GPIO6_OEN(x) ((x) << S_GPIO6_OEN)
2121 #define F_GPIO6_OEN    V_GPIO6_OEN(1U)
2122 
2123 #define S_GPIO5_OEN    21
2124 #define V_GPIO5_OEN(x) ((x) << S_GPIO5_OEN)
2125 #define F_GPIO5_OEN    V_GPIO5_OEN(1U)
2126 
2127 #define S_GPIO4_OEN    20
2128 #define V_GPIO4_OEN(x) ((x) << S_GPIO4_OEN)
2129 #define F_GPIO4_OEN    V_GPIO4_OEN(1U)
2130 
2131 #define S_GPIO3_OEN    19
2132 #define V_GPIO3_OEN(x) ((x) << S_GPIO3_OEN)
2133 #define F_GPIO3_OEN    V_GPIO3_OEN(1U)
2134 
2135 #define S_GPIO2_OEN    18
2136 #define V_GPIO2_OEN(x) ((x) << S_GPIO2_OEN)
2137 #define F_GPIO2_OEN    V_GPIO2_OEN(1U)
2138 
2139 #define S_GPIO1_OEN    17
2140 #define V_GPIO1_OEN(x) ((x) << S_GPIO1_OEN)
2141 #define F_GPIO1_OEN    V_GPIO1_OEN(1U)
2142 
2143 #define S_GPIO0_OEN    16
2144 #define V_GPIO0_OEN(x) ((x) << S_GPIO0_OEN)
2145 #define F_GPIO0_OEN    V_GPIO0_OEN(1U)
2146 
2147 #define S_GPIO11_OUT_VAL    11
2148 #define V_GPIO11_OUT_VAL(x) ((x) << S_GPIO11_OUT_VAL)
2149 #define F_GPIO11_OUT_VAL    V_GPIO11_OUT_VAL(1U)
2150 
2151 #define S_GPIO10_OUT_VAL    10
2152 #define V_GPIO10_OUT_VAL(x) ((x) << S_GPIO10_OUT_VAL)
2153 #define F_GPIO10_OUT_VAL    V_GPIO10_OUT_VAL(1U)
2154 
2155 #define S_GPIO9_OUT_VAL    9
2156 #define V_GPIO9_OUT_VAL(x) ((x) << S_GPIO9_OUT_VAL)
2157 #define F_GPIO9_OUT_VAL    V_GPIO9_OUT_VAL(1U)
2158 
2159 #define S_GPIO8_OUT_VAL    8
2160 #define V_GPIO8_OUT_VAL(x) ((x) << S_GPIO8_OUT_VAL)
2161 #define F_GPIO8_OUT_VAL    V_GPIO8_OUT_VAL(1U)
2162 
2163 #define S_GPIO7_OUT_VAL    7
2164 #define V_GPIO7_OUT_VAL(x) ((x) << S_GPIO7_OUT_VAL)
2165 #define F_GPIO7_OUT_VAL    V_GPIO7_OUT_VAL(1U)
2166 
2167 #define S_GPIO6_OUT_VAL    6
2168 #define V_GPIO6_OUT_VAL(x) ((x) << S_GPIO6_OUT_VAL)
2169 #define F_GPIO6_OUT_VAL    V_GPIO6_OUT_VAL(1U)
2170 
2171 #define S_GPIO5_OUT_VAL    5
2172 #define V_GPIO5_OUT_VAL(x) ((x) << S_GPIO5_OUT_VAL)
2173 #define F_GPIO5_OUT_VAL    V_GPIO5_OUT_VAL(1U)
2174 
2175 #define S_GPIO4_OUT_VAL    4
2176 #define V_GPIO4_OUT_VAL(x) ((x) << S_GPIO4_OUT_VAL)
2177 #define F_GPIO4_OUT_VAL    V_GPIO4_OUT_VAL(1U)
2178 
2179 #define S_GPIO3_OUT_VAL    3
2180 #define V_GPIO3_OUT_VAL(x) ((x) << S_GPIO3_OUT_VAL)
2181 #define F_GPIO3_OUT_VAL    V_GPIO3_OUT_VAL(1U)
2182 
2183 #define S_GPIO2_OUT_VAL    2
2184 #define V_GPIO2_OUT_VAL(x) ((x) << S_GPIO2_OUT_VAL)
2185 #define F_GPIO2_OUT_VAL    V_GPIO2_OUT_VAL(1U)
2186 
2187 #define S_GPIO1_OUT_VAL    1
2188 #define V_GPIO1_OUT_VAL(x) ((x) << S_GPIO1_OUT_VAL)
2189 #define F_GPIO1_OUT_VAL    V_GPIO1_OUT_VAL(1U)
2190 
2191 #define S_GPIO0_OUT_VAL    0
2192 #define V_GPIO0_OUT_VAL(x) ((x) << S_GPIO0_OUT_VAL)
2193 #define F_GPIO0_OUT_VAL    V_GPIO0_OUT_VAL(1U)
2194 
2195 #define A_T3DBG_GPIO_IN 0xd4
2196 
2197 #define S_GPIO11_CHG_DET    27
2198 #define V_GPIO11_CHG_DET(x) ((x) << S_GPIO11_CHG_DET)
2199 #define F_GPIO11_CHG_DET    V_GPIO11_CHG_DET(1U)
2200 
2201 #define S_GPIO10_CHG_DET    26
2202 #define V_GPIO10_CHG_DET(x) ((x) << S_GPIO10_CHG_DET)
2203 #define F_GPIO10_CHG_DET    V_GPIO10_CHG_DET(1U)
2204 
2205 #define S_GPIO9_CHG_DET    25
2206 #define V_GPIO9_CHG_DET(x) ((x) << S_GPIO9_CHG_DET)
2207 #define F_GPIO9_CHG_DET    V_GPIO9_CHG_DET(1U)
2208 
2209 #define S_GPIO8_CHG_DET    24
2210 #define V_GPIO8_CHG_DET(x) ((x) << S_GPIO8_CHG_DET)
2211 #define F_GPIO8_CHG_DET    V_GPIO8_CHG_DET(1U)
2212 
2213 #define S_GPIO7_CHG_DET    23
2214 #define V_GPIO7_CHG_DET(x) ((x) << S_GPIO7_CHG_DET)
2215 #define F_GPIO7_CHG_DET    V_GPIO7_CHG_DET(1U)
2216 
2217 #define S_GPIO6_CHG_DET    22
2218 #define V_GPIO6_CHG_DET(x) ((x) << S_GPIO6_CHG_DET)
2219 #define F_GPIO6_CHG_DET    V_GPIO6_CHG_DET(1U)
2220 
2221 #define S_GPIO5_CHG_DET    21
2222 #define V_GPIO5_CHG_DET(x) ((x) << S_GPIO5_CHG_DET)
2223 #define F_GPIO5_CHG_DET    V_GPIO5_CHG_DET(1U)
2224 
2225 #define S_GPIO4_CHG_DET    20
2226 #define V_GPIO4_CHG_DET(x) ((x) << S_GPIO4_CHG_DET)
2227 #define F_GPIO4_CHG_DET    V_GPIO4_CHG_DET(1U)
2228 
2229 #define S_GPIO3_CHG_DET    19
2230 #define V_GPIO3_CHG_DET(x) ((x) << S_GPIO3_CHG_DET)
2231 #define F_GPIO3_CHG_DET    V_GPIO3_CHG_DET(1U)
2232 
2233 #define S_GPIO2_CHG_DET    18
2234 #define V_GPIO2_CHG_DET(x) ((x) << S_GPIO2_CHG_DET)
2235 #define F_GPIO2_CHG_DET    V_GPIO2_CHG_DET(1U)
2236 
2237 #define S_GPIO1_CHG_DET    17
2238 #define V_GPIO1_CHG_DET(x) ((x) << S_GPIO1_CHG_DET)
2239 #define F_GPIO1_CHG_DET    V_GPIO1_CHG_DET(1U)
2240 
2241 #define S_GPIO0_CHG_DET    16
2242 #define V_GPIO0_CHG_DET(x) ((x) << S_GPIO0_CHG_DET)
2243 #define F_GPIO0_CHG_DET    V_GPIO0_CHG_DET(1U)
2244 
2245 #define S_GPIO11_IN    11
2246 #define V_GPIO11_IN(x) ((x) << S_GPIO11_IN)
2247 #define F_GPIO11_IN    V_GPIO11_IN(1U)
2248 
2249 #define S_GPIO10_IN    10
2250 #define V_GPIO10_IN(x) ((x) << S_GPIO10_IN)
2251 #define F_GPIO10_IN    V_GPIO10_IN(1U)
2252 
2253 #define S_GPIO9_IN    9
2254 #define V_GPIO9_IN(x) ((x) << S_GPIO9_IN)
2255 #define F_GPIO9_IN    V_GPIO9_IN(1U)
2256 
2257 #define S_GPIO8_IN    8
2258 #define V_GPIO8_IN(x) ((x) << S_GPIO8_IN)
2259 #define F_GPIO8_IN    V_GPIO8_IN(1U)
2260 
2261 #define S_GPIO7_IN    7
2262 #define V_GPIO7_IN(x) ((x) << S_GPIO7_IN)
2263 #define F_GPIO7_IN    V_GPIO7_IN(1U)
2264 
2265 #define S_GPIO6_IN    6
2266 #define V_GPIO6_IN(x) ((x) << S_GPIO6_IN)
2267 #define F_GPIO6_IN    V_GPIO6_IN(1U)
2268 
2269 #define S_GPIO5_IN    5
2270 #define V_GPIO5_IN(x) ((x) << S_GPIO5_IN)
2271 #define F_GPIO5_IN    V_GPIO5_IN(1U)
2272 
2273 #define S_GPIO4_IN    4
2274 #define V_GPIO4_IN(x) ((x) << S_GPIO4_IN)
2275 #define F_GPIO4_IN    V_GPIO4_IN(1U)
2276 
2277 #define S_GPIO3_IN    3
2278 #define V_GPIO3_IN(x) ((x) << S_GPIO3_IN)
2279 #define F_GPIO3_IN    V_GPIO3_IN(1U)
2280 
2281 #define S_GPIO2_IN    2
2282 #define V_GPIO2_IN(x) ((x) << S_GPIO2_IN)
2283 #define F_GPIO2_IN    V_GPIO2_IN(1U)
2284 
2285 #define S_GPIO1_IN    1
2286 #define V_GPIO1_IN(x) ((x) << S_GPIO1_IN)
2287 #define F_GPIO1_IN    V_GPIO1_IN(1U)
2288 
2289 #define S_GPIO0_IN    0
2290 #define V_GPIO0_IN(x) ((x) << S_GPIO0_IN)
2291 #define F_GPIO0_IN    V_GPIO0_IN(1U)
2292 
2293 #define A_T3DBG_INT_ENABLE 0xd8
2294 
2295 #define S_C_LOCK    21
2296 #define V_C_LOCK(x) ((x) << S_C_LOCK)
2297 #define F_C_LOCK    V_C_LOCK(1U)
2298 
2299 #define S_M_LOCK    20
2300 #define V_M_LOCK(x) ((x) << S_M_LOCK)
2301 #define F_M_LOCK    V_M_LOCK(1U)
2302 
2303 #define S_U_LOCK    19
2304 #define V_U_LOCK(x) ((x) << S_U_LOCK)
2305 #define F_U_LOCK    V_U_LOCK(1U)
2306 
2307 #define S_R_LOCK    18
2308 #define V_R_LOCK(x) ((x) << S_R_LOCK)
2309 #define F_R_LOCK    V_R_LOCK(1U)
2310 
2311 #define S_PX_LOCK    17
2312 #define V_PX_LOCK(x) ((x) << S_PX_LOCK)
2313 #define F_PX_LOCK    V_PX_LOCK(1U)
2314 
2315 #define S_GPIO11    11
2316 #define V_GPIO11(x) ((x) << S_GPIO11)
2317 #define F_GPIO11    V_GPIO11(1U)
2318 
2319 #define S_GPIO10    10
2320 #define V_GPIO10(x) ((x) << S_GPIO10)
2321 #define F_GPIO10    V_GPIO10(1U)
2322 
2323 #define S_GPIO9    9
2324 #define V_GPIO9(x) ((x) << S_GPIO9)
2325 #define F_GPIO9    V_GPIO9(1U)
2326 
2327 #define S_GPIO8    8
2328 #define V_GPIO8(x) ((x) << S_GPIO8)
2329 #define F_GPIO8    V_GPIO8(1U)
2330 
2331 #define S_GPIO7    7
2332 #define V_GPIO7(x) ((x) << S_GPIO7)
2333 #define F_GPIO7    V_GPIO7(1U)
2334 
2335 #define S_GPIO6    6
2336 #define V_GPIO6(x) ((x) << S_GPIO6)
2337 #define F_GPIO6    V_GPIO6(1U)
2338 
2339 #define S_GPIO5    5
2340 #define V_GPIO5(x) ((x) << S_GPIO5)
2341 #define F_GPIO5    V_GPIO5(1U)
2342 
2343 #define S_GPIO4    4
2344 #define V_GPIO4(x) ((x) << S_GPIO4)
2345 #define F_GPIO4    V_GPIO4(1U)
2346 
2347 #define S_GPIO3    3
2348 #define V_GPIO3(x) ((x) << S_GPIO3)
2349 #define F_GPIO3    V_GPIO3(1U)
2350 
2351 #define S_GPIO2    2
2352 #define V_GPIO2(x) ((x) << S_GPIO2)
2353 #define F_GPIO2    V_GPIO2(1U)
2354 
2355 #define S_GPIO1    1
2356 #define V_GPIO1(x) ((x) << S_GPIO1)
2357 #define F_GPIO1    V_GPIO1(1U)
2358 
2359 #define S_GPIO0    0
2360 #define V_GPIO0(x) ((x) << S_GPIO0)
2361 #define F_GPIO0    V_GPIO0(1U)
2362 
2363 #define S_PE_LOCK    16
2364 #define V_PE_LOCK(x) ((x) << S_PE_LOCK)
2365 #define F_PE_LOCK    V_PE_LOCK(1U)
2366 
2367 #define A_T3DBG_INT_CAUSE 0xdc
2368 #define A_T3DBG_DBG0_RST_VALUE 0xe0
2369 
2370 #define S_DEBUGDATA    0
2371 #define M_DEBUGDATA    0xff
2372 #define V_DEBUGDATA(x) ((x) << S_DEBUGDATA)
2373 #define G_DEBUGDATA(x) (((x) >> S_DEBUGDATA) & M_DEBUGDATA)
2374 
2375 #define A_T3DBG_PLL_OCLK_PAD_EN 0xe4
2376 
2377 #define S_PCIE_OCLK_EN    20
2378 #define V_PCIE_OCLK_EN(x) ((x) << S_PCIE_OCLK_EN)
2379 #define F_PCIE_OCLK_EN    V_PCIE_OCLK_EN(1U)
2380 
2381 #define S_PCLKTREE_DBG_EN    17
2382 #define V_PCLKTREE_DBG_EN(x) ((x) << S_PCLKTREE_DBG_EN)
2383 #define F_PCLKTREE_DBG_EN    V_PCLKTREE_DBG_EN(1U)
2384 
2385 #define S_PCIX_OCLK_EN    16
2386 #define V_PCIX_OCLK_EN(x) ((x) << S_PCIX_OCLK_EN)
2387 #define F_PCIX_OCLK_EN    V_PCIX_OCLK_EN(1U)
2388 
2389 #define S_U_OCLK_EN    12
2390 #define V_U_OCLK_EN(x) ((x) << S_U_OCLK_EN)
2391 #define F_U_OCLK_EN    V_U_OCLK_EN(1U)
2392 
2393 #define S_R_OCLK_EN    8
2394 #define V_R_OCLK_EN(x) ((x) << S_R_OCLK_EN)
2395 #define F_R_OCLK_EN    V_R_OCLK_EN(1U)
2396 
2397 #define S_M_OCLK_EN    4
2398 #define V_M_OCLK_EN(x) ((x) << S_M_OCLK_EN)
2399 #define F_M_OCLK_EN    V_M_OCLK_EN(1U)
2400 
2401 #define S_C_OCLK_EN    0
2402 #define V_C_OCLK_EN(x) ((x) << S_C_OCLK_EN)
2403 #define F_C_OCLK_EN    V_C_OCLK_EN(1U)
2404 
2405 #define A_T3DBG_PLL_LOCK 0xe8
2406 
2407 #define S_PCIX_LOCK    16
2408 #define V_PCIX_LOCK(x) ((x) << S_PCIX_LOCK)
2409 #define F_PCIX_LOCK    V_PCIX_LOCK(1U)
2410 
2411 #define S_PLL_U_LOCK    12
2412 #define V_PLL_U_LOCK(x) ((x) << S_PLL_U_LOCK)
2413 #define F_PLL_U_LOCK    V_PLL_U_LOCK(1U)
2414 
2415 #define S_PLL_R_LOCK    8
2416 #define V_PLL_R_LOCK(x) ((x) << S_PLL_R_LOCK)
2417 #define F_PLL_R_LOCK    V_PLL_R_LOCK(1U)
2418 
2419 #define S_PLL_M_LOCK    4
2420 #define V_PLL_M_LOCK(x) ((x) << S_PLL_M_LOCK)
2421 #define F_PLL_M_LOCK    V_PLL_M_LOCK(1U)
2422 
2423 #define S_PLL_C_LOCK    0
2424 #define V_PLL_C_LOCK(x) ((x) << S_PLL_C_LOCK)
2425 #define F_PLL_C_LOCK    V_PLL_C_LOCK(1U)
2426 
2427 #define S_PCIE_LOCK    20
2428 #define V_PCIE_LOCK(x) ((x) << S_PCIE_LOCK)
2429 #define F_PCIE_LOCK    V_PCIE_LOCK(1U)
2430 
2431 #define A_T3DBG_SERDES_RBC_CFG 0xec
2432 
2433 #define S_X_RBC_LANE_SEL    16
2434 #define M_X_RBC_LANE_SEL    0x3
2435 #define V_X_RBC_LANE_SEL(x) ((x) << S_X_RBC_LANE_SEL)
2436 #define G_X_RBC_LANE_SEL(x) (((x) >> S_X_RBC_LANE_SEL) & M_X_RBC_LANE_SEL)
2437 
2438 #define S_X_RBC_DBG_EN    12
2439 #define V_X_RBC_DBG_EN(x) ((x) << S_X_RBC_DBG_EN)
2440 #define F_X_RBC_DBG_EN    V_X_RBC_DBG_EN(1U)
2441 
2442 #define S_X_SERDES_SEL    8
2443 #define V_X_SERDES_SEL(x) ((x) << S_X_SERDES_SEL)
2444 #define F_X_SERDES_SEL    V_X_SERDES_SEL(1U)
2445 
2446 #define S_PE_RBC_LANE_SEL    4
2447 #define M_PE_RBC_LANE_SEL    0x7
2448 #define V_PE_RBC_LANE_SEL(x) ((x) << S_PE_RBC_LANE_SEL)
2449 #define G_PE_RBC_LANE_SEL(x) (((x) >> S_PE_RBC_LANE_SEL) & M_PE_RBC_LANE_SEL)
2450 
2451 #define S_PE_RBC_DBG_EN    0
2452 #define V_PE_RBC_DBG_EN(x) ((x) << S_PE_RBC_DBG_EN)
2453 #define F_PE_RBC_DBG_EN    V_PE_RBC_DBG_EN(1U)
2454 
2455 #define A_T3DBG_GPIO_ACT_LOW 0xf0
2456 
2457 #define S_C_LOCK_ACT_LOW    21
2458 #define V_C_LOCK_ACT_LOW(x) ((x) << S_C_LOCK_ACT_LOW)
2459 #define F_C_LOCK_ACT_LOW    V_C_LOCK_ACT_LOW(1U)
2460 
2461 #define S_M_LOCK_ACT_LOW    20
2462 #define V_M_LOCK_ACT_LOW(x) ((x) << S_M_LOCK_ACT_LOW)
2463 #define F_M_LOCK_ACT_LOW    V_M_LOCK_ACT_LOW(1U)
2464 
2465 #define S_U_LOCK_ACT_LOW    19
2466 #define V_U_LOCK_ACT_LOW(x) ((x) << S_U_LOCK_ACT_LOW)
2467 #define F_U_LOCK_ACT_LOW    V_U_LOCK_ACT_LOW(1U)
2468 
2469 #define S_R_LOCK_ACT_LOW    18
2470 #define V_R_LOCK_ACT_LOW(x) ((x) << S_R_LOCK_ACT_LOW)
2471 #define F_R_LOCK_ACT_LOW    V_R_LOCK_ACT_LOW(1U)
2472 
2473 #define S_PX_LOCK_ACT_LOW    17
2474 #define V_PX_LOCK_ACT_LOW(x) ((x) << S_PX_LOCK_ACT_LOW)
2475 #define F_PX_LOCK_ACT_LOW    V_PX_LOCK_ACT_LOW(1U)
2476 
2477 #define S_GPIO11_ACT_LOW    11
2478 #define V_GPIO11_ACT_LOW(x) ((x) << S_GPIO11_ACT_LOW)
2479 #define F_GPIO11_ACT_LOW    V_GPIO11_ACT_LOW(1U)
2480 
2481 #define S_GPIO10_ACT_LOW    10
2482 #define V_GPIO10_ACT_LOW(x) ((x) << S_GPIO10_ACT_LOW)
2483 #define F_GPIO10_ACT_LOW    V_GPIO10_ACT_LOW(1U)
2484 
2485 #define S_GPIO9_ACT_LOW    9
2486 #define V_GPIO9_ACT_LOW(x) ((x) << S_GPIO9_ACT_LOW)
2487 #define F_GPIO9_ACT_LOW    V_GPIO9_ACT_LOW(1U)
2488 
2489 #define S_GPIO8_ACT_LOW    8
2490 #define V_GPIO8_ACT_LOW(x) ((x) << S_GPIO8_ACT_LOW)
2491 #define F_GPIO8_ACT_LOW    V_GPIO8_ACT_LOW(1U)
2492 
2493 #define S_GPIO7_ACT_LOW    7
2494 #define V_GPIO7_ACT_LOW(x) ((x) << S_GPIO7_ACT_LOW)
2495 #define F_GPIO7_ACT_LOW    V_GPIO7_ACT_LOW(1U)
2496 
2497 #define S_GPIO6_ACT_LOW    6
2498 #define V_GPIO6_ACT_LOW(x) ((x) << S_GPIO6_ACT_LOW)
2499 #define F_GPIO6_ACT_LOW    V_GPIO6_ACT_LOW(1U)
2500 
2501 #define S_GPIO5_ACT_LOW    5
2502 #define V_GPIO5_ACT_LOW(x) ((x) << S_GPIO5_ACT_LOW)
2503 #define F_GPIO5_ACT_LOW    V_GPIO5_ACT_LOW(1U)
2504 
2505 #define S_GPIO4_ACT_LOW    4
2506 #define V_GPIO4_ACT_LOW(x) ((x) << S_GPIO4_ACT_LOW)
2507 #define F_GPIO4_ACT_LOW    V_GPIO4_ACT_LOW(1U)
2508 
2509 #define S_GPIO3_ACT_LOW    3
2510 #define V_GPIO3_ACT_LOW(x) ((x) << S_GPIO3_ACT_LOW)
2511 #define F_GPIO3_ACT_LOW    V_GPIO3_ACT_LOW(1U)
2512 
2513 #define S_GPIO2_ACT_LOW    2
2514 #define V_GPIO2_ACT_LOW(x) ((x) << S_GPIO2_ACT_LOW)
2515 #define F_GPIO2_ACT_LOW    V_GPIO2_ACT_LOW(1U)
2516 
2517 #define S_GPIO1_ACT_LOW    1
2518 #define V_GPIO1_ACT_LOW(x) ((x) << S_GPIO1_ACT_LOW)
2519 #define F_GPIO1_ACT_LOW    V_GPIO1_ACT_LOW(1U)
2520 
2521 #define S_GPIO0_ACT_LOW    0
2522 #define V_GPIO0_ACT_LOW(x) ((x) << S_GPIO0_ACT_LOW)
2523 #define F_GPIO0_ACT_LOW    V_GPIO0_ACT_LOW(1U)
2524 
2525 #define S_PE_LOCK_ACT_LOW    16
2526 #define V_PE_LOCK_ACT_LOW(x) ((x) << S_PE_LOCK_ACT_LOW)
2527 #define F_PE_LOCK_ACT_LOW    V_PE_LOCK_ACT_LOW(1U)
2528 
2529 #define A_T3DBG_PMON_CFG 0xf4
2530 
2531 #define S_PMON_DONE    29
2532 #define V_PMON_DONE(x) ((x) << S_PMON_DONE)
2533 #define F_PMON_DONE    V_PMON_DONE(1U)
2534 
2535 #define S_PMON_FAIL    28
2536 #define V_PMON_FAIL(x) ((x) << S_PMON_FAIL)
2537 #define F_PMON_FAIL    V_PMON_FAIL(1U)
2538 
2539 #define S_PMON_FDEL_AUTO    22
2540 #define M_PMON_FDEL_AUTO    0x3f
2541 #define V_PMON_FDEL_AUTO(x) ((x) << S_PMON_FDEL_AUTO)
2542 #define G_PMON_FDEL_AUTO(x) (((x) >> S_PMON_FDEL_AUTO) & M_PMON_FDEL_AUTO)
2543 
2544 #define S_PMON_CDEL_AUTO    16
2545 #define M_PMON_CDEL_AUTO    0x3f
2546 #define V_PMON_CDEL_AUTO(x) ((x) << S_PMON_CDEL_AUTO)
2547 #define G_PMON_CDEL_AUTO(x) (((x) >> S_PMON_CDEL_AUTO) & M_PMON_CDEL_AUTO)
2548 
2549 #define S_PMON_FDEL_MANUAL    10
2550 #define M_PMON_FDEL_MANUAL    0x3f
2551 #define V_PMON_FDEL_MANUAL(x) ((x) << S_PMON_FDEL_MANUAL)
2552 #define G_PMON_FDEL_MANUAL(x) (((x) >> S_PMON_FDEL_MANUAL) & M_PMON_FDEL_MANUAL)
2553 
2554 #define S_PMON_CDEL_MANUAL    4
2555 #define M_PMON_CDEL_MANUAL    0x3f
2556 #define V_PMON_CDEL_MANUAL(x) ((x) << S_PMON_CDEL_MANUAL)
2557 #define G_PMON_CDEL_MANUAL(x) (((x) >> S_PMON_CDEL_MANUAL) & M_PMON_CDEL_MANUAL)
2558 
2559 #define S_PMON_MANUAL    1
2560 #define V_PMON_MANUAL(x) ((x) << S_PMON_MANUAL)
2561 #define F_PMON_MANUAL    V_PMON_MANUAL(1U)
2562 
2563 #define S_PMON_AUTO    0
2564 #define V_PMON_AUTO(x) ((x) << S_PMON_AUTO)
2565 #define F_PMON_AUTO    V_PMON_AUTO(1U)
2566 
2567 #define A_T3DBG_SERDES_REFCLK_CFG 0xf8
2568 
2569 #define S_PE_REFCLK_DBG_EN    12
2570 #define V_PE_REFCLK_DBG_EN(x) ((x) << S_PE_REFCLK_DBG_EN)
2571 #define F_PE_REFCLK_DBG_EN    V_PE_REFCLK_DBG_EN(1U)
2572 
2573 #define S_X_REFCLK_DBG_EN    8
2574 #define V_X_REFCLK_DBG_EN(x) ((x) << S_X_REFCLK_DBG_EN)
2575 #define F_X_REFCLK_DBG_EN    V_X_REFCLK_DBG_EN(1U)
2576 
2577 #define S_PE_REFCLK_TERMADJ    5
2578 #define M_PE_REFCLK_TERMADJ    0x3
2579 #define V_PE_REFCLK_TERMADJ(x) ((x) << S_PE_REFCLK_TERMADJ)
2580 #define G_PE_REFCLK_TERMADJ(x) (((x) >> S_PE_REFCLK_TERMADJ) & M_PE_REFCLK_TERMADJ)
2581 
2582 #define S_PE_REFCLK_PD    4
2583 #define V_PE_REFCLK_PD(x) ((x) << S_PE_REFCLK_PD)
2584 #define F_PE_REFCLK_PD    V_PE_REFCLK_PD(1U)
2585 
2586 #define S_X_REFCLK_TERMADJ    1
2587 #define M_X_REFCLK_TERMADJ    0x3
2588 #define V_X_REFCLK_TERMADJ(x) ((x) << S_X_REFCLK_TERMADJ)
2589 #define G_X_REFCLK_TERMADJ(x) (((x) >> S_X_REFCLK_TERMADJ) & M_X_REFCLK_TERMADJ)
2590 
2591 #define S_X_REFCLK_PD    0
2592 #define V_X_REFCLK_PD(x) ((x) << S_X_REFCLK_PD)
2593 #define F_X_REFCLK_PD    V_X_REFCLK_PD(1U)
2594 
2595 #define A_T3DBG_PCIE_PMA_BSPIN_CFG 0xfc
2596 
2597 #define S_BSMODEQUAD1    31
2598 #define V_BSMODEQUAD1(x) ((x) << S_BSMODEQUAD1)
2599 #define F_BSMODEQUAD1    V_BSMODEQUAD1(1U)
2600 
2601 #define S_BSINSELLANE7    29
2602 #define M_BSINSELLANE7    0x3
2603 #define V_BSINSELLANE7(x) ((x) << S_BSINSELLANE7)
2604 #define G_BSINSELLANE7(x) (((x) >> S_BSINSELLANE7) & M_BSINSELLANE7)
2605 
2606 #define S_BSENLANE7    28
2607 #define V_BSENLANE7(x) ((x) << S_BSENLANE7)
2608 #define F_BSENLANE7    V_BSENLANE7(1U)
2609 
2610 #define S_BSINSELLANE6    25
2611 #define M_BSINSELLANE6    0x3
2612 #define V_BSINSELLANE6(x) ((x) << S_BSINSELLANE6)
2613 #define G_BSINSELLANE6(x) (((x) >> S_BSINSELLANE6) & M_BSINSELLANE6)
2614 
2615 #define S_BSENLANE6    24
2616 #define V_BSENLANE6(x) ((x) << S_BSENLANE6)
2617 #define F_BSENLANE6    V_BSENLANE6(1U)
2618 
2619 #define S_BSINSELLANE5    21
2620 #define M_BSINSELLANE5    0x3
2621 #define V_BSINSELLANE5(x) ((x) << S_BSINSELLANE5)
2622 #define G_BSINSELLANE5(x) (((x) >> S_BSINSELLANE5) & M_BSINSELLANE5)
2623 
2624 #define S_BSENLANE5    20
2625 #define V_BSENLANE5(x) ((x) << S_BSENLANE5)
2626 #define F_BSENLANE5    V_BSENLANE5(1U)
2627 
2628 #define S_BSINSELLANE4    17
2629 #define M_BSINSELLANE4    0x3
2630 #define V_BSINSELLANE4(x) ((x) << S_BSINSELLANE4)
2631 #define G_BSINSELLANE4(x) (((x) >> S_BSINSELLANE4) & M_BSINSELLANE4)
2632 
2633 #define S_BSENLANE4    16
2634 #define V_BSENLANE4(x) ((x) << S_BSENLANE4)
2635 #define F_BSENLANE4    V_BSENLANE4(1U)
2636 
2637 #define S_BSMODEQUAD0    15
2638 #define V_BSMODEQUAD0(x) ((x) << S_BSMODEQUAD0)
2639 #define F_BSMODEQUAD0    V_BSMODEQUAD0(1U)
2640 
2641 #define S_BSINSELLANE3    13
2642 #define M_BSINSELLANE3    0x3
2643 #define V_BSINSELLANE3(x) ((x) << S_BSINSELLANE3)
2644 #define G_BSINSELLANE3(x) (((x) >> S_BSINSELLANE3) & M_BSINSELLANE3)
2645 
2646 #define S_BSENLANE3    12
2647 #define V_BSENLANE3(x) ((x) << S_BSENLANE3)
2648 #define F_BSENLANE3    V_BSENLANE3(1U)
2649 
2650 #define S_BSINSELLANE2    9
2651 #define M_BSINSELLANE2    0x3
2652 #define V_BSINSELLANE2(x) ((x) << S_BSINSELLANE2)
2653 #define G_BSINSELLANE2(x) (((x) >> S_BSINSELLANE2) & M_BSINSELLANE2)
2654 
2655 #define S_BSENLANE2    8
2656 #define V_BSENLANE2(x) ((x) << S_BSENLANE2)
2657 #define F_BSENLANE2    V_BSENLANE2(1U)
2658 
2659 #define S_BSINSELLANE1    5
2660 #define M_BSINSELLANE1    0x3
2661 #define V_BSINSELLANE1(x) ((x) << S_BSINSELLANE1)
2662 #define G_BSINSELLANE1(x) (((x) >> S_BSINSELLANE1) & M_BSINSELLANE1)
2663 
2664 #define S_BSENLANE1    4
2665 #define V_BSENLANE1(x) ((x) << S_BSENLANE1)
2666 #define F_BSENLANE1    V_BSENLANE1(1U)
2667 
2668 #define S_BSINSELLANE0    1
2669 #define M_BSINSELLANE0    0x3
2670 #define V_BSINSELLANE0(x) ((x) << S_BSINSELLANE0)
2671 #define G_BSINSELLANE0(x) (((x) >> S_BSINSELLANE0) & M_BSINSELLANE0)
2672 
2673 #define S_BSENLANE0    0
2674 #define V_BSENLANE0(x) ((x) << S_BSENLANE0)
2675 #define F_BSENLANE0    V_BSENLANE0(1U)
2676 
2677 /* registers for module MC7_PMRX */
2678 #define MC7_PMRX_BASE_ADDR 0x100
2679 
2680 #define A_MC7_CFG 0x100
2681 
2682 #define S_IMPSETUPDATE    14
2683 #define V_IMPSETUPDATE(x) ((x) << S_IMPSETUPDATE)
2684 #define F_IMPSETUPDATE    V_IMPSETUPDATE(1U)
2685 
2686 #define S_IFEN    13
2687 #define V_IFEN(x) ((x) << S_IFEN)
2688 #define F_IFEN    V_IFEN(1U)
2689 
2690 #define S_TERM300    12
2691 #define V_TERM300(x) ((x) << S_TERM300)
2692 #define F_TERM300    V_TERM300(1U)
2693 
2694 #define S_TERM150    11
2695 #define V_TERM150(x) ((x) << S_TERM150)
2696 #define F_TERM150    V_TERM150(1U)
2697 
2698 #define S_SLOW    10
2699 #define V_SLOW(x) ((x) << S_SLOW)
2700 #define F_SLOW    V_SLOW(1U)
2701 
2702 #define S_WIDTH    8
2703 #define M_WIDTH    0x3
2704 #define V_WIDTH(x) ((x) << S_WIDTH)
2705 #define G_WIDTH(x) (((x) >> S_WIDTH) & M_WIDTH)
2706 
2707 #define S_ODTEN    7
2708 #define V_ODTEN(x) ((x) << S_ODTEN)
2709 #define F_ODTEN    V_ODTEN(1U)
2710 
2711 #define S_BKS    6
2712 #define V_BKS(x) ((x) << S_BKS)
2713 #define F_BKS    V_BKS(1U)
2714 
2715 #define S_ORG    5
2716 #define V_ORG(x) ((x) << S_ORG)
2717 #define F_ORG    V_ORG(1U)
2718 
2719 #define S_DEN    2
2720 #define M_DEN    0x7
2721 #define V_DEN(x) ((x) << S_DEN)
2722 #define G_DEN(x) (((x) >> S_DEN) & M_DEN)
2723 
2724 #define S_RDY    1
2725 #define V_RDY(x) ((x) << S_RDY)
2726 #define F_RDY    V_RDY(1U)
2727 
2728 #define S_CLKEN    0
2729 #define V_CLKEN(x) ((x) << S_CLKEN)
2730 #define F_CLKEN    V_CLKEN(1U)
2731 
2732 #define A_MC7_MODE 0x104
2733 
2734 #define S_MODE    0
2735 #define M_MODE    0xffff
2736 #define V_MODE(x) ((x) << S_MODE)
2737 #define G_MODE(x) (((x) >> S_MODE) & M_MODE)
2738 
2739 #define A_MC7_EXT_MODE1 0x108
2740 
2741 #define S_OCDADJUSTMODE    20
2742 #define V_OCDADJUSTMODE(x) ((x) << S_OCDADJUSTMODE)
2743 #define F_OCDADJUSTMODE    V_OCDADJUSTMODE(1U)
2744 
2745 #define S_OCDCODE    16
2746 #define M_OCDCODE    0xf
2747 #define V_OCDCODE(x) ((x) << S_OCDCODE)
2748 #define G_OCDCODE(x) (((x) >> S_OCDCODE) & M_OCDCODE)
2749 
2750 #define S_EXTMODE1    0
2751 #define M_EXTMODE1    0xffff
2752 #define V_EXTMODE1(x) ((x) << S_EXTMODE1)
2753 #define G_EXTMODE1(x) (((x) >> S_EXTMODE1) & M_EXTMODE1)
2754 
2755 #define A_MC7_EXT_MODE2 0x10c
2756 
2757 #define S_EXTMODE2    0
2758 #define M_EXTMODE2    0xffff
2759 #define V_EXTMODE2(x) ((x) << S_EXTMODE2)
2760 #define G_EXTMODE2(x) (((x) >> S_EXTMODE2) & M_EXTMODE2)
2761 
2762 #define A_MC7_EXT_MODE3 0x110
2763 
2764 #define S_EXTMODE3    0
2765 #define M_EXTMODE3    0xffff
2766 #define V_EXTMODE3(x) ((x) << S_EXTMODE3)
2767 #define G_EXTMODE3(x) (((x) >> S_EXTMODE3) & M_EXTMODE3)
2768 
2769 #define A_MC7_PRE 0x114
2770 #define A_MC7_REF 0x118
2771 
2772 #define S_PREREFDIV    1
2773 #define M_PREREFDIV    0x3fff
2774 #define V_PREREFDIV(x) ((x) << S_PREREFDIV)
2775 #define G_PREREFDIV(x) (((x) >> S_PREREFDIV) & M_PREREFDIV)
2776 
2777 #define S_PERREFEN    0
2778 #define V_PERREFEN(x) ((x) << S_PERREFEN)
2779 #define F_PERREFEN    V_PERREFEN(1U)
2780 
2781 #define A_MC7_DLL 0x11c
2782 
2783 #define S_DLLLOCK    31
2784 #define V_DLLLOCK(x) ((x) << S_DLLLOCK)
2785 #define F_DLLLOCK    V_DLLLOCK(1U)
2786 
2787 #define S_DLLDELTA    24
2788 #define M_DLLDELTA    0x7f
2789 #define V_DLLDELTA(x) ((x) << S_DLLDELTA)
2790 #define G_DLLDELTA(x) (((x) >> S_DLLDELTA) & M_DLLDELTA)
2791 
2792 #define S_MANDELTA    3
2793 #define M_MANDELTA    0x7f
2794 #define V_MANDELTA(x) ((x) << S_MANDELTA)
2795 #define G_MANDELTA(x) (((x) >> S_MANDELTA) & M_MANDELTA)
2796 
2797 #define S_DLLDELTASEL    2
2798 #define V_DLLDELTASEL(x) ((x) << S_DLLDELTASEL)
2799 #define F_DLLDELTASEL    V_DLLDELTASEL(1U)
2800 
2801 #define S_DLLENB    1
2802 #define V_DLLENB(x) ((x) << S_DLLENB)
2803 #define F_DLLENB    V_DLLENB(1U)
2804 
2805 #define S_DLLRST    0
2806 #define V_DLLRST(x) ((x) << S_DLLRST)
2807 #define F_DLLRST    V_DLLRST(1U)
2808 
2809 #define A_MC7_PARM 0x120
2810 
2811 #define S_ACTTOPREDLY    26
2812 #define M_ACTTOPREDLY    0xf
2813 #define V_ACTTOPREDLY(x) ((x) << S_ACTTOPREDLY)
2814 #define G_ACTTOPREDLY(x) (((x) >> S_ACTTOPREDLY) & M_ACTTOPREDLY)
2815 
2816 #define S_ACTTORDWRDLY    23
2817 #define M_ACTTORDWRDLY    0x7
2818 #define V_ACTTORDWRDLY(x) ((x) << S_ACTTORDWRDLY)
2819 #define G_ACTTORDWRDLY(x) (((x) >> S_ACTTORDWRDLY) & M_ACTTORDWRDLY)
2820 
2821 #define S_PRECYC    20
2822 #define M_PRECYC    0x7
2823 #define V_PRECYC(x) ((x) << S_PRECYC)
2824 #define G_PRECYC(x) (((x) >> S_PRECYC) & M_PRECYC)
2825 
2826 #define S_REFCYC    13
2827 #define M_REFCYC    0x7f
2828 #define V_REFCYC(x) ((x) << S_REFCYC)
2829 #define G_REFCYC(x) (((x) >> S_REFCYC) & M_REFCYC)
2830 
2831 #define S_BKCYC    8
2832 #define M_BKCYC    0x1f
2833 #define V_BKCYC(x) ((x) << S_BKCYC)
2834 #define G_BKCYC(x) (((x) >> S_BKCYC) & M_BKCYC)
2835 
2836 #define S_WRTORDDLY    4
2837 #define M_WRTORDDLY    0xf
2838 #define V_WRTORDDLY(x) ((x) << S_WRTORDDLY)
2839 #define G_WRTORDDLY(x) (((x) >> S_WRTORDDLY) & M_WRTORDDLY)
2840 
2841 #define S_RDTOWRDLY    0
2842 #define M_RDTOWRDLY    0xf
2843 #define V_RDTOWRDLY(x) ((x) << S_RDTOWRDLY)
2844 #define G_RDTOWRDLY(x) (((x) >> S_RDTOWRDLY) & M_RDTOWRDLY)
2845 
2846 #define A_MC7_HWM_WRR 0x124
2847 
2848 #define S_MEM_HWM    26
2849 #define M_MEM_HWM    0x3f
2850 #define V_MEM_HWM(x) ((x) << S_MEM_HWM)
2851 #define G_MEM_HWM(x) (((x) >> S_MEM_HWM) & M_MEM_HWM)
2852 
2853 #define S_ULP_HWM    22
2854 #define M_ULP_HWM    0xf
2855 #define V_ULP_HWM(x) ((x) << S_ULP_HWM)
2856 #define G_ULP_HWM(x) (((x) >> S_ULP_HWM) & M_ULP_HWM)
2857 
2858 #define S_TOT_RLD_WT    14
2859 #define M_TOT_RLD_WT    0xff
2860 #define V_TOT_RLD_WT(x) ((x) << S_TOT_RLD_WT)
2861 #define G_TOT_RLD_WT(x) (((x) >> S_TOT_RLD_WT) & M_TOT_RLD_WT)
2862 
2863 #define S_MEM_RLD_WT    7
2864 #define M_MEM_RLD_WT    0x7f
2865 #define V_MEM_RLD_WT(x) ((x) << S_MEM_RLD_WT)
2866 #define G_MEM_RLD_WT(x) (((x) >> S_MEM_RLD_WT) & M_MEM_RLD_WT)
2867 
2868 #define S_ULP_RLD_WT    0
2869 #define M_ULP_RLD_WT    0x7f
2870 #define V_ULP_RLD_WT(x) ((x) << S_ULP_RLD_WT)
2871 #define G_ULP_RLD_WT(x) (((x) >> S_ULP_RLD_WT) & M_ULP_RLD_WT)
2872 
2873 #define A_MC7_CAL 0x128
2874 
2875 #define S_BUSY    31
2876 #define V_BUSY(x) ((x) << S_BUSY)
2877 #define F_BUSY    V_BUSY(1U)
2878 
2879 #define S_CAL_FAULT    30
2880 #define V_CAL_FAULT(x) ((x) << S_CAL_FAULT)
2881 #define F_CAL_FAULT    V_CAL_FAULT(1U)
2882 
2883 #define S_PER_CAL_DIV    22
2884 #define M_PER_CAL_DIV    0xff
2885 #define V_PER_CAL_DIV(x) ((x) << S_PER_CAL_DIV)
2886 #define G_PER_CAL_DIV(x) (((x) >> S_PER_CAL_DIV) & M_PER_CAL_DIV)
2887 
2888 #define S_PER_CAL_EN    21
2889 #define V_PER_CAL_EN(x) ((x) << S_PER_CAL_EN)
2890 #define F_PER_CAL_EN    V_PER_CAL_EN(1U)
2891 
2892 #define S_SGL_CAL_EN    20
2893 #define V_SGL_CAL_EN(x) ((x) << S_SGL_CAL_EN)
2894 #define F_SGL_CAL_EN    V_SGL_CAL_EN(1U)
2895 
2896 #define S_IMP_UPD_MODE    19
2897 #define V_IMP_UPD_MODE(x) ((x) << S_IMP_UPD_MODE)
2898 #define F_IMP_UPD_MODE    V_IMP_UPD_MODE(1U)
2899 
2900 #define S_IMP_SEL    18
2901 #define V_IMP_SEL(x) ((x) << S_IMP_SEL)
2902 #define F_IMP_SEL    V_IMP_SEL(1U)
2903 
2904 #define S_IMP_MAN_PD    15
2905 #define M_IMP_MAN_PD    0x7
2906 #define V_IMP_MAN_PD(x) ((x) << S_IMP_MAN_PD)
2907 #define G_IMP_MAN_PD(x) (((x) >> S_IMP_MAN_PD) & M_IMP_MAN_PD)
2908 
2909 #define S_IMP_MAN_PU    12
2910 #define M_IMP_MAN_PU    0x7
2911 #define V_IMP_MAN_PU(x) ((x) << S_IMP_MAN_PU)
2912 #define G_IMP_MAN_PU(x) (((x) >> S_IMP_MAN_PU) & M_IMP_MAN_PU)
2913 
2914 #define S_IMP_CAL_PD    9
2915 #define M_IMP_CAL_PD    0x7
2916 #define V_IMP_CAL_PD(x) ((x) << S_IMP_CAL_PD)
2917 #define G_IMP_CAL_PD(x) (((x) >> S_IMP_CAL_PD) & M_IMP_CAL_PD)
2918 
2919 #define S_IMP_CAL_PU    6
2920 #define M_IMP_CAL_PU    0x7
2921 #define V_IMP_CAL_PU(x) ((x) << S_IMP_CAL_PU)
2922 #define G_IMP_CAL_PU(x) (((x) >> S_IMP_CAL_PU) & M_IMP_CAL_PU)
2923 
2924 #define S_IMP_SET_PD    3
2925 #define M_IMP_SET_PD    0x7
2926 #define V_IMP_SET_PD(x) ((x) << S_IMP_SET_PD)
2927 #define G_IMP_SET_PD(x) (((x) >> S_IMP_SET_PD) & M_IMP_SET_PD)
2928 
2929 #define S_IMP_SET_PU    0
2930 #define M_IMP_SET_PU    0x7
2931 #define V_IMP_SET_PU(x) ((x) << S_IMP_SET_PU)
2932 #define G_IMP_SET_PU(x) (((x) >> S_IMP_SET_PU) & M_IMP_SET_PU)
2933 
2934 #define A_MC7_ERR_ADDR 0x12c
2935 
2936 #define S_ERRADDRESS    3
2937 #define M_ERRADDRESS    0x1fffffff
2938 #define V_ERRADDRESS(x) ((x) << S_ERRADDRESS)
2939 #define G_ERRADDRESS(x) (((x) >> S_ERRADDRESS) & M_ERRADDRESS)
2940 
2941 #define S_ERRAGENT    1
2942 #define M_ERRAGENT    0x3
2943 #define V_ERRAGENT(x) ((x) << S_ERRAGENT)
2944 #define G_ERRAGENT(x) (((x) >> S_ERRAGENT) & M_ERRAGENT)
2945 
2946 #define S_ERROP    0
2947 #define V_ERROP(x) ((x) << S_ERROP)
2948 #define F_ERROP    V_ERROP(1U)
2949 
2950 #define A_MC7_ECC 0x130
2951 
2952 #define S_UECNT    10
2953 #define M_UECNT    0xff
2954 #define V_UECNT(x) ((x) << S_UECNT)
2955 #define G_UECNT(x) (((x) >> S_UECNT) & M_UECNT)
2956 
2957 #define S_CECNT    2
2958 #define M_CECNT    0xff
2959 #define V_CECNT(x) ((x) << S_CECNT)
2960 #define G_CECNT(x) (((x) >> S_CECNT) & M_CECNT)
2961 
2962 #define S_ECCCHKEN    1
2963 #define V_ECCCHKEN(x) ((x) << S_ECCCHKEN)
2964 #define F_ECCCHKEN    V_ECCCHKEN(1U)
2965 
2966 #define S_ECCGENEN    0
2967 #define V_ECCGENEN(x) ((x) << S_ECCGENEN)
2968 #define F_ECCGENEN    V_ECCGENEN(1U)
2969 
2970 #define A_MC7_CE_ADDR 0x134
2971 #define A_MC7_CE_DATA0 0x138
2972 #define A_MC7_CE_DATA1 0x13c
2973 #define A_MC7_CE_DATA2 0x140
2974 
2975 #define S_DATA    0
2976 #define M_DATA    0xff
2977 #define V_DATA(x) ((x) << S_DATA)
2978 #define G_DATA(x) (((x) >> S_DATA) & M_DATA)
2979 
2980 #define A_MC7_UE_ADDR 0x144
2981 #define A_MC7_UE_DATA0 0x148
2982 #define A_MC7_UE_DATA1 0x14c
2983 #define A_MC7_UE_DATA2 0x150
2984 #define A_MC7_BD_ADDR 0x154
2985 
2986 #define S_ADDR    3
2987 #define M_ADDR    0x1fffffff
2988 #define V_ADDR(x) ((x) << S_ADDR)
2989 #define G_ADDR(x) (((x) >> S_ADDR) & M_ADDR)
2990 
2991 #define A_MC7_BD_DATA0 0x158
2992 #define A_MC7_BD_DATA1 0x15c
2993 #define A_MC7_BD_DATA2 0x160
2994 #define A_MC7_BD_OP 0x164
2995 
2996 #define S_OP    0
2997 #define V_OP(x) ((x) << S_OP)
2998 #define F_OP    V_OP(1U)
2999 
3000 #define A_MC7_BIST_ADDR_BEG 0x168
3001 
3002 #define S_ADDRBEG    5
3003 #define M_ADDRBEG    0x7ffffff
3004 #define V_ADDRBEG(x) ((x) << S_ADDRBEG)
3005 #define G_ADDRBEG(x) (((x) >> S_ADDRBEG) & M_ADDRBEG)
3006 
3007 #define A_MC7_BIST_ADDR_END 0x16c
3008 
3009 #define S_ADDREND    5
3010 #define M_ADDREND    0x7ffffff
3011 #define V_ADDREND(x) ((x) << S_ADDREND)
3012 #define G_ADDREND(x) (((x) >> S_ADDREND) & M_ADDREND)
3013 
3014 #define A_MC7_BIST_DATA 0x170
3015 #define A_MC7_BIST_OP 0x174
3016 
3017 #define S_GAP    4
3018 #define M_GAP    0x1f
3019 #define V_GAP(x) ((x) << S_GAP)
3020 #define G_GAP(x) (((x) >> S_GAP) & M_GAP)
3021 
3022 #define S_CONT    3
3023 #define V_CONT(x) ((x) << S_CONT)
3024 #define F_CONT    V_CONT(1U)
3025 
3026 #define S_DATAPAT    1
3027 #define M_DATAPAT    0x3
3028 #define V_DATAPAT(x) ((x) << S_DATAPAT)
3029 #define G_DATAPAT(x) (((x) >> S_DATAPAT) & M_DATAPAT)
3030 
3031 #define A_MC7_INT_ENABLE 0x178
3032 
3033 #define S_AE    17
3034 #define V_AE(x) ((x) << S_AE)
3035 #define F_AE    V_AE(1U)
3036 
3037 #define S_PE    2
3038 #define M_PE    0x7fff
3039 #define V_PE(x) ((x) << S_PE)
3040 #define G_PE(x) (((x) >> S_PE) & M_PE)
3041 
3042 #define S_UE    1
3043 #define V_UE(x) ((x) << S_UE)
3044 #define F_UE    V_UE(1U)
3045 
3046 #define S_CE    0
3047 #define V_CE(x) ((x) << S_CE)
3048 #define F_CE    V_CE(1U)
3049 
3050 #define A_MC7_INT_CAUSE 0x17c
3051 
3052 /* registers for module MC7_PMTX */
3053 #define MC7_PMTX_BASE_ADDR 0x180
3054 
3055 /* registers for module MC7_CM */
3056 #define MC7_CM_BASE_ADDR 0x200
3057 
3058 /* registers for module CIM */
3059 #define CIM_BASE_ADDR 0x280
3060 
3061 #define A_CIM_BOOT_CFG 0x280
3062 
3063 #define S_BOOTADDR    2
3064 #define M_BOOTADDR    0x3fffffff
3065 #define V_BOOTADDR(x) ((x) << S_BOOTADDR)
3066 #define G_BOOTADDR(x) (((x) >> S_BOOTADDR) & M_BOOTADDR)
3067 
3068 #define S_BOOTSDRAM    1
3069 #define V_BOOTSDRAM(x) ((x) << S_BOOTSDRAM)
3070 #define F_BOOTSDRAM    V_BOOTSDRAM(1U)
3071 
3072 #define S_UPCRST    0
3073 #define V_UPCRST(x) ((x) << S_UPCRST)
3074 #define F_UPCRST    V_UPCRST(1U)
3075 
3076 #define A_CIM_FLASH_BASE_ADDR 0x284
3077 
3078 #define S_FLASHBASEADDR    2
3079 #define M_FLASHBASEADDR    0x3fffff
3080 #define V_FLASHBASEADDR(x) ((x) << S_FLASHBASEADDR)
3081 #define G_FLASHBASEADDR(x) (((x) >> S_FLASHBASEADDR) & M_FLASHBASEADDR)
3082 
3083 #define A_CIM_FLASH_ADDR_SIZE 0x288
3084 
3085 #define S_FLASHADDRSIZE    2
3086 #define M_FLASHADDRSIZE    0x3fffff
3087 #define V_FLASHADDRSIZE(x) ((x) << S_FLASHADDRSIZE)
3088 #define G_FLASHADDRSIZE(x) (((x) >> S_FLASHADDRSIZE) & M_FLASHADDRSIZE)
3089 
3090 #define A_CIM_SDRAM_BASE_ADDR 0x28c
3091 
3092 #define S_SDRAMBASEADDR    2
3093 #define M_SDRAMBASEADDR    0x3fffffff
3094 #define V_SDRAMBASEADDR(x) ((x) << S_SDRAMBASEADDR)
3095 #define G_SDRAMBASEADDR(x) (((x) >> S_SDRAMBASEADDR) & M_SDRAMBASEADDR)
3096 
3097 #define A_CIM_SDRAM_ADDR_SIZE 0x290
3098 
3099 #define S_SDRAMADDRSIZE    2
3100 #define M_SDRAMADDRSIZE    0x3fffffff
3101 #define V_SDRAMADDRSIZE(x) ((x) << S_SDRAMADDRSIZE)
3102 #define G_SDRAMADDRSIZE(x) (((x) >> S_SDRAMADDRSIZE) & M_SDRAMADDRSIZE)
3103 
3104 #define A_CIM_UP_SPARE_INT 0x294
3105 
3106 #define S_UPSPAREINT    0
3107 #define M_UPSPAREINT    0x7
3108 #define V_UPSPAREINT(x) ((x) << S_UPSPAREINT)
3109 #define G_UPSPAREINT(x) (((x) >> S_UPSPAREINT) & M_UPSPAREINT)
3110 
3111 #define A_CIM_HOST_INT_ENABLE 0x298
3112 
3113 #define S_DTAGPARERR    28
3114 #define V_DTAGPARERR(x) ((x) << S_DTAGPARERR)
3115 #define F_DTAGPARERR    V_DTAGPARERR(1U)
3116 
3117 #define S_ITAGPARERR    27
3118 #define V_ITAGPARERR(x) ((x) << S_ITAGPARERR)
3119 #define F_ITAGPARERR    V_ITAGPARERR(1U)
3120 
3121 #define S_IBQTPPARERR    26
3122 #define V_IBQTPPARERR(x) ((x) << S_IBQTPPARERR)
3123 #define F_IBQTPPARERR    V_IBQTPPARERR(1U)
3124 
3125 #define S_IBQULPPARERR    25
3126 #define V_IBQULPPARERR(x) ((x) << S_IBQULPPARERR)
3127 #define F_IBQULPPARERR    V_IBQULPPARERR(1U)
3128 
3129 #define S_IBQSGEHIPARERR    24
3130 #define V_IBQSGEHIPARERR(x) ((x) << S_IBQSGEHIPARERR)
3131 #define F_IBQSGEHIPARERR    V_IBQSGEHIPARERR(1U)
3132 
3133 #define S_IBQSGELOPARERR    23
3134 #define V_IBQSGELOPARERR(x) ((x) << S_IBQSGELOPARERR)
3135 #define F_IBQSGELOPARERR    V_IBQSGELOPARERR(1U)
3136 
3137 #define S_OBQULPLOPARERR    22
3138 #define V_OBQULPLOPARERR(x) ((x) << S_OBQULPLOPARERR)
3139 #define F_OBQULPLOPARERR    V_OBQULPLOPARERR(1U)
3140 
3141 #define S_OBQULPHIPARERR    21
3142 #define V_OBQULPHIPARERR(x) ((x) << S_OBQULPHIPARERR)
3143 #define F_OBQULPHIPARERR    V_OBQULPHIPARERR(1U)
3144 
3145 #define S_OBQSGEPARERR    20
3146 #define V_OBQSGEPARERR(x) ((x) << S_OBQSGEPARERR)
3147 #define F_OBQSGEPARERR    V_OBQSGEPARERR(1U)
3148 
3149 #define S_DCACHEPARERR    19
3150 #define V_DCACHEPARERR(x) ((x) << S_DCACHEPARERR)
3151 #define F_DCACHEPARERR    V_DCACHEPARERR(1U)
3152 
3153 #define S_ICACHEPARERR    18
3154 #define V_ICACHEPARERR(x) ((x) << S_ICACHEPARERR)
3155 #define F_ICACHEPARERR    V_ICACHEPARERR(1U)
3156 
3157 #define S_DRAMPARERR    17
3158 #define V_DRAMPARERR(x) ((x) << S_DRAMPARERR)
3159 #define F_DRAMPARERR    V_DRAMPARERR(1U)
3160 
3161 #define S_TIMER1INTEN    15
3162 #define V_TIMER1INTEN(x) ((x) << S_TIMER1INTEN)
3163 #define F_TIMER1INTEN    V_TIMER1INTEN(1U)
3164 
3165 #define S_TIMER0INTEN    14
3166 #define V_TIMER0INTEN(x) ((x) << S_TIMER0INTEN)
3167 #define F_TIMER0INTEN    V_TIMER0INTEN(1U)
3168 
3169 #define S_PREFDROPINTEN    13
3170 #define V_PREFDROPINTEN(x) ((x) << S_PREFDROPINTEN)
3171 #define F_PREFDROPINTEN    V_PREFDROPINTEN(1U)
3172 
3173 #define S_BLKWRPLINTEN    12
3174 #define V_BLKWRPLINTEN(x) ((x) << S_BLKWRPLINTEN)
3175 #define F_BLKWRPLINTEN    V_BLKWRPLINTEN(1U)
3176 
3177 #define S_BLKRDPLINTEN    11
3178 #define V_BLKRDPLINTEN(x) ((x) << S_BLKRDPLINTEN)
3179 #define F_BLKRDPLINTEN    V_BLKRDPLINTEN(1U)
3180 
3181 #define S_BLKWRCTLINTEN    10
3182 #define V_BLKWRCTLINTEN(x) ((x) << S_BLKWRCTLINTEN)
3183 #define F_BLKWRCTLINTEN    V_BLKWRCTLINTEN(1U)
3184 
3185 #define S_BLKRDCTLINTEN    9
3186 #define V_BLKRDCTLINTEN(x) ((x) << S_BLKRDCTLINTEN)
3187 #define F_BLKRDCTLINTEN    V_BLKRDCTLINTEN(1U)
3188 
3189 #define S_BLKWRFLASHINTEN    8
3190 #define V_BLKWRFLASHINTEN(x) ((x) << S_BLKWRFLASHINTEN)
3191 #define F_BLKWRFLASHINTEN    V_BLKWRFLASHINTEN(1U)
3192 
3193 #define S_BLKRDFLASHINTEN    7
3194 #define V_BLKRDFLASHINTEN(x) ((x) << S_BLKRDFLASHINTEN)
3195 #define F_BLKRDFLASHINTEN    V_BLKRDFLASHINTEN(1U)
3196 
3197 #define S_SGLWRFLASHINTEN    6
3198 #define V_SGLWRFLASHINTEN(x) ((x) << S_SGLWRFLASHINTEN)
3199 #define F_SGLWRFLASHINTEN    V_SGLWRFLASHINTEN(1U)
3200 
3201 #define S_WRBLKFLASHINTEN    5
3202 #define V_WRBLKFLASHINTEN(x) ((x) << S_WRBLKFLASHINTEN)
3203 #define F_WRBLKFLASHINTEN    V_WRBLKFLASHINTEN(1U)
3204 
3205 #define S_BLKWRBOOTINTEN    4
3206 #define V_BLKWRBOOTINTEN(x) ((x) << S_BLKWRBOOTINTEN)
3207 #define F_BLKWRBOOTINTEN    V_BLKWRBOOTINTEN(1U)
3208 
3209 #define S_BLKRDBOOTINTEN    3
3210 #define V_BLKRDBOOTINTEN(x) ((x) << S_BLKRDBOOTINTEN)
3211 #define F_BLKRDBOOTINTEN    V_BLKRDBOOTINTEN(1U)
3212 
3213 #define S_FLASHRANGEINTEN    2
3214 #define V_FLASHRANGEINTEN(x) ((x) << S_FLASHRANGEINTEN)
3215 #define F_FLASHRANGEINTEN    V_FLASHRANGEINTEN(1U)
3216 
3217 #define S_SDRAMRANGEINTEN    1
3218 #define V_SDRAMRANGEINTEN(x) ((x) << S_SDRAMRANGEINTEN)
3219 #define F_SDRAMRANGEINTEN    V_SDRAMRANGEINTEN(1U)
3220 
3221 #define S_RSVDSPACEINTEN    0
3222 #define V_RSVDSPACEINTEN(x) ((x) << S_RSVDSPACEINTEN)
3223 #define F_RSVDSPACEINTEN    V_RSVDSPACEINTEN(1U)
3224 
3225 #define A_CIM_HOST_INT_CAUSE 0x29c
3226 
3227 #define S_TIMER1INT    15
3228 #define V_TIMER1INT(x) ((x) << S_TIMER1INT)
3229 #define F_TIMER1INT    V_TIMER1INT(1U)
3230 
3231 #define S_TIMER0INT    14
3232 #define V_TIMER0INT(x) ((x) << S_TIMER0INT)
3233 #define F_TIMER0INT    V_TIMER0INT(1U)
3234 
3235 #define S_PREFDROPINT    13
3236 #define V_PREFDROPINT(x) ((x) << S_PREFDROPINT)
3237 #define F_PREFDROPINT    V_PREFDROPINT(1U)
3238 
3239 #define S_BLKWRPLINT    12
3240 #define V_BLKWRPLINT(x) ((x) << S_BLKWRPLINT)
3241 #define F_BLKWRPLINT    V_BLKWRPLINT(1U)
3242 
3243 #define S_BLKRDPLINT    11
3244 #define V_BLKRDPLINT(x) ((x) << S_BLKRDPLINT)
3245 #define F_BLKRDPLINT    V_BLKRDPLINT(1U)
3246 
3247 #define S_BLKWRCTLINT    10
3248 #define V_BLKWRCTLINT(x) ((x) << S_BLKWRCTLINT)
3249 #define F_BLKWRCTLINT    V_BLKWRCTLINT(1U)
3250 
3251 #define S_BLKRDCTLINT    9
3252 #define V_BLKRDCTLINT(x) ((x) << S_BLKRDCTLINT)
3253 #define F_BLKRDCTLINT    V_BLKRDCTLINT(1U)
3254 
3255 #define S_BLKWRFLASHINT    8
3256 #define V_BLKWRFLASHINT(x) ((x) << S_BLKWRFLASHINT)
3257 #define F_BLKWRFLASHINT    V_BLKWRFLASHINT(1U)
3258 
3259 #define S_BLKRDFLASHINT    7
3260 #define V_BLKRDFLASHINT(x) ((x) << S_BLKRDFLASHINT)
3261 #define F_BLKRDFLASHINT    V_BLKRDFLASHINT(1U)
3262 
3263 #define S_SGLWRFLASHINT    6
3264 #define V_SGLWRFLASHINT(x) ((x) << S_SGLWRFLASHINT)
3265 #define F_SGLWRFLASHINT    V_SGLWRFLASHINT(1U)
3266 
3267 #define S_WRBLKFLASHINT    5
3268 #define V_WRBLKFLASHINT(x) ((x) << S_WRBLKFLASHINT)
3269 #define F_WRBLKFLASHINT    V_WRBLKFLASHINT(1U)
3270 
3271 #define S_BLKWRBOOTINT    4
3272 #define V_BLKWRBOOTINT(x) ((x) << S_BLKWRBOOTINT)
3273 #define F_BLKWRBOOTINT    V_BLKWRBOOTINT(1U)
3274 
3275 #define S_BLKRDBOOTINT    3
3276 #define V_BLKRDBOOTINT(x) ((x) << S_BLKRDBOOTINT)
3277 #define F_BLKRDBOOTINT    V_BLKRDBOOTINT(1U)
3278 
3279 #define S_FLASHRANGEINT    2
3280 #define V_FLASHRANGEINT(x) ((x) << S_FLASHRANGEINT)
3281 #define F_FLASHRANGEINT    V_FLASHRANGEINT(1U)
3282 
3283 #define S_SDRAMRANGEINT    1
3284 #define V_SDRAMRANGEINT(x) ((x) << S_SDRAMRANGEINT)
3285 #define F_SDRAMRANGEINT    V_SDRAMRANGEINT(1U)
3286 
3287 #define S_RSVDSPACEINT    0
3288 #define V_RSVDSPACEINT(x) ((x) << S_RSVDSPACEINT)
3289 #define F_RSVDSPACEINT    V_RSVDSPACEINT(1U)
3290 
3291 #define A_CIM_UP_INT_ENABLE 0x2a0
3292 
3293 #define S_MSTPLINTEN    16
3294 #define V_MSTPLINTEN(x) ((x) << S_MSTPLINTEN)
3295 #define F_MSTPLINTEN    V_MSTPLINTEN(1U)
3296 
3297 #define A_CIM_UP_INT_CAUSE 0x2a4
3298 
3299 #define S_MSTPLINT    16
3300 #define V_MSTPLINT(x) ((x) << S_MSTPLINT)
3301 #define F_MSTPLINT    V_MSTPLINT(1U)
3302 
3303 #define A_CIM_IBQ_FULLA_THRSH 0x2a8
3304 
3305 #define S_IBQ0FULLTHRSH    0
3306 #define M_IBQ0FULLTHRSH    0x1ff
3307 #define V_IBQ0FULLTHRSH(x) ((x) << S_IBQ0FULLTHRSH)
3308 #define G_IBQ0FULLTHRSH(x) (((x) >> S_IBQ0FULLTHRSH) & M_IBQ0FULLTHRSH)
3309 
3310 #define S_IBQ1FULLTHRSH    16
3311 #define M_IBQ1FULLTHRSH    0x1ff
3312 #define V_IBQ1FULLTHRSH(x) ((x) << S_IBQ1FULLTHRSH)
3313 #define G_IBQ1FULLTHRSH(x) (((x) >> S_IBQ1FULLTHRSH) & M_IBQ1FULLTHRSH)
3314 
3315 #define A_CIM_IBQ_FULLB_THRSH 0x2ac
3316 
3317 #define S_IBQ2FULLTHRSH    0
3318 #define M_IBQ2FULLTHRSH    0x1ff
3319 #define V_IBQ2FULLTHRSH(x) ((x) << S_IBQ2FULLTHRSH)
3320 #define G_IBQ2FULLTHRSH(x) (((x) >> S_IBQ2FULLTHRSH) & M_IBQ2FULLTHRSH)
3321 
3322 #define S_IBQ3FULLTHRSH    16
3323 #define M_IBQ3FULLTHRSH    0x1ff
3324 #define V_IBQ3FULLTHRSH(x) ((x) << S_IBQ3FULLTHRSH)
3325 #define G_IBQ3FULLTHRSH(x) (((x) >> S_IBQ3FULLTHRSH) & M_IBQ3FULLTHRSH)
3326 
3327 #define A_CIM_HOST_ACC_CTRL 0x2b0
3328 
3329 #define S_HOSTBUSY    17
3330 #define V_HOSTBUSY(x) ((x) << S_HOSTBUSY)
3331 #define F_HOSTBUSY    V_HOSTBUSY(1U)
3332 
3333 #define S_HOSTWRITE    16
3334 #define V_HOSTWRITE(x) ((x) << S_HOSTWRITE)
3335 #define F_HOSTWRITE    V_HOSTWRITE(1U)
3336 
3337 #define S_HOSTADDR    0
3338 #define M_HOSTADDR    0xffff
3339 #define V_HOSTADDR(x) ((x) << S_HOSTADDR)
3340 #define G_HOSTADDR(x) (((x) >> S_HOSTADDR) & M_HOSTADDR)
3341 
3342 #define A_CIM_HOST_ACC_DATA 0x2b4
3343 #define A_CIM_IBQ_DBG_CFG 0x2c0
3344 
3345 #define S_IBQDBGADDR    16
3346 #define M_IBQDBGADDR    0x1ff
3347 #define V_IBQDBGADDR(x) ((x) << S_IBQDBGADDR)
3348 #define G_IBQDBGADDR(x) (((x) >> S_IBQDBGADDR) & M_IBQDBGADDR)
3349 
3350 #define S_IBQDBGQID    3
3351 #define M_IBQDBGQID    0x3
3352 #define V_IBQDBGQID(x) ((x) << S_IBQDBGQID)
3353 #define G_IBQDBGQID(x) (((x) >> S_IBQDBGQID) & M_IBQDBGQID)
3354 
3355 #define S_IBQDBGWR    2
3356 #define V_IBQDBGWR(x) ((x) << S_IBQDBGWR)
3357 #define F_IBQDBGWR    V_IBQDBGWR(1U)
3358 
3359 #define S_IBQDBGBUSY    1
3360 #define V_IBQDBGBUSY(x) ((x) << S_IBQDBGBUSY)
3361 #define F_IBQDBGBUSY    V_IBQDBGBUSY(1U)
3362 
3363 #define S_IBQDBGEN    0
3364 #define V_IBQDBGEN(x) ((x) << S_IBQDBGEN)
3365 #define F_IBQDBGEN    V_IBQDBGEN(1U)
3366 
3367 #define A_CIM_OBQ_DBG_CFG 0x2c4
3368 
3369 #define S_OBQDBGADDR    16
3370 #define M_OBQDBGADDR    0x1ff
3371 #define V_OBQDBGADDR(x) ((x) << S_OBQDBGADDR)
3372 #define G_OBQDBGADDR(x) (((x) >> S_OBQDBGADDR) & M_OBQDBGADDR)
3373 
3374 #define S_OBQDBGQID    3
3375 #define M_OBQDBGQID    0x3
3376 #define V_OBQDBGQID(x) ((x) << S_OBQDBGQID)
3377 #define G_OBQDBGQID(x) (((x) >> S_OBQDBGQID) & M_OBQDBGQID)
3378 
3379 #define S_OBQDBGWR    2
3380 #define V_OBQDBGWR(x) ((x) << S_OBQDBGWR)
3381 #define F_OBQDBGWR    V_OBQDBGWR(1U)
3382 
3383 #define S_OBQDBGBUSY    1
3384 #define V_OBQDBGBUSY(x) ((x) << S_OBQDBGBUSY)
3385 #define F_OBQDBGBUSY    V_OBQDBGBUSY(1U)
3386 
3387 #define S_OBQDBGEN    0
3388 #define V_OBQDBGEN(x) ((x) << S_OBQDBGEN)
3389 #define F_OBQDBGEN    V_OBQDBGEN(1U)
3390 
3391 #define A_CIM_IBQ_DBG_DATA 0x2c8
3392 #define A_CIM_OBQ_DBG_DATA 0x2cc
3393 #define A_CIM_CDEBUGDATA 0x2d0
3394 
3395 #define S_CDEBUGDATAH    16
3396 #define M_CDEBUGDATAH    0xffff
3397 #define V_CDEBUGDATAH(x) ((x) << S_CDEBUGDATAH)
3398 #define G_CDEBUGDATAH(x) (((x) >> S_CDEBUGDATAH) & M_CDEBUGDATAH)
3399 
3400 #define S_CDEBUGDATAL    0
3401 #define M_CDEBUGDATAL    0xffff
3402 #define V_CDEBUGDATAL(x) ((x) << S_CDEBUGDATAL)
3403 #define G_CDEBUGDATAL(x) (((x) >> S_CDEBUGDATAL) & M_CDEBUGDATAL)
3404 
3405 #define A_CIM_DEBUGCFG 0x2e0
3406 
3407 #define S_POLADBGRDPTR    23
3408 #define M_POLADBGRDPTR    0x1ff
3409 #define V_POLADBGRDPTR(x) ((x) << S_POLADBGRDPTR)
3410 #define G_POLADBGRDPTR(x) (((x) >> S_POLADBGRDPTR) & M_POLADBGRDPTR)
3411 
3412 #define S_PILADBGRDPTR    14
3413 #define M_PILADBGRDPTR    0x1ff
3414 #define V_PILADBGRDPTR(x) ((x) << S_PILADBGRDPTR)
3415 #define G_PILADBGRDPTR(x) (((x) >> S_PILADBGRDPTR) & M_PILADBGRDPTR)
3416 
3417 #define S_CIM_LADBGEN    12
3418 #define V_CIM_LADBGEN(x) ((x) << S_CIM_LADBGEN)
3419 #define F_CIM_LADBGEN    V_CIM_LADBGEN(1U)
3420 
3421 #define S_DEBUGSELHI    5
3422 #define M_DEBUGSELHI    0x1f
3423 #define V_DEBUGSELHI(x) ((x) << S_DEBUGSELHI)
3424 #define G_DEBUGSELHI(x) (((x) >> S_DEBUGSELHI) & M_DEBUGSELHI)
3425 
3426 #define S_DEBUGSELLO    0
3427 #define M_DEBUGSELLO    0x1f
3428 #define V_DEBUGSELLO(x) ((x) << S_DEBUGSELLO)
3429 #define G_DEBUGSELLO(x) (((x) >> S_DEBUGSELLO) & M_DEBUGSELLO)
3430 
3431 #define A_CIM_DEBUGSTS 0x2e4
3432 
3433 #define S_POLADBGWRPTR    16
3434 #define M_POLADBGWRPTR    0x1ff
3435 #define V_POLADBGWRPTR(x) ((x) << S_POLADBGWRPTR)
3436 #define G_POLADBGWRPTR(x) (((x) >> S_POLADBGWRPTR) & M_POLADBGWRPTR)
3437 
3438 #define S_PILADBGWRPTR    0
3439 #define M_PILADBGWRPTR    0x1ff
3440 #define V_PILADBGWRPTR(x) ((x) << S_PILADBGWRPTR)
3441 #define G_PILADBGWRPTR(x) (((x) >> S_PILADBGWRPTR) & M_PILADBGWRPTR)
3442 
3443 #define A_CIM_PO_LA_DEBUGDATA 0x2e8
3444 #define A_CIM_PI_LA_DEBUGDATA 0x2ec
3445 
3446 /* registers for module TP1 */
3447 #define TP1_BASE_ADDR 0x300
3448 
3449 #define A_TP_IN_CONFIG 0x300
3450 
3451 #define S_RXFBARBPRIO    25
3452 #define V_RXFBARBPRIO(x) ((x) << S_RXFBARBPRIO)
3453 #define F_RXFBARBPRIO    V_RXFBARBPRIO(1U)
3454 
3455 #define S_TXFBARBPRIO    24
3456 #define V_TXFBARBPRIO(x) ((x) << S_TXFBARBPRIO)
3457 #define F_TXFBARBPRIO    V_TXFBARBPRIO(1U)
3458 
3459 #define S_DBMAXOPCNT    16
3460 #define M_DBMAXOPCNT    0xff
3461 #define V_DBMAXOPCNT(x) ((x) << S_DBMAXOPCNT)
3462 #define G_DBMAXOPCNT(x) (((x) >> S_DBMAXOPCNT) & M_DBMAXOPCNT)
3463 
3464 #define S_IPV6ENABLE    15
3465 #define V_IPV6ENABLE(x) ((x) << S_IPV6ENABLE)
3466 #define F_IPV6ENABLE    V_IPV6ENABLE(1U)
3467 
3468 #define S_NICMODE    14
3469 #define V_NICMODE(x) ((x) << S_NICMODE)
3470 #define F_NICMODE    V_NICMODE(1U)
3471 
3472 #define S_ECHECKSUMCHECKTCP    13
3473 #define V_ECHECKSUMCHECKTCP(x) ((x) << S_ECHECKSUMCHECKTCP)
3474 #define F_ECHECKSUMCHECKTCP    V_ECHECKSUMCHECKTCP(1U)
3475 
3476 #define S_ECHECKSUMCHECKIP    12
3477 #define V_ECHECKSUMCHECKIP(x) ((x) << S_ECHECKSUMCHECKIP)
3478 #define F_ECHECKSUMCHECKIP    V_ECHECKSUMCHECKIP(1U)
3479 
3480 #define S_ECPL    10
3481 #define V_ECPL(x) ((x) << S_ECPL)
3482 #define F_ECPL    V_ECPL(1U)
3483 
3484 #define S_EETHERNET    8
3485 #define V_EETHERNET(x) ((x) << S_EETHERNET)
3486 #define F_EETHERNET    V_EETHERNET(1U)
3487 
3488 #define S_ETUNNEL    7
3489 #define V_ETUNNEL(x) ((x) << S_ETUNNEL)
3490 #define F_ETUNNEL    V_ETUNNEL(1U)
3491 
3492 #define S_CCHECKSUMCHECKTCP    6
3493 #define V_CCHECKSUMCHECKTCP(x) ((x) << S_CCHECKSUMCHECKTCP)
3494 #define F_CCHECKSUMCHECKTCP    V_CCHECKSUMCHECKTCP(1U)
3495 
3496 #define S_CCHECKSUMCHECKIP    5
3497 #define V_CCHECKSUMCHECKIP(x) ((x) << S_CCHECKSUMCHECKIP)
3498 #define F_CCHECKSUMCHECKIP    V_CCHECKSUMCHECKIP(1U)
3499 
3500 #define S_CCPL    3
3501 #define V_CCPL(x) ((x) << S_CCPL)
3502 #define F_CCPL    V_CCPL(1U)
3503 
3504 #define S_CETHERNET    1
3505 #define V_CETHERNET(x) ((x) << S_CETHERNET)
3506 #define F_CETHERNET    V_CETHERNET(1U)
3507 
3508 #define S_CTUNNEL    0
3509 #define V_CTUNNEL(x) ((x) << S_CTUNNEL)
3510 #define F_CTUNNEL    V_CTUNNEL(1U)
3511 
3512 #define A_TP_OUT_CONFIG 0x304
3513 
3514 #define S_IPIDSPLITMODE    16
3515 #define V_IPIDSPLITMODE(x) ((x) << S_IPIDSPLITMODE)
3516 #define F_IPIDSPLITMODE    V_IPIDSPLITMODE(1U)
3517 
3518 #define S_VLANEXTRACTIONENABLE2NDPORT    13
3519 #define V_VLANEXTRACTIONENABLE2NDPORT(x) ((x) << S_VLANEXTRACTIONENABLE2NDPORT)
3520 #define F_VLANEXTRACTIONENABLE2NDPORT    V_VLANEXTRACTIONENABLE2NDPORT(1U)
3521 
3522 #define S_VLANEXTRACTIONENABLE    12
3523 #define V_VLANEXTRACTIONENABLE(x) ((x) << S_VLANEXTRACTIONENABLE)
3524 #define F_VLANEXTRACTIONENABLE    V_VLANEXTRACTIONENABLE(1U)
3525 
3526 #define S_ECHECKSUMGENERATETCP    11
3527 #define V_ECHECKSUMGENERATETCP(x) ((x) << S_ECHECKSUMGENERATETCP)
3528 #define F_ECHECKSUMGENERATETCP    V_ECHECKSUMGENERATETCP(1U)
3529 
3530 #define S_ECHECKSUMGENERATEIP    10
3531 #define V_ECHECKSUMGENERATEIP(x) ((x) << S_ECHECKSUMGENERATEIP)
3532 #define F_ECHECKSUMGENERATEIP    V_ECHECKSUMGENERATEIP(1U)
3533 
3534 #define S_OUT_ECPL    8
3535 #define V_OUT_ECPL(x) ((x) << S_OUT_ECPL)
3536 #define F_OUT_ECPL    V_OUT_ECPL(1U)
3537 
3538 #define S_OUT_EETHERNET    6
3539 #define V_OUT_EETHERNET(x) ((x) << S_OUT_EETHERNET)
3540 #define F_OUT_EETHERNET    V_OUT_EETHERNET(1U)
3541 
3542 #define S_CCHECKSUMGENERATETCP    5
3543 #define V_CCHECKSUMGENERATETCP(x) ((x) << S_CCHECKSUMGENERATETCP)
3544 #define F_CCHECKSUMGENERATETCP    V_CCHECKSUMGENERATETCP(1U)
3545 
3546 #define S_CCHECKSUMGENERATEIP    4
3547 #define V_CCHECKSUMGENERATEIP(x) ((x) << S_CCHECKSUMGENERATEIP)
3548 #define F_CCHECKSUMGENERATEIP    V_CCHECKSUMGENERATEIP(1U)
3549 
3550 #define S_OUT_CCPL    2
3551 #define V_OUT_CCPL(x) ((x) << S_OUT_CCPL)
3552 #define F_OUT_CCPL    V_OUT_CCPL(1U)
3553 
3554 #define S_OUT_CETHERNET    0
3555 #define V_OUT_CETHERNET(x) ((x) << S_OUT_CETHERNET)
3556 #define F_OUT_CETHERNET    V_OUT_CETHERNET(1U)
3557 
3558 #define A_TP_GLOBAL_CONFIG 0x308
3559 
3560 #define S_SYNCOOKIEPARAMS    26
3561 #define M_SYNCOOKIEPARAMS    0x3f
3562 #define V_SYNCOOKIEPARAMS(x) ((x) << S_SYNCOOKIEPARAMS)
3563 #define G_SYNCOOKIEPARAMS(x) (((x) >> S_SYNCOOKIEPARAMS) & M_SYNCOOKIEPARAMS)
3564 
3565 #define S_RXFLOWCONTROLDISABLE    25
3566 #define V_RXFLOWCONTROLDISABLE(x) ((x) << S_RXFLOWCONTROLDISABLE)
3567 #define F_RXFLOWCONTROLDISABLE    V_RXFLOWCONTROLDISABLE(1U)
3568 
3569 #define S_TXPACINGENABLE    24
3570 #define V_TXPACINGENABLE(x) ((x) << S_TXPACINGENABLE)
3571 #define F_TXPACINGENABLE    V_TXPACINGENABLE(1U)
3572 
3573 #define S_ATTACKFILTERENABLE    23
3574 #define V_ATTACKFILTERENABLE(x) ((x) << S_ATTACKFILTERENABLE)
3575 #define F_ATTACKFILTERENABLE    V_ATTACKFILTERENABLE(1U)
3576 
3577 #define S_SYNCOOKIENOOPTIONS    22
3578 #define V_SYNCOOKIENOOPTIONS(x) ((x) << S_SYNCOOKIENOOPTIONS)
3579 #define F_SYNCOOKIENOOPTIONS    V_SYNCOOKIENOOPTIONS(1U)
3580 
3581 #define S_PROTECTEDMODE    21
3582 #define V_PROTECTEDMODE(x) ((x) << S_PROTECTEDMODE)
3583 #define F_PROTECTEDMODE    V_PROTECTEDMODE(1U)
3584 
3585 #define S_PINGDROP    20
3586 #define V_PINGDROP(x) ((x) << S_PINGDROP)
3587 #define F_PINGDROP    V_PINGDROP(1U)
3588 
3589 #define S_FRAGMENTDROP    19
3590 #define V_FRAGMENTDROP(x) ((x) << S_FRAGMENTDROP)
3591 #define F_FRAGMENTDROP    V_FRAGMENTDROP(1U)
3592 
3593 #define S_FIVETUPLELOOKUP    17
3594 #define M_FIVETUPLELOOKUP    0x3
3595 #define V_FIVETUPLELOOKUP(x) ((x) << S_FIVETUPLELOOKUP)
3596 #define G_FIVETUPLELOOKUP(x) (((x) >> S_FIVETUPLELOOKUP) & M_FIVETUPLELOOKUP)
3597 
3598 #define S_PATHMTU    15
3599 #define V_PATHMTU(x) ((x) << S_PATHMTU)
3600 #define F_PATHMTU    V_PATHMTU(1U)
3601 
3602 #define S_IPIDENTSPLIT    14
3603 #define V_IPIDENTSPLIT(x) ((x) << S_IPIDENTSPLIT)
3604 #define F_IPIDENTSPLIT    V_IPIDENTSPLIT(1U)
3605 
3606 #define S_IPCHECKSUMOFFLOAD    13
3607 #define V_IPCHECKSUMOFFLOAD(x) ((x) << S_IPCHECKSUMOFFLOAD)
3608 #define F_IPCHECKSUMOFFLOAD    V_IPCHECKSUMOFFLOAD(1U)
3609 
3610 #define S_UDPCHECKSUMOFFLOAD    12
3611 #define V_UDPCHECKSUMOFFLOAD(x) ((x) << S_UDPCHECKSUMOFFLOAD)
3612 #define F_UDPCHECKSUMOFFLOAD    V_UDPCHECKSUMOFFLOAD(1U)
3613 
3614 #define S_TCPCHECKSUMOFFLOAD    11
3615 #define V_TCPCHECKSUMOFFLOAD(x) ((x) << S_TCPCHECKSUMOFFLOAD)
3616 #define F_TCPCHECKSUMOFFLOAD    V_TCPCHECKSUMOFFLOAD(1U)
3617 
3618 #define S_QOSMAPPING    10
3619 #define V_QOSMAPPING(x) ((x) << S_QOSMAPPING)
3620 #define F_QOSMAPPING    V_QOSMAPPING(1U)
3621 
3622 #define S_TCAMSERVERUSE    8
3623 #define M_TCAMSERVERUSE    0x3
3624 #define V_TCAMSERVERUSE(x) ((x) << S_TCAMSERVERUSE)
3625 #define G_TCAMSERVERUSE(x) (((x) >> S_TCAMSERVERUSE) & M_TCAMSERVERUSE)
3626 
3627 #define S_IPTTL    0
3628 #define M_IPTTL    0xff
3629 #define V_IPTTL(x) ((x) << S_IPTTL)
3630 #define G_IPTTL(x) (((x) >> S_IPTTL) & M_IPTTL)
3631 
3632 #define A_TP_GLOBAL_RX_CREDIT 0x30c
3633 #define A_TP_CMM_SIZE 0x310
3634 
3635 #define S_CMMEMMGRSIZE    0
3636 #define M_CMMEMMGRSIZE    0xfffffff
3637 #define V_CMMEMMGRSIZE(x) ((x) << S_CMMEMMGRSIZE)
3638 #define G_CMMEMMGRSIZE(x) (((x) >> S_CMMEMMGRSIZE) & M_CMMEMMGRSIZE)
3639 
3640 #define A_TP_CMM_MM_BASE 0x314
3641 
3642 #define S_CMMEMMGRBASE    0
3643 #define M_CMMEMMGRBASE    0xfffffff
3644 #define V_CMMEMMGRBASE(x) ((x) << S_CMMEMMGRBASE)
3645 #define G_CMMEMMGRBASE(x) (((x) >> S_CMMEMMGRBASE) & M_CMMEMMGRBASE)
3646 
3647 #define A_TP_CMM_TIMER_BASE 0x318
3648 
3649 #define S_CMTIMERMAXNUM    28
3650 #define M_CMTIMERMAXNUM    0x3
3651 #define V_CMTIMERMAXNUM(x) ((x) << S_CMTIMERMAXNUM)
3652 #define G_CMTIMERMAXNUM(x) (((x) >> S_CMTIMERMAXNUM) & M_CMTIMERMAXNUM)
3653 
3654 #define S_CMTIMERBASE    0
3655 #define M_CMTIMERBASE    0xfffffff
3656 #define V_CMTIMERBASE(x) ((x) << S_CMTIMERBASE)
3657 #define G_CMTIMERBASE(x) (((x) >> S_CMTIMERBASE) & M_CMTIMERBASE)
3658 
3659 #define A_TP_PMM_SIZE 0x31c
3660 
3661 #define S_PMSIZE    0
3662 #define M_PMSIZE    0xfffffff
3663 #define V_PMSIZE(x) ((x) << S_PMSIZE)
3664 #define G_PMSIZE(x) (((x) >> S_PMSIZE) & M_PMSIZE)
3665 
3666 #define A_TP_PMM_TX_BASE 0x320
3667 #define A_TP_PMM_DEFRAG_BASE 0x324
3668 #define A_TP_PMM_RX_BASE 0x328
3669 #define A_TP_PMM_RX_PAGE_SIZE 0x32c
3670 #define A_TP_PMM_RX_MAX_PAGE 0x330
3671 
3672 #define S_PMRXMAXPAGE    0
3673 #define M_PMRXMAXPAGE    0x1fffff
3674 #define V_PMRXMAXPAGE(x) ((x) << S_PMRXMAXPAGE)
3675 #define G_PMRXMAXPAGE(x) (((x) >> S_PMRXMAXPAGE) & M_PMRXMAXPAGE)
3676 
3677 #define A_TP_PMM_TX_PAGE_SIZE 0x334
3678 #define A_TP_PMM_TX_MAX_PAGE 0x338
3679 
3680 #define S_PMTXMAXPAGE    0
3681 #define M_PMTXMAXPAGE    0x1fffff
3682 #define V_PMTXMAXPAGE(x) ((x) << S_PMTXMAXPAGE)
3683 #define G_PMTXMAXPAGE(x) (((x) >> S_PMTXMAXPAGE) & M_PMTXMAXPAGE)
3684 
3685 #define A_TP_TCP_OPTIONS 0x340
3686 
3687 #define S_MTUDEFAULT    16
3688 #define M_MTUDEFAULT    0xffff
3689 #define V_MTUDEFAULT(x) ((x) << S_MTUDEFAULT)
3690 #define G_MTUDEFAULT(x) (((x) >> S_MTUDEFAULT) & M_MTUDEFAULT)
3691 
3692 #define S_MTUENABLE    10
3693 #define V_MTUENABLE(x) ((x) << S_MTUENABLE)
3694 #define F_MTUENABLE    V_MTUENABLE(1U)
3695 
3696 #define S_SACKTX    9
3697 #define V_SACKTX(x) ((x) << S_SACKTX)
3698 #define F_SACKTX    V_SACKTX(1U)
3699 
3700 #define S_SACKRX    8
3701 #define V_SACKRX(x) ((x) << S_SACKRX)
3702 #define F_SACKRX    V_SACKRX(1U)
3703 
3704 #define S_SACKMODE    4
3705 #define M_SACKMODE    0x3
3706 #define V_SACKMODE(x) ((x) << S_SACKMODE)
3707 #define G_SACKMODE(x) (((x) >> S_SACKMODE) & M_SACKMODE)
3708 
3709 #define S_WINDOWSCALEMODE    2
3710 #define M_WINDOWSCALEMODE    0x3
3711 #define V_WINDOWSCALEMODE(x) ((x) << S_WINDOWSCALEMODE)
3712 #define G_WINDOWSCALEMODE(x) (((x) >> S_WINDOWSCALEMODE) & M_WINDOWSCALEMODE)
3713 
3714 #define S_TIMESTAMPSMODE    0
3715 #define M_TIMESTAMPSMODE    0x3
3716 #define V_TIMESTAMPSMODE(x) ((x) << S_TIMESTAMPSMODE)
3717 #define G_TIMESTAMPSMODE(x) (((x) >> S_TIMESTAMPSMODE) & M_TIMESTAMPSMODE)
3718 
3719 #define A_TP_DACK_CONFIG 0x344
3720 
3721 #define S_AUTOSTATE3    30
3722 #define M_AUTOSTATE3    0x3
3723 #define V_AUTOSTATE3(x) ((x) << S_AUTOSTATE3)
3724 #define G_AUTOSTATE3(x) (((x) >> S_AUTOSTATE3) & M_AUTOSTATE3)
3725 
3726 #define S_AUTOSTATE2    28
3727 #define M_AUTOSTATE2    0x3
3728 #define V_AUTOSTATE2(x) ((x) << S_AUTOSTATE2)
3729 #define G_AUTOSTATE2(x) (((x) >> S_AUTOSTATE2) & M_AUTOSTATE2)
3730 
3731 #define S_AUTOSTATE1    26
3732 #define M_AUTOSTATE1    0x3
3733 #define V_AUTOSTATE1(x) ((x) << S_AUTOSTATE1)
3734 #define G_AUTOSTATE1(x) (((x) >> S_AUTOSTATE1) & M_AUTOSTATE1)
3735 
3736 #define S_BYTETHRESHOLD    5
3737 #define M_BYTETHRESHOLD    0xfffff
3738 #define V_BYTETHRESHOLD(x) ((x) << S_BYTETHRESHOLD)
3739 #define G_BYTETHRESHOLD(x) (((x) >> S_BYTETHRESHOLD) & M_BYTETHRESHOLD)
3740 
3741 #define S_MSSTHRESHOLD    3
3742 #define M_MSSTHRESHOLD    0x3
3743 #define V_MSSTHRESHOLD(x) ((x) << S_MSSTHRESHOLD)
3744 #define G_MSSTHRESHOLD(x) (((x) >> S_MSSTHRESHOLD) & M_MSSTHRESHOLD)
3745 
3746 #define S_AUTOCAREFUL    2
3747 #define V_AUTOCAREFUL(x) ((x) << S_AUTOCAREFUL)
3748 #define F_AUTOCAREFUL    V_AUTOCAREFUL(1U)
3749 
3750 #define S_AUTOENABLE    1
3751 #define V_AUTOENABLE(x) ((x) << S_AUTOENABLE)
3752 #define F_AUTOENABLE    V_AUTOENABLE(1U)
3753 
3754 #define S_DACK_MODE    0
3755 #define V_DACK_MODE(x) ((x) << S_DACK_MODE)
3756 #define F_DACK_MODE    V_DACK_MODE(1U)
3757 
3758 #define A_TP_PC_CONFIG 0x348
3759 
3760 #define S_CMCACHEDISABLE    31
3761 #define V_CMCACHEDISABLE(x) ((x) << S_CMCACHEDISABLE)
3762 #define F_CMCACHEDISABLE    V_CMCACHEDISABLE(1U)
3763 
3764 #define S_ENABLEOCSPIFULL    30
3765 #define V_ENABLEOCSPIFULL(x) ((x) << S_ENABLEOCSPIFULL)
3766 #define F_ENABLEOCSPIFULL    V_ENABLEOCSPIFULL(1U)
3767 
3768 #define S_ENABLEFLMERRORDDP    29
3769 #define V_ENABLEFLMERRORDDP(x) ((x) << S_ENABLEFLMERRORDDP)
3770 #define F_ENABLEFLMERRORDDP    V_ENABLEFLMERRORDDP(1U)
3771 
3772 #define S_LOCKTID    28
3773 #define V_LOCKTID(x) ((x) << S_LOCKTID)
3774 #define F_LOCKTID    V_LOCKTID(1U)
3775 
3776 #define S_FIXRCVWND    27
3777 #define V_FIXRCVWND(x) ((x) << S_FIXRCVWND)
3778 #define F_FIXRCVWND    V_FIXRCVWND(1U)
3779 
3780 #define S_TXTOSQUEUEMAPMODE    26
3781 #define V_TXTOSQUEUEMAPMODE(x) ((x) << S_TXTOSQUEUEMAPMODE)
3782 #define F_TXTOSQUEUEMAPMODE    V_TXTOSQUEUEMAPMODE(1U)
3783 
3784 #define S_RDDPCONGEN    25
3785 #define V_RDDPCONGEN(x) ((x) << S_RDDPCONGEN)
3786 #define F_RDDPCONGEN    V_RDDPCONGEN(1U)
3787 
3788 #define S_ENABLEONFLYPDU    24
3789 #define V_ENABLEONFLYPDU(x) ((x) << S_ENABLEONFLYPDU)
3790 #define F_ENABLEONFLYPDU    V_ENABLEONFLYPDU(1U)
3791 
3792 #define S_ENABLEEPCMDAFULL    23
3793 #define V_ENABLEEPCMDAFULL(x) ((x) << S_ENABLEEPCMDAFULL)
3794 #define F_ENABLEEPCMDAFULL    V_ENABLEEPCMDAFULL(1U)
3795 
3796 #define S_MODULATEUNIONMODE    22
3797 #define V_MODULATEUNIONMODE(x) ((x) << S_MODULATEUNIONMODE)
3798 #define F_MODULATEUNIONMODE    V_MODULATEUNIONMODE(1U)
3799 
3800 #define S_TXDATAACKRATEENABLE    21
3801 #define V_TXDATAACKRATEENABLE(x) ((x) << S_TXDATAACKRATEENABLE)
3802 #define F_TXDATAACKRATEENABLE    V_TXDATAACKRATEENABLE(1U)
3803 
3804 #define S_TXDEFERENABLE    20
3805 #define V_TXDEFERENABLE(x) ((x) << S_TXDEFERENABLE)
3806 #define F_TXDEFERENABLE    V_TXDEFERENABLE(1U)
3807 
3808 #define S_RXCONGESTIONMODE    19
3809 #define V_RXCONGESTIONMODE(x) ((x) << S_RXCONGESTIONMODE)
3810 #define F_RXCONGESTIONMODE    V_RXCONGESTIONMODE(1U)
3811 
3812 #define S_HEARBEATONCEDACK    18
3813 #define V_HEARBEATONCEDACK(x) ((x) << S_HEARBEATONCEDACK)
3814 #define F_HEARBEATONCEDACK    V_HEARBEATONCEDACK(1U)
3815 
3816 #define S_HEARBEATONCEHEAP    17
3817 #define V_HEARBEATONCEHEAP(x) ((x) << S_HEARBEATONCEHEAP)
3818 #define F_HEARBEATONCEHEAP    V_HEARBEATONCEHEAP(1U)
3819 
3820 #define S_HEARBEATDACK    16
3821 #define V_HEARBEATDACK(x) ((x) << S_HEARBEATDACK)
3822 #define F_HEARBEATDACK    V_HEARBEATDACK(1U)
3823 
3824 #define S_TXCONGESTIONMODE    15
3825 #define V_TXCONGESTIONMODE(x) ((x) << S_TXCONGESTIONMODE)
3826 #define F_TXCONGESTIONMODE    V_TXCONGESTIONMODE(1U)
3827 
3828 #define S_ACCEPTLATESTRCVADV    14
3829 #define V_ACCEPTLATESTRCVADV(x) ((x) << S_ACCEPTLATESTRCVADV)
3830 #define F_ACCEPTLATESTRCVADV    V_ACCEPTLATESTRCVADV(1U)
3831 
3832 #define S_DISABLESYNDATA    13
3833 #define V_DISABLESYNDATA(x) ((x) << S_DISABLESYNDATA)
3834 #define F_DISABLESYNDATA    V_DISABLESYNDATA(1U)
3835 
3836 #define S_DISABLEWINDOWPSH    12
3837 #define V_DISABLEWINDOWPSH(x) ((x) << S_DISABLEWINDOWPSH)
3838 #define F_DISABLEWINDOWPSH    V_DISABLEWINDOWPSH(1U)
3839 
3840 #define S_DISABLEFINOLDDATA    11
3841 #define V_DISABLEFINOLDDATA(x) ((x) << S_DISABLEFINOLDDATA)
3842 #define F_DISABLEFINOLDDATA    V_DISABLEFINOLDDATA(1U)
3843 
3844 #define S_ENABLEFLMERROR    10
3845 #define V_ENABLEFLMERROR(x) ((x) << S_ENABLEFLMERROR)
3846 #define F_ENABLEFLMERROR    V_ENABLEFLMERROR(1U)
3847 
3848 #define S_DISABLENEXTMTU    9
3849 #define V_DISABLENEXTMTU(x) ((x) << S_DISABLENEXTMTU)
3850 #define F_DISABLENEXTMTU    V_DISABLENEXTMTU(1U)
3851 
3852 #define S_FILTERPEERFIN    8
3853 #define V_FILTERPEERFIN(x) ((x) << S_FILTERPEERFIN)
3854 #define F_FILTERPEERFIN    V_FILTERPEERFIN(1U)
3855 
3856 #define S_ENABLEFEEDBACKSEND    7
3857 #define V_ENABLEFEEDBACKSEND(x) ((x) << S_ENABLEFEEDBACKSEND)
3858 #define F_ENABLEFEEDBACKSEND    V_ENABLEFEEDBACKSEND(1U)
3859 
3860 #define S_ENABLERDMAERROR    6
3861 #define V_ENABLERDMAERROR(x) ((x) << S_ENABLERDMAERROR)
3862 #define F_ENABLERDMAERROR    V_ENABLERDMAERROR(1U)
3863 
3864 #define S_ENABLEDDPFLOWCONTROL    5
3865 #define V_ENABLEDDPFLOWCONTROL(x) ((x) << S_ENABLEDDPFLOWCONTROL)
3866 #define F_ENABLEDDPFLOWCONTROL    V_ENABLEDDPFLOWCONTROL(1U)
3867 
3868 #define S_DISABLEHELDFIN    4
3869 #define V_DISABLEHELDFIN(x) ((x) << S_DISABLEHELDFIN)
3870 #define F_DISABLEHELDFIN    V_DISABLEHELDFIN(1U)
3871 
3872 #define S_TABLELATENCYDELTA    0
3873 #define M_TABLELATENCYDELTA    0xf
3874 #define V_TABLELATENCYDELTA(x) ((x) << S_TABLELATENCYDELTA)
3875 #define G_TABLELATENCYDELTA(x) (((x) >> S_TABLELATENCYDELTA) & M_TABLELATENCYDELTA)
3876 
3877 #define A_TP_PC_CONFIG2 0x34c
3878 
3879 #define S_DISBLEDAPARBIT0    15
3880 #define V_DISBLEDAPARBIT0(x) ((x) << S_DISBLEDAPARBIT0)
3881 #define F_DISBLEDAPARBIT0    V_DISBLEDAPARBIT0(1U)
3882 
3883 #define S_ENABLEARPMISS    13
3884 #define V_ENABLEARPMISS(x) ((x) << S_ENABLEARPMISS)
3885 #define F_ENABLEARPMISS    V_ENABLEARPMISS(1U)
3886 
3887 #define S_ENABLENONOFDTNLSYN    12
3888 #define V_ENABLENONOFDTNLSYN(x) ((x) << S_ENABLENONOFDTNLSYN)
3889 #define F_ENABLENONOFDTNLSYN    V_ENABLENONOFDTNLSYN(1U)
3890 
3891 #define S_ENABLEIPV6RSS    11
3892 #define V_ENABLEIPV6RSS(x) ((x) << S_ENABLEIPV6RSS)
3893 #define F_ENABLEIPV6RSS    V_ENABLEIPV6RSS(1U)
3894 
3895 #define S_ENABLEDROPRQEMPTYPKT    10
3896 #define V_ENABLEDROPRQEMPTYPKT(x) ((x) << S_ENABLEDROPRQEMPTYPKT)
3897 #define F_ENABLEDROPRQEMPTYPKT    V_ENABLEDROPRQEMPTYPKT(1U)
3898 
3899 #define S_ENABLETXPORTFROMDA2    9
3900 #define V_ENABLETXPORTFROMDA2(x) ((x) << S_ENABLETXPORTFROMDA2)
3901 #define F_ENABLETXPORTFROMDA2    V_ENABLETXPORTFROMDA2(1U)
3902 
3903 #define S_ENABLERXPKTTMSTPRSS    8
3904 #define V_ENABLERXPKTTMSTPRSS(x) ((x) << S_ENABLERXPKTTMSTPRSS)
3905 #define F_ENABLERXPKTTMSTPRSS    V_ENABLERXPKTTMSTPRSS(1U)
3906 
3907 #define S_ENABLESNDUNAINRXDATA    7
3908 #define V_ENABLESNDUNAINRXDATA(x) ((x) << S_ENABLESNDUNAINRXDATA)
3909 #define F_ENABLESNDUNAINRXDATA    V_ENABLESNDUNAINRXDATA(1U)
3910 
3911 #define S_ENABLERXPORTFROMADDR    6
3912 #define V_ENABLERXPORTFROMADDR(x) ((x) << S_ENABLERXPORTFROMADDR)
3913 #define F_ENABLERXPORTFROMADDR    V_ENABLERXPORTFROMADDR(1U)
3914 
3915 #define S_ENABLETXPORTFROMDA    5
3916 #define V_ENABLETXPORTFROMDA(x) ((x) << S_ENABLETXPORTFROMDA)
3917 #define F_ENABLETXPORTFROMDA    V_ENABLETXPORTFROMDA(1U)
3918 
3919 #define S_ENABLECHDRAFULL    4
3920 #define V_ENABLECHDRAFULL(x) ((x) << S_ENABLECHDRAFULL)
3921 #define F_ENABLECHDRAFULL    V_ENABLECHDRAFULL(1U)
3922 
3923 #define S_ENABLENONOFDSCBBIT    3
3924 #define V_ENABLENONOFDSCBBIT(x) ((x) << S_ENABLENONOFDSCBBIT)
3925 #define F_ENABLENONOFDSCBBIT    V_ENABLENONOFDSCBBIT(1U)
3926 
3927 #define S_ENABLENONOFDTIDRSS    2
3928 #define V_ENABLENONOFDTIDRSS(x) ((x) << S_ENABLENONOFDTIDRSS)
3929 #define F_ENABLENONOFDTIDRSS    V_ENABLENONOFDTIDRSS(1U)
3930 
3931 #define S_ENABLENONOFDTCBRSS    1
3932 #define V_ENABLENONOFDTCBRSS(x) ((x) << S_ENABLENONOFDTCBRSS)
3933 #define F_ENABLENONOFDTCBRSS    V_ENABLENONOFDTCBRSS(1U)
3934 
3935 #define S_ENABLEOLDRXFORWARD    0
3936 #define V_ENABLEOLDRXFORWARD(x) ((x) << S_ENABLEOLDRXFORWARD)
3937 #define F_ENABLEOLDRXFORWARD    V_ENABLEOLDRXFORWARD(1U)
3938 
3939 #define S_CHDRAFULL    4
3940 #define V_CHDRAFULL(x) ((x) << S_CHDRAFULL)
3941 #define F_CHDRAFULL    V_CHDRAFULL(1U)
3942 
3943 #define A_TP_TCP_BACKOFF_REG0 0x350
3944 
3945 #define S_TIMERBACKOFFINDEX3    24
3946 #define M_TIMERBACKOFFINDEX3    0xff
3947 #define V_TIMERBACKOFFINDEX3(x) ((x) << S_TIMERBACKOFFINDEX3)
3948 #define G_TIMERBACKOFFINDEX3(x) (((x) >> S_TIMERBACKOFFINDEX3) & M_TIMERBACKOFFINDEX3)
3949 
3950 #define S_TIMERBACKOFFINDEX2    16
3951 #define M_TIMERBACKOFFINDEX2    0xff
3952 #define V_TIMERBACKOFFINDEX2(x) ((x) << S_TIMERBACKOFFINDEX2)
3953 #define G_TIMERBACKOFFINDEX2(x) (((x) >> S_TIMERBACKOFFINDEX2) & M_TIMERBACKOFFINDEX2)
3954 
3955 #define S_TIMERBACKOFFINDEX1    8
3956 #define M_TIMERBACKOFFINDEX1    0xff
3957 #define V_TIMERBACKOFFINDEX1(x) ((x) << S_TIMERBACKOFFINDEX1)
3958 #define G_TIMERBACKOFFINDEX1(x) (((x) >> S_TIMERBACKOFFINDEX1) & M_TIMERBACKOFFINDEX1)
3959 
3960 #define S_TIMERBACKOFFINDEX0    0
3961 #define M_TIMERBACKOFFINDEX0    0xff
3962 #define V_TIMERBACKOFFINDEX0(x) ((x) << S_TIMERBACKOFFINDEX0)
3963 #define G_TIMERBACKOFFINDEX0(x) (((x) >> S_TIMERBACKOFFINDEX0) & M_TIMERBACKOFFINDEX0)
3964 
3965 #define A_TP_TCP_BACKOFF_REG1 0x354
3966 
3967 #define S_TIMERBACKOFFINDEX7    24
3968 #define M_TIMERBACKOFFINDEX7    0xff
3969 #define V_TIMERBACKOFFINDEX7(x) ((x) << S_TIMERBACKOFFINDEX7)
3970 #define G_TIMERBACKOFFINDEX7(x) (((x) >> S_TIMERBACKOFFINDEX7) & M_TIMERBACKOFFINDEX7)
3971 
3972 #define S_TIMERBACKOFFINDEX6    16
3973 #define M_TIMERBACKOFFINDEX6    0xff
3974 #define V_TIMERBACKOFFINDEX6(x) ((x) << S_TIMERBACKOFFINDEX6)
3975 #define G_TIMERBACKOFFINDEX6(x) (((x) >> S_TIMERBACKOFFINDEX6) & M_TIMERBACKOFFINDEX6)
3976 
3977 #define S_TIMERBACKOFFINDEX5    8
3978 #define M_TIMERBACKOFFINDEX5    0xff
3979 #define V_TIMERBACKOFFINDEX5(x) ((x) << S_TIMERBACKOFFINDEX5)
3980 #define G_TIMERBACKOFFINDEX5(x) (((x) >> S_TIMERBACKOFFINDEX5) & M_TIMERBACKOFFINDEX5)
3981 
3982 #define S_TIMERBACKOFFINDEX4    0
3983 #define M_TIMERBACKOFFINDEX4    0xff
3984 #define V_TIMERBACKOFFINDEX4(x) ((x) << S_TIMERBACKOFFINDEX4)
3985 #define G_TIMERBACKOFFINDEX4(x) (((x) >> S_TIMERBACKOFFINDEX4) & M_TIMERBACKOFFINDEX4)
3986 
3987 #define A_TP_TCP_BACKOFF_REG2 0x358
3988 
3989 #define S_TIMERBACKOFFINDEX11    24
3990 #define M_TIMERBACKOFFINDEX11    0xff
3991 #define V_TIMERBACKOFFINDEX11(x) ((x) << S_TIMERBACKOFFINDEX11)
3992 #define G_TIMERBACKOFFINDEX11(x) (((x) >> S_TIMERBACKOFFINDEX11) & M_TIMERBACKOFFINDEX11)
3993 
3994 #define S_TIMERBACKOFFINDEX10    16
3995 #define M_TIMERBACKOFFINDEX10    0xff
3996 #define V_TIMERBACKOFFINDEX10(x) ((x) << S_TIMERBACKOFFINDEX10)
3997 #define G_TIMERBACKOFFINDEX10(x) (((x) >> S_TIMERBACKOFFINDEX10) & M_TIMERBACKOFFINDEX10)
3998 
3999 #define S_TIMERBACKOFFINDEX9    8
4000 #define M_TIMERBACKOFFINDEX9    0xff
4001 #define V_TIMERBACKOFFINDEX9(x) ((x) << S_TIMERBACKOFFINDEX9)
4002 #define G_TIMERBACKOFFINDEX9(x) (((x) >> S_TIMERBACKOFFINDEX9) & M_TIMERBACKOFFINDEX9)
4003 
4004 #define S_TIMERBACKOFFINDEX8    0
4005 #define M_TIMERBACKOFFINDEX8    0xff
4006 #define V_TIMERBACKOFFINDEX8(x) ((x) << S_TIMERBACKOFFINDEX8)
4007 #define G_TIMERBACKOFFINDEX8(x) (((x) >> S_TIMERBACKOFFINDEX8) & M_TIMERBACKOFFINDEX8)
4008 
4009 #define A_TP_TCP_BACKOFF_REG3 0x35c
4010 
4011 #define S_TIMERBACKOFFINDEX15    24
4012 #define M_TIMERBACKOFFINDEX15    0xff
4013 #define V_TIMERBACKOFFINDEX15(x) ((x) << S_TIMERBACKOFFINDEX15)
4014 #define G_TIMERBACKOFFINDEX15(x) (((x) >> S_TIMERBACKOFFINDEX15) & M_TIMERBACKOFFINDEX15)
4015 
4016 #define S_TIMERBACKOFFINDEX14    16
4017 #define M_TIMERBACKOFFINDEX14    0xff
4018 #define V_TIMERBACKOFFINDEX14(x) ((x) << S_TIMERBACKOFFINDEX14)
4019 #define G_TIMERBACKOFFINDEX14(x) (((x) >> S_TIMERBACKOFFINDEX14) & M_TIMERBACKOFFINDEX14)
4020 
4021 #define S_TIMERBACKOFFINDEX13    8
4022 #define M_TIMERBACKOFFINDEX13    0xff
4023 #define V_TIMERBACKOFFINDEX13(x) ((x) << S_TIMERBACKOFFINDEX13)
4024 #define G_TIMERBACKOFFINDEX13(x) (((x) >> S_TIMERBACKOFFINDEX13) & M_TIMERBACKOFFINDEX13)
4025 
4026 #define S_TIMERBACKOFFINDEX12    0
4027 #define M_TIMERBACKOFFINDEX12    0xff
4028 #define V_TIMERBACKOFFINDEX12(x) ((x) << S_TIMERBACKOFFINDEX12)
4029 #define G_TIMERBACKOFFINDEX12(x) (((x) >> S_TIMERBACKOFFINDEX12) & M_TIMERBACKOFFINDEX12)
4030 
4031 #define A_TP_PARA_REG0 0x360
4032 
4033 #define S_INITCWND    24
4034 #define M_INITCWND    0x7
4035 #define V_INITCWND(x) ((x) << S_INITCWND)
4036 #define G_INITCWND(x) (((x) >> S_INITCWND) & M_INITCWND)
4037 
4038 #define S_DUPACKTHRESH    20
4039 #define M_DUPACKTHRESH    0xf
4040 #define V_DUPACKTHRESH(x) ((x) << S_DUPACKTHRESH)
4041 #define G_DUPACKTHRESH(x) (((x) >> S_DUPACKTHRESH) & M_DUPACKTHRESH)
4042 
4043 #define A_TP_PARA_REG1 0x364
4044 
4045 #define S_INITRWND    16
4046 #define M_INITRWND    0xffff
4047 #define V_INITRWND(x) ((x) << S_INITRWND)
4048 #define G_INITRWND(x) (((x) >> S_INITRWND) & M_INITRWND)
4049 
4050 #define S_INITIALSSTHRESH    0
4051 #define M_INITIALSSTHRESH    0xffff
4052 #define V_INITIALSSTHRESH(x) ((x) << S_INITIALSSTHRESH)
4053 #define G_INITIALSSTHRESH(x) (((x) >> S_INITIALSSTHRESH) & M_INITIALSSTHRESH)
4054 
4055 #define A_TP_PARA_REG2 0x368
4056 
4057 #define S_MAXRXDATA    16
4058 #define M_MAXRXDATA    0xffff
4059 #define V_MAXRXDATA(x) ((x) << S_MAXRXDATA)
4060 #define G_MAXRXDATA(x) (((x) >> S_MAXRXDATA) & M_MAXRXDATA)
4061 
4062 #define S_RXCOALESCESIZE    0
4063 #define M_RXCOALESCESIZE    0xffff
4064 #define V_RXCOALESCESIZE(x) ((x) << S_RXCOALESCESIZE)
4065 #define G_RXCOALESCESIZE(x) (((x) >> S_RXCOALESCESIZE) & M_RXCOALESCESIZE)
4066 
4067 #define A_TP_PARA_REG3 0x36c
4068 
4069 #define S_TUNNELCNGDROP1    21
4070 #define V_TUNNELCNGDROP1(x) ((x) << S_TUNNELCNGDROP1)
4071 #define F_TUNNELCNGDROP1    V_TUNNELCNGDROP1(1U)
4072 
4073 #define S_TUNNELCNGDROP0    20
4074 #define V_TUNNELCNGDROP0(x) ((x) << S_TUNNELCNGDROP0)
4075 #define F_TUNNELCNGDROP0    V_TUNNELCNGDROP0(1U)
4076 
4077 #define S_TXDATAACKIDX    16
4078 #define M_TXDATAACKIDX    0xf
4079 #define V_TXDATAACKIDX(x) ((x) << S_TXDATAACKIDX)
4080 #define G_TXDATAACKIDX(x) (((x) >> S_TXDATAACKIDX) & M_TXDATAACKIDX)
4081 
4082 #define S_RXFRAGENABLE    12
4083 #define M_RXFRAGENABLE    0x7
4084 #define V_RXFRAGENABLE(x) ((x) << S_RXFRAGENABLE)
4085 #define G_RXFRAGENABLE(x) (((x) >> S_RXFRAGENABLE) & M_RXFRAGENABLE)
4086 
4087 #define S_TXPACEFIXEDSTRICT    11
4088 #define V_TXPACEFIXEDSTRICT(x) ((x) << S_TXPACEFIXEDSTRICT)
4089 #define F_TXPACEFIXEDSTRICT    V_TXPACEFIXEDSTRICT(1U)
4090 
4091 #define S_TXPACEAUTOSTRICT    10
4092 #define V_TXPACEAUTOSTRICT(x) ((x) << S_TXPACEAUTOSTRICT)
4093 #define F_TXPACEAUTOSTRICT    V_TXPACEAUTOSTRICT(1U)
4094 
4095 #define S_TXPACEFIXED    9
4096 #define V_TXPACEFIXED(x) ((x) << S_TXPACEFIXED)
4097 #define F_TXPACEFIXED    V_TXPACEFIXED(1U)
4098 
4099 #define S_TXPACEAUTO    8
4100 #define V_TXPACEAUTO(x) ((x) << S_TXPACEAUTO)
4101 #define F_TXPACEAUTO    V_TXPACEAUTO(1U)
4102 
4103 #define S_RXURGTUNNEL    6
4104 #define V_RXURGTUNNEL(x) ((x) << S_RXURGTUNNEL)
4105 #define F_RXURGTUNNEL    V_RXURGTUNNEL(1U)
4106 
4107 #define S_RXURGMODE    5
4108 #define V_RXURGMODE(x) ((x) << S_RXURGMODE)
4109 #define F_RXURGMODE    V_RXURGMODE(1U)
4110 
4111 #define S_TXURGMODE    4
4112 #define V_TXURGMODE(x) ((x) << S_TXURGMODE)
4113 #define F_TXURGMODE    V_TXURGMODE(1U)
4114 
4115 #define S_CNGCTRLMODE    2
4116 #define M_CNGCTRLMODE    0x3
4117 #define V_CNGCTRLMODE(x) ((x) << S_CNGCTRLMODE)
4118 #define G_CNGCTRLMODE(x) (((x) >> S_CNGCTRLMODE) & M_CNGCTRLMODE)
4119 
4120 #define S_RXCOALESCEENABLE    1
4121 #define V_RXCOALESCEENABLE(x) ((x) << S_RXCOALESCEENABLE)
4122 #define F_RXCOALESCEENABLE    V_RXCOALESCEENABLE(1U)
4123 
4124 #define S_RXCOALESCEPSHEN    0
4125 #define V_RXCOALESCEPSHEN(x) ((x) << S_RXCOALESCEPSHEN)
4126 #define F_RXCOALESCEPSHEN    V_RXCOALESCEPSHEN(1U)
4127 
4128 #define A_TP_PARA_REG4 0x370
4129 
4130 #define S_HIGHSPEEDCFG    24
4131 #define M_HIGHSPEEDCFG    0xff
4132 #define V_HIGHSPEEDCFG(x) ((x) << S_HIGHSPEEDCFG)
4133 #define G_HIGHSPEEDCFG(x) (((x) >> S_HIGHSPEEDCFG) & M_HIGHSPEEDCFG)
4134 
4135 #define S_NEWRENOCFG    16
4136 #define M_NEWRENOCFG    0xff
4137 #define V_NEWRENOCFG(x) ((x) << S_NEWRENOCFG)
4138 #define G_NEWRENOCFG(x) (((x) >> S_NEWRENOCFG) & M_NEWRENOCFG)
4139 
4140 #define S_TAHOECFG    8
4141 #define M_TAHOECFG    0xff
4142 #define V_TAHOECFG(x) ((x) << S_TAHOECFG)
4143 #define G_TAHOECFG(x) (((x) >> S_TAHOECFG) & M_TAHOECFG)
4144 
4145 #define S_RENOCFG    0
4146 #define M_RENOCFG    0xff
4147 #define V_RENOCFG(x) ((x) << S_RENOCFG)
4148 #define G_RENOCFG(x) (((x) >> S_RENOCFG) & M_RENOCFG)
4149 
4150 #define A_TP_PARA_REG5 0x374
4151 
4152 #define S_INDICATESIZE    16
4153 #define M_INDICATESIZE    0xffff
4154 #define V_INDICATESIZE(x) ((x) << S_INDICATESIZE)
4155 #define G_INDICATESIZE(x) (((x) >> S_INDICATESIZE) & M_INDICATESIZE)
4156 
4157 #define S_SCHDENABLE    8
4158 #define V_SCHDENABLE(x) ((x) << S_SCHDENABLE)
4159 #define F_SCHDENABLE    V_SCHDENABLE(1U)
4160 
4161 #define S_RXDDPOFFINIT    3
4162 #define V_RXDDPOFFINIT(x) ((x) << S_RXDDPOFFINIT)
4163 #define F_RXDDPOFFINIT    V_RXDDPOFFINIT(1U)
4164 
4165 #define S_ONFLYDDPENABLE    2
4166 #define V_ONFLYDDPENABLE(x) ((x) << S_ONFLYDDPENABLE)
4167 #define F_ONFLYDDPENABLE    V_ONFLYDDPENABLE(1U)
4168 
4169 #define S_DACKTIMERSPIN    1
4170 #define V_DACKTIMERSPIN(x) ((x) << S_DACKTIMERSPIN)
4171 #define F_DACKTIMERSPIN    V_DACKTIMERSPIN(1U)
4172 
4173 #define S_PUSHTIMERENABLE    0
4174 #define V_PUSHTIMERENABLE(x) ((x) << S_PUSHTIMERENABLE)
4175 #define F_PUSHTIMERENABLE    V_PUSHTIMERENABLE(1U)
4176 
4177 #define A_TP_PARA_REG6 0x378
4178 
4179 #define S_TXPDUSIZEADJ    16
4180 #define M_TXPDUSIZEADJ    0xff
4181 #define V_TXPDUSIZEADJ(x) ((x) << S_TXPDUSIZEADJ)
4182 #define G_TXPDUSIZEADJ(x) (((x) >> S_TXPDUSIZEADJ) & M_TXPDUSIZEADJ)
4183 
4184 #define S_ENABLEDEFERACK    12
4185 #define V_ENABLEDEFERACK(x) ((x) << S_ENABLEDEFERACK)
4186 #define F_ENABLEDEFERACK    V_ENABLEDEFERACK(1U)
4187 
4188 #define S_ENABLEESND    11
4189 #define V_ENABLEESND(x) ((x) << S_ENABLEESND)
4190 #define F_ENABLEESND    V_ENABLEESND(1U)
4191 
4192 #define S_ENABLECSND    10
4193 #define V_ENABLECSND(x) ((x) << S_ENABLECSND)
4194 #define F_ENABLECSND    V_ENABLECSND(1U)
4195 
4196 #define S_ENABLEPDUE    9
4197 #define V_ENABLEPDUE(x) ((x) << S_ENABLEPDUE)
4198 #define F_ENABLEPDUE    V_ENABLEPDUE(1U)
4199 
4200 #define S_ENABLEPDUC    8
4201 #define V_ENABLEPDUC(x) ((x) << S_ENABLEPDUC)
4202 #define F_ENABLEPDUC    V_ENABLEPDUC(1U)
4203 
4204 #define S_ENABLEBUFI    7
4205 #define V_ENABLEBUFI(x) ((x) << S_ENABLEBUFI)
4206 #define F_ENABLEBUFI    V_ENABLEBUFI(1U)
4207 
4208 #define S_ENABLEBUFE    6
4209 #define V_ENABLEBUFE(x) ((x) << S_ENABLEBUFE)
4210 #define F_ENABLEBUFE    V_ENABLEBUFE(1U)
4211 
4212 #define S_ENABLEDEFER    5
4213 #define V_ENABLEDEFER(x) ((x) << S_ENABLEDEFER)
4214 #define F_ENABLEDEFER    V_ENABLEDEFER(1U)
4215 
4216 #define S_ENABLECLEARRXMTOOS    4
4217 #define V_ENABLECLEARRXMTOOS(x) ((x) << S_ENABLECLEARRXMTOOS)
4218 #define F_ENABLECLEARRXMTOOS    V_ENABLECLEARRXMTOOS(1U)
4219 
4220 #define S_DISABLEPDUCNG    3
4221 #define V_DISABLEPDUCNG(x) ((x) << S_DISABLEPDUCNG)
4222 #define F_DISABLEPDUCNG    V_DISABLEPDUCNG(1U)
4223 
4224 #define S_DISABLEPDUTIMEOUT    2
4225 #define V_DISABLEPDUTIMEOUT(x) ((x) << S_DISABLEPDUTIMEOUT)
4226 #define F_DISABLEPDUTIMEOUT    V_DISABLEPDUTIMEOUT(1U)
4227 
4228 #define S_DISABLEPDURXMT    1
4229 #define V_DISABLEPDURXMT(x) ((x) << S_DISABLEPDURXMT)
4230 #define F_DISABLEPDURXMT    V_DISABLEPDURXMT(1U)
4231 
4232 #define S_DISABLEPDUXMT    0
4233 #define V_DISABLEPDUXMT(x) ((x) << S_DISABLEPDUXMT)
4234 #define F_DISABLEPDUXMT    V_DISABLEPDUXMT(1U)
4235 
4236 #define S_ENABLEEPDU    14
4237 #define V_ENABLEEPDU(x) ((x) << S_ENABLEEPDU)
4238 #define F_ENABLEEPDU    V_ENABLEEPDU(1U)
4239 
4240 #define S_T3A_ENABLEESND    13
4241 #define V_T3A_ENABLEESND(x) ((x) << S_T3A_ENABLEESND)
4242 #define F_T3A_ENABLEESND    V_T3A_ENABLEESND(1U)
4243 
4244 #define S_T3A_ENABLECSND    12
4245 #define V_T3A_ENABLECSND(x) ((x) << S_T3A_ENABLECSND)
4246 #define F_T3A_ENABLECSND    V_T3A_ENABLECSND(1U)
4247 
4248 #define S_T3A_ENABLEDEFERACK    9
4249 #define V_T3A_ENABLEDEFERACK(x) ((x) << S_T3A_ENABLEDEFERACK)
4250 #define F_T3A_ENABLEDEFERACK    V_T3A_ENABLEDEFERACK(1U)
4251 
4252 #define S_ENABLEPDUI    7
4253 #define V_ENABLEPDUI(x) ((x) << S_ENABLEPDUI)
4254 #define F_ENABLEPDUI    V_ENABLEPDUI(1U)
4255 
4256 #define S_T3A_ENABLEPDUE    6
4257 #define V_T3A_ENABLEPDUE(x) ((x) << S_T3A_ENABLEPDUE)
4258 #define F_T3A_ENABLEPDUE    V_T3A_ENABLEPDUE(1U)
4259 
4260 #define A_TP_PARA_REG7 0x37c
4261 
4262 #define S_PMMAXXFERLEN1    16
4263 #define M_PMMAXXFERLEN1    0xffff
4264 #define V_PMMAXXFERLEN1(x) ((x) << S_PMMAXXFERLEN1)
4265 #define G_PMMAXXFERLEN1(x) (((x) >> S_PMMAXXFERLEN1) & M_PMMAXXFERLEN1)
4266 
4267 #define S_PMMAXXFERLEN0    0
4268 #define M_PMMAXXFERLEN0    0xffff
4269 #define V_PMMAXXFERLEN0(x) ((x) << S_PMMAXXFERLEN0)
4270 #define G_PMMAXXFERLEN0(x) (((x) >> S_PMMAXXFERLEN0) & M_PMMAXXFERLEN0)
4271 
4272 #define A_TP_TIMER_RESOLUTION 0x390
4273 
4274 #define S_TIMERRESOLUTION    16
4275 #define M_TIMERRESOLUTION    0xff
4276 #define V_TIMERRESOLUTION(x) ((x) << S_TIMERRESOLUTION)
4277 #define G_TIMERRESOLUTION(x) (((x) >> S_TIMERRESOLUTION) & M_TIMERRESOLUTION)
4278 
4279 #define S_TIMESTAMPRESOLUTION    8
4280 #define M_TIMESTAMPRESOLUTION    0xff
4281 #define V_TIMESTAMPRESOLUTION(x) ((x) << S_TIMESTAMPRESOLUTION)
4282 #define G_TIMESTAMPRESOLUTION(x) (((x) >> S_TIMESTAMPRESOLUTION) & M_TIMESTAMPRESOLUTION)
4283 
4284 #define S_DELAYEDACKRESOLUTION    0
4285 #define M_DELAYEDACKRESOLUTION    0xff
4286 #define V_DELAYEDACKRESOLUTION(x) ((x) << S_DELAYEDACKRESOLUTION)
4287 #define G_DELAYEDACKRESOLUTION(x) (((x) >> S_DELAYEDACKRESOLUTION) & M_DELAYEDACKRESOLUTION)
4288 
4289 #define A_TP_MSL 0x394
4290 
4291 #define S_MSL    0
4292 #define M_MSL    0x3fffffff
4293 #define V_MSL(x) ((x) << S_MSL)
4294 #define G_MSL(x) (((x) >> S_MSL) & M_MSL)
4295 
4296 #define A_TP_RXT_MIN 0x398
4297 
4298 #define S_RXTMIN    0
4299 #define M_RXTMIN    0x3fffffff
4300 #define V_RXTMIN(x) ((x) << S_RXTMIN)
4301 #define G_RXTMIN(x) (((x) >> S_RXTMIN) & M_RXTMIN)
4302 
4303 #define A_TP_RXT_MAX 0x39c
4304 
4305 #define S_RXTMAX    0
4306 #define M_RXTMAX    0x3fffffff
4307 #define V_RXTMAX(x) ((x) << S_RXTMAX)
4308 #define G_RXTMAX(x) (((x) >> S_RXTMAX) & M_RXTMAX)
4309 
4310 #define A_TP_PERS_MIN 0x3a0
4311 
4312 #define S_PERSMIN    0
4313 #define M_PERSMIN    0x3fffffff
4314 #define V_PERSMIN(x) ((x) << S_PERSMIN)
4315 #define G_PERSMIN(x) (((x) >> S_PERSMIN) & M_PERSMIN)
4316 
4317 #define A_TP_PERS_MAX 0x3a4
4318 
4319 #define S_PERSMAX    0
4320 #define M_PERSMAX    0x3fffffff
4321 #define V_PERSMAX(x) ((x) << S_PERSMAX)
4322 #define G_PERSMAX(x) (((x) >> S_PERSMAX) & M_PERSMAX)
4323 
4324 #define A_TP_KEEP_IDLE 0x3a8
4325 
4326 #define S_KEEPALIVEIDLE    0
4327 #define M_KEEPALIVEIDLE    0x3fffffff
4328 #define V_KEEPALIVEIDLE(x) ((x) << S_KEEPALIVEIDLE)
4329 #define G_KEEPALIVEIDLE(x) (((x) >> S_KEEPALIVEIDLE) & M_KEEPALIVEIDLE)
4330 
4331 #define A_TP_KEEP_INTVL 0x3ac
4332 
4333 #define S_KEEPALIVEINTVL    0
4334 #define M_KEEPALIVEINTVL    0x3fffffff
4335 #define V_KEEPALIVEINTVL(x) ((x) << S_KEEPALIVEINTVL)
4336 #define G_KEEPALIVEINTVL(x) (((x) >> S_KEEPALIVEINTVL) & M_KEEPALIVEINTVL)
4337 
4338 #define A_TP_INIT_SRTT 0x3b0
4339 
4340 #define S_INITSRTT    0
4341 #define M_INITSRTT    0xffff
4342 #define V_INITSRTT(x) ((x) << S_INITSRTT)
4343 #define G_INITSRTT(x) (((x) >> S_INITSRTT) & M_INITSRTT)
4344 
4345 #define A_TP_DACK_TIMER 0x3b4
4346 
4347 #define S_DACKTIME    0
4348 #define M_DACKTIME    0xfff
4349 #define V_DACKTIME(x) ((x) << S_DACKTIME)
4350 #define G_DACKTIME(x) (((x) >> S_DACKTIME) & M_DACKTIME)
4351 
4352 #define A_TP_FINWAIT2_TIMER 0x3b8
4353 
4354 #define S_FINWAIT2TIME    0
4355 #define M_FINWAIT2TIME    0x3fffffff
4356 #define V_FINWAIT2TIME(x) ((x) << S_FINWAIT2TIME)
4357 #define G_FINWAIT2TIME(x) (((x) >> S_FINWAIT2TIME) & M_FINWAIT2TIME)
4358 
4359 #define A_TP_FAST_FINWAIT2_TIMER 0x3bc
4360 
4361 #define S_FASTFINWAIT2TIME    0
4362 #define M_FASTFINWAIT2TIME    0x3fffffff
4363 #define V_FASTFINWAIT2TIME(x) ((x) << S_FASTFINWAIT2TIME)
4364 #define G_FASTFINWAIT2TIME(x) (((x) >> S_FASTFINWAIT2TIME) & M_FASTFINWAIT2TIME)
4365 
4366 #define A_TP_SHIFT_CNT 0x3c0
4367 
4368 #define S_SYNSHIFTMAX    24
4369 #define M_SYNSHIFTMAX    0xff
4370 #define V_SYNSHIFTMAX(x) ((x) << S_SYNSHIFTMAX)
4371 #define G_SYNSHIFTMAX(x) (((x) >> S_SYNSHIFTMAX) & M_SYNSHIFTMAX)
4372 
4373 #define S_RXTSHIFTMAXR1    20
4374 #define M_RXTSHIFTMAXR1    0xf
4375 #define V_RXTSHIFTMAXR1(x) ((x) << S_RXTSHIFTMAXR1)
4376 #define G_RXTSHIFTMAXR1(x) (((x) >> S_RXTSHIFTMAXR1) & M_RXTSHIFTMAXR1)
4377 
4378 #define S_RXTSHIFTMAXR2    16
4379 #define M_RXTSHIFTMAXR2    0xf
4380 #define V_RXTSHIFTMAXR2(x) ((x) << S_RXTSHIFTMAXR2)
4381 #define G_RXTSHIFTMAXR2(x) (((x) >> S_RXTSHIFTMAXR2) & M_RXTSHIFTMAXR2)
4382 
4383 #define S_PERSHIFTBACKOFFMAX    12
4384 #define M_PERSHIFTBACKOFFMAX    0xf
4385 #define V_PERSHIFTBACKOFFMAX(x) ((x) << S_PERSHIFTBACKOFFMAX)
4386 #define G_PERSHIFTBACKOFFMAX(x) (((x) >> S_PERSHIFTBACKOFFMAX) & M_PERSHIFTBACKOFFMAX)
4387 
4388 #define S_PERSHIFTMAX    8
4389 #define M_PERSHIFTMAX    0xf
4390 #define V_PERSHIFTMAX(x) ((x) << S_PERSHIFTMAX)
4391 #define G_PERSHIFTMAX(x) (((x) >> S_PERSHIFTMAX) & M_PERSHIFTMAX)
4392 
4393 #define S_KEEPALIVEMAX    0
4394 #define M_KEEPALIVEMAX    0xff
4395 #define V_KEEPALIVEMAX(x) ((x) << S_KEEPALIVEMAX)
4396 #define G_KEEPALIVEMAX(x) (((x) >> S_KEEPALIVEMAX) & M_KEEPALIVEMAX)
4397 
4398 #define A_TP_TIME_HI 0x3c8
4399 #define A_TP_TIME_LO 0x3cc
4400 #define A_TP_MTU_PORT_TABLE 0x3d0
4401 
4402 #define S_PORT1MTUVALUE    16
4403 #define M_PORT1MTUVALUE    0xffff
4404 #define V_PORT1MTUVALUE(x) ((x) << S_PORT1MTUVALUE)
4405 #define G_PORT1MTUVALUE(x) (((x) >> S_PORT1MTUVALUE) & M_PORT1MTUVALUE)
4406 
4407 #define S_PORT0MTUVALUE    0
4408 #define M_PORT0MTUVALUE    0xffff
4409 #define V_PORT0MTUVALUE(x) ((x) << S_PORT0MTUVALUE)
4410 #define G_PORT0MTUVALUE(x) (((x) >> S_PORT0MTUVALUE) & M_PORT0MTUVALUE)
4411 
4412 #define A_TP_ULP_TABLE 0x3d4
4413 
4414 #define S_ULPTYPE7FIELD    28
4415 #define M_ULPTYPE7FIELD    0xf
4416 #define V_ULPTYPE7FIELD(x) ((x) << S_ULPTYPE7FIELD)
4417 #define G_ULPTYPE7FIELD(x) (((x) >> S_ULPTYPE7FIELD) & M_ULPTYPE7FIELD)
4418 
4419 #define S_ULPTYPE6FIELD    24
4420 #define M_ULPTYPE6FIELD    0xf
4421 #define V_ULPTYPE6FIELD(x) ((x) << S_ULPTYPE6FIELD)
4422 #define G_ULPTYPE6FIELD(x) (((x) >> S_ULPTYPE6FIELD) & M_ULPTYPE6FIELD)
4423 
4424 #define S_ULPTYPE5FIELD    20
4425 #define M_ULPTYPE5FIELD    0xf
4426 #define V_ULPTYPE5FIELD(x) ((x) << S_ULPTYPE5FIELD)
4427 #define G_ULPTYPE5FIELD(x) (((x) >> S_ULPTYPE5FIELD) & M_ULPTYPE5FIELD)
4428 
4429 #define S_ULPTYPE4FIELD    16
4430 #define M_ULPTYPE4FIELD    0xf
4431 #define V_ULPTYPE4FIELD(x) ((x) << S_ULPTYPE4FIELD)
4432 #define G_ULPTYPE4FIELD(x) (((x) >> S_ULPTYPE4FIELD) & M_ULPTYPE4FIELD)
4433 
4434 #define S_ULPTYPE3FIELD    12
4435 #define M_ULPTYPE3FIELD    0xf
4436 #define V_ULPTYPE3FIELD(x) ((x) << S_ULPTYPE3FIELD)
4437 #define G_ULPTYPE3FIELD(x) (((x) >> S_ULPTYPE3FIELD) & M_ULPTYPE3FIELD)
4438 
4439 #define S_ULPTYPE2FIELD    8
4440 #define M_ULPTYPE2FIELD    0xf
4441 #define V_ULPTYPE2FIELD(x) ((x) << S_ULPTYPE2FIELD)
4442 #define G_ULPTYPE2FIELD(x) (((x) >> S_ULPTYPE2FIELD) & M_ULPTYPE2FIELD)
4443 
4444 #define S_ULPTYPE1FIELD    4
4445 #define M_ULPTYPE1FIELD    0xf
4446 #define V_ULPTYPE1FIELD(x) ((x) << S_ULPTYPE1FIELD)
4447 #define G_ULPTYPE1FIELD(x) (((x) >> S_ULPTYPE1FIELD) & M_ULPTYPE1FIELD)
4448 
4449 #define S_ULPTYPE0FIELD    0
4450 #define M_ULPTYPE0FIELD    0xf
4451 #define V_ULPTYPE0FIELD(x) ((x) << S_ULPTYPE0FIELD)
4452 #define G_ULPTYPE0FIELD(x) (((x) >> S_ULPTYPE0FIELD) & M_ULPTYPE0FIELD)
4453 
4454 #define A_TP_PACE_TABLE 0x3d8
4455 #define A_TP_CCTRL_TABLE 0x3dc
4456 #define A_TP_TOS_TABLE 0x3e0
4457 #define A_TP_MTU_TABLE 0x3e4
4458 #define A_TP_RSS_MAP_TABLE 0x3e8
4459 #define A_TP_RSS_LKP_TABLE 0x3ec
4460 #define A_TP_RSS_CONFIG 0x3f0
4461 
4462 #define S_TNL4TUPEN    29
4463 #define V_TNL4TUPEN(x) ((x) << S_TNL4TUPEN)
4464 #define F_TNL4TUPEN    V_TNL4TUPEN(1U)
4465 
4466 #define S_TNL2TUPEN    28
4467 #define V_TNL2TUPEN(x) ((x) << S_TNL2TUPEN)
4468 #define F_TNL2TUPEN    V_TNL2TUPEN(1U)
4469 
4470 #define S_TNLPRTEN    26
4471 #define V_TNLPRTEN(x) ((x) << S_TNLPRTEN)
4472 #define F_TNLPRTEN    V_TNLPRTEN(1U)
4473 
4474 #define S_TNLMAPEN    25
4475 #define V_TNLMAPEN(x) ((x) << S_TNLMAPEN)
4476 #define F_TNLMAPEN    V_TNLMAPEN(1U)
4477 
4478 #define S_TNLLKPEN    24
4479 #define V_TNLLKPEN(x) ((x) << S_TNLLKPEN)
4480 #define F_TNLLKPEN    V_TNLLKPEN(1U)
4481 
4482 #define S_OFD4TUPEN    21
4483 #define V_OFD4TUPEN(x) ((x) << S_OFD4TUPEN)
4484 #define F_OFD4TUPEN    V_OFD4TUPEN(1U)
4485 
4486 #define S_OFD2TUPEN    20
4487 #define V_OFD2TUPEN(x) ((x) << S_OFD2TUPEN)
4488 #define F_OFD2TUPEN    V_OFD2TUPEN(1U)
4489 
4490 #define S_OFDMAPEN    17
4491 #define V_OFDMAPEN(x) ((x) << S_OFDMAPEN)
4492 #define F_OFDMAPEN    V_OFDMAPEN(1U)
4493 
4494 #define S_OFDLKPEN    16
4495 #define V_OFDLKPEN(x) ((x) << S_OFDLKPEN)
4496 #define F_OFDLKPEN    V_OFDLKPEN(1U)
4497 
4498 #define S_SYN4TUPEN    13
4499 #define V_SYN4TUPEN(x) ((x) << S_SYN4TUPEN)
4500 #define F_SYN4TUPEN    V_SYN4TUPEN(1U)
4501 
4502 #define S_SYN2TUPEN    12
4503 #define V_SYN2TUPEN(x) ((x) << S_SYN2TUPEN)
4504 #define F_SYN2TUPEN    V_SYN2TUPEN(1U)
4505 
4506 #define S_SYNMAPEN    9
4507 #define V_SYNMAPEN(x) ((x) << S_SYNMAPEN)
4508 #define F_SYNMAPEN    V_SYNMAPEN(1U)
4509 
4510 #define S_SYNLKPEN    8
4511 #define V_SYNLKPEN(x) ((x) << S_SYNLKPEN)
4512 #define F_SYNLKPEN    V_SYNLKPEN(1U)
4513 
4514 #define S_RRCPLMAPEN    7
4515 #define V_RRCPLMAPEN(x) ((x) << S_RRCPLMAPEN)
4516 #define F_RRCPLMAPEN    V_RRCPLMAPEN(1U)
4517 
4518 #define S_RRCPLCPUSIZE    4
4519 #define M_RRCPLCPUSIZE    0x7
4520 #define V_RRCPLCPUSIZE(x) ((x) << S_RRCPLCPUSIZE)
4521 #define G_RRCPLCPUSIZE(x) (((x) >> S_RRCPLCPUSIZE) & M_RRCPLCPUSIZE)
4522 
4523 #define S_RQFEEDBACKENABLE    3
4524 #define V_RQFEEDBACKENABLE(x) ((x) << S_RQFEEDBACKENABLE)
4525 #define F_RQFEEDBACKENABLE    V_RQFEEDBACKENABLE(1U)
4526 
4527 #define S_HASHTOEPLITZ    2
4528 #define V_HASHTOEPLITZ(x) ((x) << S_HASHTOEPLITZ)
4529 #define F_HASHTOEPLITZ    V_HASHTOEPLITZ(1U)
4530 
4531 #define S_HASHSAVE    1
4532 #define V_HASHSAVE(x) ((x) << S_HASHSAVE)
4533 #define F_HASHSAVE    V_HASHSAVE(1U)
4534 
4535 #define S_DISABLE    0
4536 #define V_DISABLE(x) ((x) << S_DISABLE)
4537 #define F_DISABLE    V_DISABLE(1U)
4538 
4539 #define A_TP_RSS_CONFIG_TNL 0x3f4
4540 
4541 #define S_MASKSIZE    28
4542 #define M_MASKSIZE    0x7
4543 #define V_MASKSIZE(x) ((x) << S_MASKSIZE)
4544 #define G_MASKSIZE(x) (((x) >> S_MASKSIZE) & M_MASKSIZE)
4545 
4546 #define S_DEFAULTCPUBASE    22
4547 #define M_DEFAULTCPUBASE    0x3f
4548 #define V_DEFAULTCPUBASE(x) ((x) << S_DEFAULTCPUBASE)
4549 #define G_DEFAULTCPUBASE(x) (((x) >> S_DEFAULTCPUBASE) & M_DEFAULTCPUBASE)
4550 
4551 #define S_DEFAULTCPU    16
4552 #define M_DEFAULTCPU    0x3f
4553 #define V_DEFAULTCPU(x) ((x) << S_DEFAULTCPU)
4554 #define G_DEFAULTCPU(x) (((x) >> S_DEFAULTCPU) & M_DEFAULTCPU)
4555 
4556 #define S_DEFAULTQUEUE    0
4557 #define M_DEFAULTQUEUE    0xffff
4558 #define V_DEFAULTQUEUE(x) ((x) << S_DEFAULTQUEUE)
4559 #define G_DEFAULTQUEUE(x) (((x) >> S_DEFAULTQUEUE) & M_DEFAULTQUEUE)
4560 
4561 #define A_TP_RSS_CONFIG_OFD 0x3f8
4562 #define A_TP_RSS_CONFIG_SYN 0x3fc
4563 #define A_TP_RSS_SECRET_KEY0 0x400
4564 #define A_TP_RSS_SECRET_KEY1 0x404
4565 #define A_TP_RSS_SECRET_KEY2 0x408
4566 #define A_TP_RSS_SECRET_KEY3 0x40c
4567 #define A_TP_TM_PIO_ADDR 0x418
4568 #define A_TP_TM_PIO_DATA 0x41c
4569 #define A_TP_TX_MOD_QUE_TABLE 0x420
4570 #define A_TP_TX_RESOURCE_LIMIT 0x424
4571 
4572 #define S_TX_RESOURCE_LIMIT_CH1_PC    24
4573 #define M_TX_RESOURCE_LIMIT_CH1_PC    0xff
4574 #define V_TX_RESOURCE_LIMIT_CH1_PC(x) ((x) << S_TX_RESOURCE_LIMIT_CH1_PC)
4575 #define G_TX_RESOURCE_LIMIT_CH1_PC(x) (((x) >> S_TX_RESOURCE_LIMIT_CH1_PC) & M_TX_RESOURCE_LIMIT_CH1_PC)
4576 
4577 #define S_TX_RESOURCE_LIMIT_CH1_NON_PC    16
4578 #define M_TX_RESOURCE_LIMIT_CH1_NON_PC    0xff
4579 #define V_TX_RESOURCE_LIMIT_CH1_NON_PC(x) ((x) << S_TX_RESOURCE_LIMIT_CH1_NON_PC)
4580 #define G_TX_RESOURCE_LIMIT_CH1_NON_PC(x) (((x) >> S_TX_RESOURCE_LIMIT_CH1_NON_PC) & M_TX_RESOURCE_LIMIT_CH1_NON_PC)
4581 
4582 #define S_TX_RESOURCE_LIMIT_CH0_PC    8
4583 #define M_TX_RESOURCE_LIMIT_CH0_PC    0xff
4584 #define V_TX_RESOURCE_LIMIT_CH0_PC(x) ((x) << S_TX_RESOURCE_LIMIT_CH0_PC)
4585 #define G_TX_RESOURCE_LIMIT_CH0_PC(x) (((x) >> S_TX_RESOURCE_LIMIT_CH0_PC) & M_TX_RESOURCE_LIMIT_CH0_PC)
4586 
4587 #define S_TX_RESOURCE_LIMIT_CH0_NON_PC    0
4588 #define M_TX_RESOURCE_LIMIT_CH0_NON_PC    0xff
4589 #define V_TX_RESOURCE_LIMIT_CH0_NON_PC(x) ((x) << S_TX_RESOURCE_LIMIT_CH0_NON_PC)
4590 #define G_TX_RESOURCE_LIMIT_CH0_NON_PC(x) (((x) >> S_TX_RESOURCE_LIMIT_CH0_NON_PC) & M_TX_RESOURCE_LIMIT_CH0_NON_PC)
4591 
4592 #define A_TP_TX_MOD_QUEUE_REQ_MAP 0x428
4593 
4594 #define S_RX_MOD_WEIGHT    24
4595 #define M_RX_MOD_WEIGHT    0xff
4596 #define V_RX_MOD_WEIGHT(x) ((x) << S_RX_MOD_WEIGHT)
4597 #define G_RX_MOD_WEIGHT(x) (((x) >> S_RX_MOD_WEIGHT) & M_RX_MOD_WEIGHT)
4598 
4599 #define S_TX_MOD_WEIGHT    16
4600 #define M_TX_MOD_WEIGHT    0xff
4601 #define V_TX_MOD_WEIGHT(x) ((x) << S_TX_MOD_WEIGHT)
4602 #define G_TX_MOD_WEIGHT(x) (((x) >> S_TX_MOD_WEIGHT) & M_TX_MOD_WEIGHT)
4603 
4604 #define S_TX_MOD_TIMER_MODE    8
4605 #define M_TX_MOD_TIMER_MODE    0xff
4606 #define V_TX_MOD_TIMER_MODE(x) ((x) << S_TX_MOD_TIMER_MODE)
4607 #define G_TX_MOD_TIMER_MODE(x) (((x) >> S_TX_MOD_TIMER_MODE) & M_TX_MOD_TIMER_MODE)
4608 
4609 #define S_TX_MOD_QUEUE_REQ_MAP    0
4610 #define M_TX_MOD_QUEUE_REQ_MAP    0xff
4611 #define V_TX_MOD_QUEUE_REQ_MAP(x) ((x) << S_TX_MOD_QUEUE_REQ_MAP)
4612 #define G_TX_MOD_QUEUE_REQ_MAP(x) (((x) >> S_TX_MOD_QUEUE_REQ_MAP) & M_TX_MOD_QUEUE_REQ_MAP)
4613 
4614 #define A_TP_TX_MOD_QUEUE_WEIGHT1 0x42c
4615 
4616 #define S_TP_TX_MODQ_WGHT7    24
4617 #define M_TP_TX_MODQ_WGHT7    0xff
4618 #define V_TP_TX_MODQ_WGHT7(x) ((x) << S_TP_TX_MODQ_WGHT7)
4619 #define G_TP_TX_MODQ_WGHT7(x) (((x) >> S_TP_TX_MODQ_WGHT7) & M_TP_TX_MODQ_WGHT7)
4620 
4621 #define S_TP_TX_MODQ_WGHT6    16
4622 #define M_TP_TX_MODQ_WGHT6    0xff
4623 #define V_TP_TX_MODQ_WGHT6(x) ((x) << S_TP_TX_MODQ_WGHT6)
4624 #define G_TP_TX_MODQ_WGHT6(x) (((x) >> S_TP_TX_MODQ_WGHT6) & M_TP_TX_MODQ_WGHT6)
4625 
4626 #define S_TP_TX_MODQ_WGHT5    8
4627 #define M_TP_TX_MODQ_WGHT5    0xff
4628 #define V_TP_TX_MODQ_WGHT5(x) ((x) << S_TP_TX_MODQ_WGHT5)
4629 #define G_TP_TX_MODQ_WGHT5(x) (((x) >> S_TP_TX_MODQ_WGHT5) & M_TP_TX_MODQ_WGHT5)
4630 
4631 #define S_TP_TX_MODQ_WGHT4    0
4632 #define M_TP_TX_MODQ_WGHT4    0xff
4633 #define V_TP_TX_MODQ_WGHT4(x) ((x) << S_TP_TX_MODQ_WGHT4)
4634 #define G_TP_TX_MODQ_WGHT4(x) (((x) >> S_TP_TX_MODQ_WGHT4) & M_TP_TX_MODQ_WGHT4)
4635 
4636 #define A_TP_TX_MOD_QUEUE_WEIGHT0 0x430
4637 
4638 #define S_TP_TX_MODQ_WGHT3    24
4639 #define M_TP_TX_MODQ_WGHT3    0xff
4640 #define V_TP_TX_MODQ_WGHT3(x) ((x) << S_TP_TX_MODQ_WGHT3)
4641 #define G_TP_TX_MODQ_WGHT3(x) (((x) >> S_TP_TX_MODQ_WGHT3) & M_TP_TX_MODQ_WGHT3)
4642 
4643 #define S_TP_TX_MODQ_WGHT2    16
4644 #define M_TP_TX_MODQ_WGHT2    0xff
4645 #define V_TP_TX_MODQ_WGHT2(x) ((x) << S_TP_TX_MODQ_WGHT2)
4646 #define G_TP_TX_MODQ_WGHT2(x) (((x) >> S_TP_TX_MODQ_WGHT2) & M_TP_TX_MODQ_WGHT2)
4647 
4648 #define S_TP_TX_MODQ_WGHT1    8
4649 #define M_TP_TX_MODQ_WGHT1    0xff
4650 #define V_TP_TX_MODQ_WGHT1(x) ((x) << S_TP_TX_MODQ_WGHT1)
4651 #define G_TP_TX_MODQ_WGHT1(x) (((x) >> S_TP_TX_MODQ_WGHT1) & M_TP_TX_MODQ_WGHT1)
4652 
4653 #define S_TP_TX_MODQ_WGHT0    0
4654 #define M_TP_TX_MODQ_WGHT0    0xff
4655 #define V_TP_TX_MODQ_WGHT0(x) ((x) << S_TP_TX_MODQ_WGHT0)
4656 #define G_TP_TX_MODQ_WGHT0(x) (((x) >> S_TP_TX_MODQ_WGHT0) & M_TP_TX_MODQ_WGHT0)
4657 
4658 #define A_TP_MOD_CHANNEL_WEIGHT 0x434
4659 
4660 #define S_RX_MOD_CHANNEL_WEIGHT1    24
4661 #define M_RX_MOD_CHANNEL_WEIGHT1    0xff
4662 #define V_RX_MOD_CHANNEL_WEIGHT1(x) ((x) << S_RX_MOD_CHANNEL_WEIGHT1)
4663 #define G_RX_MOD_CHANNEL_WEIGHT1(x) (((x) >> S_RX_MOD_CHANNEL_WEIGHT1) & M_RX_MOD_CHANNEL_WEIGHT1)
4664 
4665 #define S_RX_MOD_CHANNEL_WEIGHT0    16
4666 #define M_RX_MOD_CHANNEL_WEIGHT0    0xff
4667 #define V_RX_MOD_CHANNEL_WEIGHT0(x) ((x) << S_RX_MOD_CHANNEL_WEIGHT0)
4668 #define G_RX_MOD_CHANNEL_WEIGHT0(x) (((x) >> S_RX_MOD_CHANNEL_WEIGHT0) & M_RX_MOD_CHANNEL_WEIGHT0)
4669 
4670 #define S_TX_MOD_CHANNEL_WEIGHT1    8
4671 #define M_TX_MOD_CHANNEL_WEIGHT1    0xff
4672 #define V_TX_MOD_CHANNEL_WEIGHT1(x) ((x) << S_TX_MOD_CHANNEL_WEIGHT1)
4673 #define G_TX_MOD_CHANNEL_WEIGHT1(x) (((x) >> S_TX_MOD_CHANNEL_WEIGHT1) & M_TX_MOD_CHANNEL_WEIGHT1)
4674 
4675 #define S_TX_MOD_CHANNEL_WEIGHT0    0
4676 #define M_TX_MOD_CHANNEL_WEIGHT0    0xff
4677 #define V_TX_MOD_CHANNEL_WEIGHT0(x) ((x) << S_TX_MOD_CHANNEL_WEIGHT0)
4678 #define G_TX_MOD_CHANNEL_WEIGHT0(x) (((x) >> S_TX_MOD_CHANNEL_WEIGHT0) & M_TX_MOD_CHANNEL_WEIGHT0)
4679 
4680 #define A_TP_MOD_RATE_LIMIT 0x438
4681 
4682 #define S_RX_MOD_RATE_LIMIT_INC    24
4683 #define M_RX_MOD_RATE_LIMIT_INC    0xff
4684 #define V_RX_MOD_RATE_LIMIT_INC(x) ((x) << S_RX_MOD_RATE_LIMIT_INC)
4685 #define G_RX_MOD_RATE_LIMIT_INC(x) (((x) >> S_RX_MOD_RATE_LIMIT_INC) & M_RX_MOD_RATE_LIMIT_INC)
4686 
4687 #define S_RX_MOD_RATE_LIMIT_TICK    16
4688 #define M_RX_MOD_RATE_LIMIT_TICK    0xff
4689 #define V_RX_MOD_RATE_LIMIT_TICK(x) ((x) << S_RX_MOD_RATE_LIMIT_TICK)
4690 #define G_RX_MOD_RATE_LIMIT_TICK(x) (((x) >> S_RX_MOD_RATE_LIMIT_TICK) & M_RX_MOD_RATE_LIMIT_TICK)
4691 
4692 #define S_TX_MOD_RATE_LIMIT_INC    8
4693 #define M_TX_MOD_RATE_LIMIT_INC    0xff
4694 #define V_TX_MOD_RATE_LIMIT_INC(x) ((x) << S_TX_MOD_RATE_LIMIT_INC)
4695 #define G_TX_MOD_RATE_LIMIT_INC(x) (((x) >> S_TX_MOD_RATE_LIMIT_INC) & M_TX_MOD_RATE_LIMIT_INC)
4696 
4697 #define S_TX_MOD_RATE_LIMIT_TICK    0
4698 #define M_TX_MOD_RATE_LIMIT_TICK    0xff
4699 #define V_TX_MOD_RATE_LIMIT_TICK(x) ((x) << S_TX_MOD_RATE_LIMIT_TICK)
4700 #define G_TX_MOD_RATE_LIMIT_TICK(x) (((x) >> S_TX_MOD_RATE_LIMIT_TICK) & M_TX_MOD_RATE_LIMIT_TICK)
4701 
4702 #define A_TP_PIO_ADDR 0x440
4703 #define A_TP_PIO_DATA 0x444
4704 #define A_TP_RESET 0x44c
4705 
4706 #define S_FLSTINITENABLE    1
4707 #define V_FLSTINITENABLE(x) ((x) << S_FLSTINITENABLE)
4708 #define F_FLSTINITENABLE    V_FLSTINITENABLE(1U)
4709 
4710 #define S_TPRESET    0
4711 #define V_TPRESET(x) ((x) << S_TPRESET)
4712 #define F_TPRESET    V_TPRESET(1U)
4713 
4714 #define A_TP_MIB_INDEX 0x450
4715 #define A_TP_MIB_RDATA 0x454
4716 #define A_TP_SYNC_TIME_HI 0x458
4717 #define A_TP_SYNC_TIME_LO 0x45c
4718 #define A_TP_CMM_MM_RX_FLST_BASE 0x460
4719 
4720 #define S_CMRXFLSTBASE    0
4721 #define M_CMRXFLSTBASE    0xfffffff
4722 #define V_CMRXFLSTBASE(x) ((x) << S_CMRXFLSTBASE)
4723 #define G_CMRXFLSTBASE(x) (((x) >> S_CMRXFLSTBASE) & M_CMRXFLSTBASE)
4724 
4725 #define A_TP_CMM_MM_TX_FLST_BASE 0x464
4726 
4727 #define S_CMTXFLSTBASE    0
4728 #define M_CMTXFLSTBASE    0xfffffff
4729 #define V_CMTXFLSTBASE(x) ((x) << S_CMTXFLSTBASE)
4730 #define G_CMTXFLSTBASE(x) (((x) >> S_CMTXFLSTBASE) & M_CMTXFLSTBASE)
4731 
4732 #define A_TP_CMM_MM_PS_FLST_BASE 0x468
4733 
4734 #define S_CMPSFLSTBASE    0
4735 #define M_CMPSFLSTBASE    0xfffffff
4736 #define V_CMPSFLSTBASE(x) ((x) << S_CMPSFLSTBASE)
4737 #define G_CMPSFLSTBASE(x) (((x) >> S_CMPSFLSTBASE) & M_CMPSFLSTBASE)
4738 
4739 #define A_TP_CMM_MM_MAX_PSTRUCT 0x46c
4740 
4741 #define S_CMMAXPSTRUCT    0
4742 #define M_CMMAXPSTRUCT    0x1fffff
4743 #define V_CMMAXPSTRUCT(x) ((x) << S_CMMAXPSTRUCT)
4744 #define G_CMMAXPSTRUCT(x) (((x) >> S_CMMAXPSTRUCT) & M_CMMAXPSTRUCT)
4745 
4746 #define A_TP_INT_ENABLE 0x470
4747 
4748 #define S_FLMTXFLSTEMPTY    30
4749 #define V_FLMTXFLSTEMPTY(x) ((x) << S_FLMTXFLSTEMPTY)
4750 #define F_FLMTXFLSTEMPTY    V_FLMTXFLSTEMPTY(1U)
4751 
4752 #define S_FLMRXFLSTEMPTY    29
4753 #define V_FLMRXFLSTEMPTY(x) ((x) << S_FLMRXFLSTEMPTY)
4754 #define F_FLMRXFLSTEMPTY    V_FLMRXFLSTEMPTY(1U)
4755 
4756 #define S_FLMPERRSET    28
4757 #define V_FLMPERRSET(x) ((x) << S_FLMPERRSET)
4758 #define F_FLMPERRSET    V_FLMPERRSET(1U)
4759 
4760 #define S_PROTOCOLSRAMPERR    27
4761 #define V_PROTOCOLSRAMPERR(x) ((x) << S_PROTOCOLSRAMPERR)
4762 #define F_PROTOCOLSRAMPERR    V_PROTOCOLSRAMPERR(1U)
4763 
4764 #define S_ARPLUTPERR    26
4765 #define V_ARPLUTPERR(x) ((x) << S_ARPLUTPERR)
4766 #define F_ARPLUTPERR    V_ARPLUTPERR(1U)
4767 
4768 #define S_CMRCFOPPERR    25
4769 #define V_CMRCFOPPERR(x) ((x) << S_CMRCFOPPERR)
4770 #define F_CMRCFOPPERR    V_CMRCFOPPERR(1U)
4771 
4772 #define S_CMCACHEPERR    24
4773 #define V_CMCACHEPERR(x) ((x) << S_CMCACHEPERR)
4774 #define F_CMCACHEPERR    V_CMCACHEPERR(1U)
4775 
4776 #define S_CMRCFDATAPERR    23
4777 #define V_CMRCFDATAPERR(x) ((x) << S_CMRCFDATAPERR)
4778 #define F_CMRCFDATAPERR    V_CMRCFDATAPERR(1U)
4779 
4780 #define S_DBL2TLUTPERR    22
4781 #define V_DBL2TLUTPERR(x) ((x) << S_DBL2TLUTPERR)
4782 #define F_DBL2TLUTPERR    V_DBL2TLUTPERR(1U)
4783 
4784 #define S_DBTXTIDPERR    21
4785 #define V_DBTXTIDPERR(x) ((x) << S_DBTXTIDPERR)
4786 #define F_DBTXTIDPERR    V_DBTXTIDPERR(1U)
4787 
4788 #define S_DBEXTPERR    20
4789 #define V_DBEXTPERR(x) ((x) << S_DBEXTPERR)
4790 #define F_DBEXTPERR    V_DBEXTPERR(1U)
4791 
4792 #define S_DBOPPERR    19
4793 #define V_DBOPPERR(x) ((x) << S_DBOPPERR)
4794 #define F_DBOPPERR    V_DBOPPERR(1U)
4795 
4796 #define S_TMCACHEPERR    18
4797 #define V_TMCACHEPERR(x) ((x) << S_TMCACHEPERR)
4798 #define F_TMCACHEPERR    V_TMCACHEPERR(1U)
4799 
4800 #define S_ETPOUTCPLFIFOPERR    17
4801 #define V_ETPOUTCPLFIFOPERR(x) ((x) << S_ETPOUTCPLFIFOPERR)
4802 #define F_ETPOUTCPLFIFOPERR    V_ETPOUTCPLFIFOPERR(1U)
4803 
4804 #define S_ETPOUTTCPFIFOPERR    16
4805 #define V_ETPOUTTCPFIFOPERR(x) ((x) << S_ETPOUTTCPFIFOPERR)
4806 #define F_ETPOUTTCPFIFOPERR    V_ETPOUTTCPFIFOPERR(1U)
4807 
4808 #define S_ETPOUTIPFIFOPERR    15
4809 #define V_ETPOUTIPFIFOPERR(x) ((x) << S_ETPOUTIPFIFOPERR)
4810 #define F_ETPOUTIPFIFOPERR    V_ETPOUTIPFIFOPERR(1U)
4811 
4812 #define S_ETPOUTETHFIFOPERR    14
4813 #define V_ETPOUTETHFIFOPERR(x) ((x) << S_ETPOUTETHFIFOPERR)
4814 #define F_ETPOUTETHFIFOPERR    V_ETPOUTETHFIFOPERR(1U)
4815 
4816 #define S_ETPINCPLFIFOPERR    13
4817 #define V_ETPINCPLFIFOPERR(x) ((x) << S_ETPINCPLFIFOPERR)
4818 #define F_ETPINCPLFIFOPERR    V_ETPINCPLFIFOPERR(1U)
4819 
4820 #define S_ETPINTCPOPTFIFOPERR    12
4821 #define V_ETPINTCPOPTFIFOPERR(x) ((x) << S_ETPINTCPOPTFIFOPERR)
4822 #define F_ETPINTCPOPTFIFOPERR    V_ETPINTCPOPTFIFOPERR(1U)
4823 
4824 #define S_ETPINTCPFIFOPERR    11
4825 #define V_ETPINTCPFIFOPERR(x) ((x) << S_ETPINTCPFIFOPERR)
4826 #define F_ETPINTCPFIFOPERR    V_ETPINTCPFIFOPERR(1U)
4827 
4828 #define S_ETPINIPFIFOPERR    10
4829 #define V_ETPINIPFIFOPERR(x) ((x) << S_ETPINIPFIFOPERR)
4830 #define F_ETPINIPFIFOPERR    V_ETPINIPFIFOPERR(1U)
4831 
4832 #define S_ETPINETHFIFOPERR    9
4833 #define V_ETPINETHFIFOPERR(x) ((x) << S_ETPINETHFIFOPERR)
4834 #define F_ETPINETHFIFOPERR    V_ETPINETHFIFOPERR(1U)
4835 
4836 #define S_CTPOUTCPLFIFOPERR    8
4837 #define V_CTPOUTCPLFIFOPERR(x) ((x) << S_CTPOUTCPLFIFOPERR)
4838 #define F_CTPOUTCPLFIFOPERR    V_CTPOUTCPLFIFOPERR(1U)
4839 
4840 #define S_CTPOUTTCPFIFOPERR    7
4841 #define V_CTPOUTTCPFIFOPERR(x) ((x) << S_CTPOUTTCPFIFOPERR)
4842 #define F_CTPOUTTCPFIFOPERR    V_CTPOUTTCPFIFOPERR(1U)
4843 
4844 #define S_CTPOUTIPFIFOPERR    6
4845 #define V_CTPOUTIPFIFOPERR(x) ((x) << S_CTPOUTIPFIFOPERR)
4846 #define F_CTPOUTIPFIFOPERR    V_CTPOUTIPFIFOPERR(1U)
4847 
4848 #define S_CTPOUTETHFIFOPERR    5
4849 #define V_CTPOUTETHFIFOPERR(x) ((x) << S_CTPOUTETHFIFOPERR)
4850 #define F_CTPOUTETHFIFOPERR    V_CTPOUTETHFIFOPERR(1U)
4851 
4852 #define S_CTPINCPLFIFOPERR    4
4853 #define V_CTPINCPLFIFOPERR(x) ((x) << S_CTPINCPLFIFOPERR)
4854 #define F_CTPINCPLFIFOPERR    V_CTPINCPLFIFOPERR(1U)
4855 
4856 #define S_CTPINTCPOPFIFOPERR    3
4857 #define V_CTPINTCPOPFIFOPERR(x) ((x) << S_CTPINTCPOPFIFOPERR)
4858 #define F_CTPINTCPOPFIFOPERR    V_CTPINTCPOPFIFOPERR(1U)
4859 
4860 #define S_CTPINTCPFIFOPERR    2
4861 #define V_CTPINTCPFIFOPERR(x) ((x) << S_CTPINTCPFIFOPERR)
4862 #define F_CTPINTCPFIFOPERR    V_CTPINTCPFIFOPERR(1U)
4863 
4864 #define S_CTPINIPFIFOPERR    1
4865 #define V_CTPINIPFIFOPERR(x) ((x) << S_CTPINIPFIFOPERR)
4866 #define F_CTPINIPFIFOPERR    V_CTPINIPFIFOPERR(1U)
4867 
4868 #define S_CTPINETHFIFOPERR    0
4869 #define V_CTPINETHFIFOPERR(x) ((x) << S_CTPINETHFIFOPERR)
4870 #define F_CTPINETHFIFOPERR    V_CTPINETHFIFOPERR(1U)
4871 
4872 #define A_TP_INT_CAUSE 0x474
4873 #define A_TP_FLM_FREE_PS_CNT 0x480
4874 
4875 #define S_FREEPSTRUCTCOUNT    0
4876 #define M_FREEPSTRUCTCOUNT    0x1fffff
4877 #define V_FREEPSTRUCTCOUNT(x) ((x) << S_FREEPSTRUCTCOUNT)
4878 #define G_FREEPSTRUCTCOUNT(x) (((x) >> S_FREEPSTRUCTCOUNT) & M_FREEPSTRUCTCOUNT)
4879 
4880 #define A_TP_FLM_FREE_RX_CNT 0x484
4881 
4882 #define S_FREERXPAGECOUNT    0
4883 #define M_FREERXPAGECOUNT    0x1fffff
4884 #define V_FREERXPAGECOUNT(x) ((x) << S_FREERXPAGECOUNT)
4885 #define G_FREERXPAGECOUNT(x) (((x) >> S_FREERXPAGECOUNT) & M_FREERXPAGECOUNT)
4886 
4887 #define A_TP_FLM_FREE_TX_CNT 0x488
4888 
4889 #define S_FREETXPAGECOUNT    0
4890 #define M_FREETXPAGECOUNT    0x1fffff
4891 #define V_FREETXPAGECOUNT(x) ((x) << S_FREETXPAGECOUNT)
4892 #define G_FREETXPAGECOUNT(x) (((x) >> S_FREETXPAGECOUNT) & M_FREETXPAGECOUNT)
4893 
4894 #define A_TP_TM_HEAP_PUSH_CNT 0x48c
4895 #define A_TP_TM_HEAP_POP_CNT 0x490
4896 #define A_TP_TM_DACK_PUSH_CNT 0x494
4897 #define A_TP_TM_DACK_POP_CNT 0x498
4898 #define A_TP_TM_MOD_PUSH_CNT 0x49c
4899 #define A_TP_MOD_POP_CNT 0x4a0
4900 #define A_TP_TIMER_SEPARATOR 0x4a4
4901 #define A_TP_DEBUG_SEL 0x4a8
4902 #define A_TP_DEBUG_FLAGS 0x4ac
4903 
4904 #define S_RXTIMERDACKFIRST    26
4905 #define V_RXTIMERDACKFIRST(x) ((x) << S_RXTIMERDACKFIRST)
4906 #define F_RXTIMERDACKFIRST    V_RXTIMERDACKFIRST(1U)
4907 
4908 #define S_RXTIMERDACK    25
4909 #define V_RXTIMERDACK(x) ((x) << S_RXTIMERDACK)
4910 #define F_RXTIMERDACK    V_RXTIMERDACK(1U)
4911 
4912 #define S_RXTIMERHEARTBEAT    24
4913 #define V_RXTIMERHEARTBEAT(x) ((x) << S_RXTIMERHEARTBEAT)
4914 #define F_RXTIMERHEARTBEAT    V_RXTIMERHEARTBEAT(1U)
4915 
4916 #define S_RXPAWSDROP    23
4917 #define V_RXPAWSDROP(x) ((x) << S_RXPAWSDROP)
4918 #define F_RXPAWSDROP    V_RXPAWSDROP(1U)
4919 
4920 #define S_RXURGDATADROP    22
4921 #define V_RXURGDATADROP(x) ((x) << S_RXURGDATADROP)
4922 #define F_RXURGDATADROP    V_RXURGDATADROP(1U)
4923 
4924 #define S_RXFUTUREDATA    21
4925 #define V_RXFUTUREDATA(x) ((x) << S_RXFUTUREDATA)
4926 #define F_RXFUTUREDATA    V_RXFUTUREDATA(1U)
4927 
4928 #define S_RXRCVRXMDATA    20
4929 #define V_RXRCVRXMDATA(x) ((x) << S_RXRCVRXMDATA)
4930 #define F_RXRCVRXMDATA    V_RXRCVRXMDATA(1U)
4931 
4932 #define S_RXRCVOOODATAFIN    19
4933 #define V_RXRCVOOODATAFIN(x) ((x) << S_RXRCVOOODATAFIN)
4934 #define F_RXRCVOOODATAFIN    V_RXRCVOOODATAFIN(1U)
4935 
4936 #define S_RXRCVOOODATA    18
4937 #define V_RXRCVOOODATA(x) ((x) << S_RXRCVOOODATA)
4938 #define F_RXRCVOOODATA    V_RXRCVOOODATA(1U)
4939 
4940 #define S_RXRCVWNDZERO    17
4941 #define V_RXRCVWNDZERO(x) ((x) << S_RXRCVWNDZERO)
4942 #define F_RXRCVWNDZERO    V_RXRCVWNDZERO(1U)
4943 
4944 #define S_RXRCVWNDLTMSS    16
4945 #define V_RXRCVWNDLTMSS(x) ((x) << S_RXRCVWNDLTMSS)
4946 #define F_RXRCVWNDLTMSS    V_RXRCVWNDLTMSS(1U)
4947 
4948 #define S_TXDUPACKINC    11
4949 #define V_TXDUPACKINC(x) ((x) << S_TXDUPACKINC)
4950 #define F_TXDUPACKINC    V_TXDUPACKINC(1U)
4951 
4952 #define S_TXRXMURG    10
4953 #define V_TXRXMURG(x) ((x) << S_TXRXMURG)
4954 #define F_TXRXMURG    V_TXRXMURG(1U)
4955 
4956 #define S_TXRXMFIN    9
4957 #define V_TXRXMFIN(x) ((x) << S_TXRXMFIN)
4958 #define F_TXRXMFIN    V_TXRXMFIN(1U)
4959 
4960 #define S_TXRXMSYN    8
4961 #define V_TXRXMSYN(x) ((x) << S_TXRXMSYN)
4962 #define F_TXRXMSYN    V_TXRXMSYN(1U)
4963 
4964 #define S_TXRXMNEWRENO    7
4965 #define V_TXRXMNEWRENO(x) ((x) << S_TXRXMNEWRENO)
4966 #define F_TXRXMNEWRENO    V_TXRXMNEWRENO(1U)
4967 
4968 #define S_TXRXMFAST    6
4969 #define V_TXRXMFAST(x) ((x) << S_TXRXMFAST)
4970 #define F_TXRXMFAST    V_TXRXMFAST(1U)
4971 
4972 #define S_TXRXMTIMER    5
4973 #define V_TXRXMTIMER(x) ((x) << S_TXRXMTIMER)
4974 #define F_TXRXMTIMER    V_TXRXMTIMER(1U)
4975 
4976 #define S_TXRXMTIMERKEEPALIVE    4
4977 #define V_TXRXMTIMERKEEPALIVE(x) ((x) << S_TXRXMTIMERKEEPALIVE)
4978 #define F_TXRXMTIMERKEEPALIVE    V_TXRXMTIMERKEEPALIVE(1U)
4979 
4980 #define S_TXRXMTIMERPERSIST    3
4981 #define V_TXRXMTIMERPERSIST(x) ((x) << S_TXRXMTIMERPERSIST)
4982 #define F_TXRXMTIMERPERSIST    V_TXRXMTIMERPERSIST(1U)
4983 
4984 #define S_TXRCVADVSHRUNK    2
4985 #define V_TXRCVADVSHRUNK(x) ((x) << S_TXRCVADVSHRUNK)
4986 #define F_TXRCVADVSHRUNK    V_TXRCVADVSHRUNK(1U)
4987 
4988 #define S_TXRCVADVZERO    1
4989 #define V_TXRCVADVZERO(x) ((x) << S_TXRCVADVZERO)
4990 #define F_TXRCVADVZERO    V_TXRCVADVZERO(1U)
4991 
4992 #define S_TXRCVADVLTMSS    0
4993 #define V_TXRCVADVLTMSS(x) ((x) << S_TXRCVADVLTMSS)
4994 #define F_TXRCVADVLTMSS    V_TXRCVADVLTMSS(1U)
4995 
4996 #define S_RXDEBUGFLAGS    16
4997 #define M_RXDEBUGFLAGS    0xffff
4998 #define V_RXDEBUGFLAGS(x) ((x) << S_RXDEBUGFLAGS)
4999 #define G_RXDEBUGFLAGS(x) (((x) >> S_RXDEBUGFLAGS) & M_RXDEBUGFLAGS)
5000 
5001 #define S_TXDEBUGFLAGS    0
5002 #define M_TXDEBUGFLAGS    0xffff
5003 #define V_TXDEBUGFLAGS(x) ((x) << S_TXDEBUGFLAGS)
5004 #define G_TXDEBUGFLAGS(x) (((x) >> S_TXDEBUGFLAGS) & M_TXDEBUGFLAGS)
5005 
5006 #define A_TP_PROXY_FLOW_CNTL 0x4b0
5007 #define A_TP_CM_FLOW_CNTL_MODE 0x4b0
5008 
5009 #define S_CMFLOWCACHEDISABLE    0
5010 #define V_CMFLOWCACHEDISABLE(x) ((x) << S_CMFLOWCACHEDISABLE)
5011 #define F_CMFLOWCACHEDISABLE    V_CMFLOWCACHEDISABLE(1U)
5012 
5013 #define A_TP_PC_CONGESTION_CNTL 0x4b4
5014 
5015 #define S_EDROPTUNNEL    19
5016 #define V_EDROPTUNNEL(x) ((x) << S_EDROPTUNNEL)
5017 #define F_EDROPTUNNEL    V_EDROPTUNNEL(1U)
5018 
5019 #define S_CDROPTUNNEL    18
5020 #define V_CDROPTUNNEL(x) ((x) << S_CDROPTUNNEL)
5021 #define F_CDROPTUNNEL    V_CDROPTUNNEL(1U)
5022 
5023 #define S_ETHRESHOLD    12
5024 #define M_ETHRESHOLD    0x3f
5025 #define V_ETHRESHOLD(x) ((x) << S_ETHRESHOLD)
5026 #define G_ETHRESHOLD(x) (((x) >> S_ETHRESHOLD) & M_ETHRESHOLD)
5027 
5028 #define S_CTHRESHOLD    6
5029 #define M_CTHRESHOLD    0x3f
5030 #define V_CTHRESHOLD(x) ((x) << S_CTHRESHOLD)
5031 #define G_CTHRESHOLD(x) (((x) >> S_CTHRESHOLD) & M_CTHRESHOLD)
5032 
5033 #define S_TXTHRESHOLD    0
5034 #define M_TXTHRESHOLD    0x3f
5035 #define V_TXTHRESHOLD(x) ((x) << S_TXTHRESHOLD)
5036 #define G_TXTHRESHOLD(x) (((x) >> S_TXTHRESHOLD) & M_TXTHRESHOLD)
5037 
5038 #define A_TP_TX_DROP_COUNT 0x4bc
5039 #define A_TP_CLEAR_DEBUG 0x4c0
5040 
5041 #define S_CLRDEBUG    0
5042 #define V_CLRDEBUG(x) ((x) << S_CLRDEBUG)
5043 #define F_CLRDEBUG    V_CLRDEBUG(1U)
5044 
5045 #define A_TP_DEBUG_VEC 0x4c4
5046 #define A_TP_DEBUG_VEC2 0x4c8
5047 #define A_TP_DEBUG_REG_SEL 0x4cc
5048 #define A_TP_DEBUG 0x4d0
5049 #define A_TP_DBG_LA_CONFIG 0x4d4
5050 #define A_TP_DBG_LA_DATAH 0x4d8
5051 #define A_TP_DBG_LA_DATAL 0x4dc
5052 #define A_TP_EMBED_OP_FIELD0 0x4e8
5053 #define A_TP_EMBED_OP_FIELD1 0x4ec
5054 #define A_TP_EMBED_OP_FIELD2 0x4f0
5055 #define A_TP_EMBED_OP_FIELD3 0x4f4
5056 #define A_TP_EMBED_OP_FIELD4 0x4f8
5057 #define A_TP_EMBED_OP_FIELD5 0x4fc
5058 #define A_TP_TX_MOD_Q7_Q6_TIMER_SEPARATOR 0x0
5059 #define A_TP_TX_MOD_Q5_Q4_TIMER_SEPARATOR 0x1
5060 #define A_TP_TX_MOD_Q3_Q2_TIMER_SEPARATOR 0x2
5061 #define A_TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR 0x3
5062 #define A_TP_RX_MOD_Q1_Q0_TIMER_SEPARATOR 0x4
5063 #define A_TP_TX_MOD_Q7_Q6_RATE_LIMIT 0x5
5064 #define A_TP_TX_MOD_Q5_Q4_RATE_LIMIT 0x6
5065 #define A_TP_TX_MOD_Q3_Q2_RATE_LIMIT 0x7
5066 #define A_TP_TX_MOD_Q1_Q0_RATE_LIMIT 0x8
5067 #define A_TP_RX_MOD_Q1_Q0_RATE_LIMIT 0x9
5068 #define A_TP_TX_TRC_KEY0 0x20
5069 #define A_TP_TX_TRC_MASK0 0x21
5070 #define A_TP_TX_TRC_KEY1 0x22
5071 #define A_TP_TX_TRC_MASK1 0x23
5072 #define A_TP_TX_TRC_KEY2 0x24
5073 #define A_TP_TX_TRC_MASK2 0x25
5074 #define A_TP_TX_TRC_KEY3 0x26
5075 #define A_TP_TX_TRC_MASK3 0x27
5076 #define A_TP_IPMI_CFG1 0x28
5077 
5078 #define S_VLANENABLE    31
5079 #define V_VLANENABLE(x) ((x) << S_VLANENABLE)
5080 #define F_VLANENABLE    V_VLANENABLE(1U)
5081 
5082 #define S_PRIMARYPORTENABLE    30
5083 #define V_PRIMARYPORTENABLE(x) ((x) << S_PRIMARYPORTENABLE)
5084 #define F_PRIMARYPORTENABLE    V_PRIMARYPORTENABLE(1U)
5085 
5086 #define S_SECUREPORTENABLE    29
5087 #define V_SECUREPORTENABLE(x) ((x) << S_SECUREPORTENABLE)
5088 #define F_SECUREPORTENABLE    V_SECUREPORTENABLE(1U)
5089 
5090 #define S_ARPENABLE    28
5091 #define V_ARPENABLE(x) ((x) << S_ARPENABLE)
5092 #define F_ARPENABLE    V_ARPENABLE(1U)
5093 
5094 #define S_VLAN    0
5095 #define M_VLAN    0xffff
5096 #define V_VLAN(x) ((x) << S_VLAN)
5097 #define G_VLAN(x) (((x) >> S_VLAN) & M_VLAN)
5098 
5099 #define A_TP_IPMI_CFG2 0x29
5100 
5101 #define S_SECUREPORT    16
5102 #define M_SECUREPORT    0xffff
5103 #define V_SECUREPORT(x) ((x) << S_SECUREPORT)
5104 #define G_SECUREPORT(x) (((x) >> S_SECUREPORT) & M_SECUREPORT)
5105 
5106 #define S_PRIMARYPORT    0
5107 #define M_PRIMARYPORT    0xffff
5108 #define V_PRIMARYPORT(x) ((x) << S_PRIMARYPORT)
5109 #define G_PRIMARYPORT(x) (((x) >> S_PRIMARYPORT) & M_PRIMARYPORT)
5110 
5111 #define A_TP_RX_TRC_KEY0 0x120
5112 #define A_TP_RX_TRC_MASK0 0x121
5113 #define A_TP_RX_TRC_KEY1 0x122
5114 #define A_TP_RX_TRC_MASK1 0x123
5115 #define A_TP_RX_TRC_KEY2 0x124
5116 #define A_TP_RX_TRC_MASK2 0x125
5117 #define A_TP_RX_TRC_KEY3 0x126
5118 #define A_TP_RX_TRC_MASK3 0x127
5119 #define A_TP_QOS_RX_TOS_MAP_H 0x128
5120 #define A_TP_QOS_RX_TOS_MAP_L 0x129
5121 #define A_TP_QOS_RX_MAP_MODE 0x12a
5122 
5123 #define S_DEFAULTCH    11
5124 #define V_DEFAULTCH(x) ((x) << S_DEFAULTCH)
5125 #define F_DEFAULTCH    V_DEFAULTCH(1U)
5126 
5127 #define S_RXMAPMODE    8
5128 #define M_RXMAPMODE    0x7
5129 #define V_RXMAPMODE(x) ((x) << S_RXMAPMODE)
5130 #define G_RXMAPMODE(x) (((x) >> S_RXMAPMODE) & M_RXMAPMODE)
5131 
5132 #define S_RXVLANMAP    7
5133 #define V_RXVLANMAP(x) ((x) << S_RXVLANMAP)
5134 #define F_RXVLANMAP    V_RXVLANMAP(1U)
5135 
5136 #define A_TP_TX_DROP_CFG_CH0 0x12b
5137 
5138 #define S_TIMERENABLED    31
5139 #define V_TIMERENABLED(x) ((x) << S_TIMERENABLED)
5140 #define F_TIMERENABLED    V_TIMERENABLED(1U)
5141 
5142 #define S_TIMERERRORENABLE    30
5143 #define V_TIMERERRORENABLE(x) ((x) << S_TIMERERRORENABLE)
5144 #define F_TIMERERRORENABLE    V_TIMERERRORENABLE(1U)
5145 
5146 #define S_TIMERTHRESHOLD    4
5147 #define M_TIMERTHRESHOLD    0x3ffffff
5148 #define V_TIMERTHRESHOLD(x) ((x) << S_TIMERTHRESHOLD)
5149 #define G_TIMERTHRESHOLD(x) (((x) >> S_TIMERTHRESHOLD) & M_TIMERTHRESHOLD)
5150 
5151 #define S_PACKETDROPS    0
5152 #define M_PACKETDROPS    0xf
5153 #define V_PACKETDROPS(x) ((x) << S_PACKETDROPS)
5154 #define G_PACKETDROPS(x) (((x) >> S_PACKETDROPS) & M_PACKETDROPS)
5155 
5156 #define A_TP_TX_DROP_CFG_CH1 0x12c
5157 #define A_TP_TX_DROP_CNT_CH0 0x12d
5158 
5159 #define S_TXDROPCNTCH0SENT    16
5160 #define M_TXDROPCNTCH0SENT    0xffff
5161 #define V_TXDROPCNTCH0SENT(x) ((x) << S_TXDROPCNTCH0SENT)
5162 #define G_TXDROPCNTCH0SENT(x) (((x) >> S_TXDROPCNTCH0SENT) & M_TXDROPCNTCH0SENT)
5163 
5164 #define S_TXDROPCNTCH0RCVD    0
5165 #define M_TXDROPCNTCH0RCVD    0xffff
5166 #define V_TXDROPCNTCH0RCVD(x) ((x) << S_TXDROPCNTCH0RCVD)
5167 #define G_TXDROPCNTCH0RCVD(x) (((x) >> S_TXDROPCNTCH0RCVD) & M_TXDROPCNTCH0RCVD)
5168 
5169 #define A_TP_TX_DROP_CNT_CH1 0x12e
5170 
5171 #define S_TXDROPCNTCH1SENT    16
5172 #define M_TXDROPCNTCH1SENT    0xffff
5173 #define V_TXDROPCNTCH1SENT(x) ((x) << S_TXDROPCNTCH1SENT)
5174 #define G_TXDROPCNTCH1SENT(x) (((x) >> S_TXDROPCNTCH1SENT) & M_TXDROPCNTCH1SENT)
5175 
5176 #define S_TXDROPCNTCH1RCVD    0
5177 #define M_TXDROPCNTCH1RCVD    0xffff
5178 #define V_TXDROPCNTCH1RCVD(x) ((x) << S_TXDROPCNTCH1RCVD)
5179 #define G_TXDROPCNTCH1RCVD(x) (((x) >> S_TXDROPCNTCH1RCVD) & M_TXDROPCNTCH1RCVD)
5180 
5181 #define A_TP_TX_DROP_MODE 0x12f
5182 
5183 #define S_TXDROPMODECH1    1
5184 #define V_TXDROPMODECH1(x) ((x) << S_TXDROPMODECH1)
5185 #define F_TXDROPMODECH1    V_TXDROPMODECH1(1U)
5186 
5187 #define S_TXDROPMODECH0    0
5188 #define V_TXDROPMODECH0(x) ((x) << S_TXDROPMODECH0)
5189 #define F_TXDROPMODECH0    V_TXDROPMODECH0(1U)
5190 
5191 #define A_TP_VLAN_PRI_MAP 0x137
5192 
5193 #define S_VLANPRIMAP7    14
5194 #define M_VLANPRIMAP7    0x3
5195 #define V_VLANPRIMAP7(x) ((x) << S_VLANPRIMAP7)
5196 #define G_VLANPRIMAP7(x) (((x) >> S_VLANPRIMAP7) & M_VLANPRIMAP7)
5197 
5198 #define S_VLANPRIMAP6    12
5199 #define M_VLANPRIMAP6    0x3
5200 #define V_VLANPRIMAP6(x) ((x) << S_VLANPRIMAP6)
5201 #define G_VLANPRIMAP6(x) (((x) >> S_VLANPRIMAP6) & M_VLANPRIMAP6)
5202 
5203 #define S_VLANPRIMAP5    10
5204 #define M_VLANPRIMAP5    0x3
5205 #define V_VLANPRIMAP5(x) ((x) << S_VLANPRIMAP5)
5206 #define G_VLANPRIMAP5(x) (((x) >> S_VLANPRIMAP5) & M_VLANPRIMAP5)
5207 
5208 #define S_VLANPRIMAP4    8
5209 #define M_VLANPRIMAP4    0x3
5210 #define V_VLANPRIMAP4(x) ((x) << S_VLANPRIMAP4)
5211 #define G_VLANPRIMAP4(x) (((x) >> S_VLANPRIMAP4) & M_VLANPRIMAP4)
5212 
5213 #define S_VLANPRIMAP3    6
5214 #define M_VLANPRIMAP3    0x3
5215 #define V_VLANPRIMAP3(x) ((x) << S_VLANPRIMAP3)
5216 #define G_VLANPRIMAP3(x) (((x) >> S_VLANPRIMAP3) & M_VLANPRIMAP3)
5217 
5218 #define S_VLANPRIMAP2    4
5219 #define M_VLANPRIMAP2    0x3
5220 #define V_VLANPRIMAP2(x) ((x) << S_VLANPRIMAP2)
5221 #define G_VLANPRIMAP2(x) (((x) >> S_VLANPRIMAP2) & M_VLANPRIMAP2)
5222 
5223 #define S_VLANPRIMAP1    2
5224 #define M_VLANPRIMAP1    0x3
5225 #define V_VLANPRIMAP1(x) ((x) << S_VLANPRIMAP1)
5226 #define G_VLANPRIMAP1(x) (((x) >> S_VLANPRIMAP1) & M_VLANPRIMAP1)
5227 
5228 #define S_VLANPRIMAP0    0
5229 #define M_VLANPRIMAP0    0x3
5230 #define V_VLANPRIMAP0(x) ((x) << S_VLANPRIMAP0)
5231 #define G_VLANPRIMAP0(x) (((x) >> S_VLANPRIMAP0) & M_VLANPRIMAP0)
5232 
5233 #define A_TP_MAC_MATCH_MAP0 0x138
5234 
5235 #define S_MACMATCHMAP7    21
5236 #define M_MACMATCHMAP7    0x7
5237 #define V_MACMATCHMAP7(x) ((x) << S_MACMATCHMAP7)
5238 #define G_MACMATCHMAP7(x) (((x) >> S_MACMATCHMAP7) & M_MACMATCHMAP7)
5239 
5240 #define S_MACMATCHMAP6    18
5241 #define M_MACMATCHMAP6    0x7
5242 #define V_MACMATCHMAP6(x) ((x) << S_MACMATCHMAP6)
5243 #define G_MACMATCHMAP6(x) (((x) >> S_MACMATCHMAP6) & M_MACMATCHMAP6)
5244 
5245 #define S_MACMATCHMAP5    15
5246 #define M_MACMATCHMAP5    0x7
5247 #define V_MACMATCHMAP5(x) ((x) << S_MACMATCHMAP5)
5248 #define G_MACMATCHMAP5(x) (((x) >> S_MACMATCHMAP5) & M_MACMATCHMAP5)
5249 
5250 #define S_MACMATCHMAP4    12
5251 #define M_MACMATCHMAP4    0x7
5252 #define V_MACMATCHMAP4(x) ((x) << S_MACMATCHMAP4)
5253 #define G_MACMATCHMAP4(x) (((x) >> S_MACMATCHMAP4) & M_MACMATCHMAP4)
5254 
5255 #define S_MACMATCHMAP3    9
5256 #define M_MACMATCHMAP3    0x7
5257 #define V_MACMATCHMAP3(x) ((x) << S_MACMATCHMAP3)
5258 #define G_MACMATCHMAP3(x) (((x) >> S_MACMATCHMAP3) & M_MACMATCHMAP3)
5259 
5260 #define S_MACMATCHMAP2    6
5261 #define M_MACMATCHMAP2    0x7
5262 #define V_MACMATCHMAP2(x) ((x) << S_MACMATCHMAP2)
5263 #define G_MACMATCHMAP2(x) (((x) >> S_MACMATCHMAP2) & M_MACMATCHMAP2)
5264 
5265 #define S_MACMATCHMAP1    3
5266 #define M_MACMATCHMAP1    0x7
5267 #define V_MACMATCHMAP1(x) ((x) << S_MACMATCHMAP1)
5268 #define G_MACMATCHMAP1(x) (((x) >> S_MACMATCHMAP1) & M_MACMATCHMAP1)
5269 
5270 #define S_MACMATCHMAP0    0
5271 #define M_MACMATCHMAP0    0x7
5272 #define V_MACMATCHMAP0(x) ((x) << S_MACMATCHMAP0)
5273 #define G_MACMATCHMAP0(x) (((x) >> S_MACMATCHMAP0) & M_MACMATCHMAP0)
5274 
5275 #define A_TP_MAC_MATCH_MAP1 0x139
5276 #define A_TP_INGRESS_CONFIG 0x141
5277 
5278 #define S_LOOKUPEVERYPKT    28
5279 #define V_LOOKUPEVERYPKT(x) ((x) << S_LOOKUPEVERYPKT)
5280 #define F_LOOKUPEVERYPKT    V_LOOKUPEVERYPKT(1U)
5281 
5282 #define S_ENABLEINSERTIONSFD    27
5283 #define V_ENABLEINSERTIONSFD(x) ((x) << S_ENABLEINSERTIONSFD)
5284 #define F_ENABLEINSERTIONSFD    V_ENABLEINSERTIONSFD(1U)
5285 
5286 #define S_ENABLEINSERTION    26
5287 #define V_ENABLEINSERTION(x) ((x) << S_ENABLEINSERTION)
5288 #define F_ENABLEINSERTION    V_ENABLEINSERTION(1U)
5289 
5290 #define S_ENABLEEXTRACTIONSFD    25
5291 #define V_ENABLEEXTRACTIONSFD(x) ((x) << S_ENABLEEXTRACTIONSFD)
5292 #define F_ENABLEEXTRACTIONSFD    V_ENABLEEXTRACTIONSFD(1U)
5293 
5294 #define S_ENABLEEXTRACT    24
5295 #define V_ENABLEEXTRACT(x) ((x) << S_ENABLEEXTRACT)
5296 #define F_ENABLEEXTRACT    V_ENABLEEXTRACT(1U)
5297 
5298 #define S_BITPOS3    18
5299 #define M_BITPOS3    0x3f
5300 #define V_BITPOS3(x) ((x) << S_BITPOS3)
5301 #define G_BITPOS3(x) (((x) >> S_BITPOS3) & M_BITPOS3)
5302 
5303 #define S_BITPOS2    12
5304 #define M_BITPOS2    0x3f
5305 #define V_BITPOS2(x) ((x) << S_BITPOS2)
5306 #define G_BITPOS2(x) (((x) >> S_BITPOS2) & M_BITPOS2)
5307 
5308 #define S_BITPOS1    6
5309 #define M_BITPOS1    0x3f
5310 #define V_BITPOS1(x) ((x) << S_BITPOS1)
5311 #define G_BITPOS1(x) (((x) >> S_BITPOS1) & M_BITPOS1)
5312 
5313 #define S_BITPOS0    0
5314 #define M_BITPOS0    0x3f
5315 #define V_BITPOS0(x) ((x) << S_BITPOS0)
5316 #define G_BITPOS0(x) (((x) >> S_BITPOS0) & M_BITPOS0)
5317 
5318 #define A_TP_PREAMBLE_MSB 0x142
5319 #define A_TP_PREAMBLE_LSB 0x143
5320 #define A_TP_EGRESS_CONFIG 0x145
5321 
5322 #define S_REWRITEFORCETOSIZE    0
5323 #define V_REWRITEFORCETOSIZE(x) ((x) << S_REWRITEFORCETOSIZE)
5324 #define F_REWRITEFORCETOSIZE    V_REWRITEFORCETOSIZE(1U)
5325 
5326 #define A_TP_INTF_FROM_TX_PKT 0x244
5327 
5328 #define S_INTFFROMTXPKT    0
5329 #define V_INTFFROMTXPKT(x) ((x) << S_INTFFROMTXPKT)
5330 #define F_INTFFROMTXPKT    V_INTFFROMTXPKT(1U)
5331 
5332 #define A_TP_FIFO_CONFIG 0x8c0
5333 
5334 #define S_RXFIFOCONFIG    10
5335 #define M_RXFIFOCONFIG    0x3f
5336 #define V_RXFIFOCONFIG(x) ((x) << S_RXFIFOCONFIG)
5337 #define G_RXFIFOCONFIG(x) (((x) >> S_RXFIFOCONFIG) & M_RXFIFOCONFIG)
5338 
5339 #define S_TXFIFOCONFIG    2
5340 #define M_TXFIFOCONFIG    0x3f
5341 #define V_TXFIFOCONFIG(x) ((x) << S_TXFIFOCONFIG)
5342 #define G_TXFIFOCONFIG(x) (((x) >> S_TXFIFOCONFIG) & M_TXFIFOCONFIG)
5343 
5344 /* registers for module ULP2_RX */
5345 #define ULP2_RX_BASE_ADDR 0x500
5346 
5347 #define A_ULPRX_CTL 0x500
5348 
5349 #define S_PCMD1THRESHOLD    24
5350 #define M_PCMD1THRESHOLD    0xff
5351 #define V_PCMD1THRESHOLD(x) ((x) << S_PCMD1THRESHOLD)
5352 #define G_PCMD1THRESHOLD(x) (((x) >> S_PCMD1THRESHOLD) & M_PCMD1THRESHOLD)
5353 
5354 #define S_PCMD0THRESHOLD    16
5355 #define M_PCMD0THRESHOLD    0xff
5356 #define V_PCMD0THRESHOLD(x) ((x) << S_PCMD0THRESHOLD)
5357 #define G_PCMD0THRESHOLD(x) (((x) >> S_PCMD0THRESHOLD) & M_PCMD0THRESHOLD)
5358 
5359 #define S_ROUND_ROBIN    4
5360 #define V_ROUND_ROBIN(x) ((x) << S_ROUND_ROBIN)
5361 #define F_ROUND_ROBIN    V_ROUND_ROBIN(1U)
5362 
5363 #define S_RDMA_PERMISSIVE_MODE    3
5364 #define V_RDMA_PERMISSIVE_MODE(x) ((x) << S_RDMA_PERMISSIVE_MODE)
5365 #define F_RDMA_PERMISSIVE_MODE    V_RDMA_PERMISSIVE_MODE(1U)
5366 
5367 #define S_PAGEPODME    2
5368 #define V_PAGEPODME(x) ((x) << S_PAGEPODME)
5369 #define F_PAGEPODME    V_PAGEPODME(1U)
5370 
5371 #define S_ISCSITAGTCB    1
5372 #define V_ISCSITAGTCB(x) ((x) << S_ISCSITAGTCB)
5373 #define F_ISCSITAGTCB    V_ISCSITAGTCB(1U)
5374 
5375 #define S_TDDPTAGTCB    0
5376 #define V_TDDPTAGTCB(x) ((x) << S_TDDPTAGTCB)
5377 #define F_TDDPTAGTCB    V_TDDPTAGTCB(1U)
5378 
5379 #define A_ULPRX_INT_ENABLE 0x504
5380 
5381 #define S_DATASELFRAMEERR0    7
5382 #define V_DATASELFRAMEERR0(x) ((x) << S_DATASELFRAMEERR0)
5383 #define F_DATASELFRAMEERR0    V_DATASELFRAMEERR0(1U)
5384 
5385 #define S_DATASELFRAMEERR1    6
5386 #define V_DATASELFRAMEERR1(x) ((x) << S_DATASELFRAMEERR1)
5387 #define F_DATASELFRAMEERR1    V_DATASELFRAMEERR1(1U)
5388 
5389 #define S_PCMDMUXPERR    5
5390 #define V_PCMDMUXPERR(x) ((x) << S_PCMDMUXPERR)
5391 #define F_PCMDMUXPERR    V_PCMDMUXPERR(1U)
5392 
5393 #define S_ARBFPERR    4
5394 #define V_ARBFPERR(x) ((x) << S_ARBFPERR)
5395 #define F_ARBFPERR    V_ARBFPERR(1U)
5396 
5397 #define S_ARBPF0PERR    3
5398 #define V_ARBPF0PERR(x) ((x) << S_ARBPF0PERR)
5399 #define F_ARBPF0PERR    V_ARBPF0PERR(1U)
5400 
5401 #define S_ARBPF1PERR    2
5402 #define V_ARBPF1PERR(x) ((x) << S_ARBPF1PERR)
5403 #define F_ARBPF1PERR    V_ARBPF1PERR(1U)
5404 
5405 #define S_PARERRPCMD    1
5406 #define V_PARERRPCMD(x) ((x) << S_PARERRPCMD)
5407 #define F_PARERRPCMD    V_PARERRPCMD(1U)
5408 
5409 #define S_PARERRDATA    0
5410 #define V_PARERRDATA(x) ((x) << S_PARERRDATA)
5411 #define F_PARERRDATA    V_PARERRDATA(1U)
5412 
5413 #define S_PARERR    0
5414 #define V_PARERR(x) ((x) << S_PARERR)
5415 #define F_PARERR    V_PARERR(1U)
5416 
5417 #define A_ULPRX_INT_CAUSE 0x508
5418 #define A_ULPRX_ISCSI_LLIMIT 0x50c
5419 
5420 #define S_ISCSILLIMIT    6
5421 #define M_ISCSILLIMIT    0x3ffffff
5422 #define V_ISCSILLIMIT(x) ((x) << S_ISCSILLIMIT)
5423 #define G_ISCSILLIMIT(x) (((x) >> S_ISCSILLIMIT) & M_ISCSILLIMIT)
5424 
5425 #define A_ULPRX_ISCSI_ULIMIT 0x510
5426 
5427 #define S_ISCSIULIMIT    6
5428 #define M_ISCSIULIMIT    0x3ffffff
5429 #define V_ISCSIULIMIT(x) ((x) << S_ISCSIULIMIT)
5430 #define G_ISCSIULIMIT(x) (((x) >> S_ISCSIULIMIT) & M_ISCSIULIMIT)
5431 
5432 #define A_ULPRX_ISCSI_TAGMASK 0x514
5433 
5434 #define S_ISCSITAGMASK    6
5435 #define M_ISCSITAGMASK    0x3ffffff
5436 #define V_ISCSITAGMASK(x) ((x) << S_ISCSITAGMASK)
5437 #define G_ISCSITAGMASK(x) (((x) >> S_ISCSITAGMASK) & M_ISCSITAGMASK)
5438 
5439 #define A_ULPRX_ISCSI_PSZ 0x518
5440 
5441 #define S_HPZ3    24
5442 #define M_HPZ3    0xf
5443 #define V_HPZ3(x) ((x) << S_HPZ3)
5444 #define G_HPZ3(x) (((x) >> S_HPZ3) & M_HPZ3)
5445 
5446 #define S_HPZ2    16
5447 #define M_HPZ2    0xf
5448 #define V_HPZ2(x) ((x) << S_HPZ2)
5449 #define G_HPZ2(x) (((x) >> S_HPZ2) & M_HPZ2)
5450 
5451 #define S_HPZ1    8
5452 #define M_HPZ1    0xf
5453 #define V_HPZ1(x) ((x) << S_HPZ1)
5454 #define G_HPZ1(x) (((x) >> S_HPZ1) & M_HPZ1)
5455 
5456 #define S_HPZ0    0
5457 #define M_HPZ0    0xf
5458 #define V_HPZ0(x) ((x) << S_HPZ0)
5459 #define G_HPZ0(x) (((x) >> S_HPZ0) & M_HPZ0)
5460 
5461 #define A_ULPRX_TDDP_LLIMIT 0x51c
5462 
5463 #define S_TDDPLLIMIT    6
5464 #define M_TDDPLLIMIT    0x3ffffff
5465 #define V_TDDPLLIMIT(x) ((x) << S_TDDPLLIMIT)
5466 #define G_TDDPLLIMIT(x) (((x) >> S_TDDPLLIMIT) & M_TDDPLLIMIT)
5467 
5468 #define A_ULPRX_TDDP_ULIMIT 0x520
5469 
5470 #define S_TDDPULIMIT    6
5471 #define M_TDDPULIMIT    0x3ffffff
5472 #define V_TDDPULIMIT(x) ((x) << S_TDDPULIMIT)
5473 #define G_TDDPULIMIT(x) (((x) >> S_TDDPULIMIT) & M_TDDPULIMIT)
5474 
5475 #define A_ULPRX_TDDP_TAGMASK 0x524
5476 
5477 #define S_TDDPTAGMASK    6
5478 #define M_TDDPTAGMASK    0x3ffffff
5479 #define V_TDDPTAGMASK(x) ((x) << S_TDDPTAGMASK)
5480 #define G_TDDPTAGMASK(x) (((x) >> S_TDDPTAGMASK) & M_TDDPTAGMASK)
5481 
5482 #define A_ULPRX_TDDP_PSZ 0x528
5483 #define A_ULPRX_STAG_LLIMIT 0x52c
5484 #define A_ULPRX_STAG_ULIMIT 0x530
5485 #define A_ULPRX_RQ_LLIMIT 0x534
5486 #define A_ULPRX_RQ_ULIMIT 0x538
5487 #define A_ULPRX_PBL_LLIMIT 0x53c
5488 #define A_ULPRX_PBL_ULIMIT 0x540
5489 
5490 /* registers for module ULP2_TX */
5491 #define ULP2_TX_BASE_ADDR 0x580
5492 
5493 #define A_ULPTX_CONFIG 0x580
5494 
5495 #define S_CFG_CQE_SOP_MASK    1
5496 #define V_CFG_CQE_SOP_MASK(x) ((x) << S_CFG_CQE_SOP_MASK)
5497 #define F_CFG_CQE_SOP_MASK    V_CFG_CQE_SOP_MASK(1U)
5498 
5499 #define S_CFG_RR_ARB    0
5500 #define V_CFG_RR_ARB(x) ((x) << S_CFG_RR_ARB)
5501 #define F_CFG_RR_ARB    V_CFG_RR_ARB(1U)
5502 
5503 #define A_ULPTX_INT_ENABLE 0x584
5504 
5505 #define S_CMD_FIFO_PERR_SET1    7
5506 #define V_CMD_FIFO_PERR_SET1(x) ((x) << S_CMD_FIFO_PERR_SET1)
5507 #define F_CMD_FIFO_PERR_SET1    V_CMD_FIFO_PERR_SET1(1U)
5508 
5509 #define S_CMD_FIFO_PERR_SET0    6
5510 #define V_CMD_FIFO_PERR_SET0(x) ((x) << S_CMD_FIFO_PERR_SET0)
5511 #define F_CMD_FIFO_PERR_SET0    V_CMD_FIFO_PERR_SET0(1U)
5512 
5513 #define S_LSO_HDR_SRAM_PERR_SET1    5
5514 #define V_LSO_HDR_SRAM_PERR_SET1(x) ((x) << S_LSO_HDR_SRAM_PERR_SET1)
5515 #define F_LSO_HDR_SRAM_PERR_SET1    V_LSO_HDR_SRAM_PERR_SET1(1U)
5516 
5517 #define S_LSO_HDR_SRAM_PERR_SET0    4
5518 #define V_LSO_HDR_SRAM_PERR_SET0(x) ((x) << S_LSO_HDR_SRAM_PERR_SET0)
5519 #define F_LSO_HDR_SRAM_PERR_SET0    V_LSO_HDR_SRAM_PERR_SET0(1U)
5520 
5521 #define S_IMM_DATA_PERR_SET_CH1    3
5522 #define V_IMM_DATA_PERR_SET_CH1(x) ((x) << S_IMM_DATA_PERR_SET_CH1)
5523 #define F_IMM_DATA_PERR_SET_CH1    V_IMM_DATA_PERR_SET_CH1(1U)
5524 
5525 #define S_IMM_DATA_PERR_SET_CH0    2
5526 #define V_IMM_DATA_PERR_SET_CH0(x) ((x) << S_IMM_DATA_PERR_SET_CH0)
5527 #define F_IMM_DATA_PERR_SET_CH0    V_IMM_DATA_PERR_SET_CH0(1U)
5528 
5529 #define S_PBL_BOUND_ERR_CH1    1
5530 #define V_PBL_BOUND_ERR_CH1(x) ((x) << S_PBL_BOUND_ERR_CH1)
5531 #define F_PBL_BOUND_ERR_CH1    V_PBL_BOUND_ERR_CH1(1U)
5532 
5533 #define S_PBL_BOUND_ERR_CH0    0
5534 #define V_PBL_BOUND_ERR_CH0(x) ((x) << S_PBL_BOUND_ERR_CH0)
5535 #define F_PBL_BOUND_ERR_CH0    V_PBL_BOUND_ERR_CH0(1U)
5536 
5537 #define A_ULPTX_INT_CAUSE 0x588
5538 #define A_ULPTX_TPT_LLIMIT 0x58c
5539 #define A_ULPTX_TPT_ULIMIT 0x590
5540 #define A_ULPTX_PBL_LLIMIT 0x594
5541 #define A_ULPTX_PBL_ULIMIT 0x598
5542 #define A_ULPTX_CPL_ERR_OFFSET 0x59c
5543 #define A_ULPTX_CPL_ERR_MASK 0x5a0
5544 #define A_ULPTX_CPL_ERR_VALUE 0x5a4
5545 #define A_ULPTX_CPL_PACK_SIZE 0x5a8
5546 
5547 #define S_VALUE    24
5548 #define M_VALUE    0xff
5549 #define V_VALUE(x) ((x) << S_VALUE)
5550 #define G_VALUE(x) (((x) >> S_VALUE) & M_VALUE)
5551 
5552 #define S_CH1SIZE2    24
5553 #define M_CH1SIZE2    0xff
5554 #define V_CH1SIZE2(x) ((x) << S_CH1SIZE2)
5555 #define G_CH1SIZE2(x) (((x) >> S_CH1SIZE2) & M_CH1SIZE2)
5556 
5557 #define S_CH1SIZE1    16
5558 #define M_CH1SIZE1    0xff
5559 #define V_CH1SIZE1(x) ((x) << S_CH1SIZE1)
5560 #define G_CH1SIZE1(x) (((x) >> S_CH1SIZE1) & M_CH1SIZE1)
5561 
5562 #define S_CH0SIZE2    8
5563 #define M_CH0SIZE2    0xff
5564 #define V_CH0SIZE2(x) ((x) << S_CH0SIZE2)
5565 #define G_CH0SIZE2(x) (((x) >> S_CH0SIZE2) & M_CH0SIZE2)
5566 
5567 #define S_CH0SIZE1    0
5568 #define M_CH0SIZE1    0xff
5569 #define V_CH0SIZE1(x) ((x) << S_CH0SIZE1)
5570 #define G_CH0SIZE1(x) (((x) >> S_CH0SIZE1) & M_CH0SIZE1)
5571 
5572 #define A_ULPTX_DMA_WEIGHT 0x5ac
5573 
5574 #define S_D1_WEIGHT    16
5575 #define M_D1_WEIGHT    0xffff
5576 #define V_D1_WEIGHT(x) ((x) << S_D1_WEIGHT)
5577 #define G_D1_WEIGHT(x) (((x) >> S_D1_WEIGHT) & M_D1_WEIGHT)
5578 
5579 #define S_D0_WEIGHT    0
5580 #define M_D0_WEIGHT    0xffff
5581 #define V_D0_WEIGHT(x) ((x) << S_D0_WEIGHT)
5582 #define G_D0_WEIGHT(x) (((x) >> S_D0_WEIGHT) & M_D0_WEIGHT)
5583 
5584 /* registers for module PM1_RX */
5585 #define PM1_RX_BASE_ADDR 0x5c0
5586 
5587 #define A_PM1_RX_CFG 0x5c0
5588 #define A_PM1_RX_MODE 0x5c4
5589 
5590 #define S_STAT_CHANNEL    1
5591 #define V_STAT_CHANNEL(x) ((x) << S_STAT_CHANNEL)
5592 #define F_STAT_CHANNEL    V_STAT_CHANNEL(1U)
5593 
5594 #define S_PRIORITY_CH    0
5595 #define V_PRIORITY_CH(x) ((x) << S_PRIORITY_CH)
5596 #define F_PRIORITY_CH    V_PRIORITY_CH(1U)
5597 
5598 #define A_PM1_RX_STAT_CONFIG 0x5c8
5599 #define A_PM1_RX_STAT_COUNT 0x5cc
5600 #define A_PM1_RX_STAT_MSB 0x5d0
5601 #define A_PM1_RX_STAT_LSB 0x5d4
5602 #define A_PM1_RX_INT_ENABLE 0x5d8
5603 
5604 #define S_ZERO_E_CMD_ERROR    18
5605 #define V_ZERO_E_CMD_ERROR(x) ((x) << S_ZERO_E_CMD_ERROR)
5606 #define F_ZERO_E_CMD_ERROR    V_ZERO_E_CMD_ERROR(1U)
5607 
5608 #define S_IESPI0_FIFO2X_RX_FRAMING_ERROR    17
5609 #define V_IESPI0_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_IESPI0_FIFO2X_RX_FRAMING_ERROR)
5610 #define F_IESPI0_FIFO2X_RX_FRAMING_ERROR    V_IESPI0_FIFO2X_RX_FRAMING_ERROR(1U)
5611 
5612 #define S_IESPI1_FIFO2X_RX_FRAMING_ERROR    16
5613 #define V_IESPI1_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_IESPI1_FIFO2X_RX_FRAMING_ERROR)
5614 #define F_IESPI1_FIFO2X_RX_FRAMING_ERROR    V_IESPI1_FIFO2X_RX_FRAMING_ERROR(1U)
5615 
5616 #define S_IESPI0_RX_FRAMING_ERROR    15
5617 #define V_IESPI0_RX_FRAMING_ERROR(x) ((x) << S_IESPI0_RX_FRAMING_ERROR)
5618 #define F_IESPI0_RX_FRAMING_ERROR    V_IESPI0_RX_FRAMING_ERROR(1U)
5619 
5620 #define S_IESPI1_RX_FRAMING_ERROR    14
5621 #define V_IESPI1_RX_FRAMING_ERROR(x) ((x) << S_IESPI1_RX_FRAMING_ERROR)
5622 #define F_IESPI1_RX_FRAMING_ERROR    V_IESPI1_RX_FRAMING_ERROR(1U)
5623 
5624 #define S_IESPI0_TX_FRAMING_ERROR    13
5625 #define V_IESPI0_TX_FRAMING_ERROR(x) ((x) << S_IESPI0_TX_FRAMING_ERROR)
5626 #define F_IESPI0_TX_FRAMING_ERROR    V_IESPI0_TX_FRAMING_ERROR(1U)
5627 
5628 #define S_IESPI1_TX_FRAMING_ERROR    12
5629 #define V_IESPI1_TX_FRAMING_ERROR(x) ((x) << S_IESPI1_TX_FRAMING_ERROR)
5630 #define F_IESPI1_TX_FRAMING_ERROR    V_IESPI1_TX_FRAMING_ERROR(1U)
5631 
5632 #define S_OCSPI0_RX_FRAMING_ERROR    11
5633 #define V_OCSPI0_RX_FRAMING_ERROR(x) ((x) << S_OCSPI0_RX_FRAMING_ERROR)
5634 #define F_OCSPI0_RX_FRAMING_ERROR    V_OCSPI0_RX_FRAMING_ERROR(1U)
5635 
5636 #define S_OCSPI1_RX_FRAMING_ERROR    10
5637 #define V_OCSPI1_RX_FRAMING_ERROR(x) ((x) << S_OCSPI1_RX_FRAMING_ERROR)
5638 #define F_OCSPI1_RX_FRAMING_ERROR    V_OCSPI1_RX_FRAMING_ERROR(1U)
5639 
5640 #define S_OCSPI0_TX_FRAMING_ERROR    9
5641 #define V_OCSPI0_TX_FRAMING_ERROR(x) ((x) << S_OCSPI0_TX_FRAMING_ERROR)
5642 #define F_OCSPI0_TX_FRAMING_ERROR    V_OCSPI0_TX_FRAMING_ERROR(1U)
5643 
5644 #define S_OCSPI1_TX_FRAMING_ERROR    8
5645 #define V_OCSPI1_TX_FRAMING_ERROR(x) ((x) << S_OCSPI1_TX_FRAMING_ERROR)
5646 #define F_OCSPI1_TX_FRAMING_ERROR    V_OCSPI1_TX_FRAMING_ERROR(1U)
5647 
5648 #define S_OCSPI0_OFIFO2X_TX_FRAMING_ERROR    7
5649 #define V_OCSPI0_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OCSPI0_OFIFO2X_TX_FRAMING_ERROR)
5650 #define F_OCSPI0_OFIFO2X_TX_FRAMING_ERROR    V_OCSPI0_OFIFO2X_TX_FRAMING_ERROR(1U)
5651 
5652 #define S_OCSPI1_OFIFO2X_TX_FRAMING_ERROR    6
5653 #define V_OCSPI1_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OCSPI1_OFIFO2X_TX_FRAMING_ERROR)
5654 #define F_OCSPI1_OFIFO2X_TX_FRAMING_ERROR    V_OCSPI1_OFIFO2X_TX_FRAMING_ERROR(1U)
5655 
5656 #define S_IESPI_PAR_ERROR    3
5657 #define M_IESPI_PAR_ERROR    0x7
5658 #define V_IESPI_PAR_ERROR(x) ((x) << S_IESPI_PAR_ERROR)
5659 #define G_IESPI_PAR_ERROR(x) (((x) >> S_IESPI_PAR_ERROR) & M_IESPI_PAR_ERROR)
5660 
5661 #define S_OCSPI_PAR_ERROR    0
5662 #define M_OCSPI_PAR_ERROR    0x7
5663 #define V_OCSPI_PAR_ERROR(x) ((x) << S_OCSPI_PAR_ERROR)
5664 #define G_OCSPI_PAR_ERROR(x) (((x) >> S_OCSPI_PAR_ERROR) & M_OCSPI_PAR_ERROR)
5665 
5666 #define A_PM1_RX_INT_CAUSE 0x5dc
5667 
5668 /* registers for module PM1_TX */
5669 #define PM1_TX_BASE_ADDR 0x5e0
5670 
5671 #define A_PM1_TX_CFG 0x5e0
5672 #define A_PM1_TX_MODE 0x5e4
5673 #define A_PM1_TX_STAT_CONFIG 0x5e8
5674 #define A_PM1_TX_STAT_COUNT 0x5ec
5675 #define A_PM1_TX_STAT_MSB 0x5f0
5676 #define A_PM1_TX_STAT_LSB 0x5f4
5677 #define A_PM1_TX_INT_ENABLE 0x5f8
5678 
5679 #define S_ZERO_C_CMD_ERROR    18
5680 #define V_ZERO_C_CMD_ERROR(x) ((x) << S_ZERO_C_CMD_ERROR)
5681 #define F_ZERO_C_CMD_ERROR    V_ZERO_C_CMD_ERROR(1U)
5682 
5683 #define S_ICSPI0_FIFO2X_RX_FRAMING_ERROR    17
5684 #define V_ICSPI0_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_ICSPI0_FIFO2X_RX_FRAMING_ERROR)
5685 #define F_ICSPI0_FIFO2X_RX_FRAMING_ERROR    V_ICSPI0_FIFO2X_RX_FRAMING_ERROR(1U)
5686 
5687 #define S_ICSPI1_FIFO2X_RX_FRAMING_ERROR    16
5688 #define V_ICSPI1_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_ICSPI1_FIFO2X_RX_FRAMING_ERROR)
5689 #define F_ICSPI1_FIFO2X_RX_FRAMING_ERROR    V_ICSPI1_FIFO2X_RX_FRAMING_ERROR(1U)
5690 
5691 #define S_ICSPI0_RX_FRAMING_ERROR    15
5692 #define V_ICSPI0_RX_FRAMING_ERROR(x) ((x) << S_ICSPI0_RX_FRAMING_ERROR)
5693 #define F_ICSPI0_RX_FRAMING_ERROR    V_ICSPI0_RX_FRAMING_ERROR(1U)
5694 
5695 #define S_ICSPI1_RX_FRAMING_ERROR    14
5696 #define V_ICSPI1_RX_FRAMING_ERROR(x) ((x) << S_ICSPI1_RX_FRAMING_ERROR)
5697 #define F_ICSPI1_RX_FRAMING_ERROR    V_ICSPI1_RX_FRAMING_ERROR(1U)
5698 
5699 #define S_ICSPI0_TX_FRAMING_ERROR    13
5700 #define V_ICSPI0_TX_FRAMING_ERROR(x) ((x) << S_ICSPI0_TX_FRAMING_ERROR)
5701 #define F_ICSPI0_TX_FRAMING_ERROR    V_ICSPI0_TX_FRAMING_ERROR(1U)
5702 
5703 #define S_ICSPI1_TX_FRAMING_ERROR    12
5704 #define V_ICSPI1_TX_FRAMING_ERROR(x) ((x) << S_ICSPI1_TX_FRAMING_ERROR)
5705 #define F_ICSPI1_TX_FRAMING_ERROR    V_ICSPI1_TX_FRAMING_ERROR(1U)
5706 
5707 #define S_OESPI0_RX_FRAMING_ERROR    11
5708 #define V_OESPI0_RX_FRAMING_ERROR(x) ((x) << S_OESPI0_RX_FRAMING_ERROR)
5709 #define F_OESPI0_RX_FRAMING_ERROR    V_OESPI0_RX_FRAMING_ERROR(1U)
5710 
5711 #define S_OESPI1_RX_FRAMING_ERROR    10
5712 #define V_OESPI1_RX_FRAMING_ERROR(x) ((x) << S_OESPI1_RX_FRAMING_ERROR)
5713 #define F_OESPI1_RX_FRAMING_ERROR    V_OESPI1_RX_FRAMING_ERROR(1U)
5714 
5715 #define S_OESPI0_TX_FRAMING_ERROR    9
5716 #define V_OESPI0_TX_FRAMING_ERROR(x) ((x) << S_OESPI0_TX_FRAMING_ERROR)
5717 #define F_OESPI0_TX_FRAMING_ERROR    V_OESPI0_TX_FRAMING_ERROR(1U)
5718 
5719 #define S_OESPI1_TX_FRAMING_ERROR    8
5720 #define V_OESPI1_TX_FRAMING_ERROR(x) ((x) << S_OESPI1_TX_FRAMING_ERROR)
5721 #define F_OESPI1_TX_FRAMING_ERROR    V_OESPI1_TX_FRAMING_ERROR(1U)
5722 
5723 #define S_OESPI0_OFIFO2X_TX_FRAMING_ERROR    7
5724 #define V_OESPI0_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OESPI0_OFIFO2X_TX_FRAMING_ERROR)
5725 #define F_OESPI0_OFIFO2X_TX_FRAMING_ERROR    V_OESPI0_OFIFO2X_TX_FRAMING_ERROR(1U)
5726 
5727 #define S_OESPI1_OFIFO2X_TX_FRAMING_ERROR    6
5728 #define V_OESPI1_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OESPI1_OFIFO2X_TX_FRAMING_ERROR)
5729 #define F_OESPI1_OFIFO2X_TX_FRAMING_ERROR    V_OESPI1_OFIFO2X_TX_FRAMING_ERROR(1U)
5730 
5731 #define S_ICSPI_PAR_ERROR    3
5732 #define M_ICSPI_PAR_ERROR    0x7
5733 #define V_ICSPI_PAR_ERROR(x) ((x) << S_ICSPI_PAR_ERROR)
5734 #define G_ICSPI_PAR_ERROR(x) (((x) >> S_ICSPI_PAR_ERROR) & M_ICSPI_PAR_ERROR)
5735 
5736 #define S_OESPI_PAR_ERROR    0
5737 #define M_OESPI_PAR_ERROR    0x7
5738 #define V_OESPI_PAR_ERROR(x) ((x) << S_OESPI_PAR_ERROR)
5739 #define G_OESPI_PAR_ERROR(x) (((x) >> S_OESPI_PAR_ERROR) & M_OESPI_PAR_ERROR)
5740 
5741 #define A_PM1_TX_INT_CAUSE 0x5fc
5742 
5743 /* registers for module MPS0 */
5744 #define MPS0_BASE_ADDR 0x600
5745 
5746 #define A_MPS_CFG 0x600
5747 
5748 #define S_ENFORCEPKT    11
5749 #define V_ENFORCEPKT(x) ((x) << S_ENFORCEPKT)
5750 #define F_ENFORCEPKT    V_ENFORCEPKT(1U)
5751 
5752 #define S_SGETPQID    8
5753 #define M_SGETPQID    0x7
5754 #define V_SGETPQID(x) ((x) << S_SGETPQID)
5755 #define G_SGETPQID(x) (((x) >> S_SGETPQID) & M_SGETPQID)
5756 
5757 #define S_TPRXPORTSIZE    7
5758 #define V_TPRXPORTSIZE(x) ((x) << S_TPRXPORTSIZE)
5759 #define F_TPRXPORTSIZE    V_TPRXPORTSIZE(1U)
5760 
5761 #define S_TPTXPORT1SIZE    6
5762 #define V_TPTXPORT1SIZE(x) ((x) << S_TPTXPORT1SIZE)
5763 #define F_TPTXPORT1SIZE    V_TPTXPORT1SIZE(1U)
5764 
5765 #define S_TPTXPORT0SIZE    5
5766 #define V_TPTXPORT0SIZE(x) ((x) << S_TPTXPORT0SIZE)
5767 #define F_TPTXPORT0SIZE    V_TPTXPORT0SIZE(1U)
5768 
5769 #define S_TPRXPORTEN    4
5770 #define V_TPRXPORTEN(x) ((x) << S_TPRXPORTEN)
5771 #define F_TPRXPORTEN    V_TPRXPORTEN(1U)
5772 
5773 #define S_TPTXPORT1EN    3
5774 #define V_TPTXPORT1EN(x) ((x) << S_TPTXPORT1EN)
5775 #define F_TPTXPORT1EN    V_TPTXPORT1EN(1U)
5776 
5777 #define S_TPTXPORT0EN    2
5778 #define V_TPTXPORT0EN(x) ((x) << S_TPTXPORT0EN)
5779 #define F_TPTXPORT0EN    V_TPTXPORT0EN(1U)
5780 
5781 #define S_PORT1ACTIVE    1
5782 #define V_PORT1ACTIVE(x) ((x) << S_PORT1ACTIVE)
5783 #define F_PORT1ACTIVE    V_PORT1ACTIVE(1U)
5784 
5785 #define S_PORT0ACTIVE    0
5786 #define V_PORT0ACTIVE(x) ((x) << S_PORT0ACTIVE)
5787 #define F_PORT0ACTIVE    V_PORT0ACTIVE(1U)
5788 
5789 #define A_MPS_DRR_CFG1 0x604
5790 
5791 #define S_RLDWTTPD1    11
5792 #define M_RLDWTTPD1    0x7ff
5793 #define V_RLDWTTPD1(x) ((x) << S_RLDWTTPD1)
5794 #define G_RLDWTTPD1(x) (((x) >> S_RLDWTTPD1) & M_RLDWTTPD1)
5795 
5796 #define S_RLDWTTPD0    0
5797 #define M_RLDWTTPD0    0x7ff
5798 #define V_RLDWTTPD0(x) ((x) << S_RLDWTTPD0)
5799 #define G_RLDWTTPD0(x) (((x) >> S_RLDWTTPD0) & M_RLDWTTPD0)
5800 
5801 #define A_MPS_DRR_CFG2 0x608
5802 
5803 #define S_RLDWTTOTAL    0
5804 #define M_RLDWTTOTAL    0xfff
5805 #define V_RLDWTTOTAL(x) ((x) << S_RLDWTTOTAL)
5806 #define G_RLDWTTOTAL(x) (((x) >> S_RLDWTTOTAL) & M_RLDWTTOTAL)
5807 
5808 #define A_MPS_MCA_STATUS 0x60c
5809 
5810 #define S_MCAPKTCNT    12
5811 #define M_MCAPKTCNT    0xfffff
5812 #define V_MCAPKTCNT(x) ((x) << S_MCAPKTCNT)
5813 #define G_MCAPKTCNT(x) (((x) >> S_MCAPKTCNT) & M_MCAPKTCNT)
5814 
5815 #define S_MCADEPTH    0
5816 #define M_MCADEPTH    0xfff
5817 #define V_MCADEPTH(x) ((x) << S_MCADEPTH)
5818 #define G_MCADEPTH(x) (((x) >> S_MCADEPTH) & M_MCADEPTH)
5819 
5820 #define A_MPS_TX0_TP_CNT 0x610
5821 
5822 #define S_TX0TPDISCNT    24
5823 #define M_TX0TPDISCNT    0xff
5824 #define V_TX0TPDISCNT(x) ((x) << S_TX0TPDISCNT)
5825 #define G_TX0TPDISCNT(x) (((x) >> S_TX0TPDISCNT) & M_TX0TPDISCNT)
5826 
5827 #define S_TX0TPCNT    0
5828 #define M_TX0TPCNT    0xffffff
5829 #define V_TX0TPCNT(x) ((x) << S_TX0TPCNT)
5830 #define G_TX0TPCNT(x) (((x) >> S_TX0TPCNT) & M_TX0TPCNT)
5831 
5832 #define A_MPS_TX1_TP_CNT 0x614
5833 
5834 #define S_TX1TPDISCNT    24
5835 #define M_TX1TPDISCNT    0xff
5836 #define V_TX1TPDISCNT(x) ((x) << S_TX1TPDISCNT)
5837 #define G_TX1TPDISCNT(x) (((x) >> S_TX1TPDISCNT) & M_TX1TPDISCNT)
5838 
5839 #define S_TX1TPCNT    0
5840 #define M_TX1TPCNT    0xffffff
5841 #define V_TX1TPCNT(x) ((x) << S_TX1TPCNT)
5842 #define G_TX1TPCNT(x) (((x) >> S_TX1TPCNT) & M_TX1TPCNT)
5843 
5844 #define A_MPS_RX_TP_CNT 0x618
5845 
5846 #define S_RXTPDISCNT    24
5847 #define M_RXTPDISCNT    0xff
5848 #define V_RXTPDISCNT(x) ((x) << S_RXTPDISCNT)
5849 #define G_RXTPDISCNT(x) (((x) >> S_RXTPDISCNT) & M_RXTPDISCNT)
5850 
5851 #define S_RXTPCNT    0
5852 #define M_RXTPCNT    0xffffff
5853 #define V_RXTPCNT(x) ((x) << S_RXTPCNT)
5854 #define G_RXTPCNT(x) (((x) >> S_RXTPCNT) & M_RXTPCNT)
5855 
5856 #define A_MPS_INT_ENABLE 0x61c
5857 
5858 #define S_MCAPARERRENB    6
5859 #define M_MCAPARERRENB    0x7
5860 #define V_MCAPARERRENB(x) ((x) << S_MCAPARERRENB)
5861 #define G_MCAPARERRENB(x) (((x) >> S_MCAPARERRENB) & M_MCAPARERRENB)
5862 
5863 #define S_RXTPPARERRENB    4
5864 #define M_RXTPPARERRENB    0x3
5865 #define V_RXTPPARERRENB(x) ((x) << S_RXTPPARERRENB)
5866 #define G_RXTPPARERRENB(x) (((x) >> S_RXTPPARERRENB) & M_RXTPPARERRENB)
5867 
5868 #define S_TX1TPPARERRENB    2
5869 #define M_TX1TPPARERRENB    0x3
5870 #define V_TX1TPPARERRENB(x) ((x) << S_TX1TPPARERRENB)
5871 #define G_TX1TPPARERRENB(x) (((x) >> S_TX1TPPARERRENB) & M_TX1TPPARERRENB)
5872 
5873 #define S_TX0TPPARERRENB    0
5874 #define M_TX0TPPARERRENB    0x3
5875 #define V_TX0TPPARERRENB(x) ((x) << S_TX0TPPARERRENB)
5876 #define G_TX0TPPARERRENB(x) (((x) >> S_TX0TPPARERRENB) & M_TX0TPPARERRENB)
5877 
5878 #define A_MPS_INT_CAUSE 0x620
5879 
5880 #define S_MCAPARERR    6
5881 #define M_MCAPARERR    0x7
5882 #define V_MCAPARERR(x) ((x) << S_MCAPARERR)
5883 #define G_MCAPARERR(x) (((x) >> S_MCAPARERR) & M_MCAPARERR)
5884 
5885 #define S_RXTPPARERR    4
5886 #define M_RXTPPARERR    0x3
5887 #define V_RXTPPARERR(x) ((x) << S_RXTPPARERR)
5888 #define G_RXTPPARERR(x) (((x) >> S_RXTPPARERR) & M_RXTPPARERR)
5889 
5890 #define S_TX1TPPARERR    2
5891 #define M_TX1TPPARERR    0x3
5892 #define V_TX1TPPARERR(x) ((x) << S_TX1TPPARERR)
5893 #define G_TX1TPPARERR(x) (((x) >> S_TX1TPPARERR) & M_TX1TPPARERR)
5894 
5895 #define S_TX0TPPARERR    0
5896 #define M_TX0TPPARERR    0x3
5897 #define V_TX0TPPARERR(x) ((x) << S_TX0TPPARERR)
5898 #define G_TX0TPPARERR(x) (((x) >> S_TX0TPPARERR) & M_TX0TPPARERR)
5899 
5900 /* registers for module CPL_SWITCH */
5901 #define CPL_SWITCH_BASE_ADDR 0x640
5902 
5903 #define A_CPL_SWITCH_CNTRL 0x640
5904 
5905 #define S_CPL_PKT_TID    8
5906 #define M_CPL_PKT_TID    0xffffff
5907 #define V_CPL_PKT_TID(x) ((x) << S_CPL_PKT_TID)
5908 #define G_CPL_PKT_TID(x) (((x) >> S_CPL_PKT_TID) & M_CPL_PKT_TID)
5909 
5910 #define S_CIM_TO_UP_FULL_SIZE    4
5911 #define V_CIM_TO_UP_FULL_SIZE(x) ((x) << S_CIM_TO_UP_FULL_SIZE)
5912 #define F_CIM_TO_UP_FULL_SIZE    V_CIM_TO_UP_FULL_SIZE(1U)
5913 
5914 #define S_CPU_NO_3F_CIM_ENABLE    3
5915 #define V_CPU_NO_3F_CIM_ENABLE(x) ((x) << S_CPU_NO_3F_CIM_ENABLE)
5916 #define F_CPU_NO_3F_CIM_ENABLE    V_CPU_NO_3F_CIM_ENABLE(1U)
5917 
5918 #define S_SWITCH_TABLE_ENABLE    2
5919 #define V_SWITCH_TABLE_ENABLE(x) ((x) << S_SWITCH_TABLE_ENABLE)
5920 #define F_SWITCH_TABLE_ENABLE    V_SWITCH_TABLE_ENABLE(1U)
5921 
5922 #define S_SGE_ENABLE    1
5923 #define V_SGE_ENABLE(x) ((x) << S_SGE_ENABLE)
5924 #define F_SGE_ENABLE    V_SGE_ENABLE(1U)
5925 
5926 #define S_CIM_ENABLE    0
5927 #define V_CIM_ENABLE(x) ((x) << S_CIM_ENABLE)
5928 #define F_CIM_ENABLE    V_CIM_ENABLE(1U)
5929 
5930 #define A_CPL_SWITCH_TBL_IDX 0x644
5931 
5932 #define S_SWITCH_TBL_IDX    0
5933 #define M_SWITCH_TBL_IDX    0xf
5934 #define V_SWITCH_TBL_IDX(x) ((x) << S_SWITCH_TBL_IDX)
5935 #define G_SWITCH_TBL_IDX(x) (((x) >> S_SWITCH_TBL_IDX) & M_SWITCH_TBL_IDX)
5936 
5937 #define A_CPL_SWITCH_TBL_DATA 0x648
5938 #define A_CPL_SWITCH_ZERO_ERROR 0x64c
5939 
5940 #define S_ZERO_CMD    0
5941 #define M_ZERO_CMD    0xff
5942 #define V_ZERO_CMD(x) ((x) << S_ZERO_CMD)
5943 #define G_ZERO_CMD(x) (((x) >> S_ZERO_CMD) & M_ZERO_CMD)
5944 
5945 #define A_CPL_INTR_ENABLE 0x650
5946 
5947 #define S_CIM_OP_MAP_PERR    5
5948 #define V_CIM_OP_MAP_PERR(x) ((x) << S_CIM_OP_MAP_PERR)
5949 #define F_CIM_OP_MAP_PERR    V_CIM_OP_MAP_PERR(1U)
5950 
5951 #define S_CIM_OVFL_ERROR    4
5952 #define V_CIM_OVFL_ERROR(x) ((x) << S_CIM_OVFL_ERROR)
5953 #define F_CIM_OVFL_ERROR    V_CIM_OVFL_ERROR(1U)
5954 
5955 #define S_TP_FRAMING_ERROR    3
5956 #define V_TP_FRAMING_ERROR(x) ((x) << S_TP_FRAMING_ERROR)
5957 #define F_TP_FRAMING_ERROR    V_TP_FRAMING_ERROR(1U)
5958 
5959 #define S_SGE_FRAMING_ERROR    2
5960 #define V_SGE_FRAMING_ERROR(x) ((x) << S_SGE_FRAMING_ERROR)
5961 #define F_SGE_FRAMING_ERROR    V_SGE_FRAMING_ERROR(1U)
5962 
5963 #define S_CIM_FRAMING_ERROR    1
5964 #define V_CIM_FRAMING_ERROR(x) ((x) << S_CIM_FRAMING_ERROR)
5965 #define F_CIM_FRAMING_ERROR    V_CIM_FRAMING_ERROR(1U)
5966 
5967 #define S_ZERO_SWITCH_ERROR    0
5968 #define V_ZERO_SWITCH_ERROR(x) ((x) << S_ZERO_SWITCH_ERROR)
5969 #define F_ZERO_SWITCH_ERROR    V_ZERO_SWITCH_ERROR(1U)
5970 
5971 #define A_CPL_INTR_CAUSE 0x654
5972 #define A_CPL_MAP_TBL_IDX 0x658
5973 
5974 #define S_CPL_MAP_TBL_IDX    0
5975 #define M_CPL_MAP_TBL_IDX    0xff
5976 #define V_CPL_MAP_TBL_IDX(x) ((x) << S_CPL_MAP_TBL_IDX)
5977 #define G_CPL_MAP_TBL_IDX(x) (((x) >> S_CPL_MAP_TBL_IDX) & M_CPL_MAP_TBL_IDX)
5978 
5979 #define A_CPL_MAP_TBL_DATA 0x65c
5980 
5981 #define S_CPL_MAP_TBL_DATA    0
5982 #define M_CPL_MAP_TBL_DATA    0xff
5983 #define V_CPL_MAP_TBL_DATA(x) ((x) << S_CPL_MAP_TBL_DATA)
5984 #define G_CPL_MAP_TBL_DATA(x) (((x) >> S_CPL_MAP_TBL_DATA) & M_CPL_MAP_TBL_DATA)
5985 
5986 /* registers for module SMB0 */
5987 #define SMB0_BASE_ADDR 0x660
5988 
5989 #define A_SMB_GLOBAL_TIME_CFG 0x660
5990 
5991 #define S_LADBGWRPTR    24
5992 #define M_LADBGWRPTR    0xff
5993 #define V_LADBGWRPTR(x) ((x) << S_LADBGWRPTR)
5994 #define G_LADBGWRPTR(x) (((x) >> S_LADBGWRPTR) & M_LADBGWRPTR)
5995 
5996 #define S_LADBGRDPTR    16
5997 #define M_LADBGRDPTR    0xff
5998 #define V_LADBGRDPTR(x) ((x) << S_LADBGRDPTR)
5999 #define G_LADBGRDPTR(x) (((x) >> S_LADBGRDPTR) & M_LADBGRDPTR)
6000 
6001 #define S_LADBGEN    13
6002 #define V_LADBGEN(x) ((x) << S_LADBGEN)
6003 #define F_LADBGEN    V_LADBGEN(1U)
6004 
6005 #define S_MACROCNTCFG    8
6006 #define M_MACROCNTCFG    0x1f
6007 #define V_MACROCNTCFG(x) ((x) << S_MACROCNTCFG)
6008 #define G_MACROCNTCFG(x) (((x) >> S_MACROCNTCFG) & M_MACROCNTCFG)
6009 
6010 #define S_MICROCNTCFG    0
6011 #define M_MICROCNTCFG    0xff
6012 #define V_MICROCNTCFG(x) ((x) << S_MICROCNTCFG)
6013 #define G_MICROCNTCFG(x) (((x) >> S_MICROCNTCFG) & M_MICROCNTCFG)
6014 
6015 #define A_SMB_MST_TIMEOUT_CFG 0x664
6016 
6017 #define S_DEBUGSELH    28
6018 #define M_DEBUGSELH    0xf
6019 #define V_DEBUGSELH(x) ((x) << S_DEBUGSELH)
6020 #define G_DEBUGSELH(x) (((x) >> S_DEBUGSELH) & M_DEBUGSELH)
6021 
6022 #define S_DEBUGSELL    24
6023 #define M_DEBUGSELL    0xf
6024 #define V_DEBUGSELL(x) ((x) << S_DEBUGSELL)
6025 #define G_DEBUGSELL(x) (((x) >> S_DEBUGSELL) & M_DEBUGSELL)
6026 
6027 #define S_MSTTIMEOUTCFG    0
6028 #define M_MSTTIMEOUTCFG    0xffffff
6029 #define V_MSTTIMEOUTCFG(x) ((x) << S_MSTTIMEOUTCFG)
6030 #define G_MSTTIMEOUTCFG(x) (((x) >> S_MSTTIMEOUTCFG) & M_MSTTIMEOUTCFG)
6031 
6032 #define A_SMB_MST_CTL_CFG 0x668
6033 
6034 #define S_MSTFIFODBG    31
6035 #define V_MSTFIFODBG(x) ((x) << S_MSTFIFODBG)
6036 #define F_MSTFIFODBG    V_MSTFIFODBG(1U)
6037 
6038 #define S_MSTFIFODBGCLR    30
6039 #define V_MSTFIFODBGCLR(x) ((x) << S_MSTFIFODBGCLR)
6040 #define F_MSTFIFODBGCLR    V_MSTFIFODBGCLR(1U)
6041 
6042 #define S_MSTRXBYTECFG    12
6043 #define M_MSTRXBYTECFG    0x3f
6044 #define V_MSTRXBYTECFG(x) ((x) << S_MSTRXBYTECFG)
6045 #define G_MSTRXBYTECFG(x) (((x) >> S_MSTRXBYTECFG) & M_MSTRXBYTECFG)
6046 
6047 #define S_MSTTXBYTECFG    6
6048 #define M_MSTTXBYTECFG    0x3f
6049 #define V_MSTTXBYTECFG(x) ((x) << S_MSTTXBYTECFG)
6050 #define G_MSTTXBYTECFG(x) (((x) >> S_MSTTXBYTECFG) & M_MSTTXBYTECFG)
6051 
6052 #define S_MSTRESET    1
6053 #define V_MSTRESET(x) ((x) << S_MSTRESET)
6054 #define F_MSTRESET    V_MSTRESET(1U)
6055 
6056 #define S_MSTCTLEN    0
6057 #define V_MSTCTLEN(x) ((x) << S_MSTCTLEN)
6058 #define F_MSTCTLEN    V_MSTCTLEN(1U)
6059 
6060 #define A_SMB_MST_CTL_STS 0x66c
6061 
6062 #define S_MSTRXBYTECNT    12
6063 #define M_MSTRXBYTECNT    0x3f
6064 #define V_MSTRXBYTECNT(x) ((x) << S_MSTRXBYTECNT)
6065 #define G_MSTRXBYTECNT(x) (((x) >> S_MSTRXBYTECNT) & M_MSTRXBYTECNT)
6066 
6067 #define S_MSTTXBYTECNT    6
6068 #define M_MSTTXBYTECNT    0x3f
6069 #define V_MSTTXBYTECNT(x) ((x) << S_MSTTXBYTECNT)
6070 #define G_MSTTXBYTECNT(x) (((x) >> S_MSTTXBYTECNT) & M_MSTTXBYTECNT)
6071 
6072 #define S_MSTBUSYSTS    0
6073 #define V_MSTBUSYSTS(x) ((x) << S_MSTBUSYSTS)
6074 #define F_MSTBUSYSTS    V_MSTBUSYSTS(1U)
6075 
6076 #define A_SMB_MST_TX_FIFO_RDWR 0x670
6077 #define A_SMB_MST_RX_FIFO_RDWR 0x674
6078 #define A_SMB_SLV_TIMEOUT_CFG 0x678
6079 
6080 #define S_SLVTIMEOUTCFG    0
6081 #define M_SLVTIMEOUTCFG    0xffffff
6082 #define V_SLVTIMEOUTCFG(x) ((x) << S_SLVTIMEOUTCFG)
6083 #define G_SLVTIMEOUTCFG(x) (((x) >> S_SLVTIMEOUTCFG) & M_SLVTIMEOUTCFG)
6084 
6085 #define A_SMB_SLV_CTL_CFG 0x67c
6086 
6087 #define S_SLVFIFODBG    31
6088 #define V_SLVFIFODBG(x) ((x) << S_SLVFIFODBG)
6089 #define F_SLVFIFODBG    V_SLVFIFODBG(1U)
6090 
6091 #define S_SLVFIFODBGCLR    30
6092 #define V_SLVFIFODBGCLR(x) ((x) << S_SLVFIFODBGCLR)
6093 #define F_SLVFIFODBGCLR    V_SLVFIFODBGCLR(1U)
6094 
6095 #define S_SLVADDRCFG    4
6096 #define M_SLVADDRCFG    0x7f
6097 #define V_SLVADDRCFG(x) ((x) << S_SLVADDRCFG)
6098 #define G_SLVADDRCFG(x) (((x) >> S_SLVADDRCFG) & M_SLVADDRCFG)
6099 
6100 #define S_SLVALRTSET    2
6101 #define V_SLVALRTSET(x) ((x) << S_SLVALRTSET)
6102 #define F_SLVALRTSET    V_SLVALRTSET(1U)
6103 
6104 #define S_SLVRESET    1
6105 #define V_SLVRESET(x) ((x) << S_SLVRESET)
6106 #define F_SLVRESET    V_SLVRESET(1U)
6107 
6108 #define S_SLVCTLEN    0
6109 #define V_SLVCTLEN(x) ((x) << S_SLVCTLEN)
6110 #define F_SLVCTLEN    V_SLVCTLEN(1U)
6111 
6112 #define A_SMB_SLV_CTL_STS 0x680
6113 
6114 #define S_SLVFIFOTXCNT    12
6115 #define M_SLVFIFOTXCNT    0x3f
6116 #define V_SLVFIFOTXCNT(x) ((x) << S_SLVFIFOTXCNT)
6117 #define G_SLVFIFOTXCNT(x) (((x) >> S_SLVFIFOTXCNT) & M_SLVFIFOTXCNT)
6118 
6119 #define S_SLVFIFOCNT    6
6120 #define M_SLVFIFOCNT    0x3f
6121 #define V_SLVFIFOCNT(x) ((x) << S_SLVFIFOCNT)
6122 #define G_SLVFIFOCNT(x) (((x) >> S_SLVFIFOCNT) & M_SLVFIFOCNT)
6123 
6124 #define S_SLVALRTSTS    2
6125 #define V_SLVALRTSTS(x) ((x) << S_SLVALRTSTS)
6126 #define F_SLVALRTSTS    V_SLVALRTSTS(1U)
6127 
6128 #define S_SLVBUSYSTS    0
6129 #define V_SLVBUSYSTS(x) ((x) << S_SLVBUSYSTS)
6130 #define F_SLVBUSYSTS    V_SLVBUSYSTS(1U)
6131 
6132 #define A_SMB_SLV_FIFO_RDWR 0x684
6133 #define A_SMB_SLV_CMD_FIFO_RDWR 0x688
6134 #define A_SMB_INT_ENABLE 0x68c
6135 
6136 #define S_SLVTIMEOUTINTEN    7
6137 #define V_SLVTIMEOUTINTEN(x) ((x) << S_SLVTIMEOUTINTEN)
6138 #define F_SLVTIMEOUTINTEN    V_SLVTIMEOUTINTEN(1U)
6139 
6140 #define S_SLVERRINTEN    6
6141 #define V_SLVERRINTEN(x) ((x) << S_SLVERRINTEN)
6142 #define F_SLVERRINTEN    V_SLVERRINTEN(1U)
6143 
6144 #define S_SLVDONEINTEN    5
6145 #define V_SLVDONEINTEN(x) ((x) << S_SLVDONEINTEN)
6146 #define F_SLVDONEINTEN    V_SLVDONEINTEN(1U)
6147 
6148 #define S_SLVRXRDYINTEN    4
6149 #define V_SLVRXRDYINTEN(x) ((x) << S_SLVRXRDYINTEN)
6150 #define F_SLVRXRDYINTEN    V_SLVRXRDYINTEN(1U)
6151 
6152 #define S_MSTTIMEOUTINTEN    3
6153 #define V_MSTTIMEOUTINTEN(x) ((x) << S_MSTTIMEOUTINTEN)
6154 #define F_MSTTIMEOUTINTEN    V_MSTTIMEOUTINTEN(1U)
6155 
6156 #define S_MSTNACKINTEN    2
6157 #define V_MSTNACKINTEN(x) ((x) << S_MSTNACKINTEN)
6158 #define F_MSTNACKINTEN    V_MSTNACKINTEN(1U)
6159 
6160 #define S_MSTLOSTARBINTEN    1
6161 #define V_MSTLOSTARBINTEN(x) ((x) << S_MSTLOSTARBINTEN)
6162 #define F_MSTLOSTARBINTEN    V_MSTLOSTARBINTEN(1U)
6163 
6164 #define S_MSTDONEINTEN    0
6165 #define V_MSTDONEINTEN(x) ((x) << S_MSTDONEINTEN)
6166 #define F_MSTDONEINTEN    V_MSTDONEINTEN(1U)
6167 
6168 #define A_SMB_INT_CAUSE 0x690
6169 
6170 #define S_SLVTIMEOUTINT    7
6171 #define V_SLVTIMEOUTINT(x) ((x) << S_SLVTIMEOUTINT)
6172 #define F_SLVTIMEOUTINT    V_SLVTIMEOUTINT(1U)
6173 
6174 #define S_SLVERRINT    6
6175 #define V_SLVERRINT(x) ((x) << S_SLVERRINT)
6176 #define F_SLVERRINT    V_SLVERRINT(1U)
6177 
6178 #define S_SLVDONEINT    5
6179 #define V_SLVDONEINT(x) ((x) << S_SLVDONEINT)
6180 #define F_SLVDONEINT    V_SLVDONEINT(1U)
6181 
6182 #define S_SLVRXRDYINT    4
6183 #define V_SLVRXRDYINT(x) ((x) << S_SLVRXRDYINT)
6184 #define F_SLVRXRDYINT    V_SLVRXRDYINT(1U)
6185 
6186 #define S_MSTTIMEOUTINT    3
6187 #define V_MSTTIMEOUTINT(x) ((x) << S_MSTTIMEOUTINT)
6188 #define F_MSTTIMEOUTINT    V_MSTTIMEOUTINT(1U)
6189 
6190 #define S_MSTNACKINT    2
6191 #define V_MSTNACKINT(x) ((x) << S_MSTNACKINT)
6192 #define F_MSTNACKINT    V_MSTNACKINT(1U)
6193 
6194 #define S_MSTLOSTARBINT    1
6195 #define V_MSTLOSTARBINT(x) ((x) << S_MSTLOSTARBINT)
6196 #define F_MSTLOSTARBINT    V_MSTLOSTARBINT(1U)
6197 
6198 #define S_MSTDONEINT    0
6199 #define V_MSTDONEINT(x) ((x) << S_MSTDONEINT)
6200 #define F_MSTDONEINT    V_MSTDONEINT(1U)
6201 
6202 #define A_SMB_DEBUG_DATA 0x694
6203 
6204 #define S_DEBUGDATAH    16
6205 #define M_DEBUGDATAH    0xffff
6206 #define V_DEBUGDATAH(x) ((x) << S_DEBUGDATAH)
6207 #define G_DEBUGDATAH(x) (((x) >> S_DEBUGDATAH) & M_DEBUGDATAH)
6208 
6209 #define S_DEBUGDATAL    0
6210 #define M_DEBUGDATAL    0xffff
6211 #define V_DEBUGDATAL(x) ((x) << S_DEBUGDATAL)
6212 #define G_DEBUGDATAL(x) (((x) >> S_DEBUGDATAL) & M_DEBUGDATAL)
6213 
6214 #define A_SMB_DEBUG_LA 0x69c
6215 
6216 #define S_DEBUGLAREQADDR    0
6217 #define M_DEBUGLAREQADDR    0x3ff
6218 #define V_DEBUGLAREQADDR(x) ((x) << S_DEBUGLAREQADDR)
6219 #define G_DEBUGLAREQADDR(x) (((x) >> S_DEBUGLAREQADDR) & M_DEBUGLAREQADDR)
6220 
6221 /* registers for module I2CM0 */
6222 #define I2CM0_BASE_ADDR 0x6a0
6223 
6224 #define A_I2C_CFG 0x6a0
6225 
6226 #define S_I2C_CLKDIV    0
6227 #define M_I2C_CLKDIV    0xfff
6228 #define V_I2C_CLKDIV(x) ((x) << S_I2C_CLKDIV)
6229 #define G_I2C_CLKDIV(x) (((x) >> S_I2C_CLKDIV) & M_I2C_CLKDIV)
6230 
6231 #define A_I2C_DATA 0x6a4
6232 #define A_I2C_OP 0x6a8
6233 
6234 #define S_ACK    30
6235 #define V_ACK(x) ((x) << S_ACK)
6236 #define F_ACK    V_ACK(1U)
6237 
6238 #define S_I2C_CONT    1
6239 #define V_I2C_CONT(x) ((x) << S_I2C_CONT)
6240 #define F_I2C_CONT    V_I2C_CONT(1U)
6241 
6242 /* registers for module MI1 */
6243 #define MI1_BASE_ADDR 0x6b0
6244 
6245 #define A_MI1_CFG 0x6b0
6246 
6247 #define S_CLKDIV    5
6248 #define M_CLKDIV    0xff
6249 #define V_CLKDIV(x) ((x) << S_CLKDIV)
6250 #define G_CLKDIV(x) (((x) >> S_CLKDIV) & M_CLKDIV)
6251 
6252 #define S_ST    3
6253 #define M_ST    0x3
6254 #define V_ST(x) ((x) << S_ST)
6255 #define G_ST(x) (((x) >> S_ST) & M_ST)
6256 
6257 #define S_PREEN    2
6258 #define V_PREEN(x) ((x) << S_PREEN)
6259 #define F_PREEN    V_PREEN(1U)
6260 
6261 #define S_MDIINV    1
6262 #define V_MDIINV(x) ((x) << S_MDIINV)
6263 #define F_MDIINV    V_MDIINV(1U)
6264 
6265 #define S_MDIEN    0
6266 #define V_MDIEN(x) ((x) << S_MDIEN)
6267 #define F_MDIEN    V_MDIEN(1U)
6268 
6269 #define A_MI1_ADDR 0x6b4
6270 
6271 #define S_PHYADDR    5
6272 #define M_PHYADDR    0x1f
6273 #define V_PHYADDR(x) ((x) << S_PHYADDR)
6274 #define G_PHYADDR(x) (((x) >> S_PHYADDR) & M_PHYADDR)
6275 
6276 #define S_REGADDR    0
6277 #define M_REGADDR    0x1f
6278 #define V_REGADDR(x) ((x) << S_REGADDR)
6279 #define G_REGADDR(x) (((x) >> S_REGADDR) & M_REGADDR)
6280 
6281 #define A_MI1_DATA 0x6b8
6282 
6283 #define S_MDI_DATA    0
6284 #define M_MDI_DATA    0xffff
6285 #define V_MDI_DATA(x) ((x) << S_MDI_DATA)
6286 #define G_MDI_DATA(x) (((x) >> S_MDI_DATA) & M_MDI_DATA)
6287 
6288 #define A_MI1_OP 0x6bc
6289 
6290 #define S_INC    2
6291 #define V_INC(x) ((x) << S_INC)
6292 #define F_INC    V_INC(1U)
6293 
6294 #define S_MDI_OP    0
6295 #define M_MDI_OP    0x3
6296 #define V_MDI_OP(x) ((x) << S_MDI_OP)
6297 #define G_MDI_OP(x) (((x) >> S_MDI_OP) & M_MDI_OP)
6298 
6299 /* registers for module JM1 */
6300 #define JM1_BASE_ADDR 0x6c0
6301 
6302 #define A_JM_CFG 0x6c0
6303 
6304 #define S_JM_CLKDIV    2
6305 #define M_JM_CLKDIV    0xff
6306 #define V_JM_CLKDIV(x) ((x) << S_JM_CLKDIV)
6307 #define G_JM_CLKDIV(x) (((x) >> S_JM_CLKDIV) & M_JM_CLKDIV)
6308 
6309 #define S_TRST    1
6310 #define V_TRST(x) ((x) << S_TRST)
6311 #define F_TRST    V_TRST(1U)
6312 
6313 #define S_EN    0
6314 #define V_EN(x) ((x) << S_EN)
6315 #define F_EN    V_EN(1U)
6316 
6317 #define A_JM_MODE 0x6c4
6318 #define A_JM_DATA 0x6c8
6319 #define A_JM_OP 0x6cc
6320 
6321 #define S_CNT    0
6322 #define M_CNT    0x1f
6323 #define V_CNT(x) ((x) << S_CNT)
6324 #define G_CNT(x) (((x) >> S_CNT) & M_CNT)
6325 
6326 /* registers for module SF1 */
6327 #define SF1_BASE_ADDR 0x6d8
6328 
6329 #define A_SF_DATA 0x6d8
6330 #define A_SF_OP 0x6dc
6331 
6332 #define S_BYTECNT    1
6333 #define M_BYTECNT    0x3
6334 #define V_BYTECNT(x) ((x) << S_BYTECNT)
6335 #define G_BYTECNT(x) (((x) >> S_BYTECNT) & M_BYTECNT)
6336 
6337 /* registers for module PL3 */
6338 #define PL3_BASE_ADDR 0x6e0
6339 
6340 #define A_PL_INT_ENABLE0 0x6e0
6341 
6342 #define S_SW    25
6343 #define V_SW(x) ((x) << S_SW)
6344 #define F_SW    V_SW(1U)
6345 
6346 #define S_EXT    24
6347 #define V_EXT(x) ((x) << S_EXT)
6348 #define F_EXT    V_EXT(1U)
6349 
6350 #define S_T3DBG    23
6351 #define V_T3DBG(x) ((x) << S_T3DBG)
6352 #define F_T3DBG    V_T3DBG(1U)
6353 
6354 #define S_XGMAC0_1    20
6355 #define V_XGMAC0_1(x) ((x) << S_XGMAC0_1)
6356 #define F_XGMAC0_1    V_XGMAC0_1(1U)
6357 
6358 #define S_XGMAC0_0    19
6359 #define V_XGMAC0_0(x) ((x) << S_XGMAC0_0)
6360 #define F_XGMAC0_0    V_XGMAC0_0(1U)
6361 
6362 #define S_MC5A    18
6363 #define V_MC5A(x) ((x) << S_MC5A)
6364 #define F_MC5A    V_MC5A(1U)
6365 
6366 #define S_SF1    17
6367 #define V_SF1(x) ((x) << S_SF1)
6368 #define F_SF1    V_SF1(1U)
6369 
6370 #define S_SMB0    15
6371 #define V_SMB0(x) ((x) << S_SMB0)
6372 #define F_SMB0    V_SMB0(1U)
6373 
6374 #define S_I2CM0    14
6375 #define V_I2CM0(x) ((x) << S_I2CM0)
6376 #define F_I2CM0    V_I2CM0(1U)
6377 
6378 #define S_MI1    13
6379 #define V_MI1(x) ((x) << S_MI1)
6380 #define F_MI1    V_MI1(1U)
6381 
6382 #define S_CPL_SWITCH    12
6383 #define V_CPL_SWITCH(x) ((x) << S_CPL_SWITCH)
6384 #define F_CPL_SWITCH    V_CPL_SWITCH(1U)
6385 
6386 #define S_MPS0    11
6387 #define V_MPS0(x) ((x) << S_MPS0)
6388 #define F_MPS0    V_MPS0(1U)
6389 
6390 #define S_PM1_TX    10
6391 #define V_PM1_TX(x) ((x) << S_PM1_TX)
6392 #define F_PM1_TX    V_PM1_TX(1U)
6393 
6394 #define S_PM1_RX    9
6395 #define V_PM1_RX(x) ((x) << S_PM1_RX)
6396 #define F_PM1_RX    V_PM1_RX(1U)
6397 
6398 #define S_ULP2_TX    8
6399 #define V_ULP2_TX(x) ((x) << S_ULP2_TX)
6400 #define F_ULP2_TX    V_ULP2_TX(1U)
6401 
6402 #define S_ULP2_RX    7
6403 #define V_ULP2_RX(x) ((x) << S_ULP2_RX)
6404 #define F_ULP2_RX    V_ULP2_RX(1U)
6405 
6406 #define S_TP1    6
6407 #define V_TP1(x) ((x) << S_TP1)
6408 #define F_TP1    V_TP1(1U)
6409 
6410 #define S_CIM    5
6411 #define V_CIM(x) ((x) << S_CIM)
6412 #define F_CIM    V_CIM(1U)
6413 
6414 #define S_MC7_CM    4
6415 #define V_MC7_CM(x) ((x) << S_MC7_CM)
6416 #define F_MC7_CM    V_MC7_CM(1U)
6417 
6418 #define S_MC7_PMTX    3
6419 #define V_MC7_PMTX(x) ((x) << S_MC7_PMTX)
6420 #define F_MC7_PMTX    V_MC7_PMTX(1U)
6421 
6422 #define S_MC7_PMRX    2
6423 #define V_MC7_PMRX(x) ((x) << S_MC7_PMRX)
6424 #define F_MC7_PMRX    V_MC7_PMRX(1U)
6425 
6426 #define S_PCIM0    1
6427 #define V_PCIM0(x) ((x) << S_PCIM0)
6428 #define F_PCIM0    V_PCIM0(1U)
6429 
6430 #define S_SGE3    0
6431 #define V_SGE3(x) ((x) << S_SGE3)
6432 #define F_SGE3    V_SGE3(1U)
6433 
6434 #define A_PL_INT_CAUSE0 0x6e4
6435 #define A_PL_INT_ENABLE1 0x6e8
6436 #define A_PL_INT_CAUSE1 0x6ec
6437 #define A_PL_RST 0x6f0
6438 
6439 #define S_FATALPERREN    4
6440 #define V_FATALPERREN(x) ((x) << S_FATALPERREN)
6441 #define F_FATALPERREN    V_FATALPERREN(1U)
6442 
6443 #define S_SWINT1    3
6444 #define V_SWINT1(x) ((x) << S_SWINT1)
6445 #define F_SWINT1    V_SWINT1(1U)
6446 
6447 #define S_SWINT0    2
6448 #define V_SWINT0(x) ((x) << S_SWINT0)
6449 #define F_SWINT0    V_SWINT0(1U)
6450 
6451 #define S_CRSTWRM    1
6452 #define V_CRSTWRM(x) ((x) << S_CRSTWRM)
6453 #define F_CRSTWRM    V_CRSTWRM(1U)
6454 
6455 #define A_PL_REV 0x6f4
6456 
6457 #define S_REV    0
6458 #define M_REV    0xf
6459 #define V_REV(x) ((x) << S_REV)
6460 #define G_REV(x) (((x) >> S_REV) & M_REV)
6461 
6462 #define A_PL_CLI 0x6f8
6463 #define A_PL_LCK 0x6fc
6464 
6465 #define S_LCK    0
6466 #define M_LCK    0x3
6467 #define V_LCK(x) ((x) << S_LCK)
6468 #define G_LCK(x) (((x) >> S_LCK) & M_LCK)
6469 
6470 /* registers for module MC5A */
6471 #define MC5A_BASE_ADDR 0x700
6472 
6473 #define A_MC5_BUF_CONFIG 0x700
6474 
6475 #define S_TERM300_240    31
6476 #define V_TERM300_240(x) ((x) << S_TERM300_240)
6477 #define F_TERM300_240    V_TERM300_240(1U)
6478 
6479 #define S_MC5_TERM150    30
6480 #define V_MC5_TERM150(x) ((x) << S_MC5_TERM150)
6481 #define F_MC5_TERM150    V_MC5_TERM150(1U)
6482 
6483 #define S_TERM60    29
6484 #define V_TERM60(x) ((x) << S_TERM60)
6485 #define F_TERM60    V_TERM60(1U)
6486 
6487 #define S_GDDRIII    28
6488 #define V_GDDRIII(x) ((x) << S_GDDRIII)
6489 #define F_GDDRIII    V_GDDRIII(1U)
6490 
6491 #define S_GDDRII    27
6492 #define V_GDDRII(x) ((x) << S_GDDRII)
6493 #define F_GDDRII    V_GDDRII(1U)
6494 
6495 #define S_GDDRI    26
6496 #define V_GDDRI(x) ((x) << S_GDDRI)
6497 #define F_GDDRI    V_GDDRI(1U)
6498 
6499 #define S_READ    25
6500 #define V_READ(x) ((x) << S_READ)
6501 #define F_READ    V_READ(1U)
6502 
6503 #define S_IMP_SET_UPDATE    24
6504 #define V_IMP_SET_UPDATE(x) ((x) << S_IMP_SET_UPDATE)
6505 #define F_IMP_SET_UPDATE    V_IMP_SET_UPDATE(1U)
6506 
6507 #define S_CAL_UPDATE    23
6508 #define V_CAL_UPDATE(x) ((x) << S_CAL_UPDATE)
6509 #define F_CAL_UPDATE    V_CAL_UPDATE(1U)
6510 
6511 #define S_CAL_BUSY    22
6512 #define V_CAL_BUSY(x) ((x) << S_CAL_BUSY)
6513 #define F_CAL_BUSY    V_CAL_BUSY(1U)
6514 
6515 #define S_CAL_ERROR    21
6516 #define V_CAL_ERROR(x) ((x) << S_CAL_ERROR)
6517 #define F_CAL_ERROR    V_CAL_ERROR(1U)
6518 
6519 #define S_SGL_CAL_EN    20
6520 #define V_SGL_CAL_EN(x) ((x) << S_SGL_CAL_EN)
6521 #define F_SGL_CAL_EN    V_SGL_CAL_EN(1U)
6522 
6523 #define S_IMP_UPD_MODE    19
6524 #define V_IMP_UPD_MODE(x) ((x) << S_IMP_UPD_MODE)
6525 #define F_IMP_UPD_MODE    V_IMP_UPD_MODE(1U)
6526 
6527 #define S_IMP_SEL    18
6528 #define V_IMP_SEL(x) ((x) << S_IMP_SEL)
6529 #define F_IMP_SEL    V_IMP_SEL(1U)
6530 
6531 #define S_MAN_PU    15
6532 #define M_MAN_PU    0x7
6533 #define V_MAN_PU(x) ((x) << S_MAN_PU)
6534 #define G_MAN_PU(x) (((x) >> S_MAN_PU) & M_MAN_PU)
6535 
6536 #define S_MAN_PD    12
6537 #define M_MAN_PD    0x7
6538 #define V_MAN_PD(x) ((x) << S_MAN_PD)
6539 #define G_MAN_PD(x) (((x) >> S_MAN_PD) & M_MAN_PD)
6540 
6541 #define S_CAL_PU    9
6542 #define M_CAL_PU    0x7
6543 #define V_CAL_PU(x) ((x) << S_CAL_PU)
6544 #define G_CAL_PU(x) (((x) >> S_CAL_PU) & M_CAL_PU)
6545 
6546 #define S_CAL_PD    6
6547 #define M_CAL_PD    0x7
6548 #define V_CAL_PD(x) ((x) << S_CAL_PD)
6549 #define G_CAL_PD(x) (((x) >> S_CAL_PD) & M_CAL_PD)
6550 
6551 #define S_SET_PU    3
6552 #define M_SET_PU    0x7
6553 #define V_SET_PU(x) ((x) << S_SET_PU)
6554 #define G_SET_PU(x) (((x) >> S_SET_PU) & M_SET_PU)
6555 
6556 #define S_SET_PD    0
6557 #define M_SET_PD    0x7
6558 #define V_SET_PD(x) ((x) << S_SET_PD)
6559 #define G_SET_PD(x) (((x) >> S_SET_PD) & M_SET_PD)
6560 
6561 #define S_CAL_IMP_UPD    23
6562 #define V_CAL_IMP_UPD(x) ((x) << S_CAL_IMP_UPD)
6563 #define F_CAL_IMP_UPD    V_CAL_IMP_UPD(1U)
6564 
6565 #define A_MC5_DB_CONFIG 0x704
6566 
6567 #define S_TMCFGWRLOCK    31
6568 #define V_TMCFGWRLOCK(x) ((x) << S_TMCFGWRLOCK)
6569 #define F_TMCFGWRLOCK    V_TMCFGWRLOCK(1U)
6570 
6571 #define S_TMTYPEHI    30
6572 #define V_TMTYPEHI(x) ((x) << S_TMTYPEHI)
6573 #define F_TMTYPEHI    V_TMTYPEHI(1U)
6574 
6575 #define S_TMPARTSIZE    28
6576 #define M_TMPARTSIZE    0x3
6577 #define V_TMPARTSIZE(x) ((x) << S_TMPARTSIZE)
6578 #define G_TMPARTSIZE(x) (((x) >> S_TMPARTSIZE) & M_TMPARTSIZE)
6579 
6580 #define S_TMTYPE    26
6581 #define M_TMTYPE    0x3
6582 #define V_TMTYPE(x) ((x) << S_TMTYPE)
6583 #define G_TMTYPE(x) (((x) >> S_TMTYPE) & M_TMTYPE)
6584 
6585 #define S_TMPARTCOUNT    24
6586 #define M_TMPARTCOUNT    0x3
6587 #define V_TMPARTCOUNT(x) ((x) << S_TMPARTCOUNT)
6588 #define G_TMPARTCOUNT(x) (((x) >> S_TMPARTCOUNT) & M_TMPARTCOUNT)
6589 
6590 #define S_NLIP    18
6591 #define M_NLIP    0x3f
6592 #define V_NLIP(x) ((x) << S_NLIP)
6593 #define G_NLIP(x) (((x) >> S_NLIP) & M_NLIP)
6594 
6595 #define S_COMPEN    17
6596 #define V_COMPEN(x) ((x) << S_COMPEN)
6597 #define F_COMPEN    V_COMPEN(1U)
6598 
6599 #define S_BUILD    16
6600 #define V_BUILD(x) ((x) << S_BUILD)
6601 #define F_BUILD    V_BUILD(1U)
6602 
6603 #define S_FILTEREN    11
6604 #define V_FILTEREN(x) ((x) << S_FILTEREN)
6605 #define F_FILTEREN    V_FILTEREN(1U)
6606 
6607 #define S_CLIPUPDATE    10
6608 #define V_CLIPUPDATE(x) ((x) << S_CLIPUPDATE)
6609 #define F_CLIPUPDATE    V_CLIPUPDATE(1U)
6610 
6611 #define S_TM_IO_PDOWN    9
6612 #define V_TM_IO_PDOWN(x) ((x) << S_TM_IO_PDOWN)
6613 #define F_TM_IO_PDOWN    V_TM_IO_PDOWN(1U)
6614 
6615 #define S_SYNMODE    7
6616 #define M_SYNMODE    0x3
6617 #define V_SYNMODE(x) ((x) << S_SYNMODE)
6618 #define G_SYNMODE(x) (((x) >> S_SYNMODE) & M_SYNMODE)
6619 
6620 #define S_PRTYEN    6
6621 #define V_PRTYEN(x) ((x) << S_PRTYEN)
6622 #define F_PRTYEN    V_PRTYEN(1U)
6623 
6624 #define S_MBUSEN    5
6625 #define V_MBUSEN(x) ((x) << S_MBUSEN)
6626 #define F_MBUSEN    V_MBUSEN(1U)
6627 
6628 #define S_DBGIEN    4
6629 #define V_DBGIEN(x) ((x) << S_DBGIEN)
6630 #define F_DBGIEN    V_DBGIEN(1U)
6631 
6632 #define S_TCMCFGOVR    3
6633 #define V_TCMCFGOVR(x) ((x) << S_TCMCFGOVR)
6634 #define F_TCMCFGOVR    V_TCMCFGOVR(1U)
6635 
6636 #define S_TMRDY    2
6637 #define V_TMRDY(x) ((x) << S_TMRDY)
6638 #define F_TMRDY    V_TMRDY(1U)
6639 
6640 #define S_TMRST    1
6641 #define V_TMRST(x) ((x) << S_TMRST)
6642 #define F_TMRST    V_TMRST(1U)
6643 
6644 #define S_TMMODE    0
6645 #define V_TMMODE(x) ((x) << S_TMMODE)
6646 #define F_TMMODE    V_TMMODE(1U)
6647 
6648 #define A_MC5_MISC 0x708
6649 
6650 #define S_LIP_CMP_UNAVAILABLE    0
6651 #define M_LIP_CMP_UNAVAILABLE    0xf
6652 #define V_LIP_CMP_UNAVAILABLE(x) ((x) << S_LIP_CMP_UNAVAILABLE)
6653 #define G_LIP_CMP_UNAVAILABLE(x) (((x) >> S_LIP_CMP_UNAVAILABLE) & M_LIP_CMP_UNAVAILABLE)
6654 
6655 #define A_MC5_DB_ROUTING_TABLE_INDEX 0x70c
6656 
6657 #define S_RTINDX    0
6658 #define M_RTINDX    0x3fffff
6659 #define V_RTINDX(x) ((x) << S_RTINDX)
6660 #define G_RTINDX(x) (((x) >> S_RTINDX) & M_RTINDX)
6661 
6662 #define A_MC5_DB_FILTER_TABLE 0x710
6663 
6664 #define S_SRINDX    0
6665 #define M_SRINDX    0x3fffff
6666 #define V_SRINDX(x) ((x) << S_SRINDX)
6667 #define G_SRINDX(x) (((x) >> S_SRINDX) & M_SRINDX)
6668 
6669 #define A_MC5_DB_SERVER_INDEX 0x714
6670 #define A_MC5_DB_LIP_RAM_ADDR 0x718
6671 
6672 #define S_RAMWR    8
6673 #define V_RAMWR(x) ((x) << S_RAMWR)
6674 #define F_RAMWR    V_RAMWR(1U)
6675 
6676 #define S_RAMADDR    0
6677 #define M_RAMADDR    0x3f
6678 #define V_RAMADDR(x) ((x) << S_RAMADDR)
6679 #define G_RAMADDR(x) (((x) >> S_RAMADDR) & M_RAMADDR)
6680 
6681 #define A_MC5_DB_LIP_RAM_DATA 0x71c
6682 #define A_MC5_DB_RSP_LATENCY 0x720
6683 
6684 #define S_RDLAT    16
6685 #define M_RDLAT    0x1f
6686 #define V_RDLAT(x) ((x) << S_RDLAT)
6687 #define G_RDLAT(x) (((x) >> S_RDLAT) & M_RDLAT)
6688 
6689 #define S_LRNLAT    8
6690 #define M_LRNLAT    0x1f
6691 #define V_LRNLAT(x) ((x) << S_LRNLAT)
6692 #define G_LRNLAT(x) (((x) >> S_LRNLAT) & M_LRNLAT)
6693 
6694 #define S_SRCHLAT    0
6695 #define M_SRCHLAT    0x1f
6696 #define V_SRCHLAT(x) ((x) << S_SRCHLAT)
6697 #define G_SRCHLAT(x) (((x) >> S_SRCHLAT) & M_SRCHLAT)
6698 
6699 #define A_MC5_DB_PARITY_LATENCY 0x724
6700 
6701 #define S_PARLAT    0
6702 #define M_PARLAT    0xf
6703 #define V_PARLAT(x) ((x) << S_PARLAT)
6704 #define G_PARLAT(x) (((x) >> S_PARLAT) & M_PARLAT)
6705 
6706 #define A_MC5_DB_WR_LRN_VERIFY 0x728
6707 
6708 #define S_VWVEREN    2
6709 #define V_VWVEREN(x) ((x) << S_VWVEREN)
6710 #define F_VWVEREN    V_VWVEREN(1U)
6711 
6712 #define S_LRNVEREN    1
6713 #define V_LRNVEREN(x) ((x) << S_LRNVEREN)
6714 #define F_LRNVEREN    V_LRNVEREN(1U)
6715 
6716 #define S_POVEREN    0
6717 #define V_POVEREN(x) ((x) << S_POVEREN)
6718 #define F_POVEREN    V_POVEREN(1U)
6719 
6720 #define A_MC5_DB_PART_ID_INDEX 0x72c
6721 
6722 #define S_IDINDEX    0
6723 #define M_IDINDEX    0xf
6724 #define V_IDINDEX(x) ((x) << S_IDINDEX)
6725 #define G_IDINDEX(x) (((x) >> S_IDINDEX) & M_IDINDEX)
6726 
6727 #define A_MC5_DB_RESET_MAX 0x730
6728 
6729 #define S_RSTMAX    0
6730 #define M_RSTMAX    0xf
6731 #define V_RSTMAX(x) ((x) << S_RSTMAX)
6732 #define G_RSTMAX(x) (((x) >> S_RSTMAX) & M_RSTMAX)
6733 
6734 #define A_MC5_DB_ACT_CNT 0x734
6735 
6736 #define S_ACTCNT    0
6737 #define M_ACTCNT    0xfffff
6738 #define V_ACTCNT(x) ((x) << S_ACTCNT)
6739 #define G_ACTCNT(x) (((x) >> S_ACTCNT) & M_ACTCNT)
6740 
6741 #define A_MC5_DB_CLIP_MAP 0x738
6742 
6743 #define S_CLIPMAPOP    31
6744 #define V_CLIPMAPOP(x) ((x) << S_CLIPMAPOP)
6745 #define F_CLIPMAPOP    V_CLIPMAPOP(1U)
6746 
6747 #define S_CLIPMAPVAL    16
6748 #define M_CLIPMAPVAL    0x3f
6749 #define V_CLIPMAPVAL(x) ((x) << S_CLIPMAPVAL)
6750 #define G_CLIPMAPVAL(x) (((x) >> S_CLIPMAPVAL) & M_CLIPMAPVAL)
6751 
6752 #define S_CLIPMAPADDR    0
6753 #define M_CLIPMAPADDR    0x3f
6754 #define V_CLIPMAPADDR(x) ((x) << S_CLIPMAPADDR)
6755 #define G_CLIPMAPADDR(x) (((x) >> S_CLIPMAPADDR) & M_CLIPMAPADDR)
6756 
6757 #define A_MC5_DB_SIZE 0x73c
6758 #define A_MC5_DB_INT_ENABLE 0x740
6759 
6760 #define S_MSGSEL    28
6761 #define M_MSGSEL    0xf
6762 #define V_MSGSEL(x) ((x) << S_MSGSEL)
6763 #define G_MSGSEL(x) (((x) >> S_MSGSEL) & M_MSGSEL)
6764 
6765 #define S_DELACTEMPTY    18
6766 #define V_DELACTEMPTY(x) ((x) << S_DELACTEMPTY)
6767 #define F_DELACTEMPTY    V_DELACTEMPTY(1U)
6768 
6769 #define S_DISPQPARERR    17
6770 #define V_DISPQPARERR(x) ((x) << S_DISPQPARERR)
6771 #define F_DISPQPARERR    V_DISPQPARERR(1U)
6772 
6773 #define S_REQQPARERR    16
6774 #define V_REQQPARERR(x) ((x) << S_REQQPARERR)
6775 #define F_REQQPARERR    V_REQQPARERR(1U)
6776 
6777 #define S_UNKNOWNCMD    15
6778 #define V_UNKNOWNCMD(x) ((x) << S_UNKNOWNCMD)
6779 #define F_UNKNOWNCMD    V_UNKNOWNCMD(1U)
6780 
6781 #define S_SYNCOOKIEOFF    11
6782 #define V_SYNCOOKIEOFF(x) ((x) << S_SYNCOOKIEOFF)
6783 #define F_SYNCOOKIEOFF    V_SYNCOOKIEOFF(1U)
6784 
6785 #define S_SYNCOOKIEBAD    10
6786 #define V_SYNCOOKIEBAD(x) ((x) << S_SYNCOOKIEBAD)
6787 #define F_SYNCOOKIEBAD    V_SYNCOOKIEBAD(1U)
6788 
6789 #define S_SYNCOOKIE    9
6790 #define V_SYNCOOKIE(x) ((x) << S_SYNCOOKIE)
6791 #define F_SYNCOOKIE    V_SYNCOOKIE(1U)
6792 
6793 #define S_NFASRCHFAIL    8
6794 #define V_NFASRCHFAIL(x) ((x) << S_NFASRCHFAIL)
6795 #define F_NFASRCHFAIL    V_NFASRCHFAIL(1U)
6796 
6797 #define S_ACTRGNFULL    7
6798 #define V_ACTRGNFULL(x) ((x) << S_ACTRGNFULL)
6799 #define F_ACTRGNFULL    V_ACTRGNFULL(1U)
6800 
6801 #define S_PARITYERR    6
6802 #define V_PARITYERR(x) ((x) << S_PARITYERR)
6803 #define F_PARITYERR    V_PARITYERR(1U)
6804 
6805 #define S_LIPMISS    5
6806 #define V_LIPMISS(x) ((x) << S_LIPMISS)
6807 #define F_LIPMISS    V_LIPMISS(1U)
6808 
6809 #define S_LIP0    4
6810 #define V_LIP0(x) ((x) << S_LIP0)
6811 #define F_LIP0    V_LIP0(1U)
6812 
6813 #define S_MISS    3
6814 #define V_MISS(x) ((x) << S_MISS)
6815 #define F_MISS    V_MISS(1U)
6816 
6817 #define S_ROUTINGHIT    2
6818 #define V_ROUTINGHIT(x) ((x) << S_ROUTINGHIT)
6819 #define F_ROUTINGHIT    V_ROUTINGHIT(1U)
6820 
6821 #define S_ACTIVEHIT    1
6822 #define V_ACTIVEHIT(x) ((x) << S_ACTIVEHIT)
6823 #define F_ACTIVEHIT    V_ACTIVEHIT(1U)
6824 
6825 #define S_ACTIVEOUTHIT    0
6826 #define V_ACTIVEOUTHIT(x) ((x) << S_ACTIVEOUTHIT)
6827 #define F_ACTIVEOUTHIT    V_ACTIVEOUTHIT(1U)
6828 
6829 #define A_MC5_DB_INT_CAUSE 0x744
6830 #define A_MC5_DB_INT_TID 0x748
6831 
6832 #define S_INTTID    0
6833 #define M_INTTID    0xfffff
6834 #define V_INTTID(x) ((x) << S_INTTID)
6835 #define G_INTTID(x) (((x) >> S_INTTID) & M_INTTID)
6836 
6837 #define A_MC5_DB_INT_PTID 0x74c
6838 
6839 #define S_INTPTID    0
6840 #define M_INTPTID    0xfffff
6841 #define V_INTPTID(x) ((x) << S_INTPTID)
6842 #define G_INTPTID(x) (((x) >> S_INTPTID) & M_INTPTID)
6843 
6844 #define A_MC5_DB_DBGI_CONFIG 0x774
6845 
6846 #define S_WRREQSIZE    22
6847 #define M_WRREQSIZE    0x3ff
6848 #define V_WRREQSIZE(x) ((x) << S_WRREQSIZE)
6849 #define G_WRREQSIZE(x) (((x) >> S_WRREQSIZE) & M_WRREQSIZE)
6850 
6851 #define S_SADRSEL    4
6852 #define V_SADRSEL(x) ((x) << S_SADRSEL)
6853 #define F_SADRSEL    V_SADRSEL(1U)
6854 
6855 #define S_CMDMODE    0
6856 #define M_CMDMODE    0x7
6857 #define V_CMDMODE(x) ((x) << S_CMDMODE)
6858 #define G_CMDMODE(x) (((x) >> S_CMDMODE) & M_CMDMODE)
6859 
6860 #define A_MC5_DB_DBGI_REQ_CMD 0x778
6861 
6862 #define S_MBUSCMD    0
6863 #define M_MBUSCMD    0xf
6864 #define V_MBUSCMD(x) ((x) << S_MBUSCMD)
6865 #define G_MBUSCMD(x) (((x) >> S_MBUSCMD) & M_MBUSCMD)
6866 
6867 #define S_IDTCMDHI    11
6868 #define M_IDTCMDHI    0x7
6869 #define V_IDTCMDHI(x) ((x) << S_IDTCMDHI)
6870 #define G_IDTCMDHI(x) (((x) >> S_IDTCMDHI) & M_IDTCMDHI)
6871 
6872 #define S_IDTCMDLO    0
6873 #define M_IDTCMDLO    0xf
6874 #define V_IDTCMDLO(x) ((x) << S_IDTCMDLO)
6875 #define G_IDTCMDLO(x) (((x) >> S_IDTCMDLO) & M_IDTCMDLO)
6876 
6877 #define S_IDTCMD    0
6878 #define M_IDTCMD    0xfffff
6879 #define V_IDTCMD(x) ((x) << S_IDTCMD)
6880 #define G_IDTCMD(x) (((x) >> S_IDTCMD) & M_IDTCMD)
6881 
6882 #define S_LCMDB    16
6883 #define M_LCMDB    0x7ff
6884 #define V_LCMDB(x) ((x) << S_LCMDB)
6885 #define G_LCMDB(x) (((x) >> S_LCMDB) & M_LCMDB)
6886 
6887 #define S_LCMDA    0
6888 #define M_LCMDA    0x7ff
6889 #define V_LCMDA(x) ((x) << S_LCMDA)
6890 #define G_LCMDA(x) (((x) >> S_LCMDA) & M_LCMDA)
6891 
6892 #define A_MC5_DB_DBGI_REQ_ADDR0 0x77c
6893 #define A_MC5_DB_DBGI_REQ_ADDR1 0x780
6894 #define A_MC5_DB_DBGI_REQ_ADDR2 0x784
6895 
6896 #define S_DBGIREQADRHI    0
6897 #define M_DBGIREQADRHI    0xff
6898 #define V_DBGIREQADRHI(x) ((x) << S_DBGIREQADRHI)
6899 #define G_DBGIREQADRHI(x) (((x) >> S_DBGIREQADRHI) & M_DBGIREQADRHI)
6900 
6901 #define A_MC5_DB_DBGI_REQ_DATA0 0x788
6902 #define A_MC5_DB_DBGI_REQ_DATA1 0x78c
6903 #define A_MC5_DB_DBGI_REQ_DATA2 0x790
6904 #define A_MC5_DB_DBGI_REQ_DATA3 0x794
6905 #define A_MC5_DB_DBGI_REQ_DATA4 0x798
6906 
6907 #define S_DBGIREQDATA4    0
6908 #define M_DBGIREQDATA4    0xffff
6909 #define V_DBGIREQDATA4(x) ((x) << S_DBGIREQDATA4)
6910 #define G_DBGIREQDATA4(x) (((x) >> S_DBGIREQDATA4) & M_DBGIREQDATA4)
6911 
6912 #define A_MC5_DB_DBGI_REQ_MASK0 0x79c
6913 #define A_MC5_DB_DBGI_REQ_MASK1 0x7a0
6914 #define A_MC5_DB_DBGI_REQ_MASK2 0x7a4
6915 #define A_MC5_DB_DBGI_REQ_MASK3 0x7a8
6916 #define A_MC5_DB_DBGI_REQ_MASK4 0x7ac
6917 
6918 #define S_DBGIREQMSK4    0
6919 #define M_DBGIREQMSK4    0xffff
6920 #define V_DBGIREQMSK4(x) ((x) << S_DBGIREQMSK4)
6921 #define G_DBGIREQMSK4(x) (((x) >> S_DBGIREQMSK4) & M_DBGIREQMSK4)
6922 
6923 #define A_MC5_DB_DBGI_RSP_STATUS 0x7b0
6924 
6925 #define S_DBGIRSPMSG    8
6926 #define M_DBGIRSPMSG    0xf
6927 #define V_DBGIRSPMSG(x) ((x) << S_DBGIRSPMSG)
6928 #define G_DBGIRSPMSG(x) (((x) >> S_DBGIRSPMSG) & M_DBGIRSPMSG)
6929 
6930 #define S_DBGIRSPMSGVLD    2
6931 #define V_DBGIRSPMSGVLD(x) ((x) << S_DBGIRSPMSGVLD)
6932 #define F_DBGIRSPMSGVLD    V_DBGIRSPMSGVLD(1U)
6933 
6934 #define S_DBGIRSPHIT    1
6935 #define V_DBGIRSPHIT(x) ((x) << S_DBGIRSPHIT)
6936 #define F_DBGIRSPHIT    V_DBGIRSPHIT(1U)
6937 
6938 #define S_DBGIRSPVALID    0
6939 #define V_DBGIRSPVALID(x) ((x) << S_DBGIRSPVALID)
6940 #define F_DBGIRSPVALID    V_DBGIRSPVALID(1U)
6941 
6942 #define A_MC5_DB_DBGI_RSP_DATA0 0x7b4
6943 #define A_MC5_DB_DBGI_RSP_DATA1 0x7b8
6944 #define A_MC5_DB_DBGI_RSP_DATA2 0x7bc
6945 #define A_MC5_DB_DBGI_RSP_DATA3 0x7c0
6946 #define A_MC5_DB_DBGI_RSP_DATA4 0x7c4
6947 
6948 #define S_DBGIRSPDATA3    0
6949 #define M_DBGIRSPDATA3    0xffff
6950 #define V_DBGIRSPDATA3(x) ((x) << S_DBGIRSPDATA3)
6951 #define G_DBGIRSPDATA3(x) (((x) >> S_DBGIRSPDATA3) & M_DBGIRSPDATA3)
6952 
6953 #define A_MC5_DB_DBGI_RSP_LAST_CMD 0x7c8
6954 
6955 #define S_LASTCMDB    16
6956 #define M_LASTCMDB    0x7ff
6957 #define V_LASTCMDB(x) ((x) << S_LASTCMDB)
6958 #define G_LASTCMDB(x) (((x) >> S_LASTCMDB) & M_LASTCMDB)
6959 
6960 #define S_LASTCMDA    0
6961 #define M_LASTCMDA    0x7ff
6962 #define V_LASTCMDA(x) ((x) << S_LASTCMDA)
6963 #define G_LASTCMDA(x) (((x) >> S_LASTCMDA) & M_LASTCMDA)
6964 
6965 #define A_MC5_DB_POPEN_DATA_WR_CMD 0x7cc
6966 
6967 #define S_PO_DWR    0
6968 #define M_PO_DWR    0xfffff
6969 #define V_PO_DWR(x) ((x) << S_PO_DWR)
6970 #define G_PO_DWR(x) (((x) >> S_PO_DWR) & M_PO_DWR)
6971 
6972 #define A_MC5_DB_POPEN_MASK_WR_CMD 0x7d0
6973 
6974 #define S_PO_MWR    0
6975 #define M_PO_MWR    0xfffff
6976 #define V_PO_MWR(x) ((x) << S_PO_MWR)
6977 #define G_PO_MWR(x) (((x) >> S_PO_MWR) & M_PO_MWR)
6978 
6979 #define A_MC5_DB_AOPEN_SRCH_CMD 0x7d4
6980 
6981 #define S_AO_SRCH    0
6982 #define M_AO_SRCH    0xfffff
6983 #define V_AO_SRCH(x) ((x) << S_AO_SRCH)
6984 #define G_AO_SRCH(x) (((x) >> S_AO_SRCH) & M_AO_SRCH)
6985 
6986 #define A_MC5_DB_AOPEN_LRN_CMD 0x7d8
6987 
6988 #define S_AO_LRN    0
6989 #define M_AO_LRN    0xfffff
6990 #define V_AO_LRN(x) ((x) << S_AO_LRN)
6991 #define G_AO_LRN(x) (((x) >> S_AO_LRN) & M_AO_LRN)
6992 
6993 #define A_MC5_DB_SYN_SRCH_CMD 0x7dc
6994 
6995 #define S_SYN_SRCH    0
6996 #define M_SYN_SRCH    0xfffff
6997 #define V_SYN_SRCH(x) ((x) << S_SYN_SRCH)
6998 #define G_SYN_SRCH(x) (((x) >> S_SYN_SRCH) & M_SYN_SRCH)
6999 
7000 #define A_MC5_DB_SYN_LRN_CMD 0x7e0
7001 
7002 #define S_SYN_LRN    0
7003 #define M_SYN_LRN    0xfffff
7004 #define V_SYN_LRN(x) ((x) << S_SYN_LRN)
7005 #define G_SYN_LRN(x) (((x) >> S_SYN_LRN) & M_SYN_LRN)
7006 
7007 #define A_MC5_DB_ACK_SRCH_CMD 0x7e4
7008 
7009 #define S_ACK_SRCH    0
7010 #define M_ACK_SRCH    0xfffff
7011 #define V_ACK_SRCH(x) ((x) << S_ACK_SRCH)
7012 #define G_ACK_SRCH(x) (((x) >> S_ACK_SRCH) & M_ACK_SRCH)
7013 
7014 #define A_MC5_DB_ACK_LRN_CMD 0x7e8
7015 
7016 #define S_ACK_LRN    0
7017 #define M_ACK_LRN    0xfffff
7018 #define V_ACK_LRN(x) ((x) << S_ACK_LRN)
7019 #define G_ACK_LRN(x) (((x) >> S_ACK_LRN) & M_ACK_LRN)
7020 
7021 #define A_MC5_DB_ILOOKUP_CMD 0x7ec
7022 
7023 #define S_I_SRCH    0
7024 #define M_I_SRCH    0xfffff
7025 #define V_I_SRCH(x) ((x) << S_I_SRCH)
7026 #define G_I_SRCH(x) (((x) >> S_I_SRCH) & M_I_SRCH)
7027 
7028 #define A_MC5_DB_ELOOKUP_CMD 0x7f0
7029 
7030 #define S_E_SRCH    0
7031 #define M_E_SRCH    0xfffff
7032 #define V_E_SRCH(x) ((x) << S_E_SRCH)
7033 #define G_E_SRCH(x) (((x) >> S_E_SRCH) & M_E_SRCH)
7034 
7035 #define A_MC5_DB_DATA_WRITE_CMD 0x7f4
7036 
7037 #define S_WRITE    0
7038 #define M_WRITE    0xfffff
7039 #define V_WRITE(x) ((x) << S_WRITE)
7040 #define G_WRITE(x) (((x) >> S_WRITE) & M_WRITE)
7041 
7042 #define A_MC5_DB_DATA_READ_CMD 0x7f8
7043 
7044 #define S_READCMD    0
7045 #define M_READCMD    0xfffff
7046 #define V_READCMD(x) ((x) << S_READCMD)
7047 #define G_READCMD(x) (((x) >> S_READCMD) & M_READCMD)
7048 
7049 #define A_MC5_DB_MASK_WRITE_CMD 0x7fc
7050 
7051 #define S_MASKWR    0
7052 #define M_MASKWR    0xffff
7053 #define V_MASKWR(x) ((x) << S_MASKWR)
7054 #define G_MASKWR(x) (((x) >> S_MASKWR) & M_MASKWR)
7055 
7056 /* registers for module XGMAC0_0 */
7057 #define XGMAC0_0_BASE_ADDR 0x800
7058 
7059 #define A_XGM_TX_CTRL 0x800
7060 
7061 #define S_SENDPAUSE    2
7062 #define V_SENDPAUSE(x) ((x) << S_SENDPAUSE)
7063 #define F_SENDPAUSE    V_SENDPAUSE(1U)
7064 
7065 #define S_SENDZEROPAUSE    1
7066 #define V_SENDZEROPAUSE(x) ((x) << S_SENDZEROPAUSE)
7067 #define F_SENDZEROPAUSE    V_SENDZEROPAUSE(1U)
7068 
7069 #define S_TXEN    0
7070 #define V_TXEN(x) ((x) << S_TXEN)
7071 #define F_TXEN    V_TXEN(1U)
7072 
7073 #define A_XGM_TX_CFG 0x804
7074 
7075 #define S_CFGCLKSPEED    2
7076 #define M_CFGCLKSPEED    0x7
7077 #define V_CFGCLKSPEED(x) ((x) << S_CFGCLKSPEED)
7078 #define G_CFGCLKSPEED(x) (((x) >> S_CFGCLKSPEED) & M_CFGCLKSPEED)
7079 
7080 #define S_STRETCHMODE    1
7081 #define V_STRETCHMODE(x) ((x) << S_STRETCHMODE)
7082 #define F_STRETCHMODE    V_STRETCHMODE(1U)
7083 
7084 #define S_TXPAUSEEN    0
7085 #define V_TXPAUSEEN(x) ((x) << S_TXPAUSEEN)
7086 #define F_TXPAUSEEN    V_TXPAUSEEN(1U)
7087 
7088 #define A_XGM_TX_PAUSE_QUANTA 0x808
7089 
7090 #define S_TXPAUSEQUANTA    0
7091 #define M_TXPAUSEQUANTA    0xffff
7092 #define V_TXPAUSEQUANTA(x) ((x) << S_TXPAUSEQUANTA)
7093 #define G_TXPAUSEQUANTA(x) (((x) >> S_TXPAUSEQUANTA) & M_TXPAUSEQUANTA)
7094 
7095 #define A_XGM_RX_CTRL 0x80c
7096 
7097 #define S_RXEN    0
7098 #define V_RXEN(x) ((x) << S_RXEN)
7099 #define F_RXEN    V_RXEN(1U)
7100 
7101 #define A_XGM_RX_CFG 0x810
7102 
7103 #define S_CON802_3PREAMBLE    12
7104 #define V_CON802_3PREAMBLE(x) ((x) << S_CON802_3PREAMBLE)
7105 #define F_CON802_3PREAMBLE    V_CON802_3PREAMBLE(1U)
7106 
7107 #define S_ENNON802_3PREAMBLE    11
7108 #define V_ENNON802_3PREAMBLE(x) ((x) << S_ENNON802_3PREAMBLE)
7109 #define F_ENNON802_3PREAMBLE    V_ENNON802_3PREAMBLE(1U)
7110 
7111 #define S_COPYPREAMBLE    10
7112 #define V_COPYPREAMBLE(x) ((x) << S_COPYPREAMBLE)
7113 #define F_COPYPREAMBLE    V_COPYPREAMBLE(1U)
7114 
7115 #define S_DISPAUSEFRAMES    9
7116 #define V_DISPAUSEFRAMES(x) ((x) << S_DISPAUSEFRAMES)
7117 #define F_DISPAUSEFRAMES    V_DISPAUSEFRAMES(1U)
7118 
7119 #define S_EN1536BFRAMES    8
7120 #define V_EN1536BFRAMES(x) ((x) << S_EN1536BFRAMES)
7121 #define F_EN1536BFRAMES    V_EN1536BFRAMES(1U)
7122 
7123 #define S_ENJUMBO    7
7124 #define V_ENJUMBO(x) ((x) << S_ENJUMBO)
7125 #define F_ENJUMBO    V_ENJUMBO(1U)
7126 
7127 #define S_RMFCS    6
7128 #define V_RMFCS(x) ((x) << S_RMFCS)
7129 #define F_RMFCS    V_RMFCS(1U)
7130 
7131 #define S_DISNONVLAN    5
7132 #define V_DISNONVLAN(x) ((x) << S_DISNONVLAN)
7133 #define F_DISNONVLAN    V_DISNONVLAN(1U)
7134 
7135 #define S_ENEXTMATCH    4
7136 #define V_ENEXTMATCH(x) ((x) << S_ENEXTMATCH)
7137 #define F_ENEXTMATCH    V_ENEXTMATCH(1U)
7138 
7139 #define S_ENHASHUCAST    3
7140 #define V_ENHASHUCAST(x) ((x) << S_ENHASHUCAST)
7141 #define F_ENHASHUCAST    V_ENHASHUCAST(1U)
7142 
7143 #define S_ENHASHMCAST    2
7144 #define V_ENHASHMCAST(x) ((x) << S_ENHASHMCAST)
7145 #define F_ENHASHMCAST    V_ENHASHMCAST(1U)
7146 
7147 #define S_DISBCAST    1
7148 #define V_DISBCAST(x) ((x) << S_DISBCAST)
7149 #define F_DISBCAST    V_DISBCAST(1U)
7150 
7151 #define S_COPYALLFRAMES    0
7152 #define V_COPYALLFRAMES(x) ((x) << S_COPYALLFRAMES)
7153 #define F_COPYALLFRAMES    V_COPYALLFRAMES(1U)
7154 
7155 #define A_XGM_RX_HASH_LOW 0x814
7156 #define A_XGM_RX_HASH_HIGH 0x818
7157 #define A_XGM_RX_EXACT_MATCH_LOW_1 0x81c
7158 #define A_XGM_RX_EXACT_MATCH_HIGH_1 0x820
7159 
7160 #define S_ADDRESS_HIGH    0
7161 #define M_ADDRESS_HIGH    0xffff
7162 #define V_ADDRESS_HIGH(x) ((x) << S_ADDRESS_HIGH)
7163 #define G_ADDRESS_HIGH(x) (((x) >> S_ADDRESS_HIGH) & M_ADDRESS_HIGH)
7164 
7165 #define A_XGM_RX_EXACT_MATCH_LOW_2 0x824
7166 #define A_XGM_RX_EXACT_MATCH_HIGH_2 0x828
7167 #define A_XGM_RX_EXACT_MATCH_LOW_3 0x82c
7168 #define A_XGM_RX_EXACT_MATCH_HIGH_3 0x830
7169 #define A_XGM_RX_EXACT_MATCH_LOW_4 0x834
7170 #define A_XGM_RX_EXACT_MATCH_HIGH_4 0x838
7171 #define A_XGM_RX_EXACT_MATCH_LOW_5 0x83c
7172 #define A_XGM_RX_EXACT_MATCH_HIGH_5 0x840
7173 #define A_XGM_RX_EXACT_MATCH_LOW_6 0x844
7174 #define A_XGM_RX_EXACT_MATCH_HIGH_6 0x848
7175 #define A_XGM_RX_EXACT_MATCH_LOW_7 0x84c
7176 #define A_XGM_RX_EXACT_MATCH_HIGH_7 0x850
7177 #define A_XGM_RX_EXACT_MATCH_LOW_8 0x854
7178 #define A_XGM_RX_EXACT_MATCH_HIGH_8 0x858
7179 #define A_XGM_RX_TYPE_MATCH_1 0x85c
7180 
7181 #define S_ENTYPEMATCH    31
7182 #define V_ENTYPEMATCH(x) ((x) << S_ENTYPEMATCH)
7183 #define F_ENTYPEMATCH    V_ENTYPEMATCH(1U)
7184 
7185 #define S_TYPE    0
7186 #define M_TYPE    0xffff
7187 #define V_TYPE(x) ((x) << S_TYPE)
7188 #define G_TYPE(x) (((x) >> S_TYPE) & M_TYPE)
7189 
7190 #define A_XGM_RX_TYPE_MATCH_2 0x860
7191 #define A_XGM_RX_TYPE_MATCH_3 0x864
7192 #define A_XGM_RX_TYPE_MATCH_4 0x868
7193 #define A_XGM_INT_STATUS 0x86c
7194 
7195 #define S_XGMIIEXTINT    10
7196 #define V_XGMIIEXTINT(x) ((x) << S_XGMIIEXTINT)
7197 #define F_XGMIIEXTINT    V_XGMIIEXTINT(1U)
7198 
7199 #define S_LINKFAULTCHANGE    9
7200 #define V_LINKFAULTCHANGE(x) ((x) << S_LINKFAULTCHANGE)
7201 #define F_LINKFAULTCHANGE    V_LINKFAULTCHANGE(1U)
7202 
7203 #define S_PHYFRAMECOMPLETE    8
7204 #define V_PHYFRAMECOMPLETE(x) ((x) << S_PHYFRAMECOMPLETE)
7205 #define F_PHYFRAMECOMPLETE    V_PHYFRAMECOMPLETE(1U)
7206 
7207 #define S_PAUSEFRAMETXMT    7
7208 #define V_PAUSEFRAMETXMT(x) ((x) << S_PAUSEFRAMETXMT)
7209 #define F_PAUSEFRAMETXMT    V_PAUSEFRAMETXMT(1U)
7210 
7211 #define S_PAUSECNTRTIMEOUT    6
7212 #define V_PAUSECNTRTIMEOUT(x) ((x) << S_PAUSECNTRTIMEOUT)
7213 #define F_PAUSECNTRTIMEOUT    V_PAUSECNTRTIMEOUT(1U)
7214 
7215 #define S_NON0PAUSERCVD    5
7216 #define V_NON0PAUSERCVD(x) ((x) << S_NON0PAUSERCVD)
7217 #define F_NON0PAUSERCVD    V_NON0PAUSERCVD(1U)
7218 
7219 #define S_STATOFLOW    4
7220 #define V_STATOFLOW(x) ((x) << S_STATOFLOW)
7221 #define F_STATOFLOW    V_STATOFLOW(1U)
7222 
7223 #define S_TXERRFIFO    3
7224 #define V_TXERRFIFO(x) ((x) << S_TXERRFIFO)
7225 #define F_TXERRFIFO    V_TXERRFIFO(1U)
7226 
7227 #define S_TXUFLOW    2
7228 #define V_TXUFLOW(x) ((x) << S_TXUFLOW)
7229 #define F_TXUFLOW    V_TXUFLOW(1U)
7230 
7231 #define S_FRAMETXMT    1
7232 #define V_FRAMETXMT(x) ((x) << S_FRAMETXMT)
7233 #define F_FRAMETXMT    V_FRAMETXMT(1U)
7234 
7235 #define S_FRAMERCVD    0
7236 #define V_FRAMERCVD(x) ((x) << S_FRAMERCVD)
7237 #define F_FRAMERCVD    V_FRAMERCVD(1U)
7238 
7239 #define A_XGM_XGM_INT_MASK 0x870
7240 #define A_XGM_XGM_INT_ENABLE 0x874
7241 #define A_XGM_XGM_INT_DISABLE 0x878
7242 #define A_XGM_TX_PAUSE_TIMER 0x87c
7243 
7244 #define S_CURPAUSETIMER    0
7245 #define M_CURPAUSETIMER    0xffff
7246 #define V_CURPAUSETIMER(x) ((x) << S_CURPAUSETIMER)
7247 #define G_CURPAUSETIMER(x) (((x) >> S_CURPAUSETIMER) & M_CURPAUSETIMER)
7248 
7249 #define A_XGM_STAT_CTRL 0x880
7250 
7251 #define S_READSNPSHOT    4
7252 #define V_READSNPSHOT(x) ((x) << S_READSNPSHOT)
7253 #define F_READSNPSHOT    V_READSNPSHOT(1U)
7254 
7255 #define S_TAKESNPSHOT    3
7256 #define V_TAKESNPSHOT(x) ((x) << S_TAKESNPSHOT)
7257 #define F_TAKESNPSHOT    V_TAKESNPSHOT(1U)
7258 
7259 #define S_CLRSTATS    2
7260 #define V_CLRSTATS(x) ((x) << S_CLRSTATS)
7261 #define F_CLRSTATS    V_CLRSTATS(1U)
7262 
7263 #define S_INCRSTATS    1
7264 #define V_INCRSTATS(x) ((x) << S_INCRSTATS)
7265 #define F_INCRSTATS    V_INCRSTATS(1U)
7266 
7267 #define S_ENTESTMODEWR    0
7268 #define V_ENTESTMODEWR(x) ((x) << S_ENTESTMODEWR)
7269 #define F_ENTESTMODEWR    V_ENTESTMODEWR(1U)
7270 
7271 #define A_XGM_RXFIFO_CFG 0x884
7272 
7273 #define S_RXFIFO_EMPTY    31
7274 #define V_RXFIFO_EMPTY(x) ((x) << S_RXFIFO_EMPTY)
7275 #define F_RXFIFO_EMPTY    V_RXFIFO_EMPTY(1U)
7276 
7277 #define S_RXFIFO_FULL    30
7278 #define V_RXFIFO_FULL(x) ((x) << S_RXFIFO_FULL)
7279 #define F_RXFIFO_FULL    V_RXFIFO_FULL(1U)
7280 
7281 #define S_RXFIFOPAUSEHWM    17
7282 #define M_RXFIFOPAUSEHWM    0xfff
7283 #define V_RXFIFOPAUSEHWM(x) ((x) << S_RXFIFOPAUSEHWM)
7284 #define G_RXFIFOPAUSEHWM(x) (((x) >> S_RXFIFOPAUSEHWM) & M_RXFIFOPAUSEHWM)
7285 
7286 #define S_RXFIFOPAUSELWM    5
7287 #define M_RXFIFOPAUSELWM    0xfff
7288 #define V_RXFIFOPAUSELWM(x) ((x) << S_RXFIFOPAUSELWM)
7289 #define G_RXFIFOPAUSELWM(x) (((x) >> S_RXFIFOPAUSELWM) & M_RXFIFOPAUSELWM)
7290 
7291 #define S_FORCEDPAUSE    4
7292 #define V_FORCEDPAUSE(x) ((x) << S_FORCEDPAUSE)
7293 #define F_FORCEDPAUSE    V_FORCEDPAUSE(1U)
7294 
7295 #define S_EXTERNLOOPBACK    3
7296 #define V_EXTERNLOOPBACK(x) ((x) << S_EXTERNLOOPBACK)
7297 #define F_EXTERNLOOPBACK    V_EXTERNLOOPBACK(1U)
7298 
7299 #define S_RXBYTESWAP    2
7300 #define V_RXBYTESWAP(x) ((x) << S_RXBYTESWAP)
7301 #define F_RXBYTESWAP    V_RXBYTESWAP(1U)
7302 
7303 #define S_RXSTRFRWRD    1
7304 #define V_RXSTRFRWRD(x) ((x) << S_RXSTRFRWRD)
7305 #define F_RXSTRFRWRD    V_RXSTRFRWRD(1U)
7306 
7307 #define S_DISERRFRAMES    0
7308 #define V_DISERRFRAMES(x) ((x) << S_DISERRFRAMES)
7309 #define F_DISERRFRAMES    V_DISERRFRAMES(1U)
7310 
7311 #define A_XGM_TXFIFO_CFG 0x888
7312 
7313 #define S_TXFIFO_EMPTY    31
7314 #define V_TXFIFO_EMPTY(x) ((x) << S_TXFIFO_EMPTY)
7315 #define F_TXFIFO_EMPTY    V_TXFIFO_EMPTY(1U)
7316 
7317 #define S_TXFIFO_FULL    30
7318 #define V_TXFIFO_FULL(x) ((x) << S_TXFIFO_FULL)
7319 #define F_TXFIFO_FULL    V_TXFIFO_FULL(1U)
7320 
7321 #define S_UNDERUNFIX    22
7322 #define V_UNDERUNFIX(x) ((x) << S_UNDERUNFIX)
7323 #define F_UNDERUNFIX    V_UNDERUNFIX(1U)
7324 
7325 #define S_ENDROPPKT    21
7326 #define V_ENDROPPKT(x) ((x) << S_ENDROPPKT)
7327 #define F_ENDROPPKT    V_ENDROPPKT(1U)
7328 
7329 #define S_TXIPG    13
7330 #define M_TXIPG    0xff
7331 #define V_TXIPG(x) ((x) << S_TXIPG)
7332 #define G_TXIPG(x) (((x) >> S_TXIPG) & M_TXIPG)
7333 
7334 #define S_TXFIFOTHRESH    4
7335 #define M_TXFIFOTHRESH    0x1ff
7336 #define V_TXFIFOTHRESH(x) ((x) << S_TXFIFOTHRESH)
7337 #define G_TXFIFOTHRESH(x) (((x) >> S_TXFIFOTHRESH) & M_TXFIFOTHRESH)
7338 
7339 #define S_INTERNLOOPBACK    3
7340 #define V_INTERNLOOPBACK(x) ((x) << S_INTERNLOOPBACK)
7341 #define F_INTERNLOOPBACK    V_INTERNLOOPBACK(1U)
7342 
7343 #define S_TXBYTESWAP    2
7344 #define V_TXBYTESWAP(x) ((x) << S_TXBYTESWAP)
7345 #define F_TXBYTESWAP    V_TXBYTESWAP(1U)
7346 
7347 #define S_DISCRC    1
7348 #define V_DISCRC(x) ((x) << S_DISCRC)
7349 #define F_DISCRC    V_DISCRC(1U)
7350 
7351 #define S_DISPREAMBLE    0
7352 #define V_DISPREAMBLE(x) ((x) << S_DISPREAMBLE)
7353 #define F_DISPREAMBLE    V_DISPREAMBLE(1U)
7354 
7355 #define A_XGM_SLOW_TIMER 0x88c
7356 
7357 #define S_PAUSESLOWTIMEREN    31
7358 #define V_PAUSESLOWTIMEREN(x) ((x) << S_PAUSESLOWTIMEREN)
7359 #define F_PAUSESLOWTIMEREN    V_PAUSESLOWTIMEREN(1U)
7360 
7361 #define S_PAUSESLOWTIMER    0
7362 #define M_PAUSESLOWTIMER    0xfffff
7363 #define V_PAUSESLOWTIMER(x) ((x) << S_PAUSESLOWTIMER)
7364 #define G_PAUSESLOWTIMER(x) (((x) >> S_PAUSESLOWTIMER) & M_PAUSESLOWTIMER)
7365 
7366 #define A_XGM_PAUSE_TIMER 0x890
7367 
7368 #define S_PAUSETIMER    0
7369 #define M_PAUSETIMER    0xfffff
7370 #define V_PAUSETIMER(x) ((x) << S_PAUSETIMER)
7371 #define G_PAUSETIMER(x) (((x) >> S_PAUSETIMER) & M_PAUSETIMER)
7372 
7373 #define A_XGM_SERDES_CTRL 0x890
7374 
7375 #define S_SERDESEN    25
7376 #define V_SERDESEN(x) ((x) << S_SERDESEN)
7377 #define F_SERDESEN    V_SERDESEN(1U)
7378 
7379 #define S_SERDESRESET_    24
7380 #define V_SERDESRESET_(x) ((x) << S_SERDESRESET_)
7381 #define F_SERDESRESET_    V_SERDESRESET_(1U)
7382 
7383 #define S_CMURANGE    21
7384 #define M_CMURANGE    0x7
7385 #define V_CMURANGE(x) ((x) << S_CMURANGE)
7386 #define G_CMURANGE(x) (((x) >> S_CMURANGE) & M_CMURANGE)
7387 
7388 #define S_BGENB    20
7389 #define V_BGENB(x) ((x) << S_BGENB)
7390 #define F_BGENB    V_BGENB(1U)
7391 
7392 #define S_ENSKPDROP    19
7393 #define V_ENSKPDROP(x) ((x) << S_ENSKPDROP)
7394 #define F_ENSKPDROP    V_ENSKPDROP(1U)
7395 
7396 #define S_ENCOMMA    18
7397 #define V_ENCOMMA(x) ((x) << S_ENCOMMA)
7398 #define F_ENCOMMA    V_ENCOMMA(1U)
7399 
7400 #define S_EN8B10B    17
7401 #define V_EN8B10B(x) ((x) << S_EN8B10B)
7402 #define F_EN8B10B    V_EN8B10B(1U)
7403 
7404 #define S_ENELBUF    16
7405 #define V_ENELBUF(x) ((x) << S_ENELBUF)
7406 #define F_ENELBUF    V_ENELBUF(1U)
7407 
7408 #define S_GAIN    11
7409 #define M_GAIN    0x1f
7410 #define V_GAIN(x) ((x) << S_GAIN)
7411 #define G_GAIN(x) (((x) >> S_GAIN) & M_GAIN)
7412 
7413 #define S_BANDGAP    7
7414 #define M_BANDGAP    0xf
7415 #define V_BANDGAP(x) ((x) << S_BANDGAP)
7416 #define G_BANDGAP(x) (((x) >> S_BANDGAP) & M_BANDGAP)
7417 
7418 #define S_LPBKEN    5
7419 #define M_LPBKEN    0x3
7420 #define V_LPBKEN(x) ((x) << S_LPBKEN)
7421 #define G_LPBKEN(x) (((x) >> S_LPBKEN) & M_LPBKEN)
7422 
7423 #define S_RXENABLE    4
7424 #define V_RXENABLE(x) ((x) << S_RXENABLE)
7425 #define F_RXENABLE    V_RXENABLE(1U)
7426 
7427 #define S_TXENABLE    3
7428 #define V_TXENABLE(x) ((x) << S_TXENABLE)
7429 #define F_TXENABLE    V_TXENABLE(1U)
7430 
7431 #define A_XGM_XAUI_PCS_TEST 0x894
7432 
7433 #define S_TESTPATTERN    1
7434 #define M_TESTPATTERN    0x3
7435 #define V_TESTPATTERN(x) ((x) << S_TESTPATTERN)
7436 #define G_TESTPATTERN(x) (((x) >> S_TESTPATTERN) & M_TESTPATTERN)
7437 
7438 #define S_ENTEST    0
7439 #define V_ENTEST(x) ((x) << S_ENTEST)
7440 #define F_ENTEST    V_ENTEST(1U)
7441 
7442 #define A_XGM_RGMII_CTRL 0x898
7443 
7444 #define S_PHALIGNFIFOTHRESH    1
7445 #define M_PHALIGNFIFOTHRESH    0x3
7446 #define V_PHALIGNFIFOTHRESH(x) ((x) << S_PHALIGNFIFOTHRESH)
7447 #define G_PHALIGNFIFOTHRESH(x) (((x) >> S_PHALIGNFIFOTHRESH) & M_PHALIGNFIFOTHRESH)
7448 
7449 #define S_TXCLK90SHIFT    0
7450 #define V_TXCLK90SHIFT(x) ((x) << S_TXCLK90SHIFT)
7451 #define F_TXCLK90SHIFT    V_TXCLK90SHIFT(1U)
7452 
7453 #define A_XGM_RGMII_IMP 0x89c
7454 
7455 #define S_CALRESET    8
7456 #define V_CALRESET(x) ((x) << S_CALRESET)
7457 #define F_CALRESET    V_CALRESET(1U)
7458 
7459 #define S_CALUPDATE    7
7460 #define V_CALUPDATE(x) ((x) << S_CALUPDATE)
7461 #define F_CALUPDATE    V_CALUPDATE(1U)
7462 
7463 #define S_XGM_IMPSETUPDATE    6
7464 #define V_XGM_IMPSETUPDATE(x) ((x) << S_XGM_IMPSETUPDATE)
7465 #define F_XGM_IMPSETUPDATE    V_XGM_IMPSETUPDATE(1U)
7466 
7467 #define S_RGMIIIMPPD    3
7468 #define M_RGMIIIMPPD    0x7
7469 #define V_RGMIIIMPPD(x) ((x) << S_RGMIIIMPPD)
7470 #define G_RGMIIIMPPD(x) (((x) >> S_RGMIIIMPPD) & M_RGMIIIMPPD)
7471 
7472 #define S_RGMIIIMPPU    0
7473 #define M_RGMIIIMPPU    0x7
7474 #define V_RGMIIIMPPU(x) ((x) << S_RGMIIIMPPU)
7475 #define G_RGMIIIMPPU(x) (((x) >> S_RGMIIIMPPU) & M_RGMIIIMPPU)
7476 
7477 #define A_XGM_XAUI_IMP 0x8a0
7478 
7479 #define S_XGM_CALFAULT    29
7480 #define V_XGM_CALFAULT(x) ((x) << S_XGM_CALFAULT)
7481 #define F_XGM_CALFAULT    V_XGM_CALFAULT(1U)
7482 
7483 #define S_CALIMP    24
7484 #define M_CALIMP    0x1f
7485 #define V_CALIMP(x) ((x) << S_CALIMP)
7486 #define G_CALIMP(x) (((x) >> S_CALIMP) & M_CALIMP)
7487 
7488 #define S_XAUIIMP    0
7489 #define M_XAUIIMP    0x7
7490 #define V_XAUIIMP(x) ((x) << S_XAUIIMP)
7491 #define G_XAUIIMP(x) (((x) >> S_XAUIIMP) & M_XAUIIMP)
7492 
7493 #define A_XGM_SERDES_BIST 0x8a4
7494 
7495 #define S_BISTDONE    28
7496 #define M_BISTDONE    0xf
7497 #define V_BISTDONE(x) ((x) << S_BISTDONE)
7498 #define G_BISTDONE(x) (((x) >> S_BISTDONE) & M_BISTDONE)
7499 
7500 #define S_BISTCYCLETHRESH    3
7501 #define M_BISTCYCLETHRESH    0x1ffff
7502 #define V_BISTCYCLETHRESH(x) ((x) << S_BISTCYCLETHRESH)
7503 #define G_BISTCYCLETHRESH(x) (((x) >> S_BISTCYCLETHRESH) & M_BISTCYCLETHRESH)
7504 
7505 #define A_XGM_RX_MAX_PKT_SIZE 0x8a8
7506 
7507 #define S_RXMAXFRAMERSIZE    17
7508 #define M_RXMAXFRAMERSIZE    0x3fff
7509 #define V_RXMAXFRAMERSIZE(x) ((x) << S_RXMAXFRAMERSIZE)
7510 #define G_RXMAXFRAMERSIZE(x) (((x) >> S_RXMAXFRAMERSIZE) & M_RXMAXFRAMERSIZE)
7511 
7512 #define S_RXENERRORGATHER    16
7513 #define V_RXENERRORGATHER(x) ((x) << S_RXENERRORGATHER)
7514 #define F_RXENERRORGATHER    V_RXENERRORGATHER(1U)
7515 
7516 #define S_RXENSINGLEFLIT    15
7517 #define V_RXENSINGLEFLIT(x) ((x) << S_RXENSINGLEFLIT)
7518 #define F_RXENSINGLEFLIT    V_RXENSINGLEFLIT(1U)
7519 
7520 #define S_RXENFRAMER    14
7521 #define V_RXENFRAMER(x) ((x) << S_RXENFRAMER)
7522 #define F_RXENFRAMER    V_RXENFRAMER(1U)
7523 
7524 #define S_RXMAXPKTSIZE    0
7525 #define M_RXMAXPKTSIZE    0x3fff
7526 #define V_RXMAXPKTSIZE(x) ((x) << S_RXMAXPKTSIZE)
7527 #define G_RXMAXPKTSIZE(x) (((x) >> S_RXMAXPKTSIZE) & M_RXMAXPKTSIZE)
7528 
7529 #define A_XGM_RESET_CTRL 0x8ac
7530 
7531 #define S_XGMAC_STOP_EN    4
7532 #define V_XGMAC_STOP_EN(x) ((x) << S_XGMAC_STOP_EN)
7533 #define F_XGMAC_STOP_EN    V_XGMAC_STOP_EN(1U)
7534 
7535 #define S_XG2G_RESET_    3
7536 #define V_XG2G_RESET_(x) ((x) << S_XG2G_RESET_)
7537 #define F_XG2G_RESET_    V_XG2G_RESET_(1U)
7538 
7539 #define S_RGMII_RESET_    2
7540 #define V_RGMII_RESET_(x) ((x) << S_RGMII_RESET_)
7541 #define F_RGMII_RESET_    V_RGMII_RESET_(1U)
7542 
7543 #define S_PCS_RESET_    1
7544 #define V_PCS_RESET_(x) ((x) << S_PCS_RESET_)
7545 #define F_PCS_RESET_    V_PCS_RESET_(1U)
7546 
7547 #define S_MAC_RESET_    0
7548 #define V_MAC_RESET_(x) ((x) << S_MAC_RESET_)
7549 #define F_MAC_RESET_    V_MAC_RESET_(1U)
7550 
7551 #define A_XGM_XAUI1G_CTRL 0x8b0
7552 
7553 #define S_XAUI1GLINKID    0
7554 #define M_XAUI1GLINKID    0x3
7555 #define V_XAUI1GLINKID(x) ((x) << S_XAUI1GLINKID)
7556 #define G_XAUI1GLINKID(x) (((x) >> S_XAUI1GLINKID) & M_XAUI1GLINKID)
7557 
7558 #define A_XGM_SERDES_LANE_CTRL 0x8b4
7559 
7560 #define S_LANEREVERSAL    8
7561 #define V_LANEREVERSAL(x) ((x) << S_LANEREVERSAL)
7562 #define F_LANEREVERSAL    V_LANEREVERSAL(1U)
7563 
7564 #define S_TXPOLARITY    4
7565 #define M_TXPOLARITY    0xf
7566 #define V_TXPOLARITY(x) ((x) << S_TXPOLARITY)
7567 #define G_TXPOLARITY(x) (((x) >> S_TXPOLARITY) & M_TXPOLARITY)
7568 
7569 #define S_RXPOLARITY    0
7570 #define M_RXPOLARITY    0xf
7571 #define V_RXPOLARITY(x) ((x) << S_RXPOLARITY)
7572 #define G_RXPOLARITY(x) (((x) >> S_RXPOLARITY) & M_RXPOLARITY)
7573 
7574 #define A_XGM_PORT_CFG 0x8b8
7575 
7576 #define S_SAFESPEEDCHANGE    4
7577 #define V_SAFESPEEDCHANGE(x) ((x) << S_SAFESPEEDCHANGE)
7578 #define F_SAFESPEEDCHANGE    V_SAFESPEEDCHANGE(1U)
7579 
7580 #define S_CLKDIVRESET_    3
7581 #define V_CLKDIVRESET_(x) ((x) << S_CLKDIVRESET_)
7582 #define F_CLKDIVRESET_    V_CLKDIVRESET_(1U)
7583 
7584 #define S_PORTSPEED    1
7585 #define M_PORTSPEED    0x3
7586 #define V_PORTSPEED(x) ((x) << S_PORTSPEED)
7587 #define G_PORTSPEED(x) (((x) >> S_PORTSPEED) & M_PORTSPEED)
7588 
7589 #define S_ENRGMII    0
7590 #define V_ENRGMII(x) ((x) << S_ENRGMII)
7591 #define F_ENRGMII    V_ENRGMII(1U)
7592 
7593 #define A_XGM_EPIO_DATA0 0x8c0
7594 #define A_XGM_EPIO_DATA1 0x8c4
7595 #define A_XGM_EPIO_DATA2 0x8c8
7596 #define A_XGM_EPIO_DATA3 0x8cc
7597 #define A_XGM_EPIO_OP 0x8d0
7598 
7599 #define S_PIO_READY    31
7600 #define V_PIO_READY(x) ((x) << S_PIO_READY)
7601 #define F_PIO_READY    V_PIO_READY(1U)
7602 
7603 #define S_PIO_WRRD    24
7604 #define V_PIO_WRRD(x) ((x) << S_PIO_WRRD)
7605 #define F_PIO_WRRD    V_PIO_WRRD(1U)
7606 
7607 #define S_PIO_ADDRESS    0
7608 #define M_PIO_ADDRESS    0xff
7609 #define V_PIO_ADDRESS(x) ((x) << S_PIO_ADDRESS)
7610 #define G_PIO_ADDRESS(x) (((x) >> S_PIO_ADDRESS) & M_PIO_ADDRESS)
7611 
7612 #define A_XGM_INT_ENABLE 0x8d4
7613 
7614 #define S_XAUIPCSDECERR    24
7615 #define V_XAUIPCSDECERR(x) ((x) << S_XAUIPCSDECERR)
7616 #define F_XAUIPCSDECERR    V_XAUIPCSDECERR(1U)
7617 
7618 #define S_RGMIIRXFIFOOVERFLOW    23
7619 #define V_RGMIIRXFIFOOVERFLOW(x) ((x) << S_RGMIIRXFIFOOVERFLOW)
7620 #define F_RGMIIRXFIFOOVERFLOW    V_RGMIIRXFIFOOVERFLOW(1U)
7621 
7622 #define S_RGMIIRXFIFOUNDERFLOW    22
7623 #define V_RGMIIRXFIFOUNDERFLOW(x) ((x) << S_RGMIIRXFIFOUNDERFLOW)
7624 #define F_RGMIIRXFIFOUNDERFLOW    V_RGMIIRXFIFOUNDERFLOW(1U)
7625 
7626 #define S_RXPKTSIZEERROR    21
7627 #define V_RXPKTSIZEERROR(x) ((x) << S_RXPKTSIZEERROR)
7628 #define F_RXPKTSIZEERROR    V_RXPKTSIZEERROR(1U)
7629 
7630 #define S_WOLPATDETECTED    20
7631 #define V_WOLPATDETECTED(x) ((x) << S_WOLPATDETECTED)
7632 #define F_WOLPATDETECTED    V_WOLPATDETECTED(1U)
7633 
7634 #define S_TXFIFO_PRTY_ERR    17
7635 #define M_TXFIFO_PRTY_ERR    0x7
7636 #define V_TXFIFO_PRTY_ERR(x) ((x) << S_TXFIFO_PRTY_ERR)
7637 #define G_TXFIFO_PRTY_ERR(x) (((x) >> S_TXFIFO_PRTY_ERR) & M_TXFIFO_PRTY_ERR)
7638 
7639 #define S_RXFIFO_PRTY_ERR    14
7640 #define M_RXFIFO_PRTY_ERR    0x7
7641 #define V_RXFIFO_PRTY_ERR(x) ((x) << S_RXFIFO_PRTY_ERR)
7642 #define G_RXFIFO_PRTY_ERR(x) (((x) >> S_RXFIFO_PRTY_ERR) & M_RXFIFO_PRTY_ERR)
7643 
7644 #define S_TXFIFO_UNDERRUN    13
7645 #define V_TXFIFO_UNDERRUN(x) ((x) << S_TXFIFO_UNDERRUN)
7646 #define F_TXFIFO_UNDERRUN    V_TXFIFO_UNDERRUN(1U)
7647 
7648 #define S_RXFIFO_OVERFLOW    12
7649 #define V_RXFIFO_OVERFLOW(x) ((x) << S_RXFIFO_OVERFLOW)
7650 #define F_RXFIFO_OVERFLOW    V_RXFIFO_OVERFLOW(1U)
7651 
7652 #define S_SERDESBISTERR    8
7653 #define M_SERDESBISTERR    0xf
7654 #define V_SERDESBISTERR(x) ((x) << S_SERDESBISTERR)
7655 #define G_SERDESBISTERR(x) (((x) >> S_SERDESBISTERR) & M_SERDESBISTERR)
7656 
7657 #define S_SERDESLOWSIGCHANGE    4
7658 #define M_SERDESLOWSIGCHANGE    0xf
7659 #define V_SERDESLOWSIGCHANGE(x) ((x) << S_SERDESLOWSIGCHANGE)
7660 #define G_SERDESLOWSIGCHANGE(x) (((x) >> S_SERDESLOWSIGCHANGE) & M_SERDESLOWSIGCHANGE)
7661 
7662 #define S_XAUIPCSCTCERR    3
7663 #define V_XAUIPCSCTCERR(x) ((x) << S_XAUIPCSCTCERR)
7664 #define F_XAUIPCSCTCERR    V_XAUIPCSCTCERR(1U)
7665 
7666 #define S_XAUIPCSALIGNCHANGE    2
7667 #define V_XAUIPCSALIGNCHANGE(x) ((x) << S_XAUIPCSALIGNCHANGE)
7668 #define F_XAUIPCSALIGNCHANGE    V_XAUIPCSALIGNCHANGE(1U)
7669 
7670 #define S_RGMIILINKSTSCHANGE    1
7671 #define V_RGMIILINKSTSCHANGE(x) ((x) << S_RGMIILINKSTSCHANGE)
7672 #define F_RGMIILINKSTSCHANGE    V_RGMIILINKSTSCHANGE(1U)
7673 
7674 #define S_XGM_INT    0
7675 #define V_XGM_INT(x) ((x) << S_XGM_INT)
7676 #define F_XGM_INT    V_XGM_INT(1U)
7677 
7678 #define S_SERDESCMULOCK_LOSS    24
7679 #define V_SERDESCMULOCK_LOSS(x) ((x) << S_SERDESCMULOCK_LOSS)
7680 #define F_SERDESCMULOCK_LOSS    V_SERDESCMULOCK_LOSS(1U)
7681 
7682 #define S_SERDESBIST_ERR    8
7683 #define M_SERDESBIST_ERR    0xf
7684 #define V_SERDESBIST_ERR(x) ((x) << S_SERDESBIST_ERR)
7685 #define G_SERDESBIST_ERR(x) (((x) >> S_SERDESBIST_ERR) & M_SERDESBIST_ERR)
7686 
7687 #define S_SERDES_LOS    4
7688 #define M_SERDES_LOS    0xf
7689 #define V_SERDES_LOS(x) ((x) << S_SERDES_LOS)
7690 #define G_SERDES_LOS(x) (((x) >> S_SERDES_LOS) & M_SERDES_LOS)
7691 
7692 #define A_XGM_INT_CAUSE 0x8d8
7693 #define A_XGM_XAUI_ACT_CTRL 0x8dc
7694 
7695 #define S_TXACTENABLE    1
7696 #define V_TXACTENABLE(x) ((x) << S_TXACTENABLE)
7697 #define F_TXACTENABLE    V_TXACTENABLE(1U)
7698 
7699 #define A_XGM_SERDES_CTRL0 0x8e0
7700 
7701 #define S_INTSERLPBK3    27
7702 #define V_INTSERLPBK3(x) ((x) << S_INTSERLPBK3)
7703 #define F_INTSERLPBK3    V_INTSERLPBK3(1U)
7704 
7705 #define S_INTSERLPBK2    26
7706 #define V_INTSERLPBK2(x) ((x) << S_INTSERLPBK2)
7707 #define F_INTSERLPBK2    V_INTSERLPBK2(1U)
7708 
7709 #define S_INTSERLPBK1    25
7710 #define V_INTSERLPBK1(x) ((x) << S_INTSERLPBK1)
7711 #define F_INTSERLPBK1    V_INTSERLPBK1(1U)
7712 
7713 #define S_INTSERLPBK0    24
7714 #define V_INTSERLPBK0(x) ((x) << S_INTSERLPBK0)
7715 #define F_INTSERLPBK0    V_INTSERLPBK0(1U)
7716 
7717 #define S_RESET3    23
7718 #define V_RESET3(x) ((x) << S_RESET3)
7719 #define F_RESET3    V_RESET3(1U)
7720 
7721 #define S_RESET2    22
7722 #define V_RESET2(x) ((x) << S_RESET2)
7723 #define F_RESET2    V_RESET2(1U)
7724 
7725 #define S_RESET1    21
7726 #define V_RESET1(x) ((x) << S_RESET1)
7727 #define F_RESET1    V_RESET1(1U)
7728 
7729 #define S_RESET0    20
7730 #define V_RESET0(x) ((x) << S_RESET0)
7731 #define F_RESET0    V_RESET0(1U)
7732 
7733 #define S_PWRDN3    19
7734 #define V_PWRDN3(x) ((x) << S_PWRDN3)
7735 #define F_PWRDN3    V_PWRDN3(1U)
7736 
7737 #define S_PWRDN2    18
7738 #define V_PWRDN2(x) ((x) << S_PWRDN2)
7739 #define F_PWRDN2    V_PWRDN2(1U)
7740 
7741 #define S_PWRDN1    17
7742 #define V_PWRDN1(x) ((x) << S_PWRDN1)
7743 #define F_PWRDN1    V_PWRDN1(1U)
7744 
7745 #define S_PWRDN0    16
7746 #define V_PWRDN0(x) ((x) << S_PWRDN0)
7747 #define F_PWRDN0    V_PWRDN0(1U)
7748 
7749 #define S_RESETPLL23    15
7750 #define V_RESETPLL23(x) ((x) << S_RESETPLL23)
7751 #define F_RESETPLL23    V_RESETPLL23(1U)
7752 
7753 #define S_RESETPLL01    14
7754 #define V_RESETPLL01(x) ((x) << S_RESETPLL01)
7755 #define F_RESETPLL01    V_RESETPLL01(1U)
7756 
7757 #define S_PW23    12
7758 #define M_PW23    0x3
7759 #define V_PW23(x) ((x) << S_PW23)
7760 #define G_PW23(x) (((x) >> S_PW23) & M_PW23)
7761 
7762 #define S_PW01    10
7763 #define M_PW01    0x3
7764 #define V_PW01(x) ((x) << S_PW01)
7765 #define G_PW01(x) (((x) >> S_PW01) & M_PW01)
7766 
7767 #define S_XGM_DEQ    6
7768 #define M_XGM_DEQ    0xf
7769 #define V_XGM_DEQ(x) ((x) << S_XGM_DEQ)
7770 #define G_XGM_DEQ(x) (((x) >> S_XGM_DEQ) & M_XGM_DEQ)
7771 
7772 #define S_XGM_DTX    2
7773 #define M_XGM_DTX    0xf
7774 #define V_XGM_DTX(x) ((x) << S_XGM_DTX)
7775 #define G_XGM_DTX(x) (((x) >> S_XGM_DTX) & M_XGM_DTX)
7776 
7777 #define S_XGM_LODRV    1
7778 #define V_XGM_LODRV(x) ((x) << S_XGM_LODRV)
7779 #define F_XGM_LODRV    V_XGM_LODRV(1U)
7780 
7781 #define S_XGM_HIDRV    0
7782 #define V_XGM_HIDRV(x) ((x) << S_XGM_HIDRV)
7783 #define F_XGM_HIDRV    V_XGM_HIDRV(1U)
7784 
7785 #define A_XGM_SERDES_CTRL1 0x8e4
7786 
7787 #define S_FMOFFSET3    19
7788 #define M_FMOFFSET3    0x1f
7789 #define V_FMOFFSET3(x) ((x) << S_FMOFFSET3)
7790 #define G_FMOFFSET3(x) (((x) >> S_FMOFFSET3) & M_FMOFFSET3)
7791 
7792 #define S_FMOFFSETEN3    18
7793 #define V_FMOFFSETEN3(x) ((x) << S_FMOFFSETEN3)
7794 #define F_FMOFFSETEN3    V_FMOFFSETEN3(1U)
7795 
7796 #define S_FMOFFSET2    13
7797 #define M_FMOFFSET2    0x1f
7798 #define V_FMOFFSET2(x) ((x) << S_FMOFFSET2)
7799 #define G_FMOFFSET2(x) (((x) >> S_FMOFFSET2) & M_FMOFFSET2)
7800 
7801 #define S_FMOFFSETEN2    12
7802 #define V_FMOFFSETEN2(x) ((x) << S_FMOFFSETEN2)
7803 #define F_FMOFFSETEN2    V_FMOFFSETEN2(1U)
7804 
7805 #define S_FMOFFSET1    7
7806 #define M_FMOFFSET1    0x1f
7807 #define V_FMOFFSET1(x) ((x) << S_FMOFFSET1)
7808 #define G_FMOFFSET1(x) (((x) >> S_FMOFFSET1) & M_FMOFFSET1)
7809 
7810 #define S_FMOFFSETEN1    6
7811 #define V_FMOFFSETEN1(x) ((x) << S_FMOFFSETEN1)
7812 #define F_FMOFFSETEN1    V_FMOFFSETEN1(1U)
7813 
7814 #define S_FMOFFSET0    1
7815 #define M_FMOFFSET0    0x1f
7816 #define V_FMOFFSET0(x) ((x) << S_FMOFFSET0)
7817 #define G_FMOFFSET0(x) (((x) >> S_FMOFFSET0) & M_FMOFFSET0)
7818 
7819 #define S_FMOFFSETEN0    0
7820 #define V_FMOFFSETEN0(x) ((x) << S_FMOFFSETEN0)
7821 #define F_FMOFFSETEN0    V_FMOFFSETEN0(1U)
7822 
7823 #define A_XGM_SERDES_CTRL2 0x8e8
7824 
7825 #define S_DNIN3    11
7826 #define V_DNIN3(x) ((x) << S_DNIN3)
7827 #define F_DNIN3    V_DNIN3(1U)
7828 
7829 #define S_UPIN3    10
7830 #define V_UPIN3(x) ((x) << S_UPIN3)
7831 #define F_UPIN3    V_UPIN3(1U)
7832 
7833 #define S_RXSLAVE3    9
7834 #define V_RXSLAVE3(x) ((x) << S_RXSLAVE3)
7835 #define F_RXSLAVE3    V_RXSLAVE3(1U)
7836 
7837 #define S_DNIN2    8
7838 #define V_DNIN2(x) ((x) << S_DNIN2)
7839 #define F_DNIN2    V_DNIN2(1U)
7840 
7841 #define S_UPIN2    7
7842 #define V_UPIN2(x) ((x) << S_UPIN2)
7843 #define F_UPIN2    V_UPIN2(1U)
7844 
7845 #define S_RXSLAVE2    6
7846 #define V_RXSLAVE2(x) ((x) << S_RXSLAVE2)
7847 #define F_RXSLAVE2    V_RXSLAVE2(1U)
7848 
7849 #define S_DNIN1    5
7850 #define V_DNIN1(x) ((x) << S_DNIN1)
7851 #define F_DNIN1    V_DNIN1(1U)
7852 
7853 #define S_UPIN1    4
7854 #define V_UPIN1(x) ((x) << S_UPIN1)
7855 #define F_UPIN1    V_UPIN1(1U)
7856 
7857 #define S_RXSLAVE1    3
7858 #define V_RXSLAVE1(x) ((x) << S_RXSLAVE1)
7859 #define F_RXSLAVE1    V_RXSLAVE1(1U)
7860 
7861 #define S_DNIN0    2
7862 #define V_DNIN0(x) ((x) << S_DNIN0)
7863 #define F_DNIN0    V_DNIN0(1U)
7864 
7865 #define S_UPIN0    1
7866 #define V_UPIN0(x) ((x) << S_UPIN0)
7867 #define F_UPIN0    V_UPIN0(1U)
7868 
7869 #define S_RXSLAVE0    0
7870 #define V_RXSLAVE0(x) ((x) << S_RXSLAVE0)
7871 #define F_RXSLAVE0    V_RXSLAVE0(1U)
7872 
7873 #define A_XGM_SERDES_CTRL3 0x8ec
7874 
7875 #define S_EXTBISTCHKERRCLR3    31
7876 #define V_EXTBISTCHKERRCLR3(x) ((x) << S_EXTBISTCHKERRCLR3)
7877 #define F_EXTBISTCHKERRCLR3    V_EXTBISTCHKERRCLR3(1U)
7878 
7879 #define S_EXTBISTCHKEN3    30
7880 #define V_EXTBISTCHKEN3(x) ((x) << S_EXTBISTCHKEN3)
7881 #define F_EXTBISTCHKEN3    V_EXTBISTCHKEN3(1U)
7882 
7883 #define S_EXTBISTGENEN3    29
7884 #define V_EXTBISTGENEN3(x) ((x) << S_EXTBISTGENEN3)
7885 #define F_EXTBISTGENEN3    V_EXTBISTGENEN3(1U)
7886 
7887 #define S_EXTBISTPAT3    26
7888 #define M_EXTBISTPAT3    0x7
7889 #define V_EXTBISTPAT3(x) ((x) << S_EXTBISTPAT3)
7890 #define G_EXTBISTPAT3(x) (((x) >> S_EXTBISTPAT3) & M_EXTBISTPAT3)
7891 
7892 #define S_EXTPARRESET3    25
7893 #define V_EXTPARRESET3(x) ((x) << S_EXTPARRESET3)
7894 #define F_EXTPARRESET3    V_EXTPARRESET3(1U)
7895 
7896 #define S_EXTPARLPBK3    24
7897 #define V_EXTPARLPBK3(x) ((x) << S_EXTPARLPBK3)
7898 #define F_EXTPARLPBK3    V_EXTPARLPBK3(1U)
7899 
7900 #define S_EXTBISTCHKERRCLR2    23
7901 #define V_EXTBISTCHKERRCLR2(x) ((x) << S_EXTBISTCHKERRCLR2)
7902 #define F_EXTBISTCHKERRCLR2    V_EXTBISTCHKERRCLR2(1U)
7903 
7904 #define S_EXTBISTCHKEN2    22
7905 #define V_EXTBISTCHKEN2(x) ((x) << S_EXTBISTCHKEN2)
7906 #define F_EXTBISTCHKEN2    V_EXTBISTCHKEN2(1U)
7907 
7908 #define S_EXTBISTGENEN2    21
7909 #define V_EXTBISTGENEN2(x) ((x) << S_EXTBISTGENEN2)
7910 #define F_EXTBISTGENEN2    V_EXTBISTGENEN2(1U)
7911 
7912 #define S_EXTBISTPAT2    18
7913 #define M_EXTBISTPAT2    0x7
7914 #define V_EXTBISTPAT2(x) ((x) << S_EXTBISTPAT2)
7915 #define G_EXTBISTPAT2(x) (((x) >> S_EXTBISTPAT2) & M_EXTBISTPAT2)
7916 
7917 #define S_EXTPARRESET2    17
7918 #define V_EXTPARRESET2(x) ((x) << S_EXTPARRESET2)
7919 #define F_EXTPARRESET2    V_EXTPARRESET2(1U)
7920 
7921 #define S_EXTPARLPBK2    16
7922 #define V_EXTPARLPBK2(x) ((x) << S_EXTPARLPBK2)
7923 #define F_EXTPARLPBK2    V_EXTPARLPBK2(1U)
7924 
7925 #define S_EXTBISTCHKERRCLR1    15
7926 #define V_EXTBISTCHKERRCLR1(x) ((x) << S_EXTBISTCHKERRCLR1)
7927 #define F_EXTBISTCHKERRCLR1    V_EXTBISTCHKERRCLR1(1U)
7928 
7929 #define S_EXTBISTCHKEN1    14
7930 #define V_EXTBISTCHKEN1(x) ((x) << S_EXTBISTCHKEN1)
7931 #define F_EXTBISTCHKEN1    V_EXTBISTCHKEN1(1U)
7932 
7933 #define S_EXTBISTGENEN1    13
7934 #define V_EXTBISTGENEN1(x) ((x) << S_EXTBISTGENEN1)
7935 #define F_EXTBISTGENEN1    V_EXTBISTGENEN1(1U)
7936 
7937 #define S_EXTBISTPAT1    10
7938 #define M_EXTBISTPAT1    0x7
7939 #define V_EXTBISTPAT1(x) ((x) << S_EXTBISTPAT1)
7940 #define G_EXTBISTPAT1(x) (((x) >> S_EXTBISTPAT1) & M_EXTBISTPAT1)
7941 
7942 #define S_EXTPARRESET1    9
7943 #define V_EXTPARRESET1(x) ((x) << S_EXTPARRESET1)
7944 #define F_EXTPARRESET1    V_EXTPARRESET1(1U)
7945 
7946 #define S_EXTPARLPBK1    8
7947 #define V_EXTPARLPBK1(x) ((x) << S_EXTPARLPBK1)
7948 #define F_EXTPARLPBK1    V_EXTPARLPBK1(1U)
7949 
7950 #define S_EXTBISTCHKERRCLR0    7
7951 #define V_EXTBISTCHKERRCLR0(x) ((x) << S_EXTBISTCHKERRCLR0)
7952 #define F_EXTBISTCHKERRCLR0    V_EXTBISTCHKERRCLR0(1U)
7953 
7954 #define S_EXTBISTCHKEN0    6
7955 #define V_EXTBISTCHKEN0(x) ((x) << S_EXTBISTCHKEN0)
7956 #define F_EXTBISTCHKEN0    V_EXTBISTCHKEN0(1U)
7957 
7958 #define S_EXTBISTGENEN0    5
7959 #define V_EXTBISTGENEN0(x) ((x) << S_EXTBISTGENEN0)
7960 #define F_EXTBISTGENEN0    V_EXTBISTGENEN0(1U)
7961 
7962 #define S_EXTBISTPAT0    2
7963 #define M_EXTBISTPAT0    0x7
7964 #define V_EXTBISTPAT0(x) ((x) << S_EXTBISTPAT0)
7965 #define G_EXTBISTPAT0(x) (((x) >> S_EXTBISTPAT0) & M_EXTBISTPAT0)
7966 
7967 #define S_EXTPARRESET0    1
7968 #define V_EXTPARRESET0(x) ((x) << S_EXTPARRESET0)
7969 #define F_EXTPARRESET0    V_EXTPARRESET0(1U)
7970 
7971 #define S_EXTPARLPBK0    0
7972 #define V_EXTPARLPBK0(x) ((x) << S_EXTPARLPBK0)
7973 #define F_EXTPARLPBK0    V_EXTPARLPBK0(1U)
7974 
7975 #define A_XGM_SERDES_STAT0 0x8f0
7976 
7977 #define S_EXTBISTCHKERRCNT0    4
7978 #define M_EXTBISTCHKERRCNT0    0xffffff
7979 #define V_EXTBISTCHKERRCNT0(x) ((x) << S_EXTBISTCHKERRCNT0)
7980 #define G_EXTBISTCHKERRCNT0(x) (((x) >> S_EXTBISTCHKERRCNT0) & M_EXTBISTCHKERRCNT0)
7981 
7982 #define S_EXTBISTCHKFMD0    3
7983 #define V_EXTBISTCHKFMD0(x) ((x) << S_EXTBISTCHKFMD0)
7984 #define F_EXTBISTCHKFMD0    V_EXTBISTCHKFMD0(1U)
7985 
7986 #define S_LOWSIGFORCEEN0    2
7987 #define V_LOWSIGFORCEEN0(x) ((x) << S_LOWSIGFORCEEN0)
7988 #define F_LOWSIGFORCEEN0    V_LOWSIGFORCEEN0(1U)
7989 
7990 #define S_LOWSIGFORCEVALUE0    1
7991 #define V_LOWSIGFORCEVALUE0(x) ((x) << S_LOWSIGFORCEVALUE0)
7992 #define F_LOWSIGFORCEVALUE0    V_LOWSIGFORCEVALUE0(1U)
7993 
7994 #define S_LOWSIG0    0
7995 #define V_LOWSIG0(x) ((x) << S_LOWSIG0)
7996 #define F_LOWSIG0    V_LOWSIG0(1U)
7997 
7998 #define A_XGM_SERDES_STAT1 0x8f4
7999 
8000 #define S_EXTBISTCHKERRCNT1    4
8001 #define M_EXTBISTCHKERRCNT1    0xffffff
8002 #define V_EXTBISTCHKERRCNT1(x) ((x) << S_EXTBISTCHKERRCNT1)
8003 #define G_EXTBISTCHKERRCNT1(x) (((x) >> S_EXTBISTCHKERRCNT1) & M_EXTBISTCHKERRCNT1)
8004 
8005 #define S_EXTBISTCHKFMD1    3
8006 #define V_EXTBISTCHKFMD1(x) ((x) << S_EXTBISTCHKFMD1)
8007 #define F_EXTBISTCHKFMD1    V_EXTBISTCHKFMD1(1U)
8008 
8009 #define S_LOWSIGFORCEEN1    2
8010 #define V_LOWSIGFORCEEN1(x) ((x) << S_LOWSIGFORCEEN1)
8011 #define F_LOWSIGFORCEEN1    V_LOWSIGFORCEEN1(1U)
8012 
8013 #define S_LOWSIGFORCEVALUE1    1
8014 #define V_LOWSIGFORCEVALUE1(x) ((x) << S_LOWSIGFORCEVALUE1)
8015 #define F_LOWSIGFORCEVALUE1    V_LOWSIGFORCEVALUE1(1U)
8016 
8017 #define S_LOWSIG1    0
8018 #define V_LOWSIG1(x) ((x) << S_LOWSIG1)
8019 #define F_LOWSIG1    V_LOWSIG1(1U)
8020 
8021 #define A_XGM_SERDES_STAT2 0x8f8
8022 
8023 #define S_EXTBISTCHKERRCNT2    4
8024 #define M_EXTBISTCHKERRCNT2    0xffffff
8025 #define V_EXTBISTCHKERRCNT2(x) ((x) << S_EXTBISTCHKERRCNT2)
8026 #define G_EXTBISTCHKERRCNT2(x) (((x) >> S_EXTBISTCHKERRCNT2) & M_EXTBISTCHKERRCNT2)
8027 
8028 #define S_EXTBISTCHKFMD2    3
8029 #define V_EXTBISTCHKFMD2(x) ((x) << S_EXTBISTCHKFMD2)
8030 #define F_EXTBISTCHKFMD2    V_EXTBISTCHKFMD2(1U)
8031 
8032 #define S_LOWSIGFORCEEN2    2
8033 #define V_LOWSIGFORCEEN2(x) ((x) << S_LOWSIGFORCEEN2)
8034 #define F_LOWSIGFORCEEN2    V_LOWSIGFORCEEN2(1U)
8035 
8036 #define S_LOWSIGFORCEVALUE2    1
8037 #define V_LOWSIGFORCEVALUE2(x) ((x) << S_LOWSIGFORCEVALUE2)
8038 #define F_LOWSIGFORCEVALUE2    V_LOWSIGFORCEVALUE2(1U)
8039 
8040 #define S_LOWSIG2    0
8041 #define V_LOWSIG2(x) ((x) << S_LOWSIG2)
8042 #define F_LOWSIG2    V_LOWSIG2(1U)
8043 
8044 #define A_XGM_SERDES_STAT3 0x8fc
8045 
8046 #define S_EXTBISTCHKERRCNT3    4
8047 #define M_EXTBISTCHKERRCNT3    0xffffff
8048 #define V_EXTBISTCHKERRCNT3(x) ((x) << S_EXTBISTCHKERRCNT3)
8049 #define G_EXTBISTCHKERRCNT3(x) (((x) >> S_EXTBISTCHKERRCNT3) & M_EXTBISTCHKERRCNT3)
8050 
8051 #define S_EXTBISTCHKFMD3    3
8052 #define V_EXTBISTCHKFMD3(x) ((x) << S_EXTBISTCHKFMD3)
8053 #define F_EXTBISTCHKFMD3    V_EXTBISTCHKFMD3(1U)
8054 
8055 #define S_LOWSIGFORCEEN3    2
8056 #define V_LOWSIGFORCEEN3(x) ((x) << S_LOWSIGFORCEEN3)
8057 #define F_LOWSIGFORCEEN3    V_LOWSIGFORCEEN3(1U)
8058 
8059 #define S_LOWSIGFORCEVALUE3    1
8060 #define V_LOWSIGFORCEVALUE3(x) ((x) << S_LOWSIGFORCEVALUE3)
8061 #define F_LOWSIGFORCEVALUE3    V_LOWSIGFORCEVALUE3(1U)
8062 
8063 #define S_LOWSIG3    0
8064 #define V_LOWSIG3(x) ((x) << S_LOWSIG3)
8065 #define F_LOWSIG3    V_LOWSIG3(1U)
8066 
8067 #define A_XGM_STAT_TX_BYTE_LOW 0x900
8068 #define A_XGM_STAT_TX_BYTE_HIGH 0x904
8069 
8070 #define S_TXBYTES_HIGH    0
8071 #define M_TXBYTES_HIGH    0x1fff
8072 #define V_TXBYTES_HIGH(x) ((x) << S_TXBYTES_HIGH)
8073 #define G_TXBYTES_HIGH(x) (((x) >> S_TXBYTES_HIGH) & M_TXBYTES_HIGH)
8074 
8075 #define A_XGM_STAT_TX_FRAME_LOW 0x908
8076 #define A_XGM_STAT_TX_FRAME_HIGH 0x90c
8077 
8078 #define S_TXFRAMES_HIGH    0
8079 #define M_TXFRAMES_HIGH    0xf
8080 #define V_TXFRAMES_HIGH(x) ((x) << S_TXFRAMES_HIGH)
8081 #define G_TXFRAMES_HIGH(x) (((x) >> S_TXFRAMES_HIGH) & M_TXFRAMES_HIGH)
8082 
8083 #define A_XGM_STAT_TX_BCAST 0x910
8084 #define A_XGM_STAT_TX_MCAST 0x914
8085 #define A_XGM_STAT_TX_PAUSE 0x918
8086 #define A_XGM_STAT_TX_64B_FRAMES 0x91c
8087 #define A_XGM_STAT_TX_65_127B_FRAMES 0x920
8088 #define A_XGM_STAT_TX_128_255B_FRAMES 0x924
8089 #define A_XGM_STAT_TX_256_511B_FRAMES 0x928
8090 #define A_XGM_STAT_TX_512_1023B_FRAMES 0x92c
8091 #define A_XGM_STAT_TX_1024_1518B_FRAMES 0x930
8092 #define A_XGM_STAT_TX_1519_MAXB_FRAMES 0x934
8093 #define A_XGM_STAT_TX_ERR_FRAMES 0x938
8094 #define A_XGM_STAT_RX_BYTES_LOW 0x93c
8095 #define A_XGM_STAT_RX_BYTES_HIGH 0x940
8096 
8097 #define S_RXBYTES_HIGH    0
8098 #define M_RXBYTES_HIGH    0x1fff
8099 #define V_RXBYTES_HIGH(x) ((x) << S_RXBYTES_HIGH)
8100 #define G_RXBYTES_HIGH(x) (((x) >> S_RXBYTES_HIGH) & M_RXBYTES_HIGH)
8101 
8102 #define A_XGM_STAT_RX_FRAMES_LOW 0x944
8103 #define A_XGM_STAT_RX_FRAMES_HIGH 0x948
8104 
8105 #define S_RXFRAMES_HIGH    0
8106 #define M_RXFRAMES_HIGH    0xf
8107 #define V_RXFRAMES_HIGH(x) ((x) << S_RXFRAMES_HIGH)
8108 #define G_RXFRAMES_HIGH(x) (((x) >> S_RXFRAMES_HIGH) & M_RXFRAMES_HIGH)
8109 
8110 #define A_XGM_STAT_RX_BCAST_FRAMES 0x94c
8111 #define A_XGM_STAT_RX_MCAST_FRAMES 0x950
8112 #define A_XGM_STAT_RX_PAUSE_FRAMES 0x954
8113 
8114 #define S_RXPAUSEFRAMES    0
8115 #define M_RXPAUSEFRAMES    0xffff
8116 #define V_RXPAUSEFRAMES(x) ((x) << S_RXPAUSEFRAMES)
8117 #define G_RXPAUSEFRAMES(x) (((x) >> S_RXPAUSEFRAMES) & M_RXPAUSEFRAMES)
8118 
8119 #define A_XGM_STAT_RX_64B_FRAMES 0x958
8120 #define A_XGM_STAT_RX_65_127B_FRAMES 0x95c
8121 #define A_XGM_STAT_RX_128_255B_FRAMES 0x960
8122 #define A_XGM_STAT_RX_256_511B_FRAMES 0x964
8123 #define A_XGM_STAT_RX_512_1023B_FRAMES 0x968
8124 #define A_XGM_STAT_RX_1024_1518B_FRAMES 0x96c
8125 #define A_XGM_STAT_RX_1519_MAXB_FRAMES 0x970
8126 #define A_XGM_STAT_RX_SHORT_FRAMES 0x974
8127 
8128 #define S_RXSHORTFRAMES    0
8129 #define M_RXSHORTFRAMES    0xffff
8130 #define V_RXSHORTFRAMES(x) ((x) << S_RXSHORTFRAMES)
8131 #define G_RXSHORTFRAMES(x) (((x) >> S_RXSHORTFRAMES) & M_RXSHORTFRAMES)
8132 
8133 #define A_XGM_STAT_RX_OVERSIZE_FRAMES 0x978
8134 
8135 #define S_RXOVERSIZEFRAMES    0
8136 #define M_RXOVERSIZEFRAMES    0xffff
8137 #define V_RXOVERSIZEFRAMES(x) ((x) << S_RXOVERSIZEFRAMES)
8138 #define G_RXOVERSIZEFRAMES(x) (((x) >> S_RXOVERSIZEFRAMES) & M_RXOVERSIZEFRAMES)
8139 
8140 #define A_XGM_STAT_RX_JABBER_FRAMES 0x97c
8141 
8142 #define S_RXJABBERFRAMES    0
8143 #define M_RXJABBERFRAMES    0xffff
8144 #define V_RXJABBERFRAMES(x) ((x) << S_RXJABBERFRAMES)
8145 #define G_RXJABBERFRAMES(x) (((x) >> S_RXJABBERFRAMES) & M_RXJABBERFRAMES)
8146 
8147 #define A_XGM_STAT_RX_CRC_ERR_FRAMES 0x980
8148 
8149 #define S_RXCRCERRFRAMES    0
8150 #define M_RXCRCERRFRAMES    0xffff
8151 #define V_RXCRCERRFRAMES(x) ((x) << S_RXCRCERRFRAMES)
8152 #define G_RXCRCERRFRAMES(x) (((x) >> S_RXCRCERRFRAMES) & M_RXCRCERRFRAMES)
8153 
8154 #define A_XGM_STAT_RX_LENGTH_ERR_FRAMES 0x984
8155 
8156 #define S_RXLENGTHERRFRAMES    0
8157 #define M_RXLENGTHERRFRAMES    0xffff
8158 #define V_RXLENGTHERRFRAMES(x) ((x) << S_RXLENGTHERRFRAMES)
8159 #define G_RXLENGTHERRFRAMES(x) (((x) >> S_RXLENGTHERRFRAMES) & M_RXLENGTHERRFRAMES)
8160 
8161 #define A_XGM_STAT_RX_SYM_CODE_ERR_FRAMES 0x988
8162 
8163 #define S_RXSYMCODEERRFRAMES    0
8164 #define M_RXSYMCODEERRFRAMES    0xffff
8165 #define V_RXSYMCODEERRFRAMES(x) ((x) << S_RXSYMCODEERRFRAMES)
8166 #define G_RXSYMCODEERRFRAMES(x) (((x) >> S_RXSYMCODEERRFRAMES) & M_RXSYMCODEERRFRAMES)
8167 
8168 #define A_XGM_SERDES_STATUS0 0x98c
8169 
8170 #define S_RXERRLANE3    9
8171 #define M_RXERRLANE3    0x7
8172 #define V_RXERRLANE3(x) ((x) << S_RXERRLANE3)
8173 #define G_RXERRLANE3(x) (((x) >> S_RXERRLANE3) & M_RXERRLANE3)
8174 
8175 #define S_RXERRLANE2    6
8176 #define M_RXERRLANE2    0x7
8177 #define V_RXERRLANE2(x) ((x) << S_RXERRLANE2)
8178 #define G_RXERRLANE2(x) (((x) >> S_RXERRLANE2) & M_RXERRLANE2)
8179 
8180 #define S_RXERRLANE1    3
8181 #define M_RXERRLANE1    0x7
8182 #define V_RXERRLANE1(x) ((x) << S_RXERRLANE1)
8183 #define G_RXERRLANE1(x) (((x) >> S_RXERRLANE1) & M_RXERRLANE1)
8184 
8185 #define S_RXERRLANE0    0
8186 #define M_RXERRLANE0    0x7
8187 #define V_RXERRLANE0(x) ((x) << S_RXERRLANE0)
8188 #define G_RXERRLANE0(x) (((x) >> S_RXERRLANE0) & M_RXERRLANE0)
8189 
8190 #define A_XGM_SERDES_STATUS1 0x990
8191 
8192 #define S_RXKLOCKLANE3    11
8193 #define V_RXKLOCKLANE3(x) ((x) << S_RXKLOCKLANE3)
8194 #define F_RXKLOCKLANE3    V_RXKLOCKLANE3(1U)
8195 
8196 #define S_RXKLOCKLANE2    10
8197 #define V_RXKLOCKLANE2(x) ((x) << S_RXKLOCKLANE2)
8198 #define F_RXKLOCKLANE2    V_RXKLOCKLANE2(1U)
8199 
8200 #define S_RXKLOCKLANE1    9
8201 #define V_RXKLOCKLANE1(x) ((x) << S_RXKLOCKLANE1)
8202 #define F_RXKLOCKLANE1    V_RXKLOCKLANE1(1U)
8203 
8204 #define S_RXKLOCKLANE0    8
8205 #define V_RXKLOCKLANE0(x) ((x) << S_RXKLOCKLANE0)
8206 #define F_RXKLOCKLANE0    V_RXKLOCKLANE0(1U)
8207 
8208 #define S_RXUFLOWLANE3    7
8209 #define V_RXUFLOWLANE3(x) ((x) << S_RXUFLOWLANE3)
8210 #define F_RXUFLOWLANE3    V_RXUFLOWLANE3(1U)
8211 
8212 #define S_RXUFLOWLANE2    6
8213 #define V_RXUFLOWLANE2(x) ((x) << S_RXUFLOWLANE2)
8214 #define F_RXUFLOWLANE2    V_RXUFLOWLANE2(1U)
8215 
8216 #define S_RXUFLOWLANE1    5
8217 #define V_RXUFLOWLANE1(x) ((x) << S_RXUFLOWLANE1)
8218 #define F_RXUFLOWLANE1    V_RXUFLOWLANE1(1U)
8219 
8220 #define S_RXUFLOWLANE0    4
8221 #define V_RXUFLOWLANE0(x) ((x) << S_RXUFLOWLANE0)
8222 #define F_RXUFLOWLANE0    V_RXUFLOWLANE0(1U)
8223 
8224 #define S_RXOFLOWLANE3    3
8225 #define V_RXOFLOWLANE3(x) ((x) << S_RXOFLOWLANE3)
8226 #define F_RXOFLOWLANE3    V_RXOFLOWLANE3(1U)
8227 
8228 #define S_RXOFLOWLANE2    2
8229 #define V_RXOFLOWLANE2(x) ((x) << S_RXOFLOWLANE2)
8230 #define F_RXOFLOWLANE2    V_RXOFLOWLANE2(1U)
8231 
8232 #define S_RXOFLOWLANE1    1
8233 #define V_RXOFLOWLANE1(x) ((x) << S_RXOFLOWLANE1)
8234 #define F_RXOFLOWLANE1    V_RXOFLOWLANE1(1U)
8235 
8236 #define S_RXOFLOWLANE0    0
8237 #define V_RXOFLOWLANE0(x) ((x) << S_RXOFLOWLANE0)
8238 #define F_RXOFLOWLANE0    V_RXOFLOWLANE0(1U)
8239 
8240 #define A_XGM_SERDES_STATUS2 0x994
8241 
8242 #define S_XGM_RXEIDLANE3    11
8243 #define V_XGM_RXEIDLANE3(x) ((x) << S_XGM_RXEIDLANE3)
8244 #define F_XGM_RXEIDLANE3    V_XGM_RXEIDLANE3(1U)
8245 
8246 #define S_XGM_RXEIDLANE2    10
8247 #define V_XGM_RXEIDLANE2(x) ((x) << S_XGM_RXEIDLANE2)
8248 #define F_XGM_RXEIDLANE2    V_XGM_RXEIDLANE2(1U)
8249 
8250 #define S_XGM_RXEIDLANE1    9
8251 #define V_XGM_RXEIDLANE1(x) ((x) << S_XGM_RXEIDLANE1)
8252 #define F_XGM_RXEIDLANE1    V_XGM_RXEIDLANE1(1U)
8253 
8254 #define S_XGM_RXEIDLANE0    8
8255 #define V_XGM_RXEIDLANE0(x) ((x) << S_XGM_RXEIDLANE0)
8256 #define F_XGM_RXEIDLANE0    V_XGM_RXEIDLANE0(1U)
8257 
8258 #define S_RXREMSKIPLANE3    7
8259 #define V_RXREMSKIPLANE3(x) ((x) << S_RXREMSKIPLANE3)
8260 #define F_RXREMSKIPLANE3    V_RXREMSKIPLANE3(1U)
8261 
8262 #define S_RXREMSKIPLANE2    6
8263 #define V_RXREMSKIPLANE2(x) ((x) << S_RXREMSKIPLANE2)
8264 #define F_RXREMSKIPLANE2    V_RXREMSKIPLANE2(1U)
8265 
8266 #define S_RXREMSKIPLANE1    5
8267 #define V_RXREMSKIPLANE1(x) ((x) << S_RXREMSKIPLANE1)
8268 #define F_RXREMSKIPLANE1    V_RXREMSKIPLANE1(1U)
8269 
8270 #define S_RXREMSKIPLANE0    4
8271 #define V_RXREMSKIPLANE0(x) ((x) << S_RXREMSKIPLANE0)
8272 #define F_RXREMSKIPLANE0    V_RXREMSKIPLANE0(1U)
8273 
8274 #define S_RXADDSKIPLANE3    3
8275 #define V_RXADDSKIPLANE3(x) ((x) << S_RXADDSKIPLANE3)
8276 #define F_RXADDSKIPLANE3    V_RXADDSKIPLANE3(1U)
8277 
8278 #define S_RXADDSKIPLANE2    2
8279 #define V_RXADDSKIPLANE2(x) ((x) << S_RXADDSKIPLANE2)
8280 #define F_RXADDSKIPLANE2    V_RXADDSKIPLANE2(1U)
8281 
8282 #define S_RXADDSKIPLANE1    1
8283 #define V_RXADDSKIPLANE1(x) ((x) << S_RXADDSKIPLANE1)
8284 #define F_RXADDSKIPLANE1    V_RXADDSKIPLANE1(1U)
8285 
8286 #define S_RXADDSKIPLANE0    0
8287 #define V_RXADDSKIPLANE0(x) ((x) << S_RXADDSKIPLANE0)
8288 #define F_RXADDSKIPLANE0    V_RXADDSKIPLANE0(1U)
8289 
8290 #define A_XGM_XAUI_PCS_ERR 0x998
8291 
8292 #define S_PCS_SYNCSTATUS    5
8293 #define M_PCS_SYNCSTATUS    0xf
8294 #define V_PCS_SYNCSTATUS(x) ((x) << S_PCS_SYNCSTATUS)
8295 #define G_PCS_SYNCSTATUS(x) (((x) >> S_PCS_SYNCSTATUS) & M_PCS_SYNCSTATUS)
8296 
8297 #define S_PCS_CTCFIFOERR    1
8298 #define M_PCS_CTCFIFOERR    0xf
8299 #define V_PCS_CTCFIFOERR(x) ((x) << S_PCS_CTCFIFOERR)
8300 #define G_PCS_CTCFIFOERR(x) (((x) >> S_PCS_CTCFIFOERR) & M_PCS_CTCFIFOERR)
8301 
8302 #define S_PCS_NOTALIGNED    0
8303 #define V_PCS_NOTALIGNED(x) ((x) << S_PCS_NOTALIGNED)
8304 #define F_PCS_NOTALIGNED    V_PCS_NOTALIGNED(1U)
8305 
8306 #define A_XGM_RGMII_STATUS 0x99c
8307 
8308 #define S_GMIIDUPLEX    3
8309 #define V_GMIIDUPLEX(x) ((x) << S_GMIIDUPLEX)
8310 #define F_GMIIDUPLEX    V_GMIIDUPLEX(1U)
8311 
8312 #define S_GMIISPEED    1
8313 #define M_GMIISPEED    0x3
8314 #define V_GMIISPEED(x) ((x) << S_GMIISPEED)
8315 #define G_GMIISPEED(x) (((x) >> S_GMIISPEED) & M_GMIISPEED)
8316 
8317 #define S_GMIILINKSTATUS    0
8318 #define V_GMIILINKSTATUS(x) ((x) << S_GMIILINKSTATUS)
8319 #define F_GMIILINKSTATUS    V_GMIILINKSTATUS(1U)
8320 
8321 #define A_XGM_WOL_STATUS 0x9a0
8322 
8323 #define S_PATDETECTED    31
8324 #define V_PATDETECTED(x) ((x) << S_PATDETECTED)
8325 #define F_PATDETECTED    V_PATDETECTED(1U)
8326 
8327 #define S_MATCHEDFILTER    0
8328 #define M_MATCHEDFILTER    0x7
8329 #define V_MATCHEDFILTER(x) ((x) << S_MATCHEDFILTER)
8330 #define G_MATCHEDFILTER(x) (((x) >> S_MATCHEDFILTER) & M_MATCHEDFILTER)
8331 
8332 #define A_XGM_RX_MAX_PKT_SIZE_ERR_CNT 0x9a4
8333 #define A_XGM_TX_SPI4_SOP_EOP_CNT 0x9a8
8334 
8335 #define S_TXSPI4SOPCNT    16
8336 #define M_TXSPI4SOPCNT    0xffff
8337 #define V_TXSPI4SOPCNT(x) ((x) << S_TXSPI4SOPCNT)
8338 #define G_TXSPI4SOPCNT(x) (((x) >> S_TXSPI4SOPCNT) & M_TXSPI4SOPCNT)
8339 
8340 #define S_TXSPI4EOPCNT    0
8341 #define M_TXSPI4EOPCNT    0xffff
8342 #define V_TXSPI4EOPCNT(x) ((x) << S_TXSPI4EOPCNT)
8343 #define G_TXSPI4EOPCNT(x) (((x) >> S_TXSPI4EOPCNT) & M_TXSPI4EOPCNT)
8344 
8345 #define A_XGM_RX_SPI4_SOP_EOP_CNT 0x9ac
8346 
8347 #define S_RXSPI4SOPCNT    16
8348 #define M_RXSPI4SOPCNT    0xffff
8349 #define V_RXSPI4SOPCNT(x) ((x) << S_RXSPI4SOPCNT)
8350 #define G_RXSPI4SOPCNT(x) (((x) >> S_RXSPI4SOPCNT) & M_RXSPI4SOPCNT)
8351 
8352 #define S_RXSPI4EOPCNT    0
8353 #define M_RXSPI4EOPCNT    0xffff
8354 #define V_RXSPI4EOPCNT(x) ((x) << S_RXSPI4EOPCNT)
8355 #define G_RXSPI4EOPCNT(x) (((x) >> S_RXSPI4EOPCNT) & M_RXSPI4EOPCNT)
8356 
8357 /* registers for module XGMAC0_1 */
8358 #define XGMAC0_1_BASE_ADDR 0xa00
8359