1 /************************************************************************** 2 3 Copyright (c) 2007, Chelsio Inc. 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Neither the name of the Chelsio Corporation nor the names of its 13 contributors may be used to endorse or promote products derived from 14 this software without specific prior written permission. 15 16 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 20 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 POSSIBILITY OF SUCH DAMAGE. 27 28 ***************************************************************************/ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #ifdef CONFIG_DEFINED 34 #include <common/cxgb_common.h> 35 #include <common/cxgb_regs.h> 36 #else 37 #include <dev/cxgb/common/cxgb_common.h> 38 #include <dev/cxgb/common/cxgb_regs.h> 39 #endif 40 41 enum { 42 IDT75P52100 = 4, 43 IDT75N43102 = 5 44 }; 45 46 /* DBGI command mode */ 47 enum { 48 DBGI_MODE_MBUS = 0, 49 DBGI_MODE_IDT52100 = 5 50 }; 51 52 /* IDT 75P52100 commands */ 53 #define IDT_CMD_READ 0 54 #define IDT_CMD_WRITE 1 55 #define IDT_CMD_SEARCH 2 56 #define IDT_CMD_LEARN 3 57 58 /* IDT LAR register address and value for 144-bit mode (low 32 bits) */ 59 #define IDT_LAR_ADR0 0x180006 60 #define IDT_LAR_MODE144 0xffff0000 61 62 /* IDT SCR and SSR addresses (low 32 bits) */ 63 #define IDT_SCR_ADR0 0x180000 64 #define IDT_SSR0_ADR0 0x180002 65 #define IDT_SSR1_ADR0 0x180004 66 67 /* IDT GMR base address (low 32 bits) */ 68 #define IDT_GMR_BASE_ADR0 0x180020 69 70 /* IDT data and mask array base addresses (low 32 bits) */ 71 #define IDT_DATARY_BASE_ADR0 0 72 #define IDT_MSKARY_BASE_ADR0 0x80000 73 74 /* IDT 75N43102 commands */ 75 #define IDT4_CMD_SEARCH144 3 76 #define IDT4_CMD_WRITE 4 77 #define IDT4_CMD_READ 5 78 79 /* IDT 75N43102 SCR address (low 32 bits) */ 80 #define IDT4_SCR_ADR0 0x3 81 82 /* IDT 75N43102 GMR base addresses (low 32 bits) */ 83 #define IDT4_GMR_BASE0 0x10 84 #define IDT4_GMR_BASE1 0x20 85 #define IDT4_GMR_BASE2 0x30 86 87 /* IDT 75N43102 data and mask array base addresses (low 32 bits) */ 88 #define IDT4_DATARY_BASE_ADR0 0x1000000 89 #define IDT4_MSKARY_BASE_ADR0 0x2000000 90 91 #define MAX_WRITE_ATTEMPTS 5 92 93 #define MAX_ROUTES 2048 94 95 /* 96 * Issue a command to the TCAM and wait for its completion. The address and 97 * any data required by the command must have been setup by the caller. 98 */ 99 static int mc5_cmd_write(adapter_t *adapter, u32 cmd) 100 { 101 t3_write_reg(adapter, A_MC5_DB_DBGI_REQ_CMD, cmd); 102 return t3_wait_op_done(adapter, A_MC5_DB_DBGI_RSP_STATUS, 103 F_DBGIRSPVALID, 1, MAX_WRITE_ATTEMPTS, 1); 104 } 105 106 static inline void dbgi_wr_addr3(adapter_t *adapter, u32 v1, u32 v2, u32 v3) 107 { 108 t3_write_reg(adapter, A_MC5_DB_DBGI_REQ_ADDR0, v1); 109 t3_write_reg(adapter, A_MC5_DB_DBGI_REQ_ADDR1, v2); 110 t3_write_reg(adapter, A_MC5_DB_DBGI_REQ_ADDR2, v3); 111 } 112 113 static inline void dbgi_wr_data3(adapter_t *adapter, u32 v1, u32 v2, u32 v3) 114 { 115 t3_write_reg(adapter, A_MC5_DB_DBGI_REQ_DATA0, v1); 116 t3_write_reg(adapter, A_MC5_DB_DBGI_REQ_DATA1, v2); 117 t3_write_reg(adapter, A_MC5_DB_DBGI_REQ_DATA2, v3); 118 } 119 120 static inline void dbgi_rd_rsp3(adapter_t *adapter, u32 *v1, u32 *v2, u32 *v3) 121 { 122 *v1 = t3_read_reg(adapter, A_MC5_DB_DBGI_RSP_DATA0); 123 *v2 = t3_read_reg(adapter, A_MC5_DB_DBGI_RSP_DATA1); 124 *v3 = t3_read_reg(adapter, A_MC5_DB_DBGI_RSP_DATA2); 125 } 126 127 /* 128 * Write data to the TCAM register at address (0, 0, addr_lo) using the TCAM 129 * command cmd. The data to be written must have been set up by the caller. 130 * Returns -1 on failure, 0 on success. 131 */ 132 static int mc5_write(adapter_t *adapter, u32 addr_lo, u32 cmd) 133 { 134 t3_write_reg(adapter, A_MC5_DB_DBGI_REQ_ADDR0, addr_lo); 135 if (mc5_cmd_write(adapter, cmd) == 0) 136 return 0; 137 CH_ERR(adapter, "MC5 timeout writing to TCAM address 0x%x\n", addr_lo); 138 return -1; 139 } 140 141 static int init_mask_data_array(struct mc5 *mc5, u32 mask_array_base, 142 u32 data_array_base, u32 write_cmd, 143 int addr_shift) 144 { 145 unsigned int i; 146 adapter_t *adap = mc5->adapter; 147 148 /* 149 * We need the size of the TCAM data and mask arrays in terms of 150 * 72-bit entries. 151 */ 152 unsigned int size72 = mc5->tcam_size; 153 unsigned int server_base = t3_read_reg(adap, A_MC5_DB_SERVER_INDEX); 154 155 if (mc5->mode == MC5_MODE_144_BIT) { 156 size72 *= 2; /* 1 144-bit entry is 2 72-bit entries */ 157 server_base *= 2; 158 } 159 160 /* Clear the data array */ 161 dbgi_wr_data3(adap, 0, 0, 0); 162 for (i = 0; i < size72; i++) 163 if (mc5_write(adap, data_array_base + (i << addr_shift), 164 write_cmd)) 165 return -1; 166 167 /* Initialize the mask array. */ 168 dbgi_wr_data3(adap, 0xffffffff, 0xffffffff, 0xff); 169 for (i = 0; i < size72; i++) { 170 if (i == server_base) /* entering server or routing region */ 171 t3_write_reg(adap, A_MC5_DB_DBGI_REQ_DATA0, 172 mc5->mode == MC5_MODE_144_BIT ? 173 0xfffffff9 : 0xfffffffd); 174 if (mc5_write(adap, mask_array_base + (i << addr_shift), 175 write_cmd)) 176 return -1; 177 } 178 return 0; 179 } 180 181 static int init_idt52100(struct mc5 *mc5) 182 { 183 int i; 184 adapter_t *adap = mc5->adapter; 185 186 t3_write_reg(adap, A_MC5_DB_RSP_LATENCY, 187 V_RDLAT(0x15) | V_LRNLAT(0x15) | V_SRCHLAT(0x15)); 188 t3_write_reg(adap, A_MC5_DB_PART_ID_INDEX, 2); 189 190 /* 191 * Use GMRs 14-15 for ELOOKUP, GMRs 12-13 for SYN lookups, and 192 * GMRs 8-9 for ACK- and AOPEN searches. 193 */ 194 t3_write_reg(adap, A_MC5_DB_POPEN_DATA_WR_CMD, IDT_CMD_WRITE); 195 t3_write_reg(adap, A_MC5_DB_POPEN_MASK_WR_CMD, IDT_CMD_WRITE); 196 t3_write_reg(adap, A_MC5_DB_AOPEN_SRCH_CMD, IDT_CMD_SEARCH); 197 t3_write_reg(adap, A_MC5_DB_AOPEN_LRN_CMD, IDT_CMD_LEARN); 198 t3_write_reg(adap, A_MC5_DB_SYN_SRCH_CMD, IDT_CMD_SEARCH | 0x6000); 199 t3_write_reg(adap, A_MC5_DB_SYN_LRN_CMD, IDT_CMD_LEARN); 200 t3_write_reg(adap, A_MC5_DB_ACK_SRCH_CMD, IDT_CMD_SEARCH); 201 t3_write_reg(adap, A_MC5_DB_ACK_LRN_CMD, IDT_CMD_LEARN); 202 t3_write_reg(adap, A_MC5_DB_ILOOKUP_CMD, IDT_CMD_SEARCH); 203 t3_write_reg(adap, A_MC5_DB_ELOOKUP_CMD, IDT_CMD_SEARCH | 0x7000); 204 t3_write_reg(adap, A_MC5_DB_DATA_WRITE_CMD, IDT_CMD_WRITE); 205 t3_write_reg(adap, A_MC5_DB_DATA_READ_CMD, IDT_CMD_READ); 206 207 /* Set DBGI command mode for IDT TCAM. */ 208 t3_write_reg(adap, A_MC5_DB_DBGI_CONFIG, DBGI_MODE_IDT52100); 209 210 /* Set up LAR */ 211 dbgi_wr_data3(adap, IDT_LAR_MODE144, 0, 0); 212 if (mc5_write(adap, IDT_LAR_ADR0, IDT_CMD_WRITE)) 213 goto err; 214 215 /* Set up SSRs */ 216 dbgi_wr_data3(adap, 0xffffffff, 0xffffffff, 0); 217 if (mc5_write(adap, IDT_SSR0_ADR0, IDT_CMD_WRITE) || 218 mc5_write(adap, IDT_SSR1_ADR0, IDT_CMD_WRITE)) 219 goto err; 220 221 /* Set up GMRs */ 222 for (i = 0; i < 32; ++i) { 223 if (i >= 12 && i < 15) 224 dbgi_wr_data3(adap, 0xfffffff9, 0xffffffff, 0xff); 225 else if (i == 15) 226 dbgi_wr_data3(adap, 0xfffffff9, 0xffff8007, 0xff); 227 else 228 dbgi_wr_data3(adap, 0xffffffff, 0xffffffff, 0xff); 229 230 if (mc5_write(adap, IDT_GMR_BASE_ADR0 + i, IDT_CMD_WRITE)) 231 goto err; 232 } 233 234 /* Set up SCR */ 235 dbgi_wr_data3(adap, 1, 0, 0); 236 if (mc5_write(adap, IDT_SCR_ADR0, IDT_CMD_WRITE)) 237 goto err; 238 239 return init_mask_data_array(mc5, IDT_MSKARY_BASE_ADR0, 240 IDT_DATARY_BASE_ADR0, IDT_CMD_WRITE, 0); 241 err: 242 return -EIO; 243 } 244 245 static int init_idt43102(struct mc5 *mc5) 246 { 247 int i; 248 adapter_t *adap = mc5->adapter; 249 250 t3_write_reg(adap, A_MC5_DB_RSP_LATENCY, 251 adap->params.rev == 0 ? V_RDLAT(0xd) | V_SRCHLAT(0x11) : 252 V_RDLAT(0xd) | V_SRCHLAT(0x12)); 253 254 /* 255 * Use GMRs 24-25 for ELOOKUP, GMRs 20-21 for SYN lookups, and no mask 256 * for ACK- and AOPEN searches. 257 */ 258 t3_write_reg(adap, A_MC5_DB_POPEN_DATA_WR_CMD, IDT4_CMD_WRITE); 259 t3_write_reg(adap, A_MC5_DB_POPEN_MASK_WR_CMD, IDT4_CMD_WRITE); 260 t3_write_reg(adap, A_MC5_DB_AOPEN_SRCH_CMD, 261 IDT4_CMD_SEARCH144 | 0x3800); 262 t3_write_reg(adap, A_MC5_DB_SYN_SRCH_CMD, IDT4_CMD_SEARCH144); 263 t3_write_reg(adap, A_MC5_DB_ACK_SRCH_CMD, IDT4_CMD_SEARCH144 | 0x3800); 264 t3_write_reg(adap, A_MC5_DB_ILOOKUP_CMD, IDT4_CMD_SEARCH144 | 0x3800); 265 t3_write_reg(adap, A_MC5_DB_ELOOKUP_CMD, IDT4_CMD_SEARCH144 | 0x800); 266 t3_write_reg(adap, A_MC5_DB_DATA_WRITE_CMD, IDT4_CMD_WRITE); 267 t3_write_reg(adap, A_MC5_DB_DATA_READ_CMD, IDT4_CMD_READ); 268 269 t3_write_reg(adap, A_MC5_DB_PART_ID_INDEX, 3); 270 271 /* Set DBGI command mode for IDT TCAM. */ 272 t3_write_reg(adap, A_MC5_DB_DBGI_CONFIG, DBGI_MODE_IDT52100); 273 274 /* Set up GMRs */ 275 dbgi_wr_data3(adap, 0xffffffff, 0xffffffff, 0xff); 276 for (i = 0; i < 7; ++i) 277 if (mc5_write(adap, IDT4_GMR_BASE0 + i, IDT4_CMD_WRITE)) 278 goto err; 279 280 for (i = 0; i < 4; ++i) 281 if (mc5_write(adap, IDT4_GMR_BASE2 + i, IDT4_CMD_WRITE)) 282 goto err; 283 284 dbgi_wr_data3(adap, 0xfffffff9, 0xffffffff, 0xff); 285 if (mc5_write(adap, IDT4_GMR_BASE1, IDT4_CMD_WRITE) || 286 mc5_write(adap, IDT4_GMR_BASE1 + 1, IDT4_CMD_WRITE) || 287 mc5_write(adap, IDT4_GMR_BASE1 + 4, IDT4_CMD_WRITE)) 288 goto err; 289 290 dbgi_wr_data3(adap, 0xfffffff9, 0xffff8007, 0xff); 291 if (mc5_write(adap, IDT4_GMR_BASE1 + 5, IDT4_CMD_WRITE)) 292 goto err; 293 294 /* Set up SCR */ 295 dbgi_wr_data3(adap, 0xf0000000, 0, 0); 296 if (mc5_write(adap, IDT4_SCR_ADR0, IDT4_CMD_WRITE)) 297 goto err; 298 299 return init_mask_data_array(mc5, IDT4_MSKARY_BASE_ADR0, 300 IDT4_DATARY_BASE_ADR0, IDT4_CMD_WRITE, 1); 301 err: 302 return -EIO; 303 } 304 305 /* Put MC5 in DBGI mode. */ 306 static inline void mc5_dbgi_mode_enable(const struct mc5 *mc5) 307 { 308 t3_write_reg(mc5->adapter, A_MC5_DB_CONFIG, 309 V_TMMODE(mc5->mode == MC5_MODE_72_BIT) | F_DBGIEN); 310 } 311 312 /* Put MC5 in M-Bus mode. */ 313 static void mc5_dbgi_mode_disable(const struct mc5 *mc5) 314 { 315 t3_write_reg(mc5->adapter, A_MC5_DB_CONFIG, 316 V_TMMODE(mc5->mode == MC5_MODE_72_BIT) | 317 V_COMPEN(mc5->mode == MC5_MODE_72_BIT) | 318 V_PRTYEN(mc5->parity_enabled) | F_MBUSEN); 319 } 320 321 /* 322 * Initialization that requires the OS and protocol layers to already 323 * be intialized goes here. 324 */ 325 int t3_mc5_init(struct mc5 *mc5, unsigned int nservers, unsigned int nfilters, 326 unsigned int nroutes) 327 { 328 u32 cfg; 329 int err; 330 unsigned int tcam_size = mc5->tcam_size; 331 adapter_t *adap = mc5->adapter; 332 333 if (!tcam_size) 334 return 0; 335 336 if (nroutes > MAX_ROUTES || nroutes + nservers + nfilters > tcam_size) 337 return -EINVAL; 338 339 /* Reset the TCAM */ 340 cfg = t3_read_reg(adap, A_MC5_DB_CONFIG) & ~F_TMMODE; 341 cfg |= V_TMMODE(mc5->mode == MC5_MODE_72_BIT) | F_TMRST; 342 t3_write_reg(adap, A_MC5_DB_CONFIG, cfg); 343 if (t3_wait_op_done(adap, A_MC5_DB_CONFIG, F_TMRDY, 1, 500, 0)) { 344 CH_ERR(adap, "TCAM reset timed out\n"); 345 return -1; 346 } 347 348 t3_write_reg(adap, A_MC5_DB_ROUTING_TABLE_INDEX, tcam_size - nroutes); 349 t3_write_reg(adap, A_MC5_DB_FILTER_TABLE, 350 tcam_size - nroutes - nfilters); 351 t3_write_reg(adap, A_MC5_DB_SERVER_INDEX, 352 tcam_size - nroutes - nfilters - nservers); 353 354 mc5->parity_enabled = 1; 355 356 /* All the TCAM addresses we access have only the low 32 bits non 0 */ 357 t3_write_reg(adap, A_MC5_DB_DBGI_REQ_ADDR1, 0); 358 t3_write_reg(adap, A_MC5_DB_DBGI_REQ_ADDR2, 0); 359 360 mc5_dbgi_mode_enable(mc5); 361 362 switch (mc5->part_type) { 363 case IDT75P52100: 364 err = init_idt52100(mc5); 365 break; 366 case IDT75N43102: 367 err = init_idt43102(mc5); 368 break; 369 default: 370 CH_ERR(adap, "Unsupported TCAM type %d\n", mc5->part_type); 371 err = -EINVAL; 372 break; 373 } 374 375 mc5_dbgi_mode_disable(mc5); 376 return err; 377 } 378 379 /* 380 * read_mc5_range - dump a part of the memory managed by MC5 381 * @mc5: the MC5 handle 382 * @start: the start address for the dump 383 * @n: number of 72-bit words to read 384 * @buf: result buffer 385 * 386 * Read n 72-bit words from MC5 memory from the given start location. 387 */ 388 int t3_read_mc5_range(const struct mc5 *mc5, unsigned int start, 389 unsigned int n, u32 *buf) 390 { 391 u32 read_cmd; 392 int err = 0; 393 adapter_t *adap = mc5->adapter; 394 395 if (mc5->part_type == IDT75P52100) 396 read_cmd = IDT_CMD_READ; 397 else if (mc5->part_type == IDT75N43102) 398 read_cmd = IDT4_CMD_READ; 399 else 400 return -EINVAL; 401 402 mc5_dbgi_mode_enable(mc5); 403 404 while (n--) { 405 t3_write_reg(adap, A_MC5_DB_DBGI_REQ_ADDR0, start++); 406 if (mc5_cmd_write(adap, read_cmd)) { 407 err = -EIO; 408 break; 409 } 410 dbgi_rd_rsp3(adap, buf + 2, buf + 1, buf); 411 buf += 3; 412 } 413 414 mc5_dbgi_mode_disable(mc5); 415 return 0; 416 } 417 418 #define MC5_INT_FATAL (F_PARITYERR | F_REQQPARERR | F_DISPQPARERR) 419 420 /* 421 * MC5 interrupt handler 422 */ 423 void t3_mc5_intr_handler(struct mc5 *mc5) 424 { 425 adapter_t *adap = mc5->adapter; 426 u32 cause = t3_read_reg(adap, A_MC5_DB_INT_CAUSE); 427 428 if ((cause & F_PARITYERR) && mc5->parity_enabled) { 429 CH_ALERT(adap, "MC5 parity error\n"); 430 mc5->stats.parity_err++; 431 } 432 433 if (cause & F_REQQPARERR) { 434 CH_ALERT(adap, "MC5 request queue parity error\n"); 435 mc5->stats.reqq_parity_err++; 436 } 437 438 if (cause & F_DISPQPARERR) { 439 CH_ALERT(adap, "MC5 dispatch queue parity error\n"); 440 mc5->stats.dispq_parity_err++; 441 } 442 443 if (cause & F_ACTRGNFULL) 444 mc5->stats.active_rgn_full++; 445 if (cause & F_NFASRCHFAIL) 446 mc5->stats.nfa_srch_err++; 447 if (cause & F_UNKNOWNCMD) 448 mc5->stats.unknown_cmd++; 449 if (cause & F_DELACTEMPTY) 450 mc5->stats.del_act_empty++; 451 if (cause & MC5_INT_FATAL) 452 t3_fatal_err(adap); 453 454 t3_write_reg(adap, A_MC5_DB_INT_CAUSE, cause); 455 } 456 457 void __devinit t3_mc5_prep(adapter_t *adapter, struct mc5 *mc5, int mode) 458 { 459 #define K * 1024 460 461 static unsigned int tcam_part_size[] = { /* in K 72-bit entries */ 462 64 K, 128 K, 256 K, 32 K 463 }; 464 465 #undef K 466 467 u32 cfg = t3_read_reg(adapter, A_MC5_DB_CONFIG); 468 469 mc5->adapter = adapter; 470 mc5->mode = (unsigned char) mode; 471 mc5->part_type = (unsigned char) G_TMTYPE(cfg); 472 if (cfg & F_TMTYPEHI) 473 mc5->part_type |= 4; 474 475 mc5->tcam_size = tcam_part_size[G_TMPARTSIZE(cfg)]; 476 if (mode == MC5_MODE_144_BIT) 477 mc5->tcam_size /= 2; 478 } 479