1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2004-2005 Nate Lawson (SDG) 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/cpu.h> 35 #include <sys/kernel.h> 36 #include <sys/malloc.h> 37 #include <sys/module.h> 38 #include <sys/pcpu.h> 39 #include <sys/sysctl.h> 40 #include <sys/systm.h> 41 42 #include <dev/pci/pcivar.h> 43 #include <machine/bus.h> 44 #include <machine/resource.h> 45 #include <sys/rman.h> 46 47 #include "cpufreq_if.h" 48 49 /* 50 * The SpeedStep ICH feature is a chipset-initiated voltage and frequency 51 * transition available on the ICH2M, 3M, and 4M. It is different from 52 * the newer Pentium-M SpeedStep feature. It offers only two levels of 53 * frequency/voltage. Often, the BIOS will select one of the levels via 54 * SMM code during the power-on process (i.e., choose a lower level if the 55 * system is off AC power.) 56 */ 57 58 struct ichss_softc { 59 device_t dev; 60 int bm_rid; /* Bus-mastering control (PM2REG). */ 61 struct resource *bm_reg; 62 int ctrl_rid; /* Control/status register. */ 63 struct resource *ctrl_reg; 64 struct cf_setting sets[2]; /* Only two settings. */ 65 }; 66 67 /* Supported PCI IDs. */ 68 #define PCI_VENDOR_INTEL 0x8086 69 #define PCI_DEV_82801BA 0x244c /* ICH2M */ 70 #define PCI_DEV_82801CA 0x248c /* ICH3M */ 71 #define PCI_DEV_82801DB 0x24cc /* ICH4M */ 72 #define PCI_DEV_82815_MC 0x1130 /* Unsupported/buggy part */ 73 74 /* PCI config registers for finding PMBASE and enabling SpeedStep. */ 75 #define ICHSS_PMBASE_OFFSET 0x40 76 #define ICHSS_PMCFG_OFFSET 0xa0 77 78 /* Values and masks. */ 79 #define ICHSS_ENABLE (1<<3) /* Enable SpeedStep control. */ 80 #define ICHSS_IO_REG 0x1 /* Access register via I/O space. */ 81 #define ICHSS_PMBASE_MASK 0xff80 /* PMBASE address bits. */ 82 #define ICHSS_CTRL_BIT 0x1 /* 0 is high speed, 1 is low. */ 83 #define ICHSS_BM_DISABLE 0x1 84 85 /* Offsets from PMBASE for various registers. */ 86 #define ICHSS_BM_OFFSET 0x20 87 #define ICHSS_CTRL_OFFSET 0x50 88 89 #define ICH_GET_REG(reg) \ 90 (bus_space_read_1(rman_get_bustag((reg)), \ 91 rman_get_bushandle((reg)), 0)) 92 #define ICH_SET_REG(reg, val) \ 93 (bus_space_write_1(rman_get_bustag((reg)), \ 94 rman_get_bushandle((reg)), 0, (val))) 95 96 static void ichss_identify(driver_t *driver, device_t parent); 97 static int ichss_probe(device_t dev); 98 static int ichss_attach(device_t dev); 99 static int ichss_detach(device_t dev); 100 static int ichss_settings(device_t dev, struct cf_setting *sets, 101 int *count); 102 static int ichss_set(device_t dev, const struct cf_setting *set); 103 static int ichss_get(device_t dev, struct cf_setting *set); 104 static int ichss_type(device_t dev, int *type); 105 106 static device_method_t ichss_methods[] = { 107 /* Device interface */ 108 DEVMETHOD(device_identify, ichss_identify), 109 DEVMETHOD(device_probe, ichss_probe), 110 DEVMETHOD(device_attach, ichss_attach), 111 DEVMETHOD(device_detach, ichss_detach), 112 113 /* cpufreq interface */ 114 DEVMETHOD(cpufreq_drv_set, ichss_set), 115 DEVMETHOD(cpufreq_drv_get, ichss_get), 116 DEVMETHOD(cpufreq_drv_type, ichss_type), 117 DEVMETHOD(cpufreq_drv_settings, ichss_settings), 118 DEVMETHOD_END 119 }; 120 static driver_t ichss_driver = { 121 "ichss", ichss_methods, sizeof(struct ichss_softc) 122 }; 123 static devclass_t ichss_devclass; 124 DRIVER_MODULE(ichss, cpu, ichss_driver, ichss_devclass, 0, 0); 125 126 static device_t ich_device; 127 128 #if 0 129 #define DPRINT(x...) printf(x) 130 #else 131 #define DPRINT(x...) 132 #endif 133 134 static void 135 ichss_identify(driver_t *driver, device_t parent) 136 { 137 device_t child; 138 uint32_t pmbase; 139 140 if (resource_disabled("ichss", 0)) 141 return; 142 143 /* 144 * It appears that ICH SpeedStep only requires a single CPU to 145 * set the value (since the chipset is shared by all CPUs.) 146 * Thus, we only add a child to cpu 0. 147 */ 148 if (device_get_unit(parent) != 0) 149 return; 150 151 /* Avoid duplicates. */ 152 if (device_find_child(parent, "ichss", -1)) 153 return; 154 155 /* 156 * ICH2/3/4-M I/O Controller Hub is at bus 0, slot 1F, function 0. 157 * E.g. see Section 6.1 "PCI Devices and Functions" and table 6.1 of 158 * Intel(r) 82801BA I/O Controller Hub 2 (ICH2) and Intel(r) 82801BAM 159 * I/O Controller Hub 2 Mobile (ICH2-M). 160 */ 161 ich_device = pci_find_bsf(0, 0x1f, 0); 162 if (ich_device == NULL || 163 pci_get_vendor(ich_device) != PCI_VENDOR_INTEL || 164 (pci_get_device(ich_device) != PCI_DEV_82801BA && 165 pci_get_device(ich_device) != PCI_DEV_82801CA && 166 pci_get_device(ich_device) != PCI_DEV_82801DB)) 167 return; 168 169 /* 170 * Certain systems with ICH2 and an Intel 82815_MC host bridge 171 * where the host bridge's revision is < 5 lockup if SpeedStep 172 * is used. 173 */ 174 if (pci_get_device(ich_device) == PCI_DEV_82801BA) { 175 device_t hostb; 176 177 hostb = pci_find_bsf(0, 0, 0); 178 if (hostb != NULL && 179 pci_get_vendor(hostb) == PCI_VENDOR_INTEL && 180 pci_get_device(hostb) == PCI_DEV_82815_MC && 181 pci_get_revid(hostb) < 5) 182 return; 183 } 184 185 /* Find the PMBASE register from our PCI config header. */ 186 pmbase = pci_read_config(ich_device, ICHSS_PMBASE_OFFSET, 187 sizeof(pmbase)); 188 if ((pmbase & ICHSS_IO_REG) == 0) { 189 printf("ichss: invalid PMBASE memory type\n"); 190 return; 191 } 192 pmbase &= ICHSS_PMBASE_MASK; 193 if (pmbase == 0) { 194 printf("ichss: invalid zero PMBASE address\n"); 195 return; 196 } 197 DPRINT("ichss: PMBASE is %#x\n", pmbase); 198 199 child = BUS_ADD_CHILD(parent, 20, "ichss", 0); 200 if (child == NULL) { 201 device_printf(parent, "add SpeedStep child failed\n"); 202 return; 203 } 204 205 /* Add the bus master arbitration and control registers. */ 206 bus_set_resource(child, SYS_RES_IOPORT, 0, pmbase + ICHSS_BM_OFFSET, 207 1); 208 bus_set_resource(child, SYS_RES_IOPORT, 1, pmbase + ICHSS_CTRL_OFFSET, 209 1); 210 } 211 212 static int 213 ichss_probe(device_t dev) 214 { 215 device_t est_dev, perf_dev; 216 int error, type; 217 218 /* 219 * If the ACPI perf driver has attached and is not just offering 220 * info, let it manage things. Also, if Enhanced SpeedStep is 221 * available, don't attach. 222 */ 223 perf_dev = device_find_child(device_get_parent(dev), "acpi_perf", -1); 224 if (perf_dev && device_is_attached(perf_dev)) { 225 error = CPUFREQ_DRV_TYPE(perf_dev, &type); 226 if (error == 0 && (type & CPUFREQ_FLAG_INFO_ONLY) == 0) 227 return (ENXIO); 228 } 229 est_dev = device_find_child(device_get_parent(dev), "est", -1); 230 if (est_dev && device_is_attached(est_dev)) 231 return (ENXIO); 232 233 device_set_desc(dev, "SpeedStep ICH"); 234 return (-1000); 235 } 236 237 static int 238 ichss_attach(device_t dev) 239 { 240 struct ichss_softc *sc; 241 uint16_t ss_en; 242 243 sc = device_get_softc(dev); 244 sc->dev = dev; 245 246 sc->bm_rid = 0; 247 sc->bm_reg = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &sc->bm_rid, 248 RF_ACTIVE); 249 if (sc->bm_reg == NULL) { 250 device_printf(dev, "failed to alloc BM arb register\n"); 251 return (ENXIO); 252 } 253 sc->ctrl_rid = 1; 254 sc->ctrl_reg = bus_alloc_resource_any(dev, SYS_RES_IOPORT, 255 &sc->ctrl_rid, RF_ACTIVE); 256 if (sc->ctrl_reg == NULL) { 257 device_printf(dev, "failed to alloc control register\n"); 258 bus_release_resource(dev, SYS_RES_IOPORT, sc->bm_rid, 259 sc->bm_reg); 260 return (ENXIO); 261 } 262 263 /* Activate SpeedStep control if not already enabled. */ 264 ss_en = pci_read_config(ich_device, ICHSS_PMCFG_OFFSET, sizeof(ss_en)); 265 if ((ss_en & ICHSS_ENABLE) == 0) { 266 device_printf(dev, "enabling SpeedStep support\n"); 267 pci_write_config(ich_device, ICHSS_PMCFG_OFFSET, 268 ss_en | ICHSS_ENABLE, sizeof(ss_en)); 269 } 270 271 /* Setup some defaults for our exported settings. */ 272 sc->sets[0].freq = CPUFREQ_VAL_UNKNOWN; 273 sc->sets[0].volts = CPUFREQ_VAL_UNKNOWN; 274 sc->sets[0].power = CPUFREQ_VAL_UNKNOWN; 275 sc->sets[0].lat = 1000; 276 sc->sets[0].dev = dev; 277 sc->sets[1] = sc->sets[0]; 278 cpufreq_register(dev); 279 280 return (0); 281 } 282 283 static int 284 ichss_detach(device_t dev) 285 { 286 /* TODO: teardown BM and CTRL registers. */ 287 return (ENXIO); 288 } 289 290 static int 291 ichss_settings(device_t dev, struct cf_setting *sets, int *count) 292 { 293 struct ichss_softc *sc; 294 struct cf_setting set; 295 int first, i; 296 297 if (sets == NULL || count == NULL) 298 return (EINVAL); 299 if (*count < 2) { 300 *count = 2; 301 return (E2BIG); 302 } 303 sc = device_get_softc(dev); 304 305 /* 306 * Estimate frequencies for both levels, temporarily switching to 307 * the other one if we haven't calibrated it yet. 308 */ 309 ichss_get(dev, &set); 310 for (i = 0; i < 2; i++) { 311 if (sc->sets[i].freq == CPUFREQ_VAL_UNKNOWN) { 312 first = (i == 0) ? 1 : 0; 313 ichss_set(dev, &sc->sets[i]); 314 ichss_set(dev, &sc->sets[first]); 315 } 316 } 317 318 bcopy(sc->sets, sets, sizeof(sc->sets)); 319 *count = 2; 320 321 return (0); 322 } 323 324 static int 325 ichss_set(device_t dev, const struct cf_setting *set) 326 { 327 struct ichss_softc *sc; 328 uint8_t bmval, new_val, old_val, req_val; 329 uint64_t rate; 330 register_t regs; 331 332 /* Look up appropriate bit value based on frequency. */ 333 sc = device_get_softc(dev); 334 if (CPUFREQ_CMP(set->freq, sc->sets[0].freq)) 335 req_val = 0; 336 else if (CPUFREQ_CMP(set->freq, sc->sets[1].freq)) 337 req_val = ICHSS_CTRL_BIT; 338 else 339 return (EINVAL); 340 DPRINT("ichss: requested setting %d\n", req_val); 341 342 /* Disable interrupts and get the other register contents. */ 343 regs = intr_disable(); 344 old_val = ICH_GET_REG(sc->ctrl_reg) & ~ICHSS_CTRL_BIT; 345 346 /* 347 * Disable bus master arbitration, write the new value to the control 348 * register, and then re-enable bus master arbitration. 349 */ 350 bmval = ICH_GET_REG(sc->bm_reg) | ICHSS_BM_DISABLE; 351 ICH_SET_REG(sc->bm_reg, bmval); 352 ICH_SET_REG(sc->ctrl_reg, old_val | req_val); 353 ICH_SET_REG(sc->bm_reg, bmval & ~ICHSS_BM_DISABLE); 354 355 /* Get the new value and re-enable interrupts. */ 356 new_val = ICH_GET_REG(sc->ctrl_reg); 357 intr_restore(regs); 358 359 /* Check if the desired state was indeed selected. */ 360 if (req_val != (new_val & ICHSS_CTRL_BIT)) { 361 device_printf(sc->dev, "transition to %d failed\n", req_val); 362 return (ENXIO); 363 } 364 365 /* Re-initialize our cycle counter if we don't know this new state. */ 366 if (sc->sets[req_val].freq == CPUFREQ_VAL_UNKNOWN) { 367 cpu_est_clockrate(0, &rate); 368 sc->sets[req_val].freq = rate / 1000000; 369 DPRINT("ichss: set calibrated new rate of %d\n", 370 sc->sets[req_val].freq); 371 } 372 373 return (0); 374 } 375 376 static int 377 ichss_get(device_t dev, struct cf_setting *set) 378 { 379 struct ichss_softc *sc; 380 uint64_t rate; 381 uint8_t state; 382 383 sc = device_get_softc(dev); 384 state = ICH_GET_REG(sc->ctrl_reg) & ICHSS_CTRL_BIT; 385 386 /* If we haven't changed settings yet, estimate the current value. */ 387 if (sc->sets[state].freq == CPUFREQ_VAL_UNKNOWN) { 388 cpu_est_clockrate(0, &rate); 389 sc->sets[state].freq = rate / 1000000; 390 DPRINT("ichss: get calibrated new rate of %d\n", 391 sc->sets[state].freq); 392 } 393 *set = sc->sets[state]; 394 395 return (0); 396 } 397 398 static int 399 ichss_type(device_t dev, int *type) 400 { 401 402 if (type == NULL) 403 return (EINVAL); 404 405 *type = CPUFREQ_TYPE_ABSOLUTE; 406 return (0); 407 } 408