1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2004-2005 Nate Lawson (SDG) 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #include <sys/param.h> 33 #include <sys/bus.h> 34 #include <sys/cpu.h> 35 #include <sys/kernel.h> 36 #include <sys/malloc.h> 37 #include <sys/module.h> 38 #include <sys/pcpu.h> 39 #include <sys/sysctl.h> 40 #include <sys/systm.h> 41 42 #include <dev/pci/pcivar.h> 43 #include <machine/bus.h> 44 #include <machine/resource.h> 45 #include <sys/rman.h> 46 47 #include "cpufreq_if.h" 48 49 /* 50 * The SpeedStep ICH feature is a chipset-initiated voltage and frequency 51 * transition available on the ICH2M, 3M, and 4M. It is different from 52 * the newer Pentium-M SpeedStep feature. It offers only two levels of 53 * frequency/voltage. Often, the BIOS will select one of the levels via 54 * SMM code during the power-on process (i.e., choose a lower level if the 55 * system is off AC power.) 56 */ 57 58 struct ichss_softc { 59 device_t dev; 60 int bm_rid; /* Bus-mastering control (PM2REG). */ 61 struct resource *bm_reg; 62 int ctrl_rid; /* Control/status register. */ 63 struct resource *ctrl_reg; 64 struct cf_setting sets[2]; /* Only two settings. */ 65 }; 66 67 /* Supported PCI IDs. */ 68 #define PCI_VENDOR_INTEL 0x8086 69 #define PCI_DEV_82801BA 0x244c /* ICH2M */ 70 #define PCI_DEV_82801CA 0x248c /* ICH3M */ 71 #define PCI_DEV_82801DB 0x24cc /* ICH4M */ 72 #define PCI_DEV_82815_MC 0x1130 /* Unsupported/buggy part */ 73 74 /* PCI config registers for finding PMBASE and enabling SpeedStep. */ 75 #define ICHSS_PMBASE_OFFSET 0x40 76 #define ICHSS_PMCFG_OFFSET 0xa0 77 78 /* Values and masks. */ 79 #define ICHSS_ENABLE (1<<3) /* Enable SpeedStep control. */ 80 #define ICHSS_IO_REG 0x1 /* Access register via I/O space. */ 81 #define ICHSS_PMBASE_MASK 0xff80 /* PMBASE address bits. */ 82 #define ICHSS_CTRL_BIT 0x1 /* 0 is high speed, 1 is low. */ 83 #define ICHSS_BM_DISABLE 0x1 84 85 /* Offsets from PMBASE for various registers. */ 86 #define ICHSS_BM_OFFSET 0x20 87 #define ICHSS_CTRL_OFFSET 0x50 88 89 #define ICH_GET_REG(reg) \ 90 (bus_space_read_1(rman_get_bustag((reg)), \ 91 rman_get_bushandle((reg)), 0)) 92 #define ICH_SET_REG(reg, val) \ 93 (bus_space_write_1(rman_get_bustag((reg)), \ 94 rman_get_bushandle((reg)), 0, (val))) 95 96 static void ichss_identify(driver_t *driver, device_t parent); 97 static int ichss_probe(device_t dev); 98 static int ichss_attach(device_t dev); 99 static int ichss_detach(device_t dev); 100 static int ichss_settings(device_t dev, struct cf_setting *sets, 101 int *count); 102 static int ichss_set(device_t dev, const struct cf_setting *set); 103 static int ichss_get(device_t dev, struct cf_setting *set); 104 static int ichss_type(device_t dev, int *type); 105 106 static device_method_t ichss_methods[] = { 107 /* Device interface */ 108 DEVMETHOD(device_identify, ichss_identify), 109 DEVMETHOD(device_probe, ichss_probe), 110 DEVMETHOD(device_attach, ichss_attach), 111 DEVMETHOD(device_detach, ichss_detach), 112 113 /* cpufreq interface */ 114 DEVMETHOD(cpufreq_drv_set, ichss_set), 115 DEVMETHOD(cpufreq_drv_get, ichss_get), 116 DEVMETHOD(cpufreq_drv_type, ichss_type), 117 DEVMETHOD(cpufreq_drv_settings, ichss_settings), 118 DEVMETHOD_END 119 }; 120 121 static driver_t ichss_driver = { 122 "ichss", ichss_methods, sizeof(struct ichss_softc) 123 }; 124 125 DRIVER_MODULE(ichss, cpu, ichss_driver, 0, 0); 126 127 static device_t ich_device; 128 129 #if 0 130 #define DPRINT(x...) printf(x) 131 #else 132 #define DPRINT(x...) 133 #endif 134 135 static void 136 ichss_identify(driver_t *driver, device_t parent) 137 { 138 device_t child; 139 uint32_t pmbase; 140 141 if (resource_disabled("ichss", 0)) 142 return; 143 144 /* 145 * It appears that ICH SpeedStep only requires a single CPU to 146 * set the value (since the chipset is shared by all CPUs.) 147 * Thus, we only add a child to cpu 0. 148 */ 149 if (device_get_unit(parent) != 0) 150 return; 151 152 /* Avoid duplicates. */ 153 if (device_find_child(parent, "ichss", -1)) 154 return; 155 156 /* 157 * ICH2/3/4-M I/O Controller Hub is at bus 0, slot 1F, function 0. 158 * E.g. see Section 6.1 "PCI Devices and Functions" and table 6.1 of 159 * Intel(r) 82801BA I/O Controller Hub 2 (ICH2) and Intel(r) 82801BAM 160 * I/O Controller Hub 2 Mobile (ICH2-M). 161 */ 162 ich_device = pci_find_bsf(0, 0x1f, 0); 163 if (ich_device == NULL || 164 pci_get_vendor(ich_device) != PCI_VENDOR_INTEL || 165 (pci_get_device(ich_device) != PCI_DEV_82801BA && 166 pci_get_device(ich_device) != PCI_DEV_82801CA && 167 pci_get_device(ich_device) != PCI_DEV_82801DB)) 168 return; 169 170 /* 171 * Certain systems with ICH2 and an Intel 82815_MC host bridge 172 * where the host bridge's revision is < 5 lockup if SpeedStep 173 * is used. 174 */ 175 if (pci_get_device(ich_device) == PCI_DEV_82801BA) { 176 device_t hostb; 177 178 hostb = pci_find_bsf(0, 0, 0); 179 if (hostb != NULL && 180 pci_get_vendor(hostb) == PCI_VENDOR_INTEL && 181 pci_get_device(hostb) == PCI_DEV_82815_MC && 182 pci_get_revid(hostb) < 5) 183 return; 184 } 185 186 /* Find the PMBASE register from our PCI config header. */ 187 pmbase = pci_read_config(ich_device, ICHSS_PMBASE_OFFSET, 188 sizeof(pmbase)); 189 if ((pmbase & ICHSS_IO_REG) == 0) { 190 printf("ichss: invalid PMBASE memory type\n"); 191 return; 192 } 193 pmbase &= ICHSS_PMBASE_MASK; 194 if (pmbase == 0) { 195 printf("ichss: invalid zero PMBASE address\n"); 196 return; 197 } 198 DPRINT("ichss: PMBASE is %#x\n", pmbase); 199 200 child = BUS_ADD_CHILD(parent, 20, "ichss", 0); 201 if (child == NULL) { 202 device_printf(parent, "add SpeedStep child failed\n"); 203 return; 204 } 205 206 /* Add the bus master arbitration and control registers. */ 207 bus_set_resource(child, SYS_RES_IOPORT, 0, pmbase + ICHSS_BM_OFFSET, 208 1); 209 bus_set_resource(child, SYS_RES_IOPORT, 1, pmbase + ICHSS_CTRL_OFFSET, 210 1); 211 } 212 213 static int 214 ichss_probe(device_t dev) 215 { 216 device_t est_dev, perf_dev; 217 int error, type; 218 219 /* 220 * If the ACPI perf driver has attached and is not just offering 221 * info, let it manage things. Also, if Enhanced SpeedStep is 222 * available, don't attach. 223 */ 224 perf_dev = device_find_child(device_get_parent(dev), "acpi_perf", -1); 225 if (perf_dev && device_is_attached(perf_dev)) { 226 error = CPUFREQ_DRV_TYPE(perf_dev, &type); 227 if (error == 0 && (type & CPUFREQ_FLAG_INFO_ONLY) == 0) 228 return (ENXIO); 229 } 230 est_dev = device_find_child(device_get_parent(dev), "est", -1); 231 if (est_dev && device_is_attached(est_dev)) 232 return (ENXIO); 233 234 device_set_desc(dev, "SpeedStep ICH"); 235 return (-1000); 236 } 237 238 static int 239 ichss_attach(device_t dev) 240 { 241 struct ichss_softc *sc; 242 uint16_t ss_en; 243 244 sc = device_get_softc(dev); 245 sc->dev = dev; 246 247 sc->bm_rid = 0; 248 sc->bm_reg = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &sc->bm_rid, 249 RF_ACTIVE); 250 if (sc->bm_reg == NULL) { 251 device_printf(dev, "failed to alloc BM arb register\n"); 252 return (ENXIO); 253 } 254 sc->ctrl_rid = 1; 255 sc->ctrl_reg = bus_alloc_resource_any(dev, SYS_RES_IOPORT, 256 &sc->ctrl_rid, RF_ACTIVE); 257 if (sc->ctrl_reg == NULL) { 258 device_printf(dev, "failed to alloc control register\n"); 259 bus_release_resource(dev, SYS_RES_IOPORT, sc->bm_rid, 260 sc->bm_reg); 261 return (ENXIO); 262 } 263 264 /* Activate SpeedStep control if not already enabled. */ 265 ss_en = pci_read_config(ich_device, ICHSS_PMCFG_OFFSET, sizeof(ss_en)); 266 if ((ss_en & ICHSS_ENABLE) == 0) { 267 device_printf(dev, "enabling SpeedStep support\n"); 268 pci_write_config(ich_device, ICHSS_PMCFG_OFFSET, 269 ss_en | ICHSS_ENABLE, sizeof(ss_en)); 270 } 271 272 /* Setup some defaults for our exported settings. */ 273 sc->sets[0].freq = CPUFREQ_VAL_UNKNOWN; 274 sc->sets[0].volts = CPUFREQ_VAL_UNKNOWN; 275 sc->sets[0].power = CPUFREQ_VAL_UNKNOWN; 276 sc->sets[0].lat = 1000; 277 sc->sets[0].dev = dev; 278 sc->sets[1] = sc->sets[0]; 279 cpufreq_register(dev); 280 281 return (0); 282 } 283 284 static int 285 ichss_detach(device_t dev) 286 { 287 /* TODO: teardown BM and CTRL registers. */ 288 return (ENXIO); 289 } 290 291 static int 292 ichss_settings(device_t dev, struct cf_setting *sets, int *count) 293 { 294 struct ichss_softc *sc; 295 struct cf_setting set; 296 int first, i; 297 298 if (sets == NULL || count == NULL) 299 return (EINVAL); 300 if (*count < 2) { 301 *count = 2; 302 return (E2BIG); 303 } 304 sc = device_get_softc(dev); 305 306 /* 307 * Estimate frequencies for both levels, temporarily switching to 308 * the other one if we haven't calibrated it yet. 309 */ 310 ichss_get(dev, &set); 311 for (i = 0; i < 2; i++) { 312 if (sc->sets[i].freq == CPUFREQ_VAL_UNKNOWN) { 313 first = (i == 0) ? 1 : 0; 314 ichss_set(dev, &sc->sets[i]); 315 ichss_set(dev, &sc->sets[first]); 316 } 317 } 318 319 bcopy(sc->sets, sets, sizeof(sc->sets)); 320 *count = 2; 321 322 return (0); 323 } 324 325 static int 326 ichss_set(device_t dev, const struct cf_setting *set) 327 { 328 struct ichss_softc *sc; 329 uint8_t bmval, new_val, old_val, req_val; 330 uint64_t rate; 331 register_t regs; 332 333 /* Look up appropriate bit value based on frequency. */ 334 sc = device_get_softc(dev); 335 if (CPUFREQ_CMP(set->freq, sc->sets[0].freq)) 336 req_val = 0; 337 else if (CPUFREQ_CMP(set->freq, sc->sets[1].freq)) 338 req_val = ICHSS_CTRL_BIT; 339 else 340 return (EINVAL); 341 DPRINT("ichss: requested setting %d\n", req_val); 342 343 /* Disable interrupts and get the other register contents. */ 344 regs = intr_disable(); 345 old_val = ICH_GET_REG(sc->ctrl_reg) & ~ICHSS_CTRL_BIT; 346 347 /* 348 * Disable bus master arbitration, write the new value to the control 349 * register, and then re-enable bus master arbitration. 350 */ 351 bmval = ICH_GET_REG(sc->bm_reg) | ICHSS_BM_DISABLE; 352 ICH_SET_REG(sc->bm_reg, bmval); 353 ICH_SET_REG(sc->ctrl_reg, old_val | req_val); 354 ICH_SET_REG(sc->bm_reg, bmval & ~ICHSS_BM_DISABLE); 355 356 /* Get the new value and re-enable interrupts. */ 357 new_val = ICH_GET_REG(sc->ctrl_reg); 358 intr_restore(regs); 359 360 /* Check if the desired state was indeed selected. */ 361 if (req_val != (new_val & ICHSS_CTRL_BIT)) { 362 device_printf(sc->dev, "transition to %d failed\n", req_val); 363 return (ENXIO); 364 } 365 366 /* Re-initialize our cycle counter if we don't know this new state. */ 367 if (sc->sets[req_val].freq == CPUFREQ_VAL_UNKNOWN) { 368 cpu_est_clockrate(0, &rate); 369 sc->sets[req_val].freq = rate / 1000000; 370 DPRINT("ichss: set calibrated new rate of %d\n", 371 sc->sets[req_val].freq); 372 } 373 374 return (0); 375 } 376 377 static int 378 ichss_get(device_t dev, struct cf_setting *set) 379 { 380 struct ichss_softc *sc; 381 uint64_t rate; 382 uint8_t state; 383 384 sc = device_get_softc(dev); 385 state = ICH_GET_REG(sc->ctrl_reg) & ICHSS_CTRL_BIT; 386 387 /* If we haven't changed settings yet, estimate the current value. */ 388 if (sc->sets[state].freq == CPUFREQ_VAL_UNKNOWN) { 389 cpu_est_clockrate(0, &rate); 390 sc->sets[state].freq = rate / 1000000; 391 DPRINT("ichss: get calibrated new rate of %d\n", 392 sc->sets[state].freq); 393 } 394 *set = sc->sets[state]; 395 396 return (0); 397 } 398 399 static int 400 ichss_type(device_t dev, int *type) 401 { 402 403 if (type == NULL) 404 return (EINVAL); 405 406 *type = CPUFREQ_TYPE_ABSOLUTE; 407 return (0); 408 } 409