1 /*- 2 * Copyright (c) 2004-2005 Nate Lawson (SDG) 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include <sys/param.h> 31 #include <sys/bus.h> 32 #include <sys/cpu.h> 33 #include <sys/kernel.h> 34 #include <sys/malloc.h> 35 #include <sys/module.h> 36 #include <sys/pcpu.h> 37 #include <sys/sysctl.h> 38 #include <sys/systm.h> 39 40 #include <dev/pci/pcivar.h> 41 #include <machine/bus.h> 42 #include <machine/clock.h> 43 #include <machine/resource.h> 44 #include <sys/rman.h> 45 46 #include "cpufreq_if.h" 47 48 /* 49 * The SpeedStep ICH feature is a chipset-initiated voltage and frequency 50 * transition available on the ICH2M, 3M, and 4M. It is different from 51 * the newer Pentium-M SpeedStep feature. It offers only two levels of 52 * frequency/voltage. Often, the BIOS will select one of the levels via 53 * SMM code during the power-on process (i.e., choose a lower level if the 54 * system is off AC power.) 55 */ 56 57 struct ichss_softc { 58 device_t dev; 59 int bm_rid; /* Bus-mastering control (PM2REG). */ 60 struct resource *bm_reg; 61 int ctrl_rid; /* Control/status register. */ 62 struct resource *ctrl_reg; 63 struct cf_setting sets[2]; /* Only two settings. */ 64 }; 65 66 /* Supported PCI IDs. */ 67 #define PCI_VENDOR_INTEL 0x8086 68 #define PCI_DEV_82801BA 0x244c /* ICH2M */ 69 #define PCI_DEV_82801CA 0x248c /* ICH3M */ 70 #define PCI_DEV_82801DB 0x24cc /* ICH4M */ 71 #define PCI_DEV_82815BA 0x1130 /* Unsupported/buggy part */ 72 73 /* PCI config registers for finding PMBASE and enabling SpeedStep. */ 74 #define ICHSS_PMBASE_OFFSET 0x40 75 #define ICHSS_PMCFG_OFFSET 0xa0 76 77 /* Values and masks. */ 78 #define ICHSS_ENABLE (1<<3) /* Enable SpeedStep control. */ 79 #define ICHSS_IO_REG 0x1 /* Access register via I/O space. */ 80 #define ICHSS_PMBASE_MASK 0xff80 /* PMBASE address bits. */ 81 #define ICHSS_CTRL_BIT 0x1 /* 0 is high speed, 1 is low. */ 82 #define ICHSS_BM_DISABLE 0x1 83 84 /* Offsets from PMBASE for various registers. */ 85 #define ICHSS_BM_OFFSET 0x20 86 #define ICHSS_CTRL_OFFSET 0x50 87 88 #define ICH_GET_REG(reg) \ 89 (bus_space_read_1(rman_get_bustag((reg)), \ 90 rman_get_bushandle((reg)), 0)) 91 #define ICH_SET_REG(reg, val) \ 92 (bus_space_write_1(rman_get_bustag((reg)), \ 93 rman_get_bushandle((reg)), 0, (val))) 94 95 static int ichss_pci_probe(device_t dev); 96 static int ichss_probe(device_t dev); 97 static int ichss_attach(device_t dev); 98 static int ichss_detach(device_t dev); 99 static int ichss_settings(device_t dev, struct cf_setting *sets, 100 int *count, int *type); 101 static int ichss_set(device_t dev, const struct cf_setting *set); 102 static int ichss_get(device_t dev, struct cf_setting *set); 103 104 static device_method_t ichss_methods[] = { 105 /* Device interface */ 106 DEVMETHOD(device_probe, ichss_probe), 107 DEVMETHOD(device_attach, ichss_attach), 108 DEVMETHOD(device_detach, ichss_detach), 109 110 /* cpufreq interface */ 111 DEVMETHOD(cpufreq_drv_set, ichss_set), 112 DEVMETHOD(cpufreq_drv_get, ichss_get), 113 DEVMETHOD(cpufreq_drv_settings, ichss_settings), 114 {0, 0} 115 }; 116 static driver_t ichss_driver = { 117 "ichss", ichss_methods, sizeof(struct ichss_softc) 118 }; 119 static devclass_t ichss_devclass; 120 DRIVER_MODULE(ichss, cpu, ichss_driver, ichss_devclass, 0, 0); 121 122 static device_method_t ichss_pci_methods[] = { 123 DEVMETHOD(device_probe, ichss_pci_probe), 124 {0, 0} 125 }; 126 static driver_t ichss_pci_driver = { 127 "ichss_pci", ichss_pci_methods, 0 128 }; 129 static devclass_t ichss_pci_devclass; 130 DRIVER_MODULE(ichss_pci, pci, ichss_pci_driver, ichss_pci_devclass, 0, 0); 131 132 #if 0 133 #define DPRINT(x...) printf(x) 134 #else 135 #define DPRINT(x...) 136 #endif 137 138 /* 139 * We detect the chipset by looking for its LPC bus ID during the PCI 140 * scan and reading its config registers during the probe. However, 141 * we add the ichss child under the cpu device since even though the 142 * chipset provides the control, it really affects the cpu only. 143 * 144 * XXX This approach does not work if the module is loaded after boot. 145 */ 146 static int 147 ichss_pci_probe(device_t dev) 148 { 149 device_t child, parent; 150 uint32_t pmbase; 151 uint16_t ss_en; 152 153 /* 154 * TODO: add a quirk to disable if we see the 82815_MC along 155 * with the 82801BA and revision < 5. 156 */ 157 if (pci_get_vendor(dev) != PCI_VENDOR_INTEL || 158 (pci_get_device(dev) != PCI_DEV_82801BA && 159 pci_get_device(dev) != PCI_DEV_82801CA && 160 pci_get_device(dev) != PCI_DEV_82801DB)) 161 return (ENXIO); 162 163 /* Only one CPU is supported for this hardware. */ 164 if (devclass_get_device(ichss_devclass, 0)) 165 return (ENXIO); 166 167 /* Add a child under the CPU parent. */ 168 parent = devclass_get_device(devclass_find("cpu"), 0); 169 KASSERT(parent != NULL, ("cpu parent is NULL")); 170 child = BUS_ADD_CHILD(parent, 0, "ichss", 0); 171 if (child == NULL) { 172 device_printf(parent, "add SpeedStep child failed\n"); 173 return (ENXIO); 174 } 175 176 /* Find the PMBASE register from our PCI config header. */ 177 pmbase = pci_read_config(dev, ICHSS_PMBASE_OFFSET, sizeof(pmbase)); 178 if ((pmbase & ICHSS_IO_REG) == 0) { 179 printf("ichss: invalid PMBASE memory type\n"); 180 return (ENXIO); 181 } 182 pmbase &= ICHSS_PMBASE_MASK; 183 if (pmbase == 0) { 184 printf("ichss: invalid zero PMBASE address\n"); 185 return (ENXIO); 186 } 187 DPRINT("ichss: PMBASE is %#x\n", pmbase); 188 189 /* Add the bus master arbitration and control registers. */ 190 bus_set_resource(child, SYS_RES_IOPORT, 0, pmbase + ICHSS_BM_OFFSET, 191 1); 192 bus_set_resource(child, SYS_RES_IOPORT, 1, pmbase + ICHSS_CTRL_OFFSET, 193 1); 194 195 /* Activate SpeedStep control if not already enabled. */ 196 ss_en = pci_read_config(dev, ICHSS_PMCFG_OFFSET, sizeof(ss_en)); 197 if ((ss_en & ICHSS_ENABLE) == 0) { 198 printf("ichss: enabling SpeedStep support\n"); 199 pci_write_config(dev, ICHSS_PMCFG_OFFSET, 200 ss_en | ICHSS_ENABLE, sizeof(ss_en)); 201 } 202 203 /* Attach the new CPU child now. */ 204 device_probe_and_attach(child); 205 206 return (ENXIO); 207 } 208 209 static int 210 ichss_probe(device_t dev) 211 { 212 device_t perf_dev; 213 214 /* If the ACPI perf driver has attached, let it manage things. */ 215 perf_dev = devclass_get_device(devclass_find("acpi_perf"), 0); 216 if (perf_dev && device_is_attached(perf_dev)) 217 return (ENXIO); 218 219 device_set_desc(dev, "SpeedStep ICH"); 220 return (-1000); 221 } 222 223 static int 224 ichss_attach(device_t dev) 225 { 226 struct ichss_softc *sc; 227 228 sc = device_get_softc(dev); 229 sc->dev = dev; 230 231 sc->bm_rid = 0; 232 sc->bm_reg = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &sc->bm_rid, 233 RF_ACTIVE); 234 if (sc->bm_reg == NULL) { 235 device_printf(dev, "failed to alloc BM arb register\n"); 236 return (ENXIO); 237 } 238 sc->ctrl_rid = 1; 239 sc->ctrl_reg = bus_alloc_resource_any(dev, SYS_RES_IOPORT, 240 &sc->ctrl_rid, RF_ACTIVE); 241 if (sc->ctrl_reg == NULL) { 242 device_printf(dev, "failed to alloc control register\n"); 243 bus_release_resource(dev, SYS_RES_IOPORT, sc->bm_rid, 244 sc->bm_reg); 245 return (ENXIO); 246 } 247 248 /* Setup some defaults for our exported settings. */ 249 sc->sets[0].freq = CPUFREQ_VAL_UNKNOWN; 250 sc->sets[0].volts = CPUFREQ_VAL_UNKNOWN; 251 sc->sets[0].power = CPUFREQ_VAL_UNKNOWN; 252 sc->sets[0].lat = 1000; 253 sc->sets[0].dev = dev; 254 sc->sets[1] = sc->sets[0]; 255 cpufreq_register(dev); 256 257 return (0); 258 } 259 260 static int 261 ichss_detach(device_t dev) 262 { 263 /* TODO: teardown BM and CTRL registers. */ 264 return (ENXIO); 265 } 266 267 static int 268 ichss_settings(device_t dev, struct cf_setting *sets, int *count, int *type) 269 { 270 struct ichss_softc *sc; 271 struct cf_setting set; 272 int first, i; 273 274 if (sets == NULL || count == NULL) 275 return (EINVAL); 276 if (*count < 2) { 277 *count = 2; 278 return (E2BIG); 279 } 280 sc = device_get_softc(dev); 281 282 /* 283 * Estimate frequencies for both levels, temporarily switching to 284 * the other one if we haven't calibrated it yet. 285 */ 286 ichss_get(dev, &set); 287 for (i = 0; i < 2; i++) { 288 if (sc->sets[i].freq == CPUFREQ_VAL_UNKNOWN) { 289 first = (i == 0) ? 1 : 0; 290 ichss_set(dev, &sc->sets[i]); 291 ichss_set(dev, &sc->sets[first]); 292 } 293 } 294 295 bcopy(sc->sets, sets, sizeof(sc->sets)); 296 *count = 2; 297 *type = CPUFREQ_TYPE_ABSOLUTE; 298 299 return (0); 300 } 301 302 static int 303 ichss_set(device_t dev, const struct cf_setting *set) 304 { 305 struct ichss_softc *sc; 306 uint8_t bmval, new_val, old_val, req_val; 307 uint64_t rate; 308 register_t regs; 309 310 /* Look up appropriate bit value based on frequency. */ 311 sc = device_get_softc(dev); 312 if (CPUFREQ_CMP(set->freq, sc->sets[0].freq)) 313 req_val = 0; 314 else if (CPUFREQ_CMP(set->freq, sc->sets[1].freq)) 315 req_val = ICHSS_CTRL_BIT; 316 else 317 return (EINVAL); 318 DPRINT("ichss: requested setting %d\n", req_val); 319 320 /* Disable interrupts and get the other register contents. */ 321 regs = intr_disable(); 322 old_val = ICH_GET_REG(sc->ctrl_reg) & ~ICHSS_CTRL_BIT; 323 324 /* 325 * Disable bus master arbitration, write the new value to the control 326 * register, and then re-enable bus master arbitration. 327 */ 328 bmval = ICH_GET_REG(sc->bm_reg) | ICHSS_BM_DISABLE; 329 ICH_SET_REG(sc->bm_reg, bmval); 330 ICH_SET_REG(sc->ctrl_reg, old_val | req_val); 331 ICH_SET_REG(sc->bm_reg, bmval & ~ICHSS_BM_DISABLE); 332 333 /* Get the new value and re-enable interrupts. */ 334 new_val = ICH_GET_REG(sc->ctrl_reg); 335 intr_restore(regs); 336 337 /* Check if the desired state was indeed selected. */ 338 if (req_val != (new_val & ICHSS_CTRL_BIT)) { 339 device_printf(sc->dev, "transition to %d failed\n", req_val); 340 return (ENXIO); 341 } 342 343 /* Re-initialize our cycle counter if we don't know this new state. */ 344 if (sc->sets[req_val].freq == CPUFREQ_VAL_UNKNOWN) { 345 cpu_est_clockrate(0, &rate); 346 sc->sets[req_val].freq = rate / 1000000; 347 DPRINT("ichss: set calibrated new rate of %d\n", 348 sc->sets[req_val].freq); 349 } 350 351 return (0); 352 } 353 354 static int 355 ichss_get(device_t dev, struct cf_setting *set) 356 { 357 struct ichss_softc *sc; 358 uint64_t rate; 359 uint8_t state; 360 361 sc = device_get_softc(dev); 362 state = ICH_GET_REG(sc->ctrl_reg) & ICHSS_CTRL_BIT; 363 364 /* If we haven't changed settings yet, estimate the current value. */ 365 if (sc->sets[state].freq == CPUFREQ_VAL_UNKNOWN) { 366 cpu_est_clockrate(0, &rate); 367 sc->sets[state].freq = rate / 1000000; 368 DPRINT("ichss: get calibrated new rate of %d\n", 369 sc->sets[state].freq); 370 } 371 *set = sc->sets[state]; 372 373 return (0); 374 } 375