1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2007, 2008 Rui Paulo <rpaulo@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 17 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 18 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 19 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 20 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 21 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 22 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 24 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 25 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 * POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 /* 30 * Device driver for Intel's On Die thermal sensor via MSR. 31 * First introduced in Intel's Core line of processors. 32 */ 33 34 #include <sys/cdefs.h> 35 __FBSDID("$FreeBSD$"); 36 37 #include <sys/param.h> 38 #include <sys/bus.h> 39 #include <sys/systm.h> 40 #include <sys/types.h> 41 #include <sys/module.h> 42 #include <sys/conf.h> 43 #include <sys/kernel.h> 44 #include <sys/sysctl.h> 45 #include <sys/proc.h> /* for curthread */ 46 #include <sys/sched.h> 47 48 #include <machine/specialreg.h> 49 #include <machine/cpufunc.h> 50 #include <machine/cputypes.h> 51 #include <machine/md_var.h> 52 53 #define TZ_ZEROC 2731 54 55 #define THERM_STATUS_LOG 0x02 56 #define THERM_STATUS 0x01 57 #define THERM_STATUS_TEMP_SHIFT 16 58 #define THERM_STATUS_TEMP_MASK 0x7f 59 #define THERM_STATUS_RES_SHIFT 27 60 #define THERM_STATUS_RES_MASK 0x0f 61 #define THERM_STATUS_VALID_SHIFT 31 62 #define THERM_STATUS_VALID_MASK 0x01 63 64 struct coretemp_softc { 65 device_t sc_dev; 66 int sc_tjmax; 67 unsigned int sc_throttle_log; 68 }; 69 70 /* 71 * Device methods. 72 */ 73 static void coretemp_identify(driver_t *driver, device_t parent); 74 static int coretemp_probe(device_t dev); 75 static int coretemp_attach(device_t dev); 76 static int coretemp_detach(device_t dev); 77 78 static uint64_t coretemp_get_thermal_msr(int cpu); 79 static void coretemp_clear_thermal_msr(int cpu); 80 static int coretemp_get_val_sysctl(SYSCTL_HANDLER_ARGS); 81 static int coretemp_throttle_log_sysctl(SYSCTL_HANDLER_ARGS); 82 83 static device_method_t coretemp_methods[] = { 84 /* Device interface */ 85 DEVMETHOD(device_identify, coretemp_identify), 86 DEVMETHOD(device_probe, coretemp_probe), 87 DEVMETHOD(device_attach, coretemp_attach), 88 DEVMETHOD(device_detach, coretemp_detach), 89 90 DEVMETHOD_END 91 }; 92 93 static driver_t coretemp_driver = { 94 "coretemp", 95 coretemp_methods, 96 sizeof(struct coretemp_softc), 97 }; 98 99 enum therm_info { 100 CORETEMP_TEMP, 101 CORETEMP_DELTA, 102 CORETEMP_RESOLUTION, 103 CORETEMP_TJMAX, 104 }; 105 106 static devclass_t coretemp_devclass; 107 DRIVER_MODULE(coretemp, cpu, coretemp_driver, coretemp_devclass, NULL, 108 NULL); 109 110 static void 111 coretemp_identify(driver_t *driver, device_t parent) 112 { 113 device_t child; 114 u_int regs[4]; 115 116 /* Make sure we're not being doubly invoked. */ 117 if (device_find_child(parent, "coretemp", -1) != NULL) 118 return; 119 120 /* Check that CPUID 0x06 is supported and the vendor is Intel.*/ 121 if (cpu_high < 6 || cpu_vendor_id != CPU_VENDOR_INTEL) 122 return; 123 /* 124 * CPUID 0x06 returns 1 if the processor has on-die thermal 125 * sensors. EBX[0:3] contains the number of sensors. 126 */ 127 do_cpuid(0x06, regs); 128 if ((regs[0] & 0x1) != 1) 129 return; 130 131 /* 132 * We add a child for each CPU since settings must be performed 133 * on each CPU in the SMP case. 134 */ 135 child = device_add_child(parent, "coretemp", -1); 136 if (child == NULL) 137 device_printf(parent, "add coretemp child failed\n"); 138 } 139 140 static int 141 coretemp_probe(device_t dev) 142 { 143 if (resource_disabled("coretemp", 0)) 144 return (ENXIO); 145 146 device_set_desc(dev, "CPU On-Die Thermal Sensors"); 147 148 return (BUS_PROBE_GENERIC); 149 } 150 151 static int 152 coretemp_attach(device_t dev) 153 { 154 struct coretemp_softc *sc = device_get_softc(dev); 155 device_t pdev; 156 uint64_t msr; 157 int cpu_model, cpu_stepping; 158 int ret, tjtarget; 159 struct sysctl_oid *oid; 160 struct sysctl_ctx_list *ctx; 161 162 sc->sc_dev = dev; 163 pdev = device_get_parent(dev); 164 cpu_model = CPUID_TO_MODEL(cpu_id); 165 cpu_stepping = cpu_id & CPUID_STEPPING; 166 167 /* 168 * Some CPUs, namely the PIII, don't have thermal sensors, but 169 * report them when the CPUID check is performed in 170 * coretemp_identify(). This leads to a later GPF when the sensor 171 * is queried via a MSR, so we stop here. 172 */ 173 if (cpu_model < 0xe) 174 return (ENXIO); 175 176 #if 0 /* 177 * XXXrpaulo: I have this CPU model and when it returns from C3 178 * coretemp continues to function properly. 179 */ 180 181 /* 182 * Check for errata AE18. 183 * "Processor Digital Thermal Sensor (DTS) Readout stops 184 * updating upon returning from C3/C4 state." 185 * 186 * Adapted from the Linux coretemp driver. 187 */ 188 if (cpu_model == 0xe && cpu_stepping < 0xc) { 189 msr = rdmsr(MSR_BIOS_SIGN); 190 msr = msr >> 32; 191 if (msr < 0x39) { 192 device_printf(dev, "not supported (Intel errata " 193 "AE18), try updating your BIOS\n"); 194 return (ENXIO); 195 } 196 } 197 #endif 198 199 /* 200 * Use 100C as the initial value. 201 */ 202 sc->sc_tjmax = 100; 203 204 if ((cpu_model == 0xf && cpu_stepping >= 2) || cpu_model == 0xe) { 205 /* 206 * On some Core 2 CPUs, there's an undocumented MSR that 207 * can tell us if Tj(max) is 100 or 85. 208 * 209 * The if-clause for CPUs having the MSR_IA32_EXT_CONFIG was adapted 210 * from the Linux coretemp driver. 211 */ 212 msr = rdmsr(MSR_IA32_EXT_CONFIG); 213 if (msr & (1 << 30)) 214 sc->sc_tjmax = 85; 215 } else if (cpu_model == 0x17) { 216 switch (cpu_stepping) { 217 case 0x6: /* Mobile Core 2 Duo */ 218 sc->sc_tjmax = 105; 219 break; 220 default: /* Unknown stepping */ 221 break; 222 } 223 } else if (cpu_model == 0x1c) { 224 switch (cpu_stepping) { 225 case 0xa: /* 45nm Atom D400, N400 and D500 series */ 226 sc->sc_tjmax = 100; 227 break; 228 default: 229 sc->sc_tjmax = 90; 230 break; 231 } 232 } else { 233 /* 234 * Attempt to get Tj(max) from MSR IA32_TEMPERATURE_TARGET. 235 * 236 * This method is described in Intel white paper "CPU 237 * Monitoring With DTS/PECI". (#322683) 238 */ 239 ret = rdmsr_safe(MSR_IA32_TEMPERATURE_TARGET, &msr); 240 if (ret == 0) { 241 tjtarget = (msr >> 16) & 0xff; 242 243 /* 244 * On earlier generation of processors, the value 245 * obtained from IA32_TEMPERATURE_TARGET register is 246 * an offset that needs to be summed with a model 247 * specific base. It is however not clear what 248 * these numbers are, with the publicly available 249 * documents from Intel. 250 * 251 * For now, we consider [70, 110]C range, as 252 * described in #322683, as "reasonable" and accept 253 * these values whenever the MSR is available for 254 * read, regardless the CPU model. 255 */ 256 if (tjtarget >= 70 && tjtarget <= 110) 257 sc->sc_tjmax = tjtarget; 258 else 259 device_printf(dev, "Tj(target) value %d " 260 "does not seem right.\n", tjtarget); 261 } else 262 device_printf(dev, "Can not get Tj(target) " 263 "from your CPU, using 100C.\n"); 264 } 265 266 if (bootverbose) 267 device_printf(dev, "Setting TjMax=%d\n", sc->sc_tjmax); 268 269 ctx = device_get_sysctl_ctx(dev); 270 271 oid = SYSCTL_ADD_NODE(ctx, 272 SYSCTL_CHILDREN(device_get_sysctl_tree(pdev)), OID_AUTO, 273 "coretemp", CTLFLAG_RD, NULL, "Per-CPU thermal information"); 274 275 /* 276 * Add the MIBs to dev.cpu.N and dev.cpu.N.coretemp. 277 */ 278 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(device_get_sysctl_tree(pdev)), 279 OID_AUTO, "temperature", CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, 280 dev, CORETEMP_TEMP, coretemp_get_val_sysctl, "IK", 281 "Current temperature"); 282 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(oid), OID_AUTO, "delta", 283 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, dev, CORETEMP_DELTA, 284 coretemp_get_val_sysctl, "I", 285 "Delta between TCC activation and current temperature"); 286 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(oid), OID_AUTO, "resolution", 287 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, dev, CORETEMP_RESOLUTION, 288 coretemp_get_val_sysctl, "I", 289 "Resolution of CPU thermal sensor"); 290 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(oid), OID_AUTO, "tjmax", 291 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, dev, CORETEMP_TJMAX, 292 coretemp_get_val_sysctl, "IK", 293 "TCC activation temperature"); 294 SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(oid), OID_AUTO, 295 "throttle_log", CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_MPSAFE, dev, 0, 296 coretemp_throttle_log_sysctl, "I", 297 "Set to 1 if the thermal sensor has tripped"); 298 299 return (0); 300 } 301 302 static int 303 coretemp_detach(device_t dev) 304 { 305 return (0); 306 } 307 308 static uint64_t 309 coretemp_get_thermal_msr(int cpu) 310 { 311 uint64_t msr; 312 313 thread_lock(curthread); 314 sched_bind(curthread, cpu); 315 thread_unlock(curthread); 316 317 /* 318 * The digital temperature reading is located at bit 16 319 * of MSR_THERM_STATUS. 320 * 321 * There is a bit on that MSR that indicates whether the 322 * temperature is valid or not. 323 * 324 * The temperature is computed by subtracting the temperature 325 * reading by Tj(max). 326 */ 327 msr = rdmsr(MSR_THERM_STATUS); 328 329 thread_lock(curthread); 330 sched_unbind(curthread); 331 thread_unlock(curthread); 332 333 return (msr); 334 } 335 336 static void 337 coretemp_clear_thermal_msr(int cpu) 338 { 339 thread_lock(curthread); 340 sched_bind(curthread, cpu); 341 thread_unlock(curthread); 342 343 wrmsr(MSR_THERM_STATUS, 0); 344 345 thread_lock(curthread); 346 sched_unbind(curthread); 347 thread_unlock(curthread); 348 } 349 350 static int 351 coretemp_get_val_sysctl(SYSCTL_HANDLER_ARGS) 352 { 353 device_t dev; 354 uint64_t msr; 355 int val, tmp; 356 struct coretemp_softc *sc; 357 enum therm_info type; 358 char stemp[16]; 359 360 dev = (device_t) arg1; 361 msr = coretemp_get_thermal_msr(device_get_unit(dev)); 362 sc = device_get_softc(dev); 363 type = arg2; 364 365 if (((msr >> THERM_STATUS_VALID_SHIFT) & THERM_STATUS_VALID_MASK) != 1) { 366 val = -1; 367 } else { 368 switch (type) { 369 case CORETEMP_TEMP: 370 tmp = (msr >> THERM_STATUS_TEMP_SHIFT) & 371 THERM_STATUS_TEMP_MASK; 372 val = (sc->sc_tjmax - tmp) * 10 + TZ_ZEROC; 373 break; 374 case CORETEMP_DELTA: 375 val = (msr >> THERM_STATUS_TEMP_SHIFT) & 376 THERM_STATUS_TEMP_MASK; 377 break; 378 case CORETEMP_RESOLUTION: 379 val = (msr >> THERM_STATUS_RES_SHIFT) & 380 THERM_STATUS_RES_MASK; 381 break; 382 case CORETEMP_TJMAX: 383 val = sc->sc_tjmax * 10 + TZ_ZEROC; 384 break; 385 } 386 } 387 388 if (msr & THERM_STATUS_LOG) { 389 coretemp_clear_thermal_msr(device_get_unit(dev)); 390 sc->sc_throttle_log = 1; 391 392 /* 393 * Check for Critical Temperature Status and Critical 394 * Temperature Log. It doesn't really matter if the 395 * current temperature is invalid because the "Critical 396 * Temperature Log" bit will tell us if the Critical 397 * Temperature has * been reached in past. It's not 398 * directly related to the current temperature. 399 * 400 * If we reach a critical level, allow devctl(4) 401 * to catch this and shutdown the system. 402 */ 403 if (msr & THERM_STATUS) { 404 tmp = (msr >> THERM_STATUS_TEMP_SHIFT) & 405 THERM_STATUS_TEMP_MASK; 406 tmp = (sc->sc_tjmax - tmp) * 10 + TZ_ZEROC; 407 device_printf(dev, "critical temperature detected, " 408 "suggest system shutdown\n"); 409 snprintf(stemp, sizeof(stemp), "%d", tmp); 410 devctl_notify("coretemp", "Thermal", stemp, 411 "notify=0xcc"); 412 } 413 } 414 415 return (sysctl_handle_int(oidp, &val, 0, req)); 416 } 417 418 static int 419 coretemp_throttle_log_sysctl(SYSCTL_HANDLER_ARGS) 420 { 421 device_t dev; 422 uint64_t msr; 423 int error, val; 424 struct coretemp_softc *sc; 425 426 dev = (device_t) arg1; 427 msr = coretemp_get_thermal_msr(device_get_unit(dev)); 428 sc = device_get_softc(dev); 429 430 if (msr & THERM_STATUS_LOG) { 431 coretemp_clear_thermal_msr(device_get_unit(dev)); 432 sc->sc_throttle_log = 1; 433 } 434 435 val = sc->sc_throttle_log; 436 437 error = sysctl_handle_int(oidp, &val, 0, req); 438 439 if (error || !req->newptr) 440 return (error); 441 else if (val != 0) 442 return (EINVAL); 443 444 coretemp_clear_thermal_msr(device_get_unit(dev)); 445 sc->sc_throttle_log = 0; 446 447 return (0); 448 } 449