1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * StarFive JH7110 PLL Clock Generator Driver 4 * 5 * Copyright (C) 2022 Xingyu Wu <xingyu.wu@starfivetech.com> 6 */ 7 8 #define PLL0_DACPD_SHIFT 24 9 #define PLL0_DACPD_MASK 0x1000000 10 #define PLL_0_DACPD_SHIFT 24 11 #define PLL_0_DACPD_MASK 0x1000000 12 13 #define PLL0_DSMPD_SHIFT 25 14 #define PLL0_DSMPD_MASK 0x2000000 15 #define PLL0_FBDIV_SHIFT 0 16 #define PLL0_FBDIV_MASK 0xFFF 17 #define PLL0_FRAC_SHIFT 0 18 #define PLL0_FRAC_MASK 0xFFFFFF 19 #define PLL0_POSTDIV1_SHIFT 28 20 #define PLL0_POSTDIV1_MASK 0x30000000 21 #define PLL0_PREDIV_SHIFT 0 22 #define PLL0_PREDIV_MASK 0x3F 23 24 #define PLL1_DACPD_SHIFT 15 25 #define PLL1_DACPD_MASK 0x8000 26 #define PLL1_DSMPD_SHIFT 16 27 #define PLL1_DSMPD_MASK 0x10000 28 #define PLL1_FBDIV_SHIFT 17 29 #define PLL1_FBDIV_MASK 0x1FFE0000 30 #define PLL1_FRAC_SHIFT 0 31 #define PLL1_FRAC_MASK 0xFFFFFF 32 #define PLL1_POSTDIV1_SHIFT 28 33 #define PLL1_POSTDIV1_MASK 0x30000000 34 #define PLL1_PREDIV_SHIFT 0 35 #define PLL1_PREDIV_MASK 0x3F 36 37 #define PLL2_DACPD_SHIFT 15 38 #define PLL2_DACPD_MASK 0x8000 39 #define PLL2_DSMPD_SHIFT 16 40 #define PLL2_DSMPD_MASK 0x10000 41 #define PLL2_FBDIV_SHIFT 17 42 #define PLL2_FBDIV_MASK 0x1FFE0000 43 #define PLL2_FRAC_SHIFT 0 44 #define PLL2_FRAC_MASK 0xFFFFFF 45 #define PLL2_POSTDIV1_SHIFT 28 46 #define PLL2_POSTDIV1_MASK 0x30000000 47 #define PLL2_PREDIV_SHIFT 0 48 #define PLL2_PREDIV_MASK 0x3F 49 50 #define FRAC_PATR_SIZE 1000 51 52 struct jh7110_pll_syscon_value { 53 uint64_t freq; 54 uint32_t prediv; 55 uint32_t fbdiv; 56 uint32_t postdiv1; 57 uint32_t dacpd; 58 uint32_t dsmpd; 59 uint32_t frac; 60 }; 61 62 enum starfive_pll0_freq_value { 63 PLL0_FREQ_375_VALUE = 375000000, 64 PLL0_FREQ_500_VALUE = 500000000, 65 PLL0_FREQ_625_VALUE = 625000000, 66 PLL0_FREQ_750_VALUE = 750000000, 67 PLL0_FREQ_875_VALUE = 875000000, 68 PLL0_FREQ_1000_VALUE = 1000000000, 69 PLL0_FREQ_1250_VALUE = 1250000000, 70 PLL0_FREQ_1375_VALUE = 1375000000, 71 PLL0_FREQ_1500_VALUE = 1500000000 72 }; 73 74 enum starfive_pll0_freq { 75 PLL0_FREQ_375 = 0, 76 PLL0_FREQ_500, 77 PLL0_FREQ_625, 78 PLL0_FREQ_750, 79 PLL0_FREQ_875, 80 PLL0_FREQ_1000, 81 PLL0_FREQ_1250, 82 PLL0_FREQ_1375, 83 PLL0_FREQ_1500, 84 PLL0_FREQ_MAX = PLL0_FREQ_1500 85 }; 86 87 enum starfive_pll1_freq_value { 88 PLL1_FREQ_1066_VALUE = 1066000000, 89 }; 90 91 enum starfive_pll1_freq { 92 PLL1_FREQ_1066 = 0, 93 }; 94 95 enum starfive_pll2_freq_value { 96 PLL2_FREQ_1188_VALUE = 1188000000, 97 PLL2_FREQ_12288_VALUE = 1228800000, 98 }; 99 100 enum starfive_pll2_freq { 101 PLL2_FREQ_1188 = 0, 102 PLL2_FREQ_12288, 103 }; 104 105 static const struct jh7110_pll_syscon_value 106 jh7110_pll0_syscon_freq[] = { 107 [PLL0_FREQ_375] = { 108 .freq = PLL0_FREQ_375_VALUE, 109 .prediv = 8, 110 .fbdiv = 125, 111 .postdiv1 = 1, 112 .dacpd = 1, 113 .dsmpd = 1, 114 }, 115 [PLL0_FREQ_500] = { 116 .freq = PLL0_FREQ_500_VALUE, 117 .prediv = 6, 118 .fbdiv = 125, 119 .postdiv1 = 1, 120 .dacpd = 1, 121 .dsmpd = 1, 122 }, 123 [PLL0_FREQ_625] = { 124 .freq = PLL0_FREQ_625_VALUE, 125 .prediv = 24, 126 .fbdiv = 625, 127 .postdiv1 = 1, 128 .dacpd = 1, 129 .dsmpd = 1, 130 }, 131 [PLL0_FREQ_750] = { 132 .freq = PLL0_FREQ_750_VALUE, 133 .prediv = 4, 134 .fbdiv = 125, 135 .postdiv1 = 1, 136 .dacpd = 1, 137 .dsmpd = 1, 138 }, 139 [PLL0_FREQ_875] = { 140 .freq = PLL0_FREQ_875_VALUE, 141 .prediv = 24, 142 .fbdiv = 875, 143 .postdiv1 = 1, 144 .dacpd = 1, 145 .dsmpd = 1, 146 }, 147 [PLL0_FREQ_1000] = { 148 .freq = PLL0_FREQ_1000_VALUE, 149 .prediv = 3, 150 .fbdiv = 125, 151 .postdiv1 = 1, 152 .dacpd = 1, 153 .dsmpd = 1, 154 }, 155 [PLL0_FREQ_1250] = { 156 .freq = PLL0_FREQ_1250_VALUE, 157 .prediv = 12, 158 .fbdiv = 625, 159 .postdiv1 = 1, 160 .dacpd = 1, 161 .dsmpd = 1, 162 }, 163 [PLL0_FREQ_1375] = { 164 .freq = PLL0_FREQ_1375_VALUE, 165 .prediv = 24, 166 .fbdiv = 1375, 167 .postdiv1 = 1, 168 .dacpd = 1, 169 .dsmpd = 1, 170 }, 171 [PLL0_FREQ_1500] = { 172 .freq = PLL0_FREQ_1500_VALUE, 173 .prediv = 2, 174 .fbdiv = 125, 175 .postdiv1 = 1, 176 .dacpd = 1, 177 .dsmpd = 1, 178 }, 179 }; 180 181 static const struct jh7110_pll_syscon_value 182 jh7110_pll1_syscon_freq[] = { 183 [PLL1_FREQ_1066] = { 184 .freq = PLL1_FREQ_1066_VALUE, 185 .prediv = 12, 186 .fbdiv = 533, 187 .postdiv1 = 1, 188 .dacpd = 1, 189 .dsmpd = 1, 190 }, 191 }; 192 193 static const struct jh7110_pll_syscon_value 194 jh7110_pll2_syscon_freq[] = { 195 [PLL2_FREQ_1188] = { 196 .freq = PLL2_FREQ_1188_VALUE, 197 .prediv = 2, 198 .fbdiv = 99, 199 .postdiv1 = 1, 200 .dacpd = 1, 201 .dsmpd = 1, 202 }, 203 [PLL2_FREQ_12288] = { 204 .freq = PLL2_FREQ_12288_VALUE, 205 .prediv = 5, 206 .fbdiv = 256, 207 .postdiv1 = 1, 208 .dacpd = 1, 209 .dsmpd = 1, 210 }, 211 }; 212