1*0612538eSJari Sihvola /*- 2*0612538eSJari Sihvola * SPDX-License-Identifier: BSD-2-Clause 3*0612538eSJari Sihvola * 4*0612538eSJari Sihvola * Copyright (c) 2024 Jari Sihvola <jsihv@gmx.com> 5*0612538eSJari Sihvola */ 6*0612538eSJari Sihvola 7*0612538eSJari Sihvola #ifndef _JH7110_CLK_H_ 8*0612538eSJari Sihvola #define _JH7110_CLK_H_ 9*0612538eSJari Sihvola 10*0612538eSJari Sihvola #include <dev/clk/clk.h> 11*0612538eSJari Sihvola 12*0612538eSJari Sihvola #define JH7110_CLK_HAS_GATE 0x01 13*0612538eSJari Sihvola #define JH7110_CLK_HAS_MUX 0x02 14*0612538eSJari Sihvola #define JH7110_CLK_HAS_DIV 0x04 15*0612538eSJari Sihvola #define JH7110_CLK_HAS_INV 0x08 16*0612538eSJari Sihvola 17*0612538eSJari Sihvola #define AONCRG_RESET_SELECTOR 0x38 18*0612538eSJari Sihvola #define AONCRG_RESET_STATUS 0x3c 19*0612538eSJari Sihvola #define STGCRG_RESET_SELECTOR 0x74 20*0612538eSJari Sihvola #define STGCRG_RESET_STATUS 0x78 21*0612538eSJari Sihvola #define SYSCRG_RESET_SELECTOR 0x2f8 22*0612538eSJari Sihvola #define SYSCRG_RESET_STATUS 0x308 23*0612538eSJari Sihvola 24*0612538eSJari Sihvola struct jh7110_clkgen_softc { 25*0612538eSJari Sihvola struct mtx mtx; 26*0612538eSJari Sihvola struct clkdom *clkdom; 27*0612538eSJari Sihvola struct resource *mem_res; 28*0612538eSJari Sihvola uint32_t reset_status_offset; 29*0612538eSJari Sihvola uint32_t reset_selector_offset; 30*0612538eSJari Sihvola }; 31*0612538eSJari Sihvola 32*0612538eSJari Sihvola struct jh7110_clk_def { 33*0612538eSJari Sihvola struct clknode_init_def clkdef; 34*0612538eSJari Sihvola uint32_t offset; 35*0612538eSJari Sihvola uint32_t flags; 36*0612538eSJari Sihvola uint64_t d_max; 37*0612538eSJari Sihvola }; 38*0612538eSJari Sihvola 39*0612538eSJari Sihvola #define JH7110_CLK(_idx, _name, _pn, _d_max, _flags) \ 40*0612538eSJari Sihvola { \ 41*0612538eSJari Sihvola .clkdef.id = _idx, \ 42*0612538eSJari Sihvola .clkdef.name = _name, \ 43*0612538eSJari Sihvola .clkdef.parent_names = _pn, \ 44*0612538eSJari Sihvola .clkdef.parent_cnt = nitems(_pn), \ 45*0612538eSJari Sihvola .clkdef.flags = CLK_NODE_STATIC_STRINGS, \ 46*0612538eSJari Sihvola .flags = _flags, \ 47*0612538eSJari Sihvola .d_max = _d_max, \ 48*0612538eSJari Sihvola } 49*0612538eSJari Sihvola 50*0612538eSJari Sihvola #define JH7110_GATE(_idx, _name, _pn) \ 51*0612538eSJari Sihvola JH7110_CLK(_idx, _name, _pn, 0, JH7110_CLK_HAS_GATE) 52*0612538eSJari Sihvola #define JH7110_MUX(_idx, _name, _pn) \ 53*0612538eSJari Sihvola JH7110_CLK(_idx, _name, _pn, 0, JH7110_CLK_HAS_MUX) 54*0612538eSJari Sihvola #define JH7110_DIV(_idx, _name, _pn, _d_max) \ 55*0612538eSJari Sihvola JH7110_CLK(_idx, _name, _pn, _d_max, JH7110_CLK_HAS_DIV) 56*0612538eSJari Sihvola #define JH7110_GATEMUX(_idx, _name, _pn) \ 57*0612538eSJari Sihvola JH7110_CLK(_idx, _name, _pn, 0, JH7110_CLK_HAS_GATE | \ 58*0612538eSJari Sihvola JH7110_CLK_HAS_MUX) 59*0612538eSJari Sihvola #define JH7110_GATEDIV(_idx, _name, _pn, _d_max) \ 60*0612538eSJari Sihvola JH7110_CLK(_idx, _name, _pn, _d_max, JH7110_CLK_HAS_GATE | \ 61*0612538eSJari Sihvola JH7110_CLK_HAS_DIV) 62*0612538eSJari Sihvola #define JH7110_INV(_idx, _name, _pn) \ 63*0612538eSJari Sihvola JH7110_CLK(_idx, _name, _pn, 0, JH7110_CLK_HAS_INV) 64*0612538eSJari Sihvola 65*0612538eSJari Sihvola int jh7110_clk_register(struct clkdom *clkdom, 66*0612538eSJari Sihvola const struct jh7110_clk_def *clkdef); 67*0612538eSJari Sihvola int jh7110_ofw_map(struct clkdom *clkdom, uint32_t ncells, phandle_t *cells, 68*0612538eSJari Sihvola struct clknode **clk); 69*0612538eSJari Sihvola int jh7110_reset_is_asserted(device_t dev, intptr_t id, bool *reset); 70*0612538eSJari Sihvola int jh7110_reset_assert(device_t dev, intptr_t id, bool assert); 71*0612538eSJari Sihvola 72*0612538eSJari Sihvola #endif /* _JH7110_CLK_H_ */ 73