xref: /freebsd/sys/dev/clk/rockchip/rk_clk_pll.h (revision f81cdf24ba5436367377f7c8e8f51f6df2a75ca7)
1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause
3  *
4  * Copyright 2018 Emmanuel Vadot <manu@FreeBSD.org>
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions
8  * are met:
9  * 1. Redistributions of source code must retain the above copyright
10  *    notice, this list of conditions and the following disclaimer.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  *
15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25  * SUCH DAMAGE.
26  */
27 
28 #ifndef _RK_CLK_PLL_H_
29 #define _RK_CLK_PLL_H_
30 
31 #include <dev/clk/clk.h>
32 
33 struct rk_clk_pll_rate {
34 	uint32_t	freq;
35 	uint32_t	refdiv;
36 	uint32_t	fbdiv;
37 	uint32_t	postdiv1;
38 	uint32_t	postdiv2;
39 	uint32_t	dsmpd;
40 	uint32_t	frac;
41 	uint32_t	bwadj;
42 };
43 
44 struct rk_clk_pll_def {
45 	struct clknode_init_def	clkdef;
46 	uint32_t		base_offset;
47 
48 	uint32_t		gate_offset;
49 	uint32_t		gate_shift;
50 
51 	uint32_t		mode_reg;
52 	uint32_t		mode_shift;
53 
54 	uint32_t		flags;
55 
56 	struct rk_clk_pll_rate	*rates;
57 	struct rk_clk_pll_rate	*frac_rates;
58 };
59 
60 #define	RK_CLK_PLL_HAVE_GATE	0x1
61 
62 int rk3066_clk_pll_register(struct clkdom *clkdom, struct rk_clk_pll_def *clkdef);
63 int rk3328_clk_pll_register(struct clkdom *clkdom, struct rk_clk_pll_def *clkdef);
64 int rk3399_clk_pll_register(struct clkdom *clkdom, struct rk_clk_pll_def *clkdef);
65 
66 #endif /* _RK_CLK_PLL_H_ */
67