1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2018 Emmanuel Vadot <manu@freebsd.org> 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 20 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 21 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 22 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 23 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 #include <sys/param.h> 29 #include <sys/systm.h> 30 #include <sys/bus.h> 31 #include <sys/rman.h> 32 #include <sys/kernel.h> 33 #include <sys/module.h> 34 #include <machine/bus.h> 35 36 #include <dev/fdt/simplebus.h> 37 38 #include <dev/ofw/ofw_bus.h> 39 #include <dev/ofw/ofw_bus_subr.h> 40 41 #ifdef __aarch64__ 42 #include "opt_soc.h" 43 #endif 44 45 #include <dev/clk/clk_div.h> 46 #include <dev/clk/clk_fixed.h> 47 #include <dev/clk/clk_mux.h> 48 49 #include <dev/hwreset/hwreset.h> 50 51 #include <dev/clk/allwinner/aw_ccung.h> 52 53 #include <dt-bindings/clock/sun8i-de2.h> 54 #include <dt-bindings/reset/sun8i-de2.h> 55 56 enum CCU_DE2 { 57 H3_CCU = 1, 58 A64_CCU, 59 }; 60 61 /* Non exported clocks */ 62 #define CLK_MIXER0_DIV 3 63 #define CLK_MIXER1_DIV 4 64 #define CLK_WB_DIV 5 65 66 static struct aw_ccung_reset h3_de2_ccu_resets[] = { 67 CCU_RESET(RST_MIXER0, 0x08, 0) 68 CCU_RESET(RST_WB, 0x08, 2) 69 }; 70 71 static struct aw_ccung_reset a64_de2_ccu_resets[] = { 72 CCU_RESET(RST_MIXER0, 0x08, 0) 73 CCU_RESET(RST_MIXER1, 0x08, 1) 74 CCU_RESET(RST_WB, 0x08, 2) 75 }; 76 77 static struct aw_ccung_gate h3_de2_ccu_gates[] = { 78 CCU_GATE(CLK_BUS_MIXER0, "mixer0", "mixer0-div", 0x00, 0) 79 CCU_GATE(CLK_BUS_WB, "wb", "wb-div", 0x00, 2) 80 81 CCU_GATE(CLK_MIXER0, "bus-mixer0", "bus-de", 0x04, 0) 82 CCU_GATE(CLK_WB, "bus-wb", "bus-de", 0x04, 2) 83 }; 84 85 static struct aw_ccung_gate a64_de2_ccu_gates[] = { 86 CCU_GATE(CLK_BUS_MIXER0, "mixer0", "mixer0-div", 0x00, 0) 87 CCU_GATE(CLK_BUS_MIXER1, "mixer1", "mixer1-div", 0x00, 1) 88 CCU_GATE(CLK_BUS_WB, "wb", "wb-div", 0x00, 2) 89 90 CCU_GATE(CLK_MIXER0, "bus-mixer0", "bus-de", 0x04, 0) 91 CCU_GATE(CLK_MIXER1, "bus-mixer1", "bus-de", 0x04, 1) 92 CCU_GATE(CLK_WB, "bus-wb", "bus-de", 0x04, 2) 93 }; 94 95 static const char *div_parents[] = {"de"}; 96 97 NM_CLK(mixer0_div_clk, 98 CLK_MIXER0_DIV, /* id */ 99 "mixer0-div", div_parents, /* names, parents */ 100 0x0C, /* offset */ 101 0, 0, 1, AW_CLK_FACTOR_FIXED, /* N factor (fake)*/ 102 0, 4, 0, 0, /* M flags */ 103 0, 0, /* mux */ 104 0, /* gate */ 105 AW_CLK_SCALE_CHANGE); /* flags */ 106 107 NM_CLK(mixer1_div_clk, 108 CLK_MIXER1_DIV, /* id */ 109 "mixer1-div", div_parents, /* names, parents */ 110 0x0C, /* offset */ 111 0, 0, 1, AW_CLK_FACTOR_FIXED, /* N factor (fake)*/ 112 4, 4, 0, 0, /* M flags */ 113 0, 0, /* mux */ 114 0, /* gate */ 115 AW_CLK_SCALE_CHANGE); /* flags */ 116 117 NM_CLK(wb_div_clk, 118 CLK_WB_DIV, /* id */ 119 "wb-div", div_parents, /* names, parents */ 120 0x0C, /* offset */ 121 0, 0, 1, AW_CLK_FACTOR_FIXED, /* N factor (fake)*/ 122 8, 4, 0, 0, /* M flags */ 123 0, 0, /* mux */ 124 0, /* gate */ 125 AW_CLK_SCALE_CHANGE); /* flags */ 126 127 static struct aw_ccung_clk h3_de2_ccu_clks[] = { 128 { .type = AW_CLK_NM, .clk.nm = &mixer0_div_clk}, 129 { .type = AW_CLK_NM, .clk.nm = &wb_div_clk}, 130 }; 131 132 static struct aw_ccung_clk a64_de2_ccu_clks[] = { 133 { .type = AW_CLK_NM, .clk.nm = &mixer0_div_clk}, 134 { .type = AW_CLK_NM, .clk.nm = &mixer1_div_clk}, 135 { .type = AW_CLK_NM, .clk.nm = &wb_div_clk}, 136 }; 137 138 static struct ofw_compat_data compat_data[] = { 139 {"allwinner,sun8i-h3-de2-clk", H3_CCU}, 140 {"allwinner,sun50i-a64-de2-clk", A64_CCU}, 141 {NULL, 0} 142 }; 143 144 static int 145 ccu_de2_probe(device_t dev) 146 { 147 148 if (!ofw_bus_status_okay(dev)) 149 return (ENXIO); 150 151 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 152 return (ENXIO); 153 154 device_set_desc(dev, "Allwinner DE2 Clock Control Unit"); 155 return (BUS_PROBE_DEFAULT); 156 } 157 158 static int 159 ccu_de2_attach(device_t dev) 160 { 161 struct aw_ccung_softc *sc; 162 phandle_t node; 163 clk_t mod, bus; 164 hwreset_t rst_de; 165 enum CCU_DE2 type; 166 167 sc = device_get_softc(dev); 168 node = ofw_bus_get_node(dev); 169 170 type = (enum CCU_DE2)ofw_bus_search_compatible(dev, compat_data)->ocd_data; 171 172 switch (type) { 173 case H3_CCU: 174 sc->resets = h3_de2_ccu_resets; 175 sc->nresets = nitems(h3_de2_ccu_resets); 176 sc->gates = h3_de2_ccu_gates; 177 sc->ngates = nitems(h3_de2_ccu_gates); 178 sc->clks = h3_de2_ccu_clks; 179 sc->nclks = nitems(h3_de2_ccu_clks); 180 break; 181 case A64_CCU: 182 sc->resets = a64_de2_ccu_resets; 183 sc->nresets = nitems(a64_de2_ccu_resets); 184 sc->gates = a64_de2_ccu_gates; 185 sc->ngates = nitems(a64_de2_ccu_gates); 186 sc->clks = a64_de2_ccu_clks; 187 sc->nclks = nitems(a64_de2_ccu_clks); 188 break; 189 } 190 191 if (hwreset_get_by_ofw_idx(dev, node, 0, &rst_de) != 0) { 192 device_printf(dev, "Cannot get de reset\n"); 193 return (ENXIO); 194 } 195 if (hwreset_deassert(rst_de) != 0) { 196 device_printf(dev, "Cannot de-assert de reset\n"); 197 return (ENXIO); 198 } 199 200 if (clk_get_by_ofw_name(dev, node, "mod", &mod) != 0) { 201 device_printf(dev, "Cannot get mod clock\n"); 202 return (ENXIO); 203 } 204 if (clk_enable(mod) != 0) { 205 device_printf(dev, "Cannot enable mod clock\n"); 206 return (ENXIO); 207 } 208 209 if (clk_get_by_ofw_name(dev, node, "bus", &bus) != 0) { 210 device_printf(dev, "Cannot get bus clock\n"); 211 return (ENXIO); 212 } 213 if (clk_enable(bus) != 0) { 214 device_printf(dev, "Cannot enable bus clock\n"); 215 return (ENXIO); 216 } 217 218 return (aw_ccung_attach(dev)); 219 } 220 221 static device_method_t ccu_de2_methods[] = { 222 /* Device interface */ 223 DEVMETHOD(device_probe, ccu_de2_probe), 224 DEVMETHOD(device_attach, ccu_de2_attach), 225 226 DEVMETHOD_END 227 }; 228 229 DEFINE_CLASS_1(ccu_de2, ccu_de2_driver, ccu_de2_methods, 230 sizeof(struct aw_ccung_softc), aw_ccung_driver); 231 232 EARLY_DRIVER_MODULE(ccu_de2, simplebus, ccu_de2_driver, 0, 0, 233 BUS_PASS_RESOURCE + BUS_PASS_ORDER_LAST); 234