1 /*- 2 * Copyright (c) 2001 Michael Smith 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29 /* 30 * Structure and I/O definitions for the Command Interface for SCSI-3 Support. 31 * 32 * Data in command CDBs are in big-endian format. All other data is little-endian. 33 * This header only supports little-endian hosts at this time. 34 */ 35 36 union ciss_device_address 37 { 38 struct /* MODE_PERIPHERAL and MODE_MASK_PERIPHERAL */ 39 { 40 u_int32_t target:24; /* SCSI target */ 41 u_int32_t bus:6; /* SCSI bus */ 42 u_int32_t mode:2; /* CISS_HDR_ADDRESS_MODE_* */ 43 u_int32_t extra_address; /* SCSI-3 level-2 and level-3 address bytes */ 44 } physical; 45 struct /* MODE_LOGICAL */ 46 { 47 u_int32_t lun:30; /* logical device ID */ 48 u_int32_t mode:2; /* CISS_HDR_ADDRESS_MODE_LOGICAL */ 49 u_int32_t :32; /* reserved */ 50 } logical; 51 struct 52 { 53 u_int32_t :30; 54 u_int32_t mode:2; 55 u_int32_t :32; 56 } mode; 57 }; 58 #define CISS_HDR_ADDRESS_MODE_PERIPHERAL 0x0 59 #define CISS_HDR_ADDRESS_MODE_LOGICAL 0x1 60 #define CISS_HDR_ADDRESS_MODE_MASK_PERIPHERAL 0x3 61 62 struct ciss_header 63 { 64 u_int8_t :8; /* reserved */ 65 u_int8_t sg_in_list; /* SG's in the command structure */ 66 u_int16_t sg_total; /* total count of SGs for this command */ 67 u_int32_t host_tag; /* host identifier, bits 0&1 must be clear */ 68 #define CISS_HDR_HOST_TAG_ERROR (1<<1) 69 u_int32_t host_tag_zeroes; /* tag is 64 bits, but interface only supports 32 */ 70 union ciss_device_address address; 71 } __packed; 72 73 struct ciss_cdb 74 { 75 u_int8_t cdb_length; /* valid CDB bytes */ 76 u_int8_t type:3; 77 #define CISS_CDB_TYPE_COMMAND 0 78 #define CISS_CDB_TYPE_MESSAGE 1 79 u_int8_t attribute:3; 80 #define CISS_CDB_ATTRIBUTE_UNTAGGED 0 81 #define CISS_CDB_ATTRIBUTE_SIMPLE 4 82 #define CISS_CDB_ATTRIBUTE_HEAD_OF_QUEUE 5 83 #define CISS_CDB_ATTRIBUTE_ORDERED 6 84 #define CISS_CDB_ATTRIBUTE_AUTO_CONTINGENT 7 85 u_int8_t direction:2; 86 #define CISS_CDB_DIRECTION_NONE 0 87 #define CISS_CDB_DIRECTION_WRITE 1 88 #define CISS_CDB_DIRECTION_READ 2 89 u_int16_t timeout; /* seconds */ 90 #define CISS_CDB_BUFFER_SIZE 16 91 u_int8_t cdb[CISS_CDB_BUFFER_SIZE]; 92 } __packed; 93 94 struct ciss_error_info_pointer 95 { 96 u_int64_t error_info_address; /* points to ciss_error_info structure */ 97 u_int32_t error_info_length; 98 } __packed; 99 100 struct ciss_error_info 101 { 102 u_int8_t scsi_status; 103 #define CISS_SCSI_STATUS_GOOD 0x00 /* these are scsi-standard values */ 104 #define CISS_SCSI_STATUS_CHECK_CONDITION 0x02 105 #define CISS_SCSI_STATUS_CONDITION_MET 0x04 106 #define CISS_SCSI_STATUS_BUSY 0x08 107 #define CISS_SCSI_STATUS_INDETERMINATE 0x10 108 #define CISS_SCSI_STATUS_INDETERMINATE_CM 0x14 109 #define CISS_SCSI_STATUS_RESERVATION_CONFLICT 0x18 110 #define CISS_SCSI_STATUS_COMMAND_TERMINATED 0x22 111 #define CISS_SCSI_STATUS_QUEUE_FULL 0x28 112 #define CISS_SCSI_STATUS_ACA_ACTIVE 0x30 113 u_int8_t sense_length; 114 u_int16_t command_status; 115 #define CISS_CMD_STATUS_SUCCESS 0 116 #define CISS_CMD_STATUS_TARGET_STATUS 1 117 #define CISS_CMD_STATUS_DATA_UNDERRUN 2 118 #define CISS_CMD_STATUS_DATA_OVERRUN 3 119 #define CISS_CMD_STATUS_INVALID_COMMAND 4 120 #define CISS_CMD_STATUS_PROTOCOL_ERROR 5 121 #define CISS_CMD_STATUS_HARDWARE_ERROR 6 122 #define CISS_CMD_STATUS_CONNECTION_LOST 7 123 #define CISS_CMD_STATUS_ABORTED 8 124 #define CISS_CMD_STATUS_ABORT_FAILED 9 125 #define CISS_CMD_STATUS_UNSOLICITED_ABORT 10 126 #define CISS_CMD_STATUS_TIMEOUT 11 127 #define CISS_CMD_STATUS_UNABORTABLE 12 128 u_int32_t residual_count; 129 union { 130 struct { 131 u_int8_t res1[3]; 132 u_int8_t type; 133 u_int32_t error_info; 134 } common_info __packed; 135 struct { 136 u_int8_t res1[2]; 137 u_int8_t offense_size; 138 u_int8_t offense_offset; 139 u_int32_t offense_value; 140 } invalid_command __packed; 141 } additional_error_info; 142 u_int8_t sense_info[0]; 143 } __packed; 144 145 struct ciss_sg_entry 146 { 147 u_int64_t address; 148 #define CISS_SG_ADDRESS_BITBUCKET (~(u_int64_t)0) 149 u_int32_t length; 150 u_int32_t :31; 151 u_int32_t extension:1; /* address points to another s/g chain */ 152 } __packed; 153 154 struct ciss_command 155 { 156 struct ciss_header header; 157 struct ciss_cdb cdb; 158 struct ciss_error_info_pointer error_info; 159 struct ciss_sg_entry sg[0]; 160 } __packed; 161 162 #define CISS_OPCODE_REPORT_LOGICAL_LUNS 0xc2 163 #define CISS_OPCODE_REPORT_PHYSICAL_LUNS 0xc3 164 165 struct ciss_lun_report 166 { 167 u_int32_t list_size; /* big-endian */ 168 u_int32_t :32; 169 union ciss_device_address lun[0]; 170 } __packed; 171 172 #define CISS_VPD_LOGICAL_DRIVE_GEOMETRY 0xc1 173 struct ciss_ldrive_geometry 174 { 175 u_int8_t periph_qualifier:3; 176 u_int8_t periph_devtype:5; 177 u_int8_t page_code; 178 u_int8_t res1; 179 u_int8_t page_length; 180 u_int16_t cylinders; /* big-endian */ 181 u_int8_t heads; 182 u_int8_t sectors; 183 u_int8_t fault_tolerance; 184 u_int8_t res2[3]; 185 } __attribute__ ((packed)); 186 187 struct ciss_report_cdb 188 { 189 u_int8_t opcode; 190 u_int8_t reserved[5]; 191 u_int32_t length; /* big-endian */ 192 u_int8_t :8; 193 u_int8_t control; 194 } __packed; 195 196 /* 197 * Note that it's not clear whether we have to set the detail field to 198 * the tag of the command to be aborted, or the tag field in the command itself; 199 * documentation conflicts on this. 200 */ 201 #define CISS_OPCODE_MESSAGE_ABORT 0x00 202 #define CISS_MESSAGE_ABORT_TASK 0x00 203 #define CISS_MESSAGE_ABORT_TASK_SET 0x01 204 #define CISS_MESSAGE_ABORT_CLEAR_ACA 0x02 205 #define CISS_MESSAGE_ABORT_CLEAR_TASK_SET 0x03 206 207 #define CISS_OPCODE_MESSAGE_RESET 0x01 208 #define CISS_MESSAGE_RESET_CONTROLLER 0x00 209 #define CISS_MESSAGE_RESET_BUS 0x01 210 #define CISS_MESSAGE_RESET_TARGET 0x03 211 #define CISS_MESSAGE_RESET_LOGICAL_UNIT 0x04 212 213 #define CISS_OPCODE_MESSAGE_SCAN 0x02 214 #define CISS_MESSAGE_SCAN_CONTROLLER 0x00 215 #define CISS_MESSAGE_SCAN_BUS 0x01 216 #define CISS_MESSAGE_SCAN_TARGET 0x03 217 #define CISS_MESSAGE_SCAN_LOGICAL_UNIT 0x04 218 219 #define CISS_OPCODE_MESSAGE_NOP 0x03 220 221 struct ciss_message_cdb 222 { 223 u_int8_t opcode; 224 u_int8_t type; 225 u_int16_t :16; 226 u_int32_t abort_tag; /* XXX endianness? */ 227 u_int8_t reserved[8]; 228 } __packed; 229 230 /* 231 * CISS vendor-specific commands/messages. 232 * 233 * Note that while messages and vendor-specific commands are 234 * differentiated, they are handled in basically the same way and can 235 * be considered to be basically the same thing, as long as the cdb 236 * type field is set correctly. 237 */ 238 #define CISS_OPCODE_READ 0xc0 239 #define CISS_OPCODE_WRITE 0xc1 240 #define CISS_COMMAND_NOTIFY_ON_EVENT 0xd0 241 #define CISS_COMMAND_ABORT_NOTIFY 0xd1 242 243 struct ciss_notify_cdb 244 { 245 u_int8_t opcode; 246 u_int8_t command; 247 u_int8_t res1[2]; 248 u_int16_t timeout; /* seconds, little-endian */ 249 u_int8_t res2; /* reserved */ 250 u_int8_t synchronous:1; /* return immediately */ 251 u_int8_t ordered:1; /* return events in recorded order */ 252 u_int8_t seek_to_oldest:1; /* reset read counter to oldest event */ 253 u_int8_t new_only:1; /* ignore any queued events */ 254 u_int8_t :4; 255 u_int32_t length; /* must be 512, little-endian */ 256 #define CISS_NOTIFY_DATA_SIZE 512 257 u_int8_t control; 258 } __packed; 259 260 #define CISS_NOTIFY_NOTIFIER 0 261 #define CISS_NOTIFY_NOTIFIER_STATUS 0 262 #define CISS_NOTIFY_NOTIFIER_PROTOCOL 1 263 264 #define CISS_NOTIFY_HOTPLUG 1 265 #define CISS_NOTIFY_HOTPLUG_PHYSICAL 0 266 #define CISS_NOTIFY_HOTPLUG_POWERSUPPLY 1 267 #define CISS_NOTIFY_HOTPLUG_FAN 2 268 #define CISS_NOTIFY_HOTPLUG_POWER 3 269 #define CISS_NOTIFY_HOTPLUG_REDUNDANT 4 270 271 #define CISS_NOTIFY_HARDWARE 2 272 #define CISS_NOTIFY_HARDWARE_CABLES 0 273 #define CISS_NOTIFY_HARDWARE_MEMORY 1 274 #define CISS_NOTIFY_HARDWARE_FAN 2 275 #define CISS_NOTIFY_HARDWARE_VRM 3 276 277 #define CISS_NOTIFY_ENVIRONMENT 3 278 #define CISS_NOTIFY_ENVIRONMENT_TEMPERATURE 0 279 #define CISS_NOTIFY_ENVIRONMENT_POWERSUPPLY 1 280 #define CISS_NOTIFY_ENVIRONMENT_CHASSIS 2 281 #define CISS_NOTIFY_ENVIRONMENT_POWER 3 282 283 #define CISS_NOTIFY_PHYSICAL 4 284 #define CISS_NOTIFY_PHYSICAL_STATE 0 285 286 #define CISS_NOTIFY_LOGICAL 5 287 #define CISS_NOTIFY_LOGICAL_STATUS 0 288 #define CISS_NOTIFY_LOGICAL_ERROR 1 289 #define CISS_NOTIFY_LOGICAL_SURFACE 2 290 291 #define CISS_NOTIFY_REDUNDANT 6 292 #define CISS_NOTIFY_REDUNDANT_STATUS 0 293 294 #define CISS_NOTIFY_CISS 8 295 #define CISS_NOTIFY_CISS_REDUNDANT_CHANGE 0 296 #define CISS_NOTIFY_CISS_PATH_STATUS 1 297 #define CISS_NOTIFY_CISS_HARDWARE_ERROR 2 298 #define CISS_NOTIFY_CISS_LOGICAL 3 299 300 struct ciss_notify_drive 301 { 302 u_int16_t physical_drive_number; 303 u_int8_t configured_drive_flag; 304 u_int8_t spare_drive_flag; 305 u_int8_t big_physical_drive_number; 306 u_int8_t enclosure_bay_number; 307 } __packed; 308 309 struct ciss_notify_locator 310 { 311 u_int16_t port; 312 u_int16_t id; 313 u_int16_t box; 314 } __packed; 315 316 struct ciss_notify_redundant_controller 317 { 318 u_int16_t slot; 319 } __packed; 320 321 struct ciss_notify_logical_status 322 { 323 u_int16_t logical_drive; 324 u_int8_t previous_state; 325 u_int8_t new_state; 326 u_int8_t spare_state; 327 } __packed; 328 329 struct ciss_notify_rebuild_aborted 330 { 331 u_int16_t logical_drive; 332 u_int8_t replacement_drive; 333 u_int8_t error_drive; 334 u_int8_t big_replacement_drive; 335 u_int8_t big_error_drive; 336 } __packed; 337 338 struct ciss_notify_io_error 339 { 340 u_int16_t logical_drive; 341 u_int32_t lba; 342 u_int16_t block_count; 343 u_int8_t command; 344 u_int8_t failure_bus; 345 u_int8_t failure_drive; 346 u_int64_t big_lba; 347 } __packed; 348 349 struct ciss_notify_consistency_completed 350 { 351 u_int16_t logical_drive; 352 } __packed; 353 354 struct ciss_notify 355 { 356 u_int32_t timestamp; /* seconds since controller power-on */ 357 u_int16_t class; 358 u_int16_t subclass; 359 u_int16_t detail; 360 union 361 { 362 struct ciss_notify_drive drive; 363 struct ciss_notify_locator location; 364 struct ciss_notify_redundant_controller redundant_controller; 365 struct ciss_notify_logical_status logical_status; 366 struct ciss_notify_rebuild_aborted rebuild_aborted; 367 struct ciss_notify_io_error io_error; 368 struct ciss_notify_consistency_completed consistency_completed; 369 u_int8_t data[64]; 370 } data; 371 char message[80]; 372 u_int32_t tag; 373 u_int16_t date; 374 u_int16_t year; 375 u_int32_t time; 376 u_int16_t pre_power_up_time; 377 union ciss_device_address device; 378 /* XXX pads to 512 bytes */ 379 } __packed; 380 381 /* 382 * CISS config table, which describes the controller's 383 * supported interface(s) and capabilities. 384 * 385 * This is mapped directly via PCI. 386 */ 387 struct ciss_config_table 388 { 389 char signature[4]; /* "CISS" */ 390 u_int32_t valence; 391 #define CISS_MIN_VALENCE 1 /* only value currently supported */ 392 #define CISS_MAX_VALENCE 1 393 u_int32_t supported_methods; 394 #define CISS_TRANSPORT_METHOD_READY (1<<0) 395 #define CISS_TRANSPORT_METHOD_SIMPLE (1<<1) 396 u_int32_t active_method; 397 u_int32_t requested_method; 398 u_int32_t command_physlimit; 399 u_int32_t interrupt_coalesce_delay; 400 u_int32_t interrupt_coalesce_count; 401 u_int32_t max_outstanding_commands; 402 u_int32_t bus_types; 403 #define CISS_TRANSPORT_BUS_TYPE_ULTRA2 (1<<0) 404 #define CISS_TRANSPORT_BUS_TYPE_ULTRA3 (1<<1) 405 #define CISS_TRANSPORT_BUS_TYPE_FIBRE1 (1<<8) 406 #define CISS_TRANSPORT_BUS_TYPE_FIBRE2 (1<<9) 407 u_int32_t transport_offset; 408 char server_name[16]; 409 u_int32_t heartbeat; 410 u_int32_t host_driver; 411 #define CISS_DRIVER_SUPPORT_UNIT_ATTENTION (1<<0) 412 #define CISS_DRIVER_QUICK_INIT (1<<1) 413 #define CISS_DRIVER_INTERRUPT_ON_LOCKUP (1<<2) 414 #define CISS_DRIVER_SUPPORT_MIXED_Q_TAGS (1<<3) 415 #define CISS_DRIVER_HOST_IS_ALPHA (1<<4) 416 #define CISS_DRIVER_MULTI_LUN_SUPPORT (1<<5) 417 #define CISS_DRIVER_MESSAGE_REQUESTS_SUPPORTED (1<<7) 418 #define CISS_DRIVER_DAUGHTER_ATTACHED (1<<8) 419 #define CISS_DRIVER_SCSI_PREFETCH (1<<9) 420 u_int32_t max_sg_length; /* 31 in older firmware */ 421 } __packed; 422 423 /* 424 * In a flagrant violation of what CISS seems to be meant to be about, 425 * Compaq recycle a goodly portion of their previous generation's 426 * command set (and all the legacy baggage related to a design 427 * originally aimed at narrow SCSI) through the Array Controller Read 428 * and Array Controller Write interface. 429 * 430 * Command ID values here can be looked up for in the 431 * publically-available documentation for the older controllers; note 432 * that the command layout is necessarily different to fit within the 433 * CDB. 434 */ 435 #define CISS_ARRAY_CONTROLLER_READ 0x26 436 #define CISS_ARRAY_CONTROLLER_WRITE 0x27 437 438 #define CISS_BMIC_ID_LDRIVE 0x10 439 #define CISS_BMIC_ID_CTLR 0x11 440 #define CISS_BMIC_ID_LSTATUS 0x12 441 #define CISS_BMIC_ID_PDRIVE 0x15 442 #define CISS_BMIC_BLINK_PDRIVE 0x16 443 #define CISS_BMIC_SENSE_BLINK_PDRIVE 0x17 444 #define CISS_BMIC_FLUSH_CACHE 0xc2 445 #define CISS_BMIC_ACCEPT_MEDIA 0xe0 446 447 /* 448 * When numbering drives, the original design assumed that 449 * drives 0-7 are on the first SCSI bus, 8-15 on the second, 450 * and so forth. In order to handle modern SCSI configurations, 451 * the MSB is set in the drive ID field, in which case the 452 * modulus changes from 8 to the number of supported drives 453 * per SCSI bus (as obtained from the ID_CTLR command). 454 * This feature is referred to as BIG_MAP support, and we assume 455 * that all CISS controllers support it. 456 */ 457 458 #define CISS_BIG_MAP_ID(sc, bus, target) \ 459 (0x80 | \ 460 ((sc)->ciss_id->drives_per_scsi_bus * (bus)) | \ 461 (target)) 462 463 #define CISS_BIG_MAP_BUS(sc, id) \ 464 (((id) & 0x80) ? (((id) & ~0x80) / (sc)->ciss_id->drives_per_scsi_bus) : -1) 465 466 #define CISS_BIG_MAP_TARGET(sc, id) \ 467 (((id) & 0x80) ? (((id) & ~0x80) % (sc)->ciss_id->drives_per_scsi_bus) : -1) 468 469 #define CISS_BIG_MAP_ENTRIES 128 /* number of entries in a BIG_MAP */ 470 471 /* 472 * In the device address of a logical volume, the bus number 473 * is encoded into the logical lun volume number starting 474 * at the second byte, with the first byte defining the 475 * logical drive number. 476 */ 477 #define CISS_LUN_TO_BUS(x) (((x) >> 16) & 0xFF) 478 #define CISS_LUN_TO_TARGET(x) ((x) & 0xFF) 479 480 /* 481 * BMIC CDB 482 * 483 * Note that the phys_drive/res1 field is nominally the 32-bit 484 * "block number" field, but the only BMIC command(s) of interest 485 * implemented overload the MSB (note big-endian format here) 486 * to be the physical drive ID, so we define accordingly. 487 */ 488 struct ciss_bmic_cdb { 489 u_int8_t opcode; 490 u_int8_t log_drive; 491 u_int8_t phys_drive; 492 u_int8_t res1[3]; 493 u_int8_t bmic_opcode; 494 u_int16_t size; /* big-endian */ 495 u_int8_t res2; 496 } __packed; 497 498 /* 499 * BMIC command command/return structures. 500 */ 501 502 /* CISS_BMIC_ID_LDRIVE */ 503 struct ciss_bmic_id_ldrive { 504 u_int16_t block_size; 505 u_int32_t blocks_available; 506 u_int8_t drive_parameter_table[16]; /* XXX define */ 507 u_int8_t fault_tolerance; 508 #define CISS_LDRIVE_RAID0 0 509 #define CISS_LDRIVE_RAID4 1 510 #define CISS_LDRIVE_RAID1 2 511 #define CISS_LDRIVE_RAID5 3 512 #define CISS_LDRIVE_RAID51 4 513 #define CISS_LDRIVE_RAIDADG 5 514 u_int8_t res1[2]; 515 #if 0 /* only for identify logical drive extended (0x18) */ 516 u_int32_t logical_drive_identifier; 517 char logical_drive_label[64]; 518 #endif 519 } __packed; 520 521 /* CISS_BMIC_ID_LSTATUS */ 522 struct ciss_bmic_id_lstatus { 523 u_int8_t status; 524 #define CISS_LSTATUS_OK 0 525 #define CISS_LSTATUS_FAILED 1 526 #define CISS_LSTATUS_NOT_CONFIGURED 2 527 #define CISS_LSTATUS_INTERIM_RECOVERY 3 528 #define CISS_LSTATUS_READY_RECOVERY 4 529 #define CISS_LSTATUS_RECOVERING 5 530 #define CISS_LSTATUS_WRONG_PDRIVE 6 531 #define CISS_LSTATUS_MISSING_PDRIVE 7 532 #define CISS_LSTATUS_EXPANDING 10 533 #define CISS_LSTATUS_BECOMING_READY 11 534 #define CISS_LSTATUS_QUEUED_FOR_EXPANSION 12 535 u_int32_t deprecated_drive_failure_map; 536 u_int8_t res1[416]; 537 u_int32_t blocks_to_recover; 538 u_int8_t deprecated_drive_rebuilding; 539 u_int16_t deprecated_remap_count[32]; 540 u_int32_t deprecated_replacement_map; 541 u_int32_t deprecated_active_spare_map; 542 u_int8_t spare_configured:1; 543 u_int8_t spare_rebuilding:1; 544 u_int8_t spare_rebuilt:1; 545 u_int8_t spare_failed:1; 546 u_int8_t spare_switched:1; 547 u_int8_t spare_available:1; 548 u_int8_t res2:2; 549 u_int8_t deprecated_spare_to_replace_map[32]; 550 u_int32_t deprecated_replaced_marked_ok_map; 551 u_int8_t media_exchanged; 552 u_int8_t cache_failure; 553 u_int8_t expand_failure; 554 u_int8_t rebuild_read_failure:1; 555 u_int8_t rebuild_write_failure:1; 556 u_int8_t res3:6; 557 u_int8_t drive_failure_map[CISS_BIG_MAP_ENTRIES / 8]; 558 u_int16_t remap_count[CISS_BIG_MAP_ENTRIES]; 559 u_int8_t replacement_map[CISS_BIG_MAP_ENTRIES / 8]; 560 u_int8_t active_spare_map[CISS_BIG_MAP_ENTRIES / 8]; 561 u_int8_t spare_to_replace_map[CISS_BIG_MAP_ENTRIES]; 562 u_int8_t replaced_marked_ok_map[CISS_BIG_MAP_ENTRIES / 8]; 563 u_int8_t drive_rebuilding; 564 } __packed; 565 566 /* CISS_BMIC_ID_CTLR */ 567 struct ciss_bmic_id_table { 568 u_int8_t configured_logical_drives; 569 u_int32_t config_signature; 570 char running_firmware_revision[4]; 571 char stored_firmware_revision[4]; 572 u_int8_t hardware_revision; 573 u_int8_t res1[4]; 574 u_int32_t deprecated_drive_present_map; 575 u_int32_t deprecated_external_drive_present_map; 576 u_int32_t board_id; 577 u_int8_t res2; 578 u_int32_t deprecated_non_disk_map; 579 u_int8_t res3[5]; 580 char marketting_revision; 581 u_int8_t res4:3; 582 u_int8_t more_than_seven_supported:1; 583 u_int8_t res5:3; 584 u_int8_t big_map_supported:1; /* must be set! */ 585 u_int8_t res6[2]; 586 u_int8_t scsi_bus_count; 587 u_int32_t res7; 588 u_int32_t controller_clock; 589 u_int8_t drives_per_scsi_bus; 590 u_int8_t big_drive_present_map[CISS_BIG_MAP_ENTRIES / 8]; 591 u_int8_t big_external_drive_present_map[CISS_BIG_MAP_ENTRIES / 8]; 592 u_int8_t big_non_disk_map[CISS_BIG_MAP_ENTRIES / 8]; 593 } __packed; 594 595 /* CISS_BMIC_ID_PDRIVE */ 596 struct ciss_bmic_id_pdrive { 597 u_int8_t scsi_bus; 598 u_int8_t scsi_id; 599 u_int16_t block_size; 600 u_int32_t total_blocks; 601 u_int32_t reserved_blocks; 602 char model[40]; 603 char serial[40]; 604 char revision[8]; 605 u_int8_t inquiry_bits; 606 u_int8_t res1[2]; 607 u_int8_t drive_present:1; 608 u_int8_t non_disk:1; 609 u_int8_t wide:1; 610 u_int8_t synchronous:1; 611 u_int8_t narrow:1; 612 u_int8_t wide_downgraded_to_narrow:1; 613 u_int8_t ultra:1; 614 u_int8_t ultra2:1; 615 u_int8_t SMART:1; 616 u_int8_t SMART_errors_recorded:1; 617 u_int8_t SMART_errors_enabled:1; 618 u_int8_t SMART_errors_detected:1; 619 u_int8_t external:1; 620 u_int8_t configured:1; 621 u_int8_t configured_spare:1; 622 u_int8_t cache_saved_enabled:1; 623 u_int8_t res2; 624 u_int8_t res3:6; 625 u_int8_t cache_currently_enabled:1; 626 u_int8_t cache_safe:1; 627 u_int8_t res4[5]; 628 char connector[2]; 629 u_int8_t res5; 630 u_int8_t bay; 631 u_int16_t rpm; 632 u_int8_t drive_type; 633 u_int8_t res6[393]; 634 } __packed; 635 636 /* CISS_BMIC_BLINK_PDRIVE */ 637 /* CISS_BMIC_SENSE_BLINK_PDRIVE */ 638 struct ciss_bmic_blink_pdrive { 639 u_int32_t blink_duration; /* 10ths of a second */ 640 u_int32_t duration_elapsed; /* only for sense command */ 641 u_int8_t blinktab[256]; 642 #define CISS_BMIC_BLINK_ALL 1 643 #define CISS_BMIC_BLINK_TIMED 2 644 u_int8_t res2[248]; 645 } __packed; 646 647 /* CISS_BMIC_FLUSH_CACHE */ 648 struct ciss_bmic_flush_cache { 649 u_int16_t flag; 650 #define CISS_BMIC_FLUSH_AND_ENABLE 0 651 #define CISS_BMIC_FLUSH_AND_DISABLE 1 652 u_int8_t res1[510]; 653 } __packed; 654 655 #ifdef _KERNEL 656 /* 657 * CISS "simple" transport layer. 658 * 659 * Note that there are two slightly different versions of this interface 660 * with different interrupt mask bits. There's nothing like consistency... 661 */ 662 #define CISS_TL_SIMPLE_BAR_REGS 0x10 /* BAR pointing to register space */ 663 #define CISS_TL_SIMPLE_BAR_CFG 0x14 /* BAR pointing to space containing config table */ 664 665 #define CISS_TL_SIMPLE_IDBR 0x20 /* inbound doorbell register */ 666 #define CISS_TL_SIMPLE_IDBR_CFG_TABLE (1<<0) /* notify controller of config table update */ 667 668 #define CISS_TL_SIMPLE_ISR 0x30 /* interrupt status register */ 669 #define CISS_TL_SIMPLE_IMR 0x34 /* interrupt mask register */ 670 #define CISS_TL_SIMPLE_INTR_OPQ_SA5 (1<<3) /* OPQ not empty interrupt, SA5 boards */ 671 #define CISS_TL_SIMPLE_INTR_OPQ_SA5B (1<<2) /* OPQ not empty interrupt, SA5B boards */ 672 673 #define CISS_TL_SIMPLE_IPQ 0x40 /* inbound post queue */ 674 #define CISS_TL_SIMPLE_OPQ 0x44 /* outbound post queue */ 675 #define CISS_TL_SIMPLE_OPQ_EMPTY (~(u_int32_t)0) 676 677 #define CISS_TL_SIMPLE_CFG_BAR 0xb4 /* should be 0x14 */ 678 #define CISS_TL_SIMPLE_CFG_OFF 0xb8 /* offset in BAR at which config table is located */ 679 680 /* 681 * Register access primitives. 682 */ 683 #define CISS_TL_SIMPLE_READ(sc, ofs) \ 684 bus_space_read_4(sc->ciss_regs_btag, sc->ciss_regs_bhandle, ofs) 685 #define CISS_TL_SIMPLE_WRITE(sc, ofs, val) \ 686 bus_space_write_4(sc->ciss_regs_btag, sc->ciss_regs_bhandle, ofs, val) 687 688 #define CISS_TL_SIMPLE_POST_CMD(sc, phys) CISS_TL_SIMPLE_WRITE(sc, CISS_TL_SIMPLE_IPQ, phys) 689 #define CISS_TL_SIMPLE_FETCH_CMD(sc) CISS_TL_SIMPLE_READ(sc, CISS_TL_SIMPLE_OPQ) 690 691 /* 692 * XXX documentation conflicts with the Linux driver as to whether setting or clearing 693 * bits masks interrupts 694 */ 695 #define CISS_TL_SIMPLE_DISABLE_INTERRUPTS(sc) \ 696 CISS_TL_SIMPLE_WRITE(sc, CISS_TL_SIMPLE_IMR, \ 697 CISS_TL_SIMPLE_READ(sc, CISS_TL_SIMPLE_IMR) | (sc)->ciss_interrupt_mask) 698 #define CISS_TL_SIMPLE_ENABLE_INTERRUPTS(sc) \ 699 CISS_TL_SIMPLE_WRITE(sc, CISS_TL_SIMPLE_IMR, \ 700 CISS_TL_SIMPLE_READ(sc, CISS_TL_SIMPLE_IMR) & ~(sc)->ciss_interrupt_mask) 701 702 #define CISS_TL_SIMPLE_OPQ_INTERRUPT(sc) \ 703 (CISS_TL_SIMPLE_READ(sc, CISS_TL_SIMPLE_ISR) & (sc)->ciss_interrupt_mask) 704 705 #endif /* _KERNEL */ 706