1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2001 Michael Smith 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * $FreeBSD$ 29 */ 30 31 /* 32 * Structure and I/O definitions for the Command Interface for SCSI-3 Support. 33 * 34 * Data in command CDBs are in big-endian format. All other data is little-endian. 35 * This header only supports little-endian hosts at this time. 36 */ 37 38 union ciss_device_address 39 { 40 struct /* MODE_PERIPHERAL and MODE_MASK_PERIPHERAL */ 41 { 42 u_int32_t target:24; /* SCSI target */ 43 u_int32_t bus:6; /* SCSI bus */ 44 u_int32_t mode:2; /* CISS_HDR_ADDRESS_MODE_* */ 45 u_int32_t extra_address; /* SCSI-3 level-2 and level-3 address bytes */ 46 } physical; 47 struct /* MODE_LOGICAL */ 48 { 49 u_int32_t lun:30; /* logical device ID */ 50 u_int32_t mode:2; /* CISS_HDR_ADDRESS_MODE_LOGICAL */ 51 u_int32_t :32; /* reserved */ 52 } logical; 53 struct 54 { 55 u_int32_t :30; 56 u_int32_t mode:2; 57 u_int32_t :32; 58 } mode; 59 }; 60 #define CISS_HDR_ADDRESS_MODE_PERIPHERAL 0x0 61 #define CISS_HDR_ADDRESS_MODE_LOGICAL 0x1 62 #define CISS_HDR_ADDRESS_MODE_MASK_PERIPHERAL 0x3 63 64 #define CISS_EXTRA_MODE2(extra) ((extra & 0xc0000000) >> 30) 65 #define CISS_EXTRA_BUS2(extra) ((extra & 0x3f000000) >> 24) 66 #define CISS_EXTRA_TARGET2(extra) ((extra & 0x00ff0000) >> 16) 67 #define CISS_EXTRA_MODE3(extra) ((extra & 0x0000c000) >> 14) 68 #define CISS_EXTRA_BUS3(extra) ((extra & 0x00003f00) >> 8) 69 #define CISS_EXTRA_TARGET3(extra) ((extra & 0x000000ff)) 70 71 struct ciss_header 72 { 73 u_int8_t :8; /* reserved */ 74 u_int8_t sg_in_list; /* SG's in the command structure */ 75 u_int16_t sg_total; /* total count of SGs for this command */ 76 u_int32_t host_tag; /* host identifier, bits 0&1 must be clear */ 77 #define CISS_HDR_HOST_TAG_ERROR (1<<1) 78 u_int32_t host_tag_zeroes; /* tag is 64 bits, but interface only supports 32 */ 79 union ciss_device_address address; 80 } __packed; 81 82 struct ciss_cdb 83 { 84 u_int8_t cdb_length; /* valid CDB bytes */ 85 u_int8_t type:3; 86 #define CISS_CDB_TYPE_COMMAND 0 87 #define CISS_CDB_TYPE_MESSAGE 1 88 u_int8_t attribute:3; 89 #define CISS_CDB_ATTRIBUTE_UNTAGGED 0 90 #define CISS_CDB_ATTRIBUTE_SIMPLE 4 91 #define CISS_CDB_ATTRIBUTE_HEAD_OF_QUEUE 5 92 #define CISS_CDB_ATTRIBUTE_ORDERED 6 93 #define CISS_CDB_ATTRIBUTE_AUTO_CONTINGENT 7 94 u_int8_t direction:2; 95 #define CISS_CDB_DIRECTION_NONE 0 96 #define CISS_CDB_DIRECTION_WRITE 1 97 #define CISS_CDB_DIRECTION_READ 2 98 u_int16_t timeout; /* seconds */ 99 #define CISS_CDB_BUFFER_SIZE 16 100 u_int8_t cdb[CISS_CDB_BUFFER_SIZE]; 101 } __packed; 102 103 struct ciss_error_info_pointer 104 { 105 u_int64_t error_info_address; /* points to ciss_error_info structure */ 106 u_int32_t error_info_length; 107 } __packed; 108 109 struct ciss_error_info 110 { 111 u_int8_t scsi_status; 112 #define CISS_SCSI_STATUS_GOOD 0x00 /* these are scsi-standard values */ 113 #define CISS_SCSI_STATUS_CHECK_CONDITION 0x02 114 #define CISS_SCSI_STATUS_CONDITION_MET 0x04 115 #define CISS_SCSI_STATUS_BUSY 0x08 116 #define CISS_SCSI_STATUS_INDETERMINATE 0x10 117 #define CISS_SCSI_STATUS_INDETERMINATE_CM 0x14 118 #define CISS_SCSI_STATUS_RESERVATION_CONFLICT 0x18 119 #define CISS_SCSI_STATUS_COMMAND_TERMINATED 0x22 120 #define CISS_SCSI_STATUS_QUEUE_FULL 0x28 121 #define CISS_SCSI_STATUS_ACA_ACTIVE 0x30 122 u_int8_t sense_length; 123 u_int16_t command_status; 124 #define CISS_CMD_STATUS_SUCCESS 0 125 #define CISS_CMD_STATUS_TARGET_STATUS 1 126 #define CISS_CMD_STATUS_DATA_UNDERRUN 2 127 #define CISS_CMD_STATUS_DATA_OVERRUN 3 128 #define CISS_CMD_STATUS_INVALID_COMMAND 4 129 #define CISS_CMD_STATUS_PROTOCOL_ERROR 5 130 #define CISS_CMD_STATUS_HARDWARE_ERROR 6 131 #define CISS_CMD_STATUS_CONNECTION_LOST 7 132 #define CISS_CMD_STATUS_ABORTED 8 133 #define CISS_CMD_STATUS_ABORT_FAILED 9 134 #define CISS_CMD_STATUS_UNSOLICITED_ABORT 10 135 #define CISS_CMD_STATUS_TIMEOUT 11 136 #define CISS_CMD_STATUS_UNABORTABLE 12 137 u_int32_t residual_count; 138 union { 139 struct { 140 u_int8_t res1[3]; 141 u_int8_t type; 142 u_int32_t error_info; 143 } __packed common_info; 144 struct { 145 u_int8_t res1[2]; 146 u_int8_t offense_size; 147 u_int8_t offense_offset; 148 u_int32_t offense_value; 149 } __packed invalid_command; 150 } additional_error_info; 151 u_int8_t sense_info[0]; 152 } __packed; 153 154 struct ciss_sg_entry 155 { 156 u_int64_t address; 157 #define CISS_SG_ADDRESS_BITBUCKET (~(u_int64_t)0) 158 u_int32_t length; 159 u_int32_t :31; 160 u_int32_t extension:1; /* address points to another s/g chain */ 161 } __packed; 162 163 struct ciss_command 164 { 165 struct ciss_header header; 166 struct ciss_cdb cdb; 167 struct ciss_error_info_pointer error_info; 168 struct ciss_sg_entry sg[0]; 169 } __packed; 170 171 #define CISS_OPCODE_REPORT_LOGICAL_LUNS 0xc2 172 #define CISS_OPCODE_REPORT_PHYSICAL_LUNS 0xc3 173 174 struct ciss_lun_report 175 { 176 u_int32_t list_size; /* big-endian */ 177 u_int32_t :32; 178 union ciss_device_address lun[0]; 179 } __packed; 180 181 #define CISS_VPD_LOGICAL_DRIVE_GEOMETRY 0xc1 182 struct ciss_ldrive_geometry 183 { 184 u_int8_t periph_qualifier:3; 185 u_int8_t periph_devtype:5; 186 u_int8_t page_code; 187 u_int8_t res1; 188 u_int8_t page_length; 189 u_int16_t cylinders; /* big-endian */ 190 u_int8_t heads; 191 u_int8_t sectors; 192 u_int8_t fault_tolerance; 193 u_int8_t res2[3]; 194 } __attribute__ ((packed)); 195 196 struct ciss_report_cdb 197 { 198 u_int8_t opcode; 199 u_int8_t reserved[5]; 200 u_int32_t length; /* big-endian */ 201 u_int8_t :8; 202 u_int8_t control; 203 } __packed; 204 205 /* 206 * Note that it's not clear whether we have to set the detail field to 207 * the tag of the command to be aborted, or the tag field in the command itself; 208 * documentation conflicts on this. 209 */ 210 #define CISS_OPCODE_MESSAGE_ABORT 0x00 211 #define CISS_MESSAGE_ABORT_TASK 0x00 212 #define CISS_MESSAGE_ABORT_TASK_SET 0x01 213 #define CISS_MESSAGE_ABORT_CLEAR_ACA 0x02 214 #define CISS_MESSAGE_ABORT_CLEAR_TASK_SET 0x03 215 216 #define CISS_OPCODE_MESSAGE_RESET 0x01 217 #define CISS_MESSAGE_RESET_CONTROLLER 0x00 218 #define CISS_MESSAGE_RESET_BUS 0x01 219 #define CISS_MESSAGE_RESET_TARGET 0x03 220 #define CISS_MESSAGE_RESET_LOGICAL_UNIT 0x04 221 222 #define CISS_OPCODE_MESSAGE_SCAN 0x02 223 #define CISS_MESSAGE_SCAN_CONTROLLER 0x00 224 #define CISS_MESSAGE_SCAN_BUS 0x01 225 #define CISS_MESSAGE_SCAN_TARGET 0x03 226 #define CISS_MESSAGE_SCAN_LOGICAL_UNIT 0x04 227 228 #define CISS_OPCODE_MESSAGE_NOP 0x03 229 230 struct ciss_message_cdb 231 { 232 u_int8_t opcode; 233 u_int8_t type; 234 u_int16_t :16; 235 u_int32_t abort_tag; /* XXX endianness? */ 236 u_int8_t reserved[8]; 237 } __packed; 238 239 /* 240 * CISS vendor-specific commands/messages. 241 * 242 * Note that while messages and vendor-specific commands are 243 * differentiated, they are handled in basically the same way and can 244 * be considered to be basically the same thing, as long as the cdb 245 * type field is set correctly. 246 */ 247 #define CISS_OPCODE_READ 0xc0 248 #define CISS_OPCODE_WRITE 0xc1 249 #define CISS_COMMAND_NOTIFY_ON_EVENT 0xd0 250 #define CISS_COMMAND_ABORT_NOTIFY 0xd1 251 252 struct ciss_notify_cdb 253 { 254 u_int8_t opcode; 255 u_int8_t command; 256 u_int8_t res1[2]; 257 u_int16_t timeout; /* seconds, little-endian */ 258 u_int8_t res2; /* reserved */ 259 u_int8_t synchronous:1; /* return immediately */ 260 u_int8_t ordered:1; /* return events in recorded order */ 261 u_int8_t seek_to_oldest:1; /* reset read counter to oldest event */ 262 u_int8_t new_only:1; /* ignore any queued events */ 263 u_int8_t :4; 264 u_int32_t length; /* must be 512, little-endian */ 265 #define CISS_NOTIFY_DATA_SIZE 512 266 u_int8_t control; 267 } __packed; 268 269 #define CISS_NOTIFY_NOTIFIER 0 270 #define CISS_NOTIFY_NOTIFIER_STATUS 0 271 #define CISS_NOTIFY_NOTIFIER_PROTOCOL 1 272 273 #define CISS_NOTIFY_HOTPLUG 1 274 #define CISS_NOTIFY_HOTPLUG_PHYSICAL 0 275 #define CISS_NOTIFY_HOTPLUG_POWERSUPPLY 1 276 #define CISS_NOTIFY_HOTPLUG_FAN 2 277 #define CISS_NOTIFY_HOTPLUG_POWER 3 278 #define CISS_NOTIFY_HOTPLUG_REDUNDANT 4 279 #define CISS_NOTIFY_HOTPLUG_NONDISK 5 280 281 #define CISS_NOTIFY_HARDWARE 2 282 #define CISS_NOTIFY_HARDWARE_CABLES 0 283 #define CISS_NOTIFY_HARDWARE_MEMORY 1 284 #define CISS_NOTIFY_HARDWARE_FAN 2 285 #define CISS_NOTIFY_HARDWARE_VRM 3 286 287 #define CISS_NOTIFY_ENVIRONMENT 3 288 #define CISS_NOTIFY_ENVIRONMENT_TEMPERATURE 0 289 #define CISS_NOTIFY_ENVIRONMENT_POWERSUPPLY 1 290 #define CISS_NOTIFY_ENVIRONMENT_CHASSIS 2 291 #define CISS_NOTIFY_ENVIRONMENT_POWER 3 292 293 #define CISS_NOTIFY_PHYSICAL 4 294 #define CISS_NOTIFY_PHYSICAL_STATE 0 295 296 #define CISS_NOTIFY_LOGICAL 5 297 #define CISS_NOTIFY_LOGICAL_STATUS 0 298 #define CISS_NOTIFY_LOGICAL_ERROR 1 299 #define CISS_NOTIFY_LOGICAL_SURFACE 2 300 301 #define CISS_NOTIFY_REDUNDANT 6 302 #define CISS_NOTIFY_REDUNDANT_STATUS 0 303 304 #define CISS_NOTIFY_CISS 8 305 #define CISS_NOTIFY_CISS_REDUNDANT_CHANGE 0 306 #define CISS_NOTIFY_CISS_PATH_STATUS 1 307 #define CISS_NOTIFY_CISS_HARDWARE_ERROR 2 308 #define CISS_NOTIFY_CISS_LOGICAL 3 309 310 struct ciss_notify_drive 311 { 312 u_int16_t physical_drive_number; 313 u_int8_t configured_drive_flag; 314 u_int8_t spare_drive_flag; 315 u_int8_t big_physical_drive_number; 316 u_int8_t enclosure_bay_number; 317 } __packed; 318 319 struct ciss_notify_locator 320 { 321 u_int16_t port; 322 u_int16_t id; 323 u_int16_t box; 324 } __packed; 325 326 struct ciss_notify_redundant_controller 327 { 328 u_int16_t slot; 329 } __packed; 330 331 struct ciss_notify_logical_status 332 { 333 u_int16_t logical_drive; 334 u_int8_t previous_state; 335 u_int8_t new_state; 336 u_int8_t spare_state; 337 } __packed; 338 339 struct ciss_notify_rebuild_aborted 340 { 341 u_int16_t logical_drive; 342 u_int8_t replacement_drive; 343 u_int8_t error_drive; 344 u_int8_t big_replacement_drive; 345 u_int8_t big_error_drive; 346 } __packed; 347 348 struct ciss_notify_io_error 349 { 350 u_int16_t logical_drive; 351 u_int32_t lba; 352 u_int16_t block_count; 353 u_int8_t command; 354 u_int8_t failure_bus; 355 u_int8_t failure_drive; 356 u_int64_t big_lba; 357 } __packed; 358 359 struct ciss_notify_consistency_completed 360 { 361 u_int16_t logical_drive; 362 } __packed; 363 364 struct ciss_notify 365 { 366 u_int32_t timestamp; /* seconds since controller power-on */ 367 u_int16_t class; 368 u_int16_t subclass; 369 u_int16_t detail; 370 union 371 { 372 struct ciss_notify_drive drive; 373 struct ciss_notify_locator location; 374 struct ciss_notify_redundant_controller redundant_controller; 375 struct ciss_notify_logical_status logical_status; 376 struct ciss_notify_rebuild_aborted rebuild_aborted; 377 struct ciss_notify_io_error io_error; 378 struct ciss_notify_consistency_completed consistency_completed; 379 u_int8_t data[64]; 380 } data; 381 char message[80]; 382 u_int32_t tag; 383 u_int16_t date; 384 u_int16_t year; 385 u_int32_t time; 386 u_int16_t pre_power_up_time; 387 union ciss_device_address device; 388 /* XXX pads to 512 bytes */ 389 } __packed; 390 391 /* 392 * CISS config table, which describes the controller's 393 * supported interface(s) and capabilities. 394 * 395 * This is mapped directly via PCI. 396 */ 397 struct ciss_config_table 398 { 399 char signature[4]; /* "CISS" */ 400 u_int32_t valence; 401 u_int32_t supported_methods; 402 #define CISS_TRANSPORT_METHOD_READY (1<<0) 403 #define CISS_TRANSPORT_METHOD_SIMPLE (1<<1) 404 #define CISS_TRANSPORT_METHOD_PERF (1<<2) 405 u_int32_t active_method; 406 u_int32_t requested_method; 407 u_int32_t command_physlimit; 408 u_int32_t interrupt_coalesce_delay; 409 u_int32_t interrupt_coalesce_count; 410 u_int32_t max_outstanding_commands; 411 u_int32_t bus_types; 412 #define CISS_TRANSPORT_BUS_TYPE_ULTRA2 (1<<0) 413 #define CISS_TRANSPORT_BUS_TYPE_ULTRA3 (1<<1) 414 #define CISS_TRANSPORT_BUS_TYPE_FIBRE1 (1<<8) 415 #define CISS_TRANSPORT_BUS_TYPE_FIBRE2 (1<<9) 416 u_int32_t transport_offset; 417 char server_name[16]; 418 u_int32_t heartbeat; 419 u_int32_t host_driver; 420 #define CISS_DRIVER_SUPPORT_UNIT_ATTENTION (1<<0) 421 #define CISS_DRIVER_QUICK_INIT (1<<1) 422 #define CISS_DRIVER_INTERRUPT_ON_LOCKUP (1<<2) 423 #define CISS_DRIVER_SUPPORT_MIXED_Q_TAGS (1<<3) 424 #define CISS_DRIVER_HOST_IS_ALPHA (1<<4) 425 #define CISS_DRIVER_MULTI_LUN_SUPPORT (1<<5) 426 #define CISS_DRIVER_MESSAGE_REQUESTS_SUPPORTED (1<<7) 427 #define CISS_DRIVER_DAUGHTER_ATTACHED (1<<8) 428 #define CISS_DRIVER_SCSI_PREFETCH (1<<9) 429 u_int32_t max_sg_length; /* 31 in older firmware */ 430 /* 431 * these fields appear in OpenCISS Spec 1.06 432 * http://cciss.sourceforge.net/#docs 433 */ 434 u_int32_t max_logical_supported; 435 u_int32_t max_physical_supported; 436 u_int32_t max_physical_per_logical; 437 u_int32_t max_perfomant_mode_cmds; 438 u_int32_t max_block_fetch_count; 439 } __packed; 440 441 /* 442 * Configuration table for the Performant transport. Only 4 request queues 443 * are mentioned in this table, though apparently up to 256 can exist. 444 */ 445 struct ciss_perf_config { 446 uint32_t fetch_count[8]; 447 #define CISS_SG_FETCH_MAX 0 448 #define CISS_SG_FETCH_1 1 449 #define CISS_SG_FETCH_2 2 450 #define CISS_SG_FETCH_4 3 451 #define CISS_SG_FETCH_8 4 452 #define CISS_SG_FETCH_16 5 453 #define CISS_SG_FETCH_32 6 454 #define CISS_SG_FETCH_NONE 7 455 uint32_t rq_size; 456 uint32_t rq_count; 457 uint32_t rq_bank_lo; 458 uint32_t rq_bank_hi; 459 struct { 460 uint32_t rq_addr_lo; 461 uint32_t rq_addr_hi; 462 } __packed rq[4]; 463 } __packed; 464 465 /* 466 * In a flagrant violation of what CISS seems to be meant to be about, 467 * Compaq recycle a goodly portion of their previous generation's 468 * command set (and all the legacy baggage related to a design 469 * originally aimed at narrow SCSI) through the Array Controller Read 470 * and Array Controller Write interface. 471 * 472 * Command ID values here can be looked up for in the 473 * publically-available documentation for the older controllers; note 474 * that the command layout is necessarily different to fit within the 475 * CDB. 476 */ 477 #define CISS_ARRAY_CONTROLLER_READ 0x26 478 #define CISS_ARRAY_CONTROLLER_WRITE 0x27 479 480 #define CISS_BMIC_ID_LDRIVE 0x10 481 #define CISS_BMIC_ID_CTLR 0x11 482 #define CISS_BMIC_ID_LSTATUS 0x12 483 #define CISS_BMIC_ID_PDRIVE 0x15 484 #define CISS_BMIC_BLINK_PDRIVE 0x16 485 #define CISS_BMIC_SENSE_BLINK_PDRIVE 0x17 486 #define CISS_BMIC_SOFT_RESET 0x40 487 #define CISS_BMIC_FLUSH_CACHE 0xc2 488 #define CISS_BMIC_ACCEPT_MEDIA 0xe0 489 490 /* 491 * When numbering drives, the original design assumed that 492 * drives 0-7 are on the first SCSI bus, 8-15 on the second, 493 * and so forth. In order to handle modern SCSI configurations, 494 * the MSB is set in the drive ID field, in which case the 495 * modulus changes from 8 to the number of supported drives 496 * per SCSI bus (as obtained from the ID_CTLR command). 497 * This feature is referred to as BIG_MAP support, and we assume 498 * that all CISS controllers support it. 499 */ 500 501 #define CISS_BIG_MAP_ID(sc, bus, target) \ 502 (0x80 | \ 503 ((sc)->ciss_id->drives_per_scsi_bus * (bus)) | \ 504 (target)) 505 506 #define CISS_BIG_MAP_BUS(sc, id) \ 507 (((id) & 0x80) ? (((id) & ~0x80) / (sc)->ciss_id->drives_per_scsi_bus) : -1) 508 509 #define CISS_BIG_MAP_TARGET(sc, id) \ 510 (((id) & 0x80) ? (((id) & ~0x80) % (sc)->ciss_id->drives_per_scsi_bus) : -1) 511 512 #define CISS_BIG_MAP_ENTRIES 128 /* number of entries in a BIG_MAP */ 513 514 /* 515 * In the device address of a logical volume, the bus number 516 * is encoded into the logical lun volume number starting 517 * at the second byte, with the first byte defining the 518 * logical drive number. 519 */ 520 #define CISS_LUN_TO_BUS(x) (((x) >> 16) & 0xFF) 521 #define CISS_LUN_TO_TARGET(x) ((x) & 0xFF) 522 523 /* 524 * BMIC CDB 525 * 526 * Note that the phys_drive/res1 field is nominally the 32-bit 527 * "block number" field, but the only BMIC command(s) of interest 528 * implemented overload the MSB (note big-endian format here) 529 * to be the physical drive ID, so we define accordingly. 530 */ 531 struct ciss_bmic_cdb { 532 u_int8_t opcode; 533 u_int8_t log_drive; 534 u_int8_t phys_drive; 535 u_int8_t res1[3]; 536 u_int8_t bmic_opcode; 537 u_int16_t size; /* big-endian */ 538 u_int8_t res2; 539 } __packed; 540 541 /* 542 * BMIC command command/return structures. 543 */ 544 545 /* CISS_BMIC_ID_LDRIVE */ 546 struct ciss_bmic_id_ldrive { 547 u_int16_t block_size; 548 u_int32_t blocks_available; 549 u_int8_t drive_parameter_table[16]; /* XXX define */ 550 u_int8_t fault_tolerance; 551 #define CISS_LDRIVE_RAID0 0 552 #define CISS_LDRIVE_RAID4 1 553 #define CISS_LDRIVE_RAID1 2 554 #define CISS_LDRIVE_RAID5 3 555 #define CISS_LDRIVE_RAID51 4 556 #define CISS_LDRIVE_RAIDADG 5 557 u_int8_t res1; 558 u_int8_t bios_disable_flag; 559 u_int8_t res2; 560 u_int32_t logical_drive_identifier; 561 char logical_drive_label[64]; 562 u_int64_t big_blocks_available; 563 u_int8_t res3[410]; 564 } __packed; 565 566 /* CISS_BMIC_ID_LSTATUS */ 567 struct ciss_bmic_id_lstatus { 568 u_int8_t status; 569 #define CISS_LSTATUS_OK 0 570 #define CISS_LSTATUS_FAILED 1 571 #define CISS_LSTATUS_NOT_CONFIGURED 2 572 #define CISS_LSTATUS_INTERIM_RECOVERY 3 573 #define CISS_LSTATUS_READY_RECOVERY 4 574 #define CISS_LSTATUS_RECOVERING 5 575 #define CISS_LSTATUS_WRONG_PDRIVE 6 576 #define CISS_LSTATUS_MISSING_PDRIVE 7 577 #define CISS_LSTATUS_EXPANDING 10 578 #define CISS_LSTATUS_BECOMING_READY 11 579 #define CISS_LSTATUS_QUEUED_FOR_EXPANSION 12 580 u_int32_t deprecated_drive_failure_map; 581 u_int8_t res1[416]; 582 u_int32_t blocks_to_recover; 583 u_int8_t deprecated_drive_rebuilding; 584 u_int16_t deprecated_remap_count[32]; 585 u_int32_t deprecated_replacement_map; 586 u_int32_t deprecated_active_spare_map; 587 u_int8_t spare_configured:1; 588 u_int8_t spare_rebuilding:1; 589 u_int8_t spare_rebuilt:1; 590 u_int8_t spare_failed:1; 591 u_int8_t spare_switched:1; 592 u_int8_t spare_available:1; 593 u_int8_t res2:2; 594 u_int8_t deprecated_spare_to_replace_map[32]; 595 u_int32_t deprecated_replaced_marked_ok_map; 596 u_int8_t media_exchanged; 597 u_int8_t cache_failure; 598 u_int8_t expand_failure; 599 u_int8_t rebuild_read_failure:1; 600 u_int8_t rebuild_write_failure:1; 601 u_int8_t res3:6; 602 u_int8_t drive_failure_map[CISS_BIG_MAP_ENTRIES / 8]; 603 u_int16_t remap_count[CISS_BIG_MAP_ENTRIES]; 604 u_int8_t replacement_map[CISS_BIG_MAP_ENTRIES / 8]; 605 u_int8_t active_spare_map[CISS_BIG_MAP_ENTRIES / 8]; 606 u_int8_t spare_to_replace_map[CISS_BIG_MAP_ENTRIES]; 607 u_int8_t replaced_marked_ok_map[CISS_BIG_MAP_ENTRIES / 8]; 608 u_int8_t drive_rebuilding; 609 u_int64_t big_blocks_to_recover; 610 u_int8_t res4[28]; 611 } __packed; 612 613 /* CISS_BMIC_ID_CTLR */ 614 struct ciss_bmic_id_table { 615 u_int8_t configured_logical_drives; 616 u_int32_t config_signature; 617 char running_firmware_revision[4]; 618 char stored_firmware_revision[4]; 619 u_int8_t hardware_revision; 620 u_int8_t boot_block_revision[4]; 621 u_int32_t deprecated_drive_present_map; 622 u_int32_t deprecated_external_drive_present_map; 623 u_int32_t board_id; 624 u_int8_t swapped_error_cable; 625 u_int32_t deprecated_non_disk_map; 626 u_int8_t bad_host_ram_addr; 627 u_int8_t cpu_revision; 628 u_int8_t res3[3]; 629 char marketting_revision; 630 u_int8_t controller_flags; 631 #define CONTROLLER_FLAGS_FLASH_ROM_INSTALLED 0x01 632 #define CONTROLLER_FLAGS_DIAGS_MODE_BIT 0x02 633 #define CONTROLLER_FLAGS_EXPAND_32MB_FX 0x04 634 #define CONTROLLER_FLAGS_MORE_THAN_7_SUPPORT 0x08 635 #define CONTROLLER_FLAGS_DAISY_SUPPORT_BIT 0x10 636 #define CONTROLLER_FLAGS_RES6 0x20 637 #define CONTROLLER_FLAGS_RES7 0x40 638 #define CONTROLLER_FLAGS_BIG_MAP_SUPPORT 0x80 639 u_int8_t host_flags; 640 #define HOST_FLAGS_SDB_ASIC_WORK_AROUND 0x01 641 #define HOST_FLAGS_PCI_DATA_BUS_PARITY_SUPPORT 0x02 642 #define HOST_FLAGS_RES3 0x04 643 #define HOST_FLAGS_RES4 0x08 644 #define HOST_FLAGS_RES5 0x10 645 #define HOST_FLAGS_RES6 0x20 646 #define HOST_FLAGS_RES7 0x30 647 #define HOST_FLAGS_RES8 0x40 648 u_int8_t expand_disable_code; 649 #define EXPAND_DISABLE_NOT_NEEDED 0x01 650 #define EXPAND_DISABLE_MISSING_CACHE_BOARD 0x02 651 #define EXPAND_DISABLE_WCXC_FATAL_CACHE_BITS 0x04 652 #define EXPAND_DISABLE_CACHE_PERM_DISABLED 0x08 653 #define EXPAND_DISABLE_RAM_ALLOCATION_FAILED 0x10 654 #define EXPAND_DISABLE_BATTEREIS_DISCHARGED 0x20 655 #define EXPAND_DISABLE_RES7 0x40 656 #define EXPAND_DISABLE_REBUILD_RUNNING 0x80 657 u_int8_t scsi_chip_count; 658 u_int32_t maximum_blocks; 659 u_int32_t controller_clock; 660 u_int8_t drives_per_scsi_bus; 661 u_int8_t big_drive_present_map[CISS_BIG_MAP_ENTRIES / 8]; 662 u_int8_t big_external_drive_present_map[CISS_BIG_MAP_ENTRIES / 8]; 663 u_int8_t big_non_disk_map[CISS_BIG_MAP_ENTRIES / 8]; 664 665 u_int16_t task_flags; /* used for FW debugging */ 666 u_int8_t ICL_bus_map; /* Bitmap used for ICL between controllers */ 667 u_int8_t redund_ctlr_modes_support; /* See REDUNDANT MODE VALUES */ 668 u_int8_t curr_redund_ctlr_mode; 669 u_int8_t redund_ctlr_status; 670 u_int8_t redund_op_failure_code; 671 672 u_int8_t unsupported_nile_bus; 673 u_int8_t host_i2c_autorev; 674 u_int8_t cpld_revision; 675 u_int8_t fibre_chip_count; 676 u_int8_t daughterboard_type; 677 u_int8_t more_swapped_config_cable_error; 678 679 u_int8_t license_key_status; 680 u_int8_t access_module_status; 681 u_int8_t features_supported[12]; 682 u_int8_t rec_rom_inact_rev[4]; /* Recovery ROM inactive f/w revision */ 683 u_int8_t rec_rom_act_status; /* Recovery ROM flags */ 684 u_int8_t pci_to_pci_status; /* PCI to PCI bridge status */ 685 u_int32_t redundant_server_info; /* Reserved for future use */ 686 u_int8_t percent_write_cache; /* Percent of memory allocated to write cache */ 687 u_int16_t daughterboard_size_mb; /* Total size (MB) of cache board */ 688 u_int8_t cache_batter_count; /* Number of cache batteries */ 689 u_int16_t total_controller_mem_mb; /* Total size (MB) of atttached memory */ 690 u_int8_t more_controller_flags; /* Additional controller flags byte */ 691 u_int8_t x_board_host_i2c_rev; /* 2nd byte of 3 byte autorev field */ 692 u_int8_t battery_pic_rev; /* BBWC PIC revision */ 693 /* 694 * Below here I have no documentation on the rest of this data structure. It is 695 * inferred from the opensource cciss_vol_status application. I assume that this 696 * data strucutre is 512 bytes in total size, do not exceed it. 697 */ 698 u_int8_t bDdffVersion[4]; /* DDFF update engine version */ 699 u_int16_t usMaxLogicalUnits; /* Maximum logical units supported */ 700 u_int16_t usExtLogicalUnitCount; /* Big num configured logical units */ 701 u_int16_t usMaxPhysicalDevices; /* Maximum physical devices supported */ 702 u_int16_t usMaxPhyDrvPerLogicalUnit; /* Max physical drive per logical unit */ 703 u_int8_t bEnclosureCount; /* Number of attached enclosures */ 704 u_int8_t bExpanderCount; /* Number of expanders detected */ 705 u_int16_t usOffsetToEDPbitmap; /* Offset to extended drive present map*/ 706 u_int16_t usOffsetToEEDPbitmap; /* Offset to extended external drive present map */ 707 u_int16_t usOffsetToENDbitmap; /* Offset to extended non-disk map */ 708 u_int8_t bInternalPortStatus[8]; /* Internal port status bytes */ 709 u_int8_t bExternalPortStatus[8]; /* External port status bytes */ 710 u_int32_t uiYetMoreControllerFlags;/* Yet More Controller flags */ 711 #define YMORE_CONTROLLER_FLAGS_JBOD_SUPPORTED \ 712 ( 1 << 25 ) /* Controller has JBOD support */ 713 714 u_int8_t bLastLockup; /* Last lockup code */ 715 u_int8_t bSlot; /* PCI slot according to option ROM*/ 716 u_int16_t usBuildNum; /* Build number */ 717 u_int32_t uiMaxSafeFullStripeSize; /* Maximum safe full stripe size */ 718 u_int32_t uiTotalLength; /* Total structure length */ 719 u_int8_t bVendorID[8]; /* Vendor ID */ 720 u_int8_t bProductID[16]; /* Product ID */ 721 /* 722 * These are even more obscure as they seem to only be available in cciss_vol_status 723 */ 724 u_int32_t ExtendedLastLockupCode; 725 u_int16_t MaxRaid; 726 u_int16_t MaxParity; 727 u_int16_t MaxADGStripSize; 728 u_int16_t YetMoreSwappedCables; 729 u_int8_t MaxDevicePaths; 730 u_int8_t PowerUPNvramFlags; 731 #define PWR_UP_FLAG_JBOD_ENABLED 0x08 /*JBOD mode is enabled, all RAID features off */ 732 733 u_int16_t ZonedOffset; 734 u_int32_t FixedFieldsLength; 735 u_int8_t FWCompileTimeStamp[24]; 736 u_int32_t EvenMoreControllerFlags; 737 u_int8_t padding[240]; 738 } __packed; 739 740 /* CISS_BMIC_ID_PDRIVE */ 741 struct ciss_bmic_id_pdrive { 742 u_int8_t scsi_bus; 743 u_int8_t scsi_id; 744 u_int16_t block_size; 745 u_int32_t total_blocks; 746 u_int32_t reserved_blocks; 747 char model[40]; 748 char serial[40]; 749 char revision[8]; 750 u_int8_t inquiry_bits; 751 u_int8_t res1[2]; 752 u_int8_t drive_present:1; 753 u_int8_t non_disk:1; 754 u_int8_t wide:1; 755 u_int8_t synchronous:1; 756 u_int8_t narrow:1; 757 u_int8_t wide_downgraded_to_narrow:1; 758 u_int8_t ultra:1; 759 u_int8_t ultra2:1; 760 u_int8_t SMART:1; 761 u_int8_t SMART_errors_recorded:1; 762 u_int8_t SMART_errors_enabled:1; 763 u_int8_t SMART_errors_detected:1; 764 u_int8_t external:1; 765 u_int8_t configured:1; 766 u_int8_t configured_spare:1; 767 u_int8_t cache_saved_enabled:1; 768 u_int8_t res2; 769 u_int8_t res3:6; 770 u_int8_t cache_currently_enabled:1; 771 u_int8_t cache_safe:1; 772 u_int8_t res4[5]; 773 char connector[2]; 774 u_int8_t res5; 775 u_int8_t bay; 776 u_int16_t rpm; 777 u_int8_t drive_type; 778 u_int8_t res6[393]; 779 } __packed; 780 781 /* CISS_BMIC_BLINK_PDRIVE */ 782 /* CISS_BMIC_SENSE_BLINK_PDRIVE */ 783 struct ciss_bmic_blink_pdrive { 784 u_int32_t blink_duration; /* 10ths of a second */ 785 u_int32_t duration_elapsed; /* only for sense command */ 786 u_int8_t blinktab[256]; 787 #define CISS_BMIC_BLINK_ALL 1 788 #define CISS_BMIC_BLINK_TIMED 2 789 u_int8_t res2[248]; 790 } __packed; 791 792 /* CISS_BMIC_FLUSH_CACHE */ 793 struct ciss_bmic_flush_cache { 794 u_int16_t flag; 795 #define CISS_BMIC_FLUSH_AND_ENABLE 0 796 #define CISS_BMIC_FLUSH_AND_DISABLE 1 797 u_int8_t res1[510]; 798 } __packed; 799 800 #ifdef _KERNEL 801 /* 802 * CISS "simple" transport layer. 803 * 804 * Note that there are two slightly different versions of this interface 805 * with different interrupt mask bits. There's nothing like consistency... 806 */ 807 #define CISS_TL_SIMPLE_BAR_REGS 0x10 /* BAR pointing to register space */ 808 #define CISS_TL_SIMPLE_BAR_CFG 0x14 /* BAR pointing to space containing config table */ 809 810 #define CISS_TL_SIMPLE_IDBR 0x20 /* inbound doorbell register */ 811 #define CISS_TL_SIMPLE_IDBR_CFG_TABLE (1<<0) /* notify controller of config table update */ 812 813 #define CISS_TL_SIMPLE_ISR 0x30 /* interrupt status register */ 814 #define CISS_TL_SIMPLE_IMR 0x34 /* interrupt mask register */ 815 #define CISS_TL_SIMPLE_INTR_OPQ_SA5 (1<<3) /* OPQ not empty interrupt, SA5 boards */ 816 #define CISS_TL_SIMPLE_INTR_OPQ_SA5B (1<<2) /* OPQ not empty interrupt, SA5B boards */ 817 818 #define CISS_TL_SIMPLE_IPQ 0x40 /* inbound post queue */ 819 #define CISS_TL_SIMPLE_OPQ 0x44 /* outbound post queue */ 820 #define CISS_TL_SIMPLE_OPQ_EMPTY (~(u_int32_t)0) 821 822 #define CISS_TL_SIMPLE_OSR 0x9c /* outbound status register */ 823 #define CISS_TL_SIMPLE_ODC 0xa0 /* outbound doorbell clear register */ 824 #define CISS_TL_SIMPLE_ODC_CLEAR (0x1) 825 826 #define CISS_TL_SIMPLE_CFG_BAR 0xb4 /* should be 0x14 */ 827 #define CISS_TL_SIMPLE_CFG_OFF 0xb8 /* offset in BAR at which config table is located */ 828 829 /* 830 * Register access primitives. 831 */ 832 #define CISS_TL_SIMPLE_READ(sc, ofs) \ 833 bus_space_read_4(sc->ciss_regs_btag, sc->ciss_regs_bhandle, ofs) 834 #define CISS_TL_SIMPLE_WRITE(sc, ofs, val) \ 835 bus_space_write_4(sc->ciss_regs_btag, sc->ciss_regs_bhandle, ofs, val) 836 837 #define CISS_TL_SIMPLE_POST_CMD(sc, phys) CISS_TL_SIMPLE_WRITE(sc, CISS_TL_SIMPLE_IPQ, phys) 838 #define CISS_TL_SIMPLE_FETCH_CMD(sc) CISS_TL_SIMPLE_READ(sc, CISS_TL_SIMPLE_OPQ) 839 840 #define CISS_TL_PERF_INTR_OPQ (CISS_TL_SIMPLE_INTR_OPQ_SA5 | CISS_TL_SIMPLE_INTR_OPQ_SA5B) 841 #define CISS_TL_PERF_INTR_MSI 0x01 842 843 #define CISS_TL_PERF_POST_CMD(sc, cr) CISS_TL_SIMPLE_WRITE(sc, CISS_TL_SIMPLE_IPQ, cr->cr_ccphys | (cr)->cr_sg_tag) 844 #define CISS_TL_PERF_FLUSH_INT(sc) CISS_TL_SIMPLE_READ(sc, CISS_TL_SIMPLE_OSR) 845 #define CISS_TL_PERF_CLEAR_INT(sc) CISS_TL_SIMPLE_WRITE(sc, CISS_TL_SIMPLE_ODC, CISS_TL_SIMPLE_ODC_CLEAR) 846 #define CISS_CYCLE_MASK 0x00000001 847 848 /* Only need one MSI/MSI-X vector */ 849 #define CISS_MSI_COUNT 1 850 851 #define CISS_TL_SIMPLE_DISABLE_INTERRUPTS(sc) \ 852 CISS_TL_SIMPLE_WRITE(sc, CISS_TL_SIMPLE_IMR, \ 853 CISS_TL_SIMPLE_READ(sc, CISS_TL_SIMPLE_IMR) | (sc)->ciss_interrupt_mask) 854 #define CISS_TL_SIMPLE_ENABLE_INTERRUPTS(sc) \ 855 CISS_TL_SIMPLE_WRITE(sc, CISS_TL_SIMPLE_IMR, \ 856 CISS_TL_SIMPLE_READ(sc, CISS_TL_SIMPLE_IMR) & ~(sc)->ciss_interrupt_mask) 857 858 #endif /* _KERNEL */ 859