1 /*- 2 * Copyright (c) 2007, Juniper Networks, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. Neither the name of the author nor the names of any co-contributors 14 * may be used to endorse or promote products derived from this software 15 * without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 22 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 23 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 24 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 25 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD$ 30 */ 31 32 #ifndef _DEV_CFI_REG_H_ 33 #define _DEV_CFI_REG_H_ 34 35 struct cfi_qry { 36 u_char reserved[16]; 37 u_char ident[3]; /* "QRY" */ 38 u_char pri_vend[2]; 39 u_char pri_vend_eqt[2]; 40 u_char alt_vend[2]; 41 u_char alt_vend_eqt[2]; 42 /* System Interface Information. */ 43 u_char min_vcc; 44 u_char max_vcc; 45 u_char min_vpp; 46 u_char max_vpp; 47 u_char tto_byte_write; /* 2**n milliseconds. */ 48 u_char tto_buf_write; /* 2**n milliseconds. */ 49 u_char tto_block_erase; /* 2**n milliseconds. */ 50 u_char tto_chip_erase; /* 2**n milliseconds. */ 51 u_char mto_byte_write; /* 2**n times typical t/o. */ 52 u_char mto_buf_write; /* 2**n times typical t/o. */ 53 u_char mto_block_erase; /* 2**n times typical t/o. */ 54 u_char mto_chip_erase; /* 2**n times typical t/o. */ 55 /* Device Geometry Definition. */ 56 u_char size; /* 2**n bytes. */ 57 u_char iface[2]; 58 u_char max_buf_write_size[2]; /* 2**n. */ 59 u_char nregions; /* Number of erase regions. */ 60 u_char region[4]; /* Single entry. */ 61 /* Additional entries follow. */ 62 /* Primary Vendor-specific Extended Query table follows. */ 63 /* Alternate Vendor-specific Extended Query table follows. */ 64 }; 65 66 #define CFI_QRY_CMD_ADDR 0x55 67 #define CFI_QRY_CMD_DATA 0x98 68 69 #define CFI_QRY_IDENT offsetof(struct cfi_qry, ident) 70 #define CFI_QRY_VEND offsetof(struct cfi_qry, pri_vend) 71 72 #define CFI_QRY_TTO_WRITE offsetof(struct cfi_qry, tto_byte_write) 73 #define CFI_QRY_TTO_ERASE offsetof(struct cfi_qry, tto_block_erase) 74 #define CFI_QRY_MTO_WRITE offsetof(struct cfi_qry, mto_byte_write) 75 #define CFI_QRY_MTO_ERASE offsetof(struct cfi_qry, mto_block_erase) 76 77 #define CFI_QRY_SIZE offsetof(struct cfi_qry, size) 78 #define CFI_QRY_IFACE offsetof(struct cfi_qry, iface) 79 #define CFI_QRY_NREGIONS offsetof(struct cfi_qry, nregions) 80 #define CFI_QRY_REGION0 offsetof(struct cfi_qry, region) 81 #define CFI_QRY_REGION(x) (CFI_QRY_REGION0 + (x) * 4) 82 83 #define CFI_VEND_NONE 0x0000 84 #define CFI_VEND_INTEL_ECS 0x0001 85 #define CFI_VEND_AMD_SCS 0x0002 86 #define CFI_VEND_INTEL_SCS 0x0003 87 #define CFI_VEND_AMD_ECS 0x0004 88 #define CFI_VEND_MITSUBISHI_SCS 0x0100 89 #define CFI_VEND_MITSUBISHI_ECS 0x0101 90 91 #define CFI_IFACE_X8 0x0000 92 #define CFI_IFACE_X16 0x0001 93 #define CFI_IFACE_X8X16 0x0002 94 #define CFI_IFACE_X32 0x0003 95 #define CFI_IFACE_X16X32 0x0005 96 97 /* Standard Command Set (aka Basic Command Set) */ 98 #define CFI_BCS_BLOCK_ERASE 0x20 99 #define CFI_BCS_PROGRAM 0x40 100 #define CFI_BCS_CLEAR_STATUS 0x50 101 #define CFI_BCS_READ_STATUS 0x70 102 #define CFI_BCS_ERASE_SUSPEND 0xb0 103 #define CFI_BCS_ERASE_RESUME 0xd0 /* Equals CONFIRM */ 104 #define CFI_BCS_CONFIRM 0xd0 105 #define CFI_BCS_READ_ARRAY 0xff 106 107 /* Intel commands. */ 108 #define CFI_INTEL_READ_ID 0x90 /* Read Identifier */ 109 #define CFI_INTEL_PP_SETUP 0xc0 /* Protection Program Setup */ 110 111 /* NB: these are addresses for 16-bit accesses */ 112 #define CFI_INTEL_PLR 0x80 /* Protection Lock Register */ 113 #define CFI_INTEL_PR(n) (0x81+(n)) /* Protection Register */ 114 115 /* Status register definitions */ 116 #define CFI_INTEL_STATUS_WSMS 0x0080 /* Write Machine Status */ 117 #define CFI_INTEL_STATUS_ESS 0x0040 /* Erase Suspend Status */ 118 #define CFI_INTEL_STATUS_ECLBS 0x0020 /* Erase and Clear Lock-Bit Status */ 119 #define CFI_INTEL_STATUS_PSLBS 0x0010 /* Program and Set Lock-Bit Status */ 120 #define CFI_INTEL_STATUS_VPENS 0x0008 /* Programming Voltage Status */ 121 #define CFI_INTEL_STATUS_PSS 0x0004 /* Program Suspend Status */ 122 #define CFI_INTEL_STATUS_DPS 0x0002 /* Device Protect Status */ 123 #define CFI_INTEL_STATUS_RSVD 0x0001 /* reserved */ 124 125 /* eXtended Status register definitions */ 126 #define CFI_INTEL_XSTATUS_WBS 0x8000 /* Write Buffer Status */ 127 #define CFI_INTEL_XSTATUS_RSVD 0x7f00 /* reserved */ 128 129 /* AMD commands. */ 130 #define CFI_AMD_BLOCK_ERASE 0x30 131 #define CFI_AMD_UNLOCK_ACK 0x55 132 #define CFI_AMD_ERASE_SECTOR 0x80 133 #define CFI_AMD_PROGRAM 0xa0 134 #define CFI_AMD_UNLOCK 0xaa 135 136 #define AMD_ADDR_START 0xaaa 137 #define AMD_ADDR_ACK 0x555 138 139 #endif /* _DEV_CFI_REG_H_ */ 140