xref: /freebsd/sys/dev/cas/if_casvar.h (revision fcb560670601b2a4d87bb31d7531c8dcc37ee71b)
1 /*-
2  * Copyright (C) 2001 Eduardo Horvath.
3  * Copyright (c) 2008 Marius Strobl <marius@FreeBSD.org>
4  * All rights reserved.
5  *
6  * Redistribution and use in source and binary forms, with or without
7  * modification, are permitted provided that the following conditions
8  * are met:
9  * 1. Redistributions of source code must retain the above copyright
10  *    notice, this list of conditions and the following disclaimer.
11  * 2. Redistributions in binary form must reproduce the above copyright
12  *    notice, this list of conditions and the following disclaimer in the
13  *    documentation and/or other materials provided with the distribution.
14  *
15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR  ``AS IS'' AND
16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR  BE LIABLE
19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25  * SUCH DAMAGE.
26  *
27  *	from: NetBSD: gemvar.h,v 1.8 2002/05/15 02:36:12 matt Exp
28  *	from: FreeBSD: if_gemvar.h 177560 2008-03-24 17:23:53Z marius
29  *
30  * $FreeBSD$
31  */
32 
33 #ifndef	_IF_CASVAR_H
34 #define	_IF_CASVAR_H
35 
36 /*
37  * The page size is configurable, but needs to be at least 8k (the
38  * default) in order to also support jumbo buffers.
39  */
40 #define	CAS_PAGE_SIZE		8192
41 
42 /*
43  * Transmit descriptor ring size - this is arbitrary, but allocate
44  * enough descriptors for 64 pending transmissions and 16 segments
45  * per packet.  This limit is not actually enforced (packets with
46  * more segments can be sent, depending on the busdma backend); it
47  * is however used as an estimate for the TX window size.
48  */
49 #define	CAS_NTXSEGS		16
50 
51 #define	CAS_TXQUEUELEN		64
52 #define	CAS_NTXDESC		(CAS_TXQUEUELEN * CAS_NTXSEGS)
53 #define	CAS_MAXTXFREE		(CAS_NTXDESC - 1)
54 #define	CAS_NTXDESC_MASK	(CAS_NTXDESC - 1)
55 #define	CAS_NEXTTX(x)		((x + 1) & CAS_NTXDESC_MASK)
56 
57 /*
58  * Receive completion ring size - we have one completion per
59  * incoming packet (though the opposite isn't necessarily true),
60  * so this logic is a little simpler.
61  */
62 #define	CAS_NRXCOMP		4096
63 #define	CAS_NRXCOMP_MASK	(CAS_NRXCOMP - 1)
64 #define	CAS_NEXTRXCOMP(x)	((x + 1) & CAS_NRXCOMP_MASK)
65 
66 /*
67  * Receive descriptor ring sizes - for Cassini+ and Saturn both
68  * rings must be at least initialized.
69  */
70 #define	CAS_NRXDESC		1024
71 #define	CAS_NRXDESC_MASK	(CAS_NRXDESC - 1)
72 #define	CAS_NEXTRXDESC(x)	((x + 1) & CAS_NRXDESC_MASK)
73 #define	CAS_NRXDESC2		32
74 #define	CAS_NRXDESC2_MASK	(CAS_NRXDESC2 - 1)
75 #define	CAS_NEXTRXDESC2(x)	((x + 1) & CAS_NRXDESC2_MASK)
76 
77 /*
78  * How many ticks to wait until to retry on a RX descriptor that is
79  * still owned by the hardware.
80  */
81 #define	CAS_RXOWN_TICKS		(hz / 50)
82 
83 /*
84  * Control structures are DMA'd to the chip.  We allocate them
85  * in a single clump that maps to a single DMA segment to make
86  * several things easier.
87  */
88 struct cas_control_data {
89 	struct cas_desc ccd_txdescs[CAS_NTXDESC];	/* TX descriptors */
90 	struct cas_rx_comp ccd_rxcomps[CAS_NRXCOMP];	/* RX completions */
91 	struct cas_desc ccd_rxdescs[CAS_NRXDESC];	/* RX descriptors */
92 	struct cas_desc ccd_rxdescs2[CAS_NRXDESC2];	/* RX descriptors 2 */
93 };
94 
95 #define	CAS_CDOFF(x)		offsetof(struct cas_control_data, x)
96 #define	CAS_CDTXDOFF(x)		CAS_CDOFF(ccd_txdescs[(x)])
97 #define	CAS_CDRXCOFF(x)		CAS_CDOFF(ccd_rxcomps[(x)])
98 #define	CAS_CDRXDOFF(x)		CAS_CDOFF(ccd_rxdescs[(x)])
99 #define	CAS_CDRXD2OFF(x)	CAS_CDOFF(ccd_rxdescs2[(x)])
100 
101 /*
102  * software state for transmit job mbufs (may be elements of mbuf chains)
103  */
104 struct cas_txsoft {
105 	struct mbuf *txs_mbuf;		/* head of our mbuf chain */
106 	bus_dmamap_t txs_dmamap;	/* our DMA map */
107 	u_int txs_firstdesc;		/* first descriptor in packet */
108 	u_int txs_lastdesc;		/* last descriptor in packet */
109 	u_int txs_ndescs;		/* number of descriptors */
110 	STAILQ_ENTRY(cas_txsoft) txs_q;
111 };
112 
113 STAILQ_HEAD(cas_txsq, cas_txsoft);
114 
115 /*
116  * software state for receive descriptors
117  */
118 struct cas_rxdsoft {
119 	void *rxds_buf;			/* receive buffer */
120 	bus_dmamap_t rxds_dmamap;	/* our DMA map */
121 	bus_addr_t rxds_paddr;		/* physical address of the segment */
122 #if __FreeBSD_version < 800016
123 	struct cas_softc *rxds_sc;	/* softc pointer */
124 	u_int rxds_idx;			/* our index */
125 #endif
126 	u_int rxds_refcount;		/* hardware + mbuf references */
127 };
128 
129 /*
130  * software state per device
131  */
132 struct cas_softc {
133 	struct ifnet	*sc_ifp;
134 	struct mtx	sc_mtx;
135 	device_t	sc_miibus;
136 	struct mii_data	*sc_mii;	/* MII media control */
137 	device_t	sc_dev;		/* generic device information */
138 	u_char		sc_enaddr[ETHER_ADDR_LEN];
139 	struct callout	sc_tick_ch;	/* tick callout */
140 	struct callout	sc_rx_ch;	/* delayed RX callout */
141 	struct task	sc_intr_task;
142 	struct task	sc_tx_task;
143 	struct taskqueue	*sc_tq;
144 	u_int		sc_wdog_timer;	/* watchdog timer */
145 
146 	void		*sc_ih;
147 	struct resource *sc_res[2];
148 #define	CAS_RES_INTR	0
149 #define	CAS_RES_MEM	1
150 
151 	bus_dma_tag_t	sc_pdmatag;	/* parent bus DMA tag */
152 	bus_dma_tag_t	sc_rdmatag;	/* RX bus DMA tag */
153 	bus_dma_tag_t	sc_tdmatag;	/* TX bus DMA tag */
154 	bus_dma_tag_t	sc_cdmatag;	/* control data bus DMA tag */
155 	bus_dmamap_t	sc_dmamap;	/* bus DMA handle */
156 
157 	u_int		sc_variant;
158 #define	CAS_UNKNOWN	0		/* don't know */
159 #define	CAS_CAS		1		/* Sun Cassini */
160 #define	CAS_CASPLUS	2		/* Sun Cassini+ */
161 #define	CAS_SATURN	3		/* National Semiconductor Saturn */
162 
163 	u_int		sc_flags;
164 #define	CAS_INITED	(1 << 0)	/* reset persistent regs init'ed */
165 #define	CAS_NO_CSUM	(1 << 1)	/* don't use hardware checksumming */
166 #define	CAS_LINK	(1 << 2)	/* link is up */
167 #define	CAS_REG_PLUS	(1 << 3)	/* has Cassini+ registers */
168 #define	CAS_SERDES	(1 << 4)	/* use the SERDES */
169 #define	CAS_TABORT	(1 << 5)	/* has target abort issues */
170 
171 	bus_dmamap_t	sc_cddmamap;	/* control data DMA map */
172 	bus_addr_t	sc_cddma;
173 
174 	/*
175 	 * software state for transmit and receive descriptors
176 	 */
177 	struct cas_txsoft sc_txsoft[CAS_TXQUEUELEN];
178 	struct cas_rxdsoft sc_rxdsoft[CAS_NRXDESC];
179 
180 	/*
181 	 * control data structures
182 	 */
183 	struct cas_control_data *sc_control_data;
184 #define	sc_txdescs	sc_control_data->ccd_txdescs
185 #define	sc_rxcomps	sc_control_data->ccd_rxcomps
186 #define	sc_rxdescs	sc_control_data->ccd_rxdescs
187 #define	sc_rxdescs2	sc_control_data->ccd_rxdescs2
188 
189 	u_int		sc_txfree;	/* number of free TX descriptors */
190 	u_int		sc_txnext;	/* next ready TX descriptor */
191 	u_int		sc_txwin;	/* TX desc. since last TX intr. */
192 
193 	struct cas_txsq	sc_txfreeq;	/* free software TX descriptors */
194 	struct cas_txsq	sc_txdirtyq;	/* dirty software TX descriptors */
195 
196 	u_int		sc_rxcptr;	/* next ready RX completion */
197 	u_int		sc_rxdptr;	/* next ready RX descriptor */
198 
199 	uint32_t	sc_mac_rxcfg;	/* RX MAC conf. % CAS_MAC_RX_CONF_EN */
200 
201 	int		sc_ifflags;
202 };
203 
204 #define	CAS_BARRIER(sc, offs, len, flags)				\
205 	bus_barrier((sc)->sc_res[CAS_RES_MEM], (offs), (len), (flags))
206 
207 #define	CAS_READ_N(n, sc, offs)						\
208 	bus_read_ ## n((sc)->sc_res[CAS_RES_MEM], (offs))
209 #define	CAS_READ_1(sc, offs)		CAS_READ_N(1, (sc), (offs))
210 #define	CAS_READ_2(sc, offs)		CAS_READ_N(2, (sc), (offs))
211 #define	CAS_READ_4(sc, offs)		CAS_READ_N(4, (sc), (offs))
212 
213 #define	CAS_WRITE_N(n, sc, offs, v)					\
214 	bus_write_ ## n((sc)->sc_res[CAS_RES_MEM], (offs), (v))
215 #define	CAS_WRITE_1(sc, offs, v)	CAS_WRITE_N(1, (sc), (offs), (v))
216 #define	CAS_WRITE_2(sc, offs, v)	CAS_WRITE_N(2, (sc), (offs), (v))
217 #define	CAS_WRITE_4(sc, offs, v)	CAS_WRITE_N(4, (sc), (offs), (v))
218 
219 #define	CAS_CDTXDADDR(sc, x)	((sc)->sc_cddma + CAS_CDTXDOFF((x)))
220 #define	CAS_CDRXCADDR(sc, x)	((sc)->sc_cddma + CAS_CDRXCOFF((x)))
221 #define	CAS_CDRXDADDR(sc, x)	((sc)->sc_cddma + CAS_CDRXDOFF((x)))
222 #define	CAS_CDRXD2ADDR(sc, x)	((sc)->sc_cddma + CAS_CDRXD2OFF((x)))
223 
224 #define	CAS_CDSYNC(sc, ops)						\
225 	bus_dmamap_sync((sc)->sc_cdmatag, (sc)->sc_cddmamap, (ops));
226 
227 #define	__CAS_UPDATE_RXDESC(rxd, rxds, s)				\
228 do {									\
229 									\
230 	refcount_init(&(rxds)->rxds_refcount, 1);			\
231 	(rxd)->cd_buf_ptr = htole64((rxds)->rxds_paddr);		\
232 	KASSERT((s) < CAS_RD_BUF_INDEX_MASK >> CAS_RD_BUF_INDEX_SHFT,	\
233 	    ("%s: RX buffer index too large!", __func__));		\
234 	(rxd)->cd_flags =						\
235 	    htole64((uint64_t)((s) << CAS_RD_BUF_INDEX_SHFT));		\
236 } while (0)
237 
238 #define	CAS_UPDATE_RXDESC(sc, d, s)					\
239 	__CAS_UPDATE_RXDESC(&(sc)->sc_rxdescs[(d)],			\
240 	    &(sc)->sc_rxdsoft[(s)], (s))
241 
242 #if __FreeBSD_version < 800016
243 #define	CAS_INIT_RXDESC(sc, d, s)					\
244 do {									\
245 	struct cas_rxdsoft *__rxds = &(sc)->sc_rxdsoft[(s)];		\
246 									\
247 	__rxds->rxds_sc = (sc);						\
248 	__rxds->rxds_idx = (s);						\
249 	__CAS_UPDATE_RXDESC(&(sc)->sc_rxdescs[(d)], __rxds, (s));	\
250 } while (0)
251 #else
252 #define	CAS_INIT_RXDESC(sc, d, s)	CAS_UPDATE_RXDESC(sc, d, s)
253 #endif
254 
255 #define	CAS_LOCK_INIT(_sc, _name)					\
256 	mtx_init(&(_sc)->sc_mtx, _name, MTX_NETWORK_LOCK, MTX_DEF)
257 #define	CAS_LOCK(_sc)			mtx_lock(&(_sc)->sc_mtx)
258 #define	CAS_UNLOCK(_sc)			mtx_unlock(&(_sc)->sc_mtx)
259 #define	CAS_LOCK_ASSERT(_sc, _what)	mtx_assert(&(_sc)->sc_mtx, (_what))
260 #define	CAS_LOCK_DESTROY(_sc)		mtx_destroy(&(_sc)->sc_mtx)
261 #define	CAS_LOCK_OWNED(_sc)		mtx_owned(&(_sc)->sc_mtx)
262 
263 #endif
264