1 /*- 2 * Copyright (C) 2001 Eduardo Horvath. 3 * Copyright (c) 2001-2003 Thomas Moestl 4 * Copyright (c) 2007-2009 Marius Strobl <marius@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * from: NetBSD: gem.c,v 1.21 2002/06/01 23:50:58 lukem Exp 29 * from: FreeBSD: if_gem.c 182060 2008-08-23 15:03:26Z marius 30 */ 31 32 #include <sys/cdefs.h> 33 __FBSDID("$FreeBSD$"); 34 35 /* 36 * driver for Sun Cassini/Cassini+ and National Semiconductor DP83065 37 * Saturn Gigabit Ethernet controllers 38 */ 39 40 #if 0 41 #define CAS_DEBUG 42 #endif 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/bus.h> 47 #include <sys/callout.h> 48 #include <sys/endian.h> 49 #include <sys/mbuf.h> 50 #include <sys/malloc.h> 51 #include <sys/kernel.h> 52 #include <sys/lock.h> 53 #include <sys/module.h> 54 #include <sys/mutex.h> 55 #include <sys/refcount.h> 56 #include <sys/resource.h> 57 #include <sys/rman.h> 58 #include <sys/socket.h> 59 #include <sys/sockio.h> 60 #include <sys/taskqueue.h> 61 62 #include <net/bpf.h> 63 #include <net/ethernet.h> 64 #include <net/if.h> 65 #include <net/if_arp.h> 66 #include <net/if_dl.h> 67 #include <net/if_media.h> 68 #include <net/if_types.h> 69 #include <net/if_vlan_var.h> 70 71 #include <netinet/in.h> 72 #include <netinet/in_systm.h> 73 #include <netinet/ip.h> 74 #include <netinet/tcp.h> 75 #include <netinet/udp.h> 76 77 #include <machine/bus.h> 78 #if defined(__powerpc__) || defined(__sparc64__) 79 #include <dev/ofw/ofw_bus.h> 80 #include <dev/ofw/openfirm.h> 81 #include <machine/ofw_machdep.h> 82 #endif 83 #include <machine/resource.h> 84 85 #include <dev/mii/mii.h> 86 #include <dev/mii/miivar.h> 87 88 #include <dev/cas/if_casreg.h> 89 #include <dev/cas/if_casvar.h> 90 91 #include <dev/pci/pcireg.h> 92 #include <dev/pci/pcivar.h> 93 94 #include "miibus_if.h" 95 96 #define RINGASSERT(n , min, max) \ 97 CTASSERT(powerof2(n) && (n) >= (min) && (n) <= (max)) 98 99 RINGASSERT(CAS_NRXCOMP, 128, 32768); 100 RINGASSERT(CAS_NRXDESC, 32, 8192); 101 RINGASSERT(CAS_NRXDESC2, 32, 8192); 102 RINGASSERT(CAS_NTXDESC, 32, 8192); 103 104 #undef RINGASSERT 105 106 #define CCDASSERT(m, a) \ 107 CTASSERT((offsetof(struct cas_control_data, m) & ((a) - 1)) == 0) 108 109 CCDASSERT(ccd_rxcomps, CAS_RX_COMP_ALIGN); 110 CCDASSERT(ccd_rxdescs, CAS_RX_DESC_ALIGN); 111 CCDASSERT(ccd_rxdescs2, CAS_RX_DESC_ALIGN); 112 113 #undef CCDASSERT 114 115 #define CAS_TRIES 10000 116 117 /* 118 * According to documentation, the hardware has support for basic TCP 119 * checksum offloading only, in practice this can be also used for UDP 120 * however (i.e. the problem of previous Sun NICs that a checksum of 0x0 121 * is not converted to 0xffff no longer exists). 122 */ 123 #define CAS_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 124 125 static inline void cas_add_rxdesc(struct cas_softc *sc, u_int idx); 126 static int cas_attach(struct cas_softc *sc); 127 static int cas_bitwait(struct cas_softc *sc, bus_addr_t r, uint32_t clr, 128 uint32_t set); 129 static void cas_cddma_callback(void *xsc, bus_dma_segment_t *segs, 130 int nsegs, int error); 131 static void cas_detach(struct cas_softc *sc); 132 static int cas_disable_rx(struct cas_softc *sc); 133 static int cas_disable_tx(struct cas_softc *sc); 134 static void cas_eint(struct cas_softc *sc, u_int status); 135 static void cas_free(void *arg1, void* arg2); 136 static void cas_init(void *xsc); 137 static void cas_init_locked(struct cas_softc *sc); 138 static void cas_init_regs(struct cas_softc *sc); 139 static int cas_intr(void *v); 140 static void cas_intr_task(void *arg, int pending __unused); 141 static int cas_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data); 142 static int cas_load_txmbuf(struct cas_softc *sc, struct mbuf **m_head); 143 static int cas_mediachange(struct ifnet *ifp); 144 static void cas_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr); 145 static void cas_meminit(struct cas_softc *sc); 146 static void cas_mifinit(struct cas_softc *sc); 147 static int cas_mii_readreg(device_t dev, int phy, int reg); 148 static void cas_mii_statchg(device_t dev); 149 static int cas_mii_writereg(device_t dev, int phy, int reg, int val); 150 static void cas_reset(struct cas_softc *sc); 151 static int cas_reset_rx(struct cas_softc *sc); 152 static int cas_reset_tx(struct cas_softc *sc); 153 static void cas_resume(struct cas_softc *sc); 154 static u_int cas_descsize(u_int sz); 155 static void cas_rint(struct cas_softc *sc); 156 static void cas_rint_timeout(void *arg); 157 static inline void cas_rxcksum(struct mbuf *m, uint16_t cksum); 158 static inline void cas_rxcompinit(struct cas_rx_comp *rxcomp); 159 static u_int cas_rxcompsize(u_int sz); 160 static void cas_rxdma_callback(void *xsc, bus_dma_segment_t *segs, 161 int nsegs, int error); 162 static void cas_setladrf(struct cas_softc *sc); 163 static void cas_start(struct ifnet *ifp); 164 static void cas_stop(struct ifnet *ifp); 165 static void cas_suspend(struct cas_softc *sc); 166 static void cas_tick(void *arg); 167 static void cas_tint(struct cas_softc *sc); 168 static void cas_tx_task(void *arg, int pending __unused); 169 static inline void cas_txkick(struct cas_softc *sc); 170 static void cas_watchdog(struct cas_softc *sc); 171 172 static devclass_t cas_devclass; 173 174 MODULE_DEPEND(cas, ether, 1, 1, 1); 175 MODULE_DEPEND(cas, miibus, 1, 1, 1); 176 177 #ifdef CAS_DEBUG 178 #include <sys/ktr.h> 179 #define KTR_CAS KTR_SPARE2 180 #endif 181 182 static int 183 cas_attach(struct cas_softc *sc) 184 { 185 struct cas_txsoft *txs; 186 struct ifnet *ifp; 187 int error, i; 188 uint32_t v; 189 190 /* Set up ifnet structure. */ 191 ifp = sc->sc_ifp = if_alloc(IFT_ETHER); 192 if (ifp == NULL) 193 return (ENOSPC); 194 ifp->if_softc = sc; 195 if_initname(ifp, device_get_name(sc->sc_dev), 196 device_get_unit(sc->sc_dev)); 197 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 198 ifp->if_start = cas_start; 199 ifp->if_ioctl = cas_ioctl; 200 ifp->if_init = cas_init; 201 IFQ_SET_MAXLEN(&ifp->if_snd, CAS_TXQUEUELEN); 202 ifp->if_snd.ifq_drv_maxlen = CAS_TXQUEUELEN; 203 IFQ_SET_READY(&ifp->if_snd); 204 205 callout_init_mtx(&sc->sc_tick_ch, &sc->sc_mtx, 0); 206 callout_init_mtx(&sc->sc_rx_ch, &sc->sc_mtx, 0); 207 /* Create local taskq. */ 208 TASK_INIT(&sc->sc_intr_task, 0, cas_intr_task, sc); 209 TASK_INIT(&sc->sc_tx_task, 1, cas_tx_task, ifp); 210 sc->sc_tq = taskqueue_create_fast("cas_taskq", M_WAITOK, 211 taskqueue_thread_enqueue, &sc->sc_tq); 212 if (sc->sc_tq == NULL) { 213 device_printf(sc->sc_dev, "could not create taskqueue\n"); 214 error = ENXIO; 215 goto fail_ifnet; 216 } 217 error = taskqueue_start_threads(&sc->sc_tq, 1, PI_NET, "%s taskq", 218 device_get_nameunit(sc->sc_dev)); 219 if (error != 0) { 220 device_printf(sc->sc_dev, "could not start threads\n"); 221 goto fail_taskq; 222 } 223 224 /* Make sure the chip is stopped. */ 225 cas_reset(sc); 226 227 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 228 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 229 BUS_SPACE_MAXSIZE, 0, BUS_SPACE_MAXSIZE, 0, NULL, NULL, 230 &sc->sc_pdmatag); 231 if (error != 0) 232 goto fail_taskq; 233 234 error = bus_dma_tag_create(sc->sc_pdmatag, 1, 0, 235 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 236 CAS_PAGE_SIZE, 1, CAS_PAGE_SIZE, 0, NULL, NULL, &sc->sc_rdmatag); 237 if (error != 0) 238 goto fail_ptag; 239 240 error = bus_dma_tag_create(sc->sc_pdmatag, 1, 0, 241 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 242 MCLBYTES * CAS_NTXSEGS, CAS_NTXSEGS, MCLBYTES, 243 BUS_DMA_ALLOCNOW, NULL, NULL, &sc->sc_tdmatag); 244 if (error != 0) 245 goto fail_rtag; 246 247 error = bus_dma_tag_create(sc->sc_pdmatag, CAS_TX_DESC_ALIGN, 0, 248 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 249 sizeof(struct cas_control_data), 1, 250 sizeof(struct cas_control_data), 0, 251 NULL, NULL, &sc->sc_cdmatag); 252 if (error != 0) 253 goto fail_ttag; 254 255 /* 256 * Allocate the control data structures, create and load the 257 * DMA map for it. 258 */ 259 if ((error = bus_dmamem_alloc(sc->sc_cdmatag, 260 (void **)&sc->sc_control_data, 261 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 262 &sc->sc_cddmamap)) != 0) { 263 device_printf(sc->sc_dev, 264 "unable to allocate control data, error = %d\n", error); 265 goto fail_ctag; 266 } 267 268 sc->sc_cddma = 0; 269 if ((error = bus_dmamap_load(sc->sc_cdmatag, sc->sc_cddmamap, 270 sc->sc_control_data, sizeof(struct cas_control_data), 271 cas_cddma_callback, sc, 0)) != 0 || sc->sc_cddma == 0) { 272 device_printf(sc->sc_dev, 273 "unable to load control data DMA map, error = %d\n", 274 error); 275 goto fail_cmem; 276 } 277 278 /* 279 * Initialize the transmit job descriptors. 280 */ 281 STAILQ_INIT(&sc->sc_txfreeq); 282 STAILQ_INIT(&sc->sc_txdirtyq); 283 284 /* 285 * Create the transmit buffer DMA maps. 286 */ 287 error = ENOMEM; 288 for (i = 0; i < CAS_TXQUEUELEN; i++) { 289 txs = &sc->sc_txsoft[i]; 290 txs->txs_mbuf = NULL; 291 txs->txs_ndescs = 0; 292 if ((error = bus_dmamap_create(sc->sc_tdmatag, 0, 293 &txs->txs_dmamap)) != 0) { 294 device_printf(sc->sc_dev, 295 "unable to create TX DMA map %d, error = %d\n", 296 i, error); 297 goto fail_txd; 298 } 299 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 300 } 301 302 /* 303 * Allocate the receive buffers, create and load the DMA maps 304 * for them. 305 */ 306 for (i = 0; i < CAS_NRXDESC; i++) { 307 if ((error = bus_dmamem_alloc(sc->sc_rdmatag, 308 &sc->sc_rxdsoft[i].rxds_buf, BUS_DMA_WAITOK, 309 &sc->sc_rxdsoft[i].rxds_dmamap)) != 0) { 310 device_printf(sc->sc_dev, 311 "unable to allocate RX buffer %d, error = %d\n", 312 i, error); 313 goto fail_rxmem; 314 } 315 316 sc->sc_rxdptr = i; 317 sc->sc_rxdsoft[i].rxds_paddr = 0; 318 if ((error = bus_dmamap_load(sc->sc_rdmatag, 319 sc->sc_rxdsoft[i].rxds_dmamap, sc->sc_rxdsoft[i].rxds_buf, 320 CAS_PAGE_SIZE, cas_rxdma_callback, sc, 0)) != 0 || 321 sc->sc_rxdsoft[i].rxds_paddr == 0) { 322 device_printf(sc->sc_dev, 323 "unable to load RX DMA map %d, error = %d\n", 324 i, error); 325 goto fail_rxmap; 326 } 327 } 328 329 if ((sc->sc_flags & CAS_SERDES) == 0) { 330 CAS_WRITE_4(sc, CAS_PCS_DATAPATH, CAS_PCS_DATAPATH_MII); 331 CAS_BARRIER(sc, CAS_PCS_DATAPATH, 4, 332 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 333 cas_mifinit(sc); 334 /* 335 * Look for an external PHY. 336 */ 337 error = ENXIO; 338 v = CAS_READ_4(sc, CAS_MIF_CONF); 339 if ((v & CAS_MIF_CONF_MDI1) != 0) { 340 v |= CAS_MIF_CONF_PHY_SELECT; 341 CAS_WRITE_4(sc, CAS_MIF_CONF, v); 342 CAS_BARRIER(sc, CAS_MIF_CONF, 4, 343 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 344 /* Enable/unfreeze the GMII pins of Saturn. */ 345 if (sc->sc_variant == CAS_SATURN) { 346 CAS_WRITE_4(sc, CAS_SATURN_PCFG, 347 CAS_READ_4(sc, CAS_SATURN_PCFG) & 348 ~CAS_SATURN_PCFG_FSI); 349 CAS_BARRIER(sc, CAS_SATURN_PCFG, 4, 350 BUS_SPACE_BARRIER_READ | 351 BUS_SPACE_BARRIER_WRITE); 352 DELAY(10000); 353 } 354 error = mii_attach(sc->sc_dev, &sc->sc_miibus, ifp, 355 cas_mediachange, cas_mediastatus, BMSR_DEFCAPMASK, 356 MII_PHY_ANY, MII_OFFSET_ANY, MIIF_DOPAUSE); 357 } 358 /* 359 * Fall back on an internal PHY if no external PHY was found. 360 */ 361 if (error != 0 && (v & CAS_MIF_CONF_MDI0) != 0) { 362 v &= ~CAS_MIF_CONF_PHY_SELECT; 363 CAS_WRITE_4(sc, CAS_MIF_CONF, v); 364 CAS_BARRIER(sc, CAS_MIF_CONF, 4, 365 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 366 /* Freeze the GMII pins of Saturn for saving power. */ 367 if (sc->sc_variant == CAS_SATURN) { 368 CAS_WRITE_4(sc, CAS_SATURN_PCFG, 369 CAS_READ_4(sc, CAS_SATURN_PCFG) | 370 CAS_SATURN_PCFG_FSI); 371 CAS_BARRIER(sc, CAS_SATURN_PCFG, 4, 372 BUS_SPACE_BARRIER_READ | 373 BUS_SPACE_BARRIER_WRITE); 374 DELAY(10000); 375 } 376 error = mii_attach(sc->sc_dev, &sc->sc_miibus, ifp, 377 cas_mediachange, cas_mediastatus, BMSR_DEFCAPMASK, 378 MII_PHY_ANY, MII_OFFSET_ANY, MIIF_DOPAUSE); 379 } 380 } else { 381 /* 382 * Use the external PCS SERDES. 383 */ 384 CAS_WRITE_4(sc, CAS_PCS_DATAPATH, CAS_PCS_DATAPATH_SERDES); 385 CAS_BARRIER(sc, CAS_PCS_DATAPATH, 4, BUS_SPACE_BARRIER_WRITE); 386 /* Enable/unfreeze the SERDES pins of Saturn. */ 387 if (sc->sc_variant == CAS_SATURN) { 388 CAS_WRITE_4(sc, CAS_SATURN_PCFG, 0); 389 CAS_BARRIER(sc, CAS_SATURN_PCFG, 4, 390 BUS_SPACE_BARRIER_WRITE); 391 } 392 CAS_WRITE_4(sc, CAS_PCS_SERDES_CTRL, CAS_PCS_SERDES_CTRL_ESD); 393 CAS_BARRIER(sc, CAS_PCS_SERDES_CTRL, 4, 394 BUS_SPACE_BARRIER_WRITE); 395 CAS_WRITE_4(sc, CAS_PCS_CONF, CAS_PCS_CONF_EN); 396 CAS_BARRIER(sc, CAS_PCS_CONF, 4, 397 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 398 error = mii_attach(sc->sc_dev, &sc->sc_miibus, ifp, 399 cas_mediachange, cas_mediastatus, BMSR_DEFCAPMASK, 400 CAS_PHYAD_EXTERNAL, MII_OFFSET_ANY, MIIF_DOPAUSE); 401 } 402 if (error != 0) { 403 device_printf(sc->sc_dev, "attaching PHYs failed\n"); 404 goto fail_rxmap; 405 } 406 sc->sc_mii = device_get_softc(sc->sc_miibus); 407 408 /* 409 * From this point forward, the attachment cannot fail. A failure 410 * before this point releases all resources that may have been 411 * allocated. 412 */ 413 414 /* Announce FIFO sizes. */ 415 v = CAS_READ_4(sc, CAS_TX_FIFO_SIZE); 416 device_printf(sc->sc_dev, "%ukB RX FIFO, %ukB TX FIFO\n", 417 CAS_RX_FIFO_SIZE / 1024, v / 16); 418 419 /* Attach the interface. */ 420 ether_ifattach(ifp, sc->sc_enaddr); 421 422 /* 423 * Tell the upper layer(s) we support long frames/checksum offloads. 424 */ 425 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 426 ifp->if_capabilities = IFCAP_VLAN_MTU; 427 if ((sc->sc_flags & CAS_NO_CSUM) == 0) { 428 ifp->if_capabilities |= IFCAP_HWCSUM; 429 ifp->if_hwassist = CAS_CSUM_FEATURES; 430 } 431 ifp->if_capenable = ifp->if_capabilities; 432 433 return (0); 434 435 /* 436 * Free any resources we've allocated during the failed attach 437 * attempt. Do this in reverse order and fall through. 438 */ 439 fail_rxmap: 440 for (i = 0; i < CAS_NRXDESC; i++) 441 if (sc->sc_rxdsoft[i].rxds_paddr != 0) 442 bus_dmamap_unload(sc->sc_rdmatag, 443 sc->sc_rxdsoft[i].rxds_dmamap); 444 fail_rxmem: 445 for (i = 0; i < CAS_NRXDESC; i++) 446 if (sc->sc_rxdsoft[i].rxds_buf != NULL) 447 bus_dmamem_free(sc->sc_rdmatag, 448 sc->sc_rxdsoft[i].rxds_buf, 449 sc->sc_rxdsoft[i].rxds_dmamap); 450 fail_txd: 451 for (i = 0; i < CAS_TXQUEUELEN; i++) 452 if (sc->sc_txsoft[i].txs_dmamap != NULL) 453 bus_dmamap_destroy(sc->sc_tdmatag, 454 sc->sc_txsoft[i].txs_dmamap); 455 bus_dmamap_unload(sc->sc_cdmatag, sc->sc_cddmamap); 456 fail_cmem: 457 bus_dmamem_free(sc->sc_cdmatag, sc->sc_control_data, 458 sc->sc_cddmamap); 459 fail_ctag: 460 bus_dma_tag_destroy(sc->sc_cdmatag); 461 fail_ttag: 462 bus_dma_tag_destroy(sc->sc_tdmatag); 463 fail_rtag: 464 bus_dma_tag_destroy(sc->sc_rdmatag); 465 fail_ptag: 466 bus_dma_tag_destroy(sc->sc_pdmatag); 467 fail_taskq: 468 taskqueue_free(sc->sc_tq); 469 fail_ifnet: 470 if_free(ifp); 471 return (error); 472 } 473 474 static void 475 cas_detach(struct cas_softc *sc) 476 { 477 struct ifnet *ifp = sc->sc_ifp; 478 int i; 479 480 ether_ifdetach(ifp); 481 CAS_LOCK(sc); 482 cas_stop(ifp); 483 CAS_UNLOCK(sc); 484 callout_drain(&sc->sc_tick_ch); 485 callout_drain(&sc->sc_rx_ch); 486 taskqueue_drain(sc->sc_tq, &sc->sc_intr_task); 487 taskqueue_drain(sc->sc_tq, &sc->sc_tx_task); 488 if_free(ifp); 489 taskqueue_free(sc->sc_tq); 490 device_delete_child(sc->sc_dev, sc->sc_miibus); 491 492 for (i = 0; i < CAS_NRXDESC; i++) 493 if (sc->sc_rxdsoft[i].rxds_dmamap != NULL) 494 bus_dmamap_sync(sc->sc_rdmatag, 495 sc->sc_rxdsoft[i].rxds_dmamap, 496 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 497 for (i = 0; i < CAS_NRXDESC; i++) 498 if (sc->sc_rxdsoft[i].rxds_paddr != 0) 499 bus_dmamap_unload(sc->sc_rdmatag, 500 sc->sc_rxdsoft[i].rxds_dmamap); 501 for (i = 0; i < CAS_NRXDESC; i++) 502 if (sc->sc_rxdsoft[i].rxds_buf != NULL) 503 bus_dmamem_free(sc->sc_rdmatag, 504 sc->sc_rxdsoft[i].rxds_buf, 505 sc->sc_rxdsoft[i].rxds_dmamap); 506 for (i = 0; i < CAS_TXQUEUELEN; i++) 507 if (sc->sc_txsoft[i].txs_dmamap != NULL) 508 bus_dmamap_destroy(sc->sc_tdmatag, 509 sc->sc_txsoft[i].txs_dmamap); 510 CAS_CDSYNC(sc, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 511 bus_dmamap_unload(sc->sc_cdmatag, sc->sc_cddmamap); 512 bus_dmamem_free(sc->sc_cdmatag, sc->sc_control_data, 513 sc->sc_cddmamap); 514 bus_dma_tag_destroy(sc->sc_cdmatag); 515 bus_dma_tag_destroy(sc->sc_tdmatag); 516 bus_dma_tag_destroy(sc->sc_rdmatag); 517 bus_dma_tag_destroy(sc->sc_pdmatag); 518 } 519 520 static void 521 cas_suspend(struct cas_softc *sc) 522 { 523 struct ifnet *ifp = sc->sc_ifp; 524 525 CAS_LOCK(sc); 526 cas_stop(ifp); 527 CAS_UNLOCK(sc); 528 } 529 530 static void 531 cas_resume(struct cas_softc *sc) 532 { 533 struct ifnet *ifp = sc->sc_ifp; 534 535 CAS_LOCK(sc); 536 /* 537 * On resume all registers have to be initialized again like 538 * after power-on. 539 */ 540 sc->sc_flags &= ~CAS_INITED; 541 if (ifp->if_flags & IFF_UP) 542 cas_init_locked(sc); 543 CAS_UNLOCK(sc); 544 } 545 546 static inline void 547 cas_rxcksum(struct mbuf *m, uint16_t cksum) 548 { 549 struct ether_header *eh; 550 struct ip *ip; 551 struct udphdr *uh; 552 uint16_t *opts; 553 int32_t hlen, len, pktlen; 554 uint32_t temp32; 555 556 pktlen = m->m_pkthdr.len; 557 if (pktlen < sizeof(struct ether_header) + sizeof(struct ip)) 558 return; 559 eh = mtod(m, struct ether_header *); 560 if (eh->ether_type != htons(ETHERTYPE_IP)) 561 return; 562 ip = (struct ip *)(eh + 1); 563 if (ip->ip_v != IPVERSION) 564 return; 565 566 hlen = ip->ip_hl << 2; 567 pktlen -= sizeof(struct ether_header); 568 if (hlen < sizeof(struct ip)) 569 return; 570 if (ntohs(ip->ip_len) < hlen) 571 return; 572 if (ntohs(ip->ip_len) != pktlen) 573 return; 574 if (ip->ip_off & htons(IP_MF | IP_OFFMASK)) 575 return; /* Cannot handle fragmented packet. */ 576 577 switch (ip->ip_p) { 578 case IPPROTO_TCP: 579 if (pktlen < (hlen + sizeof(struct tcphdr))) 580 return; 581 break; 582 case IPPROTO_UDP: 583 if (pktlen < (hlen + sizeof(struct udphdr))) 584 return; 585 uh = (struct udphdr *)((uint8_t *)ip + hlen); 586 if (uh->uh_sum == 0) 587 return; /* no checksum */ 588 break; 589 default: 590 return; 591 } 592 593 cksum = ~cksum; 594 /* checksum fixup for IP options */ 595 len = hlen - sizeof(struct ip); 596 if (len > 0) { 597 opts = (uint16_t *)(ip + 1); 598 for (; len > 0; len -= sizeof(uint16_t), opts++) { 599 temp32 = cksum - *opts; 600 temp32 = (temp32 >> 16) + (temp32 & 65535); 601 cksum = temp32 & 65535; 602 } 603 } 604 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID; 605 m->m_pkthdr.csum_data = cksum; 606 } 607 608 static void 609 cas_cddma_callback(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 610 { 611 struct cas_softc *sc = xsc; 612 613 if (error != 0) 614 return; 615 if (nsegs != 1) 616 panic("%s: bad control buffer segment count", __func__); 617 sc->sc_cddma = segs[0].ds_addr; 618 } 619 620 static void 621 cas_rxdma_callback(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 622 { 623 struct cas_softc *sc = xsc; 624 625 if (error != 0) 626 return; 627 if (nsegs != 1) 628 panic("%s: bad RX buffer segment count", __func__); 629 sc->sc_rxdsoft[sc->sc_rxdptr].rxds_paddr = segs[0].ds_addr; 630 } 631 632 static void 633 cas_tick(void *arg) 634 { 635 struct cas_softc *sc = arg; 636 struct ifnet *ifp = sc->sc_ifp; 637 uint32_t v; 638 639 CAS_LOCK_ASSERT(sc, MA_OWNED); 640 641 /* 642 * Unload collision and error counters. 643 */ 644 ifp->if_collisions += 645 CAS_READ_4(sc, CAS_MAC_NORM_COLL_CNT) + 646 CAS_READ_4(sc, CAS_MAC_FIRST_COLL_CNT); 647 v = CAS_READ_4(sc, CAS_MAC_EXCESS_COLL_CNT) + 648 CAS_READ_4(sc, CAS_MAC_LATE_COLL_CNT); 649 ifp->if_collisions += v; 650 ifp->if_oerrors += v; 651 ifp->if_ierrors += 652 CAS_READ_4(sc, CAS_MAC_RX_LEN_ERR_CNT) + 653 CAS_READ_4(sc, CAS_MAC_RX_ALIGN_ERR) + 654 CAS_READ_4(sc, CAS_MAC_RX_CRC_ERR_CNT) + 655 CAS_READ_4(sc, CAS_MAC_RX_CODE_VIOL); 656 657 /* 658 * Then clear the hardware counters. 659 */ 660 CAS_WRITE_4(sc, CAS_MAC_NORM_COLL_CNT, 0); 661 CAS_WRITE_4(sc, CAS_MAC_FIRST_COLL_CNT, 0); 662 CAS_WRITE_4(sc, CAS_MAC_EXCESS_COLL_CNT, 0); 663 CAS_WRITE_4(sc, CAS_MAC_LATE_COLL_CNT, 0); 664 CAS_WRITE_4(sc, CAS_MAC_RX_LEN_ERR_CNT, 0); 665 CAS_WRITE_4(sc, CAS_MAC_RX_ALIGN_ERR, 0); 666 CAS_WRITE_4(sc, CAS_MAC_RX_CRC_ERR_CNT, 0); 667 CAS_WRITE_4(sc, CAS_MAC_RX_CODE_VIOL, 0); 668 669 mii_tick(sc->sc_mii); 670 671 if (sc->sc_txfree != CAS_MAXTXFREE) 672 cas_tint(sc); 673 674 cas_watchdog(sc); 675 676 callout_reset(&sc->sc_tick_ch, hz, cas_tick, sc); 677 } 678 679 static int 680 cas_bitwait(struct cas_softc *sc, bus_addr_t r, uint32_t clr, uint32_t set) 681 { 682 int i; 683 uint32_t reg; 684 685 for (i = CAS_TRIES; i--; DELAY(100)) { 686 reg = CAS_READ_4(sc, r); 687 if ((reg & clr) == 0 && (reg & set) == set) 688 return (1); 689 } 690 return (0); 691 } 692 693 static void 694 cas_reset(struct cas_softc *sc) 695 { 696 697 #ifdef CAS_DEBUG 698 CTR2(KTR_CAS, "%s: %s", device_get_name(sc->sc_dev), __func__); 699 #endif 700 /* Disable all interrupts in order to avoid spurious ones. */ 701 CAS_WRITE_4(sc, CAS_INTMASK, 0xffffffff); 702 703 cas_reset_rx(sc); 704 cas_reset_tx(sc); 705 706 /* 707 * Do a full reset modulo the result of the last auto-negotiation 708 * when using the SERDES. 709 */ 710 CAS_WRITE_4(sc, CAS_RESET, CAS_RESET_RX | CAS_RESET_TX | 711 ((sc->sc_flags & CAS_SERDES) != 0 ? CAS_RESET_PCS_DIS : 0)); 712 CAS_BARRIER(sc, CAS_RESET, 4, 713 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 714 DELAY(3000); 715 if (!cas_bitwait(sc, CAS_RESET, CAS_RESET_RX | CAS_RESET_TX, 0)) 716 device_printf(sc->sc_dev, "cannot reset device\n"); 717 } 718 719 static void 720 cas_stop(struct ifnet *ifp) 721 { 722 struct cas_softc *sc = ifp->if_softc; 723 struct cas_txsoft *txs; 724 725 #ifdef CAS_DEBUG 726 CTR2(KTR_CAS, "%s: %s", device_get_name(sc->sc_dev), __func__); 727 #endif 728 729 callout_stop(&sc->sc_tick_ch); 730 callout_stop(&sc->sc_rx_ch); 731 732 /* Disable all interrupts in order to avoid spurious ones. */ 733 CAS_WRITE_4(sc, CAS_INTMASK, 0xffffffff); 734 735 cas_reset_tx(sc); 736 cas_reset_rx(sc); 737 738 /* 739 * Release any queued transmit buffers. 740 */ 741 while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 742 STAILQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 743 if (txs->txs_ndescs != 0) { 744 bus_dmamap_sync(sc->sc_tdmatag, txs->txs_dmamap, 745 BUS_DMASYNC_POSTWRITE); 746 bus_dmamap_unload(sc->sc_tdmatag, txs->txs_dmamap); 747 if (txs->txs_mbuf != NULL) { 748 m_freem(txs->txs_mbuf); 749 txs->txs_mbuf = NULL; 750 } 751 } 752 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 753 } 754 755 /* 756 * Mark the interface down and cancel the watchdog timer. 757 */ 758 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 759 sc->sc_flags &= ~CAS_LINK; 760 sc->sc_wdog_timer = 0; 761 } 762 763 static int 764 cas_reset_rx(struct cas_softc *sc) 765 { 766 767 /* 768 * Resetting while DMA is in progress can cause a bus hang, so we 769 * disable DMA first. 770 */ 771 (void)cas_disable_rx(sc); 772 CAS_WRITE_4(sc, CAS_RX_CONF, 0); 773 CAS_BARRIER(sc, CAS_RX_CONF, 4, 774 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 775 if (!cas_bitwait(sc, CAS_RX_CONF, CAS_RX_CONF_RXDMA_EN, 0)) 776 device_printf(sc->sc_dev, "cannot disable RX DMA\n"); 777 778 /* Finally, reset the ERX. */ 779 CAS_WRITE_4(sc, CAS_RESET, CAS_RESET_RX | 780 ((sc->sc_flags & CAS_SERDES) != 0 ? CAS_RESET_PCS_DIS : 0)); 781 CAS_BARRIER(sc, CAS_RESET, 4, 782 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 783 if (!cas_bitwait(sc, CAS_RESET, CAS_RESET_RX, 0)) { 784 device_printf(sc->sc_dev, "cannot reset receiver\n"); 785 return (1); 786 } 787 return (0); 788 } 789 790 static int 791 cas_reset_tx(struct cas_softc *sc) 792 { 793 794 /* 795 * Resetting while DMA is in progress can cause a bus hang, so we 796 * disable DMA first. 797 */ 798 (void)cas_disable_tx(sc); 799 CAS_WRITE_4(sc, CAS_TX_CONF, 0); 800 CAS_BARRIER(sc, CAS_TX_CONF, 4, 801 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 802 if (!cas_bitwait(sc, CAS_TX_CONF, CAS_TX_CONF_TXDMA_EN, 0)) 803 device_printf(sc->sc_dev, "cannot disable TX DMA\n"); 804 805 /* Finally, reset the ETX. */ 806 CAS_WRITE_4(sc, CAS_RESET, CAS_RESET_TX | 807 ((sc->sc_flags & CAS_SERDES) != 0 ? CAS_RESET_PCS_DIS : 0)); 808 CAS_BARRIER(sc, CAS_RESET, 4, 809 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 810 if (!cas_bitwait(sc, CAS_RESET, CAS_RESET_TX, 0)) { 811 device_printf(sc->sc_dev, "cannot reset transmitter\n"); 812 return (1); 813 } 814 return (0); 815 } 816 817 static int 818 cas_disable_rx(struct cas_softc *sc) 819 { 820 821 CAS_WRITE_4(sc, CAS_MAC_RX_CONF, 822 CAS_READ_4(sc, CAS_MAC_RX_CONF) & ~CAS_MAC_RX_CONF_EN); 823 CAS_BARRIER(sc, CAS_MAC_RX_CONF, 4, 824 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 825 if (cas_bitwait(sc, CAS_MAC_RX_CONF, CAS_MAC_RX_CONF_EN, 0)) 826 return (1); 827 device_printf(sc->sc_dev, "cannot disable RX MAC\n"); 828 return (0); 829 } 830 831 static int 832 cas_disable_tx(struct cas_softc *sc) 833 { 834 835 CAS_WRITE_4(sc, CAS_MAC_TX_CONF, 836 CAS_READ_4(sc, CAS_MAC_TX_CONF) & ~CAS_MAC_TX_CONF_EN); 837 CAS_BARRIER(sc, CAS_MAC_TX_CONF, 4, 838 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 839 if (cas_bitwait(sc, CAS_MAC_TX_CONF, CAS_MAC_TX_CONF_EN, 0)) 840 return (1); 841 device_printf(sc->sc_dev, "cannot disable TX MAC\n"); 842 return (0); 843 } 844 845 static inline void 846 cas_rxcompinit(struct cas_rx_comp *rxcomp) 847 { 848 849 rxcomp->crc_word1 = 0; 850 rxcomp->crc_word2 = 0; 851 rxcomp->crc_word3 = 852 htole64(CAS_SET(ETHER_HDR_LEN + sizeof(struct ip), CAS_RC3_CSO)); 853 rxcomp->crc_word4 = htole64(CAS_RC4_ZERO); 854 } 855 856 static void 857 cas_meminit(struct cas_softc *sc) 858 { 859 int i; 860 861 CAS_LOCK_ASSERT(sc, MA_OWNED); 862 863 /* 864 * Initialize the transmit descriptor ring. 865 */ 866 for (i = 0; i < CAS_NTXDESC; i++) { 867 sc->sc_txdescs[i].cd_flags = 0; 868 sc->sc_txdescs[i].cd_buf_ptr = 0; 869 } 870 sc->sc_txfree = CAS_MAXTXFREE; 871 sc->sc_txnext = 0; 872 sc->sc_txwin = 0; 873 874 /* 875 * Initialize the receive completion ring. 876 */ 877 for (i = 0; i < CAS_NRXCOMP; i++) 878 cas_rxcompinit(&sc->sc_rxcomps[i]); 879 sc->sc_rxcptr = 0; 880 881 /* 882 * Initialize the first receive descriptor ring. We leave 883 * the second one zeroed as we don't actually use it. 884 */ 885 for (i = 0; i < CAS_NRXDESC; i++) 886 CAS_INIT_RXDESC(sc, i, i); 887 sc->sc_rxdptr = 0; 888 889 CAS_CDSYNC(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 890 } 891 892 static u_int 893 cas_descsize(u_int sz) 894 { 895 896 switch (sz) { 897 case 32: 898 return (CAS_DESC_32); 899 case 64: 900 return (CAS_DESC_64); 901 case 128: 902 return (CAS_DESC_128); 903 case 256: 904 return (CAS_DESC_256); 905 case 512: 906 return (CAS_DESC_512); 907 case 1024: 908 return (CAS_DESC_1K); 909 case 2048: 910 return (CAS_DESC_2K); 911 case 4096: 912 return (CAS_DESC_4K); 913 case 8192: 914 return (CAS_DESC_8K); 915 default: 916 printf("%s: invalid descriptor ring size %d\n", __func__, sz); 917 return (CAS_DESC_32); 918 } 919 } 920 921 static u_int 922 cas_rxcompsize(u_int sz) 923 { 924 925 switch (sz) { 926 case 128: 927 return (CAS_RX_CONF_COMP_128); 928 case 256: 929 return (CAS_RX_CONF_COMP_256); 930 case 512: 931 return (CAS_RX_CONF_COMP_512); 932 case 1024: 933 return (CAS_RX_CONF_COMP_1K); 934 case 2048: 935 return (CAS_RX_CONF_COMP_2K); 936 case 4096: 937 return (CAS_RX_CONF_COMP_4K); 938 case 8192: 939 return (CAS_RX_CONF_COMP_8K); 940 case 16384: 941 return (CAS_RX_CONF_COMP_16K); 942 case 32768: 943 return (CAS_RX_CONF_COMP_32K); 944 default: 945 printf("%s: invalid dcompletion ring size %d\n", __func__, sz); 946 return (CAS_RX_CONF_COMP_128); 947 } 948 } 949 950 static void 951 cas_init(void *xsc) 952 { 953 struct cas_softc *sc = xsc; 954 955 CAS_LOCK(sc); 956 cas_init_locked(sc); 957 CAS_UNLOCK(sc); 958 } 959 960 /* 961 * Initialization of interface; set up initialization block 962 * and transmit/receive descriptor rings. 963 */ 964 static void 965 cas_init_locked(struct cas_softc *sc) 966 { 967 struct ifnet *ifp = sc->sc_ifp; 968 uint32_t v; 969 970 CAS_LOCK_ASSERT(sc, MA_OWNED); 971 972 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 973 return; 974 975 #ifdef CAS_DEBUG 976 CTR2(KTR_CAS, "%s: %s: calling stop", device_get_name(sc->sc_dev), 977 __func__); 978 #endif 979 /* 980 * Initialization sequence. The numbered steps below correspond 981 * to the sequence outlined in section 6.3.5.1 in the Ethernet 982 * Channel Engine manual (part of the PCIO manual). 983 * See also the STP2002-STQ document from Sun Microsystems. 984 */ 985 986 /* step 1 & 2. Reset the Ethernet Channel. */ 987 cas_stop(ifp); 988 cas_reset(sc); 989 #ifdef CAS_DEBUG 990 CTR2(KTR_CAS, "%s: %s: restarting", device_get_name(sc->sc_dev), 991 __func__); 992 #endif 993 994 if ((sc->sc_flags & CAS_SERDES) == 0) 995 /* Re-initialize the MIF. */ 996 cas_mifinit(sc); 997 998 /* step 3. Setup data structures in host memory. */ 999 cas_meminit(sc); 1000 1001 /* step 4. TX MAC registers & counters */ 1002 cas_init_regs(sc); 1003 1004 /* step 5. RX MAC registers & counters */ 1005 1006 /* step 6 & 7. Program Ring Base Addresses. */ 1007 CAS_WRITE_4(sc, CAS_TX_DESC3_BASE_HI, 1008 (((uint64_t)CAS_CDTXDADDR(sc, 0)) >> 32)); 1009 CAS_WRITE_4(sc, CAS_TX_DESC3_BASE_LO, 1010 CAS_CDTXDADDR(sc, 0) & 0xffffffff); 1011 1012 CAS_WRITE_4(sc, CAS_RX_COMP_BASE_HI, 1013 (((uint64_t)CAS_CDRXCADDR(sc, 0)) >> 32)); 1014 CAS_WRITE_4(sc, CAS_RX_COMP_BASE_LO, 1015 CAS_CDRXCADDR(sc, 0) & 0xffffffff); 1016 1017 CAS_WRITE_4(sc, CAS_RX_DESC_BASE_HI, 1018 (((uint64_t)CAS_CDRXDADDR(sc, 0)) >> 32)); 1019 CAS_WRITE_4(sc, CAS_RX_DESC_BASE_LO, 1020 CAS_CDRXDADDR(sc, 0) & 0xffffffff); 1021 1022 if ((sc->sc_flags & CAS_REG_PLUS) != 0) { 1023 CAS_WRITE_4(sc, CAS_RX_DESC2_BASE_HI, 1024 (((uint64_t)CAS_CDRXD2ADDR(sc, 0)) >> 32)); 1025 CAS_WRITE_4(sc, CAS_RX_DESC2_BASE_LO, 1026 CAS_CDRXD2ADDR(sc, 0) & 0xffffffff); 1027 } 1028 1029 #ifdef CAS_DEBUG 1030 CTR5(KTR_CAS, 1031 "loading TXDR %lx, RXCR %lx, RXDR %lx, RXD2R %lx, cddma %lx", 1032 CAS_CDTXDADDR(sc, 0), CAS_CDRXCADDR(sc, 0), CAS_CDRXDADDR(sc, 0), 1033 CAS_CDRXD2ADDR(sc, 0), sc->sc_cddma); 1034 #endif 1035 1036 /* step 8. Global Configuration & Interrupt Masks */ 1037 1038 /* Disable weighted round robin. */ 1039 CAS_WRITE_4(sc, CAS_CAW, CAS_CAW_RR_DIS); 1040 1041 /* 1042 * Enable infinite bursts for revisions without PCI issues if 1043 * applicable. Doing so greatly improves the TX performance on 1044 * !__sparc64__. 1045 */ 1046 CAS_WRITE_4(sc, CAS_INF_BURST, 1047 #if !defined(__sparc64__) 1048 (sc->sc_flags & CAS_TABORT) == 0 ? CAS_INF_BURST_EN : 1049 #endif 1050 0); 1051 1052 /* Set up interrupts. */ 1053 CAS_WRITE_4(sc, CAS_INTMASK, 1054 ~(CAS_INTR_TX_INT_ME | CAS_INTR_TX_TAG_ERR | 1055 CAS_INTR_RX_DONE | CAS_INTR_RX_BUF_NA | CAS_INTR_RX_TAG_ERR | 1056 CAS_INTR_RX_COMP_FULL | CAS_INTR_RX_BUF_AEMPTY | 1057 CAS_INTR_RX_COMP_AFULL | CAS_INTR_RX_LEN_MMATCH | 1058 CAS_INTR_PCI_ERROR_INT 1059 #ifdef CAS_DEBUG 1060 | CAS_INTR_PCS_INT | CAS_INTR_MIF 1061 #endif 1062 )); 1063 /* Don't clear top level interrupts when CAS_STATUS_ALIAS is read. */ 1064 CAS_WRITE_4(sc, CAS_CLEAR_ALIAS, 0); 1065 CAS_WRITE_4(sc, CAS_MAC_RX_MASK, ~CAS_MAC_RX_OVERFLOW); 1066 CAS_WRITE_4(sc, CAS_MAC_TX_MASK, 1067 ~(CAS_MAC_TX_UNDERRUN | CAS_MAC_TX_MAX_PKT_ERR)); 1068 #ifdef CAS_DEBUG 1069 CAS_WRITE_4(sc, CAS_MAC_CTRL_MASK, 1070 ~(CAS_MAC_CTRL_PAUSE_RCVD | CAS_MAC_CTRL_PAUSE | 1071 CAS_MAC_CTRL_NON_PAUSE)); 1072 #else 1073 CAS_WRITE_4(sc, CAS_MAC_CTRL_MASK, 1074 CAS_MAC_CTRL_PAUSE_RCVD | CAS_MAC_CTRL_PAUSE | 1075 CAS_MAC_CTRL_NON_PAUSE); 1076 #endif 1077 1078 /* Enable PCI error interrupts. */ 1079 CAS_WRITE_4(sc, CAS_ERROR_MASK, 1080 ~(CAS_ERROR_DTRTO | CAS_ERROR_OTHER | CAS_ERROR_DMAW_ZERO | 1081 CAS_ERROR_DMAR_ZERO | CAS_ERROR_RTRTO)); 1082 1083 /* Enable PCI error interrupts in BIM configuration. */ 1084 CAS_WRITE_4(sc, CAS_BIM_CONF, 1085 CAS_BIM_CONF_DPAR_EN | CAS_BIM_CONF_RMA_EN | CAS_BIM_CONF_RTA_EN); 1086 1087 /* 1088 * step 9. ETX Configuration: encode receive descriptor ring size, 1089 * enable DMA and disable pre-interrupt writeback completion. 1090 */ 1091 v = cas_descsize(CAS_NTXDESC) << CAS_TX_CONF_DESC3_SHFT; 1092 CAS_WRITE_4(sc, CAS_TX_CONF, v | CAS_TX_CONF_TXDMA_EN | 1093 CAS_TX_CONF_RDPP_DIS | CAS_TX_CONF_PICWB_DIS); 1094 1095 /* step 10. ERX Configuration */ 1096 1097 /* 1098 * Encode receive completion and descriptor ring sizes, set the 1099 * swivel offset. 1100 */ 1101 v = cas_rxcompsize(CAS_NRXCOMP) << CAS_RX_CONF_COMP_SHFT; 1102 v |= cas_descsize(CAS_NRXDESC) << CAS_RX_CONF_DESC_SHFT; 1103 if ((sc->sc_flags & CAS_REG_PLUS) != 0) 1104 v |= cas_descsize(CAS_NRXDESC2) << CAS_RX_CONF_DESC2_SHFT; 1105 CAS_WRITE_4(sc, CAS_RX_CONF, 1106 v | (ETHER_ALIGN << CAS_RX_CONF_SOFF_SHFT)); 1107 1108 /* Set the PAUSE thresholds. We use the maximum OFF threshold. */ 1109 CAS_WRITE_4(sc, CAS_RX_PTHRS, 1110 (111 << CAS_RX_PTHRS_XOFF_SHFT) | (15 << CAS_RX_PTHRS_XON_SHFT)); 1111 1112 /* RX blanking */ 1113 CAS_WRITE_4(sc, CAS_RX_BLANK, 1114 (15 << CAS_RX_BLANK_TIME_SHFT) | (5 << CAS_RX_BLANK_PKTS_SHFT)); 1115 1116 /* Set RX_COMP_AFULL threshold to half of the RX completions. */ 1117 CAS_WRITE_4(sc, CAS_RX_AEMPTY_THRS, 1118 (CAS_NRXCOMP / 2) << CAS_RX_AEMPTY_COMP_SHFT); 1119 1120 /* Initialize the RX page size register as appropriate for 8k. */ 1121 CAS_WRITE_4(sc, CAS_RX_PSZ, 1122 (CAS_RX_PSZ_8K << CAS_RX_PSZ_SHFT) | 1123 (4 << CAS_RX_PSZ_MB_CNT_SHFT) | 1124 (CAS_RX_PSZ_MB_STRD_2K << CAS_RX_PSZ_MB_STRD_SHFT) | 1125 (CAS_RX_PSZ_MB_OFF_64 << CAS_RX_PSZ_MB_OFF_SHFT)); 1126 1127 /* Disable RX random early detection. */ 1128 CAS_WRITE_4(sc, CAS_RX_RED, 0); 1129 1130 /* Zero the RX reassembly DMA table. */ 1131 for (v = 0; v <= CAS_RX_REAS_DMA_ADDR_LC; v++) { 1132 CAS_WRITE_4(sc, CAS_RX_REAS_DMA_ADDR, v); 1133 CAS_WRITE_4(sc, CAS_RX_REAS_DMA_DATA_LO, 0); 1134 CAS_WRITE_4(sc, CAS_RX_REAS_DMA_DATA_MD, 0); 1135 CAS_WRITE_4(sc, CAS_RX_REAS_DMA_DATA_HI, 0); 1136 } 1137 1138 /* Ensure the RX control FIFO and RX IPP FIFO addresses are zero. */ 1139 CAS_WRITE_4(sc, CAS_RX_CTRL_FIFO, 0); 1140 CAS_WRITE_4(sc, CAS_RX_IPP_ADDR, 0); 1141 1142 /* Finally, enable RX DMA. */ 1143 CAS_WRITE_4(sc, CAS_RX_CONF, 1144 CAS_READ_4(sc, CAS_RX_CONF) | CAS_RX_CONF_RXDMA_EN); 1145 1146 /* step 11. Configure Media. */ 1147 1148 /* step 12. RX_MAC Configuration Register */ 1149 v = CAS_READ_4(sc, CAS_MAC_RX_CONF); 1150 v &= ~(CAS_MAC_RX_CONF_STRPPAD | CAS_MAC_RX_CONF_EN); 1151 v |= CAS_MAC_RX_CONF_STRPFCS; 1152 sc->sc_mac_rxcfg = v; 1153 /* 1154 * Clear the RX filter and reprogram it. This will also set the 1155 * current RX MAC configuration and enable it. 1156 */ 1157 cas_setladrf(sc); 1158 1159 /* step 13. TX_MAC Configuration Register */ 1160 v = CAS_READ_4(sc, CAS_MAC_TX_CONF); 1161 v |= CAS_MAC_TX_CONF_EN; 1162 (void)cas_disable_tx(sc); 1163 CAS_WRITE_4(sc, CAS_MAC_TX_CONF, v); 1164 1165 /* step 14. Issue Transmit Pending command. */ 1166 1167 /* step 15. Give the receiver a swift kick. */ 1168 CAS_WRITE_4(sc, CAS_RX_KICK, CAS_NRXDESC - 4); 1169 CAS_WRITE_4(sc, CAS_RX_COMP_TAIL, 0); 1170 if ((sc->sc_flags & CAS_REG_PLUS) != 0) 1171 CAS_WRITE_4(sc, CAS_RX_KICK2, CAS_NRXDESC2 - 4); 1172 1173 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1174 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1175 1176 mii_mediachg(sc->sc_mii); 1177 1178 /* Start the one second timer. */ 1179 sc->sc_wdog_timer = 0; 1180 callout_reset(&sc->sc_tick_ch, hz, cas_tick, sc); 1181 } 1182 1183 static int 1184 cas_load_txmbuf(struct cas_softc *sc, struct mbuf **m_head) 1185 { 1186 bus_dma_segment_t txsegs[CAS_NTXSEGS]; 1187 struct cas_txsoft *txs; 1188 struct ip *ip; 1189 struct mbuf *m; 1190 uint64_t cflags; 1191 int error, nexttx, nsegs, offset, seg; 1192 1193 CAS_LOCK_ASSERT(sc, MA_OWNED); 1194 1195 /* Get a work queue entry. */ 1196 if ((txs = STAILQ_FIRST(&sc->sc_txfreeq)) == NULL) { 1197 /* Ran out of descriptors. */ 1198 return (ENOBUFS); 1199 } 1200 1201 cflags = 0; 1202 if (((*m_head)->m_pkthdr.csum_flags & CAS_CSUM_FEATURES) != 0) { 1203 if (M_WRITABLE(*m_head) == 0) { 1204 m = m_dup(*m_head, M_NOWAIT); 1205 m_freem(*m_head); 1206 *m_head = m; 1207 if (m == NULL) 1208 return (ENOBUFS); 1209 } 1210 offset = sizeof(struct ether_header); 1211 m = m_pullup(*m_head, offset + sizeof(struct ip)); 1212 if (m == NULL) { 1213 *m_head = NULL; 1214 return (ENOBUFS); 1215 } 1216 ip = (struct ip *)(mtod(m, caddr_t) + offset); 1217 offset += (ip->ip_hl << 2); 1218 cflags = (offset << CAS_TD_CKSUM_START_SHFT) | 1219 ((offset + m->m_pkthdr.csum_data) << 1220 CAS_TD_CKSUM_STUFF_SHFT) | CAS_TD_CKSUM_EN; 1221 *m_head = m; 1222 } 1223 1224 error = bus_dmamap_load_mbuf_sg(sc->sc_tdmatag, txs->txs_dmamap, 1225 *m_head, txsegs, &nsegs, BUS_DMA_NOWAIT); 1226 if (error == EFBIG) { 1227 m = m_collapse(*m_head, M_NOWAIT, CAS_NTXSEGS); 1228 if (m == NULL) { 1229 m_freem(*m_head); 1230 *m_head = NULL; 1231 return (ENOBUFS); 1232 } 1233 *m_head = m; 1234 error = bus_dmamap_load_mbuf_sg(sc->sc_tdmatag, 1235 txs->txs_dmamap, *m_head, txsegs, &nsegs, 1236 BUS_DMA_NOWAIT); 1237 if (error != 0) { 1238 m_freem(*m_head); 1239 *m_head = NULL; 1240 return (error); 1241 } 1242 } else if (error != 0) 1243 return (error); 1244 /* If nsegs is wrong then the stack is corrupt. */ 1245 KASSERT(nsegs <= CAS_NTXSEGS, 1246 ("%s: too many DMA segments (%d)", __func__, nsegs)); 1247 if (nsegs == 0) { 1248 m_freem(*m_head); 1249 *m_head = NULL; 1250 return (EIO); 1251 } 1252 1253 /* 1254 * Ensure we have enough descriptors free to describe 1255 * the packet. Note, we always reserve one descriptor 1256 * at the end of the ring as a termination point, in 1257 * order to prevent wrap-around. 1258 */ 1259 if (nsegs > sc->sc_txfree - 1) { 1260 txs->txs_ndescs = 0; 1261 bus_dmamap_unload(sc->sc_tdmatag, txs->txs_dmamap); 1262 return (ENOBUFS); 1263 } 1264 1265 txs->txs_ndescs = nsegs; 1266 txs->txs_firstdesc = sc->sc_txnext; 1267 nexttx = txs->txs_firstdesc; 1268 for (seg = 0; seg < nsegs; seg++, nexttx = CAS_NEXTTX(nexttx)) { 1269 #ifdef CAS_DEBUG 1270 CTR6(KTR_CAS, 1271 "%s: mapping seg %d (txd %d), len %lx, addr %#lx (%#lx)", 1272 __func__, seg, nexttx, txsegs[seg].ds_len, 1273 txsegs[seg].ds_addr, htole64(txsegs[seg].ds_addr)); 1274 #endif 1275 sc->sc_txdescs[nexttx].cd_buf_ptr = 1276 htole64(txsegs[seg].ds_addr); 1277 KASSERT(txsegs[seg].ds_len < 1278 CAS_TD_BUF_LEN_MASK >> CAS_TD_BUF_LEN_SHFT, 1279 ("%s: segment size too large!", __func__)); 1280 sc->sc_txdescs[nexttx].cd_flags = 1281 htole64(txsegs[seg].ds_len << CAS_TD_BUF_LEN_SHFT); 1282 txs->txs_lastdesc = nexttx; 1283 } 1284 1285 /* Set EOF on the last descriptor. */ 1286 #ifdef CAS_DEBUG 1287 CTR3(KTR_CAS, "%s: end of frame at segment %d, TX %d", 1288 __func__, seg, nexttx); 1289 #endif 1290 sc->sc_txdescs[txs->txs_lastdesc].cd_flags |= 1291 htole64(CAS_TD_END_OF_FRAME); 1292 1293 /* Lastly set SOF on the first descriptor. */ 1294 #ifdef CAS_DEBUG 1295 CTR3(KTR_CAS, "%s: start of frame at segment %d, TX %d", 1296 __func__, seg, nexttx); 1297 #endif 1298 if (sc->sc_txwin += nsegs > CAS_MAXTXFREE * 2 / 3) { 1299 sc->sc_txwin = 0; 1300 sc->sc_txdescs[txs->txs_firstdesc].cd_flags |= 1301 htole64(cflags | CAS_TD_START_OF_FRAME | CAS_TD_INT_ME); 1302 } else 1303 sc->sc_txdescs[txs->txs_firstdesc].cd_flags |= 1304 htole64(cflags | CAS_TD_START_OF_FRAME); 1305 1306 /* Sync the DMA map. */ 1307 bus_dmamap_sync(sc->sc_tdmatag, txs->txs_dmamap, 1308 BUS_DMASYNC_PREWRITE); 1309 1310 #ifdef CAS_DEBUG 1311 CTR4(KTR_CAS, "%s: setting firstdesc=%d, lastdesc=%d, ndescs=%d", 1312 __func__, txs->txs_firstdesc, txs->txs_lastdesc, 1313 txs->txs_ndescs); 1314 #endif 1315 STAILQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 1316 STAILQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1317 txs->txs_mbuf = *m_head; 1318 1319 sc->sc_txnext = CAS_NEXTTX(txs->txs_lastdesc); 1320 sc->sc_txfree -= txs->txs_ndescs; 1321 1322 return (0); 1323 } 1324 1325 static void 1326 cas_init_regs(struct cas_softc *sc) 1327 { 1328 int i; 1329 const u_char *laddr = IF_LLADDR(sc->sc_ifp); 1330 1331 CAS_LOCK_ASSERT(sc, MA_OWNED); 1332 1333 /* These registers are not cleared on reset. */ 1334 if ((sc->sc_flags & CAS_INITED) == 0) { 1335 /* magic values */ 1336 CAS_WRITE_4(sc, CAS_MAC_IPG0, 0); 1337 CAS_WRITE_4(sc, CAS_MAC_IPG1, 8); 1338 CAS_WRITE_4(sc, CAS_MAC_IPG2, 4); 1339 1340 /* min frame length */ 1341 CAS_WRITE_4(sc, CAS_MAC_MIN_FRAME, ETHER_MIN_LEN); 1342 /* max frame length and max burst size */ 1343 CAS_WRITE_4(sc, CAS_MAC_MAX_BF, 1344 ((ETHER_MAX_LEN_JUMBO + ETHER_VLAN_ENCAP_LEN) << 1345 CAS_MAC_MAX_BF_FRM_SHFT) | 1346 (0x2000 << CAS_MAC_MAX_BF_BST_SHFT)); 1347 1348 /* more magic values */ 1349 CAS_WRITE_4(sc, CAS_MAC_PREAMBLE_LEN, 0x7); 1350 CAS_WRITE_4(sc, CAS_MAC_JAM_SIZE, 0x4); 1351 CAS_WRITE_4(sc, CAS_MAC_ATTEMPT_LIMIT, 0x10); 1352 CAS_WRITE_4(sc, CAS_MAC_CTRL_TYPE, 0x8808); 1353 1354 /* random number seed */ 1355 CAS_WRITE_4(sc, CAS_MAC_RANDOM_SEED, 1356 ((laddr[5] << 8) | laddr[4]) & 0x3ff); 1357 1358 /* secondary MAC addresses: 0:0:0:0:0:0 */ 1359 for (i = CAS_MAC_ADDR3; i <= CAS_MAC_ADDR41; 1360 i += CAS_MAC_ADDR4 - CAS_MAC_ADDR3) 1361 CAS_WRITE_4(sc, i, 0); 1362 1363 /* MAC control address: 01:80:c2:00:00:01 */ 1364 CAS_WRITE_4(sc, CAS_MAC_ADDR42, 0x0001); 1365 CAS_WRITE_4(sc, CAS_MAC_ADDR43, 0xc200); 1366 CAS_WRITE_4(sc, CAS_MAC_ADDR44, 0x0180); 1367 1368 /* MAC filter address: 0:0:0:0:0:0 */ 1369 CAS_WRITE_4(sc, CAS_MAC_AFILTER0, 0); 1370 CAS_WRITE_4(sc, CAS_MAC_AFILTER1, 0); 1371 CAS_WRITE_4(sc, CAS_MAC_AFILTER2, 0); 1372 CAS_WRITE_4(sc, CAS_MAC_AFILTER_MASK1_2, 0); 1373 CAS_WRITE_4(sc, CAS_MAC_AFILTER_MASK0, 0); 1374 1375 /* Zero the hash table. */ 1376 for (i = CAS_MAC_HASH0; i <= CAS_MAC_HASH15; 1377 i += CAS_MAC_HASH1 - CAS_MAC_HASH0) 1378 CAS_WRITE_4(sc, i, 0); 1379 1380 sc->sc_flags |= CAS_INITED; 1381 } 1382 1383 /* Counters need to be zeroed. */ 1384 CAS_WRITE_4(sc, CAS_MAC_NORM_COLL_CNT, 0); 1385 CAS_WRITE_4(sc, CAS_MAC_FIRST_COLL_CNT, 0); 1386 CAS_WRITE_4(sc, CAS_MAC_EXCESS_COLL_CNT, 0); 1387 CAS_WRITE_4(sc, CAS_MAC_LATE_COLL_CNT, 0); 1388 CAS_WRITE_4(sc, CAS_MAC_DEFER_TMR_CNT, 0); 1389 CAS_WRITE_4(sc, CAS_MAC_PEAK_ATTEMPTS, 0); 1390 CAS_WRITE_4(sc, CAS_MAC_RX_FRAME_COUNT, 0); 1391 CAS_WRITE_4(sc, CAS_MAC_RX_LEN_ERR_CNT, 0); 1392 CAS_WRITE_4(sc, CAS_MAC_RX_ALIGN_ERR, 0); 1393 CAS_WRITE_4(sc, CAS_MAC_RX_CRC_ERR_CNT, 0); 1394 CAS_WRITE_4(sc, CAS_MAC_RX_CODE_VIOL, 0); 1395 1396 /* Set XOFF PAUSE time. */ 1397 CAS_WRITE_4(sc, CAS_MAC_SPC, 0x1BF0 << CAS_MAC_SPC_TIME_SHFT); 1398 1399 /* Set the station address. */ 1400 CAS_WRITE_4(sc, CAS_MAC_ADDR0, (laddr[4] << 8) | laddr[5]); 1401 CAS_WRITE_4(sc, CAS_MAC_ADDR1, (laddr[2] << 8) | laddr[3]); 1402 CAS_WRITE_4(sc, CAS_MAC_ADDR2, (laddr[0] << 8) | laddr[1]); 1403 1404 /* Enable MII outputs. */ 1405 CAS_WRITE_4(sc, CAS_MAC_XIF_CONF, CAS_MAC_XIF_CONF_TX_OE); 1406 } 1407 1408 static void 1409 cas_tx_task(void *arg, int pending __unused) 1410 { 1411 struct ifnet *ifp; 1412 1413 ifp = (struct ifnet *)arg; 1414 cas_start(ifp); 1415 } 1416 1417 static inline void 1418 cas_txkick(struct cas_softc *sc) 1419 { 1420 1421 /* 1422 * Update the TX kick register. This register has to point to the 1423 * descriptor after the last valid one and for optimum performance 1424 * should be incremented in multiples of 4 (the DMA engine fetches/ 1425 * updates descriptors in batches of 4). 1426 */ 1427 #ifdef CAS_DEBUG 1428 CTR3(KTR_CAS, "%s: %s: kicking TX %d", 1429 device_get_name(sc->sc_dev), __func__, sc->sc_txnext); 1430 #endif 1431 CAS_CDSYNC(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1432 CAS_WRITE_4(sc, CAS_TX_KICK3, sc->sc_txnext); 1433 } 1434 1435 static void 1436 cas_start(struct ifnet *ifp) 1437 { 1438 struct cas_softc *sc = ifp->if_softc; 1439 struct mbuf *m; 1440 int kicked, ntx; 1441 1442 CAS_LOCK(sc); 1443 1444 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1445 IFF_DRV_RUNNING || (sc->sc_flags & CAS_LINK) == 0) { 1446 CAS_UNLOCK(sc); 1447 return; 1448 } 1449 1450 if (sc->sc_txfree < CAS_MAXTXFREE / 4) 1451 cas_tint(sc); 1452 1453 #ifdef CAS_DEBUG 1454 CTR4(KTR_CAS, "%s: %s: txfree %d, txnext %d", 1455 device_get_name(sc->sc_dev), __func__, sc->sc_txfree, 1456 sc->sc_txnext); 1457 #endif 1458 ntx = 0; 1459 kicked = 0; 1460 for (; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && sc->sc_txfree > 1;) { 1461 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 1462 if (m == NULL) 1463 break; 1464 if (cas_load_txmbuf(sc, &m) != 0) { 1465 if (m == NULL) 1466 break; 1467 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1468 IFQ_DRV_PREPEND(&ifp->if_snd, m); 1469 break; 1470 } 1471 if ((sc->sc_txnext % 4) == 0) { 1472 cas_txkick(sc); 1473 kicked = 1; 1474 } else 1475 kicked = 0; 1476 ntx++; 1477 BPF_MTAP(ifp, m); 1478 } 1479 1480 if (ntx > 0) { 1481 if (kicked == 0) 1482 cas_txkick(sc); 1483 #ifdef CAS_DEBUG 1484 CTR2(KTR_CAS, "%s: packets enqueued, OWN on %d", 1485 device_get_name(sc->sc_dev), sc->sc_txnext); 1486 #endif 1487 1488 /* Set a watchdog timer in case the chip flakes out. */ 1489 sc->sc_wdog_timer = 5; 1490 #ifdef CAS_DEBUG 1491 CTR3(KTR_CAS, "%s: %s: watchdog %d", 1492 device_get_name(sc->sc_dev), __func__, 1493 sc->sc_wdog_timer); 1494 #endif 1495 } 1496 1497 CAS_UNLOCK(sc); 1498 } 1499 1500 static void 1501 cas_tint(struct cas_softc *sc) 1502 { 1503 struct ifnet *ifp = sc->sc_ifp; 1504 struct cas_txsoft *txs; 1505 int progress; 1506 uint32_t txlast; 1507 #ifdef CAS_DEBUG 1508 int i; 1509 1510 CAS_LOCK_ASSERT(sc, MA_OWNED); 1511 1512 CTR2(KTR_CAS, "%s: %s", device_get_name(sc->sc_dev), __func__); 1513 #endif 1514 1515 /* 1516 * Go through our TX list and free mbufs for those 1517 * frames that have been transmitted. 1518 */ 1519 progress = 0; 1520 CAS_CDSYNC(sc, BUS_DMASYNC_POSTREAD); 1521 while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1522 #ifdef CAS_DEBUG 1523 if ((ifp->if_flags & IFF_DEBUG) != 0) { 1524 printf(" txsoft %p transmit chain:\n", txs); 1525 for (i = txs->txs_firstdesc;; i = CAS_NEXTTX(i)) { 1526 printf("descriptor %d: ", i); 1527 printf("cd_flags: 0x%016llx\t", 1528 (long long)le64toh( 1529 sc->sc_txdescs[i].cd_flags)); 1530 printf("cd_buf_ptr: 0x%016llx\n", 1531 (long long)le64toh( 1532 sc->sc_txdescs[i].cd_buf_ptr)); 1533 if (i == txs->txs_lastdesc) 1534 break; 1535 } 1536 } 1537 #endif 1538 1539 /* 1540 * In theory, we could harvest some descriptors before 1541 * the ring is empty, but that's a bit complicated. 1542 * 1543 * CAS_TX_COMPn points to the last descriptor 1544 * processed + 1. 1545 */ 1546 txlast = CAS_READ_4(sc, CAS_TX_COMP3); 1547 #ifdef CAS_DEBUG 1548 CTR4(KTR_CAS, "%s: txs->txs_firstdesc = %d, " 1549 "txs->txs_lastdesc = %d, txlast = %d", 1550 __func__, txs->txs_firstdesc, txs->txs_lastdesc, txlast); 1551 #endif 1552 if (txs->txs_firstdesc <= txs->txs_lastdesc) { 1553 if ((txlast >= txs->txs_firstdesc) && 1554 (txlast <= txs->txs_lastdesc)) 1555 break; 1556 } else { 1557 /* Ick -- this command wraps. */ 1558 if ((txlast >= txs->txs_firstdesc) || 1559 (txlast <= txs->txs_lastdesc)) 1560 break; 1561 } 1562 1563 #ifdef CAS_DEBUG 1564 CTR1(KTR_CAS, "%s: releasing a descriptor", __func__); 1565 #endif 1566 STAILQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1567 1568 sc->sc_txfree += txs->txs_ndescs; 1569 1570 bus_dmamap_sync(sc->sc_tdmatag, txs->txs_dmamap, 1571 BUS_DMASYNC_POSTWRITE); 1572 bus_dmamap_unload(sc->sc_tdmatag, txs->txs_dmamap); 1573 if (txs->txs_mbuf != NULL) { 1574 m_freem(txs->txs_mbuf); 1575 txs->txs_mbuf = NULL; 1576 } 1577 1578 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1579 1580 ifp->if_opackets++; 1581 progress = 1; 1582 } 1583 1584 #ifdef CAS_DEBUG 1585 CTR5(KTR_CAS, "%s: CAS_TX_SM1 %x CAS_TX_SM2 %x CAS_TX_DESC_BASE %llx " 1586 "CAS_TX_COMP3 %x", 1587 __func__, CAS_READ_4(sc, CAS_TX_SM1), CAS_READ_4(sc, CAS_TX_SM2), 1588 ((long long)CAS_READ_4(sc, CAS_TX_DESC3_BASE_HI) << 32) | 1589 CAS_READ_4(sc, CAS_TX_DESC3_BASE_LO), 1590 CAS_READ_4(sc, CAS_TX_COMP3)); 1591 #endif 1592 1593 if (progress) { 1594 /* We freed some descriptors, so reset IFF_DRV_OACTIVE. */ 1595 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1596 if (STAILQ_EMPTY(&sc->sc_txdirtyq)) 1597 sc->sc_wdog_timer = 0; 1598 } 1599 1600 #ifdef CAS_DEBUG 1601 CTR3(KTR_CAS, "%s: %s: watchdog %d", 1602 device_get_name(sc->sc_dev), __func__, sc->sc_wdog_timer); 1603 #endif 1604 } 1605 1606 static void 1607 cas_rint_timeout(void *arg) 1608 { 1609 struct cas_softc *sc = arg; 1610 1611 CAS_LOCK_ASSERT(sc, MA_OWNED); 1612 1613 cas_rint(sc); 1614 } 1615 1616 static void 1617 cas_rint(struct cas_softc *sc) 1618 { 1619 struct cas_rxdsoft *rxds, *rxds2; 1620 struct ifnet *ifp = sc->sc_ifp; 1621 struct mbuf *m, *m2; 1622 uint64_t word1, word2, word3, word4; 1623 uint32_t rxhead; 1624 u_int idx, idx2, len, off, skip; 1625 1626 CAS_LOCK_ASSERT(sc, MA_OWNED); 1627 1628 callout_stop(&sc->sc_rx_ch); 1629 1630 #ifdef CAS_DEBUG 1631 CTR2(KTR_CAS, "%s: %s", device_get_name(sc->sc_dev), __func__); 1632 #endif 1633 1634 #define PRINTWORD(n, delimiter) \ 1635 printf("word ## n: 0x%016llx%c", (long long)word ## n, delimiter) 1636 1637 #define SKIPASSERT(n) \ 1638 KASSERT(sc->sc_rxcomps[sc->sc_rxcptr].crc_word ## n == 0, \ 1639 ("%s: word ## n not 0", __func__)) 1640 1641 #define WORDTOH(n) \ 1642 word ## n = le64toh(sc->sc_rxcomps[sc->sc_rxcptr].crc_word ## n) 1643 1644 /* 1645 * Read the completion head register once. This limits 1646 * how long the following loop can execute. 1647 */ 1648 rxhead = CAS_READ_4(sc, CAS_RX_COMP_HEAD); 1649 #ifdef CAS_DEBUG 1650 CTR4(KTR_CAS, "%s: sc->sc_rxcptr %d, sc->sc_rxdptr %d, head %d", 1651 __func__, sc->sc_rxcptr, sc->sc_rxdptr, rxhead); 1652 #endif 1653 skip = 0; 1654 CAS_CDSYNC(sc, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1655 for (; sc->sc_rxcptr != rxhead; 1656 sc->sc_rxcptr = CAS_NEXTRXCOMP(sc->sc_rxcptr)) { 1657 if (skip != 0) { 1658 SKIPASSERT(1); 1659 SKIPASSERT(2); 1660 SKIPASSERT(3); 1661 1662 --skip; 1663 goto skip; 1664 } 1665 1666 WORDTOH(1); 1667 WORDTOH(2); 1668 WORDTOH(3); 1669 WORDTOH(4); 1670 1671 #ifdef CAS_DEBUG 1672 if ((ifp->if_flags & IFF_DEBUG) != 0) { 1673 printf(" completion %d: ", sc->sc_rxcptr); 1674 PRINTWORD(1, '\t'); 1675 PRINTWORD(2, '\t'); 1676 PRINTWORD(3, '\t'); 1677 PRINTWORD(4, '\n'); 1678 } 1679 #endif 1680 1681 if (__predict_false( 1682 (word1 & CAS_RC1_TYPE_MASK) == CAS_RC1_TYPE_HW || 1683 (word4 & CAS_RC4_ZERO) != 0)) { 1684 /* 1685 * The descriptor is still marked as owned, although 1686 * it is supposed to have completed. This has been 1687 * observed on some machines. Just exiting here 1688 * might leave the packet sitting around until another 1689 * one arrives to trigger a new interrupt, which is 1690 * generally undesirable, so set up a timeout. 1691 */ 1692 callout_reset(&sc->sc_rx_ch, CAS_RXOWN_TICKS, 1693 cas_rint_timeout, sc); 1694 break; 1695 } 1696 1697 if (__predict_false( 1698 (word4 & (CAS_RC4_BAD | CAS_RC4_LEN_MMATCH)) != 0)) { 1699 ifp->if_ierrors++; 1700 device_printf(sc->sc_dev, 1701 "receive error: CRC error\n"); 1702 continue; 1703 } 1704 1705 KASSERT(CAS_GET(word1, CAS_RC1_DATA_SIZE) == 0 || 1706 CAS_GET(word2, CAS_RC2_HDR_SIZE) == 0, 1707 ("%s: data and header present", __func__)); 1708 KASSERT((word1 & CAS_RC1_SPLIT_PKT) == 0 || 1709 CAS_GET(word2, CAS_RC2_HDR_SIZE) == 0, 1710 ("%s: split and header present", __func__)); 1711 KASSERT(CAS_GET(word1, CAS_RC1_DATA_SIZE) == 0 || 1712 (word1 & CAS_RC1_RELEASE_HDR) == 0, 1713 ("%s: data present but header release", __func__)); 1714 KASSERT(CAS_GET(word2, CAS_RC2_HDR_SIZE) == 0 || 1715 (word1 & CAS_RC1_RELEASE_DATA) == 0, 1716 ("%s: header present but data release", __func__)); 1717 1718 if ((len = CAS_GET(word2, CAS_RC2_HDR_SIZE)) != 0) { 1719 idx = CAS_GET(word2, CAS_RC2_HDR_INDEX); 1720 off = CAS_GET(word2, CAS_RC2_HDR_OFF); 1721 #ifdef CAS_DEBUG 1722 CTR4(KTR_CAS, "%s: hdr at idx %d, off %d, len %d", 1723 __func__, idx, off, len); 1724 #endif 1725 rxds = &sc->sc_rxdsoft[idx]; 1726 MGETHDR(m, M_NOWAIT, MT_DATA); 1727 if (m != NULL) { 1728 refcount_acquire(&rxds->rxds_refcount); 1729 bus_dmamap_sync(sc->sc_rdmatag, 1730 rxds->rxds_dmamap, BUS_DMASYNC_POSTREAD); 1731 #if __FreeBSD_version < 800016 1732 MEXTADD(m, (caddr_t)rxds->rxds_buf + 1733 off * 256 + ETHER_ALIGN, len, cas_free, 1734 rxds, M_RDONLY, EXT_NET_DRV); 1735 #else 1736 MEXTADD(m, (caddr_t)rxds->rxds_buf + 1737 off * 256 + ETHER_ALIGN, len, cas_free, 1738 sc, (void *)(uintptr_t)idx, 1739 M_RDONLY, EXT_NET_DRV); 1740 #endif 1741 if ((m->m_flags & M_EXT) == 0) { 1742 m_freem(m); 1743 m = NULL; 1744 } 1745 } 1746 if (m != NULL) { 1747 m->m_pkthdr.rcvif = ifp; 1748 m->m_pkthdr.len = m->m_len = len; 1749 ifp->if_ipackets++; 1750 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 1751 cas_rxcksum(m, CAS_GET(word4, 1752 CAS_RC4_TCP_CSUM)); 1753 /* Pass it on. */ 1754 CAS_UNLOCK(sc); 1755 (*ifp->if_input)(ifp, m); 1756 CAS_LOCK(sc); 1757 } else 1758 ifp->if_iqdrops++; 1759 1760 if ((word1 & CAS_RC1_RELEASE_HDR) != 0 && 1761 refcount_release(&rxds->rxds_refcount) != 0) 1762 cas_add_rxdesc(sc, idx); 1763 } else if ((len = CAS_GET(word1, CAS_RC1_DATA_SIZE)) != 0) { 1764 idx = CAS_GET(word1, CAS_RC1_DATA_INDEX); 1765 off = CAS_GET(word1, CAS_RC1_DATA_OFF); 1766 #ifdef CAS_DEBUG 1767 CTR4(KTR_CAS, "%s: data at idx %d, off %d, len %d", 1768 __func__, idx, off, len); 1769 #endif 1770 rxds = &sc->sc_rxdsoft[idx]; 1771 MGETHDR(m, M_NOWAIT, MT_DATA); 1772 if (m != NULL) { 1773 refcount_acquire(&rxds->rxds_refcount); 1774 off += ETHER_ALIGN; 1775 m->m_len = min(CAS_PAGE_SIZE - off, len); 1776 bus_dmamap_sync(sc->sc_rdmatag, 1777 rxds->rxds_dmamap, BUS_DMASYNC_POSTREAD); 1778 #if __FreeBSD_version < 800016 1779 MEXTADD(m, (caddr_t)rxds->rxds_buf + off, 1780 m->m_len, cas_free, rxds, M_RDONLY, 1781 EXT_NET_DRV); 1782 #else 1783 MEXTADD(m, (caddr_t)rxds->rxds_buf + off, 1784 m->m_len, cas_free, sc, 1785 (void *)(uintptr_t)idx, M_RDONLY, 1786 EXT_NET_DRV); 1787 #endif 1788 if ((m->m_flags & M_EXT) == 0) { 1789 m_freem(m); 1790 m = NULL; 1791 } 1792 } 1793 idx2 = 0; 1794 m2 = NULL; 1795 rxds2 = NULL; 1796 if ((word1 & CAS_RC1_SPLIT_PKT) != 0) { 1797 KASSERT((word1 & CAS_RC1_RELEASE_NEXT) != 0, 1798 ("%s: split but no release next", 1799 __func__)); 1800 1801 idx2 = CAS_GET(word2, CAS_RC2_NEXT_INDEX); 1802 #ifdef CAS_DEBUG 1803 CTR2(KTR_CAS, "%s: split at idx %d", 1804 __func__, idx2); 1805 #endif 1806 rxds2 = &sc->sc_rxdsoft[idx2]; 1807 if (m != NULL) { 1808 MGET(m2, M_NOWAIT, MT_DATA); 1809 if (m2 != NULL) { 1810 refcount_acquire( 1811 &rxds2->rxds_refcount); 1812 m2->m_len = len - m->m_len; 1813 bus_dmamap_sync( 1814 sc->sc_rdmatag, 1815 rxds2->rxds_dmamap, 1816 BUS_DMASYNC_POSTREAD); 1817 #if __FreeBSD_version < 800016 1818 MEXTADD(m2, 1819 (caddr_t)rxds2->rxds_buf, 1820 m2->m_len, cas_free, 1821 rxds2, M_RDONLY, 1822 EXT_NET_DRV); 1823 #else 1824 MEXTADD(m2, 1825 (caddr_t)rxds2->rxds_buf, 1826 m2->m_len, cas_free, sc, 1827 (void *)(uintptr_t)idx2, 1828 M_RDONLY, EXT_NET_DRV); 1829 #endif 1830 if ((m2->m_flags & M_EXT) == 1831 0) { 1832 m_freem(m2); 1833 m2 = NULL; 1834 } 1835 } 1836 } 1837 if (m2 != NULL) 1838 m->m_next = m2; 1839 else if (m != NULL) { 1840 m_freem(m); 1841 m = NULL; 1842 } 1843 } 1844 if (m != NULL) { 1845 m->m_pkthdr.rcvif = ifp; 1846 m->m_pkthdr.len = len; 1847 ifp->if_ipackets++; 1848 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 1849 cas_rxcksum(m, CAS_GET(word4, 1850 CAS_RC4_TCP_CSUM)); 1851 /* Pass it on. */ 1852 CAS_UNLOCK(sc); 1853 (*ifp->if_input)(ifp, m); 1854 CAS_LOCK(sc); 1855 } else 1856 ifp->if_iqdrops++; 1857 1858 if ((word1 & CAS_RC1_RELEASE_DATA) != 0 && 1859 refcount_release(&rxds->rxds_refcount) != 0) 1860 cas_add_rxdesc(sc, idx); 1861 if ((word1 & CAS_RC1_SPLIT_PKT) != 0 && 1862 refcount_release(&rxds2->rxds_refcount) != 0) 1863 cas_add_rxdesc(sc, idx2); 1864 } 1865 1866 skip = CAS_GET(word1, CAS_RC1_SKIP); 1867 1868 skip: 1869 cas_rxcompinit(&sc->sc_rxcomps[sc->sc_rxcptr]); 1870 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 1871 break; 1872 } 1873 CAS_CDSYNC(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1874 CAS_WRITE_4(sc, CAS_RX_COMP_TAIL, sc->sc_rxcptr); 1875 1876 #undef PRINTWORD 1877 #undef SKIPASSERT 1878 #undef WORDTOH 1879 1880 #ifdef CAS_DEBUG 1881 CTR4(KTR_CAS, "%s: done sc->sc_rxcptr %d, sc->sc_rxdptr %d, head %d", 1882 __func__, sc->sc_rxcptr, sc->sc_rxdptr, 1883 CAS_READ_4(sc, CAS_RX_COMP_HEAD)); 1884 #endif 1885 } 1886 1887 static void 1888 cas_free(void *arg1, void *arg2) 1889 { 1890 struct cas_rxdsoft *rxds; 1891 struct cas_softc *sc; 1892 u_int idx, locked; 1893 1894 #if __FreeBSD_version < 800016 1895 rxds = arg2; 1896 sc = rxds->rxds_sc; 1897 idx = rxds->rxds_idx; 1898 #else 1899 sc = arg1; 1900 idx = (uintptr_t)arg2; 1901 rxds = &sc->sc_rxdsoft[idx]; 1902 #endif 1903 if (refcount_release(&rxds->rxds_refcount) == 0) 1904 return; 1905 1906 /* 1907 * NB: this function can be called via m_freem(9) within 1908 * this driver! 1909 */ 1910 if ((locked = CAS_LOCK_OWNED(sc)) == 0) 1911 CAS_LOCK(sc); 1912 cas_add_rxdesc(sc, idx); 1913 if (locked == 0) 1914 CAS_UNLOCK(sc); 1915 } 1916 1917 static inline void 1918 cas_add_rxdesc(struct cas_softc *sc, u_int idx) 1919 { 1920 1921 CAS_LOCK_ASSERT(sc, MA_OWNED); 1922 1923 bus_dmamap_sync(sc->sc_rdmatag, sc->sc_rxdsoft[idx].rxds_dmamap, 1924 BUS_DMASYNC_PREREAD); 1925 CAS_UPDATE_RXDESC(sc, sc->sc_rxdptr, idx); 1926 sc->sc_rxdptr = CAS_NEXTRXDESC(sc->sc_rxdptr); 1927 1928 /* 1929 * Update the RX kick register. This register has to point to the 1930 * descriptor after the last valid one (before the current batch) 1931 * and for optimum performance should be incremented in multiples 1932 * of 4 (the DMA engine fetches/updates descriptors in batches of 4). 1933 */ 1934 if ((sc->sc_rxdptr % 4) == 0) { 1935 CAS_CDSYNC(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1936 CAS_WRITE_4(sc, CAS_RX_KICK, 1937 (sc->sc_rxdptr + CAS_NRXDESC - 4) & CAS_NRXDESC_MASK); 1938 } 1939 } 1940 1941 static void 1942 cas_eint(struct cas_softc *sc, u_int status) 1943 { 1944 struct ifnet *ifp = sc->sc_ifp; 1945 1946 CAS_LOCK_ASSERT(sc, MA_OWNED); 1947 1948 ifp->if_ierrors++; 1949 1950 device_printf(sc->sc_dev, "%s: status 0x%x", __func__, status); 1951 if ((status & CAS_INTR_PCI_ERROR_INT) != 0) { 1952 status = CAS_READ_4(sc, CAS_ERROR_STATUS); 1953 printf(", PCI bus error 0x%x", status); 1954 if ((status & CAS_ERROR_OTHER) != 0) { 1955 status = pci_read_config(sc->sc_dev, PCIR_STATUS, 2); 1956 printf(", PCI status 0x%x", status); 1957 pci_write_config(sc->sc_dev, PCIR_STATUS, status, 2); 1958 } 1959 } 1960 printf("\n"); 1961 1962 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1963 cas_init_locked(sc); 1964 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1965 taskqueue_enqueue(sc->sc_tq, &sc->sc_tx_task); 1966 } 1967 1968 static int 1969 cas_intr(void *v) 1970 { 1971 struct cas_softc *sc = v; 1972 1973 if (__predict_false((CAS_READ_4(sc, CAS_STATUS_ALIAS) & 1974 CAS_INTR_SUMMARY) == 0)) 1975 return (FILTER_STRAY); 1976 1977 /* Disable interrupts. */ 1978 CAS_WRITE_4(sc, CAS_INTMASK, 0xffffffff); 1979 taskqueue_enqueue(sc->sc_tq, &sc->sc_intr_task); 1980 1981 return (FILTER_HANDLED); 1982 } 1983 1984 static void 1985 cas_intr_task(void *arg, int pending __unused) 1986 { 1987 struct cas_softc *sc = arg; 1988 struct ifnet *ifp = sc->sc_ifp; 1989 uint32_t status, status2; 1990 1991 CAS_LOCK_ASSERT(sc, MA_NOTOWNED); 1992 1993 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 1994 return; 1995 1996 status = CAS_READ_4(sc, CAS_STATUS); 1997 if (__predict_false((status & CAS_INTR_SUMMARY) == 0)) 1998 goto done; 1999 2000 CAS_LOCK(sc); 2001 #ifdef CAS_DEBUG 2002 CTR4(KTR_CAS, "%s: %s: cplt %x, status %x", 2003 device_get_name(sc->sc_dev), __func__, 2004 (status >> CAS_STATUS_TX_COMP3_SHFT), (u_int)status); 2005 2006 /* 2007 * PCS interrupts must be cleared, otherwise no traffic is passed! 2008 */ 2009 if ((status & CAS_INTR_PCS_INT) != 0) { 2010 status2 = 2011 CAS_READ_4(sc, CAS_PCS_INTR_STATUS) | 2012 CAS_READ_4(sc, CAS_PCS_INTR_STATUS); 2013 if ((status2 & CAS_PCS_INTR_LINK) != 0) 2014 device_printf(sc->sc_dev, 2015 "%s: PCS link status changed\n", __func__); 2016 } 2017 if ((status & CAS_MAC_CTRL_STATUS) != 0) { 2018 status2 = CAS_READ_4(sc, CAS_MAC_CTRL_STATUS); 2019 if ((status2 & CAS_MAC_CTRL_PAUSE) != 0) 2020 device_printf(sc->sc_dev, 2021 "%s: PAUSE received (PAUSE time %d slots)\n", 2022 __func__, 2023 (status2 & CAS_MAC_CTRL_STATUS_PT_MASK) >> 2024 CAS_MAC_CTRL_STATUS_PT_SHFT); 2025 if ((status2 & CAS_MAC_CTRL_PAUSE) != 0) 2026 device_printf(sc->sc_dev, 2027 "%s: transited to PAUSE state\n", __func__); 2028 if ((status2 & CAS_MAC_CTRL_NON_PAUSE) != 0) 2029 device_printf(sc->sc_dev, 2030 "%s: transited to non-PAUSE state\n", __func__); 2031 } 2032 if ((status & CAS_INTR_MIF) != 0) 2033 device_printf(sc->sc_dev, "%s: MIF interrupt\n", __func__); 2034 #endif 2035 2036 if (__predict_false((status & 2037 (CAS_INTR_TX_TAG_ERR | CAS_INTR_RX_TAG_ERR | 2038 CAS_INTR_RX_LEN_MMATCH | CAS_INTR_PCI_ERROR_INT)) != 0)) { 2039 cas_eint(sc, status); 2040 CAS_UNLOCK(sc); 2041 return; 2042 } 2043 2044 if (__predict_false(status & CAS_INTR_TX_MAC_INT)) { 2045 status2 = CAS_READ_4(sc, CAS_MAC_TX_STATUS); 2046 if ((status2 & 2047 (CAS_MAC_TX_UNDERRUN | CAS_MAC_TX_MAX_PKT_ERR)) != 0) 2048 ifp->if_oerrors++; 2049 else if ((status2 & ~CAS_MAC_TX_FRAME_XMTD) != 0) 2050 device_printf(sc->sc_dev, 2051 "MAC TX fault, status %x\n", status2); 2052 } 2053 2054 if (__predict_false(status & CAS_INTR_RX_MAC_INT)) { 2055 status2 = CAS_READ_4(sc, CAS_MAC_RX_STATUS); 2056 if ((status2 & CAS_MAC_RX_OVERFLOW) != 0) 2057 ifp->if_ierrors++; 2058 else if ((status2 & ~CAS_MAC_RX_FRAME_RCVD) != 0) 2059 device_printf(sc->sc_dev, 2060 "MAC RX fault, status %x\n", status2); 2061 } 2062 2063 if ((status & 2064 (CAS_INTR_RX_DONE | CAS_INTR_RX_BUF_NA | CAS_INTR_RX_COMP_FULL | 2065 CAS_INTR_RX_BUF_AEMPTY | CAS_INTR_RX_COMP_AFULL)) != 0) { 2066 cas_rint(sc); 2067 #ifdef CAS_DEBUG 2068 if (__predict_false((status & 2069 (CAS_INTR_RX_BUF_NA | CAS_INTR_RX_COMP_FULL | 2070 CAS_INTR_RX_BUF_AEMPTY | CAS_INTR_RX_COMP_AFULL)) != 0)) 2071 device_printf(sc->sc_dev, 2072 "RX fault, status %x\n", status); 2073 #endif 2074 } 2075 2076 if ((status & 2077 (CAS_INTR_TX_INT_ME | CAS_INTR_TX_ALL | CAS_INTR_TX_DONE)) != 0) 2078 cas_tint(sc); 2079 2080 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 2081 CAS_UNLOCK(sc); 2082 return; 2083 } else if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2084 taskqueue_enqueue(sc->sc_tq, &sc->sc_tx_task); 2085 CAS_UNLOCK(sc); 2086 2087 status = CAS_READ_4(sc, CAS_STATUS_ALIAS); 2088 if (__predict_false((status & CAS_INTR_SUMMARY) != 0)) { 2089 taskqueue_enqueue(sc->sc_tq, &sc->sc_intr_task); 2090 return; 2091 } 2092 2093 done: 2094 /* Re-enable interrupts. */ 2095 CAS_WRITE_4(sc, CAS_INTMASK, 2096 ~(CAS_INTR_TX_INT_ME | CAS_INTR_TX_TAG_ERR | 2097 CAS_INTR_RX_DONE | CAS_INTR_RX_BUF_NA | CAS_INTR_RX_TAG_ERR | 2098 CAS_INTR_RX_COMP_FULL | CAS_INTR_RX_BUF_AEMPTY | 2099 CAS_INTR_RX_COMP_AFULL | CAS_INTR_RX_LEN_MMATCH | 2100 CAS_INTR_PCI_ERROR_INT 2101 #ifdef CAS_DEBUG 2102 | CAS_INTR_PCS_INT | CAS_INTR_MIF 2103 #endif 2104 )); 2105 } 2106 2107 static void 2108 cas_watchdog(struct cas_softc *sc) 2109 { 2110 struct ifnet *ifp = sc->sc_ifp; 2111 2112 CAS_LOCK_ASSERT(sc, MA_OWNED); 2113 2114 #ifdef CAS_DEBUG 2115 CTR4(KTR_CAS, 2116 "%s: CAS_RX_CONF %x CAS_MAC_RX_STATUS %x CAS_MAC_RX_CONF %x", 2117 __func__, CAS_READ_4(sc, CAS_RX_CONF), 2118 CAS_READ_4(sc, CAS_MAC_RX_STATUS), 2119 CAS_READ_4(sc, CAS_MAC_RX_CONF)); 2120 CTR4(KTR_CAS, 2121 "%s: CAS_TX_CONF %x CAS_MAC_TX_STATUS %x CAS_MAC_TX_CONF %x", 2122 __func__, CAS_READ_4(sc, CAS_TX_CONF), 2123 CAS_READ_4(sc, CAS_MAC_TX_STATUS), 2124 CAS_READ_4(sc, CAS_MAC_TX_CONF)); 2125 #endif 2126 2127 if (sc->sc_wdog_timer == 0 || --sc->sc_wdog_timer != 0) 2128 return; 2129 2130 if ((sc->sc_flags & CAS_LINK) != 0) 2131 device_printf(sc->sc_dev, "device timeout\n"); 2132 else if (bootverbose) 2133 device_printf(sc->sc_dev, "device timeout (no link)\n"); 2134 ++ifp->if_oerrors; 2135 2136 /* Try to get more packets going. */ 2137 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2138 cas_init_locked(sc); 2139 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2140 taskqueue_enqueue(sc->sc_tq, &sc->sc_tx_task); 2141 } 2142 2143 static void 2144 cas_mifinit(struct cas_softc *sc) 2145 { 2146 2147 /* Configure the MIF in frame mode. */ 2148 CAS_WRITE_4(sc, CAS_MIF_CONF, 2149 CAS_READ_4(sc, CAS_MIF_CONF) & ~CAS_MIF_CONF_BB_MODE); 2150 CAS_BARRIER(sc, CAS_MIF_CONF, 4, 2151 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 2152 } 2153 2154 /* 2155 * MII interface 2156 * 2157 * The MII interface supports at least three different operating modes: 2158 * 2159 * Bitbang mode is implemented using data, clock and output enable registers. 2160 * 2161 * Frame mode is implemented by loading a complete frame into the frame 2162 * register and polling the valid bit for completion. 2163 * 2164 * Polling mode uses the frame register but completion is indicated by 2165 * an interrupt. 2166 * 2167 */ 2168 static int 2169 cas_mii_readreg(device_t dev, int phy, int reg) 2170 { 2171 struct cas_softc *sc; 2172 int n; 2173 uint32_t v; 2174 2175 #ifdef CAS_DEBUG_PHY 2176 printf("%s: phy %d reg %d\n", __func__, phy, reg); 2177 #endif 2178 2179 sc = device_get_softc(dev); 2180 if ((sc->sc_flags & CAS_SERDES) != 0) { 2181 switch (reg) { 2182 case MII_BMCR: 2183 reg = CAS_PCS_CTRL; 2184 break; 2185 case MII_BMSR: 2186 reg = CAS_PCS_STATUS; 2187 break; 2188 case MII_PHYIDR1: 2189 case MII_PHYIDR2: 2190 return (0); 2191 case MII_ANAR: 2192 reg = CAS_PCS_ANAR; 2193 break; 2194 case MII_ANLPAR: 2195 reg = CAS_PCS_ANLPAR; 2196 break; 2197 case MII_EXTSR: 2198 return (EXTSR_1000XFDX | EXTSR_1000XHDX); 2199 default: 2200 device_printf(sc->sc_dev, 2201 "%s: unhandled register %d\n", __func__, reg); 2202 return (0); 2203 } 2204 return (CAS_READ_4(sc, reg)); 2205 } 2206 2207 /* Construct the frame command. */ 2208 v = CAS_MIF_FRAME_READ | 2209 (phy << CAS_MIF_FRAME_PHY_SHFT) | 2210 (reg << CAS_MIF_FRAME_REG_SHFT); 2211 2212 CAS_WRITE_4(sc, CAS_MIF_FRAME, v); 2213 CAS_BARRIER(sc, CAS_MIF_FRAME, 4, 2214 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 2215 for (n = 0; n < 100; n++) { 2216 DELAY(1); 2217 v = CAS_READ_4(sc, CAS_MIF_FRAME); 2218 if (v & CAS_MIF_FRAME_TA_LSB) 2219 return (v & CAS_MIF_FRAME_DATA); 2220 } 2221 2222 device_printf(sc->sc_dev, "%s: timed out\n", __func__); 2223 return (0); 2224 } 2225 2226 static int 2227 cas_mii_writereg(device_t dev, int phy, int reg, int val) 2228 { 2229 struct cas_softc *sc; 2230 int n; 2231 uint32_t v; 2232 2233 #ifdef CAS_DEBUG_PHY 2234 printf("%s: phy %d reg %d val %x\n", phy, reg, val, __func__); 2235 #endif 2236 2237 sc = device_get_softc(dev); 2238 if ((sc->sc_flags & CAS_SERDES) != 0) { 2239 switch (reg) { 2240 case MII_BMSR: 2241 reg = CAS_PCS_STATUS; 2242 break; 2243 case MII_BMCR: 2244 reg = CAS_PCS_CTRL; 2245 if ((val & CAS_PCS_CTRL_RESET) == 0) 2246 break; 2247 CAS_WRITE_4(sc, CAS_PCS_CTRL, val); 2248 CAS_BARRIER(sc, CAS_PCS_CTRL, 4, 2249 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 2250 if (!cas_bitwait(sc, CAS_PCS_CTRL, 2251 CAS_PCS_CTRL_RESET, 0)) 2252 device_printf(sc->sc_dev, 2253 "cannot reset PCS\n"); 2254 /* FALLTHROUGH */ 2255 case MII_ANAR: 2256 CAS_WRITE_4(sc, CAS_PCS_CONF, 0); 2257 CAS_BARRIER(sc, CAS_PCS_CONF, 4, 2258 BUS_SPACE_BARRIER_WRITE); 2259 CAS_WRITE_4(sc, CAS_PCS_ANAR, val); 2260 CAS_BARRIER(sc, CAS_PCS_ANAR, 4, 2261 BUS_SPACE_BARRIER_WRITE); 2262 CAS_WRITE_4(sc, CAS_PCS_SERDES_CTRL, 2263 CAS_PCS_SERDES_CTRL_ESD); 2264 CAS_BARRIER(sc, CAS_PCS_CONF, 4, 2265 BUS_SPACE_BARRIER_WRITE); 2266 CAS_WRITE_4(sc, CAS_PCS_CONF, 2267 CAS_PCS_CONF_EN); 2268 CAS_BARRIER(sc, CAS_PCS_CONF, 4, 2269 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 2270 return (0); 2271 case MII_ANLPAR: 2272 reg = CAS_PCS_ANLPAR; 2273 break; 2274 default: 2275 device_printf(sc->sc_dev, 2276 "%s: unhandled register %d\n", __func__, reg); 2277 return (0); 2278 } 2279 CAS_WRITE_4(sc, reg, val); 2280 CAS_BARRIER(sc, reg, 4, 2281 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 2282 return (0); 2283 } 2284 2285 /* Construct the frame command. */ 2286 v = CAS_MIF_FRAME_WRITE | 2287 (phy << CAS_MIF_FRAME_PHY_SHFT) | 2288 (reg << CAS_MIF_FRAME_REG_SHFT) | 2289 (val & CAS_MIF_FRAME_DATA); 2290 2291 CAS_WRITE_4(sc, CAS_MIF_FRAME, v); 2292 CAS_BARRIER(sc, CAS_MIF_FRAME, 4, 2293 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 2294 for (n = 0; n < 100; n++) { 2295 DELAY(1); 2296 v = CAS_READ_4(sc, CAS_MIF_FRAME); 2297 if (v & CAS_MIF_FRAME_TA_LSB) 2298 return (1); 2299 } 2300 2301 device_printf(sc->sc_dev, "%s: timed out\n", __func__); 2302 return (0); 2303 } 2304 2305 static void 2306 cas_mii_statchg(device_t dev) 2307 { 2308 struct cas_softc *sc; 2309 struct ifnet *ifp; 2310 int gigabit; 2311 uint32_t rxcfg, txcfg, v; 2312 2313 sc = device_get_softc(dev); 2314 ifp = sc->sc_ifp; 2315 2316 CAS_LOCK_ASSERT(sc, MA_OWNED); 2317 2318 #ifdef CAS_DEBUG 2319 if ((ifp->if_flags & IFF_DEBUG) != 0) 2320 device_printf(sc->sc_dev, "%s: status changen", __func__); 2321 #endif 2322 2323 if ((sc->sc_mii->mii_media_status & IFM_ACTIVE) != 0 && 2324 IFM_SUBTYPE(sc->sc_mii->mii_media_active) != IFM_NONE) 2325 sc->sc_flags |= CAS_LINK; 2326 else 2327 sc->sc_flags &= ~CAS_LINK; 2328 2329 switch (IFM_SUBTYPE(sc->sc_mii->mii_media_active)) { 2330 case IFM_1000_SX: 2331 case IFM_1000_LX: 2332 case IFM_1000_CX: 2333 case IFM_1000_T: 2334 gigabit = 1; 2335 break; 2336 default: 2337 gigabit = 0; 2338 } 2339 2340 /* 2341 * The configuration done here corresponds to the steps F) and 2342 * G) and as far as enabling of RX and TX MAC goes also step H) 2343 * of the initialization sequence outlined in section 11.2.1 of 2344 * the Cassini+ ASIC Specification. 2345 */ 2346 2347 rxcfg = sc->sc_mac_rxcfg; 2348 rxcfg &= ~CAS_MAC_RX_CONF_CARR; 2349 txcfg = CAS_MAC_TX_CONF_EN_IPG0 | CAS_MAC_TX_CONF_NGU | 2350 CAS_MAC_TX_CONF_NGUL; 2351 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) != 0) 2352 txcfg |= CAS_MAC_TX_CONF_ICARR | CAS_MAC_TX_CONF_ICOLLIS; 2353 else if (gigabit != 0) { 2354 rxcfg |= CAS_MAC_RX_CONF_CARR; 2355 txcfg |= CAS_MAC_TX_CONF_CARR; 2356 } 2357 (void)cas_disable_tx(sc); 2358 CAS_WRITE_4(sc, CAS_MAC_TX_CONF, txcfg); 2359 (void)cas_disable_rx(sc); 2360 CAS_WRITE_4(sc, CAS_MAC_RX_CONF, rxcfg); 2361 2362 v = CAS_READ_4(sc, CAS_MAC_CTRL_CONF) & 2363 ~(CAS_MAC_CTRL_CONF_TXP | CAS_MAC_CTRL_CONF_RXP); 2364 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & 2365 IFM_ETH_RXPAUSE) != 0) 2366 v |= CAS_MAC_CTRL_CONF_RXP; 2367 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & 2368 IFM_ETH_TXPAUSE) != 0) 2369 v |= CAS_MAC_CTRL_CONF_TXP; 2370 CAS_WRITE_4(sc, CAS_MAC_CTRL_CONF, v); 2371 2372 /* 2373 * All supported chips have a bug causing incorrect checksum 2374 * to be calculated when letting them strip the FCS in half- 2375 * duplex mode. In theory we could disable FCS stripping and 2376 * manually adjust the checksum accordingly. It seems to make 2377 * more sense to optimze for the common case and just disable 2378 * hardware checksumming in half-duplex mode though. 2379 */ 2380 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) == 0) { 2381 ifp->if_capenable &= ~IFCAP_HWCSUM; 2382 ifp->if_hwassist = 0; 2383 } else if ((sc->sc_flags & CAS_NO_CSUM) == 0) { 2384 ifp->if_capenable = ifp->if_capabilities; 2385 ifp->if_hwassist = CAS_CSUM_FEATURES; 2386 } 2387 2388 if (sc->sc_variant == CAS_SATURN) { 2389 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) == 0) 2390 /* silicon bug workaround */ 2391 CAS_WRITE_4(sc, CAS_MAC_PREAMBLE_LEN, 0x41); 2392 else 2393 CAS_WRITE_4(sc, CAS_MAC_PREAMBLE_LEN, 0x7); 2394 } 2395 2396 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) == 0 && 2397 gigabit != 0) 2398 CAS_WRITE_4(sc, CAS_MAC_SLOT_TIME, 2399 CAS_MAC_SLOT_TIME_CARR); 2400 else 2401 CAS_WRITE_4(sc, CAS_MAC_SLOT_TIME, 2402 CAS_MAC_SLOT_TIME_NORM); 2403 2404 /* XIF Configuration */ 2405 v = CAS_MAC_XIF_CONF_TX_OE | CAS_MAC_XIF_CONF_LNKLED; 2406 if ((sc->sc_flags & CAS_SERDES) == 0) { 2407 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) == 0) 2408 v |= CAS_MAC_XIF_CONF_NOECHO; 2409 v |= CAS_MAC_XIF_CONF_BUF_OE; 2410 } 2411 if (gigabit != 0) 2412 v |= CAS_MAC_XIF_CONF_GMII; 2413 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) != 0) 2414 v |= CAS_MAC_XIF_CONF_FDXLED; 2415 CAS_WRITE_4(sc, CAS_MAC_XIF_CONF, v); 2416 2417 sc->sc_mac_rxcfg = rxcfg; 2418 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && 2419 (sc->sc_flags & CAS_LINK) != 0) { 2420 CAS_WRITE_4(sc, CAS_MAC_TX_CONF, 2421 txcfg | CAS_MAC_TX_CONF_EN); 2422 CAS_WRITE_4(sc, CAS_MAC_RX_CONF, 2423 rxcfg | CAS_MAC_RX_CONF_EN); 2424 } 2425 } 2426 2427 static int 2428 cas_mediachange(struct ifnet *ifp) 2429 { 2430 struct cas_softc *sc = ifp->if_softc; 2431 int error; 2432 2433 /* XXX add support for serial media. */ 2434 2435 CAS_LOCK(sc); 2436 error = mii_mediachg(sc->sc_mii); 2437 CAS_UNLOCK(sc); 2438 return (error); 2439 } 2440 2441 static void 2442 cas_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 2443 { 2444 struct cas_softc *sc = ifp->if_softc; 2445 2446 CAS_LOCK(sc); 2447 if ((ifp->if_flags & IFF_UP) == 0) { 2448 CAS_UNLOCK(sc); 2449 return; 2450 } 2451 2452 mii_pollstat(sc->sc_mii); 2453 ifmr->ifm_active = sc->sc_mii->mii_media_active; 2454 ifmr->ifm_status = sc->sc_mii->mii_media_status; 2455 CAS_UNLOCK(sc); 2456 } 2457 2458 static int 2459 cas_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 2460 { 2461 struct cas_softc *sc = ifp->if_softc; 2462 struct ifreq *ifr = (struct ifreq *)data; 2463 int error; 2464 2465 error = 0; 2466 switch (cmd) { 2467 case SIOCSIFFLAGS: 2468 CAS_LOCK(sc); 2469 if ((ifp->if_flags & IFF_UP) != 0) { 2470 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && 2471 ((ifp->if_flags ^ sc->sc_ifflags) & 2472 (IFF_ALLMULTI | IFF_PROMISC)) != 0) 2473 cas_setladrf(sc); 2474 else 2475 cas_init_locked(sc); 2476 } else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2477 cas_stop(ifp); 2478 sc->sc_ifflags = ifp->if_flags; 2479 CAS_UNLOCK(sc); 2480 break; 2481 case SIOCSIFCAP: 2482 CAS_LOCK(sc); 2483 if ((sc->sc_flags & CAS_NO_CSUM) != 0) { 2484 error = EINVAL; 2485 CAS_UNLOCK(sc); 2486 break; 2487 } 2488 ifp->if_capenable = ifr->ifr_reqcap; 2489 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 2490 ifp->if_hwassist = CAS_CSUM_FEATURES; 2491 else 2492 ifp->if_hwassist = 0; 2493 CAS_UNLOCK(sc); 2494 break; 2495 case SIOCADDMULTI: 2496 case SIOCDELMULTI: 2497 CAS_LOCK(sc); 2498 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2499 cas_setladrf(sc); 2500 CAS_UNLOCK(sc); 2501 break; 2502 case SIOCSIFMTU: 2503 if ((ifr->ifr_mtu < ETHERMIN) || 2504 (ifr->ifr_mtu > ETHERMTU_JUMBO)) 2505 error = EINVAL; 2506 else 2507 ifp->if_mtu = ifr->ifr_mtu; 2508 break; 2509 case SIOCGIFMEDIA: 2510 case SIOCSIFMEDIA: 2511 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii->mii_media, cmd); 2512 break; 2513 default: 2514 error = ether_ioctl(ifp, cmd, data); 2515 break; 2516 } 2517 2518 return (error); 2519 } 2520 2521 static void 2522 cas_setladrf(struct cas_softc *sc) 2523 { 2524 struct ifnet *ifp = sc->sc_ifp; 2525 struct ifmultiaddr *inm; 2526 int i; 2527 uint32_t hash[16]; 2528 uint32_t crc, v; 2529 2530 CAS_LOCK_ASSERT(sc, MA_OWNED); 2531 2532 /* 2533 * Turn off the RX MAC and the hash filter as required by the Sun 2534 * Cassini programming restrictions. 2535 */ 2536 v = sc->sc_mac_rxcfg & ~(CAS_MAC_RX_CONF_HFILTER | 2537 CAS_MAC_RX_CONF_EN); 2538 CAS_WRITE_4(sc, CAS_MAC_RX_CONF, v); 2539 CAS_BARRIER(sc, CAS_MAC_RX_CONF, 4, 2540 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 2541 if (!cas_bitwait(sc, CAS_MAC_RX_CONF, CAS_MAC_RX_CONF_HFILTER | 2542 CAS_MAC_RX_CONF_EN, 0)) 2543 device_printf(sc->sc_dev, 2544 "cannot disable RX MAC or hash filter\n"); 2545 2546 v &= ~(CAS_MAC_RX_CONF_PROMISC | CAS_MAC_RX_CONF_PGRP); 2547 if ((ifp->if_flags & IFF_PROMISC) != 0) { 2548 v |= CAS_MAC_RX_CONF_PROMISC; 2549 goto chipit; 2550 } 2551 if ((ifp->if_flags & IFF_ALLMULTI) != 0) { 2552 v |= CAS_MAC_RX_CONF_PGRP; 2553 goto chipit; 2554 } 2555 2556 /* 2557 * Set up multicast address filter by passing all multicast 2558 * addresses through a crc generator, and then using the high 2559 * order 8 bits as an index into the 256 bit logical address 2560 * filter. The high order 4 bits selects the word, while the 2561 * other 4 bits select the bit within the word (where bit 0 2562 * is the MSB). 2563 */ 2564 2565 /* Clear the hash table. */ 2566 memset(hash, 0, sizeof(hash)); 2567 2568 if_maddr_rlock(ifp); 2569 TAILQ_FOREACH(inm, &ifp->if_multiaddrs, ifma_link) { 2570 if (inm->ifma_addr->sa_family != AF_LINK) 2571 continue; 2572 crc = ether_crc32_le(LLADDR((struct sockaddr_dl *) 2573 inm->ifma_addr), ETHER_ADDR_LEN); 2574 2575 /* We just want the 8 most significant bits. */ 2576 crc >>= 24; 2577 2578 /* Set the corresponding bit in the filter. */ 2579 hash[crc >> 4] |= 1 << (15 - (crc & 15)); 2580 } 2581 if_maddr_runlock(ifp); 2582 2583 v |= CAS_MAC_RX_CONF_HFILTER; 2584 2585 /* Now load the hash table into the chip (if we are using it). */ 2586 for (i = 0; i < 16; i++) 2587 CAS_WRITE_4(sc, 2588 CAS_MAC_HASH0 + i * (CAS_MAC_HASH1 - CAS_MAC_HASH0), 2589 hash[i]); 2590 2591 chipit: 2592 sc->sc_mac_rxcfg = v; 2593 CAS_WRITE_4(sc, CAS_MAC_RX_CONF, v | CAS_MAC_RX_CONF_EN); 2594 } 2595 2596 static int cas_pci_attach(device_t dev); 2597 static int cas_pci_detach(device_t dev); 2598 static int cas_pci_probe(device_t dev); 2599 static int cas_pci_resume(device_t dev); 2600 static int cas_pci_suspend(device_t dev); 2601 2602 static device_method_t cas_pci_methods[] = { 2603 /* Device interface */ 2604 DEVMETHOD(device_probe, cas_pci_probe), 2605 DEVMETHOD(device_attach, cas_pci_attach), 2606 DEVMETHOD(device_detach, cas_pci_detach), 2607 DEVMETHOD(device_suspend, cas_pci_suspend), 2608 DEVMETHOD(device_resume, cas_pci_resume), 2609 /* Use the suspend handler here, it is all that is required. */ 2610 DEVMETHOD(device_shutdown, cas_pci_suspend), 2611 2612 /* MII interface */ 2613 DEVMETHOD(miibus_readreg, cas_mii_readreg), 2614 DEVMETHOD(miibus_writereg, cas_mii_writereg), 2615 DEVMETHOD(miibus_statchg, cas_mii_statchg), 2616 2617 DEVMETHOD_END 2618 }; 2619 2620 static driver_t cas_pci_driver = { 2621 "cas", 2622 cas_pci_methods, 2623 sizeof(struct cas_softc) 2624 }; 2625 2626 DRIVER_MODULE(cas, pci, cas_pci_driver, cas_devclass, 0, 0); 2627 DRIVER_MODULE(miibus, cas, miibus_driver, miibus_devclass, 0, 0); 2628 MODULE_DEPEND(cas, pci, 1, 1, 1); 2629 2630 static const struct cas_pci_dev { 2631 uint32_t cpd_devid; 2632 uint8_t cpd_revid; 2633 int cpd_variant; 2634 const char *cpd_desc; 2635 } cas_pci_devlist[] = { 2636 { 0x0035100b, 0x0, CAS_SATURN, "NS DP83065 Saturn Gigabit Ethernet" }, 2637 { 0xabba108e, 0x10, CAS_CASPLUS, "Sun Cassini+ Gigabit Ethernet" }, 2638 { 0xabba108e, 0x0, CAS_CAS, "Sun Cassini Gigabit Ethernet" }, 2639 { 0, 0, 0, NULL } 2640 }; 2641 2642 static int 2643 cas_pci_probe(device_t dev) 2644 { 2645 int i; 2646 2647 for (i = 0; cas_pci_devlist[i].cpd_desc != NULL; i++) { 2648 if (pci_get_devid(dev) == cas_pci_devlist[i].cpd_devid && 2649 pci_get_revid(dev) >= cas_pci_devlist[i].cpd_revid) { 2650 device_set_desc(dev, cas_pci_devlist[i].cpd_desc); 2651 return (BUS_PROBE_DEFAULT); 2652 } 2653 } 2654 2655 return (ENXIO); 2656 } 2657 2658 static struct resource_spec cas_pci_res_spec[] = { 2659 { SYS_RES_IRQ, 0, RF_SHAREABLE | RF_ACTIVE }, /* CAS_RES_INTR */ 2660 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, /* CAS_RES_MEM */ 2661 { -1, 0 } 2662 }; 2663 2664 #define CAS_LOCAL_MAC_ADDRESS "local-mac-address" 2665 #define CAS_PHY_INTERFACE "phy-interface" 2666 #define CAS_PHY_TYPE "phy-type" 2667 #define CAS_PHY_TYPE_PCS "pcs" 2668 2669 static int 2670 cas_pci_attach(device_t dev) 2671 { 2672 char buf[sizeof(CAS_LOCAL_MAC_ADDRESS)]; 2673 struct cas_softc *sc; 2674 int i; 2675 #if !(defined(__powerpc__) || defined(__sparc64__)) 2676 u_char enaddr[4][ETHER_ADDR_LEN]; 2677 u_int j, k, lma, pcs[4], phy; 2678 #endif 2679 2680 sc = device_get_softc(dev); 2681 sc->sc_variant = CAS_UNKNOWN; 2682 for (i = 0; cas_pci_devlist[i].cpd_desc != NULL; i++) { 2683 if (pci_get_devid(dev) == cas_pci_devlist[i].cpd_devid && 2684 pci_get_revid(dev) >= cas_pci_devlist[i].cpd_revid) { 2685 sc->sc_variant = cas_pci_devlist[i].cpd_variant; 2686 break; 2687 } 2688 } 2689 if (sc->sc_variant == CAS_UNKNOWN) { 2690 device_printf(dev, "unknown adaptor\n"); 2691 return (ENXIO); 2692 } 2693 2694 pci_enable_busmaster(dev); 2695 2696 sc->sc_dev = dev; 2697 if (sc->sc_variant == CAS_CAS && pci_get_devid(dev) < 0x02) 2698 /* Hardware checksumming may hang TX. */ 2699 sc->sc_flags |= CAS_NO_CSUM; 2700 if (sc->sc_variant == CAS_CASPLUS || sc->sc_variant == CAS_SATURN) 2701 sc->sc_flags |= CAS_REG_PLUS; 2702 if (sc->sc_variant == CAS_CAS || 2703 (sc->sc_variant == CAS_CASPLUS && pci_get_revid(dev) < 0x11)) 2704 sc->sc_flags |= CAS_TABORT; 2705 if (bootverbose) 2706 device_printf(dev, "flags=0x%x\n", sc->sc_flags); 2707 2708 if (bus_alloc_resources(dev, cas_pci_res_spec, sc->sc_res)) { 2709 device_printf(dev, "failed to allocate resources\n"); 2710 bus_release_resources(dev, cas_pci_res_spec, sc->sc_res); 2711 return (ENXIO); 2712 } 2713 2714 CAS_LOCK_INIT(sc, device_get_nameunit(dev)); 2715 2716 #if defined(__powerpc__) || defined(__sparc64__) 2717 OF_getetheraddr(dev, sc->sc_enaddr); 2718 if (OF_getprop(ofw_bus_get_node(dev), CAS_PHY_INTERFACE, buf, 2719 sizeof(buf)) > 0 || OF_getprop(ofw_bus_get_node(dev), 2720 CAS_PHY_TYPE, buf, sizeof(buf)) > 0) { 2721 buf[sizeof(buf) - 1] = '\0'; 2722 if (strcmp(buf, CAS_PHY_TYPE_PCS) == 0) 2723 sc->sc_flags |= CAS_SERDES; 2724 } 2725 #else 2726 /* 2727 * Dig out VPD (vital product data) and read the MAC address as well 2728 * as the PHY type. The VPD resides in the PCI Expansion ROM (PCI 2729 * FCode) and can't be accessed via the PCI capability pointer. 2730 * SUNW,pci-ce and SUNW,pci-qge use the Enhanced VPD format described 2731 * in the free US Patent 7149820. 2732 */ 2733 2734 #define PCI_ROMHDR_SIZE 0x1c 2735 #define PCI_ROMHDR_SIG 0x00 2736 #define PCI_ROMHDR_SIG_MAGIC 0xaa55 /* little endian */ 2737 #define PCI_ROMHDR_PTR_DATA 0x18 2738 #define PCI_ROM_SIZE 0x18 2739 #define PCI_ROM_SIG 0x00 2740 #define PCI_ROM_SIG_MAGIC 0x52494350 /* "PCIR", endian */ 2741 /* reversed */ 2742 #define PCI_ROM_VENDOR 0x04 2743 #define PCI_ROM_DEVICE 0x06 2744 #define PCI_ROM_PTR_VPD 0x08 2745 #define PCI_VPDRES_BYTE0 0x00 2746 #define PCI_VPDRES_ISLARGE(x) ((x) & 0x80) 2747 #define PCI_VPDRES_LARGE_NAME(x) ((x) & 0x7f) 2748 #define PCI_VPDRES_LARGE_LEN_LSB 0x01 2749 #define PCI_VPDRES_LARGE_LEN_MSB 0x02 2750 #define PCI_VPDRES_LARGE_SIZE 0x03 2751 #define PCI_VPDRES_TYPE_ID_STRING 0x02 /* large */ 2752 #define PCI_VPDRES_TYPE_VPD 0x10 /* large */ 2753 #define PCI_VPD_KEY0 0x00 2754 #define PCI_VPD_KEY1 0x01 2755 #define PCI_VPD_LEN 0x02 2756 #define PCI_VPD_SIZE 0x03 2757 2758 #define CAS_ROM_READ_1(sc, offs) \ 2759 CAS_READ_1((sc), CAS_PCI_ROM_OFFSET + (offs)) 2760 #define CAS_ROM_READ_2(sc, offs) \ 2761 CAS_READ_2((sc), CAS_PCI_ROM_OFFSET + (offs)) 2762 #define CAS_ROM_READ_4(sc, offs) \ 2763 CAS_READ_4((sc), CAS_PCI_ROM_OFFSET + (offs)) 2764 2765 lma = phy = 0; 2766 memset(enaddr, 0, sizeof(enaddr)); 2767 memset(pcs, 0, sizeof(pcs)); 2768 2769 /* Enable PCI Expansion ROM access. */ 2770 CAS_WRITE_4(sc, CAS_BIM_LDEV_OEN, 2771 CAS_BIM_LDEV_OEN_PAD | CAS_BIM_LDEV_OEN_PROM); 2772 2773 /* Read PCI Expansion ROM header. */ 2774 if (CAS_ROM_READ_2(sc, PCI_ROMHDR_SIG) != PCI_ROMHDR_SIG_MAGIC || 2775 (i = CAS_ROM_READ_2(sc, PCI_ROMHDR_PTR_DATA)) < 2776 PCI_ROMHDR_SIZE) { 2777 device_printf(dev, "unexpected PCI Expansion ROM header\n"); 2778 goto fail_prom; 2779 } 2780 2781 /* Read PCI Expansion ROM data. */ 2782 if (CAS_ROM_READ_4(sc, i + PCI_ROM_SIG) != PCI_ROM_SIG_MAGIC || 2783 CAS_ROM_READ_2(sc, i + PCI_ROM_VENDOR) != pci_get_vendor(dev) || 2784 CAS_ROM_READ_2(sc, i + PCI_ROM_DEVICE) != pci_get_device(dev) || 2785 (j = CAS_ROM_READ_2(sc, i + PCI_ROM_PTR_VPD)) < 2786 i + PCI_ROM_SIZE) { 2787 device_printf(dev, "unexpected PCI Expansion ROM data\n"); 2788 goto fail_prom; 2789 } 2790 2791 /* Read PCI VPD. */ 2792 next: 2793 if (PCI_VPDRES_ISLARGE(CAS_ROM_READ_1(sc, 2794 j + PCI_VPDRES_BYTE0)) == 0) { 2795 device_printf(dev, "no large PCI VPD\n"); 2796 goto fail_prom; 2797 } 2798 2799 i = (CAS_ROM_READ_1(sc, j + PCI_VPDRES_LARGE_LEN_MSB) << 8) | 2800 CAS_ROM_READ_1(sc, j + PCI_VPDRES_LARGE_LEN_LSB); 2801 switch (PCI_VPDRES_LARGE_NAME(CAS_ROM_READ_1(sc, 2802 j + PCI_VPDRES_BYTE0))) { 2803 case PCI_VPDRES_TYPE_ID_STRING: 2804 /* Skip identifier string. */ 2805 j += PCI_VPDRES_LARGE_SIZE + i; 2806 goto next; 2807 case PCI_VPDRES_TYPE_VPD: 2808 for (j += PCI_VPDRES_LARGE_SIZE; i > 0; 2809 i -= PCI_VPD_SIZE + CAS_ROM_READ_1(sc, j + PCI_VPD_LEN), 2810 j += PCI_VPD_SIZE + CAS_ROM_READ_1(sc, j + PCI_VPD_LEN)) { 2811 if (CAS_ROM_READ_1(sc, j + PCI_VPD_KEY0) != 'Z') 2812 /* no Enhanced VPD */ 2813 continue; 2814 if (CAS_ROM_READ_1(sc, j + PCI_VPD_SIZE) != 'I') 2815 /* no instance property */ 2816 continue; 2817 if (CAS_ROM_READ_1(sc, j + PCI_VPD_SIZE + 3) == 'B') { 2818 /* byte array */ 2819 if (CAS_ROM_READ_1(sc, 2820 j + PCI_VPD_SIZE + 4) != ETHER_ADDR_LEN) 2821 continue; 2822 bus_read_region_1(sc->sc_res[CAS_RES_MEM], 2823 CAS_PCI_ROM_OFFSET + j + PCI_VPD_SIZE + 5, 2824 buf, sizeof(buf)); 2825 buf[sizeof(buf) - 1] = '\0'; 2826 if (strcmp(buf, CAS_LOCAL_MAC_ADDRESS) != 0) 2827 continue; 2828 bus_read_region_1(sc->sc_res[CAS_RES_MEM], 2829 CAS_PCI_ROM_OFFSET + j + PCI_VPD_SIZE + 2830 5 + sizeof(CAS_LOCAL_MAC_ADDRESS), 2831 enaddr[lma], sizeof(enaddr[lma])); 2832 lma++; 2833 if (lma == 4 && phy == 4) 2834 break; 2835 } else if (CAS_ROM_READ_1(sc, j + PCI_VPD_SIZE + 3) == 2836 'S') { 2837 /* string */ 2838 if (CAS_ROM_READ_1(sc, 2839 j + PCI_VPD_SIZE + 4) != 2840 sizeof(CAS_PHY_TYPE_PCS)) 2841 continue; 2842 bus_read_region_1(sc->sc_res[CAS_RES_MEM], 2843 CAS_PCI_ROM_OFFSET + j + PCI_VPD_SIZE + 5, 2844 buf, sizeof(buf)); 2845 buf[sizeof(buf) - 1] = '\0'; 2846 if (strcmp(buf, CAS_PHY_INTERFACE) == 0) 2847 k = sizeof(CAS_PHY_INTERFACE); 2848 else if (strcmp(buf, CAS_PHY_TYPE) == 0) 2849 k = sizeof(CAS_PHY_TYPE); 2850 else 2851 continue; 2852 bus_read_region_1(sc->sc_res[CAS_RES_MEM], 2853 CAS_PCI_ROM_OFFSET + j + PCI_VPD_SIZE + 2854 5 + k, buf, sizeof(buf)); 2855 buf[sizeof(buf) - 1] = '\0'; 2856 if (strcmp(buf, CAS_PHY_TYPE_PCS) == 0) 2857 pcs[phy] = 1; 2858 phy++; 2859 if (lma == 4 && phy == 4) 2860 break; 2861 } 2862 } 2863 break; 2864 default: 2865 device_printf(dev, "unexpected PCI VPD\n"); 2866 goto fail_prom; 2867 } 2868 2869 fail_prom: 2870 CAS_WRITE_4(sc, CAS_BIM_LDEV_OEN, 0); 2871 2872 if (lma == 0) { 2873 device_printf(dev, "could not determine Ethernet address\n"); 2874 goto fail; 2875 } 2876 i = 0; 2877 if (lma > 1 && pci_get_slot(dev) < nitems(enaddr)) 2878 i = pci_get_slot(dev); 2879 memcpy(sc->sc_enaddr, enaddr[i], ETHER_ADDR_LEN); 2880 2881 if (phy == 0) { 2882 device_printf(dev, "could not determine PHY type\n"); 2883 goto fail; 2884 } 2885 i = 0; 2886 if (phy > 1 && pci_get_slot(dev) < nitems(pcs)) 2887 i = pci_get_slot(dev); 2888 if (pcs[i] != 0) 2889 sc->sc_flags |= CAS_SERDES; 2890 #endif 2891 2892 if (cas_attach(sc) != 0) { 2893 device_printf(dev, "could not be attached\n"); 2894 goto fail; 2895 } 2896 2897 if (bus_setup_intr(dev, sc->sc_res[CAS_RES_INTR], INTR_TYPE_NET | 2898 INTR_MPSAFE, cas_intr, NULL, sc, &sc->sc_ih) != 0) { 2899 device_printf(dev, "failed to set up interrupt\n"); 2900 cas_detach(sc); 2901 goto fail; 2902 } 2903 return (0); 2904 2905 fail: 2906 CAS_LOCK_DESTROY(sc); 2907 bus_release_resources(dev, cas_pci_res_spec, sc->sc_res); 2908 return (ENXIO); 2909 } 2910 2911 static int 2912 cas_pci_detach(device_t dev) 2913 { 2914 struct cas_softc *sc; 2915 2916 sc = device_get_softc(dev); 2917 bus_teardown_intr(dev, sc->sc_res[CAS_RES_INTR], sc->sc_ih); 2918 cas_detach(sc); 2919 CAS_LOCK_DESTROY(sc); 2920 bus_release_resources(dev, cas_pci_res_spec, sc->sc_res); 2921 return (0); 2922 } 2923 2924 static int 2925 cas_pci_suspend(device_t dev) 2926 { 2927 2928 cas_suspend(device_get_softc(dev)); 2929 return (0); 2930 } 2931 2932 static int 2933 cas_pci_resume(device_t dev) 2934 { 2935 2936 cas_resume(device_get_softc(dev)); 2937 return (0); 2938 } 2939