1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (C) 2001 Eduardo Horvath. 5 * Copyright (c) 2001-2003 Thomas Moestl 6 * Copyright (c) 2007-2009 Marius Strobl <marius@FreeBSD.org> 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * from: NetBSD: gem.c,v 1.21 2002/06/01 23:50:58 lukem Exp 31 * from: FreeBSD: if_gem.c 182060 2008-08-23 15:03:26Z marius 32 */ 33 34 #include <sys/cdefs.h> 35 /* 36 * driver for Sun Cassini/Cassini+ and National Semiconductor DP83065 37 * Saturn Gigabit Ethernet controllers 38 */ 39 40 #if 0 41 #define CAS_DEBUG 42 #endif 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/bus.h> 47 #include <sys/callout.h> 48 #include <sys/endian.h> 49 #include <sys/mbuf.h> 50 #include <sys/malloc.h> 51 #include <sys/kernel.h> 52 #include <sys/lock.h> 53 #include <sys/module.h> 54 #include <sys/mutex.h> 55 #include <sys/refcount.h> 56 #include <sys/resource.h> 57 #include <sys/rman.h> 58 #include <sys/socket.h> 59 #include <sys/sockio.h> 60 #include <sys/taskqueue.h> 61 62 #include <net/bpf.h> 63 #include <net/ethernet.h> 64 #include <net/if.h> 65 #include <net/if_var.h> 66 #include <net/if_arp.h> 67 #include <net/if_dl.h> 68 #include <net/if_media.h> 69 #include <net/if_types.h> 70 #include <net/if_vlan_var.h> 71 72 #include <netinet/in.h> 73 #include <netinet/in_systm.h> 74 #include <netinet/ip.h> 75 #include <netinet/tcp.h> 76 #include <netinet/udp.h> 77 78 #include <machine/bus.h> 79 #if defined(__powerpc__) 80 #include <dev/ofw/ofw_bus.h> 81 #include <dev/ofw/openfirm.h> 82 #include <machine/ofw_machdep.h> 83 #endif 84 #include <machine/resource.h> 85 86 #include <dev/mii/mii.h> 87 #include <dev/mii/miivar.h> 88 89 #include <dev/cas/if_casreg.h> 90 #include <dev/cas/if_casvar.h> 91 92 #include <dev/pci/pcireg.h> 93 #include <dev/pci/pcivar.h> 94 95 #include "miibus_if.h" 96 97 #define RINGASSERT(n , min, max) \ 98 CTASSERT(powerof2(n) && (n) >= (min) && (n) <= (max)) 99 100 RINGASSERT(CAS_NRXCOMP, 128, 32768); 101 RINGASSERT(CAS_NRXDESC, 32, 8192); 102 RINGASSERT(CAS_NRXDESC2, 32, 8192); 103 RINGASSERT(CAS_NTXDESC, 32, 8192); 104 105 #undef RINGASSERT 106 107 #define CCDASSERT(m, a) \ 108 CTASSERT((offsetof(struct cas_control_data, m) & ((a) - 1)) == 0) 109 110 CCDASSERT(ccd_rxcomps, CAS_RX_COMP_ALIGN); 111 CCDASSERT(ccd_rxdescs, CAS_RX_DESC_ALIGN); 112 CCDASSERT(ccd_rxdescs2, CAS_RX_DESC_ALIGN); 113 114 #undef CCDASSERT 115 116 #define CAS_TRIES 10000 117 118 /* 119 * According to documentation, the hardware has support for basic TCP 120 * checksum offloading only, in practice this can be also used for UDP 121 * however (i.e. the problem of previous Sun NICs that a checksum of 0x0 122 * is not converted to 0xffff no longer exists). 123 */ 124 #define CAS_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 125 126 static inline void cas_add_rxdesc(struct cas_softc *sc, u_int idx); 127 static int cas_attach(struct cas_softc *sc); 128 static int cas_bitwait(struct cas_softc *sc, bus_addr_t r, uint32_t clr, 129 uint32_t set); 130 static void cas_cddma_callback(void *xsc, bus_dma_segment_t *segs, 131 int nsegs, int error); 132 static void cas_detach(struct cas_softc *sc); 133 static int cas_disable_rx(struct cas_softc *sc); 134 static int cas_disable_tx(struct cas_softc *sc); 135 static void cas_eint(struct cas_softc *sc, u_int status); 136 static void cas_free(struct mbuf *m); 137 static void cas_init(void *xsc); 138 static void cas_init_locked(struct cas_softc *sc); 139 static void cas_init_regs(struct cas_softc *sc); 140 static int cas_intr(void *v); 141 static void cas_intr_task(void *arg, int pending __unused); 142 static int cas_ioctl(if_t ifp, u_long cmd, caddr_t data); 143 static int cas_load_txmbuf(struct cas_softc *sc, struct mbuf **m_head); 144 static int cas_mediachange(if_t ifp); 145 static void cas_mediastatus(if_t ifp, struct ifmediareq *ifmr); 146 static void cas_meminit(struct cas_softc *sc); 147 static void cas_mifinit(struct cas_softc *sc); 148 static int cas_mii_readreg(device_t dev, int phy, int reg); 149 static void cas_mii_statchg(device_t dev); 150 static int cas_mii_writereg(device_t dev, int phy, int reg, int val); 151 static void cas_reset(struct cas_softc *sc); 152 static int cas_reset_rx(struct cas_softc *sc); 153 static int cas_reset_tx(struct cas_softc *sc); 154 static void cas_resume(struct cas_softc *sc); 155 static u_int cas_descsize(u_int sz); 156 static void cas_rint(struct cas_softc *sc); 157 static void cas_rint_timeout(void *arg); 158 static inline void cas_rxcksum(struct mbuf *m, uint16_t cksum); 159 static inline void cas_rxcompinit(struct cas_rx_comp *rxcomp); 160 static u_int cas_rxcompsize(u_int sz); 161 static void cas_rxdma_callback(void *xsc, bus_dma_segment_t *segs, 162 int nsegs, int error); 163 static void cas_setladrf(struct cas_softc *sc); 164 static void cas_start(if_t ifp); 165 static void cas_stop(if_t ifp); 166 static void cas_suspend(struct cas_softc *sc); 167 static void cas_tick(void *arg); 168 static void cas_tint(struct cas_softc *sc); 169 static void cas_tx_task(void *arg, int pending __unused); 170 static inline void cas_txkick(struct cas_softc *sc); 171 static void cas_watchdog(struct cas_softc *sc); 172 173 MODULE_DEPEND(cas, ether, 1, 1, 1); 174 MODULE_DEPEND(cas, miibus, 1, 1, 1); 175 176 #ifdef CAS_DEBUG 177 #include <sys/ktr.h> 178 #define KTR_CAS KTR_SPARE2 179 #endif 180 181 static int 182 cas_attach(struct cas_softc *sc) 183 { 184 struct cas_txsoft *txs; 185 if_t ifp; 186 int error, i; 187 uint32_t v; 188 189 /* Set up ifnet structure. */ 190 ifp = sc->sc_ifp = if_alloc(IFT_ETHER); 191 if_setsoftc(ifp, sc); 192 if_initname(ifp, device_get_name(sc->sc_dev), 193 device_get_unit(sc->sc_dev)); 194 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 195 if_setstartfn(ifp, cas_start); 196 if_setioctlfn(ifp, cas_ioctl); 197 if_setinitfn(ifp, cas_init); 198 if_setsendqlen(ifp, CAS_TXQUEUELEN); 199 if_setsendqready(ifp); 200 201 callout_init_mtx(&sc->sc_tick_ch, &sc->sc_mtx, 0); 202 callout_init_mtx(&sc->sc_rx_ch, &sc->sc_mtx, 0); 203 /* Create local taskq. */ 204 NET_TASK_INIT(&sc->sc_intr_task, 0, cas_intr_task, sc); 205 TASK_INIT(&sc->sc_tx_task, 1, cas_tx_task, ifp); 206 sc->sc_tq = taskqueue_create_fast("cas_taskq", M_WAITOK, 207 taskqueue_thread_enqueue, &sc->sc_tq); 208 error = taskqueue_start_threads(&sc->sc_tq, 1, PI_NET, "%s taskq", 209 device_get_nameunit(sc->sc_dev)); 210 if (error != 0) { 211 device_printf(sc->sc_dev, "could not start threads\n"); 212 goto fail_taskq; 213 } 214 215 /* Make sure the chip is stopped. */ 216 cas_reset(sc); 217 218 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 219 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 220 BUS_SPACE_MAXSIZE, 0, BUS_SPACE_MAXSIZE, 0, NULL, NULL, 221 &sc->sc_pdmatag); 222 if (error != 0) 223 goto fail_taskq; 224 225 error = bus_dma_tag_create(sc->sc_pdmatag, 1, 0, 226 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 227 CAS_PAGE_SIZE, 1, CAS_PAGE_SIZE, 0, NULL, NULL, &sc->sc_rdmatag); 228 if (error != 0) 229 goto fail_ptag; 230 231 error = bus_dma_tag_create(sc->sc_pdmatag, 1, 0, 232 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 233 MCLBYTES * CAS_NTXSEGS, CAS_NTXSEGS, MCLBYTES, 234 BUS_DMA_ALLOCNOW, NULL, NULL, &sc->sc_tdmatag); 235 if (error != 0) 236 goto fail_rtag; 237 238 error = bus_dma_tag_create(sc->sc_pdmatag, CAS_TX_DESC_ALIGN, 0, 239 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 240 sizeof(struct cas_control_data), 1, 241 sizeof(struct cas_control_data), 0, 242 NULL, NULL, &sc->sc_cdmatag); 243 if (error != 0) 244 goto fail_ttag; 245 246 /* 247 * Allocate the control data structures, create and load the 248 * DMA map for it. 249 */ 250 if ((error = bus_dmamem_alloc(sc->sc_cdmatag, 251 (void **)&sc->sc_control_data, 252 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 253 &sc->sc_cddmamap)) != 0) { 254 device_printf(sc->sc_dev, 255 "unable to allocate control data, error = %d\n", error); 256 goto fail_ctag; 257 } 258 259 sc->sc_cddma = 0; 260 if ((error = bus_dmamap_load(sc->sc_cdmatag, sc->sc_cddmamap, 261 sc->sc_control_data, sizeof(struct cas_control_data), 262 cas_cddma_callback, sc, 0)) != 0 || sc->sc_cddma == 0) { 263 device_printf(sc->sc_dev, 264 "unable to load control data DMA map, error = %d\n", 265 error); 266 goto fail_cmem; 267 } 268 269 /* 270 * Initialize the transmit job descriptors. 271 */ 272 STAILQ_INIT(&sc->sc_txfreeq); 273 STAILQ_INIT(&sc->sc_txdirtyq); 274 275 /* 276 * Create the transmit buffer DMA maps. 277 */ 278 error = ENOMEM; 279 for (i = 0; i < CAS_TXQUEUELEN; i++) { 280 txs = &sc->sc_txsoft[i]; 281 txs->txs_mbuf = NULL; 282 txs->txs_ndescs = 0; 283 if ((error = bus_dmamap_create(sc->sc_tdmatag, 0, 284 &txs->txs_dmamap)) != 0) { 285 device_printf(sc->sc_dev, 286 "unable to create TX DMA map %d, error = %d\n", 287 i, error); 288 goto fail_txd; 289 } 290 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 291 } 292 293 /* 294 * Allocate the receive buffers, create and load the DMA maps 295 * for them. 296 */ 297 for (i = 0; i < CAS_NRXDESC; i++) { 298 if ((error = bus_dmamem_alloc(sc->sc_rdmatag, 299 &sc->sc_rxdsoft[i].rxds_buf, BUS_DMA_WAITOK, 300 &sc->sc_rxdsoft[i].rxds_dmamap)) != 0) { 301 device_printf(sc->sc_dev, 302 "unable to allocate RX buffer %d, error = %d\n", 303 i, error); 304 goto fail_rxmem; 305 } 306 307 sc->sc_rxdptr = i; 308 sc->sc_rxdsoft[i].rxds_paddr = 0; 309 if ((error = bus_dmamap_load(sc->sc_rdmatag, 310 sc->sc_rxdsoft[i].rxds_dmamap, sc->sc_rxdsoft[i].rxds_buf, 311 CAS_PAGE_SIZE, cas_rxdma_callback, sc, 0)) != 0 || 312 sc->sc_rxdsoft[i].rxds_paddr == 0) { 313 device_printf(sc->sc_dev, 314 "unable to load RX DMA map %d, error = %d\n", 315 i, error); 316 goto fail_rxmap; 317 } 318 } 319 320 if ((sc->sc_flags & CAS_SERDES) == 0) { 321 CAS_WRITE_4(sc, CAS_PCS_DATAPATH, CAS_PCS_DATAPATH_MII); 322 CAS_BARRIER(sc, CAS_PCS_DATAPATH, 4, 323 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 324 cas_mifinit(sc); 325 /* 326 * Look for an external PHY. 327 */ 328 error = ENXIO; 329 v = CAS_READ_4(sc, CAS_MIF_CONF); 330 if ((v & CAS_MIF_CONF_MDI1) != 0) { 331 v |= CAS_MIF_CONF_PHY_SELECT; 332 CAS_WRITE_4(sc, CAS_MIF_CONF, v); 333 CAS_BARRIER(sc, CAS_MIF_CONF, 4, 334 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 335 /* Enable/unfreeze the GMII pins of Saturn. */ 336 if (sc->sc_variant == CAS_SATURN) { 337 CAS_WRITE_4(sc, CAS_SATURN_PCFG, 338 CAS_READ_4(sc, CAS_SATURN_PCFG) & 339 ~CAS_SATURN_PCFG_FSI); 340 CAS_BARRIER(sc, CAS_SATURN_PCFG, 4, 341 BUS_SPACE_BARRIER_READ | 342 BUS_SPACE_BARRIER_WRITE); 343 DELAY(10000); 344 } 345 error = mii_attach(sc->sc_dev, &sc->sc_miibus, ifp, 346 cas_mediachange, cas_mediastatus, BMSR_DEFCAPMASK, 347 MII_PHY_ANY, MII_OFFSET_ANY, MIIF_DOPAUSE); 348 } 349 /* 350 * Fall back on an internal PHY if no external PHY was found. 351 */ 352 if (error != 0 && (v & CAS_MIF_CONF_MDI0) != 0) { 353 v &= ~CAS_MIF_CONF_PHY_SELECT; 354 CAS_WRITE_4(sc, CAS_MIF_CONF, v); 355 CAS_BARRIER(sc, CAS_MIF_CONF, 4, 356 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 357 /* Freeze the GMII pins of Saturn for saving power. */ 358 if (sc->sc_variant == CAS_SATURN) { 359 CAS_WRITE_4(sc, CAS_SATURN_PCFG, 360 CAS_READ_4(sc, CAS_SATURN_PCFG) | 361 CAS_SATURN_PCFG_FSI); 362 CAS_BARRIER(sc, CAS_SATURN_PCFG, 4, 363 BUS_SPACE_BARRIER_READ | 364 BUS_SPACE_BARRIER_WRITE); 365 DELAY(10000); 366 } 367 error = mii_attach(sc->sc_dev, &sc->sc_miibus, ifp, 368 cas_mediachange, cas_mediastatus, BMSR_DEFCAPMASK, 369 MII_PHY_ANY, MII_OFFSET_ANY, MIIF_DOPAUSE); 370 } 371 } else { 372 /* 373 * Use the external PCS SERDES. 374 */ 375 CAS_WRITE_4(sc, CAS_PCS_DATAPATH, CAS_PCS_DATAPATH_SERDES); 376 CAS_BARRIER(sc, CAS_PCS_DATAPATH, 4, BUS_SPACE_BARRIER_WRITE); 377 /* Enable/unfreeze the SERDES pins of Saturn. */ 378 if (sc->sc_variant == CAS_SATURN) { 379 CAS_WRITE_4(sc, CAS_SATURN_PCFG, 0); 380 CAS_BARRIER(sc, CAS_SATURN_PCFG, 4, 381 BUS_SPACE_BARRIER_WRITE); 382 } 383 CAS_WRITE_4(sc, CAS_PCS_SERDES_CTRL, CAS_PCS_SERDES_CTRL_ESD); 384 CAS_BARRIER(sc, CAS_PCS_SERDES_CTRL, 4, 385 BUS_SPACE_BARRIER_WRITE); 386 CAS_WRITE_4(sc, CAS_PCS_CONF, CAS_PCS_CONF_EN); 387 CAS_BARRIER(sc, CAS_PCS_CONF, 4, 388 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 389 error = mii_attach(sc->sc_dev, &sc->sc_miibus, ifp, 390 cas_mediachange, cas_mediastatus, BMSR_DEFCAPMASK, 391 CAS_PHYAD_EXTERNAL, MII_OFFSET_ANY, MIIF_DOPAUSE); 392 } 393 if (error != 0) { 394 device_printf(sc->sc_dev, "attaching PHYs failed\n"); 395 goto fail_rxmap; 396 } 397 sc->sc_mii = device_get_softc(sc->sc_miibus); 398 399 /* 400 * From this point forward, the attachment cannot fail. A failure 401 * before this point releases all resources that may have been 402 * allocated. 403 */ 404 405 /* Announce FIFO sizes. */ 406 v = CAS_READ_4(sc, CAS_TX_FIFO_SIZE); 407 device_printf(sc->sc_dev, "%ukB RX FIFO, %ukB TX FIFO\n", 408 CAS_RX_FIFO_SIZE / 1024, v / 16); 409 410 /* Attach the interface. */ 411 ether_ifattach(ifp, sc->sc_enaddr); 412 413 /* 414 * Tell the upper layer(s) we support long frames/checksum offloads. 415 */ 416 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 417 if_setcapabilities(ifp, IFCAP_VLAN_MTU); 418 if ((sc->sc_flags & CAS_NO_CSUM) == 0) { 419 if_setcapabilitiesbit(ifp, IFCAP_HWCSUM, 0); 420 if_sethwassist(ifp, CAS_CSUM_FEATURES); 421 } 422 if_setcapenable(ifp, if_getcapabilities(ifp)); 423 424 return (0); 425 426 /* 427 * Free any resources we've allocated during the failed attach 428 * attempt. Do this in reverse order and fall through. 429 */ 430 fail_rxmap: 431 for (i = 0; i < CAS_NRXDESC; i++) 432 if (sc->sc_rxdsoft[i].rxds_paddr != 0) 433 bus_dmamap_unload(sc->sc_rdmatag, 434 sc->sc_rxdsoft[i].rxds_dmamap); 435 fail_rxmem: 436 for (i = 0; i < CAS_NRXDESC; i++) 437 if (sc->sc_rxdsoft[i].rxds_buf != NULL) 438 bus_dmamem_free(sc->sc_rdmatag, 439 sc->sc_rxdsoft[i].rxds_buf, 440 sc->sc_rxdsoft[i].rxds_dmamap); 441 fail_txd: 442 for (i = 0; i < CAS_TXQUEUELEN; i++) 443 if (sc->sc_txsoft[i].txs_dmamap != NULL) 444 bus_dmamap_destroy(sc->sc_tdmatag, 445 sc->sc_txsoft[i].txs_dmamap); 446 bus_dmamap_unload(sc->sc_cdmatag, sc->sc_cddmamap); 447 fail_cmem: 448 bus_dmamem_free(sc->sc_cdmatag, sc->sc_control_data, 449 sc->sc_cddmamap); 450 fail_ctag: 451 bus_dma_tag_destroy(sc->sc_cdmatag); 452 fail_ttag: 453 bus_dma_tag_destroy(sc->sc_tdmatag); 454 fail_rtag: 455 bus_dma_tag_destroy(sc->sc_rdmatag); 456 fail_ptag: 457 bus_dma_tag_destroy(sc->sc_pdmatag); 458 fail_taskq: 459 taskqueue_free(sc->sc_tq); 460 if_free(ifp); 461 return (error); 462 } 463 464 static void 465 cas_detach(struct cas_softc *sc) 466 { 467 if_t ifp = sc->sc_ifp; 468 int i; 469 470 ether_ifdetach(ifp); 471 CAS_LOCK(sc); 472 cas_stop(ifp); 473 CAS_UNLOCK(sc); 474 callout_drain(&sc->sc_tick_ch); 475 callout_drain(&sc->sc_rx_ch); 476 taskqueue_drain(sc->sc_tq, &sc->sc_intr_task); 477 taskqueue_drain(sc->sc_tq, &sc->sc_tx_task); 478 if_free(ifp); 479 taskqueue_free(sc->sc_tq); 480 device_delete_child(sc->sc_dev, sc->sc_miibus); 481 482 for (i = 0; i < CAS_NRXDESC; i++) 483 if (sc->sc_rxdsoft[i].rxds_dmamap != NULL) 484 bus_dmamap_sync(sc->sc_rdmatag, 485 sc->sc_rxdsoft[i].rxds_dmamap, 486 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 487 for (i = 0; i < CAS_NRXDESC; i++) 488 if (sc->sc_rxdsoft[i].rxds_paddr != 0) 489 bus_dmamap_unload(sc->sc_rdmatag, 490 sc->sc_rxdsoft[i].rxds_dmamap); 491 for (i = 0; i < CAS_NRXDESC; i++) 492 if (sc->sc_rxdsoft[i].rxds_buf != NULL) 493 bus_dmamem_free(sc->sc_rdmatag, 494 sc->sc_rxdsoft[i].rxds_buf, 495 sc->sc_rxdsoft[i].rxds_dmamap); 496 for (i = 0; i < CAS_TXQUEUELEN; i++) 497 if (sc->sc_txsoft[i].txs_dmamap != NULL) 498 bus_dmamap_destroy(sc->sc_tdmatag, 499 sc->sc_txsoft[i].txs_dmamap); 500 CAS_CDSYNC(sc, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 501 bus_dmamap_unload(sc->sc_cdmatag, sc->sc_cddmamap); 502 bus_dmamem_free(sc->sc_cdmatag, sc->sc_control_data, 503 sc->sc_cddmamap); 504 bus_dma_tag_destroy(sc->sc_cdmatag); 505 bus_dma_tag_destroy(sc->sc_tdmatag); 506 bus_dma_tag_destroy(sc->sc_rdmatag); 507 bus_dma_tag_destroy(sc->sc_pdmatag); 508 } 509 510 static void 511 cas_suspend(struct cas_softc *sc) 512 { 513 if_t ifp = sc->sc_ifp; 514 515 CAS_LOCK(sc); 516 cas_stop(ifp); 517 CAS_UNLOCK(sc); 518 } 519 520 static void 521 cas_resume(struct cas_softc *sc) 522 { 523 if_t ifp = sc->sc_ifp; 524 525 CAS_LOCK(sc); 526 /* 527 * On resume all registers have to be initialized again like 528 * after power-on. 529 */ 530 sc->sc_flags &= ~CAS_INITED; 531 if (if_getflags(ifp) & IFF_UP) 532 cas_init_locked(sc); 533 CAS_UNLOCK(sc); 534 } 535 536 static inline void 537 cas_rxcksum(struct mbuf *m, uint16_t cksum) 538 { 539 struct ether_header *eh; 540 struct ip *ip; 541 struct udphdr *uh; 542 uint16_t *opts; 543 int32_t hlen, len, pktlen; 544 uint32_t temp32; 545 546 pktlen = m->m_pkthdr.len; 547 if (pktlen < sizeof(struct ether_header) + sizeof(struct ip)) 548 return; 549 eh = mtod(m, struct ether_header *); 550 if (eh->ether_type != htons(ETHERTYPE_IP)) 551 return; 552 ip = (struct ip *)(eh + 1); 553 if (ip->ip_v != IPVERSION) 554 return; 555 556 hlen = ip->ip_hl << 2; 557 pktlen -= sizeof(struct ether_header); 558 if (hlen < sizeof(struct ip)) 559 return; 560 if (ntohs(ip->ip_len) < hlen) 561 return; 562 if (ntohs(ip->ip_len) != pktlen) 563 return; 564 if (ip->ip_off & htons(IP_MF | IP_OFFMASK)) 565 return; /* Cannot handle fragmented packet. */ 566 567 switch (ip->ip_p) { 568 case IPPROTO_TCP: 569 if (pktlen < (hlen + sizeof(struct tcphdr))) 570 return; 571 break; 572 case IPPROTO_UDP: 573 if (pktlen < (hlen + sizeof(struct udphdr))) 574 return; 575 uh = (struct udphdr *)((uint8_t *)ip + hlen); 576 if (uh->uh_sum == 0) 577 return; /* no checksum */ 578 break; 579 default: 580 return; 581 } 582 583 cksum = ~cksum; 584 /* checksum fixup for IP options */ 585 len = hlen - sizeof(struct ip); 586 if (len > 0) { 587 opts = (uint16_t *)(ip + 1); 588 for (; len > 0; len -= sizeof(uint16_t), opts++) { 589 temp32 = cksum - *opts; 590 temp32 = (temp32 >> 16) + (temp32 & 65535); 591 cksum = temp32 & 65535; 592 } 593 } 594 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID; 595 m->m_pkthdr.csum_data = cksum; 596 } 597 598 static void 599 cas_cddma_callback(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 600 { 601 struct cas_softc *sc = xsc; 602 603 if (error != 0) 604 return; 605 if (nsegs != 1) 606 panic("%s: bad control buffer segment count", __func__); 607 sc->sc_cddma = segs[0].ds_addr; 608 } 609 610 static void 611 cas_rxdma_callback(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 612 { 613 struct cas_softc *sc = xsc; 614 615 if (error != 0) 616 return; 617 if (nsegs != 1) 618 panic("%s: bad RX buffer segment count", __func__); 619 sc->sc_rxdsoft[sc->sc_rxdptr].rxds_paddr = segs[0].ds_addr; 620 } 621 622 static void 623 cas_tick(void *arg) 624 { 625 struct cas_softc *sc = arg; 626 if_t ifp = sc->sc_ifp; 627 uint32_t v; 628 629 CAS_LOCK_ASSERT(sc, MA_OWNED); 630 631 /* 632 * Unload collision and error counters. 633 */ 634 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 635 CAS_READ_4(sc, CAS_MAC_NORM_COLL_CNT) + 636 CAS_READ_4(sc, CAS_MAC_FIRST_COLL_CNT)); 637 v = CAS_READ_4(sc, CAS_MAC_EXCESS_COLL_CNT) + 638 CAS_READ_4(sc, CAS_MAC_LATE_COLL_CNT); 639 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, v); 640 if_inc_counter(ifp, IFCOUNTER_OERRORS, v); 641 if_inc_counter(ifp, IFCOUNTER_IERRORS, 642 CAS_READ_4(sc, CAS_MAC_RX_LEN_ERR_CNT) + 643 CAS_READ_4(sc, CAS_MAC_RX_ALIGN_ERR) + 644 CAS_READ_4(sc, CAS_MAC_RX_CRC_ERR_CNT) + 645 CAS_READ_4(sc, CAS_MAC_RX_CODE_VIOL)); 646 647 /* 648 * Then clear the hardware counters. 649 */ 650 CAS_WRITE_4(sc, CAS_MAC_NORM_COLL_CNT, 0); 651 CAS_WRITE_4(sc, CAS_MAC_FIRST_COLL_CNT, 0); 652 CAS_WRITE_4(sc, CAS_MAC_EXCESS_COLL_CNT, 0); 653 CAS_WRITE_4(sc, CAS_MAC_LATE_COLL_CNT, 0); 654 CAS_WRITE_4(sc, CAS_MAC_RX_LEN_ERR_CNT, 0); 655 CAS_WRITE_4(sc, CAS_MAC_RX_ALIGN_ERR, 0); 656 CAS_WRITE_4(sc, CAS_MAC_RX_CRC_ERR_CNT, 0); 657 CAS_WRITE_4(sc, CAS_MAC_RX_CODE_VIOL, 0); 658 659 mii_tick(sc->sc_mii); 660 661 if (sc->sc_txfree != CAS_MAXTXFREE) 662 cas_tint(sc); 663 664 cas_watchdog(sc); 665 666 callout_reset(&sc->sc_tick_ch, hz, cas_tick, sc); 667 } 668 669 static int 670 cas_bitwait(struct cas_softc *sc, bus_addr_t r, uint32_t clr, uint32_t set) 671 { 672 int i; 673 uint32_t reg; 674 675 for (i = CAS_TRIES; i--; DELAY(100)) { 676 reg = CAS_READ_4(sc, r); 677 if ((reg & clr) == 0 && (reg & set) == set) 678 return (1); 679 } 680 return (0); 681 } 682 683 static void 684 cas_reset(struct cas_softc *sc) 685 { 686 687 #ifdef CAS_DEBUG 688 CTR2(KTR_CAS, "%s: %s", device_get_name(sc->sc_dev), __func__); 689 #endif 690 /* Disable all interrupts in order to avoid spurious ones. */ 691 CAS_WRITE_4(sc, CAS_INTMASK, 0xffffffff); 692 693 cas_reset_rx(sc); 694 cas_reset_tx(sc); 695 696 /* 697 * Do a full reset modulo the result of the last auto-negotiation 698 * when using the SERDES. 699 */ 700 CAS_WRITE_4(sc, CAS_RESET, CAS_RESET_RX | CAS_RESET_TX | 701 ((sc->sc_flags & CAS_SERDES) != 0 ? CAS_RESET_PCS_DIS : 0)); 702 CAS_BARRIER(sc, CAS_RESET, 4, 703 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 704 DELAY(3000); 705 if (!cas_bitwait(sc, CAS_RESET, CAS_RESET_RX | CAS_RESET_TX, 0)) 706 device_printf(sc->sc_dev, "cannot reset device\n"); 707 } 708 709 static void 710 cas_stop(if_t ifp) 711 { 712 struct cas_softc *sc = if_getsoftc(ifp); 713 struct cas_txsoft *txs; 714 715 #ifdef CAS_DEBUG 716 CTR2(KTR_CAS, "%s: %s", device_get_name(sc->sc_dev), __func__); 717 #endif 718 719 callout_stop(&sc->sc_tick_ch); 720 callout_stop(&sc->sc_rx_ch); 721 722 /* Disable all interrupts in order to avoid spurious ones. */ 723 CAS_WRITE_4(sc, CAS_INTMASK, 0xffffffff); 724 725 cas_reset_tx(sc); 726 cas_reset_rx(sc); 727 728 /* 729 * Release any queued transmit buffers. 730 */ 731 while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 732 STAILQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 733 if (txs->txs_ndescs != 0) { 734 bus_dmamap_sync(sc->sc_tdmatag, txs->txs_dmamap, 735 BUS_DMASYNC_POSTWRITE); 736 bus_dmamap_unload(sc->sc_tdmatag, txs->txs_dmamap); 737 if (txs->txs_mbuf != NULL) { 738 m_freem(txs->txs_mbuf); 739 txs->txs_mbuf = NULL; 740 } 741 } 742 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 743 } 744 745 /* 746 * Mark the interface down and cancel the watchdog timer. 747 */ 748 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)); 749 sc->sc_flags &= ~CAS_LINK; 750 sc->sc_wdog_timer = 0; 751 } 752 753 static int 754 cas_reset_rx(struct cas_softc *sc) 755 { 756 757 /* 758 * Resetting while DMA is in progress can cause a bus hang, so we 759 * disable DMA first. 760 */ 761 (void)cas_disable_rx(sc); 762 CAS_WRITE_4(sc, CAS_RX_CONF, 0); 763 CAS_BARRIER(sc, CAS_RX_CONF, 4, 764 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 765 if (!cas_bitwait(sc, CAS_RX_CONF, CAS_RX_CONF_RXDMA_EN, 0)) 766 device_printf(sc->sc_dev, "cannot disable RX DMA\n"); 767 768 /* Finally, reset the ERX. */ 769 CAS_WRITE_4(sc, CAS_RESET, CAS_RESET_RX | 770 ((sc->sc_flags & CAS_SERDES) != 0 ? CAS_RESET_PCS_DIS : 0)); 771 CAS_BARRIER(sc, CAS_RESET, 4, 772 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 773 if (!cas_bitwait(sc, CAS_RESET, CAS_RESET_RX, 0)) { 774 device_printf(sc->sc_dev, "cannot reset receiver\n"); 775 return (1); 776 } 777 return (0); 778 } 779 780 static int 781 cas_reset_tx(struct cas_softc *sc) 782 { 783 784 /* 785 * Resetting while DMA is in progress can cause a bus hang, so we 786 * disable DMA first. 787 */ 788 (void)cas_disable_tx(sc); 789 CAS_WRITE_4(sc, CAS_TX_CONF, 0); 790 CAS_BARRIER(sc, CAS_TX_CONF, 4, 791 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 792 if (!cas_bitwait(sc, CAS_TX_CONF, CAS_TX_CONF_TXDMA_EN, 0)) 793 device_printf(sc->sc_dev, "cannot disable TX DMA\n"); 794 795 /* Finally, reset the ETX. */ 796 CAS_WRITE_4(sc, CAS_RESET, CAS_RESET_TX | 797 ((sc->sc_flags & CAS_SERDES) != 0 ? CAS_RESET_PCS_DIS : 0)); 798 CAS_BARRIER(sc, CAS_RESET, 4, 799 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 800 if (!cas_bitwait(sc, CAS_RESET, CAS_RESET_TX, 0)) { 801 device_printf(sc->sc_dev, "cannot reset transmitter\n"); 802 return (1); 803 } 804 return (0); 805 } 806 807 static int 808 cas_disable_rx(struct cas_softc *sc) 809 { 810 811 CAS_WRITE_4(sc, CAS_MAC_RX_CONF, 812 CAS_READ_4(sc, CAS_MAC_RX_CONF) & ~CAS_MAC_RX_CONF_EN); 813 CAS_BARRIER(sc, CAS_MAC_RX_CONF, 4, 814 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 815 if (cas_bitwait(sc, CAS_MAC_RX_CONF, CAS_MAC_RX_CONF_EN, 0)) 816 return (1); 817 if (bootverbose) 818 device_printf(sc->sc_dev, "cannot disable RX MAC\n"); 819 return (0); 820 } 821 822 static int 823 cas_disable_tx(struct cas_softc *sc) 824 { 825 826 CAS_WRITE_4(sc, CAS_MAC_TX_CONF, 827 CAS_READ_4(sc, CAS_MAC_TX_CONF) & ~CAS_MAC_TX_CONF_EN); 828 CAS_BARRIER(sc, CAS_MAC_TX_CONF, 4, 829 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 830 if (cas_bitwait(sc, CAS_MAC_TX_CONF, CAS_MAC_TX_CONF_EN, 0)) 831 return (1); 832 if (bootverbose) 833 device_printf(sc->sc_dev, "cannot disable TX MAC\n"); 834 return (0); 835 } 836 837 static inline void 838 cas_rxcompinit(struct cas_rx_comp *rxcomp) 839 { 840 841 rxcomp->crc_word1 = 0; 842 rxcomp->crc_word2 = 0; 843 rxcomp->crc_word3 = 844 htole64(CAS_SET(ETHER_HDR_LEN + sizeof(struct ip), CAS_RC3_CSO)); 845 rxcomp->crc_word4 = htole64(CAS_RC4_ZERO); 846 } 847 848 static void 849 cas_meminit(struct cas_softc *sc) 850 { 851 int i; 852 853 CAS_LOCK_ASSERT(sc, MA_OWNED); 854 855 /* 856 * Initialize the transmit descriptor ring. 857 */ 858 for (i = 0; i < CAS_NTXDESC; i++) { 859 sc->sc_txdescs[i].cd_flags = 0; 860 sc->sc_txdescs[i].cd_buf_ptr = 0; 861 } 862 sc->sc_txfree = CAS_MAXTXFREE; 863 sc->sc_txnext = 0; 864 sc->sc_txwin = 0; 865 866 /* 867 * Initialize the receive completion ring. 868 */ 869 for (i = 0; i < CAS_NRXCOMP; i++) 870 cas_rxcompinit(&sc->sc_rxcomps[i]); 871 sc->sc_rxcptr = 0; 872 873 /* 874 * Initialize the first receive descriptor ring. We leave 875 * the second one zeroed as we don't actually use it. 876 */ 877 for (i = 0; i < CAS_NRXDESC; i++) 878 CAS_INIT_RXDESC(sc, i, i); 879 sc->sc_rxdptr = 0; 880 881 CAS_CDSYNC(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 882 } 883 884 static u_int 885 cas_descsize(u_int sz) 886 { 887 888 switch (sz) { 889 case 32: 890 return (CAS_DESC_32); 891 case 64: 892 return (CAS_DESC_64); 893 case 128: 894 return (CAS_DESC_128); 895 case 256: 896 return (CAS_DESC_256); 897 case 512: 898 return (CAS_DESC_512); 899 case 1024: 900 return (CAS_DESC_1K); 901 case 2048: 902 return (CAS_DESC_2K); 903 case 4096: 904 return (CAS_DESC_4K); 905 case 8192: 906 return (CAS_DESC_8K); 907 default: 908 printf("%s: invalid descriptor ring size %d\n", __func__, sz); 909 return (CAS_DESC_32); 910 } 911 } 912 913 static u_int 914 cas_rxcompsize(u_int sz) 915 { 916 917 switch (sz) { 918 case 128: 919 return (CAS_RX_CONF_COMP_128); 920 case 256: 921 return (CAS_RX_CONF_COMP_256); 922 case 512: 923 return (CAS_RX_CONF_COMP_512); 924 case 1024: 925 return (CAS_RX_CONF_COMP_1K); 926 case 2048: 927 return (CAS_RX_CONF_COMP_2K); 928 case 4096: 929 return (CAS_RX_CONF_COMP_4K); 930 case 8192: 931 return (CAS_RX_CONF_COMP_8K); 932 case 16384: 933 return (CAS_RX_CONF_COMP_16K); 934 case 32768: 935 return (CAS_RX_CONF_COMP_32K); 936 default: 937 printf("%s: invalid dcompletion ring size %d\n", __func__, sz); 938 return (CAS_RX_CONF_COMP_128); 939 } 940 } 941 942 static void 943 cas_init(void *xsc) 944 { 945 struct cas_softc *sc = xsc; 946 947 CAS_LOCK(sc); 948 cas_init_locked(sc); 949 CAS_UNLOCK(sc); 950 } 951 952 /* 953 * Initialization of interface; set up initialization block 954 * and transmit/receive descriptor rings. 955 */ 956 static void 957 cas_init_locked(struct cas_softc *sc) 958 { 959 if_t ifp = sc->sc_ifp; 960 uint32_t v; 961 962 CAS_LOCK_ASSERT(sc, MA_OWNED); 963 964 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 965 return; 966 967 #ifdef CAS_DEBUG 968 CTR2(KTR_CAS, "%s: %s: calling stop", device_get_name(sc->sc_dev), 969 __func__); 970 #endif 971 /* 972 * Initialization sequence. The numbered steps below correspond 973 * to the sequence outlined in section 6.3.5.1 in the Ethernet 974 * Channel Engine manual (part of the PCIO manual). 975 * See also the STP2002-STQ document from Sun Microsystems. 976 */ 977 978 /* step 1 & 2. Reset the Ethernet Channel. */ 979 cas_stop(ifp); 980 cas_reset(sc); 981 #ifdef CAS_DEBUG 982 CTR2(KTR_CAS, "%s: %s: restarting", device_get_name(sc->sc_dev), 983 __func__); 984 #endif 985 986 if ((sc->sc_flags & CAS_SERDES) == 0) 987 /* Re-initialize the MIF. */ 988 cas_mifinit(sc); 989 990 /* step 3. Setup data structures in host memory. */ 991 cas_meminit(sc); 992 993 /* step 4. TX MAC registers & counters */ 994 cas_init_regs(sc); 995 996 /* step 5. RX MAC registers & counters */ 997 998 /* step 6 & 7. Program Ring Base Addresses. */ 999 CAS_WRITE_4(sc, CAS_TX_DESC3_BASE_HI, 1000 (((uint64_t)CAS_CDTXDADDR(sc, 0)) >> 32)); 1001 CAS_WRITE_4(sc, CAS_TX_DESC3_BASE_LO, 1002 CAS_CDTXDADDR(sc, 0) & 0xffffffff); 1003 1004 CAS_WRITE_4(sc, CAS_RX_COMP_BASE_HI, 1005 (((uint64_t)CAS_CDRXCADDR(sc, 0)) >> 32)); 1006 CAS_WRITE_4(sc, CAS_RX_COMP_BASE_LO, 1007 CAS_CDRXCADDR(sc, 0) & 0xffffffff); 1008 1009 CAS_WRITE_4(sc, CAS_RX_DESC_BASE_HI, 1010 (((uint64_t)CAS_CDRXDADDR(sc, 0)) >> 32)); 1011 CAS_WRITE_4(sc, CAS_RX_DESC_BASE_LO, 1012 CAS_CDRXDADDR(sc, 0) & 0xffffffff); 1013 1014 if ((sc->sc_flags & CAS_REG_PLUS) != 0) { 1015 CAS_WRITE_4(sc, CAS_RX_DESC2_BASE_HI, 1016 (((uint64_t)CAS_CDRXD2ADDR(sc, 0)) >> 32)); 1017 CAS_WRITE_4(sc, CAS_RX_DESC2_BASE_LO, 1018 CAS_CDRXD2ADDR(sc, 0) & 0xffffffff); 1019 } 1020 1021 #ifdef CAS_DEBUG 1022 CTR5(KTR_CAS, 1023 "loading TXDR %lx, RXCR %lx, RXDR %lx, RXD2R %lx, cddma %lx", 1024 CAS_CDTXDADDR(sc, 0), CAS_CDRXCADDR(sc, 0), CAS_CDRXDADDR(sc, 0), 1025 CAS_CDRXD2ADDR(sc, 0), sc->sc_cddma); 1026 #endif 1027 1028 /* step 8. Global Configuration & Interrupt Masks */ 1029 1030 /* Disable weighted round robin. */ 1031 CAS_WRITE_4(sc, CAS_CAW, CAS_CAW_RR_DIS); 1032 1033 /* 1034 * Enable infinite bursts for revisions without PCI issues if 1035 * applicable. Doing so greatly improves the TX performance. 1036 */ 1037 CAS_WRITE_4(sc, CAS_INF_BURST, 1038 (sc->sc_flags & CAS_TABORT) == 0 ? CAS_INF_BURST_EN : 1039 0); 1040 1041 /* Set up interrupts. */ 1042 CAS_WRITE_4(sc, CAS_INTMASK, 1043 ~(CAS_INTR_TX_INT_ME | CAS_INTR_TX_TAG_ERR | 1044 CAS_INTR_RX_DONE | CAS_INTR_RX_BUF_NA | CAS_INTR_RX_TAG_ERR | 1045 CAS_INTR_RX_COMP_FULL | CAS_INTR_RX_BUF_AEMPTY | 1046 CAS_INTR_RX_COMP_AFULL | CAS_INTR_RX_LEN_MMATCH | 1047 CAS_INTR_PCI_ERROR_INT 1048 #ifdef CAS_DEBUG 1049 | CAS_INTR_PCS_INT | CAS_INTR_MIF 1050 #endif 1051 )); 1052 /* Don't clear top level interrupts when CAS_STATUS_ALIAS is read. */ 1053 CAS_WRITE_4(sc, CAS_CLEAR_ALIAS, 0); 1054 CAS_WRITE_4(sc, CAS_MAC_RX_MASK, ~CAS_MAC_RX_OVERFLOW); 1055 CAS_WRITE_4(sc, CAS_MAC_TX_MASK, 1056 ~(CAS_MAC_TX_UNDERRUN | CAS_MAC_TX_MAX_PKT_ERR)); 1057 #ifdef CAS_DEBUG 1058 CAS_WRITE_4(sc, CAS_MAC_CTRL_MASK, 1059 ~(CAS_MAC_CTRL_PAUSE_RCVD | CAS_MAC_CTRL_PAUSE | 1060 CAS_MAC_CTRL_NON_PAUSE)); 1061 #else 1062 CAS_WRITE_4(sc, CAS_MAC_CTRL_MASK, 1063 CAS_MAC_CTRL_PAUSE_RCVD | CAS_MAC_CTRL_PAUSE | 1064 CAS_MAC_CTRL_NON_PAUSE); 1065 #endif 1066 1067 /* Enable PCI error interrupts. */ 1068 CAS_WRITE_4(sc, CAS_ERROR_MASK, 1069 ~(CAS_ERROR_DTRTO | CAS_ERROR_OTHER | CAS_ERROR_DMAW_ZERO | 1070 CAS_ERROR_DMAR_ZERO | CAS_ERROR_RTRTO)); 1071 1072 /* Enable PCI error interrupts in BIM configuration. */ 1073 CAS_WRITE_4(sc, CAS_BIM_CONF, 1074 CAS_BIM_CONF_DPAR_EN | CAS_BIM_CONF_RMA_EN | CAS_BIM_CONF_RTA_EN); 1075 1076 /* 1077 * step 9. ETX Configuration: encode receive descriptor ring size, 1078 * enable DMA and disable pre-interrupt writeback completion. 1079 */ 1080 v = cas_descsize(CAS_NTXDESC) << CAS_TX_CONF_DESC3_SHFT; 1081 CAS_WRITE_4(sc, CAS_TX_CONF, v | CAS_TX_CONF_TXDMA_EN | 1082 CAS_TX_CONF_RDPP_DIS | CAS_TX_CONF_PICWB_DIS); 1083 1084 /* step 10. ERX Configuration */ 1085 1086 /* 1087 * Encode receive completion and descriptor ring sizes, set the 1088 * swivel offset. 1089 */ 1090 v = cas_rxcompsize(CAS_NRXCOMP) << CAS_RX_CONF_COMP_SHFT; 1091 v |= cas_descsize(CAS_NRXDESC) << CAS_RX_CONF_DESC_SHFT; 1092 if ((sc->sc_flags & CAS_REG_PLUS) != 0) 1093 v |= cas_descsize(CAS_NRXDESC2) << CAS_RX_CONF_DESC2_SHFT; 1094 CAS_WRITE_4(sc, CAS_RX_CONF, 1095 v | (ETHER_ALIGN << CAS_RX_CONF_SOFF_SHFT)); 1096 1097 /* Set the PAUSE thresholds. We use the maximum OFF threshold. */ 1098 CAS_WRITE_4(sc, CAS_RX_PTHRS, 1099 (111 << CAS_RX_PTHRS_XOFF_SHFT) | (15 << CAS_RX_PTHRS_XON_SHFT)); 1100 1101 /* RX blanking */ 1102 CAS_WRITE_4(sc, CAS_RX_BLANK, 1103 (15 << CAS_RX_BLANK_TIME_SHFT) | (5 << CAS_RX_BLANK_PKTS_SHFT)); 1104 1105 /* Set RX_COMP_AFULL threshold to half of the RX completions. */ 1106 CAS_WRITE_4(sc, CAS_RX_AEMPTY_THRS, 1107 (CAS_NRXCOMP / 2) << CAS_RX_AEMPTY_COMP_SHFT); 1108 1109 /* Initialize the RX page size register as appropriate for 8k. */ 1110 CAS_WRITE_4(sc, CAS_RX_PSZ, 1111 (CAS_RX_PSZ_8K << CAS_RX_PSZ_SHFT) | 1112 (4 << CAS_RX_PSZ_MB_CNT_SHFT) | 1113 (CAS_RX_PSZ_MB_STRD_2K << CAS_RX_PSZ_MB_STRD_SHFT) | 1114 (CAS_RX_PSZ_MB_OFF_64 << CAS_RX_PSZ_MB_OFF_SHFT)); 1115 1116 /* Disable RX random early detection. */ 1117 CAS_WRITE_4(sc, CAS_RX_RED, 0); 1118 1119 /* Zero the RX reassembly DMA table. */ 1120 for (v = 0; v <= CAS_RX_REAS_DMA_ADDR_LC; v++) { 1121 CAS_WRITE_4(sc, CAS_RX_REAS_DMA_ADDR, v); 1122 CAS_WRITE_4(sc, CAS_RX_REAS_DMA_DATA_LO, 0); 1123 CAS_WRITE_4(sc, CAS_RX_REAS_DMA_DATA_MD, 0); 1124 CAS_WRITE_4(sc, CAS_RX_REAS_DMA_DATA_HI, 0); 1125 } 1126 1127 /* Ensure the RX control FIFO and RX IPP FIFO addresses are zero. */ 1128 CAS_WRITE_4(sc, CAS_RX_CTRL_FIFO, 0); 1129 CAS_WRITE_4(sc, CAS_RX_IPP_ADDR, 0); 1130 1131 /* Finally, enable RX DMA. */ 1132 CAS_WRITE_4(sc, CAS_RX_CONF, 1133 CAS_READ_4(sc, CAS_RX_CONF) | CAS_RX_CONF_RXDMA_EN); 1134 1135 /* step 11. Configure Media. */ 1136 1137 /* step 12. RX_MAC Configuration Register */ 1138 v = CAS_READ_4(sc, CAS_MAC_RX_CONF); 1139 v &= ~(CAS_MAC_RX_CONF_STRPPAD | CAS_MAC_RX_CONF_EN); 1140 v |= CAS_MAC_RX_CONF_STRPFCS; 1141 sc->sc_mac_rxcfg = v; 1142 /* 1143 * Clear the RX filter and reprogram it. This will also set the 1144 * current RX MAC configuration and enable it. 1145 */ 1146 cas_setladrf(sc); 1147 1148 /* step 13. TX_MAC Configuration Register */ 1149 v = CAS_READ_4(sc, CAS_MAC_TX_CONF); 1150 v |= CAS_MAC_TX_CONF_EN; 1151 (void)cas_disable_tx(sc); 1152 CAS_WRITE_4(sc, CAS_MAC_TX_CONF, v); 1153 1154 /* step 14. Issue Transmit Pending command. */ 1155 1156 /* step 15. Give the receiver a swift kick. */ 1157 CAS_WRITE_4(sc, CAS_RX_KICK, CAS_NRXDESC - 4); 1158 CAS_WRITE_4(sc, CAS_RX_COMP_TAIL, 0); 1159 if ((sc->sc_flags & CAS_REG_PLUS) != 0) 1160 CAS_WRITE_4(sc, CAS_RX_KICK2, CAS_NRXDESC2 - 4); 1161 1162 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0); 1163 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 1164 1165 mii_mediachg(sc->sc_mii); 1166 1167 /* Start the one second timer. */ 1168 sc->sc_wdog_timer = 0; 1169 callout_reset(&sc->sc_tick_ch, hz, cas_tick, sc); 1170 } 1171 1172 static int 1173 cas_load_txmbuf(struct cas_softc *sc, struct mbuf **m_head) 1174 { 1175 bus_dma_segment_t txsegs[CAS_NTXSEGS]; 1176 struct cas_txsoft *txs; 1177 struct ip *ip; 1178 struct mbuf *m; 1179 uint64_t cflags; 1180 int error, nexttx, nsegs, offset, seg; 1181 1182 CAS_LOCK_ASSERT(sc, MA_OWNED); 1183 1184 /* Get a work queue entry. */ 1185 if ((txs = STAILQ_FIRST(&sc->sc_txfreeq)) == NULL) { 1186 /* Ran out of descriptors. */ 1187 return (ENOBUFS); 1188 } 1189 1190 cflags = 0; 1191 if (((*m_head)->m_pkthdr.csum_flags & CAS_CSUM_FEATURES) != 0) { 1192 if (M_WRITABLE(*m_head) == 0) { 1193 m = m_dup(*m_head, M_NOWAIT); 1194 m_freem(*m_head); 1195 *m_head = m; 1196 if (m == NULL) 1197 return (ENOBUFS); 1198 } 1199 offset = sizeof(struct ether_header); 1200 m = m_pullup(*m_head, offset + sizeof(struct ip)); 1201 if (m == NULL) { 1202 *m_head = NULL; 1203 return (ENOBUFS); 1204 } 1205 ip = (struct ip *)(mtod(m, caddr_t) + offset); 1206 offset += (ip->ip_hl << 2); 1207 cflags = (offset << CAS_TD_CKSUM_START_SHFT) | 1208 ((offset + m->m_pkthdr.csum_data) << 1209 CAS_TD_CKSUM_STUFF_SHFT) | CAS_TD_CKSUM_EN; 1210 *m_head = m; 1211 } 1212 1213 error = bus_dmamap_load_mbuf_sg(sc->sc_tdmatag, txs->txs_dmamap, 1214 *m_head, txsegs, &nsegs, BUS_DMA_NOWAIT); 1215 if (error == EFBIG) { 1216 m = m_collapse(*m_head, M_NOWAIT, CAS_NTXSEGS); 1217 if (m == NULL) { 1218 m_freem(*m_head); 1219 *m_head = NULL; 1220 return (ENOBUFS); 1221 } 1222 *m_head = m; 1223 error = bus_dmamap_load_mbuf_sg(sc->sc_tdmatag, 1224 txs->txs_dmamap, *m_head, txsegs, &nsegs, 1225 BUS_DMA_NOWAIT); 1226 if (error != 0) { 1227 m_freem(*m_head); 1228 *m_head = NULL; 1229 return (error); 1230 } 1231 } else if (error != 0) 1232 return (error); 1233 /* If nsegs is wrong then the stack is corrupt. */ 1234 KASSERT(nsegs <= CAS_NTXSEGS, 1235 ("%s: too many DMA segments (%d)", __func__, nsegs)); 1236 if (nsegs == 0) { 1237 m_freem(*m_head); 1238 *m_head = NULL; 1239 return (EIO); 1240 } 1241 1242 /* 1243 * Ensure we have enough descriptors free to describe 1244 * the packet. Note, we always reserve one descriptor 1245 * at the end of the ring as a termination point, in 1246 * order to prevent wrap-around. 1247 */ 1248 if (nsegs > sc->sc_txfree - 1) { 1249 txs->txs_ndescs = 0; 1250 bus_dmamap_unload(sc->sc_tdmatag, txs->txs_dmamap); 1251 return (ENOBUFS); 1252 } 1253 1254 txs->txs_ndescs = nsegs; 1255 txs->txs_firstdesc = sc->sc_txnext; 1256 nexttx = txs->txs_firstdesc; 1257 for (seg = 0; seg < nsegs; seg++, nexttx = CAS_NEXTTX(nexttx)) { 1258 #ifdef CAS_DEBUG 1259 CTR6(KTR_CAS, 1260 "%s: mapping seg %d (txd %d), len %lx, addr %#lx (%#lx)", 1261 __func__, seg, nexttx, txsegs[seg].ds_len, 1262 txsegs[seg].ds_addr, htole64(txsegs[seg].ds_addr)); 1263 #endif 1264 sc->sc_txdescs[nexttx].cd_buf_ptr = 1265 htole64(txsegs[seg].ds_addr); 1266 KASSERT(txsegs[seg].ds_len < 1267 CAS_TD_BUF_LEN_MASK >> CAS_TD_BUF_LEN_SHFT, 1268 ("%s: segment size too large!", __func__)); 1269 sc->sc_txdescs[nexttx].cd_flags = 1270 htole64(txsegs[seg].ds_len << CAS_TD_BUF_LEN_SHFT); 1271 txs->txs_lastdesc = nexttx; 1272 } 1273 1274 /* Set EOF on the last descriptor. */ 1275 #ifdef CAS_DEBUG 1276 CTR3(KTR_CAS, "%s: end of frame at segment %d, TX %d", 1277 __func__, seg, nexttx); 1278 #endif 1279 sc->sc_txdescs[txs->txs_lastdesc].cd_flags |= 1280 htole64(CAS_TD_END_OF_FRAME); 1281 1282 /* Lastly set SOF on the first descriptor. */ 1283 #ifdef CAS_DEBUG 1284 CTR3(KTR_CAS, "%s: start of frame at segment %d, TX %d", 1285 __func__, seg, nexttx); 1286 #endif 1287 if (sc->sc_txwin += nsegs > CAS_MAXTXFREE * 2 / 3) { 1288 sc->sc_txwin = 0; 1289 sc->sc_txdescs[txs->txs_firstdesc].cd_flags |= 1290 htole64(cflags | CAS_TD_START_OF_FRAME | CAS_TD_INT_ME); 1291 } else 1292 sc->sc_txdescs[txs->txs_firstdesc].cd_flags |= 1293 htole64(cflags | CAS_TD_START_OF_FRAME); 1294 1295 /* Sync the DMA map. */ 1296 bus_dmamap_sync(sc->sc_tdmatag, txs->txs_dmamap, 1297 BUS_DMASYNC_PREWRITE); 1298 1299 #ifdef CAS_DEBUG 1300 CTR4(KTR_CAS, "%s: setting firstdesc=%d, lastdesc=%d, ndescs=%d", 1301 __func__, txs->txs_firstdesc, txs->txs_lastdesc, 1302 txs->txs_ndescs); 1303 #endif 1304 STAILQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 1305 STAILQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1306 txs->txs_mbuf = *m_head; 1307 1308 sc->sc_txnext = CAS_NEXTTX(txs->txs_lastdesc); 1309 sc->sc_txfree -= txs->txs_ndescs; 1310 1311 return (0); 1312 } 1313 1314 static void 1315 cas_init_regs(struct cas_softc *sc) 1316 { 1317 int i; 1318 const u_char *laddr = if_getlladdr(sc->sc_ifp); 1319 1320 CAS_LOCK_ASSERT(sc, MA_OWNED); 1321 1322 /* These registers are not cleared on reset. */ 1323 if ((sc->sc_flags & CAS_INITED) == 0) { 1324 /* magic values */ 1325 CAS_WRITE_4(sc, CAS_MAC_IPG0, 0); 1326 CAS_WRITE_4(sc, CAS_MAC_IPG1, 8); 1327 CAS_WRITE_4(sc, CAS_MAC_IPG2, 4); 1328 1329 /* min frame length */ 1330 CAS_WRITE_4(sc, CAS_MAC_MIN_FRAME, ETHER_MIN_LEN); 1331 /* max frame length and max burst size */ 1332 CAS_WRITE_4(sc, CAS_MAC_MAX_BF, 1333 ((ETHER_MAX_LEN_JUMBO + ETHER_VLAN_ENCAP_LEN) << 1334 CAS_MAC_MAX_BF_FRM_SHFT) | 1335 (0x2000 << CAS_MAC_MAX_BF_BST_SHFT)); 1336 1337 /* more magic values */ 1338 CAS_WRITE_4(sc, CAS_MAC_PREAMBLE_LEN, 0x7); 1339 CAS_WRITE_4(sc, CAS_MAC_JAM_SIZE, 0x4); 1340 CAS_WRITE_4(sc, CAS_MAC_ATTEMPT_LIMIT, 0x10); 1341 CAS_WRITE_4(sc, CAS_MAC_CTRL_TYPE, 0x8808); 1342 1343 /* random number seed */ 1344 CAS_WRITE_4(sc, CAS_MAC_RANDOM_SEED, 1345 ((laddr[5] << 8) | laddr[4]) & 0x3ff); 1346 1347 /* secondary MAC addresses: 0:0:0:0:0:0 */ 1348 for (i = CAS_MAC_ADDR3; i <= CAS_MAC_ADDR41; 1349 i += CAS_MAC_ADDR4 - CAS_MAC_ADDR3) 1350 CAS_WRITE_4(sc, i, 0); 1351 1352 /* MAC control address: 01:80:c2:00:00:01 */ 1353 CAS_WRITE_4(sc, CAS_MAC_ADDR42, 0x0001); 1354 CAS_WRITE_4(sc, CAS_MAC_ADDR43, 0xc200); 1355 CAS_WRITE_4(sc, CAS_MAC_ADDR44, 0x0180); 1356 1357 /* MAC filter address: 0:0:0:0:0:0 */ 1358 CAS_WRITE_4(sc, CAS_MAC_AFILTER0, 0); 1359 CAS_WRITE_4(sc, CAS_MAC_AFILTER1, 0); 1360 CAS_WRITE_4(sc, CAS_MAC_AFILTER2, 0); 1361 CAS_WRITE_4(sc, CAS_MAC_AFILTER_MASK1_2, 0); 1362 CAS_WRITE_4(sc, CAS_MAC_AFILTER_MASK0, 0); 1363 1364 /* Zero the hash table. */ 1365 for (i = CAS_MAC_HASH0; i <= CAS_MAC_HASH15; 1366 i += CAS_MAC_HASH1 - CAS_MAC_HASH0) 1367 CAS_WRITE_4(sc, i, 0); 1368 1369 sc->sc_flags |= CAS_INITED; 1370 } 1371 1372 /* Counters need to be zeroed. */ 1373 CAS_WRITE_4(sc, CAS_MAC_NORM_COLL_CNT, 0); 1374 CAS_WRITE_4(sc, CAS_MAC_FIRST_COLL_CNT, 0); 1375 CAS_WRITE_4(sc, CAS_MAC_EXCESS_COLL_CNT, 0); 1376 CAS_WRITE_4(sc, CAS_MAC_LATE_COLL_CNT, 0); 1377 CAS_WRITE_4(sc, CAS_MAC_DEFER_TMR_CNT, 0); 1378 CAS_WRITE_4(sc, CAS_MAC_PEAK_ATTEMPTS, 0); 1379 CAS_WRITE_4(sc, CAS_MAC_RX_FRAME_COUNT, 0); 1380 CAS_WRITE_4(sc, CAS_MAC_RX_LEN_ERR_CNT, 0); 1381 CAS_WRITE_4(sc, CAS_MAC_RX_ALIGN_ERR, 0); 1382 CAS_WRITE_4(sc, CAS_MAC_RX_CRC_ERR_CNT, 0); 1383 CAS_WRITE_4(sc, CAS_MAC_RX_CODE_VIOL, 0); 1384 1385 /* Set XOFF PAUSE time. */ 1386 CAS_WRITE_4(sc, CAS_MAC_SPC, 0x1BF0 << CAS_MAC_SPC_TIME_SHFT); 1387 1388 /* Set the station address. */ 1389 CAS_WRITE_4(sc, CAS_MAC_ADDR0, (laddr[4] << 8) | laddr[5]); 1390 CAS_WRITE_4(sc, CAS_MAC_ADDR1, (laddr[2] << 8) | laddr[3]); 1391 CAS_WRITE_4(sc, CAS_MAC_ADDR2, (laddr[0] << 8) | laddr[1]); 1392 1393 /* Enable MII outputs. */ 1394 CAS_WRITE_4(sc, CAS_MAC_XIF_CONF, CAS_MAC_XIF_CONF_TX_OE); 1395 } 1396 1397 static void 1398 cas_tx_task(void *arg, int pending __unused) 1399 { 1400 if_t ifp; 1401 1402 ifp = (if_t)arg; 1403 cas_start(ifp); 1404 } 1405 1406 static inline void 1407 cas_txkick(struct cas_softc *sc) 1408 { 1409 1410 /* 1411 * Update the TX kick register. This register has to point to the 1412 * descriptor after the last valid one and for optimum performance 1413 * should be incremented in multiples of 4 (the DMA engine fetches/ 1414 * updates descriptors in batches of 4). 1415 */ 1416 #ifdef CAS_DEBUG 1417 CTR3(KTR_CAS, "%s: %s: kicking TX %d", 1418 device_get_name(sc->sc_dev), __func__, sc->sc_txnext); 1419 #endif 1420 CAS_CDSYNC(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1421 CAS_WRITE_4(sc, CAS_TX_KICK3, sc->sc_txnext); 1422 } 1423 1424 static void 1425 cas_start(if_t ifp) 1426 { 1427 struct cas_softc *sc = if_getsoftc(ifp); 1428 struct mbuf *m; 1429 int kicked, ntx; 1430 1431 CAS_LOCK(sc); 1432 1433 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1434 IFF_DRV_RUNNING || (sc->sc_flags & CAS_LINK) == 0) { 1435 CAS_UNLOCK(sc); 1436 return; 1437 } 1438 1439 if (sc->sc_txfree < CAS_MAXTXFREE / 4) 1440 cas_tint(sc); 1441 1442 #ifdef CAS_DEBUG 1443 CTR4(KTR_CAS, "%s: %s: txfree %d, txnext %d", 1444 device_get_name(sc->sc_dev), __func__, sc->sc_txfree, 1445 sc->sc_txnext); 1446 #endif 1447 ntx = 0; 1448 kicked = 0; 1449 for (; !if_sendq_empty(ifp) && sc->sc_txfree > 1;) { 1450 m = if_dequeue(ifp); 1451 if (m == NULL) 1452 break; 1453 if (cas_load_txmbuf(sc, &m) != 0) { 1454 if (m == NULL) 1455 break; 1456 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 1457 if_sendq_prepend(ifp, m); 1458 break; 1459 } 1460 if ((sc->sc_txnext % 4) == 0) { 1461 cas_txkick(sc); 1462 kicked = 1; 1463 } else 1464 kicked = 0; 1465 ntx++; 1466 BPF_MTAP(ifp, m); 1467 } 1468 1469 if (ntx > 0) { 1470 if (kicked == 0) 1471 cas_txkick(sc); 1472 #ifdef CAS_DEBUG 1473 CTR2(KTR_CAS, "%s: packets enqueued, OWN on %d", 1474 device_get_name(sc->sc_dev), sc->sc_txnext); 1475 #endif 1476 1477 /* Set a watchdog timer in case the chip flakes out. */ 1478 sc->sc_wdog_timer = 5; 1479 #ifdef CAS_DEBUG 1480 CTR3(KTR_CAS, "%s: %s: watchdog %d", 1481 device_get_name(sc->sc_dev), __func__, 1482 sc->sc_wdog_timer); 1483 #endif 1484 } 1485 1486 CAS_UNLOCK(sc); 1487 } 1488 1489 static void 1490 cas_tint(struct cas_softc *sc) 1491 { 1492 if_t ifp = sc->sc_ifp; 1493 struct cas_txsoft *txs; 1494 int progress; 1495 uint32_t txlast; 1496 #ifdef CAS_DEBUG 1497 int i; 1498 1499 CAS_LOCK_ASSERT(sc, MA_OWNED); 1500 1501 CTR2(KTR_CAS, "%s: %s", device_get_name(sc->sc_dev), __func__); 1502 #endif 1503 1504 /* 1505 * Go through our TX list and free mbufs for those 1506 * frames that have been transmitted. 1507 */ 1508 progress = 0; 1509 CAS_CDSYNC(sc, BUS_DMASYNC_POSTREAD); 1510 while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1511 #ifdef CAS_DEBUG 1512 if ((if_getflags(ifp) & IFF_DEBUG) != 0) { 1513 printf(" txsoft %p transmit chain:\n", txs); 1514 for (i = txs->txs_firstdesc;; i = CAS_NEXTTX(i)) { 1515 printf("descriptor %d: ", i); 1516 printf("cd_flags: 0x%016llx\t", 1517 (long long)le64toh( 1518 sc->sc_txdescs[i].cd_flags)); 1519 printf("cd_buf_ptr: 0x%016llx\n", 1520 (long long)le64toh( 1521 sc->sc_txdescs[i].cd_buf_ptr)); 1522 if (i == txs->txs_lastdesc) 1523 break; 1524 } 1525 } 1526 #endif 1527 1528 /* 1529 * In theory, we could harvest some descriptors before 1530 * the ring is empty, but that's a bit complicated. 1531 * 1532 * CAS_TX_COMPn points to the last descriptor 1533 * processed + 1. 1534 */ 1535 txlast = CAS_READ_4(sc, CAS_TX_COMP3); 1536 #ifdef CAS_DEBUG 1537 CTR4(KTR_CAS, "%s: txs->txs_firstdesc = %d, " 1538 "txs->txs_lastdesc = %d, txlast = %d", 1539 __func__, txs->txs_firstdesc, txs->txs_lastdesc, txlast); 1540 #endif 1541 if (txs->txs_firstdesc <= txs->txs_lastdesc) { 1542 if ((txlast >= txs->txs_firstdesc) && 1543 (txlast <= txs->txs_lastdesc)) 1544 break; 1545 } else { 1546 /* Ick -- this command wraps. */ 1547 if ((txlast >= txs->txs_firstdesc) || 1548 (txlast <= txs->txs_lastdesc)) 1549 break; 1550 } 1551 1552 #ifdef CAS_DEBUG 1553 CTR1(KTR_CAS, "%s: releasing a descriptor", __func__); 1554 #endif 1555 STAILQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1556 1557 sc->sc_txfree += txs->txs_ndescs; 1558 1559 bus_dmamap_sync(sc->sc_tdmatag, txs->txs_dmamap, 1560 BUS_DMASYNC_POSTWRITE); 1561 bus_dmamap_unload(sc->sc_tdmatag, txs->txs_dmamap); 1562 if (txs->txs_mbuf != NULL) { 1563 m_freem(txs->txs_mbuf); 1564 txs->txs_mbuf = NULL; 1565 } 1566 1567 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1568 1569 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 1570 progress = 1; 1571 } 1572 1573 #ifdef CAS_DEBUG 1574 CTR5(KTR_CAS, "%s: CAS_TX_SM1 %x CAS_TX_SM2 %x CAS_TX_DESC_BASE %llx " 1575 "CAS_TX_COMP3 %x", 1576 __func__, CAS_READ_4(sc, CAS_TX_SM1), CAS_READ_4(sc, CAS_TX_SM2), 1577 ((long long)CAS_READ_4(sc, CAS_TX_DESC3_BASE_HI) << 32) | 1578 CAS_READ_4(sc, CAS_TX_DESC3_BASE_LO), 1579 CAS_READ_4(sc, CAS_TX_COMP3)); 1580 #endif 1581 1582 if (progress) { 1583 /* We freed some descriptors, so reset IFF_DRV_OACTIVE. */ 1584 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 1585 if (STAILQ_EMPTY(&sc->sc_txdirtyq)) 1586 sc->sc_wdog_timer = 0; 1587 } 1588 1589 #ifdef CAS_DEBUG 1590 CTR3(KTR_CAS, "%s: %s: watchdog %d", 1591 device_get_name(sc->sc_dev), __func__, sc->sc_wdog_timer); 1592 #endif 1593 } 1594 1595 static void 1596 cas_rint_timeout(void *arg) 1597 { 1598 struct epoch_tracker et; 1599 struct cas_softc *sc = arg; 1600 1601 CAS_LOCK_ASSERT(sc, MA_OWNED); 1602 1603 NET_EPOCH_ENTER(et); 1604 cas_rint(sc); 1605 NET_EPOCH_EXIT(et); 1606 } 1607 1608 static void 1609 cas_rint(struct cas_softc *sc) 1610 { 1611 struct cas_rxdsoft *rxds, *rxds2; 1612 if_t ifp = sc->sc_ifp; 1613 struct mbuf *m, *m2; 1614 uint64_t word1, word2, word3 __unused, word4; 1615 uint32_t rxhead; 1616 u_int idx, idx2, len, off, skip; 1617 1618 CAS_LOCK_ASSERT(sc, MA_OWNED); 1619 1620 callout_stop(&sc->sc_rx_ch); 1621 1622 #ifdef CAS_DEBUG 1623 CTR2(KTR_CAS, "%s: %s", device_get_name(sc->sc_dev), __func__); 1624 #endif 1625 1626 #define PRINTWORD(n, delimiter) \ 1627 printf("word ## n: 0x%016llx%c", (long long)word ## n, delimiter) 1628 1629 #define SKIPASSERT(n) \ 1630 KASSERT(sc->sc_rxcomps[sc->sc_rxcptr].crc_word ## n == 0, \ 1631 ("%s: word ## n not 0", __func__)) 1632 1633 #define WORDTOH(n) \ 1634 word ## n = le64toh(sc->sc_rxcomps[sc->sc_rxcptr].crc_word ## n) 1635 1636 /* 1637 * Read the completion head register once. This limits 1638 * how long the following loop can execute. 1639 */ 1640 rxhead = CAS_READ_4(sc, CAS_RX_COMP_HEAD); 1641 #ifdef CAS_DEBUG 1642 CTR4(KTR_CAS, "%s: sc->sc_rxcptr %d, sc->sc_rxdptr %d, head %d", 1643 __func__, sc->sc_rxcptr, sc->sc_rxdptr, rxhead); 1644 #endif 1645 skip = 0; 1646 CAS_CDSYNC(sc, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1647 for (; sc->sc_rxcptr != rxhead; 1648 sc->sc_rxcptr = CAS_NEXTRXCOMP(sc->sc_rxcptr)) { 1649 if (skip != 0) { 1650 SKIPASSERT(1); 1651 SKIPASSERT(2); 1652 SKIPASSERT(3); 1653 1654 --skip; 1655 goto skip; 1656 } 1657 1658 WORDTOH(1); 1659 WORDTOH(2); 1660 WORDTOH(3); 1661 WORDTOH(4); 1662 1663 #ifdef CAS_DEBUG 1664 if ((if_getflags(ifp) & IFF_DEBUG) != 0) { 1665 printf(" completion %d: ", sc->sc_rxcptr); 1666 PRINTWORD(1, '\t'); 1667 PRINTWORD(2, '\t'); 1668 PRINTWORD(3, '\t'); 1669 PRINTWORD(4, '\n'); 1670 } 1671 #endif 1672 1673 if (__predict_false( 1674 (word1 & CAS_RC1_TYPE_MASK) == CAS_RC1_TYPE_HW || 1675 (word4 & CAS_RC4_ZERO) != 0)) { 1676 /* 1677 * The descriptor is still marked as owned, although 1678 * it is supposed to have completed. This has been 1679 * observed on some machines. Just exiting here 1680 * might leave the packet sitting around until another 1681 * one arrives to trigger a new interrupt, which is 1682 * generally undesirable, so set up a timeout. 1683 */ 1684 callout_reset(&sc->sc_rx_ch, CAS_RXOWN_TICKS, 1685 cas_rint_timeout, sc); 1686 break; 1687 } 1688 1689 if (__predict_false( 1690 (word4 & (CAS_RC4_BAD | CAS_RC4_LEN_MMATCH)) != 0)) { 1691 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 1692 device_printf(sc->sc_dev, 1693 "receive error: CRC error\n"); 1694 continue; 1695 } 1696 1697 KASSERT(CAS_GET(word1, CAS_RC1_DATA_SIZE) == 0 || 1698 CAS_GET(word2, CAS_RC2_HDR_SIZE) == 0, 1699 ("%s: data and header present", __func__)); 1700 KASSERT((word1 & CAS_RC1_SPLIT_PKT) == 0 || 1701 CAS_GET(word2, CAS_RC2_HDR_SIZE) == 0, 1702 ("%s: split and header present", __func__)); 1703 KASSERT(CAS_GET(word1, CAS_RC1_DATA_SIZE) == 0 || 1704 (word1 & CAS_RC1_RELEASE_HDR) == 0, 1705 ("%s: data present but header release", __func__)); 1706 KASSERT(CAS_GET(word2, CAS_RC2_HDR_SIZE) == 0 || 1707 (word1 & CAS_RC1_RELEASE_DATA) == 0, 1708 ("%s: header present but data release", __func__)); 1709 1710 if ((len = CAS_GET(word2, CAS_RC2_HDR_SIZE)) != 0) { 1711 idx = CAS_GET(word2, CAS_RC2_HDR_INDEX); 1712 off = CAS_GET(word2, CAS_RC2_HDR_OFF); 1713 #ifdef CAS_DEBUG 1714 CTR4(KTR_CAS, "%s: hdr at idx %d, off %d, len %d", 1715 __func__, idx, off, len); 1716 #endif 1717 rxds = &sc->sc_rxdsoft[idx]; 1718 MGETHDR(m, M_NOWAIT, MT_DATA); 1719 if (m != NULL) { 1720 refcount_acquire(&rxds->rxds_refcount); 1721 bus_dmamap_sync(sc->sc_rdmatag, 1722 rxds->rxds_dmamap, BUS_DMASYNC_POSTREAD); 1723 m_extadd(m, (char *)rxds->rxds_buf + 1724 off * 256 + ETHER_ALIGN, len, cas_free, 1725 sc, (void *)(uintptr_t)idx, 1726 M_RDONLY, EXT_NET_DRV); 1727 if ((m->m_flags & M_EXT) == 0) { 1728 m_freem(m); 1729 m = NULL; 1730 } 1731 } 1732 if (m != NULL) { 1733 m->m_pkthdr.rcvif = ifp; 1734 m->m_pkthdr.len = m->m_len = len; 1735 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 1736 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0) 1737 cas_rxcksum(m, CAS_GET(word4, 1738 CAS_RC4_TCP_CSUM)); 1739 /* Pass it on. */ 1740 CAS_UNLOCK(sc); 1741 if_input(ifp, m); 1742 CAS_LOCK(sc); 1743 } else 1744 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 1745 1746 if ((word1 & CAS_RC1_RELEASE_HDR) != 0 && 1747 refcount_release(&rxds->rxds_refcount) != 0) 1748 cas_add_rxdesc(sc, idx); 1749 } else if ((len = CAS_GET(word1, CAS_RC1_DATA_SIZE)) != 0) { 1750 idx = CAS_GET(word1, CAS_RC1_DATA_INDEX); 1751 off = CAS_GET(word1, CAS_RC1_DATA_OFF); 1752 #ifdef CAS_DEBUG 1753 CTR4(KTR_CAS, "%s: data at idx %d, off %d, len %d", 1754 __func__, idx, off, len); 1755 #endif 1756 rxds = &sc->sc_rxdsoft[idx]; 1757 MGETHDR(m, M_NOWAIT, MT_DATA); 1758 if (m != NULL) { 1759 refcount_acquire(&rxds->rxds_refcount); 1760 off += ETHER_ALIGN; 1761 m->m_len = min(CAS_PAGE_SIZE - off, len); 1762 bus_dmamap_sync(sc->sc_rdmatag, 1763 rxds->rxds_dmamap, BUS_DMASYNC_POSTREAD); 1764 m_extadd(m, (char *)rxds->rxds_buf + off, 1765 m->m_len, cas_free, sc, 1766 (void *)(uintptr_t)idx, M_RDONLY, 1767 EXT_NET_DRV); 1768 if ((m->m_flags & M_EXT) == 0) { 1769 m_freem(m); 1770 m = NULL; 1771 } 1772 } 1773 idx2 = 0; 1774 m2 = NULL; 1775 rxds2 = NULL; 1776 if ((word1 & CAS_RC1_SPLIT_PKT) != 0) { 1777 KASSERT((word1 & CAS_RC1_RELEASE_NEXT) != 0, 1778 ("%s: split but no release next", 1779 __func__)); 1780 1781 idx2 = CAS_GET(word2, CAS_RC2_NEXT_INDEX); 1782 #ifdef CAS_DEBUG 1783 CTR2(KTR_CAS, "%s: split at idx %d", 1784 __func__, idx2); 1785 #endif 1786 rxds2 = &sc->sc_rxdsoft[idx2]; 1787 if (m != NULL) { 1788 MGET(m2, M_NOWAIT, MT_DATA); 1789 if (m2 != NULL) { 1790 refcount_acquire( 1791 &rxds2->rxds_refcount); 1792 m2->m_len = len - m->m_len; 1793 bus_dmamap_sync( 1794 sc->sc_rdmatag, 1795 rxds2->rxds_dmamap, 1796 BUS_DMASYNC_POSTREAD); 1797 m_extadd(m2, 1798 (char *)rxds2->rxds_buf, 1799 m2->m_len, cas_free, sc, 1800 (void *)(uintptr_t)idx2, 1801 M_RDONLY, EXT_NET_DRV); 1802 if ((m2->m_flags & M_EXT) == 1803 0) { 1804 m_freem(m2); 1805 m2 = NULL; 1806 } 1807 } 1808 } 1809 if (m2 != NULL) 1810 m->m_next = m2; 1811 else if (m != NULL) { 1812 m_freem(m); 1813 m = NULL; 1814 } 1815 } 1816 if (m != NULL) { 1817 m->m_pkthdr.rcvif = ifp; 1818 m->m_pkthdr.len = len; 1819 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 1820 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0) 1821 cas_rxcksum(m, CAS_GET(word4, 1822 CAS_RC4_TCP_CSUM)); 1823 /* Pass it on. */ 1824 CAS_UNLOCK(sc); 1825 if_input(ifp, m); 1826 CAS_LOCK(sc); 1827 } else 1828 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 1829 1830 if ((word1 & CAS_RC1_RELEASE_DATA) != 0 && 1831 refcount_release(&rxds->rxds_refcount) != 0) 1832 cas_add_rxdesc(sc, idx); 1833 if ((word1 & CAS_RC1_SPLIT_PKT) != 0 && 1834 refcount_release(&rxds2->rxds_refcount) != 0) 1835 cas_add_rxdesc(sc, idx2); 1836 } 1837 1838 skip = CAS_GET(word1, CAS_RC1_SKIP); 1839 1840 skip: 1841 cas_rxcompinit(&sc->sc_rxcomps[sc->sc_rxcptr]); 1842 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) 1843 break; 1844 } 1845 CAS_CDSYNC(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1846 CAS_WRITE_4(sc, CAS_RX_COMP_TAIL, sc->sc_rxcptr); 1847 1848 #undef PRINTWORD 1849 #undef SKIPASSERT 1850 #undef WORDTOH 1851 1852 #ifdef CAS_DEBUG 1853 CTR4(KTR_CAS, "%s: done sc->sc_rxcptr %d, sc->sc_rxdptr %d, head %d", 1854 __func__, sc->sc_rxcptr, sc->sc_rxdptr, 1855 CAS_READ_4(sc, CAS_RX_COMP_HEAD)); 1856 #endif 1857 } 1858 1859 static void 1860 cas_free(struct mbuf *m) 1861 { 1862 struct cas_rxdsoft *rxds; 1863 struct cas_softc *sc; 1864 u_int idx, locked; 1865 1866 sc = m->m_ext.ext_arg1; 1867 idx = (uintptr_t)m->m_ext.ext_arg2; 1868 rxds = &sc->sc_rxdsoft[idx]; 1869 if (refcount_release(&rxds->rxds_refcount) == 0) 1870 return; 1871 1872 /* 1873 * NB: this function can be called via m_freem(9) within 1874 * this driver! 1875 */ 1876 if ((locked = CAS_LOCK_OWNED(sc)) == 0) 1877 CAS_LOCK(sc); 1878 cas_add_rxdesc(sc, idx); 1879 if (locked == 0) 1880 CAS_UNLOCK(sc); 1881 } 1882 1883 static inline void 1884 cas_add_rxdesc(struct cas_softc *sc, u_int idx) 1885 { 1886 1887 CAS_LOCK_ASSERT(sc, MA_OWNED); 1888 1889 bus_dmamap_sync(sc->sc_rdmatag, sc->sc_rxdsoft[idx].rxds_dmamap, 1890 BUS_DMASYNC_PREREAD); 1891 CAS_UPDATE_RXDESC(sc, sc->sc_rxdptr, idx); 1892 sc->sc_rxdptr = CAS_NEXTRXDESC(sc->sc_rxdptr); 1893 1894 /* 1895 * Update the RX kick register. This register has to point to the 1896 * descriptor after the last valid one (before the current batch) 1897 * and for optimum performance should be incremented in multiples 1898 * of 4 (the DMA engine fetches/updates descriptors in batches of 4). 1899 */ 1900 if ((sc->sc_rxdptr % 4) == 0) { 1901 CAS_CDSYNC(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1902 CAS_WRITE_4(sc, CAS_RX_KICK, 1903 (sc->sc_rxdptr + CAS_NRXDESC - 4) & CAS_NRXDESC_MASK); 1904 } 1905 } 1906 1907 static void 1908 cas_eint(struct cas_softc *sc, u_int status) 1909 { 1910 if_t ifp = sc->sc_ifp; 1911 1912 CAS_LOCK_ASSERT(sc, MA_OWNED); 1913 1914 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 1915 1916 device_printf(sc->sc_dev, "%s: status 0x%x", __func__, status); 1917 if ((status & CAS_INTR_PCI_ERROR_INT) != 0) { 1918 status = CAS_READ_4(sc, CAS_ERROR_STATUS); 1919 printf(", PCI bus error 0x%x", status); 1920 if ((status & CAS_ERROR_OTHER) != 0) { 1921 status = pci_read_config(sc->sc_dev, PCIR_STATUS, 2); 1922 printf(", PCI status 0x%x", status); 1923 pci_write_config(sc->sc_dev, PCIR_STATUS, status, 2); 1924 } 1925 } 1926 printf("\n"); 1927 1928 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1929 cas_init_locked(sc); 1930 if (!if_sendq_empty(ifp)) 1931 taskqueue_enqueue(sc->sc_tq, &sc->sc_tx_task); 1932 } 1933 1934 static int 1935 cas_intr(void *v) 1936 { 1937 struct cas_softc *sc = v; 1938 1939 if (__predict_false((CAS_READ_4(sc, CAS_STATUS_ALIAS) & 1940 CAS_INTR_SUMMARY) == 0)) 1941 return (FILTER_STRAY); 1942 1943 /* Disable interrupts. */ 1944 CAS_WRITE_4(sc, CAS_INTMASK, 0xffffffff); 1945 taskqueue_enqueue(sc->sc_tq, &sc->sc_intr_task); 1946 1947 return (FILTER_HANDLED); 1948 } 1949 1950 static void 1951 cas_intr_task(void *arg, int pending __unused) 1952 { 1953 struct cas_softc *sc = arg; 1954 if_t ifp = sc->sc_ifp; 1955 uint32_t status, status2; 1956 1957 CAS_LOCK_ASSERT(sc, MA_NOTOWNED); 1958 1959 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) 1960 return; 1961 1962 status = CAS_READ_4(sc, CAS_STATUS); 1963 if (__predict_false((status & CAS_INTR_SUMMARY) == 0)) 1964 goto done; 1965 1966 CAS_LOCK(sc); 1967 #ifdef CAS_DEBUG 1968 CTR4(KTR_CAS, "%s: %s: cplt %x, status %x", 1969 device_get_name(sc->sc_dev), __func__, 1970 (status >> CAS_STATUS_TX_COMP3_SHFT), (u_int)status); 1971 1972 /* 1973 * PCS interrupts must be cleared, otherwise no traffic is passed! 1974 */ 1975 if ((status & CAS_INTR_PCS_INT) != 0) { 1976 status2 = 1977 CAS_READ_4(sc, CAS_PCS_INTR_STATUS) | 1978 CAS_READ_4(sc, CAS_PCS_INTR_STATUS); 1979 if ((status2 & CAS_PCS_INTR_LINK) != 0) 1980 device_printf(sc->sc_dev, 1981 "%s: PCS link status changed\n", __func__); 1982 } 1983 if ((status & CAS_MAC_CTRL_STATUS) != 0) { 1984 status2 = CAS_READ_4(sc, CAS_MAC_CTRL_STATUS); 1985 if ((status2 & CAS_MAC_CTRL_PAUSE) != 0) 1986 device_printf(sc->sc_dev, 1987 "%s: PAUSE received (PAUSE time %d slots)\n", 1988 __func__, 1989 (status2 & CAS_MAC_CTRL_STATUS_PT_MASK) >> 1990 CAS_MAC_CTRL_STATUS_PT_SHFT); 1991 if ((status2 & CAS_MAC_CTRL_PAUSE) != 0) 1992 device_printf(sc->sc_dev, 1993 "%s: transited to PAUSE state\n", __func__); 1994 if ((status2 & CAS_MAC_CTRL_NON_PAUSE) != 0) 1995 device_printf(sc->sc_dev, 1996 "%s: transited to non-PAUSE state\n", __func__); 1997 } 1998 if ((status & CAS_INTR_MIF) != 0) 1999 device_printf(sc->sc_dev, "%s: MIF interrupt\n", __func__); 2000 #endif 2001 2002 if (__predict_false((status & 2003 (CAS_INTR_TX_TAG_ERR | CAS_INTR_RX_TAG_ERR | 2004 CAS_INTR_RX_LEN_MMATCH | CAS_INTR_PCI_ERROR_INT)) != 0)) { 2005 cas_eint(sc, status); 2006 CAS_UNLOCK(sc); 2007 return; 2008 } 2009 2010 if (__predict_false(status & CAS_INTR_TX_MAC_INT)) { 2011 status2 = CAS_READ_4(sc, CAS_MAC_TX_STATUS); 2012 if ((status2 & 2013 (CAS_MAC_TX_UNDERRUN | CAS_MAC_TX_MAX_PKT_ERR)) != 0) 2014 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 2015 else if ((status2 & ~CAS_MAC_TX_FRAME_XMTD) != 0) 2016 device_printf(sc->sc_dev, 2017 "MAC TX fault, status %x\n", status2); 2018 } 2019 2020 if (__predict_false(status & CAS_INTR_RX_MAC_INT)) { 2021 status2 = CAS_READ_4(sc, CAS_MAC_RX_STATUS); 2022 if ((status2 & CAS_MAC_RX_OVERFLOW) != 0) 2023 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 2024 else if ((status2 & ~CAS_MAC_RX_FRAME_RCVD) != 0) 2025 device_printf(sc->sc_dev, 2026 "MAC RX fault, status %x\n", status2); 2027 } 2028 2029 if ((status & 2030 (CAS_INTR_RX_DONE | CAS_INTR_RX_BUF_NA | CAS_INTR_RX_COMP_FULL | 2031 CAS_INTR_RX_BUF_AEMPTY | CAS_INTR_RX_COMP_AFULL)) != 0) { 2032 cas_rint(sc); 2033 #ifdef CAS_DEBUG 2034 if (__predict_false((status & 2035 (CAS_INTR_RX_BUF_NA | CAS_INTR_RX_COMP_FULL | 2036 CAS_INTR_RX_BUF_AEMPTY | CAS_INTR_RX_COMP_AFULL)) != 0)) 2037 device_printf(sc->sc_dev, 2038 "RX fault, status %x\n", status); 2039 #endif 2040 } 2041 2042 if ((status & 2043 (CAS_INTR_TX_INT_ME | CAS_INTR_TX_ALL | CAS_INTR_TX_DONE)) != 0) 2044 cas_tint(sc); 2045 2046 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) { 2047 CAS_UNLOCK(sc); 2048 return; 2049 } else if (!if_sendq_empty(ifp)) 2050 taskqueue_enqueue(sc->sc_tq, &sc->sc_tx_task); 2051 CAS_UNLOCK(sc); 2052 2053 status = CAS_READ_4(sc, CAS_STATUS_ALIAS); 2054 if (__predict_false((status & CAS_INTR_SUMMARY) != 0)) { 2055 taskqueue_enqueue(sc->sc_tq, &sc->sc_intr_task); 2056 return; 2057 } 2058 2059 done: 2060 /* Re-enable interrupts. */ 2061 CAS_WRITE_4(sc, CAS_INTMASK, 2062 ~(CAS_INTR_TX_INT_ME | CAS_INTR_TX_TAG_ERR | 2063 CAS_INTR_RX_DONE | CAS_INTR_RX_BUF_NA | CAS_INTR_RX_TAG_ERR | 2064 CAS_INTR_RX_COMP_FULL | CAS_INTR_RX_BUF_AEMPTY | 2065 CAS_INTR_RX_COMP_AFULL | CAS_INTR_RX_LEN_MMATCH | 2066 CAS_INTR_PCI_ERROR_INT 2067 #ifdef CAS_DEBUG 2068 | CAS_INTR_PCS_INT | CAS_INTR_MIF 2069 #endif 2070 )); 2071 } 2072 2073 static void 2074 cas_watchdog(struct cas_softc *sc) 2075 { 2076 if_t ifp = sc->sc_ifp; 2077 2078 CAS_LOCK_ASSERT(sc, MA_OWNED); 2079 2080 #ifdef CAS_DEBUG 2081 CTR4(KTR_CAS, 2082 "%s: CAS_RX_CONF %x CAS_MAC_RX_STATUS %x CAS_MAC_RX_CONF %x", 2083 __func__, CAS_READ_4(sc, CAS_RX_CONF), 2084 CAS_READ_4(sc, CAS_MAC_RX_STATUS), 2085 CAS_READ_4(sc, CAS_MAC_RX_CONF)); 2086 CTR4(KTR_CAS, 2087 "%s: CAS_TX_CONF %x CAS_MAC_TX_STATUS %x CAS_MAC_TX_CONF %x", 2088 __func__, CAS_READ_4(sc, CAS_TX_CONF), 2089 CAS_READ_4(sc, CAS_MAC_TX_STATUS), 2090 CAS_READ_4(sc, CAS_MAC_TX_CONF)); 2091 #endif 2092 2093 if (sc->sc_wdog_timer == 0 || --sc->sc_wdog_timer != 0) 2094 return; 2095 2096 if ((sc->sc_flags & CAS_LINK) != 0) 2097 device_printf(sc->sc_dev, "device timeout\n"); 2098 else if (bootverbose) 2099 device_printf(sc->sc_dev, "device timeout (no link)\n"); 2100 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 2101 2102 /* Try to get more packets going. */ 2103 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 2104 cas_init_locked(sc); 2105 if (!if_sendq_empty(ifp)) 2106 taskqueue_enqueue(sc->sc_tq, &sc->sc_tx_task); 2107 } 2108 2109 static void 2110 cas_mifinit(struct cas_softc *sc) 2111 { 2112 2113 /* Configure the MIF in frame mode. */ 2114 CAS_WRITE_4(sc, CAS_MIF_CONF, 2115 CAS_READ_4(sc, CAS_MIF_CONF) & ~CAS_MIF_CONF_BB_MODE); 2116 CAS_BARRIER(sc, CAS_MIF_CONF, 4, 2117 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 2118 } 2119 2120 /* 2121 * MII interface 2122 * 2123 * The MII interface supports at least three different operating modes: 2124 * 2125 * Bitbang mode is implemented using data, clock and output enable registers. 2126 * 2127 * Frame mode is implemented by loading a complete frame into the frame 2128 * register and polling the valid bit for completion. 2129 * 2130 * Polling mode uses the frame register but completion is indicated by 2131 * an interrupt. 2132 * 2133 */ 2134 static int 2135 cas_mii_readreg(device_t dev, int phy, int reg) 2136 { 2137 struct cas_softc *sc; 2138 int n; 2139 uint32_t v; 2140 2141 #ifdef CAS_DEBUG_PHY 2142 printf("%s: phy %d reg %d\n", __func__, phy, reg); 2143 #endif 2144 2145 sc = device_get_softc(dev); 2146 if ((sc->sc_flags & CAS_SERDES) != 0) { 2147 switch (reg) { 2148 case MII_BMCR: 2149 reg = CAS_PCS_CTRL; 2150 break; 2151 case MII_BMSR: 2152 reg = CAS_PCS_STATUS; 2153 break; 2154 case MII_PHYIDR1: 2155 case MII_PHYIDR2: 2156 return (0); 2157 case MII_ANAR: 2158 reg = CAS_PCS_ANAR; 2159 break; 2160 case MII_ANLPAR: 2161 reg = CAS_PCS_ANLPAR; 2162 break; 2163 case MII_EXTSR: 2164 return (EXTSR_1000XFDX | EXTSR_1000XHDX); 2165 default: 2166 device_printf(sc->sc_dev, 2167 "%s: unhandled register %d\n", __func__, reg); 2168 return (0); 2169 } 2170 return (CAS_READ_4(sc, reg)); 2171 } 2172 2173 /* Construct the frame command. */ 2174 v = CAS_MIF_FRAME_READ | 2175 (phy << CAS_MIF_FRAME_PHY_SHFT) | 2176 (reg << CAS_MIF_FRAME_REG_SHFT); 2177 2178 CAS_WRITE_4(sc, CAS_MIF_FRAME, v); 2179 CAS_BARRIER(sc, CAS_MIF_FRAME, 4, 2180 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 2181 for (n = 0; n < 100; n++) { 2182 DELAY(1); 2183 v = CAS_READ_4(sc, CAS_MIF_FRAME); 2184 if (v & CAS_MIF_FRAME_TA_LSB) 2185 return (v & CAS_MIF_FRAME_DATA); 2186 } 2187 2188 device_printf(sc->sc_dev, "%s: timed out\n", __func__); 2189 return (0); 2190 } 2191 2192 static int 2193 cas_mii_writereg(device_t dev, int phy, int reg, int val) 2194 { 2195 struct cas_softc *sc; 2196 int n; 2197 uint32_t v; 2198 2199 #ifdef CAS_DEBUG_PHY 2200 printf("%s: phy %d reg %d val %x\n", phy, reg, val, __func__); 2201 #endif 2202 2203 sc = device_get_softc(dev); 2204 if ((sc->sc_flags & CAS_SERDES) != 0) { 2205 switch (reg) { 2206 case MII_BMSR: 2207 reg = CAS_PCS_STATUS; 2208 break; 2209 case MII_BMCR: 2210 reg = CAS_PCS_CTRL; 2211 if ((val & CAS_PCS_CTRL_RESET) == 0) 2212 break; 2213 CAS_WRITE_4(sc, CAS_PCS_CTRL, val); 2214 CAS_BARRIER(sc, CAS_PCS_CTRL, 4, 2215 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 2216 if (!cas_bitwait(sc, CAS_PCS_CTRL, 2217 CAS_PCS_CTRL_RESET, 0)) 2218 device_printf(sc->sc_dev, 2219 "cannot reset PCS\n"); 2220 /* FALLTHROUGH */ 2221 case MII_ANAR: 2222 CAS_WRITE_4(sc, CAS_PCS_CONF, 0); 2223 CAS_BARRIER(sc, CAS_PCS_CONF, 4, 2224 BUS_SPACE_BARRIER_WRITE); 2225 CAS_WRITE_4(sc, CAS_PCS_ANAR, val); 2226 CAS_BARRIER(sc, CAS_PCS_ANAR, 4, 2227 BUS_SPACE_BARRIER_WRITE); 2228 CAS_WRITE_4(sc, CAS_PCS_SERDES_CTRL, 2229 CAS_PCS_SERDES_CTRL_ESD); 2230 CAS_BARRIER(sc, CAS_PCS_CONF, 4, 2231 BUS_SPACE_BARRIER_WRITE); 2232 CAS_WRITE_4(sc, CAS_PCS_CONF, 2233 CAS_PCS_CONF_EN); 2234 CAS_BARRIER(sc, CAS_PCS_CONF, 4, 2235 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 2236 return (0); 2237 case MII_ANLPAR: 2238 reg = CAS_PCS_ANLPAR; 2239 break; 2240 default: 2241 device_printf(sc->sc_dev, 2242 "%s: unhandled register %d\n", __func__, reg); 2243 return (0); 2244 } 2245 CAS_WRITE_4(sc, reg, val); 2246 CAS_BARRIER(sc, reg, 4, 2247 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 2248 return (0); 2249 } 2250 2251 /* Construct the frame command. */ 2252 v = CAS_MIF_FRAME_WRITE | 2253 (phy << CAS_MIF_FRAME_PHY_SHFT) | 2254 (reg << CAS_MIF_FRAME_REG_SHFT) | 2255 (val & CAS_MIF_FRAME_DATA); 2256 2257 CAS_WRITE_4(sc, CAS_MIF_FRAME, v); 2258 CAS_BARRIER(sc, CAS_MIF_FRAME, 4, 2259 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 2260 for (n = 0; n < 100; n++) { 2261 DELAY(1); 2262 v = CAS_READ_4(sc, CAS_MIF_FRAME); 2263 if (v & CAS_MIF_FRAME_TA_LSB) 2264 return (1); 2265 } 2266 2267 device_printf(sc->sc_dev, "%s: timed out\n", __func__); 2268 return (0); 2269 } 2270 2271 static void 2272 cas_mii_statchg(device_t dev) 2273 { 2274 struct cas_softc *sc; 2275 if_t ifp; 2276 int gigabit; 2277 uint32_t rxcfg, txcfg, v; 2278 2279 sc = device_get_softc(dev); 2280 ifp = sc->sc_ifp; 2281 2282 CAS_LOCK_ASSERT(sc, MA_OWNED); 2283 2284 #ifdef CAS_DEBUG 2285 if ((if_getflags(ifp) & IFF_DEBUG) != 0) 2286 device_printf(sc->sc_dev, "%s: status changen", __func__); 2287 #endif 2288 2289 if ((sc->sc_mii->mii_media_status & IFM_ACTIVE) != 0 && 2290 IFM_SUBTYPE(sc->sc_mii->mii_media_active) != IFM_NONE) 2291 sc->sc_flags |= CAS_LINK; 2292 else 2293 sc->sc_flags &= ~CAS_LINK; 2294 2295 switch (IFM_SUBTYPE(sc->sc_mii->mii_media_active)) { 2296 case IFM_1000_SX: 2297 case IFM_1000_LX: 2298 case IFM_1000_CX: 2299 case IFM_1000_T: 2300 gigabit = 1; 2301 break; 2302 default: 2303 gigabit = 0; 2304 } 2305 2306 /* 2307 * The configuration done here corresponds to the steps F) and 2308 * G) and as far as enabling of RX and TX MAC goes also step H) 2309 * of the initialization sequence outlined in section 11.2.1 of 2310 * the Cassini+ ASIC Specification. 2311 */ 2312 2313 rxcfg = sc->sc_mac_rxcfg; 2314 rxcfg &= ~CAS_MAC_RX_CONF_CARR; 2315 txcfg = CAS_MAC_TX_CONF_EN_IPG0 | CAS_MAC_TX_CONF_NGU | 2316 CAS_MAC_TX_CONF_NGUL; 2317 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) != 0) 2318 txcfg |= CAS_MAC_TX_CONF_ICARR | CAS_MAC_TX_CONF_ICOLLIS; 2319 else if (gigabit != 0) { 2320 rxcfg |= CAS_MAC_RX_CONF_CARR; 2321 txcfg |= CAS_MAC_TX_CONF_CARR; 2322 } 2323 (void)cas_disable_tx(sc); 2324 CAS_WRITE_4(sc, CAS_MAC_TX_CONF, txcfg); 2325 (void)cas_disable_rx(sc); 2326 CAS_WRITE_4(sc, CAS_MAC_RX_CONF, rxcfg); 2327 2328 v = CAS_READ_4(sc, CAS_MAC_CTRL_CONF) & 2329 ~(CAS_MAC_CTRL_CONF_TXP | CAS_MAC_CTRL_CONF_RXP); 2330 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & 2331 IFM_ETH_RXPAUSE) != 0) 2332 v |= CAS_MAC_CTRL_CONF_RXP; 2333 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & 2334 IFM_ETH_TXPAUSE) != 0) 2335 v |= CAS_MAC_CTRL_CONF_TXP; 2336 CAS_WRITE_4(sc, CAS_MAC_CTRL_CONF, v); 2337 2338 /* 2339 * All supported chips have a bug causing incorrect checksum 2340 * to be calculated when letting them strip the FCS in half- 2341 * duplex mode. In theory we could disable FCS stripping and 2342 * manually adjust the checksum accordingly. It seems to make 2343 * more sense to optimze for the common case and just disable 2344 * hardware checksumming in half-duplex mode though. 2345 */ 2346 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) == 0) { 2347 if_setcapenablebit(ifp, 0, IFCAP_HWCSUM); 2348 if_sethwassist(ifp, 0); 2349 } else if ((sc->sc_flags & CAS_NO_CSUM) == 0) { 2350 if_setcapenable(ifp, if_getcapabilities(ifp)); 2351 if_sethwassist(ifp, CAS_CSUM_FEATURES); 2352 } 2353 2354 if (sc->sc_variant == CAS_SATURN) { 2355 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) == 0) 2356 /* silicon bug workaround */ 2357 CAS_WRITE_4(sc, CAS_MAC_PREAMBLE_LEN, 0x41); 2358 else 2359 CAS_WRITE_4(sc, CAS_MAC_PREAMBLE_LEN, 0x7); 2360 } 2361 2362 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) == 0 && 2363 gigabit != 0) 2364 CAS_WRITE_4(sc, CAS_MAC_SLOT_TIME, 2365 CAS_MAC_SLOT_TIME_CARR); 2366 else 2367 CAS_WRITE_4(sc, CAS_MAC_SLOT_TIME, 2368 CAS_MAC_SLOT_TIME_NORM); 2369 2370 /* XIF Configuration */ 2371 v = CAS_MAC_XIF_CONF_TX_OE | CAS_MAC_XIF_CONF_LNKLED; 2372 if ((sc->sc_flags & CAS_SERDES) == 0) { 2373 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) == 0) 2374 v |= CAS_MAC_XIF_CONF_NOECHO; 2375 v |= CAS_MAC_XIF_CONF_BUF_OE; 2376 } 2377 if (gigabit != 0) 2378 v |= CAS_MAC_XIF_CONF_GMII; 2379 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) != 0) 2380 v |= CAS_MAC_XIF_CONF_FDXLED; 2381 CAS_WRITE_4(sc, CAS_MAC_XIF_CONF, v); 2382 2383 sc->sc_mac_rxcfg = rxcfg; 2384 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0 && 2385 (sc->sc_flags & CAS_LINK) != 0) { 2386 CAS_WRITE_4(sc, CAS_MAC_TX_CONF, 2387 txcfg | CAS_MAC_TX_CONF_EN); 2388 CAS_WRITE_4(sc, CAS_MAC_RX_CONF, 2389 rxcfg | CAS_MAC_RX_CONF_EN); 2390 } 2391 } 2392 2393 static int 2394 cas_mediachange(if_t ifp) 2395 { 2396 struct cas_softc *sc = if_getsoftc(ifp); 2397 int error; 2398 2399 /* XXX add support for serial media. */ 2400 2401 CAS_LOCK(sc); 2402 error = mii_mediachg(sc->sc_mii); 2403 CAS_UNLOCK(sc); 2404 return (error); 2405 } 2406 2407 static void 2408 cas_mediastatus(if_t ifp, struct ifmediareq *ifmr) 2409 { 2410 struct cas_softc *sc = if_getsoftc(ifp); 2411 2412 CAS_LOCK(sc); 2413 if ((if_getflags(ifp) & IFF_UP) == 0) { 2414 CAS_UNLOCK(sc); 2415 return; 2416 } 2417 2418 mii_pollstat(sc->sc_mii); 2419 ifmr->ifm_active = sc->sc_mii->mii_media_active; 2420 ifmr->ifm_status = sc->sc_mii->mii_media_status; 2421 CAS_UNLOCK(sc); 2422 } 2423 2424 static int 2425 cas_ioctl(if_t ifp, u_long cmd, caddr_t data) 2426 { 2427 struct cas_softc *sc = if_getsoftc(ifp); 2428 struct ifreq *ifr = (struct ifreq *)data; 2429 int error; 2430 2431 error = 0; 2432 switch (cmd) { 2433 case SIOCSIFFLAGS: 2434 CAS_LOCK(sc); 2435 if ((if_getflags(ifp) & IFF_UP) != 0) { 2436 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0 && 2437 ((if_getflags(ifp) ^ sc->sc_ifflags) & 2438 (IFF_ALLMULTI | IFF_PROMISC)) != 0) 2439 cas_setladrf(sc); 2440 else 2441 cas_init_locked(sc); 2442 } else if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 2443 cas_stop(ifp); 2444 sc->sc_ifflags = if_getflags(ifp); 2445 CAS_UNLOCK(sc); 2446 break; 2447 case SIOCSIFCAP: 2448 CAS_LOCK(sc); 2449 if ((sc->sc_flags & CAS_NO_CSUM) != 0) { 2450 error = EINVAL; 2451 CAS_UNLOCK(sc); 2452 break; 2453 } 2454 if_setcapenable(ifp, ifr->ifr_reqcap); 2455 if ((if_getcapenable(ifp) & IFCAP_TXCSUM) != 0) 2456 if_sethwassist(ifp, CAS_CSUM_FEATURES); 2457 else 2458 if_sethwassist(ifp, 0); 2459 CAS_UNLOCK(sc); 2460 break; 2461 case SIOCADDMULTI: 2462 case SIOCDELMULTI: 2463 CAS_LOCK(sc); 2464 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 2465 cas_setladrf(sc); 2466 CAS_UNLOCK(sc); 2467 break; 2468 case SIOCSIFMTU: 2469 if ((ifr->ifr_mtu < ETHERMIN) || 2470 (ifr->ifr_mtu > ETHERMTU_JUMBO)) 2471 error = EINVAL; 2472 else 2473 if_setmtu(ifp, ifr->ifr_mtu); 2474 break; 2475 case SIOCGIFMEDIA: 2476 case SIOCSIFMEDIA: 2477 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii->mii_media, cmd); 2478 break; 2479 default: 2480 error = ether_ioctl(ifp, cmd, data); 2481 break; 2482 } 2483 2484 return (error); 2485 } 2486 2487 static u_int 2488 cas_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 2489 { 2490 uint32_t crc, *hash = arg; 2491 2492 crc = ether_crc32_le(LLADDR(sdl), ETHER_ADDR_LEN); 2493 /* We just want the 8 most significant bits. */ 2494 crc >>= 24; 2495 /* Set the corresponding bit in the filter. */ 2496 hash[crc >> 4] |= 1 << (15 - (crc & 15)); 2497 2498 return (1); 2499 } 2500 2501 static void 2502 cas_setladrf(struct cas_softc *sc) 2503 { 2504 if_t ifp = sc->sc_ifp; 2505 int i; 2506 uint32_t hash[16]; 2507 uint32_t v; 2508 2509 CAS_LOCK_ASSERT(sc, MA_OWNED); 2510 2511 /* 2512 * Turn off the RX MAC and the hash filter as required by the Sun 2513 * Cassini programming restrictions. 2514 */ 2515 v = sc->sc_mac_rxcfg & ~(CAS_MAC_RX_CONF_HFILTER | 2516 CAS_MAC_RX_CONF_EN); 2517 CAS_WRITE_4(sc, CAS_MAC_RX_CONF, v); 2518 CAS_BARRIER(sc, CAS_MAC_RX_CONF, 4, 2519 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 2520 if (!cas_bitwait(sc, CAS_MAC_RX_CONF, CAS_MAC_RX_CONF_HFILTER | 2521 CAS_MAC_RX_CONF_EN, 0)) 2522 device_printf(sc->sc_dev, 2523 "cannot disable RX MAC or hash filter\n"); 2524 2525 v &= ~(CAS_MAC_RX_CONF_PROMISC | CAS_MAC_RX_CONF_PGRP); 2526 if ((if_getflags(ifp) & IFF_PROMISC) != 0) { 2527 v |= CAS_MAC_RX_CONF_PROMISC; 2528 goto chipit; 2529 } 2530 if ((if_getflags(ifp) & IFF_ALLMULTI) != 0) { 2531 v |= CAS_MAC_RX_CONF_PGRP; 2532 goto chipit; 2533 } 2534 2535 /* 2536 * Set up multicast address filter by passing all multicast 2537 * addresses through a crc generator, and then using the high 2538 * order 8 bits as an index into the 256 bit logical address 2539 * filter. The high order 4 bits selects the word, while the 2540 * other 4 bits select the bit within the word (where bit 0 2541 * is the MSB). 2542 */ 2543 2544 memset(hash, 0, sizeof(hash)); 2545 if_foreach_llmaddr(ifp, cas_hash_maddr, &hash); 2546 2547 v |= CAS_MAC_RX_CONF_HFILTER; 2548 2549 /* Now load the hash table into the chip (if we are using it). */ 2550 for (i = 0; i < 16; i++) 2551 CAS_WRITE_4(sc, 2552 CAS_MAC_HASH0 + i * (CAS_MAC_HASH1 - CAS_MAC_HASH0), 2553 hash[i]); 2554 2555 chipit: 2556 sc->sc_mac_rxcfg = v; 2557 CAS_WRITE_4(sc, CAS_MAC_RX_CONF, v | CAS_MAC_RX_CONF_EN); 2558 } 2559 2560 static int cas_pci_attach(device_t dev); 2561 static int cas_pci_detach(device_t dev); 2562 static int cas_pci_probe(device_t dev); 2563 static int cas_pci_resume(device_t dev); 2564 static int cas_pci_suspend(device_t dev); 2565 2566 static device_method_t cas_pci_methods[] = { 2567 /* Device interface */ 2568 DEVMETHOD(device_probe, cas_pci_probe), 2569 DEVMETHOD(device_attach, cas_pci_attach), 2570 DEVMETHOD(device_detach, cas_pci_detach), 2571 DEVMETHOD(device_suspend, cas_pci_suspend), 2572 DEVMETHOD(device_resume, cas_pci_resume), 2573 /* Use the suspend handler here, it is all that is required. */ 2574 DEVMETHOD(device_shutdown, cas_pci_suspend), 2575 2576 /* MII interface */ 2577 DEVMETHOD(miibus_readreg, cas_mii_readreg), 2578 DEVMETHOD(miibus_writereg, cas_mii_writereg), 2579 DEVMETHOD(miibus_statchg, cas_mii_statchg), 2580 2581 DEVMETHOD_END 2582 }; 2583 2584 static driver_t cas_pci_driver = { 2585 "cas", 2586 cas_pci_methods, 2587 sizeof(struct cas_softc) 2588 }; 2589 2590 static const struct cas_pci_dev { 2591 uint32_t cpd_devid; 2592 uint8_t cpd_revid; 2593 int cpd_variant; 2594 const char *cpd_desc; 2595 } cas_pci_devlist[] = { 2596 { 0x0035100b, 0x0, CAS_SATURN, "NS DP83065 Saturn Gigabit Ethernet" }, 2597 { 0xabba108e, 0x10, CAS_CASPLUS, "Sun Cassini+ Gigabit Ethernet" }, 2598 { 0xabba108e, 0x0, CAS_CAS, "Sun Cassini Gigabit Ethernet" }, 2599 { 0, 0, 0, NULL } 2600 }; 2601 2602 DRIVER_MODULE(cas, pci, cas_pci_driver, 0, 0); 2603 MODULE_PNP_INFO("W32:vendor/device", pci, cas, cas_pci_devlist, 2604 nitems(cas_pci_devlist) - 1); 2605 DRIVER_MODULE(miibus, cas, miibus_driver, 0, 0); 2606 MODULE_DEPEND(cas, pci, 1, 1, 1); 2607 2608 static int 2609 cas_pci_probe(device_t dev) 2610 { 2611 int i; 2612 2613 for (i = 0; cas_pci_devlist[i].cpd_desc != NULL; i++) { 2614 if (pci_get_devid(dev) == cas_pci_devlist[i].cpd_devid && 2615 pci_get_revid(dev) >= cas_pci_devlist[i].cpd_revid) { 2616 device_set_desc(dev, cas_pci_devlist[i].cpd_desc); 2617 return (BUS_PROBE_DEFAULT); 2618 } 2619 } 2620 2621 return (ENXIO); 2622 } 2623 2624 static struct resource_spec cas_pci_res_spec[] = { 2625 { SYS_RES_IRQ, 0, RF_SHAREABLE | RF_ACTIVE }, /* CAS_RES_INTR */ 2626 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, /* CAS_RES_MEM */ 2627 { -1, 0 } 2628 }; 2629 2630 #define CAS_LOCAL_MAC_ADDRESS "local-mac-address" 2631 #define CAS_PHY_INTERFACE "phy-interface" 2632 #define CAS_PHY_TYPE "phy-type" 2633 #define CAS_PHY_TYPE_PCS "pcs" 2634 2635 static int 2636 cas_pci_attach(device_t dev) 2637 { 2638 char buf[sizeof(CAS_LOCAL_MAC_ADDRESS)]; 2639 struct cas_softc *sc; 2640 int i; 2641 #if !defined(__powerpc__) 2642 u_char enaddr[4][ETHER_ADDR_LEN]; 2643 u_int j, k, lma, pcs[4], phy; 2644 #endif 2645 2646 sc = device_get_softc(dev); 2647 sc->sc_variant = CAS_UNKNOWN; 2648 for (i = 0; cas_pci_devlist[i].cpd_desc != NULL; i++) { 2649 if (pci_get_devid(dev) == cas_pci_devlist[i].cpd_devid && 2650 pci_get_revid(dev) >= cas_pci_devlist[i].cpd_revid) { 2651 sc->sc_variant = cas_pci_devlist[i].cpd_variant; 2652 break; 2653 } 2654 } 2655 if (sc->sc_variant == CAS_UNKNOWN) { 2656 device_printf(dev, "unknown adaptor\n"); 2657 return (ENXIO); 2658 } 2659 2660 /* PCI configuration */ 2661 pci_write_config(dev, PCIR_COMMAND, 2662 pci_read_config(dev, PCIR_COMMAND, 2) | PCIM_CMD_BUSMASTEREN | 2663 PCIM_CMD_MWRICEN | PCIM_CMD_PERRESPEN | PCIM_CMD_SERRESPEN, 2); 2664 2665 sc->sc_dev = dev; 2666 if (sc->sc_variant == CAS_CAS && pci_get_devid(dev) < 0x02) 2667 /* Hardware checksumming may hang TX. */ 2668 sc->sc_flags |= CAS_NO_CSUM; 2669 if (sc->sc_variant == CAS_CASPLUS || sc->sc_variant == CAS_SATURN) 2670 sc->sc_flags |= CAS_REG_PLUS; 2671 if (sc->sc_variant == CAS_CAS || 2672 (sc->sc_variant == CAS_CASPLUS && pci_get_revid(dev) < 0x11)) 2673 sc->sc_flags |= CAS_TABORT; 2674 if (bootverbose) 2675 device_printf(dev, "flags=0x%x\n", sc->sc_flags); 2676 2677 if (bus_alloc_resources(dev, cas_pci_res_spec, sc->sc_res)) { 2678 device_printf(dev, "failed to allocate resources\n"); 2679 bus_release_resources(dev, cas_pci_res_spec, sc->sc_res); 2680 return (ENXIO); 2681 } 2682 2683 CAS_LOCK_INIT(sc, device_get_nameunit(dev)); 2684 2685 #if defined(__powerpc__) 2686 OF_getetheraddr(dev, sc->sc_enaddr); 2687 if (OF_getprop(ofw_bus_get_node(dev), CAS_PHY_INTERFACE, buf, 2688 sizeof(buf)) > 0 || OF_getprop(ofw_bus_get_node(dev), 2689 CAS_PHY_TYPE, buf, sizeof(buf)) > 0) { 2690 buf[sizeof(buf) - 1] = '\0'; 2691 if (strcmp(buf, CAS_PHY_TYPE_PCS) == 0) 2692 sc->sc_flags |= CAS_SERDES; 2693 } 2694 #else 2695 /* 2696 * Dig out VPD (vital product data) and read the MAC address as well 2697 * as the PHY type. The VPD resides in the PCI Expansion ROM (PCI 2698 * FCode) and can't be accessed via the PCI capability pointer. 2699 * SUNW,pci-ce and SUNW,pci-qge use the Enhanced VPD format described 2700 * in the free US Patent 7149820. 2701 */ 2702 2703 #define PCI_ROMHDR_SIZE 0x1c 2704 #define PCI_ROMHDR_SIG 0x00 2705 #define PCI_ROMHDR_SIG_MAGIC 0xaa55 /* little endian */ 2706 #define PCI_ROMHDR_PTR_DATA 0x18 2707 #define PCI_ROM_SIZE 0x18 2708 #define PCI_ROM_SIG 0x00 2709 #define PCI_ROM_SIG_MAGIC 0x52494350 /* "PCIR", endian */ 2710 /* reversed */ 2711 #define PCI_ROM_VENDOR 0x04 2712 #define PCI_ROM_DEVICE 0x06 2713 #define PCI_ROM_PTR_VPD 0x08 2714 #define PCI_VPDRES_BYTE0 0x00 2715 #define PCI_VPDRES_ISLARGE(x) ((x) & 0x80) 2716 #define PCI_VPDRES_LARGE_NAME(x) ((x) & 0x7f) 2717 #define PCI_VPDRES_LARGE_LEN_LSB 0x01 2718 #define PCI_VPDRES_LARGE_LEN_MSB 0x02 2719 #define PCI_VPDRES_LARGE_SIZE 0x03 2720 #define PCI_VPDRES_TYPE_ID_STRING 0x02 /* large */ 2721 #define PCI_VPDRES_TYPE_VPD 0x10 /* large */ 2722 #define PCI_VPD_KEY0 0x00 2723 #define PCI_VPD_KEY1 0x01 2724 #define PCI_VPD_LEN 0x02 2725 #define PCI_VPD_SIZE 0x03 2726 2727 #define CAS_ROM_READ_1(sc, offs) \ 2728 CAS_READ_1((sc), CAS_PCI_ROM_OFFSET + (offs)) 2729 #define CAS_ROM_READ_2(sc, offs) \ 2730 CAS_READ_2((sc), CAS_PCI_ROM_OFFSET + (offs)) 2731 #define CAS_ROM_READ_4(sc, offs) \ 2732 CAS_READ_4((sc), CAS_PCI_ROM_OFFSET + (offs)) 2733 2734 lma = phy = 0; 2735 memset(enaddr, 0, sizeof(enaddr)); 2736 memset(pcs, 0, sizeof(pcs)); 2737 2738 /* Enable PCI Expansion ROM access. */ 2739 CAS_WRITE_4(sc, CAS_BIM_LDEV_OEN, 2740 CAS_BIM_LDEV_OEN_PAD | CAS_BIM_LDEV_OEN_PROM); 2741 2742 /* Read PCI Expansion ROM header. */ 2743 if (CAS_ROM_READ_2(sc, PCI_ROMHDR_SIG) != PCI_ROMHDR_SIG_MAGIC || 2744 (i = CAS_ROM_READ_2(sc, PCI_ROMHDR_PTR_DATA)) < 2745 PCI_ROMHDR_SIZE) { 2746 device_printf(dev, "unexpected PCI Expansion ROM header\n"); 2747 goto fail_prom; 2748 } 2749 2750 /* Read PCI Expansion ROM data. */ 2751 if (CAS_ROM_READ_4(sc, i + PCI_ROM_SIG) != PCI_ROM_SIG_MAGIC || 2752 CAS_ROM_READ_2(sc, i + PCI_ROM_VENDOR) != pci_get_vendor(dev) || 2753 CAS_ROM_READ_2(sc, i + PCI_ROM_DEVICE) != pci_get_device(dev) || 2754 (j = CAS_ROM_READ_2(sc, i + PCI_ROM_PTR_VPD)) < 2755 i + PCI_ROM_SIZE) { 2756 device_printf(dev, "unexpected PCI Expansion ROM data\n"); 2757 goto fail_prom; 2758 } 2759 2760 /* Read PCI VPD. */ 2761 next: 2762 if (PCI_VPDRES_ISLARGE(CAS_ROM_READ_1(sc, 2763 j + PCI_VPDRES_BYTE0)) == 0) { 2764 device_printf(dev, "no large PCI VPD\n"); 2765 goto fail_prom; 2766 } 2767 2768 i = (CAS_ROM_READ_1(sc, j + PCI_VPDRES_LARGE_LEN_MSB) << 8) | 2769 CAS_ROM_READ_1(sc, j + PCI_VPDRES_LARGE_LEN_LSB); 2770 switch (PCI_VPDRES_LARGE_NAME(CAS_ROM_READ_1(sc, 2771 j + PCI_VPDRES_BYTE0))) { 2772 case PCI_VPDRES_TYPE_ID_STRING: 2773 /* Skip identifier string. */ 2774 j += PCI_VPDRES_LARGE_SIZE + i; 2775 goto next; 2776 case PCI_VPDRES_TYPE_VPD: 2777 for (j += PCI_VPDRES_LARGE_SIZE; i > 0; 2778 i -= PCI_VPD_SIZE + CAS_ROM_READ_1(sc, j + PCI_VPD_LEN), 2779 j += PCI_VPD_SIZE + CAS_ROM_READ_1(sc, j + PCI_VPD_LEN)) { 2780 if (CAS_ROM_READ_1(sc, j + PCI_VPD_KEY0) != 'Z') 2781 /* no Enhanced VPD */ 2782 continue; 2783 if (CAS_ROM_READ_1(sc, j + PCI_VPD_SIZE) != 'I') 2784 /* no instance property */ 2785 continue; 2786 if (CAS_ROM_READ_1(sc, j + PCI_VPD_SIZE + 3) == 'B') { 2787 /* byte array */ 2788 if (CAS_ROM_READ_1(sc, 2789 j + PCI_VPD_SIZE + 4) != ETHER_ADDR_LEN) 2790 continue; 2791 bus_read_region_1(sc->sc_res[CAS_RES_MEM], 2792 CAS_PCI_ROM_OFFSET + j + PCI_VPD_SIZE + 5, 2793 buf, sizeof(buf)); 2794 buf[sizeof(buf) - 1] = '\0'; 2795 if (strcmp(buf, CAS_LOCAL_MAC_ADDRESS) != 0) 2796 continue; 2797 bus_read_region_1(sc->sc_res[CAS_RES_MEM], 2798 CAS_PCI_ROM_OFFSET + j + PCI_VPD_SIZE + 2799 5 + sizeof(CAS_LOCAL_MAC_ADDRESS), 2800 enaddr[lma], sizeof(enaddr[lma])); 2801 lma++; 2802 if (lma == 4 && phy == 4) 2803 break; 2804 } else if (CAS_ROM_READ_1(sc, j + PCI_VPD_SIZE + 3) == 2805 'S') { 2806 /* string */ 2807 if (CAS_ROM_READ_1(sc, 2808 j + PCI_VPD_SIZE + 4) != 2809 sizeof(CAS_PHY_TYPE_PCS)) 2810 continue; 2811 bus_read_region_1(sc->sc_res[CAS_RES_MEM], 2812 CAS_PCI_ROM_OFFSET + j + PCI_VPD_SIZE + 5, 2813 buf, sizeof(buf)); 2814 buf[sizeof(buf) - 1] = '\0'; 2815 if (strcmp(buf, CAS_PHY_INTERFACE) == 0) 2816 k = sizeof(CAS_PHY_INTERFACE); 2817 else if (strcmp(buf, CAS_PHY_TYPE) == 0) 2818 k = sizeof(CAS_PHY_TYPE); 2819 else 2820 continue; 2821 bus_read_region_1(sc->sc_res[CAS_RES_MEM], 2822 CAS_PCI_ROM_OFFSET + j + PCI_VPD_SIZE + 2823 5 + k, buf, sizeof(buf)); 2824 buf[sizeof(buf) - 1] = '\0'; 2825 if (strcmp(buf, CAS_PHY_TYPE_PCS) == 0) 2826 pcs[phy] = 1; 2827 phy++; 2828 if (lma == 4 && phy == 4) 2829 break; 2830 } 2831 } 2832 break; 2833 default: 2834 device_printf(dev, "unexpected PCI VPD\n"); 2835 goto fail_prom; 2836 } 2837 2838 fail_prom: 2839 CAS_WRITE_4(sc, CAS_BIM_LDEV_OEN, 0); 2840 2841 if (lma == 0) { 2842 device_printf(dev, "could not determine Ethernet address\n"); 2843 goto fail; 2844 } 2845 i = 0; 2846 if (lma > 1 && pci_get_slot(dev) < nitems(enaddr)) 2847 i = pci_get_slot(dev); 2848 memcpy(sc->sc_enaddr, enaddr[i], ETHER_ADDR_LEN); 2849 2850 if (phy == 0) { 2851 device_printf(dev, "could not determine PHY type\n"); 2852 goto fail; 2853 } 2854 i = 0; 2855 if (phy > 1 && pci_get_slot(dev) < nitems(pcs)) 2856 i = pci_get_slot(dev); 2857 if (pcs[i] != 0) 2858 sc->sc_flags |= CAS_SERDES; 2859 #endif 2860 2861 if (cas_attach(sc) != 0) { 2862 device_printf(dev, "could not be attached\n"); 2863 goto fail; 2864 } 2865 2866 if (bus_setup_intr(dev, sc->sc_res[CAS_RES_INTR], INTR_TYPE_NET | 2867 INTR_MPSAFE, cas_intr, NULL, sc, &sc->sc_ih) != 0) { 2868 device_printf(dev, "failed to set up interrupt\n"); 2869 cas_detach(sc); 2870 goto fail; 2871 } 2872 return (0); 2873 2874 fail: 2875 CAS_LOCK_DESTROY(sc); 2876 bus_release_resources(dev, cas_pci_res_spec, sc->sc_res); 2877 return (ENXIO); 2878 } 2879 2880 static int 2881 cas_pci_detach(device_t dev) 2882 { 2883 struct cas_softc *sc; 2884 2885 sc = device_get_softc(dev); 2886 bus_teardown_intr(dev, sc->sc_res[CAS_RES_INTR], sc->sc_ih); 2887 cas_detach(sc); 2888 CAS_LOCK_DESTROY(sc); 2889 bus_release_resources(dev, cas_pci_res_spec, sc->sc_res); 2890 return (0); 2891 } 2892 2893 static int 2894 cas_pci_suspend(device_t dev) 2895 { 2896 2897 cas_suspend(device_get_softc(dev)); 2898 return (0); 2899 } 2900 2901 static int 2902 cas_pci_resume(device_t dev) 2903 { 2904 2905 cas_resume(device_get_softc(dev)); 2906 return (0); 2907 } 2908