1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (C) 2001 Eduardo Horvath. 5 * Copyright (c) 2001-2003 Thomas Moestl 6 * Copyright (c) 2007-2009 Marius Strobl <marius@FreeBSD.org> 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 * 30 * from: NetBSD: gem.c,v 1.21 2002/06/01 23:50:58 lukem Exp 31 * from: FreeBSD: if_gem.c 182060 2008-08-23 15:03:26Z marius 32 */ 33 34 #include <sys/cdefs.h> 35 __FBSDID("$FreeBSD$"); 36 37 /* 38 * driver for Sun Cassini/Cassini+ and National Semiconductor DP83065 39 * Saturn Gigabit Ethernet controllers 40 */ 41 42 #if 0 43 #define CAS_DEBUG 44 #endif 45 46 #include <sys/param.h> 47 #include <sys/systm.h> 48 #include <sys/bus.h> 49 #include <sys/callout.h> 50 #include <sys/endian.h> 51 #include <sys/mbuf.h> 52 #include <sys/malloc.h> 53 #include <sys/kernel.h> 54 #include <sys/lock.h> 55 #include <sys/module.h> 56 #include <sys/mutex.h> 57 #include <sys/refcount.h> 58 #include <sys/resource.h> 59 #include <sys/rman.h> 60 #include <sys/socket.h> 61 #include <sys/sockio.h> 62 #include <sys/taskqueue.h> 63 64 #include <net/bpf.h> 65 #include <net/ethernet.h> 66 #include <net/if.h> 67 #include <net/if_var.h> 68 #include <net/if_arp.h> 69 #include <net/if_dl.h> 70 #include <net/if_media.h> 71 #include <net/if_types.h> 72 #include <net/if_vlan_var.h> 73 74 #include <netinet/in.h> 75 #include <netinet/in_systm.h> 76 #include <netinet/ip.h> 77 #include <netinet/tcp.h> 78 #include <netinet/udp.h> 79 80 #include <machine/bus.h> 81 #if defined(__powerpc__) 82 #include <dev/ofw/ofw_bus.h> 83 #include <dev/ofw/openfirm.h> 84 #include <machine/ofw_machdep.h> 85 #endif 86 #include <machine/resource.h> 87 88 #include <dev/mii/mii.h> 89 #include <dev/mii/miivar.h> 90 91 #include <dev/cas/if_casreg.h> 92 #include <dev/cas/if_casvar.h> 93 94 #include <dev/pci/pcireg.h> 95 #include <dev/pci/pcivar.h> 96 97 #include "miibus_if.h" 98 99 #define RINGASSERT(n , min, max) \ 100 CTASSERT(powerof2(n) && (n) >= (min) && (n) <= (max)) 101 102 RINGASSERT(CAS_NRXCOMP, 128, 32768); 103 RINGASSERT(CAS_NRXDESC, 32, 8192); 104 RINGASSERT(CAS_NRXDESC2, 32, 8192); 105 RINGASSERT(CAS_NTXDESC, 32, 8192); 106 107 #undef RINGASSERT 108 109 #define CCDASSERT(m, a) \ 110 CTASSERT((offsetof(struct cas_control_data, m) & ((a) - 1)) == 0) 111 112 CCDASSERT(ccd_rxcomps, CAS_RX_COMP_ALIGN); 113 CCDASSERT(ccd_rxdescs, CAS_RX_DESC_ALIGN); 114 CCDASSERT(ccd_rxdescs2, CAS_RX_DESC_ALIGN); 115 116 #undef CCDASSERT 117 118 #define CAS_TRIES 10000 119 120 /* 121 * According to documentation, the hardware has support for basic TCP 122 * checksum offloading only, in practice this can be also used for UDP 123 * however (i.e. the problem of previous Sun NICs that a checksum of 0x0 124 * is not converted to 0xffff no longer exists). 125 */ 126 #define CAS_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 127 128 static inline void cas_add_rxdesc(struct cas_softc *sc, u_int idx); 129 static int cas_attach(struct cas_softc *sc); 130 static int cas_bitwait(struct cas_softc *sc, bus_addr_t r, uint32_t clr, 131 uint32_t set); 132 static void cas_cddma_callback(void *xsc, bus_dma_segment_t *segs, 133 int nsegs, int error); 134 static void cas_detach(struct cas_softc *sc); 135 static int cas_disable_rx(struct cas_softc *sc); 136 static int cas_disable_tx(struct cas_softc *sc); 137 static void cas_eint(struct cas_softc *sc, u_int status); 138 static void cas_free(struct mbuf *m); 139 static void cas_init(void *xsc); 140 static void cas_init_locked(struct cas_softc *sc); 141 static void cas_init_regs(struct cas_softc *sc); 142 static int cas_intr(void *v); 143 static void cas_intr_task(void *arg, int pending __unused); 144 static int cas_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data); 145 static int cas_load_txmbuf(struct cas_softc *sc, struct mbuf **m_head); 146 static int cas_mediachange(struct ifnet *ifp); 147 static void cas_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr); 148 static void cas_meminit(struct cas_softc *sc); 149 static void cas_mifinit(struct cas_softc *sc); 150 static int cas_mii_readreg(device_t dev, int phy, int reg); 151 static void cas_mii_statchg(device_t dev); 152 static int cas_mii_writereg(device_t dev, int phy, int reg, int val); 153 static void cas_reset(struct cas_softc *sc); 154 static int cas_reset_rx(struct cas_softc *sc); 155 static int cas_reset_tx(struct cas_softc *sc); 156 static void cas_resume(struct cas_softc *sc); 157 static u_int cas_descsize(u_int sz); 158 static void cas_rint(struct cas_softc *sc); 159 static void cas_rint_timeout(void *arg); 160 static inline void cas_rxcksum(struct mbuf *m, uint16_t cksum); 161 static inline void cas_rxcompinit(struct cas_rx_comp *rxcomp); 162 static u_int cas_rxcompsize(u_int sz); 163 static void cas_rxdma_callback(void *xsc, bus_dma_segment_t *segs, 164 int nsegs, int error); 165 static void cas_setladrf(struct cas_softc *sc); 166 static void cas_start(struct ifnet *ifp); 167 static void cas_stop(struct ifnet *ifp); 168 static void cas_suspend(struct cas_softc *sc); 169 static void cas_tick(void *arg); 170 static void cas_tint(struct cas_softc *sc); 171 static void cas_tx_task(void *arg, int pending __unused); 172 static inline void cas_txkick(struct cas_softc *sc); 173 static void cas_watchdog(struct cas_softc *sc); 174 175 static devclass_t cas_devclass; 176 177 MODULE_DEPEND(cas, ether, 1, 1, 1); 178 MODULE_DEPEND(cas, miibus, 1, 1, 1); 179 180 #ifdef CAS_DEBUG 181 #include <sys/ktr.h> 182 #define KTR_CAS KTR_SPARE2 183 #endif 184 185 static int 186 cas_attach(struct cas_softc *sc) 187 { 188 struct cas_txsoft *txs; 189 struct ifnet *ifp; 190 int error, i; 191 uint32_t v; 192 193 /* Set up ifnet structure. */ 194 ifp = sc->sc_ifp = if_alloc(IFT_ETHER); 195 if (ifp == NULL) 196 return (ENOSPC); 197 ifp->if_softc = sc; 198 if_initname(ifp, device_get_name(sc->sc_dev), 199 device_get_unit(sc->sc_dev)); 200 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 201 ifp->if_start = cas_start; 202 ifp->if_ioctl = cas_ioctl; 203 ifp->if_init = cas_init; 204 IFQ_SET_MAXLEN(&ifp->if_snd, CAS_TXQUEUELEN); 205 ifp->if_snd.ifq_drv_maxlen = CAS_TXQUEUELEN; 206 IFQ_SET_READY(&ifp->if_snd); 207 208 callout_init_mtx(&sc->sc_tick_ch, &sc->sc_mtx, 0); 209 callout_init_mtx(&sc->sc_rx_ch, &sc->sc_mtx, 0); 210 /* Create local taskq. */ 211 TASK_INIT(&sc->sc_intr_task, 0, cas_intr_task, sc); 212 TASK_INIT(&sc->sc_tx_task, 1, cas_tx_task, ifp); 213 sc->sc_tq = taskqueue_create_fast("cas_taskq", M_WAITOK, 214 taskqueue_thread_enqueue, &sc->sc_tq); 215 if (sc->sc_tq == NULL) { 216 device_printf(sc->sc_dev, "could not create taskqueue\n"); 217 error = ENXIO; 218 goto fail_ifnet; 219 } 220 error = taskqueue_start_threads(&sc->sc_tq, 1, PI_NET, "%s taskq", 221 device_get_nameunit(sc->sc_dev)); 222 if (error != 0) { 223 device_printf(sc->sc_dev, "could not start threads\n"); 224 goto fail_taskq; 225 } 226 227 /* Make sure the chip is stopped. */ 228 cas_reset(sc); 229 230 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 231 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 232 BUS_SPACE_MAXSIZE, 0, BUS_SPACE_MAXSIZE, 0, NULL, NULL, 233 &sc->sc_pdmatag); 234 if (error != 0) 235 goto fail_taskq; 236 237 error = bus_dma_tag_create(sc->sc_pdmatag, 1, 0, 238 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 239 CAS_PAGE_SIZE, 1, CAS_PAGE_SIZE, 0, NULL, NULL, &sc->sc_rdmatag); 240 if (error != 0) 241 goto fail_ptag; 242 243 error = bus_dma_tag_create(sc->sc_pdmatag, 1, 0, 244 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 245 MCLBYTES * CAS_NTXSEGS, CAS_NTXSEGS, MCLBYTES, 246 BUS_DMA_ALLOCNOW, NULL, NULL, &sc->sc_tdmatag); 247 if (error != 0) 248 goto fail_rtag; 249 250 error = bus_dma_tag_create(sc->sc_pdmatag, CAS_TX_DESC_ALIGN, 0, 251 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 252 sizeof(struct cas_control_data), 1, 253 sizeof(struct cas_control_data), 0, 254 NULL, NULL, &sc->sc_cdmatag); 255 if (error != 0) 256 goto fail_ttag; 257 258 /* 259 * Allocate the control data structures, create and load the 260 * DMA map for it. 261 */ 262 if ((error = bus_dmamem_alloc(sc->sc_cdmatag, 263 (void **)&sc->sc_control_data, 264 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 265 &sc->sc_cddmamap)) != 0) { 266 device_printf(sc->sc_dev, 267 "unable to allocate control data, error = %d\n", error); 268 goto fail_ctag; 269 } 270 271 sc->sc_cddma = 0; 272 if ((error = bus_dmamap_load(sc->sc_cdmatag, sc->sc_cddmamap, 273 sc->sc_control_data, sizeof(struct cas_control_data), 274 cas_cddma_callback, sc, 0)) != 0 || sc->sc_cddma == 0) { 275 device_printf(sc->sc_dev, 276 "unable to load control data DMA map, error = %d\n", 277 error); 278 goto fail_cmem; 279 } 280 281 /* 282 * Initialize the transmit job descriptors. 283 */ 284 STAILQ_INIT(&sc->sc_txfreeq); 285 STAILQ_INIT(&sc->sc_txdirtyq); 286 287 /* 288 * Create the transmit buffer DMA maps. 289 */ 290 error = ENOMEM; 291 for (i = 0; i < CAS_TXQUEUELEN; i++) { 292 txs = &sc->sc_txsoft[i]; 293 txs->txs_mbuf = NULL; 294 txs->txs_ndescs = 0; 295 if ((error = bus_dmamap_create(sc->sc_tdmatag, 0, 296 &txs->txs_dmamap)) != 0) { 297 device_printf(sc->sc_dev, 298 "unable to create TX DMA map %d, error = %d\n", 299 i, error); 300 goto fail_txd; 301 } 302 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 303 } 304 305 /* 306 * Allocate the receive buffers, create and load the DMA maps 307 * for them. 308 */ 309 for (i = 0; i < CAS_NRXDESC; i++) { 310 if ((error = bus_dmamem_alloc(sc->sc_rdmatag, 311 &sc->sc_rxdsoft[i].rxds_buf, BUS_DMA_WAITOK, 312 &sc->sc_rxdsoft[i].rxds_dmamap)) != 0) { 313 device_printf(sc->sc_dev, 314 "unable to allocate RX buffer %d, error = %d\n", 315 i, error); 316 goto fail_rxmem; 317 } 318 319 sc->sc_rxdptr = i; 320 sc->sc_rxdsoft[i].rxds_paddr = 0; 321 if ((error = bus_dmamap_load(sc->sc_rdmatag, 322 sc->sc_rxdsoft[i].rxds_dmamap, sc->sc_rxdsoft[i].rxds_buf, 323 CAS_PAGE_SIZE, cas_rxdma_callback, sc, 0)) != 0 || 324 sc->sc_rxdsoft[i].rxds_paddr == 0) { 325 device_printf(sc->sc_dev, 326 "unable to load RX DMA map %d, error = %d\n", 327 i, error); 328 goto fail_rxmap; 329 } 330 } 331 332 if ((sc->sc_flags & CAS_SERDES) == 0) { 333 CAS_WRITE_4(sc, CAS_PCS_DATAPATH, CAS_PCS_DATAPATH_MII); 334 CAS_BARRIER(sc, CAS_PCS_DATAPATH, 4, 335 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 336 cas_mifinit(sc); 337 /* 338 * Look for an external PHY. 339 */ 340 error = ENXIO; 341 v = CAS_READ_4(sc, CAS_MIF_CONF); 342 if ((v & CAS_MIF_CONF_MDI1) != 0) { 343 v |= CAS_MIF_CONF_PHY_SELECT; 344 CAS_WRITE_4(sc, CAS_MIF_CONF, v); 345 CAS_BARRIER(sc, CAS_MIF_CONF, 4, 346 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 347 /* Enable/unfreeze the GMII pins of Saturn. */ 348 if (sc->sc_variant == CAS_SATURN) { 349 CAS_WRITE_4(sc, CAS_SATURN_PCFG, 350 CAS_READ_4(sc, CAS_SATURN_PCFG) & 351 ~CAS_SATURN_PCFG_FSI); 352 CAS_BARRIER(sc, CAS_SATURN_PCFG, 4, 353 BUS_SPACE_BARRIER_READ | 354 BUS_SPACE_BARRIER_WRITE); 355 DELAY(10000); 356 } 357 error = mii_attach(sc->sc_dev, &sc->sc_miibus, ifp, 358 cas_mediachange, cas_mediastatus, BMSR_DEFCAPMASK, 359 MII_PHY_ANY, MII_OFFSET_ANY, MIIF_DOPAUSE); 360 } 361 /* 362 * Fall back on an internal PHY if no external PHY was found. 363 */ 364 if (error != 0 && (v & CAS_MIF_CONF_MDI0) != 0) { 365 v &= ~CAS_MIF_CONF_PHY_SELECT; 366 CAS_WRITE_4(sc, CAS_MIF_CONF, v); 367 CAS_BARRIER(sc, CAS_MIF_CONF, 4, 368 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 369 /* Freeze the GMII pins of Saturn for saving power. */ 370 if (sc->sc_variant == CAS_SATURN) { 371 CAS_WRITE_4(sc, CAS_SATURN_PCFG, 372 CAS_READ_4(sc, CAS_SATURN_PCFG) | 373 CAS_SATURN_PCFG_FSI); 374 CAS_BARRIER(sc, CAS_SATURN_PCFG, 4, 375 BUS_SPACE_BARRIER_READ | 376 BUS_SPACE_BARRIER_WRITE); 377 DELAY(10000); 378 } 379 error = mii_attach(sc->sc_dev, &sc->sc_miibus, ifp, 380 cas_mediachange, cas_mediastatus, BMSR_DEFCAPMASK, 381 MII_PHY_ANY, MII_OFFSET_ANY, MIIF_DOPAUSE); 382 } 383 } else { 384 /* 385 * Use the external PCS SERDES. 386 */ 387 CAS_WRITE_4(sc, CAS_PCS_DATAPATH, CAS_PCS_DATAPATH_SERDES); 388 CAS_BARRIER(sc, CAS_PCS_DATAPATH, 4, BUS_SPACE_BARRIER_WRITE); 389 /* Enable/unfreeze the SERDES pins of Saturn. */ 390 if (sc->sc_variant == CAS_SATURN) { 391 CAS_WRITE_4(sc, CAS_SATURN_PCFG, 0); 392 CAS_BARRIER(sc, CAS_SATURN_PCFG, 4, 393 BUS_SPACE_BARRIER_WRITE); 394 } 395 CAS_WRITE_4(sc, CAS_PCS_SERDES_CTRL, CAS_PCS_SERDES_CTRL_ESD); 396 CAS_BARRIER(sc, CAS_PCS_SERDES_CTRL, 4, 397 BUS_SPACE_BARRIER_WRITE); 398 CAS_WRITE_4(sc, CAS_PCS_CONF, CAS_PCS_CONF_EN); 399 CAS_BARRIER(sc, CAS_PCS_CONF, 4, 400 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 401 error = mii_attach(sc->sc_dev, &sc->sc_miibus, ifp, 402 cas_mediachange, cas_mediastatus, BMSR_DEFCAPMASK, 403 CAS_PHYAD_EXTERNAL, MII_OFFSET_ANY, MIIF_DOPAUSE); 404 } 405 if (error != 0) { 406 device_printf(sc->sc_dev, "attaching PHYs failed\n"); 407 goto fail_rxmap; 408 } 409 sc->sc_mii = device_get_softc(sc->sc_miibus); 410 411 /* 412 * From this point forward, the attachment cannot fail. A failure 413 * before this point releases all resources that may have been 414 * allocated. 415 */ 416 417 /* Announce FIFO sizes. */ 418 v = CAS_READ_4(sc, CAS_TX_FIFO_SIZE); 419 device_printf(sc->sc_dev, "%ukB RX FIFO, %ukB TX FIFO\n", 420 CAS_RX_FIFO_SIZE / 1024, v / 16); 421 422 /* Attach the interface. */ 423 ether_ifattach(ifp, sc->sc_enaddr); 424 425 /* 426 * Tell the upper layer(s) we support long frames/checksum offloads. 427 */ 428 ifp->if_hdrlen = sizeof(struct ether_vlan_header); 429 ifp->if_capabilities = IFCAP_VLAN_MTU; 430 if ((sc->sc_flags & CAS_NO_CSUM) == 0) { 431 ifp->if_capabilities |= IFCAP_HWCSUM; 432 ifp->if_hwassist = CAS_CSUM_FEATURES; 433 } 434 ifp->if_capenable = ifp->if_capabilities; 435 436 return (0); 437 438 /* 439 * Free any resources we've allocated during the failed attach 440 * attempt. Do this in reverse order and fall through. 441 */ 442 fail_rxmap: 443 for (i = 0; i < CAS_NRXDESC; i++) 444 if (sc->sc_rxdsoft[i].rxds_paddr != 0) 445 bus_dmamap_unload(sc->sc_rdmatag, 446 sc->sc_rxdsoft[i].rxds_dmamap); 447 fail_rxmem: 448 for (i = 0; i < CAS_NRXDESC; i++) 449 if (sc->sc_rxdsoft[i].rxds_buf != NULL) 450 bus_dmamem_free(sc->sc_rdmatag, 451 sc->sc_rxdsoft[i].rxds_buf, 452 sc->sc_rxdsoft[i].rxds_dmamap); 453 fail_txd: 454 for (i = 0; i < CAS_TXQUEUELEN; i++) 455 if (sc->sc_txsoft[i].txs_dmamap != NULL) 456 bus_dmamap_destroy(sc->sc_tdmatag, 457 sc->sc_txsoft[i].txs_dmamap); 458 bus_dmamap_unload(sc->sc_cdmatag, sc->sc_cddmamap); 459 fail_cmem: 460 bus_dmamem_free(sc->sc_cdmatag, sc->sc_control_data, 461 sc->sc_cddmamap); 462 fail_ctag: 463 bus_dma_tag_destroy(sc->sc_cdmatag); 464 fail_ttag: 465 bus_dma_tag_destroy(sc->sc_tdmatag); 466 fail_rtag: 467 bus_dma_tag_destroy(sc->sc_rdmatag); 468 fail_ptag: 469 bus_dma_tag_destroy(sc->sc_pdmatag); 470 fail_taskq: 471 taskqueue_free(sc->sc_tq); 472 fail_ifnet: 473 if_free(ifp); 474 return (error); 475 } 476 477 static void 478 cas_detach(struct cas_softc *sc) 479 { 480 struct ifnet *ifp = sc->sc_ifp; 481 int i; 482 483 ether_ifdetach(ifp); 484 CAS_LOCK(sc); 485 cas_stop(ifp); 486 CAS_UNLOCK(sc); 487 callout_drain(&sc->sc_tick_ch); 488 callout_drain(&sc->sc_rx_ch); 489 taskqueue_drain(sc->sc_tq, &sc->sc_intr_task); 490 taskqueue_drain(sc->sc_tq, &sc->sc_tx_task); 491 if_free(ifp); 492 taskqueue_free(sc->sc_tq); 493 device_delete_child(sc->sc_dev, sc->sc_miibus); 494 495 for (i = 0; i < CAS_NRXDESC; i++) 496 if (sc->sc_rxdsoft[i].rxds_dmamap != NULL) 497 bus_dmamap_sync(sc->sc_rdmatag, 498 sc->sc_rxdsoft[i].rxds_dmamap, 499 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 500 for (i = 0; i < CAS_NRXDESC; i++) 501 if (sc->sc_rxdsoft[i].rxds_paddr != 0) 502 bus_dmamap_unload(sc->sc_rdmatag, 503 sc->sc_rxdsoft[i].rxds_dmamap); 504 for (i = 0; i < CAS_NRXDESC; i++) 505 if (sc->sc_rxdsoft[i].rxds_buf != NULL) 506 bus_dmamem_free(sc->sc_rdmatag, 507 sc->sc_rxdsoft[i].rxds_buf, 508 sc->sc_rxdsoft[i].rxds_dmamap); 509 for (i = 0; i < CAS_TXQUEUELEN; i++) 510 if (sc->sc_txsoft[i].txs_dmamap != NULL) 511 bus_dmamap_destroy(sc->sc_tdmatag, 512 sc->sc_txsoft[i].txs_dmamap); 513 CAS_CDSYNC(sc, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 514 bus_dmamap_unload(sc->sc_cdmatag, sc->sc_cddmamap); 515 bus_dmamem_free(sc->sc_cdmatag, sc->sc_control_data, 516 sc->sc_cddmamap); 517 bus_dma_tag_destroy(sc->sc_cdmatag); 518 bus_dma_tag_destroy(sc->sc_tdmatag); 519 bus_dma_tag_destroy(sc->sc_rdmatag); 520 bus_dma_tag_destroy(sc->sc_pdmatag); 521 } 522 523 static void 524 cas_suspend(struct cas_softc *sc) 525 { 526 struct ifnet *ifp = sc->sc_ifp; 527 528 CAS_LOCK(sc); 529 cas_stop(ifp); 530 CAS_UNLOCK(sc); 531 } 532 533 static void 534 cas_resume(struct cas_softc *sc) 535 { 536 struct ifnet *ifp = sc->sc_ifp; 537 538 CAS_LOCK(sc); 539 /* 540 * On resume all registers have to be initialized again like 541 * after power-on. 542 */ 543 sc->sc_flags &= ~CAS_INITED; 544 if (ifp->if_flags & IFF_UP) 545 cas_init_locked(sc); 546 CAS_UNLOCK(sc); 547 } 548 549 static inline void 550 cas_rxcksum(struct mbuf *m, uint16_t cksum) 551 { 552 struct ether_header *eh; 553 struct ip *ip; 554 struct udphdr *uh; 555 uint16_t *opts; 556 int32_t hlen, len, pktlen; 557 uint32_t temp32; 558 559 pktlen = m->m_pkthdr.len; 560 if (pktlen < sizeof(struct ether_header) + sizeof(struct ip)) 561 return; 562 eh = mtod(m, struct ether_header *); 563 if (eh->ether_type != htons(ETHERTYPE_IP)) 564 return; 565 ip = (struct ip *)(eh + 1); 566 if (ip->ip_v != IPVERSION) 567 return; 568 569 hlen = ip->ip_hl << 2; 570 pktlen -= sizeof(struct ether_header); 571 if (hlen < sizeof(struct ip)) 572 return; 573 if (ntohs(ip->ip_len) < hlen) 574 return; 575 if (ntohs(ip->ip_len) != pktlen) 576 return; 577 if (ip->ip_off & htons(IP_MF | IP_OFFMASK)) 578 return; /* Cannot handle fragmented packet. */ 579 580 switch (ip->ip_p) { 581 case IPPROTO_TCP: 582 if (pktlen < (hlen + sizeof(struct tcphdr))) 583 return; 584 break; 585 case IPPROTO_UDP: 586 if (pktlen < (hlen + sizeof(struct udphdr))) 587 return; 588 uh = (struct udphdr *)((uint8_t *)ip + hlen); 589 if (uh->uh_sum == 0) 590 return; /* no checksum */ 591 break; 592 default: 593 return; 594 } 595 596 cksum = ~cksum; 597 /* checksum fixup for IP options */ 598 len = hlen - sizeof(struct ip); 599 if (len > 0) { 600 opts = (uint16_t *)(ip + 1); 601 for (; len > 0; len -= sizeof(uint16_t), opts++) { 602 temp32 = cksum - *opts; 603 temp32 = (temp32 >> 16) + (temp32 & 65535); 604 cksum = temp32 & 65535; 605 } 606 } 607 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID; 608 m->m_pkthdr.csum_data = cksum; 609 } 610 611 static void 612 cas_cddma_callback(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 613 { 614 struct cas_softc *sc = xsc; 615 616 if (error != 0) 617 return; 618 if (nsegs != 1) 619 panic("%s: bad control buffer segment count", __func__); 620 sc->sc_cddma = segs[0].ds_addr; 621 } 622 623 static void 624 cas_rxdma_callback(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 625 { 626 struct cas_softc *sc = xsc; 627 628 if (error != 0) 629 return; 630 if (nsegs != 1) 631 panic("%s: bad RX buffer segment count", __func__); 632 sc->sc_rxdsoft[sc->sc_rxdptr].rxds_paddr = segs[0].ds_addr; 633 } 634 635 static void 636 cas_tick(void *arg) 637 { 638 struct cas_softc *sc = arg; 639 struct ifnet *ifp = sc->sc_ifp; 640 uint32_t v; 641 642 CAS_LOCK_ASSERT(sc, MA_OWNED); 643 644 /* 645 * Unload collision and error counters. 646 */ 647 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, 648 CAS_READ_4(sc, CAS_MAC_NORM_COLL_CNT) + 649 CAS_READ_4(sc, CAS_MAC_FIRST_COLL_CNT)); 650 v = CAS_READ_4(sc, CAS_MAC_EXCESS_COLL_CNT) + 651 CAS_READ_4(sc, CAS_MAC_LATE_COLL_CNT); 652 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, v); 653 if_inc_counter(ifp, IFCOUNTER_OERRORS, v); 654 if_inc_counter(ifp, IFCOUNTER_IERRORS, 655 CAS_READ_4(sc, CAS_MAC_RX_LEN_ERR_CNT) + 656 CAS_READ_4(sc, CAS_MAC_RX_ALIGN_ERR) + 657 CAS_READ_4(sc, CAS_MAC_RX_CRC_ERR_CNT) + 658 CAS_READ_4(sc, CAS_MAC_RX_CODE_VIOL)); 659 660 /* 661 * Then clear the hardware counters. 662 */ 663 CAS_WRITE_4(sc, CAS_MAC_NORM_COLL_CNT, 0); 664 CAS_WRITE_4(sc, CAS_MAC_FIRST_COLL_CNT, 0); 665 CAS_WRITE_4(sc, CAS_MAC_EXCESS_COLL_CNT, 0); 666 CAS_WRITE_4(sc, CAS_MAC_LATE_COLL_CNT, 0); 667 CAS_WRITE_4(sc, CAS_MAC_RX_LEN_ERR_CNT, 0); 668 CAS_WRITE_4(sc, CAS_MAC_RX_ALIGN_ERR, 0); 669 CAS_WRITE_4(sc, CAS_MAC_RX_CRC_ERR_CNT, 0); 670 CAS_WRITE_4(sc, CAS_MAC_RX_CODE_VIOL, 0); 671 672 mii_tick(sc->sc_mii); 673 674 if (sc->sc_txfree != CAS_MAXTXFREE) 675 cas_tint(sc); 676 677 cas_watchdog(sc); 678 679 callout_reset(&sc->sc_tick_ch, hz, cas_tick, sc); 680 } 681 682 static int 683 cas_bitwait(struct cas_softc *sc, bus_addr_t r, uint32_t clr, uint32_t set) 684 { 685 int i; 686 uint32_t reg; 687 688 for (i = CAS_TRIES; i--; DELAY(100)) { 689 reg = CAS_READ_4(sc, r); 690 if ((reg & clr) == 0 && (reg & set) == set) 691 return (1); 692 } 693 return (0); 694 } 695 696 static void 697 cas_reset(struct cas_softc *sc) 698 { 699 700 #ifdef CAS_DEBUG 701 CTR2(KTR_CAS, "%s: %s", device_get_name(sc->sc_dev), __func__); 702 #endif 703 /* Disable all interrupts in order to avoid spurious ones. */ 704 CAS_WRITE_4(sc, CAS_INTMASK, 0xffffffff); 705 706 cas_reset_rx(sc); 707 cas_reset_tx(sc); 708 709 /* 710 * Do a full reset modulo the result of the last auto-negotiation 711 * when using the SERDES. 712 */ 713 CAS_WRITE_4(sc, CAS_RESET, CAS_RESET_RX | CAS_RESET_TX | 714 ((sc->sc_flags & CAS_SERDES) != 0 ? CAS_RESET_PCS_DIS : 0)); 715 CAS_BARRIER(sc, CAS_RESET, 4, 716 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 717 DELAY(3000); 718 if (!cas_bitwait(sc, CAS_RESET, CAS_RESET_RX | CAS_RESET_TX, 0)) 719 device_printf(sc->sc_dev, "cannot reset device\n"); 720 } 721 722 static void 723 cas_stop(struct ifnet *ifp) 724 { 725 struct cas_softc *sc = ifp->if_softc; 726 struct cas_txsoft *txs; 727 728 #ifdef CAS_DEBUG 729 CTR2(KTR_CAS, "%s: %s", device_get_name(sc->sc_dev), __func__); 730 #endif 731 732 callout_stop(&sc->sc_tick_ch); 733 callout_stop(&sc->sc_rx_ch); 734 735 /* Disable all interrupts in order to avoid spurious ones. */ 736 CAS_WRITE_4(sc, CAS_INTMASK, 0xffffffff); 737 738 cas_reset_tx(sc); 739 cas_reset_rx(sc); 740 741 /* 742 * Release any queued transmit buffers. 743 */ 744 while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 745 STAILQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 746 if (txs->txs_ndescs != 0) { 747 bus_dmamap_sync(sc->sc_tdmatag, txs->txs_dmamap, 748 BUS_DMASYNC_POSTWRITE); 749 bus_dmamap_unload(sc->sc_tdmatag, txs->txs_dmamap); 750 if (txs->txs_mbuf != NULL) { 751 m_freem(txs->txs_mbuf); 752 txs->txs_mbuf = NULL; 753 } 754 } 755 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 756 } 757 758 /* 759 * Mark the interface down and cancel the watchdog timer. 760 */ 761 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 762 sc->sc_flags &= ~CAS_LINK; 763 sc->sc_wdog_timer = 0; 764 } 765 766 static int 767 cas_reset_rx(struct cas_softc *sc) 768 { 769 770 /* 771 * Resetting while DMA is in progress can cause a bus hang, so we 772 * disable DMA first. 773 */ 774 (void)cas_disable_rx(sc); 775 CAS_WRITE_4(sc, CAS_RX_CONF, 0); 776 CAS_BARRIER(sc, CAS_RX_CONF, 4, 777 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 778 if (!cas_bitwait(sc, CAS_RX_CONF, CAS_RX_CONF_RXDMA_EN, 0)) 779 device_printf(sc->sc_dev, "cannot disable RX DMA\n"); 780 781 /* Finally, reset the ERX. */ 782 CAS_WRITE_4(sc, CAS_RESET, CAS_RESET_RX | 783 ((sc->sc_flags & CAS_SERDES) != 0 ? CAS_RESET_PCS_DIS : 0)); 784 CAS_BARRIER(sc, CAS_RESET, 4, 785 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 786 if (!cas_bitwait(sc, CAS_RESET, CAS_RESET_RX, 0)) { 787 device_printf(sc->sc_dev, "cannot reset receiver\n"); 788 return (1); 789 } 790 return (0); 791 } 792 793 static int 794 cas_reset_tx(struct cas_softc *sc) 795 { 796 797 /* 798 * Resetting while DMA is in progress can cause a bus hang, so we 799 * disable DMA first. 800 */ 801 (void)cas_disable_tx(sc); 802 CAS_WRITE_4(sc, CAS_TX_CONF, 0); 803 CAS_BARRIER(sc, CAS_TX_CONF, 4, 804 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 805 if (!cas_bitwait(sc, CAS_TX_CONF, CAS_TX_CONF_TXDMA_EN, 0)) 806 device_printf(sc->sc_dev, "cannot disable TX DMA\n"); 807 808 /* Finally, reset the ETX. */ 809 CAS_WRITE_4(sc, CAS_RESET, CAS_RESET_TX | 810 ((sc->sc_flags & CAS_SERDES) != 0 ? CAS_RESET_PCS_DIS : 0)); 811 CAS_BARRIER(sc, CAS_RESET, 4, 812 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 813 if (!cas_bitwait(sc, CAS_RESET, CAS_RESET_TX, 0)) { 814 device_printf(sc->sc_dev, "cannot reset transmitter\n"); 815 return (1); 816 } 817 return (0); 818 } 819 820 static int 821 cas_disable_rx(struct cas_softc *sc) 822 { 823 824 CAS_WRITE_4(sc, CAS_MAC_RX_CONF, 825 CAS_READ_4(sc, CAS_MAC_RX_CONF) & ~CAS_MAC_RX_CONF_EN); 826 CAS_BARRIER(sc, CAS_MAC_RX_CONF, 4, 827 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 828 if (cas_bitwait(sc, CAS_MAC_RX_CONF, CAS_MAC_RX_CONF_EN, 0)) 829 return (1); 830 if (bootverbose) 831 device_printf(sc->sc_dev, "cannot disable RX MAC\n"); 832 return (0); 833 } 834 835 static int 836 cas_disable_tx(struct cas_softc *sc) 837 { 838 839 CAS_WRITE_4(sc, CAS_MAC_TX_CONF, 840 CAS_READ_4(sc, CAS_MAC_TX_CONF) & ~CAS_MAC_TX_CONF_EN); 841 CAS_BARRIER(sc, CAS_MAC_TX_CONF, 4, 842 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 843 if (cas_bitwait(sc, CAS_MAC_TX_CONF, CAS_MAC_TX_CONF_EN, 0)) 844 return (1); 845 if (bootverbose) 846 device_printf(sc->sc_dev, "cannot disable TX MAC\n"); 847 return (0); 848 } 849 850 static inline void 851 cas_rxcompinit(struct cas_rx_comp *rxcomp) 852 { 853 854 rxcomp->crc_word1 = 0; 855 rxcomp->crc_word2 = 0; 856 rxcomp->crc_word3 = 857 htole64(CAS_SET(ETHER_HDR_LEN + sizeof(struct ip), CAS_RC3_CSO)); 858 rxcomp->crc_word4 = htole64(CAS_RC4_ZERO); 859 } 860 861 static void 862 cas_meminit(struct cas_softc *sc) 863 { 864 int i; 865 866 CAS_LOCK_ASSERT(sc, MA_OWNED); 867 868 /* 869 * Initialize the transmit descriptor ring. 870 */ 871 for (i = 0; i < CAS_NTXDESC; i++) { 872 sc->sc_txdescs[i].cd_flags = 0; 873 sc->sc_txdescs[i].cd_buf_ptr = 0; 874 } 875 sc->sc_txfree = CAS_MAXTXFREE; 876 sc->sc_txnext = 0; 877 sc->sc_txwin = 0; 878 879 /* 880 * Initialize the receive completion ring. 881 */ 882 for (i = 0; i < CAS_NRXCOMP; i++) 883 cas_rxcompinit(&sc->sc_rxcomps[i]); 884 sc->sc_rxcptr = 0; 885 886 /* 887 * Initialize the first receive descriptor ring. We leave 888 * the second one zeroed as we don't actually use it. 889 */ 890 for (i = 0; i < CAS_NRXDESC; i++) 891 CAS_INIT_RXDESC(sc, i, i); 892 sc->sc_rxdptr = 0; 893 894 CAS_CDSYNC(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 895 } 896 897 static u_int 898 cas_descsize(u_int sz) 899 { 900 901 switch (sz) { 902 case 32: 903 return (CAS_DESC_32); 904 case 64: 905 return (CAS_DESC_64); 906 case 128: 907 return (CAS_DESC_128); 908 case 256: 909 return (CAS_DESC_256); 910 case 512: 911 return (CAS_DESC_512); 912 case 1024: 913 return (CAS_DESC_1K); 914 case 2048: 915 return (CAS_DESC_2K); 916 case 4096: 917 return (CAS_DESC_4K); 918 case 8192: 919 return (CAS_DESC_8K); 920 default: 921 printf("%s: invalid descriptor ring size %d\n", __func__, sz); 922 return (CAS_DESC_32); 923 } 924 } 925 926 static u_int 927 cas_rxcompsize(u_int sz) 928 { 929 930 switch (sz) { 931 case 128: 932 return (CAS_RX_CONF_COMP_128); 933 case 256: 934 return (CAS_RX_CONF_COMP_256); 935 case 512: 936 return (CAS_RX_CONF_COMP_512); 937 case 1024: 938 return (CAS_RX_CONF_COMP_1K); 939 case 2048: 940 return (CAS_RX_CONF_COMP_2K); 941 case 4096: 942 return (CAS_RX_CONF_COMP_4K); 943 case 8192: 944 return (CAS_RX_CONF_COMP_8K); 945 case 16384: 946 return (CAS_RX_CONF_COMP_16K); 947 case 32768: 948 return (CAS_RX_CONF_COMP_32K); 949 default: 950 printf("%s: invalid dcompletion ring size %d\n", __func__, sz); 951 return (CAS_RX_CONF_COMP_128); 952 } 953 } 954 955 static void 956 cas_init(void *xsc) 957 { 958 struct cas_softc *sc = xsc; 959 960 CAS_LOCK(sc); 961 cas_init_locked(sc); 962 CAS_UNLOCK(sc); 963 } 964 965 /* 966 * Initialization of interface; set up initialization block 967 * and transmit/receive descriptor rings. 968 */ 969 static void 970 cas_init_locked(struct cas_softc *sc) 971 { 972 struct ifnet *ifp = sc->sc_ifp; 973 uint32_t v; 974 975 CAS_LOCK_ASSERT(sc, MA_OWNED); 976 977 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 978 return; 979 980 #ifdef CAS_DEBUG 981 CTR2(KTR_CAS, "%s: %s: calling stop", device_get_name(sc->sc_dev), 982 __func__); 983 #endif 984 /* 985 * Initialization sequence. The numbered steps below correspond 986 * to the sequence outlined in section 6.3.5.1 in the Ethernet 987 * Channel Engine manual (part of the PCIO manual). 988 * See also the STP2002-STQ document from Sun Microsystems. 989 */ 990 991 /* step 1 & 2. Reset the Ethernet Channel. */ 992 cas_stop(ifp); 993 cas_reset(sc); 994 #ifdef CAS_DEBUG 995 CTR2(KTR_CAS, "%s: %s: restarting", device_get_name(sc->sc_dev), 996 __func__); 997 #endif 998 999 if ((sc->sc_flags & CAS_SERDES) == 0) 1000 /* Re-initialize the MIF. */ 1001 cas_mifinit(sc); 1002 1003 /* step 3. Setup data structures in host memory. */ 1004 cas_meminit(sc); 1005 1006 /* step 4. TX MAC registers & counters */ 1007 cas_init_regs(sc); 1008 1009 /* step 5. RX MAC registers & counters */ 1010 1011 /* step 6 & 7. Program Ring Base Addresses. */ 1012 CAS_WRITE_4(sc, CAS_TX_DESC3_BASE_HI, 1013 (((uint64_t)CAS_CDTXDADDR(sc, 0)) >> 32)); 1014 CAS_WRITE_4(sc, CAS_TX_DESC3_BASE_LO, 1015 CAS_CDTXDADDR(sc, 0) & 0xffffffff); 1016 1017 CAS_WRITE_4(sc, CAS_RX_COMP_BASE_HI, 1018 (((uint64_t)CAS_CDRXCADDR(sc, 0)) >> 32)); 1019 CAS_WRITE_4(sc, CAS_RX_COMP_BASE_LO, 1020 CAS_CDRXCADDR(sc, 0) & 0xffffffff); 1021 1022 CAS_WRITE_4(sc, CAS_RX_DESC_BASE_HI, 1023 (((uint64_t)CAS_CDRXDADDR(sc, 0)) >> 32)); 1024 CAS_WRITE_4(sc, CAS_RX_DESC_BASE_LO, 1025 CAS_CDRXDADDR(sc, 0) & 0xffffffff); 1026 1027 if ((sc->sc_flags & CAS_REG_PLUS) != 0) { 1028 CAS_WRITE_4(sc, CAS_RX_DESC2_BASE_HI, 1029 (((uint64_t)CAS_CDRXD2ADDR(sc, 0)) >> 32)); 1030 CAS_WRITE_4(sc, CAS_RX_DESC2_BASE_LO, 1031 CAS_CDRXD2ADDR(sc, 0) & 0xffffffff); 1032 } 1033 1034 #ifdef CAS_DEBUG 1035 CTR5(KTR_CAS, 1036 "loading TXDR %lx, RXCR %lx, RXDR %lx, RXD2R %lx, cddma %lx", 1037 CAS_CDTXDADDR(sc, 0), CAS_CDRXCADDR(sc, 0), CAS_CDRXDADDR(sc, 0), 1038 CAS_CDRXD2ADDR(sc, 0), sc->sc_cddma); 1039 #endif 1040 1041 /* step 8. Global Configuration & Interrupt Masks */ 1042 1043 /* Disable weighted round robin. */ 1044 CAS_WRITE_4(sc, CAS_CAW, CAS_CAW_RR_DIS); 1045 1046 /* 1047 * Enable infinite bursts for revisions without PCI issues if 1048 * applicable. Doing so greatly improves the TX performance. 1049 */ 1050 CAS_WRITE_4(sc, CAS_INF_BURST, 1051 (sc->sc_flags & CAS_TABORT) == 0 ? CAS_INF_BURST_EN : 1052 0); 1053 1054 /* Set up interrupts. */ 1055 CAS_WRITE_4(sc, CAS_INTMASK, 1056 ~(CAS_INTR_TX_INT_ME | CAS_INTR_TX_TAG_ERR | 1057 CAS_INTR_RX_DONE | CAS_INTR_RX_BUF_NA | CAS_INTR_RX_TAG_ERR | 1058 CAS_INTR_RX_COMP_FULL | CAS_INTR_RX_BUF_AEMPTY | 1059 CAS_INTR_RX_COMP_AFULL | CAS_INTR_RX_LEN_MMATCH | 1060 CAS_INTR_PCI_ERROR_INT 1061 #ifdef CAS_DEBUG 1062 | CAS_INTR_PCS_INT | CAS_INTR_MIF 1063 #endif 1064 )); 1065 /* Don't clear top level interrupts when CAS_STATUS_ALIAS is read. */ 1066 CAS_WRITE_4(sc, CAS_CLEAR_ALIAS, 0); 1067 CAS_WRITE_4(sc, CAS_MAC_RX_MASK, ~CAS_MAC_RX_OVERFLOW); 1068 CAS_WRITE_4(sc, CAS_MAC_TX_MASK, 1069 ~(CAS_MAC_TX_UNDERRUN | CAS_MAC_TX_MAX_PKT_ERR)); 1070 #ifdef CAS_DEBUG 1071 CAS_WRITE_4(sc, CAS_MAC_CTRL_MASK, 1072 ~(CAS_MAC_CTRL_PAUSE_RCVD | CAS_MAC_CTRL_PAUSE | 1073 CAS_MAC_CTRL_NON_PAUSE)); 1074 #else 1075 CAS_WRITE_4(sc, CAS_MAC_CTRL_MASK, 1076 CAS_MAC_CTRL_PAUSE_RCVD | CAS_MAC_CTRL_PAUSE | 1077 CAS_MAC_CTRL_NON_PAUSE); 1078 #endif 1079 1080 /* Enable PCI error interrupts. */ 1081 CAS_WRITE_4(sc, CAS_ERROR_MASK, 1082 ~(CAS_ERROR_DTRTO | CAS_ERROR_OTHER | CAS_ERROR_DMAW_ZERO | 1083 CAS_ERROR_DMAR_ZERO | CAS_ERROR_RTRTO)); 1084 1085 /* Enable PCI error interrupts in BIM configuration. */ 1086 CAS_WRITE_4(sc, CAS_BIM_CONF, 1087 CAS_BIM_CONF_DPAR_EN | CAS_BIM_CONF_RMA_EN | CAS_BIM_CONF_RTA_EN); 1088 1089 /* 1090 * step 9. ETX Configuration: encode receive descriptor ring size, 1091 * enable DMA and disable pre-interrupt writeback completion. 1092 */ 1093 v = cas_descsize(CAS_NTXDESC) << CAS_TX_CONF_DESC3_SHFT; 1094 CAS_WRITE_4(sc, CAS_TX_CONF, v | CAS_TX_CONF_TXDMA_EN | 1095 CAS_TX_CONF_RDPP_DIS | CAS_TX_CONF_PICWB_DIS); 1096 1097 /* step 10. ERX Configuration */ 1098 1099 /* 1100 * Encode receive completion and descriptor ring sizes, set the 1101 * swivel offset. 1102 */ 1103 v = cas_rxcompsize(CAS_NRXCOMP) << CAS_RX_CONF_COMP_SHFT; 1104 v |= cas_descsize(CAS_NRXDESC) << CAS_RX_CONF_DESC_SHFT; 1105 if ((sc->sc_flags & CAS_REG_PLUS) != 0) 1106 v |= cas_descsize(CAS_NRXDESC2) << CAS_RX_CONF_DESC2_SHFT; 1107 CAS_WRITE_4(sc, CAS_RX_CONF, 1108 v | (ETHER_ALIGN << CAS_RX_CONF_SOFF_SHFT)); 1109 1110 /* Set the PAUSE thresholds. We use the maximum OFF threshold. */ 1111 CAS_WRITE_4(sc, CAS_RX_PTHRS, 1112 (111 << CAS_RX_PTHRS_XOFF_SHFT) | (15 << CAS_RX_PTHRS_XON_SHFT)); 1113 1114 /* RX blanking */ 1115 CAS_WRITE_4(sc, CAS_RX_BLANK, 1116 (15 << CAS_RX_BLANK_TIME_SHFT) | (5 << CAS_RX_BLANK_PKTS_SHFT)); 1117 1118 /* Set RX_COMP_AFULL threshold to half of the RX completions. */ 1119 CAS_WRITE_4(sc, CAS_RX_AEMPTY_THRS, 1120 (CAS_NRXCOMP / 2) << CAS_RX_AEMPTY_COMP_SHFT); 1121 1122 /* Initialize the RX page size register as appropriate for 8k. */ 1123 CAS_WRITE_4(sc, CAS_RX_PSZ, 1124 (CAS_RX_PSZ_8K << CAS_RX_PSZ_SHFT) | 1125 (4 << CAS_RX_PSZ_MB_CNT_SHFT) | 1126 (CAS_RX_PSZ_MB_STRD_2K << CAS_RX_PSZ_MB_STRD_SHFT) | 1127 (CAS_RX_PSZ_MB_OFF_64 << CAS_RX_PSZ_MB_OFF_SHFT)); 1128 1129 /* Disable RX random early detection. */ 1130 CAS_WRITE_4(sc, CAS_RX_RED, 0); 1131 1132 /* Zero the RX reassembly DMA table. */ 1133 for (v = 0; v <= CAS_RX_REAS_DMA_ADDR_LC; v++) { 1134 CAS_WRITE_4(sc, CAS_RX_REAS_DMA_ADDR, v); 1135 CAS_WRITE_4(sc, CAS_RX_REAS_DMA_DATA_LO, 0); 1136 CAS_WRITE_4(sc, CAS_RX_REAS_DMA_DATA_MD, 0); 1137 CAS_WRITE_4(sc, CAS_RX_REAS_DMA_DATA_HI, 0); 1138 } 1139 1140 /* Ensure the RX control FIFO and RX IPP FIFO addresses are zero. */ 1141 CAS_WRITE_4(sc, CAS_RX_CTRL_FIFO, 0); 1142 CAS_WRITE_4(sc, CAS_RX_IPP_ADDR, 0); 1143 1144 /* Finally, enable RX DMA. */ 1145 CAS_WRITE_4(sc, CAS_RX_CONF, 1146 CAS_READ_4(sc, CAS_RX_CONF) | CAS_RX_CONF_RXDMA_EN); 1147 1148 /* step 11. Configure Media. */ 1149 1150 /* step 12. RX_MAC Configuration Register */ 1151 v = CAS_READ_4(sc, CAS_MAC_RX_CONF); 1152 v &= ~(CAS_MAC_RX_CONF_STRPPAD | CAS_MAC_RX_CONF_EN); 1153 v |= CAS_MAC_RX_CONF_STRPFCS; 1154 sc->sc_mac_rxcfg = v; 1155 /* 1156 * Clear the RX filter and reprogram it. This will also set the 1157 * current RX MAC configuration and enable it. 1158 */ 1159 cas_setladrf(sc); 1160 1161 /* step 13. TX_MAC Configuration Register */ 1162 v = CAS_READ_4(sc, CAS_MAC_TX_CONF); 1163 v |= CAS_MAC_TX_CONF_EN; 1164 (void)cas_disable_tx(sc); 1165 CAS_WRITE_4(sc, CAS_MAC_TX_CONF, v); 1166 1167 /* step 14. Issue Transmit Pending command. */ 1168 1169 /* step 15. Give the receiver a swift kick. */ 1170 CAS_WRITE_4(sc, CAS_RX_KICK, CAS_NRXDESC - 4); 1171 CAS_WRITE_4(sc, CAS_RX_COMP_TAIL, 0); 1172 if ((sc->sc_flags & CAS_REG_PLUS) != 0) 1173 CAS_WRITE_4(sc, CAS_RX_KICK2, CAS_NRXDESC2 - 4); 1174 1175 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1176 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1177 1178 mii_mediachg(sc->sc_mii); 1179 1180 /* Start the one second timer. */ 1181 sc->sc_wdog_timer = 0; 1182 callout_reset(&sc->sc_tick_ch, hz, cas_tick, sc); 1183 } 1184 1185 static int 1186 cas_load_txmbuf(struct cas_softc *sc, struct mbuf **m_head) 1187 { 1188 bus_dma_segment_t txsegs[CAS_NTXSEGS]; 1189 struct cas_txsoft *txs; 1190 struct ip *ip; 1191 struct mbuf *m; 1192 uint64_t cflags; 1193 int error, nexttx, nsegs, offset, seg; 1194 1195 CAS_LOCK_ASSERT(sc, MA_OWNED); 1196 1197 /* Get a work queue entry. */ 1198 if ((txs = STAILQ_FIRST(&sc->sc_txfreeq)) == NULL) { 1199 /* Ran out of descriptors. */ 1200 return (ENOBUFS); 1201 } 1202 1203 cflags = 0; 1204 if (((*m_head)->m_pkthdr.csum_flags & CAS_CSUM_FEATURES) != 0) { 1205 if (M_WRITABLE(*m_head) == 0) { 1206 m = m_dup(*m_head, M_NOWAIT); 1207 m_freem(*m_head); 1208 *m_head = m; 1209 if (m == NULL) 1210 return (ENOBUFS); 1211 } 1212 offset = sizeof(struct ether_header); 1213 m = m_pullup(*m_head, offset + sizeof(struct ip)); 1214 if (m == NULL) { 1215 *m_head = NULL; 1216 return (ENOBUFS); 1217 } 1218 ip = (struct ip *)(mtod(m, caddr_t) + offset); 1219 offset += (ip->ip_hl << 2); 1220 cflags = (offset << CAS_TD_CKSUM_START_SHFT) | 1221 ((offset + m->m_pkthdr.csum_data) << 1222 CAS_TD_CKSUM_STUFF_SHFT) | CAS_TD_CKSUM_EN; 1223 *m_head = m; 1224 } 1225 1226 error = bus_dmamap_load_mbuf_sg(sc->sc_tdmatag, txs->txs_dmamap, 1227 *m_head, txsegs, &nsegs, BUS_DMA_NOWAIT); 1228 if (error == EFBIG) { 1229 m = m_collapse(*m_head, M_NOWAIT, CAS_NTXSEGS); 1230 if (m == NULL) { 1231 m_freem(*m_head); 1232 *m_head = NULL; 1233 return (ENOBUFS); 1234 } 1235 *m_head = m; 1236 error = bus_dmamap_load_mbuf_sg(sc->sc_tdmatag, 1237 txs->txs_dmamap, *m_head, txsegs, &nsegs, 1238 BUS_DMA_NOWAIT); 1239 if (error != 0) { 1240 m_freem(*m_head); 1241 *m_head = NULL; 1242 return (error); 1243 } 1244 } else if (error != 0) 1245 return (error); 1246 /* If nsegs is wrong then the stack is corrupt. */ 1247 KASSERT(nsegs <= CAS_NTXSEGS, 1248 ("%s: too many DMA segments (%d)", __func__, nsegs)); 1249 if (nsegs == 0) { 1250 m_freem(*m_head); 1251 *m_head = NULL; 1252 return (EIO); 1253 } 1254 1255 /* 1256 * Ensure we have enough descriptors free to describe 1257 * the packet. Note, we always reserve one descriptor 1258 * at the end of the ring as a termination point, in 1259 * order to prevent wrap-around. 1260 */ 1261 if (nsegs > sc->sc_txfree - 1) { 1262 txs->txs_ndescs = 0; 1263 bus_dmamap_unload(sc->sc_tdmatag, txs->txs_dmamap); 1264 return (ENOBUFS); 1265 } 1266 1267 txs->txs_ndescs = nsegs; 1268 txs->txs_firstdesc = sc->sc_txnext; 1269 nexttx = txs->txs_firstdesc; 1270 for (seg = 0; seg < nsegs; seg++, nexttx = CAS_NEXTTX(nexttx)) { 1271 #ifdef CAS_DEBUG 1272 CTR6(KTR_CAS, 1273 "%s: mapping seg %d (txd %d), len %lx, addr %#lx (%#lx)", 1274 __func__, seg, nexttx, txsegs[seg].ds_len, 1275 txsegs[seg].ds_addr, htole64(txsegs[seg].ds_addr)); 1276 #endif 1277 sc->sc_txdescs[nexttx].cd_buf_ptr = 1278 htole64(txsegs[seg].ds_addr); 1279 KASSERT(txsegs[seg].ds_len < 1280 CAS_TD_BUF_LEN_MASK >> CAS_TD_BUF_LEN_SHFT, 1281 ("%s: segment size too large!", __func__)); 1282 sc->sc_txdescs[nexttx].cd_flags = 1283 htole64(txsegs[seg].ds_len << CAS_TD_BUF_LEN_SHFT); 1284 txs->txs_lastdesc = nexttx; 1285 } 1286 1287 /* Set EOF on the last descriptor. */ 1288 #ifdef CAS_DEBUG 1289 CTR3(KTR_CAS, "%s: end of frame at segment %d, TX %d", 1290 __func__, seg, nexttx); 1291 #endif 1292 sc->sc_txdescs[txs->txs_lastdesc].cd_flags |= 1293 htole64(CAS_TD_END_OF_FRAME); 1294 1295 /* Lastly set SOF on the first descriptor. */ 1296 #ifdef CAS_DEBUG 1297 CTR3(KTR_CAS, "%s: start of frame at segment %d, TX %d", 1298 __func__, seg, nexttx); 1299 #endif 1300 if (sc->sc_txwin += nsegs > CAS_MAXTXFREE * 2 / 3) { 1301 sc->sc_txwin = 0; 1302 sc->sc_txdescs[txs->txs_firstdesc].cd_flags |= 1303 htole64(cflags | CAS_TD_START_OF_FRAME | CAS_TD_INT_ME); 1304 } else 1305 sc->sc_txdescs[txs->txs_firstdesc].cd_flags |= 1306 htole64(cflags | CAS_TD_START_OF_FRAME); 1307 1308 /* Sync the DMA map. */ 1309 bus_dmamap_sync(sc->sc_tdmatag, txs->txs_dmamap, 1310 BUS_DMASYNC_PREWRITE); 1311 1312 #ifdef CAS_DEBUG 1313 CTR4(KTR_CAS, "%s: setting firstdesc=%d, lastdesc=%d, ndescs=%d", 1314 __func__, txs->txs_firstdesc, txs->txs_lastdesc, 1315 txs->txs_ndescs); 1316 #endif 1317 STAILQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 1318 STAILQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1319 txs->txs_mbuf = *m_head; 1320 1321 sc->sc_txnext = CAS_NEXTTX(txs->txs_lastdesc); 1322 sc->sc_txfree -= txs->txs_ndescs; 1323 1324 return (0); 1325 } 1326 1327 static void 1328 cas_init_regs(struct cas_softc *sc) 1329 { 1330 int i; 1331 const u_char *laddr = IF_LLADDR(sc->sc_ifp); 1332 1333 CAS_LOCK_ASSERT(sc, MA_OWNED); 1334 1335 /* These registers are not cleared on reset. */ 1336 if ((sc->sc_flags & CAS_INITED) == 0) { 1337 /* magic values */ 1338 CAS_WRITE_4(sc, CAS_MAC_IPG0, 0); 1339 CAS_WRITE_4(sc, CAS_MAC_IPG1, 8); 1340 CAS_WRITE_4(sc, CAS_MAC_IPG2, 4); 1341 1342 /* min frame length */ 1343 CAS_WRITE_4(sc, CAS_MAC_MIN_FRAME, ETHER_MIN_LEN); 1344 /* max frame length and max burst size */ 1345 CAS_WRITE_4(sc, CAS_MAC_MAX_BF, 1346 ((ETHER_MAX_LEN_JUMBO + ETHER_VLAN_ENCAP_LEN) << 1347 CAS_MAC_MAX_BF_FRM_SHFT) | 1348 (0x2000 << CAS_MAC_MAX_BF_BST_SHFT)); 1349 1350 /* more magic values */ 1351 CAS_WRITE_4(sc, CAS_MAC_PREAMBLE_LEN, 0x7); 1352 CAS_WRITE_4(sc, CAS_MAC_JAM_SIZE, 0x4); 1353 CAS_WRITE_4(sc, CAS_MAC_ATTEMPT_LIMIT, 0x10); 1354 CAS_WRITE_4(sc, CAS_MAC_CTRL_TYPE, 0x8808); 1355 1356 /* random number seed */ 1357 CAS_WRITE_4(sc, CAS_MAC_RANDOM_SEED, 1358 ((laddr[5] << 8) | laddr[4]) & 0x3ff); 1359 1360 /* secondary MAC addresses: 0:0:0:0:0:0 */ 1361 for (i = CAS_MAC_ADDR3; i <= CAS_MAC_ADDR41; 1362 i += CAS_MAC_ADDR4 - CAS_MAC_ADDR3) 1363 CAS_WRITE_4(sc, i, 0); 1364 1365 /* MAC control address: 01:80:c2:00:00:01 */ 1366 CAS_WRITE_4(sc, CAS_MAC_ADDR42, 0x0001); 1367 CAS_WRITE_4(sc, CAS_MAC_ADDR43, 0xc200); 1368 CAS_WRITE_4(sc, CAS_MAC_ADDR44, 0x0180); 1369 1370 /* MAC filter address: 0:0:0:0:0:0 */ 1371 CAS_WRITE_4(sc, CAS_MAC_AFILTER0, 0); 1372 CAS_WRITE_4(sc, CAS_MAC_AFILTER1, 0); 1373 CAS_WRITE_4(sc, CAS_MAC_AFILTER2, 0); 1374 CAS_WRITE_4(sc, CAS_MAC_AFILTER_MASK1_2, 0); 1375 CAS_WRITE_4(sc, CAS_MAC_AFILTER_MASK0, 0); 1376 1377 /* Zero the hash table. */ 1378 for (i = CAS_MAC_HASH0; i <= CAS_MAC_HASH15; 1379 i += CAS_MAC_HASH1 - CAS_MAC_HASH0) 1380 CAS_WRITE_4(sc, i, 0); 1381 1382 sc->sc_flags |= CAS_INITED; 1383 } 1384 1385 /* Counters need to be zeroed. */ 1386 CAS_WRITE_4(sc, CAS_MAC_NORM_COLL_CNT, 0); 1387 CAS_WRITE_4(sc, CAS_MAC_FIRST_COLL_CNT, 0); 1388 CAS_WRITE_4(sc, CAS_MAC_EXCESS_COLL_CNT, 0); 1389 CAS_WRITE_4(sc, CAS_MAC_LATE_COLL_CNT, 0); 1390 CAS_WRITE_4(sc, CAS_MAC_DEFER_TMR_CNT, 0); 1391 CAS_WRITE_4(sc, CAS_MAC_PEAK_ATTEMPTS, 0); 1392 CAS_WRITE_4(sc, CAS_MAC_RX_FRAME_COUNT, 0); 1393 CAS_WRITE_4(sc, CAS_MAC_RX_LEN_ERR_CNT, 0); 1394 CAS_WRITE_4(sc, CAS_MAC_RX_ALIGN_ERR, 0); 1395 CAS_WRITE_4(sc, CAS_MAC_RX_CRC_ERR_CNT, 0); 1396 CAS_WRITE_4(sc, CAS_MAC_RX_CODE_VIOL, 0); 1397 1398 /* Set XOFF PAUSE time. */ 1399 CAS_WRITE_4(sc, CAS_MAC_SPC, 0x1BF0 << CAS_MAC_SPC_TIME_SHFT); 1400 1401 /* Set the station address. */ 1402 CAS_WRITE_4(sc, CAS_MAC_ADDR0, (laddr[4] << 8) | laddr[5]); 1403 CAS_WRITE_4(sc, CAS_MAC_ADDR1, (laddr[2] << 8) | laddr[3]); 1404 CAS_WRITE_4(sc, CAS_MAC_ADDR2, (laddr[0] << 8) | laddr[1]); 1405 1406 /* Enable MII outputs. */ 1407 CAS_WRITE_4(sc, CAS_MAC_XIF_CONF, CAS_MAC_XIF_CONF_TX_OE); 1408 } 1409 1410 static void 1411 cas_tx_task(void *arg, int pending __unused) 1412 { 1413 struct ifnet *ifp; 1414 1415 ifp = (struct ifnet *)arg; 1416 cas_start(ifp); 1417 } 1418 1419 static inline void 1420 cas_txkick(struct cas_softc *sc) 1421 { 1422 1423 /* 1424 * Update the TX kick register. This register has to point to the 1425 * descriptor after the last valid one and for optimum performance 1426 * should be incremented in multiples of 4 (the DMA engine fetches/ 1427 * updates descriptors in batches of 4). 1428 */ 1429 #ifdef CAS_DEBUG 1430 CTR3(KTR_CAS, "%s: %s: kicking TX %d", 1431 device_get_name(sc->sc_dev), __func__, sc->sc_txnext); 1432 #endif 1433 CAS_CDSYNC(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1434 CAS_WRITE_4(sc, CAS_TX_KICK3, sc->sc_txnext); 1435 } 1436 1437 static void 1438 cas_start(struct ifnet *ifp) 1439 { 1440 struct cas_softc *sc = ifp->if_softc; 1441 struct mbuf *m; 1442 int kicked, ntx; 1443 1444 CAS_LOCK(sc); 1445 1446 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1447 IFF_DRV_RUNNING || (sc->sc_flags & CAS_LINK) == 0) { 1448 CAS_UNLOCK(sc); 1449 return; 1450 } 1451 1452 if (sc->sc_txfree < CAS_MAXTXFREE / 4) 1453 cas_tint(sc); 1454 1455 #ifdef CAS_DEBUG 1456 CTR4(KTR_CAS, "%s: %s: txfree %d, txnext %d", 1457 device_get_name(sc->sc_dev), __func__, sc->sc_txfree, 1458 sc->sc_txnext); 1459 #endif 1460 ntx = 0; 1461 kicked = 0; 1462 for (; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && sc->sc_txfree > 1;) { 1463 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 1464 if (m == NULL) 1465 break; 1466 if (cas_load_txmbuf(sc, &m) != 0) { 1467 if (m == NULL) 1468 break; 1469 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1470 IFQ_DRV_PREPEND(&ifp->if_snd, m); 1471 break; 1472 } 1473 if ((sc->sc_txnext % 4) == 0) { 1474 cas_txkick(sc); 1475 kicked = 1; 1476 } else 1477 kicked = 0; 1478 ntx++; 1479 BPF_MTAP(ifp, m); 1480 } 1481 1482 if (ntx > 0) { 1483 if (kicked == 0) 1484 cas_txkick(sc); 1485 #ifdef CAS_DEBUG 1486 CTR2(KTR_CAS, "%s: packets enqueued, OWN on %d", 1487 device_get_name(sc->sc_dev), sc->sc_txnext); 1488 #endif 1489 1490 /* Set a watchdog timer in case the chip flakes out. */ 1491 sc->sc_wdog_timer = 5; 1492 #ifdef CAS_DEBUG 1493 CTR3(KTR_CAS, "%s: %s: watchdog %d", 1494 device_get_name(sc->sc_dev), __func__, 1495 sc->sc_wdog_timer); 1496 #endif 1497 } 1498 1499 CAS_UNLOCK(sc); 1500 } 1501 1502 static void 1503 cas_tint(struct cas_softc *sc) 1504 { 1505 struct ifnet *ifp = sc->sc_ifp; 1506 struct cas_txsoft *txs; 1507 int progress; 1508 uint32_t txlast; 1509 #ifdef CAS_DEBUG 1510 int i; 1511 1512 CAS_LOCK_ASSERT(sc, MA_OWNED); 1513 1514 CTR2(KTR_CAS, "%s: %s", device_get_name(sc->sc_dev), __func__); 1515 #endif 1516 1517 /* 1518 * Go through our TX list and free mbufs for those 1519 * frames that have been transmitted. 1520 */ 1521 progress = 0; 1522 CAS_CDSYNC(sc, BUS_DMASYNC_POSTREAD); 1523 while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1524 #ifdef CAS_DEBUG 1525 if ((ifp->if_flags & IFF_DEBUG) != 0) { 1526 printf(" txsoft %p transmit chain:\n", txs); 1527 for (i = txs->txs_firstdesc;; i = CAS_NEXTTX(i)) { 1528 printf("descriptor %d: ", i); 1529 printf("cd_flags: 0x%016llx\t", 1530 (long long)le64toh( 1531 sc->sc_txdescs[i].cd_flags)); 1532 printf("cd_buf_ptr: 0x%016llx\n", 1533 (long long)le64toh( 1534 sc->sc_txdescs[i].cd_buf_ptr)); 1535 if (i == txs->txs_lastdesc) 1536 break; 1537 } 1538 } 1539 #endif 1540 1541 /* 1542 * In theory, we could harvest some descriptors before 1543 * the ring is empty, but that's a bit complicated. 1544 * 1545 * CAS_TX_COMPn points to the last descriptor 1546 * processed + 1. 1547 */ 1548 txlast = CAS_READ_4(sc, CAS_TX_COMP3); 1549 #ifdef CAS_DEBUG 1550 CTR4(KTR_CAS, "%s: txs->txs_firstdesc = %d, " 1551 "txs->txs_lastdesc = %d, txlast = %d", 1552 __func__, txs->txs_firstdesc, txs->txs_lastdesc, txlast); 1553 #endif 1554 if (txs->txs_firstdesc <= txs->txs_lastdesc) { 1555 if ((txlast >= txs->txs_firstdesc) && 1556 (txlast <= txs->txs_lastdesc)) 1557 break; 1558 } else { 1559 /* Ick -- this command wraps. */ 1560 if ((txlast >= txs->txs_firstdesc) || 1561 (txlast <= txs->txs_lastdesc)) 1562 break; 1563 } 1564 1565 #ifdef CAS_DEBUG 1566 CTR1(KTR_CAS, "%s: releasing a descriptor", __func__); 1567 #endif 1568 STAILQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1569 1570 sc->sc_txfree += txs->txs_ndescs; 1571 1572 bus_dmamap_sync(sc->sc_tdmatag, txs->txs_dmamap, 1573 BUS_DMASYNC_POSTWRITE); 1574 bus_dmamap_unload(sc->sc_tdmatag, txs->txs_dmamap); 1575 if (txs->txs_mbuf != NULL) { 1576 m_freem(txs->txs_mbuf); 1577 txs->txs_mbuf = NULL; 1578 } 1579 1580 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1581 1582 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 1583 progress = 1; 1584 } 1585 1586 #ifdef CAS_DEBUG 1587 CTR5(KTR_CAS, "%s: CAS_TX_SM1 %x CAS_TX_SM2 %x CAS_TX_DESC_BASE %llx " 1588 "CAS_TX_COMP3 %x", 1589 __func__, CAS_READ_4(sc, CAS_TX_SM1), CAS_READ_4(sc, CAS_TX_SM2), 1590 ((long long)CAS_READ_4(sc, CAS_TX_DESC3_BASE_HI) << 32) | 1591 CAS_READ_4(sc, CAS_TX_DESC3_BASE_LO), 1592 CAS_READ_4(sc, CAS_TX_COMP3)); 1593 #endif 1594 1595 if (progress) { 1596 /* We freed some descriptors, so reset IFF_DRV_OACTIVE. */ 1597 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1598 if (STAILQ_EMPTY(&sc->sc_txdirtyq)) 1599 sc->sc_wdog_timer = 0; 1600 } 1601 1602 #ifdef CAS_DEBUG 1603 CTR3(KTR_CAS, "%s: %s: watchdog %d", 1604 device_get_name(sc->sc_dev), __func__, sc->sc_wdog_timer); 1605 #endif 1606 } 1607 1608 static void 1609 cas_rint_timeout(void *arg) 1610 { 1611 struct cas_softc *sc = arg; 1612 1613 CAS_LOCK_ASSERT(sc, MA_OWNED); 1614 1615 cas_rint(sc); 1616 } 1617 1618 static void 1619 cas_rint(struct cas_softc *sc) 1620 { 1621 struct cas_rxdsoft *rxds, *rxds2; 1622 struct ifnet *ifp = sc->sc_ifp; 1623 struct mbuf *m, *m2; 1624 uint64_t word1, word2, word3, word4; 1625 uint32_t rxhead; 1626 u_int idx, idx2, len, off, skip; 1627 1628 CAS_LOCK_ASSERT(sc, MA_OWNED); 1629 1630 callout_stop(&sc->sc_rx_ch); 1631 1632 #ifdef CAS_DEBUG 1633 CTR2(KTR_CAS, "%s: %s", device_get_name(sc->sc_dev), __func__); 1634 #endif 1635 1636 #define PRINTWORD(n, delimiter) \ 1637 printf("word ## n: 0x%016llx%c", (long long)word ## n, delimiter) 1638 1639 #define SKIPASSERT(n) \ 1640 KASSERT(sc->sc_rxcomps[sc->sc_rxcptr].crc_word ## n == 0, \ 1641 ("%s: word ## n not 0", __func__)) 1642 1643 #define WORDTOH(n) \ 1644 word ## n = le64toh(sc->sc_rxcomps[sc->sc_rxcptr].crc_word ## n) 1645 1646 /* 1647 * Read the completion head register once. This limits 1648 * how long the following loop can execute. 1649 */ 1650 rxhead = CAS_READ_4(sc, CAS_RX_COMP_HEAD); 1651 #ifdef CAS_DEBUG 1652 CTR4(KTR_CAS, "%s: sc->sc_rxcptr %d, sc->sc_rxdptr %d, head %d", 1653 __func__, sc->sc_rxcptr, sc->sc_rxdptr, rxhead); 1654 #endif 1655 skip = 0; 1656 CAS_CDSYNC(sc, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1657 for (; sc->sc_rxcptr != rxhead; 1658 sc->sc_rxcptr = CAS_NEXTRXCOMP(sc->sc_rxcptr)) { 1659 if (skip != 0) { 1660 SKIPASSERT(1); 1661 SKIPASSERT(2); 1662 SKIPASSERT(3); 1663 1664 --skip; 1665 goto skip; 1666 } 1667 1668 WORDTOH(1); 1669 WORDTOH(2); 1670 WORDTOH(3); 1671 WORDTOH(4); 1672 1673 #ifdef CAS_DEBUG 1674 if ((ifp->if_flags & IFF_DEBUG) != 0) { 1675 printf(" completion %d: ", sc->sc_rxcptr); 1676 PRINTWORD(1, '\t'); 1677 PRINTWORD(2, '\t'); 1678 PRINTWORD(3, '\t'); 1679 PRINTWORD(4, '\n'); 1680 } 1681 #endif 1682 1683 if (__predict_false( 1684 (word1 & CAS_RC1_TYPE_MASK) == CAS_RC1_TYPE_HW || 1685 (word4 & CAS_RC4_ZERO) != 0)) { 1686 /* 1687 * The descriptor is still marked as owned, although 1688 * it is supposed to have completed. This has been 1689 * observed on some machines. Just exiting here 1690 * might leave the packet sitting around until another 1691 * one arrives to trigger a new interrupt, which is 1692 * generally undesirable, so set up a timeout. 1693 */ 1694 callout_reset(&sc->sc_rx_ch, CAS_RXOWN_TICKS, 1695 cas_rint_timeout, sc); 1696 break; 1697 } 1698 1699 if (__predict_false( 1700 (word4 & (CAS_RC4_BAD | CAS_RC4_LEN_MMATCH)) != 0)) { 1701 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 1702 device_printf(sc->sc_dev, 1703 "receive error: CRC error\n"); 1704 continue; 1705 } 1706 1707 KASSERT(CAS_GET(word1, CAS_RC1_DATA_SIZE) == 0 || 1708 CAS_GET(word2, CAS_RC2_HDR_SIZE) == 0, 1709 ("%s: data and header present", __func__)); 1710 KASSERT((word1 & CAS_RC1_SPLIT_PKT) == 0 || 1711 CAS_GET(word2, CAS_RC2_HDR_SIZE) == 0, 1712 ("%s: split and header present", __func__)); 1713 KASSERT(CAS_GET(word1, CAS_RC1_DATA_SIZE) == 0 || 1714 (word1 & CAS_RC1_RELEASE_HDR) == 0, 1715 ("%s: data present but header release", __func__)); 1716 KASSERT(CAS_GET(word2, CAS_RC2_HDR_SIZE) == 0 || 1717 (word1 & CAS_RC1_RELEASE_DATA) == 0, 1718 ("%s: header present but data release", __func__)); 1719 1720 if ((len = CAS_GET(word2, CAS_RC2_HDR_SIZE)) != 0) { 1721 idx = CAS_GET(word2, CAS_RC2_HDR_INDEX); 1722 off = CAS_GET(word2, CAS_RC2_HDR_OFF); 1723 #ifdef CAS_DEBUG 1724 CTR4(KTR_CAS, "%s: hdr at idx %d, off %d, len %d", 1725 __func__, idx, off, len); 1726 #endif 1727 rxds = &sc->sc_rxdsoft[idx]; 1728 MGETHDR(m, M_NOWAIT, MT_DATA); 1729 if (m != NULL) { 1730 refcount_acquire(&rxds->rxds_refcount); 1731 bus_dmamap_sync(sc->sc_rdmatag, 1732 rxds->rxds_dmamap, BUS_DMASYNC_POSTREAD); 1733 m_extadd(m, (char *)rxds->rxds_buf + 1734 off * 256 + ETHER_ALIGN, len, cas_free, 1735 sc, (void *)(uintptr_t)idx, 1736 M_RDONLY, EXT_NET_DRV); 1737 if ((m->m_flags & M_EXT) == 0) { 1738 m_freem(m); 1739 m = NULL; 1740 } 1741 } 1742 if (m != NULL) { 1743 m->m_pkthdr.rcvif = ifp; 1744 m->m_pkthdr.len = m->m_len = len; 1745 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 1746 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 1747 cas_rxcksum(m, CAS_GET(word4, 1748 CAS_RC4_TCP_CSUM)); 1749 /* Pass it on. */ 1750 CAS_UNLOCK(sc); 1751 (*ifp->if_input)(ifp, m); 1752 CAS_LOCK(sc); 1753 } else 1754 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 1755 1756 if ((word1 & CAS_RC1_RELEASE_HDR) != 0 && 1757 refcount_release(&rxds->rxds_refcount) != 0) 1758 cas_add_rxdesc(sc, idx); 1759 } else if ((len = CAS_GET(word1, CAS_RC1_DATA_SIZE)) != 0) { 1760 idx = CAS_GET(word1, CAS_RC1_DATA_INDEX); 1761 off = CAS_GET(word1, CAS_RC1_DATA_OFF); 1762 #ifdef CAS_DEBUG 1763 CTR4(KTR_CAS, "%s: data at idx %d, off %d, len %d", 1764 __func__, idx, off, len); 1765 #endif 1766 rxds = &sc->sc_rxdsoft[idx]; 1767 MGETHDR(m, M_NOWAIT, MT_DATA); 1768 if (m != NULL) { 1769 refcount_acquire(&rxds->rxds_refcount); 1770 off += ETHER_ALIGN; 1771 m->m_len = min(CAS_PAGE_SIZE - off, len); 1772 bus_dmamap_sync(sc->sc_rdmatag, 1773 rxds->rxds_dmamap, BUS_DMASYNC_POSTREAD); 1774 m_extadd(m, (char *)rxds->rxds_buf + off, 1775 m->m_len, cas_free, sc, 1776 (void *)(uintptr_t)idx, M_RDONLY, 1777 EXT_NET_DRV); 1778 if ((m->m_flags & M_EXT) == 0) { 1779 m_freem(m); 1780 m = NULL; 1781 } 1782 } 1783 idx2 = 0; 1784 m2 = NULL; 1785 rxds2 = NULL; 1786 if ((word1 & CAS_RC1_SPLIT_PKT) != 0) { 1787 KASSERT((word1 & CAS_RC1_RELEASE_NEXT) != 0, 1788 ("%s: split but no release next", 1789 __func__)); 1790 1791 idx2 = CAS_GET(word2, CAS_RC2_NEXT_INDEX); 1792 #ifdef CAS_DEBUG 1793 CTR2(KTR_CAS, "%s: split at idx %d", 1794 __func__, idx2); 1795 #endif 1796 rxds2 = &sc->sc_rxdsoft[idx2]; 1797 if (m != NULL) { 1798 MGET(m2, M_NOWAIT, MT_DATA); 1799 if (m2 != NULL) { 1800 refcount_acquire( 1801 &rxds2->rxds_refcount); 1802 m2->m_len = len - m->m_len; 1803 bus_dmamap_sync( 1804 sc->sc_rdmatag, 1805 rxds2->rxds_dmamap, 1806 BUS_DMASYNC_POSTREAD); 1807 m_extadd(m2, 1808 (char *)rxds2->rxds_buf, 1809 m2->m_len, cas_free, sc, 1810 (void *)(uintptr_t)idx2, 1811 M_RDONLY, EXT_NET_DRV); 1812 if ((m2->m_flags & M_EXT) == 1813 0) { 1814 m_freem(m2); 1815 m2 = NULL; 1816 } 1817 } 1818 } 1819 if (m2 != NULL) 1820 m->m_next = m2; 1821 else if (m != NULL) { 1822 m_freem(m); 1823 m = NULL; 1824 } 1825 } 1826 if (m != NULL) { 1827 m->m_pkthdr.rcvif = ifp; 1828 m->m_pkthdr.len = len; 1829 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 1830 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 1831 cas_rxcksum(m, CAS_GET(word4, 1832 CAS_RC4_TCP_CSUM)); 1833 /* Pass it on. */ 1834 CAS_UNLOCK(sc); 1835 (*ifp->if_input)(ifp, m); 1836 CAS_LOCK(sc); 1837 } else 1838 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 1839 1840 if ((word1 & CAS_RC1_RELEASE_DATA) != 0 && 1841 refcount_release(&rxds->rxds_refcount) != 0) 1842 cas_add_rxdesc(sc, idx); 1843 if ((word1 & CAS_RC1_SPLIT_PKT) != 0 && 1844 refcount_release(&rxds2->rxds_refcount) != 0) 1845 cas_add_rxdesc(sc, idx2); 1846 } 1847 1848 skip = CAS_GET(word1, CAS_RC1_SKIP); 1849 1850 skip: 1851 cas_rxcompinit(&sc->sc_rxcomps[sc->sc_rxcptr]); 1852 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 1853 break; 1854 } 1855 CAS_CDSYNC(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1856 CAS_WRITE_4(sc, CAS_RX_COMP_TAIL, sc->sc_rxcptr); 1857 1858 #undef PRINTWORD 1859 #undef SKIPASSERT 1860 #undef WORDTOH 1861 1862 #ifdef CAS_DEBUG 1863 CTR4(KTR_CAS, "%s: done sc->sc_rxcptr %d, sc->sc_rxdptr %d, head %d", 1864 __func__, sc->sc_rxcptr, sc->sc_rxdptr, 1865 CAS_READ_4(sc, CAS_RX_COMP_HEAD)); 1866 #endif 1867 } 1868 1869 static void 1870 cas_free(struct mbuf *m) 1871 { 1872 struct cas_rxdsoft *rxds; 1873 struct cas_softc *sc; 1874 u_int idx, locked; 1875 1876 sc = m->m_ext.ext_arg1; 1877 idx = (uintptr_t)m->m_ext.ext_arg2; 1878 rxds = &sc->sc_rxdsoft[idx]; 1879 if (refcount_release(&rxds->rxds_refcount) == 0) 1880 return; 1881 1882 /* 1883 * NB: this function can be called via m_freem(9) within 1884 * this driver! 1885 */ 1886 if ((locked = CAS_LOCK_OWNED(sc)) == 0) 1887 CAS_LOCK(sc); 1888 cas_add_rxdesc(sc, idx); 1889 if (locked == 0) 1890 CAS_UNLOCK(sc); 1891 } 1892 1893 static inline void 1894 cas_add_rxdesc(struct cas_softc *sc, u_int idx) 1895 { 1896 1897 CAS_LOCK_ASSERT(sc, MA_OWNED); 1898 1899 bus_dmamap_sync(sc->sc_rdmatag, sc->sc_rxdsoft[idx].rxds_dmamap, 1900 BUS_DMASYNC_PREREAD); 1901 CAS_UPDATE_RXDESC(sc, sc->sc_rxdptr, idx); 1902 sc->sc_rxdptr = CAS_NEXTRXDESC(sc->sc_rxdptr); 1903 1904 /* 1905 * Update the RX kick register. This register has to point to the 1906 * descriptor after the last valid one (before the current batch) 1907 * and for optimum performance should be incremented in multiples 1908 * of 4 (the DMA engine fetches/updates descriptors in batches of 4). 1909 */ 1910 if ((sc->sc_rxdptr % 4) == 0) { 1911 CAS_CDSYNC(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1912 CAS_WRITE_4(sc, CAS_RX_KICK, 1913 (sc->sc_rxdptr + CAS_NRXDESC - 4) & CAS_NRXDESC_MASK); 1914 } 1915 } 1916 1917 static void 1918 cas_eint(struct cas_softc *sc, u_int status) 1919 { 1920 struct ifnet *ifp = sc->sc_ifp; 1921 1922 CAS_LOCK_ASSERT(sc, MA_OWNED); 1923 1924 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 1925 1926 device_printf(sc->sc_dev, "%s: status 0x%x", __func__, status); 1927 if ((status & CAS_INTR_PCI_ERROR_INT) != 0) { 1928 status = CAS_READ_4(sc, CAS_ERROR_STATUS); 1929 printf(", PCI bus error 0x%x", status); 1930 if ((status & CAS_ERROR_OTHER) != 0) { 1931 status = pci_read_config(sc->sc_dev, PCIR_STATUS, 2); 1932 printf(", PCI status 0x%x", status); 1933 pci_write_config(sc->sc_dev, PCIR_STATUS, status, 2); 1934 } 1935 } 1936 printf("\n"); 1937 1938 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1939 cas_init_locked(sc); 1940 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1941 taskqueue_enqueue(sc->sc_tq, &sc->sc_tx_task); 1942 } 1943 1944 static int 1945 cas_intr(void *v) 1946 { 1947 struct cas_softc *sc = v; 1948 1949 if (__predict_false((CAS_READ_4(sc, CAS_STATUS_ALIAS) & 1950 CAS_INTR_SUMMARY) == 0)) 1951 return (FILTER_STRAY); 1952 1953 /* Disable interrupts. */ 1954 CAS_WRITE_4(sc, CAS_INTMASK, 0xffffffff); 1955 taskqueue_enqueue(sc->sc_tq, &sc->sc_intr_task); 1956 1957 return (FILTER_HANDLED); 1958 } 1959 1960 static void 1961 cas_intr_task(void *arg, int pending __unused) 1962 { 1963 struct cas_softc *sc = arg; 1964 struct ifnet *ifp = sc->sc_ifp; 1965 uint32_t status, status2; 1966 1967 CAS_LOCK_ASSERT(sc, MA_NOTOWNED); 1968 1969 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 1970 return; 1971 1972 status = CAS_READ_4(sc, CAS_STATUS); 1973 if (__predict_false((status & CAS_INTR_SUMMARY) == 0)) 1974 goto done; 1975 1976 CAS_LOCK(sc); 1977 #ifdef CAS_DEBUG 1978 CTR4(KTR_CAS, "%s: %s: cplt %x, status %x", 1979 device_get_name(sc->sc_dev), __func__, 1980 (status >> CAS_STATUS_TX_COMP3_SHFT), (u_int)status); 1981 1982 /* 1983 * PCS interrupts must be cleared, otherwise no traffic is passed! 1984 */ 1985 if ((status & CAS_INTR_PCS_INT) != 0) { 1986 status2 = 1987 CAS_READ_4(sc, CAS_PCS_INTR_STATUS) | 1988 CAS_READ_4(sc, CAS_PCS_INTR_STATUS); 1989 if ((status2 & CAS_PCS_INTR_LINK) != 0) 1990 device_printf(sc->sc_dev, 1991 "%s: PCS link status changed\n", __func__); 1992 } 1993 if ((status & CAS_MAC_CTRL_STATUS) != 0) { 1994 status2 = CAS_READ_4(sc, CAS_MAC_CTRL_STATUS); 1995 if ((status2 & CAS_MAC_CTRL_PAUSE) != 0) 1996 device_printf(sc->sc_dev, 1997 "%s: PAUSE received (PAUSE time %d slots)\n", 1998 __func__, 1999 (status2 & CAS_MAC_CTRL_STATUS_PT_MASK) >> 2000 CAS_MAC_CTRL_STATUS_PT_SHFT); 2001 if ((status2 & CAS_MAC_CTRL_PAUSE) != 0) 2002 device_printf(sc->sc_dev, 2003 "%s: transited to PAUSE state\n", __func__); 2004 if ((status2 & CAS_MAC_CTRL_NON_PAUSE) != 0) 2005 device_printf(sc->sc_dev, 2006 "%s: transited to non-PAUSE state\n", __func__); 2007 } 2008 if ((status & CAS_INTR_MIF) != 0) 2009 device_printf(sc->sc_dev, "%s: MIF interrupt\n", __func__); 2010 #endif 2011 2012 if (__predict_false((status & 2013 (CAS_INTR_TX_TAG_ERR | CAS_INTR_RX_TAG_ERR | 2014 CAS_INTR_RX_LEN_MMATCH | CAS_INTR_PCI_ERROR_INT)) != 0)) { 2015 cas_eint(sc, status); 2016 CAS_UNLOCK(sc); 2017 return; 2018 } 2019 2020 if (__predict_false(status & CAS_INTR_TX_MAC_INT)) { 2021 status2 = CAS_READ_4(sc, CAS_MAC_TX_STATUS); 2022 if ((status2 & 2023 (CAS_MAC_TX_UNDERRUN | CAS_MAC_TX_MAX_PKT_ERR)) != 0) 2024 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 2025 else if ((status2 & ~CAS_MAC_TX_FRAME_XMTD) != 0) 2026 device_printf(sc->sc_dev, 2027 "MAC TX fault, status %x\n", status2); 2028 } 2029 2030 if (__predict_false(status & CAS_INTR_RX_MAC_INT)) { 2031 status2 = CAS_READ_4(sc, CAS_MAC_RX_STATUS); 2032 if ((status2 & CAS_MAC_RX_OVERFLOW) != 0) 2033 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 2034 else if ((status2 & ~CAS_MAC_RX_FRAME_RCVD) != 0) 2035 device_printf(sc->sc_dev, 2036 "MAC RX fault, status %x\n", status2); 2037 } 2038 2039 if ((status & 2040 (CAS_INTR_RX_DONE | CAS_INTR_RX_BUF_NA | CAS_INTR_RX_COMP_FULL | 2041 CAS_INTR_RX_BUF_AEMPTY | CAS_INTR_RX_COMP_AFULL)) != 0) { 2042 cas_rint(sc); 2043 #ifdef CAS_DEBUG 2044 if (__predict_false((status & 2045 (CAS_INTR_RX_BUF_NA | CAS_INTR_RX_COMP_FULL | 2046 CAS_INTR_RX_BUF_AEMPTY | CAS_INTR_RX_COMP_AFULL)) != 0)) 2047 device_printf(sc->sc_dev, 2048 "RX fault, status %x\n", status); 2049 #endif 2050 } 2051 2052 if ((status & 2053 (CAS_INTR_TX_INT_ME | CAS_INTR_TX_ALL | CAS_INTR_TX_DONE)) != 0) 2054 cas_tint(sc); 2055 2056 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 2057 CAS_UNLOCK(sc); 2058 return; 2059 } else if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2060 taskqueue_enqueue(sc->sc_tq, &sc->sc_tx_task); 2061 CAS_UNLOCK(sc); 2062 2063 status = CAS_READ_4(sc, CAS_STATUS_ALIAS); 2064 if (__predict_false((status & CAS_INTR_SUMMARY) != 0)) { 2065 taskqueue_enqueue(sc->sc_tq, &sc->sc_intr_task); 2066 return; 2067 } 2068 2069 done: 2070 /* Re-enable interrupts. */ 2071 CAS_WRITE_4(sc, CAS_INTMASK, 2072 ~(CAS_INTR_TX_INT_ME | CAS_INTR_TX_TAG_ERR | 2073 CAS_INTR_RX_DONE | CAS_INTR_RX_BUF_NA | CAS_INTR_RX_TAG_ERR | 2074 CAS_INTR_RX_COMP_FULL | CAS_INTR_RX_BUF_AEMPTY | 2075 CAS_INTR_RX_COMP_AFULL | CAS_INTR_RX_LEN_MMATCH | 2076 CAS_INTR_PCI_ERROR_INT 2077 #ifdef CAS_DEBUG 2078 | CAS_INTR_PCS_INT | CAS_INTR_MIF 2079 #endif 2080 )); 2081 } 2082 2083 static void 2084 cas_watchdog(struct cas_softc *sc) 2085 { 2086 struct ifnet *ifp = sc->sc_ifp; 2087 2088 CAS_LOCK_ASSERT(sc, MA_OWNED); 2089 2090 #ifdef CAS_DEBUG 2091 CTR4(KTR_CAS, 2092 "%s: CAS_RX_CONF %x CAS_MAC_RX_STATUS %x CAS_MAC_RX_CONF %x", 2093 __func__, CAS_READ_4(sc, CAS_RX_CONF), 2094 CAS_READ_4(sc, CAS_MAC_RX_STATUS), 2095 CAS_READ_4(sc, CAS_MAC_RX_CONF)); 2096 CTR4(KTR_CAS, 2097 "%s: CAS_TX_CONF %x CAS_MAC_TX_STATUS %x CAS_MAC_TX_CONF %x", 2098 __func__, CAS_READ_4(sc, CAS_TX_CONF), 2099 CAS_READ_4(sc, CAS_MAC_TX_STATUS), 2100 CAS_READ_4(sc, CAS_MAC_TX_CONF)); 2101 #endif 2102 2103 if (sc->sc_wdog_timer == 0 || --sc->sc_wdog_timer != 0) 2104 return; 2105 2106 if ((sc->sc_flags & CAS_LINK) != 0) 2107 device_printf(sc->sc_dev, "device timeout\n"); 2108 else if (bootverbose) 2109 device_printf(sc->sc_dev, "device timeout (no link)\n"); 2110 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 2111 2112 /* Try to get more packets going. */ 2113 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2114 cas_init_locked(sc); 2115 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2116 taskqueue_enqueue(sc->sc_tq, &sc->sc_tx_task); 2117 } 2118 2119 static void 2120 cas_mifinit(struct cas_softc *sc) 2121 { 2122 2123 /* Configure the MIF in frame mode. */ 2124 CAS_WRITE_4(sc, CAS_MIF_CONF, 2125 CAS_READ_4(sc, CAS_MIF_CONF) & ~CAS_MIF_CONF_BB_MODE); 2126 CAS_BARRIER(sc, CAS_MIF_CONF, 4, 2127 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 2128 } 2129 2130 /* 2131 * MII interface 2132 * 2133 * The MII interface supports at least three different operating modes: 2134 * 2135 * Bitbang mode is implemented using data, clock and output enable registers. 2136 * 2137 * Frame mode is implemented by loading a complete frame into the frame 2138 * register and polling the valid bit for completion. 2139 * 2140 * Polling mode uses the frame register but completion is indicated by 2141 * an interrupt. 2142 * 2143 */ 2144 static int 2145 cas_mii_readreg(device_t dev, int phy, int reg) 2146 { 2147 struct cas_softc *sc; 2148 int n; 2149 uint32_t v; 2150 2151 #ifdef CAS_DEBUG_PHY 2152 printf("%s: phy %d reg %d\n", __func__, phy, reg); 2153 #endif 2154 2155 sc = device_get_softc(dev); 2156 if ((sc->sc_flags & CAS_SERDES) != 0) { 2157 switch (reg) { 2158 case MII_BMCR: 2159 reg = CAS_PCS_CTRL; 2160 break; 2161 case MII_BMSR: 2162 reg = CAS_PCS_STATUS; 2163 break; 2164 case MII_PHYIDR1: 2165 case MII_PHYIDR2: 2166 return (0); 2167 case MII_ANAR: 2168 reg = CAS_PCS_ANAR; 2169 break; 2170 case MII_ANLPAR: 2171 reg = CAS_PCS_ANLPAR; 2172 break; 2173 case MII_EXTSR: 2174 return (EXTSR_1000XFDX | EXTSR_1000XHDX); 2175 default: 2176 device_printf(sc->sc_dev, 2177 "%s: unhandled register %d\n", __func__, reg); 2178 return (0); 2179 } 2180 return (CAS_READ_4(sc, reg)); 2181 } 2182 2183 /* Construct the frame command. */ 2184 v = CAS_MIF_FRAME_READ | 2185 (phy << CAS_MIF_FRAME_PHY_SHFT) | 2186 (reg << CAS_MIF_FRAME_REG_SHFT); 2187 2188 CAS_WRITE_4(sc, CAS_MIF_FRAME, v); 2189 CAS_BARRIER(sc, CAS_MIF_FRAME, 4, 2190 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 2191 for (n = 0; n < 100; n++) { 2192 DELAY(1); 2193 v = CAS_READ_4(sc, CAS_MIF_FRAME); 2194 if (v & CAS_MIF_FRAME_TA_LSB) 2195 return (v & CAS_MIF_FRAME_DATA); 2196 } 2197 2198 device_printf(sc->sc_dev, "%s: timed out\n", __func__); 2199 return (0); 2200 } 2201 2202 static int 2203 cas_mii_writereg(device_t dev, int phy, int reg, int val) 2204 { 2205 struct cas_softc *sc; 2206 int n; 2207 uint32_t v; 2208 2209 #ifdef CAS_DEBUG_PHY 2210 printf("%s: phy %d reg %d val %x\n", phy, reg, val, __func__); 2211 #endif 2212 2213 sc = device_get_softc(dev); 2214 if ((sc->sc_flags & CAS_SERDES) != 0) { 2215 switch (reg) { 2216 case MII_BMSR: 2217 reg = CAS_PCS_STATUS; 2218 break; 2219 case MII_BMCR: 2220 reg = CAS_PCS_CTRL; 2221 if ((val & CAS_PCS_CTRL_RESET) == 0) 2222 break; 2223 CAS_WRITE_4(sc, CAS_PCS_CTRL, val); 2224 CAS_BARRIER(sc, CAS_PCS_CTRL, 4, 2225 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 2226 if (!cas_bitwait(sc, CAS_PCS_CTRL, 2227 CAS_PCS_CTRL_RESET, 0)) 2228 device_printf(sc->sc_dev, 2229 "cannot reset PCS\n"); 2230 /* FALLTHROUGH */ 2231 case MII_ANAR: 2232 CAS_WRITE_4(sc, CAS_PCS_CONF, 0); 2233 CAS_BARRIER(sc, CAS_PCS_CONF, 4, 2234 BUS_SPACE_BARRIER_WRITE); 2235 CAS_WRITE_4(sc, CAS_PCS_ANAR, val); 2236 CAS_BARRIER(sc, CAS_PCS_ANAR, 4, 2237 BUS_SPACE_BARRIER_WRITE); 2238 CAS_WRITE_4(sc, CAS_PCS_SERDES_CTRL, 2239 CAS_PCS_SERDES_CTRL_ESD); 2240 CAS_BARRIER(sc, CAS_PCS_CONF, 4, 2241 BUS_SPACE_BARRIER_WRITE); 2242 CAS_WRITE_4(sc, CAS_PCS_CONF, 2243 CAS_PCS_CONF_EN); 2244 CAS_BARRIER(sc, CAS_PCS_CONF, 4, 2245 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 2246 return (0); 2247 case MII_ANLPAR: 2248 reg = CAS_PCS_ANLPAR; 2249 break; 2250 default: 2251 device_printf(sc->sc_dev, 2252 "%s: unhandled register %d\n", __func__, reg); 2253 return (0); 2254 } 2255 CAS_WRITE_4(sc, reg, val); 2256 CAS_BARRIER(sc, reg, 4, 2257 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 2258 return (0); 2259 } 2260 2261 /* Construct the frame command. */ 2262 v = CAS_MIF_FRAME_WRITE | 2263 (phy << CAS_MIF_FRAME_PHY_SHFT) | 2264 (reg << CAS_MIF_FRAME_REG_SHFT) | 2265 (val & CAS_MIF_FRAME_DATA); 2266 2267 CAS_WRITE_4(sc, CAS_MIF_FRAME, v); 2268 CAS_BARRIER(sc, CAS_MIF_FRAME, 4, 2269 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 2270 for (n = 0; n < 100; n++) { 2271 DELAY(1); 2272 v = CAS_READ_4(sc, CAS_MIF_FRAME); 2273 if (v & CAS_MIF_FRAME_TA_LSB) 2274 return (1); 2275 } 2276 2277 device_printf(sc->sc_dev, "%s: timed out\n", __func__); 2278 return (0); 2279 } 2280 2281 static void 2282 cas_mii_statchg(device_t dev) 2283 { 2284 struct cas_softc *sc; 2285 struct ifnet *ifp; 2286 int gigabit; 2287 uint32_t rxcfg, txcfg, v; 2288 2289 sc = device_get_softc(dev); 2290 ifp = sc->sc_ifp; 2291 2292 CAS_LOCK_ASSERT(sc, MA_OWNED); 2293 2294 #ifdef CAS_DEBUG 2295 if ((ifp->if_flags & IFF_DEBUG) != 0) 2296 device_printf(sc->sc_dev, "%s: status changen", __func__); 2297 #endif 2298 2299 if ((sc->sc_mii->mii_media_status & IFM_ACTIVE) != 0 && 2300 IFM_SUBTYPE(sc->sc_mii->mii_media_active) != IFM_NONE) 2301 sc->sc_flags |= CAS_LINK; 2302 else 2303 sc->sc_flags &= ~CAS_LINK; 2304 2305 switch (IFM_SUBTYPE(sc->sc_mii->mii_media_active)) { 2306 case IFM_1000_SX: 2307 case IFM_1000_LX: 2308 case IFM_1000_CX: 2309 case IFM_1000_T: 2310 gigabit = 1; 2311 break; 2312 default: 2313 gigabit = 0; 2314 } 2315 2316 /* 2317 * The configuration done here corresponds to the steps F) and 2318 * G) and as far as enabling of RX and TX MAC goes also step H) 2319 * of the initialization sequence outlined in section 11.2.1 of 2320 * the Cassini+ ASIC Specification. 2321 */ 2322 2323 rxcfg = sc->sc_mac_rxcfg; 2324 rxcfg &= ~CAS_MAC_RX_CONF_CARR; 2325 txcfg = CAS_MAC_TX_CONF_EN_IPG0 | CAS_MAC_TX_CONF_NGU | 2326 CAS_MAC_TX_CONF_NGUL; 2327 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) != 0) 2328 txcfg |= CAS_MAC_TX_CONF_ICARR | CAS_MAC_TX_CONF_ICOLLIS; 2329 else if (gigabit != 0) { 2330 rxcfg |= CAS_MAC_RX_CONF_CARR; 2331 txcfg |= CAS_MAC_TX_CONF_CARR; 2332 } 2333 (void)cas_disable_tx(sc); 2334 CAS_WRITE_4(sc, CAS_MAC_TX_CONF, txcfg); 2335 (void)cas_disable_rx(sc); 2336 CAS_WRITE_4(sc, CAS_MAC_RX_CONF, rxcfg); 2337 2338 v = CAS_READ_4(sc, CAS_MAC_CTRL_CONF) & 2339 ~(CAS_MAC_CTRL_CONF_TXP | CAS_MAC_CTRL_CONF_RXP); 2340 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & 2341 IFM_ETH_RXPAUSE) != 0) 2342 v |= CAS_MAC_CTRL_CONF_RXP; 2343 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & 2344 IFM_ETH_TXPAUSE) != 0) 2345 v |= CAS_MAC_CTRL_CONF_TXP; 2346 CAS_WRITE_4(sc, CAS_MAC_CTRL_CONF, v); 2347 2348 /* 2349 * All supported chips have a bug causing incorrect checksum 2350 * to be calculated when letting them strip the FCS in half- 2351 * duplex mode. In theory we could disable FCS stripping and 2352 * manually adjust the checksum accordingly. It seems to make 2353 * more sense to optimze for the common case and just disable 2354 * hardware checksumming in half-duplex mode though. 2355 */ 2356 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) == 0) { 2357 ifp->if_capenable &= ~IFCAP_HWCSUM; 2358 ifp->if_hwassist = 0; 2359 } else if ((sc->sc_flags & CAS_NO_CSUM) == 0) { 2360 ifp->if_capenable = ifp->if_capabilities; 2361 ifp->if_hwassist = CAS_CSUM_FEATURES; 2362 } 2363 2364 if (sc->sc_variant == CAS_SATURN) { 2365 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) == 0) 2366 /* silicon bug workaround */ 2367 CAS_WRITE_4(sc, CAS_MAC_PREAMBLE_LEN, 0x41); 2368 else 2369 CAS_WRITE_4(sc, CAS_MAC_PREAMBLE_LEN, 0x7); 2370 } 2371 2372 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) == 0 && 2373 gigabit != 0) 2374 CAS_WRITE_4(sc, CAS_MAC_SLOT_TIME, 2375 CAS_MAC_SLOT_TIME_CARR); 2376 else 2377 CAS_WRITE_4(sc, CAS_MAC_SLOT_TIME, 2378 CAS_MAC_SLOT_TIME_NORM); 2379 2380 /* XIF Configuration */ 2381 v = CAS_MAC_XIF_CONF_TX_OE | CAS_MAC_XIF_CONF_LNKLED; 2382 if ((sc->sc_flags & CAS_SERDES) == 0) { 2383 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) == 0) 2384 v |= CAS_MAC_XIF_CONF_NOECHO; 2385 v |= CAS_MAC_XIF_CONF_BUF_OE; 2386 } 2387 if (gigabit != 0) 2388 v |= CAS_MAC_XIF_CONF_GMII; 2389 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) != 0) 2390 v |= CAS_MAC_XIF_CONF_FDXLED; 2391 CAS_WRITE_4(sc, CAS_MAC_XIF_CONF, v); 2392 2393 sc->sc_mac_rxcfg = rxcfg; 2394 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && 2395 (sc->sc_flags & CAS_LINK) != 0) { 2396 CAS_WRITE_4(sc, CAS_MAC_TX_CONF, 2397 txcfg | CAS_MAC_TX_CONF_EN); 2398 CAS_WRITE_4(sc, CAS_MAC_RX_CONF, 2399 rxcfg | CAS_MAC_RX_CONF_EN); 2400 } 2401 } 2402 2403 static int 2404 cas_mediachange(struct ifnet *ifp) 2405 { 2406 struct cas_softc *sc = ifp->if_softc; 2407 int error; 2408 2409 /* XXX add support for serial media. */ 2410 2411 CAS_LOCK(sc); 2412 error = mii_mediachg(sc->sc_mii); 2413 CAS_UNLOCK(sc); 2414 return (error); 2415 } 2416 2417 static void 2418 cas_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 2419 { 2420 struct cas_softc *sc = ifp->if_softc; 2421 2422 CAS_LOCK(sc); 2423 if ((ifp->if_flags & IFF_UP) == 0) { 2424 CAS_UNLOCK(sc); 2425 return; 2426 } 2427 2428 mii_pollstat(sc->sc_mii); 2429 ifmr->ifm_active = sc->sc_mii->mii_media_active; 2430 ifmr->ifm_status = sc->sc_mii->mii_media_status; 2431 CAS_UNLOCK(sc); 2432 } 2433 2434 static int 2435 cas_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 2436 { 2437 struct cas_softc *sc = ifp->if_softc; 2438 struct ifreq *ifr = (struct ifreq *)data; 2439 int error; 2440 2441 error = 0; 2442 switch (cmd) { 2443 case SIOCSIFFLAGS: 2444 CAS_LOCK(sc); 2445 if ((ifp->if_flags & IFF_UP) != 0) { 2446 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && 2447 ((ifp->if_flags ^ sc->sc_ifflags) & 2448 (IFF_ALLMULTI | IFF_PROMISC)) != 0) 2449 cas_setladrf(sc); 2450 else 2451 cas_init_locked(sc); 2452 } else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2453 cas_stop(ifp); 2454 sc->sc_ifflags = ifp->if_flags; 2455 CAS_UNLOCK(sc); 2456 break; 2457 case SIOCSIFCAP: 2458 CAS_LOCK(sc); 2459 if ((sc->sc_flags & CAS_NO_CSUM) != 0) { 2460 error = EINVAL; 2461 CAS_UNLOCK(sc); 2462 break; 2463 } 2464 ifp->if_capenable = ifr->ifr_reqcap; 2465 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 2466 ifp->if_hwassist = CAS_CSUM_FEATURES; 2467 else 2468 ifp->if_hwassist = 0; 2469 CAS_UNLOCK(sc); 2470 break; 2471 case SIOCADDMULTI: 2472 case SIOCDELMULTI: 2473 CAS_LOCK(sc); 2474 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2475 cas_setladrf(sc); 2476 CAS_UNLOCK(sc); 2477 break; 2478 case SIOCSIFMTU: 2479 if ((ifr->ifr_mtu < ETHERMIN) || 2480 (ifr->ifr_mtu > ETHERMTU_JUMBO)) 2481 error = EINVAL; 2482 else 2483 ifp->if_mtu = ifr->ifr_mtu; 2484 break; 2485 case SIOCGIFMEDIA: 2486 case SIOCSIFMEDIA: 2487 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii->mii_media, cmd); 2488 break; 2489 default: 2490 error = ether_ioctl(ifp, cmd, data); 2491 break; 2492 } 2493 2494 return (error); 2495 } 2496 2497 static u_int 2498 cas_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 2499 { 2500 uint32_t crc, *hash = arg; 2501 2502 crc = ether_crc32_le(LLADDR(sdl), ETHER_ADDR_LEN); 2503 /* We just want the 8 most significant bits. */ 2504 crc >>= 24; 2505 /* Set the corresponding bit in the filter. */ 2506 hash[crc >> 4] |= 1 << (15 - (crc & 15)); 2507 2508 return (1); 2509 } 2510 2511 static void 2512 cas_setladrf(struct cas_softc *sc) 2513 { 2514 struct ifnet *ifp = sc->sc_ifp; 2515 int i; 2516 uint32_t hash[16]; 2517 uint32_t v; 2518 2519 CAS_LOCK_ASSERT(sc, MA_OWNED); 2520 2521 /* 2522 * Turn off the RX MAC and the hash filter as required by the Sun 2523 * Cassini programming restrictions. 2524 */ 2525 v = sc->sc_mac_rxcfg & ~(CAS_MAC_RX_CONF_HFILTER | 2526 CAS_MAC_RX_CONF_EN); 2527 CAS_WRITE_4(sc, CAS_MAC_RX_CONF, v); 2528 CAS_BARRIER(sc, CAS_MAC_RX_CONF, 4, 2529 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 2530 if (!cas_bitwait(sc, CAS_MAC_RX_CONF, CAS_MAC_RX_CONF_HFILTER | 2531 CAS_MAC_RX_CONF_EN, 0)) 2532 device_printf(sc->sc_dev, 2533 "cannot disable RX MAC or hash filter\n"); 2534 2535 v &= ~(CAS_MAC_RX_CONF_PROMISC | CAS_MAC_RX_CONF_PGRP); 2536 if ((ifp->if_flags & IFF_PROMISC) != 0) { 2537 v |= CAS_MAC_RX_CONF_PROMISC; 2538 goto chipit; 2539 } 2540 if ((ifp->if_flags & IFF_ALLMULTI) != 0) { 2541 v |= CAS_MAC_RX_CONF_PGRP; 2542 goto chipit; 2543 } 2544 2545 /* 2546 * Set up multicast address filter by passing all multicast 2547 * addresses through a crc generator, and then using the high 2548 * order 8 bits as an index into the 256 bit logical address 2549 * filter. The high order 4 bits selects the word, while the 2550 * other 4 bits select the bit within the word (where bit 0 2551 * is the MSB). 2552 */ 2553 2554 memset(hash, 0, sizeof(hash)); 2555 if_foreach_llmaddr(ifp, cas_hash_maddr, &hash); 2556 2557 v |= CAS_MAC_RX_CONF_HFILTER; 2558 2559 /* Now load the hash table into the chip (if we are using it). */ 2560 for (i = 0; i < 16; i++) 2561 CAS_WRITE_4(sc, 2562 CAS_MAC_HASH0 + i * (CAS_MAC_HASH1 - CAS_MAC_HASH0), 2563 hash[i]); 2564 2565 chipit: 2566 sc->sc_mac_rxcfg = v; 2567 CAS_WRITE_4(sc, CAS_MAC_RX_CONF, v | CAS_MAC_RX_CONF_EN); 2568 } 2569 2570 static int cas_pci_attach(device_t dev); 2571 static int cas_pci_detach(device_t dev); 2572 static int cas_pci_probe(device_t dev); 2573 static int cas_pci_resume(device_t dev); 2574 static int cas_pci_suspend(device_t dev); 2575 2576 static device_method_t cas_pci_methods[] = { 2577 /* Device interface */ 2578 DEVMETHOD(device_probe, cas_pci_probe), 2579 DEVMETHOD(device_attach, cas_pci_attach), 2580 DEVMETHOD(device_detach, cas_pci_detach), 2581 DEVMETHOD(device_suspend, cas_pci_suspend), 2582 DEVMETHOD(device_resume, cas_pci_resume), 2583 /* Use the suspend handler here, it is all that is required. */ 2584 DEVMETHOD(device_shutdown, cas_pci_suspend), 2585 2586 /* MII interface */ 2587 DEVMETHOD(miibus_readreg, cas_mii_readreg), 2588 DEVMETHOD(miibus_writereg, cas_mii_writereg), 2589 DEVMETHOD(miibus_statchg, cas_mii_statchg), 2590 2591 DEVMETHOD_END 2592 }; 2593 2594 static driver_t cas_pci_driver = { 2595 "cas", 2596 cas_pci_methods, 2597 sizeof(struct cas_softc) 2598 }; 2599 2600 static const struct cas_pci_dev { 2601 uint32_t cpd_devid; 2602 uint8_t cpd_revid; 2603 int cpd_variant; 2604 const char *cpd_desc; 2605 } cas_pci_devlist[] = { 2606 { 0x0035100b, 0x0, CAS_SATURN, "NS DP83065 Saturn Gigabit Ethernet" }, 2607 { 0xabba108e, 0x10, CAS_CASPLUS, "Sun Cassini+ Gigabit Ethernet" }, 2608 { 0xabba108e, 0x0, CAS_CAS, "Sun Cassini Gigabit Ethernet" }, 2609 { 0, 0, 0, NULL } 2610 }; 2611 2612 DRIVER_MODULE(cas, pci, cas_pci_driver, cas_devclass, 0, 0); 2613 MODULE_PNP_INFO("W32:vendor/device", pci, cas, cas_pci_devlist, 2614 nitems(cas_pci_devlist) - 1); 2615 DRIVER_MODULE(miibus, cas, miibus_driver, miibus_devclass, 0, 0); 2616 MODULE_DEPEND(cas, pci, 1, 1, 1); 2617 2618 static int 2619 cas_pci_probe(device_t dev) 2620 { 2621 int i; 2622 2623 for (i = 0; cas_pci_devlist[i].cpd_desc != NULL; i++) { 2624 if (pci_get_devid(dev) == cas_pci_devlist[i].cpd_devid && 2625 pci_get_revid(dev) >= cas_pci_devlist[i].cpd_revid) { 2626 device_set_desc(dev, cas_pci_devlist[i].cpd_desc); 2627 return (BUS_PROBE_DEFAULT); 2628 } 2629 } 2630 2631 return (ENXIO); 2632 } 2633 2634 static struct resource_spec cas_pci_res_spec[] = { 2635 { SYS_RES_IRQ, 0, RF_SHAREABLE | RF_ACTIVE }, /* CAS_RES_INTR */ 2636 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, /* CAS_RES_MEM */ 2637 { -1, 0 } 2638 }; 2639 2640 #define CAS_LOCAL_MAC_ADDRESS "local-mac-address" 2641 #define CAS_PHY_INTERFACE "phy-interface" 2642 #define CAS_PHY_TYPE "phy-type" 2643 #define CAS_PHY_TYPE_PCS "pcs" 2644 2645 static int 2646 cas_pci_attach(device_t dev) 2647 { 2648 char buf[sizeof(CAS_LOCAL_MAC_ADDRESS)]; 2649 struct cas_softc *sc; 2650 int i; 2651 #if !defined(__powerpc__) 2652 u_char enaddr[4][ETHER_ADDR_LEN]; 2653 u_int j, k, lma, pcs[4], phy; 2654 #endif 2655 2656 sc = device_get_softc(dev); 2657 sc->sc_variant = CAS_UNKNOWN; 2658 for (i = 0; cas_pci_devlist[i].cpd_desc != NULL; i++) { 2659 if (pci_get_devid(dev) == cas_pci_devlist[i].cpd_devid && 2660 pci_get_revid(dev) >= cas_pci_devlist[i].cpd_revid) { 2661 sc->sc_variant = cas_pci_devlist[i].cpd_variant; 2662 break; 2663 } 2664 } 2665 if (sc->sc_variant == CAS_UNKNOWN) { 2666 device_printf(dev, "unknown adaptor\n"); 2667 return (ENXIO); 2668 } 2669 2670 /* PCI configuration */ 2671 pci_write_config(dev, PCIR_COMMAND, 2672 pci_read_config(dev, PCIR_COMMAND, 2) | PCIM_CMD_BUSMASTEREN | 2673 PCIM_CMD_MWRICEN | PCIM_CMD_PERRESPEN | PCIM_CMD_SERRESPEN, 2); 2674 2675 sc->sc_dev = dev; 2676 if (sc->sc_variant == CAS_CAS && pci_get_devid(dev) < 0x02) 2677 /* Hardware checksumming may hang TX. */ 2678 sc->sc_flags |= CAS_NO_CSUM; 2679 if (sc->sc_variant == CAS_CASPLUS || sc->sc_variant == CAS_SATURN) 2680 sc->sc_flags |= CAS_REG_PLUS; 2681 if (sc->sc_variant == CAS_CAS || 2682 (sc->sc_variant == CAS_CASPLUS && pci_get_revid(dev) < 0x11)) 2683 sc->sc_flags |= CAS_TABORT; 2684 if (bootverbose) 2685 device_printf(dev, "flags=0x%x\n", sc->sc_flags); 2686 2687 if (bus_alloc_resources(dev, cas_pci_res_spec, sc->sc_res)) { 2688 device_printf(dev, "failed to allocate resources\n"); 2689 bus_release_resources(dev, cas_pci_res_spec, sc->sc_res); 2690 return (ENXIO); 2691 } 2692 2693 CAS_LOCK_INIT(sc, device_get_nameunit(dev)); 2694 2695 #if defined(__powerpc__) 2696 OF_getetheraddr(dev, sc->sc_enaddr); 2697 if (OF_getprop(ofw_bus_get_node(dev), CAS_PHY_INTERFACE, buf, 2698 sizeof(buf)) > 0 || OF_getprop(ofw_bus_get_node(dev), 2699 CAS_PHY_TYPE, buf, sizeof(buf)) > 0) { 2700 buf[sizeof(buf) - 1] = '\0'; 2701 if (strcmp(buf, CAS_PHY_TYPE_PCS) == 0) 2702 sc->sc_flags |= CAS_SERDES; 2703 } 2704 #else 2705 /* 2706 * Dig out VPD (vital product data) and read the MAC address as well 2707 * as the PHY type. The VPD resides in the PCI Expansion ROM (PCI 2708 * FCode) and can't be accessed via the PCI capability pointer. 2709 * SUNW,pci-ce and SUNW,pci-qge use the Enhanced VPD format described 2710 * in the free US Patent 7149820. 2711 */ 2712 2713 #define PCI_ROMHDR_SIZE 0x1c 2714 #define PCI_ROMHDR_SIG 0x00 2715 #define PCI_ROMHDR_SIG_MAGIC 0xaa55 /* little endian */ 2716 #define PCI_ROMHDR_PTR_DATA 0x18 2717 #define PCI_ROM_SIZE 0x18 2718 #define PCI_ROM_SIG 0x00 2719 #define PCI_ROM_SIG_MAGIC 0x52494350 /* "PCIR", endian */ 2720 /* reversed */ 2721 #define PCI_ROM_VENDOR 0x04 2722 #define PCI_ROM_DEVICE 0x06 2723 #define PCI_ROM_PTR_VPD 0x08 2724 #define PCI_VPDRES_BYTE0 0x00 2725 #define PCI_VPDRES_ISLARGE(x) ((x) & 0x80) 2726 #define PCI_VPDRES_LARGE_NAME(x) ((x) & 0x7f) 2727 #define PCI_VPDRES_LARGE_LEN_LSB 0x01 2728 #define PCI_VPDRES_LARGE_LEN_MSB 0x02 2729 #define PCI_VPDRES_LARGE_SIZE 0x03 2730 #define PCI_VPDRES_TYPE_ID_STRING 0x02 /* large */ 2731 #define PCI_VPDRES_TYPE_VPD 0x10 /* large */ 2732 #define PCI_VPD_KEY0 0x00 2733 #define PCI_VPD_KEY1 0x01 2734 #define PCI_VPD_LEN 0x02 2735 #define PCI_VPD_SIZE 0x03 2736 2737 #define CAS_ROM_READ_1(sc, offs) \ 2738 CAS_READ_1((sc), CAS_PCI_ROM_OFFSET + (offs)) 2739 #define CAS_ROM_READ_2(sc, offs) \ 2740 CAS_READ_2((sc), CAS_PCI_ROM_OFFSET + (offs)) 2741 #define CAS_ROM_READ_4(sc, offs) \ 2742 CAS_READ_4((sc), CAS_PCI_ROM_OFFSET + (offs)) 2743 2744 lma = phy = 0; 2745 memset(enaddr, 0, sizeof(enaddr)); 2746 memset(pcs, 0, sizeof(pcs)); 2747 2748 /* Enable PCI Expansion ROM access. */ 2749 CAS_WRITE_4(sc, CAS_BIM_LDEV_OEN, 2750 CAS_BIM_LDEV_OEN_PAD | CAS_BIM_LDEV_OEN_PROM); 2751 2752 /* Read PCI Expansion ROM header. */ 2753 if (CAS_ROM_READ_2(sc, PCI_ROMHDR_SIG) != PCI_ROMHDR_SIG_MAGIC || 2754 (i = CAS_ROM_READ_2(sc, PCI_ROMHDR_PTR_DATA)) < 2755 PCI_ROMHDR_SIZE) { 2756 device_printf(dev, "unexpected PCI Expansion ROM header\n"); 2757 goto fail_prom; 2758 } 2759 2760 /* Read PCI Expansion ROM data. */ 2761 if (CAS_ROM_READ_4(sc, i + PCI_ROM_SIG) != PCI_ROM_SIG_MAGIC || 2762 CAS_ROM_READ_2(sc, i + PCI_ROM_VENDOR) != pci_get_vendor(dev) || 2763 CAS_ROM_READ_2(sc, i + PCI_ROM_DEVICE) != pci_get_device(dev) || 2764 (j = CAS_ROM_READ_2(sc, i + PCI_ROM_PTR_VPD)) < 2765 i + PCI_ROM_SIZE) { 2766 device_printf(dev, "unexpected PCI Expansion ROM data\n"); 2767 goto fail_prom; 2768 } 2769 2770 /* Read PCI VPD. */ 2771 next: 2772 if (PCI_VPDRES_ISLARGE(CAS_ROM_READ_1(sc, 2773 j + PCI_VPDRES_BYTE0)) == 0) { 2774 device_printf(dev, "no large PCI VPD\n"); 2775 goto fail_prom; 2776 } 2777 2778 i = (CAS_ROM_READ_1(sc, j + PCI_VPDRES_LARGE_LEN_MSB) << 8) | 2779 CAS_ROM_READ_1(sc, j + PCI_VPDRES_LARGE_LEN_LSB); 2780 switch (PCI_VPDRES_LARGE_NAME(CAS_ROM_READ_1(sc, 2781 j + PCI_VPDRES_BYTE0))) { 2782 case PCI_VPDRES_TYPE_ID_STRING: 2783 /* Skip identifier string. */ 2784 j += PCI_VPDRES_LARGE_SIZE + i; 2785 goto next; 2786 case PCI_VPDRES_TYPE_VPD: 2787 for (j += PCI_VPDRES_LARGE_SIZE; i > 0; 2788 i -= PCI_VPD_SIZE + CAS_ROM_READ_1(sc, j + PCI_VPD_LEN), 2789 j += PCI_VPD_SIZE + CAS_ROM_READ_1(sc, j + PCI_VPD_LEN)) { 2790 if (CAS_ROM_READ_1(sc, j + PCI_VPD_KEY0) != 'Z') 2791 /* no Enhanced VPD */ 2792 continue; 2793 if (CAS_ROM_READ_1(sc, j + PCI_VPD_SIZE) != 'I') 2794 /* no instance property */ 2795 continue; 2796 if (CAS_ROM_READ_1(sc, j + PCI_VPD_SIZE + 3) == 'B') { 2797 /* byte array */ 2798 if (CAS_ROM_READ_1(sc, 2799 j + PCI_VPD_SIZE + 4) != ETHER_ADDR_LEN) 2800 continue; 2801 bus_read_region_1(sc->sc_res[CAS_RES_MEM], 2802 CAS_PCI_ROM_OFFSET + j + PCI_VPD_SIZE + 5, 2803 buf, sizeof(buf)); 2804 buf[sizeof(buf) - 1] = '\0'; 2805 if (strcmp(buf, CAS_LOCAL_MAC_ADDRESS) != 0) 2806 continue; 2807 bus_read_region_1(sc->sc_res[CAS_RES_MEM], 2808 CAS_PCI_ROM_OFFSET + j + PCI_VPD_SIZE + 2809 5 + sizeof(CAS_LOCAL_MAC_ADDRESS), 2810 enaddr[lma], sizeof(enaddr[lma])); 2811 lma++; 2812 if (lma == 4 && phy == 4) 2813 break; 2814 } else if (CAS_ROM_READ_1(sc, j + PCI_VPD_SIZE + 3) == 2815 'S') { 2816 /* string */ 2817 if (CAS_ROM_READ_1(sc, 2818 j + PCI_VPD_SIZE + 4) != 2819 sizeof(CAS_PHY_TYPE_PCS)) 2820 continue; 2821 bus_read_region_1(sc->sc_res[CAS_RES_MEM], 2822 CAS_PCI_ROM_OFFSET + j + PCI_VPD_SIZE + 5, 2823 buf, sizeof(buf)); 2824 buf[sizeof(buf) - 1] = '\0'; 2825 if (strcmp(buf, CAS_PHY_INTERFACE) == 0) 2826 k = sizeof(CAS_PHY_INTERFACE); 2827 else if (strcmp(buf, CAS_PHY_TYPE) == 0) 2828 k = sizeof(CAS_PHY_TYPE); 2829 else 2830 continue; 2831 bus_read_region_1(sc->sc_res[CAS_RES_MEM], 2832 CAS_PCI_ROM_OFFSET + j + PCI_VPD_SIZE + 2833 5 + k, buf, sizeof(buf)); 2834 buf[sizeof(buf) - 1] = '\0'; 2835 if (strcmp(buf, CAS_PHY_TYPE_PCS) == 0) 2836 pcs[phy] = 1; 2837 phy++; 2838 if (lma == 4 && phy == 4) 2839 break; 2840 } 2841 } 2842 break; 2843 default: 2844 device_printf(dev, "unexpected PCI VPD\n"); 2845 goto fail_prom; 2846 } 2847 2848 fail_prom: 2849 CAS_WRITE_4(sc, CAS_BIM_LDEV_OEN, 0); 2850 2851 if (lma == 0) { 2852 device_printf(dev, "could not determine Ethernet address\n"); 2853 goto fail; 2854 } 2855 i = 0; 2856 if (lma > 1 && pci_get_slot(dev) < nitems(enaddr)) 2857 i = pci_get_slot(dev); 2858 memcpy(sc->sc_enaddr, enaddr[i], ETHER_ADDR_LEN); 2859 2860 if (phy == 0) { 2861 device_printf(dev, "could not determine PHY type\n"); 2862 goto fail; 2863 } 2864 i = 0; 2865 if (phy > 1 && pci_get_slot(dev) < nitems(pcs)) 2866 i = pci_get_slot(dev); 2867 if (pcs[i] != 0) 2868 sc->sc_flags |= CAS_SERDES; 2869 #endif 2870 2871 if (cas_attach(sc) != 0) { 2872 device_printf(dev, "could not be attached\n"); 2873 goto fail; 2874 } 2875 2876 if (bus_setup_intr(dev, sc->sc_res[CAS_RES_INTR], INTR_TYPE_NET | 2877 INTR_MPSAFE, cas_intr, NULL, sc, &sc->sc_ih) != 0) { 2878 device_printf(dev, "failed to set up interrupt\n"); 2879 cas_detach(sc); 2880 goto fail; 2881 } 2882 return (0); 2883 2884 fail: 2885 CAS_LOCK_DESTROY(sc); 2886 bus_release_resources(dev, cas_pci_res_spec, sc->sc_res); 2887 return (ENXIO); 2888 } 2889 2890 static int 2891 cas_pci_detach(device_t dev) 2892 { 2893 struct cas_softc *sc; 2894 2895 sc = device_get_softc(dev); 2896 bus_teardown_intr(dev, sc->sc_res[CAS_RES_INTR], sc->sc_ih); 2897 cas_detach(sc); 2898 CAS_LOCK_DESTROY(sc); 2899 bus_release_resources(dev, cas_pci_res_spec, sc->sc_res); 2900 return (0); 2901 } 2902 2903 static int 2904 cas_pci_suspend(device_t dev) 2905 { 2906 2907 cas_suspend(device_get_softc(dev)); 2908 return (0); 2909 } 2910 2911 static int 2912 cas_pci_resume(device_t dev) 2913 { 2914 2915 cas_resume(device_get_softc(dev)); 2916 return (0); 2917 } 2918