1 /*- 2 * Copyright (C) 2001 Eduardo Horvath. 3 * Copyright (c) 2001-2003 Thomas Moestl 4 * Copyright (c) 2007-2009 Marius Strobl <marius@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 * from: NetBSD: gem.c,v 1.21 2002/06/01 23:50:58 lukem Exp 29 * from: FreeBSD: if_gem.c 182060 2008-08-23 15:03:26Z marius 30 */ 31 32 #include <sys/cdefs.h> 33 __FBSDID("$FreeBSD$"); 34 35 /* 36 * driver for Sun Cassini/Cassini+ and National Semiconductor DP83065 37 * Saturn Gigabit Ethernet controllers 38 */ 39 40 #if 0 41 #define CAS_DEBUG 42 #endif 43 44 #include <sys/param.h> 45 #include <sys/systm.h> 46 #include <sys/bus.h> 47 #include <sys/callout.h> 48 #include <sys/endian.h> 49 #include <sys/mbuf.h> 50 #include <sys/malloc.h> 51 #include <sys/kernel.h> 52 #include <sys/lock.h> 53 #include <sys/module.h> 54 #include <sys/mutex.h> 55 #include <sys/refcount.h> 56 #include <sys/resource.h> 57 #include <sys/rman.h> 58 #include <sys/socket.h> 59 #include <sys/sockio.h> 60 #include <sys/taskqueue.h> 61 62 #include <net/bpf.h> 63 #include <net/ethernet.h> 64 #include <net/if.h> 65 #include <net/if_arp.h> 66 #include <net/if_dl.h> 67 #include <net/if_media.h> 68 #include <net/if_types.h> 69 #include <net/if_vlan_var.h> 70 71 #include <netinet/in.h> 72 #include <netinet/in_systm.h> 73 #include <netinet/ip.h> 74 #include <netinet/tcp.h> 75 #include <netinet/udp.h> 76 77 #include <machine/bus.h> 78 #if defined(__powerpc__) || defined(__sparc64__) 79 #include <dev/ofw/ofw_bus.h> 80 #include <dev/ofw/openfirm.h> 81 #include <machine/ofw_machdep.h> 82 #endif 83 #include <machine/resource.h> 84 85 #include <dev/mii/mii.h> 86 #include <dev/mii/miivar.h> 87 88 #include <dev/cas/if_casreg.h> 89 #include <dev/cas/if_casvar.h> 90 91 #include <dev/pci/pcireg.h> 92 #include <dev/pci/pcivar.h> 93 94 #include "miibus_if.h" 95 96 #define RINGASSERT(n , min, max) \ 97 CTASSERT(powerof2(n) && (n) >= (min) && (n) <= (max)) 98 99 RINGASSERT(CAS_NRXCOMP, 128, 32768); 100 RINGASSERT(CAS_NRXDESC, 32, 8192); 101 RINGASSERT(CAS_NRXDESC2, 32, 8192); 102 RINGASSERT(CAS_NTXDESC, 32, 8192); 103 104 #undef RINGASSERT 105 106 #define CCDASSERT(m, a) \ 107 CTASSERT((offsetof(struct cas_control_data, m) & ((a) - 1)) == 0) 108 109 CCDASSERT(ccd_rxcomps, CAS_RX_COMP_ALIGN); 110 CCDASSERT(ccd_rxdescs, CAS_RX_DESC_ALIGN); 111 CCDASSERT(ccd_rxdescs2, CAS_RX_DESC_ALIGN); 112 113 #undef CCDASSERT 114 115 #define CAS_TRIES 10000 116 117 /* 118 * According to documentation, the hardware has support for basic TCP 119 * checksum offloading only, in practice this can be also used for UDP 120 * however (i.e. the problem of previous Sun NICs that a checksum of 0x0 121 * is not converted to 0xffff no longer exists). 122 */ 123 #define CAS_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 124 125 static inline void cas_add_rxdesc(struct cas_softc *sc, u_int idx); 126 static int cas_attach(struct cas_softc *sc); 127 static int cas_bitwait(struct cas_softc *sc, bus_addr_t r, uint32_t clr, 128 uint32_t set); 129 static void cas_cddma_callback(void *xsc, bus_dma_segment_t *segs, 130 int nsegs, int error); 131 static void cas_detach(struct cas_softc *sc); 132 static int cas_disable_rx(struct cas_softc *sc); 133 static int cas_disable_tx(struct cas_softc *sc); 134 static void cas_eint(struct cas_softc *sc, u_int status); 135 static void cas_free(void *arg1, void* arg2); 136 static void cas_init(void *xsc); 137 static void cas_init_locked(struct cas_softc *sc); 138 static void cas_init_regs(struct cas_softc *sc); 139 static int cas_intr(void *v); 140 static void cas_intr_task(void *arg, int pending __unused); 141 static int cas_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data); 142 static int cas_load_txmbuf(struct cas_softc *sc, struct mbuf **m_head); 143 static int cas_mediachange(struct ifnet *ifp); 144 static void cas_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr); 145 static void cas_meminit(struct cas_softc *sc); 146 static void cas_mifinit(struct cas_softc *sc); 147 static int cas_mii_readreg(device_t dev, int phy, int reg); 148 static void cas_mii_statchg(device_t dev); 149 static int cas_mii_writereg(device_t dev, int phy, int reg, int val); 150 static void cas_reset(struct cas_softc *sc); 151 static int cas_reset_rx(struct cas_softc *sc); 152 static int cas_reset_tx(struct cas_softc *sc); 153 static void cas_resume(struct cas_softc *sc); 154 static u_int cas_descsize(u_int sz); 155 static void cas_rint(struct cas_softc *sc); 156 static void cas_rint_timeout(void *arg); 157 static inline void cas_rxcksum(struct mbuf *m, uint16_t cksum); 158 static inline void cas_rxcompinit(struct cas_rx_comp *rxcomp); 159 static u_int cas_rxcompsize(u_int sz); 160 static void cas_rxdma_callback(void *xsc, bus_dma_segment_t *segs, 161 int nsegs, int error); 162 static void cas_setladrf(struct cas_softc *sc); 163 static void cas_start(struct ifnet *ifp); 164 static void cas_stop(struct ifnet *ifp); 165 static void cas_suspend(struct cas_softc *sc); 166 static void cas_tick(void *arg); 167 static void cas_tint(struct cas_softc *sc); 168 static void cas_tx_task(void *arg, int pending __unused); 169 static inline void cas_txkick(struct cas_softc *sc); 170 static void cas_watchdog(struct cas_softc *sc); 171 172 static devclass_t cas_devclass; 173 174 MODULE_DEPEND(cas, ether, 1, 1, 1); 175 MODULE_DEPEND(cas, miibus, 1, 1, 1); 176 177 #ifdef CAS_DEBUG 178 #include <sys/ktr.h> 179 #define KTR_CAS KTR_CT2 180 #endif 181 182 static int 183 cas_attach(struct cas_softc *sc) 184 { 185 struct cas_txsoft *txs; 186 struct ifnet *ifp; 187 int error, i; 188 uint32_t v; 189 190 /* Set up ifnet structure. */ 191 ifp = sc->sc_ifp = if_alloc(IFT_ETHER); 192 if (ifp == NULL) 193 return (ENOSPC); 194 ifp->if_softc = sc; 195 if_initname(ifp, device_get_name(sc->sc_dev), 196 device_get_unit(sc->sc_dev)); 197 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 198 ifp->if_start = cas_start; 199 ifp->if_ioctl = cas_ioctl; 200 ifp->if_init = cas_init; 201 IFQ_SET_MAXLEN(&ifp->if_snd, CAS_TXQUEUELEN); 202 ifp->if_snd.ifq_drv_maxlen = CAS_TXQUEUELEN; 203 IFQ_SET_READY(&ifp->if_snd); 204 205 callout_init_mtx(&sc->sc_tick_ch, &sc->sc_mtx, 0); 206 callout_init(&sc->sc_rx_ch, 1); 207 /* Create local taskq. */ 208 TASK_INIT(&sc->sc_intr_task, 0, cas_intr_task, sc); 209 TASK_INIT(&sc->sc_tx_task, 1, cas_tx_task, ifp); 210 sc->sc_tq = taskqueue_create_fast("cas_taskq", M_WAITOK, 211 taskqueue_thread_enqueue, &sc->sc_tq); 212 if (sc->sc_tq == NULL) { 213 device_printf(sc->sc_dev, "could not create taskqueue\n"); 214 error = ENXIO; 215 goto fail_ifnet; 216 } 217 taskqueue_start_threads(&sc->sc_tq, 1, PI_NET, "%s taskq", 218 device_get_nameunit(sc->sc_dev)); 219 220 /* Make sure the chip is stopped. */ 221 cas_reset(sc); 222 223 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, 224 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 225 BUS_SPACE_MAXSIZE, 0, BUS_SPACE_MAXSIZE, 0, NULL, NULL, 226 &sc->sc_pdmatag); 227 if (error != 0) 228 goto fail_taskq; 229 230 error = bus_dma_tag_create(sc->sc_pdmatag, 1, 0, 231 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 232 CAS_PAGE_SIZE, 1, CAS_PAGE_SIZE, 0, NULL, NULL, &sc->sc_rdmatag); 233 if (error != 0) 234 goto fail_ptag; 235 236 error = bus_dma_tag_create(sc->sc_pdmatag, 1, 0, 237 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 238 MCLBYTES * CAS_NTXSEGS, CAS_NTXSEGS, MCLBYTES, 239 BUS_DMA_ALLOCNOW, NULL, NULL, &sc->sc_tdmatag); 240 if (error != 0) 241 goto fail_rtag; 242 243 error = bus_dma_tag_create(sc->sc_pdmatag, CAS_TX_DESC_ALIGN, 0, 244 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 245 sizeof(struct cas_control_data), 1, 246 sizeof(struct cas_control_data), 0, 247 NULL, NULL, &sc->sc_cdmatag); 248 if (error != 0) 249 goto fail_ttag; 250 251 /* 252 * Allocate the control data structures, create and load the 253 * DMA map for it. 254 */ 255 if ((error = bus_dmamem_alloc(sc->sc_cdmatag, 256 (void **)&sc->sc_control_data, 257 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 258 &sc->sc_cddmamap)) != 0) { 259 device_printf(sc->sc_dev, 260 "unable to allocate control data, error = %d\n", error); 261 goto fail_ctag; 262 } 263 264 sc->sc_cddma = 0; 265 if ((error = bus_dmamap_load(sc->sc_cdmatag, sc->sc_cddmamap, 266 sc->sc_control_data, sizeof(struct cas_control_data), 267 cas_cddma_callback, sc, 0)) != 0 || sc->sc_cddma == 0) { 268 device_printf(sc->sc_dev, 269 "unable to load control data DMA map, error = %d\n", 270 error); 271 goto fail_cmem; 272 } 273 274 /* 275 * Initialize the transmit job descriptors. 276 */ 277 STAILQ_INIT(&sc->sc_txfreeq); 278 STAILQ_INIT(&sc->sc_txdirtyq); 279 280 /* 281 * Create the transmit buffer DMA maps. 282 */ 283 error = ENOMEM; 284 for (i = 0; i < CAS_TXQUEUELEN; i++) { 285 txs = &sc->sc_txsoft[i]; 286 txs->txs_mbuf = NULL; 287 txs->txs_ndescs = 0; 288 if ((error = bus_dmamap_create(sc->sc_tdmatag, 0, 289 &txs->txs_dmamap)) != 0) { 290 device_printf(sc->sc_dev, 291 "unable to create TX DMA map %d, error = %d\n", 292 i, error); 293 goto fail_txd; 294 } 295 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 296 } 297 298 /* 299 * Allocate the receive buffers, create and load the DMA maps 300 * for them. 301 */ 302 for (i = 0; i < CAS_NRXDESC; i++) { 303 if ((error = bus_dmamem_alloc(sc->sc_rdmatag, 304 &sc->sc_rxdsoft[i].rxds_buf, BUS_DMA_WAITOK, 305 &sc->sc_rxdsoft[i].rxds_dmamap)) != 0) { 306 device_printf(sc->sc_dev, 307 "unable to allocate RX buffer %d, error = %d\n", 308 i, error); 309 goto fail_rxmem; 310 } 311 312 sc->sc_rxdptr = i; 313 sc->sc_rxdsoft[i].rxds_paddr = 0; 314 if ((error = bus_dmamap_load(sc->sc_rdmatag, 315 sc->sc_rxdsoft[i].rxds_dmamap, sc->sc_rxdsoft[i].rxds_buf, 316 CAS_PAGE_SIZE, cas_rxdma_callback, sc, 0)) != 0 || 317 sc->sc_rxdsoft[i].rxds_paddr == 0) { 318 device_printf(sc->sc_dev, 319 "unable to load RX DMA map %d, error = %d\n", 320 i, error); 321 goto fail_rxmap; 322 } 323 } 324 325 if ((sc->sc_flags & CAS_SERDES) == 0) { 326 CAS_WRITE_4(sc, CAS_PCS_DATAPATH, CAS_PCS_DATAPATH_MII); 327 CAS_BARRIER(sc, CAS_PCS_DATAPATH, 4, 328 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 329 cas_mifinit(sc); 330 /* 331 * Look for an external PHY. 332 */ 333 error = ENXIO; 334 v = CAS_READ_4(sc, CAS_MIF_CONF); 335 if ((v & CAS_MIF_CONF_MDI1) != 0) { 336 v |= CAS_MIF_CONF_PHY_SELECT; 337 CAS_WRITE_4(sc, CAS_MIF_CONF, v); 338 CAS_BARRIER(sc, CAS_MIF_CONF, 4, 339 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 340 /* Enable/unfreeze the GMII pins of Saturn. */ 341 if (sc->sc_variant == CAS_SATURN) { 342 CAS_WRITE_4(sc, CAS_SATURN_PCFG, 0); 343 CAS_BARRIER(sc, CAS_SATURN_PCFG, 4, 344 BUS_SPACE_BARRIER_READ | 345 BUS_SPACE_BARRIER_WRITE); 346 } 347 switch (sc->sc_variant) { 348 default: 349 sc->sc_phyad = -1; 350 break; 351 } 352 error = mii_phy_probe(sc->sc_dev, &sc->sc_miibus, 353 cas_mediachange, cas_mediastatus); 354 } 355 /* 356 * Fall back on an internal PHY if no external PHY was found. 357 */ 358 if (error != 0 && (v & CAS_MIF_CONF_MDI0) != 0) { 359 v &= ~CAS_MIF_CONF_PHY_SELECT; 360 CAS_WRITE_4(sc, CAS_MIF_CONF, v); 361 CAS_BARRIER(sc, CAS_MIF_CONF, 4, 362 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 363 /* Freeze the GMII pins of Saturn for saving power. */ 364 if (sc->sc_variant == CAS_SATURN) { 365 CAS_WRITE_4(sc, CAS_SATURN_PCFG, 366 CAS_SATURN_PCFG_FSI); 367 CAS_BARRIER(sc, CAS_SATURN_PCFG, 4, 368 BUS_SPACE_BARRIER_READ | 369 BUS_SPACE_BARRIER_WRITE); 370 } 371 switch (sc->sc_variant) { 372 default: 373 sc->sc_phyad = -1; 374 break; 375 } 376 error = mii_phy_probe(sc->sc_dev, &sc->sc_miibus, 377 cas_mediachange, cas_mediastatus); 378 } 379 } else { 380 /* 381 * Use the external PCS SERDES. 382 */ 383 CAS_WRITE_4(sc, CAS_PCS_DATAPATH, CAS_PCS_DATAPATH_SERDES); 384 CAS_BARRIER(sc, CAS_PCS_DATAPATH, 4, BUS_SPACE_BARRIER_WRITE); 385 /* Enable/unfreeze the SERDES pins of Saturn. */ 386 if (sc->sc_variant == CAS_SATURN) { 387 CAS_WRITE_4(sc, CAS_SATURN_PCFG, 0); 388 CAS_BARRIER(sc, CAS_SATURN_PCFG, 4, 389 BUS_SPACE_BARRIER_WRITE); 390 } 391 CAS_WRITE_4(sc, CAS_PCS_SERDES_CTRL, CAS_PCS_SERDES_CTRL_ESD); 392 CAS_BARRIER(sc, CAS_PCS_SERDES_CTRL, 4, 393 BUS_SPACE_BARRIER_WRITE); 394 CAS_WRITE_4(sc, CAS_PCS_CONF, CAS_PCS_CONF_EN); 395 CAS_BARRIER(sc, CAS_PCS_CONF, 4, 396 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 397 sc->sc_phyad = CAS_PHYAD_EXTERNAL; 398 error = mii_phy_probe(sc->sc_dev, &sc->sc_miibus, 399 cas_mediachange, cas_mediastatus); 400 } 401 if (error != 0) { 402 device_printf(sc->sc_dev, "PHY probe failed: %d\n", error); 403 goto fail_rxmap; 404 } 405 sc->sc_mii = device_get_softc(sc->sc_miibus); 406 407 /* 408 * From this point forward, the attachment cannot fail. A failure 409 * before this point releases all resources that may have been 410 * allocated. 411 */ 412 413 /* Announce FIFO sizes. */ 414 v = CAS_READ_4(sc, CAS_TX_FIFO_SIZE); 415 device_printf(sc->sc_dev, "%ukB RX FIFO, %ukB TX FIFO\n", 416 CAS_RX_FIFO_SIZE / 1024, v / 16); 417 418 /* Attach the interface. */ 419 ether_ifattach(ifp, sc->sc_enaddr); 420 421 /* 422 * Tell the upper layer(s) we support long frames/checksum offloads. 423 */ 424 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 425 ifp->if_capabilities = IFCAP_VLAN_MTU; 426 if ((sc->sc_flags & CAS_NO_CSUM) == 0) { 427 ifp->if_capabilities |= IFCAP_HWCSUM; 428 ifp->if_hwassist = CAS_CSUM_FEATURES; 429 } 430 ifp->if_capenable = ifp->if_capabilities; 431 432 return (0); 433 434 /* 435 * Free any resources we've allocated during the failed attach 436 * attempt. Do this in reverse order and fall through. 437 */ 438 fail_rxmap: 439 for (i = 0; i < CAS_NRXDESC; i++) 440 if (sc->sc_rxdsoft[i].rxds_paddr != 0) 441 bus_dmamap_unload(sc->sc_rdmatag, 442 sc->sc_rxdsoft[i].rxds_dmamap); 443 fail_rxmem: 444 for (i = 0; i < CAS_NRXDESC; i++) 445 if (sc->sc_rxdsoft[i].rxds_buf != NULL) 446 bus_dmamem_free(sc->sc_rdmatag, 447 sc->sc_rxdsoft[i].rxds_buf, 448 sc->sc_rxdsoft[i].rxds_dmamap); 449 fail_txd: 450 for (i = 0; i < CAS_TXQUEUELEN; i++) 451 if (sc->sc_txsoft[i].txs_dmamap != NULL) 452 bus_dmamap_destroy(sc->sc_tdmatag, 453 sc->sc_txsoft[i].txs_dmamap); 454 bus_dmamap_unload(sc->sc_cdmatag, sc->sc_cddmamap); 455 fail_cmem: 456 bus_dmamem_free(sc->sc_cdmatag, sc->sc_control_data, 457 sc->sc_cddmamap); 458 fail_ctag: 459 bus_dma_tag_destroy(sc->sc_cdmatag); 460 fail_ttag: 461 bus_dma_tag_destroy(sc->sc_tdmatag); 462 fail_rtag: 463 bus_dma_tag_destroy(sc->sc_rdmatag); 464 fail_ptag: 465 bus_dma_tag_destroy(sc->sc_pdmatag); 466 fail_taskq: 467 taskqueue_free(sc->sc_tq); 468 fail_ifnet: 469 if_free(ifp); 470 return (error); 471 } 472 473 static void 474 cas_detach(struct cas_softc *sc) 475 { 476 struct ifnet *ifp = sc->sc_ifp; 477 int i; 478 479 ether_ifdetach(ifp); 480 CAS_LOCK(sc); 481 cas_stop(ifp); 482 CAS_UNLOCK(sc); 483 callout_drain(&sc->sc_tick_ch); 484 callout_drain(&sc->sc_rx_ch); 485 taskqueue_drain(sc->sc_tq, &sc->sc_intr_task); 486 taskqueue_drain(sc->sc_tq, &sc->sc_tx_task); 487 if_free(ifp); 488 taskqueue_free(sc->sc_tq); 489 device_delete_child(sc->sc_dev, sc->sc_miibus); 490 491 for (i = 0; i < CAS_NRXDESC; i++) 492 if (sc->sc_rxdsoft[i].rxds_dmamap != NULL) 493 bus_dmamap_sync(sc->sc_rdmatag, 494 sc->sc_rxdsoft[i].rxds_dmamap, 495 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 496 for (i = 0; i < CAS_NRXDESC; i++) 497 if (sc->sc_rxdsoft[i].rxds_paddr != 0) 498 bus_dmamap_unload(sc->sc_rdmatag, 499 sc->sc_rxdsoft[i].rxds_dmamap); 500 for (i = 0; i < CAS_NRXDESC; i++) 501 if (sc->sc_rxdsoft[i].rxds_buf != NULL) 502 bus_dmamem_free(sc->sc_rdmatag, 503 sc->sc_rxdsoft[i].rxds_buf, 504 sc->sc_rxdsoft[i].rxds_dmamap); 505 for (i = 0; i < CAS_TXQUEUELEN; i++) 506 if (sc->sc_txsoft[i].txs_dmamap != NULL) 507 bus_dmamap_destroy(sc->sc_tdmatag, 508 sc->sc_txsoft[i].txs_dmamap); 509 CAS_CDSYNC(sc, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 510 bus_dmamap_unload(sc->sc_cdmatag, sc->sc_cddmamap); 511 bus_dmamem_free(sc->sc_cdmatag, sc->sc_control_data, 512 sc->sc_cddmamap); 513 bus_dma_tag_destroy(sc->sc_cdmatag); 514 bus_dma_tag_destroy(sc->sc_tdmatag); 515 bus_dma_tag_destroy(sc->sc_rdmatag); 516 bus_dma_tag_destroy(sc->sc_pdmatag); 517 } 518 519 static void 520 cas_suspend(struct cas_softc *sc) 521 { 522 struct ifnet *ifp = sc->sc_ifp; 523 524 CAS_LOCK(sc); 525 cas_stop(ifp); 526 CAS_UNLOCK(sc); 527 } 528 529 static void 530 cas_resume(struct cas_softc *sc) 531 { 532 struct ifnet *ifp = sc->sc_ifp; 533 534 CAS_LOCK(sc); 535 /* 536 * On resume all registers have to be initialized again like 537 * after power-on. 538 */ 539 sc->sc_flags &= ~CAS_INITED; 540 if (ifp->if_flags & IFF_UP) 541 cas_init_locked(sc); 542 CAS_UNLOCK(sc); 543 } 544 545 static inline void 546 cas_rxcksum(struct mbuf *m, uint16_t cksum) 547 { 548 struct ether_header *eh; 549 struct ip *ip; 550 struct udphdr *uh; 551 uint16_t *opts; 552 int32_t hlen, len, pktlen; 553 uint32_t temp32; 554 555 pktlen = m->m_pkthdr.len; 556 if (pktlen < sizeof(struct ether_header) + sizeof(struct ip)) 557 return; 558 eh = mtod(m, struct ether_header *); 559 if (eh->ether_type != htons(ETHERTYPE_IP)) 560 return; 561 ip = (struct ip *)(eh + 1); 562 if (ip->ip_v != IPVERSION) 563 return; 564 565 hlen = ip->ip_hl << 2; 566 pktlen -= sizeof(struct ether_header); 567 if (hlen < sizeof(struct ip)) 568 return; 569 if (ntohs(ip->ip_len) < hlen) 570 return; 571 if (ntohs(ip->ip_len) != pktlen) 572 return; 573 if (ip->ip_off & htons(IP_MF | IP_OFFMASK)) 574 return; /* Cannot handle fragmented packet. */ 575 576 switch (ip->ip_p) { 577 case IPPROTO_TCP: 578 if (pktlen < (hlen + sizeof(struct tcphdr))) 579 return; 580 break; 581 case IPPROTO_UDP: 582 if (pktlen < (hlen + sizeof(struct udphdr))) 583 return; 584 uh = (struct udphdr *)((uint8_t *)ip + hlen); 585 if (uh->uh_sum == 0) 586 return; /* no checksum */ 587 break; 588 default: 589 return; 590 } 591 592 cksum = ~cksum; 593 /* checksum fixup for IP options */ 594 len = hlen - sizeof(struct ip); 595 if (len > 0) { 596 opts = (uint16_t *)(ip + 1); 597 for (; len > 0; len -= sizeof(uint16_t), opts++) { 598 temp32 = cksum - *opts; 599 temp32 = (temp32 >> 16) + (temp32 & 65535); 600 cksum = temp32 & 65535; 601 } 602 } 603 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID; 604 m->m_pkthdr.csum_data = cksum; 605 } 606 607 static void 608 cas_cddma_callback(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 609 { 610 struct cas_softc *sc = xsc; 611 612 if (error != 0) 613 return; 614 if (nsegs != 1) 615 panic("%s: bad control buffer segment count", __func__); 616 sc->sc_cddma = segs[0].ds_addr; 617 } 618 619 static void 620 cas_rxdma_callback(void *xsc, bus_dma_segment_t *segs, int nsegs, int error) 621 { 622 struct cas_softc *sc = xsc; 623 624 if (error != 0) 625 return; 626 if (nsegs != 1) 627 panic("%s: bad RX buffer segment count", __func__); 628 sc->sc_rxdsoft[sc->sc_rxdptr].rxds_paddr = segs[0].ds_addr; 629 } 630 631 static void 632 cas_tick(void *arg) 633 { 634 struct cas_softc *sc = arg; 635 struct ifnet *ifp = sc->sc_ifp; 636 uint32_t v; 637 638 CAS_LOCK_ASSERT(sc, MA_OWNED); 639 640 /* 641 * Unload collision and error counters. 642 */ 643 ifp->if_collisions += 644 CAS_READ_4(sc, CAS_MAC_NORM_COLL_CNT) + 645 CAS_READ_4(sc, CAS_MAC_FIRST_COLL_CNT); 646 v = CAS_READ_4(sc, CAS_MAC_EXCESS_COLL_CNT) + 647 CAS_READ_4(sc, CAS_MAC_LATE_COLL_CNT); 648 ifp->if_collisions += v; 649 ifp->if_oerrors += v; 650 ifp->if_ierrors += 651 CAS_READ_4(sc, CAS_MAC_RX_LEN_ERR_CNT) + 652 CAS_READ_4(sc, CAS_MAC_RX_ALIGN_ERR) + 653 CAS_READ_4(sc, CAS_MAC_RX_CRC_ERR_CNT) + 654 CAS_READ_4(sc, CAS_MAC_RX_CODE_VIOL); 655 656 /* 657 * Then clear the hardware counters. 658 */ 659 CAS_WRITE_4(sc, CAS_MAC_NORM_COLL_CNT, 0); 660 CAS_WRITE_4(sc, CAS_MAC_FIRST_COLL_CNT, 0); 661 CAS_WRITE_4(sc, CAS_MAC_EXCESS_COLL_CNT, 0); 662 CAS_WRITE_4(sc, CAS_MAC_LATE_COLL_CNT, 0); 663 CAS_WRITE_4(sc, CAS_MAC_RX_LEN_ERR_CNT, 0); 664 CAS_WRITE_4(sc, CAS_MAC_RX_ALIGN_ERR, 0); 665 CAS_WRITE_4(sc, CAS_MAC_RX_CRC_ERR_CNT, 0); 666 CAS_WRITE_4(sc, CAS_MAC_RX_CODE_VIOL, 0); 667 668 mii_tick(sc->sc_mii); 669 670 if (sc->sc_txfree != CAS_MAXTXFREE) 671 cas_tint(sc); 672 673 cas_watchdog(sc); 674 675 callout_reset(&sc->sc_tick_ch, hz, cas_tick, sc); 676 } 677 678 static int 679 cas_bitwait(struct cas_softc *sc, bus_addr_t r, uint32_t clr, uint32_t set) 680 { 681 int i; 682 uint32_t reg; 683 684 for (i = CAS_TRIES; i--; DELAY(100)) { 685 reg = CAS_READ_4(sc, r); 686 if ((reg & clr) == 0 && (reg & set) == set) 687 return (1); 688 } 689 return (0); 690 } 691 692 static void 693 cas_reset(struct cas_softc *sc) 694 { 695 696 #ifdef CAS_DEBUG 697 CTR2(KTR_CAS, "%s: %s", device_get_name(sc->sc_dev), __func__); 698 #endif 699 /* Disable all interrupts in order to avoid spurious ones. */ 700 CAS_WRITE_4(sc, CAS_INTMASK, 0xffffffff); 701 702 cas_reset_rx(sc); 703 cas_reset_tx(sc); 704 705 /* 706 * Do a full reset modulo the result of the last auto-negotiation 707 * when using the SERDES. 708 */ 709 CAS_WRITE_4(sc, CAS_RESET, CAS_RESET_RX | CAS_RESET_TX | 710 ((sc->sc_flags & CAS_SERDES) != 0 ? CAS_RESET_PCS_DIS : 0)); 711 CAS_BARRIER(sc, CAS_RESET, 4, 712 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 713 DELAY(3000); 714 if (!cas_bitwait(sc, CAS_RESET, CAS_RESET_RX | CAS_RESET_TX, 0)) 715 device_printf(sc->sc_dev, "cannot reset device\n"); 716 } 717 718 static void 719 cas_stop(struct ifnet *ifp) 720 { 721 struct cas_softc *sc = ifp->if_softc; 722 struct cas_txsoft *txs; 723 724 #ifdef CAS_DEBUG 725 CTR2(KTR_CAS, "%s: %s", device_get_name(sc->sc_dev), __func__); 726 #endif 727 728 callout_stop(&sc->sc_tick_ch); 729 callout_stop(&sc->sc_rx_ch); 730 731 /* Disable all interrupts in order to avoid spurious ones. */ 732 CAS_WRITE_4(sc, CAS_INTMASK, 0xffffffff); 733 734 cas_reset_tx(sc); 735 cas_reset_rx(sc); 736 737 /* 738 * Release any queued transmit buffers. 739 */ 740 while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 741 STAILQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 742 if (txs->txs_ndescs != 0) { 743 bus_dmamap_sync(sc->sc_tdmatag, txs->txs_dmamap, 744 BUS_DMASYNC_POSTWRITE); 745 bus_dmamap_unload(sc->sc_tdmatag, txs->txs_dmamap); 746 if (txs->txs_mbuf != NULL) { 747 m_freem(txs->txs_mbuf); 748 txs->txs_mbuf = NULL; 749 } 750 } 751 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 752 } 753 754 /* 755 * Mark the interface down and cancel the watchdog timer. 756 */ 757 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 758 sc->sc_flags &= ~CAS_LINK; 759 sc->sc_wdog_timer = 0; 760 } 761 762 static int 763 cas_reset_rx(struct cas_softc *sc) 764 { 765 766 /* 767 * Resetting while DMA is in progress can cause a bus hang, so we 768 * disable DMA first. 769 */ 770 cas_disable_rx(sc); 771 CAS_WRITE_4(sc, CAS_RX_CONF, 0); 772 CAS_BARRIER(sc, CAS_RX_CONF, 4, 773 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 774 if (!cas_bitwait(sc, CAS_RX_CONF, CAS_RX_CONF_RXDMA_EN, 0)) 775 device_printf(sc->sc_dev, "cannot disable RX DMA\n"); 776 777 /* Finally, reset the ERX. */ 778 CAS_WRITE_4(sc, CAS_RESET, CAS_RESET_RX | 779 ((sc->sc_flags & CAS_SERDES) != 0 ? CAS_RESET_PCS_DIS : 0)); 780 CAS_BARRIER(sc, CAS_RESET, 4, 781 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 782 if (!cas_bitwait(sc, CAS_RESET, CAS_RESET_RX | CAS_RESET_TX, 0)) { 783 device_printf(sc->sc_dev, "cannot reset receiver\n"); 784 return (1); 785 } 786 return (0); 787 } 788 789 static int 790 cas_reset_tx(struct cas_softc *sc) 791 { 792 793 /* 794 * Resetting while DMA is in progress can cause a bus hang, so we 795 * disable DMA first. 796 */ 797 cas_disable_tx(sc); 798 CAS_WRITE_4(sc, CAS_TX_CONF, 0); 799 CAS_BARRIER(sc, CAS_TX_CONF, 4, 800 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 801 if (!cas_bitwait(sc, CAS_TX_CONF, CAS_TX_CONF_TXDMA_EN, 0)) 802 device_printf(sc->sc_dev, "cannot disable TX DMA\n"); 803 804 /* Finally, reset the ETX. */ 805 CAS_WRITE_4(sc, CAS_RESET, CAS_RESET_TX | 806 ((sc->sc_flags & CAS_SERDES) != 0 ? CAS_RESET_PCS_DIS : 0)); 807 CAS_BARRIER(sc, CAS_RESET, 4, 808 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 809 if (!cas_bitwait(sc, CAS_RESET, CAS_RESET_RX | CAS_RESET_TX, 0)) { 810 device_printf(sc->sc_dev, "cannot reset transmitter\n"); 811 return (1); 812 } 813 return (0); 814 } 815 816 static int 817 cas_disable_rx(struct cas_softc *sc) 818 { 819 820 CAS_WRITE_4(sc, CAS_MAC_RX_CONF, 821 CAS_READ_4(sc, CAS_MAC_RX_CONF) & ~CAS_MAC_RX_CONF_EN); 822 CAS_BARRIER(sc, CAS_MAC_RX_CONF, 4, 823 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 824 return (cas_bitwait(sc, CAS_MAC_RX_CONF, CAS_MAC_RX_CONF_EN, 0)); 825 } 826 827 static int 828 cas_disable_tx(struct cas_softc *sc) 829 { 830 831 CAS_WRITE_4(sc, CAS_MAC_TX_CONF, 832 CAS_READ_4(sc, CAS_MAC_TX_CONF) & ~CAS_MAC_TX_CONF_EN); 833 CAS_BARRIER(sc, CAS_MAC_TX_CONF, 4, 834 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 835 return (cas_bitwait(sc, CAS_MAC_TX_CONF, CAS_MAC_TX_CONF_EN, 0)); 836 } 837 838 static inline void 839 cas_rxcompinit(struct cas_rx_comp *rxcomp) 840 { 841 842 rxcomp->crc_word1 = 0; 843 rxcomp->crc_word2 = 0; 844 rxcomp->crc_word3 = 845 htole64(CAS_SET(ETHER_HDR_LEN + sizeof(struct ip), CAS_RC3_CSO)); 846 rxcomp->crc_word4 = htole64(CAS_RC4_ZERO); 847 } 848 849 static void 850 cas_meminit(struct cas_softc *sc) 851 { 852 int i; 853 854 CAS_LOCK_ASSERT(sc, MA_OWNED); 855 856 /* 857 * Initialize the transmit descriptor ring. 858 */ 859 for (i = 0; i < CAS_NTXDESC; i++) { 860 sc->sc_txdescs[i].cd_flags = 0; 861 sc->sc_txdescs[i].cd_buf_ptr = 0; 862 } 863 sc->sc_txfree = CAS_MAXTXFREE; 864 sc->sc_txnext = 0; 865 sc->sc_txwin = 0; 866 867 /* 868 * Initialize the receive completion ring. 869 */ 870 for (i = 0; i < CAS_NRXCOMP; i++) 871 cas_rxcompinit(&sc->sc_rxcomps[i]); 872 sc->sc_rxcptr = 0; 873 874 /* 875 * Initialize the first receive descriptor ring. We leave 876 * the second one zeroed as we don't actually use it. 877 */ 878 for (i = 0; i < CAS_NRXDESC; i++) 879 CAS_INIT_RXDESC(sc, i, i); 880 sc->sc_rxdptr = 0; 881 882 CAS_CDSYNC(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 883 } 884 885 static u_int 886 cas_descsize(u_int sz) 887 { 888 889 switch (sz) { 890 case 32: 891 return (CAS_DESC_32); 892 case 64: 893 return (CAS_DESC_64); 894 case 128: 895 return (CAS_DESC_128); 896 case 256: 897 return (CAS_DESC_256); 898 case 512: 899 return (CAS_DESC_512); 900 case 1024: 901 return (CAS_DESC_1K); 902 case 2048: 903 return (CAS_DESC_2K); 904 case 4096: 905 return (CAS_DESC_4K); 906 case 8192: 907 return (CAS_DESC_8K); 908 default: 909 printf("%s: invalid descriptor ring size %d\n", __func__, sz); 910 return (CAS_DESC_32); 911 } 912 } 913 914 static u_int 915 cas_rxcompsize(u_int sz) 916 { 917 918 switch (sz) { 919 case 128: 920 return (CAS_RX_CONF_COMP_128); 921 case 256: 922 return (CAS_RX_CONF_COMP_256); 923 case 512: 924 return (CAS_RX_CONF_COMP_512); 925 case 1024: 926 return (CAS_RX_CONF_COMP_1K); 927 case 2048: 928 return (CAS_RX_CONF_COMP_2K); 929 case 4096: 930 return (CAS_RX_CONF_COMP_4K); 931 case 8192: 932 return (CAS_RX_CONF_COMP_8K); 933 case 16384: 934 return (CAS_RX_CONF_COMP_16K); 935 case 32768: 936 return (CAS_RX_CONF_COMP_32K); 937 default: 938 printf("%s: invalid dcompletion ring size %d\n", __func__, sz); 939 return (CAS_RX_CONF_COMP_128); 940 } 941 } 942 943 static void 944 cas_init(void *xsc) 945 { 946 struct cas_softc *sc = xsc; 947 948 CAS_LOCK(sc); 949 cas_init_locked(sc); 950 CAS_UNLOCK(sc); 951 } 952 953 /* 954 * Initialization of interface; set up initialization block 955 * and transmit/receive descriptor rings. 956 */ 957 static void 958 cas_init_locked(struct cas_softc *sc) 959 { 960 struct ifnet *ifp = sc->sc_ifp; 961 uint32_t v; 962 963 CAS_LOCK_ASSERT(sc, MA_OWNED); 964 965 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 966 return; 967 968 #ifdef CAS_DEBUG 969 CTR2(KTR_CAS, "%s: %s: calling stop", device_get_name(sc->sc_dev), 970 __func__); 971 #endif 972 /* 973 * Initialization sequence. The numbered steps below correspond 974 * to the sequence outlined in section 6.3.5.1 in the Ethernet 975 * Channel Engine manual (part of the PCIO manual). 976 * See also the STP2002-STQ document from Sun Microsystems. 977 */ 978 979 /* step 1 & 2. Reset the Ethernet Channel. */ 980 cas_stop(ifp); 981 cas_reset(sc); 982 #ifdef CAS_DEBUG 983 CTR2(KTR_CAS, "%s: %s: restarting", device_get_name(sc->sc_dev), 984 __func__); 985 #endif 986 987 if ((sc->sc_flags & CAS_SERDES) == 0) 988 /* Re-initialize the MIF. */ 989 cas_mifinit(sc); 990 991 /* step 3. Setup data structures in host memory. */ 992 cas_meminit(sc); 993 994 /* step 4. TX MAC registers & counters */ 995 cas_init_regs(sc); 996 997 /* step 5. RX MAC registers & counters */ 998 cas_setladrf(sc); 999 1000 /* step 6 & 7. Program Ring Base Addresses. */ 1001 CAS_WRITE_4(sc, CAS_TX_DESC3_BASE_HI, 1002 (((uint64_t)CAS_CDTXDADDR(sc, 0)) >> 32)); 1003 CAS_WRITE_4(sc, CAS_TX_DESC3_BASE_LO, 1004 CAS_CDTXDADDR(sc, 0) & 0xffffffff); 1005 1006 CAS_WRITE_4(sc, CAS_RX_COMP_BASE_HI, 1007 (((uint64_t)CAS_CDRXCADDR(sc, 0)) >> 32)); 1008 CAS_WRITE_4(sc, CAS_RX_COMP_BASE_LO, 1009 CAS_CDRXCADDR(sc, 0) & 0xffffffff); 1010 1011 CAS_WRITE_4(sc, CAS_RX_DESC_BASE_HI, 1012 (((uint64_t)CAS_CDRXDADDR(sc, 0)) >> 32)); 1013 CAS_WRITE_4(sc, CAS_RX_DESC_BASE_LO, 1014 CAS_CDRXDADDR(sc, 0) & 0xffffffff); 1015 1016 if ((sc->sc_flags & CAS_REG_PLUS) != 0) { 1017 CAS_WRITE_4(sc, CAS_RX_DESC2_BASE_HI, 1018 (((uint64_t)CAS_CDRXD2ADDR(sc, 0)) >> 32)); 1019 CAS_WRITE_4(sc, CAS_RX_DESC2_BASE_LO, 1020 CAS_CDRXD2ADDR(sc, 0) & 0xffffffff); 1021 } 1022 1023 #ifdef CAS_DEBUG 1024 CTR5(KTR_CAS, 1025 "loading TXDR %lx, RXCR %lx, RXDR %lx, RXD2R %lx, cddma %lx", 1026 CAS_CDTXDADDR(sc, 0), CAS_CDRXCADDR(sc, 0), CAS_CDRXDADDR(sc, 0), 1027 CAS_CDRXD2ADDR(sc, 0), sc->sc_cddma); 1028 #endif 1029 1030 /* step 8. Global Configuration & Interrupt Masks */ 1031 1032 /* Disable weighted round robin. */ 1033 CAS_WRITE_4(sc, CAS_CAW, CAS_CAW_RR_DIS); 1034 1035 /* 1036 * Enable infinite bursts for revisions without PCI issues if 1037 * applicable. Doing so greatly improves the TX performance on 1038 * !__sparc64__. 1039 */ 1040 CAS_WRITE_4(sc, CAS_INF_BURST, 1041 #if !defined(__sparc64__) 1042 (sc->sc_flags & CAS_TABORT) == 0 ? CAS_INF_BURST_EN : 1043 #endif 1044 0); 1045 1046 /* Set up interrupts. */ 1047 CAS_WRITE_4(sc, CAS_INTMASK, 1048 ~(CAS_INTR_TX_INT_ME | CAS_INTR_TX_TAG_ERR | 1049 CAS_INTR_RX_DONE | CAS_INTR_RX_BUF_NA | CAS_INTR_RX_TAG_ERR | 1050 CAS_INTR_RX_COMP_FULL | CAS_INTR_RX_BUF_AEMPTY | 1051 CAS_INTR_RX_COMP_AFULL | CAS_INTR_RX_LEN_MMATCH | 1052 CAS_INTR_PCI_ERROR_INT 1053 #ifdef CAS_DEBUG 1054 | CAS_INTR_PCS_INT | CAS_INTR_MIF 1055 #endif 1056 )); 1057 /* Don't clear top level interrupts when CAS_STATUS_ALIAS is read. */ 1058 CAS_WRITE_4(sc, CAS_CLEAR_ALIAS, 0); 1059 CAS_WRITE_4(sc, CAS_MAC_RX_MASK, ~CAS_MAC_RX_OVERFLOW); 1060 CAS_WRITE_4(sc, CAS_MAC_TX_MASK, 1061 ~(CAS_MAC_TX_UNDERRUN | CAS_MAC_TX_MAX_PKT_ERR)); 1062 #ifdef CAS_DEBUG 1063 CAS_WRITE_4(sc, CAS_MAC_CTRL_MASK, 1064 ~(CAS_MAC_CTRL_PAUSE_RCVD | CAS_MAC_CTRL_PAUSE | 1065 CAS_MAC_CTRL_NON_PAUSE)); 1066 #else 1067 CAS_WRITE_4(sc, CAS_MAC_CTRL_MASK, 1068 CAS_MAC_CTRL_PAUSE_RCVD | CAS_MAC_CTRL_PAUSE | 1069 CAS_MAC_CTRL_NON_PAUSE); 1070 #endif 1071 1072 /* Enable PCI error interrupts. */ 1073 CAS_WRITE_4(sc, CAS_ERROR_MASK, 1074 ~(CAS_ERROR_DTRTO | CAS_ERROR_OTHER | CAS_ERROR_DMAW_ZERO | 1075 CAS_ERROR_DMAR_ZERO | CAS_ERROR_RTRTO)); 1076 1077 /* Enable PCI error interrupts in BIM configuration. */ 1078 CAS_WRITE_4(sc, CAS_BIM_CONF, 1079 CAS_BIM_CONF_DPAR_EN | CAS_BIM_CONF_RMA_EN | CAS_BIM_CONF_RTA_EN); 1080 1081 /* 1082 * step 9. ETX Configuration: encode receive descriptor ring size, 1083 * enable DMA and disable pre-interrupt writeback completion. 1084 */ 1085 v = cas_descsize(CAS_NTXDESC) << CAS_TX_CONF_DESC3_SHFT; 1086 CAS_WRITE_4(sc, CAS_TX_CONF, v | CAS_TX_CONF_TXDMA_EN | 1087 CAS_TX_CONF_RDPP_DIS | CAS_TX_CONF_PICWB_DIS); 1088 1089 /* step 10. ERX Configuration */ 1090 1091 /* 1092 * Encode receive completion and descriptor ring sizes, set the 1093 * swivel offset. 1094 */ 1095 v = cas_rxcompsize(CAS_NRXCOMP) << CAS_RX_CONF_COMP_SHFT; 1096 v |= cas_descsize(CAS_NRXDESC) << CAS_RX_CONF_DESC_SHFT; 1097 if ((sc->sc_flags & CAS_REG_PLUS) != 0) 1098 v |= cas_descsize(CAS_NRXDESC2) << CAS_RX_CONF_DESC2_SHFT; 1099 CAS_WRITE_4(sc, CAS_RX_CONF, 1100 v | (ETHER_ALIGN << CAS_RX_CONF_SOFF_SHFT)); 1101 1102 /* Set the PAUSE thresholds. We use the maximum OFF threshold. */ 1103 CAS_WRITE_4(sc, CAS_RX_PTHRS, 1104 ((111 * 64) << CAS_RX_PTHRS_XOFF_SHFT) | 1105 ((15 * 64) << CAS_RX_PTHRS_XON_SHFT)); 1106 1107 /* RX blanking */ 1108 CAS_WRITE_4(sc, CAS_RX_BLANK, 1109 (15 << CAS_RX_BLANK_TIME_SHFT) | (5 << CAS_RX_BLANK_PKTS_SHFT)); 1110 1111 /* Set RX_COMP_AFULL threshold to half of the RX completions. */ 1112 CAS_WRITE_4(sc, CAS_RX_AEMPTY_THRS, 1113 (CAS_NRXCOMP / 2) << CAS_RX_AEMPTY_COMP_SHFT); 1114 1115 /* Initialize the RX page size register as appropriate for 8k. */ 1116 CAS_WRITE_4(sc, CAS_RX_PSZ, 1117 (CAS_RX_PSZ_8K << CAS_RX_PSZ_SHFT) | 1118 (4 << CAS_RX_PSZ_MB_CNT_SHFT) | 1119 (CAS_RX_PSZ_MB_STRD_2K << CAS_RX_PSZ_MB_STRD_SHFT) | 1120 (CAS_RX_PSZ_MB_OFF_64 << CAS_RX_PSZ_MB_OFF_SHFT)); 1121 1122 /* Disable RX random early detection. */ 1123 CAS_WRITE_4(sc, CAS_RX_RED, 0); 1124 1125 /* Zero the RX reassembly DMA table. */ 1126 for (v = 0; v <= CAS_RX_REAS_DMA_ADDR_LC; v++) { 1127 CAS_WRITE_4(sc, CAS_RX_REAS_DMA_ADDR, v); 1128 CAS_WRITE_4(sc, CAS_RX_REAS_DMA_DATA_LO, 0); 1129 CAS_WRITE_4(sc, CAS_RX_REAS_DMA_DATA_MD, 0); 1130 CAS_WRITE_4(sc, CAS_RX_REAS_DMA_DATA_HI, 0); 1131 } 1132 1133 /* Ensure the RX control FIFO and RX IPP FIFO addresses are zero. */ 1134 CAS_WRITE_4(sc, CAS_RX_CTRL_FIFO, 0); 1135 CAS_WRITE_4(sc, CAS_RX_IPP_ADDR, 0); 1136 1137 /* Finally, enable RX DMA. */ 1138 CAS_WRITE_4(sc, CAS_RX_CONF, 1139 CAS_READ_4(sc, CAS_RX_CONF) | CAS_RX_CONF_RXDMA_EN); 1140 1141 /* step 11. Configure Media. */ 1142 1143 /* step 12. RX_MAC Configuration Register */ 1144 v = CAS_READ_4(sc, CAS_MAC_RX_CONF) & ~CAS_MAC_RX_CONF_STRPPAD; 1145 v |= CAS_MAC_RX_CONF_EN | CAS_MAC_RX_CONF_STRPFCS; 1146 CAS_WRITE_4(sc, CAS_MAC_RX_CONF, 0); 1147 CAS_BARRIER(sc, CAS_MAC_RX_CONF, 4, 1148 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 1149 if (!cas_bitwait(sc, CAS_MAC_RX_CONF, CAS_MAC_RX_CONF_EN, 0)) 1150 device_printf(sc->sc_dev, "cannot configure RX MAC\n"); 1151 CAS_WRITE_4(sc, CAS_MAC_RX_CONF, v); 1152 1153 /* step 13. TX_MAC Configuration Register */ 1154 v = CAS_READ_4(sc, CAS_MAC_TX_CONF); 1155 v |= CAS_MAC_TX_CONF_EN; 1156 CAS_WRITE_4(sc, CAS_MAC_TX_CONF, 0); 1157 CAS_BARRIER(sc, CAS_MAC_TX_CONF, 4, 1158 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 1159 if (!cas_bitwait(sc, CAS_MAC_TX_CONF, CAS_MAC_TX_CONF_EN, 0)) 1160 device_printf(sc->sc_dev, "cannot configure TX MAC\n"); 1161 CAS_WRITE_4(sc, CAS_MAC_TX_CONF, v); 1162 1163 /* step 14. Issue Transmit Pending command. */ 1164 1165 /* step 15. Give the reciever a swift kick. */ 1166 CAS_WRITE_4(sc, CAS_RX_KICK, CAS_NRXDESC - 4); 1167 CAS_WRITE_4(sc, CAS_RX_COMP_TAIL, 0); 1168 if ((sc->sc_flags & CAS_REG_PLUS) != 0) 1169 CAS_WRITE_4(sc, CAS_RX_KICK2, CAS_NRXDESC2 - 4); 1170 1171 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1172 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1173 1174 mii_mediachg(sc->sc_mii); 1175 1176 /* Start the one second timer. */ 1177 sc->sc_wdog_timer = 0; 1178 callout_reset(&sc->sc_tick_ch, hz, cas_tick, sc); 1179 } 1180 1181 static int 1182 cas_load_txmbuf(struct cas_softc *sc, struct mbuf **m_head) 1183 { 1184 bus_dma_segment_t txsegs[CAS_NTXSEGS]; 1185 struct cas_txsoft *txs; 1186 struct ip *ip; 1187 struct mbuf *m; 1188 uint64_t cflags; 1189 int error, nexttx, nsegs, offset, seg; 1190 1191 CAS_LOCK_ASSERT(sc, MA_OWNED); 1192 1193 /* Get a work queue entry. */ 1194 if ((txs = STAILQ_FIRST(&sc->sc_txfreeq)) == NULL) { 1195 /* Ran out of descriptors. */ 1196 return (ENOBUFS); 1197 } 1198 1199 cflags = 0; 1200 if (((*m_head)->m_pkthdr.csum_flags & CAS_CSUM_FEATURES) != 0) { 1201 if (M_WRITABLE(*m_head) == 0) { 1202 m = m_dup(*m_head, M_DONTWAIT); 1203 m_freem(*m_head); 1204 *m_head = m; 1205 if (m == NULL) 1206 return (ENOBUFS); 1207 } 1208 offset = sizeof(struct ether_header); 1209 m = m_pullup(*m_head, offset + sizeof(struct ip)); 1210 if (m == NULL) { 1211 *m_head = NULL; 1212 return (ENOBUFS); 1213 } 1214 ip = (struct ip *)(mtod(m, caddr_t) + offset); 1215 offset += (ip->ip_hl << 2); 1216 cflags = (offset << CAS_TD_CKSUM_START_SHFT) | 1217 ((offset + m->m_pkthdr.csum_data) << 1218 CAS_TD_CKSUM_STUFF_SHFT) | CAS_TD_CKSUM_EN; 1219 *m_head = m; 1220 } 1221 1222 error = bus_dmamap_load_mbuf_sg(sc->sc_tdmatag, txs->txs_dmamap, 1223 *m_head, txsegs, &nsegs, BUS_DMA_NOWAIT); 1224 if (error == EFBIG) { 1225 m = m_collapse(*m_head, M_DONTWAIT, CAS_NTXSEGS); 1226 if (m == NULL) { 1227 m_freem(*m_head); 1228 *m_head = NULL; 1229 return (ENOBUFS); 1230 } 1231 *m_head = m; 1232 error = bus_dmamap_load_mbuf_sg(sc->sc_tdmatag, 1233 txs->txs_dmamap, *m_head, txsegs, &nsegs, 1234 BUS_DMA_NOWAIT); 1235 if (error != 0) { 1236 m_freem(*m_head); 1237 *m_head = NULL; 1238 return (error); 1239 } 1240 } else if (error != 0) 1241 return (error); 1242 /* If nsegs is wrong then the stack is corrupt. */ 1243 KASSERT(nsegs <= CAS_NTXSEGS, 1244 ("%s: too many DMA segments (%d)", __func__, nsegs)); 1245 if (nsegs == 0) { 1246 m_freem(*m_head); 1247 *m_head = NULL; 1248 return (EIO); 1249 } 1250 1251 /* 1252 * Ensure we have enough descriptors free to describe 1253 * the packet. Note, we always reserve one descriptor 1254 * at the end of the ring as a termination point, in 1255 * order to prevent wrap-around. 1256 */ 1257 if (nsegs > sc->sc_txfree - 1) { 1258 txs->txs_ndescs = 0; 1259 bus_dmamap_unload(sc->sc_tdmatag, txs->txs_dmamap); 1260 return (ENOBUFS); 1261 } 1262 1263 txs->txs_ndescs = nsegs; 1264 txs->txs_firstdesc = sc->sc_txnext; 1265 nexttx = txs->txs_firstdesc; 1266 for (seg = 0; seg < nsegs; seg++, nexttx = CAS_NEXTTX(nexttx)) { 1267 #ifdef CAS_DEBUG 1268 CTR6(KTR_CAS, 1269 "%s: mapping seg %d (txd %d), len %lx, addr %#lx (%#lx)", 1270 __func__, seg, nexttx, txsegs[seg].ds_len, 1271 txsegs[seg].ds_addr, htole64(txsegs[seg].ds_addr)); 1272 #endif 1273 sc->sc_txdescs[nexttx].cd_buf_ptr = 1274 htole64(txsegs[seg].ds_addr); 1275 KASSERT(txsegs[seg].ds_len < 1276 CAS_TD_BUF_LEN_MASK >> CAS_TD_BUF_LEN_SHFT, 1277 ("%s: segment size too large!", __func__)); 1278 sc->sc_txdescs[nexttx].cd_flags = 1279 htole64(txsegs[seg].ds_len << CAS_TD_BUF_LEN_SHFT); 1280 txs->txs_lastdesc = nexttx; 1281 } 1282 1283 /* Set EOF on the last descriptor. */ 1284 #ifdef CAS_DEBUG 1285 CTR3(KTR_CAS, "%s: end of frame at segment %d, TX %d", 1286 __func__, seg, nexttx); 1287 #endif 1288 sc->sc_txdescs[txs->txs_lastdesc].cd_flags |= 1289 htole64(CAS_TD_END_OF_FRAME); 1290 1291 /* Lastly set SOF on the first descriptor. */ 1292 #ifdef CAS_DEBUG 1293 CTR3(KTR_CAS, "%s: start of frame at segment %d, TX %d", 1294 __func__, seg, nexttx); 1295 #endif 1296 if (sc->sc_txwin += nsegs > CAS_MAXTXFREE * 2 / 3) { 1297 sc->sc_txwin = 0; 1298 sc->sc_txdescs[txs->txs_firstdesc].cd_flags |= 1299 htole64(cflags | CAS_TD_START_OF_FRAME | CAS_TD_INT_ME); 1300 } else 1301 sc->sc_txdescs[txs->txs_firstdesc].cd_flags |= 1302 htole64(cflags | CAS_TD_START_OF_FRAME); 1303 1304 /* Sync the DMA map. */ 1305 bus_dmamap_sync(sc->sc_tdmatag, txs->txs_dmamap, 1306 BUS_DMASYNC_PREWRITE); 1307 1308 #ifdef CAS_DEBUG 1309 CTR4(KTR_CAS, "%s: setting firstdesc=%d, lastdesc=%d, ndescs=%d", 1310 __func__, txs->txs_firstdesc, txs->txs_lastdesc, 1311 txs->txs_ndescs); 1312 #endif 1313 STAILQ_REMOVE_HEAD(&sc->sc_txfreeq, txs_q); 1314 STAILQ_INSERT_TAIL(&sc->sc_txdirtyq, txs, txs_q); 1315 txs->txs_mbuf = *m_head; 1316 1317 sc->sc_txnext = CAS_NEXTTX(txs->txs_lastdesc); 1318 sc->sc_txfree -= txs->txs_ndescs; 1319 1320 return (0); 1321 } 1322 1323 static void 1324 cas_init_regs(struct cas_softc *sc) 1325 { 1326 int i; 1327 const u_char *laddr = IF_LLADDR(sc->sc_ifp); 1328 1329 CAS_LOCK_ASSERT(sc, MA_OWNED); 1330 1331 /* These registers are not cleared on reset. */ 1332 if ((sc->sc_flags & CAS_INITED) == 0) { 1333 /* magic values */ 1334 CAS_WRITE_4(sc, CAS_MAC_IPG0, 0); 1335 CAS_WRITE_4(sc, CAS_MAC_IPG1, 8); 1336 CAS_WRITE_4(sc, CAS_MAC_IPG2, 4); 1337 1338 /* min frame length */ 1339 CAS_WRITE_4(sc, CAS_MAC_MIN_FRAME, ETHER_MIN_LEN); 1340 /* max frame length and max burst size */ 1341 CAS_WRITE_4(sc, CAS_MAC_MAX_BF, 1342 ((ETHER_MAX_LEN_JUMBO + ETHER_VLAN_ENCAP_LEN) << 1343 CAS_MAC_MAX_BF_FRM_SHFT) | 1344 (0x2000 << CAS_MAC_MAX_BF_BST_SHFT)); 1345 1346 /* more magic values */ 1347 CAS_WRITE_4(sc, CAS_MAC_PREAMBLE_LEN, 0x7); 1348 CAS_WRITE_4(sc, CAS_MAC_JAM_SIZE, 0x4); 1349 CAS_WRITE_4(sc, CAS_MAC_ATTEMPT_LIMIT, 0x10); 1350 CAS_WRITE_4(sc, CAS_MAC_CTRL_TYPE, 0x8088); 1351 1352 /* random number seed */ 1353 CAS_WRITE_4(sc, CAS_MAC_RANDOM_SEED, 1354 ((laddr[5] << 8) | laddr[4]) & 0x3ff); 1355 1356 /* secondary MAC addresses: 0:0:0:0:0:0 */ 1357 for (i = CAS_MAC_ADDR3; i <= CAS_MAC_ADDR41; 1358 i += CAS_MAC_ADDR4 - CAS_MAC_ADDR3) 1359 CAS_WRITE_4(sc, i, 0); 1360 1361 /* MAC control address: 01:80:c2:00:00:01 */ 1362 CAS_WRITE_4(sc, CAS_MAC_ADDR42, 0x0001); 1363 CAS_WRITE_4(sc, CAS_MAC_ADDR43, 0xc200); 1364 CAS_WRITE_4(sc, CAS_MAC_ADDR44, 0x0180); 1365 1366 /* MAC filter address: 0:0:0:0:0:0 */ 1367 CAS_WRITE_4(sc, CAS_MAC_AFILTER0, 0); 1368 CAS_WRITE_4(sc, CAS_MAC_AFILTER1, 0); 1369 CAS_WRITE_4(sc, CAS_MAC_AFILTER2, 0); 1370 CAS_WRITE_4(sc, CAS_MAC_AFILTER_MASK1_2, 0); 1371 CAS_WRITE_4(sc, CAS_MAC_AFILTER_MASK0, 0); 1372 1373 /* Zero the hash table. */ 1374 for (i = CAS_MAC_HASH0; i <= CAS_MAC_HASH15; 1375 i += CAS_MAC_HASH1 - CAS_MAC_HASH0) 1376 CAS_WRITE_4(sc, i, 0); 1377 1378 sc->sc_flags |= CAS_INITED; 1379 } 1380 1381 /* Counters need to be zeroed. */ 1382 CAS_WRITE_4(sc, CAS_MAC_NORM_COLL_CNT, 0); 1383 CAS_WRITE_4(sc, CAS_MAC_FIRST_COLL_CNT, 0); 1384 CAS_WRITE_4(sc, CAS_MAC_EXCESS_COLL_CNT, 0); 1385 CAS_WRITE_4(sc, CAS_MAC_LATE_COLL_CNT, 0); 1386 CAS_WRITE_4(sc, CAS_MAC_DEFER_TMR_CNT, 0); 1387 CAS_WRITE_4(sc, CAS_MAC_PEAK_ATTEMPTS, 0); 1388 CAS_WRITE_4(sc, CAS_MAC_RX_FRAME_COUNT, 0); 1389 CAS_WRITE_4(sc, CAS_MAC_RX_LEN_ERR_CNT, 0); 1390 CAS_WRITE_4(sc, CAS_MAC_RX_ALIGN_ERR, 0); 1391 CAS_WRITE_4(sc, CAS_MAC_RX_CRC_ERR_CNT, 0); 1392 CAS_WRITE_4(sc, CAS_MAC_RX_CODE_VIOL, 0); 1393 1394 /* Set XOFF PAUSE time. */ 1395 CAS_WRITE_4(sc, CAS_MAC_SPC, 0x1BF0 << CAS_MAC_SPC_TIME_SHFT); 1396 1397 /* Set the station address. */ 1398 CAS_WRITE_4(sc, CAS_MAC_ADDR0, (laddr[4] << 8) | laddr[5]); 1399 CAS_WRITE_4(sc, CAS_MAC_ADDR1, (laddr[2] << 8) | laddr[3]); 1400 CAS_WRITE_4(sc, CAS_MAC_ADDR2, (laddr[0] << 8) | laddr[1]); 1401 1402 /* Enable MII outputs. */ 1403 CAS_WRITE_4(sc, CAS_MAC_XIF_CONF, CAS_MAC_XIF_CONF_TX_OE); 1404 } 1405 1406 static void 1407 cas_tx_task(void *arg, int pending __unused) 1408 { 1409 struct ifnet *ifp; 1410 1411 ifp = (struct ifnet *)arg; 1412 cas_start(ifp); 1413 } 1414 1415 static inline void 1416 cas_txkick(struct cas_softc *sc) 1417 { 1418 1419 /* 1420 * Update the TX kick register. This register has to point to the 1421 * descriptor after the last valid one and for optimum performance 1422 * should be incremented in multiples of 4 (the DMA engine fetches/ 1423 * updates descriptors in batches of 4). 1424 */ 1425 #ifdef CAS_DEBUG 1426 CTR3(KTR_CAS, "%s: %s: kicking TX %d", 1427 device_get_name(sc->sc_dev), __func__, sc->sc_txnext); 1428 #endif 1429 CAS_CDSYNC(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1430 CAS_WRITE_4(sc, CAS_TX_KICK3, sc->sc_txnext); 1431 } 1432 1433 static void 1434 cas_start(struct ifnet *ifp) 1435 { 1436 struct cas_softc *sc = ifp->if_softc; 1437 struct mbuf *m; 1438 int kicked, ntx; 1439 1440 CAS_LOCK(sc); 1441 1442 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1443 IFF_DRV_RUNNING || (sc->sc_flags & CAS_LINK) == 0) { 1444 CAS_UNLOCK(sc); 1445 return; 1446 } 1447 1448 if (sc->sc_txfree < CAS_MAXTXFREE / 4) 1449 cas_tint(sc); 1450 1451 #ifdef CAS_DEBUG 1452 CTR4(KTR_CAS, "%s: %s: txfree %d, txnext %d", 1453 device_get_name(sc->sc_dev), __func__, sc->sc_txfree, 1454 sc->sc_txnext); 1455 #endif 1456 ntx = 0; 1457 kicked = 0; 1458 for (; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && sc->sc_txfree > 1;) { 1459 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 1460 if (m == NULL) 1461 break; 1462 if (cas_load_txmbuf(sc, &m) != 0) { 1463 if (m == NULL) 1464 break; 1465 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1466 IFQ_DRV_PREPEND(&ifp->if_snd, m); 1467 break; 1468 } 1469 if ((sc->sc_txnext % 4) == 0) { 1470 cas_txkick(sc); 1471 kicked = 1; 1472 } else 1473 kicked = 0; 1474 ntx++; 1475 BPF_MTAP(ifp, m); 1476 } 1477 1478 if (ntx > 0) { 1479 if (kicked == 0) 1480 cas_txkick(sc); 1481 #ifdef CAS_DEBUG 1482 CTR2(KTR_CAS, "%s: packets enqueued, OWN on %d", 1483 device_get_name(sc->sc_dev), sc->sc_txnext); 1484 #endif 1485 1486 /* Set a watchdog timer in case the chip flakes out. */ 1487 sc->sc_wdog_timer = 5; 1488 #ifdef CAS_DEBUG 1489 CTR3(KTR_CAS, "%s: %s: watchdog %d", 1490 device_get_name(sc->sc_dev), __func__, 1491 sc->sc_wdog_timer); 1492 #endif 1493 } 1494 1495 CAS_UNLOCK(sc); 1496 } 1497 1498 static void 1499 cas_tint(struct cas_softc *sc) 1500 { 1501 struct ifnet *ifp = sc->sc_ifp; 1502 struct cas_txsoft *txs; 1503 int progress; 1504 uint32_t txlast; 1505 #ifdef CAS_DEBUG 1506 int i; 1507 1508 CAS_LOCK_ASSERT(sc, MA_OWNED); 1509 1510 CTR2(KTR_CAS, "%s: %s", device_get_name(sc->sc_dev), __func__); 1511 #endif 1512 1513 /* 1514 * Go through our TX list and free mbufs for those 1515 * frames that have been transmitted. 1516 */ 1517 progress = 0; 1518 CAS_CDSYNC(sc, BUS_DMASYNC_POSTREAD); 1519 while ((txs = STAILQ_FIRST(&sc->sc_txdirtyq)) != NULL) { 1520 #ifdef CAS_DEBUG 1521 if ((ifp->if_flags & IFF_DEBUG) != 0) { 1522 printf(" txsoft %p transmit chain:\n", txs); 1523 for (i = txs->txs_firstdesc;; i = CAS_NEXTTX(i)) { 1524 printf("descriptor %d: ", i); 1525 printf("cd_flags: 0x%016llx\t", 1526 (long long)le64toh( 1527 sc->sc_txdescs[i].cd_flags)); 1528 printf("cd_buf_ptr: 0x%016llx\n", 1529 (long long)le64toh( 1530 sc->sc_txdescs[i].cd_buf_ptr)); 1531 if (i == txs->txs_lastdesc) 1532 break; 1533 } 1534 } 1535 #endif 1536 1537 /* 1538 * In theory, we could harvest some descriptors before 1539 * the ring is empty, but that's a bit complicated. 1540 * 1541 * CAS_TX_COMPn points to the last descriptor 1542 * processed + 1. 1543 */ 1544 txlast = CAS_READ_4(sc, CAS_TX_COMP3); 1545 #ifdef CAS_DEBUG 1546 CTR4(KTR_CAS, "%s: txs->txs_firstdesc = %d, " 1547 "txs->txs_lastdesc = %d, txlast = %d", 1548 __func__, txs->txs_firstdesc, txs->txs_lastdesc, txlast); 1549 #endif 1550 if (txs->txs_firstdesc <= txs->txs_lastdesc) { 1551 if ((txlast >= txs->txs_firstdesc) && 1552 (txlast <= txs->txs_lastdesc)) 1553 break; 1554 } else { 1555 /* Ick -- this command wraps. */ 1556 if ((txlast >= txs->txs_firstdesc) || 1557 (txlast <= txs->txs_lastdesc)) 1558 break; 1559 } 1560 1561 #ifdef CAS_DEBUG 1562 CTR1(KTR_CAS, "%s: releasing a descriptor", __func__); 1563 #endif 1564 STAILQ_REMOVE_HEAD(&sc->sc_txdirtyq, txs_q); 1565 1566 sc->sc_txfree += txs->txs_ndescs; 1567 1568 bus_dmamap_sync(sc->sc_tdmatag, txs->txs_dmamap, 1569 BUS_DMASYNC_POSTWRITE); 1570 bus_dmamap_unload(sc->sc_tdmatag, txs->txs_dmamap); 1571 if (txs->txs_mbuf != NULL) { 1572 m_freem(txs->txs_mbuf); 1573 txs->txs_mbuf = NULL; 1574 } 1575 1576 STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q); 1577 1578 ifp->if_opackets++; 1579 progress = 1; 1580 } 1581 1582 #ifdef CAS_DEBUG 1583 CTR4(KTR_CAS, "%s: CAS_TX_STATE_MACHINE %x CAS_TX_DESC_BASE %llx " 1584 "CAS_TX_COMP3 %x", 1585 __func__, CAS_READ_4(sc, CAS_TX_STATE_MACHINE), 1586 ((long long)CAS_READ_4(sc, CAS_TX_DESC_BASE_HI3) << 32) | 1587 CAS_READ_4(sc, CAS_TX_DESC_BASE_LO3), 1588 CAS_READ_4(sc, CAS_TX_COMP3)); 1589 #endif 1590 1591 if (progress) { 1592 /* We freed some descriptors, so reset IFF_DRV_OACTIVE. */ 1593 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1594 if (STAILQ_EMPTY(&sc->sc_txdirtyq)) 1595 sc->sc_wdog_timer = 0; 1596 } 1597 1598 #ifdef CAS_DEBUG 1599 CTR3(KTR_CAS, "%s: %s: watchdog %d", 1600 device_get_name(sc->sc_dev), __func__, sc->sc_wdog_timer); 1601 #endif 1602 } 1603 1604 static void 1605 cas_rint_timeout(void *arg) 1606 { 1607 struct cas_softc *sc = arg; 1608 1609 CAS_LOCK_ASSERT(sc, MA_NOTOWNED); 1610 1611 cas_rint(sc); 1612 } 1613 1614 static void 1615 cas_rint(struct cas_softc *sc) 1616 { 1617 struct cas_rxdsoft *rxds, *rxds2; 1618 struct ifnet *ifp = sc->sc_ifp; 1619 struct mbuf *m, *m2; 1620 uint64_t word1, word2, word3, word4; 1621 uint32_t rxhead; 1622 u_int idx, idx2, len, off, skip; 1623 1624 CAS_LOCK_ASSERT(sc, MA_NOTOWNED); 1625 1626 callout_stop(&sc->sc_rx_ch); 1627 1628 #ifdef CAS_DEBUG 1629 CTR2(KTR_CAS, "%s: %s", device_get_name(sc->sc_dev), __func__); 1630 #endif 1631 1632 #define PRINTWORD(n, delimiter) \ 1633 printf("word ## n: 0x%016llx%c", (long long)word ## n, delimiter) 1634 1635 #define SKIPASSERT(n) \ 1636 KASSERT(sc->sc_rxcomps[sc->sc_rxcptr].crc_word ## n == 0, \ 1637 ("%s: word ## n not 0", __func__)) 1638 1639 #define WORDTOH(n) \ 1640 word ## n = le64toh(sc->sc_rxcomps[sc->sc_rxcptr].crc_word ## n) 1641 1642 /* 1643 * Read the completion head register once. This limits 1644 * how long the following loop can execute. 1645 */ 1646 rxhead = CAS_READ_4(sc, CAS_RX_COMP_HEAD); 1647 #ifdef CAS_DEBUG 1648 CTR4(KTR_CAS, "%s: sc->sc_rxcptr %d, sc->sc_rxdptr %d, head %d", 1649 __func__, sc->rxcptr, sc->sc_rxdptr, rxhead); 1650 #endif 1651 skip = 0; 1652 CAS_CDSYNC(sc, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1653 for (; sc->sc_rxcptr != rxhead; 1654 sc->sc_rxcptr = CAS_NEXTRXCOMP(sc->sc_rxcptr)) { 1655 if (skip != 0) { 1656 SKIPASSERT(1); 1657 SKIPASSERT(2); 1658 SKIPASSERT(3); 1659 1660 --skip; 1661 goto skip; 1662 } 1663 1664 WORDTOH(1); 1665 WORDTOH(2); 1666 WORDTOH(3); 1667 WORDTOH(4); 1668 1669 #ifdef CAS_DEBUG 1670 if ((ifp->if_flags & IFF_DEBUG) != 0) { 1671 printf(" completion %d: ", sc->sc_rxcptr); 1672 PRINTWORD(1, '\t'); 1673 PRINTWORD(2, '\t'); 1674 PRINTWORD(3, '\t'); 1675 PRINTWORD(4, '\n'); 1676 } 1677 #endif 1678 1679 if (__predict_false( 1680 (word1 & CAS_RC1_TYPE_MASK) == CAS_RC1_TYPE_HW || 1681 (word4 & CAS_RC4_ZERO) != 0)) { 1682 /* 1683 * The descriptor is still marked as owned, although 1684 * it is supposed to have completed. This has been 1685 * observed on some machines. Just exiting here 1686 * might leave the packet sitting around until another 1687 * one arrives to trigger a new interrupt, which is 1688 * generally undesirable, so set up a timeout. 1689 */ 1690 callout_reset(&sc->sc_rx_ch, CAS_RXOWN_TICKS, 1691 cas_rint_timeout, sc); 1692 break; 1693 } 1694 1695 if (__predict_false( 1696 (word4 & (CAS_RC4_BAD | CAS_RC4_LEN_MMATCH)) != 0)) { 1697 ifp->if_ierrors++; 1698 device_printf(sc->sc_dev, 1699 "receive error: CRC error\n"); 1700 continue; 1701 } 1702 1703 KASSERT(CAS_GET(word1, CAS_RC1_DATA_SIZE) == 0 || 1704 CAS_GET(word2, CAS_RC2_HDR_SIZE) == 0, 1705 ("%s: data and header present", __func__)); 1706 KASSERT((word1 & CAS_RC1_SPLIT_PKT) == 0 || 1707 CAS_GET(word2, CAS_RC2_HDR_SIZE) == 0, 1708 ("%s: split and header present", __func__)); 1709 KASSERT(CAS_GET(word1, CAS_RC1_DATA_SIZE) == 0 || 1710 (word1 & CAS_RC1_RELEASE_HDR) == 0, 1711 ("%s: data present but header release", __func__)); 1712 KASSERT(CAS_GET(word2, CAS_RC2_HDR_SIZE) == 0 || 1713 (word1 & CAS_RC1_RELEASE_DATA) == 0, 1714 ("%s: header present but data release", __func__)); 1715 1716 if ((len = CAS_GET(word2, CAS_RC2_HDR_SIZE)) != 0) { 1717 idx = CAS_GET(word2, CAS_RC2_HDR_INDEX); 1718 off = CAS_GET(word2, CAS_RC2_HDR_OFF); 1719 #ifdef CAS_DEBUG 1720 CTR4(KTR_CAS, "%s: hdr at idx %d, off %d, len %d", 1721 __func__, idx, off, len); 1722 #endif 1723 rxds = &sc->sc_rxdsoft[idx]; 1724 MGETHDR(m, M_DONTWAIT, MT_DATA); 1725 if (m != NULL) { 1726 refcount_acquire(&rxds->rxds_refcount); 1727 bus_dmamap_sync(sc->sc_rdmatag, 1728 rxds->rxds_dmamap, BUS_DMASYNC_POSTREAD); 1729 #if __FreeBSD_version < 800016 1730 MEXTADD(m, (caddr_t)rxds->rxds_buf + 1731 off * 256 + ETHER_ALIGN, len, cas_free, 1732 rxds, M_RDONLY, EXT_NET_DRV); 1733 #else 1734 MEXTADD(m, (caddr_t)rxds->rxds_buf + 1735 off * 256 + ETHER_ALIGN, len, cas_free, 1736 sc, (void *)(uintptr_t)idx, 1737 M_RDONLY, EXT_NET_DRV); 1738 #endif 1739 if ((m->m_flags & M_EXT) == 0) { 1740 m_freem(m); 1741 m = NULL; 1742 } 1743 } 1744 if (m != NULL) { 1745 m->m_pkthdr.rcvif = ifp; 1746 m->m_pkthdr.len = m->m_len = len; 1747 ifp->if_ipackets++; 1748 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 1749 cas_rxcksum(m, CAS_GET(word4, 1750 CAS_RC4_TCP_CSUM)); 1751 /* Pass it on. */ 1752 (*ifp->if_input)(ifp, m); 1753 } else 1754 ifp->if_ierrors++; 1755 1756 if ((word1 & CAS_RC1_RELEASE_HDR) != 0 && 1757 refcount_release(&rxds->rxds_refcount) != 0) 1758 cas_add_rxdesc(sc, idx); 1759 } else if ((len = CAS_GET(word1, CAS_RC1_DATA_SIZE)) != 0) { 1760 idx = CAS_GET(word1, CAS_RC1_DATA_INDEX); 1761 off = CAS_GET(word1, CAS_RC1_DATA_OFF); 1762 #ifdef CAS_DEBUG 1763 CTR4(KTR_CAS, "%s: data at idx %d, off %d, len %d", 1764 __func__, idx, off, len); 1765 #endif 1766 rxds = &sc->sc_rxdsoft[idx]; 1767 MGETHDR(m, M_DONTWAIT, MT_DATA); 1768 if (m != NULL) { 1769 refcount_acquire(&rxds->rxds_refcount); 1770 off += ETHER_ALIGN; 1771 m->m_len = min(CAS_PAGE_SIZE - off, len); 1772 bus_dmamap_sync(sc->sc_rdmatag, 1773 rxds->rxds_dmamap, BUS_DMASYNC_POSTREAD); 1774 #if __FreeBSD_version < 800016 1775 MEXTADD(m, (caddr_t)rxds->rxds_buf + off, 1776 m->m_len, cas_free, rxds, M_RDONLY, 1777 EXT_NET_DRV); 1778 #else 1779 MEXTADD(m, (caddr_t)rxds->rxds_buf + off, 1780 m->m_len, cas_free, sc, 1781 (void *)(uintptr_t)idx, M_RDONLY, 1782 EXT_NET_DRV); 1783 #endif 1784 if ((m->m_flags & M_EXT) == 0) { 1785 m_freem(m); 1786 m = NULL; 1787 } 1788 } 1789 idx2 = 0; 1790 rxds2 = NULL; 1791 if ((word1 & CAS_RC1_SPLIT_PKT) != 0) { 1792 KASSERT((word1 & CAS_RC1_RELEASE_NEXT) != 0, 1793 ("%s: split but no release next", 1794 __func__)); 1795 1796 idx2 = CAS_GET(word2, CAS_RC2_NEXT_INDEX); 1797 #ifdef CAS_DEBUG 1798 CTR2(KTR_CAS, "%s: split at idx %d", 1799 __func__, idx2); 1800 #endif 1801 rxds2 = &sc->sc_rxdsoft[idx2]; 1802 MGET(m2, M_DONTWAIT, MT_DATA); 1803 if (m2 != NULL) { 1804 refcount_acquire( 1805 &rxds2->rxds_refcount); 1806 m2->m_len = len - m->m_len; 1807 bus_dmamap_sync(sc->sc_rdmatag, 1808 rxds2->rxds_dmamap, 1809 BUS_DMASYNC_POSTREAD); 1810 #if __FreeBSD_version < 800016 1811 MEXTADD(m2, (caddr_t)rxds2->rxds_buf, 1812 m2->m_len, cas_free, rxds2, 1813 M_RDONLY, EXT_NET_DRV); 1814 #else 1815 MEXTADD(m2, (caddr_t)rxds2->rxds_buf, 1816 m2->m_len, cas_free, 1817 sc, (void *)(uintptr_t)idx2, 1818 M_RDONLY, EXT_NET_DRV); 1819 #endif 1820 if ((m2->m_flags & M_EXT) == 0) { 1821 m_freem(m2); 1822 m2 = NULL; 1823 } 1824 } 1825 if (m2 != NULL) 1826 m->m_next = m2; 1827 else { 1828 m_freem(m); 1829 m = NULL; 1830 } 1831 } 1832 if (m != NULL) { 1833 m->m_pkthdr.rcvif = ifp; 1834 m->m_pkthdr.len = len; 1835 ifp->if_ipackets++; 1836 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 1837 cas_rxcksum(m, CAS_GET(word4, 1838 CAS_RC4_TCP_CSUM)); 1839 /* Pass it on. */ 1840 (*ifp->if_input)(ifp, m); 1841 } else 1842 ifp->if_ierrors++; 1843 1844 if ((word1 & CAS_RC1_RELEASE_DATA) != 0 && 1845 refcount_release(&rxds->rxds_refcount) != 0) 1846 cas_add_rxdesc(sc, idx); 1847 if ((word1 & CAS_RC1_SPLIT_PKT) != 0 && 1848 refcount_release(&rxds2->rxds_refcount) != 0) 1849 cas_add_rxdesc(sc, idx2); 1850 } 1851 1852 skip = CAS_GET(word1, CAS_RC1_SKIP); 1853 1854 skip: 1855 cas_rxcompinit(&sc->sc_rxcomps[sc->sc_rxcptr]); 1856 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 1857 break; 1858 } 1859 CAS_CDSYNC(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1860 CAS_WRITE_4(sc, CAS_RX_COMP_TAIL, sc->sc_rxcptr); 1861 1862 #undef PRINTWORD 1863 #undef SKIPASSERT 1864 #undef WORDTOH 1865 1866 #ifdef CAS_DEBUG 1867 CTR4(KTR_CAS, "%s: done sc->sc_rxcptr %d, sc->sc_rxdptr %d, head %d", 1868 __func__, sc->rxcptr, sc->sc_rxdptr, 1869 CAS_READ_4(sc, CAS_RX_COMP_HEAD)); 1870 #endif 1871 } 1872 1873 static void 1874 cas_free(void *arg1, void *arg2) 1875 { 1876 struct cas_rxdsoft *rxds; 1877 struct cas_softc *sc; 1878 u_int idx; 1879 1880 #if __FreeBSD_version < 800016 1881 rxds = arg2; 1882 sc = rxds->rxds_sc; 1883 idx = rxds->rxds_idx; 1884 #else 1885 sc = arg1; 1886 idx = (uintptr_t)arg2; 1887 rxds = &sc->sc_rxdsoft[idx]; 1888 #endif 1889 if (refcount_release(&rxds->rxds_refcount) == 0) 1890 return; 1891 1892 /* 1893 * NB: this function can be called via m_freem(9) within 1894 * this driver! 1895 */ 1896 1897 cas_add_rxdesc(sc, idx); 1898 } 1899 1900 static inline void 1901 cas_add_rxdesc(struct cas_softc *sc, u_int idx) 1902 { 1903 u_int locked; 1904 1905 if ((locked = CAS_LOCK_OWNED(sc)) == 0) 1906 CAS_LOCK(sc); 1907 1908 bus_dmamap_sync(sc->sc_rdmatag, sc->sc_rxdsoft[idx].rxds_dmamap, 1909 BUS_DMASYNC_PREREAD); 1910 CAS_UPDATE_RXDESC(sc, sc->sc_rxdptr, idx); 1911 sc->sc_rxdptr = CAS_NEXTRXDESC(sc->sc_rxdptr); 1912 1913 /* 1914 * Update the RX kick register. This register has to point to the 1915 * descriptor after the last valid one (before the current batch) 1916 * and for optimum performance should be incremented in multiples 1917 * of 4 (the DMA engine fetches/updates descriptors in batches of 4). 1918 */ 1919 if ((sc->sc_rxdptr % 4) == 0) { 1920 CAS_CDSYNC(sc, BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1921 CAS_WRITE_4(sc, CAS_RX_KICK, 1922 (sc->sc_rxdptr + CAS_NRXDESC - 4) & CAS_NRXDESC_MASK); 1923 } 1924 1925 if (locked == 0) 1926 CAS_UNLOCK(sc); 1927 } 1928 1929 static void 1930 cas_eint(struct cas_softc *sc, u_int status) 1931 { 1932 struct ifnet *ifp = sc->sc_ifp; 1933 1934 CAS_LOCK_ASSERT(sc, MA_NOTOWNED); 1935 1936 ifp->if_ierrors++; 1937 1938 device_printf(sc->sc_dev, "%s: status 0x%x", __func__, status); 1939 if ((status & CAS_INTR_PCI_ERROR_INT) != 0) { 1940 status = CAS_READ_4(sc, CAS_ERROR_STATUS); 1941 printf(", PCI bus error 0x%x", status); 1942 if ((status & CAS_ERROR_OTHER) != 0) { 1943 status = pci_read_config(sc->sc_dev, PCIR_STATUS, 2); 1944 printf(", PCI status 0x%x", status); 1945 pci_write_config(sc->sc_dev, PCIR_STATUS, status, 2); 1946 } 1947 } 1948 printf("\n"); 1949 1950 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1951 cas_init(sc); 1952 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1953 taskqueue_enqueue(sc->sc_tq, &sc->sc_tx_task); 1954 } 1955 1956 static int 1957 cas_intr(void *v) 1958 { 1959 struct cas_softc *sc = v; 1960 1961 if (__predict_false((CAS_READ_4(sc, CAS_STATUS_ALIAS) & 1962 CAS_INTR_SUMMARY) == 0)) 1963 return (FILTER_STRAY); 1964 1965 /* Disable interrupts. */ 1966 CAS_WRITE_4(sc, CAS_INTMASK, 0xffffffff); 1967 taskqueue_enqueue(sc->sc_tq, &sc->sc_intr_task); 1968 1969 return (FILTER_HANDLED); 1970 } 1971 1972 static void 1973 cas_intr_task(void *arg, int pending __unused) 1974 { 1975 struct cas_softc *sc = arg; 1976 struct ifnet *ifp = sc->sc_ifp; 1977 uint32_t status, status2; 1978 1979 CAS_LOCK_ASSERT(sc, MA_NOTOWNED); 1980 1981 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 1982 return; 1983 1984 status = CAS_READ_4(sc, CAS_STATUS); 1985 if (__predict_false((status & CAS_INTR_SUMMARY) == 0)) 1986 goto done; 1987 1988 #ifdef CAS_DEBUG 1989 CTR4(KTR_CAS, "%s: %s: cplt %x, status %x", 1990 device_get_name(sc->sc_dev), __func__, 1991 (status >> CAS_STATUS_TX_COMP3_SHIFT), (u_int)status); 1992 1993 /* 1994 * PCS interrupts must be cleared, otherwise no traffic is passed! 1995 */ 1996 if ((status & CAS_INTR_PCS_INT) != 0) { 1997 status2 = 1998 CAS_READ_4(sc, CAS_PCS_INTR_STATUS) | 1999 CAS_READ_4(sc, CAS_PCS_INTR_STATUS); 2000 if ((status2 & CAS_PCS_INTR_LINK) != 0) 2001 device_printf(sc->sc_dev, 2002 "%s: PCS link status changed\n", __func__); 2003 } 2004 if ((status & CAS_MAC_CTRL_STATUS) != 0) { 2005 status2 = CAS_READ_4(sc, CAS_MAC_CTRL_STATUS); 2006 if ((status2 & CAS_MAC_CTRL_PAUSE) != 0) 2007 device_printf(sc->sc_dev, 2008 "%s: PAUSE received (PAUSE time %d slots)\n", 2009 __func__, 2010 (status2 & CAS_MAC_CTRL_STATUS_PT_MASK) >> 2011 CAS_MAC_CTRL_STATUS_PT_SHFT); 2012 if ((status2 & CAS_MAC_CTRL_PAUSE) != 0) 2013 device_printf(sc->sc_dev, 2014 "%s: transited to PAUSE state\n", __func__); 2015 if ((status2 & CAS_MAC_CTRL_NON_PAUSE) != 0) 2016 device_printf(sc->sc_dev, 2017 "%s: transited to non-PAUSE state\n", __func__); 2018 } 2019 if ((status & CAS_INTR_MIF) != 0) 2020 device_printf(sc->sc_dev, "%s: MIF interrupt\n", __func__); 2021 #endif 2022 2023 if (__predict_false((status & 2024 (CAS_INTR_TX_TAG_ERR | CAS_INTR_RX_TAG_ERR | 2025 CAS_INTR_RX_LEN_MMATCH | CAS_INTR_PCI_ERROR_INT)) != 0)) { 2026 cas_eint(sc, status); 2027 return; 2028 } 2029 2030 if (__predict_false(status & CAS_INTR_TX_MAC_INT)) { 2031 status2 = CAS_READ_4(sc, CAS_MAC_TX_STATUS); 2032 if ((status2 & 2033 (CAS_MAC_TX_UNDERRUN | CAS_MAC_TX_MAX_PKT_ERR)) != 0) 2034 sc->sc_ifp->if_oerrors++; 2035 else if ((status2 & ~CAS_MAC_TX_FRAME_XMTD) != 0) 2036 device_printf(sc->sc_dev, 2037 "MAC TX fault, status %x\n", status2); 2038 } 2039 2040 if (__predict_false(status & CAS_INTR_RX_MAC_INT)) { 2041 status2 = CAS_READ_4(sc, CAS_MAC_RX_STATUS); 2042 if ((status2 & CAS_MAC_RX_OVERFLOW) != 0) 2043 sc->sc_ifp->if_ierrors++; 2044 else if ((status2 & ~CAS_MAC_RX_FRAME_RCVD) != 0) 2045 device_printf(sc->sc_dev, 2046 "MAC RX fault, status %x\n", status2); 2047 } 2048 2049 if ((status & 2050 (CAS_INTR_RX_DONE | CAS_INTR_RX_BUF_NA | CAS_INTR_RX_COMP_FULL | 2051 CAS_INTR_RX_BUF_AEMPTY | CAS_INTR_RX_COMP_AFULL)) != 0) { 2052 cas_rint(sc); 2053 #ifdef CAS_DEBUG 2054 if (__predict_false((status & 2055 (CAS_INTR_RX_BUF_NA | CAS_INTR_RX_COMP_FULL | 2056 CAS_INTR_RX_BUF_AEMPTY | CAS_INTR_RX_COMP_AFULL)) != 0)) 2057 device_printf(sc->sc_dev, 2058 "RX fault, status %x\n", status); 2059 #endif 2060 } 2061 2062 if ((status & 2063 (CAS_INTR_TX_INT_ME | CAS_INTR_TX_ALL | CAS_INTR_TX_DONE)) != 0) { 2064 CAS_LOCK(sc); 2065 cas_tint(sc); 2066 CAS_UNLOCK(sc); 2067 } 2068 2069 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 2070 return; 2071 else if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2072 taskqueue_enqueue(sc->sc_tq, &sc->sc_tx_task); 2073 2074 status = CAS_READ_4(sc, CAS_STATUS_ALIAS); 2075 if (__predict_false((status & CAS_INTR_SUMMARY) != 0)) { 2076 taskqueue_enqueue(sc->sc_tq, &sc->sc_intr_task); 2077 return; 2078 } 2079 2080 done: 2081 /* Re-enable interrupts. */ 2082 CAS_WRITE_4(sc, CAS_INTMASK, 2083 ~(CAS_INTR_TX_INT_ME | CAS_INTR_TX_TAG_ERR | 2084 CAS_INTR_RX_DONE | CAS_INTR_RX_BUF_NA | CAS_INTR_RX_TAG_ERR | 2085 CAS_INTR_RX_COMP_FULL | CAS_INTR_RX_BUF_AEMPTY | 2086 CAS_INTR_RX_COMP_AFULL | CAS_INTR_RX_LEN_MMATCH | 2087 CAS_INTR_PCI_ERROR_INT 2088 #ifdef CAS_DEBUG 2089 | CAS_INTR_PCS_INT | CAS_INTR_MIF 2090 #endif 2091 )); 2092 } 2093 2094 static void 2095 cas_watchdog(struct cas_softc *sc) 2096 { 2097 struct ifnet *ifp = sc->sc_ifp; 2098 2099 CAS_LOCK_ASSERT(sc, MA_OWNED); 2100 2101 #ifdef CAS_DEBUG 2102 CTR4(KTR_CAS, 2103 "%s: CAS_RX_CONFIG %x CAS_MAC_RX_STATUS %x CAS_MAC_RX_CONFIG %x", 2104 __func__, CAS_READ_4(sc, CAS_RX_CONFIG), 2105 CAS_READ_4(sc, CAS_MAC_RX_STATUS), 2106 CAS_READ_4(sc, CAS_MAC_RX_CONFIG)); 2107 CTR4(KTR_CAS, 2108 "%s: CAS_TX_CONFIG %x CAS_MAC_TX_STATUS %x CAS_MAC_TX_CONFIG %x", 2109 __func__, CAS_READ_4(sc, CAS_TX_CONFIG), 2110 CAS_READ_4(sc, CAS_MAC_TX_STATUS), 2111 CAS_READ_4(sc, CAS_MAC_TX_CONFIG)); 2112 #endif 2113 2114 if (sc->sc_wdog_timer == 0 || --sc->sc_wdog_timer != 0) 2115 return; 2116 2117 if ((sc->sc_flags & CAS_LINK) != 0) 2118 device_printf(sc->sc_dev, "device timeout\n"); 2119 else if (bootverbose) 2120 device_printf(sc->sc_dev, "device timeout (no link)\n"); 2121 ++ifp->if_oerrors; 2122 2123 /* Try to get more packets going. */ 2124 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2125 cas_init_locked(sc); 2126 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2127 taskqueue_enqueue(sc->sc_tq, &sc->sc_tx_task); 2128 } 2129 2130 static void 2131 cas_mifinit(struct cas_softc *sc) 2132 { 2133 2134 /* Configure the MIF in frame mode. */ 2135 CAS_WRITE_4(sc, CAS_MIF_CONF, 2136 CAS_READ_4(sc, CAS_MIF_CONF) & ~CAS_MIF_CONF_BB_MODE); 2137 CAS_BARRIER(sc, CAS_MIF_CONF, 4, 2138 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 2139 } 2140 2141 /* 2142 * MII interface 2143 * 2144 * The MII interface supports at least three different operating modes: 2145 * 2146 * Bitbang mode is implemented using data, clock and output enable registers. 2147 * 2148 * Frame mode is implemented by loading a complete frame into the frame 2149 * register and polling the valid bit for completion. 2150 * 2151 * Polling mode uses the frame register but completion is indicated by 2152 * an interrupt. 2153 * 2154 */ 2155 static int 2156 cas_mii_readreg(device_t dev, int phy, int reg) 2157 { 2158 struct cas_softc *sc; 2159 int n; 2160 uint32_t v; 2161 2162 #ifdef CAS_DEBUG_PHY 2163 printf("%s: phy %d reg %d\n", __func__, phy, reg); 2164 #endif 2165 2166 sc = device_get_softc(dev); 2167 if (sc->sc_phyad != -1 && phy != sc->sc_phyad) 2168 return (0); 2169 2170 if ((sc->sc_flags & CAS_SERDES) != 0) { 2171 switch (reg) { 2172 case MII_BMCR: 2173 reg = CAS_PCS_CTRL; 2174 break; 2175 case MII_BMSR: 2176 reg = CAS_PCS_STATUS; 2177 break; 2178 case MII_PHYIDR1: 2179 case MII_PHYIDR2: 2180 return (0); 2181 case MII_ANAR: 2182 reg = CAS_PCS_ANAR; 2183 break; 2184 case MII_ANLPAR: 2185 reg = CAS_PCS_ANLPAR; 2186 break; 2187 case MII_EXTSR: 2188 return (EXTSR_1000XFDX | EXTSR_1000XHDX); 2189 default: 2190 device_printf(sc->sc_dev, 2191 "%s: unhandled register %d\n", __func__, reg); 2192 return (0); 2193 } 2194 return (CAS_READ_4(sc, reg)); 2195 } 2196 2197 /* Construct the frame command. */ 2198 v = CAS_MIF_FRAME_READ | 2199 (phy << CAS_MIF_FRAME_PHY_SHFT) | 2200 (reg << CAS_MIF_FRAME_REG_SHFT); 2201 2202 CAS_WRITE_4(sc, CAS_MIF_FRAME, v); 2203 CAS_BARRIER(sc, CAS_MIF_FRAME, 4, 2204 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 2205 for (n = 0; n < 100; n++) { 2206 DELAY(1); 2207 v = CAS_READ_4(sc, CAS_MIF_FRAME); 2208 if (v & CAS_MIF_FRAME_TA_LSB) 2209 return (v & CAS_MIF_FRAME_DATA); 2210 } 2211 2212 device_printf(sc->sc_dev, "%s: timed out\n", __func__); 2213 return (0); 2214 } 2215 2216 static int 2217 cas_mii_writereg(device_t dev, int phy, int reg, int val) 2218 { 2219 struct cas_softc *sc; 2220 int n; 2221 uint32_t v; 2222 2223 #ifdef CAS_DEBUG_PHY 2224 printf("%s: phy %d reg %d val %x\n", phy, reg, val, __func__); 2225 #endif 2226 2227 sc = device_get_softc(dev); 2228 if (sc->sc_phyad != -1 && phy != sc->sc_phyad) 2229 return (0); 2230 2231 if ((sc->sc_flags & CAS_SERDES) != 0) { 2232 switch (reg) { 2233 case MII_BMSR: 2234 reg = CAS_PCS_STATUS; 2235 break; 2236 case MII_BMCR: 2237 reg = CAS_PCS_CTRL; 2238 if ((val & CAS_PCS_CTRL_RESET) == 0) 2239 break; 2240 CAS_WRITE_4(sc, CAS_PCS_CTRL, val); 2241 CAS_BARRIER(sc, CAS_PCS_CTRL, 4, 2242 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 2243 if (!cas_bitwait(sc, CAS_PCS_CTRL, 2244 CAS_PCS_CTRL_RESET, 0)) 2245 device_printf(sc->sc_dev, 2246 "cannot reset PCS\n"); 2247 /* FALLTHROUGH */ 2248 case MII_ANAR: 2249 CAS_WRITE_4(sc, CAS_PCS_CONF, 0); 2250 CAS_BARRIER(sc, CAS_PCS_CONF, 4, 2251 BUS_SPACE_BARRIER_WRITE); 2252 CAS_WRITE_4(sc, CAS_PCS_ANAR, val); 2253 CAS_BARRIER(sc, CAS_PCS_ANAR, 4, 2254 BUS_SPACE_BARRIER_WRITE); 2255 CAS_WRITE_4(sc, CAS_PCS_SERDES_CTRL, 2256 CAS_PCS_SERDES_CTRL_ESD); 2257 CAS_BARRIER(sc, CAS_PCS_CONF, 4, 2258 BUS_SPACE_BARRIER_WRITE); 2259 CAS_WRITE_4(sc, CAS_PCS_CONF, 2260 CAS_PCS_CONF_EN); 2261 CAS_BARRIER(sc, CAS_PCS_CONF, 4, 2262 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 2263 return (0); 2264 case MII_ANLPAR: 2265 reg = CAS_PCS_ANLPAR; 2266 break; 2267 default: 2268 device_printf(sc->sc_dev, 2269 "%s: unhandled register %d\n", __func__, reg); 2270 return (0); 2271 } 2272 CAS_WRITE_4(sc, reg, val); 2273 CAS_BARRIER(sc, reg, 4, 2274 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 2275 return (0); 2276 } 2277 2278 /* Construct the frame command. */ 2279 v = CAS_MIF_FRAME_WRITE | 2280 (phy << CAS_MIF_FRAME_PHY_SHFT) | 2281 (reg << CAS_MIF_FRAME_REG_SHFT) | 2282 (val & CAS_MIF_FRAME_DATA); 2283 2284 CAS_WRITE_4(sc, CAS_MIF_FRAME, v); 2285 CAS_BARRIER(sc, CAS_MIF_FRAME, 4, 2286 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 2287 for (n = 0; n < 100; n++) { 2288 DELAY(1); 2289 v = CAS_READ_4(sc, CAS_MIF_FRAME); 2290 if (v & CAS_MIF_FRAME_TA_LSB) 2291 return (1); 2292 } 2293 2294 device_printf(sc->sc_dev, "%s: timed out\n", __func__); 2295 return (0); 2296 } 2297 2298 static void 2299 cas_mii_statchg(device_t dev) 2300 { 2301 struct cas_softc *sc; 2302 struct ifnet *ifp; 2303 int gigabit; 2304 uint32_t rxcfg, txcfg, v; 2305 2306 sc = device_get_softc(dev); 2307 ifp = sc->sc_ifp; 2308 2309 CAS_LOCK_ASSERT(sc, MA_OWNED); 2310 2311 #ifdef CAS_DEBUG 2312 if ((ifp->if_flags & IFF_DEBUG) != 0) 2313 device_printf(sc->sc_dev, "%s: status change: PHY = %d\n", 2314 __func__, sc->sc_phyad); 2315 #endif 2316 2317 if ((sc->sc_mii->mii_media_status & IFM_ACTIVE) != 0 && 2318 IFM_SUBTYPE(sc->sc_mii->mii_media_active) != IFM_NONE) 2319 sc->sc_flags |= CAS_LINK; 2320 else 2321 sc->sc_flags &= ~CAS_LINK; 2322 2323 switch (IFM_SUBTYPE(sc->sc_mii->mii_media_active)) { 2324 case IFM_1000_SX: 2325 case IFM_1000_LX: 2326 case IFM_1000_CX: 2327 case IFM_1000_T: 2328 gigabit = 1; 2329 break; 2330 default: 2331 gigabit = 0; 2332 } 2333 2334 /* 2335 * The configuration done here corresponds to the steps F) and 2336 * G) and as far as enabling of RX and TX MAC goes also step H) 2337 * of the initialization sequence outlined in section 11.2.1 of 2338 * the Cassini+ ASIC Specification. 2339 */ 2340 2341 rxcfg = CAS_READ_4(sc, CAS_MAC_RX_CONF); 2342 rxcfg &= ~(CAS_MAC_RX_CONF_EN | CAS_MAC_RX_CONF_CARR); 2343 txcfg = CAS_MAC_TX_CONF_EN_IPG0 | CAS_MAC_TX_CONF_NGU | 2344 CAS_MAC_TX_CONF_NGUL; 2345 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) != 0) 2346 txcfg |= CAS_MAC_TX_CONF_ICARR | CAS_MAC_TX_CONF_ICOLLIS; 2347 else if (gigabit != 0) { 2348 rxcfg |= CAS_MAC_RX_CONF_CARR; 2349 txcfg |= CAS_MAC_TX_CONF_CARR; 2350 } 2351 CAS_WRITE_4(sc, CAS_MAC_TX_CONF, 0); 2352 CAS_BARRIER(sc, CAS_MAC_TX_CONF, 4, 2353 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 2354 if (!cas_bitwait(sc, CAS_MAC_TX_CONF, CAS_MAC_TX_CONF_EN, 0)) 2355 device_printf(sc->sc_dev, "cannot disable TX MAC\n"); 2356 CAS_WRITE_4(sc, CAS_MAC_TX_CONF, txcfg); 2357 CAS_WRITE_4(sc, CAS_MAC_RX_CONF, 0); 2358 CAS_BARRIER(sc, CAS_MAC_RX_CONF, 4, 2359 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 2360 if (!cas_bitwait(sc, CAS_MAC_RX_CONF, CAS_MAC_RX_CONF_EN, 0)) 2361 device_printf(sc->sc_dev, "cannot disable RX MAC\n"); 2362 CAS_WRITE_4(sc, CAS_MAC_RX_CONF, rxcfg); 2363 2364 v = CAS_READ_4(sc, CAS_MAC_CTRL_CONF) & 2365 ~(CAS_MAC_CTRL_CONF_TXP | CAS_MAC_CTRL_CONF_RXP); 2366 #ifdef notyet 2367 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & 2368 IFM_ETH_RXPAUSE) != 0) 2369 v |= CAS_MAC_CTRL_CONF_RXP; 2370 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & 2371 IFM_ETH_TXPAUSE) != 0) 2372 v |= CAS_MAC_CTRL_CONF_TXP; 2373 #endif 2374 CAS_WRITE_4(sc, CAS_MAC_CTRL_CONF, v); 2375 2376 /* 2377 * All supported chips have a bug causing incorrect checksum 2378 * to be calculated when letting them strip the FCS in half- 2379 * duplex mode. In theory we could disable FCS stripping and 2380 * manually adjust the checksum accordingly. It seems to make 2381 * more sense to optimze for the common case and just disable 2382 * hardware checksumming in half-duplex mode though. 2383 */ 2384 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) == 0) { 2385 ifp->if_capenable &= ~IFCAP_HWCSUM; 2386 ifp->if_hwassist = 0; 2387 } else if ((sc->sc_flags & CAS_NO_CSUM) == 0) { 2388 ifp->if_capenable = ifp->if_capabilities; 2389 ifp->if_hwassist = CAS_CSUM_FEATURES; 2390 } 2391 2392 if (sc->sc_variant == CAS_SATURN) { 2393 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) == 0) 2394 /* silicon bug workaround */ 2395 CAS_WRITE_4(sc, CAS_MAC_PREAMBLE_LEN, 0x41); 2396 else 2397 CAS_WRITE_4(sc, CAS_MAC_PREAMBLE_LEN, 0x7); 2398 } 2399 2400 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) == 0 && 2401 gigabit != 0) 2402 CAS_WRITE_4(sc, CAS_MAC_SLOT_TIME, 2403 CAS_MAC_SLOT_TIME_CARR); 2404 else 2405 CAS_WRITE_4(sc, CAS_MAC_SLOT_TIME, 2406 CAS_MAC_SLOT_TIME_NORM); 2407 2408 /* XIF Configuration */ 2409 v = CAS_MAC_XIF_CONF_TX_OE | CAS_MAC_XIF_CONF_LNKLED; 2410 if ((sc->sc_flags & CAS_SERDES) == 0) { 2411 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) == 0) 2412 v |= CAS_MAC_XIF_CONF_NOECHO; 2413 v |= CAS_MAC_XIF_CONF_BUF_OE; 2414 } 2415 if (gigabit != 0) 2416 v |= CAS_MAC_XIF_CONF_GMII; 2417 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) != 0) 2418 v |= CAS_MAC_XIF_CONF_FDXLED; 2419 CAS_WRITE_4(sc, CAS_MAC_XIF_CONF, v); 2420 2421 if ((sc->sc_ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && 2422 (sc->sc_flags & CAS_LINK) != 0) { 2423 CAS_WRITE_4(sc, CAS_MAC_TX_CONF, 2424 txcfg | CAS_MAC_TX_CONF_EN); 2425 CAS_WRITE_4(sc, CAS_MAC_RX_CONF, 2426 rxcfg | CAS_MAC_RX_CONF_EN); 2427 } 2428 } 2429 2430 static int 2431 cas_mediachange(struct ifnet *ifp) 2432 { 2433 struct cas_softc *sc = ifp->if_softc; 2434 int error; 2435 2436 /* XXX add support for serial media. */ 2437 2438 CAS_LOCK(sc); 2439 error = mii_mediachg(sc->sc_mii); 2440 CAS_UNLOCK(sc); 2441 return (error); 2442 } 2443 2444 static void 2445 cas_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 2446 { 2447 struct cas_softc *sc = ifp->if_softc; 2448 2449 CAS_LOCK(sc); 2450 if ((ifp->if_flags & IFF_UP) == 0) { 2451 CAS_UNLOCK(sc); 2452 return; 2453 } 2454 2455 mii_pollstat(sc->sc_mii); 2456 ifmr->ifm_active = sc->sc_mii->mii_media_active; 2457 ifmr->ifm_status = sc->sc_mii->mii_media_status; 2458 CAS_UNLOCK(sc); 2459 } 2460 2461 static int 2462 cas_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 2463 { 2464 struct cas_softc *sc = ifp->if_softc; 2465 struct ifreq *ifr = (struct ifreq *)data; 2466 int error; 2467 2468 error = 0; 2469 switch (cmd) { 2470 case SIOCSIFFLAGS: 2471 CAS_LOCK(sc); 2472 if ((ifp->if_flags & IFF_UP) != 0) { 2473 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0 && 2474 ((ifp->if_flags ^ sc->sc_ifflags) & 2475 (IFF_ALLMULTI | IFF_PROMISC)) != 0) 2476 cas_setladrf(sc); 2477 else 2478 cas_init_locked(sc); 2479 } else if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2480 cas_stop(ifp); 2481 sc->sc_ifflags = ifp->if_flags; 2482 CAS_UNLOCK(sc); 2483 break; 2484 case SIOCSIFCAP: 2485 CAS_LOCK(sc); 2486 if ((sc->sc_flags & CAS_NO_CSUM) != 0) { 2487 error = EINVAL; 2488 CAS_UNLOCK(sc); 2489 break; 2490 } 2491 ifp->if_capenable = ifr->ifr_reqcap; 2492 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 2493 ifp->if_hwassist = CAS_CSUM_FEATURES; 2494 else 2495 ifp->if_hwassist = 0; 2496 CAS_UNLOCK(sc); 2497 break; 2498 case SIOCADDMULTI: 2499 case SIOCDELMULTI: 2500 CAS_LOCK(sc); 2501 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2502 cas_setladrf(sc); 2503 CAS_UNLOCK(sc); 2504 break; 2505 case SIOCSIFMTU: 2506 if ((ifr->ifr_mtu < ETHERMIN) || 2507 (ifr->ifr_mtu > ETHERMTU_JUMBO)) 2508 error = EINVAL; 2509 else 2510 ifp->if_mtu = ifr->ifr_mtu; 2511 break; 2512 case SIOCGIFMEDIA: 2513 case SIOCSIFMEDIA: 2514 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii->mii_media, cmd); 2515 break; 2516 default: 2517 error = ether_ioctl(ifp, cmd, data); 2518 break; 2519 } 2520 2521 return (error); 2522 } 2523 2524 static void 2525 cas_setladrf(struct cas_softc *sc) 2526 { 2527 struct ifnet *ifp = sc->sc_ifp; 2528 struct ifmultiaddr *inm; 2529 int i; 2530 uint32_t hash[16]; 2531 uint32_t crc, v; 2532 2533 CAS_LOCK_ASSERT(sc, MA_OWNED); 2534 2535 /* Get the current RX configuration. */ 2536 v = CAS_READ_4(sc, CAS_MAC_RX_CONF); 2537 2538 /* 2539 * Turn off promiscuous mode, promiscuous group mode (all multicast), 2540 * and hash filter. Depending on the case, the right bit will be 2541 * enabled. 2542 */ 2543 v &= ~(CAS_MAC_RX_CONF_PROMISC | CAS_MAC_RX_CONF_HFILTER | 2544 CAS_MAC_RX_CONF_PGRP); 2545 2546 CAS_WRITE_4(sc, CAS_MAC_RX_CONF, v); 2547 CAS_BARRIER(sc, CAS_MAC_RX_CONF, 4, 2548 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 2549 if (!cas_bitwait(sc, CAS_MAC_RX_CONF, CAS_MAC_RX_CONF_HFILTER, 0)) 2550 device_printf(sc->sc_dev, "cannot disable RX hash filter\n"); 2551 2552 if ((ifp->if_flags & IFF_PROMISC) != 0) { 2553 v |= CAS_MAC_RX_CONF_PROMISC; 2554 goto chipit; 2555 } 2556 if ((ifp->if_flags & IFF_ALLMULTI) != 0) { 2557 v |= CAS_MAC_RX_CONF_PGRP; 2558 goto chipit; 2559 } 2560 2561 /* 2562 * Set up multicast address filter by passing all multicast 2563 * addresses through a crc generator, and then using the high 2564 * order 8 bits as an index into the 256 bit logical address 2565 * filter. The high order 4 bits selects the word, while the 2566 * other 4 bits select the bit within the word (where bit 0 2567 * is the MSB). 2568 */ 2569 2570 /* Clear the hash table. */ 2571 memset(hash, 0, sizeof(hash)); 2572 2573 if_maddr_rlock(ifp); 2574 TAILQ_FOREACH(inm, &ifp->if_multiaddrs, ifma_link) { 2575 if (inm->ifma_addr->sa_family != AF_LINK) 2576 continue; 2577 crc = ether_crc32_le(LLADDR((struct sockaddr_dl *) 2578 inm->ifma_addr), ETHER_ADDR_LEN); 2579 2580 /* We just want the 8 most significant bits. */ 2581 crc >>= 24; 2582 2583 /* Set the corresponding bit in the filter. */ 2584 hash[crc >> 4] |= 1 << (15 - (crc & 15)); 2585 } 2586 if_maddr_runlock(ifp); 2587 2588 v |= CAS_MAC_RX_CONF_HFILTER; 2589 2590 /* Now load the hash table into the chip (if we are using it). */ 2591 for (i = 0; i < 16; i++) 2592 CAS_WRITE_4(sc, 2593 CAS_MAC_HASH0 + i * (CAS_MAC_HASH1 - CAS_MAC_HASH0), 2594 hash[i]); 2595 2596 chipit: 2597 CAS_WRITE_4(sc, CAS_MAC_RX_CONF, v); 2598 } 2599 2600 static int cas_pci_attach(device_t dev); 2601 static int cas_pci_detach(device_t dev); 2602 static int cas_pci_probe(device_t dev); 2603 static int cas_pci_resume(device_t dev); 2604 static int cas_pci_suspend(device_t dev); 2605 2606 static device_method_t cas_pci_methods[] = { 2607 /* Device interface */ 2608 DEVMETHOD(device_probe, cas_pci_probe), 2609 DEVMETHOD(device_attach, cas_pci_attach), 2610 DEVMETHOD(device_detach, cas_pci_detach), 2611 DEVMETHOD(device_suspend, cas_pci_suspend), 2612 DEVMETHOD(device_resume, cas_pci_resume), 2613 /* Use the suspend handler here, it is all that is required. */ 2614 DEVMETHOD(device_shutdown, cas_pci_suspend), 2615 2616 /* bus interface */ 2617 DEVMETHOD(bus_print_child, bus_generic_print_child), 2618 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 2619 2620 /* MII interface */ 2621 DEVMETHOD(miibus_readreg, cas_mii_readreg), 2622 DEVMETHOD(miibus_writereg, cas_mii_writereg), 2623 DEVMETHOD(miibus_statchg, cas_mii_statchg), 2624 2625 KOBJMETHOD_END 2626 }; 2627 2628 static driver_t cas_pci_driver = { 2629 "cas", 2630 cas_pci_methods, 2631 sizeof(struct cas_softc) 2632 }; 2633 2634 DRIVER_MODULE(cas, pci, cas_pci_driver, cas_devclass, 0, 0); 2635 DRIVER_MODULE(miibus, cas, miibus_driver, miibus_devclass, 0, 0); 2636 MODULE_DEPEND(cas, pci, 1, 1, 1); 2637 2638 static const struct cas_pci_dev { 2639 uint32_t cpd_devid; 2640 uint8_t cpd_revid; 2641 int cpd_variant; 2642 const char *cpd_desc; 2643 } const cas_pci_devlist[] = { 2644 { 0x0035100b, 0x0, CAS_SATURN, "NS DP83065 Saturn Gigabit Ethernet" }, 2645 { 0xabba108e, 0x10, CAS_CASPLUS, "Sun Cassini+ Gigabit Ethernet" }, 2646 { 0xabba108e, 0x0, CAS_CAS, "Sun Cassini Gigabit Ethernet" }, 2647 { 0, 0, 0, NULL } 2648 }; 2649 2650 static int 2651 cas_pci_probe(device_t dev) 2652 { 2653 int i; 2654 2655 for (i = 0; cas_pci_devlist[i].cpd_desc != NULL; i++) { 2656 if (pci_get_devid(dev) == cas_pci_devlist[i].cpd_devid && 2657 pci_get_revid(dev) >= cas_pci_devlist[i].cpd_revid) { 2658 device_set_desc(dev, cas_pci_devlist[i].cpd_desc); 2659 return (BUS_PROBE_DEFAULT); 2660 } 2661 } 2662 2663 return (ENXIO); 2664 } 2665 2666 static struct resource_spec cas_pci_res_spec[] = { 2667 { SYS_RES_IRQ, 0, RF_SHAREABLE | RF_ACTIVE }, /* CAS_RES_INTR */ 2668 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, /* CAS_RES_MEM */ 2669 { -1, 0 } 2670 }; 2671 2672 #define CAS_LOCAL_MAC_ADDRESS "local-mac-address" 2673 #define CAS_PHY_INTERFACE "phy-interface" 2674 #define CAS_PHY_TYPE "phy-type" 2675 #define CAS_PHY_TYPE_PCS "pcs" 2676 2677 static int 2678 cas_pci_attach(device_t dev) 2679 { 2680 char buf[sizeof(CAS_LOCAL_MAC_ADDRESS)]; 2681 struct cas_softc *sc; 2682 int i; 2683 #if !(defined(__powerpc__) || defined(__sparc64__)) 2684 u_char enaddr[4][ETHER_ADDR_LEN]; 2685 u_int j, k, lma, pcs[4], phy; 2686 #endif 2687 2688 sc = device_get_softc(dev); 2689 sc->sc_variant = CAS_UNKNOWN; 2690 for (i = 0; cas_pci_devlist[i].cpd_desc != NULL; i++) { 2691 if (pci_get_devid(dev) == cas_pci_devlist[i].cpd_devid && 2692 pci_get_revid(dev) >= cas_pci_devlist[i].cpd_revid) { 2693 sc->sc_variant = cas_pci_devlist[i].cpd_variant; 2694 break; 2695 } 2696 } 2697 if (sc->sc_variant == CAS_UNKNOWN) { 2698 device_printf(dev, "unknown adaptor\n"); 2699 return (ENXIO); 2700 } 2701 2702 pci_enable_busmaster(dev); 2703 2704 sc->sc_dev = dev; 2705 if (sc->sc_variant == CAS_CAS && pci_get_devid(dev) < 0x02) 2706 /* Hardware checksumming may hang TX. */ 2707 sc->sc_flags |= CAS_NO_CSUM; 2708 if (sc->sc_variant == CAS_CASPLUS || sc->sc_variant == CAS_SATURN) 2709 sc->sc_flags |= CAS_REG_PLUS; 2710 if (sc->sc_variant == CAS_CAS || 2711 (sc->sc_variant == CAS_CASPLUS && pci_get_revid(dev) < 0x11)) 2712 sc->sc_flags |= CAS_TABORT; 2713 if (bootverbose) 2714 device_printf(dev, "flags=0x%x\n", sc->sc_flags); 2715 2716 if (bus_alloc_resources(dev, cas_pci_res_spec, sc->sc_res)) { 2717 device_printf(dev, "failed to allocate resources\n"); 2718 bus_release_resources(dev, cas_pci_res_spec, sc->sc_res); 2719 return (ENXIO); 2720 } 2721 2722 CAS_LOCK_INIT(sc, device_get_nameunit(dev)); 2723 2724 #if defined(__powerpc__) || defined(__sparc64__) 2725 OF_getetheraddr(dev, sc->sc_enaddr); 2726 if (OF_getprop(ofw_bus_get_node(dev), CAS_PHY_INTERFACE, buf, 2727 sizeof(buf)) > 0 || OF_getprop(ofw_bus_get_node(dev), 2728 CAS_PHY_TYPE, buf, sizeof(buf)) > 0) { 2729 buf[sizeof(buf) - 1] = '\0'; 2730 if (strcmp(buf, CAS_PHY_TYPE_PCS) == 0) 2731 sc->sc_flags |= CAS_SERDES; 2732 } 2733 #else 2734 /* 2735 * Dig out VPD (vital product data) and read the MAC address as well 2736 * as the PHY type. The VPD resides in the PCI Expansion ROM (PCI 2737 * FCode) and can't be accessed via the PCI capability pointer. 2738 * SUNW,pci-ce and SUNW,pci-qge use the Enhanced VPD format described 2739 * in the free US Patent 7149820. 2740 */ 2741 2742 #define PCI_ROMHDR_SIZE 0x1c 2743 #define PCI_ROMHDR_SIG 0x00 2744 #define PCI_ROMHDR_SIG_MAGIC 0xaa55 /* little endian */ 2745 #define PCI_ROMHDR_PTR_DATA 0x18 2746 #define PCI_ROM_SIZE 0x18 2747 #define PCI_ROM_SIG 0x00 2748 #define PCI_ROM_SIG_MAGIC 0x52494350 /* "PCIR", endian */ 2749 /* reversed */ 2750 #define PCI_ROM_VENDOR 0x04 2751 #define PCI_ROM_DEVICE 0x06 2752 #define PCI_ROM_PTR_VPD 0x08 2753 #define PCI_VPDRES_BYTE0 0x00 2754 #define PCI_VPDRES_ISLARGE(x) ((x) & 0x80) 2755 #define PCI_VPDRES_LARGE_NAME(x) ((x) & 0x7f) 2756 #define PCI_VPDRES_LARGE_LEN_LSB 0x01 2757 #define PCI_VPDRES_LARGE_LEN_MSB 0x02 2758 #define PCI_VPDRES_LARGE_SIZE 0x03 2759 #define PCI_VPDRES_TYPE_ID_STRING 0x02 /* large */ 2760 #define PCI_VPDRES_TYPE_VPD 0x10 /* large */ 2761 #define PCI_VPD_KEY0 0x00 2762 #define PCI_VPD_KEY1 0x01 2763 #define PCI_VPD_LEN 0x02 2764 #define PCI_VPD_SIZE 0x03 2765 2766 #define CAS_ROM_READ_1(sc, offs) \ 2767 CAS_READ_1((sc), CAS_PCI_ROM_OFFSET + (offs)) 2768 #define CAS_ROM_READ_2(sc, offs) \ 2769 CAS_READ_2((sc), CAS_PCI_ROM_OFFSET + (offs)) 2770 #define CAS_ROM_READ_4(sc, offs) \ 2771 CAS_READ_4((sc), CAS_PCI_ROM_OFFSET + (offs)) 2772 2773 lma = phy = 0; 2774 memset(enaddr, 0, sizeof(enaddr)); 2775 memset(pcs, 0, sizeof(pcs)); 2776 2777 /* Enable PCI Expansion ROM access. */ 2778 CAS_WRITE_4(sc, CAS_BIM_LDEV_OEN, 2779 CAS_BIM_LDEV_OEN_PAD | CAS_BIM_LDEV_OEN_PROM); 2780 2781 /* Read PCI Expansion ROM header. */ 2782 if (CAS_ROM_READ_2(sc, PCI_ROMHDR_SIG) != PCI_ROMHDR_SIG_MAGIC || 2783 (i = CAS_ROM_READ_2(sc, PCI_ROMHDR_PTR_DATA)) < 2784 PCI_ROMHDR_SIZE) { 2785 device_printf(dev, "unexpected PCI Expansion ROM header\n"); 2786 goto fail_prom; 2787 } 2788 2789 /* Read PCI Expansion ROM data. */ 2790 if (CAS_ROM_READ_4(sc, i + PCI_ROM_SIG) != PCI_ROM_SIG_MAGIC || 2791 CAS_ROM_READ_2(sc, i + PCI_ROM_VENDOR) != pci_get_vendor(dev) || 2792 CAS_ROM_READ_2(sc, i + PCI_ROM_DEVICE) != pci_get_device(dev) || 2793 (j = CAS_ROM_READ_2(sc, i + PCI_ROM_PTR_VPD)) < 2794 i + PCI_ROM_SIZE) { 2795 device_printf(dev, "unexpected PCI Expansion ROM data\n"); 2796 goto fail_prom; 2797 } 2798 2799 /* Read PCI VPD. */ 2800 next: 2801 if (PCI_VPDRES_ISLARGE(CAS_ROM_READ_1(sc, 2802 j + PCI_VPDRES_BYTE0)) == 0) { 2803 device_printf(dev, "no large PCI VPD\n"); 2804 goto fail_prom; 2805 } 2806 2807 i = (CAS_ROM_READ_1(sc, j + PCI_VPDRES_LARGE_LEN_MSB) << 8) | 2808 CAS_ROM_READ_1(sc, j + PCI_VPDRES_LARGE_LEN_LSB); 2809 switch (PCI_VPDRES_LARGE_NAME(CAS_ROM_READ_1(sc, 2810 j + PCI_VPDRES_BYTE0))) { 2811 case PCI_VPDRES_TYPE_ID_STRING: 2812 /* Skip identifier string. */ 2813 j += PCI_VPDRES_LARGE_SIZE + i; 2814 goto next; 2815 case PCI_VPDRES_TYPE_VPD: 2816 for (j += PCI_VPDRES_LARGE_SIZE; i > 0; 2817 i -= PCI_VPD_SIZE + CAS_ROM_READ_1(sc, j + PCI_VPD_LEN), 2818 j += PCI_VPD_SIZE + CAS_ROM_READ_1(sc, j + PCI_VPD_LEN)) { 2819 if (CAS_ROM_READ_1(sc, j + PCI_VPD_KEY0) != 'Z') 2820 /* no Enhanced VPD */ 2821 continue; 2822 if (CAS_ROM_READ_1(sc, j + PCI_VPD_SIZE) != 'I') 2823 /* no instance property */ 2824 continue; 2825 if (CAS_ROM_READ_1(sc, j + PCI_VPD_SIZE + 3) == 'B') { 2826 /* byte array */ 2827 if (CAS_ROM_READ_1(sc, 2828 j + PCI_VPD_SIZE + 4) != ETHER_ADDR_LEN) 2829 continue; 2830 bus_read_region_1(sc->sc_res[CAS_RES_MEM], 2831 CAS_PCI_ROM_OFFSET + j + PCI_VPD_SIZE + 5, 2832 buf, sizeof(buf)); 2833 buf[sizeof(buf) - 1] = '\0'; 2834 if (strcmp(buf, CAS_LOCAL_MAC_ADDRESS) != 0) 2835 continue; 2836 bus_read_region_1(sc->sc_res[CAS_RES_MEM], 2837 CAS_PCI_ROM_OFFSET + j + PCI_VPD_SIZE + 2838 5 + sizeof(CAS_LOCAL_MAC_ADDRESS), 2839 enaddr[lma], sizeof(enaddr[lma])); 2840 lma++; 2841 if (lma == 4 && phy == 4) 2842 break; 2843 } else if (CAS_ROM_READ_1(sc, j + PCI_VPD_SIZE + 3) == 2844 'S') { 2845 /* string */ 2846 if (CAS_ROM_READ_1(sc, 2847 j + PCI_VPD_SIZE + 4) != 2848 sizeof(CAS_PHY_TYPE_PCS)) 2849 continue; 2850 bus_read_region_1(sc->sc_res[CAS_RES_MEM], 2851 CAS_PCI_ROM_OFFSET + j + PCI_VPD_SIZE + 5, 2852 buf, sizeof(buf)); 2853 buf[sizeof(buf) - 1] = '\0'; 2854 if (strcmp(buf, CAS_PHY_INTERFACE) == 0) 2855 k = sizeof(CAS_PHY_INTERFACE); 2856 else if (strcmp(buf, CAS_PHY_TYPE) == 0) 2857 k = sizeof(CAS_PHY_TYPE); 2858 else 2859 continue; 2860 bus_read_region_1(sc->sc_res[CAS_RES_MEM], 2861 CAS_PCI_ROM_OFFSET + j + PCI_VPD_SIZE + 2862 5 + k, buf, sizeof(buf)); 2863 buf[sizeof(buf) - 1] = '\0'; 2864 if (strcmp(buf, CAS_PHY_TYPE_PCS) == 0) 2865 pcs[phy] = 1; 2866 phy++; 2867 if (lma == 4 && phy == 4) 2868 break; 2869 } 2870 } 2871 break; 2872 default: 2873 device_printf(dev, "unexpected PCI VPD\n"); 2874 goto fail_prom; 2875 } 2876 2877 fail_prom: 2878 CAS_WRITE_4(sc, CAS_BIM_LDEV_OEN, 0); 2879 2880 if (lma == 0) { 2881 device_printf(dev, "could not determine Ethernet address\n"); 2882 goto fail; 2883 } 2884 i = 0; 2885 if (lma > 1 && pci_get_slot(dev) < sizeof(enaddr) / sizeof(*enaddr)) 2886 i = pci_get_slot(dev); 2887 memcpy(sc->sc_enaddr, enaddr[i], ETHER_ADDR_LEN); 2888 2889 if (phy == 0) { 2890 device_printf(dev, "could not determine PHY type\n"); 2891 goto fail; 2892 } 2893 i = 0; 2894 if (phy > 1 && pci_get_slot(dev) < sizeof(pcs) / sizeof(*pcs)) 2895 i = pci_get_slot(dev); 2896 if (pcs[i] != 0) 2897 sc->sc_flags |= CAS_SERDES; 2898 #endif 2899 2900 if (cas_attach(sc) != 0) { 2901 device_printf(dev, "could not be attached\n"); 2902 goto fail; 2903 } 2904 2905 if (bus_setup_intr(dev, sc->sc_res[CAS_RES_INTR], INTR_TYPE_NET | 2906 INTR_MPSAFE, cas_intr, NULL, sc, &sc->sc_ih) != 0) { 2907 device_printf(dev, "failed to set up interrupt\n"); 2908 cas_detach(sc); 2909 goto fail; 2910 } 2911 return (0); 2912 2913 fail: 2914 CAS_LOCK_DESTROY(sc); 2915 bus_release_resources(dev, cas_pci_res_spec, sc->sc_res); 2916 return (ENXIO); 2917 } 2918 2919 static int 2920 cas_pci_detach(device_t dev) 2921 { 2922 struct cas_softc *sc; 2923 2924 sc = device_get_softc(dev); 2925 bus_teardown_intr(dev, sc->sc_res[CAS_RES_INTR], sc->sc_ih); 2926 cas_detach(sc); 2927 CAS_LOCK_DESTROY(sc); 2928 bus_release_resources(dev, cas_pci_res_spec, sc->sc_res); 2929 return (0); 2930 } 2931 2932 static int 2933 cas_pci_suspend(device_t dev) 2934 { 2935 2936 cas_suspend(device_get_softc(dev)); 2937 return (0); 2938 } 2939 2940 static int 2941 cas_pci_resume(device_t dev) 2942 { 2943 2944 cas_resume(device_get_softc(dev)); 2945 return (0); 2946 } 2947