1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2012-2014 Thomas Skibo <thomasskibo@yahoo.com> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * A network interface driver for Cadence GEM Gigabit Ethernet 31 * interface such as the one used in Xilinx Zynq-7000 SoC. 32 * 33 * Reference: Zynq-7000 All Programmable SoC Technical Reference Manual. 34 * (v1.4) November 16, 2012. Xilinx doc UG585. GEM is covered in Ch. 16 35 * and register definitions are in appendix B.18. 36 */ 37 38 #include <sys/cdefs.h> 39 __FBSDID("$FreeBSD$"); 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/bus.h> 44 #include <sys/kernel.h> 45 #include <sys/malloc.h> 46 #include <sys/mbuf.h> 47 #include <sys/module.h> 48 #include <sys/rman.h> 49 #include <sys/socket.h> 50 #include <sys/sockio.h> 51 #include <sys/sysctl.h> 52 53 #include <machine/bus.h> 54 55 #include <net/ethernet.h> 56 #include <net/if.h> 57 #include <net/if_arp.h> 58 #include <net/if_dl.h> 59 #include <net/if_media.h> 60 #include <net/if_mib.h> 61 #include <net/if_types.h> 62 63 #ifdef INET 64 #include <netinet/in.h> 65 #include <netinet/in_systm.h> 66 #include <netinet/in_var.h> 67 #include <netinet/ip.h> 68 #endif 69 70 #include <net/bpf.h> 71 #include <net/bpfdesc.h> 72 73 #include <dev/fdt/fdt_common.h> 74 #include <dev/ofw/ofw_bus.h> 75 #include <dev/ofw/ofw_bus_subr.h> 76 77 #include <dev/mii/mii.h> 78 #include <dev/mii/miivar.h> 79 80 #ifdef EXT_RESOURCES 81 #include <dev/extres/clk/clk.h> 82 #endif 83 84 #if BUS_SPACE_MAXADDR > BUS_SPACE_MAXADDR_32BIT 85 #define CGEM64 86 #endif 87 88 #include <dev/cadence/if_cgem_hw.h> 89 90 #include "miibus_if.h" 91 92 #define IF_CGEM_NAME "cgem" 93 94 #define CGEM_NUM_RX_DESCS 512 /* size of receive descriptor ring */ 95 #define CGEM_NUM_TX_DESCS 512 /* size of transmit descriptor ring */ 96 97 /* Default for sysctl rxbufs. Must be < CGEM_NUM_RX_DESCS of course. */ 98 #define DEFAULT_NUM_RX_BUFS 256 /* number of receive bufs to queue. */ 99 100 #define TX_MAX_DMA_SEGS 8 /* maximum segs in a tx mbuf dma */ 101 102 #define CGEM_CKSUM_ASSIST (CSUM_IP | CSUM_TCP | CSUM_UDP | \ 103 CSUM_TCP_IPV6 | CSUM_UDP_IPV6) 104 105 #define HWTYPE_GENERIC_GEM 1 106 #define HWTYPE_ZYNQ 2 107 #define HWTYPE_ZYNQMP 3 108 #define HWTYPE_SIFIVE_FU540 4 109 110 static struct ofw_compat_data compat_data[] = { 111 { "cdns,zynq-gem", HWTYPE_ZYNQ }, 112 { "cdns,zynqmp-gem", HWTYPE_ZYNQMP }, 113 { "sifive,fu540-c000-gem", HWTYPE_SIFIVE_FU540 }, 114 { "cdns,gem", HWTYPE_GENERIC_GEM }, 115 { "cadence,gem", HWTYPE_GENERIC_GEM }, 116 { NULL, 0 } 117 }; 118 119 struct cgem_softc { 120 if_t ifp; 121 struct mtx sc_mtx; 122 device_t dev; 123 device_t miibus; 124 u_int mii_media_active; /* last active media */ 125 int if_old_flags; 126 struct resource *mem_res; 127 struct resource *irq_res; 128 void *intrhand; 129 struct callout tick_ch; 130 uint32_t net_ctl_shadow; 131 uint32_t net_cfg_shadow; 132 #ifdef EXT_RESOURCES 133 clk_t ref_clk; 134 #else 135 int ref_clk_num; 136 #endif 137 int neednullqs; 138 139 bus_dma_tag_t desc_dma_tag; 140 bus_dma_tag_t mbuf_dma_tag; 141 142 /* receive descriptor ring */ 143 struct cgem_rx_desc *rxring; 144 bus_addr_t rxring_physaddr; 145 struct mbuf *rxring_m[CGEM_NUM_RX_DESCS]; 146 bus_dmamap_t rxring_m_dmamap[CGEM_NUM_RX_DESCS]; 147 int rxring_hd_ptr; /* where to put rcv bufs */ 148 int rxring_tl_ptr; /* where to get receives */ 149 int rxring_queued; /* how many rcv bufs queued */ 150 bus_dmamap_t rxring_dma_map; 151 int rxbufs; /* tunable number rcv bufs */ 152 int rxhangwar; /* rx hang work-around */ 153 u_int rxoverruns; /* rx overruns */ 154 u_int rxnobufs; /* rx buf ring empty events */ 155 u_int rxdmamapfails; /* rx dmamap failures */ 156 uint32_t rx_frames_prev; 157 158 /* transmit descriptor ring */ 159 struct cgem_tx_desc *txring; 160 bus_addr_t txring_physaddr; 161 struct mbuf *txring_m[CGEM_NUM_TX_DESCS]; 162 bus_dmamap_t txring_m_dmamap[CGEM_NUM_TX_DESCS]; 163 int txring_hd_ptr; /* where to put next xmits */ 164 int txring_tl_ptr; /* next xmit mbuf to free */ 165 int txring_queued; /* num xmits segs queued */ 166 u_int txfull; /* tx ring full events */ 167 u_int txdefrags; /* tx calls to m_defrag() */ 168 u_int txdefragfails; /* tx m_defrag() failures */ 169 u_int txdmamapfails; /* tx dmamap failures */ 170 171 /* null descriptor rings */ 172 void *null_qs; 173 bus_addr_t null_qs_physaddr; 174 175 /* hardware provided statistics */ 176 struct cgem_hw_stats { 177 uint64_t tx_bytes; 178 uint32_t tx_frames; 179 uint32_t tx_frames_bcast; 180 uint32_t tx_frames_multi; 181 uint32_t tx_frames_pause; 182 uint32_t tx_frames_64b; 183 uint32_t tx_frames_65to127b; 184 uint32_t tx_frames_128to255b; 185 uint32_t tx_frames_256to511b; 186 uint32_t tx_frames_512to1023b; 187 uint32_t tx_frames_1024to1536b; 188 uint32_t tx_under_runs; 189 uint32_t tx_single_collisn; 190 uint32_t tx_multi_collisn; 191 uint32_t tx_excsv_collisn; 192 uint32_t tx_late_collisn; 193 uint32_t tx_deferred_frames; 194 uint32_t tx_carrier_sense_errs; 195 196 uint64_t rx_bytes; 197 uint32_t rx_frames; 198 uint32_t rx_frames_bcast; 199 uint32_t rx_frames_multi; 200 uint32_t rx_frames_pause; 201 uint32_t rx_frames_64b; 202 uint32_t rx_frames_65to127b; 203 uint32_t rx_frames_128to255b; 204 uint32_t rx_frames_256to511b; 205 uint32_t rx_frames_512to1023b; 206 uint32_t rx_frames_1024to1536b; 207 uint32_t rx_frames_undersize; 208 uint32_t rx_frames_oversize; 209 uint32_t rx_frames_jabber; 210 uint32_t rx_frames_fcs_errs; 211 uint32_t rx_frames_length_errs; 212 uint32_t rx_symbol_errs; 213 uint32_t rx_align_errs; 214 uint32_t rx_resource_errs; 215 uint32_t rx_overrun_errs; 216 uint32_t rx_ip_hdr_csum_errs; 217 uint32_t rx_tcp_csum_errs; 218 uint32_t rx_udp_csum_errs; 219 } stats; 220 }; 221 222 #define RD4(sc, off) (bus_read_4((sc)->mem_res, (off))) 223 #define WR4(sc, off, val) (bus_write_4((sc)->mem_res, (off), (val))) 224 #define BARRIER(sc, off, len, flags) \ 225 (bus_barrier((sc)->mem_res, (off), (len), (flags)) 226 227 #define CGEM_LOCK(sc) mtx_lock(&(sc)->sc_mtx) 228 #define CGEM_UNLOCK(sc) mtx_unlock(&(sc)->sc_mtx) 229 #define CGEM_LOCK_INIT(sc) mtx_init(&(sc)->sc_mtx, \ 230 device_get_nameunit((sc)->dev), MTX_NETWORK_LOCK, MTX_DEF) 231 #define CGEM_LOCK_DESTROY(sc) mtx_destroy(&(sc)->sc_mtx) 232 #define CGEM_ASSERT_LOCKED(sc) mtx_assert(&(sc)->sc_mtx, MA_OWNED) 233 234 /* Allow platforms to optionally provide a way to set the reference clock. */ 235 int cgem_set_ref_clk(int unit, int frequency); 236 237 static devclass_t cgem_devclass; 238 239 static int cgem_probe(device_t dev); 240 static int cgem_attach(device_t dev); 241 static int cgem_detach(device_t dev); 242 static void cgem_tick(void *); 243 static void cgem_intr(void *); 244 245 static void cgem_mediachange(struct cgem_softc *, struct mii_data *); 246 247 static void 248 cgem_get_mac(struct cgem_softc *sc, u_char eaddr[]) 249 { 250 int i; 251 uint32_t rnd; 252 253 /* See if boot loader gave us a MAC address already. */ 254 for (i = 0; i < 4; i++) { 255 uint32_t low = RD4(sc, CGEM_SPEC_ADDR_LOW(i)); 256 uint32_t high = RD4(sc, CGEM_SPEC_ADDR_HI(i)) & 0xffff; 257 if (low != 0 || high != 0) { 258 eaddr[0] = low & 0xff; 259 eaddr[1] = (low >> 8) & 0xff; 260 eaddr[2] = (low >> 16) & 0xff; 261 eaddr[3] = (low >> 24) & 0xff; 262 eaddr[4] = high & 0xff; 263 eaddr[5] = (high >> 8) & 0xff; 264 break; 265 } 266 } 267 268 /* No MAC from boot loader? Assign a random one. */ 269 if (i == 4) { 270 rnd = arc4random(); 271 272 eaddr[0] = 'b'; 273 eaddr[1] = 's'; 274 eaddr[2] = 'd'; 275 eaddr[3] = (rnd >> 16) & 0xff; 276 eaddr[4] = (rnd >> 8) & 0xff; 277 eaddr[5] = rnd & 0xff; 278 279 device_printf(sc->dev, "no mac address found, assigning " 280 "random: %02x:%02x:%02x:%02x:%02x:%02x\n", eaddr[0], 281 eaddr[1], eaddr[2], eaddr[3], eaddr[4], eaddr[5]); 282 } 283 284 /* Move address to first slot and zero out the rest. */ 285 WR4(sc, CGEM_SPEC_ADDR_LOW(0), (eaddr[3] << 24) | 286 (eaddr[2] << 16) | (eaddr[1] << 8) | eaddr[0]); 287 WR4(sc, CGEM_SPEC_ADDR_HI(0), (eaddr[5] << 8) | eaddr[4]); 288 289 for (i = 1; i < 4; i++) { 290 WR4(sc, CGEM_SPEC_ADDR_LOW(i), 0); 291 WR4(sc, CGEM_SPEC_ADDR_HI(i), 0); 292 } 293 } 294 295 /* 296 * cgem_mac_hash(): map 48-bit address to a 6-bit hash. The 6-bit hash 297 * corresponds to a bit in a 64-bit hash register. Setting that bit in the 298 * hash register enables reception of all frames with a destination address 299 * that hashes to that 6-bit value. 300 * 301 * The hash function is described in sec. 16.2.3 in the Zynq-7000 Tech 302 * Reference Manual. Bits 0-5 in the hash are the exclusive-or of 303 * every sixth bit in the destination address. 304 */ 305 static int 306 cgem_mac_hash(u_char eaddr[]) 307 { 308 int hash; 309 int i, j; 310 311 hash = 0; 312 for (i = 0; i < 6; i++) 313 for (j = i; j < 48; j += 6) 314 if ((eaddr[j >> 3] & (1 << (j & 7))) != 0) 315 hash ^= (1 << i); 316 317 return hash; 318 } 319 320 static u_int 321 cgem_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 322 { 323 uint32_t *hashes = arg; 324 int index; 325 326 index = cgem_mac_hash(LLADDR(sdl)); 327 if (index > 31) 328 hashes[0] |= (1U << (index - 32)); 329 else 330 hashes[1] |= (1U << index); 331 332 return (1); 333 } 334 335 /* 336 * After any change in rx flags or multi-cast addresses, set up hash registers 337 * and net config register bits. 338 */ 339 static void 340 cgem_rx_filter(struct cgem_softc *sc) 341 { 342 if_t ifp = sc->ifp; 343 uint32_t hashes[2] = { 0, 0 }; 344 345 sc->net_cfg_shadow &= ~(CGEM_NET_CFG_MULTI_HASH_EN | 346 CGEM_NET_CFG_NO_BCAST | CGEM_NET_CFG_COPY_ALL); 347 348 if ((if_getflags(ifp) & IFF_PROMISC) != 0) 349 sc->net_cfg_shadow |= CGEM_NET_CFG_COPY_ALL; 350 else { 351 if ((if_getflags(ifp) & IFF_BROADCAST) == 0) 352 sc->net_cfg_shadow |= CGEM_NET_CFG_NO_BCAST; 353 if ((if_getflags(ifp) & IFF_ALLMULTI) != 0) { 354 hashes[0] = 0xffffffff; 355 hashes[1] = 0xffffffff; 356 } else 357 if_foreach_llmaddr(ifp, cgem_hash_maddr, hashes); 358 359 if (hashes[0] != 0 || hashes[1] != 0) 360 sc->net_cfg_shadow |= CGEM_NET_CFG_MULTI_HASH_EN; 361 } 362 363 WR4(sc, CGEM_HASH_TOP, hashes[0]); 364 WR4(sc, CGEM_HASH_BOT, hashes[1]); 365 WR4(sc, CGEM_NET_CFG, sc->net_cfg_shadow); 366 } 367 368 /* For bus_dmamap_load() callback. */ 369 static void 370 cgem_getaddr(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 371 { 372 373 if (nsegs != 1 || error != 0) 374 return; 375 *(bus_addr_t *)arg = segs[0].ds_addr; 376 } 377 378 /* Set up null queues for priority queues we actually can't disable. */ 379 static void 380 cgem_null_qs(struct cgem_softc *sc) 381 { 382 struct cgem_rx_desc *rx_desc; 383 struct cgem_tx_desc *tx_desc; 384 uint32_t queue_mask; 385 int n; 386 387 /* Read design config register 6 to determine number of queues. */ 388 queue_mask = (RD4(sc, CGEM_DESIGN_CFG6) & 389 CGEM_DESIGN_CFG6_DMA_PRIO_Q_MASK) >> 1; 390 if (queue_mask == 0) 391 return; 392 393 /* Create empty RX queue and empty TX buf queues. */ 394 memset(sc->null_qs, 0, sizeof(struct cgem_rx_desc) + 395 sizeof(struct cgem_tx_desc)); 396 rx_desc = sc->null_qs; 397 rx_desc->addr = CGEM_RXDESC_OWN | CGEM_RXDESC_WRAP; 398 tx_desc = (struct cgem_tx_desc *)(rx_desc + 1); 399 tx_desc->ctl = CGEM_TXDESC_USED | CGEM_TXDESC_WRAP; 400 401 /* Point all valid ring base pointers to the null queues. */ 402 for (n = 1; (queue_mask & 1) != 0; n++, queue_mask >>= 1) { 403 WR4(sc, CGEM_RX_QN_BAR(n), sc->null_qs_physaddr); 404 WR4(sc, CGEM_TX_QN_BAR(n), sc->null_qs_physaddr + 405 sizeof(struct cgem_rx_desc)); 406 } 407 } 408 409 /* Create DMA'able descriptor rings. */ 410 static int 411 cgem_setup_descs(struct cgem_softc *sc) 412 { 413 int i, err; 414 int desc_rings_size = CGEM_NUM_RX_DESCS * sizeof(struct cgem_rx_desc) + 415 CGEM_NUM_TX_DESCS * sizeof(struct cgem_tx_desc); 416 417 if (sc->neednullqs) 418 desc_rings_size += sizeof(struct cgem_rx_desc) + 419 sizeof(struct cgem_tx_desc); 420 421 sc->txring = NULL; 422 sc->rxring = NULL; 423 424 /* Allocate non-cached DMA space for RX and TX descriptors. */ 425 err = bus_dma_tag_create(bus_get_dma_tag(sc->dev), 1, 426 #ifdef CGEM64 427 1ULL << 32, /* Do not cross a 4G boundary. */ 428 #else 429 0, 430 #endif 431 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 432 desc_rings_size, 1, desc_rings_size, 0, 433 busdma_lock_mutex, &sc->sc_mtx, &sc->desc_dma_tag); 434 if (err) 435 return (err); 436 437 /* Set up a bus_dma_tag for mbufs. */ 438 err = bus_dma_tag_create(bus_get_dma_tag(sc->dev), 1, 0, 439 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, 440 TX_MAX_DMA_SEGS, MCLBYTES, 0, busdma_lock_mutex, &sc->sc_mtx, 441 &sc->mbuf_dma_tag); 442 if (err) 443 return (err); 444 445 /* 446 * Allocate DMA memory in non-cacheable space. We allocate transmit, 447 * receive and null descriptor queues all at once because the 448 * hardware only provides one register for the upper 32 bits of 449 * rx and tx descriptor queues hardware addresses. 450 */ 451 err = bus_dmamem_alloc(sc->desc_dma_tag, (void **)&sc->rxring, 452 #ifdef __arm__ 453 BUS_DMA_NOWAIT | BUS_DMA_COHERENT | BUS_DMA_ZERO, 454 #else 455 BUS_DMA_NOWAIT | BUS_DMA_NOCACHE | BUS_DMA_ZERO, 456 #endif 457 &sc->rxring_dma_map); 458 if (err) 459 return (err); 460 461 /* Load descriptor DMA memory. */ 462 err = bus_dmamap_load(sc->desc_dma_tag, sc->rxring_dma_map, 463 (void *)sc->rxring, desc_rings_size, 464 cgem_getaddr, &sc->rxring_physaddr, BUS_DMA_NOWAIT); 465 if (err) 466 return (err); 467 468 /* Initialize RX descriptors. */ 469 for (i = 0; i < CGEM_NUM_RX_DESCS; i++) { 470 sc->rxring[i].addr = CGEM_RXDESC_OWN; 471 sc->rxring[i].ctl = 0; 472 sc->rxring_m[i] = NULL; 473 sc->rxring_m_dmamap[i] = NULL; 474 } 475 sc->rxring[CGEM_NUM_RX_DESCS - 1].addr |= CGEM_RXDESC_WRAP; 476 477 sc->rxring_hd_ptr = 0; 478 sc->rxring_tl_ptr = 0; 479 sc->rxring_queued = 0; 480 481 sc->txring = (struct cgem_tx_desc *)(sc->rxring + CGEM_NUM_RX_DESCS); 482 sc->txring_physaddr = sc->rxring_physaddr + CGEM_NUM_RX_DESCS * 483 sizeof(struct cgem_rx_desc); 484 485 /* Initialize TX descriptor ring. */ 486 for (i = 0; i < CGEM_NUM_TX_DESCS; i++) { 487 sc->txring[i].addr = 0; 488 sc->txring[i].ctl = CGEM_TXDESC_USED; 489 sc->txring_m[i] = NULL; 490 sc->txring_m_dmamap[i] = NULL; 491 } 492 sc->txring[CGEM_NUM_TX_DESCS - 1].ctl |= CGEM_TXDESC_WRAP; 493 494 sc->txring_hd_ptr = 0; 495 sc->txring_tl_ptr = 0; 496 sc->txring_queued = 0; 497 498 if (sc->neednullqs) { 499 sc->null_qs = (void *)(sc->txring + CGEM_NUM_TX_DESCS); 500 sc->null_qs_physaddr = sc->txring_physaddr + 501 CGEM_NUM_TX_DESCS * sizeof(struct cgem_tx_desc); 502 503 cgem_null_qs(sc); 504 } 505 506 return (0); 507 } 508 509 /* Fill receive descriptor ring with mbufs. */ 510 static void 511 cgem_fill_rqueue(struct cgem_softc *sc) 512 { 513 struct mbuf *m = NULL; 514 bus_dma_segment_t segs[TX_MAX_DMA_SEGS]; 515 int nsegs; 516 517 CGEM_ASSERT_LOCKED(sc); 518 519 while (sc->rxring_queued < sc->rxbufs) { 520 /* Get a cluster mbuf. */ 521 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 522 if (m == NULL) 523 break; 524 525 m->m_len = MCLBYTES; 526 m->m_pkthdr.len = MCLBYTES; 527 m->m_pkthdr.rcvif = sc->ifp; 528 529 /* Load map and plug in physical address. */ 530 if (bus_dmamap_create(sc->mbuf_dma_tag, 0, 531 &sc->rxring_m_dmamap[sc->rxring_hd_ptr])) { 532 sc->rxdmamapfails++; 533 m_free(m); 534 break; 535 } 536 if (bus_dmamap_load_mbuf_sg(sc->mbuf_dma_tag, 537 sc->rxring_m_dmamap[sc->rxring_hd_ptr], m, 538 segs, &nsegs, BUS_DMA_NOWAIT)) { 539 sc->rxdmamapfails++; 540 bus_dmamap_destroy(sc->mbuf_dma_tag, 541 sc->rxring_m_dmamap[sc->rxring_hd_ptr]); 542 sc->rxring_m_dmamap[sc->rxring_hd_ptr] = NULL; 543 m_free(m); 544 break; 545 } 546 sc->rxring_m[sc->rxring_hd_ptr] = m; 547 548 /* Sync cache with receive buffer. */ 549 bus_dmamap_sync(sc->mbuf_dma_tag, 550 sc->rxring_m_dmamap[sc->rxring_hd_ptr], 551 BUS_DMASYNC_PREREAD); 552 553 /* Write rx descriptor and increment head pointer. */ 554 sc->rxring[sc->rxring_hd_ptr].ctl = 0; 555 #ifdef CGEM64 556 sc->rxring[sc->rxring_hd_ptr].addrhi = segs[0].ds_addr >> 32; 557 #endif 558 if (sc->rxring_hd_ptr == CGEM_NUM_RX_DESCS - 1) { 559 sc->rxring[sc->rxring_hd_ptr].addr = segs[0].ds_addr | 560 CGEM_RXDESC_WRAP; 561 sc->rxring_hd_ptr = 0; 562 } else 563 sc->rxring[sc->rxring_hd_ptr++].addr = segs[0].ds_addr; 564 565 sc->rxring_queued++; 566 } 567 } 568 569 /* Pull received packets off of receive descriptor ring. */ 570 static void 571 cgem_recv(struct cgem_softc *sc) 572 { 573 if_t ifp = sc->ifp; 574 struct mbuf *m, *m_hd, **m_tl; 575 uint32_t ctl; 576 577 CGEM_ASSERT_LOCKED(sc); 578 579 /* Pick up all packets in which the OWN bit is set. */ 580 m_hd = NULL; 581 m_tl = &m_hd; 582 while (sc->rxring_queued > 0 && 583 (sc->rxring[sc->rxring_tl_ptr].addr & CGEM_RXDESC_OWN) != 0) { 584 ctl = sc->rxring[sc->rxring_tl_ptr].ctl; 585 586 /* Grab filled mbuf. */ 587 m = sc->rxring_m[sc->rxring_tl_ptr]; 588 sc->rxring_m[sc->rxring_tl_ptr] = NULL; 589 590 /* Sync cache with receive buffer. */ 591 bus_dmamap_sync(sc->mbuf_dma_tag, 592 sc->rxring_m_dmamap[sc->rxring_tl_ptr], 593 BUS_DMASYNC_POSTREAD); 594 595 /* Unload and destroy dmamap. */ 596 bus_dmamap_unload(sc->mbuf_dma_tag, 597 sc->rxring_m_dmamap[sc->rxring_tl_ptr]); 598 bus_dmamap_destroy(sc->mbuf_dma_tag, 599 sc->rxring_m_dmamap[sc->rxring_tl_ptr]); 600 sc->rxring_m_dmamap[sc->rxring_tl_ptr] = NULL; 601 602 /* Increment tail pointer. */ 603 if (++sc->rxring_tl_ptr == CGEM_NUM_RX_DESCS) 604 sc->rxring_tl_ptr = 0; 605 sc->rxring_queued--; 606 607 /* 608 * Check FCS and make sure entire packet landed in one mbuf 609 * cluster (which is much bigger than the largest ethernet 610 * packet). 611 */ 612 if ((ctl & CGEM_RXDESC_BAD_FCS) != 0 || 613 (ctl & (CGEM_RXDESC_SOF | CGEM_RXDESC_EOF)) != 614 (CGEM_RXDESC_SOF | CGEM_RXDESC_EOF)) { 615 /* discard. */ 616 m_free(m); 617 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 618 continue; 619 } 620 621 /* Ready it to hand off to upper layers. */ 622 m->m_data += ETHER_ALIGN; 623 m->m_len = (ctl & CGEM_RXDESC_LENGTH_MASK); 624 m->m_pkthdr.rcvif = ifp; 625 m->m_pkthdr.len = m->m_len; 626 627 /* 628 * Are we using hardware checksumming? Check the status in the 629 * receive descriptor. 630 */ 631 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0) { 632 /* TCP or UDP checks out, IP checks out too. */ 633 if ((ctl & CGEM_RXDESC_CKSUM_STAT_MASK) == 634 CGEM_RXDESC_CKSUM_STAT_TCP_GOOD || 635 (ctl & CGEM_RXDESC_CKSUM_STAT_MASK) == 636 CGEM_RXDESC_CKSUM_STAT_UDP_GOOD) { 637 m->m_pkthdr.csum_flags |= 638 CSUM_IP_CHECKED | CSUM_IP_VALID | 639 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 640 m->m_pkthdr.csum_data = 0xffff; 641 } else if ((ctl & CGEM_RXDESC_CKSUM_STAT_MASK) == 642 CGEM_RXDESC_CKSUM_STAT_IP_GOOD) { 643 /* Only IP checks out. */ 644 m->m_pkthdr.csum_flags |= 645 CSUM_IP_CHECKED | CSUM_IP_VALID; 646 m->m_pkthdr.csum_data = 0xffff; 647 } 648 } 649 650 /* Queue it up for delivery below. */ 651 *m_tl = m; 652 m_tl = &m->m_next; 653 } 654 655 /* Replenish receive buffers. */ 656 cgem_fill_rqueue(sc); 657 658 /* Unlock and send up packets. */ 659 CGEM_UNLOCK(sc); 660 while (m_hd != NULL) { 661 m = m_hd; 662 m_hd = m_hd->m_next; 663 m->m_next = NULL; 664 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 665 if_input(ifp, m); 666 } 667 CGEM_LOCK(sc); 668 } 669 670 /* Find completed transmits and free their mbufs. */ 671 static void 672 cgem_clean_tx(struct cgem_softc *sc) 673 { 674 struct mbuf *m; 675 uint32_t ctl; 676 677 CGEM_ASSERT_LOCKED(sc); 678 679 /* free up finished transmits. */ 680 while (sc->txring_queued > 0 && 681 ((ctl = sc->txring[sc->txring_tl_ptr].ctl) & 682 CGEM_TXDESC_USED) != 0) { 683 /* Sync cache. */ 684 bus_dmamap_sync(sc->mbuf_dma_tag, 685 sc->txring_m_dmamap[sc->txring_tl_ptr], 686 BUS_DMASYNC_POSTWRITE); 687 688 /* Unload and destroy DMA map. */ 689 bus_dmamap_unload(sc->mbuf_dma_tag, 690 sc->txring_m_dmamap[sc->txring_tl_ptr]); 691 bus_dmamap_destroy(sc->mbuf_dma_tag, 692 sc->txring_m_dmamap[sc->txring_tl_ptr]); 693 sc->txring_m_dmamap[sc->txring_tl_ptr] = NULL; 694 695 /* Free up the mbuf. */ 696 m = sc->txring_m[sc->txring_tl_ptr]; 697 sc->txring_m[sc->txring_tl_ptr] = NULL; 698 m_freem(m); 699 700 /* Check the status. */ 701 if ((ctl & CGEM_TXDESC_AHB_ERR) != 0) { 702 /* Serious bus error. log to console. */ 703 #ifdef CGEM64 704 device_printf(sc->dev, 705 "cgem_clean_tx: AHB error, addr=0x%x%08x\n", 706 sc->txring[sc->txring_tl_ptr].addrhi, 707 sc->txring[sc->txring_tl_ptr].addr); 708 #else 709 device_printf(sc->dev, 710 "cgem_clean_tx: AHB error, addr=0x%x\n", 711 sc->txring[sc->txring_tl_ptr].addr); 712 #endif 713 } else if ((ctl & (CGEM_TXDESC_RETRY_ERR | 714 CGEM_TXDESC_LATE_COLL)) != 0) { 715 if_inc_counter(sc->ifp, IFCOUNTER_OERRORS, 1); 716 } else 717 if_inc_counter(sc->ifp, IFCOUNTER_OPACKETS, 1); 718 719 /* 720 * If the packet spanned more than one tx descriptor, skip 721 * descriptors until we find the end so that only 722 * start-of-frame descriptors are processed. 723 */ 724 while ((ctl & CGEM_TXDESC_LAST_BUF) == 0) { 725 if ((ctl & CGEM_TXDESC_WRAP) != 0) 726 sc->txring_tl_ptr = 0; 727 else 728 sc->txring_tl_ptr++; 729 sc->txring_queued--; 730 731 ctl = sc->txring[sc->txring_tl_ptr].ctl; 732 733 sc->txring[sc->txring_tl_ptr].ctl = 734 ctl | CGEM_TXDESC_USED; 735 } 736 737 /* Next descriptor. */ 738 if ((ctl & CGEM_TXDESC_WRAP) != 0) 739 sc->txring_tl_ptr = 0; 740 else 741 sc->txring_tl_ptr++; 742 sc->txring_queued--; 743 744 if_setdrvflagbits(sc->ifp, 0, IFF_DRV_OACTIVE); 745 } 746 } 747 748 /* Start transmits. */ 749 static void 750 cgem_start_locked(if_t ifp) 751 { 752 struct cgem_softc *sc = (struct cgem_softc *) if_getsoftc(ifp); 753 struct mbuf *m; 754 bus_dma_segment_t segs[TX_MAX_DMA_SEGS]; 755 uint32_t ctl; 756 int i, nsegs, wrap, err; 757 758 CGEM_ASSERT_LOCKED(sc); 759 760 if ((if_getdrvflags(ifp) & IFF_DRV_OACTIVE) != 0) 761 return; 762 763 for (;;) { 764 /* Check that there is room in the descriptor ring. */ 765 if (sc->txring_queued >= 766 CGEM_NUM_TX_DESCS - TX_MAX_DMA_SEGS * 2) { 767 /* Try to make room. */ 768 cgem_clean_tx(sc); 769 770 /* Still no room? */ 771 if (sc->txring_queued >= 772 CGEM_NUM_TX_DESCS - TX_MAX_DMA_SEGS * 2) { 773 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 774 sc->txfull++; 775 break; 776 } 777 } 778 779 /* Grab next transmit packet. */ 780 m = if_dequeue(ifp); 781 if (m == NULL) 782 break; 783 784 /* Create and load DMA map. */ 785 if (bus_dmamap_create(sc->mbuf_dma_tag, 0, 786 &sc->txring_m_dmamap[sc->txring_hd_ptr])) { 787 m_freem(m); 788 sc->txdmamapfails++; 789 continue; 790 } 791 err = bus_dmamap_load_mbuf_sg(sc->mbuf_dma_tag, 792 sc->txring_m_dmamap[sc->txring_hd_ptr], m, segs, &nsegs, 793 BUS_DMA_NOWAIT); 794 if (err == EFBIG) { 795 /* Too many segments! defrag and try again. */ 796 struct mbuf *m2 = m_defrag(m, M_NOWAIT); 797 798 if (m2 == NULL) { 799 sc->txdefragfails++; 800 m_freem(m); 801 bus_dmamap_destroy(sc->mbuf_dma_tag, 802 sc->txring_m_dmamap[sc->txring_hd_ptr]); 803 sc->txring_m_dmamap[sc->txring_hd_ptr] = NULL; 804 continue; 805 } 806 m = m2; 807 err = bus_dmamap_load_mbuf_sg(sc->mbuf_dma_tag, 808 sc->txring_m_dmamap[sc->txring_hd_ptr], m, segs, 809 &nsegs, BUS_DMA_NOWAIT); 810 sc->txdefrags++; 811 } 812 if (err) { 813 /* Give up. */ 814 m_freem(m); 815 bus_dmamap_destroy(sc->mbuf_dma_tag, 816 sc->txring_m_dmamap[sc->txring_hd_ptr]); 817 sc->txring_m_dmamap[sc->txring_hd_ptr] = NULL; 818 sc->txdmamapfails++; 819 continue; 820 } 821 sc->txring_m[sc->txring_hd_ptr] = m; 822 823 /* Sync tx buffer with cache. */ 824 bus_dmamap_sync(sc->mbuf_dma_tag, 825 sc->txring_m_dmamap[sc->txring_hd_ptr], 826 BUS_DMASYNC_PREWRITE); 827 828 /* Set wrap flag if next packet might run off end of ring. */ 829 wrap = sc->txring_hd_ptr + nsegs + TX_MAX_DMA_SEGS >= 830 CGEM_NUM_TX_DESCS; 831 832 /* 833 * Fill in the TX descriptors back to front so that USED bit in 834 * first descriptor is cleared last. 835 */ 836 for (i = nsegs - 1; i >= 0; i--) { 837 /* Descriptor address. */ 838 sc->txring[sc->txring_hd_ptr + i].addr = 839 segs[i].ds_addr; 840 #ifdef CGEM64 841 sc->txring[sc->txring_hd_ptr + i].addrhi = 842 segs[i].ds_addr >> 32; 843 #endif 844 /* Descriptor control word. */ 845 ctl = segs[i].ds_len; 846 if (i == nsegs - 1) { 847 ctl |= CGEM_TXDESC_LAST_BUF; 848 if (wrap) 849 ctl |= CGEM_TXDESC_WRAP; 850 } 851 sc->txring[sc->txring_hd_ptr + i].ctl = ctl; 852 853 if (i != 0) 854 sc->txring_m[sc->txring_hd_ptr + i] = NULL; 855 } 856 857 if (wrap) 858 sc->txring_hd_ptr = 0; 859 else 860 sc->txring_hd_ptr += nsegs; 861 sc->txring_queued += nsegs; 862 863 /* Kick the transmitter. */ 864 WR4(sc, CGEM_NET_CTRL, sc->net_ctl_shadow | 865 CGEM_NET_CTRL_START_TX); 866 867 /* If there is a BPF listener, bounce a copy to him. */ 868 ETHER_BPF_MTAP(ifp, m); 869 } 870 } 871 872 static void 873 cgem_start(if_t ifp) 874 { 875 struct cgem_softc *sc = (struct cgem_softc *) if_getsoftc(ifp); 876 877 CGEM_LOCK(sc); 878 cgem_start_locked(ifp); 879 CGEM_UNLOCK(sc); 880 } 881 882 static void 883 cgem_poll_hw_stats(struct cgem_softc *sc) 884 { 885 uint32_t n; 886 887 CGEM_ASSERT_LOCKED(sc); 888 889 sc->stats.tx_bytes += RD4(sc, CGEM_OCTETS_TX_BOT); 890 sc->stats.tx_bytes += (uint64_t)RD4(sc, CGEM_OCTETS_TX_TOP) << 32; 891 892 sc->stats.tx_frames += RD4(sc, CGEM_FRAMES_TX); 893 sc->stats.tx_frames_bcast += RD4(sc, CGEM_BCAST_FRAMES_TX); 894 sc->stats.tx_frames_multi += RD4(sc, CGEM_MULTI_FRAMES_TX); 895 sc->stats.tx_frames_pause += RD4(sc, CGEM_PAUSE_FRAMES_TX); 896 sc->stats.tx_frames_64b += RD4(sc, CGEM_FRAMES_64B_TX); 897 sc->stats.tx_frames_65to127b += RD4(sc, CGEM_FRAMES_65_127B_TX); 898 sc->stats.tx_frames_128to255b += RD4(sc, CGEM_FRAMES_128_255B_TX); 899 sc->stats.tx_frames_256to511b += RD4(sc, CGEM_FRAMES_256_511B_TX); 900 sc->stats.tx_frames_512to1023b += RD4(sc, CGEM_FRAMES_512_1023B_TX); 901 sc->stats.tx_frames_1024to1536b += RD4(sc, CGEM_FRAMES_1024_1518B_TX); 902 sc->stats.tx_under_runs += RD4(sc, CGEM_TX_UNDERRUNS); 903 904 n = RD4(sc, CGEM_SINGLE_COLL_FRAMES); 905 sc->stats.tx_single_collisn += n; 906 if_inc_counter(sc->ifp, IFCOUNTER_COLLISIONS, n); 907 n = RD4(sc, CGEM_MULTI_COLL_FRAMES); 908 sc->stats.tx_multi_collisn += n; 909 if_inc_counter(sc->ifp, IFCOUNTER_COLLISIONS, n); 910 n = RD4(sc, CGEM_EXCESSIVE_COLL_FRAMES); 911 sc->stats.tx_excsv_collisn += n; 912 if_inc_counter(sc->ifp, IFCOUNTER_COLLISIONS, n); 913 n = RD4(sc, CGEM_LATE_COLL); 914 sc->stats.tx_late_collisn += n; 915 if_inc_counter(sc->ifp, IFCOUNTER_COLLISIONS, n); 916 917 sc->stats.tx_deferred_frames += RD4(sc, CGEM_DEFERRED_TX_FRAMES); 918 sc->stats.tx_carrier_sense_errs += RD4(sc, CGEM_CARRIER_SENSE_ERRS); 919 920 sc->stats.rx_bytes += RD4(sc, CGEM_OCTETS_RX_BOT); 921 sc->stats.rx_bytes += (uint64_t)RD4(sc, CGEM_OCTETS_RX_TOP) << 32; 922 923 sc->stats.rx_frames += RD4(sc, CGEM_FRAMES_RX); 924 sc->stats.rx_frames_bcast += RD4(sc, CGEM_BCAST_FRAMES_RX); 925 sc->stats.rx_frames_multi += RD4(sc, CGEM_MULTI_FRAMES_RX); 926 sc->stats.rx_frames_pause += RD4(sc, CGEM_PAUSE_FRAMES_RX); 927 sc->stats.rx_frames_64b += RD4(sc, CGEM_FRAMES_64B_RX); 928 sc->stats.rx_frames_65to127b += RD4(sc, CGEM_FRAMES_65_127B_RX); 929 sc->stats.rx_frames_128to255b += RD4(sc, CGEM_FRAMES_128_255B_RX); 930 sc->stats.rx_frames_256to511b += RD4(sc, CGEM_FRAMES_256_511B_RX); 931 sc->stats.rx_frames_512to1023b += RD4(sc, CGEM_FRAMES_512_1023B_RX); 932 sc->stats.rx_frames_1024to1536b += RD4(sc, CGEM_FRAMES_1024_1518B_RX); 933 sc->stats.rx_frames_undersize += RD4(sc, CGEM_UNDERSZ_RX); 934 sc->stats.rx_frames_oversize += RD4(sc, CGEM_OVERSZ_RX); 935 sc->stats.rx_frames_jabber += RD4(sc, CGEM_JABBERS_RX); 936 sc->stats.rx_frames_fcs_errs += RD4(sc, CGEM_FCS_ERRS); 937 sc->stats.rx_frames_length_errs += RD4(sc, CGEM_LENGTH_FIELD_ERRS); 938 sc->stats.rx_symbol_errs += RD4(sc, CGEM_RX_SYMBOL_ERRS); 939 sc->stats.rx_align_errs += RD4(sc, CGEM_ALIGN_ERRS); 940 sc->stats.rx_resource_errs += RD4(sc, CGEM_RX_RESOURCE_ERRS); 941 sc->stats.rx_overrun_errs += RD4(sc, CGEM_RX_OVERRUN_ERRS); 942 sc->stats.rx_ip_hdr_csum_errs += RD4(sc, CGEM_IP_HDR_CKSUM_ERRS); 943 sc->stats.rx_tcp_csum_errs += RD4(sc, CGEM_TCP_CKSUM_ERRS); 944 sc->stats.rx_udp_csum_errs += RD4(sc, CGEM_UDP_CKSUM_ERRS); 945 } 946 947 static void 948 cgem_tick(void *arg) 949 { 950 struct cgem_softc *sc = (struct cgem_softc *)arg; 951 struct mii_data *mii; 952 953 CGEM_ASSERT_LOCKED(sc); 954 955 /* Poll the phy. */ 956 if (sc->miibus != NULL) { 957 mii = device_get_softc(sc->miibus); 958 mii_tick(mii); 959 } 960 961 /* Poll statistics registers. */ 962 cgem_poll_hw_stats(sc); 963 964 /* Check for receiver hang. */ 965 if (sc->rxhangwar && sc->rx_frames_prev == sc->stats.rx_frames) { 966 /* 967 * Reset receiver logic by toggling RX_EN bit. 1usec 968 * delay is necessary especially when operating at 100mbps 969 * and 10mbps speeds. 970 */ 971 WR4(sc, CGEM_NET_CTRL, sc->net_ctl_shadow & 972 ~CGEM_NET_CTRL_RX_EN); 973 DELAY(1); 974 WR4(sc, CGEM_NET_CTRL, sc->net_ctl_shadow); 975 } 976 sc->rx_frames_prev = sc->stats.rx_frames; 977 978 /* Next callout in one second. */ 979 callout_reset(&sc->tick_ch, hz, cgem_tick, sc); 980 } 981 982 /* Interrupt handler. */ 983 static void 984 cgem_intr(void *arg) 985 { 986 struct cgem_softc *sc = (struct cgem_softc *)arg; 987 if_t ifp = sc->ifp; 988 uint32_t istatus; 989 990 CGEM_LOCK(sc); 991 992 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) { 993 CGEM_UNLOCK(sc); 994 return; 995 } 996 997 /* Read interrupt status and immediately clear the bits. */ 998 istatus = RD4(sc, CGEM_INTR_STAT); 999 WR4(sc, CGEM_INTR_STAT, istatus); 1000 1001 /* Packets received. */ 1002 if ((istatus & CGEM_INTR_RX_COMPLETE) != 0) 1003 cgem_recv(sc); 1004 1005 /* Free up any completed transmit buffers. */ 1006 cgem_clean_tx(sc); 1007 1008 /* Hresp not ok. Something is very bad with DMA. Try to clear. */ 1009 if ((istatus & CGEM_INTR_HRESP_NOT_OK) != 0) { 1010 device_printf(sc->dev, 1011 "cgem_intr: hresp not okay! rx_status=0x%x\n", 1012 RD4(sc, CGEM_RX_STAT)); 1013 WR4(sc, CGEM_RX_STAT, CGEM_RX_STAT_HRESP_NOT_OK); 1014 } 1015 1016 /* Receiver overrun. */ 1017 if ((istatus & CGEM_INTR_RX_OVERRUN) != 0) { 1018 /* Clear status bit. */ 1019 WR4(sc, CGEM_RX_STAT, CGEM_RX_STAT_OVERRUN); 1020 sc->rxoverruns++; 1021 } 1022 1023 /* Receiver ran out of bufs. */ 1024 if ((istatus & CGEM_INTR_RX_USED_READ) != 0) { 1025 WR4(sc, CGEM_NET_CTRL, sc->net_ctl_shadow | 1026 CGEM_NET_CTRL_FLUSH_DPRAM_PKT); 1027 cgem_fill_rqueue(sc); 1028 sc->rxnobufs++; 1029 } 1030 1031 /* Restart transmitter if needed. */ 1032 if (!if_sendq_empty(ifp)) 1033 cgem_start_locked(ifp); 1034 1035 CGEM_UNLOCK(sc); 1036 } 1037 1038 /* Reset hardware. */ 1039 static void 1040 cgem_reset(struct cgem_softc *sc) 1041 { 1042 1043 CGEM_ASSERT_LOCKED(sc); 1044 1045 /* Determine data bus width from design configuration register. */ 1046 switch (RD4(sc, CGEM_DESIGN_CFG1) & 1047 CGEM_DESIGN_CFG1_DMA_BUS_WIDTH_MASK) { 1048 case CGEM_DESIGN_CFG1_DMA_BUS_WIDTH_64: 1049 sc->net_cfg_shadow = CGEM_NET_CFG_DBUS_WIDTH_64; 1050 break; 1051 case CGEM_DESIGN_CFG1_DMA_BUS_WIDTH_128: 1052 sc->net_cfg_shadow = CGEM_NET_CFG_DBUS_WIDTH_128; 1053 break; 1054 default: 1055 sc->net_cfg_shadow = CGEM_NET_CFG_DBUS_WIDTH_32; 1056 } 1057 1058 WR4(sc, CGEM_NET_CTRL, 0); 1059 WR4(sc, CGEM_NET_CFG, sc->net_cfg_shadow); 1060 WR4(sc, CGEM_NET_CTRL, CGEM_NET_CTRL_CLR_STAT_REGS); 1061 WR4(sc, CGEM_TX_STAT, CGEM_TX_STAT_ALL); 1062 WR4(sc, CGEM_RX_STAT, CGEM_RX_STAT_ALL); 1063 WR4(sc, CGEM_INTR_DIS, CGEM_INTR_ALL); 1064 WR4(sc, CGEM_HASH_BOT, 0); 1065 WR4(sc, CGEM_HASH_TOP, 0); 1066 WR4(sc, CGEM_TX_QBAR, 0); /* manual says do this. */ 1067 WR4(sc, CGEM_RX_QBAR, 0); 1068 1069 /* Get management port running even if interface is down. */ 1070 sc->net_cfg_shadow |= CGEM_NET_CFG_MDC_CLK_DIV_48; 1071 WR4(sc, CGEM_NET_CFG, sc->net_cfg_shadow); 1072 1073 sc->net_ctl_shadow = CGEM_NET_CTRL_MGMT_PORT_EN; 1074 WR4(sc, CGEM_NET_CTRL, sc->net_ctl_shadow); 1075 } 1076 1077 /* Bring up the hardware. */ 1078 static void 1079 cgem_config(struct cgem_softc *sc) 1080 { 1081 if_t ifp = sc->ifp; 1082 uint32_t dma_cfg; 1083 u_char *eaddr = if_getlladdr(ifp); 1084 1085 CGEM_ASSERT_LOCKED(sc); 1086 1087 /* Program Net Config Register. */ 1088 sc->net_cfg_shadow &= (CGEM_NET_CFG_MDC_CLK_DIV_MASK | 1089 CGEM_NET_CFG_DBUS_WIDTH_MASK); 1090 sc->net_cfg_shadow |= (CGEM_NET_CFG_FCS_REMOVE | 1091 CGEM_NET_CFG_RX_BUF_OFFSET(ETHER_ALIGN) | 1092 CGEM_NET_CFG_GIGE_EN | CGEM_NET_CFG_1536RXEN | 1093 CGEM_NET_CFG_FULL_DUPLEX | CGEM_NET_CFG_SPEED100); 1094 1095 /* Enable receive checksum offloading? */ 1096 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0) 1097 sc->net_cfg_shadow |= CGEM_NET_CFG_RX_CHKSUM_OFFLD_EN; 1098 1099 WR4(sc, CGEM_NET_CFG, sc->net_cfg_shadow); 1100 1101 /* Program DMA Config Register. */ 1102 dma_cfg = CGEM_DMA_CFG_RX_BUF_SIZE(MCLBYTES) | 1103 CGEM_DMA_CFG_RX_PKTBUF_MEMSZ_SEL_8K | 1104 CGEM_DMA_CFG_TX_PKTBUF_MEMSZ_SEL | 1105 CGEM_DMA_CFG_AHB_FIXED_BURST_LEN_16 | 1106 #ifdef CGEM64 1107 CGEM_DMA_CFG_ADDR_BUS_64 | 1108 #endif 1109 CGEM_DMA_CFG_DISC_WHEN_NO_AHB; 1110 1111 /* Enable transmit checksum offloading? */ 1112 if ((if_getcapenable(ifp) & IFCAP_TXCSUM) != 0) 1113 dma_cfg |= CGEM_DMA_CFG_CHKSUM_GEN_OFFLOAD_EN; 1114 1115 WR4(sc, CGEM_DMA_CFG, dma_cfg); 1116 1117 /* Write the rx and tx descriptor ring addresses to the QBAR regs. */ 1118 WR4(sc, CGEM_RX_QBAR, (uint32_t)sc->rxring_physaddr); 1119 WR4(sc, CGEM_TX_QBAR, (uint32_t)sc->txring_physaddr); 1120 #ifdef CGEM64 1121 WR4(sc, CGEM_RX_QBAR_HI, (uint32_t)(sc->rxring_physaddr >> 32)); 1122 WR4(sc, CGEM_TX_QBAR_HI, (uint32_t)(sc->txring_physaddr >> 32)); 1123 #endif 1124 1125 /* Enable rx and tx. */ 1126 sc->net_ctl_shadow |= (CGEM_NET_CTRL_TX_EN | CGEM_NET_CTRL_RX_EN); 1127 WR4(sc, CGEM_NET_CTRL, sc->net_ctl_shadow); 1128 1129 /* Set receive address in case it changed. */ 1130 WR4(sc, CGEM_SPEC_ADDR_LOW(0), (eaddr[3] << 24) | 1131 (eaddr[2] << 16) | (eaddr[1] << 8) | eaddr[0]); 1132 WR4(sc, CGEM_SPEC_ADDR_HI(0), (eaddr[5] << 8) | eaddr[4]); 1133 1134 /* Set up interrupts. */ 1135 WR4(sc, CGEM_INTR_EN, CGEM_INTR_RX_COMPLETE | CGEM_INTR_RX_OVERRUN | 1136 CGEM_INTR_TX_USED_READ | CGEM_INTR_RX_USED_READ | 1137 CGEM_INTR_HRESP_NOT_OK); 1138 } 1139 1140 /* Turn on interface and load up receive ring with buffers. */ 1141 static void 1142 cgem_init_locked(struct cgem_softc *sc) 1143 { 1144 struct mii_data *mii; 1145 1146 CGEM_ASSERT_LOCKED(sc); 1147 1148 if ((if_getdrvflags(sc->ifp) & IFF_DRV_RUNNING) != 0) 1149 return; 1150 1151 cgem_config(sc); 1152 cgem_fill_rqueue(sc); 1153 1154 if_setdrvflagbits(sc->ifp, IFF_DRV_RUNNING, IFF_DRV_OACTIVE); 1155 1156 if (sc->miibus != NULL) { 1157 mii = device_get_softc(sc->miibus); 1158 mii_mediachg(mii); 1159 } 1160 1161 callout_reset(&sc->tick_ch, hz, cgem_tick, sc); 1162 } 1163 1164 static void 1165 cgem_init(void *arg) 1166 { 1167 struct cgem_softc *sc = (struct cgem_softc *)arg; 1168 1169 CGEM_LOCK(sc); 1170 cgem_init_locked(sc); 1171 CGEM_UNLOCK(sc); 1172 } 1173 1174 /* Turn off interface. Free up any buffers in transmit or receive queues. */ 1175 static void 1176 cgem_stop(struct cgem_softc *sc) 1177 { 1178 int i; 1179 1180 CGEM_ASSERT_LOCKED(sc); 1181 1182 callout_stop(&sc->tick_ch); 1183 1184 /* Shut down hardware. */ 1185 cgem_reset(sc); 1186 1187 /* Clear out transmit queue. */ 1188 memset(sc->txring, 0, CGEM_NUM_TX_DESCS * sizeof(struct cgem_tx_desc)); 1189 for (i = 0; i < CGEM_NUM_TX_DESCS; i++) { 1190 sc->txring[i].ctl = CGEM_TXDESC_USED; 1191 if (sc->txring_m[i]) { 1192 /* Unload and destroy dmamap. */ 1193 bus_dmamap_unload(sc->mbuf_dma_tag, 1194 sc->txring_m_dmamap[i]); 1195 bus_dmamap_destroy(sc->mbuf_dma_tag, 1196 sc->txring_m_dmamap[i]); 1197 sc->txring_m_dmamap[i] = NULL; 1198 m_freem(sc->txring_m[i]); 1199 sc->txring_m[i] = NULL; 1200 } 1201 } 1202 sc->txring[CGEM_NUM_TX_DESCS - 1].ctl |= CGEM_TXDESC_WRAP; 1203 1204 sc->txring_hd_ptr = 0; 1205 sc->txring_tl_ptr = 0; 1206 sc->txring_queued = 0; 1207 1208 /* Clear out receive queue. */ 1209 memset(sc->rxring, 0, CGEM_NUM_RX_DESCS * sizeof(struct cgem_rx_desc)); 1210 for (i = 0; i < CGEM_NUM_RX_DESCS; i++) { 1211 sc->rxring[i].addr = CGEM_RXDESC_OWN; 1212 if (sc->rxring_m[i]) { 1213 /* Unload and destroy dmamap. */ 1214 bus_dmamap_unload(sc->mbuf_dma_tag, 1215 sc->rxring_m_dmamap[i]); 1216 bus_dmamap_destroy(sc->mbuf_dma_tag, 1217 sc->rxring_m_dmamap[i]); 1218 sc->rxring_m_dmamap[i] = NULL; 1219 1220 m_freem(sc->rxring_m[i]); 1221 sc->rxring_m[i] = NULL; 1222 } 1223 } 1224 sc->rxring[CGEM_NUM_RX_DESCS - 1].addr |= CGEM_RXDESC_WRAP; 1225 1226 sc->rxring_hd_ptr = 0; 1227 sc->rxring_tl_ptr = 0; 1228 sc->rxring_queued = 0; 1229 1230 /* Force next statchg or linkchg to program net config register. */ 1231 sc->mii_media_active = 0; 1232 } 1233 1234 static int 1235 cgem_ioctl(if_t ifp, u_long cmd, caddr_t data) 1236 { 1237 struct cgem_softc *sc = if_getsoftc(ifp); 1238 struct ifreq *ifr = (struct ifreq *)data; 1239 struct mii_data *mii; 1240 int error = 0, mask; 1241 1242 switch (cmd) { 1243 case SIOCSIFFLAGS: 1244 CGEM_LOCK(sc); 1245 if ((if_getflags(ifp) & IFF_UP) != 0) { 1246 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 1247 if (((if_getflags(ifp) ^ sc->if_old_flags) & 1248 (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 1249 cgem_rx_filter(sc); 1250 } 1251 } else { 1252 cgem_init_locked(sc); 1253 } 1254 } else if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 1255 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1256 cgem_stop(sc); 1257 } 1258 sc->if_old_flags = if_getflags(ifp); 1259 CGEM_UNLOCK(sc); 1260 break; 1261 1262 case SIOCADDMULTI: 1263 case SIOCDELMULTI: 1264 /* Set up multi-cast filters. */ 1265 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 1266 CGEM_LOCK(sc); 1267 cgem_rx_filter(sc); 1268 CGEM_UNLOCK(sc); 1269 } 1270 break; 1271 1272 case SIOCSIFMEDIA: 1273 case SIOCGIFMEDIA: 1274 if (sc->miibus == NULL) 1275 return (ENXIO); 1276 mii = device_get_softc(sc->miibus); 1277 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1278 break; 1279 1280 case SIOCSIFCAP: 1281 CGEM_LOCK(sc); 1282 mask = if_getcapenable(ifp) ^ ifr->ifr_reqcap; 1283 1284 if ((mask & IFCAP_TXCSUM) != 0) { 1285 if ((ifr->ifr_reqcap & IFCAP_TXCSUM) != 0) { 1286 /* Turn on TX checksumming. */ 1287 if_setcapenablebit(ifp, IFCAP_TXCSUM | 1288 IFCAP_TXCSUM_IPV6, 0); 1289 if_sethwassistbits(ifp, CGEM_CKSUM_ASSIST, 0); 1290 1291 WR4(sc, CGEM_DMA_CFG, 1292 RD4(sc, CGEM_DMA_CFG) | 1293 CGEM_DMA_CFG_CHKSUM_GEN_OFFLOAD_EN); 1294 } else { 1295 /* Turn off TX checksumming. */ 1296 if_setcapenablebit(ifp, 0, IFCAP_TXCSUM | 1297 IFCAP_TXCSUM_IPV6); 1298 if_sethwassistbits(ifp, 0, CGEM_CKSUM_ASSIST); 1299 1300 WR4(sc, CGEM_DMA_CFG, 1301 RD4(sc, CGEM_DMA_CFG) & 1302 ~CGEM_DMA_CFG_CHKSUM_GEN_OFFLOAD_EN); 1303 } 1304 } 1305 if ((mask & IFCAP_RXCSUM) != 0) { 1306 if ((ifr->ifr_reqcap & IFCAP_RXCSUM) != 0) { 1307 /* Turn on RX checksumming. */ 1308 if_setcapenablebit(ifp, IFCAP_RXCSUM | 1309 IFCAP_RXCSUM_IPV6, 0); 1310 sc->net_cfg_shadow |= 1311 CGEM_NET_CFG_RX_CHKSUM_OFFLD_EN; 1312 WR4(sc, CGEM_NET_CFG, sc->net_cfg_shadow); 1313 } else { 1314 /* Turn off RX checksumming. */ 1315 if_setcapenablebit(ifp, 0, IFCAP_RXCSUM | 1316 IFCAP_RXCSUM_IPV6); 1317 sc->net_cfg_shadow &= 1318 ~CGEM_NET_CFG_RX_CHKSUM_OFFLD_EN; 1319 WR4(sc, CGEM_NET_CFG, sc->net_cfg_shadow); 1320 } 1321 } 1322 if ((if_getcapenable(ifp) & (IFCAP_RXCSUM | IFCAP_TXCSUM)) == 1323 (IFCAP_RXCSUM | IFCAP_TXCSUM)) 1324 if_setcapenablebit(ifp, IFCAP_VLAN_HWCSUM, 0); 1325 else 1326 if_setcapenablebit(ifp, 0, IFCAP_VLAN_HWCSUM); 1327 1328 CGEM_UNLOCK(sc); 1329 break; 1330 default: 1331 error = ether_ioctl(ifp, cmd, data); 1332 break; 1333 } 1334 1335 return (error); 1336 } 1337 1338 /* MII bus support routines. 1339 */ 1340 static int 1341 cgem_ifmedia_upd(if_t ifp) 1342 { 1343 struct cgem_softc *sc = (struct cgem_softc *) if_getsoftc(ifp); 1344 struct mii_data *mii; 1345 struct mii_softc *miisc; 1346 int error = 0; 1347 1348 mii = device_get_softc(sc->miibus); 1349 CGEM_LOCK(sc); 1350 if ((if_getflags(ifp) & IFF_UP) != 0) { 1351 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 1352 PHY_RESET(miisc); 1353 error = mii_mediachg(mii); 1354 } 1355 CGEM_UNLOCK(sc); 1356 1357 return (error); 1358 } 1359 1360 static void 1361 cgem_ifmedia_sts(if_t ifp, struct ifmediareq *ifmr) 1362 { 1363 struct cgem_softc *sc = (struct cgem_softc *) if_getsoftc(ifp); 1364 struct mii_data *mii; 1365 1366 mii = device_get_softc(sc->miibus); 1367 CGEM_LOCK(sc); 1368 mii_pollstat(mii); 1369 ifmr->ifm_active = mii->mii_media_active; 1370 ifmr->ifm_status = mii->mii_media_status; 1371 CGEM_UNLOCK(sc); 1372 } 1373 1374 static int 1375 cgem_miibus_readreg(device_t dev, int phy, int reg) 1376 { 1377 struct cgem_softc *sc = device_get_softc(dev); 1378 int tries, val; 1379 1380 WR4(sc, CGEM_PHY_MAINT, CGEM_PHY_MAINT_CLAUSE_22 | 1381 CGEM_PHY_MAINT_MUST_10 | CGEM_PHY_MAINT_OP_READ | 1382 (phy << CGEM_PHY_MAINT_PHY_ADDR_SHIFT) | 1383 (reg << CGEM_PHY_MAINT_REG_ADDR_SHIFT)); 1384 1385 /* Wait for completion. */ 1386 tries=0; 1387 while ((RD4(sc, CGEM_NET_STAT) & CGEM_NET_STAT_PHY_MGMT_IDLE) == 0) { 1388 DELAY(5); 1389 if (++tries > 200) { 1390 device_printf(dev, "phy read timeout: %d\n", reg); 1391 return (-1); 1392 } 1393 } 1394 1395 val = RD4(sc, CGEM_PHY_MAINT) & CGEM_PHY_MAINT_DATA_MASK; 1396 1397 if (reg == MII_EXTSR) 1398 /* 1399 * MAC does not support half-duplex at gig speeds. 1400 * Let mii(4) exclude the capability. 1401 */ 1402 val &= ~(EXTSR_1000XHDX | EXTSR_1000THDX); 1403 1404 return (val); 1405 } 1406 1407 static int 1408 cgem_miibus_writereg(device_t dev, int phy, int reg, int data) 1409 { 1410 struct cgem_softc *sc = device_get_softc(dev); 1411 int tries; 1412 1413 WR4(sc, CGEM_PHY_MAINT, CGEM_PHY_MAINT_CLAUSE_22 | 1414 CGEM_PHY_MAINT_MUST_10 | CGEM_PHY_MAINT_OP_WRITE | 1415 (phy << CGEM_PHY_MAINT_PHY_ADDR_SHIFT) | 1416 (reg << CGEM_PHY_MAINT_REG_ADDR_SHIFT) | 1417 (data & CGEM_PHY_MAINT_DATA_MASK)); 1418 1419 /* Wait for completion. */ 1420 tries = 0; 1421 while ((RD4(sc, CGEM_NET_STAT) & CGEM_NET_STAT_PHY_MGMT_IDLE) == 0) { 1422 DELAY(5); 1423 if (++tries > 200) { 1424 device_printf(dev, "phy write timeout: %d\n", reg); 1425 return (-1); 1426 } 1427 } 1428 1429 return (0); 1430 } 1431 1432 static void 1433 cgem_miibus_statchg(device_t dev) 1434 { 1435 struct cgem_softc *sc = device_get_softc(dev); 1436 struct mii_data *mii = device_get_softc(sc->miibus); 1437 1438 CGEM_ASSERT_LOCKED(sc); 1439 1440 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 1441 (IFM_ACTIVE | IFM_AVALID) && 1442 sc->mii_media_active != mii->mii_media_active) 1443 cgem_mediachange(sc, mii); 1444 } 1445 1446 static void 1447 cgem_miibus_linkchg(device_t dev) 1448 { 1449 struct cgem_softc *sc = device_get_softc(dev); 1450 struct mii_data *mii = device_get_softc(sc->miibus); 1451 1452 CGEM_ASSERT_LOCKED(sc); 1453 1454 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 1455 (IFM_ACTIVE | IFM_AVALID) && 1456 sc->mii_media_active != mii->mii_media_active) 1457 cgem_mediachange(sc, mii); 1458 } 1459 1460 /* 1461 * Overridable weak symbol cgem_set_ref_clk(). This allows platforms to 1462 * provide a function to set the cgem's reference clock. 1463 */ 1464 static int __used 1465 cgem_default_set_ref_clk(int unit, int frequency) 1466 { 1467 1468 return 0; 1469 } 1470 __weak_reference(cgem_default_set_ref_clk, cgem_set_ref_clk); 1471 1472 /* Call to set reference clock and network config bits according to media. */ 1473 static void 1474 cgem_mediachange(struct cgem_softc *sc, struct mii_data *mii) 1475 { 1476 int ref_clk_freq; 1477 1478 CGEM_ASSERT_LOCKED(sc); 1479 1480 /* Update hardware to reflect media. */ 1481 sc->net_cfg_shadow &= ~(CGEM_NET_CFG_SPEED100 | CGEM_NET_CFG_GIGE_EN | 1482 CGEM_NET_CFG_FULL_DUPLEX); 1483 1484 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1485 case IFM_1000_T: 1486 sc->net_cfg_shadow |= (CGEM_NET_CFG_SPEED100 | 1487 CGEM_NET_CFG_GIGE_EN); 1488 ref_clk_freq = 125000000; 1489 break; 1490 case IFM_100_TX: 1491 sc->net_cfg_shadow |= CGEM_NET_CFG_SPEED100; 1492 ref_clk_freq = 25000000; 1493 break; 1494 default: 1495 ref_clk_freq = 2500000; 1496 } 1497 1498 if ((mii->mii_media_active & IFM_FDX) != 0) 1499 sc->net_cfg_shadow |= CGEM_NET_CFG_FULL_DUPLEX; 1500 1501 WR4(sc, CGEM_NET_CFG, sc->net_cfg_shadow); 1502 1503 #ifdef EXT_RESOURCES 1504 if (sc->ref_clk != NULL) { 1505 CGEM_UNLOCK(sc); 1506 if (clk_set_freq(sc->ref_clk, ref_clk_freq, 0)) 1507 device_printf(sc->dev, "could not set ref clk to %d\n", 1508 ref_clk_freq); 1509 CGEM_LOCK(sc); 1510 } 1511 #else 1512 /* Set the reference clock if necessary. */ 1513 if (cgem_set_ref_clk(sc->ref_clk_num, ref_clk_freq)) 1514 device_printf(sc->dev, 1515 "cgem_mediachange: could not set ref clk%d to %d.\n", 1516 sc->ref_clk_num, ref_clk_freq); 1517 #endif 1518 1519 sc->mii_media_active = mii->mii_media_active; 1520 } 1521 1522 static void 1523 cgem_add_sysctls(device_t dev) 1524 { 1525 struct cgem_softc *sc = device_get_softc(dev); 1526 struct sysctl_ctx_list *ctx; 1527 struct sysctl_oid_list *child; 1528 struct sysctl_oid *tree; 1529 1530 ctx = device_get_sysctl_ctx(dev); 1531 child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev)); 1532 1533 SYSCTL_ADD_INT(ctx, child, OID_AUTO, "rxbufs", CTLFLAG_RW, 1534 &sc->rxbufs, 0, "Number receive buffers to provide"); 1535 1536 SYSCTL_ADD_INT(ctx, child, OID_AUTO, "rxhangwar", CTLFLAG_RW, 1537 &sc->rxhangwar, 0, "Enable receive hang work-around"); 1538 1539 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "_rxoverruns", CTLFLAG_RD, 1540 &sc->rxoverruns, 0, "Receive overrun events"); 1541 1542 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "_rxnobufs", CTLFLAG_RD, 1543 &sc->rxnobufs, 0, "Receive buf queue empty events"); 1544 1545 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "_rxdmamapfails", CTLFLAG_RD, 1546 &sc->rxdmamapfails, 0, "Receive DMA map failures"); 1547 1548 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "_txfull", CTLFLAG_RD, 1549 &sc->txfull, 0, "Transmit ring full events"); 1550 1551 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "_txdmamapfails", CTLFLAG_RD, 1552 &sc->txdmamapfails, 0, "Transmit DMA map failures"); 1553 1554 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "_txdefrags", CTLFLAG_RD, 1555 &sc->txdefrags, 0, "Transmit m_defrag() calls"); 1556 1557 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "_txdefragfails", CTLFLAG_RD, 1558 &sc->txdefragfails, 0, "Transmit m_defrag() failures"); 1559 1560 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", 1561 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "GEM statistics"); 1562 child = SYSCTL_CHILDREN(tree); 1563 1564 SYSCTL_ADD_UQUAD(ctx, child, OID_AUTO, "tx_bytes", CTLFLAG_RD, 1565 &sc->stats.tx_bytes, "Total bytes transmitted"); 1566 1567 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_frames", CTLFLAG_RD, 1568 &sc->stats.tx_frames, 0, "Total frames transmitted"); 1569 1570 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_frames_bcast", CTLFLAG_RD, 1571 &sc->stats.tx_frames_bcast, 0, 1572 "Number broadcast frames transmitted"); 1573 1574 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_frames_multi", CTLFLAG_RD, 1575 &sc->stats.tx_frames_multi, 0, 1576 "Number multicast frames transmitted"); 1577 1578 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_frames_pause", 1579 CTLFLAG_RD, &sc->stats.tx_frames_pause, 0, 1580 "Number pause frames transmitted"); 1581 1582 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_frames_64b", CTLFLAG_RD, 1583 &sc->stats.tx_frames_64b, 0, 1584 "Number frames transmitted of size 64 bytes or less"); 1585 1586 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_frames_65to127b", CTLFLAG_RD, 1587 &sc->stats.tx_frames_65to127b, 0, 1588 "Number frames transmitted of size 65-127 bytes"); 1589 1590 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_frames_128to255b", 1591 CTLFLAG_RD, &sc->stats.tx_frames_128to255b, 0, 1592 "Number frames transmitted of size 128-255 bytes"); 1593 1594 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_frames_256to511b", 1595 CTLFLAG_RD, &sc->stats.tx_frames_256to511b, 0, 1596 "Number frames transmitted of size 256-511 bytes"); 1597 1598 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_frames_512to1023b", 1599 CTLFLAG_RD, &sc->stats.tx_frames_512to1023b, 0, 1600 "Number frames transmitted of size 512-1023 bytes"); 1601 1602 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_frames_1024to1536b", 1603 CTLFLAG_RD, &sc->stats.tx_frames_1024to1536b, 0, 1604 "Number frames transmitted of size 1024-1536 bytes"); 1605 1606 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_under_runs", 1607 CTLFLAG_RD, &sc->stats.tx_under_runs, 0, 1608 "Number transmit under-run events"); 1609 1610 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_single_collisn", 1611 CTLFLAG_RD, &sc->stats.tx_single_collisn, 0, 1612 "Number single-collision transmit frames"); 1613 1614 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_multi_collisn", 1615 CTLFLAG_RD, &sc->stats.tx_multi_collisn, 0, 1616 "Number multi-collision transmit frames"); 1617 1618 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_excsv_collisn", 1619 CTLFLAG_RD, &sc->stats.tx_excsv_collisn, 0, 1620 "Number excessive collision transmit frames"); 1621 1622 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_late_collisn", 1623 CTLFLAG_RD, &sc->stats.tx_late_collisn, 0, 1624 "Number late-collision transmit frames"); 1625 1626 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_deferred_frames", 1627 CTLFLAG_RD, &sc->stats.tx_deferred_frames, 0, 1628 "Number deferred transmit frames"); 1629 1630 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_carrier_sense_errs", 1631 CTLFLAG_RD, &sc->stats.tx_carrier_sense_errs, 0, 1632 "Number carrier sense errors on transmit"); 1633 1634 SYSCTL_ADD_UQUAD(ctx, child, OID_AUTO, "rx_bytes", CTLFLAG_RD, 1635 &sc->stats.rx_bytes, "Total bytes received"); 1636 1637 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_frames", CTLFLAG_RD, 1638 &sc->stats.rx_frames, 0, "Total frames received"); 1639 1640 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_frames_bcast", 1641 CTLFLAG_RD, &sc->stats.rx_frames_bcast, 0, 1642 "Number broadcast frames received"); 1643 1644 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_frames_multi", 1645 CTLFLAG_RD, &sc->stats.rx_frames_multi, 0, 1646 "Number multicast frames received"); 1647 1648 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_frames_pause", 1649 CTLFLAG_RD, &sc->stats.rx_frames_pause, 0, 1650 "Number pause frames received"); 1651 1652 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_frames_64b", 1653 CTLFLAG_RD, &sc->stats.rx_frames_64b, 0, 1654 "Number frames received of size 64 bytes or less"); 1655 1656 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_frames_65to127b", 1657 CTLFLAG_RD, &sc->stats.rx_frames_65to127b, 0, 1658 "Number frames received of size 65-127 bytes"); 1659 1660 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_frames_128to255b", 1661 CTLFLAG_RD, &sc->stats.rx_frames_128to255b, 0, 1662 "Number frames received of size 128-255 bytes"); 1663 1664 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_frames_256to511b", 1665 CTLFLAG_RD, &sc->stats.rx_frames_256to511b, 0, 1666 "Number frames received of size 256-511 bytes"); 1667 1668 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_frames_512to1023b", 1669 CTLFLAG_RD, &sc->stats.rx_frames_512to1023b, 0, 1670 "Number frames received of size 512-1023 bytes"); 1671 1672 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_frames_1024to1536b", 1673 CTLFLAG_RD, &sc->stats.rx_frames_1024to1536b, 0, 1674 "Number frames received of size 1024-1536 bytes"); 1675 1676 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_frames_undersize", 1677 CTLFLAG_RD, &sc->stats.rx_frames_undersize, 0, 1678 "Number undersize frames received"); 1679 1680 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_frames_oversize", 1681 CTLFLAG_RD, &sc->stats.rx_frames_oversize, 0, 1682 "Number oversize frames received"); 1683 1684 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_frames_jabber", 1685 CTLFLAG_RD, &sc->stats.rx_frames_jabber, 0, 1686 "Number jabber frames received"); 1687 1688 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_frames_fcs_errs", 1689 CTLFLAG_RD, &sc->stats.rx_frames_fcs_errs, 0, 1690 "Number frames received with FCS errors"); 1691 1692 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_frames_length_errs", 1693 CTLFLAG_RD, &sc->stats.rx_frames_length_errs, 0, 1694 "Number frames received with length errors"); 1695 1696 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_symbol_errs", 1697 CTLFLAG_RD, &sc->stats.rx_symbol_errs, 0, 1698 "Number receive symbol errors"); 1699 1700 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_align_errs", 1701 CTLFLAG_RD, &sc->stats.rx_align_errs, 0, 1702 "Number receive alignment errors"); 1703 1704 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_resource_errs", 1705 CTLFLAG_RD, &sc->stats.rx_resource_errs, 0, 1706 "Number frames received when no rx buffer available"); 1707 1708 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_overrun_errs", 1709 CTLFLAG_RD, &sc->stats.rx_overrun_errs, 0, 1710 "Number frames received but not copied due to receive overrun"); 1711 1712 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_frames_ip_hdr_csum_errs", 1713 CTLFLAG_RD, &sc->stats.rx_ip_hdr_csum_errs, 0, 1714 "Number frames received with IP header checksum errors"); 1715 1716 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_frames_tcp_csum_errs", 1717 CTLFLAG_RD, &sc->stats.rx_tcp_csum_errs, 0, 1718 "Number frames received with TCP checksum errors"); 1719 1720 SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_frames_udp_csum_errs", 1721 CTLFLAG_RD, &sc->stats.rx_udp_csum_errs, 0, 1722 "Number frames received with UDP checksum errors"); 1723 } 1724 1725 static int 1726 cgem_probe(device_t dev) 1727 { 1728 1729 if (!ofw_bus_status_okay(dev)) 1730 return (ENXIO); 1731 1732 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 1733 return (ENXIO); 1734 1735 device_set_desc(dev, "Cadence CGEM Gigabit Ethernet Interface"); 1736 return (0); 1737 } 1738 1739 static int 1740 cgem_attach(device_t dev) 1741 { 1742 struct cgem_softc *sc = device_get_softc(dev); 1743 if_t ifp = NULL; 1744 int rid, err; 1745 u_char eaddr[ETHER_ADDR_LEN]; 1746 int hwtype; 1747 #ifndef EXT_RESOURCES 1748 phandle_t node; 1749 pcell_t cell; 1750 #endif 1751 1752 sc->dev = dev; 1753 CGEM_LOCK_INIT(sc); 1754 1755 /* Key off of compatible string and set hardware-specific options. */ 1756 hwtype = ofw_bus_search_compatible(dev, compat_data)->ocd_data; 1757 if (hwtype == HWTYPE_ZYNQMP) 1758 sc->neednullqs = 1; 1759 if (hwtype == HWTYPE_ZYNQ) 1760 sc->rxhangwar = 1; 1761 1762 #ifdef EXT_RESOURCES 1763 if (hwtype == HWTYPE_ZYNQ || hwtype == HWTYPE_ZYNQMP) { 1764 if (clk_get_by_ofw_name(dev, 0, "tx_clk", &sc->ref_clk) != 0) 1765 device_printf(dev, 1766 "could not retrieve reference clock.\n"); 1767 else if (clk_enable(sc->ref_clk) != 0) 1768 device_printf(dev, "could not enable clock.\n"); 1769 } 1770 else if (hwtype == HWTYPE_SIFIVE_FU540) { 1771 if (clk_get_by_ofw_name(dev, 0, "pclk", &sc->ref_clk) != 0) 1772 device_printf(dev, 1773 "could not retrieve reference clock.\n"); 1774 else if (clk_enable(sc->ref_clk) != 0) 1775 device_printf(dev, "could not enable clock.\n"); 1776 } 1777 #else 1778 /* Get reference clock number and base divider from fdt. */ 1779 node = ofw_bus_get_node(dev); 1780 sc->ref_clk_num = 0; 1781 if (OF_getprop(node, "ref-clock-num", &cell, sizeof(cell)) > 0) 1782 sc->ref_clk_num = fdt32_to_cpu(cell); 1783 #endif 1784 1785 /* Get memory resource. */ 1786 rid = 0; 1787 sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 1788 RF_ACTIVE); 1789 if (sc->mem_res == NULL) { 1790 device_printf(dev, "could not allocate memory resources.\n"); 1791 return (ENOMEM); 1792 } 1793 1794 /* Get IRQ resource. */ 1795 rid = 0; 1796 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1797 RF_ACTIVE); 1798 if (sc->irq_res == NULL) { 1799 device_printf(dev, "could not allocate interrupt resource.\n"); 1800 cgem_detach(dev); 1801 return (ENOMEM); 1802 } 1803 1804 /* Set up ifnet structure. */ 1805 ifp = sc->ifp = if_alloc(IFT_ETHER); 1806 if (ifp == NULL) { 1807 device_printf(dev, "could not allocate ifnet structure\n"); 1808 cgem_detach(dev); 1809 return (ENOMEM); 1810 } 1811 if_setsoftc(ifp, sc); 1812 if_initname(ifp, IF_CGEM_NAME, device_get_unit(dev)); 1813 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 1814 if_setinitfn(ifp, cgem_init); 1815 if_setioctlfn(ifp, cgem_ioctl); 1816 if_setstartfn(ifp, cgem_start); 1817 if_setcapabilitiesbit(ifp, IFCAP_HWCSUM | IFCAP_HWCSUM_IPV6 | 1818 IFCAP_VLAN_MTU | IFCAP_VLAN_HWCSUM, 0); 1819 if_setsendqlen(ifp, CGEM_NUM_TX_DESCS); 1820 if_setsendqready(ifp); 1821 1822 /* Disable hardware checksumming by default. */ 1823 if_sethwassist(ifp, 0); 1824 if_setcapenable(ifp, if_getcapabilities(ifp) & 1825 ~(IFCAP_HWCSUM | IFCAP_HWCSUM_IPV6 | IFCAP_VLAN_HWCSUM)); 1826 1827 sc->if_old_flags = if_getflags(ifp); 1828 sc->rxbufs = DEFAULT_NUM_RX_BUFS; 1829 1830 /* Reset hardware. */ 1831 CGEM_LOCK(sc); 1832 cgem_reset(sc); 1833 CGEM_UNLOCK(sc); 1834 1835 /* Attach phy to mii bus. */ 1836 err = mii_attach(dev, &sc->miibus, ifp, 1837 cgem_ifmedia_upd, cgem_ifmedia_sts, BMSR_DEFCAPMASK, 1838 MII_PHY_ANY, MII_OFFSET_ANY, 0); 1839 if (err) 1840 device_printf(dev, "warning: attaching PHYs failed\n"); 1841 1842 /* Set up TX and RX descriptor area. */ 1843 err = cgem_setup_descs(sc); 1844 if (err) { 1845 device_printf(dev, "could not set up dma mem for descs.\n"); 1846 cgem_detach(dev); 1847 return (ENOMEM); 1848 } 1849 1850 /* Get a MAC address. */ 1851 cgem_get_mac(sc, eaddr); 1852 1853 /* Start ticks. */ 1854 callout_init_mtx(&sc->tick_ch, &sc->sc_mtx, 0); 1855 1856 ether_ifattach(ifp, eaddr); 1857 1858 err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_NET | INTR_MPSAFE | 1859 INTR_EXCL, NULL, cgem_intr, sc, &sc->intrhand); 1860 if (err) { 1861 device_printf(dev, "could not set interrupt handler.\n"); 1862 ether_ifdetach(ifp); 1863 cgem_detach(dev); 1864 return (err); 1865 } 1866 1867 cgem_add_sysctls(dev); 1868 1869 return (0); 1870 } 1871 1872 static int 1873 cgem_detach(device_t dev) 1874 { 1875 struct cgem_softc *sc = device_get_softc(dev); 1876 int i; 1877 1878 if (sc == NULL) 1879 return (ENODEV); 1880 1881 if (device_is_attached(dev)) { 1882 CGEM_LOCK(sc); 1883 cgem_stop(sc); 1884 CGEM_UNLOCK(sc); 1885 callout_drain(&sc->tick_ch); 1886 if_setflagbits(sc->ifp, 0, IFF_UP); 1887 ether_ifdetach(sc->ifp); 1888 } 1889 1890 if (sc->miibus != NULL) { 1891 device_delete_child(dev, sc->miibus); 1892 sc->miibus = NULL; 1893 } 1894 1895 /* Release resources. */ 1896 if (sc->mem_res != NULL) { 1897 bus_release_resource(dev, SYS_RES_MEMORY, 1898 rman_get_rid(sc->mem_res), sc->mem_res); 1899 sc->mem_res = NULL; 1900 } 1901 if (sc->irq_res != NULL) { 1902 if (sc->intrhand) 1903 bus_teardown_intr(dev, sc->irq_res, sc->intrhand); 1904 bus_release_resource(dev, SYS_RES_IRQ, 1905 rman_get_rid(sc->irq_res), sc->irq_res); 1906 sc->irq_res = NULL; 1907 } 1908 1909 /* Release DMA resources. */ 1910 if (sc->rxring != NULL) { 1911 if (sc->rxring_physaddr != 0) { 1912 bus_dmamap_unload(sc->desc_dma_tag, 1913 sc->rxring_dma_map); 1914 sc->rxring_physaddr = 0; 1915 sc->txring_physaddr = 0; 1916 sc->null_qs_physaddr = 0; 1917 } 1918 bus_dmamem_free(sc->desc_dma_tag, sc->rxring, 1919 sc->rxring_dma_map); 1920 sc->rxring = NULL; 1921 sc->txring = NULL; 1922 sc->null_qs = NULL; 1923 1924 for (i = 0; i < CGEM_NUM_RX_DESCS; i++) 1925 if (sc->rxring_m_dmamap[i] != NULL) { 1926 bus_dmamap_destroy(sc->mbuf_dma_tag, 1927 sc->rxring_m_dmamap[i]); 1928 sc->rxring_m_dmamap[i] = NULL; 1929 } 1930 for (i = 0; i < CGEM_NUM_TX_DESCS; i++) 1931 if (sc->txring_m_dmamap[i] != NULL) { 1932 bus_dmamap_destroy(sc->mbuf_dma_tag, 1933 sc->txring_m_dmamap[i]); 1934 sc->txring_m_dmamap[i] = NULL; 1935 } 1936 } 1937 if (sc->desc_dma_tag != NULL) { 1938 bus_dma_tag_destroy(sc->desc_dma_tag); 1939 sc->desc_dma_tag = NULL; 1940 } 1941 if (sc->mbuf_dma_tag != NULL) { 1942 bus_dma_tag_destroy(sc->mbuf_dma_tag); 1943 sc->mbuf_dma_tag = NULL; 1944 } 1945 1946 #ifdef EXT_RESOURCES 1947 if (sc->ref_clk != NULL) { 1948 clk_release(sc->ref_clk); 1949 sc->ref_clk = NULL; 1950 } 1951 #endif 1952 1953 bus_generic_detach(dev); 1954 1955 CGEM_LOCK_DESTROY(sc); 1956 1957 return (0); 1958 } 1959 1960 static device_method_t cgem_methods[] = { 1961 /* Device interface */ 1962 DEVMETHOD(device_probe, cgem_probe), 1963 DEVMETHOD(device_attach, cgem_attach), 1964 DEVMETHOD(device_detach, cgem_detach), 1965 1966 /* MII interface */ 1967 DEVMETHOD(miibus_readreg, cgem_miibus_readreg), 1968 DEVMETHOD(miibus_writereg, cgem_miibus_writereg), 1969 DEVMETHOD(miibus_statchg, cgem_miibus_statchg), 1970 DEVMETHOD(miibus_linkchg, cgem_miibus_linkchg), 1971 1972 DEVMETHOD_END 1973 }; 1974 1975 static driver_t cgem_driver = { 1976 "cgem", 1977 cgem_methods, 1978 sizeof(struct cgem_softc), 1979 }; 1980 1981 DRIVER_MODULE(cgem, simplebus, cgem_driver, cgem_devclass, NULL, NULL); 1982 DRIVER_MODULE(miibus, cgem, miibus_driver, miibus_devclass, NULL, NULL); 1983 MODULE_DEPEND(cgem, miibus, 1, 1, 1); 1984 MODULE_DEPEND(cgem, ether, 1, 1, 1); 1985 SIMPLEBUS_PNP_INFO(compat_data); 1986