1 /*- 2 * Copyright (c) 2007-2013 Broadcom Corporation. All rights reserved. 3 * 4 * Eric Davis <edavis@broadcom.com> 5 * David Christensen <davidch@broadcom.com> 6 * Gary Zambrano <zambrano@broadcom.com> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. Neither the name of Broadcom Corporation nor the name of its contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written consent. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' 22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/cdefs.h> 35 __FBSDID("$FreeBSD$"); 36 37 #ifndef ECORE_SP_H 38 #define ECORE_SP_H 39 40 41 #include <sys/types.h> 42 #include <sys/endian.h> 43 #include <sys/param.h> 44 #include <sys/lock.h> 45 #include <sys/mutex.h> 46 #include <sys/malloc.h> 47 #include <sys/kernel.h> 48 #include <machine/bus.h> 49 #include <net/ethernet.h> 50 51 #if _BYTE_ORDER == _LITTLE_ENDIAN 52 #ifndef LITTLE_ENDIAN 53 #define LITTLE_ENDIAN 54 #endif 55 #ifndef __LITTLE_ENDIAN 56 #define __LITTLE_ENDIAN 57 #endif 58 #undef BIG_ENDIAN 59 #undef __BIG_ENDIAN 60 #else /* _BIG_ENDIAN */ 61 #ifndef BIG_ENDIAN 62 #define BIG_ENDIAN 63 #endif 64 #ifndef __BIG_ENDIAN 65 #define __BIG_ENDIAN 66 #endif 67 #undef LITTLE_ENDIAN 68 #undef __LITTLE_ENDIAN 69 #endif 70 71 #include "ecore_mfw_req.h" 72 #include "ecore_fw_defs.h" 73 #include "ecore_hsi.h" 74 #include "ecore_reg.h" 75 76 struct bxe_softc; 77 typedef bus_addr_t ecore_dma_addr_t; /* expected to be 64 bit wide */ 78 typedef volatile int ecore_atomic_t; 79 80 #if __FreeBSD_version < 1000002 81 typedef int bool; 82 #endif 83 84 #define ETH_ALEN ETHER_ADDR_LEN /* 6 */ 85 86 #define ECORE_SWCID_SHIFT 17 87 #define ECORE_SWCID_MASK ((0x1 << ECORE_SWCID_SHIFT) - 1) 88 89 #define ECORE_MC_HASH_SIZE 8 90 #define ECORE_MC_HASH_OFFSET(sc, i) \ 91 (BAR_TSTRORM_INTMEM + \ 92 TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(FUNC_ID(sc)) + i*4) 93 94 #define ECORE_MAX_MULTICAST 64 95 #define ECORE_MAX_EMUL_MULTI 1 96 97 #define IRO sc->iro_array 98 99 typedef struct mtx ECORE_MUTEX; 100 #define ECORE_MUTEX_INIT(_mutex) \ 101 mtx_init(_mutex, "ecore_lock", "ECORE Lock", MTX_DEF) 102 #define ECORE_MUTEX_LOCK(_mutex) mtx_lock(_mutex) 103 #define ECORE_MUTEX_UNLOCK(_mutex) mtx_unlock(_mutex) 104 105 typedef struct mtx ECORE_MUTEX_SPIN; 106 #define ECORE_SPIN_LOCK_INIT(_spin, _sc) \ 107 mtx_init(_spin, "ecore_lock", "ECORE Lock", MTX_DEF) 108 #define ECORE_SPIN_LOCK_BH(_spin) mtx_lock(_spin) /* bh = bottom-half */ 109 #define ECORE_SPIN_UNLOCK_BH(_spin) mtx_unlock(_spin) /* bh = bottom-half */ 110 111 #define ECORE_SMP_MB_AFTER_CLEAR_BIT() mb() 112 #define ECORE_SMP_MB_BEFORE_CLEAR_BIT() mb() 113 #define ECORE_SMP_MB() mb() 114 #define ECORE_SMP_RMB() rmb() 115 #define ECORE_SMP_WMB() wmb() 116 #define ECORE_MMIOWB() wmb() 117 118 #define ECORE_SET_BIT_NA(bit, var) bit_set(var, bit) /* non-atomic */ 119 #define ECORE_CLEAR_BIT_NA(bit, var) bit_clear(var, bit) /* non-atomic */ 120 #define ECORE_TEST_BIT(bit, var) bxe_test_bit(bit, var) 121 #define ECORE_SET_BIT(bit, var) bxe_set_bit(bit, var) 122 #define ECORE_CLEAR_BIT(bit, var) bxe_clear_bit(bit, var) 123 #define ECORE_TEST_AND_CLEAR_BIT(bit, var) bxe_test_and_clear_bit(bit, var) 124 125 #define ECORE_ATOMIC_READ(a) atomic_load_acq_int((volatile int *)a) 126 #define ECORE_ATOMIC_SET(a, v) atomic_store_rel_int((volatile int *)a, v) 127 #define ECORE_ATOMIC_CMPXCHG(a, o, n) bxe_cmpxchg((volatile int *)a, o, n) 128 129 #define ECORE_RET_PENDING(pending_bit, pending) \ 130 (ECORE_TEST_BIT(pending_bit, pending) ? ECORE_PENDING : ECORE_SUCCESS) 131 132 #define ECORE_SET_FLAG(value, mask, flag) \ 133 do { \ 134 (value) &= ~(mask); \ 135 (value) |= ((flag) << (mask##_SHIFT)); \ 136 } while (0) 137 138 #define ECORE_GET_FLAG(value, mask) \ 139 (((value) &= (mask)) >> (mask##_SHIFT)) 140 141 #define ECORE_MIGHT_SLEEP() 142 143 #define ECORE_FCOE_CID(sc) ((sc)->fp[FCOE_IDX(sc)].cl_id) 144 145 #define ECORE_MEMCMP(_a, _b, _s) memcmp(_a, _b, _s) 146 #define ECORE_MEMCPY(_a, _b, _s) memcpy(_a, _b, _s) 147 #define ECORE_MEMSET(_a, _c, _s) memset(_a, _c, _s) 148 149 #define ECORE_CPU_TO_LE16(x) htole16(x) 150 #define ECORE_CPU_TO_LE32(x) htole32(x) 151 152 #define ECORE_WAIT(_s, _t) DELAY(1000) 153 #define ECORE_MSLEEP(_t) DELAY((_t) * 1000) 154 155 #define ECORE_LIKELY(x) __predict_true(x) 156 #define ECORE_UNLIKELY(x) __predict_false(x) 157 158 #define ECORE_ZALLOC(_size, _flags, _sc) \ 159 malloc(_size, M_TEMP, (M_NOWAIT | M_ZERO)) 160 161 #define ECORE_CALLOC(_len, _size, _flags, _sc) \ 162 malloc(_len * _size, M_TEMP, (M_NOWAIT | M_ZERO)) 163 164 #define ECORE_FREE(_s, _buf, _size) free(_buf, M_TEMP) 165 166 #define SC_ILT(sc) ((sc)->ilt) 167 #define ILOG2(x) bxe_ilog2(x) 168 169 #define ECORE_ILT_ZALLOC(x, y, size) \ 170 do { \ 171 x = malloc(sizeof(struct bxe_dma), M_DEVBUF, (M_NOWAIT | M_ZERO)); \ 172 if (x) { \ 173 if (bxe_dma_alloc((struct bxe_softc *)sc, \ 174 size, (struct bxe_dma *)x, \ 175 "ECORE_ILT") != 0) { \ 176 free(x, M_DEVBUF); \ 177 x = NULL; \ 178 *y = 0; \ 179 } else { \ 180 *y = ((struct bxe_dma *)x)->paddr; \ 181 } \ 182 } \ 183 } while (0) 184 185 #define ECORE_ILT_FREE(x, y, size) \ 186 do { \ 187 if (x) { \ 188 bxe_dma_free((struct bxe_softc *)sc, x); \ 189 free(x, M_DEVBUF); \ 190 x = NULL; \ 191 y = 0; \ 192 } \ 193 } while (0) 194 195 #define ECORE_IS_VALID_ETHER_ADDR(_mac) TRUE 196 197 #define ECORE_IS_MF_SD_MODE IS_MF_SD_MODE 198 #define ECORE_IS_MF_SI_MODE IS_MF_SI_MODE 199 #define ECORE_IS_MF_AFEX_MODE IS_MF_AFEX_MODE 200 201 #define ECORE_SET_CTX_VALIDATION bxe_set_ctx_validation 202 203 #define ECORE_UPDATE_COALESCE_SB_INDEX bxe_update_coalesce_sb_index 204 205 #define ECORE_ALIGN(x, a) ((((x) + (a) - 1) / (a)) * (a)) 206 207 #define ECORE_REG_WR_DMAE_LEN REG_WR_DMAE_LEN 208 209 #define ECORE_PATH_ID SC_PATH 210 #define ECORE_PORT_ID SC_PORT 211 #define ECORE_FUNC_ID SC_FUNC 212 #define ECORE_ABS_FUNC_ID SC_ABS_FUNC 213 214 uint32_t calc_crc32(uint8_t *crc32_packet, uint32_t crc32_length, 215 uint32_t crc32_seed, uint8_t complement); 216 static inline uint32_t 217 ECORE_CRC32_LE(uint32_t seed, uint8_t *mac, uint32_t len) 218 { 219 uint32_t packet_buf[2] = {0}; 220 memcpy(((uint8_t *)(&packet_buf[0]))+2, &mac[0], 2); 221 memcpy(&packet_buf[1], &mac[2], 4); 222 return bswap32(calc_crc32((uint8_t *)packet_buf, 8, seed, 0)); 223 } 224 225 #define ecore_sp_post(_sc, _a, _b, _c, _d) \ 226 bxe_sp_post(_sc, _a, _b, U64_HI(_c), U64_LO(_c), _d) 227 228 #define ECORE_DBG_BREAK_IF(exp) \ 229 do { \ 230 if (__predict_false(exp)) { \ 231 panic("ECORE"); \ 232 } \ 233 } while (0) 234 235 #define ECORE_BUG() \ 236 do { \ 237 panic("BUG (%s:%d)", __FILE__, __LINE__); \ 238 } while(0); 239 240 #define ECORE_BUG_ON(exp) \ 241 do { \ 242 if (__predict_true(exp)) { \ 243 panic("BUG_ON (%s:%d)", __FILE__, __LINE__); \ 244 } \ 245 } while (0) 246 247 #define ECORE_ERR(str, ...) \ 248 BLOGE(sc, "ECORE: " str, ##__VA_ARGS__) 249 250 #define DBG_SP 0x00000004 /* defined in bxe.h */ 251 252 #define ECORE_MSG(sc, m, ...) \ 253 BLOGD(sc, DBG_SP, "ECORE: " m, ##__VA_ARGS__) 254 255 typedef struct _ecore_list_entry_t 256 { 257 struct _ecore_list_entry_t *next, *prev; 258 } ecore_list_entry_t; 259 260 typedef struct ecore_list_t 261 { 262 ecore_list_entry_t *head, *tail; 263 unsigned long cnt; 264 } ecore_list_t; 265 266 /* initialize the list */ 267 #define ECORE_LIST_INIT(_list) \ 268 do { \ 269 (_list)->head = NULL; \ 270 (_list)->tail = NULL; \ 271 (_list)->cnt = 0; \ 272 } while (0) 273 274 /* return TRUE if the element is the last on the list */ 275 #define ECORE_LIST_IS_LAST(_elem, _list) \ 276 (_elem == (_list)->tail) 277 278 /* return TRUE if the list is empty */ 279 #define ECORE_LIST_IS_EMPTY(_list) \ 280 ((_list)->cnt == 0) 281 282 /* return the first element */ 283 #define ECORE_LIST_FIRST_ENTRY(_list, cast, _link) \ 284 (cast *)((_list)->head) 285 286 /* return the next element */ 287 #define ECORE_LIST_NEXT(_elem, _link, cast) \ 288 (cast *)((&((_elem)->_link))->next) 289 290 /* push an element on the head of the list */ 291 #define ECORE_LIST_PUSH_HEAD(_elem, _list) \ 292 do { \ 293 (_elem)->prev = (ecore_list_entry_t *)0; \ 294 (_elem)->next = (_list)->head; \ 295 if ((_list)->tail == (ecore_list_entry_t *)0) { \ 296 (_list)->tail = (_elem); \ 297 } else { \ 298 (_list)->head->prev = (_elem); \ 299 } \ 300 (_list)->head = (_elem); \ 301 (_list)->cnt++; \ 302 } while (0) 303 304 /* push an element on the tail of the list */ 305 #define ECORE_LIST_PUSH_TAIL(_elem, _list) \ 306 do { \ 307 (_elem)->next = (ecore_list_entry_t *)0; \ 308 (_elem)->prev = (_list)->tail; \ 309 if ((_list)->tail) { \ 310 (_list)->tail->next = (_elem); \ 311 } else { \ 312 (_list)->head = (_elem); \ 313 } \ 314 (_list)->tail = (_elem); \ 315 (_list)->cnt++; \ 316 } while (0) 317 318 /* push list1 on the head of list2 and return with list1 as empty */ 319 #define ECORE_LIST_SPLICE_INIT(_list1, _list2) \ 320 do { \ 321 (_list1)->tail->next = (_list2)->head; \ 322 if ((_list2)->head) { \ 323 (_list2)->head->prev = (_list1)->tail; \ 324 } else { \ 325 (_list2)->tail = (_list1)->tail; \ 326 } \ 327 (_list2)->head = (_list1)->head; \ 328 (_list2)->cnt += (_list1)->cnt; \ 329 (_list1)->head = NULL; \ 330 (_list1)->tail = NULL; \ 331 (_list1)->cnt = 0; \ 332 } while (0) 333 334 /* remove an element from the list */ 335 #define ECORE_LIST_REMOVE_ENTRY(_elem, _list) \ 336 do { \ 337 if ((_list)->head == (_elem)) { \ 338 if ((_list)->head) { \ 339 (_list)->head = (_list)->head->next; \ 340 if ((_list)->head) { \ 341 (_list)->head->prev = (ecore_list_entry_t *)0; \ 342 } else { \ 343 (_list)->tail = (ecore_list_entry_t *)0; \ 344 } \ 345 (_list)->cnt--; \ 346 } \ 347 } else if ((_list)->tail == (_elem)) { \ 348 if ((_list)->tail) { \ 349 (_list)->tail = (_list)->tail->prev; \ 350 if ((_list)->tail) { \ 351 (_list)->tail->next = (ecore_list_entry_t *)0; \ 352 } else { \ 353 (_list)->head = (ecore_list_entry_t *)0; \ 354 } \ 355 (_list)->cnt--; \ 356 } \ 357 } else { \ 358 (_elem)->prev->next = (_elem)->next; \ 359 (_elem)->next->prev = (_elem)->prev; \ 360 (_list)->cnt--; \ 361 } \ 362 } while (0) 363 364 /* walk the list */ 365 #define ECORE_LIST_FOR_EACH_ENTRY(pos, _list, _link, cast) \ 366 for (pos = ECORE_LIST_FIRST_ENTRY(_list, cast, _link); \ 367 pos; \ 368 pos = ECORE_LIST_NEXT(pos, _link, cast)) 369 370 /* walk the list (safely) */ 371 #define ECORE_LIST_FOR_EACH_ENTRY_SAFE(pos, n, _list, _link, cast) \ 372 for (pos = ECORE_LIST_FIRST_ENTRY(_list, cast, _lint), \ 373 n = (pos) ? ECORE_LIST_NEXT(pos, _link, cast) : NULL; \ 374 pos != NULL; \ 375 pos = (cast *)n, \ 376 n = (pos) ? ECORE_LIST_NEXT(pos, _link, cast) : NULL) 377 378 379 /* Manipulate a bit vector defined as an array of uint64_t */ 380 381 /* Number of bits in one sge_mask array element */ 382 #define BIT_VEC64_ELEM_SZ 64 383 #define BIT_VEC64_ELEM_SHIFT 6 384 #define BIT_VEC64_ELEM_MASK ((uint64_t)BIT_VEC64_ELEM_SZ - 1) 385 386 #define __BIT_VEC64_SET_BIT(el, bit) \ 387 do { \ 388 el = ((el) | ((uint64_t)0x1 << (bit))); \ 389 } while (0) 390 391 #define __BIT_VEC64_CLEAR_BIT(el, bit) \ 392 do { \ 393 el = ((el) & (~((uint64_t)0x1 << (bit)))); \ 394 } while (0) 395 396 #define BIT_VEC64_SET_BIT(vec64, idx) \ 397 __BIT_VEC64_SET_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \ 398 (idx) & BIT_VEC64_ELEM_MASK) 399 400 #define BIT_VEC64_CLEAR_BIT(vec64, idx) \ 401 __BIT_VEC64_CLEAR_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \ 402 (idx) & BIT_VEC64_ELEM_MASK) 403 404 #define BIT_VEC64_TEST_BIT(vec64, idx) \ 405 (((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT] >> \ 406 ((idx) & BIT_VEC64_ELEM_MASK)) & 0x1) 407 408 /* 409 * Creates a bitmask of all ones in less significant bits. 410 * idx - index of the most significant bit in the created mask 411 */ 412 #define BIT_VEC64_ONES_MASK(idx) \ 413 (((uint64_t)0x1 << (((idx) & BIT_VEC64_ELEM_MASK) + 1)) - 1) 414 #define BIT_VEC64_ELEM_ONE_MASK ((uint64_t)(~0)) 415 416 /* fill in a MAC address the way the FW likes it */ 417 static inline void 418 ecore_set_fw_mac_addr(uint16_t *fw_hi, 419 uint16_t *fw_mid, 420 uint16_t *fw_lo, 421 uint8_t *mac) 422 { 423 ((uint8_t *)fw_hi)[0] = mac[1]; 424 ((uint8_t *)fw_hi)[1] = mac[0]; 425 ((uint8_t *)fw_mid)[0] = mac[3]; 426 ((uint8_t *)fw_mid)[1] = mac[2]; 427 ((uint8_t *)fw_lo)[0] = mac[5]; 428 ((uint8_t *)fw_lo)[1] = mac[4]; 429 } 430 431 432 enum ecore_status_t { 433 ECORE_EXISTS = -6, 434 ECORE_IO = -5, 435 ECORE_TIMEOUT = -4, 436 ECORE_INVAL = -3, 437 ECORE_BUSY = -2, 438 ECORE_NOMEM = -1, 439 ECORE_SUCCESS = 0, 440 /* PENDING is not an error and should be positive */ 441 ECORE_PENDING = 1, 442 }; 443 444 enum { 445 SWITCH_UPDATE, 446 AFEX_UPDATE, 447 }; 448 449 450 451 452 struct bxe_softc; 453 struct eth_context; 454 455 /* Bits representing general command's configuration */ 456 enum { 457 RAMROD_TX, 458 RAMROD_RX, 459 /* Wait until all pending commands complete */ 460 RAMROD_COMP_WAIT, 461 /* Don't send a ramrod, only update a registry */ 462 RAMROD_DRV_CLR_ONLY, 463 /* Configure HW according to the current object state */ 464 RAMROD_RESTORE, 465 /* Execute the next command now */ 466 RAMROD_EXEC, 467 /* Don't add a new command and continue execution of posponed 468 * commands. If not set a new command will be added to the 469 * pending commands list. 470 */ 471 RAMROD_CONT, 472 /* If there is another pending ramrod, wait until it finishes and 473 * re-try to submit this one. This flag can be set only in sleepable 474 * context, and should not be set from the context that completes the 475 * ramrods as deadlock will occur. 476 */ 477 RAMROD_RETRY, 478 }; 479 480 typedef enum { 481 ECORE_OBJ_TYPE_RX, 482 ECORE_OBJ_TYPE_TX, 483 ECORE_OBJ_TYPE_RX_TX, 484 } ecore_obj_type; 485 486 /* Public slow path states */ 487 enum { 488 ECORE_FILTER_MAC_PENDING, 489 ECORE_FILTER_VLAN_PENDING, 490 ECORE_FILTER_VLAN_MAC_PENDING, 491 ECORE_FILTER_RX_MODE_PENDING, 492 ECORE_FILTER_RX_MODE_SCHED, 493 ECORE_FILTER_ISCSI_ETH_START_SCHED, 494 ECORE_FILTER_ISCSI_ETH_STOP_SCHED, 495 ECORE_FILTER_FCOE_ETH_START_SCHED, 496 ECORE_FILTER_FCOE_ETH_STOP_SCHED, 497 ECORE_FILTER_BYPASS_RX_MODE_PENDING, 498 ECORE_FILTER_BYPASS_MAC_PENDING, 499 ECORE_FILTER_BYPASS_RSS_CONF_PENDING, 500 ECORE_FILTER_MCAST_PENDING, 501 ECORE_FILTER_MCAST_SCHED, 502 ECORE_FILTER_RSS_CONF_PENDING, 503 ECORE_AFEX_FCOE_Q_UPDATE_PENDING, 504 ECORE_AFEX_PENDING_VIFSET_MCP_ACK 505 }; 506 507 struct ecore_raw_obj { 508 uint8_t func_id; 509 510 /* Queue params */ 511 uint8_t cl_id; 512 uint32_t cid; 513 514 /* Ramrod data buffer params */ 515 void *rdata; 516 ecore_dma_addr_t rdata_mapping; 517 518 /* Ramrod state params */ 519 int state; /* "ramrod is pending" state bit */ 520 unsigned long *pstate; /* pointer to state buffer */ 521 522 ecore_obj_type obj_type; 523 524 int (*wait_comp)(struct bxe_softc *sc, 525 struct ecore_raw_obj *o); 526 527 bool (*check_pending)(struct ecore_raw_obj *o); 528 void (*clear_pending)(struct ecore_raw_obj *o); 529 void (*set_pending)(struct ecore_raw_obj *o); 530 }; 531 532 /************************* VLAN-MAC commands related parameters ***************/ 533 struct ecore_mac_ramrod_data { 534 uint8_t mac[ETH_ALEN]; 535 uint8_t is_inner_mac; 536 }; 537 538 struct ecore_vlan_ramrod_data { 539 uint16_t vlan; 540 }; 541 542 struct ecore_vlan_mac_ramrod_data { 543 uint8_t mac[ETH_ALEN]; 544 uint8_t is_inner_mac; 545 uint16_t vlan; 546 }; 547 548 union ecore_classification_ramrod_data { 549 struct ecore_mac_ramrod_data mac; 550 struct ecore_vlan_ramrod_data vlan; 551 struct ecore_vlan_mac_ramrod_data vlan_mac; 552 }; 553 554 /* VLAN_MAC commands */ 555 enum ecore_vlan_mac_cmd { 556 ECORE_VLAN_MAC_ADD, 557 ECORE_VLAN_MAC_DEL, 558 ECORE_VLAN_MAC_MOVE, 559 }; 560 561 struct ecore_vlan_mac_data { 562 /* Requested command: ECORE_VLAN_MAC_XX */ 563 enum ecore_vlan_mac_cmd cmd; 564 /* used to contain the data related vlan_mac_flags bits from 565 * ramrod parameters. 566 */ 567 unsigned long vlan_mac_flags; 568 569 /* Needed for MOVE command */ 570 struct ecore_vlan_mac_obj *target_obj; 571 572 union ecore_classification_ramrod_data u; 573 }; 574 575 /*************************** Exe Queue obj ************************************/ 576 union ecore_exe_queue_cmd_data { 577 struct ecore_vlan_mac_data vlan_mac; 578 579 struct { 580 /* TODO */ 581 } mcast; 582 }; 583 584 struct ecore_exeq_elem { 585 ecore_list_entry_t link; 586 587 /* Length of this element in the exe_chunk. */ 588 int cmd_len; 589 590 union ecore_exe_queue_cmd_data cmd_data; 591 }; 592 593 union ecore_qable_obj; 594 595 union ecore_exeq_comp_elem { 596 union event_ring_elem *elem; 597 }; 598 599 struct ecore_exe_queue_obj; 600 601 typedef int (*exe_q_validate)(struct bxe_softc *sc, 602 union ecore_qable_obj *o, 603 struct ecore_exeq_elem *elem); 604 605 typedef int (*exe_q_remove)(struct bxe_softc *sc, 606 union ecore_qable_obj *o, 607 struct ecore_exeq_elem *elem); 608 609 /* Return positive if entry was optimized, 0 - if not, negative 610 * in case of an error. 611 */ 612 typedef int (*exe_q_optimize)(struct bxe_softc *sc, 613 union ecore_qable_obj *o, 614 struct ecore_exeq_elem *elem); 615 typedef int (*exe_q_execute)(struct bxe_softc *sc, 616 union ecore_qable_obj *o, 617 ecore_list_t *exe_chunk, 618 unsigned long *ramrod_flags); 619 typedef struct ecore_exeq_elem * 620 (*exe_q_get)(struct ecore_exe_queue_obj *o, 621 struct ecore_exeq_elem *elem); 622 623 struct ecore_exe_queue_obj { 624 /* Commands pending for an execution. */ 625 ecore_list_t exe_queue; 626 627 /* Commands pending for an completion. */ 628 ecore_list_t pending_comp; 629 630 ECORE_MUTEX_SPIN lock; 631 632 /* Maximum length of commands' list for one execution */ 633 int exe_chunk_len; 634 635 union ecore_qable_obj *owner; 636 637 /****** Virtual functions ******/ 638 /** 639 * Called before commands execution for commands that are really 640 * going to be executed (after 'optimize'). 641 * 642 * Must run under exe_queue->lock 643 */ 644 exe_q_validate validate; 645 646 /** 647 * Called before removing pending commands, cleaning allocated 648 * resources (e.g., credits from validate) 649 */ 650 exe_q_remove remove; 651 652 /** 653 * This will try to cancel the current pending commands list 654 * considering the new command. 655 * 656 * Returns the number of optimized commands or a negative error code 657 * 658 * Must run under exe_queue->lock 659 */ 660 exe_q_optimize optimize; 661 662 /** 663 * Run the next commands chunk (owner specific). 664 */ 665 exe_q_execute execute; 666 667 /** 668 * Return the exe_queue element containing the specific command 669 * if any. Otherwise return NULL. 670 */ 671 exe_q_get get; 672 }; 673 /***************** Classification verbs: Set/Del MAC/VLAN/VLAN-MAC ************/ 674 /* 675 * Element in the VLAN_MAC registry list having all current configured 676 * rules. 677 */ 678 struct ecore_vlan_mac_registry_elem { 679 ecore_list_entry_t link; 680 681 /* Used to store the cam offset used for the mac/vlan/vlan-mac. 682 * Relevant for 57710 and 57711 only. VLANs and MACs share the 683 * same CAM for these chips. 684 */ 685 int cam_offset; 686 687 /* Needed for DEL and RESTORE flows */ 688 unsigned long vlan_mac_flags; 689 690 union ecore_classification_ramrod_data u; 691 }; 692 693 /* Bits representing VLAN_MAC commands specific flags */ 694 enum { 695 ECORE_UC_LIST_MAC, 696 ECORE_ETH_MAC, 697 ECORE_ISCSI_ETH_MAC, 698 ECORE_NETQ_ETH_MAC, 699 ECORE_DONT_CONSUME_CAM_CREDIT, 700 ECORE_DONT_CONSUME_CAM_CREDIT_DEST, 701 }; 702 703 struct ecore_vlan_mac_ramrod_params { 704 /* Object to run the command from */ 705 struct ecore_vlan_mac_obj *vlan_mac_obj; 706 707 /* General command flags: COMP_WAIT, etc. */ 708 unsigned long ramrod_flags; 709 710 /* Command specific configuration request */ 711 struct ecore_vlan_mac_data user_req; 712 }; 713 714 struct ecore_vlan_mac_obj { 715 struct ecore_raw_obj raw; 716 717 /* Bookkeeping list: will prevent the addition of already existing 718 * entries. 719 */ 720 ecore_list_t head; 721 /* Implement a simple reader/writer lock on the head list. 722 * all these fields should only be accessed under the exe_queue lock 723 */ 724 uint8_t head_reader; /* Num. of readers accessing head list */ 725 bool head_exe_request; /* Pending execution request. */ 726 unsigned long saved_ramrod_flags; /* Ramrods of pending execution */ 727 728 /* Execution queue interface instance */ 729 struct ecore_exe_queue_obj exe_queue; 730 731 /* MACs credit pool */ 732 struct ecore_credit_pool_obj *macs_pool; 733 734 /* VLANs credit pool */ 735 struct ecore_credit_pool_obj *vlans_pool; 736 737 /* RAMROD command to be used */ 738 int ramrod_cmd; 739 740 /* copy first n elements onto preallocated buffer 741 * 742 * @param n number of elements to get 743 * @param buf buffer preallocated by caller into which elements 744 * will be copied. Note elements are 4-byte aligned 745 * so buffer size must be able to accommodate the 746 * aligned elements. 747 * 748 * @return number of copied bytes 749 */ 750 751 int (*get_n_elements)(struct bxe_softc *sc, 752 struct ecore_vlan_mac_obj *o, int n, uint8_t *base, 753 uint8_t stride, uint8_t size); 754 755 /** 756 * Checks if ADD-ramrod with the given params may be performed. 757 * 758 * @return zero if the element may be added 759 */ 760 761 int (*check_add)(struct bxe_softc *sc, 762 struct ecore_vlan_mac_obj *o, 763 union ecore_classification_ramrod_data *data); 764 765 /** 766 * Checks if DEL-ramrod with the given params may be performed. 767 * 768 * @return TRUE if the element may be deleted 769 */ 770 struct ecore_vlan_mac_registry_elem * 771 (*check_del)(struct bxe_softc *sc, 772 struct ecore_vlan_mac_obj *o, 773 union ecore_classification_ramrod_data *data); 774 775 /** 776 * Checks if DEL-ramrod with the given params may be performed. 777 * 778 * @return TRUE if the element may be deleted 779 */ 780 bool (*check_move)(struct bxe_softc *sc, 781 struct ecore_vlan_mac_obj *src_o, 782 struct ecore_vlan_mac_obj *dst_o, 783 union ecore_classification_ramrod_data *data); 784 785 /** 786 * Update the relevant credit object(s) (consume/return 787 * correspondingly). 788 */ 789 bool (*get_credit)(struct ecore_vlan_mac_obj *o); 790 bool (*put_credit)(struct ecore_vlan_mac_obj *o); 791 bool (*get_cam_offset)(struct ecore_vlan_mac_obj *o, int *offset); 792 bool (*put_cam_offset)(struct ecore_vlan_mac_obj *o, int offset); 793 794 /** 795 * Configures one rule in the ramrod data buffer. 796 */ 797 void (*set_one_rule)(struct bxe_softc *sc, 798 struct ecore_vlan_mac_obj *o, 799 struct ecore_exeq_elem *elem, int rule_idx, 800 int cam_offset); 801 802 /** 803 * Delete all configured elements having the given 804 * vlan_mac_flags specification. Assumes no pending for 805 * execution commands. Will schedule all all currently 806 * configured MACs/VLANs/VLAN-MACs matching the vlan_mac_flags 807 * specification for deletion and will use the given 808 * ramrod_flags for the last DEL operation. 809 * 810 * @param sc 811 * @param o 812 * @param ramrod_flags RAMROD_XX flags 813 * 814 * @return 0 if the last operation has completed successfully 815 * and there are no more elements left, positive value 816 * if there are pending for completion commands, 817 * negative value in case of failure. 818 */ 819 int (*delete_all)(struct bxe_softc *sc, 820 struct ecore_vlan_mac_obj *o, 821 unsigned long *vlan_mac_flags, 822 unsigned long *ramrod_flags); 823 824 /** 825 * Reconfigures the next MAC/VLAN/VLAN-MAC element from the previously 826 * configured elements list. 827 * 828 * @param sc 829 * @param p Command parameters (RAMROD_COMP_WAIT bit in 830 * ramrod_flags is only taken into an account) 831 * @param ppos a pointer to the cookie that should be given back in the 832 * next call to make function handle the next element. If 833 * *ppos is set to NULL it will restart the iterator. 834 * If returned *ppos == NULL this means that the last 835 * element has been handled. 836 * 837 * @return int 838 */ 839 int (*restore)(struct bxe_softc *sc, 840 struct ecore_vlan_mac_ramrod_params *p, 841 struct ecore_vlan_mac_registry_elem **ppos); 842 843 /** 844 * Should be called on a completion arrival. 845 * 846 * @param sc 847 * @param o 848 * @param cqe Completion element we are handling 849 * @param ramrod_flags if RAMROD_CONT is set the next bulk of 850 * pending commands will be executed. 851 * RAMROD_DRV_CLR_ONLY and RAMROD_RESTORE 852 * may also be set if needed. 853 * 854 * @return 0 if there are neither pending nor waiting for 855 * completion commands. Positive value if there are 856 * pending for execution or for completion commands. 857 * Negative value in case of an error (including an 858 * error in the cqe). 859 */ 860 int (*complete)(struct bxe_softc *sc, struct ecore_vlan_mac_obj *o, 861 union event_ring_elem *cqe, 862 unsigned long *ramrod_flags); 863 864 /** 865 * Wait for completion of all commands. Don't schedule new ones, 866 * just wait. It assumes that the completion code will schedule 867 * for new commands. 868 */ 869 int (*wait)(struct bxe_softc *sc, struct ecore_vlan_mac_obj *o); 870 }; 871 872 enum { 873 ECORE_LLH_CAM_ISCSI_ETH_LINE = 0, 874 ECORE_LLH_CAM_ETH_LINE, 875 ECORE_LLH_CAM_MAX_PF_LINE = NIG_REG_LLH1_FUNC_MEM_SIZE / 2 876 }; 877 878 void ecore_set_mac_in_nig(struct bxe_softc *sc, 879 bool add, unsigned char *dev_addr, int index); 880 881 /** RX_MODE verbs:DROP_ALL/ACCEPT_ALL/ACCEPT_ALL_MULTI/ACCEPT_ALL_VLAN/NORMAL */ 882 883 /* RX_MODE ramrod special flags: set in rx_mode_flags field in 884 * a ecore_rx_mode_ramrod_params. 885 */ 886 enum { 887 ECORE_RX_MODE_FCOE_ETH, 888 ECORE_RX_MODE_ISCSI_ETH, 889 }; 890 891 enum { 892 ECORE_ACCEPT_UNICAST, 893 ECORE_ACCEPT_MULTICAST, 894 ECORE_ACCEPT_ALL_UNICAST, 895 ECORE_ACCEPT_ALL_MULTICAST, 896 ECORE_ACCEPT_BROADCAST, 897 ECORE_ACCEPT_UNMATCHED, 898 ECORE_ACCEPT_ANY_VLAN 899 }; 900 901 struct ecore_rx_mode_ramrod_params { 902 struct ecore_rx_mode_obj *rx_mode_obj; 903 unsigned long *pstate; 904 int state; 905 uint8_t cl_id; 906 uint32_t cid; 907 uint8_t func_id; 908 unsigned long ramrod_flags; 909 unsigned long rx_mode_flags; 910 911 /* rdata is either a pointer to eth_filter_rules_ramrod_data(e2) or to 912 * a tstorm_eth_mac_filter_config (e1x). 913 */ 914 void *rdata; 915 ecore_dma_addr_t rdata_mapping; 916 917 /* Rx mode settings */ 918 unsigned long rx_accept_flags; 919 920 /* internal switching settings */ 921 unsigned long tx_accept_flags; 922 }; 923 924 struct ecore_rx_mode_obj { 925 int (*config_rx_mode)(struct bxe_softc *sc, 926 struct ecore_rx_mode_ramrod_params *p); 927 928 int (*wait_comp)(struct bxe_softc *sc, 929 struct ecore_rx_mode_ramrod_params *p); 930 }; 931 932 /********************** Set multicast group ***********************************/ 933 934 struct ecore_mcast_list_elem { 935 ecore_list_entry_t link; 936 uint8_t *mac; 937 }; 938 939 union ecore_mcast_config_data { 940 uint8_t *mac; 941 uint8_t bin; /* used in a RESTORE flow */ 942 }; 943 944 struct ecore_mcast_ramrod_params { 945 struct ecore_mcast_obj *mcast_obj; 946 947 /* Relevant options are RAMROD_COMP_WAIT and RAMROD_DRV_CLR_ONLY */ 948 unsigned long ramrod_flags; 949 950 ecore_list_t mcast_list; /* list of struct ecore_mcast_list_elem */ 951 /** TODO: 952 * - rename it to macs_num. 953 * - Add a new command type for handling pending commands 954 * (remove "zero semantics"). 955 * 956 * Length of mcast_list. If zero and ADD_CONT command - post 957 * pending commands. 958 */ 959 int mcast_list_len; 960 }; 961 962 enum ecore_mcast_cmd { 963 ECORE_MCAST_CMD_ADD, 964 ECORE_MCAST_CMD_CONT, 965 ECORE_MCAST_CMD_DEL, 966 ECORE_MCAST_CMD_RESTORE, 967 }; 968 969 struct ecore_mcast_obj { 970 struct ecore_raw_obj raw; 971 972 union { 973 struct { 974 #define ECORE_MCAST_BINS_NUM 256 975 #define ECORE_MCAST_VEC_SZ (ECORE_MCAST_BINS_NUM / 64) 976 uint64_t vec[ECORE_MCAST_VEC_SZ]; 977 978 /** Number of BINs to clear. Should be updated 979 * immediately when a command arrives in order to 980 * properly create DEL commands. 981 */ 982 int num_bins_set; 983 } aprox_match; 984 985 struct { 986 ecore_list_t macs; 987 int num_macs_set; 988 } exact_match; 989 } registry; 990 991 /* Pending commands */ 992 ecore_list_t pending_cmds_head; 993 994 /* A state that is set in raw.pstate, when there are pending commands */ 995 int sched_state; 996 997 /* Maximal number of mcast MACs configured in one command */ 998 int max_cmd_len; 999 1000 /* Total number of currently pending MACs to configure: both 1001 * in the pending commands list and in the current command. 1002 */ 1003 int total_pending_num; 1004 1005 uint8_t engine_id; 1006 1007 /** 1008 * @param cmd command to execute (ECORE_MCAST_CMD_X, see above) 1009 */ 1010 int (*config_mcast)(struct bxe_softc *sc, 1011 struct ecore_mcast_ramrod_params *p, 1012 enum ecore_mcast_cmd cmd); 1013 1014 /** 1015 * Fills the ramrod data during the RESTORE flow. 1016 * 1017 * @param sc 1018 * @param o 1019 * @param start_idx Registry index to start from 1020 * @param rdata_idx Index in the ramrod data to start from 1021 * 1022 * @return -1 if we handled the whole registry or index of the last 1023 * handled registry element. 1024 */ 1025 int (*hdl_restore)(struct bxe_softc *sc, struct ecore_mcast_obj *o, 1026 int start_bin, int *rdata_idx); 1027 1028 int (*enqueue_cmd)(struct bxe_softc *sc, struct ecore_mcast_obj *o, 1029 struct ecore_mcast_ramrod_params *p, 1030 enum ecore_mcast_cmd cmd); 1031 1032 void (*set_one_rule)(struct bxe_softc *sc, 1033 struct ecore_mcast_obj *o, int idx, 1034 union ecore_mcast_config_data *cfg_data, 1035 enum ecore_mcast_cmd cmd); 1036 1037 /** Checks if there are more mcast MACs to be set or a previous 1038 * command is still pending. 1039 */ 1040 bool (*check_pending)(struct ecore_mcast_obj *o); 1041 1042 /** 1043 * Set/Clear/Check SCHEDULED state of the object 1044 */ 1045 void (*set_sched)(struct ecore_mcast_obj *o); 1046 void (*clear_sched)(struct ecore_mcast_obj *o); 1047 bool (*check_sched)(struct ecore_mcast_obj *o); 1048 1049 /* Wait until all pending commands complete */ 1050 int (*wait_comp)(struct bxe_softc *sc, struct ecore_mcast_obj *o); 1051 1052 /** 1053 * Handle the internal object counters needed for proper 1054 * commands handling. Checks that the provided parameters are 1055 * feasible. 1056 */ 1057 int (*validate)(struct bxe_softc *sc, 1058 struct ecore_mcast_ramrod_params *p, 1059 enum ecore_mcast_cmd cmd); 1060 1061 /** 1062 * Restore the values of internal counters in case of a failure. 1063 */ 1064 void (*revert)(struct bxe_softc *sc, 1065 struct ecore_mcast_ramrod_params *p, 1066 int old_num_bins); 1067 1068 int (*get_registry_size)(struct ecore_mcast_obj *o); 1069 void (*set_registry_size)(struct ecore_mcast_obj *o, int n); 1070 }; 1071 1072 /*************************** Credit handling **********************************/ 1073 struct ecore_credit_pool_obj { 1074 1075 /* Current amount of credit in the pool */ 1076 ecore_atomic_t credit; 1077 1078 /* Maximum allowed credit. put() will check against it. */ 1079 int pool_sz; 1080 1081 /* Allocate a pool table statically. 1082 * 1083 * Currently the maximum allowed size is MAX_MAC_CREDIT_E2(272) 1084 * 1085 * The set bit in the table will mean that the entry is available. 1086 */ 1087 #define ECORE_POOL_VEC_SIZE (MAX_MAC_CREDIT_E2 / 64) 1088 uint64_t pool_mirror[ECORE_POOL_VEC_SIZE]; 1089 1090 /* Base pool offset (initialized differently */ 1091 int base_pool_offset; 1092 1093 /** 1094 * Get the next free pool entry. 1095 * 1096 * @return TRUE if there was a free entry in the pool 1097 */ 1098 bool (*get_entry)(struct ecore_credit_pool_obj *o, int *entry); 1099 1100 /** 1101 * Return the entry back to the pool. 1102 * 1103 * @return TRUE if entry is legal and has been successfully 1104 * returned to the pool. 1105 */ 1106 bool (*put_entry)(struct ecore_credit_pool_obj *o, int entry); 1107 1108 /** 1109 * Get the requested amount of credit from the pool. 1110 * 1111 * @param cnt Amount of requested credit 1112 * @return TRUE if the operation is successful 1113 */ 1114 bool (*get)(struct ecore_credit_pool_obj *o, int cnt); 1115 1116 /** 1117 * Returns the credit to the pool. 1118 * 1119 * @param cnt Amount of credit to return 1120 * @return TRUE if the operation is successful 1121 */ 1122 bool (*put)(struct ecore_credit_pool_obj *o, int cnt); 1123 1124 /** 1125 * Reads the current amount of credit. 1126 */ 1127 int (*check)(struct ecore_credit_pool_obj *o); 1128 }; 1129 1130 /*************************** RSS configuration ********************************/ 1131 enum { 1132 /* RSS_MODE bits are mutually exclusive */ 1133 ECORE_RSS_MODE_DISABLED, 1134 ECORE_RSS_MODE_REGULAR, 1135 1136 ECORE_RSS_SET_SRCH, /* Setup searcher, E1x specific flag */ 1137 1138 ECORE_RSS_IPV4, 1139 ECORE_RSS_IPV4_TCP, 1140 ECORE_RSS_IPV4_UDP, 1141 ECORE_RSS_IPV6, 1142 ECORE_RSS_IPV6_TCP, 1143 ECORE_RSS_IPV6_UDP, 1144 1145 ECORE_RSS_TUNNELING, 1146 }; 1147 1148 struct ecore_config_rss_params { 1149 struct ecore_rss_config_obj *rss_obj; 1150 1151 /* may have RAMROD_COMP_WAIT set only */ 1152 unsigned long ramrod_flags; 1153 1154 /* ECORE_RSS_X bits */ 1155 unsigned long rss_flags; 1156 1157 /* Number hash bits to take into an account */ 1158 uint8_t rss_result_mask; 1159 1160 /* Indirection table */ 1161 uint8_t ind_table[T_ETH_INDIRECTION_TABLE_SIZE]; 1162 1163 /* RSS hash values */ 1164 uint32_t rss_key[10]; 1165 1166 /* valid only iff ECORE_RSS_UPDATE_TOE is set */ 1167 uint16_t toe_rss_bitmap; 1168 1169 /* valid iff ECORE_RSS_TUNNELING is set */ 1170 uint16_t tunnel_value; 1171 uint16_t tunnel_mask; 1172 }; 1173 1174 struct ecore_rss_config_obj { 1175 struct ecore_raw_obj raw; 1176 1177 /* RSS engine to use */ 1178 uint8_t engine_id; 1179 1180 /* Last configured indirection table */ 1181 uint8_t ind_table[T_ETH_INDIRECTION_TABLE_SIZE]; 1182 1183 /* flags for enabling 4-tupple hash on UDP */ 1184 uint8_t udp_rss_v4; 1185 uint8_t udp_rss_v6; 1186 1187 int (*config_rss)(struct bxe_softc *sc, 1188 struct ecore_config_rss_params *p); 1189 }; 1190 1191 /*********************** Queue state update ***********************************/ 1192 1193 /* UPDATE command options */ 1194 enum { 1195 ECORE_Q_UPDATE_IN_VLAN_REM, 1196 ECORE_Q_UPDATE_IN_VLAN_REM_CHNG, 1197 ECORE_Q_UPDATE_OUT_VLAN_REM, 1198 ECORE_Q_UPDATE_OUT_VLAN_REM_CHNG, 1199 ECORE_Q_UPDATE_ANTI_SPOOF, 1200 ECORE_Q_UPDATE_ANTI_SPOOF_CHNG, 1201 ECORE_Q_UPDATE_ACTIVATE, 1202 ECORE_Q_UPDATE_ACTIVATE_CHNG, 1203 ECORE_Q_UPDATE_DEF_VLAN_EN, 1204 ECORE_Q_UPDATE_DEF_VLAN_EN_CHNG, 1205 ECORE_Q_UPDATE_SILENT_VLAN_REM_CHNG, 1206 ECORE_Q_UPDATE_SILENT_VLAN_REM, 1207 ECORE_Q_UPDATE_TX_SWITCHING_CHNG, 1208 ECORE_Q_UPDATE_TX_SWITCHING, 1209 }; 1210 1211 /* Allowed Queue states */ 1212 enum ecore_q_state { 1213 ECORE_Q_STATE_RESET, 1214 ECORE_Q_STATE_INITIALIZED, 1215 ECORE_Q_STATE_ACTIVE, 1216 ECORE_Q_STATE_MULTI_COS, 1217 ECORE_Q_STATE_MCOS_TERMINATED, 1218 ECORE_Q_STATE_INACTIVE, 1219 ECORE_Q_STATE_STOPPED, 1220 ECORE_Q_STATE_TERMINATED, 1221 ECORE_Q_STATE_FLRED, 1222 ECORE_Q_STATE_MAX, 1223 }; 1224 1225 /* Allowed Queue states */ 1226 enum ecore_q_logical_state { 1227 ECORE_Q_LOGICAL_STATE_ACTIVE, 1228 ECORE_Q_LOGICAL_STATE_STOPPED, 1229 }; 1230 1231 /* Allowed commands */ 1232 enum ecore_queue_cmd { 1233 ECORE_Q_CMD_INIT, 1234 ECORE_Q_CMD_SETUP, 1235 ECORE_Q_CMD_SETUP_TX_ONLY, 1236 ECORE_Q_CMD_DEACTIVATE, 1237 ECORE_Q_CMD_ACTIVATE, 1238 ECORE_Q_CMD_UPDATE, 1239 ECORE_Q_CMD_UPDATE_TPA, 1240 ECORE_Q_CMD_HALT, 1241 ECORE_Q_CMD_CFC_DEL, 1242 ECORE_Q_CMD_TERMINATE, 1243 ECORE_Q_CMD_EMPTY, 1244 ECORE_Q_CMD_MAX, 1245 }; 1246 1247 /* queue SETUP + INIT flags */ 1248 enum { 1249 ECORE_Q_FLG_TPA, 1250 ECORE_Q_FLG_TPA_IPV6, 1251 ECORE_Q_FLG_TPA_GRO, 1252 ECORE_Q_FLG_STATS, 1253 ECORE_Q_FLG_ZERO_STATS, 1254 ECORE_Q_FLG_ACTIVE, 1255 ECORE_Q_FLG_OV, 1256 ECORE_Q_FLG_VLAN, 1257 ECORE_Q_FLG_COS, 1258 ECORE_Q_FLG_HC, 1259 ECORE_Q_FLG_HC_EN, 1260 ECORE_Q_FLG_DHC, 1261 ECORE_Q_FLG_OOO, 1262 ECORE_Q_FLG_FCOE, 1263 ECORE_Q_FLG_LEADING_RSS, 1264 ECORE_Q_FLG_MCAST, 1265 ECORE_Q_FLG_DEF_VLAN, 1266 ECORE_Q_FLG_TX_SWITCH, 1267 ECORE_Q_FLG_TX_SEC, 1268 ECORE_Q_FLG_ANTI_SPOOF, 1269 ECORE_Q_FLG_SILENT_VLAN_REM, 1270 ECORE_Q_FLG_FORCE_DEFAULT_PRI, 1271 ECORE_Q_FLG_REFUSE_OUTBAND_VLAN, 1272 ECORE_Q_FLG_PCSUM_ON_PKT, 1273 ECORE_Q_FLG_TUN_INC_INNER_IP_ID 1274 }; 1275 1276 /* Queue type options: queue type may be a combination of below. */ 1277 enum ecore_q_type { 1278 ECORE_Q_TYPE_FWD, 1279 /** TODO: Consider moving both these flags into the init() 1280 * ramrod params. 1281 */ 1282 ECORE_Q_TYPE_HAS_RX, 1283 ECORE_Q_TYPE_HAS_TX, 1284 }; 1285 1286 #define ECORE_PRIMARY_CID_INDEX 0 1287 #define ECORE_MULTI_TX_COS_E1X 3 /* QM only */ 1288 #define ECORE_MULTI_TX_COS_E2_E3A0 2 1289 #define ECORE_MULTI_TX_COS_E3B0 3 1290 #define ECORE_MULTI_TX_COS 3 /* Maximum possible */ 1291 #define MAC_PAD (ECORE_ALIGN(ETH_ALEN, sizeof(uint32_t)) - ETH_ALEN) 1292 1293 struct ecore_queue_init_params { 1294 struct { 1295 unsigned long flags; 1296 uint16_t hc_rate; 1297 uint8_t fw_sb_id; 1298 uint8_t sb_cq_index; 1299 } tx; 1300 1301 struct { 1302 unsigned long flags; 1303 uint16_t hc_rate; 1304 uint8_t fw_sb_id; 1305 uint8_t sb_cq_index; 1306 } rx; 1307 1308 /* CID context in the host memory */ 1309 struct eth_context *cxts[ECORE_MULTI_TX_COS]; 1310 1311 /* maximum number of cos supported by hardware */ 1312 uint8_t max_cos; 1313 }; 1314 1315 struct ecore_queue_terminate_params { 1316 /* index within the tx_only cids of this queue object */ 1317 uint8_t cid_index; 1318 }; 1319 1320 struct ecore_queue_cfc_del_params { 1321 /* index within the tx_only cids of this queue object */ 1322 uint8_t cid_index; 1323 }; 1324 1325 struct ecore_queue_update_params { 1326 unsigned long update_flags; /* ECORE_Q_UPDATE_XX bits */ 1327 uint16_t def_vlan; 1328 uint16_t silent_removal_value; 1329 uint16_t silent_removal_mask; 1330 /* index within the tx_only cids of this queue object */ 1331 uint8_t cid_index; 1332 }; 1333 1334 struct rxq_pause_params { 1335 uint16_t bd_th_lo; 1336 uint16_t bd_th_hi; 1337 uint16_t rcq_th_lo; 1338 uint16_t rcq_th_hi; 1339 uint16_t sge_th_lo; /* valid iff ECORE_Q_FLG_TPA */ 1340 uint16_t sge_th_hi; /* valid iff ECORE_Q_FLG_TPA */ 1341 uint16_t pri_map; 1342 }; 1343 1344 /* general */ 1345 struct ecore_general_setup_params { 1346 /* valid iff ECORE_Q_FLG_STATS */ 1347 uint8_t stat_id; 1348 1349 uint8_t spcl_id; 1350 uint16_t mtu; 1351 uint8_t cos; 1352 }; 1353 1354 struct ecore_rxq_setup_params { 1355 /* dma */ 1356 ecore_dma_addr_t dscr_map; 1357 ecore_dma_addr_t sge_map; 1358 ecore_dma_addr_t rcq_map; 1359 ecore_dma_addr_t rcq_np_map; 1360 1361 uint16_t drop_flags; 1362 uint16_t buf_sz; 1363 uint8_t fw_sb_id; 1364 uint8_t cl_qzone_id; 1365 1366 /* valid iff ECORE_Q_FLG_TPA */ 1367 uint16_t tpa_agg_sz; 1368 uint16_t sge_buf_sz; 1369 uint8_t max_sges_pkt; 1370 uint8_t max_tpa_queues; 1371 uint8_t rss_engine_id; 1372 1373 /* valid iff ECORE_Q_FLG_MCAST */ 1374 uint8_t mcast_engine_id; 1375 1376 uint8_t cache_line_log; 1377 1378 uint8_t sb_cq_index; 1379 1380 /* valid iff BXN2X_Q_FLG_SILENT_VLAN_REM */ 1381 uint16_t silent_removal_value; 1382 uint16_t silent_removal_mask; 1383 }; 1384 1385 struct ecore_txq_setup_params { 1386 /* dma */ 1387 ecore_dma_addr_t dscr_map; 1388 1389 uint8_t fw_sb_id; 1390 uint8_t sb_cq_index; 1391 uint8_t cos; /* valid iff ECORE_Q_FLG_COS */ 1392 uint16_t traffic_type; 1393 /* equals to the leading rss client id, used for TX classification*/ 1394 uint8_t tss_leading_cl_id; 1395 1396 /* valid iff ECORE_Q_FLG_DEF_VLAN */ 1397 uint16_t default_vlan; 1398 }; 1399 1400 struct ecore_queue_setup_params { 1401 struct ecore_general_setup_params gen_params; 1402 struct ecore_txq_setup_params txq_params; 1403 struct ecore_rxq_setup_params rxq_params; 1404 struct rxq_pause_params pause_params; 1405 unsigned long flags; 1406 }; 1407 1408 struct ecore_queue_setup_tx_only_params { 1409 struct ecore_general_setup_params gen_params; 1410 struct ecore_txq_setup_params txq_params; 1411 unsigned long flags; 1412 /* index within the tx_only cids of this queue object */ 1413 uint8_t cid_index; 1414 }; 1415 1416 struct ecore_queue_state_params { 1417 struct ecore_queue_sp_obj *q_obj; 1418 1419 /* Current command */ 1420 enum ecore_queue_cmd cmd; 1421 1422 /* may have RAMROD_COMP_WAIT set only */ 1423 unsigned long ramrod_flags; 1424 1425 /* Params according to the current command */ 1426 union { 1427 struct ecore_queue_update_params update; 1428 struct ecore_queue_setup_params setup; 1429 struct ecore_queue_init_params init; 1430 struct ecore_queue_setup_tx_only_params tx_only; 1431 struct ecore_queue_terminate_params terminate; 1432 struct ecore_queue_cfc_del_params cfc_del; 1433 } params; 1434 }; 1435 1436 struct ecore_viflist_params { 1437 uint8_t echo_res; 1438 uint8_t func_bit_map_res; 1439 }; 1440 1441 struct ecore_queue_sp_obj { 1442 uint32_t cids[ECORE_MULTI_TX_COS]; 1443 uint8_t cl_id; 1444 uint8_t func_id; 1445 1446 /* number of traffic classes supported by queue. 1447 * The primary connection of the queue supports the first traffic 1448 * class. Any further traffic class is supported by a tx-only 1449 * connection. 1450 * 1451 * Therefore max_cos is also a number of valid entries in the cids 1452 * array. 1453 */ 1454 uint8_t max_cos; 1455 uint8_t num_tx_only, next_tx_only; 1456 1457 enum ecore_q_state state, next_state; 1458 1459 /* bits from enum ecore_q_type */ 1460 unsigned long type; 1461 1462 /* ECORE_Q_CMD_XX bits. This object implements "one 1463 * pending" paradigm but for debug and tracing purposes it's 1464 * more convenient to have different bits for different 1465 * commands. 1466 */ 1467 unsigned long pending; 1468 1469 /* Buffer to use as a ramrod data and its mapping */ 1470 void *rdata; 1471 ecore_dma_addr_t rdata_mapping; 1472 1473 /** 1474 * Performs one state change according to the given parameters. 1475 * 1476 * @return 0 in case of success and negative value otherwise. 1477 */ 1478 int (*send_cmd)(struct bxe_softc *sc, 1479 struct ecore_queue_state_params *params); 1480 1481 /** 1482 * Sets the pending bit according to the requested transition. 1483 */ 1484 int (*set_pending)(struct ecore_queue_sp_obj *o, 1485 struct ecore_queue_state_params *params); 1486 1487 /** 1488 * Checks that the requested state transition is legal. 1489 */ 1490 int (*check_transition)(struct bxe_softc *sc, 1491 struct ecore_queue_sp_obj *o, 1492 struct ecore_queue_state_params *params); 1493 1494 /** 1495 * Completes the pending command. 1496 */ 1497 int (*complete_cmd)(struct bxe_softc *sc, 1498 struct ecore_queue_sp_obj *o, 1499 enum ecore_queue_cmd); 1500 1501 int (*wait_comp)(struct bxe_softc *sc, 1502 struct ecore_queue_sp_obj *o, 1503 enum ecore_queue_cmd cmd); 1504 }; 1505 1506 /********************** Function state update *********************************/ 1507 /* Allowed Function states */ 1508 enum ecore_func_state { 1509 ECORE_F_STATE_RESET, 1510 ECORE_F_STATE_INITIALIZED, 1511 ECORE_F_STATE_STARTED, 1512 ECORE_F_STATE_TX_STOPPED, 1513 ECORE_F_STATE_MAX, 1514 }; 1515 1516 /* Allowed Function commands */ 1517 enum ecore_func_cmd { 1518 ECORE_F_CMD_HW_INIT, 1519 ECORE_F_CMD_START, 1520 ECORE_F_CMD_STOP, 1521 ECORE_F_CMD_HW_RESET, 1522 ECORE_F_CMD_AFEX_UPDATE, 1523 ECORE_F_CMD_AFEX_VIFLISTS, 1524 ECORE_F_CMD_TX_STOP, 1525 ECORE_F_CMD_TX_START, 1526 ECORE_F_CMD_SWITCH_UPDATE, 1527 ECORE_F_CMD_MAX, 1528 }; 1529 1530 struct ecore_func_hw_init_params { 1531 /* A load phase returned by MCP. 1532 * 1533 * May be: 1534 * FW_MSG_CODE_DRV_LOAD_COMMON_CHIP 1535 * FW_MSG_CODE_DRV_LOAD_COMMON 1536 * FW_MSG_CODE_DRV_LOAD_PORT 1537 * FW_MSG_CODE_DRV_LOAD_FUNCTION 1538 */ 1539 uint32_t load_phase; 1540 }; 1541 1542 struct ecore_func_hw_reset_params { 1543 /* A load phase returned by MCP. 1544 * 1545 * May be: 1546 * FW_MSG_CODE_DRV_LOAD_COMMON_CHIP 1547 * FW_MSG_CODE_DRV_LOAD_COMMON 1548 * FW_MSG_CODE_DRV_LOAD_PORT 1549 * FW_MSG_CODE_DRV_LOAD_FUNCTION 1550 */ 1551 uint32_t reset_phase; 1552 }; 1553 1554 struct ecore_func_start_params { 1555 /* Multi Function mode: 1556 * - Single Function 1557 * - Switch Dependent 1558 * - Switch Independent 1559 */ 1560 uint16_t mf_mode; 1561 1562 /* Switch Dependent mode outer VLAN tag */ 1563 uint16_t sd_vlan_tag; 1564 1565 /* Function cos mode */ 1566 uint8_t network_cos_mode; 1567 1568 /* NVGRE classification enablement */ 1569 uint8_t nvgre_clss_en; 1570 1571 /* NO_GRE_TUNNEL/NVGRE_TUNNEL/L2GRE_TUNNEL/IPGRE_TUNNEL */ 1572 uint8_t gre_tunnel_mode; 1573 1574 /* GRE_OUTER_HEADERS_RSS/GRE_INNER_HEADERS_RSS/NVGRE_KEY_ENTROPY_RSS */ 1575 uint8_t gre_tunnel_rss; 1576 1577 }; 1578 1579 struct ecore_func_switch_update_params { 1580 uint8_t suspend; 1581 }; 1582 1583 struct ecore_func_afex_update_params { 1584 uint16_t vif_id; 1585 uint16_t afex_default_vlan; 1586 uint8_t allowed_priorities; 1587 }; 1588 1589 struct ecore_func_afex_viflists_params { 1590 uint16_t vif_list_index; 1591 uint8_t func_bit_map; 1592 uint8_t afex_vif_list_command; 1593 uint8_t func_to_clear; 1594 }; 1595 struct ecore_func_tx_start_params { 1596 struct priority_cos traffic_type_to_priority_cos[MAX_TRAFFIC_TYPES]; 1597 uint8_t dcb_enabled; 1598 uint8_t dcb_version; 1599 uint8_t dont_add_pri_0; 1600 }; 1601 1602 struct ecore_func_state_params { 1603 struct ecore_func_sp_obj *f_obj; 1604 1605 /* Current command */ 1606 enum ecore_func_cmd cmd; 1607 1608 /* may have RAMROD_COMP_WAIT set only */ 1609 unsigned long ramrod_flags; 1610 1611 /* Params according to the current command */ 1612 union { 1613 struct ecore_func_hw_init_params hw_init; 1614 struct ecore_func_hw_reset_params hw_reset; 1615 struct ecore_func_start_params start; 1616 struct ecore_func_switch_update_params switch_update; 1617 struct ecore_func_afex_update_params afex_update; 1618 struct ecore_func_afex_viflists_params afex_viflists; 1619 struct ecore_func_tx_start_params tx_start; 1620 } params; 1621 }; 1622 1623 struct ecore_func_sp_drv_ops { 1624 /* Init tool + runtime initialization: 1625 * - Common Chip 1626 * - Common (per Path) 1627 * - Port 1628 * - Function phases 1629 */ 1630 int (*init_hw_cmn_chip)(struct bxe_softc *sc); 1631 int (*init_hw_cmn)(struct bxe_softc *sc); 1632 int (*init_hw_port)(struct bxe_softc *sc); 1633 int (*init_hw_func)(struct bxe_softc *sc); 1634 1635 /* Reset Function HW: Common, Port, Function phases. */ 1636 void (*reset_hw_cmn)(struct bxe_softc *sc); 1637 void (*reset_hw_port)(struct bxe_softc *sc); 1638 void (*reset_hw_func)(struct bxe_softc *sc); 1639 1640 /* Init/Free GUNZIP resources */ 1641 int (*gunzip_init)(struct bxe_softc *sc); 1642 void (*gunzip_end)(struct bxe_softc *sc); 1643 1644 /* Prepare/Release FW resources */ 1645 int (*init_fw)(struct bxe_softc *sc); 1646 void (*release_fw)(struct bxe_softc *sc); 1647 }; 1648 1649 struct ecore_func_sp_obj { 1650 enum ecore_func_state state, next_state; 1651 1652 /* ECORE_FUNC_CMD_XX bits. This object implements "one 1653 * pending" paradigm but for debug and tracing purposes it's 1654 * more convenient to have different bits for different 1655 * commands. 1656 */ 1657 unsigned long pending; 1658 1659 /* Buffer to use as a ramrod data and its mapping */ 1660 void *rdata; 1661 ecore_dma_addr_t rdata_mapping; 1662 1663 /* Buffer to use as a afex ramrod data and its mapping. 1664 * This can't be same rdata as above because afex ramrod requests 1665 * can arrive to the object in parallel to other ramrod requests. 1666 */ 1667 void *afex_rdata; 1668 ecore_dma_addr_t afex_rdata_mapping; 1669 1670 /* this mutex validates that when pending flag is taken, the next 1671 * ramrod to be sent will be the one set the pending bit 1672 */ 1673 ECORE_MUTEX one_pending_mutex; 1674 1675 /* Driver interface */ 1676 struct ecore_func_sp_drv_ops *drv; 1677 1678 /** 1679 * Performs one state change according to the given parameters. 1680 * 1681 * @return 0 in case of success and negative value otherwise. 1682 */ 1683 int (*send_cmd)(struct bxe_softc *sc, 1684 struct ecore_func_state_params *params); 1685 1686 /** 1687 * Checks that the requested state transition is legal. 1688 */ 1689 int (*check_transition)(struct bxe_softc *sc, 1690 struct ecore_func_sp_obj *o, 1691 struct ecore_func_state_params *params); 1692 1693 /** 1694 * Completes the pending command. 1695 */ 1696 int (*complete_cmd)(struct bxe_softc *sc, 1697 struct ecore_func_sp_obj *o, 1698 enum ecore_func_cmd cmd); 1699 1700 int (*wait_comp)(struct bxe_softc *sc, struct ecore_func_sp_obj *o, 1701 enum ecore_func_cmd cmd); 1702 }; 1703 1704 /********************** Interfaces ********************************************/ 1705 /* Queueable objects set */ 1706 union ecore_qable_obj { 1707 struct ecore_vlan_mac_obj vlan_mac; 1708 }; 1709 /************** Function state update *********/ 1710 void ecore_init_func_obj(struct bxe_softc *sc, 1711 struct ecore_func_sp_obj *obj, 1712 void *rdata, ecore_dma_addr_t rdata_mapping, 1713 void *afex_rdata, ecore_dma_addr_t afex_rdata_mapping, 1714 struct ecore_func_sp_drv_ops *drv_iface); 1715 1716 int ecore_func_state_change(struct bxe_softc *sc, 1717 struct ecore_func_state_params *params); 1718 1719 enum ecore_func_state ecore_func_get_state(struct bxe_softc *sc, 1720 struct ecore_func_sp_obj *o); 1721 /******************* Queue State **************/ 1722 void ecore_init_queue_obj(struct bxe_softc *sc, 1723 struct ecore_queue_sp_obj *obj, uint8_t cl_id, uint32_t *cids, 1724 uint8_t cid_cnt, uint8_t func_id, void *rdata, 1725 ecore_dma_addr_t rdata_mapping, unsigned long type); 1726 1727 int ecore_queue_state_change(struct bxe_softc *sc, 1728 struct ecore_queue_state_params *params); 1729 1730 int ecore_get_q_logical_state(struct bxe_softc *sc, 1731 struct ecore_queue_sp_obj *obj); 1732 1733 /********************* VLAN-MAC ****************/ 1734 void ecore_init_mac_obj(struct bxe_softc *sc, 1735 struct ecore_vlan_mac_obj *mac_obj, 1736 uint8_t cl_id, uint32_t cid, uint8_t func_id, void *rdata, 1737 ecore_dma_addr_t rdata_mapping, int state, 1738 unsigned long *pstate, ecore_obj_type type, 1739 struct ecore_credit_pool_obj *macs_pool); 1740 1741 void ecore_init_vlan_obj(struct bxe_softc *sc, 1742 struct ecore_vlan_mac_obj *vlan_obj, 1743 uint8_t cl_id, uint32_t cid, uint8_t func_id, void *rdata, 1744 ecore_dma_addr_t rdata_mapping, int state, 1745 unsigned long *pstate, ecore_obj_type type, 1746 struct ecore_credit_pool_obj *vlans_pool); 1747 1748 void ecore_init_vlan_mac_obj(struct bxe_softc *sc, 1749 struct ecore_vlan_mac_obj *vlan_mac_obj, 1750 uint8_t cl_id, uint32_t cid, uint8_t func_id, void *rdata, 1751 ecore_dma_addr_t rdata_mapping, int state, 1752 unsigned long *pstate, ecore_obj_type type, 1753 struct ecore_credit_pool_obj *macs_pool, 1754 struct ecore_credit_pool_obj *vlans_pool); 1755 1756 int ecore_vlan_mac_h_read_lock(struct bxe_softc *sc, 1757 struct ecore_vlan_mac_obj *o); 1758 void ecore_vlan_mac_h_read_unlock(struct bxe_softc *sc, 1759 struct ecore_vlan_mac_obj *o); 1760 int ecore_vlan_mac_h_write_lock(struct bxe_softc *sc, 1761 struct ecore_vlan_mac_obj *o); 1762 void ecore_vlan_mac_h_write_unlock(struct bxe_softc *sc, 1763 struct ecore_vlan_mac_obj *o); 1764 int ecore_config_vlan_mac(struct bxe_softc *sc, 1765 struct ecore_vlan_mac_ramrod_params *p); 1766 1767 int ecore_vlan_mac_move(struct bxe_softc *sc, 1768 struct ecore_vlan_mac_ramrod_params *p, 1769 struct ecore_vlan_mac_obj *dest_o); 1770 1771 /********************* RX MODE ****************/ 1772 1773 void ecore_init_rx_mode_obj(struct bxe_softc *sc, 1774 struct ecore_rx_mode_obj *o); 1775 1776 /** 1777 * ecore_config_rx_mode - Send and RX_MODE ramrod according to the provided parameters. 1778 * 1779 * @p: Command parameters 1780 * 1781 * Return: 0 - if operation was successful and there is no pending completions, 1782 * positive number - if there are pending completions, 1783 * negative - if there were errors 1784 */ 1785 int ecore_config_rx_mode(struct bxe_softc *sc, 1786 struct ecore_rx_mode_ramrod_params *p); 1787 1788 /****************** MULTICASTS ****************/ 1789 1790 void ecore_init_mcast_obj(struct bxe_softc *sc, 1791 struct ecore_mcast_obj *mcast_obj, 1792 uint8_t mcast_cl_id, uint32_t mcast_cid, uint8_t func_id, 1793 uint8_t engine_id, void *rdata, ecore_dma_addr_t rdata_mapping, 1794 int state, unsigned long *pstate, 1795 ecore_obj_type type); 1796 1797 /** 1798 * ecore_config_mcast - Configure multicast MACs list. 1799 * 1800 * @cmd: command to execute: BNX2X_MCAST_CMD_X 1801 * 1802 * May configure a new list 1803 * provided in p->mcast_list (ECORE_MCAST_CMD_ADD), clean up 1804 * (ECORE_MCAST_CMD_DEL) or restore (ECORE_MCAST_CMD_RESTORE) a current 1805 * configuration, continue to execute the pending commands 1806 * (ECORE_MCAST_CMD_CONT). 1807 * 1808 * If previous command is still pending or if number of MACs to 1809 * configure is more that maximum number of MACs in one command, 1810 * the current command will be enqueued to the tail of the 1811 * pending commands list. 1812 * 1813 * Return: 0 is operation was successfull and there are no pending completions, 1814 * negative if there were errors, positive if there are pending 1815 * completions. 1816 */ 1817 int ecore_config_mcast(struct bxe_softc *sc, 1818 struct ecore_mcast_ramrod_params *p, 1819 enum ecore_mcast_cmd cmd); 1820 1821 /****************** CREDIT POOL ****************/ 1822 void ecore_init_mac_credit_pool(struct bxe_softc *sc, 1823 struct ecore_credit_pool_obj *p, uint8_t func_id, 1824 uint8_t func_num); 1825 void ecore_init_vlan_credit_pool(struct bxe_softc *sc, 1826 struct ecore_credit_pool_obj *p, uint8_t func_id, 1827 uint8_t func_num); 1828 1829 /****************** RSS CONFIGURATION ****************/ 1830 void ecore_init_rss_config_obj(struct bxe_softc *sc, 1831 struct ecore_rss_config_obj *rss_obj, 1832 uint8_t cl_id, uint32_t cid, uint8_t func_id, uint8_t engine_id, 1833 void *rdata, ecore_dma_addr_t rdata_mapping, 1834 int state, unsigned long *pstate, 1835 ecore_obj_type type); 1836 1837 /** 1838 * ecore_config_rss - Updates RSS configuration according to provided parameters 1839 * 1840 * Return: 0 in case of success 1841 */ 1842 int ecore_config_rss(struct bxe_softc *sc, 1843 struct ecore_config_rss_params *p); 1844 1845 /** 1846 * ecore_get_rss_ind_table - Return the current ind_table configuration. 1847 * 1848 * @ind_table: buffer to fill with the current indirection 1849 * table content. Should be at least 1850 * T_ETH_INDIRECTION_TABLE_SIZE bytes long. 1851 */ 1852 void ecore_get_rss_ind_table(struct ecore_rss_config_obj *rss_obj, 1853 uint8_t *ind_table); 1854 1855 1856 #endif /* ECORE_SP_H */ 1857 1858