1 /*- 2 * Copyright (c) 2007-2017 QLogic Corporation. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS 18 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 19 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 20 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 21 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 22 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 23 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 24 * THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #ifndef ECORE_SP_H 31 #define ECORE_SP_H 32 33 34 #include <sys/types.h> 35 #include <sys/endian.h> 36 #include <sys/param.h> 37 #include <sys/lock.h> 38 #include <sys/mutex.h> 39 #include <sys/malloc.h> 40 #include <sys/kernel.h> 41 #include <machine/bus.h> 42 #include <net/ethernet.h> 43 44 #if _BYTE_ORDER == _LITTLE_ENDIAN 45 #ifndef LITTLE_ENDIAN 46 #define LITTLE_ENDIAN 47 #endif 48 #ifndef __LITTLE_ENDIAN 49 #define __LITTLE_ENDIAN 50 #endif 51 #undef BIG_ENDIAN 52 #undef __BIG_ENDIAN 53 #else /* _BIG_ENDIAN */ 54 #ifndef BIG_ENDIAN 55 #define BIG_ENDIAN 56 #endif 57 #ifndef __BIG_ENDIAN 58 #define __BIG_ENDIAN 59 #endif 60 #undef LITTLE_ENDIAN 61 #undef __LITTLE_ENDIAN 62 #endif 63 64 #include "ecore_mfw_req.h" 65 #include "ecore_fw_defs.h" 66 #include "ecore_hsi.h" 67 #include "ecore_reg.h" 68 69 struct bxe_softc; 70 typedef bus_addr_t ecore_dma_addr_t; /* expected to be 64 bit wide */ 71 typedef volatile int ecore_atomic_t; 72 73 #ifndef __bool_true_false_are_defined 74 #ifndef __cplusplus 75 #define bool _Bool 76 #if __STDC_VERSION__ < 199901L && __GNUC__ < 3 && !defined(__INTEL_COMPILER) 77 typedef _Bool bool; 78 #endif 79 #endif /* !__cplusplus */ 80 #endif /* !__bool_true_false_are_defined$ */ 81 82 #define ETH_ALEN ETHER_ADDR_LEN /* 6 */ 83 84 #define ECORE_SWCID_SHIFT 17 85 #define ECORE_SWCID_MASK ((0x1 << ECORE_SWCID_SHIFT) - 1) 86 87 #define ECORE_MC_HASH_SIZE 8 88 #define ECORE_MC_HASH_OFFSET(sc, i) \ 89 (BAR_TSTRORM_INTMEM + \ 90 TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(FUNC_ID(sc)) + i*4) 91 92 #define ECORE_MAX_MULTICAST 64 93 #define ECORE_MAX_EMUL_MULTI 1 94 95 #define IRO sc->iro_array 96 97 typedef struct mtx ECORE_MUTEX; 98 #define ECORE_MUTEX_INIT(_mutex) \ 99 mtx_init(_mutex, "ecore_lock", "ECORE Lock", MTX_DEF) 100 #define ECORE_MUTEX_LOCK(_mutex) mtx_lock(_mutex) 101 #define ECORE_MUTEX_UNLOCK(_mutex) mtx_unlock(_mutex) 102 103 typedef struct mtx ECORE_MUTEX_SPIN; 104 #define ECORE_SPIN_LOCK_INIT(_spin, _sc) \ 105 mtx_init(_spin, "ecore_lock", "ECORE Lock", MTX_DEF) 106 #define ECORE_SPIN_LOCK_BH(_spin) mtx_lock(_spin) /* bh = bottom-half */ 107 #define ECORE_SPIN_UNLOCK_BH(_spin) mtx_unlock(_spin) /* bh = bottom-half */ 108 109 #define ECORE_SMP_MB_AFTER_CLEAR_BIT() mb() 110 #define ECORE_SMP_MB_BEFORE_CLEAR_BIT() mb() 111 #define ECORE_SMP_MB() mb() 112 #define ECORE_SMP_RMB() rmb() 113 #define ECORE_SMP_WMB() wmb() 114 #define ECORE_MMIOWB() wmb() 115 116 #define ECORE_SET_BIT_NA(bit, var) bit_set(var, bit) /* non-atomic */ 117 #define ECORE_CLEAR_BIT_NA(bit, var) bit_clear(var, bit) /* non-atomic */ 118 #define ECORE_TEST_BIT(bit, var) bxe_test_bit(bit, var) 119 #define ECORE_SET_BIT(bit, var) bxe_set_bit(bit, var) 120 #define ECORE_CLEAR_BIT(bit, var) bxe_clear_bit(bit, var) 121 #define ECORE_TEST_AND_CLEAR_BIT(bit, var) bxe_test_and_clear_bit(bit, var) 122 123 #define ECORE_ATOMIC_READ(a) atomic_load_acq_int((volatile int *)a) 124 #define ECORE_ATOMIC_SET(a, v) atomic_store_rel_int((volatile int *)a, v) 125 #define ECORE_ATOMIC_CMPXCHG(a, o, n) bxe_cmpxchg((volatile int *)a, o, n) 126 127 #define ECORE_RET_PENDING(pending_bit, pending) \ 128 (ECORE_TEST_BIT(pending_bit, pending) ? ECORE_PENDING : ECORE_SUCCESS) 129 130 #define ECORE_SET_FLAG(value, mask, flag) \ 131 do { \ 132 (value) &= ~(mask); \ 133 (value) |= ((flag) << (mask##_SHIFT)); \ 134 } while (0) 135 136 #define ECORE_GET_FLAG(value, mask) \ 137 (((value) &= (mask)) >> (mask##_SHIFT)) 138 139 #define ECORE_MIGHT_SLEEP() 140 141 #define ECORE_FCOE_CID(sc) ((sc)->fp[FCOE_IDX(sc)].cl_id) 142 143 #define ECORE_MEMCMP(_a, _b, _s) memcmp(_a, _b, _s) 144 #define ECORE_MEMCPY(_a, _b, _s) memcpy(_a, _b, _s) 145 #define ECORE_MEMSET(_a, _c, _s) memset(_a, _c, _s) 146 147 #define ECORE_CPU_TO_LE16(x) htole16(x) 148 #define ECORE_CPU_TO_LE32(x) htole32(x) 149 150 #define ECORE_WAIT(_s, _t) DELAY(1000) 151 #define ECORE_MSLEEP(_t) DELAY((_t) * 1000) 152 153 #define ECORE_LIKELY(x) __predict_true(x) 154 #define ECORE_UNLIKELY(x) __predict_false(x) 155 156 #define ECORE_ZALLOC(_size, _flags, _sc) \ 157 malloc(_size, M_TEMP, (M_NOWAIT | M_ZERO)) 158 159 #define ECORE_CALLOC(_len, _size, _flags, _sc) \ 160 malloc(_len * _size, M_TEMP, (M_NOWAIT | M_ZERO)) 161 162 #define ECORE_FREE(_s, _buf, _size) free(_buf, M_TEMP) 163 164 #define SC_ILT(sc) ((sc)->ilt) 165 #define ILOG2(x) bxe_ilog2(x) 166 167 #define ECORE_ILT_ZALLOC(x, y, size) \ 168 do { \ 169 x = malloc(sizeof(struct bxe_dma), M_DEVBUF, (M_NOWAIT | M_ZERO)); \ 170 if (x) { \ 171 if (bxe_dma_alloc((struct bxe_softc *)sc, \ 172 size, (struct bxe_dma *)x, \ 173 "ECORE_ILT") != 0) { \ 174 free(x, M_DEVBUF); \ 175 x = NULL; \ 176 *y = 0; \ 177 } else { \ 178 *y = ((struct bxe_dma *)x)->paddr; \ 179 } \ 180 } \ 181 } while (0) 182 183 #define ECORE_ILT_FREE(x, y, size) \ 184 do { \ 185 if (x) { \ 186 bxe_dma_free((struct bxe_softc *)sc, x); \ 187 free(x, M_DEVBUF); \ 188 x = NULL; \ 189 y = 0; \ 190 } \ 191 } while (0) 192 193 #define ECORE_IS_VALID_ETHER_ADDR(_mac) TRUE 194 195 #define ECORE_IS_MF_SD_MODE IS_MF_SD_MODE 196 #define ECORE_IS_MF_SI_MODE IS_MF_SI_MODE 197 #define ECORE_IS_MF_AFEX_MODE IS_MF_AFEX_MODE 198 199 #define ECORE_SET_CTX_VALIDATION bxe_set_ctx_validation 200 201 #define ECORE_UPDATE_COALESCE_SB_INDEX bxe_update_coalesce_sb_index 202 203 #define ECORE_ALIGN(x, a) ((((x) + (a) - 1) / (a)) * (a)) 204 205 #define ECORE_REG_WR_DMAE_LEN REG_WR_DMAE_LEN 206 207 #define ECORE_PATH_ID SC_PATH 208 #define ECORE_PORT_ID SC_PORT 209 #define ECORE_FUNC_ID SC_FUNC 210 #define ECORE_ABS_FUNC_ID SC_ABS_FUNC 211 212 uint32_t calc_crc32(uint8_t *crc32_packet, uint32_t crc32_length, 213 uint32_t crc32_seed, uint8_t complement); 214 static inline uint32_t 215 ECORE_CRC32_LE(uint32_t seed, uint8_t *mac, uint32_t len) 216 { 217 uint32_t packet_buf[2] = {0}; 218 memcpy(((uint8_t *)(&packet_buf[0]))+2, &mac[0], 2); 219 memcpy(&packet_buf[1], &mac[2], 4); 220 return bswap32(calc_crc32((uint8_t *)packet_buf, 8, seed, 0)); 221 } 222 223 #define ecore_sp_post(_sc, _a, _b, _c, _d) \ 224 bxe_sp_post(_sc, _a, _b, U64_HI(_c), U64_LO(_c), _d) 225 226 #ifdef ECORE_STOP_ON_ERROR 227 228 #define ECORE_DBG_BREAK_IF(exp) \ 229 do { \ 230 if (__predict_false(exp)) { \ 231 panic("ECORE"); \ 232 } \ 233 } while (0) 234 235 #define ECORE_BUG() \ 236 do { \ 237 panic("BUG (%s:%d)", __FILE__, __LINE__); \ 238 } while(0); 239 240 #define ECORE_BUG_ON(exp) \ 241 do { \ 242 if (__predict_true(exp)) { \ 243 panic("BUG_ON (%s:%d)", __FILE__, __LINE__); \ 244 } \ 245 } while (0) 246 247 #else 248 249 250 extern unsigned long bxe_debug; 251 #define BXE_DEBUG_ECORE_DBG_BREAK_IF 0x01 252 #define BXE_DEBUG_ECORE_BUG 0x02 253 #define BXE_DEBUG_ECORE_BUG_ON 0x04 254 255 #define ECORE_DBG_BREAK_IF(exp) \ 256 if (bxe_debug & BXE_DEBUG_ECORE_DBG_BREAK_IF) \ 257 printf("%s (%s,%d)\n", __FUNCTION__, __FILE__, __LINE__); 258 259 #define ECORE_BUG(exp) \ 260 if (bxe_debug & BXE_DEBUG_ECORE_BUG) \ 261 printf("%s (%s,%d)\n", __FUNCTION__, __FILE__, __LINE__); 262 263 #define ECORE_BUG_ON(exp) \ 264 if (bxe_debug & BXE_DEBUG_ECORE_BUG_ON) \ 265 printf("%s (%s,%d)\n", __FUNCTION__, __FILE__, __LINE__); 266 267 268 #endif /* #ifdef ECORE_STOP_ON_ERROR */ 269 270 #define ECORE_ERR(str, ...) \ 271 BLOGE(sc, "ECORE: " str, ##__VA_ARGS__) 272 273 #define DBG_SP 0x00000004 /* defined in bxe.h */ 274 275 #define ECORE_MSG(sc, m, ...) \ 276 BLOGD(sc, DBG_SP, "ECORE: " m, ##__VA_ARGS__) 277 278 typedef struct _ecore_list_entry_t 279 { 280 struct _ecore_list_entry_t *next, *prev; 281 } ecore_list_entry_t; 282 283 typedef struct ecore_list_t 284 { 285 ecore_list_entry_t *head, *tail; 286 unsigned long cnt; 287 } ecore_list_t; 288 289 /* initialize the list */ 290 #define ECORE_LIST_INIT(_list) \ 291 do { \ 292 (_list)->head = NULL; \ 293 (_list)->tail = NULL; \ 294 (_list)->cnt = 0; \ 295 } while (0) 296 297 /* return TRUE if the element is the last on the list */ 298 #define ECORE_LIST_IS_LAST(_elem, _list) \ 299 (_elem == (_list)->tail) 300 301 /* return TRUE if the list is empty */ 302 #define ECORE_LIST_IS_EMPTY(_list) \ 303 ((_list)->cnt == 0) 304 305 /* return the first element */ 306 #define ECORE_LIST_FIRST_ENTRY(_list, cast, _link) \ 307 (cast *)((_list)->head) 308 309 /* return the next element */ 310 #define ECORE_LIST_NEXT(_elem, _link, cast) \ 311 (cast *)((&((_elem)->_link))->next) 312 313 /* push an element on the head of the list */ 314 #define ECORE_LIST_PUSH_HEAD(_elem, _list) \ 315 do { \ 316 (_elem)->prev = (ecore_list_entry_t *)0; \ 317 (_elem)->next = (_list)->head; \ 318 if ((_list)->tail == (ecore_list_entry_t *)0) { \ 319 (_list)->tail = (_elem); \ 320 } else { \ 321 (_list)->head->prev = (_elem); \ 322 } \ 323 (_list)->head = (_elem); \ 324 (_list)->cnt++; \ 325 } while (0) 326 327 /* push an element on the tail of the list */ 328 #define ECORE_LIST_PUSH_TAIL(_elem, _list) \ 329 do { \ 330 (_elem)->next = (ecore_list_entry_t *)0; \ 331 (_elem)->prev = (_list)->tail; \ 332 if ((_list)->tail) { \ 333 (_list)->tail->next = (_elem); \ 334 } else { \ 335 (_list)->head = (_elem); \ 336 } \ 337 (_list)->tail = (_elem); \ 338 (_list)->cnt++; \ 339 } while (0) 340 341 /* push list1 on the head of list2 and return with list1 as empty */ 342 #define ECORE_LIST_SPLICE_INIT(_list1, _list2) \ 343 do { \ 344 (_list1)->tail->next = (_list2)->head; \ 345 if ((_list2)->head) { \ 346 (_list2)->head->prev = (_list1)->tail; \ 347 } else { \ 348 (_list2)->tail = (_list1)->tail; \ 349 } \ 350 (_list2)->head = (_list1)->head; \ 351 (_list2)->cnt += (_list1)->cnt; \ 352 (_list1)->head = NULL; \ 353 (_list1)->tail = NULL; \ 354 (_list1)->cnt = 0; \ 355 } while (0) 356 357 /* remove an element from the list */ 358 #define ECORE_LIST_REMOVE_ENTRY(_elem, _list) \ 359 do { \ 360 if ((_list)->head == (_elem)) { \ 361 if ((_list)->head) { \ 362 (_list)->head = (_list)->head->next; \ 363 if ((_list)->head) { \ 364 (_list)->head->prev = (ecore_list_entry_t *)0; \ 365 } else { \ 366 (_list)->tail = (ecore_list_entry_t *)0; \ 367 } \ 368 (_list)->cnt--; \ 369 } \ 370 } else if ((_list)->tail == (_elem)) { \ 371 if ((_list)->tail) { \ 372 (_list)->tail = (_list)->tail->prev; \ 373 if ((_list)->tail) { \ 374 (_list)->tail->next = (ecore_list_entry_t *)0; \ 375 } else { \ 376 (_list)->head = (ecore_list_entry_t *)0; \ 377 } \ 378 (_list)->cnt--; \ 379 } \ 380 } else { \ 381 (_elem)->prev->next = (_elem)->next; \ 382 (_elem)->next->prev = (_elem)->prev; \ 383 (_list)->cnt--; \ 384 } \ 385 } while (0) 386 387 /* walk the list */ 388 #define ECORE_LIST_FOR_EACH_ENTRY(pos, _list, _link, cast) \ 389 for (pos = ECORE_LIST_FIRST_ENTRY(_list, cast, _link); \ 390 pos; \ 391 pos = ECORE_LIST_NEXT(pos, _link, cast)) 392 393 /* walk the list (safely) */ 394 #define ECORE_LIST_FOR_EACH_ENTRY_SAFE(pos, n, _list, _link, cast) \ 395 for (pos = ECORE_LIST_FIRST_ENTRY(_list, cast, _lint), \ 396 n = (pos) ? ECORE_LIST_NEXT(pos, _link, cast) : NULL; \ 397 pos != NULL; \ 398 pos = (cast *)n, \ 399 n = (pos) ? ECORE_LIST_NEXT(pos, _link, cast) : NULL) 400 401 402 /* Manipulate a bit vector defined as an array of uint64_t */ 403 404 /* Number of bits in one sge_mask array element */ 405 #define BIT_VEC64_ELEM_SZ 64 406 #define BIT_VEC64_ELEM_SHIFT 6 407 #define BIT_VEC64_ELEM_MASK ((uint64_t)BIT_VEC64_ELEM_SZ - 1) 408 409 #define __BIT_VEC64_SET_BIT(el, bit) \ 410 do { \ 411 el = ((el) | ((uint64_t)0x1 << (bit))); \ 412 } while (0) 413 414 #define __BIT_VEC64_CLEAR_BIT(el, bit) \ 415 do { \ 416 el = ((el) & (~((uint64_t)0x1 << (bit)))); \ 417 } while (0) 418 419 #define BIT_VEC64_SET_BIT(vec64, idx) \ 420 __BIT_VEC64_SET_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \ 421 (idx) & BIT_VEC64_ELEM_MASK) 422 423 #define BIT_VEC64_CLEAR_BIT(vec64, idx) \ 424 __BIT_VEC64_CLEAR_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \ 425 (idx) & BIT_VEC64_ELEM_MASK) 426 427 #define BIT_VEC64_TEST_BIT(vec64, idx) \ 428 (((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT] >> \ 429 ((idx) & BIT_VEC64_ELEM_MASK)) & 0x1) 430 431 /* 432 * Creates a bitmask of all ones in less significant bits. 433 * idx - index of the most significant bit in the created mask 434 */ 435 #define BIT_VEC64_ONES_MASK(idx) \ 436 (((uint64_t)0x1 << (((idx) & BIT_VEC64_ELEM_MASK) + 1)) - 1) 437 #define BIT_VEC64_ELEM_ONE_MASK ((uint64_t)(~0)) 438 439 /* fill in a MAC address the way the FW likes it */ 440 static inline void 441 ecore_set_fw_mac_addr(uint16_t *fw_hi, 442 uint16_t *fw_mid, 443 uint16_t *fw_lo, 444 uint8_t *mac) 445 { 446 ((uint8_t *)fw_hi)[0] = mac[1]; 447 ((uint8_t *)fw_hi)[1] = mac[0]; 448 ((uint8_t *)fw_mid)[0] = mac[3]; 449 ((uint8_t *)fw_mid)[1] = mac[2]; 450 ((uint8_t *)fw_lo)[0] = mac[5]; 451 ((uint8_t *)fw_lo)[1] = mac[4]; 452 } 453 454 455 enum ecore_status_t { 456 ECORE_EXISTS = -6, 457 ECORE_IO = -5, 458 ECORE_TIMEOUT = -4, 459 ECORE_INVAL = -3, 460 ECORE_BUSY = -2, 461 ECORE_NOMEM = -1, 462 ECORE_SUCCESS = 0, 463 /* PENDING is not an error and should be positive */ 464 ECORE_PENDING = 1, 465 }; 466 467 enum { 468 SWITCH_UPDATE, 469 AFEX_UPDATE, 470 }; 471 472 473 474 475 struct bxe_softc; 476 struct eth_context; 477 478 /* Bits representing general command's configuration */ 479 enum { 480 RAMROD_TX, 481 RAMROD_RX, 482 /* Wait until all pending commands complete */ 483 RAMROD_COMP_WAIT, 484 /* Don't send a ramrod, only update a registry */ 485 RAMROD_DRV_CLR_ONLY, 486 /* Configure HW according to the current object state */ 487 RAMROD_RESTORE, 488 /* Execute the next command now */ 489 RAMROD_EXEC, 490 /* Don't add a new command and continue execution of posponed 491 * commands. If not set a new command will be added to the 492 * pending commands list. 493 */ 494 RAMROD_CONT, 495 /* If there is another pending ramrod, wait until it finishes and 496 * re-try to submit this one. This flag can be set only in sleepable 497 * context, and should not be set from the context that completes the 498 * ramrods as deadlock will occur. 499 */ 500 RAMROD_RETRY, 501 }; 502 503 typedef enum { 504 ECORE_OBJ_TYPE_RX, 505 ECORE_OBJ_TYPE_TX, 506 ECORE_OBJ_TYPE_RX_TX, 507 } ecore_obj_type; 508 509 /* Public slow path states */ 510 enum { 511 ECORE_FILTER_MAC_PENDING, 512 ECORE_FILTER_VLAN_PENDING, 513 ECORE_FILTER_VLAN_MAC_PENDING, 514 ECORE_FILTER_RX_MODE_PENDING, 515 ECORE_FILTER_RX_MODE_SCHED, 516 ECORE_FILTER_ISCSI_ETH_START_SCHED, 517 ECORE_FILTER_ISCSI_ETH_STOP_SCHED, 518 ECORE_FILTER_FCOE_ETH_START_SCHED, 519 ECORE_FILTER_FCOE_ETH_STOP_SCHED, 520 ECORE_FILTER_BYPASS_RX_MODE_PENDING, 521 ECORE_FILTER_BYPASS_MAC_PENDING, 522 ECORE_FILTER_BYPASS_RSS_CONF_PENDING, 523 ECORE_FILTER_MCAST_PENDING, 524 ECORE_FILTER_MCAST_SCHED, 525 ECORE_FILTER_RSS_CONF_PENDING, 526 ECORE_AFEX_FCOE_Q_UPDATE_PENDING, 527 ECORE_AFEX_PENDING_VIFSET_MCP_ACK, 528 ECORE_FILTER_VXLAN_PENDING 529 }; 530 531 struct ecore_raw_obj { 532 uint8_t func_id; 533 534 /* Queue params */ 535 uint8_t cl_id; 536 uint32_t cid; 537 538 /* Ramrod data buffer params */ 539 void *rdata; 540 ecore_dma_addr_t rdata_mapping; 541 542 /* Ramrod state params */ 543 int state; /* "ramrod is pending" state bit */ 544 unsigned long *pstate; /* pointer to state buffer */ 545 546 ecore_obj_type obj_type; 547 548 int (*wait_comp)(struct bxe_softc *sc, 549 struct ecore_raw_obj *o); 550 551 bool (*check_pending)(struct ecore_raw_obj *o); 552 void (*clear_pending)(struct ecore_raw_obj *o); 553 void (*set_pending)(struct ecore_raw_obj *o); 554 }; 555 556 /************************* VLAN-MAC commands related parameters ***************/ 557 struct ecore_mac_ramrod_data { 558 uint8_t mac[ETH_ALEN]; 559 uint8_t is_inner_mac; 560 }; 561 562 struct ecore_vlan_ramrod_data { 563 uint16_t vlan; 564 }; 565 566 struct ecore_vlan_mac_ramrod_data { 567 uint8_t mac[ETH_ALEN]; 568 uint8_t is_inner_mac; 569 uint16_t vlan; 570 }; 571 572 struct ecore_vxlan_fltr_ramrod_data { 573 uint8_t innermac[ETH_ALEN]; 574 uint32_t vni; 575 }; 576 577 union ecore_classification_ramrod_data { 578 struct ecore_mac_ramrod_data mac; 579 struct ecore_vlan_ramrod_data vlan; 580 struct ecore_vlan_mac_ramrod_data vlan_mac; 581 struct ecore_vxlan_fltr_ramrod_data vxlan_fltr; 582 }; 583 584 /* VLAN_MAC commands */ 585 enum ecore_vlan_mac_cmd { 586 ECORE_VLAN_MAC_ADD, 587 ECORE_VLAN_MAC_DEL, 588 ECORE_VLAN_MAC_MOVE, 589 }; 590 591 struct ecore_vlan_mac_data { 592 /* Requested command: ECORE_VLAN_MAC_XX */ 593 enum ecore_vlan_mac_cmd cmd; 594 /* used to contain the data related vlan_mac_flags bits from 595 * ramrod parameters. 596 */ 597 unsigned long vlan_mac_flags; 598 599 /* Needed for MOVE command */ 600 struct ecore_vlan_mac_obj *target_obj; 601 602 union ecore_classification_ramrod_data u; 603 }; 604 605 /*************************** Exe Queue obj ************************************/ 606 union ecore_exe_queue_cmd_data { 607 struct ecore_vlan_mac_data vlan_mac; 608 609 struct { 610 /* TODO */ 611 } mcast; 612 }; 613 614 struct ecore_exeq_elem { 615 ecore_list_entry_t link; 616 617 /* Length of this element in the exe_chunk. */ 618 int cmd_len; 619 620 union ecore_exe_queue_cmd_data cmd_data; 621 }; 622 623 union ecore_qable_obj; 624 625 union ecore_exeq_comp_elem { 626 union event_ring_elem *elem; 627 }; 628 629 struct ecore_exe_queue_obj; 630 631 typedef int (*exe_q_validate)(struct bxe_softc *sc, 632 union ecore_qable_obj *o, 633 struct ecore_exeq_elem *elem); 634 635 typedef int (*exe_q_remove)(struct bxe_softc *sc, 636 union ecore_qable_obj *o, 637 struct ecore_exeq_elem *elem); 638 639 /* Return positive if entry was optimized, 0 - if not, negative 640 * in case of an error. 641 */ 642 typedef int (*exe_q_optimize)(struct bxe_softc *sc, 643 union ecore_qable_obj *o, 644 struct ecore_exeq_elem *elem); 645 typedef int (*exe_q_execute)(struct bxe_softc *sc, 646 union ecore_qable_obj *o, 647 ecore_list_t *exe_chunk, 648 unsigned long *ramrod_flags); 649 typedef struct ecore_exeq_elem * 650 (*exe_q_get)(struct ecore_exe_queue_obj *o, 651 struct ecore_exeq_elem *elem); 652 653 struct ecore_exe_queue_obj { 654 /* Commands pending for an execution. */ 655 ecore_list_t exe_queue; 656 657 /* Commands pending for an completion. */ 658 ecore_list_t pending_comp; 659 660 ECORE_MUTEX_SPIN lock; 661 662 /* Maximum length of commands' list for one execution */ 663 int exe_chunk_len; 664 665 union ecore_qable_obj *owner; 666 667 /****** Virtual functions ******/ 668 /** 669 * Called before commands execution for commands that are really 670 * going to be executed (after 'optimize'). 671 * 672 * Must run under exe_queue->lock 673 */ 674 exe_q_validate validate; 675 676 /** 677 * Called before removing pending commands, cleaning allocated 678 * resources (e.g., credits from validate) 679 */ 680 exe_q_remove remove; 681 682 /** 683 * This will try to cancel the current pending commands list 684 * considering the new command. 685 * 686 * Returns the number of optimized commands or a negative error code 687 * 688 * Must run under exe_queue->lock 689 */ 690 exe_q_optimize optimize; 691 692 /** 693 * Run the next commands chunk (owner specific). 694 */ 695 exe_q_execute execute; 696 697 /** 698 * Return the exe_queue element containing the specific command 699 * if any. Otherwise return NULL. 700 */ 701 exe_q_get get; 702 }; 703 /***************** Classification verbs: Set/Del MAC/VLAN/VLAN-MAC ************/ 704 /* 705 * Element in the VLAN_MAC registry list having all current configured 706 * rules. 707 */ 708 struct ecore_vlan_mac_registry_elem { 709 ecore_list_entry_t link; 710 711 /* Used to store the cam offset used for the mac/vlan/vlan-mac. 712 * Relevant for 57710 and 57711 only. VLANs and MACs share the 713 * same CAM for these chips. 714 */ 715 int cam_offset; 716 717 /* Needed for DEL and RESTORE flows */ 718 unsigned long vlan_mac_flags; 719 720 union ecore_classification_ramrod_data u; 721 }; 722 723 /* Bits representing VLAN_MAC commands specific flags */ 724 enum { 725 ECORE_UC_LIST_MAC, 726 ECORE_ETH_MAC, 727 ECORE_ISCSI_ETH_MAC, 728 ECORE_NETQ_ETH_MAC, 729 ECORE_DONT_CONSUME_CAM_CREDIT, 730 ECORE_DONT_CONSUME_CAM_CREDIT_DEST, 731 }; 732 /* When looking for matching filters, some flags are not interesting */ 733 #define ECORE_VLAN_MAC_CMP_MASK (1 << ECORE_UC_LIST_MAC | \ 734 1 << ECORE_ETH_MAC | \ 735 1 << ECORE_ISCSI_ETH_MAC | \ 736 1 << ECORE_NETQ_ETH_MAC) 737 #define ECORE_VLAN_MAC_CMP_FLAGS(flags) \ 738 ((flags) & ECORE_VLAN_MAC_CMP_MASK) 739 740 struct ecore_vlan_mac_ramrod_params { 741 /* Object to run the command from */ 742 struct ecore_vlan_mac_obj *vlan_mac_obj; 743 744 /* General command flags: COMP_WAIT, etc. */ 745 unsigned long ramrod_flags; 746 747 /* Command specific configuration request */ 748 struct ecore_vlan_mac_data user_req; 749 }; 750 751 struct ecore_vlan_mac_obj { 752 struct ecore_raw_obj raw; 753 754 /* Bookkeeping list: will prevent the addition of already existing 755 * entries. 756 */ 757 ecore_list_t head; 758 /* Implement a simple reader/writer lock on the head list. 759 * all these fields should only be accessed under the exe_queue lock 760 */ 761 uint8_t head_reader; /* Num. of readers accessing head list */ 762 bool head_exe_request; /* Pending execution request. */ 763 unsigned long saved_ramrod_flags; /* Ramrods of pending execution */ 764 765 /* Execution queue interface instance */ 766 struct ecore_exe_queue_obj exe_queue; 767 768 /* MACs credit pool */ 769 struct ecore_credit_pool_obj *macs_pool; 770 771 /* VLANs credit pool */ 772 struct ecore_credit_pool_obj *vlans_pool; 773 774 /* RAMROD command to be used */ 775 int ramrod_cmd; 776 777 /* copy first n elements onto preallocated buffer 778 * 779 * @param n number of elements to get 780 * @param buf buffer preallocated by caller into which elements 781 * will be copied. Note elements are 4-byte aligned 782 * so buffer size must be able to accommodate the 783 * aligned elements. 784 * 785 * @return number of copied bytes 786 */ 787 788 int (*get_n_elements)(struct bxe_softc *sc, 789 struct ecore_vlan_mac_obj *o, int n, uint8_t *base, 790 uint8_t stride, uint8_t size); 791 792 /** 793 * Checks if ADD-ramrod with the given params may be performed. 794 * 795 * @return zero if the element may be added 796 */ 797 798 int (*check_add)(struct bxe_softc *sc, 799 struct ecore_vlan_mac_obj *o, 800 union ecore_classification_ramrod_data *data); 801 802 /** 803 * Checks if DEL-ramrod with the given params may be performed. 804 * 805 * @return TRUE if the element may be deleted 806 */ 807 struct ecore_vlan_mac_registry_elem * 808 (*check_del)(struct bxe_softc *sc, 809 struct ecore_vlan_mac_obj *o, 810 union ecore_classification_ramrod_data *data); 811 812 /** 813 * Checks if DEL-ramrod with the given params may be performed. 814 * 815 * @return TRUE if the element may be deleted 816 */ 817 bool (*check_move)(struct bxe_softc *sc, 818 struct ecore_vlan_mac_obj *src_o, 819 struct ecore_vlan_mac_obj *dst_o, 820 union ecore_classification_ramrod_data *data); 821 822 /** 823 * Update the relevant credit object(s) (consume/return 824 * correspondingly). 825 */ 826 bool (*get_credit)(struct ecore_vlan_mac_obj *o); 827 bool (*put_credit)(struct ecore_vlan_mac_obj *o); 828 bool (*get_cam_offset)(struct ecore_vlan_mac_obj *o, int *offset); 829 bool (*put_cam_offset)(struct ecore_vlan_mac_obj *o, int offset); 830 831 /** 832 * Configures one rule in the ramrod data buffer. 833 */ 834 void (*set_one_rule)(struct bxe_softc *sc, 835 struct ecore_vlan_mac_obj *o, 836 struct ecore_exeq_elem *elem, int rule_idx, 837 int cam_offset); 838 839 /** 840 * Delete all configured elements having the given 841 * vlan_mac_flags specification. Assumes no pending for 842 * execution commands. Will schedule all all currently 843 * configured MACs/VLANs/VLAN-MACs matching the vlan_mac_flags 844 * specification for deletion and will use the given 845 * ramrod_flags for the last DEL operation. 846 * 847 * @param sc 848 * @param o 849 * @param ramrod_flags RAMROD_XX flags 850 * 851 * @return 0 if the last operation has completed successfully 852 * and there are no more elements left, positive value 853 * if there are pending for completion commands, 854 * negative value in case of failure. 855 */ 856 int (*delete_all)(struct bxe_softc *sc, 857 struct ecore_vlan_mac_obj *o, 858 unsigned long *vlan_mac_flags, 859 unsigned long *ramrod_flags); 860 861 /** 862 * Reconfigures the next MAC/VLAN/VLAN-MAC element from the previously 863 * configured elements list. 864 * 865 * @param sc 866 * @param p Command parameters (RAMROD_COMP_WAIT bit in 867 * ramrod_flags is only taken into an account) 868 * @param ppos a pointer to the cookie that should be given back in the 869 * next call to make function handle the next element. If 870 * *ppos is set to NULL it will restart the iterator. 871 * If returned *ppos == NULL this means that the last 872 * element has been handled. 873 * 874 * @return int 875 */ 876 int (*restore)(struct bxe_softc *sc, 877 struct ecore_vlan_mac_ramrod_params *p, 878 struct ecore_vlan_mac_registry_elem **ppos); 879 880 /** 881 * Should be called on a completion arrival. 882 * 883 * @param sc 884 * @param o 885 * @param cqe Completion element we are handling 886 * @param ramrod_flags if RAMROD_CONT is set the next bulk of 887 * pending commands will be executed. 888 * RAMROD_DRV_CLR_ONLY and RAMROD_RESTORE 889 * may also be set if needed. 890 * 891 * @return 0 if there are neither pending nor waiting for 892 * completion commands. Positive value if there are 893 * pending for execution or for completion commands. 894 * Negative value in case of an error (including an 895 * error in the cqe). 896 */ 897 int (*complete)(struct bxe_softc *sc, struct ecore_vlan_mac_obj *o, 898 union event_ring_elem *cqe, 899 unsigned long *ramrod_flags); 900 901 /** 902 * Wait for completion of all commands. Don't schedule new ones, 903 * just wait. It assumes that the completion code will schedule 904 * for new commands. 905 */ 906 int (*wait)(struct bxe_softc *sc, struct ecore_vlan_mac_obj *o); 907 }; 908 909 enum { 910 ECORE_LLH_CAM_ISCSI_ETH_LINE = 0, 911 ECORE_LLH_CAM_ETH_LINE, 912 ECORE_LLH_CAM_MAX_PF_LINE = NIG_REG_LLH1_FUNC_MEM_SIZE / 2 913 }; 914 915 void ecore_set_mac_in_nig(struct bxe_softc *sc, 916 bool add, unsigned char *dev_addr, int index); 917 918 /** RX_MODE verbs:DROP_ALL/ACCEPT_ALL/ACCEPT_ALL_MULTI/ACCEPT_ALL_VLAN/NORMAL */ 919 920 /* RX_MODE ramrod special flags: set in rx_mode_flags field in 921 * a ecore_rx_mode_ramrod_params. 922 */ 923 enum { 924 ECORE_RX_MODE_FCOE_ETH, 925 ECORE_RX_MODE_ISCSI_ETH, 926 }; 927 928 enum { 929 ECORE_ACCEPT_UNICAST, 930 ECORE_ACCEPT_MULTICAST, 931 ECORE_ACCEPT_ALL_UNICAST, 932 ECORE_ACCEPT_ALL_MULTICAST, 933 ECORE_ACCEPT_BROADCAST, 934 ECORE_ACCEPT_UNMATCHED, 935 ECORE_ACCEPT_ANY_VLAN 936 }; 937 938 struct ecore_rx_mode_ramrod_params { 939 struct ecore_rx_mode_obj *rx_mode_obj; 940 unsigned long *pstate; 941 int state; 942 uint8_t cl_id; 943 uint32_t cid; 944 uint8_t func_id; 945 unsigned long ramrod_flags; 946 unsigned long rx_mode_flags; 947 948 /* rdata is either a pointer to eth_filter_rules_ramrod_data(e2) or to 949 * a tstorm_eth_mac_filter_config (e1x). 950 */ 951 void *rdata; 952 ecore_dma_addr_t rdata_mapping; 953 954 /* Rx mode settings */ 955 unsigned long rx_accept_flags; 956 957 /* internal switching settings */ 958 unsigned long tx_accept_flags; 959 }; 960 961 struct ecore_rx_mode_obj { 962 int (*config_rx_mode)(struct bxe_softc *sc, 963 struct ecore_rx_mode_ramrod_params *p); 964 965 int (*wait_comp)(struct bxe_softc *sc, 966 struct ecore_rx_mode_ramrod_params *p); 967 }; 968 969 /********************** Set multicast group ***********************************/ 970 971 struct ecore_mcast_list_elem { 972 ecore_list_entry_t link; 973 uint8_t *mac; 974 }; 975 976 union ecore_mcast_config_data { 977 uint8_t *mac; 978 uint8_t bin; /* used in a RESTORE flow */ 979 }; 980 981 struct ecore_mcast_ramrod_params { 982 struct ecore_mcast_obj *mcast_obj; 983 984 /* Relevant options are RAMROD_COMP_WAIT and RAMROD_DRV_CLR_ONLY */ 985 unsigned long ramrod_flags; 986 987 ecore_list_t mcast_list; /* list of struct ecore_mcast_list_elem */ 988 /** TODO: 989 * - rename it to macs_num. 990 * - Add a new command type for handling pending commands 991 * (remove "zero semantics"). 992 * 993 * Length of mcast_list. If zero and ADD_CONT command - post 994 * pending commands. 995 */ 996 int mcast_list_len; 997 }; 998 999 enum ecore_mcast_cmd { 1000 ECORE_MCAST_CMD_ADD, 1001 ECORE_MCAST_CMD_CONT, 1002 ECORE_MCAST_CMD_DEL, 1003 ECORE_MCAST_CMD_RESTORE, 1004 }; 1005 1006 struct ecore_mcast_obj { 1007 struct ecore_raw_obj raw; 1008 1009 union { 1010 struct { 1011 #define ECORE_MCAST_BINS_NUM 256 1012 #define ECORE_MCAST_VEC_SZ (ECORE_MCAST_BINS_NUM / 64) 1013 uint64_t vec[ECORE_MCAST_VEC_SZ]; 1014 1015 /** Number of BINs to clear. Should be updated 1016 * immediately when a command arrives in order to 1017 * properly create DEL commands. 1018 */ 1019 int num_bins_set; 1020 } aprox_match; 1021 1022 struct { 1023 ecore_list_t macs; 1024 int num_macs_set; 1025 } exact_match; 1026 } registry; 1027 1028 /* Pending commands */ 1029 ecore_list_t pending_cmds_head; 1030 1031 /* A state that is set in raw.pstate, when there are pending commands */ 1032 int sched_state; 1033 1034 /* Maximal number of mcast MACs configured in one command */ 1035 int max_cmd_len; 1036 1037 /* Total number of currently pending MACs to configure: both 1038 * in the pending commands list and in the current command. 1039 */ 1040 int total_pending_num; 1041 1042 uint8_t engine_id; 1043 1044 /** 1045 * @param cmd command to execute (ECORE_MCAST_CMD_X, see above) 1046 */ 1047 int (*config_mcast)(struct bxe_softc *sc, 1048 struct ecore_mcast_ramrod_params *p, 1049 enum ecore_mcast_cmd cmd); 1050 1051 /** 1052 * Fills the ramrod data during the RESTORE flow. 1053 * 1054 * @param sc 1055 * @param o 1056 * @param start_idx Registry index to start from 1057 * @param rdata_idx Index in the ramrod data to start from 1058 * 1059 * @return -1 if we handled the whole registry or index of the last 1060 * handled registry element. 1061 */ 1062 int (*hdl_restore)(struct bxe_softc *sc, struct ecore_mcast_obj *o, 1063 int start_bin, int *rdata_idx); 1064 1065 int (*enqueue_cmd)(struct bxe_softc *sc, struct ecore_mcast_obj *o, 1066 struct ecore_mcast_ramrod_params *p, 1067 enum ecore_mcast_cmd cmd); 1068 1069 void (*set_one_rule)(struct bxe_softc *sc, 1070 struct ecore_mcast_obj *o, int idx, 1071 union ecore_mcast_config_data *cfg_data, 1072 enum ecore_mcast_cmd cmd); 1073 1074 /** Checks if there are more mcast MACs to be set or a previous 1075 * command is still pending. 1076 */ 1077 bool (*check_pending)(struct ecore_mcast_obj *o); 1078 1079 /** 1080 * Set/Clear/Check SCHEDULED state of the object 1081 */ 1082 void (*set_sched)(struct ecore_mcast_obj *o); 1083 void (*clear_sched)(struct ecore_mcast_obj *o); 1084 bool (*check_sched)(struct ecore_mcast_obj *o); 1085 1086 /* Wait until all pending commands complete */ 1087 int (*wait_comp)(struct bxe_softc *sc, struct ecore_mcast_obj *o); 1088 1089 /** 1090 * Handle the internal object counters needed for proper 1091 * commands handling. Checks that the provided parameters are 1092 * feasible. 1093 */ 1094 int (*validate)(struct bxe_softc *sc, 1095 struct ecore_mcast_ramrod_params *p, 1096 enum ecore_mcast_cmd cmd); 1097 1098 /** 1099 * Restore the values of internal counters in case of a failure. 1100 */ 1101 void (*revert)(struct bxe_softc *sc, 1102 struct ecore_mcast_ramrod_params *p, 1103 int old_num_bins); 1104 1105 int (*get_registry_size)(struct ecore_mcast_obj *o); 1106 void (*set_registry_size)(struct ecore_mcast_obj *o, int n); 1107 }; 1108 1109 /*************************** Credit handling **********************************/ 1110 struct ecore_credit_pool_obj { 1111 1112 /* Current amount of credit in the pool */ 1113 ecore_atomic_t credit; 1114 1115 /* Maximum allowed credit. put() will check against it. */ 1116 int pool_sz; 1117 1118 /* Allocate a pool table statically. 1119 * 1120 * Currently the maximum allowed size is MAX_MAC_CREDIT_E2(272) 1121 * 1122 * The set bit in the table will mean that the entry is available. 1123 */ 1124 #define ECORE_POOL_VEC_SIZE (MAX_MAC_CREDIT_E2 / 64) 1125 uint64_t pool_mirror[ECORE_POOL_VEC_SIZE]; 1126 1127 /* Base pool offset (initialized differently */ 1128 int base_pool_offset; 1129 1130 /** 1131 * Get the next free pool entry. 1132 * 1133 * @return TRUE if there was a free entry in the pool 1134 */ 1135 bool (*get_entry)(struct ecore_credit_pool_obj *o, int *entry); 1136 1137 /** 1138 * Return the entry back to the pool. 1139 * 1140 * @return TRUE if entry is legal and has been successfully 1141 * returned to the pool. 1142 */ 1143 bool (*put_entry)(struct ecore_credit_pool_obj *o, int entry); 1144 1145 /** 1146 * Get the requested amount of credit from the pool. 1147 * 1148 * @param cnt Amount of requested credit 1149 * @return TRUE if the operation is successful 1150 */ 1151 bool (*get)(struct ecore_credit_pool_obj *o, int cnt); 1152 1153 /** 1154 * Returns the credit to the pool. 1155 * 1156 * @param cnt Amount of credit to return 1157 * @return TRUE if the operation is successful 1158 */ 1159 bool (*put)(struct ecore_credit_pool_obj *o, int cnt); 1160 1161 /** 1162 * Reads the current amount of credit. 1163 */ 1164 int (*check)(struct ecore_credit_pool_obj *o); 1165 }; 1166 1167 /*************************** RSS configuration ********************************/ 1168 enum { 1169 /* RSS_MODE bits are mutually exclusive */ 1170 ECORE_RSS_MODE_DISABLED, 1171 ECORE_RSS_MODE_REGULAR, 1172 1173 ECORE_RSS_SET_SRCH, /* Setup searcher, E1x specific flag */ 1174 1175 ECORE_RSS_IPV4, 1176 ECORE_RSS_IPV4_TCP, 1177 ECORE_RSS_IPV4_UDP, 1178 ECORE_RSS_IPV6, 1179 ECORE_RSS_IPV6_TCP, 1180 ECORE_RSS_IPV6_UDP, 1181 1182 ECORE_RSS_IPV4_VXLAN, 1183 ECORE_RSS_IPV6_VXLAN, 1184 ECORE_RSS_TUNN_INNER_HDRS, 1185 }; 1186 1187 struct ecore_config_rss_params { 1188 struct ecore_rss_config_obj *rss_obj; 1189 1190 /* may have RAMROD_COMP_WAIT set only */ 1191 unsigned long ramrod_flags; 1192 1193 /* ECORE_RSS_X bits */ 1194 unsigned long rss_flags; 1195 1196 /* Number hash bits to take into an account */ 1197 uint8_t rss_result_mask; 1198 1199 /* Indirection table */ 1200 uint8_t ind_table[T_ETH_INDIRECTION_TABLE_SIZE]; 1201 1202 /* RSS hash values */ 1203 uint32_t rss_key[10]; 1204 1205 /* valid only iff ECORE_RSS_UPDATE_TOE is set */ 1206 uint16_t toe_rss_bitmap; 1207 }; 1208 1209 struct ecore_rss_config_obj { 1210 struct ecore_raw_obj raw; 1211 1212 /* RSS engine to use */ 1213 uint8_t engine_id; 1214 1215 /* Last configured indirection table */ 1216 uint8_t ind_table[T_ETH_INDIRECTION_TABLE_SIZE]; 1217 1218 /* flags for enabling 4-tupple hash on UDP */ 1219 uint8_t udp_rss_v4; 1220 uint8_t udp_rss_v6; 1221 1222 int (*config_rss)(struct bxe_softc *sc, 1223 struct ecore_config_rss_params *p); 1224 }; 1225 1226 /*********************** Queue state update ***********************************/ 1227 1228 /* UPDATE command options */ 1229 enum { 1230 ECORE_Q_UPDATE_IN_VLAN_REM, 1231 ECORE_Q_UPDATE_IN_VLAN_REM_CHNG, 1232 ECORE_Q_UPDATE_OUT_VLAN_REM, 1233 ECORE_Q_UPDATE_OUT_VLAN_REM_CHNG, 1234 ECORE_Q_UPDATE_ANTI_SPOOF, 1235 ECORE_Q_UPDATE_ANTI_SPOOF_CHNG, 1236 ECORE_Q_UPDATE_ACTIVATE, 1237 ECORE_Q_UPDATE_ACTIVATE_CHNG, 1238 ECORE_Q_UPDATE_DEF_VLAN_EN, 1239 ECORE_Q_UPDATE_DEF_VLAN_EN_CHNG, 1240 ECORE_Q_UPDATE_SILENT_VLAN_REM_CHNG, 1241 ECORE_Q_UPDATE_SILENT_VLAN_REM, 1242 ECORE_Q_UPDATE_TX_SWITCHING_CHNG, 1243 ECORE_Q_UPDATE_TX_SWITCHING, 1244 ECORE_Q_UPDATE_PTP_PKTS_CHNG, 1245 ECORE_Q_UPDATE_PTP_PKTS, 1246 }; 1247 1248 /* Allowed Queue states */ 1249 enum ecore_q_state { 1250 ECORE_Q_STATE_RESET, 1251 ECORE_Q_STATE_INITIALIZED, 1252 ECORE_Q_STATE_ACTIVE, 1253 ECORE_Q_STATE_MULTI_COS, 1254 ECORE_Q_STATE_MCOS_TERMINATED, 1255 ECORE_Q_STATE_INACTIVE, 1256 ECORE_Q_STATE_STOPPED, 1257 ECORE_Q_STATE_TERMINATED, 1258 ECORE_Q_STATE_FLRED, 1259 ECORE_Q_STATE_MAX, 1260 }; 1261 1262 /* Allowed Queue states */ 1263 enum ecore_q_logical_state { 1264 ECORE_Q_LOGICAL_STATE_ACTIVE, 1265 ECORE_Q_LOGICAL_STATE_STOPPED, 1266 }; 1267 1268 /* Allowed commands */ 1269 enum ecore_queue_cmd { 1270 ECORE_Q_CMD_INIT, 1271 ECORE_Q_CMD_SETUP, 1272 ECORE_Q_CMD_SETUP_TX_ONLY, 1273 ECORE_Q_CMD_DEACTIVATE, 1274 ECORE_Q_CMD_ACTIVATE, 1275 ECORE_Q_CMD_UPDATE, 1276 ECORE_Q_CMD_UPDATE_TPA, 1277 ECORE_Q_CMD_HALT, 1278 ECORE_Q_CMD_CFC_DEL, 1279 ECORE_Q_CMD_TERMINATE, 1280 ECORE_Q_CMD_EMPTY, 1281 ECORE_Q_CMD_MAX, 1282 }; 1283 1284 /* queue SETUP + INIT flags */ 1285 enum { 1286 ECORE_Q_FLG_TPA, 1287 ECORE_Q_FLG_TPA_IPV6, 1288 ECORE_Q_FLG_TPA_GRO, 1289 ECORE_Q_FLG_STATS, 1290 ECORE_Q_FLG_ZERO_STATS, 1291 ECORE_Q_FLG_ACTIVE, 1292 ECORE_Q_FLG_OV, 1293 ECORE_Q_FLG_VLAN, 1294 ECORE_Q_FLG_COS, 1295 ECORE_Q_FLG_HC, 1296 ECORE_Q_FLG_HC_EN, 1297 ECORE_Q_FLG_DHC, 1298 ECORE_Q_FLG_OOO, 1299 ECORE_Q_FLG_FCOE, 1300 ECORE_Q_FLG_LEADING_RSS, 1301 ECORE_Q_FLG_MCAST, 1302 ECORE_Q_FLG_DEF_VLAN, 1303 ECORE_Q_FLG_TX_SWITCH, 1304 ECORE_Q_FLG_TX_SEC, 1305 ECORE_Q_FLG_ANTI_SPOOF, 1306 ECORE_Q_FLG_SILENT_VLAN_REM, 1307 ECORE_Q_FLG_FORCE_DEFAULT_PRI, 1308 ECORE_Q_FLG_REFUSE_OUTBAND_VLAN, 1309 ECORE_Q_FLG_PCSUM_ON_PKT, 1310 ECORE_Q_FLG_TUN_INC_INNER_IP_ID 1311 }; 1312 1313 /* Queue type options: queue type may be a combination of below. */ 1314 enum ecore_q_type { 1315 ECORE_Q_TYPE_FWD, 1316 /** TODO: Consider moving both these flags into the init() 1317 * ramrod params. 1318 */ 1319 ECORE_Q_TYPE_HAS_RX, 1320 ECORE_Q_TYPE_HAS_TX, 1321 }; 1322 1323 #define ECORE_PRIMARY_CID_INDEX 0 1324 #define ECORE_MULTI_TX_COS_E1X 3 /* QM only */ 1325 #define ECORE_MULTI_TX_COS_E2_E3A0 2 1326 #define ECORE_MULTI_TX_COS_E3B0 3 1327 #define ECORE_MULTI_TX_COS 3 /* Maximum possible */ 1328 #define MAC_PAD (ECORE_ALIGN(ETH_ALEN, sizeof(uint32_t)) - ETH_ALEN) 1329 /* DMAE channel to be used by FW for timesync workaroun. A driver that sends 1330 * timesync-related ramrods must not use this DMAE command ID. 1331 */ 1332 #define FW_DMAE_CMD_ID 6 1333 1334 struct ecore_queue_init_params { 1335 struct { 1336 unsigned long flags; 1337 uint16_t hc_rate; 1338 uint8_t fw_sb_id; 1339 uint8_t sb_cq_index; 1340 } tx; 1341 1342 struct { 1343 unsigned long flags; 1344 uint16_t hc_rate; 1345 uint8_t fw_sb_id; 1346 uint8_t sb_cq_index; 1347 } rx; 1348 1349 /* CID context in the host memory */ 1350 struct eth_context *cxts[ECORE_MULTI_TX_COS]; 1351 1352 /* maximum number of cos supported by hardware */ 1353 uint8_t max_cos; 1354 }; 1355 1356 struct ecore_queue_terminate_params { 1357 /* index within the tx_only cids of this queue object */ 1358 uint8_t cid_index; 1359 }; 1360 1361 struct ecore_queue_cfc_del_params { 1362 /* index within the tx_only cids of this queue object */ 1363 uint8_t cid_index; 1364 }; 1365 1366 struct ecore_queue_update_params { 1367 unsigned long update_flags; /* ECORE_Q_UPDATE_XX bits */ 1368 uint16_t def_vlan; 1369 uint16_t silent_removal_value; 1370 uint16_t silent_removal_mask; 1371 /* index within the tx_only cids of this queue object */ 1372 uint8_t cid_index; 1373 }; 1374 1375 struct ecore_queue_update_tpa_params { 1376 ecore_dma_addr_t sge_map; 1377 uint8_t update_ipv4; 1378 uint8_t update_ipv6; 1379 uint8_t max_tpa_queues; 1380 uint8_t max_sges_pkt; 1381 uint8_t complete_on_both_clients; 1382 uint8_t dont_verify_thr; 1383 uint8_t tpa_mode; 1384 uint8_t _pad; 1385 1386 uint16_t sge_buff_sz; 1387 uint16_t max_agg_sz; 1388 1389 uint16_t sge_pause_thr_low; 1390 uint16_t sge_pause_thr_high; 1391 }; 1392 1393 struct rxq_pause_params { 1394 uint16_t bd_th_lo; 1395 uint16_t bd_th_hi; 1396 uint16_t rcq_th_lo; 1397 uint16_t rcq_th_hi; 1398 uint16_t sge_th_lo; /* valid iff ECORE_Q_FLG_TPA */ 1399 uint16_t sge_th_hi; /* valid iff ECORE_Q_FLG_TPA */ 1400 uint16_t pri_map; 1401 }; 1402 1403 /* general */ 1404 struct ecore_general_setup_params { 1405 /* valid iff ECORE_Q_FLG_STATS */ 1406 uint8_t stat_id; 1407 1408 uint8_t spcl_id; 1409 uint16_t mtu; 1410 uint8_t cos; 1411 1412 uint8_t fp_hsi; 1413 }; 1414 1415 struct ecore_rxq_setup_params { 1416 /* dma */ 1417 ecore_dma_addr_t dscr_map; 1418 ecore_dma_addr_t sge_map; 1419 ecore_dma_addr_t rcq_map; 1420 ecore_dma_addr_t rcq_np_map; 1421 1422 uint16_t drop_flags; 1423 uint16_t buf_sz; 1424 uint8_t fw_sb_id; 1425 uint8_t cl_qzone_id; 1426 1427 /* valid iff ECORE_Q_FLG_TPA */ 1428 uint16_t tpa_agg_sz; 1429 uint16_t sge_buf_sz; 1430 uint8_t max_sges_pkt; 1431 uint8_t max_tpa_queues; 1432 uint8_t rss_engine_id; 1433 1434 /* valid iff ECORE_Q_FLG_MCAST */ 1435 uint8_t mcast_engine_id; 1436 1437 uint8_t cache_line_log; 1438 1439 uint8_t sb_cq_index; 1440 1441 /* valid iff BXN2X_Q_FLG_SILENT_VLAN_REM */ 1442 uint16_t silent_removal_value; 1443 uint16_t silent_removal_mask; 1444 }; 1445 1446 struct ecore_txq_setup_params { 1447 /* dma */ 1448 ecore_dma_addr_t dscr_map; 1449 1450 uint8_t fw_sb_id; 1451 uint8_t sb_cq_index; 1452 uint8_t cos; /* valid iff ECORE_Q_FLG_COS */ 1453 uint16_t traffic_type; 1454 /* equals to the leading rss client id, used for TX classification*/ 1455 uint8_t tss_leading_cl_id; 1456 1457 /* valid iff ECORE_Q_FLG_DEF_VLAN */ 1458 uint16_t default_vlan; 1459 }; 1460 1461 struct ecore_queue_setup_params { 1462 struct ecore_general_setup_params gen_params; 1463 struct ecore_txq_setup_params txq_params; 1464 struct ecore_rxq_setup_params rxq_params; 1465 struct rxq_pause_params pause_params; 1466 unsigned long flags; 1467 }; 1468 1469 struct ecore_queue_setup_tx_only_params { 1470 struct ecore_general_setup_params gen_params; 1471 struct ecore_txq_setup_params txq_params; 1472 unsigned long flags; 1473 /* index within the tx_only cids of this queue object */ 1474 uint8_t cid_index; 1475 }; 1476 1477 struct ecore_queue_state_params { 1478 struct ecore_queue_sp_obj *q_obj; 1479 1480 /* Current command */ 1481 enum ecore_queue_cmd cmd; 1482 1483 /* may have RAMROD_COMP_WAIT set only */ 1484 unsigned long ramrod_flags; 1485 1486 /* Params according to the current command */ 1487 union { 1488 struct ecore_queue_update_params update; 1489 struct ecore_queue_update_tpa_params update_tpa; 1490 struct ecore_queue_setup_params setup; 1491 struct ecore_queue_init_params init; 1492 struct ecore_queue_setup_tx_only_params tx_only; 1493 struct ecore_queue_terminate_params terminate; 1494 struct ecore_queue_cfc_del_params cfc_del; 1495 } params; 1496 }; 1497 1498 struct ecore_viflist_params { 1499 uint8_t echo_res; 1500 uint8_t func_bit_map_res; 1501 }; 1502 1503 struct ecore_queue_sp_obj { 1504 uint32_t cids[ECORE_MULTI_TX_COS]; 1505 uint8_t cl_id; 1506 uint8_t func_id; 1507 1508 /* number of traffic classes supported by queue. 1509 * The primary connection of the queue supports the first traffic 1510 * class. Any further traffic class is supported by a tx-only 1511 * connection. 1512 * 1513 * Therefore max_cos is also a number of valid entries in the cids 1514 * array. 1515 */ 1516 uint8_t max_cos; 1517 uint8_t num_tx_only, next_tx_only; 1518 1519 enum ecore_q_state state, next_state; 1520 1521 /* bits from enum ecore_q_type */ 1522 unsigned long type; 1523 1524 /* ECORE_Q_CMD_XX bits. This object implements "one 1525 * pending" paradigm but for debug and tracing purposes it's 1526 * more convenient to have different bits for different 1527 * commands. 1528 */ 1529 unsigned long pending; 1530 1531 /* Buffer to use as a ramrod data and its mapping */ 1532 void *rdata; 1533 ecore_dma_addr_t rdata_mapping; 1534 1535 /** 1536 * Performs one state change according to the given parameters. 1537 * 1538 * @return 0 in case of success and negative value otherwise. 1539 */ 1540 int (*send_cmd)(struct bxe_softc *sc, 1541 struct ecore_queue_state_params *params); 1542 1543 /** 1544 * Sets the pending bit according to the requested transition. 1545 */ 1546 int (*set_pending)(struct ecore_queue_sp_obj *o, 1547 struct ecore_queue_state_params *params); 1548 1549 /** 1550 * Checks that the requested state transition is legal. 1551 */ 1552 int (*check_transition)(struct bxe_softc *sc, 1553 struct ecore_queue_sp_obj *o, 1554 struct ecore_queue_state_params *params); 1555 1556 /** 1557 * Completes the pending command. 1558 */ 1559 int (*complete_cmd)(struct bxe_softc *sc, 1560 struct ecore_queue_sp_obj *o, 1561 enum ecore_queue_cmd); 1562 1563 int (*wait_comp)(struct bxe_softc *sc, 1564 struct ecore_queue_sp_obj *o, 1565 enum ecore_queue_cmd cmd); 1566 }; 1567 1568 /********************** Function state update *********************************/ 1569 1570 /* UPDATE command options */ 1571 enum { 1572 ECORE_F_UPDATE_TX_SWITCH_SUSPEND_CHNG, 1573 ECORE_F_UPDATE_TX_SWITCH_SUSPEND, 1574 ECORE_F_UPDATE_SD_VLAN_TAG_CHNG, 1575 ECORE_F_UPDATE_SD_VLAN_ETH_TYPE_CHNG, 1576 ECORE_F_UPDATE_VLAN_FORCE_PRIO_CHNG, 1577 ECORE_F_UPDATE_VLAN_FORCE_PRIO_FLAG, 1578 ECORE_F_UPDATE_TUNNEL_CFG_CHNG, 1579 ECORE_F_UPDATE_TUNNEL_INNER_CLSS_L2GRE, 1580 ECORE_F_UPDATE_TUNNEL_INNER_CLSS_VXLAN, 1581 ECORE_F_UPDATE_TUNNEL_INNER_CLSS_L2GENEVE, 1582 ECORE_F_UPDATE_TUNNEL_INNER_RSS, 1583 }; 1584 1585 /* Allowed Function states */ 1586 enum ecore_func_state { 1587 ECORE_F_STATE_RESET, 1588 ECORE_F_STATE_INITIALIZED, 1589 ECORE_F_STATE_STARTED, 1590 ECORE_F_STATE_TX_STOPPED, 1591 ECORE_F_STATE_MAX, 1592 }; 1593 1594 /* Allowed Function commands */ 1595 enum ecore_func_cmd { 1596 ECORE_F_CMD_HW_INIT, 1597 ECORE_F_CMD_START, 1598 ECORE_F_CMD_STOP, 1599 ECORE_F_CMD_HW_RESET, 1600 ECORE_F_CMD_AFEX_UPDATE, 1601 ECORE_F_CMD_AFEX_VIFLISTS, 1602 ECORE_F_CMD_TX_STOP, 1603 ECORE_F_CMD_TX_START, 1604 ECORE_F_CMD_SWITCH_UPDATE, 1605 ECORE_F_CMD_SET_TIMESYNC, 1606 ECORE_F_CMD_MAX, 1607 }; 1608 1609 struct ecore_func_hw_init_params { 1610 /* A load phase returned by MCP. 1611 * 1612 * May be: 1613 * FW_MSG_CODE_DRV_LOAD_COMMON_CHIP 1614 * FW_MSG_CODE_DRV_LOAD_COMMON 1615 * FW_MSG_CODE_DRV_LOAD_PORT 1616 * FW_MSG_CODE_DRV_LOAD_FUNCTION 1617 */ 1618 uint32_t load_phase; 1619 }; 1620 1621 struct ecore_func_hw_reset_params { 1622 /* A load phase returned by MCP. 1623 * 1624 * May be: 1625 * FW_MSG_CODE_DRV_LOAD_COMMON_CHIP 1626 * FW_MSG_CODE_DRV_LOAD_COMMON 1627 * FW_MSG_CODE_DRV_LOAD_PORT 1628 * FW_MSG_CODE_DRV_LOAD_FUNCTION 1629 */ 1630 uint32_t reset_phase; 1631 }; 1632 1633 struct ecore_func_start_params { 1634 /* Multi Function mode: 1635 * - Single Function 1636 * - Switch Dependent 1637 * - Switch Independent 1638 */ 1639 uint16_t mf_mode; 1640 1641 /* Switch Dependent mode outer VLAN tag */ 1642 uint16_t sd_vlan_tag; 1643 1644 /* Function cos mode */ 1645 uint8_t network_cos_mode; 1646 1647 /* UDP dest port for VXLAN */ 1648 uint16_t vxlan_dst_port; 1649 1650 /* UDP dest port for Geneve */ 1651 uint16_t geneve_dst_port; 1652 1653 /* Enable inner Rx classifications for L2GRE packets */ 1654 uint8_t inner_clss_l2gre; 1655 1656 /* Enable inner Rx classifications for L2-Geneve packets */ 1657 uint8_t inner_clss_l2geneve; 1658 1659 /* Enable inner Rx classification for vxlan packets */ 1660 uint8_t inner_clss_vxlan; 1661 1662 /* Enable RSS according to inner header */ 1663 uint8_t inner_rss; 1664 1665 /** Allows accepting of packets failing MF classification, possibly 1666 * only matching a given ethertype 1667 */ 1668 uint8_t class_fail; 1669 uint16_t class_fail_ethtype; 1670 1671 /* Override priority of output packets */ 1672 uint8_t sd_vlan_force_pri; 1673 uint8_t sd_vlan_force_pri_val; 1674 1675 /* Replace vlan's ethertype */ 1676 uint16_t sd_vlan_eth_type; 1677 1678 /* Prevent inner vlans from being added by FW */ 1679 uint8_t no_added_tags; 1680 1681 /* Inner-to-Outer vlan priority mapping */ 1682 uint8_t c2s_pri[MAX_VLAN_PRIORITIES]; 1683 uint8_t c2s_pri_default; 1684 uint8_t c2s_pri_valid; 1685 }; 1686 1687 struct ecore_func_switch_update_params { 1688 unsigned long changes; /* ECORE_F_UPDATE_XX bits */ 1689 uint16_t vlan; 1690 uint16_t vlan_eth_type; 1691 uint8_t vlan_force_prio; 1692 uint16_t vxlan_dst_port; 1693 uint16_t geneve_dst_port; 1694 }; 1695 1696 struct ecore_func_afex_update_params { 1697 uint16_t vif_id; 1698 uint16_t afex_default_vlan; 1699 uint8_t allowed_priorities; 1700 }; 1701 1702 struct ecore_func_afex_viflists_params { 1703 uint16_t vif_list_index; 1704 uint8_t func_bit_map; 1705 uint8_t afex_vif_list_command; 1706 uint8_t func_to_clear; 1707 }; 1708 1709 struct ecore_func_tx_start_params { 1710 struct priority_cos traffic_type_to_priority_cos[MAX_TRAFFIC_TYPES]; 1711 uint8_t dcb_enabled; 1712 uint8_t dcb_version; 1713 uint8_t dont_add_pri_0; 1714 uint8_t dcb_outer_pri[MAX_TRAFFIC_TYPES]; 1715 }; 1716 1717 struct ecore_func_set_timesync_params { 1718 /* Reset, set or keep the current drift value */ 1719 uint8_t drift_adjust_cmd; 1720 /* Dec, inc or keep the current offset */ 1721 uint8_t offset_cmd; 1722 /* Drift value direction */ 1723 uint8_t add_sub_drift_adjust_value; 1724 /* Drift, period and offset values to be used according to the commands 1725 * above. 1726 */ 1727 uint8_t drift_adjust_value; 1728 uint32_t drift_adjust_period; 1729 uint64_t offset_delta; 1730 }; 1731 1732 struct ecore_func_state_params { 1733 struct ecore_func_sp_obj *f_obj; 1734 1735 /* Current command */ 1736 enum ecore_func_cmd cmd; 1737 1738 /* may have RAMROD_COMP_WAIT set only */ 1739 unsigned long ramrod_flags; 1740 1741 /* Params according to the current command */ 1742 union { 1743 struct ecore_func_hw_init_params hw_init; 1744 struct ecore_func_hw_reset_params hw_reset; 1745 struct ecore_func_start_params start; 1746 struct ecore_func_switch_update_params switch_update; 1747 struct ecore_func_afex_update_params afex_update; 1748 struct ecore_func_afex_viflists_params afex_viflists; 1749 struct ecore_func_tx_start_params tx_start; 1750 struct ecore_func_set_timesync_params set_timesync; 1751 } params; 1752 }; 1753 1754 struct ecore_func_sp_drv_ops { 1755 /* Init tool + runtime initialization: 1756 * - Common Chip 1757 * - Common (per Path) 1758 * - Port 1759 * - Function phases 1760 */ 1761 int (*init_hw_cmn_chip)(struct bxe_softc *sc); 1762 int (*init_hw_cmn)(struct bxe_softc *sc); 1763 int (*init_hw_port)(struct bxe_softc *sc); 1764 int (*init_hw_func)(struct bxe_softc *sc); 1765 1766 /* Reset Function HW: Common, Port, Function phases. */ 1767 void (*reset_hw_cmn)(struct bxe_softc *sc); 1768 void (*reset_hw_port)(struct bxe_softc *sc); 1769 void (*reset_hw_func)(struct bxe_softc *sc); 1770 1771 /* Init/Free GUNZIP resources */ 1772 int (*gunzip_init)(struct bxe_softc *sc); 1773 void (*gunzip_end)(struct bxe_softc *sc); 1774 1775 /* Prepare/Release FW resources */ 1776 int (*init_fw)(struct bxe_softc *sc); 1777 void (*release_fw)(struct bxe_softc *sc); 1778 }; 1779 1780 struct ecore_func_sp_obj { 1781 enum ecore_func_state state, next_state; 1782 1783 /* ECORE_FUNC_CMD_XX bits. This object implements "one 1784 * pending" paradigm but for debug and tracing purposes it's 1785 * more convenient to have different bits for different 1786 * commands. 1787 */ 1788 unsigned long pending; 1789 1790 /* Buffer to use as a ramrod data and its mapping */ 1791 void *rdata; 1792 ecore_dma_addr_t rdata_mapping; 1793 1794 /* Buffer to use as a afex ramrod data and its mapping. 1795 * This can't be same rdata as above because afex ramrod requests 1796 * can arrive to the object in parallel to other ramrod requests. 1797 */ 1798 void *afex_rdata; 1799 ecore_dma_addr_t afex_rdata_mapping; 1800 1801 /* this mutex validates that when pending flag is taken, the next 1802 * ramrod to be sent will be the one set the pending bit 1803 */ 1804 ECORE_MUTEX one_pending_mutex; 1805 1806 /* Driver interface */ 1807 struct ecore_func_sp_drv_ops *drv; 1808 1809 /** 1810 * Performs one state change according to the given parameters. 1811 * 1812 * @return 0 in case of success and negative value otherwise. 1813 */ 1814 int (*send_cmd)(struct bxe_softc *sc, 1815 struct ecore_func_state_params *params); 1816 1817 /** 1818 * Checks that the requested state transition is legal. 1819 */ 1820 int (*check_transition)(struct bxe_softc *sc, 1821 struct ecore_func_sp_obj *o, 1822 struct ecore_func_state_params *params); 1823 1824 /** 1825 * Completes the pending command. 1826 */ 1827 int (*complete_cmd)(struct bxe_softc *sc, 1828 struct ecore_func_sp_obj *o, 1829 enum ecore_func_cmd cmd); 1830 1831 int (*wait_comp)(struct bxe_softc *sc, struct ecore_func_sp_obj *o, 1832 enum ecore_func_cmd cmd); 1833 }; 1834 1835 /********************** Interfaces ********************************************/ 1836 /* Queueable objects set */ 1837 union ecore_qable_obj { 1838 struct ecore_vlan_mac_obj vlan_mac; 1839 }; 1840 /************** Function state update *********/ 1841 void ecore_init_func_obj(struct bxe_softc *sc, 1842 struct ecore_func_sp_obj *obj, 1843 void *rdata, ecore_dma_addr_t rdata_mapping, 1844 void *afex_rdata, ecore_dma_addr_t afex_rdata_mapping, 1845 struct ecore_func_sp_drv_ops *drv_iface); 1846 1847 int ecore_func_state_change(struct bxe_softc *sc, 1848 struct ecore_func_state_params *params); 1849 1850 enum ecore_func_state ecore_func_get_state(struct bxe_softc *sc, 1851 struct ecore_func_sp_obj *o); 1852 /******************* Queue State **************/ 1853 void ecore_init_queue_obj(struct bxe_softc *sc, 1854 struct ecore_queue_sp_obj *obj, uint8_t cl_id, uint32_t *cids, 1855 uint8_t cid_cnt, uint8_t func_id, void *rdata, 1856 ecore_dma_addr_t rdata_mapping, unsigned long type); 1857 1858 int ecore_queue_state_change(struct bxe_softc *sc, 1859 struct ecore_queue_state_params *params); 1860 1861 int ecore_get_q_logical_state(struct bxe_softc *sc, 1862 struct ecore_queue_sp_obj *obj); 1863 1864 /********************* VLAN-MAC ****************/ 1865 void ecore_init_mac_obj(struct bxe_softc *sc, 1866 struct ecore_vlan_mac_obj *mac_obj, 1867 uint8_t cl_id, uint32_t cid, uint8_t func_id, void *rdata, 1868 ecore_dma_addr_t rdata_mapping, int state, 1869 unsigned long *pstate, ecore_obj_type type, 1870 struct ecore_credit_pool_obj *macs_pool); 1871 1872 void ecore_init_vlan_obj(struct bxe_softc *sc, 1873 struct ecore_vlan_mac_obj *vlan_obj, 1874 uint8_t cl_id, uint32_t cid, uint8_t func_id, void *rdata, 1875 ecore_dma_addr_t rdata_mapping, int state, 1876 unsigned long *pstate, ecore_obj_type type, 1877 struct ecore_credit_pool_obj *vlans_pool); 1878 1879 void ecore_init_vlan_mac_obj(struct bxe_softc *sc, 1880 struct ecore_vlan_mac_obj *vlan_mac_obj, 1881 uint8_t cl_id, uint32_t cid, uint8_t func_id, void *rdata, 1882 ecore_dma_addr_t rdata_mapping, int state, 1883 unsigned long *pstate, ecore_obj_type type, 1884 struct ecore_credit_pool_obj *macs_pool, 1885 struct ecore_credit_pool_obj *vlans_pool); 1886 1887 void ecore_init_vxlan_fltr_obj(struct bxe_softc *sc, 1888 struct ecore_vlan_mac_obj *vlan_mac_obj, 1889 uint8_t cl_id, uint32_t cid, uint8_t func_id, void *rdata, 1890 ecore_dma_addr_t rdata_mapping, int state, 1891 unsigned long *pstate, ecore_obj_type type, 1892 struct ecore_credit_pool_obj *macs_pool, 1893 struct ecore_credit_pool_obj *vlans_pool); 1894 1895 int ecore_vlan_mac_h_read_lock(struct bxe_softc *sc, 1896 struct ecore_vlan_mac_obj *o); 1897 void ecore_vlan_mac_h_read_unlock(struct bxe_softc *sc, 1898 struct ecore_vlan_mac_obj *o); 1899 int ecore_vlan_mac_h_write_lock(struct bxe_softc *sc, 1900 struct ecore_vlan_mac_obj *o); 1901 void ecore_vlan_mac_h_write_unlock(struct bxe_softc *sc, 1902 struct ecore_vlan_mac_obj *o); 1903 int ecore_config_vlan_mac(struct bxe_softc *sc, 1904 struct ecore_vlan_mac_ramrod_params *p); 1905 1906 int ecore_vlan_mac_move(struct bxe_softc *sc, 1907 struct ecore_vlan_mac_ramrod_params *p, 1908 struct ecore_vlan_mac_obj *dest_o); 1909 1910 /********************* RX MODE ****************/ 1911 1912 void ecore_init_rx_mode_obj(struct bxe_softc *sc, 1913 struct ecore_rx_mode_obj *o); 1914 1915 /** 1916 * ecore_config_rx_mode - Send and RX_MODE ramrod according to the provided parameters. 1917 * 1918 * @p: Command parameters 1919 * 1920 * Return: 0 - if operation was successful and there is no pending completions, 1921 * positive number - if there are pending completions, 1922 * negative - if there were errors 1923 */ 1924 int ecore_config_rx_mode(struct bxe_softc *sc, 1925 struct ecore_rx_mode_ramrod_params *p); 1926 1927 /****************** MULTICASTS ****************/ 1928 1929 void ecore_init_mcast_obj(struct bxe_softc *sc, 1930 struct ecore_mcast_obj *mcast_obj, 1931 uint8_t mcast_cl_id, uint32_t mcast_cid, uint8_t func_id, 1932 uint8_t engine_id, void *rdata, ecore_dma_addr_t rdata_mapping, 1933 int state, unsigned long *pstate, 1934 ecore_obj_type type); 1935 1936 /** 1937 * ecore_config_mcast - Configure multicast MACs list. 1938 * 1939 * @cmd: command to execute: BNX2X_MCAST_CMD_X 1940 * 1941 * May configure a new list 1942 * provided in p->mcast_list (ECORE_MCAST_CMD_ADD), clean up 1943 * (ECORE_MCAST_CMD_DEL) or restore (ECORE_MCAST_CMD_RESTORE) a current 1944 * configuration, continue to execute the pending commands 1945 * (ECORE_MCAST_CMD_CONT). 1946 * 1947 * If previous command is still pending or if number of MACs to 1948 * configure is more that maximum number of MACs in one command, 1949 * the current command will be enqueued to the tail of the 1950 * pending commands list. 1951 * 1952 * Return: 0 is operation was successful and there are no pending completions, 1953 * negative if there were errors, positive if there are pending 1954 * completions. 1955 */ 1956 int ecore_config_mcast(struct bxe_softc *sc, 1957 struct ecore_mcast_ramrod_params *p, 1958 enum ecore_mcast_cmd cmd); 1959 1960 /****************** CREDIT POOL ****************/ 1961 void ecore_init_mac_credit_pool(struct bxe_softc *sc, 1962 struct ecore_credit_pool_obj *p, uint8_t func_id, 1963 uint8_t func_num); 1964 void ecore_init_vlan_credit_pool(struct bxe_softc *sc, 1965 struct ecore_credit_pool_obj *p, uint8_t func_id, 1966 uint8_t func_num); 1967 void ecore_init_credit_pool(struct ecore_credit_pool_obj *p, 1968 int base, int credit); 1969 1970 /****************** RSS CONFIGURATION ****************/ 1971 void ecore_init_rss_config_obj(struct bxe_softc *sc, 1972 struct ecore_rss_config_obj *rss_obj, 1973 uint8_t cl_id, uint32_t cid, uint8_t func_id, uint8_t engine_id, 1974 void *rdata, ecore_dma_addr_t rdata_mapping, 1975 int state, unsigned long *pstate, 1976 ecore_obj_type type); 1977 1978 /** 1979 * ecore_config_rss - Updates RSS configuration according to provided parameters 1980 * 1981 * Return: 0 in case of success 1982 */ 1983 int ecore_config_rss(struct bxe_softc *sc, 1984 struct ecore_config_rss_params *p); 1985 1986 /** 1987 * ecore_get_rss_ind_table - Return the current ind_table configuration. 1988 * 1989 * @ind_table: buffer to fill with the current indirection 1990 * table content. Should be at least 1991 * T_ETH_INDIRECTION_TABLE_SIZE bytes long. 1992 */ 1993 void ecore_get_rss_ind_table(struct ecore_rss_config_obj *rss_obj, 1994 uint8_t *ind_table); 1995 1996 #define PF_MAC_CREDIT_E2(sc, func_num) \ 1997 ((MAX_MAC_CREDIT_E2 - GET_NUM_VFS_PER_PATH(sc) * VF_MAC_CREDIT_CNT) / \ 1998 func_num + GET_NUM_VFS_PER_PF(sc) * VF_MAC_CREDIT_CNT) 1999 2000 #define PF_VLAN_CREDIT_E2(sc, func_num) \ 2001 ((MAX_MAC_CREDIT_E2 - GET_NUM_VFS_PER_PATH(sc) * VF_VLAN_CREDIT_CNT) / \ 2002 func_num + GET_NUM_VFS_PER_PF(sc) * VF_VLAN_CREDIT_CNT) 2003 2004 2005 #endif /* ECORE_SP_H */ 2006 2007