1 /*- 2 * Copyright (c) 2007-2014 QLogic Corporation. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' 15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS 18 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 19 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 20 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 21 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 22 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 23 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 24 * THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #ifndef ECORE_SP_H 31 #define ECORE_SP_H 32 33 34 #include <sys/types.h> 35 #include <sys/endian.h> 36 #include <sys/param.h> 37 #include <sys/lock.h> 38 #include <sys/mutex.h> 39 #include <sys/malloc.h> 40 #include <sys/kernel.h> 41 #include <machine/bus.h> 42 #include <net/ethernet.h> 43 44 #if _BYTE_ORDER == _LITTLE_ENDIAN 45 #ifndef LITTLE_ENDIAN 46 #define LITTLE_ENDIAN 47 #endif 48 #ifndef __LITTLE_ENDIAN 49 #define __LITTLE_ENDIAN 50 #endif 51 #undef BIG_ENDIAN 52 #undef __BIG_ENDIAN 53 #else /* _BIG_ENDIAN */ 54 #ifndef BIG_ENDIAN 55 #define BIG_ENDIAN 56 #endif 57 #ifndef __BIG_ENDIAN 58 #define __BIG_ENDIAN 59 #endif 60 #undef LITTLE_ENDIAN 61 #undef __LITTLE_ENDIAN 62 #endif 63 64 #include "ecore_mfw_req.h" 65 #include "ecore_fw_defs.h" 66 #include "ecore_hsi.h" 67 #include "ecore_reg.h" 68 69 struct bxe_softc; 70 typedef bus_addr_t ecore_dma_addr_t; /* expected to be 64 bit wide */ 71 typedef volatile int ecore_atomic_t; 72 73 #ifndef __bool_true_false_are_defined 74 #ifndef __cplusplus 75 #define bool _Bool 76 #if __STDC_VERSION__ < 199901L && __GNUC__ < 3 && !defined(__INTEL_COMPILER) 77 typedef _Bool bool; 78 #endif 79 #endif /* !__cplusplus */ 80 #endif /* !__bool_true_false_are_defined$ */ 81 82 #define ETH_ALEN ETHER_ADDR_LEN /* 6 */ 83 84 #define ECORE_SWCID_SHIFT 17 85 #define ECORE_SWCID_MASK ((0x1 << ECORE_SWCID_SHIFT) - 1) 86 87 #define ECORE_MC_HASH_SIZE 8 88 #define ECORE_MC_HASH_OFFSET(sc, i) \ 89 (BAR_TSTRORM_INTMEM + \ 90 TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(FUNC_ID(sc)) + i*4) 91 92 #define ECORE_MAX_MULTICAST 64 93 #define ECORE_MAX_EMUL_MULTI 1 94 95 #define IRO sc->iro_array 96 97 typedef struct mtx ECORE_MUTEX; 98 #define ECORE_MUTEX_INIT(_mutex) \ 99 mtx_init(_mutex, "ecore_lock", "ECORE Lock", MTX_DEF) 100 #define ECORE_MUTEX_LOCK(_mutex) mtx_lock(_mutex) 101 #define ECORE_MUTEX_UNLOCK(_mutex) mtx_unlock(_mutex) 102 103 typedef struct mtx ECORE_MUTEX_SPIN; 104 #define ECORE_SPIN_LOCK_INIT(_spin, _sc) \ 105 mtx_init(_spin, "ecore_lock", "ECORE Lock", MTX_DEF) 106 #define ECORE_SPIN_LOCK_BH(_spin) mtx_lock(_spin) /* bh = bottom-half */ 107 #define ECORE_SPIN_UNLOCK_BH(_spin) mtx_unlock(_spin) /* bh = bottom-half */ 108 109 #define ECORE_SMP_MB_AFTER_CLEAR_BIT() mb() 110 #define ECORE_SMP_MB_BEFORE_CLEAR_BIT() mb() 111 #define ECORE_SMP_MB() mb() 112 #define ECORE_SMP_RMB() rmb() 113 #define ECORE_SMP_WMB() wmb() 114 #define ECORE_MMIOWB() wmb() 115 116 #define ECORE_SET_BIT_NA(bit, var) bit_set(var, bit) /* non-atomic */ 117 #define ECORE_CLEAR_BIT_NA(bit, var) bit_clear(var, bit) /* non-atomic */ 118 #define ECORE_TEST_BIT(bit, var) bxe_test_bit(bit, var) 119 #define ECORE_SET_BIT(bit, var) bxe_set_bit(bit, var) 120 #define ECORE_CLEAR_BIT(bit, var) bxe_clear_bit(bit, var) 121 #define ECORE_TEST_AND_CLEAR_BIT(bit, var) bxe_test_and_clear_bit(bit, var) 122 123 #define ECORE_ATOMIC_READ(a) atomic_load_acq_int((volatile int *)a) 124 #define ECORE_ATOMIC_SET(a, v) atomic_store_rel_int((volatile int *)a, v) 125 #define ECORE_ATOMIC_CMPXCHG(a, o, n) bxe_cmpxchg((volatile int *)a, o, n) 126 127 #define ECORE_RET_PENDING(pending_bit, pending) \ 128 (ECORE_TEST_BIT(pending_bit, pending) ? ECORE_PENDING : ECORE_SUCCESS) 129 130 #define ECORE_SET_FLAG(value, mask, flag) \ 131 do { \ 132 (value) &= ~(mask); \ 133 (value) |= ((flag) << (mask##_SHIFT)); \ 134 } while (0) 135 136 #define ECORE_GET_FLAG(value, mask) \ 137 (((value) &= (mask)) >> (mask##_SHIFT)) 138 139 #define ECORE_MIGHT_SLEEP() 140 141 #define ECORE_FCOE_CID(sc) ((sc)->fp[FCOE_IDX(sc)].cl_id) 142 143 #define ECORE_MEMCMP(_a, _b, _s) memcmp(_a, _b, _s) 144 #define ECORE_MEMCPY(_a, _b, _s) memcpy(_a, _b, _s) 145 #define ECORE_MEMSET(_a, _c, _s) memset(_a, _c, _s) 146 147 #define ECORE_CPU_TO_LE16(x) htole16(x) 148 #define ECORE_CPU_TO_LE32(x) htole32(x) 149 150 #define ECORE_WAIT(_s, _t) DELAY(1000) 151 #define ECORE_MSLEEP(_t) DELAY((_t) * 1000) 152 153 #define ECORE_LIKELY(x) __predict_true(x) 154 #define ECORE_UNLIKELY(x) __predict_false(x) 155 156 #define ECORE_ZALLOC(_size, _flags, _sc) \ 157 malloc(_size, M_TEMP, (M_NOWAIT | M_ZERO)) 158 159 #define ECORE_CALLOC(_len, _size, _flags, _sc) \ 160 malloc(_len * _size, M_TEMP, (M_NOWAIT | M_ZERO)) 161 162 #define ECORE_FREE(_s, _buf, _size) free(_buf, M_TEMP) 163 164 #define SC_ILT(sc) ((sc)->ilt) 165 #define ILOG2(x) bxe_ilog2(x) 166 167 #define ECORE_ILT_ZALLOC(x, y, size) \ 168 do { \ 169 x = malloc(sizeof(struct bxe_dma), M_DEVBUF, (M_NOWAIT | M_ZERO)); \ 170 if (x) { \ 171 if (bxe_dma_alloc((struct bxe_softc *)sc, \ 172 size, (struct bxe_dma *)x, \ 173 "ECORE_ILT") != 0) { \ 174 free(x, M_DEVBUF); \ 175 x = NULL; \ 176 *y = 0; \ 177 } else { \ 178 *y = ((struct bxe_dma *)x)->paddr; \ 179 } \ 180 } \ 181 } while (0) 182 183 #define ECORE_ILT_FREE(x, y, size) \ 184 do { \ 185 if (x) { \ 186 bxe_dma_free((struct bxe_softc *)sc, x); \ 187 free(x, M_DEVBUF); \ 188 x = NULL; \ 189 y = 0; \ 190 } \ 191 } while (0) 192 193 #define ECORE_IS_VALID_ETHER_ADDR(_mac) TRUE 194 195 #define ECORE_IS_MF_SD_MODE IS_MF_SD_MODE 196 #define ECORE_IS_MF_SI_MODE IS_MF_SI_MODE 197 #define ECORE_IS_MF_AFEX_MODE IS_MF_AFEX_MODE 198 199 #define ECORE_SET_CTX_VALIDATION bxe_set_ctx_validation 200 201 #define ECORE_UPDATE_COALESCE_SB_INDEX bxe_update_coalesce_sb_index 202 203 #define ECORE_ALIGN(x, a) ((((x) + (a) - 1) / (a)) * (a)) 204 205 #define ECORE_REG_WR_DMAE_LEN REG_WR_DMAE_LEN 206 207 #define ECORE_PATH_ID SC_PATH 208 #define ECORE_PORT_ID SC_PORT 209 #define ECORE_FUNC_ID SC_FUNC 210 #define ECORE_ABS_FUNC_ID SC_ABS_FUNC 211 212 uint32_t calc_crc32(uint8_t *crc32_packet, uint32_t crc32_length, 213 uint32_t crc32_seed, uint8_t complement); 214 static inline uint32_t 215 ECORE_CRC32_LE(uint32_t seed, uint8_t *mac, uint32_t len) 216 { 217 uint32_t packet_buf[2] = {0}; 218 memcpy(((uint8_t *)(&packet_buf[0]))+2, &mac[0], 2); 219 memcpy(&packet_buf[1], &mac[2], 4); 220 return bswap32(calc_crc32((uint8_t *)packet_buf, 8, seed, 0)); 221 } 222 223 #define ecore_sp_post(_sc, _a, _b, _c, _d) \ 224 bxe_sp_post(_sc, _a, _b, U64_HI(_c), U64_LO(_c), _d) 225 226 #ifdef ECORE_STOP_ON_ERROR 227 228 #define ECORE_DBG_BREAK_IF(exp) \ 229 do { \ 230 if (__predict_false(exp)) { \ 231 panic("ECORE"); \ 232 } \ 233 } while (0) 234 235 #define ECORE_BUG() \ 236 do { \ 237 panic("BUG (%s:%d)", __FILE__, __LINE__); \ 238 } while(0); 239 240 #define ECORE_BUG_ON(exp) \ 241 do { \ 242 if (__predict_true(exp)) { \ 243 panic("BUG_ON (%s:%d)", __FILE__, __LINE__); \ 244 } \ 245 } while (0) 246 247 #else 248 249 #define ECORE_DBG_BREAK_IF(exp) \ 250 printf("%s (%s,%d)\n", __FUNCTION__, __FILE__, __LINE__); 251 252 #define ECORE_BUG(exp) \ 253 printf("%s (%s,%d)\n", __FUNCTION__, __FILE__, __LINE__); 254 255 #define ECORE_BUG_ON(exp) \ 256 printf("%s (%s,%d)\n", __FUNCTION__, __FILE__, __LINE__); 257 258 259 #endif /* #ifdef ECORE_STOP_ON_ERROR */ 260 261 #define ECORE_ERR(str, ...) \ 262 BLOGE(sc, "ECORE: " str, ##__VA_ARGS__) 263 264 #define DBG_SP 0x00000004 /* defined in bxe.h */ 265 266 #define ECORE_MSG(sc, m, ...) \ 267 BLOGD(sc, DBG_SP, "ECORE: " m, ##__VA_ARGS__) 268 269 typedef struct _ecore_list_entry_t 270 { 271 struct _ecore_list_entry_t *next, *prev; 272 } ecore_list_entry_t; 273 274 typedef struct ecore_list_t 275 { 276 ecore_list_entry_t *head, *tail; 277 unsigned long cnt; 278 } ecore_list_t; 279 280 /* initialize the list */ 281 #define ECORE_LIST_INIT(_list) \ 282 do { \ 283 (_list)->head = NULL; \ 284 (_list)->tail = NULL; \ 285 (_list)->cnt = 0; \ 286 } while (0) 287 288 /* return TRUE if the element is the last on the list */ 289 #define ECORE_LIST_IS_LAST(_elem, _list) \ 290 (_elem == (_list)->tail) 291 292 /* return TRUE if the list is empty */ 293 #define ECORE_LIST_IS_EMPTY(_list) \ 294 ((_list)->cnt == 0) 295 296 /* return the first element */ 297 #define ECORE_LIST_FIRST_ENTRY(_list, cast, _link) \ 298 (cast *)((_list)->head) 299 300 /* return the next element */ 301 #define ECORE_LIST_NEXT(_elem, _link, cast) \ 302 (cast *)((&((_elem)->_link))->next) 303 304 /* push an element on the head of the list */ 305 #define ECORE_LIST_PUSH_HEAD(_elem, _list) \ 306 do { \ 307 (_elem)->prev = (ecore_list_entry_t *)0; \ 308 (_elem)->next = (_list)->head; \ 309 if ((_list)->tail == (ecore_list_entry_t *)0) { \ 310 (_list)->tail = (_elem); \ 311 } else { \ 312 (_list)->head->prev = (_elem); \ 313 } \ 314 (_list)->head = (_elem); \ 315 (_list)->cnt++; \ 316 } while (0) 317 318 /* push an element on the tail of the list */ 319 #define ECORE_LIST_PUSH_TAIL(_elem, _list) \ 320 do { \ 321 (_elem)->next = (ecore_list_entry_t *)0; \ 322 (_elem)->prev = (_list)->tail; \ 323 if ((_list)->tail) { \ 324 (_list)->tail->next = (_elem); \ 325 } else { \ 326 (_list)->head = (_elem); \ 327 } \ 328 (_list)->tail = (_elem); \ 329 (_list)->cnt++; \ 330 } while (0) 331 332 /* push list1 on the head of list2 and return with list1 as empty */ 333 #define ECORE_LIST_SPLICE_INIT(_list1, _list2) \ 334 do { \ 335 (_list1)->tail->next = (_list2)->head; \ 336 if ((_list2)->head) { \ 337 (_list2)->head->prev = (_list1)->tail; \ 338 } else { \ 339 (_list2)->tail = (_list1)->tail; \ 340 } \ 341 (_list2)->head = (_list1)->head; \ 342 (_list2)->cnt += (_list1)->cnt; \ 343 (_list1)->head = NULL; \ 344 (_list1)->tail = NULL; \ 345 (_list1)->cnt = 0; \ 346 } while (0) 347 348 /* remove an element from the list */ 349 #define ECORE_LIST_REMOVE_ENTRY(_elem, _list) \ 350 do { \ 351 if ((_list)->head == (_elem)) { \ 352 if ((_list)->head) { \ 353 (_list)->head = (_list)->head->next; \ 354 if ((_list)->head) { \ 355 (_list)->head->prev = (ecore_list_entry_t *)0; \ 356 } else { \ 357 (_list)->tail = (ecore_list_entry_t *)0; \ 358 } \ 359 (_list)->cnt--; \ 360 } \ 361 } else if ((_list)->tail == (_elem)) { \ 362 if ((_list)->tail) { \ 363 (_list)->tail = (_list)->tail->prev; \ 364 if ((_list)->tail) { \ 365 (_list)->tail->next = (ecore_list_entry_t *)0; \ 366 } else { \ 367 (_list)->head = (ecore_list_entry_t *)0; \ 368 } \ 369 (_list)->cnt--; \ 370 } \ 371 } else { \ 372 (_elem)->prev->next = (_elem)->next; \ 373 (_elem)->next->prev = (_elem)->prev; \ 374 (_list)->cnt--; \ 375 } \ 376 } while (0) 377 378 /* walk the list */ 379 #define ECORE_LIST_FOR_EACH_ENTRY(pos, _list, _link, cast) \ 380 for (pos = ECORE_LIST_FIRST_ENTRY(_list, cast, _link); \ 381 pos; \ 382 pos = ECORE_LIST_NEXT(pos, _link, cast)) 383 384 /* walk the list (safely) */ 385 #define ECORE_LIST_FOR_EACH_ENTRY_SAFE(pos, n, _list, _link, cast) \ 386 for (pos = ECORE_LIST_FIRST_ENTRY(_list, cast, _lint), \ 387 n = (pos) ? ECORE_LIST_NEXT(pos, _link, cast) : NULL; \ 388 pos != NULL; \ 389 pos = (cast *)n, \ 390 n = (pos) ? ECORE_LIST_NEXT(pos, _link, cast) : NULL) 391 392 393 /* Manipulate a bit vector defined as an array of uint64_t */ 394 395 /* Number of bits in one sge_mask array element */ 396 #define BIT_VEC64_ELEM_SZ 64 397 #define BIT_VEC64_ELEM_SHIFT 6 398 #define BIT_VEC64_ELEM_MASK ((uint64_t)BIT_VEC64_ELEM_SZ - 1) 399 400 #define __BIT_VEC64_SET_BIT(el, bit) \ 401 do { \ 402 el = ((el) | ((uint64_t)0x1 << (bit))); \ 403 } while (0) 404 405 #define __BIT_VEC64_CLEAR_BIT(el, bit) \ 406 do { \ 407 el = ((el) & (~((uint64_t)0x1 << (bit)))); \ 408 } while (0) 409 410 #define BIT_VEC64_SET_BIT(vec64, idx) \ 411 __BIT_VEC64_SET_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \ 412 (idx) & BIT_VEC64_ELEM_MASK) 413 414 #define BIT_VEC64_CLEAR_BIT(vec64, idx) \ 415 __BIT_VEC64_CLEAR_BIT((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT], \ 416 (idx) & BIT_VEC64_ELEM_MASK) 417 418 #define BIT_VEC64_TEST_BIT(vec64, idx) \ 419 (((vec64)[(idx) >> BIT_VEC64_ELEM_SHIFT] >> \ 420 ((idx) & BIT_VEC64_ELEM_MASK)) & 0x1) 421 422 /* 423 * Creates a bitmask of all ones in less significant bits. 424 * idx - index of the most significant bit in the created mask 425 */ 426 #define BIT_VEC64_ONES_MASK(idx) \ 427 (((uint64_t)0x1 << (((idx) & BIT_VEC64_ELEM_MASK) + 1)) - 1) 428 #define BIT_VEC64_ELEM_ONE_MASK ((uint64_t)(~0)) 429 430 /* fill in a MAC address the way the FW likes it */ 431 static inline void 432 ecore_set_fw_mac_addr(uint16_t *fw_hi, 433 uint16_t *fw_mid, 434 uint16_t *fw_lo, 435 uint8_t *mac) 436 { 437 ((uint8_t *)fw_hi)[0] = mac[1]; 438 ((uint8_t *)fw_hi)[1] = mac[0]; 439 ((uint8_t *)fw_mid)[0] = mac[3]; 440 ((uint8_t *)fw_mid)[1] = mac[2]; 441 ((uint8_t *)fw_lo)[0] = mac[5]; 442 ((uint8_t *)fw_lo)[1] = mac[4]; 443 } 444 445 446 enum ecore_status_t { 447 ECORE_EXISTS = -6, 448 ECORE_IO = -5, 449 ECORE_TIMEOUT = -4, 450 ECORE_INVAL = -3, 451 ECORE_BUSY = -2, 452 ECORE_NOMEM = -1, 453 ECORE_SUCCESS = 0, 454 /* PENDING is not an error and should be positive */ 455 ECORE_PENDING = 1, 456 }; 457 458 enum { 459 SWITCH_UPDATE, 460 AFEX_UPDATE, 461 }; 462 463 464 465 466 struct bxe_softc; 467 struct eth_context; 468 469 /* Bits representing general command's configuration */ 470 enum { 471 RAMROD_TX, 472 RAMROD_RX, 473 /* Wait until all pending commands complete */ 474 RAMROD_COMP_WAIT, 475 /* Don't send a ramrod, only update a registry */ 476 RAMROD_DRV_CLR_ONLY, 477 /* Configure HW according to the current object state */ 478 RAMROD_RESTORE, 479 /* Execute the next command now */ 480 RAMROD_EXEC, 481 /* Don't add a new command and continue execution of posponed 482 * commands. If not set a new command will be added to the 483 * pending commands list. 484 */ 485 RAMROD_CONT, 486 /* If there is another pending ramrod, wait until it finishes and 487 * re-try to submit this one. This flag can be set only in sleepable 488 * context, and should not be set from the context that completes the 489 * ramrods as deadlock will occur. 490 */ 491 RAMROD_RETRY, 492 }; 493 494 typedef enum { 495 ECORE_OBJ_TYPE_RX, 496 ECORE_OBJ_TYPE_TX, 497 ECORE_OBJ_TYPE_RX_TX, 498 } ecore_obj_type; 499 500 /* Public slow path states */ 501 enum { 502 ECORE_FILTER_MAC_PENDING, 503 ECORE_FILTER_VLAN_PENDING, 504 ECORE_FILTER_VLAN_MAC_PENDING, 505 ECORE_FILTER_RX_MODE_PENDING, 506 ECORE_FILTER_RX_MODE_SCHED, 507 ECORE_FILTER_ISCSI_ETH_START_SCHED, 508 ECORE_FILTER_ISCSI_ETH_STOP_SCHED, 509 ECORE_FILTER_FCOE_ETH_START_SCHED, 510 ECORE_FILTER_FCOE_ETH_STOP_SCHED, 511 ECORE_FILTER_BYPASS_RX_MODE_PENDING, 512 ECORE_FILTER_BYPASS_MAC_PENDING, 513 ECORE_FILTER_BYPASS_RSS_CONF_PENDING, 514 ECORE_FILTER_MCAST_PENDING, 515 ECORE_FILTER_MCAST_SCHED, 516 ECORE_FILTER_RSS_CONF_PENDING, 517 ECORE_AFEX_FCOE_Q_UPDATE_PENDING, 518 ECORE_AFEX_PENDING_VIFSET_MCP_ACK 519 }; 520 521 struct ecore_raw_obj { 522 uint8_t func_id; 523 524 /* Queue params */ 525 uint8_t cl_id; 526 uint32_t cid; 527 528 /* Ramrod data buffer params */ 529 void *rdata; 530 ecore_dma_addr_t rdata_mapping; 531 532 /* Ramrod state params */ 533 int state; /* "ramrod is pending" state bit */ 534 unsigned long *pstate; /* pointer to state buffer */ 535 536 ecore_obj_type obj_type; 537 538 int (*wait_comp)(struct bxe_softc *sc, 539 struct ecore_raw_obj *o); 540 541 bool (*check_pending)(struct ecore_raw_obj *o); 542 void (*clear_pending)(struct ecore_raw_obj *o); 543 void (*set_pending)(struct ecore_raw_obj *o); 544 }; 545 546 /************************* VLAN-MAC commands related parameters ***************/ 547 struct ecore_mac_ramrod_data { 548 uint8_t mac[ETH_ALEN]; 549 uint8_t is_inner_mac; 550 }; 551 552 struct ecore_vlan_ramrod_data { 553 uint16_t vlan; 554 }; 555 556 struct ecore_vlan_mac_ramrod_data { 557 uint8_t mac[ETH_ALEN]; 558 uint8_t is_inner_mac; 559 uint16_t vlan; 560 }; 561 562 union ecore_classification_ramrod_data { 563 struct ecore_mac_ramrod_data mac; 564 struct ecore_vlan_ramrod_data vlan; 565 struct ecore_vlan_mac_ramrod_data vlan_mac; 566 }; 567 568 /* VLAN_MAC commands */ 569 enum ecore_vlan_mac_cmd { 570 ECORE_VLAN_MAC_ADD, 571 ECORE_VLAN_MAC_DEL, 572 ECORE_VLAN_MAC_MOVE, 573 }; 574 575 struct ecore_vlan_mac_data { 576 /* Requested command: ECORE_VLAN_MAC_XX */ 577 enum ecore_vlan_mac_cmd cmd; 578 /* used to contain the data related vlan_mac_flags bits from 579 * ramrod parameters. 580 */ 581 unsigned long vlan_mac_flags; 582 583 /* Needed for MOVE command */ 584 struct ecore_vlan_mac_obj *target_obj; 585 586 union ecore_classification_ramrod_data u; 587 }; 588 589 /*************************** Exe Queue obj ************************************/ 590 union ecore_exe_queue_cmd_data { 591 struct ecore_vlan_mac_data vlan_mac; 592 593 struct { 594 /* TODO */ 595 } mcast; 596 }; 597 598 struct ecore_exeq_elem { 599 ecore_list_entry_t link; 600 601 /* Length of this element in the exe_chunk. */ 602 int cmd_len; 603 604 union ecore_exe_queue_cmd_data cmd_data; 605 }; 606 607 union ecore_qable_obj; 608 609 union ecore_exeq_comp_elem { 610 union event_ring_elem *elem; 611 }; 612 613 struct ecore_exe_queue_obj; 614 615 typedef int (*exe_q_validate)(struct bxe_softc *sc, 616 union ecore_qable_obj *o, 617 struct ecore_exeq_elem *elem); 618 619 typedef int (*exe_q_remove)(struct bxe_softc *sc, 620 union ecore_qable_obj *o, 621 struct ecore_exeq_elem *elem); 622 623 /* Return positive if entry was optimized, 0 - if not, negative 624 * in case of an error. 625 */ 626 typedef int (*exe_q_optimize)(struct bxe_softc *sc, 627 union ecore_qable_obj *o, 628 struct ecore_exeq_elem *elem); 629 typedef int (*exe_q_execute)(struct bxe_softc *sc, 630 union ecore_qable_obj *o, 631 ecore_list_t *exe_chunk, 632 unsigned long *ramrod_flags); 633 typedef struct ecore_exeq_elem * 634 (*exe_q_get)(struct ecore_exe_queue_obj *o, 635 struct ecore_exeq_elem *elem); 636 637 struct ecore_exe_queue_obj { 638 /* Commands pending for an execution. */ 639 ecore_list_t exe_queue; 640 641 /* Commands pending for an completion. */ 642 ecore_list_t pending_comp; 643 644 ECORE_MUTEX_SPIN lock; 645 646 /* Maximum length of commands' list for one execution */ 647 int exe_chunk_len; 648 649 union ecore_qable_obj *owner; 650 651 /****** Virtual functions ******/ 652 /** 653 * Called before commands execution for commands that are really 654 * going to be executed (after 'optimize'). 655 * 656 * Must run under exe_queue->lock 657 */ 658 exe_q_validate validate; 659 660 /** 661 * Called before removing pending commands, cleaning allocated 662 * resources (e.g., credits from validate) 663 */ 664 exe_q_remove remove; 665 666 /** 667 * This will try to cancel the current pending commands list 668 * considering the new command. 669 * 670 * Returns the number of optimized commands or a negative error code 671 * 672 * Must run under exe_queue->lock 673 */ 674 exe_q_optimize optimize; 675 676 /** 677 * Run the next commands chunk (owner specific). 678 */ 679 exe_q_execute execute; 680 681 /** 682 * Return the exe_queue element containing the specific command 683 * if any. Otherwise return NULL. 684 */ 685 exe_q_get get; 686 }; 687 /***************** Classification verbs: Set/Del MAC/VLAN/VLAN-MAC ************/ 688 /* 689 * Element in the VLAN_MAC registry list having all current configured 690 * rules. 691 */ 692 struct ecore_vlan_mac_registry_elem { 693 ecore_list_entry_t link; 694 695 /* Used to store the cam offset used for the mac/vlan/vlan-mac. 696 * Relevant for 57710 and 57711 only. VLANs and MACs share the 697 * same CAM for these chips. 698 */ 699 int cam_offset; 700 701 /* Needed for DEL and RESTORE flows */ 702 unsigned long vlan_mac_flags; 703 704 union ecore_classification_ramrod_data u; 705 }; 706 707 /* Bits representing VLAN_MAC commands specific flags */ 708 enum { 709 ECORE_UC_LIST_MAC, 710 ECORE_ETH_MAC, 711 ECORE_ISCSI_ETH_MAC, 712 ECORE_NETQ_ETH_MAC, 713 ECORE_DONT_CONSUME_CAM_CREDIT, 714 ECORE_DONT_CONSUME_CAM_CREDIT_DEST, 715 }; 716 717 struct ecore_vlan_mac_ramrod_params { 718 /* Object to run the command from */ 719 struct ecore_vlan_mac_obj *vlan_mac_obj; 720 721 /* General command flags: COMP_WAIT, etc. */ 722 unsigned long ramrod_flags; 723 724 /* Command specific configuration request */ 725 struct ecore_vlan_mac_data user_req; 726 }; 727 728 struct ecore_vlan_mac_obj { 729 struct ecore_raw_obj raw; 730 731 /* Bookkeeping list: will prevent the addition of already existing 732 * entries. 733 */ 734 ecore_list_t head; 735 /* Implement a simple reader/writer lock on the head list. 736 * all these fields should only be accessed under the exe_queue lock 737 */ 738 uint8_t head_reader; /* Num. of readers accessing head list */ 739 bool head_exe_request; /* Pending execution request. */ 740 unsigned long saved_ramrod_flags; /* Ramrods of pending execution */ 741 742 /* Execution queue interface instance */ 743 struct ecore_exe_queue_obj exe_queue; 744 745 /* MACs credit pool */ 746 struct ecore_credit_pool_obj *macs_pool; 747 748 /* VLANs credit pool */ 749 struct ecore_credit_pool_obj *vlans_pool; 750 751 /* RAMROD command to be used */ 752 int ramrod_cmd; 753 754 /* copy first n elements onto preallocated buffer 755 * 756 * @param n number of elements to get 757 * @param buf buffer preallocated by caller into which elements 758 * will be copied. Note elements are 4-byte aligned 759 * so buffer size must be able to accommodate the 760 * aligned elements. 761 * 762 * @return number of copied bytes 763 */ 764 765 int (*get_n_elements)(struct bxe_softc *sc, 766 struct ecore_vlan_mac_obj *o, int n, uint8_t *base, 767 uint8_t stride, uint8_t size); 768 769 /** 770 * Checks if ADD-ramrod with the given params may be performed. 771 * 772 * @return zero if the element may be added 773 */ 774 775 int (*check_add)(struct bxe_softc *sc, 776 struct ecore_vlan_mac_obj *o, 777 union ecore_classification_ramrod_data *data); 778 779 /** 780 * Checks if DEL-ramrod with the given params may be performed. 781 * 782 * @return TRUE if the element may be deleted 783 */ 784 struct ecore_vlan_mac_registry_elem * 785 (*check_del)(struct bxe_softc *sc, 786 struct ecore_vlan_mac_obj *o, 787 union ecore_classification_ramrod_data *data); 788 789 /** 790 * Checks if DEL-ramrod with the given params may be performed. 791 * 792 * @return TRUE if the element may be deleted 793 */ 794 bool (*check_move)(struct bxe_softc *sc, 795 struct ecore_vlan_mac_obj *src_o, 796 struct ecore_vlan_mac_obj *dst_o, 797 union ecore_classification_ramrod_data *data); 798 799 /** 800 * Update the relevant credit object(s) (consume/return 801 * correspondingly). 802 */ 803 bool (*get_credit)(struct ecore_vlan_mac_obj *o); 804 bool (*put_credit)(struct ecore_vlan_mac_obj *o); 805 bool (*get_cam_offset)(struct ecore_vlan_mac_obj *o, int *offset); 806 bool (*put_cam_offset)(struct ecore_vlan_mac_obj *o, int offset); 807 808 /** 809 * Configures one rule in the ramrod data buffer. 810 */ 811 void (*set_one_rule)(struct bxe_softc *sc, 812 struct ecore_vlan_mac_obj *o, 813 struct ecore_exeq_elem *elem, int rule_idx, 814 int cam_offset); 815 816 /** 817 * Delete all configured elements having the given 818 * vlan_mac_flags specification. Assumes no pending for 819 * execution commands. Will schedule all all currently 820 * configured MACs/VLANs/VLAN-MACs matching the vlan_mac_flags 821 * specification for deletion and will use the given 822 * ramrod_flags for the last DEL operation. 823 * 824 * @param sc 825 * @param o 826 * @param ramrod_flags RAMROD_XX flags 827 * 828 * @return 0 if the last operation has completed successfully 829 * and there are no more elements left, positive value 830 * if there are pending for completion commands, 831 * negative value in case of failure. 832 */ 833 int (*delete_all)(struct bxe_softc *sc, 834 struct ecore_vlan_mac_obj *o, 835 unsigned long *vlan_mac_flags, 836 unsigned long *ramrod_flags); 837 838 /** 839 * Reconfigures the next MAC/VLAN/VLAN-MAC element from the previously 840 * configured elements list. 841 * 842 * @param sc 843 * @param p Command parameters (RAMROD_COMP_WAIT bit in 844 * ramrod_flags is only taken into an account) 845 * @param ppos a pointer to the cookie that should be given back in the 846 * next call to make function handle the next element. If 847 * *ppos is set to NULL it will restart the iterator. 848 * If returned *ppos == NULL this means that the last 849 * element has been handled. 850 * 851 * @return int 852 */ 853 int (*restore)(struct bxe_softc *sc, 854 struct ecore_vlan_mac_ramrod_params *p, 855 struct ecore_vlan_mac_registry_elem **ppos); 856 857 /** 858 * Should be called on a completion arrival. 859 * 860 * @param sc 861 * @param o 862 * @param cqe Completion element we are handling 863 * @param ramrod_flags if RAMROD_CONT is set the next bulk of 864 * pending commands will be executed. 865 * RAMROD_DRV_CLR_ONLY and RAMROD_RESTORE 866 * may also be set if needed. 867 * 868 * @return 0 if there are neither pending nor waiting for 869 * completion commands. Positive value if there are 870 * pending for execution or for completion commands. 871 * Negative value in case of an error (including an 872 * error in the cqe). 873 */ 874 int (*complete)(struct bxe_softc *sc, struct ecore_vlan_mac_obj *o, 875 union event_ring_elem *cqe, 876 unsigned long *ramrod_flags); 877 878 /** 879 * Wait for completion of all commands. Don't schedule new ones, 880 * just wait. It assumes that the completion code will schedule 881 * for new commands. 882 */ 883 int (*wait)(struct bxe_softc *sc, struct ecore_vlan_mac_obj *o); 884 }; 885 886 enum { 887 ECORE_LLH_CAM_ISCSI_ETH_LINE = 0, 888 ECORE_LLH_CAM_ETH_LINE, 889 ECORE_LLH_CAM_MAX_PF_LINE = NIG_REG_LLH1_FUNC_MEM_SIZE / 2 890 }; 891 892 void ecore_set_mac_in_nig(struct bxe_softc *sc, 893 bool add, unsigned char *dev_addr, int index); 894 895 /** RX_MODE verbs:DROP_ALL/ACCEPT_ALL/ACCEPT_ALL_MULTI/ACCEPT_ALL_VLAN/NORMAL */ 896 897 /* RX_MODE ramrod special flags: set in rx_mode_flags field in 898 * a ecore_rx_mode_ramrod_params. 899 */ 900 enum { 901 ECORE_RX_MODE_FCOE_ETH, 902 ECORE_RX_MODE_ISCSI_ETH, 903 }; 904 905 enum { 906 ECORE_ACCEPT_UNICAST, 907 ECORE_ACCEPT_MULTICAST, 908 ECORE_ACCEPT_ALL_UNICAST, 909 ECORE_ACCEPT_ALL_MULTICAST, 910 ECORE_ACCEPT_BROADCAST, 911 ECORE_ACCEPT_UNMATCHED, 912 ECORE_ACCEPT_ANY_VLAN 913 }; 914 915 struct ecore_rx_mode_ramrod_params { 916 struct ecore_rx_mode_obj *rx_mode_obj; 917 unsigned long *pstate; 918 int state; 919 uint8_t cl_id; 920 uint32_t cid; 921 uint8_t func_id; 922 unsigned long ramrod_flags; 923 unsigned long rx_mode_flags; 924 925 /* rdata is either a pointer to eth_filter_rules_ramrod_data(e2) or to 926 * a tstorm_eth_mac_filter_config (e1x). 927 */ 928 void *rdata; 929 ecore_dma_addr_t rdata_mapping; 930 931 /* Rx mode settings */ 932 unsigned long rx_accept_flags; 933 934 /* internal switching settings */ 935 unsigned long tx_accept_flags; 936 }; 937 938 struct ecore_rx_mode_obj { 939 int (*config_rx_mode)(struct bxe_softc *sc, 940 struct ecore_rx_mode_ramrod_params *p); 941 942 int (*wait_comp)(struct bxe_softc *sc, 943 struct ecore_rx_mode_ramrod_params *p); 944 }; 945 946 /********************** Set multicast group ***********************************/ 947 948 struct ecore_mcast_list_elem { 949 ecore_list_entry_t link; 950 uint8_t *mac; 951 }; 952 953 union ecore_mcast_config_data { 954 uint8_t *mac; 955 uint8_t bin; /* used in a RESTORE flow */ 956 }; 957 958 struct ecore_mcast_ramrod_params { 959 struct ecore_mcast_obj *mcast_obj; 960 961 /* Relevant options are RAMROD_COMP_WAIT and RAMROD_DRV_CLR_ONLY */ 962 unsigned long ramrod_flags; 963 964 ecore_list_t mcast_list; /* list of struct ecore_mcast_list_elem */ 965 /** TODO: 966 * - rename it to macs_num. 967 * - Add a new command type for handling pending commands 968 * (remove "zero semantics"). 969 * 970 * Length of mcast_list. If zero and ADD_CONT command - post 971 * pending commands. 972 */ 973 int mcast_list_len; 974 }; 975 976 enum ecore_mcast_cmd { 977 ECORE_MCAST_CMD_ADD, 978 ECORE_MCAST_CMD_CONT, 979 ECORE_MCAST_CMD_DEL, 980 ECORE_MCAST_CMD_RESTORE, 981 }; 982 983 struct ecore_mcast_obj { 984 struct ecore_raw_obj raw; 985 986 union { 987 struct { 988 #define ECORE_MCAST_BINS_NUM 256 989 #define ECORE_MCAST_VEC_SZ (ECORE_MCAST_BINS_NUM / 64) 990 uint64_t vec[ECORE_MCAST_VEC_SZ]; 991 992 /** Number of BINs to clear. Should be updated 993 * immediately when a command arrives in order to 994 * properly create DEL commands. 995 */ 996 int num_bins_set; 997 } aprox_match; 998 999 struct { 1000 ecore_list_t macs; 1001 int num_macs_set; 1002 } exact_match; 1003 } registry; 1004 1005 /* Pending commands */ 1006 ecore_list_t pending_cmds_head; 1007 1008 /* A state that is set in raw.pstate, when there are pending commands */ 1009 int sched_state; 1010 1011 /* Maximal number of mcast MACs configured in one command */ 1012 int max_cmd_len; 1013 1014 /* Total number of currently pending MACs to configure: both 1015 * in the pending commands list and in the current command. 1016 */ 1017 int total_pending_num; 1018 1019 uint8_t engine_id; 1020 1021 /** 1022 * @param cmd command to execute (ECORE_MCAST_CMD_X, see above) 1023 */ 1024 int (*config_mcast)(struct bxe_softc *sc, 1025 struct ecore_mcast_ramrod_params *p, 1026 enum ecore_mcast_cmd cmd); 1027 1028 /** 1029 * Fills the ramrod data during the RESTORE flow. 1030 * 1031 * @param sc 1032 * @param o 1033 * @param start_idx Registry index to start from 1034 * @param rdata_idx Index in the ramrod data to start from 1035 * 1036 * @return -1 if we handled the whole registry or index of the last 1037 * handled registry element. 1038 */ 1039 int (*hdl_restore)(struct bxe_softc *sc, struct ecore_mcast_obj *o, 1040 int start_bin, int *rdata_idx); 1041 1042 int (*enqueue_cmd)(struct bxe_softc *sc, struct ecore_mcast_obj *o, 1043 struct ecore_mcast_ramrod_params *p, 1044 enum ecore_mcast_cmd cmd); 1045 1046 void (*set_one_rule)(struct bxe_softc *sc, 1047 struct ecore_mcast_obj *o, int idx, 1048 union ecore_mcast_config_data *cfg_data, 1049 enum ecore_mcast_cmd cmd); 1050 1051 /** Checks if there are more mcast MACs to be set or a previous 1052 * command is still pending. 1053 */ 1054 bool (*check_pending)(struct ecore_mcast_obj *o); 1055 1056 /** 1057 * Set/Clear/Check SCHEDULED state of the object 1058 */ 1059 void (*set_sched)(struct ecore_mcast_obj *o); 1060 void (*clear_sched)(struct ecore_mcast_obj *o); 1061 bool (*check_sched)(struct ecore_mcast_obj *o); 1062 1063 /* Wait until all pending commands complete */ 1064 int (*wait_comp)(struct bxe_softc *sc, struct ecore_mcast_obj *o); 1065 1066 /** 1067 * Handle the internal object counters needed for proper 1068 * commands handling. Checks that the provided parameters are 1069 * feasible. 1070 */ 1071 int (*validate)(struct bxe_softc *sc, 1072 struct ecore_mcast_ramrod_params *p, 1073 enum ecore_mcast_cmd cmd); 1074 1075 /** 1076 * Restore the values of internal counters in case of a failure. 1077 */ 1078 void (*revert)(struct bxe_softc *sc, 1079 struct ecore_mcast_ramrod_params *p, 1080 int old_num_bins); 1081 1082 int (*get_registry_size)(struct ecore_mcast_obj *o); 1083 void (*set_registry_size)(struct ecore_mcast_obj *o, int n); 1084 }; 1085 1086 /*************************** Credit handling **********************************/ 1087 struct ecore_credit_pool_obj { 1088 1089 /* Current amount of credit in the pool */ 1090 ecore_atomic_t credit; 1091 1092 /* Maximum allowed credit. put() will check against it. */ 1093 int pool_sz; 1094 1095 /* Allocate a pool table statically. 1096 * 1097 * Currently the maximum allowed size is MAX_MAC_CREDIT_E2(272) 1098 * 1099 * The set bit in the table will mean that the entry is available. 1100 */ 1101 #define ECORE_POOL_VEC_SIZE (MAX_MAC_CREDIT_E2 / 64) 1102 uint64_t pool_mirror[ECORE_POOL_VEC_SIZE]; 1103 1104 /* Base pool offset (initialized differently */ 1105 int base_pool_offset; 1106 1107 /** 1108 * Get the next free pool entry. 1109 * 1110 * @return TRUE if there was a free entry in the pool 1111 */ 1112 bool (*get_entry)(struct ecore_credit_pool_obj *o, int *entry); 1113 1114 /** 1115 * Return the entry back to the pool. 1116 * 1117 * @return TRUE if entry is legal and has been successfully 1118 * returned to the pool. 1119 */ 1120 bool (*put_entry)(struct ecore_credit_pool_obj *o, int entry); 1121 1122 /** 1123 * Get the requested amount of credit from the pool. 1124 * 1125 * @param cnt Amount of requested credit 1126 * @return TRUE if the operation is successful 1127 */ 1128 bool (*get)(struct ecore_credit_pool_obj *o, int cnt); 1129 1130 /** 1131 * Returns the credit to the pool. 1132 * 1133 * @param cnt Amount of credit to return 1134 * @return TRUE if the operation is successful 1135 */ 1136 bool (*put)(struct ecore_credit_pool_obj *o, int cnt); 1137 1138 /** 1139 * Reads the current amount of credit. 1140 */ 1141 int (*check)(struct ecore_credit_pool_obj *o); 1142 }; 1143 1144 /*************************** RSS configuration ********************************/ 1145 enum { 1146 /* RSS_MODE bits are mutually exclusive */ 1147 ECORE_RSS_MODE_DISABLED, 1148 ECORE_RSS_MODE_REGULAR, 1149 1150 ECORE_RSS_SET_SRCH, /* Setup searcher, E1x specific flag */ 1151 1152 ECORE_RSS_IPV4, 1153 ECORE_RSS_IPV4_TCP, 1154 ECORE_RSS_IPV4_UDP, 1155 ECORE_RSS_IPV6, 1156 ECORE_RSS_IPV6_TCP, 1157 ECORE_RSS_IPV6_UDP, 1158 1159 ECORE_RSS_TUNNELING, 1160 #if defined(__VMKLNX__) && (VMWARE_ESX_DDK_VERSION < 55000) /* ! BNX2X_UPSTREAM */ 1161 ECORE_RSS_MODE_ESX51, 1162 #endif 1163 }; 1164 1165 struct ecore_config_rss_params { 1166 struct ecore_rss_config_obj *rss_obj; 1167 1168 /* may have RAMROD_COMP_WAIT set only */ 1169 unsigned long ramrod_flags; 1170 1171 /* ECORE_RSS_X bits */ 1172 unsigned long rss_flags; 1173 1174 /* Number hash bits to take into an account */ 1175 uint8_t rss_result_mask; 1176 1177 /* Indirection table */ 1178 uint8_t ind_table[T_ETH_INDIRECTION_TABLE_SIZE]; 1179 1180 /* RSS hash values */ 1181 uint32_t rss_key[10]; 1182 1183 /* valid only iff ECORE_RSS_UPDATE_TOE is set */ 1184 uint16_t toe_rss_bitmap; 1185 1186 /* valid iff ECORE_RSS_TUNNELING is set */ 1187 uint16_t tunnel_value; 1188 uint16_t tunnel_mask; 1189 }; 1190 1191 struct ecore_rss_config_obj { 1192 struct ecore_raw_obj raw; 1193 1194 /* RSS engine to use */ 1195 uint8_t engine_id; 1196 1197 /* Last configured indirection table */ 1198 uint8_t ind_table[T_ETH_INDIRECTION_TABLE_SIZE]; 1199 1200 /* flags for enabling 4-tupple hash on UDP */ 1201 uint8_t udp_rss_v4; 1202 uint8_t udp_rss_v6; 1203 1204 int (*config_rss)(struct bxe_softc *sc, 1205 struct ecore_config_rss_params *p); 1206 }; 1207 1208 /*********************** Queue state update ***********************************/ 1209 1210 /* UPDATE command options */ 1211 enum { 1212 ECORE_Q_UPDATE_IN_VLAN_REM, 1213 ECORE_Q_UPDATE_IN_VLAN_REM_CHNG, 1214 ECORE_Q_UPDATE_OUT_VLAN_REM, 1215 ECORE_Q_UPDATE_OUT_VLAN_REM_CHNG, 1216 ECORE_Q_UPDATE_ANTI_SPOOF, 1217 ECORE_Q_UPDATE_ANTI_SPOOF_CHNG, 1218 ECORE_Q_UPDATE_ACTIVATE, 1219 ECORE_Q_UPDATE_ACTIVATE_CHNG, 1220 ECORE_Q_UPDATE_DEF_VLAN_EN, 1221 ECORE_Q_UPDATE_DEF_VLAN_EN_CHNG, 1222 ECORE_Q_UPDATE_SILENT_VLAN_REM_CHNG, 1223 ECORE_Q_UPDATE_SILENT_VLAN_REM, 1224 ECORE_Q_UPDATE_TX_SWITCHING_CHNG, 1225 ECORE_Q_UPDATE_TX_SWITCHING, 1226 }; 1227 1228 /* Allowed Queue states */ 1229 enum ecore_q_state { 1230 ECORE_Q_STATE_RESET, 1231 ECORE_Q_STATE_INITIALIZED, 1232 ECORE_Q_STATE_ACTIVE, 1233 ECORE_Q_STATE_MULTI_COS, 1234 ECORE_Q_STATE_MCOS_TERMINATED, 1235 ECORE_Q_STATE_INACTIVE, 1236 ECORE_Q_STATE_STOPPED, 1237 ECORE_Q_STATE_TERMINATED, 1238 ECORE_Q_STATE_FLRED, 1239 ECORE_Q_STATE_MAX, 1240 }; 1241 1242 /* Allowed Queue states */ 1243 enum ecore_q_logical_state { 1244 ECORE_Q_LOGICAL_STATE_ACTIVE, 1245 ECORE_Q_LOGICAL_STATE_STOPPED, 1246 }; 1247 1248 /* Allowed commands */ 1249 enum ecore_queue_cmd { 1250 ECORE_Q_CMD_INIT, 1251 ECORE_Q_CMD_SETUP, 1252 ECORE_Q_CMD_SETUP_TX_ONLY, 1253 ECORE_Q_CMD_DEACTIVATE, 1254 ECORE_Q_CMD_ACTIVATE, 1255 ECORE_Q_CMD_UPDATE, 1256 ECORE_Q_CMD_UPDATE_TPA, 1257 ECORE_Q_CMD_HALT, 1258 ECORE_Q_CMD_CFC_DEL, 1259 ECORE_Q_CMD_TERMINATE, 1260 ECORE_Q_CMD_EMPTY, 1261 ECORE_Q_CMD_MAX, 1262 }; 1263 1264 /* queue SETUP + INIT flags */ 1265 enum { 1266 ECORE_Q_FLG_TPA, 1267 ECORE_Q_FLG_TPA_IPV6, 1268 ECORE_Q_FLG_TPA_GRO, 1269 ECORE_Q_FLG_STATS, 1270 ECORE_Q_FLG_ZERO_STATS, 1271 ECORE_Q_FLG_ACTIVE, 1272 ECORE_Q_FLG_OV, 1273 ECORE_Q_FLG_VLAN, 1274 ECORE_Q_FLG_COS, 1275 ECORE_Q_FLG_HC, 1276 ECORE_Q_FLG_HC_EN, 1277 ECORE_Q_FLG_DHC, 1278 ECORE_Q_FLG_OOO, 1279 ECORE_Q_FLG_FCOE, 1280 ECORE_Q_FLG_LEADING_RSS, 1281 ECORE_Q_FLG_MCAST, 1282 ECORE_Q_FLG_DEF_VLAN, 1283 ECORE_Q_FLG_TX_SWITCH, 1284 ECORE_Q_FLG_TX_SEC, 1285 ECORE_Q_FLG_ANTI_SPOOF, 1286 ECORE_Q_FLG_SILENT_VLAN_REM, 1287 ECORE_Q_FLG_FORCE_DEFAULT_PRI, 1288 ECORE_Q_FLG_REFUSE_OUTBAND_VLAN, 1289 ECORE_Q_FLG_PCSUM_ON_PKT, 1290 ECORE_Q_FLG_TUN_INC_INNER_IP_ID 1291 }; 1292 1293 /* Queue type options: queue type may be a combination of below. */ 1294 enum ecore_q_type { 1295 ECORE_Q_TYPE_FWD, 1296 /** TODO: Consider moving both these flags into the init() 1297 * ramrod params. 1298 */ 1299 ECORE_Q_TYPE_HAS_RX, 1300 ECORE_Q_TYPE_HAS_TX, 1301 }; 1302 1303 #define ECORE_PRIMARY_CID_INDEX 0 1304 #define ECORE_MULTI_TX_COS_E1X 3 /* QM only */ 1305 #define ECORE_MULTI_TX_COS_E2_E3A0 2 1306 #define ECORE_MULTI_TX_COS_E3B0 3 1307 #define ECORE_MULTI_TX_COS 3 /* Maximum possible */ 1308 #define MAC_PAD (ECORE_ALIGN(ETH_ALEN, sizeof(uint32_t)) - ETH_ALEN) 1309 1310 struct ecore_queue_init_params { 1311 struct { 1312 unsigned long flags; 1313 uint16_t hc_rate; 1314 uint8_t fw_sb_id; 1315 uint8_t sb_cq_index; 1316 } tx; 1317 1318 struct { 1319 unsigned long flags; 1320 uint16_t hc_rate; 1321 uint8_t fw_sb_id; 1322 uint8_t sb_cq_index; 1323 } rx; 1324 1325 /* CID context in the host memory */ 1326 struct eth_context *cxts[ECORE_MULTI_TX_COS]; 1327 1328 /* maximum number of cos supported by hardware */ 1329 uint8_t max_cos; 1330 }; 1331 1332 struct ecore_queue_terminate_params { 1333 /* index within the tx_only cids of this queue object */ 1334 uint8_t cid_index; 1335 }; 1336 1337 struct ecore_queue_cfc_del_params { 1338 /* index within the tx_only cids of this queue object */ 1339 uint8_t cid_index; 1340 }; 1341 1342 struct ecore_queue_update_params { 1343 unsigned long update_flags; /* ECORE_Q_UPDATE_XX bits */ 1344 uint16_t def_vlan; 1345 uint16_t silent_removal_value; 1346 uint16_t silent_removal_mask; 1347 /* index within the tx_only cids of this queue object */ 1348 uint8_t cid_index; 1349 }; 1350 1351 struct rxq_pause_params { 1352 uint16_t bd_th_lo; 1353 uint16_t bd_th_hi; 1354 uint16_t rcq_th_lo; 1355 uint16_t rcq_th_hi; 1356 uint16_t sge_th_lo; /* valid iff ECORE_Q_FLG_TPA */ 1357 uint16_t sge_th_hi; /* valid iff ECORE_Q_FLG_TPA */ 1358 uint16_t pri_map; 1359 }; 1360 1361 /* general */ 1362 struct ecore_general_setup_params { 1363 /* valid iff ECORE_Q_FLG_STATS */ 1364 uint8_t stat_id; 1365 1366 uint8_t spcl_id; 1367 uint16_t mtu; 1368 uint8_t cos; 1369 }; 1370 1371 struct ecore_rxq_setup_params { 1372 /* dma */ 1373 ecore_dma_addr_t dscr_map; 1374 ecore_dma_addr_t sge_map; 1375 ecore_dma_addr_t rcq_map; 1376 ecore_dma_addr_t rcq_np_map; 1377 1378 uint16_t drop_flags; 1379 uint16_t buf_sz; 1380 uint8_t fw_sb_id; 1381 uint8_t cl_qzone_id; 1382 1383 /* valid iff ECORE_Q_FLG_TPA */ 1384 uint16_t tpa_agg_sz; 1385 uint16_t sge_buf_sz; 1386 uint8_t max_sges_pkt; 1387 uint8_t max_tpa_queues; 1388 uint8_t rss_engine_id; 1389 1390 /* valid iff ECORE_Q_FLG_MCAST */ 1391 uint8_t mcast_engine_id; 1392 1393 uint8_t cache_line_log; 1394 1395 uint8_t sb_cq_index; 1396 1397 /* valid iff BXN2X_Q_FLG_SILENT_VLAN_REM */ 1398 uint16_t silent_removal_value; 1399 uint16_t silent_removal_mask; 1400 }; 1401 1402 struct ecore_txq_setup_params { 1403 /* dma */ 1404 ecore_dma_addr_t dscr_map; 1405 1406 uint8_t fw_sb_id; 1407 uint8_t sb_cq_index; 1408 uint8_t cos; /* valid iff ECORE_Q_FLG_COS */ 1409 uint16_t traffic_type; 1410 /* equals to the leading rss client id, used for TX classification*/ 1411 uint8_t tss_leading_cl_id; 1412 1413 /* valid iff ECORE_Q_FLG_DEF_VLAN */ 1414 uint16_t default_vlan; 1415 }; 1416 1417 struct ecore_queue_setup_params { 1418 struct ecore_general_setup_params gen_params; 1419 struct ecore_txq_setup_params txq_params; 1420 struct ecore_rxq_setup_params rxq_params; 1421 struct rxq_pause_params pause_params; 1422 unsigned long flags; 1423 }; 1424 1425 struct ecore_queue_setup_tx_only_params { 1426 struct ecore_general_setup_params gen_params; 1427 struct ecore_txq_setup_params txq_params; 1428 unsigned long flags; 1429 /* index within the tx_only cids of this queue object */ 1430 uint8_t cid_index; 1431 }; 1432 1433 struct ecore_queue_state_params { 1434 struct ecore_queue_sp_obj *q_obj; 1435 1436 /* Current command */ 1437 enum ecore_queue_cmd cmd; 1438 1439 /* may have RAMROD_COMP_WAIT set only */ 1440 unsigned long ramrod_flags; 1441 1442 /* Params according to the current command */ 1443 union { 1444 struct ecore_queue_update_params update; 1445 struct ecore_queue_setup_params setup; 1446 struct ecore_queue_init_params init; 1447 struct ecore_queue_setup_tx_only_params tx_only; 1448 struct ecore_queue_terminate_params terminate; 1449 struct ecore_queue_cfc_del_params cfc_del; 1450 } params; 1451 }; 1452 1453 struct ecore_viflist_params { 1454 uint8_t echo_res; 1455 uint8_t func_bit_map_res; 1456 }; 1457 1458 struct ecore_queue_sp_obj { 1459 uint32_t cids[ECORE_MULTI_TX_COS]; 1460 uint8_t cl_id; 1461 uint8_t func_id; 1462 1463 /* number of traffic classes supported by queue. 1464 * The primary connection of the queue supports the first traffic 1465 * class. Any further traffic class is supported by a tx-only 1466 * connection. 1467 * 1468 * Therefore max_cos is also a number of valid entries in the cids 1469 * array. 1470 */ 1471 uint8_t max_cos; 1472 uint8_t num_tx_only, next_tx_only; 1473 1474 enum ecore_q_state state, next_state; 1475 1476 /* bits from enum ecore_q_type */ 1477 unsigned long type; 1478 1479 /* ECORE_Q_CMD_XX bits. This object implements "one 1480 * pending" paradigm but for debug and tracing purposes it's 1481 * more convenient to have different bits for different 1482 * commands. 1483 */ 1484 unsigned long pending; 1485 1486 /* Buffer to use as a ramrod data and its mapping */ 1487 void *rdata; 1488 ecore_dma_addr_t rdata_mapping; 1489 1490 /** 1491 * Performs one state change according to the given parameters. 1492 * 1493 * @return 0 in case of success and negative value otherwise. 1494 */ 1495 int (*send_cmd)(struct bxe_softc *sc, 1496 struct ecore_queue_state_params *params); 1497 1498 /** 1499 * Sets the pending bit according to the requested transition. 1500 */ 1501 int (*set_pending)(struct ecore_queue_sp_obj *o, 1502 struct ecore_queue_state_params *params); 1503 1504 /** 1505 * Checks that the requested state transition is legal. 1506 */ 1507 int (*check_transition)(struct bxe_softc *sc, 1508 struct ecore_queue_sp_obj *o, 1509 struct ecore_queue_state_params *params); 1510 1511 /** 1512 * Completes the pending command. 1513 */ 1514 int (*complete_cmd)(struct bxe_softc *sc, 1515 struct ecore_queue_sp_obj *o, 1516 enum ecore_queue_cmd); 1517 1518 int (*wait_comp)(struct bxe_softc *sc, 1519 struct ecore_queue_sp_obj *o, 1520 enum ecore_queue_cmd cmd); 1521 }; 1522 1523 /********************** Function state update *********************************/ 1524 /* Allowed Function states */ 1525 enum ecore_func_state { 1526 ECORE_F_STATE_RESET, 1527 ECORE_F_STATE_INITIALIZED, 1528 ECORE_F_STATE_STARTED, 1529 ECORE_F_STATE_TX_STOPPED, 1530 ECORE_F_STATE_MAX, 1531 }; 1532 1533 /* Allowed Function commands */ 1534 enum ecore_func_cmd { 1535 ECORE_F_CMD_HW_INIT, 1536 ECORE_F_CMD_START, 1537 ECORE_F_CMD_STOP, 1538 ECORE_F_CMD_HW_RESET, 1539 ECORE_F_CMD_AFEX_UPDATE, 1540 ECORE_F_CMD_AFEX_VIFLISTS, 1541 ECORE_F_CMD_TX_STOP, 1542 ECORE_F_CMD_TX_START, 1543 ECORE_F_CMD_SWITCH_UPDATE, 1544 ECORE_F_CMD_MAX, 1545 }; 1546 1547 struct ecore_func_hw_init_params { 1548 /* A load phase returned by MCP. 1549 * 1550 * May be: 1551 * FW_MSG_CODE_DRV_LOAD_COMMON_CHIP 1552 * FW_MSG_CODE_DRV_LOAD_COMMON 1553 * FW_MSG_CODE_DRV_LOAD_PORT 1554 * FW_MSG_CODE_DRV_LOAD_FUNCTION 1555 */ 1556 uint32_t load_phase; 1557 }; 1558 1559 struct ecore_func_hw_reset_params { 1560 /* A load phase returned by MCP. 1561 * 1562 * May be: 1563 * FW_MSG_CODE_DRV_LOAD_COMMON_CHIP 1564 * FW_MSG_CODE_DRV_LOAD_COMMON 1565 * FW_MSG_CODE_DRV_LOAD_PORT 1566 * FW_MSG_CODE_DRV_LOAD_FUNCTION 1567 */ 1568 uint32_t reset_phase; 1569 }; 1570 1571 struct ecore_func_start_params { 1572 /* Multi Function mode: 1573 * - Single Function 1574 * - Switch Dependent 1575 * - Switch Independent 1576 */ 1577 uint16_t mf_mode; 1578 1579 /* Switch Dependent mode outer VLAN tag */ 1580 uint16_t sd_vlan_tag; 1581 1582 /* Function cos mode */ 1583 uint8_t network_cos_mode; 1584 1585 /* NVGRE classification enablement */ 1586 uint8_t nvgre_clss_en; 1587 1588 /* NO_GRE_TUNNEL/NVGRE_TUNNEL/L2GRE_TUNNEL/IPGRE_TUNNEL */ 1589 uint8_t gre_tunnel_mode; 1590 1591 /* GRE_OUTER_HEADERS_RSS/GRE_INNER_HEADERS_RSS/NVGRE_KEY_ENTROPY_RSS */ 1592 uint8_t gre_tunnel_rss; 1593 1594 }; 1595 1596 struct ecore_func_switch_update_params { 1597 uint8_t suspend; 1598 }; 1599 1600 struct ecore_func_afex_update_params { 1601 uint16_t vif_id; 1602 uint16_t afex_default_vlan; 1603 uint8_t allowed_priorities; 1604 }; 1605 1606 struct ecore_func_afex_viflists_params { 1607 uint16_t vif_list_index; 1608 uint8_t func_bit_map; 1609 uint8_t afex_vif_list_command; 1610 uint8_t func_to_clear; 1611 }; 1612 struct ecore_func_tx_start_params { 1613 struct priority_cos traffic_type_to_priority_cos[MAX_TRAFFIC_TYPES]; 1614 uint8_t dcb_enabled; 1615 uint8_t dcb_version; 1616 uint8_t dont_add_pri_0; 1617 }; 1618 1619 struct ecore_func_state_params { 1620 struct ecore_func_sp_obj *f_obj; 1621 1622 /* Current command */ 1623 enum ecore_func_cmd cmd; 1624 1625 /* may have RAMROD_COMP_WAIT set only */ 1626 unsigned long ramrod_flags; 1627 1628 /* Params according to the current command */ 1629 union { 1630 struct ecore_func_hw_init_params hw_init; 1631 struct ecore_func_hw_reset_params hw_reset; 1632 struct ecore_func_start_params start; 1633 struct ecore_func_switch_update_params switch_update; 1634 struct ecore_func_afex_update_params afex_update; 1635 struct ecore_func_afex_viflists_params afex_viflists; 1636 struct ecore_func_tx_start_params tx_start; 1637 } params; 1638 }; 1639 1640 struct ecore_func_sp_drv_ops { 1641 /* Init tool + runtime initialization: 1642 * - Common Chip 1643 * - Common (per Path) 1644 * - Port 1645 * - Function phases 1646 */ 1647 int (*init_hw_cmn_chip)(struct bxe_softc *sc); 1648 int (*init_hw_cmn)(struct bxe_softc *sc); 1649 int (*init_hw_port)(struct bxe_softc *sc); 1650 int (*init_hw_func)(struct bxe_softc *sc); 1651 1652 /* Reset Function HW: Common, Port, Function phases. */ 1653 void (*reset_hw_cmn)(struct bxe_softc *sc); 1654 void (*reset_hw_port)(struct bxe_softc *sc); 1655 void (*reset_hw_func)(struct bxe_softc *sc); 1656 1657 /* Init/Free GUNZIP resources */ 1658 int (*gunzip_init)(struct bxe_softc *sc); 1659 void (*gunzip_end)(struct bxe_softc *sc); 1660 1661 /* Prepare/Release FW resources */ 1662 int (*init_fw)(struct bxe_softc *sc); 1663 void (*release_fw)(struct bxe_softc *sc); 1664 }; 1665 1666 struct ecore_func_sp_obj { 1667 enum ecore_func_state state, next_state; 1668 1669 /* ECORE_FUNC_CMD_XX bits. This object implements "one 1670 * pending" paradigm but for debug and tracing purposes it's 1671 * more convenient to have different bits for different 1672 * commands. 1673 */ 1674 unsigned long pending; 1675 1676 /* Buffer to use as a ramrod data and its mapping */ 1677 void *rdata; 1678 ecore_dma_addr_t rdata_mapping; 1679 1680 /* Buffer to use as a afex ramrod data and its mapping. 1681 * This can't be same rdata as above because afex ramrod requests 1682 * can arrive to the object in parallel to other ramrod requests. 1683 */ 1684 void *afex_rdata; 1685 ecore_dma_addr_t afex_rdata_mapping; 1686 1687 /* this mutex validates that when pending flag is taken, the next 1688 * ramrod to be sent will be the one set the pending bit 1689 */ 1690 ECORE_MUTEX one_pending_mutex; 1691 1692 /* Driver interface */ 1693 struct ecore_func_sp_drv_ops *drv; 1694 1695 /** 1696 * Performs one state change according to the given parameters. 1697 * 1698 * @return 0 in case of success and negative value otherwise. 1699 */ 1700 int (*send_cmd)(struct bxe_softc *sc, 1701 struct ecore_func_state_params *params); 1702 1703 /** 1704 * Checks that the requested state transition is legal. 1705 */ 1706 int (*check_transition)(struct bxe_softc *sc, 1707 struct ecore_func_sp_obj *o, 1708 struct ecore_func_state_params *params); 1709 1710 /** 1711 * Completes the pending command. 1712 */ 1713 int (*complete_cmd)(struct bxe_softc *sc, 1714 struct ecore_func_sp_obj *o, 1715 enum ecore_func_cmd cmd); 1716 1717 int (*wait_comp)(struct bxe_softc *sc, struct ecore_func_sp_obj *o, 1718 enum ecore_func_cmd cmd); 1719 }; 1720 1721 /********************** Interfaces ********************************************/ 1722 /* Queueable objects set */ 1723 union ecore_qable_obj { 1724 struct ecore_vlan_mac_obj vlan_mac; 1725 }; 1726 /************** Function state update *********/ 1727 void ecore_init_func_obj(struct bxe_softc *sc, 1728 struct ecore_func_sp_obj *obj, 1729 void *rdata, ecore_dma_addr_t rdata_mapping, 1730 void *afex_rdata, ecore_dma_addr_t afex_rdata_mapping, 1731 struct ecore_func_sp_drv_ops *drv_iface); 1732 1733 int ecore_func_state_change(struct bxe_softc *sc, 1734 struct ecore_func_state_params *params); 1735 1736 enum ecore_func_state ecore_func_get_state(struct bxe_softc *sc, 1737 struct ecore_func_sp_obj *o); 1738 /******************* Queue State **************/ 1739 void ecore_init_queue_obj(struct bxe_softc *sc, 1740 struct ecore_queue_sp_obj *obj, uint8_t cl_id, uint32_t *cids, 1741 uint8_t cid_cnt, uint8_t func_id, void *rdata, 1742 ecore_dma_addr_t rdata_mapping, unsigned long type); 1743 1744 int ecore_queue_state_change(struct bxe_softc *sc, 1745 struct ecore_queue_state_params *params); 1746 1747 int ecore_get_q_logical_state(struct bxe_softc *sc, 1748 struct ecore_queue_sp_obj *obj); 1749 1750 /********************* VLAN-MAC ****************/ 1751 void ecore_init_mac_obj(struct bxe_softc *sc, 1752 struct ecore_vlan_mac_obj *mac_obj, 1753 uint8_t cl_id, uint32_t cid, uint8_t func_id, void *rdata, 1754 ecore_dma_addr_t rdata_mapping, int state, 1755 unsigned long *pstate, ecore_obj_type type, 1756 struct ecore_credit_pool_obj *macs_pool); 1757 1758 void ecore_init_vlan_obj(struct bxe_softc *sc, 1759 struct ecore_vlan_mac_obj *vlan_obj, 1760 uint8_t cl_id, uint32_t cid, uint8_t func_id, void *rdata, 1761 ecore_dma_addr_t rdata_mapping, int state, 1762 unsigned long *pstate, ecore_obj_type type, 1763 struct ecore_credit_pool_obj *vlans_pool); 1764 1765 void ecore_init_vlan_mac_obj(struct bxe_softc *sc, 1766 struct ecore_vlan_mac_obj *vlan_mac_obj, 1767 uint8_t cl_id, uint32_t cid, uint8_t func_id, void *rdata, 1768 ecore_dma_addr_t rdata_mapping, int state, 1769 unsigned long *pstate, ecore_obj_type type, 1770 struct ecore_credit_pool_obj *macs_pool, 1771 struct ecore_credit_pool_obj *vlans_pool); 1772 1773 int ecore_vlan_mac_h_read_lock(struct bxe_softc *sc, 1774 struct ecore_vlan_mac_obj *o); 1775 void ecore_vlan_mac_h_read_unlock(struct bxe_softc *sc, 1776 struct ecore_vlan_mac_obj *o); 1777 int ecore_vlan_mac_h_write_lock(struct bxe_softc *sc, 1778 struct ecore_vlan_mac_obj *o); 1779 void ecore_vlan_mac_h_write_unlock(struct bxe_softc *sc, 1780 struct ecore_vlan_mac_obj *o); 1781 int ecore_config_vlan_mac(struct bxe_softc *sc, 1782 struct ecore_vlan_mac_ramrod_params *p); 1783 1784 int ecore_vlan_mac_move(struct bxe_softc *sc, 1785 struct ecore_vlan_mac_ramrod_params *p, 1786 struct ecore_vlan_mac_obj *dest_o); 1787 1788 /********************* RX MODE ****************/ 1789 1790 void ecore_init_rx_mode_obj(struct bxe_softc *sc, 1791 struct ecore_rx_mode_obj *o); 1792 1793 /** 1794 * ecore_config_rx_mode - Send and RX_MODE ramrod according to the provided parameters. 1795 * 1796 * @p: Command parameters 1797 * 1798 * Return: 0 - if operation was successful and there is no pending completions, 1799 * positive number - if there are pending completions, 1800 * negative - if there were errors 1801 */ 1802 int ecore_config_rx_mode(struct bxe_softc *sc, 1803 struct ecore_rx_mode_ramrod_params *p); 1804 1805 /****************** MULTICASTS ****************/ 1806 1807 void ecore_init_mcast_obj(struct bxe_softc *sc, 1808 struct ecore_mcast_obj *mcast_obj, 1809 uint8_t mcast_cl_id, uint32_t mcast_cid, uint8_t func_id, 1810 uint8_t engine_id, void *rdata, ecore_dma_addr_t rdata_mapping, 1811 int state, unsigned long *pstate, 1812 ecore_obj_type type); 1813 1814 /** 1815 * ecore_config_mcast - Configure multicast MACs list. 1816 * 1817 * @cmd: command to execute: BNX2X_MCAST_CMD_X 1818 * 1819 * May configure a new list 1820 * provided in p->mcast_list (ECORE_MCAST_CMD_ADD), clean up 1821 * (ECORE_MCAST_CMD_DEL) or restore (ECORE_MCAST_CMD_RESTORE) a current 1822 * configuration, continue to execute the pending commands 1823 * (ECORE_MCAST_CMD_CONT). 1824 * 1825 * If previous command is still pending or if number of MACs to 1826 * configure is more that maximum number of MACs in one command, 1827 * the current command will be enqueued to the tail of the 1828 * pending commands list. 1829 * 1830 * Return: 0 is operation was successfull and there are no pending completions, 1831 * negative if there were errors, positive if there are pending 1832 * completions. 1833 */ 1834 int ecore_config_mcast(struct bxe_softc *sc, 1835 struct ecore_mcast_ramrod_params *p, 1836 enum ecore_mcast_cmd cmd); 1837 1838 /****************** CREDIT POOL ****************/ 1839 void ecore_init_mac_credit_pool(struct bxe_softc *sc, 1840 struct ecore_credit_pool_obj *p, uint8_t func_id, 1841 uint8_t func_num); 1842 void ecore_init_vlan_credit_pool(struct bxe_softc *sc, 1843 struct ecore_credit_pool_obj *p, uint8_t func_id, 1844 uint8_t func_num); 1845 1846 /****************** RSS CONFIGURATION ****************/ 1847 void ecore_init_rss_config_obj(struct bxe_softc *sc, 1848 struct ecore_rss_config_obj *rss_obj, 1849 uint8_t cl_id, uint32_t cid, uint8_t func_id, uint8_t engine_id, 1850 void *rdata, ecore_dma_addr_t rdata_mapping, 1851 int state, unsigned long *pstate, 1852 ecore_obj_type type); 1853 1854 /** 1855 * ecore_config_rss - Updates RSS configuration according to provided parameters 1856 * 1857 * Return: 0 in case of success 1858 */ 1859 int ecore_config_rss(struct bxe_softc *sc, 1860 struct ecore_config_rss_params *p); 1861 1862 /** 1863 * ecore_get_rss_ind_table - Return the current ind_table configuration. 1864 * 1865 * @ind_table: buffer to fill with the current indirection 1866 * table content. Should be at least 1867 * T_ETH_INDIRECTION_TABLE_SIZE bytes long. 1868 */ 1869 void ecore_get_rss_ind_table(struct ecore_rss_config_obj *rss_obj, 1870 uint8_t *ind_table); 1871 1872 /* set as inline so printout will show the offending function */ 1873 int validate_vlan_mac(struct bxe_softc *sc, 1874 struct ecore_vlan_mac_obj *vlan_mac); 1875 1876 #endif /* ECORE_SP_H */ 1877 1878