1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2007-2017 QLogic Corporation. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 26 * THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 #ifndef ECORE_INIT_H 31 #define ECORE_INIT_H 32 33 /* Init operation types and structures */ 34 enum { 35 OP_RD = 0x1, /* read a single register */ 36 OP_WR, /* write a single register */ 37 OP_SW, /* copy a string to the device */ 38 OP_ZR, /* clear memory */ 39 OP_ZP, /* unzip then copy with DMAE */ 40 OP_WR_64, /* write 64 bit pattern */ 41 OP_WB, /* copy a string using DMAE */ 42 #ifndef FW_ZIP_SUPPORT 43 OP_FW, /* copy an array from fw data (only used with unzipped FW) */ 44 #endif 45 OP_WB_ZR, /* Clear a string using DMAE or indirect-wr */ 46 OP_IF_MODE_OR, /* Skip the following ops if all init modes don't match */ 47 OP_IF_MODE_AND, /* Skip the following ops if any init modes don't match */ 48 OP_IF_PHASE, 49 OP_RT, 50 OP_DELAY, 51 OP_VERIFY, 52 OP_MAX 53 }; 54 55 enum { 56 STAGE_START, 57 STAGE_END, 58 }; 59 60 /* Returns the index of start or end of a specific block stage in ops array*/ 61 #define BLOCK_OPS_IDX(block, stage, end) \ 62 (2*(((block)*NUM_OF_INIT_PHASES) + (stage)) + (end)) 63 64 65 /* structs for the various opcodes */ 66 struct raw_op { 67 uint32_t op:8; 68 uint32_t offset:24; 69 uint32_t raw_data; 70 }; 71 72 struct op_read { 73 uint32_t op:8; 74 uint32_t offset:24; 75 uint32_t val; 76 }; 77 78 struct op_write { 79 uint32_t op:8; 80 uint32_t offset:24; 81 uint32_t val; 82 }; 83 84 struct op_arr_write { 85 uint32_t op:8; 86 uint32_t offset:24; 87 #ifdef __BIG_ENDIAN 88 uint16_t data_len; 89 uint16_t data_off; 90 #else /* __LITTLE_ENDIAN */ 91 uint16_t data_off; 92 uint16_t data_len; 93 #endif 94 }; 95 96 struct op_zero { 97 uint32_t op:8; 98 uint32_t offset:24; 99 uint32_t len; 100 }; 101 102 struct op_if_mode { 103 uint32_t op:8; 104 uint32_t cmd_offset:24; 105 uint32_t mode_bit_map; 106 }; 107 108 struct op_if_phase { 109 uint32_t op:8; 110 uint32_t cmd_offset:24; 111 uint32_t phase_bit_map; 112 }; 113 114 struct op_delay { 115 uint32_t op:8; 116 uint32_t reserved:24; 117 uint32_t delay; 118 }; 119 120 union init_op { 121 struct op_read read; 122 struct op_write write; 123 struct op_arr_write arr_wr; 124 struct op_zero zero; 125 struct raw_op raw; 126 struct op_if_mode if_mode; 127 struct op_if_phase if_phase; 128 struct op_delay delay; 129 }; 130 131 132 /* Init Phases */ 133 enum { 134 PHASE_COMMON, 135 PHASE_PORT0, 136 PHASE_PORT1, 137 PHASE_PF0, 138 PHASE_PF1, 139 PHASE_PF2, 140 PHASE_PF3, 141 PHASE_PF4, 142 PHASE_PF5, 143 PHASE_PF6, 144 PHASE_PF7, 145 NUM_OF_INIT_PHASES 146 }; 147 148 /* Init Modes */ 149 enum { 150 MODE_ASIC = 0x00000001, 151 MODE_FPGA = 0x00000002, 152 MODE_EMUL = 0x00000004, 153 MODE_E2 = 0x00000008, 154 MODE_E3 = 0x00000010, 155 MODE_PORT2 = 0x00000020, 156 MODE_PORT4 = 0x00000040, 157 MODE_SF = 0x00000080, 158 MODE_MF = 0x00000100, 159 MODE_MF_SD = 0x00000200, 160 MODE_MF_SI = 0x00000400, 161 MODE_MF_AFEX = 0x00000800, 162 MODE_E3_A0 = 0x00001000, 163 MODE_E3_B0 = 0x00002000, 164 MODE_COS3 = 0x00004000, 165 MODE_COS6 = 0x00008000, 166 MODE_LITTLE_ENDIAN = 0x00010000, 167 MODE_BIG_ENDIAN = 0x00020000, 168 }; 169 170 /* Init Blocks */ 171 enum { 172 BLOCK_ATC, 173 BLOCK_BRB1, 174 BLOCK_CCM, 175 BLOCK_CDU, 176 BLOCK_CFC, 177 BLOCK_CSDM, 178 BLOCK_CSEM, 179 BLOCK_DBG, 180 BLOCK_DMAE, 181 BLOCK_DORQ, 182 BLOCK_HC, 183 BLOCK_IGU, 184 BLOCK_MISC, 185 BLOCK_NIG, 186 BLOCK_PBF, 187 BLOCK_PGLUE_B, 188 BLOCK_PRS, 189 BLOCK_PXP2, 190 BLOCK_PXP, 191 BLOCK_QM, 192 BLOCK_SRC, 193 BLOCK_TCM, 194 BLOCK_TM, 195 BLOCK_TSDM, 196 BLOCK_TSEM, 197 BLOCK_UCM, 198 BLOCK_UPB, 199 BLOCK_USDM, 200 BLOCK_USEM, 201 BLOCK_XCM, 202 BLOCK_XPB, 203 BLOCK_XSDM, 204 BLOCK_XSEM, 205 BLOCK_MISC_AEU, 206 NUM_OF_INIT_BLOCKS 207 }; 208 209 210 211 212 213 214 215 216 /* Vnics per mode */ 217 #define ECORE_PORT2_MODE_NUM_VNICS 4 218 219 220 /* QM queue numbers */ 221 #define ECORE_ETH_Q 0 222 #define ECORE_TOE_Q 3 223 #define ECORE_TOE_ACK_Q 6 224 #define ECORE_ISCSI_Q 9 225 #define ECORE_ISCSI_ACK_Q 11 226 #define ECORE_FCOE_Q 10 227 228 /* Vnics per mode */ 229 #define ECORE_PORT4_MODE_NUM_VNICS 2 230 231 /* COS offset for port1 in E3 B0 4port mode */ 232 #define ECORE_E3B0_PORT1_COS_OFFSET 3 233 234 /* QM Register addresses */ 235 #define ECORE_Q_VOQ_REG_ADDR(pf_q_num)\ 236 (QM_REG_QVOQIDX_0 + 4 * (pf_q_num)) 237 #define ECORE_VOQ_Q_REG_ADDR(cos, pf_q_num)\ 238 (QM_REG_VOQQMASK_0_LSB + 4 * ((cos) * 2 + ((pf_q_num) >> 5))) 239 #define ECORE_Q_CMDQ_REG_ADDR(pf_q_num)\ 240 (QM_REG_BYTECRDCMDQ_0 + 4 * ((pf_q_num) >> 4)) 241 242 /* extracts the QM queue number for the specified port and vnic */ 243 #define ECORE_PF_Q_NUM(q_num, port, vnic)\ 244 ((((port) << 1) | (vnic)) * 16 + (q_num)) 245 246 247 /* Maps the specified queue to the specified COS */ 248 static inline void ecore_map_q_cos(struct bxe_softc *sc, uint32_t q_num, uint32_t new_cos) 249 { 250 /* find current COS mapping */ 251 uint32_t curr_cos = REG_RD(sc, QM_REG_QVOQIDX_0 + q_num * 4); 252 253 /* check if queue->COS mapping has changed */ 254 if (curr_cos != new_cos) { 255 uint32_t num_vnics = ECORE_PORT2_MODE_NUM_VNICS; 256 uint32_t reg_addr, reg_bit_map, vnic; 257 258 /* update parameters for 4port mode */ 259 if (INIT_MODE_FLAGS(sc) & MODE_PORT4) { 260 num_vnics = ECORE_PORT4_MODE_NUM_VNICS; 261 if (PORT_ID(sc)) { 262 curr_cos += ECORE_E3B0_PORT1_COS_OFFSET; 263 new_cos += ECORE_E3B0_PORT1_COS_OFFSET; 264 } 265 } 266 267 /* change queue mapping for each VNIC */ 268 for (vnic = 0; vnic < num_vnics; vnic++) { 269 uint32_t pf_q_num = 270 ECORE_PF_Q_NUM(q_num, PORT_ID(sc), vnic); 271 uint32_t q_bit_map = 1 << (pf_q_num & 0x1f); 272 273 /* overwrite queue->VOQ mapping */ 274 REG_WR(sc, ECORE_Q_VOQ_REG_ADDR(pf_q_num), new_cos); 275 276 /* clear queue bit from current COS bit map */ 277 reg_addr = ECORE_VOQ_Q_REG_ADDR(curr_cos, pf_q_num); 278 reg_bit_map = REG_RD(sc, reg_addr); 279 REG_WR(sc, reg_addr, reg_bit_map & (~q_bit_map)); 280 281 /* set queue bit in new COS bit map */ 282 reg_addr = ECORE_VOQ_Q_REG_ADDR(new_cos, pf_q_num); 283 reg_bit_map = REG_RD(sc, reg_addr); 284 REG_WR(sc, reg_addr, reg_bit_map | q_bit_map); 285 286 /* set/clear queue bit in command-queue bit map 287 (E2/E3A0 only, valid COS values are 0/1) */ 288 if (!(INIT_MODE_FLAGS(sc) & MODE_E3_B0)) { 289 reg_addr = ECORE_Q_CMDQ_REG_ADDR(pf_q_num); 290 reg_bit_map = REG_RD(sc, reg_addr); 291 q_bit_map = 1 << (2 * (pf_q_num & 0xf)); 292 reg_bit_map = new_cos ? 293 (reg_bit_map | q_bit_map) : 294 (reg_bit_map & (~q_bit_map)); 295 REG_WR(sc, reg_addr, reg_bit_map); 296 } 297 } 298 } 299 } 300 301 /* Configures the QM according to the specified per-traffic-type COSes */ 302 static inline void ecore_dcb_config_qm(struct bxe_softc *sc, enum cos_mode mode, 303 struct priority_cos *traffic_cos) 304 { 305 ecore_map_q_cos(sc, ECORE_FCOE_Q, 306 traffic_cos[LLFC_TRAFFIC_TYPE_FCOE].cos); 307 ecore_map_q_cos(sc, ECORE_ISCSI_Q, 308 traffic_cos[LLFC_TRAFFIC_TYPE_ISCSI].cos); 309 ecore_map_q_cos(sc, ECORE_ISCSI_ACK_Q, 310 traffic_cos[LLFC_TRAFFIC_TYPE_ISCSI].cos); 311 if (mode != STATIC_COS) { 312 /* required only in OVERRIDE_COS mode */ 313 ecore_map_q_cos(sc, ECORE_ETH_Q, 314 traffic_cos[LLFC_TRAFFIC_TYPE_NW].cos); 315 ecore_map_q_cos(sc, ECORE_TOE_Q, 316 traffic_cos[LLFC_TRAFFIC_TYPE_NW].cos); 317 ecore_map_q_cos(sc, ECORE_TOE_ACK_Q, 318 traffic_cos[LLFC_TRAFFIC_TYPE_NW].cos); 319 } 320 } 321 322 323 /* 324 * congestion management port init api description 325 * the api works as follows: 326 * the driver should pass the cmng_init_input struct, the port_init function 327 * will prepare the required internal ram structure which will be passed back 328 * to the driver (cmng_init) that will write it into the internal ram. 329 * 330 * IMPORTANT REMARKS: 331 * 1. the cmng_init struct does not represent the contiguous internal ram 332 * structure. the driver should use the XSTORM_CMNG_PERPORT_VARS_OFFSET 333 * offset in order to write the port sub struct and the 334 * PFID_FROM_PORT_AND_VNIC offset for writing the vnic sub struct (in other 335 * words - don't use memcpy!). 336 * 2. although the cmng_init struct is filled for the maximal vnic number 337 * possible, the driver should only write the valid vnics into the internal 338 * ram according to the appropriate port mode. 339 */ 340 #define BITS_TO_BYTES(x) ((x)/8) 341 342 /* CMNG constants, as derived from system spec calculations */ 343 344 /* default MIN rate in case VNIC min rate is configured to zero- 100Mbps */ 345 #define DEF_MIN_RATE 100 346 347 /* resolution of the rate shaping timer - 400 usec */ 348 #define RS_PERIODIC_TIMEOUT_USEC 400 349 350 /* 351 * number of bytes in single QM arbitration cycle - 352 * coefficient for calculating the fairness timer 353 */ 354 #define QM_ARB_BYTES 160000 355 356 /* resolution of Min algorithm 1:100 */ 357 #define MIN_RES 100 358 359 /* 360 * how many bytes above threshold for 361 * the minimal credit of Min algorithm 362 */ 363 #define MIN_ABOVE_THRESH 32768 364 365 /* 366 * Fairness algorithm integration time coefficient - 367 * for calculating the actual Tfair 368 */ 369 #define T_FAIR_COEF ((MIN_ABOVE_THRESH + QM_ARB_BYTES) * 8 * MIN_RES) 370 371 /* Memory of fairness algorithm - 2 cycles */ 372 #define FAIR_MEM 2 373 #define SAFC_TIMEOUT_USEC 52 374 375 #define SDM_TICKS 4 376 377 378 static inline void ecore_init_max(const struct cmng_init_input *input_data, 379 uint32_t r_param, struct cmng_init *ram_data) 380 { 381 uint32_t vnic; 382 struct cmng_vnic *vdata = &ram_data->vnic; 383 struct cmng_struct_per_port *pdata = &ram_data->port; 384 /* 385 * rate shaping per-port variables 386 * 100 micro seconds in SDM ticks = 25 387 * since each tick is 4 microSeconds 388 */ 389 390 pdata->rs_vars.rs_periodic_timeout = 391 RS_PERIODIC_TIMEOUT_USEC / SDM_TICKS; 392 393 /* this is the threshold below which no timer arming will occur. 394 * 1.25 coefficient is for the threshold to be a little bigger 395 * then the real time to compensate for timer in-accuracy 396 */ 397 pdata->rs_vars.rs_threshold = 398 (5 * RS_PERIODIC_TIMEOUT_USEC * r_param)/4; 399 400 /* rate shaping per-vnic variables */ 401 for (vnic = 0; vnic < ECORE_PORT2_MODE_NUM_VNICS; vnic++) { 402 /* global vnic counter */ 403 vdata->vnic_max_rate[vnic].vn_counter.rate = 404 input_data->vnic_max_rate[vnic]; 405 /* 406 * maximal Mbps for this vnic 407 * the quota in each timer period - number of bytes 408 * transmitted in this period 409 */ 410 vdata->vnic_max_rate[vnic].vn_counter.quota = 411 RS_PERIODIC_TIMEOUT_USEC * 412 (uint32_t)vdata->vnic_max_rate[vnic].vn_counter.rate / 8; 413 } 414 415 } 416 417 static inline void ecore_init_max_per_vn(uint16_t vnic_max_rate, 418 struct rate_shaping_vars_per_vn *ram_data) 419 { 420 /* global vnic counter */ 421 ram_data->vn_counter.rate = vnic_max_rate; 422 423 /* 424 * maximal Mbps for this vnic 425 * the quota in each timer period - number of bytes 426 * transmitted in this period 427 */ 428 ram_data->vn_counter.quota = 429 RS_PERIODIC_TIMEOUT_USEC * (uint32_t)vnic_max_rate / 8; 430 } 431 432 static inline void ecore_init_min(const struct cmng_init_input *input_data, 433 uint32_t r_param, struct cmng_init *ram_data) 434 { 435 uint32_t vnic, fair_periodic_timeout_usec, vnicWeightSum, tFair; 436 struct cmng_vnic *vdata = &ram_data->vnic; 437 struct cmng_struct_per_port *pdata = &ram_data->port; 438 439 /* this is the resolution of the fairness timer */ 440 fair_periodic_timeout_usec = QM_ARB_BYTES / r_param; 441 442 /* 443 * fairness per-port variables 444 * for 10G it is 1000usec. for 1G it is 10000usec. 445 */ 446 tFair = T_FAIR_COEF / input_data->port_rate; 447 448 /* this is the threshold below which we won't arm the timer anymore */ 449 pdata->fair_vars.fair_threshold = QM_ARB_BYTES; 450 451 /* 452 * we multiply by 1e3/8 to get bytes/msec. We don't want the credits 453 * to pass a credit of the T_FAIR*FAIR_MEM (algorithm resolution) 454 */ 455 pdata->fair_vars.upper_bound = r_param * tFair * FAIR_MEM; 456 457 /* since each tick is 4 microSeconds */ 458 pdata->fair_vars.fairness_timeout = 459 fair_periodic_timeout_usec / SDM_TICKS; 460 461 /* calculate sum of weights */ 462 vnicWeightSum = 0; 463 464 for (vnic = 0; vnic < ECORE_PORT2_MODE_NUM_VNICS; vnic++) 465 vnicWeightSum += input_data->vnic_min_rate[vnic]; 466 467 /* global vnic counter */ 468 if (vnicWeightSum > 0) { 469 /* fairness per-vnic variables */ 470 for (vnic = 0; vnic < ECORE_PORT2_MODE_NUM_VNICS; vnic++) { 471 /* 472 * this is the credit for each period of the fairness 473 * algorithm - number of bytes in T_FAIR (this vnic 474 * share of the port rate) 475 */ 476 vdata->vnic_min_rate[vnic].vn_credit_delta = 477 ((uint32_t)(input_data->vnic_min_rate[vnic]) * 100 * 478 (T_FAIR_COEF / (8 * 100 * vnicWeightSum))); 479 if (vdata->vnic_min_rate[vnic].vn_credit_delta < 480 pdata->fair_vars.fair_threshold + 481 MIN_ABOVE_THRESH) { 482 vdata->vnic_min_rate[vnic].vn_credit_delta = 483 pdata->fair_vars.fair_threshold + 484 MIN_ABOVE_THRESH; 485 } 486 } 487 } 488 } 489 490 static inline void ecore_init_fw_wrr(const struct cmng_init_input *input_data, 491 uint32_t r_param, struct cmng_init *ram_data) 492 { 493 uint32_t vnic, cos; 494 uint32_t cosWeightSum = 0; 495 struct cmng_vnic *vdata = &ram_data->vnic; 496 struct cmng_struct_per_port *pdata = &ram_data->port; 497 498 for (cos = 0; cos < MAX_COS_NUMBER; cos++) 499 cosWeightSum += input_data->cos_min_rate[cos]; 500 501 if (cosWeightSum > 0) { 502 503 for (vnic = 0; vnic < ECORE_PORT2_MODE_NUM_VNICS; vnic++) { 504 /* 505 * Since cos and vnic shouldn't work together the rate 506 * to divide between the coses is the port rate. 507 */ 508 uint32_t *ccd = vdata->vnic_min_rate[vnic].cos_credit_delta; 509 for (cos = 0; cos < MAX_COS_NUMBER; cos++) { 510 /* 511 * this is the credit for each period of 512 * the fairness algorithm - number of bytes 513 * in T_FAIR (this cos share of the vnic rate) 514 */ 515 ccd[cos] = 516 ((uint32_t)input_data->cos_min_rate[cos] * 100 * 517 (T_FAIR_COEF / (8 * 100 * cosWeightSum))); 518 if (ccd[cos] < pdata->fair_vars.fair_threshold 519 + MIN_ABOVE_THRESH) { 520 ccd[cos] = 521 pdata->fair_vars.fair_threshold + 522 MIN_ABOVE_THRESH; 523 } 524 } 525 } 526 } 527 } 528 529 static inline void ecore_init_safc(const struct cmng_init_input *input_data, 530 struct cmng_init *ram_data) 531 { 532 /* in microSeconds */ 533 ram_data->port.safc_vars.safc_timeout_usec = SAFC_TIMEOUT_USEC; 534 } 535 536 /* Congestion management port init */ 537 static inline void ecore_init_cmng(const struct cmng_init_input *input_data, 538 struct cmng_init *ram_data) 539 { 540 uint32_t r_param; 541 ECORE_MEMSET(ram_data, 0,sizeof(struct cmng_init)); 542 543 ram_data->port.flags = input_data->flags; 544 545 /* 546 * number of bytes transmitted in a rate of 10Gbps 547 * in one usec = 1.25KB. 548 */ 549 r_param = BITS_TO_BYTES(input_data->port_rate); 550 ecore_init_max(input_data, r_param, ram_data); 551 ecore_init_min(input_data, r_param, ram_data); 552 ecore_init_fw_wrr(input_data, r_param, ram_data); 553 ecore_init_safc(input_data, ram_data); 554 } 555 556 557 558 559 /* Returns the index of start or end of a specific block stage in ops array*/ 560 #define BLOCK_OPS_IDX(block, stage, end) \ 561 (2*(((block)*NUM_OF_INIT_PHASES) + (stage)) + (end)) 562 563 564 #define INITOP_SET 0 /* set the HW directly */ 565 #define INITOP_CLEAR 1 /* clear the HW directly */ 566 #define INITOP_INIT 2 /* set the init-value array */ 567 568 /**************************************************************************** 569 * ILT management 570 ****************************************************************************/ 571 struct ilt_line { 572 ecore_dma_addr_t page_mapping; 573 void *page; 574 uint32_t size; 575 }; 576 577 struct ilt_client_info { 578 uint32_t page_size; 579 uint16_t start; 580 uint16_t end; 581 uint16_t client_num; 582 uint16_t flags; 583 #define ILT_CLIENT_SKIP_INIT 0x1 584 #define ILT_CLIENT_SKIP_MEM 0x2 585 }; 586 587 struct ecore_ilt { 588 uint32_t start_line; 589 struct ilt_line *lines; 590 struct ilt_client_info clients[4]; 591 #define ILT_CLIENT_CDU 0 592 #define ILT_CLIENT_QM 1 593 #define ILT_CLIENT_SRC 2 594 #define ILT_CLIENT_TM 3 595 }; 596 597 /**************************************************************************** 598 * SRC configuration 599 ****************************************************************************/ 600 struct src_ent { 601 uint8_t opaque[56]; 602 uint64_t next; 603 }; 604 605 /**************************************************************************** 606 * Parity configuration 607 ****************************************************************************/ 608 #define BLOCK_PRTY_INFO(block, en_mask, m1, m1h, m2, m3) \ 609 { \ 610 block##_REG_##block##_PRTY_MASK, \ 611 block##_REG_##block##_PRTY_STS_CLR, \ 612 en_mask, {m1, m1h, m2, m3}, #block \ 613 } 614 615 #define BLOCK_PRTY_INFO_0(block, en_mask, m1, m1h, m2, m3) \ 616 { \ 617 block##_REG_##block##_PRTY_MASK_0, \ 618 block##_REG_##block##_PRTY_STS_CLR_0, \ 619 en_mask, {m1, m1h, m2, m3}, #block"_0" \ 620 } 621 622 #define BLOCK_PRTY_INFO_1(block, en_mask, m1, m1h, m2, m3) \ 623 { \ 624 block##_REG_##block##_PRTY_MASK_1, \ 625 block##_REG_##block##_PRTY_STS_CLR_1, \ 626 en_mask, {m1, m1h, m2, m3}, #block"_1" \ 627 } 628 629 static const struct { 630 uint32_t mask_addr; 631 uint32_t sts_clr_addr; 632 uint32_t en_mask; /* Mask to enable parity attentions */ 633 struct { 634 uint32_t e1; /* 57710 */ 635 uint32_t e1h; /* 57711 */ 636 uint32_t e2; /* 57712 */ 637 uint32_t e3; /* 578xx */ 638 } reg_mask; /* Register mask (all valid bits) */ 639 char name[8]; /* Block's longest name is 7 characters long 640 * (name + suffix) 641 */ 642 } ecore_blocks_parity_data[] = { 643 /* bit 19 masked */ 644 /* REG_WR(bp, PXP_REG_PXP_PRTY_MASK, 0x80000); */ 645 /* bit 5,18,20-31 */ 646 /* REG_WR(bp, PXP2_REG_PXP2_PRTY_MASK_0, 0xfff40020); */ 647 /* bit 5 */ 648 /* REG_WR(bp, PXP2_REG_PXP2_PRTY_MASK_1, 0x20); */ 649 /* REG_WR(bp, HC_REG_HC_PRTY_MASK, 0x0); */ 650 /* REG_WR(bp, MISC_REG_MISC_PRTY_MASK, 0x0); */ 651 652 /* Block IGU, MISC, PXP and PXP2 parity errors as long as we don't 653 * want to handle "system kill" flow at the moment. 654 */ 655 BLOCK_PRTY_INFO(PXP, 0x7ffffff, 0x3ffffff, 0x3ffffff, 0x7ffffff, 656 0x7ffffff), 657 BLOCK_PRTY_INFO_0(PXP2, 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 658 0xffffffff), 659 BLOCK_PRTY_INFO_1(PXP2, 0x1ffffff, 0x7f, 0x7f, 0x7ff, 0x1ffffff), 660 BLOCK_PRTY_INFO(HC, 0x7, 0x7, 0x7, 0, 0), 661 BLOCK_PRTY_INFO(NIG, 0xffffffff, 0x3fffffff, 0xffffffff, 0, 0), 662 BLOCK_PRTY_INFO_0(NIG, 0xffffffff, 0, 0, 0xffffffff, 0xffffffff), 663 BLOCK_PRTY_INFO_1(NIG, 0xffff, 0, 0, 0xff, 0xffff), 664 BLOCK_PRTY_INFO(IGU, 0x7ff, 0, 0, 0x7ff, 0x7ff), 665 BLOCK_PRTY_INFO(MISC, 0x1, 0x1, 0x1, 0x1, 0x1), 666 BLOCK_PRTY_INFO(QM, 0, 0x1ff, 0xfff, 0xfff, 0xfff), 667 BLOCK_PRTY_INFO(ATC, 0x1f, 0, 0, 0x1f, 0x1f), 668 BLOCK_PRTY_INFO(PGLUE_B, 0x3, 0, 0, 0x3, 0x3), 669 BLOCK_PRTY_INFO(DORQ, 0, 0x3, 0x3, 0x3, 0x3), 670 {GRCBASE_UPB + PB_REG_PB_PRTY_MASK, 671 GRCBASE_UPB + PB_REG_PB_PRTY_STS_CLR, 0xf, 672 {0xf, 0xf, 0xf, 0xf}, "UPB"}, 673 {GRCBASE_XPB + PB_REG_PB_PRTY_MASK, 674 GRCBASE_XPB + PB_REG_PB_PRTY_STS_CLR, 0, 675 {0xf, 0xf, 0xf, 0xf}, "XPB"}, 676 BLOCK_PRTY_INFO(SRC, 0x4, 0x7, 0x7, 0x7, 0x7), 677 BLOCK_PRTY_INFO(CDU, 0, 0x1f, 0x1f, 0x1f, 0x1f), 678 BLOCK_PRTY_INFO(CFC, 0, 0xf, 0xf, 0xf, 0x3f), 679 BLOCK_PRTY_INFO(DBG, 0, 0x1, 0x1, 0x1, 0x1), 680 BLOCK_PRTY_INFO(DMAE, 0, 0xf, 0xf, 0xf, 0xf), 681 BLOCK_PRTY_INFO(BRB1, 0, 0xf, 0xf, 0xf, 0xf), 682 BLOCK_PRTY_INFO(PRS, (1<<6), 0xff, 0xff, 0xff, 0xff), 683 BLOCK_PRTY_INFO(PBF, 0, 0, 0x3ffff, 0xfffff, 0xfffffff), 684 BLOCK_PRTY_INFO(TM, 0, 0, 0x7f, 0x7f, 0x7f), 685 BLOCK_PRTY_INFO(TSDM, 0x18, 0x7ff, 0x7ff, 0x7ff, 0x7ff), 686 BLOCK_PRTY_INFO(CSDM, 0x8, 0x7ff, 0x7ff, 0x7ff, 0x7ff), 687 BLOCK_PRTY_INFO(USDM, 0x38, 0x7ff, 0x7ff, 0x7ff, 0x7ff), 688 BLOCK_PRTY_INFO(XSDM, 0x8, 0x7ff, 0x7ff, 0x7ff, 0x7ff), 689 BLOCK_PRTY_INFO(TCM, 0, 0, 0x7ffffff, 0x7ffffff, 0x7ffffff), 690 BLOCK_PRTY_INFO(CCM, 0, 0, 0x7ffffff, 0x7ffffff, 0x7ffffff), 691 BLOCK_PRTY_INFO(UCM, 0, 0, 0x7ffffff, 0x7ffffff, 0x7ffffff), 692 BLOCK_PRTY_INFO(XCM, 0, 0, 0x3fffffff, 0x3fffffff, 0x3fffffff), 693 BLOCK_PRTY_INFO_0(TSEM, 0, 0xffffffff, 0xffffffff, 0xffffffff, 694 0xffffffff), 695 BLOCK_PRTY_INFO_1(TSEM, 0, 0x3, 0x1f, 0x3f, 0x3f), 696 BLOCK_PRTY_INFO_0(USEM, 0, 0xffffffff, 0xffffffff, 0xffffffff, 697 0xffffffff), 698 BLOCK_PRTY_INFO_1(USEM, 0, 0x3, 0x1f, 0x1f, 0x1f), 699 BLOCK_PRTY_INFO_0(CSEM, 0, 0xffffffff, 0xffffffff, 0xffffffff, 700 0xffffffff), 701 BLOCK_PRTY_INFO_1(CSEM, 0, 0x3, 0x1f, 0x1f, 0x1f), 702 BLOCK_PRTY_INFO_0(XSEM, 0, 0xffffffff, 0xffffffff, 0xffffffff, 703 0xffffffff), 704 BLOCK_PRTY_INFO_1(XSEM, 0, 0x3, 0x1f, 0x3f, 0x3f), 705 }; 706 707 708 /* [28] MCP Latched rom_parity 709 * [29] MCP Latched ump_rx_parity 710 * [30] MCP Latched ump_tx_parity 711 * [31] MCP Latched scpad_parity 712 */ 713 #define MISC_AEU_ENABLE_MCP_PRTY_SUB_BITS \ 714 (AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | \ 715 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | \ 716 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY) 717 718 #define MISC_AEU_ENABLE_MCP_PRTY_BITS \ 719 (MISC_AEU_ENABLE_MCP_PRTY_SUB_BITS | \ 720 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY) 721 722 /* Below registers control the MCP parity attention output. When 723 * MISC_AEU_ENABLE_MCP_PRTY_BITS are set - attentions are 724 * enabled, when cleared - disabled. 725 */ 726 static const struct { 727 uint32_t addr; 728 uint32_t bits; 729 } mcp_attn_ctl_regs[] = { 730 { MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0, 731 MISC_AEU_ENABLE_MCP_PRTY_BITS }, 732 { MISC_REG_AEU_ENABLE4_NIG_0, 733 MISC_AEU_ENABLE_MCP_PRTY_SUB_BITS }, 734 { MISC_REG_AEU_ENABLE4_PXP_0, 735 MISC_AEU_ENABLE_MCP_PRTY_SUB_BITS }, 736 { MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0, 737 MISC_AEU_ENABLE_MCP_PRTY_BITS }, 738 { MISC_REG_AEU_ENABLE4_NIG_1, 739 MISC_AEU_ENABLE_MCP_PRTY_SUB_BITS }, 740 { MISC_REG_AEU_ENABLE4_PXP_1, 741 MISC_AEU_ENABLE_MCP_PRTY_SUB_BITS } 742 }; 743 744 static inline void ecore_set_mcp_parity(struct bxe_softc *sc, uint8_t enable) 745 { 746 int i; 747 uint32_t reg_val; 748 749 for (i = 0; i < ARRSIZE(mcp_attn_ctl_regs); i++) { 750 reg_val = REG_RD(sc, mcp_attn_ctl_regs[i].addr); 751 752 if (enable) 753 reg_val |= MISC_AEU_ENABLE_MCP_PRTY_BITS; /* Linux is using mcp_attn_ctl_regs[i].bits */ 754 else 755 reg_val &= ~MISC_AEU_ENABLE_MCP_PRTY_BITS; /* Linux is using mcp_attn_ctl_regs[i].bits */ 756 757 REG_WR(sc, mcp_attn_ctl_regs[i].addr, reg_val); 758 } 759 } 760 761 static inline uint32_t ecore_parity_reg_mask(struct bxe_softc *sc, int idx) 762 { 763 if (CHIP_IS_E1(sc)) 764 return ecore_blocks_parity_data[idx].reg_mask.e1; 765 else if (CHIP_IS_E1H(sc)) 766 return ecore_blocks_parity_data[idx].reg_mask.e1h; 767 else if (CHIP_IS_E2(sc)) 768 return ecore_blocks_parity_data[idx].reg_mask.e2; 769 else /* CHIP_IS_E3 */ 770 return ecore_blocks_parity_data[idx].reg_mask.e3; 771 } 772 773 static inline void ecore_disable_blocks_parity(struct bxe_softc *sc) 774 { 775 int i; 776 777 for (i = 0; i < ARRSIZE(ecore_blocks_parity_data); i++) { 778 uint32_t dis_mask = ecore_parity_reg_mask(sc, i); 779 780 if (dis_mask) { 781 REG_WR(sc, ecore_blocks_parity_data[i].mask_addr, 782 dis_mask); 783 ECORE_MSG(sc, "Setting parity mask " 784 "for %s to\t\t0x%x\n", 785 ecore_blocks_parity_data[i].name, dis_mask); 786 } 787 } 788 789 /* Disable MCP parity attentions */ 790 ecore_set_mcp_parity(sc, FALSE); 791 } 792 793 /** 794 * Clear the parity error status registers. 795 */ 796 static inline void ecore_clear_blocks_parity(struct bxe_softc *sc) 797 { 798 int i; 799 uint32_t reg_val, mcp_aeu_bits = 800 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY | 801 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY | 802 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY | 803 AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY; 804 805 /* Clear SEM_FAST parities */ 806 REG_WR(sc, XSEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1); 807 REG_WR(sc, TSEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1); 808 REG_WR(sc, USEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1); 809 REG_WR(sc, CSEM_REG_FAST_MEMORY + SEM_FAST_REG_PARITY_RST, 0x1); 810 811 for (i = 0; i < ARRSIZE(ecore_blocks_parity_data); i++) { 812 uint32_t reg_mask = ecore_parity_reg_mask(sc, i); 813 814 if (reg_mask) { 815 reg_val = REG_RD(sc, ecore_blocks_parity_data[i]. 816 sts_clr_addr); 817 if (reg_val & reg_mask) 818 ECORE_MSG(sc, 819 "Parity errors in %s: 0x%x\n", 820 ecore_blocks_parity_data[i].name, 821 reg_val & reg_mask); 822 } 823 } 824 825 /* Check if there were parity attentions in MCP */ 826 reg_val = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_MCP); 827 if (reg_val & mcp_aeu_bits) 828 ECORE_MSG(sc, "Parity error in MCP: 0x%x\n", 829 reg_val & mcp_aeu_bits); 830 831 /* Clear parity attentions in MCP: 832 * [7] clears Latched rom_parity 833 * [8] clears Latched ump_rx_parity 834 * [9] clears Latched ump_tx_parity 835 * [10] clears Latched scpad_parity (both ports) 836 */ 837 REG_WR(sc, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x780); 838 } 839 840 static inline void ecore_enable_blocks_parity(struct bxe_softc *sc) 841 { 842 int i; 843 844 for (i = 0; i < ARRSIZE(ecore_blocks_parity_data); i++) { 845 uint32_t reg_mask = ecore_parity_reg_mask(sc, i); 846 847 if (reg_mask) 848 REG_WR(sc, ecore_blocks_parity_data[i].mask_addr, 849 ecore_blocks_parity_data[i].en_mask & reg_mask); 850 } 851 852 /* Enable MCP parity attentions */ 853 ecore_set_mcp_parity(sc, TRUE); 854 } 855 856 857 #endif /* ECORE_INIT_H */ 858 859