1 /*- 2 * Copyright (c) 2007-2013 Broadcom Corporation. All rights reserved. 3 * 4 * Eric Davis <edavis@broadcom.com> 5 * David Christensen <davidch@broadcom.com> 6 * Gary Zambrano <zambrano@broadcom.com> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. Neither the name of Broadcom Corporation nor the name of its contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written consent. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' 22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/cdefs.h> 35 __FBSDID("$FreeBSD$"); 36 37 #ifndef ECORE_HSI_H 38 #define ECORE_HSI_H 39 40 #define FW_ENCODE_32BIT_PATTERN 0x1e1e1e1e 41 42 struct license_key { 43 uint32_t reserved[6]; 44 45 uint32_t max_iscsi_conn; 46 #define LICENSE_MAX_ISCSI_TRGT_CONN_MASK 0xFFFF 47 #define LICENSE_MAX_ISCSI_TRGT_CONN_SHIFT 0 48 #define LICENSE_MAX_ISCSI_INIT_CONN_MASK 0xFFFF0000 49 #define LICENSE_MAX_ISCSI_INIT_CONN_SHIFT 16 50 51 uint32_t reserved_a; 52 53 uint32_t max_fcoe_conn; 54 #define LICENSE_MAX_FCOE_TRGT_CONN_MASK 0xFFFF 55 #define LICENSE_MAX_FCOE_TRGT_CONN_SHIFT 0 56 #define LICENSE_MAX_FCOE_INIT_CONN_MASK 0xFFFF0000 57 #define LICENSE_MAX_FCOE_INIT_CONN_SHIFT 16 58 59 uint32_t reserved_b[4]; 60 }; 61 62 typedef struct license_key license_key_t; 63 64 65 /**************************************************************************** 66 * Shared HW configuration * 67 ****************************************************************************/ 68 #define PIN_CFG_NA 0x00000000 69 #define PIN_CFG_GPIO0_P0 0x00000001 70 #define PIN_CFG_GPIO1_P0 0x00000002 71 #define PIN_CFG_GPIO2_P0 0x00000003 72 #define PIN_CFG_GPIO3_P0 0x00000004 73 #define PIN_CFG_GPIO0_P1 0x00000005 74 #define PIN_CFG_GPIO1_P1 0x00000006 75 #define PIN_CFG_GPIO2_P1 0x00000007 76 #define PIN_CFG_GPIO3_P1 0x00000008 77 #define PIN_CFG_EPIO0 0x00000009 78 #define PIN_CFG_EPIO1 0x0000000a 79 #define PIN_CFG_EPIO2 0x0000000b 80 #define PIN_CFG_EPIO3 0x0000000c 81 #define PIN_CFG_EPIO4 0x0000000d 82 #define PIN_CFG_EPIO5 0x0000000e 83 #define PIN_CFG_EPIO6 0x0000000f 84 #define PIN_CFG_EPIO7 0x00000010 85 #define PIN_CFG_EPIO8 0x00000011 86 #define PIN_CFG_EPIO9 0x00000012 87 #define PIN_CFG_EPIO10 0x00000013 88 #define PIN_CFG_EPIO11 0x00000014 89 #define PIN_CFG_EPIO12 0x00000015 90 #define PIN_CFG_EPIO13 0x00000016 91 #define PIN_CFG_EPIO14 0x00000017 92 #define PIN_CFG_EPIO15 0x00000018 93 #define PIN_CFG_EPIO16 0x00000019 94 #define PIN_CFG_EPIO17 0x0000001a 95 #define PIN_CFG_EPIO18 0x0000001b 96 #define PIN_CFG_EPIO19 0x0000001c 97 #define PIN_CFG_EPIO20 0x0000001d 98 #define PIN_CFG_EPIO21 0x0000001e 99 #define PIN_CFG_EPIO22 0x0000001f 100 #define PIN_CFG_EPIO23 0x00000020 101 #define PIN_CFG_EPIO24 0x00000021 102 #define PIN_CFG_EPIO25 0x00000022 103 #define PIN_CFG_EPIO26 0x00000023 104 #define PIN_CFG_EPIO27 0x00000024 105 #define PIN_CFG_EPIO28 0x00000025 106 #define PIN_CFG_EPIO29 0x00000026 107 #define PIN_CFG_EPIO30 0x00000027 108 #define PIN_CFG_EPIO31 0x00000028 109 110 /* EPIO definition */ 111 #define EPIO_CFG_NA 0x00000000 112 #define EPIO_CFG_EPIO0 0x00000001 113 #define EPIO_CFG_EPIO1 0x00000002 114 #define EPIO_CFG_EPIO2 0x00000003 115 #define EPIO_CFG_EPIO3 0x00000004 116 #define EPIO_CFG_EPIO4 0x00000005 117 #define EPIO_CFG_EPIO5 0x00000006 118 #define EPIO_CFG_EPIO6 0x00000007 119 #define EPIO_CFG_EPIO7 0x00000008 120 #define EPIO_CFG_EPIO8 0x00000009 121 #define EPIO_CFG_EPIO9 0x0000000a 122 #define EPIO_CFG_EPIO10 0x0000000b 123 #define EPIO_CFG_EPIO11 0x0000000c 124 #define EPIO_CFG_EPIO12 0x0000000d 125 #define EPIO_CFG_EPIO13 0x0000000e 126 #define EPIO_CFG_EPIO14 0x0000000f 127 #define EPIO_CFG_EPIO15 0x00000010 128 #define EPIO_CFG_EPIO16 0x00000011 129 #define EPIO_CFG_EPIO17 0x00000012 130 #define EPIO_CFG_EPIO18 0x00000013 131 #define EPIO_CFG_EPIO19 0x00000014 132 #define EPIO_CFG_EPIO20 0x00000015 133 #define EPIO_CFG_EPIO21 0x00000016 134 #define EPIO_CFG_EPIO22 0x00000017 135 #define EPIO_CFG_EPIO23 0x00000018 136 #define EPIO_CFG_EPIO24 0x00000019 137 #define EPIO_CFG_EPIO25 0x0000001a 138 #define EPIO_CFG_EPIO26 0x0000001b 139 #define EPIO_CFG_EPIO27 0x0000001c 140 #define EPIO_CFG_EPIO28 0x0000001d 141 #define EPIO_CFG_EPIO29 0x0000001e 142 #define EPIO_CFG_EPIO30 0x0000001f 143 #define EPIO_CFG_EPIO31 0x00000020 144 145 struct mac_addr { 146 uint32_t upper; 147 uint32_t lower; 148 }; 149 150 151 struct shared_hw_cfg { /* NVRAM Offset */ 152 /* Up to 16 bytes of NULL-terminated string */ 153 uint8_t part_num[16]; /* 0x104 */ 154 155 uint32_t config; /* 0x114 */ 156 #define SHARED_HW_CFG_MDIO_VOLTAGE_MASK 0x00000001 157 #define SHARED_HW_CFG_MDIO_VOLTAGE_SHIFT 0 158 #define SHARED_HW_CFG_MDIO_VOLTAGE_1_2V 0x00000000 159 #define SHARED_HW_CFG_MDIO_VOLTAGE_2_5V 0x00000001 160 161 #define SHARED_HW_CFG_PORT_SWAP 0x00000004 162 163 #define SHARED_HW_CFG_BEACON_WOL_EN 0x00000008 164 165 #define SHARED_HW_CFG_PCIE_GEN3_DISABLED 0x00000000 166 #define SHARED_HW_CFG_PCIE_GEN3_ENABLED 0x00000010 167 168 #define SHARED_HW_CFG_MFW_SELECT_MASK 0x00000700 169 #define SHARED_HW_CFG_MFW_SELECT_SHIFT 8 170 /* Whatever MFW found in NVM 171 (if multiple found, priority order is: NC-SI, UMP, IPMI) */ 172 #define SHARED_HW_CFG_MFW_SELECT_DEFAULT 0x00000000 173 #define SHARED_HW_CFG_MFW_SELECT_NC_SI 0x00000100 174 #define SHARED_HW_CFG_MFW_SELECT_UMP 0x00000200 175 #define SHARED_HW_CFG_MFW_SELECT_IPMI 0x00000300 176 /* Use SPIO4 as an arbiter between: 0-NC_SI, 1-IPMI 177 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */ 178 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_IPMI 0x00000400 179 /* Use SPIO4 as an arbiter between: 0-UMP, 1-IPMI 180 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */ 181 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_UMP_IPMI 0x00000500 182 /* Use SPIO4 as an arbiter between: 0-NC-SI, 1-UMP 183 (can only be used when an add-in board, not BMC, pulls-down SPIO4) */ 184 #define SHARED_HW_CFG_MFW_SELECT_SPIO4_NC_SI_UMP 0x00000600 185 186 /* Adjust the PCIe G2 Tx amplitude driver for all Tx lanes. For 187 backwards compatibility, value of 0 is disabling this feature. 188 That means that though 0 is a valid value, it cannot be 189 configured. */ 190 #define SHARED_HW_CFG_G2_TX_DRIVE_MASK 0x0000F000 191 #define SHARED_HW_CFG_G2_TX_DRIVE_SHIFT 12 192 193 #define SHARED_HW_CFG_LED_MODE_MASK 0x000F0000 194 #define SHARED_HW_CFG_LED_MODE_SHIFT 16 195 #define SHARED_HW_CFG_LED_MAC1 0x00000000 196 #define SHARED_HW_CFG_LED_PHY1 0x00010000 197 #define SHARED_HW_CFG_LED_PHY2 0x00020000 198 #define SHARED_HW_CFG_LED_PHY3 0x00030000 199 #define SHARED_HW_CFG_LED_MAC2 0x00040000 200 #define SHARED_HW_CFG_LED_PHY4 0x00050000 201 #define SHARED_HW_CFG_LED_PHY5 0x00060000 202 #define SHARED_HW_CFG_LED_PHY6 0x00070000 203 #define SHARED_HW_CFG_LED_MAC3 0x00080000 204 #define SHARED_HW_CFG_LED_PHY7 0x00090000 205 #define SHARED_HW_CFG_LED_PHY9 0x000a0000 206 #define SHARED_HW_CFG_LED_PHY11 0x000b0000 207 #define SHARED_HW_CFG_LED_MAC4 0x000c0000 208 #define SHARED_HW_CFG_LED_PHY8 0x000d0000 209 #define SHARED_HW_CFG_LED_EXTPHY1 0x000e0000 210 #define SHARED_HW_CFG_LED_EXTPHY2 0x000f0000 211 212 #define SHARED_HW_CFG_SRIOV_MASK 0x40000000 213 #define SHARED_HW_CFG_SRIOV_DISABLED 0x00000000 214 #define SHARED_HW_CFG_SRIOV_ENABLED 0x40000000 215 216 #define SHARED_HW_CFG_ATC_MASK 0x80000000 217 #define SHARED_HW_CFG_ATC_DISABLED 0x00000000 218 #define SHARED_HW_CFG_ATC_ENABLED 0x80000000 219 220 uint32_t config2; /* 0x118 */ 221 222 #define SHARED_HW_CFG_PCIE_GEN2_MASK 0x00000100 223 #define SHARED_HW_CFG_PCIE_GEN2_SHIFT 8 224 #define SHARED_HW_CFG_PCIE_GEN2_DISABLED 0x00000000 225 #define SHARED_HW_CFG_PCIE_GEN2_ENABLED 0x00000100 226 227 #define SHARED_HW_CFG_SMBUS_TIMING_MASK 0x00001000 228 #define SHARED_HW_CFG_SMBUS_TIMING_100KHZ 0x00000000 229 #define SHARED_HW_CFG_SMBUS_TIMING_400KHZ 0x00001000 230 231 #define SHARED_HW_CFG_HIDE_PORT1 0x00002000 232 233 234 /* Output low when PERST is asserted */ 235 #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_MASK 0x00008000 236 #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_DISABLED 0x00000000 237 #define SHARED_HW_CFG_SPIO4_FOLLOW_PERST_ENABLED 0x00008000 238 239 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_MASK 0x00070000 240 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_SHIFT 16 241 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_HW 0x00000000 242 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_0DB 0x00010000 243 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_3_5DB 0x00020000 244 #define SHARED_HW_CFG_PCIE_GEN2_PREEMPHASIS_6_0DB 0x00030000 245 246 /* The fan failure mechanism is usually related to the PHY type 247 since the power consumption of the board is determined by the PHY. 248 Currently, fan is required for most designs with SFX7101, BCM8727 249 and BCM8481. If a fan is not required for a board which uses one 250 of those PHYs, this field should be set to "Disabled". If a fan is 251 required for a different PHY type, this option should be set to 252 "Enabled". The fan failure indication is expected on SPIO5 */ 253 #define SHARED_HW_CFG_FAN_FAILURE_MASK 0x00180000 254 #define SHARED_HW_CFG_FAN_FAILURE_SHIFT 19 255 #define SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE 0x00000000 256 #define SHARED_HW_CFG_FAN_FAILURE_DISABLED 0x00080000 257 #define SHARED_HW_CFG_FAN_FAILURE_ENABLED 0x00100000 258 259 /* ASPM Power Management support */ 260 #define SHARED_HW_CFG_ASPM_SUPPORT_MASK 0x00600000 261 #define SHARED_HW_CFG_ASPM_SUPPORT_SHIFT 21 262 #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_L1_ENABLED 0x00000000 263 #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_DISABLED 0x00200000 264 #define SHARED_HW_CFG_ASPM_SUPPORT_L1_DISABLED 0x00400000 265 #define SHARED_HW_CFG_ASPM_SUPPORT_L0S_L1_DISABLED 0x00600000 266 267 /* The value of PM_TL_IGNORE_REQS (bit0) in PCI register 268 tl_control_0 (register 0x2800) */ 269 #define SHARED_HW_CFG_PREVENT_L1_ENTRY_MASK 0x00800000 270 #define SHARED_HW_CFG_PREVENT_L1_ENTRY_DISABLED 0x00000000 271 #define SHARED_HW_CFG_PREVENT_L1_ENTRY_ENABLED 0x00800000 272 273 274 /* Set the MDC/MDIO access for the first external phy */ 275 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK 0x1C000000 276 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT 26 277 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE 0x00000000 278 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0 0x04000000 279 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1 0x08000000 280 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH 0x0c000000 281 #define SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED 0x10000000 282 283 /* Set the MDC/MDIO access for the second external phy */ 284 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK 0xE0000000 285 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT 29 286 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_PHY_TYPE 0x00000000 287 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC0 0x20000000 288 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_EMAC1 0x40000000 289 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_BOTH 0x60000000 290 #define SHARED_HW_CFG_MDC_MDIO_ACCESS2_SWAPPED 0x80000000 291 292 /* Max number of PF MSIX vectors */ 293 uint32_t config_3; /* 0x11C */ 294 #define SHARED_HW_CFG_PF_MSIX_MAX_NUM_MASK 0x0000007F 295 #define SHARED_HW_CFG_PF_MSIX_MAX_NUM_SHIFT 0 296 297 uint32_t ump_nc_si_config; /* 0x120 */ 298 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MASK 0x00000003 299 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_SHIFT 0 300 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MAC 0x00000000 301 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_PHY 0x00000001 302 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_MII 0x00000000 303 #define SHARED_HW_CFG_UMP_NC_SI_MII_MODE_RMII 0x00000002 304 305 /* Reserved bits: 226-230 */ 306 307 /* The output pin template BSC_SEL which selects the I2C for this 308 port in the I2C Mux */ 309 uint32_t board; /* 0x124 */ 310 #define SHARED_HW_CFG_E3_I2C_MUX0_MASK 0x0000003F 311 #define SHARED_HW_CFG_E3_I2C_MUX0_SHIFT 0 312 313 #define SHARED_HW_CFG_E3_I2C_MUX1_MASK 0x00000FC0 314 #define SHARED_HW_CFG_E3_I2C_MUX1_SHIFT 6 315 /* Use the PIN_CFG_XXX defines on top */ 316 #define SHARED_HW_CFG_BOARD_REV_MASK 0x00FF0000 317 #define SHARED_HW_CFG_BOARD_REV_SHIFT 16 318 319 #define SHARED_HW_CFG_BOARD_MAJOR_VER_MASK 0x0F000000 320 #define SHARED_HW_CFG_BOARD_MAJOR_VER_SHIFT 24 321 322 #define SHARED_HW_CFG_BOARD_MINOR_VER_MASK 0xF0000000 323 #define SHARED_HW_CFG_BOARD_MINOR_VER_SHIFT 28 324 325 uint32_t wc_lane_config; /* 0x128 */ 326 #define SHARED_HW_CFG_LANE_SWAP_CFG_MASK 0x0000FFFF 327 #define SHARED_HW_CFG_LANE_SWAP_CFG_SHIFT 0 328 #define SHARED_HW_CFG_LANE_SWAP_CFG_32103210 0x00001b1b 329 #define SHARED_HW_CFG_LANE_SWAP_CFG_32100123 0x00001be4 330 #define SHARED_HW_CFG_LANE_SWAP_CFG_31200213 0x000027d8 331 #define SHARED_HW_CFG_LANE_SWAP_CFG_02133120 0x0000d827 332 #define SHARED_HW_CFG_LANE_SWAP_CFG_01233210 0x0000e41b 333 #define SHARED_HW_CFG_LANE_SWAP_CFG_01230123 0x0000e4e4 334 #define SHARED_HW_CFG_LANE_SWAP_CFG_TX_MASK 0x000000FF 335 #define SHARED_HW_CFG_LANE_SWAP_CFG_TX_SHIFT 0 336 #define SHARED_HW_CFG_LANE_SWAP_CFG_RX_MASK 0x0000FF00 337 #define SHARED_HW_CFG_LANE_SWAP_CFG_RX_SHIFT 8 338 339 /* TX lane Polarity swap */ 340 #define SHARED_HW_CFG_TX_LANE0_POL_FLIP_ENABLED 0x00010000 341 #define SHARED_HW_CFG_TX_LANE1_POL_FLIP_ENABLED 0x00020000 342 #define SHARED_HW_CFG_TX_LANE2_POL_FLIP_ENABLED 0x00040000 343 #define SHARED_HW_CFG_TX_LANE3_POL_FLIP_ENABLED 0x00080000 344 /* TX lane Polarity swap */ 345 #define SHARED_HW_CFG_RX_LANE0_POL_FLIP_ENABLED 0x00100000 346 #define SHARED_HW_CFG_RX_LANE1_POL_FLIP_ENABLED 0x00200000 347 #define SHARED_HW_CFG_RX_LANE2_POL_FLIP_ENABLED 0x00400000 348 #define SHARED_HW_CFG_RX_LANE3_POL_FLIP_ENABLED 0x00800000 349 350 /* Selects the port layout of the board */ 351 #define SHARED_HW_CFG_E3_PORT_LAYOUT_MASK 0x0F000000 352 #define SHARED_HW_CFG_E3_PORT_LAYOUT_SHIFT 24 353 #define SHARED_HW_CFG_E3_PORT_LAYOUT_2P_01 0x00000000 354 #define SHARED_HW_CFG_E3_PORT_LAYOUT_2P_10 0x01000000 355 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_0123 0x02000000 356 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_1032 0x03000000 357 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_2301 0x04000000 358 #define SHARED_HW_CFG_E3_PORT_LAYOUT_4P_3210 0x05000000 359 }; 360 361 362 /**************************************************************************** 363 * Port HW configuration * 364 ****************************************************************************/ 365 struct port_hw_cfg { /* port 0: 0x12c port 1: 0x2bc */ 366 367 uint32_t pci_id; 368 #define PORT_HW_CFG_PCI_DEVICE_ID_MASK 0x0000FFFF 369 #define PORT_HW_CFG_PCI_DEVICE_ID_SHIFT 0 370 371 #define PORT_HW_CFG_PCI_VENDOR_ID_MASK 0xFFFF0000 372 #define PORT_HW_CFG_PCI_VENDOR_ID_SHIFT 16 373 374 uint32_t pci_sub_id; 375 #define PORT_HW_CFG_PCI_SUBSYS_VENDOR_ID_MASK 0x0000FFFF 376 #define PORT_HW_CFG_PCI_SUBSYS_VENDOR_ID_SHIFT 0 377 378 #define PORT_HW_CFG_PCI_SUBSYS_DEVICE_ID_MASK 0xFFFF0000 379 #define PORT_HW_CFG_PCI_SUBSYS_DEVICE_ID_SHIFT 16 380 381 uint32_t power_dissipated; 382 #define PORT_HW_CFG_POWER_DIS_D0_MASK 0x000000FF 383 #define PORT_HW_CFG_POWER_DIS_D0_SHIFT 0 384 #define PORT_HW_CFG_POWER_DIS_D1_MASK 0x0000FF00 385 #define PORT_HW_CFG_POWER_DIS_D1_SHIFT 8 386 #define PORT_HW_CFG_POWER_DIS_D2_MASK 0x00FF0000 387 #define PORT_HW_CFG_POWER_DIS_D2_SHIFT 16 388 #define PORT_HW_CFG_POWER_DIS_D3_MASK 0xFF000000 389 #define PORT_HW_CFG_POWER_DIS_D3_SHIFT 24 390 391 uint32_t power_consumed; 392 #define PORT_HW_CFG_POWER_CONS_D0_MASK 0x000000FF 393 #define PORT_HW_CFG_POWER_CONS_D0_SHIFT 0 394 #define PORT_HW_CFG_POWER_CONS_D1_MASK 0x0000FF00 395 #define PORT_HW_CFG_POWER_CONS_D1_SHIFT 8 396 #define PORT_HW_CFG_POWER_CONS_D2_MASK 0x00FF0000 397 #define PORT_HW_CFG_POWER_CONS_D2_SHIFT 16 398 #define PORT_HW_CFG_POWER_CONS_D3_MASK 0xFF000000 399 #define PORT_HW_CFG_POWER_CONS_D3_SHIFT 24 400 401 uint32_t mac_upper; 402 uint32_t mac_lower; /* 0x140 */ 403 #define PORT_HW_CFG_UPPERMAC_MASK 0x0000FFFF 404 #define PORT_HW_CFG_UPPERMAC_SHIFT 0 405 406 407 uint32_t iscsi_mac_upper; /* Upper 16 bits are always zeroes */ 408 uint32_t iscsi_mac_lower; 409 410 uint32_t rdma_mac_upper; /* Upper 16 bits are always zeroes */ 411 uint32_t rdma_mac_lower; 412 413 uint32_t serdes_config; 414 #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_MASK 0x0000FFFF 415 #define PORT_HW_CFG_SERDES_TX_DRV_PRE_EMPHASIS_SHIFT 0 416 417 #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_MASK 0xFFFF0000 418 #define PORT_HW_CFG_SERDES_RX_DRV_EQUALIZER_SHIFT 16 419 420 421 /* Default values: 2P-64, 4P-32 */ 422 uint32_t reserved; 423 424 uint32_t vf_config; /* 0x15C */ 425 #define PORT_HW_CFG_VF_PCI_DEVICE_ID_MASK 0xFFFF0000 426 #define PORT_HW_CFG_VF_PCI_DEVICE_ID_SHIFT 16 427 428 uint32_t mf_pci_id; /* 0x160 */ 429 #define PORT_HW_CFG_MF_PCI_DEVICE_ID_MASK 0x0000FFFF 430 #define PORT_HW_CFG_MF_PCI_DEVICE_ID_SHIFT 0 431 432 /* Controls the TX laser of the SFP+ module */ 433 uint32_t sfp_ctrl; /* 0x164 */ 434 #define PORT_HW_CFG_TX_LASER_MASK 0x000000FF 435 #define PORT_HW_CFG_TX_LASER_SHIFT 0 436 #define PORT_HW_CFG_TX_LASER_MDIO 0x00000000 437 #define PORT_HW_CFG_TX_LASER_GPIO0 0x00000001 438 #define PORT_HW_CFG_TX_LASER_GPIO1 0x00000002 439 #define PORT_HW_CFG_TX_LASER_GPIO2 0x00000003 440 #define PORT_HW_CFG_TX_LASER_GPIO3 0x00000004 441 442 /* Controls the fault module LED of the SFP+ */ 443 #define PORT_HW_CFG_FAULT_MODULE_LED_MASK 0x0000FF00 444 #define PORT_HW_CFG_FAULT_MODULE_LED_SHIFT 8 445 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO0 0x00000000 446 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO1 0x00000100 447 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO2 0x00000200 448 #define PORT_HW_CFG_FAULT_MODULE_LED_GPIO3 0x00000300 449 #define PORT_HW_CFG_FAULT_MODULE_LED_DISABLED 0x00000400 450 451 /* The output pin TX_DIS that controls the TX laser of the SFP+ 452 module. Use the PIN_CFG_XXX defines on top */ 453 uint32_t e3_sfp_ctrl; /* 0x168 */ 454 #define PORT_HW_CFG_E3_TX_LASER_MASK 0x000000FF 455 #define PORT_HW_CFG_E3_TX_LASER_SHIFT 0 456 457 /* The output pin for SFPP_TYPE which turns on the Fault module LED */ 458 #define PORT_HW_CFG_E3_FAULT_MDL_LED_MASK 0x0000FF00 459 #define PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT 8 460 461 /* The input pin MOD_ABS that indicates whether SFP+ module is 462 present or not. Use the PIN_CFG_XXX defines on top */ 463 #define PORT_HW_CFG_E3_MOD_ABS_MASK 0x00FF0000 464 #define PORT_HW_CFG_E3_MOD_ABS_SHIFT 16 465 466 /* The output pin PWRDIS_SFP_X which disable the power of the SFP+ 467 module. Use the PIN_CFG_XXX defines on top */ 468 #define PORT_HW_CFG_E3_PWR_DIS_MASK 0xFF000000 469 #define PORT_HW_CFG_E3_PWR_DIS_SHIFT 24 470 471 /* 472 * The input pin which signals module transmit fault. Use the 473 * PIN_CFG_XXX defines on top 474 */ 475 uint32_t e3_cmn_pin_cfg; /* 0x16C */ 476 #define PORT_HW_CFG_E3_TX_FAULT_MASK 0x000000FF 477 #define PORT_HW_CFG_E3_TX_FAULT_SHIFT 0 478 479 /* The output pin which reset the PHY. Use the PIN_CFG_XXX defines on 480 top */ 481 #define PORT_HW_CFG_E3_PHY_RESET_MASK 0x0000FF00 482 #define PORT_HW_CFG_E3_PHY_RESET_SHIFT 8 483 484 /* 485 * The output pin which powers down the PHY. Use the PIN_CFG_XXX 486 * defines on top 487 */ 488 #define PORT_HW_CFG_E3_PWR_DOWN_MASK 0x00FF0000 489 #define PORT_HW_CFG_E3_PWR_DOWN_SHIFT 16 490 491 /* The output pin values BSC_SEL which selects the I2C for this port 492 in the I2C Mux */ 493 #define PORT_HW_CFG_E3_I2C_MUX0_MASK 0x01000000 494 #define PORT_HW_CFG_E3_I2C_MUX1_MASK 0x02000000 495 496 497 /* 498 * The input pin I_FAULT which indicate over-current has occurred. 499 * Use the PIN_CFG_XXX defines on top 500 */ 501 uint32_t e3_cmn_pin_cfg1; /* 0x170 */ 502 #define PORT_HW_CFG_E3_OVER_CURRENT_MASK 0x000000FF 503 #define PORT_HW_CFG_E3_OVER_CURRENT_SHIFT 0 504 505 /* pause on host ring */ 506 uint32_t generic_features; /* 0x174 */ 507 #define PORT_HW_CFG_PAUSE_ON_HOST_RING_MASK 0x00000001 508 #define PORT_HW_CFG_PAUSE_ON_HOST_RING_SHIFT 0 509 #define PORT_HW_CFG_PAUSE_ON_HOST_RING_DISABLED 0x00000000 510 #define PORT_HW_CFG_PAUSE_ON_HOST_RING_ENABLED 0x00000001 511 512 /* SFP+ Tx Equalization: NIC recommended and tested value is 0xBEB2 513 * LOM recommended and tested value is 0xBEB2. Using a different 514 * value means using a value not tested by BRCM 515 */ 516 uint32_t sfi_tap_values; /* 0x178 */ 517 #define PORT_HW_CFG_TX_EQUALIZATION_MASK 0x0000FFFF 518 #define PORT_HW_CFG_TX_EQUALIZATION_SHIFT 0 519 520 /* SFP+ Tx driver broadcast IDRIVER: NIC recommended and tested 521 * value is 0x2. LOM recommended and tested value is 0x2. Using a 522 * different value means using a value not tested by BRCM 523 */ 524 #define PORT_HW_CFG_TX_DRV_BROADCAST_MASK 0x000F0000 525 #define PORT_HW_CFG_TX_DRV_BROADCAST_SHIFT 16 526 527 uint32_t reserved0[5]; /* 0x17c */ 528 529 uint32_t aeu_int_mask; /* 0x190 */ 530 531 uint32_t media_type; /* 0x194 */ 532 #define PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK 0x000000FF 533 #define PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT 0 534 535 #define PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK 0x0000FF00 536 #define PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT 8 537 538 #define PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK 0x00FF0000 539 #define PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT 16 540 541 /* 4 times 16 bits for all 4 lanes. In case external PHY is present 542 (not direct mode), those values will not take effect on the 4 XGXS 543 lanes. For some external PHYs (such as 8706 and 8726) the values 544 will be used to configure the external PHY in those cases, not 545 all 4 values are needed. */ 546 uint16_t xgxs_config_rx[4]; /* 0x198 */ 547 uint16_t xgxs_config_tx[4]; /* 0x1A0 */ 548 549 550 /* For storing FCOE mac on shared memory */ 551 uint32_t fcoe_fip_mac_upper; 552 #define PORT_HW_CFG_FCOE_UPPERMAC_MASK 0x0000ffff 553 #define PORT_HW_CFG_FCOE_UPPERMAC_SHIFT 0 554 uint32_t fcoe_fip_mac_lower; 555 556 uint32_t fcoe_wwn_port_name_upper; 557 uint32_t fcoe_wwn_port_name_lower; 558 559 uint32_t fcoe_wwn_node_name_upper; 560 uint32_t fcoe_wwn_node_name_lower; 561 562 /* wwpn for npiv enabled */ 563 uint32_t wwpn_for_npiv_config; /* 0x1C0 */ 564 #define PORT_HW_CFG_WWPN_FOR_NPIV_ENABLED_MASK 0x00000001 565 #define PORT_HW_CFG_WWPN_FOR_NPIV_ENABLED_SHIFT 0 566 #define PORT_HW_CFG_WWPN_FOR_NPIV_ENABLED_DISABLED 0x00000000 567 #define PORT_HW_CFG_WWPN_FOR_NPIV_ENABLED_ENABLED 0x00000001 568 569 /* wwpn for npiv valid addresses */ 570 uint32_t wwpn_for_npiv_valid_addresses; /* 0x1C4 */ 571 #define PORT_HW_CFG_WWPN_FOR_NPIV_ADDRESS_BITMAP_MASK 0x0000FFFF 572 #define PORT_HW_CFG_WWPN_FOR_NPIV_ADDRESS_BITMAP_SHIFT 0 573 574 struct mac_addr wwpn_for_niv_macs[16]; 575 576 /* Reserved bits: 2272-2336 For storing FCOE mac on shared memory */ 577 uint32_t Reserved1[14]; 578 579 uint32_t pf_allocation; /* 0x280 */ 580 /* number of vfs per PF, if 0 - sriov disabled */ 581 #define PORT_HW_CFG_NUMBER_OF_VFS_MASK 0x000000FF 582 #define PORT_HW_CFG_NUMBER_OF_VFS_SHIFT 0 583 584 /* Enable RJ45 magjack pair swapping on 10GBase-T PHY (0=default), 585 84833 only */ 586 uint32_t xgbt_phy_cfg; /* 0x284 */ 587 #define PORT_HW_CFG_RJ45_PAIR_SWAP_MASK 0x000000FF 588 #define PORT_HW_CFG_RJ45_PAIR_SWAP_SHIFT 0 589 590 uint32_t default_cfg; /* 0x288 */ 591 #define PORT_HW_CFG_GPIO0_CONFIG_MASK 0x00000003 592 #define PORT_HW_CFG_GPIO0_CONFIG_SHIFT 0 593 #define PORT_HW_CFG_GPIO0_CONFIG_NA 0x00000000 594 #define PORT_HW_CFG_GPIO0_CONFIG_LOW 0x00000001 595 #define PORT_HW_CFG_GPIO0_CONFIG_HIGH 0x00000002 596 #define PORT_HW_CFG_GPIO0_CONFIG_INPUT 0x00000003 597 598 #define PORT_HW_CFG_GPIO1_CONFIG_MASK 0x0000000C 599 #define PORT_HW_CFG_GPIO1_CONFIG_SHIFT 2 600 #define PORT_HW_CFG_GPIO1_CONFIG_NA 0x00000000 601 #define PORT_HW_CFG_GPIO1_CONFIG_LOW 0x00000004 602 #define PORT_HW_CFG_GPIO1_CONFIG_HIGH 0x00000008 603 #define PORT_HW_CFG_GPIO1_CONFIG_INPUT 0x0000000c 604 605 #define PORT_HW_CFG_GPIO2_CONFIG_MASK 0x00000030 606 #define PORT_HW_CFG_GPIO2_CONFIG_SHIFT 4 607 #define PORT_HW_CFG_GPIO2_CONFIG_NA 0x00000000 608 #define PORT_HW_CFG_GPIO2_CONFIG_LOW 0x00000010 609 #define PORT_HW_CFG_GPIO2_CONFIG_HIGH 0x00000020 610 #define PORT_HW_CFG_GPIO2_CONFIG_INPUT 0x00000030 611 612 #define PORT_HW_CFG_GPIO3_CONFIG_MASK 0x000000C0 613 #define PORT_HW_CFG_GPIO3_CONFIG_SHIFT 6 614 #define PORT_HW_CFG_GPIO3_CONFIG_NA 0x00000000 615 #define PORT_HW_CFG_GPIO3_CONFIG_LOW 0x00000040 616 #define PORT_HW_CFG_GPIO3_CONFIG_HIGH 0x00000080 617 #define PORT_HW_CFG_GPIO3_CONFIG_INPUT 0x000000c0 618 619 /* When KR link is required to be set to force which is not 620 KR-compliant, this parameter determine what is the trigger for it. 621 When GPIO is selected, low input will force the speed. Currently 622 default speed is 1G. In the future, it may be widen to select the 623 forced speed in with another parameter. Note when force-1G is 624 enabled, it override option 56: Link Speed option. */ 625 #define PORT_HW_CFG_FORCE_KR_ENABLER_MASK 0x00000F00 626 #define PORT_HW_CFG_FORCE_KR_ENABLER_SHIFT 8 627 #define PORT_HW_CFG_FORCE_KR_ENABLER_NOT_FORCED 0x00000000 628 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO0_P0 0x00000100 629 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO1_P0 0x00000200 630 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO2_P0 0x00000300 631 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO3_P0 0x00000400 632 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO0_P1 0x00000500 633 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO1_P1 0x00000600 634 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO2_P1 0x00000700 635 #define PORT_HW_CFG_FORCE_KR_ENABLER_GPIO3_P1 0x00000800 636 #define PORT_HW_CFG_FORCE_KR_ENABLER_FORCED 0x00000900 637 /* Enable to determine with which GPIO to reset the external phy */ 638 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK 0x000F0000 639 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT 16 640 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_PHY_TYPE 0x00000000 641 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0 0x00010000 642 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0 0x00020000 643 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0 0x00030000 644 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0 0x00040000 645 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1 0x00050000 646 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1 0x00060000 647 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1 0x00070000 648 #define PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1 0x00080000 649 650 /* Enable BAM on KR */ 651 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_MASK 0x00100000 652 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_SHIFT 20 653 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_DISABLED 0x00000000 654 #define PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED 0x00100000 655 656 /* Enable Common Mode Sense */ 657 #define PORT_HW_CFG_ENABLE_CMS_MASK 0x00200000 658 #define PORT_HW_CFG_ENABLE_CMS_SHIFT 21 659 #define PORT_HW_CFG_ENABLE_CMS_DISABLED 0x00000000 660 #define PORT_HW_CFG_ENABLE_CMS_ENABLED 0x00200000 661 662 /* Determine the Serdes electrical interface */ 663 #define PORT_HW_CFG_NET_SERDES_IF_MASK 0x0F000000 664 #define PORT_HW_CFG_NET_SERDES_IF_SHIFT 24 665 #define PORT_HW_CFG_NET_SERDES_IF_SGMII 0x00000000 666 #define PORT_HW_CFG_NET_SERDES_IF_XFI 0x01000000 667 #define PORT_HW_CFG_NET_SERDES_IF_SFI 0x02000000 668 #define PORT_HW_CFG_NET_SERDES_IF_KR 0x03000000 669 #define PORT_HW_CFG_NET_SERDES_IF_DXGXS 0x04000000 670 #define PORT_HW_CFG_NET_SERDES_IF_KR2 0x05000000 671 672 /* SFP+ main TAP and post TAP volumes */ 673 #define PORT_HW_CFG_TAP_LEVELS_MASK 0x70000000 674 #define PORT_HW_CFG_TAP_LEVELS_SHIFT 28 675 #define PORT_HW_CFG_TAP_LEVELS_POST_15_MAIN_43 0x00000000 676 #define PORT_HW_CFG_TAP_LEVELS_POST_14_MAIN_44 0x10000000 677 #define PORT_HW_CFG_TAP_LEVELS_POST_13_MAIN_45 0x20000000 678 #define PORT_HW_CFG_TAP_LEVELS_POST_12_MAIN_46 0x30000000 679 #define PORT_HW_CFG_TAP_LEVELS_POST_11_MAIN_47 0x40000000 680 #define PORT_HW_CFG_TAP_LEVELS_POST_10_MAIN_48 0x50000000 681 682 uint32_t speed_capability_mask2; /* 0x28C */ 683 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_MASK 0x0000FFFF 684 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_SHIFT 0 685 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10M_FULL 0x00000001 686 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10M_HALF 0x00000002 687 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_100M_HALF 0x00000004 688 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_100M_FULL 0x00000008 689 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_1G 0x00000010 690 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_2_5G 0x00000020 691 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_10G 0x00000040 692 #define PORT_HW_CFG_SPEED_CAPABILITY2_D3_20G 0x00000080 693 694 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_MASK 0xFFFF0000 695 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_SHIFT 16 696 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10M_FULL 0x00010000 697 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10M_HALF 0x00020000 698 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_100M_HALF 0x00040000 699 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_100M_FULL 0x00080000 700 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_1G 0x00100000 701 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_2_5G 0x00200000 702 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_10G 0x00400000 703 #define PORT_HW_CFG_SPEED_CAPABILITY2_D0_20G 0x00800000 704 705 706 /* In the case where two media types (e.g. copper and fiber) are 707 present and electrically active at the same time, PHY Selection 708 will determine which of the two PHYs will be designated as the 709 Active PHY and used for a connection to the network. */ 710 uint32_t multi_phy_config; /* 0x290 */ 711 #define PORT_HW_CFG_PHY_SELECTION_MASK 0x00000007 712 #define PORT_HW_CFG_PHY_SELECTION_SHIFT 0 713 #define PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT 0x00000000 714 #define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY 0x00000001 715 #define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY 0x00000002 716 #define PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY 0x00000003 717 #define PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY 0x00000004 718 719 /* When enabled, all second phy nvram parameters will be swapped 720 with the first phy parameters */ 721 #define PORT_HW_CFG_PHY_SWAPPED_MASK 0x00000008 722 #define PORT_HW_CFG_PHY_SWAPPED_SHIFT 3 723 #define PORT_HW_CFG_PHY_SWAPPED_DISABLED 0x00000000 724 #define PORT_HW_CFG_PHY_SWAPPED_ENABLED 0x00000008 725 726 727 /* Address of the second external phy */ 728 uint32_t external_phy_config2; /* 0x294 */ 729 #define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_MASK 0x000000FF 730 #define PORT_HW_CFG_XGXS_EXT_PHY2_ADDR_SHIFT 0 731 732 /* The second XGXS external PHY type */ 733 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_MASK 0x0000FF00 734 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SHIFT 8 735 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_DIRECT 0x00000000 736 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8071 0x00000100 737 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8072 0x00000200 738 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8073 0x00000300 739 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8705 0x00000400 740 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8706 0x00000500 741 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8726 0x00000600 742 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8481 0x00000700 743 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_SFX7101 0x00000800 744 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727 0x00000900 745 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8727_NOC 0x00000a00 746 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84823 0x00000b00 747 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54640 0x00000c00 748 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84833 0x00000d00 749 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54618SE 0x00000e00 750 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM8722 0x00000f00 751 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM54616 0x00001000 752 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_BCM84834 0x00001100 753 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_FAILURE 0x0000fd00 754 #define PORT_HW_CFG_XGXS_EXT_PHY2_TYPE_NOT_CONN 0x0000ff00 755 756 757 /* 4 times 16 bits for all 4 lanes. For some external PHYs (such as 758 8706, 8726 and 8727) not all 4 values are needed. */ 759 uint16_t xgxs_config2_rx[4]; /* 0x296 */ 760 uint16_t xgxs_config2_tx[4]; /* 0x2A0 */ 761 762 uint32_t lane_config; 763 #define PORT_HW_CFG_LANE_SWAP_CFG_MASK 0x0000FFFF 764 #define PORT_HW_CFG_LANE_SWAP_CFG_SHIFT 0 765 /* AN and forced */ 766 #define PORT_HW_CFG_LANE_SWAP_CFG_01230123 0x00001b1b 767 /* forced only */ 768 #define PORT_HW_CFG_LANE_SWAP_CFG_01233210 0x00001be4 769 /* forced only */ 770 #define PORT_HW_CFG_LANE_SWAP_CFG_31203120 0x0000d8d8 771 /* forced only */ 772 #define PORT_HW_CFG_LANE_SWAP_CFG_32103210 0x0000e4e4 773 #define PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK 0x000000FF 774 #define PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT 0 775 #define PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK 0x0000FF00 776 #define PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT 8 777 #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK 0x0000C000 778 #define PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT 14 779 780 /* Indicate whether to swap the external phy polarity */ 781 #define PORT_HW_CFG_SWAP_PHY_POLARITY_MASK 0x00010000 782 #define PORT_HW_CFG_SWAP_PHY_POLARITY_DISABLED 0x00000000 783 #define PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED 0x00010000 784 785 786 uint32_t external_phy_config; 787 #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK 0x000000FF 788 #define PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT 0 789 790 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK 0x0000FF00 791 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SHIFT 8 792 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT 0x00000000 793 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8071 0x00000100 794 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8072 0x00000200 795 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073 0x00000300 796 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705 0x00000400 797 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706 0x00000500 798 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726 0x00000600 799 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481 0x00000700 800 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101 0x00000800 801 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727 0x00000900 802 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC 0x00000a00 803 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823 0x00000b00 804 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54640 0x00000c00 805 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833 0x00000d00 806 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE 0x00000e00 807 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722 0x00000f00 808 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616 0x00001000 809 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834 0x00001100 810 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT_WC 0x0000fc00 811 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE 0x0000fd00 812 #define PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN 0x0000ff00 813 814 #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_MASK 0x00FF0000 815 #define PORT_HW_CFG_SERDES_EXT_PHY_ADDR_SHIFT 16 816 817 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK 0xFF000000 818 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_SHIFT 24 819 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT 0x00000000 820 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_BCM5482 0x01000000 821 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD 0x02000000 822 #define PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN 0xff000000 823 824 uint32_t speed_capability_mask; 825 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_MASK 0x0000FFFF 826 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_SHIFT 0 827 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_FULL 0x00000001 828 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10M_HALF 0x00000002 829 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_HALF 0x00000004 830 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_100M_FULL 0x00000008 831 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_1G 0x00000010 832 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_2_5G 0x00000020 833 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_10G 0x00000040 834 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_20G 0x00000080 835 #define PORT_HW_CFG_SPEED_CAPABILITY_D3_RESERVED 0x0000f000 836 837 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_MASK 0xFFFF0000 838 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_SHIFT 16 839 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL 0x00010000 840 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF 0x00020000 841 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF 0x00040000 842 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL 0x00080000 843 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_1G 0x00100000 844 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G 0x00200000 845 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_10G 0x00400000 846 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_20G 0x00800000 847 #define PORT_HW_CFG_SPEED_CAPABILITY_D0_RESERVED 0xf0000000 848 849 /* A place to hold the original MAC address as a backup */ 850 uint32_t backup_mac_upper; /* 0x2B4 */ 851 uint32_t backup_mac_lower; /* 0x2B8 */ 852 853 }; 854 855 856 /**************************************************************************** 857 * Shared Feature configuration * 858 ****************************************************************************/ 859 struct shared_feat_cfg { /* NVRAM Offset */ 860 861 uint32_t config; /* 0x450 */ 862 #define SHARED_FEATURE_BMC_ECHO_MODE_EN 0x00000001 863 864 /* Use NVRAM values instead of HW default values */ 865 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_MASK \ 866 0x00000002 867 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_DISABLED \ 868 0x00000000 869 #define SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED \ 870 0x00000002 871 872 #define SHARED_FEAT_CFG_NCSI_ID_METHOD_MASK 0x00000008 873 #define SHARED_FEAT_CFG_NCSI_ID_METHOD_SPIO 0x00000000 874 #define SHARED_FEAT_CFG_NCSI_ID_METHOD_NVRAM 0x00000008 875 876 #define SHARED_FEAT_CFG_NCSI_ID_MASK 0x00000030 877 #define SHARED_FEAT_CFG_NCSI_ID_SHIFT 4 878 879 /* Override the OTP back to single function mode. When using GPIO, 880 high means only SF, 0 is according to CLP configuration */ 881 #define SHARED_FEAT_CFG_FORCE_SF_MODE_MASK 0x00000700 882 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SHIFT 8 883 #define SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED 0x00000000 884 #define SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF 0x00000100 885 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SPIO4 0x00000200 886 #define SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT 0x00000300 887 #define SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE 0x00000400 888 889 /* Act as if the FCoE license is invalid */ 890 #define SHARED_FEAT_CFG_PREVENT_FCOE 0x00001000 891 892 /* Force FLR capability to all ports */ 893 #define SHARED_FEAT_CFG_FORCE_FLR_CAPABILITY 0x00002000 894 895 /* Act as if the iSCSI license is invalid */ 896 #define SHARED_FEAT_CFG_PREVENT_ISCSI_MASK 0x00004000 897 #define SHARED_FEAT_CFG_PREVENT_ISCSI_SHIFT 14 898 #define SHARED_FEAT_CFG_PREVENT_ISCSI_DISABLED 0x00000000 899 #define SHARED_FEAT_CFG_PREVENT_ISCSI_ENABLED 0x00004000 900 901 /* The interval in seconds between sending LLDP packets. Set to zero 902 to disable the feature */ 903 #define SHARED_FEAT_CFG_LLDP_XMIT_INTERVAL_MASK 0x00FF0000 904 #define SHARED_FEAT_CFG_LLDP_XMIT_INTERVAL_SHIFT 16 905 906 /* The assigned device type ID for LLDP usage */ 907 #define SHARED_FEAT_CFG_LLDP_DEVICE_TYPE_ID_MASK 0xFF000000 908 #define SHARED_FEAT_CFG_LLDP_DEVICE_TYPE_ID_SHIFT 24 909 910 }; 911 912 913 /**************************************************************************** 914 * Port Feature configuration * 915 ****************************************************************************/ 916 struct port_feat_cfg { /* port 0: 0x454 port 1: 0x4c8 */ 917 918 uint32_t config; 919 #define PORT_FEAT_CFG_BAR1_SIZE_MASK 0x0000000F 920 #define PORT_FEAT_CFG_BAR1_SIZE_SHIFT 0 921 #define PORT_FEAT_CFG_BAR1_SIZE_DISABLED 0x00000000 922 #define PORT_FEAT_CFG_BAR1_SIZE_64K 0x00000001 923 #define PORT_FEAT_CFG_BAR1_SIZE_128K 0x00000002 924 #define PORT_FEAT_CFG_BAR1_SIZE_256K 0x00000003 925 #define PORT_FEAT_CFG_BAR1_SIZE_512K 0x00000004 926 #define PORT_FEAT_CFG_BAR1_SIZE_1M 0x00000005 927 #define PORT_FEAT_CFG_BAR1_SIZE_2M 0x00000006 928 #define PORT_FEAT_CFG_BAR1_SIZE_4M 0x00000007 929 #define PORT_FEAT_CFG_BAR1_SIZE_8M 0x00000008 930 #define PORT_FEAT_CFG_BAR1_SIZE_16M 0x00000009 931 #define PORT_FEAT_CFG_BAR1_SIZE_32M 0x0000000a 932 #define PORT_FEAT_CFG_BAR1_SIZE_64M 0x0000000b 933 #define PORT_FEAT_CFG_BAR1_SIZE_128M 0x0000000c 934 #define PORT_FEAT_CFG_BAR1_SIZE_256M 0x0000000d 935 #define PORT_FEAT_CFG_BAR1_SIZE_512M 0x0000000e 936 #define PORT_FEAT_CFG_BAR1_SIZE_1G 0x0000000f 937 #define PORT_FEAT_CFG_BAR2_SIZE_MASK 0x000000F0 938 #define PORT_FEAT_CFG_BAR2_SIZE_SHIFT 4 939 #define PORT_FEAT_CFG_BAR2_SIZE_DISABLED 0x00000000 940 #define PORT_FEAT_CFG_BAR2_SIZE_64K 0x00000010 941 #define PORT_FEAT_CFG_BAR2_SIZE_128K 0x00000020 942 #define PORT_FEAT_CFG_BAR2_SIZE_256K 0x00000030 943 #define PORT_FEAT_CFG_BAR2_SIZE_512K 0x00000040 944 #define PORT_FEAT_CFG_BAR2_SIZE_1M 0x00000050 945 #define PORT_FEAT_CFG_BAR2_SIZE_2M 0x00000060 946 #define PORT_FEAT_CFG_BAR2_SIZE_4M 0x00000070 947 #define PORT_FEAT_CFG_BAR2_SIZE_8M 0x00000080 948 #define PORT_FEAT_CFG_BAR2_SIZE_16M 0x00000090 949 #define PORT_FEAT_CFG_BAR2_SIZE_32M 0x000000a0 950 #define PORT_FEAT_CFG_BAR2_SIZE_64M 0x000000b0 951 #define PORT_FEAT_CFG_BAR2_SIZE_128M 0x000000c0 952 #define PORT_FEAT_CFG_BAR2_SIZE_256M 0x000000d0 953 #define PORT_FEAT_CFG_BAR2_SIZE_512M 0x000000e0 954 #define PORT_FEAT_CFG_BAR2_SIZE_1G 0x000000f0 955 956 #define PORT_FEAT_CFG_DCBX_MASK 0x00000100 957 #define PORT_FEAT_CFG_DCBX_DISABLED 0x00000000 958 #define PORT_FEAT_CFG_DCBX_ENABLED 0x00000100 959 960 #define PORT_FEAT_CFG_AUTOGREEEN_MASK 0x00000200 961 #define PORT_FEAT_CFG_AUTOGREEEN_SHIFT 9 962 #define PORT_FEAT_CFG_AUTOGREEEN_DISABLED 0x00000000 963 #define PORT_FEAT_CFG_AUTOGREEEN_ENABLED 0x00000200 964 965 #define PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK 0x00000C00 966 #define PORT_FEAT_CFG_STORAGE_PERSONALITY_SHIFT 10 967 #define PORT_FEAT_CFG_STORAGE_PERSONALITY_DEFAULT 0x00000000 968 #define PORT_FEAT_CFG_STORAGE_PERSONALITY_FCOE 0x00000400 969 #define PORT_FEAT_CFG_STORAGE_PERSONALITY_ISCSI 0x00000800 970 #define PORT_FEAT_CFG_STORAGE_PERSONALITY_BOTH 0x00000c00 971 972 #define PORT_FEATURE_EN_SIZE_MASK 0x0f000000 973 #define PORT_FEATURE_EN_SIZE_SHIFT 24 974 #define PORT_FEATURE_WOL_ENABLED 0x01000000 975 #define PORT_FEATURE_MBA_ENABLED 0x02000000 976 #define PORT_FEATURE_MFW_ENABLED 0x04000000 977 978 /* Advertise expansion ROM even if MBA is disabled */ 979 #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_MASK 0x08000000 980 #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_DISABLED 0x00000000 981 #define PORT_FEAT_CFG_FORCE_EXP_ROM_ADV_ENABLED 0x08000000 982 983 /* Check the optic vendor via i2c against a list of approved modules 984 in a separate nvram image */ 985 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK 0xE0000000 986 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_SHIFT 29 987 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT \ 988 0x00000000 989 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER \ 990 0x20000000 991 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG 0x40000000 992 #define PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN 0x60000000 993 994 uint32_t wol_config; 995 /* Default is used when driver sets to "auto" mode */ 996 #define PORT_FEATURE_WOL_ACPI_UPON_MGMT 0x00000010 997 998 uint32_t mba_config; 999 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_MASK 0x00000007 1000 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_SHIFT 0 1001 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_PXE 0x00000000 1002 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_RPL 0x00000001 1003 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_BOOTP 0x00000002 1004 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_ISCSIB 0x00000003 1005 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_FCOE_BOOT 0x00000004 1006 #define PORT_FEATURE_MBA_BOOT_AGENT_TYPE_NONE 0x00000007 1007 1008 #define PORT_FEATURE_MBA_BOOT_RETRY_MASK 0x00000038 1009 #define PORT_FEATURE_MBA_BOOT_RETRY_SHIFT 3 1010 1011 #define PORT_FEATURE_MBA_SETUP_PROMPT_ENABLE 0x00000400 1012 #define PORT_FEATURE_MBA_HOTKEY_MASK 0x00000800 1013 #define PORT_FEATURE_MBA_HOTKEY_CTRL_S 0x00000000 1014 #define PORT_FEATURE_MBA_HOTKEY_CTRL_B 0x00000800 1015 1016 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_MASK 0x000FF000 1017 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_SHIFT 12 1018 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_DISABLED 0x00000000 1019 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2K 0x00001000 1020 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4K 0x00002000 1021 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8K 0x00003000 1022 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16K 0x00004000 1023 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32K 0x00005000 1024 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_64K 0x00006000 1025 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_128K 0x00007000 1026 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_256K 0x00008000 1027 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_512K 0x00009000 1028 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_1M 0x0000a000 1029 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_2M 0x0000b000 1030 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_4M 0x0000c000 1031 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_8M 0x0000d000 1032 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_16M 0x0000e000 1033 #define PORT_FEATURE_MBA_EXP_ROM_SIZE_32M 0x0000f000 1034 #define PORT_FEATURE_MBA_MSG_TIMEOUT_MASK 0x00F00000 1035 #define PORT_FEATURE_MBA_MSG_TIMEOUT_SHIFT 20 1036 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_MASK 0x03000000 1037 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_SHIFT 24 1038 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_AUTO 0x00000000 1039 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_BBS 0x01000000 1040 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT18H 0x02000000 1041 #define PORT_FEATURE_MBA_BIOS_BOOTSTRAP_INT19H 0x03000000 1042 #define PORT_FEATURE_MBA_LINK_SPEED_MASK 0x3C000000 1043 #define PORT_FEATURE_MBA_LINK_SPEED_SHIFT 26 1044 #define PORT_FEATURE_MBA_LINK_SPEED_AUTO 0x00000000 1045 #define PORT_FEATURE_MBA_LINK_SPEED_10M_HALF 0x04000000 1046 #define PORT_FEATURE_MBA_LINK_SPEED_10M_FULL 0x08000000 1047 #define PORT_FEATURE_MBA_LINK_SPEED_100M_HALF 0x0c000000 1048 #define PORT_FEATURE_MBA_LINK_SPEED_100M_FULL 0x10000000 1049 #define PORT_FEATURE_MBA_LINK_SPEED_1G 0x14000000 1050 #define PORT_FEATURE_MBA_LINK_SPEED_2_5G 0x18000000 1051 #define PORT_FEATURE_MBA_LINK_SPEED_10G 0x1c000000 1052 #define PORT_FEATURE_MBA_LINK_SPEED_20G 0x20000000 1053 1054 uint32_t Reserved0; /* 0x460 */ 1055 1056 uint32_t mba_vlan_cfg; 1057 #define PORT_FEATURE_MBA_VLAN_TAG_MASK 0x0000FFFF 1058 #define PORT_FEATURE_MBA_VLAN_TAG_SHIFT 0 1059 #define PORT_FEATURE_MBA_VLAN_EN 0x00010000 1060 1061 uint32_t Reserved1; 1062 uint32_t smbus_config; 1063 #define PORT_FEATURE_SMBUS_ADDR_MASK 0x000000fe 1064 #define PORT_FEATURE_SMBUS_ADDR_SHIFT 1 1065 1066 uint32_t vf_config; 1067 #define PORT_FEAT_CFG_VF_BAR2_SIZE_MASK 0x0000000F 1068 #define PORT_FEAT_CFG_VF_BAR2_SIZE_SHIFT 0 1069 #define PORT_FEAT_CFG_VF_BAR2_SIZE_DISABLED 0x00000000 1070 #define PORT_FEAT_CFG_VF_BAR2_SIZE_4K 0x00000001 1071 #define PORT_FEAT_CFG_VF_BAR2_SIZE_8K 0x00000002 1072 #define PORT_FEAT_CFG_VF_BAR2_SIZE_16K 0x00000003 1073 #define PORT_FEAT_CFG_VF_BAR2_SIZE_32K 0x00000004 1074 #define PORT_FEAT_CFG_VF_BAR2_SIZE_64K 0x00000005 1075 #define PORT_FEAT_CFG_VF_BAR2_SIZE_128K 0x00000006 1076 #define PORT_FEAT_CFG_VF_BAR2_SIZE_256K 0x00000007 1077 #define PORT_FEAT_CFG_VF_BAR2_SIZE_512K 0x00000008 1078 #define PORT_FEAT_CFG_VF_BAR2_SIZE_1M 0x00000009 1079 #define PORT_FEAT_CFG_VF_BAR2_SIZE_2M 0x0000000a 1080 #define PORT_FEAT_CFG_VF_BAR2_SIZE_4M 0x0000000b 1081 #define PORT_FEAT_CFG_VF_BAR2_SIZE_8M 0x0000000c 1082 #define PORT_FEAT_CFG_VF_BAR2_SIZE_16M 0x0000000d 1083 #define PORT_FEAT_CFG_VF_BAR2_SIZE_32M 0x0000000e 1084 #define PORT_FEAT_CFG_VF_BAR2_SIZE_64M 0x0000000f 1085 1086 uint32_t link_config; /* Used as HW defaults for the driver */ 1087 1088 #define PORT_FEATURE_FLOW_CONTROL_MASK 0x00000700 1089 #define PORT_FEATURE_FLOW_CONTROL_SHIFT 8 1090 #define PORT_FEATURE_FLOW_CONTROL_AUTO 0x00000000 1091 #define PORT_FEATURE_FLOW_CONTROL_TX 0x00000100 1092 #define PORT_FEATURE_FLOW_CONTROL_RX 0x00000200 1093 #define PORT_FEATURE_FLOW_CONTROL_BOTH 0x00000300 1094 #define PORT_FEATURE_FLOW_CONTROL_NONE 0x00000400 1095 #define PORT_FEATURE_FLOW_CONTROL_SAFC_RX 0x00000500 1096 #define PORT_FEATURE_FLOW_CONTROL_SAFC_TX 0x00000600 1097 #define PORT_FEATURE_FLOW_CONTROL_SAFC_BOTH 0x00000700 1098 1099 #define PORT_FEATURE_LINK_SPEED_MASK 0x000F0000 1100 #define PORT_FEATURE_LINK_SPEED_SHIFT 16 1101 #define PORT_FEATURE_LINK_SPEED_AUTO 0x00000000 1102 #define PORT_FEATURE_LINK_SPEED_10M_FULL 0x00010000 1103 #define PORT_FEATURE_LINK_SPEED_10M_HALF 0x00020000 1104 #define PORT_FEATURE_LINK_SPEED_100M_HALF 0x00030000 1105 #define PORT_FEATURE_LINK_SPEED_100M_FULL 0x00040000 1106 #define PORT_FEATURE_LINK_SPEED_1G 0x00050000 1107 #define PORT_FEATURE_LINK_SPEED_2_5G 0x00060000 1108 #define PORT_FEATURE_LINK_SPEED_10G_CX4 0x00070000 1109 #define PORT_FEATURE_LINK_SPEED_20G 0x00080000 1110 1111 #define PORT_FEATURE_CONNECTED_SWITCH_MASK 0x03000000 1112 #define PORT_FEATURE_CONNECTED_SWITCH_SHIFT 24 1113 /* (forced) low speed switch (< 10G) */ 1114 #define PORT_FEATURE_CON_SWITCH_1G_SWITCH 0x00000000 1115 /* (forced) high speed switch (>= 10G) */ 1116 #define PORT_FEATURE_CON_SWITCH_10G_SWITCH 0x01000000 1117 #define PORT_FEATURE_CON_SWITCH_AUTO_DETECT 0x02000000 1118 #define PORT_FEATURE_CON_SWITCH_ONE_TIME_DETECT 0x03000000 1119 1120 1121 /* The default for MCP link configuration, 1122 uses the same defines as link_config */ 1123 uint32_t mfw_wol_link_cfg; 1124 1125 /* The default for the driver of the second external phy, 1126 uses the same defines as link_config */ 1127 uint32_t link_config2; /* 0x47C */ 1128 1129 /* The default for MCP of the second external phy, 1130 uses the same defines as link_config */ 1131 uint32_t mfw_wol_link_cfg2; /* 0x480 */ 1132 1133 1134 /* EEE power saving mode */ 1135 uint32_t eee_power_mode; /* 0x484 */ 1136 #define PORT_FEAT_CFG_EEE_POWER_MODE_MASK 0x000000FF 1137 #define PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT 0 1138 #define PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED 0x00000000 1139 #define PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED 0x00000001 1140 #define PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE 0x00000002 1141 #define PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY 0x00000003 1142 1143 1144 uint32_t Reserved2[16]; /* 0x488 */ 1145 }; 1146 1147 /**************************************************************************** 1148 * Device Information * 1149 ****************************************************************************/ 1150 struct shm_dev_info { /* size */ 1151 1152 uint32_t bc_rev; /* 8 bits each: major, minor, build */ /* 4 */ 1153 1154 struct shared_hw_cfg shared_hw_config; /* 40 */ 1155 1156 struct port_hw_cfg port_hw_config[PORT_MAX]; /* 400*2=800 */ 1157 1158 struct shared_feat_cfg shared_feature_config; /* 4 */ 1159 1160 struct port_feat_cfg port_feature_config[PORT_MAX];/* 116*2=232 */ 1161 1162 }; 1163 1164 struct extended_dev_info_shared_cfg { /* NVRAM OFFSET */ 1165 1166 /* Threshold in celcius to start using the fan */ 1167 uint32_t temperature_monitor1; /* 0x4000 */ 1168 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_THRESH_MASK 0x0000007F 1169 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_THRESH_SHIFT 0 1170 1171 /* Threshold in celcius to shut down the board */ 1172 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_THRESH_MASK 0x00007F00 1173 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_THRESH_SHIFT 8 1174 1175 /* EPIO of fan temperature status */ 1176 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_MASK 0x00FF0000 1177 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_SHIFT 16 1178 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_NA 0x00000000 1179 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO0 0x00010000 1180 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO1 0x00020000 1181 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO2 0x00030000 1182 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO3 0x00040000 1183 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO4 0x00050000 1184 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO5 0x00060000 1185 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO6 0x00070000 1186 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO7 0x00080000 1187 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO8 0x00090000 1188 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO9 0x000a0000 1189 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO10 0x000b0000 1190 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO11 0x000c0000 1191 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO12 0x000d0000 1192 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO13 0x000e0000 1193 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO14 0x000f0000 1194 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO15 0x00100000 1195 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO16 0x00110000 1196 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO17 0x00120000 1197 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO18 0x00130000 1198 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO19 0x00140000 1199 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO20 0x00150000 1200 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO21 0x00160000 1201 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO22 0x00170000 1202 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO23 0x00180000 1203 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO24 0x00190000 1204 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO25 0x001a0000 1205 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO26 0x001b0000 1206 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO27 0x001c0000 1207 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO28 0x001d0000 1208 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO29 0x001e0000 1209 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO30 0x001f0000 1210 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_FAN_EPIO_EPIO31 0x00200000 1211 1212 /* EPIO of shut down temperature status */ 1213 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_MASK 0xFF000000 1214 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_SHIFT 24 1215 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_NA 0x00000000 1216 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO0 0x01000000 1217 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO1 0x02000000 1218 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO2 0x03000000 1219 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO3 0x04000000 1220 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO4 0x05000000 1221 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO5 0x06000000 1222 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO6 0x07000000 1223 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO7 0x08000000 1224 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO8 0x09000000 1225 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO9 0x0a000000 1226 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO10 0x0b000000 1227 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO11 0x0c000000 1228 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO12 0x0d000000 1229 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO13 0x0e000000 1230 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO14 0x0f000000 1231 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO15 0x10000000 1232 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO16 0x11000000 1233 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO17 0x12000000 1234 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO18 0x13000000 1235 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO19 0x14000000 1236 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO20 0x15000000 1237 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO21 0x16000000 1238 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO22 0x17000000 1239 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO23 0x18000000 1240 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO24 0x19000000 1241 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO25 0x1a000000 1242 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO26 0x1b000000 1243 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO27 0x1c000000 1244 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO28 0x1d000000 1245 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO29 0x1e000000 1246 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO30 0x1f000000 1247 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SHUT_EPIO_EPIO31 0x20000000 1248 1249 1250 /* EPIO of shut down temperature status */ 1251 uint32_t temperature_monitor2; /* 0x4004 */ 1252 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_PERIOD_MASK 0x0000FFFF 1253 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_PERIOD_SHIFT 0 1254 1255 1256 /* MFW flavor to be used */ 1257 uint32_t mfw_cfg; /* 0x4008 */ 1258 #define EXTENDED_DEV_INFO_SHARED_CFG_MFW_FLAVOR_MASK 0x000000FF 1259 #define EXTENDED_DEV_INFO_SHARED_CFG_MFW_FLAVOR_SHIFT 0 1260 #define EXTENDED_DEV_INFO_SHARED_CFG_MFW_FLAVOR_NA 0x00000000 1261 #define EXTENDED_DEV_INFO_SHARED_CFG_MFW_FLAVOR_A 0x00000001 1262 1263 /* Should NIC data query remain enabled upon last drv unload */ 1264 #define EXTENDED_DEV_INFO_SHARED_CFG_OCBB_EN_LAST_DRV_MASK 0x00000100 1265 #define EXTENDED_DEV_INFO_SHARED_CFG_OCBB_EN_LAST_DRV_SHIFT 8 1266 #define EXTENDED_DEV_INFO_SHARED_CFG_OCBB_EN_LAST_DRV_DISABLED 0x00000000 1267 #define EXTENDED_DEV_INFO_SHARED_CFG_OCBB_EN_LAST_DRV_ENABLED 0x00000100 1268 1269 /* Hide DCBX feature in CCM/BACS menus */ 1270 #define EXTENDED_DEV_INFO_SHARED_CFG_HIDE_DCBX_FEAT_MASK 0x00010000 1271 #define EXTENDED_DEV_INFO_SHARED_CFG_HIDE_DCBX_FEAT_SHIFT 16 1272 #define EXTENDED_DEV_INFO_SHARED_CFG_HIDE_DCBX_FEAT_DISABLED 0x00000000 1273 #define EXTENDED_DEV_INFO_SHARED_CFG_HIDE_DCBX_FEAT_ENABLED 0x00010000 1274 1275 uint32_t smbus_config; /* 0x400C */ 1276 #define EXTENDED_DEV_INFO_SHARED_CFG_SMBUS_ADDR_MASK 0x000000FF 1277 #define EXTENDED_DEV_INFO_SHARED_CFG_SMBUS_ADDR_SHIFT 0 1278 1279 /* Switching regulator loop gain */ 1280 uint32_t board_cfg; /* 0x4010 */ 1281 #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_MASK 0x0000000F 1282 #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_SHIFT 0 1283 #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_HW_DEFAULT 0x00000000 1284 #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_X2 0x00000008 1285 #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_X4 0x00000009 1286 #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_X8 0x0000000a 1287 #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_X16 0x0000000b 1288 #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_DIV8 0x0000000c 1289 #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_DIV4 0x0000000d 1290 #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_DIV2 0x0000000e 1291 #define EXTENDED_DEV_INFO_SHARED_CFG_LOOP_GAIN_X1 0x0000000f 1292 1293 /* whether shadow swim feature is supported */ 1294 #define EXTENDED_DEV_INFO_SHARED_CFG_SHADOW_SWIM_MASK 0x00000100 1295 #define EXTENDED_DEV_INFO_SHARED_CFG_SHADOW_SWIM_SHIFT 8 1296 #define EXTENDED_DEV_INFO_SHARED_CFG_SHADOW_SWIM_DISABLED 0x00000000 1297 #define EXTENDED_DEV_INFO_SHARED_CFG_SHADOW_SWIM_ENABLED 0x00000100 1298 1299 /* whether to show/hide SRIOV menu in CCM */ 1300 #define EXTENDED_DEV_INFO_SHARED_CFG_SRIOV_SHOW_MENU_MASK 0x00000200 1301 #define EXTENDED_DEV_INFO_SHARED_CFG_SRIOV_SHOW_MENU_SHIFT 9 1302 #define EXTENDED_DEV_INFO_SHARED_CFG_SRIOV_SHOW_MENU 0x00000000 1303 #define EXTENDED_DEV_INFO_SHARED_CFG_SRIOV_HIDE_MENU 0x00000200 1304 1305 /* Threshold in celcius for max continuous operation */ 1306 uint32_t temperature_report; /* 0x4014 */ 1307 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_MCOT_MASK 0x0000007F 1308 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_MCOT_SHIFT 0 1309 1310 /* Threshold in celcius for sensor caution */ 1311 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SCT_MASK 0x00007F00 1312 #define EXTENDED_DEV_INFO_SHARED_CFG_TEMP_SCT_SHIFT 8 1313 1314 /* wwn node prefix to be used (unless value is 0) */ 1315 uint32_t wwn_prefix; /* 0x4018 */ 1316 #define EXTENDED_DEV_INFO_SHARED_CFG_WWN_NODE_PREFIX0_MASK 0x000000FF 1317 #define EXTENDED_DEV_INFO_SHARED_CFG_WWN_NODE_PREFIX0_SHIFT 0 1318 1319 #define EXTENDED_DEV_INFO_SHARED_CFG_WWN_NODE_PREFIX1_MASK 0x0000FF00 1320 #define EXTENDED_DEV_INFO_SHARED_CFG_WWN_NODE_PREFIX1_SHIFT 8 1321 1322 /* wwn port prefix to be used (unless value is 0) */ 1323 #define EXTENDED_DEV_INFO_SHARED_CFG_WWN_PORT_PREFIX0_MASK 0x00FF0000 1324 #define EXTENDED_DEV_INFO_SHARED_CFG_WWN_PORT_PREFIX0_SHIFT 16 1325 1326 /* wwn port prefix to be used (unless value is 0) */ 1327 #define EXTENDED_DEV_INFO_SHARED_CFG_WWN_PORT_PREFIX1_MASK 0xFF000000 1328 #define EXTENDED_DEV_INFO_SHARED_CFG_WWN_PORT_PREFIX1_SHIFT 24 1329 1330 /* General debug nvm cfg */ 1331 uint32_t dbg_cfg_flags; /* 0x401C */ 1332 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_MASK 0x000FFFFF 1333 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SHIFT 0 1334 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_ENABLE 0x00000001 1335 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_EN_SIGDET_FILTER 0x00000002 1336 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SET_LP_TX_PRESET7 0x00000004 1337 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SET_TX_ANA_DEFAULT 0x00000008 1338 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SET_PLL_ANA_DEFAULT 0x00000010 1339 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_FORCE_G1PLL_RETUNE 0x00000020 1340 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SET_RX_ANA_DEFAULT 0x00000040 1341 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_FORCE_SERDES_RX_CLK 0x00000080 1342 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_DIS_RX_LP_EIEOS 0x00000100 1343 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_FINALIZE_UCODE 0x00000200 1344 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_HOLDOFF_REQ 0x00000400 1345 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_RX_SIGDET_OVERRIDE 0x00000800 1346 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_GP_PORG_UC_RESET 0x00001000 1347 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SUPPRESS_COMPEN_EVT 0x00002000 1348 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_ADJ_TXEQ_P0_P1 0x00004000 1349 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_G3_PLL_RETUNE 0x00008000 1350 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_SET_MAC_PHY_CTL8 0x00010000 1351 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_DIS_MAC_G3_FRM_ERR 0x00020000 1352 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_INFERRED_EI 0x00040000 1353 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_GEN3_COMPLI_ENA 0x00080000 1354 1355 /* Debug signet rx threshold */ 1356 uint32_t dbg_rx_sigdet_threshold; /* 0x4020 */ 1357 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_RX_SIGDET_MASK 0x00000007 1358 #define EXTENDED_DEV_INFO_SHARED_CFG_DBG_RX_SIGDET_SHIFT 0 1359 1360 /* Enable IFFE feature */ 1361 uint32_t iffe_features; /* 0x4024 */ 1362 #define EXTENDED_DEV_INFO_SHARED_CFG_ENABLE_IFFE_MASK 0x00000001 1363 #define EXTENDED_DEV_INFO_SHARED_CFG_ENABLE_IFFE_SHIFT 0 1364 #define EXTENDED_DEV_INFO_SHARED_CFG_ENABLE_IFFE_DISABLED 0x00000000 1365 #define EXTENDED_DEV_INFO_SHARED_CFG_ENABLE_IFFE_ENABLED 0x00000001 1366 1367 /* Allowable port enablement (bitmask for ports 3-1) */ 1368 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_PORT_MASK 0x0000000E 1369 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_PORT_SHIFT 1 1370 1371 /* Allow iSCSI offload override */ 1372 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_ISCSI_MASK 0x00000010 1373 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_ISCSI_SHIFT 4 1374 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_ISCSI_DISABLED 0x00000000 1375 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_ISCSI_ENABLED 0x00000010 1376 1377 /* Allow FCoE offload override */ 1378 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_FCOE_MASK 0x00000020 1379 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_FCOE_SHIFT 5 1380 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_FCOE_DISABLED 0x00000000 1381 #define EXTENDED_DEV_INFO_SHARED_CFG_OVERRIDE_FCOE_ENABLED 0x00000020 1382 1383 /* Tie to adaptor */ 1384 #define EXTENDED_DEV_INFO_SHARED_CFG_TIE_ADAPTOR_MASK 0x00008000 1385 #define EXTENDED_DEV_INFO_SHARED_CFG_TIE_ADAPTOR_SHIFT 15 1386 #define EXTENDED_DEV_INFO_SHARED_CFG_TIE_ADAPTOR_DISABLED 0x00000000 1387 #define EXTENDED_DEV_INFO_SHARED_CFG_TIE_ADAPTOR_ENABLED 0x00008000 1388 1389 /* Currently enabled port(s) (bitmask for ports 3-1) */ 1390 uint32_t current_iffe_mask; /* 0x4028 */ 1391 #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_CFG_MASK 0x0000000E 1392 #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_CFG_SHIFT 1 1393 1394 /* Current iSCSI offload */ 1395 #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_ISCSI_MASK 0x00000010 1396 #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_ISCSI_SHIFT 4 1397 #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_ISCSI_DISABLED 0x00000000 1398 #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_ISCSI_ENABLED 0x00000010 1399 1400 /* Current FCoE offload */ 1401 #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_FCOE_MASK 0x00000020 1402 #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_FCOE_SHIFT 5 1403 #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_FCOE_DISABLED 0x00000000 1404 #define EXTENDED_DEV_INFO_SHARED_CFG_CURRENT_FCOE_ENABLED 0x00000020 1405 1406 /* FW set this pin to "0" (assert) these signal if either of its MAC 1407 * or PHY specific threshold values is exceeded. 1408 * Values are standard GPIO/EPIO pins. 1409 */ 1410 uint32_t threshold_pin; /* 0x402C */ 1411 #define EXTENDED_DEV_INFO_SHARED_CFG_TCONTROL_PIN_MASK 0x000000FF 1412 #define EXTENDED_DEV_INFO_SHARED_CFG_TCONTROL_PIN_SHIFT 0 1413 #define EXTENDED_DEV_INFO_SHARED_CFG_TWARNING_PIN_MASK 0x0000FF00 1414 #define EXTENDED_DEV_INFO_SHARED_CFG_TWARNING_PIN_SHIFT 8 1415 #define EXTENDED_DEV_INFO_SHARED_CFG_TCRITICAL_PIN_MASK 0x00FF0000 1416 #define EXTENDED_DEV_INFO_SHARED_CFG_TCRITICAL_PIN_SHIFT 16 1417 1418 /* MAC die temperature threshold in Celsius. */ 1419 uint32_t mac_threshold_val; /* 0x4030 */ 1420 #define EXTENDED_DEV_INFO_SHARED_CFG_CONTROL_MAC_THRESH_MASK 0x000000FF 1421 #define EXTENDED_DEV_INFO_SHARED_CFG_CONTROL_MAC_THRESH_SHIFT 0 1422 #define EXTENDED_DEV_INFO_SHARED_CFG_WARNING_MAC_THRESH_MASK 0x0000FF00 1423 #define EXTENDED_DEV_INFO_SHARED_CFG_WARNING_MAC_THRESH_SHIFT 8 1424 #define EXTENDED_DEV_INFO_SHARED_CFG_CRITICAL_MAC_THRESH_MASK 0x00FF0000 1425 #define EXTENDED_DEV_INFO_SHARED_CFG_CRITICAL_MAC_THRESH_SHIFT 16 1426 1427 /* PHY die temperature threshold in Celsius. */ 1428 uint32_t phy_threshold_val; /* 0x4034 */ 1429 #define EXTENDED_DEV_INFO_SHARED_CFG_CONTROL_PHY_THRESH_MASK 0x000000FF 1430 #define EXTENDED_DEV_INFO_SHARED_CFG_CONTROL_PHY_THRESH_SHIFT 0 1431 #define EXTENDED_DEV_INFO_SHARED_CFG_WARNING_PHY_THRESH_MASK 0x0000FF00 1432 #define EXTENDED_DEV_INFO_SHARED_CFG_WARNING_PHY_THRESH_SHIFT 8 1433 #define EXTENDED_DEV_INFO_SHARED_CFG_CRITICAL_PHY_THRESH_MASK 0x00FF0000 1434 #define EXTENDED_DEV_INFO_SHARED_CFG_CRITICAL_PHY_THRESH_SHIFT 16 1435 1436 /* External pins to communicate with host. 1437 * Values are standard GPIO/EPIO pins. 1438 */ 1439 uint32_t host_pin; /* 0x4038 */ 1440 #define EXTENDED_DEV_INFO_SHARED_CFG_I2C_ISOLATE_MASK 0x000000FF 1441 #define EXTENDED_DEV_INFO_SHARED_CFG_I2C_ISOLATE_SHIFT 0 1442 #define EXTENDED_DEV_INFO_SHARED_CFG_MEZZ_FAULT_MASK 0x0000FF00 1443 #define EXTENDED_DEV_INFO_SHARED_CFG_MEZZ_FAULT_SHIFT 8 1444 #define EXTENDED_DEV_INFO_SHARED_CFG_MEZZ_VPD_UPDATE_MASK 0x00FF0000 1445 #define EXTENDED_DEV_INFO_SHARED_CFG_MEZZ_VPD_UPDATE_SHIFT 16 1446 #define EXTENDED_DEV_INFO_SHARED_CFG_VPD_CACHE_COMP_MASK 0xFF000000 1447 #define EXTENDED_DEV_INFO_SHARED_CFG_VPD_CACHE_COMP_SHIFT 24 1448 }; 1449 1450 1451 #if !defined(__LITTLE_ENDIAN) && !defined(__BIG_ENDIAN) 1452 #error "Missing either LITTLE_ENDIAN or BIG_ENDIAN definition." 1453 #endif 1454 1455 #define FUNC_0 0 1456 #define FUNC_1 1 1457 #define FUNC_2 2 1458 #define FUNC_3 3 1459 #define FUNC_4 4 1460 #define FUNC_5 5 1461 #define FUNC_6 6 1462 #define FUNC_7 7 1463 #define E1_FUNC_MAX 2 1464 #define E1H_FUNC_MAX 8 1465 #define E2_FUNC_MAX 4 /* per path */ 1466 1467 #define VN_0 0 1468 #define VN_1 1 1469 #define VN_2 2 1470 #define VN_3 3 1471 #define E1VN_MAX 1 1472 #define E1HVN_MAX 4 1473 1474 #define E2_VF_MAX 64 /* HC_REG_VF_CONFIGURATION_SIZE */ 1475 /* This value (in milliseconds) determines the frequency of the driver 1476 * issuing the PULSE message code. The firmware monitors this periodic 1477 * pulse to determine when to switch to an OS-absent mode. */ 1478 #define DRV_PULSE_PERIOD_MS 250 1479 1480 /* This value (in milliseconds) determines how long the driver should 1481 * wait for an acknowledgement from the firmware before timing out. Once 1482 * the firmware has timed out, the driver will assume there is no firmware 1483 * running and there won't be any firmware-driver synchronization during a 1484 * driver reset. */ 1485 #define FW_ACK_TIME_OUT_MS 5000 1486 1487 #define FW_ACK_POLL_TIME_MS 1 1488 1489 #define FW_ACK_NUM_OF_POLL (FW_ACK_TIME_OUT_MS/FW_ACK_POLL_TIME_MS) 1490 1491 #define MFW_TRACE_SIGNATURE 0x54524342 1492 1493 /**************************************************************************** 1494 * Driver <-> FW Mailbox * 1495 ****************************************************************************/ 1496 struct drv_port_mb { 1497 1498 uint32_t link_status; 1499 /* Driver should update this field on any link change event */ 1500 1501 #define LINK_STATUS_NONE (0<<0) 1502 #define LINK_STATUS_LINK_FLAG_MASK 0x00000001 1503 #define LINK_STATUS_LINK_UP 0x00000001 1504 #define LINK_STATUS_SPEED_AND_DUPLEX_MASK 0x0000001E 1505 #define LINK_STATUS_SPEED_AND_DUPLEX_AN_NOT_COMPLETE (0<<1) 1506 #define LINK_STATUS_SPEED_AND_DUPLEX_10THD (1<<1) 1507 #define LINK_STATUS_SPEED_AND_DUPLEX_10TFD (2<<1) 1508 #define LINK_STATUS_SPEED_AND_DUPLEX_100TXHD (3<<1) 1509 #define LINK_STATUS_SPEED_AND_DUPLEX_100T4 (4<<1) 1510 #define LINK_STATUS_SPEED_AND_DUPLEX_100TXFD (5<<1) 1511 #define LINK_STATUS_SPEED_AND_DUPLEX_1000THD (6<<1) 1512 #define LINK_STATUS_SPEED_AND_DUPLEX_1000TFD (7<<1) 1513 #define LINK_STATUS_SPEED_AND_DUPLEX_1000XFD (7<<1) 1514 #define LINK_STATUS_SPEED_AND_DUPLEX_2500THD (8<<1) 1515 #define LINK_STATUS_SPEED_AND_DUPLEX_2500TFD (9<<1) 1516 #define LINK_STATUS_SPEED_AND_DUPLEX_2500XFD (9<<1) 1517 #define LINK_STATUS_SPEED_AND_DUPLEX_10GTFD (10<<1) 1518 #define LINK_STATUS_SPEED_AND_DUPLEX_10GXFD (10<<1) 1519 #define LINK_STATUS_SPEED_AND_DUPLEX_20GTFD (11<<1) 1520 #define LINK_STATUS_SPEED_AND_DUPLEX_20GXFD (11<<1) 1521 1522 #define LINK_STATUS_AUTO_NEGOTIATE_FLAG_MASK 0x00000020 1523 #define LINK_STATUS_AUTO_NEGOTIATE_ENABLED 0x00000020 1524 1525 #define LINK_STATUS_AUTO_NEGOTIATE_COMPLETE 0x00000040 1526 #define LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK 0x00000080 1527 #define LINK_STATUS_PARALLEL_DETECTION_USED 0x00000080 1528 1529 #define LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE 0x00000200 1530 #define LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE 0x00000400 1531 #define LINK_STATUS_LINK_PARTNER_100T4_CAPABLE 0x00000800 1532 #define LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE 0x00001000 1533 #define LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE 0x00002000 1534 #define LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE 0x00004000 1535 #define LINK_STATUS_LINK_PARTNER_10THD_CAPABLE 0x00008000 1536 1537 #define LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK 0x00010000 1538 #define LINK_STATUS_TX_FLOW_CONTROL_ENABLED 0x00010000 1539 1540 #define LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK 0x00020000 1541 #define LINK_STATUS_RX_FLOW_CONTROL_ENABLED 0x00020000 1542 1543 #define LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK 0x000C0000 1544 #define LINK_STATUS_LINK_PARTNER_NOT_PAUSE_CAPABLE (0<<18) 1545 #define LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE (1<<18) 1546 #define LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE (2<<18) 1547 #define LINK_STATUS_LINK_PARTNER_BOTH_PAUSE (3<<18) 1548 1549 #define LINK_STATUS_SERDES_LINK 0x00100000 1550 1551 #define LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE 0x00200000 1552 #define LINK_STATUS_LINK_PARTNER_2500XHD_CAPABLE 0x00400000 1553 #define LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE 0x00800000 1554 #define LINK_STATUS_LINK_PARTNER_20GXFD_CAPABLE 0x10000000 1555 1556 #define LINK_STATUS_PFC_ENABLED 0x20000000 1557 1558 #define LINK_STATUS_PHYSICAL_LINK_FLAG 0x40000000 1559 #define LINK_STATUS_SFP_TX_FAULT 0x80000000 1560 1561 uint32_t port_stx; 1562 1563 uint32_t stat_nig_timer; 1564 1565 /* MCP firmware does not use this field */ 1566 uint32_t ext_phy_fw_version; 1567 1568 }; 1569 1570 1571 struct drv_func_mb { 1572 1573 uint32_t drv_mb_header; 1574 #define DRV_MSG_CODE_MASK 0xffff0000 1575 #define DRV_MSG_CODE_LOAD_REQ 0x10000000 1576 #define DRV_MSG_CODE_LOAD_DONE 0x11000000 1577 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_EN 0x20000000 1578 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS 0x20010000 1579 #define DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP 0x20020000 1580 #define DRV_MSG_CODE_UNLOAD_DONE 0x21000000 1581 #define DRV_MSG_CODE_DCC_OK 0x30000000 1582 #define DRV_MSG_CODE_DCC_FAILURE 0x31000000 1583 #define DRV_MSG_CODE_DIAG_ENTER_REQ 0x50000000 1584 #define DRV_MSG_CODE_DIAG_EXIT_REQ 0x60000000 1585 #define DRV_MSG_CODE_VALIDATE_KEY 0x70000000 1586 #define DRV_MSG_CODE_GET_CURR_KEY 0x80000000 1587 #define DRV_MSG_CODE_GET_UPGRADE_KEY 0x81000000 1588 #define DRV_MSG_CODE_GET_MANUF_KEY 0x82000000 1589 #define DRV_MSG_CODE_LOAD_L2B_PRAM 0x90000000 1590 1591 /* 1592 * The optic module verification command requires bootcode 1593 * v5.0.6 or later, te specific optic module verification command 1594 * requires bootcode v5.2.12 or later 1595 */ 1596 #define DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL 0xa0000000 1597 #define REQ_BC_VER_4_VRFY_FIRST_PHY_OPT_MDL 0x00050006 1598 #define DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL 0xa1000000 1599 #define REQ_BC_VER_4_VRFY_SPECIFIC_PHY_OPT_MDL 0x00050234 1600 #define DRV_MSG_CODE_VRFY_AFEX_SUPPORTED 0xa2000000 1601 #define REQ_BC_VER_4_VRFY_AFEX_SUPPORTED 0x00070002 1602 #define REQ_BC_VER_4_SFP_TX_DISABLE_SUPPORTED 0x00070014 1603 #define REQ_BC_VER_4_MT_SUPPORTED 0x00070201 1604 #define REQ_BC_VER_4_PFC_STATS_SUPPORTED 0x00070201 1605 #define REQ_BC_VER_4_FCOE_FEATURES 0x00070209 1606 1607 #define DRV_MSG_CODE_DCBX_ADMIN_PMF_MSG 0xb0000000 1608 #define DRV_MSG_CODE_DCBX_PMF_DRV_OK 0xb2000000 1609 #define REQ_BC_VER_4_DCBX_ADMIN_MSG_NON_PMF 0x00070401 1610 1611 #define DRV_MSG_CODE_VF_DISABLED_DONE 0xc0000000 1612 1613 #define DRV_MSG_CODE_AFEX_DRIVER_SETMAC 0xd0000000 1614 #define DRV_MSG_CODE_AFEX_LISTGET_ACK 0xd1000000 1615 #define DRV_MSG_CODE_AFEX_LISTSET_ACK 0xd2000000 1616 #define DRV_MSG_CODE_AFEX_STATSGET_ACK 0xd3000000 1617 #define DRV_MSG_CODE_AFEX_VIFSET_ACK 0xd4000000 1618 1619 #define DRV_MSG_CODE_DRV_INFO_ACK 0xd8000000 1620 #define DRV_MSG_CODE_DRV_INFO_NACK 0xd9000000 1621 1622 #define DRV_MSG_CODE_EEE_RESULTS_ACK 0xda000000 1623 1624 #define DRV_MSG_CODE_RMMOD 0xdb000000 1625 #define REQ_BC_VER_4_RMMOD_CMD 0x0007080f 1626 1627 #define DRV_MSG_CODE_SET_MF_BW 0xe0000000 1628 #define REQ_BC_VER_4_SET_MF_BW 0x00060202 1629 #define DRV_MSG_CODE_SET_MF_BW_ACK 0xe1000000 1630 1631 #define DRV_MSG_CODE_LINK_STATUS_CHANGED 0x01000000 1632 1633 #define DRV_MSG_CODE_INITIATE_FLR 0x02000000 1634 #define REQ_BC_VER_4_INITIATE_FLR 0x00070213 1635 1636 #define BIOS_MSG_CODE_LIC_CHALLENGE 0xff010000 1637 #define BIOS_MSG_CODE_LIC_RESPONSE 0xff020000 1638 #define BIOS_MSG_CODE_VIRT_MAC_PRIM 0xff030000 1639 #define BIOS_MSG_CODE_VIRT_MAC_ISCSI 0xff040000 1640 1641 #define DRV_MSG_CODE_IMG_OFFSET_REQ 0xe2000000 1642 #define DRV_MSG_CODE_IMG_SIZE_REQ 0xe3000000 1643 1644 #define DRV_MSG_SEQ_NUMBER_MASK 0x0000ffff 1645 1646 uint32_t drv_mb_param; 1647 #define DRV_MSG_CODE_SET_MF_BW_MIN_MASK 0x00ff0000 1648 #define DRV_MSG_CODE_SET_MF_BW_MAX_MASK 0xff000000 1649 1650 #define DRV_MSG_CODE_UNLOAD_NON_D3_POWER 0x00000001 1651 #define DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET 0x00000002 1652 1653 #define DRV_MSG_CODE_LOAD_REQ_WITH_LFA 0x0000100a 1654 #define DRV_MSG_CODE_LOAD_REQ_FORCE_LFA 0x00002000 1655 1656 #define DRV_MSG_CODE_USR_BLK_IMAGE_REQ 0x00000001 1657 1658 uint32_t fw_mb_header; 1659 #define FW_MSG_CODE_MASK 0xffff0000 1660 #define FW_MSG_CODE_DRV_LOAD_COMMON 0x10100000 1661 #define FW_MSG_CODE_DRV_LOAD_PORT 0x10110000 1662 #define FW_MSG_CODE_DRV_LOAD_FUNCTION 0x10120000 1663 /* Load common chip is supported from bc 6.0.0 */ 1664 #define REQ_BC_VER_4_DRV_LOAD_COMMON_CHIP 0x00060000 1665 #define FW_MSG_CODE_DRV_LOAD_COMMON_CHIP 0x10130000 1666 1667 #define FW_MSG_CODE_DRV_LOAD_REFUSED 0x10200000 1668 #define FW_MSG_CODE_DRV_LOAD_DONE 0x11100000 1669 #define FW_MSG_CODE_DRV_UNLOAD_COMMON 0x20100000 1670 #define FW_MSG_CODE_DRV_UNLOAD_PORT 0x20110000 1671 #define FW_MSG_CODE_DRV_UNLOAD_FUNCTION 0x20120000 1672 #define FW_MSG_CODE_DRV_UNLOAD_DONE 0x21100000 1673 #define FW_MSG_CODE_DCC_DONE 0x30100000 1674 #define FW_MSG_CODE_LLDP_DONE 0x40100000 1675 #define FW_MSG_CODE_DIAG_ENTER_DONE 0x50100000 1676 #define FW_MSG_CODE_DIAG_REFUSE 0x50200000 1677 #define FW_MSG_CODE_DIAG_EXIT_DONE 0x60100000 1678 #define FW_MSG_CODE_VALIDATE_KEY_SUCCESS 0x70100000 1679 #define FW_MSG_CODE_VALIDATE_KEY_FAILURE 0x70200000 1680 #define FW_MSG_CODE_GET_KEY_DONE 0x80100000 1681 #define FW_MSG_CODE_NO_KEY 0x80f00000 1682 #define FW_MSG_CODE_LIC_INFO_NOT_READY 0x80f80000 1683 #define FW_MSG_CODE_L2B_PRAM_LOADED 0x90100000 1684 #define FW_MSG_CODE_L2B_PRAM_T_LOAD_FAILURE 0x90210000 1685 #define FW_MSG_CODE_L2B_PRAM_C_LOAD_FAILURE 0x90220000 1686 #define FW_MSG_CODE_L2B_PRAM_X_LOAD_FAILURE 0x90230000 1687 #define FW_MSG_CODE_L2B_PRAM_U_LOAD_FAILURE 0x90240000 1688 #define FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS 0xa0100000 1689 #define FW_MSG_CODE_VRFY_OPT_MDL_INVLD_IMG 0xa0200000 1690 #define FW_MSG_CODE_VRFY_OPT_MDL_UNAPPROVED 0xa0300000 1691 #define FW_MSG_CODE_VF_DISABLED_DONE 0xb0000000 1692 #define FW_MSG_CODE_HW_SET_INVALID_IMAGE 0xb0100000 1693 1694 #define FW_MSG_CODE_AFEX_DRIVER_SETMAC_DONE 0xd0100000 1695 #define FW_MSG_CODE_AFEX_LISTGET_ACK 0xd1100000 1696 #define FW_MSG_CODE_AFEX_LISTSET_ACK 0xd2100000 1697 #define FW_MSG_CODE_AFEX_STATSGET_ACK 0xd3100000 1698 #define FW_MSG_CODE_AFEX_VIFSET_ACK 0xd4100000 1699 1700 #define FW_MSG_CODE_DRV_INFO_ACK 0xd8100000 1701 #define FW_MSG_CODE_DRV_INFO_NACK 0xd9100000 1702 1703 #define FW_MSG_CODE_EEE_RESULS_ACK 0xda100000 1704 1705 #define FW_MSG_CODE_RMMOD_ACK 0xdb100000 1706 1707 #define FW_MSG_CODE_SET_MF_BW_SENT 0xe0000000 1708 #define FW_MSG_CODE_SET_MF_BW_DONE 0xe1000000 1709 1710 #define FW_MSG_CODE_LINK_CHANGED_ACK 0x01100000 1711 1712 #define FW_MSG_CODE_FLR_ACK 0x02000000 1713 #define FW_MSG_CODE_FLR_NACK 0x02100000 1714 1715 #define FW_MSG_CODE_LIC_CHALLENGE 0xff010000 1716 #define FW_MSG_CODE_LIC_RESPONSE 0xff020000 1717 #define FW_MSG_CODE_VIRT_MAC_PRIM 0xff030000 1718 #define FW_MSG_CODE_VIRT_MAC_ISCSI 0xff040000 1719 1720 #define FW_MSG_CODE_IMG_OFFSET_RESPONSE 0xe2100000 1721 #define FW_MSG_CODE_IMG_SIZE_RESPONSE 0xe3100000 1722 1723 #define FW_MSG_SEQ_NUMBER_MASK 0x0000ffff 1724 1725 uint32_t fw_mb_param; 1726 1727 #define FW_PARAM_INVALID_IMG 0xffffffff 1728 1729 uint32_t drv_pulse_mb; 1730 #define DRV_PULSE_SEQ_MASK 0x00007fff 1731 #define DRV_PULSE_SYSTEM_TIME_MASK 0xffff0000 1732 /* 1733 * The system time is in the format of 1734 * (year-2001)*12*32 + month*32 + day. 1735 */ 1736 #define DRV_PULSE_ALWAYS_ALIVE 0x00008000 1737 /* 1738 * Indicate to the firmware not to go into the 1739 * OS-absent when it is not getting driver pulse. 1740 * This is used for debugging as well for PXE(MBA). 1741 */ 1742 1743 uint32_t mcp_pulse_mb; 1744 #define MCP_PULSE_SEQ_MASK 0x00007fff 1745 #define MCP_PULSE_ALWAYS_ALIVE 0x00008000 1746 /* Indicates to the driver not to assert due to lack 1747 * of MCP response */ 1748 #define MCP_EVENT_MASK 0xffff0000 1749 #define MCP_EVENT_OTHER_DRIVER_RESET_REQ 0x00010000 1750 1751 uint32_t iscsi_boot_signature; 1752 uint32_t iscsi_boot_block_offset; 1753 1754 uint32_t drv_status; 1755 #define DRV_STATUS_PMF 0x00000001 1756 #define DRV_STATUS_VF_DISABLED 0x00000002 1757 #define DRV_STATUS_SET_MF_BW 0x00000004 1758 #define DRV_STATUS_LINK_EVENT 0x00000008 1759 1760 #define DRV_STATUS_DCC_EVENT_MASK 0x0000ff00 1761 #define DRV_STATUS_DCC_DISABLE_ENABLE_PF 0x00000100 1762 #define DRV_STATUS_DCC_BANDWIDTH_ALLOCATION 0x00000200 1763 #define DRV_STATUS_DCC_CHANGE_MAC_ADDRESS 0x00000400 1764 #define DRV_STATUS_DCC_RESERVED1 0x00000800 1765 #define DRV_STATUS_DCC_SET_PROTOCOL 0x00001000 1766 #define DRV_STATUS_DCC_SET_PRIORITY 0x00002000 1767 1768 #define DRV_STATUS_DCBX_EVENT_MASK 0x000f0000 1769 #define DRV_STATUS_DCBX_NEGOTIATION_RESULTS 0x00010000 1770 #define DRV_STATUS_AFEX_EVENT_MASK 0x03f00000 1771 #define DRV_STATUS_AFEX_LISTGET_REQ 0x00100000 1772 #define DRV_STATUS_AFEX_LISTSET_REQ 0x00200000 1773 #define DRV_STATUS_AFEX_STATSGET_REQ 0x00400000 1774 #define DRV_STATUS_AFEX_VIFSET_REQ 0x00800000 1775 1776 #define DRV_STATUS_DRV_INFO_REQ 0x04000000 1777 1778 #define DRV_STATUS_EEE_NEGOTIATION_RESULTS 0x08000000 1779 1780 uint32_t virt_mac_upper; 1781 #define VIRT_MAC_SIGN_MASK 0xffff0000 1782 #define VIRT_MAC_SIGNATURE 0x564d0000 1783 uint32_t virt_mac_lower; 1784 1785 }; 1786 1787 1788 /**************************************************************************** 1789 * Management firmware state * 1790 ****************************************************************************/ 1791 /* Allocate 440 bytes for management firmware */ 1792 #define MGMTFW_STATE_WORD_SIZE 110 1793 1794 struct mgmtfw_state { 1795 uint32_t opaque[MGMTFW_STATE_WORD_SIZE]; 1796 }; 1797 1798 1799 /**************************************************************************** 1800 * Multi-Function configuration * 1801 ****************************************************************************/ 1802 struct shared_mf_cfg { 1803 1804 uint32_t clp_mb; 1805 #define SHARED_MF_CLP_SET_DEFAULT 0x00000000 1806 /* set by CLP */ 1807 #define SHARED_MF_CLP_EXIT 0x00000001 1808 /* set by MCP */ 1809 #define SHARED_MF_CLP_EXIT_DONE 0x00010000 1810 1811 }; 1812 1813 struct port_mf_cfg { 1814 1815 uint32_t dynamic_cfg; /* device control channel */ 1816 #define PORT_MF_CFG_E1HOV_TAG_MASK 0x0000ffff 1817 #define PORT_MF_CFG_E1HOV_TAG_SHIFT 0 1818 #define PORT_MF_CFG_E1HOV_TAG_DEFAULT PORT_MF_CFG_E1HOV_TAG_MASK 1819 1820 uint32_t reserved[1]; 1821 1822 }; 1823 1824 struct func_mf_cfg { 1825 1826 uint32_t config; 1827 /* E/R/I/D */ 1828 /* function 0 of each port cannot be hidden */ 1829 #define FUNC_MF_CFG_FUNC_HIDE 0x00000001 1830 1831 #define FUNC_MF_CFG_PROTOCOL_MASK 0x00000006 1832 #define FUNC_MF_CFG_PROTOCOL_FCOE 0x00000000 1833 #define FUNC_MF_CFG_PROTOCOL_ETHERNET 0x00000002 1834 #define FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA 0x00000004 1835 #define FUNC_MF_CFG_PROTOCOL_ISCSI 0x00000006 1836 #define FUNC_MF_CFG_PROTOCOL_DEFAULT \ 1837 FUNC_MF_CFG_PROTOCOL_ETHERNET_WITH_RDMA 1838 1839 #define FUNC_MF_CFG_FUNC_DISABLED 0x00000008 1840 #define FUNC_MF_CFG_FUNC_DELETED 0x00000010 1841 1842 #define FUNC_MF_CFG_FUNC_BOOT_MASK 0x00000060 1843 #define FUNC_MF_CFG_FUNC_BOOT_BIOS_CTRL 0x00000000 1844 #define FUNC_MF_CFG_FUNC_BOOT_VCM_DISABLED 0x00000020 1845 #define FUNC_MF_CFG_FUNC_BOOT_VCM_ENABLED 0x00000040 1846 1847 /* PRI */ 1848 /* 0 - low priority, 3 - high priority */ 1849 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK 0x00000300 1850 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT 8 1851 #define FUNC_MF_CFG_TRANSMIT_PRIORITY_DEFAULT 0x00000000 1852 1853 /* MINBW, MAXBW */ 1854 /* value range - 0..100, increments in 100Mbps */ 1855 #define FUNC_MF_CFG_MIN_BW_MASK 0x00ff0000 1856 #define FUNC_MF_CFG_MIN_BW_SHIFT 16 1857 #define FUNC_MF_CFG_MIN_BW_DEFAULT 0x00000000 1858 #define FUNC_MF_CFG_MAX_BW_MASK 0xff000000 1859 #define FUNC_MF_CFG_MAX_BW_SHIFT 24 1860 #define FUNC_MF_CFG_MAX_BW_DEFAULT 0x64000000 1861 1862 uint32_t mac_upper; /* MAC */ 1863 #define FUNC_MF_CFG_UPPERMAC_MASK 0x0000ffff 1864 #define FUNC_MF_CFG_UPPERMAC_SHIFT 0 1865 #define FUNC_MF_CFG_UPPERMAC_DEFAULT FUNC_MF_CFG_UPPERMAC_MASK 1866 uint32_t mac_lower; 1867 #define FUNC_MF_CFG_LOWERMAC_DEFAULT 0xffffffff 1868 1869 uint32_t e1hov_tag; /* VNI */ 1870 #define FUNC_MF_CFG_E1HOV_TAG_MASK 0x0000ffff 1871 #define FUNC_MF_CFG_E1HOV_TAG_SHIFT 0 1872 #define FUNC_MF_CFG_E1HOV_TAG_DEFAULT FUNC_MF_CFG_E1HOV_TAG_MASK 1873 1874 /* afex default VLAN ID - 12 bits */ 1875 #define FUNC_MF_CFG_AFEX_VLAN_MASK 0x0fff0000 1876 #define FUNC_MF_CFG_AFEX_VLAN_SHIFT 16 1877 1878 uint32_t afex_config; 1879 #define FUNC_MF_CFG_AFEX_COS_FILTER_MASK 0x000000ff 1880 #define FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT 0 1881 #define FUNC_MF_CFG_AFEX_MBA_ENABLED_MASK 0x0000ff00 1882 #define FUNC_MF_CFG_AFEX_MBA_ENABLED_SHIFT 8 1883 #define FUNC_MF_CFG_AFEX_MBA_ENABLED_VAL 0x00000100 1884 #define FUNC_MF_CFG_AFEX_VLAN_MODE_MASK 0x000f0000 1885 #define FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT 16 1886 1887 uint32_t pf_allocation; 1888 /* number of vfs in function, if 0 - sriov disabled */ 1889 #define FUNC_MF_CFG_NUMBER_OF_VFS_MASK 0x000000FF 1890 #define FUNC_MF_CFG_NUMBER_OF_VFS_SHIFT 0 1891 }; 1892 1893 enum mf_cfg_afex_vlan_mode { 1894 FUNC_MF_CFG_AFEX_VLAN_TRUNK_MODE = 0, 1895 FUNC_MF_CFG_AFEX_VLAN_ACCESS_MODE, 1896 FUNC_MF_CFG_AFEX_VLAN_TRUNK_TAG_NATIVE_MODE 1897 }; 1898 1899 /* This structure is not applicable and should not be accessed on 57711 */ 1900 struct func_ext_cfg { 1901 uint32_t func_cfg; 1902 #define MACP_FUNC_CFG_FLAGS_MASK 0x0000007F 1903 #define MACP_FUNC_CFG_FLAGS_SHIFT 0 1904 #define MACP_FUNC_CFG_FLAGS_ENABLED 0x00000001 1905 #define MACP_FUNC_CFG_FLAGS_ETHERNET 0x00000002 1906 #define MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD 0x00000004 1907 #define MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD 0x00000008 1908 #define MACP_FUNC_CFG_PAUSE_ON_HOST_RING 0x00000080 1909 1910 uint32_t iscsi_mac_addr_upper; 1911 uint32_t iscsi_mac_addr_lower; 1912 1913 uint32_t fcoe_mac_addr_upper; 1914 uint32_t fcoe_mac_addr_lower; 1915 1916 uint32_t fcoe_wwn_port_name_upper; 1917 uint32_t fcoe_wwn_port_name_lower; 1918 1919 uint32_t fcoe_wwn_node_name_upper; 1920 uint32_t fcoe_wwn_node_name_lower; 1921 1922 uint32_t preserve_data; 1923 #define MF_FUNC_CFG_PRESERVE_L2_MAC (1<<0) 1924 #define MF_FUNC_CFG_PRESERVE_ISCSI_MAC (1<<1) 1925 #define MF_FUNC_CFG_PRESERVE_FCOE_MAC (1<<2) 1926 #define MF_FUNC_CFG_PRESERVE_FCOE_WWN_P (1<<3) 1927 #define MF_FUNC_CFG_PRESERVE_FCOE_WWN_N (1<<4) 1928 #define MF_FUNC_CFG_PRESERVE_TX_BW (1<<5) 1929 }; 1930 1931 struct mf_cfg { 1932 1933 struct shared_mf_cfg shared_mf_config; /* 0x4 */ 1934 struct port_mf_cfg port_mf_config[NVM_PATH_MAX][PORT_MAX]; 1935 /* 0x10*2=0x20 */ 1936 /* for all chips, there are 8 mf functions */ 1937 struct func_mf_cfg func_mf_config[E1H_FUNC_MAX]; /* 0x18 * 8 = 0xc0 */ 1938 /* 1939 * Extended configuration per function - this array does not exist and 1940 * should not be accessed on 57711 1941 */ 1942 struct func_ext_cfg func_ext_config[E1H_FUNC_MAX]; /* 0x28 * 8 = 0x140*/ 1943 }; /* 0x224 */ 1944 1945 /**************************************************************************** 1946 * Shared Memory Region * 1947 ****************************************************************************/ 1948 struct shmem_region { /* SharedMem Offset (size) */ 1949 1950 uint32_t validity_map[PORT_MAX]; /* 0x0 (4*2 = 0x8) */ 1951 #define SHR_MEM_FORMAT_REV_MASK 0xff000000 1952 #define SHR_MEM_FORMAT_REV_ID ('A'<<24) 1953 /* validity bits */ 1954 #define SHR_MEM_VALIDITY_PCI_CFG 0x00100000 1955 #define SHR_MEM_VALIDITY_MB 0x00200000 1956 #define SHR_MEM_VALIDITY_DEV_INFO 0x00400000 1957 #define SHR_MEM_VALIDITY_RESERVED 0x00000007 1958 /* One licensing bit should be set */ 1959 #define SHR_MEM_VALIDITY_LIC_KEY_IN_EFFECT_MASK 0x00000038 1960 #define SHR_MEM_VALIDITY_LIC_MANUF_KEY_IN_EFFECT 0x00000008 1961 #define SHR_MEM_VALIDITY_LIC_UPGRADE_KEY_IN_EFFECT 0x00000010 1962 #define SHR_MEM_VALIDITY_LIC_NO_KEY_IN_EFFECT 0x00000020 1963 /* Active MFW */ 1964 #define SHR_MEM_VALIDITY_ACTIVE_MFW_UNKNOWN 0x00000000 1965 #define SHR_MEM_VALIDITY_ACTIVE_MFW_MASK 0x000001c0 1966 #define SHR_MEM_VALIDITY_ACTIVE_MFW_IPMI 0x00000040 1967 #define SHR_MEM_VALIDITY_ACTIVE_MFW_UMP 0x00000080 1968 #define SHR_MEM_VALIDITY_ACTIVE_MFW_NCSI 0x000000c0 1969 #define SHR_MEM_VALIDITY_ACTIVE_MFW_NONE 0x000001c0 1970 1971 struct shm_dev_info dev_info; /* 0x8 (0x438) */ 1972 1973 license_key_t drv_lic_key[PORT_MAX]; /* 0x440 (52*2=0x68) */ 1974 1975 /* FW information (for internal FW use) */ 1976 uint32_t fw_info_fio_offset; /* 0x4a8 (0x4) */ 1977 struct mgmtfw_state mgmtfw_state; /* 0x4ac (0x1b8) */ 1978 1979 struct drv_port_mb port_mb[PORT_MAX]; /* 0x664 (16*2=0x20) */ 1980 1981 1982 #ifdef BMAPI 1983 /* This is a variable length array */ 1984 /* the number of function depends on the chip type */ 1985 struct drv_func_mb func_mb[1]; /* 0x684 (44*2/4/8=0x58/0xb0/0x160) */ 1986 #else 1987 /* the number of function depends on the chip type */ 1988 struct drv_func_mb func_mb[]; /* 0x684 (44*2/4/8=0x58/0xb0/0x160) */ 1989 #endif /* BMAPI */ 1990 1991 }; /* 57710 = 0x6dc | 57711 = 0x7E4 | 57712 = 0x734 */ 1992 1993 /**************************************************************************** 1994 * Shared Memory 2 Region * 1995 ****************************************************************************/ 1996 /* The fw_flr_ack is actually built in the following way: */ 1997 /* 8 bit: PF ack */ 1998 /* 64 bit: VF ack */ 1999 /* 8 bit: ios_dis_ack */ 2000 /* In order to maintain endianity in the mailbox hsi, we want to keep using */ 2001 /* uint32_t. The fw must have the VF right after the PF since this is how it */ 2002 /* access arrays(it expects always the VF to reside after the PF, and that */ 2003 /* makes the calculation much easier for it. ) */ 2004 /* In order to answer both limitations, and keep the struct small, the code */ 2005 /* will abuse the structure defined here to achieve the actual partition */ 2006 /* above */ 2007 /****************************************************************************/ 2008 struct fw_flr_ack { 2009 uint32_t pf_ack; 2010 uint32_t vf_ack[1]; 2011 uint32_t iov_dis_ack; 2012 }; 2013 2014 struct fw_flr_mb { 2015 uint32_t aggint; 2016 uint32_t opgen_addr; 2017 struct fw_flr_ack ack; 2018 }; 2019 2020 struct eee_remote_vals { 2021 uint32_t tx_tw; 2022 uint32_t rx_tw; 2023 }; 2024 2025 /**** SUPPORT FOR SHMEM ARRRAYS *** 2026 * The SHMEM HSI is aligned on 32 bit boundaries which makes it difficult to 2027 * define arrays with storage types smaller then unsigned dwords. 2028 * The macros below add generic support for SHMEM arrays with numeric elements 2029 * that can span 2,4,8 or 16 bits. The array underlying type is a 32 bit dword 2030 * array with individual bit-filed elements accessed using shifts and masks. 2031 * 2032 */ 2033 2034 /* eb is the bitwidth of a single element */ 2035 #define SHMEM_ARRAY_MASK(eb) ((1<<(eb))-1) 2036 #define SHMEM_ARRAY_ENTRY(i, eb) ((i)/(32/(eb))) 2037 2038 /* the bit-position macro allows the used to flip the order of the arrays 2039 * elements on a per byte or word boundary. 2040 * 2041 * example: an array with 8 entries each 4 bit wide. This array will fit into 2042 * a single dword. The diagrmas below show the array order of the nibbles. 2043 * 2044 * SHMEM_ARRAY_BITPOS(i, 4, 4) defines the stadard ordering: 2045 * 2046 * | | | | 2047 * 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 2048 * | | | | 2049 * 2050 * SHMEM_ARRAY_BITPOS(i, 4, 8) defines a flip ordering per byte: 2051 * 2052 * | | | | 2053 * 1 | 0 | 3 | 2 | 5 | 4 | 7 | 6 | 2054 * | | | | 2055 * 2056 * SHMEM_ARRAY_BITPOS(i, 4, 16) defines a flip ordering per word: 2057 * 2058 * | | | | 2059 * 3 | 2 | 1 | 0 | 7 | 6 | 5 | 4 | 2060 * | | | | 2061 */ 2062 #define SHMEM_ARRAY_BITPOS(i, eb, fb) \ 2063 ((((32/(fb)) - 1 - ((i)/((fb)/(eb))) % (32/(fb))) * (fb)) + \ 2064 (((i)%((fb)/(eb))) * (eb))) 2065 2066 #define SHMEM_ARRAY_GET(a, i, eb, fb) \ 2067 ((a[SHMEM_ARRAY_ENTRY(i, eb)] >> SHMEM_ARRAY_BITPOS(i, eb, fb)) & \ 2068 SHMEM_ARRAY_MASK(eb)) 2069 2070 #define SHMEM_ARRAY_SET(a, i, eb, fb, val) \ 2071 do { \ 2072 a[SHMEM_ARRAY_ENTRY(i, eb)] &= ~(SHMEM_ARRAY_MASK(eb) << \ 2073 SHMEM_ARRAY_BITPOS(i, eb, fb)); \ 2074 a[SHMEM_ARRAY_ENTRY(i, eb)] |= (((val) & SHMEM_ARRAY_MASK(eb)) << \ 2075 SHMEM_ARRAY_BITPOS(i, eb, fb)); \ 2076 } while (0) 2077 2078 2079 /****START OF DCBX STRUCTURES DECLARATIONS****/ 2080 #define DCBX_MAX_NUM_PRI_PG_ENTRIES 8 2081 #define DCBX_PRI_PG_BITWIDTH 4 2082 #define DCBX_PRI_PG_FBITS 8 2083 #define DCBX_PRI_PG_GET(a, i) \ 2084 SHMEM_ARRAY_GET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS) 2085 #define DCBX_PRI_PG_SET(a, i, val) \ 2086 SHMEM_ARRAY_SET(a, i, DCBX_PRI_PG_BITWIDTH, DCBX_PRI_PG_FBITS, val) 2087 #define DCBX_MAX_NUM_PG_BW_ENTRIES 8 2088 #define DCBX_BW_PG_BITWIDTH 8 2089 #define DCBX_PG_BW_GET(a, i) \ 2090 SHMEM_ARRAY_GET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH) 2091 #define DCBX_PG_BW_SET(a, i, val) \ 2092 SHMEM_ARRAY_SET(a, i, DCBX_BW_PG_BITWIDTH, DCBX_BW_PG_BITWIDTH, val) 2093 #define DCBX_STRICT_PRI_PG 15 2094 #define DCBX_MAX_APP_PROTOCOL 16 2095 #define DCBX_MAX_APP_LOCAL 32 2096 #define FCOE_APP_IDX 0 2097 #define ISCSI_APP_IDX 1 2098 #define PREDEFINED_APP_IDX_MAX 2 2099 2100 2101 /* Big/Little endian have the same representation. */ 2102 struct dcbx_ets_feature { 2103 /* 2104 * For Admin MIB - is this feature supported by the 2105 * driver | For Local MIB - should this feature be enabled. 2106 */ 2107 uint32_t enabled; 2108 uint32_t pg_bw_tbl[2]; 2109 uint32_t pri_pg_tbl[1]; 2110 }; 2111 2112 /* Driver structure in LE */ 2113 struct dcbx_pfc_feature { 2114 #ifdef __BIG_ENDIAN 2115 uint8_t pri_en_bitmap; 2116 #define DCBX_PFC_PRI_0 0x01 2117 #define DCBX_PFC_PRI_1 0x02 2118 #define DCBX_PFC_PRI_2 0x04 2119 #define DCBX_PFC_PRI_3 0x08 2120 #define DCBX_PFC_PRI_4 0x10 2121 #define DCBX_PFC_PRI_5 0x20 2122 #define DCBX_PFC_PRI_6 0x40 2123 #define DCBX_PFC_PRI_7 0x80 2124 uint8_t pfc_caps; 2125 uint8_t reserved; 2126 uint8_t enabled; 2127 #elif defined(__LITTLE_ENDIAN) 2128 uint8_t enabled; 2129 uint8_t reserved; 2130 uint8_t pfc_caps; 2131 uint8_t pri_en_bitmap; 2132 #define DCBX_PFC_PRI_0 0x01 2133 #define DCBX_PFC_PRI_1 0x02 2134 #define DCBX_PFC_PRI_2 0x04 2135 #define DCBX_PFC_PRI_3 0x08 2136 #define DCBX_PFC_PRI_4 0x10 2137 #define DCBX_PFC_PRI_5 0x20 2138 #define DCBX_PFC_PRI_6 0x40 2139 #define DCBX_PFC_PRI_7 0x80 2140 #endif 2141 }; 2142 2143 struct dcbx_app_priority_entry { 2144 #ifdef __BIG_ENDIAN 2145 uint16_t app_id; 2146 uint8_t pri_bitmap; 2147 uint8_t appBitfield; 2148 #define DCBX_APP_ENTRY_VALID 0x01 2149 #define DCBX_APP_ENTRY_SF_MASK 0x30 2150 #define DCBX_APP_ENTRY_SF_SHIFT 4 2151 #define DCBX_APP_SF_ETH_TYPE 0x10 2152 #define DCBX_APP_SF_PORT 0x20 2153 #elif defined(__LITTLE_ENDIAN) 2154 uint8_t appBitfield; 2155 #define DCBX_APP_ENTRY_VALID 0x01 2156 #define DCBX_APP_ENTRY_SF_MASK 0x30 2157 #define DCBX_APP_ENTRY_SF_SHIFT 4 2158 #define DCBX_APP_SF_ETH_TYPE 0x10 2159 #define DCBX_APP_SF_PORT 0x20 2160 uint8_t pri_bitmap; 2161 uint16_t app_id; 2162 #endif 2163 }; 2164 2165 2166 /* FW structure in BE */ 2167 struct dcbx_app_priority_feature { 2168 #ifdef __BIG_ENDIAN 2169 uint8_t reserved; 2170 uint8_t default_pri; 2171 uint8_t tc_supported; 2172 uint8_t enabled; 2173 #elif defined(__LITTLE_ENDIAN) 2174 uint8_t enabled; 2175 uint8_t tc_supported; 2176 uint8_t default_pri; 2177 uint8_t reserved; 2178 #endif 2179 struct dcbx_app_priority_entry app_pri_tbl[DCBX_MAX_APP_PROTOCOL]; 2180 }; 2181 2182 /* FW structure in BE */ 2183 struct dcbx_features { 2184 /* PG feature */ 2185 struct dcbx_ets_feature ets; 2186 /* PFC feature */ 2187 struct dcbx_pfc_feature pfc; 2188 /* APP feature */ 2189 struct dcbx_app_priority_feature app; 2190 }; 2191 2192 /* LLDP protocol parameters */ 2193 /* FW structure in BE */ 2194 struct lldp_params { 2195 #ifdef __BIG_ENDIAN 2196 uint8_t msg_fast_tx_interval; 2197 uint8_t msg_tx_hold; 2198 uint8_t msg_tx_interval; 2199 uint8_t admin_status; 2200 #define LLDP_TX_ONLY 0x01 2201 #define LLDP_RX_ONLY 0x02 2202 #define LLDP_TX_RX 0x03 2203 #define LLDP_DISABLED 0x04 2204 uint8_t reserved1; 2205 uint8_t tx_fast; 2206 uint8_t tx_crd_max; 2207 uint8_t tx_crd; 2208 #elif defined(__LITTLE_ENDIAN) 2209 uint8_t admin_status; 2210 #define LLDP_TX_ONLY 0x01 2211 #define LLDP_RX_ONLY 0x02 2212 #define LLDP_TX_RX 0x03 2213 #define LLDP_DISABLED 0x04 2214 uint8_t msg_tx_interval; 2215 uint8_t msg_tx_hold; 2216 uint8_t msg_fast_tx_interval; 2217 uint8_t tx_crd; 2218 uint8_t tx_crd_max; 2219 uint8_t tx_fast; 2220 uint8_t reserved1; 2221 #endif 2222 #define REM_CHASSIS_ID_STAT_LEN 4 2223 #define REM_PORT_ID_STAT_LEN 4 2224 /* Holds remote Chassis ID TLV header, subtype and 9B of payload. */ 2225 uint32_t peer_chassis_id[REM_CHASSIS_ID_STAT_LEN]; 2226 /* Holds remote Port ID TLV header, subtype and 9B of payload. */ 2227 uint32_t peer_port_id[REM_PORT_ID_STAT_LEN]; 2228 }; 2229 2230 struct lldp_dcbx_stat { 2231 #define LOCAL_CHASSIS_ID_STAT_LEN 2 2232 #define LOCAL_PORT_ID_STAT_LEN 2 2233 /* Holds local Chassis ID 8B payload of constant subtype 4. */ 2234 uint32_t local_chassis_id[LOCAL_CHASSIS_ID_STAT_LEN]; 2235 /* Holds local Port ID 8B payload of constant subtype 3. */ 2236 uint32_t local_port_id[LOCAL_PORT_ID_STAT_LEN]; 2237 /* Number of DCBX frames transmitted. */ 2238 uint32_t num_tx_dcbx_pkts; 2239 /* Number of DCBX frames received. */ 2240 uint32_t num_rx_dcbx_pkts; 2241 }; 2242 2243 /* ADMIN MIB - DCBX local machine default configuration. */ 2244 struct lldp_admin_mib { 2245 uint32_t ver_cfg_flags; 2246 #define DCBX_ETS_CONFIG_TX_ENABLED 0x00000001 2247 #define DCBX_PFC_CONFIG_TX_ENABLED 0x00000002 2248 #define DCBX_APP_CONFIG_TX_ENABLED 0x00000004 2249 #define DCBX_ETS_RECO_TX_ENABLED 0x00000008 2250 #define DCBX_ETS_RECO_VALID 0x00000010 2251 #define DCBX_ETS_WILLING 0x00000020 2252 #define DCBX_PFC_WILLING 0x00000040 2253 #define DCBX_APP_WILLING 0x00000080 2254 #define DCBX_VERSION_CEE 0x00000100 2255 #define DCBX_VERSION_IEEE 0x00000200 2256 #define DCBX_DCBX_ENABLED 0x00000400 2257 #define DCBX_CEE_VERSION_MASK 0x0000f000 2258 #define DCBX_CEE_VERSION_SHIFT 12 2259 #define DCBX_CEE_MAX_VERSION_MASK 0x000f0000 2260 #define DCBX_CEE_MAX_VERSION_SHIFT 16 2261 struct dcbx_features features; 2262 }; 2263 2264 /* REMOTE MIB - remote machine DCBX configuration. */ 2265 struct lldp_remote_mib { 2266 uint32_t prefix_seq_num; 2267 uint32_t flags; 2268 #define DCBX_ETS_TLV_RX 0x00000001 2269 #define DCBX_PFC_TLV_RX 0x00000002 2270 #define DCBX_APP_TLV_RX 0x00000004 2271 #define DCBX_ETS_RX_ERROR 0x00000010 2272 #define DCBX_PFC_RX_ERROR 0x00000020 2273 #define DCBX_APP_RX_ERROR 0x00000040 2274 #define DCBX_ETS_REM_WILLING 0x00000100 2275 #define DCBX_PFC_REM_WILLING 0x00000200 2276 #define DCBX_APP_REM_WILLING 0x00000400 2277 #define DCBX_REMOTE_ETS_RECO_VALID 0x00001000 2278 #define DCBX_REMOTE_MIB_VALID 0x00002000 2279 struct dcbx_features features; 2280 uint32_t suffix_seq_num; 2281 }; 2282 2283 /* LOCAL MIB - operational DCBX configuration - transmitted on Tx LLDPDU. */ 2284 struct lldp_local_mib { 2285 uint32_t prefix_seq_num; 2286 /* Indicates if there is mismatch with negotiation results. */ 2287 uint32_t error; 2288 #define DCBX_LOCAL_ETS_ERROR 0x00000001 2289 #define DCBX_LOCAL_PFC_ERROR 0x00000002 2290 #define DCBX_LOCAL_APP_ERROR 0x00000004 2291 #define DCBX_LOCAL_PFC_MISMATCH 0x00000010 2292 #define DCBX_LOCAL_APP_MISMATCH 0x00000020 2293 #define DCBX_REMOTE_MIB_ERROR 0x00000040 2294 #define DCBX_REMOTE_ETS_TLV_NOT_FOUND 0x00000080 2295 #define DCBX_REMOTE_PFC_TLV_NOT_FOUND 0x00000100 2296 #define DCBX_REMOTE_APP_TLV_NOT_FOUND 0x00000200 2297 struct dcbx_features features; 2298 uint32_t suffix_seq_num; 2299 }; 2300 2301 struct lldp_local_mib_ext { 2302 uint32_t prefix_seq_num; 2303 /* APP TLV extension - 16 more entries for negotiation results*/ 2304 struct dcbx_app_priority_entry app_pri_tbl_ext[DCBX_MAX_APP_PROTOCOL]; 2305 uint32_t suffix_seq_num; 2306 }; 2307 /***END OF DCBX STRUCTURES DECLARATIONS***/ 2308 2309 /***********************************************************/ 2310 /* Elink section */ 2311 /***********************************************************/ 2312 #define SHMEM_LINK_CONFIG_SIZE 2 2313 struct shmem_lfa { 2314 uint32_t req_duplex; 2315 #define REQ_DUPLEX_PHY0_MASK 0x0000ffff 2316 #define REQ_DUPLEX_PHY0_SHIFT 0 2317 #define REQ_DUPLEX_PHY1_MASK 0xffff0000 2318 #define REQ_DUPLEX_PHY1_SHIFT 16 2319 uint32_t req_flow_ctrl; 2320 #define REQ_FLOW_CTRL_PHY0_MASK 0x0000ffff 2321 #define REQ_FLOW_CTRL_PHY0_SHIFT 0 2322 #define REQ_FLOW_CTRL_PHY1_MASK 0xffff0000 2323 #define REQ_FLOW_CTRL_PHY1_SHIFT 16 2324 uint32_t req_line_speed; /* Also determine AutoNeg */ 2325 #define REQ_LINE_SPD_PHY0_MASK 0x0000ffff 2326 #define REQ_LINE_SPD_PHY0_SHIFT 0 2327 #define REQ_LINE_SPD_PHY1_MASK 0xffff0000 2328 #define REQ_LINE_SPD_PHY1_SHIFT 16 2329 uint32_t speed_cap_mask[SHMEM_LINK_CONFIG_SIZE]; 2330 uint32_t additional_config; 2331 #define REQ_FC_AUTO_ADV_MASK 0x0000ffff 2332 #define REQ_FC_AUTO_ADV0_SHIFT 0 2333 #define NO_LFA_DUE_TO_DCC_MASK 0x00010000 2334 uint32_t lfa_sts; 2335 #define LFA_LINK_FLAP_REASON_OFFSET 0 2336 #define LFA_LINK_FLAP_REASON_MASK 0x000000ff 2337 #define LFA_LINK_DOWN 0x1 2338 #define LFA_LOOPBACK_ENABLED 0x2 2339 #define LFA_DUPLEX_MISMATCH 0x3 2340 #define LFA_MFW_IS_TOO_OLD 0x4 2341 #define LFA_LINK_SPEED_MISMATCH 0x5 2342 #define LFA_FLOW_CTRL_MISMATCH 0x6 2343 #define LFA_SPEED_CAP_MISMATCH 0x7 2344 #define LFA_DCC_LFA_DISABLED 0x8 2345 #define LFA_EEE_MISMATCH 0x9 2346 2347 #define LINK_FLAP_AVOIDANCE_COUNT_OFFSET 8 2348 #define LINK_FLAP_AVOIDANCE_COUNT_MASK 0x0000ff00 2349 2350 #define LINK_FLAP_COUNT_OFFSET 16 2351 #define LINK_FLAP_COUNT_MASK 0x00ff0000 2352 2353 #define LFA_FLAGS_MASK 0xff000000 2354 #define SHMEM_LFA_DONT_CLEAR_STAT (1<<24) 2355 2356 }; 2357 2358 struct shmem2_region { 2359 2360 uint32_t size; /* 0x0000 */ 2361 2362 uint32_t dcc_support; /* 0x0004 */ 2363 #define SHMEM_DCC_SUPPORT_NONE 0x00000000 2364 #define SHMEM_DCC_SUPPORT_DISABLE_ENABLE_PF_TLV 0x00000001 2365 #define SHMEM_DCC_SUPPORT_BANDWIDTH_ALLOCATION_TLV 0x00000004 2366 #define SHMEM_DCC_SUPPORT_CHANGE_MAC_ADDRESS_TLV 0x00000008 2367 #define SHMEM_DCC_SUPPORT_SET_PROTOCOL_TLV 0x00000040 2368 #define SHMEM_DCC_SUPPORT_SET_PRIORITY_TLV 0x00000080 2369 2370 uint32_t ext_phy_fw_version2[PORT_MAX]; /* 0x0008 */ 2371 /* 2372 * For backwards compatibility, if the mf_cfg_addr does not exist 2373 * (the size filed is smaller than 0xc) the mf_cfg resides at the 2374 * end of struct shmem_region 2375 */ 2376 uint32_t mf_cfg_addr; /* 0x0010 */ 2377 #define SHMEM_MF_CFG_ADDR_NONE 0x00000000 2378 2379 struct fw_flr_mb flr_mb; /* 0x0014 */ 2380 uint32_t dcbx_lldp_params_offset; /* 0x0028 */ 2381 #define SHMEM_LLDP_DCBX_PARAMS_NONE 0x00000000 2382 uint32_t dcbx_neg_res_offset; /* 0x002c */ 2383 #define SHMEM_DCBX_NEG_RES_NONE 0x00000000 2384 uint32_t dcbx_remote_mib_offset; /* 0x0030 */ 2385 #define SHMEM_DCBX_REMOTE_MIB_NONE 0x00000000 2386 /* 2387 * The other shmemX_base_addr holds the other path's shmem address 2388 * required for example in case of common phy init, or for path1 to know 2389 * the address of mcp debug trace which is located in offset from shmem 2390 * of path0 2391 */ 2392 uint32_t other_shmem_base_addr; /* 0x0034 */ 2393 uint32_t other_shmem2_base_addr; /* 0x0038 */ 2394 /* 2395 * mcp_vf_disabled is set by the MCP to indicate the driver about VFs 2396 * which were disabled/flred 2397 */ 2398 uint32_t mcp_vf_disabled[E2_VF_MAX / 32]; /* 0x003c */ 2399 2400 /* 2401 * drv_ack_vf_disabled is set by the PF driver to ack handled disabled 2402 * VFs 2403 */ 2404 uint32_t drv_ack_vf_disabled[E2_FUNC_MAX][E2_VF_MAX / 32]; /* 0x0044 */ 2405 2406 uint32_t dcbx_lldp_dcbx_stat_offset; /* 0x0064 */ 2407 #define SHMEM_LLDP_DCBX_STAT_NONE 0x00000000 2408 2409 /* 2410 * edebug_driver_if field is used to transfer messages between edebug 2411 * app to the driver through shmem2. 2412 * 2413 * message format: 2414 * bits 0-2 - function number / instance of driver to perform request 2415 * bits 3-5 - op code / is_ack? 2416 * bits 6-63 - data 2417 */ 2418 uint32_t edebug_driver_if[2]; /* 0x0068 */ 2419 #define EDEBUG_DRIVER_IF_OP_CODE_GET_PHYS_ADDR 1 2420 #define EDEBUG_DRIVER_IF_OP_CODE_GET_BUS_ADDR 2 2421 #define EDEBUG_DRIVER_IF_OP_CODE_DISABLE_STAT 3 2422 2423 uint32_t nvm_retain_bitmap_addr; /* 0x0070 */ 2424 2425 /* afex support of that driver */ 2426 uint32_t afex_driver_support; /* 0x0074 */ 2427 #define SHMEM_AFEX_VERSION_MASK 0x100f 2428 #define SHMEM_AFEX_SUPPORTED_VERSION_ONE 0x1001 2429 #define SHMEM_AFEX_REDUCED_DRV_LOADED 0x8000 2430 2431 /* driver receives addr in scratchpad to which it should respond */ 2432 uint32_t afex_scratchpad_addr_to_write[E2_FUNC_MAX]; 2433 2434 /* 2435 * generic params from MCP to driver (value depends on the msg sent 2436 * to driver 2437 */ 2438 uint32_t afex_param1_to_driver[E2_FUNC_MAX]; /* 0x0088 */ 2439 uint32_t afex_param2_to_driver[E2_FUNC_MAX]; /* 0x0098 */ 2440 2441 uint32_t swim_base_addr; /* 0x0108 */ 2442 uint32_t swim_funcs; 2443 uint32_t swim_main_cb; 2444 2445 /* 2446 * bitmap notifying which VIF profiles stored in nvram are enabled by 2447 * switch 2448 */ 2449 uint32_t afex_profiles_enabled[2]; 2450 2451 /* generic flags controlled by the driver */ 2452 uint32_t drv_flags; 2453 #define DRV_FLAGS_DCB_CONFIGURED 0x0 2454 #define DRV_FLAGS_DCB_CONFIGURATION_ABORTED 0x1 2455 #define DRV_FLAGS_DCB_MFW_CONFIGURED 0x2 2456 2457 #define DRV_FLAGS_PORT_MASK ((1 << DRV_FLAGS_DCB_CONFIGURED) | \ 2458 (1 << DRV_FLAGS_DCB_CONFIGURATION_ABORTED) | \ 2459 (1 << DRV_FLAGS_DCB_MFW_CONFIGURED)) 2460 /* Port offset*/ 2461 #define DRV_FLAGS_P0_OFFSET 0 2462 #define DRV_FLAGS_P1_OFFSET 16 2463 #define DRV_FLAGS_GET_PORT_OFFSET(_port) ((0 == _port) ? \ 2464 DRV_FLAGS_P0_OFFSET : \ 2465 DRV_FLAGS_P1_OFFSET) 2466 2467 #define DRV_FLAGS_GET_PORT_MASK(_port) (DRV_FLAGS_PORT_MASK << \ 2468 DRV_FLAGS_GET_PORT_OFFSET(_port)) 2469 2470 #define DRV_FLAGS_FILED_BY_PORT(_field_bit, _port) (1 << ( \ 2471 (_field_bit) + DRV_FLAGS_GET_PORT_OFFSET(_port))) 2472 2473 /* pointer to extended dev_info shared data copied from nvm image */ 2474 uint32_t extended_dev_info_shared_addr; 2475 uint32_t ncsi_oem_data_addr; 2476 2477 uint32_t sensor_data_addr; 2478 uint32_t buffer_block_addr; 2479 uint32_t sensor_data_req_update_interval; 2480 uint32_t temperature_in_half_celsius; 2481 uint32_t glob_struct_in_host; 2482 2483 uint32_t dcbx_neg_res_ext_offset; 2484 #define SHMEM_DCBX_NEG_RES_EXT_NONE 0x00000000 2485 2486 uint32_t drv_capabilities_flag[E2_FUNC_MAX]; 2487 #define DRV_FLAGS_CAPABILITIES_LOADED_SUPPORTED 0x00000001 2488 #define DRV_FLAGS_CAPABILITIES_LOADED_L2 0x00000002 2489 #define DRV_FLAGS_CAPABILITIES_LOADED_FCOE 0x00000004 2490 #define DRV_FLAGS_CAPABILITIES_LOADED_ISCSI 0x00000008 2491 2492 uint32_t extended_dev_info_shared_cfg_size; 2493 2494 uint32_t dcbx_en[PORT_MAX]; 2495 2496 /* The offset points to the multi threaded meta structure */ 2497 uint32_t multi_thread_data_offset; 2498 2499 /* address of DMAable host address holding values from the drivers */ 2500 uint32_t drv_info_host_addr_lo; 2501 uint32_t drv_info_host_addr_hi; 2502 2503 /* general values written by the MFW (such as current version) */ 2504 uint32_t drv_info_control; 2505 #define DRV_INFO_CONTROL_VER_MASK 0x000000ff 2506 #define DRV_INFO_CONTROL_VER_SHIFT 0 2507 #define DRV_INFO_CONTROL_OP_CODE_MASK 0x0000ff00 2508 #define DRV_INFO_CONTROL_OP_CODE_SHIFT 8 2509 uint32_t ibft_host_addr; /* initialized by option ROM */ 2510 2511 struct eee_remote_vals eee_remote_vals[PORT_MAX]; 2512 uint32_t pf_allocation[E2_FUNC_MAX]; 2513 #define PF_ALLOACTION_MSIX_VECTORS_MASK 0x000000ff /* real value, as PCI config space can show only maximum of 64 vectors */ 2514 #define PF_ALLOACTION_MSIX_VECTORS_SHIFT 0 2515 2516 /* the status of EEE auto-negotiation 2517 * bits 15:0 the configured tx-lpi entry timer value. Depends on bit 31. 2518 * bits 19:16 the supported modes for EEE. 2519 * bits 23:20 the speeds advertised for EEE. 2520 * bits 27:24 the speeds the Link partner advertised for EEE. 2521 * The supported/adv. modes in bits 27:19 originate from the 2522 * SHMEM_EEE_XXX_ADV definitions (where XXX is replaced by speed). 2523 * bit 28 when 1'b1 EEE was requested. 2524 * bit 29 when 1'b1 tx lpi was requested. 2525 * bit 30 when 1'b1 EEE was negotiated. Tx lpi will be asserted iff 2526 * 30:29 are 2'b11. 2527 * bit 31 when 1'b0 bits 15:0 contain a PORT_FEAT_CFG_EEE_ define as 2528 * value. When 1'b1 those bits contains a value times 16 microseconds. 2529 */ 2530 uint32_t eee_status[PORT_MAX]; 2531 #define SHMEM_EEE_TIMER_MASK 0x0000ffff 2532 #define SHMEM_EEE_SUPPORTED_MASK 0x000f0000 2533 #define SHMEM_EEE_SUPPORTED_SHIFT 16 2534 #define SHMEM_EEE_ADV_STATUS_MASK 0x00f00000 2535 #define SHMEM_EEE_100M_ADV (1<<0) 2536 #define SHMEM_EEE_1G_ADV (1<<1) 2537 #define SHMEM_EEE_10G_ADV (1<<2) 2538 #define SHMEM_EEE_ADV_STATUS_SHIFT 20 2539 #define SHMEM_EEE_LP_ADV_STATUS_MASK 0x0f000000 2540 #define SHMEM_EEE_LP_ADV_STATUS_SHIFT 24 2541 #define SHMEM_EEE_REQUESTED_BIT 0x10000000 2542 #define SHMEM_EEE_LPI_REQUESTED_BIT 0x20000000 2543 #define SHMEM_EEE_ACTIVE_BIT 0x40000000 2544 #define SHMEM_EEE_TIME_OUTPUT_BIT 0x80000000 2545 2546 uint32_t sizeof_port_stats; 2547 2548 /* Link Flap Avoidance */ 2549 uint32_t lfa_host_addr[PORT_MAX]; 2550 2551 /* External PHY temperature in deg C. */ 2552 uint32_t extphy_temps_in_celsius; 2553 #define EXTPHY1_TEMP_MASK 0x0000ffff 2554 #define EXTPHY1_TEMP_SHIFT 0 2555 2556 uint32_t ocdata_info_addr; /* Offset 0x148 */ 2557 uint32_t drv_func_info_addr; /* Offset 0x14C */ 2558 uint32_t drv_func_info_size; /* Offset 0x150 */ 2559 uint32_t link_attr_sync[PORT_MAX]; /* Offset 0x154 */ 2560 #define LINK_ATTR_SYNC_KR2_ENABLE (1<<0) 2561 }; 2562 2563 2564 struct emac_stats { 2565 uint32_t rx_stat_ifhcinoctets; 2566 uint32_t rx_stat_ifhcinbadoctets; 2567 uint32_t rx_stat_etherstatsfragments; 2568 uint32_t rx_stat_ifhcinucastpkts; 2569 uint32_t rx_stat_ifhcinmulticastpkts; 2570 uint32_t rx_stat_ifhcinbroadcastpkts; 2571 uint32_t rx_stat_dot3statsfcserrors; 2572 uint32_t rx_stat_dot3statsalignmenterrors; 2573 uint32_t rx_stat_dot3statscarriersenseerrors; 2574 uint32_t rx_stat_xonpauseframesreceived; 2575 uint32_t rx_stat_xoffpauseframesreceived; 2576 uint32_t rx_stat_maccontrolframesreceived; 2577 uint32_t rx_stat_xoffstateentered; 2578 uint32_t rx_stat_dot3statsframestoolong; 2579 uint32_t rx_stat_etherstatsjabbers; 2580 uint32_t rx_stat_etherstatsundersizepkts; 2581 uint32_t rx_stat_etherstatspkts64octets; 2582 uint32_t rx_stat_etherstatspkts65octetsto127octets; 2583 uint32_t rx_stat_etherstatspkts128octetsto255octets; 2584 uint32_t rx_stat_etherstatspkts256octetsto511octets; 2585 uint32_t rx_stat_etherstatspkts512octetsto1023octets; 2586 uint32_t rx_stat_etherstatspkts1024octetsto1522octets; 2587 uint32_t rx_stat_etherstatspktsover1522octets; 2588 2589 uint32_t rx_stat_falsecarriererrors; 2590 2591 uint32_t tx_stat_ifhcoutoctets; 2592 uint32_t tx_stat_ifhcoutbadoctets; 2593 uint32_t tx_stat_etherstatscollisions; 2594 uint32_t tx_stat_outxonsent; 2595 uint32_t tx_stat_outxoffsent; 2596 uint32_t tx_stat_flowcontroldone; 2597 uint32_t tx_stat_dot3statssinglecollisionframes; 2598 uint32_t tx_stat_dot3statsmultiplecollisionframes; 2599 uint32_t tx_stat_dot3statsdeferredtransmissions; 2600 uint32_t tx_stat_dot3statsexcessivecollisions; 2601 uint32_t tx_stat_dot3statslatecollisions; 2602 uint32_t tx_stat_ifhcoutucastpkts; 2603 uint32_t tx_stat_ifhcoutmulticastpkts; 2604 uint32_t tx_stat_ifhcoutbroadcastpkts; 2605 uint32_t tx_stat_etherstatspkts64octets; 2606 uint32_t tx_stat_etherstatspkts65octetsto127octets; 2607 uint32_t tx_stat_etherstatspkts128octetsto255octets; 2608 uint32_t tx_stat_etherstatspkts256octetsto511octets; 2609 uint32_t tx_stat_etherstatspkts512octetsto1023octets; 2610 uint32_t tx_stat_etherstatspkts1024octetsto1522octets; 2611 uint32_t tx_stat_etherstatspktsover1522octets; 2612 uint32_t tx_stat_dot3statsinternalmactransmiterrors; 2613 }; 2614 2615 2616 struct bmac1_stats { 2617 uint32_t tx_stat_gtpkt_lo; 2618 uint32_t tx_stat_gtpkt_hi; 2619 uint32_t tx_stat_gtxpf_lo; 2620 uint32_t tx_stat_gtxpf_hi; 2621 uint32_t tx_stat_gtfcs_lo; 2622 uint32_t tx_stat_gtfcs_hi; 2623 uint32_t tx_stat_gtmca_lo; 2624 uint32_t tx_stat_gtmca_hi; 2625 uint32_t tx_stat_gtbca_lo; 2626 uint32_t tx_stat_gtbca_hi; 2627 uint32_t tx_stat_gtfrg_lo; 2628 uint32_t tx_stat_gtfrg_hi; 2629 uint32_t tx_stat_gtovr_lo; 2630 uint32_t tx_stat_gtovr_hi; 2631 uint32_t tx_stat_gt64_lo; 2632 uint32_t tx_stat_gt64_hi; 2633 uint32_t tx_stat_gt127_lo; 2634 uint32_t tx_stat_gt127_hi; 2635 uint32_t tx_stat_gt255_lo; 2636 uint32_t tx_stat_gt255_hi; 2637 uint32_t tx_stat_gt511_lo; 2638 uint32_t tx_stat_gt511_hi; 2639 uint32_t tx_stat_gt1023_lo; 2640 uint32_t tx_stat_gt1023_hi; 2641 uint32_t tx_stat_gt1518_lo; 2642 uint32_t tx_stat_gt1518_hi; 2643 uint32_t tx_stat_gt2047_lo; 2644 uint32_t tx_stat_gt2047_hi; 2645 uint32_t tx_stat_gt4095_lo; 2646 uint32_t tx_stat_gt4095_hi; 2647 uint32_t tx_stat_gt9216_lo; 2648 uint32_t tx_stat_gt9216_hi; 2649 uint32_t tx_stat_gt16383_lo; 2650 uint32_t tx_stat_gt16383_hi; 2651 uint32_t tx_stat_gtmax_lo; 2652 uint32_t tx_stat_gtmax_hi; 2653 uint32_t tx_stat_gtufl_lo; 2654 uint32_t tx_stat_gtufl_hi; 2655 uint32_t tx_stat_gterr_lo; 2656 uint32_t tx_stat_gterr_hi; 2657 uint32_t tx_stat_gtbyt_lo; 2658 uint32_t tx_stat_gtbyt_hi; 2659 2660 uint32_t rx_stat_gr64_lo; 2661 uint32_t rx_stat_gr64_hi; 2662 uint32_t rx_stat_gr127_lo; 2663 uint32_t rx_stat_gr127_hi; 2664 uint32_t rx_stat_gr255_lo; 2665 uint32_t rx_stat_gr255_hi; 2666 uint32_t rx_stat_gr511_lo; 2667 uint32_t rx_stat_gr511_hi; 2668 uint32_t rx_stat_gr1023_lo; 2669 uint32_t rx_stat_gr1023_hi; 2670 uint32_t rx_stat_gr1518_lo; 2671 uint32_t rx_stat_gr1518_hi; 2672 uint32_t rx_stat_gr2047_lo; 2673 uint32_t rx_stat_gr2047_hi; 2674 uint32_t rx_stat_gr4095_lo; 2675 uint32_t rx_stat_gr4095_hi; 2676 uint32_t rx_stat_gr9216_lo; 2677 uint32_t rx_stat_gr9216_hi; 2678 uint32_t rx_stat_gr16383_lo; 2679 uint32_t rx_stat_gr16383_hi; 2680 uint32_t rx_stat_grmax_lo; 2681 uint32_t rx_stat_grmax_hi; 2682 uint32_t rx_stat_grpkt_lo; 2683 uint32_t rx_stat_grpkt_hi; 2684 uint32_t rx_stat_grfcs_lo; 2685 uint32_t rx_stat_grfcs_hi; 2686 uint32_t rx_stat_grmca_lo; 2687 uint32_t rx_stat_grmca_hi; 2688 uint32_t rx_stat_grbca_lo; 2689 uint32_t rx_stat_grbca_hi; 2690 uint32_t rx_stat_grxcf_lo; 2691 uint32_t rx_stat_grxcf_hi; 2692 uint32_t rx_stat_grxpf_lo; 2693 uint32_t rx_stat_grxpf_hi; 2694 uint32_t rx_stat_grxuo_lo; 2695 uint32_t rx_stat_grxuo_hi; 2696 uint32_t rx_stat_grjbr_lo; 2697 uint32_t rx_stat_grjbr_hi; 2698 uint32_t rx_stat_grovr_lo; 2699 uint32_t rx_stat_grovr_hi; 2700 uint32_t rx_stat_grflr_lo; 2701 uint32_t rx_stat_grflr_hi; 2702 uint32_t rx_stat_grmeg_lo; 2703 uint32_t rx_stat_grmeg_hi; 2704 uint32_t rx_stat_grmeb_lo; 2705 uint32_t rx_stat_grmeb_hi; 2706 uint32_t rx_stat_grbyt_lo; 2707 uint32_t rx_stat_grbyt_hi; 2708 uint32_t rx_stat_grund_lo; 2709 uint32_t rx_stat_grund_hi; 2710 uint32_t rx_stat_grfrg_lo; 2711 uint32_t rx_stat_grfrg_hi; 2712 uint32_t rx_stat_grerb_lo; 2713 uint32_t rx_stat_grerb_hi; 2714 uint32_t rx_stat_grfre_lo; 2715 uint32_t rx_stat_grfre_hi; 2716 uint32_t rx_stat_gripj_lo; 2717 uint32_t rx_stat_gripj_hi; 2718 }; 2719 2720 struct bmac2_stats { 2721 uint32_t tx_stat_gtpk_lo; /* gtpok */ 2722 uint32_t tx_stat_gtpk_hi; /* gtpok */ 2723 uint32_t tx_stat_gtxpf_lo; /* gtpf */ 2724 uint32_t tx_stat_gtxpf_hi; /* gtpf */ 2725 uint32_t tx_stat_gtpp_lo; /* NEW BMAC2 */ 2726 uint32_t tx_stat_gtpp_hi; /* NEW BMAC2 */ 2727 uint32_t tx_stat_gtfcs_lo; 2728 uint32_t tx_stat_gtfcs_hi; 2729 uint32_t tx_stat_gtuca_lo; /* NEW BMAC2 */ 2730 uint32_t tx_stat_gtuca_hi; /* NEW BMAC2 */ 2731 uint32_t tx_stat_gtmca_lo; 2732 uint32_t tx_stat_gtmca_hi; 2733 uint32_t tx_stat_gtbca_lo; 2734 uint32_t tx_stat_gtbca_hi; 2735 uint32_t tx_stat_gtovr_lo; 2736 uint32_t tx_stat_gtovr_hi; 2737 uint32_t tx_stat_gtfrg_lo; 2738 uint32_t tx_stat_gtfrg_hi; 2739 uint32_t tx_stat_gtpkt1_lo; /* gtpkt */ 2740 uint32_t tx_stat_gtpkt1_hi; /* gtpkt */ 2741 uint32_t tx_stat_gt64_lo; 2742 uint32_t tx_stat_gt64_hi; 2743 uint32_t tx_stat_gt127_lo; 2744 uint32_t tx_stat_gt127_hi; 2745 uint32_t tx_stat_gt255_lo; 2746 uint32_t tx_stat_gt255_hi; 2747 uint32_t tx_stat_gt511_lo; 2748 uint32_t tx_stat_gt511_hi; 2749 uint32_t tx_stat_gt1023_lo; 2750 uint32_t tx_stat_gt1023_hi; 2751 uint32_t tx_stat_gt1518_lo; 2752 uint32_t tx_stat_gt1518_hi; 2753 uint32_t tx_stat_gt2047_lo; 2754 uint32_t tx_stat_gt2047_hi; 2755 uint32_t tx_stat_gt4095_lo; 2756 uint32_t tx_stat_gt4095_hi; 2757 uint32_t tx_stat_gt9216_lo; 2758 uint32_t tx_stat_gt9216_hi; 2759 uint32_t tx_stat_gt16383_lo; 2760 uint32_t tx_stat_gt16383_hi; 2761 uint32_t tx_stat_gtmax_lo; 2762 uint32_t tx_stat_gtmax_hi; 2763 uint32_t tx_stat_gtufl_lo; 2764 uint32_t tx_stat_gtufl_hi; 2765 uint32_t tx_stat_gterr_lo; 2766 uint32_t tx_stat_gterr_hi; 2767 uint32_t tx_stat_gtbyt_lo; 2768 uint32_t tx_stat_gtbyt_hi; 2769 2770 uint32_t rx_stat_gr64_lo; 2771 uint32_t rx_stat_gr64_hi; 2772 uint32_t rx_stat_gr127_lo; 2773 uint32_t rx_stat_gr127_hi; 2774 uint32_t rx_stat_gr255_lo; 2775 uint32_t rx_stat_gr255_hi; 2776 uint32_t rx_stat_gr511_lo; 2777 uint32_t rx_stat_gr511_hi; 2778 uint32_t rx_stat_gr1023_lo; 2779 uint32_t rx_stat_gr1023_hi; 2780 uint32_t rx_stat_gr1518_lo; 2781 uint32_t rx_stat_gr1518_hi; 2782 uint32_t rx_stat_gr2047_lo; 2783 uint32_t rx_stat_gr2047_hi; 2784 uint32_t rx_stat_gr4095_lo; 2785 uint32_t rx_stat_gr4095_hi; 2786 uint32_t rx_stat_gr9216_lo; 2787 uint32_t rx_stat_gr9216_hi; 2788 uint32_t rx_stat_gr16383_lo; 2789 uint32_t rx_stat_gr16383_hi; 2790 uint32_t rx_stat_grmax_lo; 2791 uint32_t rx_stat_grmax_hi; 2792 uint32_t rx_stat_grpkt_lo; 2793 uint32_t rx_stat_grpkt_hi; 2794 uint32_t rx_stat_grfcs_lo; 2795 uint32_t rx_stat_grfcs_hi; 2796 uint32_t rx_stat_gruca_lo; 2797 uint32_t rx_stat_gruca_hi; 2798 uint32_t rx_stat_grmca_lo; 2799 uint32_t rx_stat_grmca_hi; 2800 uint32_t rx_stat_grbca_lo; 2801 uint32_t rx_stat_grbca_hi; 2802 uint32_t rx_stat_grxpf_lo; /* grpf */ 2803 uint32_t rx_stat_grxpf_hi; /* grpf */ 2804 uint32_t rx_stat_grpp_lo; 2805 uint32_t rx_stat_grpp_hi; 2806 uint32_t rx_stat_grxuo_lo; /* gruo */ 2807 uint32_t rx_stat_grxuo_hi; /* gruo */ 2808 uint32_t rx_stat_grjbr_lo; 2809 uint32_t rx_stat_grjbr_hi; 2810 uint32_t rx_stat_grovr_lo; 2811 uint32_t rx_stat_grovr_hi; 2812 uint32_t rx_stat_grxcf_lo; /* grcf */ 2813 uint32_t rx_stat_grxcf_hi; /* grcf */ 2814 uint32_t rx_stat_grflr_lo; 2815 uint32_t rx_stat_grflr_hi; 2816 uint32_t rx_stat_grpok_lo; 2817 uint32_t rx_stat_grpok_hi; 2818 uint32_t rx_stat_grmeg_lo; 2819 uint32_t rx_stat_grmeg_hi; 2820 uint32_t rx_stat_grmeb_lo; 2821 uint32_t rx_stat_grmeb_hi; 2822 uint32_t rx_stat_grbyt_lo; 2823 uint32_t rx_stat_grbyt_hi; 2824 uint32_t rx_stat_grund_lo; 2825 uint32_t rx_stat_grund_hi; 2826 uint32_t rx_stat_grfrg_lo; 2827 uint32_t rx_stat_grfrg_hi; 2828 uint32_t rx_stat_grerb_lo; /* grerrbyt */ 2829 uint32_t rx_stat_grerb_hi; /* grerrbyt */ 2830 uint32_t rx_stat_grfre_lo; /* grfrerr */ 2831 uint32_t rx_stat_grfre_hi; /* grfrerr */ 2832 uint32_t rx_stat_gripj_lo; 2833 uint32_t rx_stat_gripj_hi; 2834 }; 2835 2836 struct mstat_stats { 2837 struct { 2838 /* OTE MSTAT on E3 has a bug where this register's contents are 2839 * actually tx_gtxpok + tx_gtxpf + (possibly)tx_gtxpp 2840 */ 2841 uint32_t tx_gtxpok_lo; 2842 uint32_t tx_gtxpok_hi; 2843 uint32_t tx_gtxpf_lo; 2844 uint32_t tx_gtxpf_hi; 2845 uint32_t tx_gtxpp_lo; 2846 uint32_t tx_gtxpp_hi; 2847 uint32_t tx_gtfcs_lo; 2848 uint32_t tx_gtfcs_hi; 2849 uint32_t tx_gtuca_lo; 2850 uint32_t tx_gtuca_hi; 2851 uint32_t tx_gtmca_lo; 2852 uint32_t tx_gtmca_hi; 2853 uint32_t tx_gtgca_lo; 2854 uint32_t tx_gtgca_hi; 2855 uint32_t tx_gtpkt_lo; 2856 uint32_t tx_gtpkt_hi; 2857 uint32_t tx_gt64_lo; 2858 uint32_t tx_gt64_hi; 2859 uint32_t tx_gt127_lo; 2860 uint32_t tx_gt127_hi; 2861 uint32_t tx_gt255_lo; 2862 uint32_t tx_gt255_hi; 2863 uint32_t tx_gt511_lo; 2864 uint32_t tx_gt511_hi; 2865 uint32_t tx_gt1023_lo; 2866 uint32_t tx_gt1023_hi; 2867 uint32_t tx_gt1518_lo; 2868 uint32_t tx_gt1518_hi; 2869 uint32_t tx_gt2047_lo; 2870 uint32_t tx_gt2047_hi; 2871 uint32_t tx_gt4095_lo; 2872 uint32_t tx_gt4095_hi; 2873 uint32_t tx_gt9216_lo; 2874 uint32_t tx_gt9216_hi; 2875 uint32_t tx_gt16383_lo; 2876 uint32_t tx_gt16383_hi; 2877 uint32_t tx_gtufl_lo; 2878 uint32_t tx_gtufl_hi; 2879 uint32_t tx_gterr_lo; 2880 uint32_t tx_gterr_hi; 2881 uint32_t tx_gtbyt_lo; 2882 uint32_t tx_gtbyt_hi; 2883 uint32_t tx_collisions_lo; 2884 uint32_t tx_collisions_hi; 2885 uint32_t tx_singlecollision_lo; 2886 uint32_t tx_singlecollision_hi; 2887 uint32_t tx_multiplecollisions_lo; 2888 uint32_t tx_multiplecollisions_hi; 2889 uint32_t tx_deferred_lo; 2890 uint32_t tx_deferred_hi; 2891 uint32_t tx_excessivecollisions_lo; 2892 uint32_t tx_excessivecollisions_hi; 2893 uint32_t tx_latecollisions_lo; 2894 uint32_t tx_latecollisions_hi; 2895 } stats_tx; 2896 2897 struct { 2898 uint32_t rx_gr64_lo; 2899 uint32_t rx_gr64_hi; 2900 uint32_t rx_gr127_lo; 2901 uint32_t rx_gr127_hi; 2902 uint32_t rx_gr255_lo; 2903 uint32_t rx_gr255_hi; 2904 uint32_t rx_gr511_lo; 2905 uint32_t rx_gr511_hi; 2906 uint32_t rx_gr1023_lo; 2907 uint32_t rx_gr1023_hi; 2908 uint32_t rx_gr1518_lo; 2909 uint32_t rx_gr1518_hi; 2910 uint32_t rx_gr2047_lo; 2911 uint32_t rx_gr2047_hi; 2912 uint32_t rx_gr4095_lo; 2913 uint32_t rx_gr4095_hi; 2914 uint32_t rx_gr9216_lo; 2915 uint32_t rx_gr9216_hi; 2916 uint32_t rx_gr16383_lo; 2917 uint32_t rx_gr16383_hi; 2918 uint32_t rx_grpkt_lo; 2919 uint32_t rx_grpkt_hi; 2920 uint32_t rx_grfcs_lo; 2921 uint32_t rx_grfcs_hi; 2922 uint32_t rx_gruca_lo; 2923 uint32_t rx_gruca_hi; 2924 uint32_t rx_grmca_lo; 2925 uint32_t rx_grmca_hi; 2926 uint32_t rx_grbca_lo; 2927 uint32_t rx_grbca_hi; 2928 uint32_t rx_grxpf_lo; 2929 uint32_t rx_grxpf_hi; 2930 uint32_t rx_grxpp_lo; 2931 uint32_t rx_grxpp_hi; 2932 uint32_t rx_grxuo_lo; 2933 uint32_t rx_grxuo_hi; 2934 uint32_t rx_grovr_lo; 2935 uint32_t rx_grovr_hi; 2936 uint32_t rx_grxcf_lo; 2937 uint32_t rx_grxcf_hi; 2938 uint32_t rx_grflr_lo; 2939 uint32_t rx_grflr_hi; 2940 uint32_t rx_grpok_lo; 2941 uint32_t rx_grpok_hi; 2942 uint32_t rx_grbyt_lo; 2943 uint32_t rx_grbyt_hi; 2944 uint32_t rx_grund_lo; 2945 uint32_t rx_grund_hi; 2946 uint32_t rx_grfrg_lo; 2947 uint32_t rx_grfrg_hi; 2948 uint32_t rx_grerb_lo; 2949 uint32_t rx_grerb_hi; 2950 uint32_t rx_grfre_lo; 2951 uint32_t rx_grfre_hi; 2952 2953 uint32_t rx_alignmenterrors_lo; 2954 uint32_t rx_alignmenterrors_hi; 2955 uint32_t rx_falsecarrier_lo; 2956 uint32_t rx_falsecarrier_hi; 2957 uint32_t rx_llfcmsgcnt_lo; 2958 uint32_t rx_llfcmsgcnt_hi; 2959 } stats_rx; 2960 }; 2961 2962 union mac_stats { 2963 struct emac_stats emac_stats; 2964 struct bmac1_stats bmac1_stats; 2965 struct bmac2_stats bmac2_stats; 2966 struct mstat_stats mstat_stats; 2967 }; 2968 2969 2970 struct mac_stx { 2971 /* in_bad_octets */ 2972 uint32_t rx_stat_ifhcinbadoctets_hi; 2973 uint32_t rx_stat_ifhcinbadoctets_lo; 2974 2975 /* out_bad_octets */ 2976 uint32_t tx_stat_ifhcoutbadoctets_hi; 2977 uint32_t tx_stat_ifhcoutbadoctets_lo; 2978 2979 /* crc_receive_errors */ 2980 uint32_t rx_stat_dot3statsfcserrors_hi; 2981 uint32_t rx_stat_dot3statsfcserrors_lo; 2982 /* alignment_errors */ 2983 uint32_t rx_stat_dot3statsalignmenterrors_hi; 2984 uint32_t rx_stat_dot3statsalignmenterrors_lo; 2985 /* carrier_sense_errors */ 2986 uint32_t rx_stat_dot3statscarriersenseerrors_hi; 2987 uint32_t rx_stat_dot3statscarriersenseerrors_lo; 2988 /* false_carrier_detections */ 2989 uint32_t rx_stat_falsecarriererrors_hi; 2990 uint32_t rx_stat_falsecarriererrors_lo; 2991 2992 /* runt_packets_received */ 2993 uint32_t rx_stat_etherstatsundersizepkts_hi; 2994 uint32_t rx_stat_etherstatsundersizepkts_lo; 2995 /* jabber_packets_received */ 2996 uint32_t rx_stat_dot3statsframestoolong_hi; 2997 uint32_t rx_stat_dot3statsframestoolong_lo; 2998 2999 /* error_runt_packets_received */ 3000 uint32_t rx_stat_etherstatsfragments_hi; 3001 uint32_t rx_stat_etherstatsfragments_lo; 3002 /* error_jabber_packets_received */ 3003 uint32_t rx_stat_etherstatsjabbers_hi; 3004 uint32_t rx_stat_etherstatsjabbers_lo; 3005 3006 /* control_frames_received */ 3007 uint32_t rx_stat_maccontrolframesreceived_hi; 3008 uint32_t rx_stat_maccontrolframesreceived_lo; 3009 uint32_t rx_stat_mac_xpf_hi; 3010 uint32_t rx_stat_mac_xpf_lo; 3011 uint32_t rx_stat_mac_xcf_hi; 3012 uint32_t rx_stat_mac_xcf_lo; 3013 3014 /* xoff_state_entered */ 3015 uint32_t rx_stat_xoffstateentered_hi; 3016 uint32_t rx_stat_xoffstateentered_lo; 3017 /* pause_xon_frames_received */ 3018 uint32_t rx_stat_xonpauseframesreceived_hi; 3019 uint32_t rx_stat_xonpauseframesreceived_lo; 3020 /* pause_xoff_frames_received */ 3021 uint32_t rx_stat_xoffpauseframesreceived_hi; 3022 uint32_t rx_stat_xoffpauseframesreceived_lo; 3023 /* pause_xon_frames_transmitted */ 3024 uint32_t tx_stat_outxonsent_hi; 3025 uint32_t tx_stat_outxonsent_lo; 3026 /* pause_xoff_frames_transmitted */ 3027 uint32_t tx_stat_outxoffsent_hi; 3028 uint32_t tx_stat_outxoffsent_lo; 3029 /* flow_control_done */ 3030 uint32_t tx_stat_flowcontroldone_hi; 3031 uint32_t tx_stat_flowcontroldone_lo; 3032 3033 /* ether_stats_collisions */ 3034 uint32_t tx_stat_etherstatscollisions_hi; 3035 uint32_t tx_stat_etherstatscollisions_lo; 3036 /* single_collision_transmit_frames */ 3037 uint32_t tx_stat_dot3statssinglecollisionframes_hi; 3038 uint32_t tx_stat_dot3statssinglecollisionframes_lo; 3039 /* multiple_collision_transmit_frames */ 3040 uint32_t tx_stat_dot3statsmultiplecollisionframes_hi; 3041 uint32_t tx_stat_dot3statsmultiplecollisionframes_lo; 3042 /* deferred_transmissions */ 3043 uint32_t tx_stat_dot3statsdeferredtransmissions_hi; 3044 uint32_t tx_stat_dot3statsdeferredtransmissions_lo; 3045 /* excessive_collision_frames */ 3046 uint32_t tx_stat_dot3statsexcessivecollisions_hi; 3047 uint32_t tx_stat_dot3statsexcessivecollisions_lo; 3048 /* late_collision_frames */ 3049 uint32_t tx_stat_dot3statslatecollisions_hi; 3050 uint32_t tx_stat_dot3statslatecollisions_lo; 3051 3052 /* frames_transmitted_64_bytes */ 3053 uint32_t tx_stat_etherstatspkts64octets_hi; 3054 uint32_t tx_stat_etherstatspkts64octets_lo; 3055 /* frames_transmitted_65_127_bytes */ 3056 uint32_t tx_stat_etherstatspkts65octetsto127octets_hi; 3057 uint32_t tx_stat_etherstatspkts65octetsto127octets_lo; 3058 /* frames_transmitted_128_255_bytes */ 3059 uint32_t tx_stat_etherstatspkts128octetsto255octets_hi; 3060 uint32_t tx_stat_etherstatspkts128octetsto255octets_lo; 3061 /* frames_transmitted_256_511_bytes */ 3062 uint32_t tx_stat_etherstatspkts256octetsto511octets_hi; 3063 uint32_t tx_stat_etherstatspkts256octetsto511octets_lo; 3064 /* frames_transmitted_512_1023_bytes */ 3065 uint32_t tx_stat_etherstatspkts512octetsto1023octets_hi; 3066 uint32_t tx_stat_etherstatspkts512octetsto1023octets_lo; 3067 /* frames_transmitted_1024_1522_bytes */ 3068 uint32_t tx_stat_etherstatspkts1024octetsto1522octets_hi; 3069 uint32_t tx_stat_etherstatspkts1024octetsto1522octets_lo; 3070 /* frames_transmitted_1523_9022_bytes */ 3071 uint32_t tx_stat_etherstatspktsover1522octets_hi; 3072 uint32_t tx_stat_etherstatspktsover1522octets_lo; 3073 uint32_t tx_stat_mac_2047_hi; 3074 uint32_t tx_stat_mac_2047_lo; 3075 uint32_t tx_stat_mac_4095_hi; 3076 uint32_t tx_stat_mac_4095_lo; 3077 uint32_t tx_stat_mac_9216_hi; 3078 uint32_t tx_stat_mac_9216_lo; 3079 uint32_t tx_stat_mac_16383_hi; 3080 uint32_t tx_stat_mac_16383_lo; 3081 3082 /* internal_mac_transmit_errors */ 3083 uint32_t tx_stat_dot3statsinternalmactransmiterrors_hi; 3084 uint32_t tx_stat_dot3statsinternalmactransmiterrors_lo; 3085 3086 /* if_out_discards */ 3087 uint32_t tx_stat_mac_ufl_hi; 3088 uint32_t tx_stat_mac_ufl_lo; 3089 }; 3090 3091 3092 #define MAC_STX_IDX_MAX 2 3093 3094 struct host_port_stats { 3095 uint32_t host_port_stats_counter; 3096 3097 struct mac_stx mac_stx[MAC_STX_IDX_MAX]; 3098 3099 uint32_t brb_drop_hi; 3100 uint32_t brb_drop_lo; 3101 3102 uint32_t not_used; /* obsolete as of MFW 7.2.1 */ 3103 3104 uint32_t pfc_frames_tx_hi; 3105 uint32_t pfc_frames_tx_lo; 3106 uint32_t pfc_frames_rx_hi; 3107 uint32_t pfc_frames_rx_lo; 3108 3109 uint32_t eee_lpi_count_hi; 3110 uint32_t eee_lpi_count_lo; 3111 }; 3112 3113 3114 struct host_func_stats { 3115 uint32_t host_func_stats_start; 3116 3117 uint32_t total_bytes_received_hi; 3118 uint32_t total_bytes_received_lo; 3119 3120 uint32_t total_bytes_transmitted_hi; 3121 uint32_t total_bytes_transmitted_lo; 3122 3123 uint32_t total_unicast_packets_received_hi; 3124 uint32_t total_unicast_packets_received_lo; 3125 3126 uint32_t total_multicast_packets_received_hi; 3127 uint32_t total_multicast_packets_received_lo; 3128 3129 uint32_t total_broadcast_packets_received_hi; 3130 uint32_t total_broadcast_packets_received_lo; 3131 3132 uint32_t total_unicast_packets_transmitted_hi; 3133 uint32_t total_unicast_packets_transmitted_lo; 3134 3135 uint32_t total_multicast_packets_transmitted_hi; 3136 uint32_t total_multicast_packets_transmitted_lo; 3137 3138 uint32_t total_broadcast_packets_transmitted_hi; 3139 uint32_t total_broadcast_packets_transmitted_lo; 3140 3141 uint32_t valid_bytes_received_hi; 3142 uint32_t valid_bytes_received_lo; 3143 3144 uint32_t host_func_stats_end; 3145 }; 3146 3147 /* VIC definitions */ 3148 #define VICSTATST_UIF_INDEX 2 3149 3150 /* 3151 * stats collected for afex. 3152 * NOTE: structure is exactly as expected to be received by the switch. 3153 * order must remain exactly as is unless protocol changes ! 3154 */ 3155 struct afex_stats { 3156 uint32_t tx_unicast_frames_hi; 3157 uint32_t tx_unicast_frames_lo; 3158 uint32_t tx_unicast_bytes_hi; 3159 uint32_t tx_unicast_bytes_lo; 3160 uint32_t tx_multicast_frames_hi; 3161 uint32_t tx_multicast_frames_lo; 3162 uint32_t tx_multicast_bytes_hi; 3163 uint32_t tx_multicast_bytes_lo; 3164 uint32_t tx_broadcast_frames_hi; 3165 uint32_t tx_broadcast_frames_lo; 3166 uint32_t tx_broadcast_bytes_hi; 3167 uint32_t tx_broadcast_bytes_lo; 3168 uint32_t tx_frames_discarded_hi; 3169 uint32_t tx_frames_discarded_lo; 3170 uint32_t tx_frames_dropped_hi; 3171 uint32_t tx_frames_dropped_lo; 3172 3173 uint32_t rx_unicast_frames_hi; 3174 uint32_t rx_unicast_frames_lo; 3175 uint32_t rx_unicast_bytes_hi; 3176 uint32_t rx_unicast_bytes_lo; 3177 uint32_t rx_multicast_frames_hi; 3178 uint32_t rx_multicast_frames_lo; 3179 uint32_t rx_multicast_bytes_hi; 3180 uint32_t rx_multicast_bytes_lo; 3181 uint32_t rx_broadcast_frames_hi; 3182 uint32_t rx_broadcast_frames_lo; 3183 uint32_t rx_broadcast_bytes_hi; 3184 uint32_t rx_broadcast_bytes_lo; 3185 uint32_t rx_frames_discarded_hi; 3186 uint32_t rx_frames_discarded_lo; 3187 uint32_t rx_frames_dropped_hi; 3188 uint32_t rx_frames_dropped_lo; 3189 }; 3190 3191 /* To maintain backward compatibility between FW and drivers, new elements */ 3192 /* should be added to the end of the structure. */ 3193 3194 /* Per Port Statistics */ 3195 struct port_info { 3196 uint32_t size; /* size of this structure (i.e. sizeof(port_info)) */ 3197 uint32_t enabled; /* 0 =Disabled, 1= Enabled */ 3198 uint32_t link_speed; /* multiplier of 100Mb */ 3199 uint32_t wol_support; /* WoL Support (i.e. Non-Zero if WOL supported ) */ 3200 uint32_t flow_control; /* 802.3X Flow Ctrl. 0=off 1=RX 2=TX 3=RX&TX.*/ 3201 uint32_t flex10; /* Flex10 mode enabled. non zero = yes */ 3202 uint32_t rx_drops; /* RX Discards. Counters roll over, never reset */ 3203 uint32_t rx_errors; /* RX Errors. Physical Port Stats L95, All PFs and NC-SI. 3204 This is flagged by Consumer as an error. */ 3205 uint32_t rx_uncast_lo; /* RX Unicast Packets. Free running counters: */ 3206 uint32_t rx_uncast_hi; /* RX Unicast Packets. Free running counters: */ 3207 uint32_t rx_mcast_lo; /* RX Multicast Packets */ 3208 uint32_t rx_mcast_hi; /* RX Multicast Packets */ 3209 uint32_t rx_bcast_lo; /* RX Broadcast Packets */ 3210 uint32_t rx_bcast_hi; /* RX Broadcast Packets */ 3211 uint32_t tx_uncast_lo; /* TX Unicast Packets */ 3212 uint32_t tx_uncast_hi; /* TX Unicast Packets */ 3213 uint32_t tx_mcast_lo; /* TX Multicast Packets */ 3214 uint32_t tx_mcast_hi; /* TX Multicast Packets */ 3215 uint32_t tx_bcast_lo; /* TX Broadcast Packets */ 3216 uint32_t tx_bcast_hi; /* TX Broadcast Packets */ 3217 uint32_t tx_errors; /* TX Errors */ 3218 uint32_t tx_discards; /* TX Discards */ 3219 uint32_t rx_frames_lo; /* RX Frames received */ 3220 uint32_t rx_frames_hi; /* RX Frames received */ 3221 uint32_t rx_bytes_lo; /* RX Bytes received */ 3222 uint32_t rx_bytes_hi; /* RX Bytes received */ 3223 uint32_t tx_frames_lo; /* TX Frames sent */ 3224 uint32_t tx_frames_hi; /* TX Frames sent */ 3225 uint32_t tx_bytes_lo; /* TX Bytes sent */ 3226 uint32_t tx_bytes_hi; /* TX Bytes sent */ 3227 uint32_t link_status; /* Port P Link Status. 1:0 bit for port enabled. 3228 1:1 bit for link good, 3229 2:1 Set if link changed between last poll. */ 3230 uint32_t tx_pfc_frames_lo; /* PFC Frames sent. */ 3231 uint32_t tx_pfc_frames_hi; /* PFC Frames sent. */ 3232 uint32_t rx_pfc_frames_lo; /* PFC Frames Received. */ 3233 uint32_t rx_pfc_frames_hi; /* PFC Frames Received. */ 3234 }; 3235 3236 3237 #define BCM_5710_FW_MAJOR_VERSION 7 3238 #define BCM_5710_FW_MINOR_VERSION 8 3239 #define BCM_5710_FW_REVISION_VERSION 51 3240 #define BCM_5710_FW_ENGINEERING_VERSION 0 3241 #define BCM_5710_FW_COMPILE_FLAGS 1 3242 3243 3244 /* 3245 * attention bits $$KEEP_ENDIANNESS$$ 3246 */ 3247 struct atten_sp_status_block 3248 { 3249 uint32_t attn_bits /* 16 bit of attention signal lines */; 3250 uint32_t attn_bits_ack /* 16 bit of attention signal ack */; 3251 uint8_t status_block_id /* status block id */; 3252 uint8_t reserved0 /* resreved for padding */; 3253 uint16_t attn_bits_index /* attention bits running index */; 3254 uint32_t reserved1 /* resreved for padding */; 3255 }; 3256 3257 3258 /* 3259 * The eth aggregative context of Cstorm 3260 */ 3261 struct cstorm_eth_ag_context 3262 { 3263 uint32_t __reserved0[10]; 3264 }; 3265 3266 3267 /* 3268 * dmae command structure 3269 */ 3270 struct dmae_command 3271 { 3272 uint32_t opcode; 3273 #define DMAE_COMMAND_SRC (0x1<<0) /* BitField opcode Whether the source is the PCIe or the GRC. 0- The source is the PCIe 1- The source is the GRC. */ 3274 #define DMAE_COMMAND_SRC_SHIFT 0 3275 #define DMAE_COMMAND_DST (0x3<<1) /* BitField opcode The destination of the DMA can be: 0-None 1-PCIe 2-GRC 3-None */ 3276 #define DMAE_COMMAND_DST_SHIFT 1 3277 #define DMAE_COMMAND_C_DST (0x1<<3) /* BitField opcode The destination of the completion: 0-PCIe 1-GRC */ 3278 #define DMAE_COMMAND_C_DST_SHIFT 3 3279 #define DMAE_COMMAND_C_TYPE_ENABLE (0x1<<4) /* BitField opcode Whether to write a completion word to the completion destination: 0-Do not write a completion word 1-Write the completion word */ 3280 #define DMAE_COMMAND_C_TYPE_ENABLE_SHIFT 4 3281 #define DMAE_COMMAND_C_TYPE_CRC_ENABLE (0x1<<5) /* BitField opcode Whether to write a CRC word to the completion destination 0-Do not write a CRC word 1-Write a CRC word */ 3282 #define DMAE_COMMAND_C_TYPE_CRC_ENABLE_SHIFT 5 3283 #define DMAE_COMMAND_C_TYPE_CRC_OFFSET (0x7<<6) /* BitField opcode The CRC word should be taken from the DMAE GRC space from address 9+X, where X is the value in these bits. */ 3284 #define DMAE_COMMAND_C_TYPE_CRC_OFFSET_SHIFT 6 3285 #define DMAE_COMMAND_ENDIANITY (0x3<<9) /* BitField opcode swapping mode. */ 3286 #define DMAE_COMMAND_ENDIANITY_SHIFT 9 3287 #define DMAE_COMMAND_PORT (0x1<<11) /* BitField opcode Which network port ID to present to the PCI request interface */ 3288 #define DMAE_COMMAND_PORT_SHIFT 11 3289 #define DMAE_COMMAND_CRC_RESET (0x1<<12) /* BitField opcode reset crc result */ 3290 #define DMAE_COMMAND_CRC_RESET_SHIFT 12 3291 #define DMAE_COMMAND_SRC_RESET (0x1<<13) /* BitField opcode reset source address in next go */ 3292 #define DMAE_COMMAND_SRC_RESET_SHIFT 13 3293 #define DMAE_COMMAND_DST_RESET (0x1<<14) /* BitField opcode reset dest address in next go */ 3294 #define DMAE_COMMAND_DST_RESET_SHIFT 14 3295 #define DMAE_COMMAND_E1HVN (0x3<<15) /* BitField opcode vnic number E2 and onwards source vnic */ 3296 #define DMAE_COMMAND_E1HVN_SHIFT 15 3297 #define DMAE_COMMAND_DST_VN (0x3<<17) /* BitField opcode E2 and onwards dest vnic */ 3298 #define DMAE_COMMAND_DST_VN_SHIFT 17 3299 #define DMAE_COMMAND_C_FUNC (0x1<<19) /* BitField opcode E2 and onwards which function gets the completion src_vn(e1hvn)-0 dst_vn-1 */ 3300 #define DMAE_COMMAND_C_FUNC_SHIFT 19 3301 #define DMAE_COMMAND_ERR_POLICY (0x3<<20) /* BitField opcode E2 and onwards what to do when theres a completion and a PCI error regular-0 error indication-1 no completion-2 */ 3302 #define DMAE_COMMAND_ERR_POLICY_SHIFT 20 3303 #define DMAE_COMMAND_RESERVED0 (0x3FF<<22) /* BitField opcode */ 3304 #define DMAE_COMMAND_RESERVED0_SHIFT 22 3305 uint32_t src_addr_lo /* source address low/grc address */; 3306 uint32_t src_addr_hi /* source address hi */; 3307 uint32_t dst_addr_lo /* dest address low/grc address */; 3308 uint32_t dst_addr_hi /* dest address hi */; 3309 #if defined(__BIG_ENDIAN) 3310 uint16_t opcode_iov; 3311 #define DMAE_COMMAND_SRC_VFID (0x3F<<0) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility source VF id */ 3312 #define DMAE_COMMAND_SRC_VFID_SHIFT 0 3313 #define DMAE_COMMAND_SRC_VFPF (0x1<<6) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility selects the source function PF-0, VF-1 */ 3314 #define DMAE_COMMAND_SRC_VFPF_SHIFT 6 3315 #define DMAE_COMMAND_RESERVED1 (0x1<<7) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility */ 3316 #define DMAE_COMMAND_RESERVED1_SHIFT 7 3317 #define DMAE_COMMAND_DST_VFID (0x3F<<8) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility destination VF id */ 3318 #define DMAE_COMMAND_DST_VFID_SHIFT 8 3319 #define DMAE_COMMAND_DST_VFPF (0x1<<14) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility selects the destination function PF-0, VF-1 */ 3320 #define DMAE_COMMAND_DST_VFPF_SHIFT 14 3321 #define DMAE_COMMAND_RESERVED2 (0x1<<15) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility */ 3322 #define DMAE_COMMAND_RESERVED2_SHIFT 15 3323 uint16_t len /* copy length */; 3324 #elif defined(__LITTLE_ENDIAN) 3325 uint16_t len /* copy length */; 3326 uint16_t opcode_iov; 3327 #define DMAE_COMMAND_SRC_VFID (0x3F<<0) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility source VF id */ 3328 #define DMAE_COMMAND_SRC_VFID_SHIFT 0 3329 #define DMAE_COMMAND_SRC_VFPF (0x1<<6) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility selects the source function PF-0, VF-1 */ 3330 #define DMAE_COMMAND_SRC_VFPF_SHIFT 6 3331 #define DMAE_COMMAND_RESERVED1 (0x1<<7) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility */ 3332 #define DMAE_COMMAND_RESERVED1_SHIFT 7 3333 #define DMAE_COMMAND_DST_VFID (0x3F<<8) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility destination VF id */ 3334 #define DMAE_COMMAND_DST_VFID_SHIFT 8 3335 #define DMAE_COMMAND_DST_VFPF (0x1<<14) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility selects the destination function PF-0, VF-1 */ 3336 #define DMAE_COMMAND_DST_VFPF_SHIFT 14 3337 #define DMAE_COMMAND_RESERVED2 (0x1<<15) /* BitField opcode_iovE2 and onward, set to 0 for backward compatibility */ 3338 #define DMAE_COMMAND_RESERVED2_SHIFT 15 3339 #endif 3340 uint32_t comp_addr_lo /* completion address low/grc address */; 3341 uint32_t comp_addr_hi /* completion address hi */; 3342 uint32_t comp_val /* value to write to completion address */; 3343 uint32_t crc32 /* crc32 result */; 3344 uint32_t crc32_c /* crc32_c result */; 3345 #if defined(__BIG_ENDIAN) 3346 uint16_t crc16_c /* crc16_c result */; 3347 uint16_t crc16 /* crc16 result */; 3348 #elif defined(__LITTLE_ENDIAN) 3349 uint16_t crc16 /* crc16 result */; 3350 uint16_t crc16_c /* crc16_c result */; 3351 #endif 3352 #if defined(__BIG_ENDIAN) 3353 uint16_t reserved3; 3354 uint16_t crc_t10 /* crc_t10 result */; 3355 #elif defined(__LITTLE_ENDIAN) 3356 uint16_t crc_t10 /* crc_t10 result */; 3357 uint16_t reserved3; 3358 #endif 3359 #if defined(__BIG_ENDIAN) 3360 uint16_t xsum8 /* checksum8 result */; 3361 uint16_t xsum16 /* checksum16 result */; 3362 #elif defined(__LITTLE_ENDIAN) 3363 uint16_t xsum16 /* checksum16 result */; 3364 uint16_t xsum8 /* checksum8 result */; 3365 #endif 3366 }; 3367 3368 3369 /* 3370 * common data for all protocols 3371 */ 3372 struct doorbell_hdr 3373 { 3374 uint8_t header; 3375 #define DOORBELL_HDR_RX (0x1<<0) /* BitField header 1 for rx doorbell, 0 for tx doorbell */ 3376 #define DOORBELL_HDR_RX_SHIFT 0 3377 #define DOORBELL_HDR_DB_TYPE (0x1<<1) /* BitField header 0 for normal doorbell, 1 for advertise wnd doorbell */ 3378 #define DOORBELL_HDR_DB_TYPE_SHIFT 1 3379 #define DOORBELL_HDR_DPM_SIZE (0x3<<2) /* BitField header rdma tx only: DPM transaction size specifier (64/128/256/512 bytes) */ 3380 #define DOORBELL_HDR_DPM_SIZE_SHIFT 2 3381 #define DOORBELL_HDR_CONN_TYPE (0xF<<4) /* BitField header connection type */ 3382 #define DOORBELL_HDR_CONN_TYPE_SHIFT 4 3383 }; 3384 3385 /* 3386 * Ethernet doorbell 3387 */ 3388 struct eth_tx_doorbell 3389 { 3390 #if defined(__BIG_ENDIAN) 3391 uint16_t npackets /* number of data bytes that were added in the doorbell */; 3392 uint8_t params; 3393 #define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0) /* BitField params number of buffer descriptors that were added in the doorbell */ 3394 #define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0 3395 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6) /* BitField params tx fin command flag */ 3396 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6 3397 #define ETH_TX_DOORBELL_SPARE (0x1<<7) /* BitField params doorbell queue spare flag */ 3398 #define ETH_TX_DOORBELL_SPARE_SHIFT 7 3399 struct doorbell_hdr hdr; 3400 #elif defined(__LITTLE_ENDIAN) 3401 struct doorbell_hdr hdr; 3402 uint8_t params; 3403 #define ETH_TX_DOORBELL_NUM_BDS (0x3F<<0) /* BitField params number of buffer descriptors that were added in the doorbell */ 3404 #define ETH_TX_DOORBELL_NUM_BDS_SHIFT 0 3405 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG (0x1<<6) /* BitField params tx fin command flag */ 3406 #define ETH_TX_DOORBELL_RESERVED_TX_FIN_FLAG_SHIFT 6 3407 #define ETH_TX_DOORBELL_SPARE (0x1<<7) /* BitField params doorbell queue spare flag */ 3408 #define ETH_TX_DOORBELL_SPARE_SHIFT 7 3409 uint16_t npackets /* number of data bytes that were added in the doorbell */; 3410 #endif 3411 }; 3412 3413 3414 /* 3415 * 3 lines. status block $$KEEP_ENDIANNESS$$ 3416 */ 3417 struct hc_status_block_e1x 3418 { 3419 uint16_t index_values[HC_SB_MAX_INDICES_E1X] /* indices reported by cstorm */; 3420 uint16_t running_index[HC_SB_MAX_SM] /* Status Block running indices */; 3421 uint32_t rsrv[11]; 3422 }; 3423 3424 /* 3425 * host status block 3426 */ 3427 struct host_hc_status_block_e1x 3428 { 3429 struct hc_status_block_e1x sb /* fast path indices */; 3430 }; 3431 3432 3433 /* 3434 * 3 lines. status block $$KEEP_ENDIANNESS$$ 3435 */ 3436 struct hc_status_block_e2 3437 { 3438 uint16_t index_values[HC_SB_MAX_INDICES_E2] /* indices reported by cstorm */; 3439 uint16_t running_index[HC_SB_MAX_SM] /* Status Block running indices */; 3440 uint32_t reserved[11]; 3441 }; 3442 3443 /* 3444 * host status block 3445 */ 3446 struct host_hc_status_block_e2 3447 { 3448 struct hc_status_block_e2 sb /* fast path indices */; 3449 }; 3450 3451 3452 /* 3453 * 5 lines. slow-path status block $$KEEP_ENDIANNESS$$ 3454 */ 3455 struct hc_sp_status_block 3456 { 3457 uint16_t index_values[HC_SP_SB_MAX_INDICES] /* indices reported by cstorm */; 3458 uint16_t running_index /* Status Block running index */; 3459 uint16_t rsrv; 3460 uint32_t rsrv1; 3461 }; 3462 3463 /* 3464 * host status block 3465 */ 3466 struct host_sp_status_block 3467 { 3468 struct atten_sp_status_block atten_status_block /* attention bits section */; 3469 struct hc_sp_status_block sp_sb /* slow path indices */; 3470 }; 3471 3472 3473 /* 3474 * IGU driver acknowledgment register 3475 */ 3476 struct igu_ack_register 3477 { 3478 #if defined(__BIG_ENDIAN) 3479 uint16_t sb_id_and_flags; 3480 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0) /* BitField sb_id_and_flags 0-15: non default status blocks, 16: default status block */ 3481 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0 3482 #define IGU_ACK_REGISTER_STORM_ID (0x7<<5) /* BitField sb_id_and_flags 0-3:storm id, 4: attn status block (valid in default sb only) */ 3483 #define IGU_ACK_REGISTER_STORM_ID_SHIFT 5 3484 #define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8) /* BitField sb_id_and_flags if set, acknowledges status block index */ 3485 #define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8 3486 #define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9) /* BitField sb_id_and_flags interrupt enable/disable/nop: use IGU_INT_xxx constants */ 3487 #define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9 3488 #define IGU_ACK_REGISTER_RESERVED (0x1F<<11) /* BitField sb_id_and_flags */ 3489 #define IGU_ACK_REGISTER_RESERVED_SHIFT 11 3490 uint16_t status_block_index /* status block index acknowledgement */; 3491 #elif defined(__LITTLE_ENDIAN) 3492 uint16_t status_block_index /* status block index acknowledgement */; 3493 uint16_t sb_id_and_flags; 3494 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID (0x1F<<0) /* BitField sb_id_and_flags 0-15: non default status blocks, 16: default status block */ 3495 #define IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT 0 3496 #define IGU_ACK_REGISTER_STORM_ID (0x7<<5) /* BitField sb_id_and_flags 0-3:storm id, 4: attn status block (valid in default sb only) */ 3497 #define IGU_ACK_REGISTER_STORM_ID_SHIFT 5 3498 #define IGU_ACK_REGISTER_UPDATE_INDEX (0x1<<8) /* BitField sb_id_and_flags if set, acknowledges status block index */ 3499 #define IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT 8 3500 #define IGU_ACK_REGISTER_INTERRUPT_MODE (0x3<<9) /* BitField sb_id_and_flags interrupt enable/disable/nop: use IGU_INT_xxx constants */ 3501 #define IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT 9 3502 #define IGU_ACK_REGISTER_RESERVED (0x1F<<11) /* BitField sb_id_and_flags */ 3503 #define IGU_ACK_REGISTER_RESERVED_SHIFT 11 3504 #endif 3505 }; 3506 3507 3508 /* 3509 * IGU driver acknowledgement register 3510 */ 3511 struct igu_backward_compatible 3512 { 3513 uint32_t sb_id_and_flags; 3514 #define IGU_BACKWARD_COMPATIBLE_SB_INDEX (0xFFFF<<0) /* BitField sb_id_and_flags */ 3515 #define IGU_BACKWARD_COMPATIBLE_SB_INDEX_SHIFT 0 3516 #define IGU_BACKWARD_COMPATIBLE_SB_SELECT (0x1F<<16) /* BitField sb_id_and_flags */ 3517 #define IGU_BACKWARD_COMPATIBLE_SB_SELECT_SHIFT 16 3518 #define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS (0x7<<21) /* BitField sb_id_and_flags 0-3:storm id, 4: attn status block (valid in default sb only) */ 3519 #define IGU_BACKWARD_COMPATIBLE_SEGMENT_ACCESS_SHIFT 21 3520 #define IGU_BACKWARD_COMPATIBLE_BUPDATE (0x1<<24) /* BitField sb_id_and_flags if set, acknowledges status block index */ 3521 #define IGU_BACKWARD_COMPATIBLE_BUPDATE_SHIFT 24 3522 #define IGU_BACKWARD_COMPATIBLE_ENABLE_INT (0x3<<25) /* BitField sb_id_and_flags interrupt enable/disable/nop: use IGU_INT_xxx constants */ 3523 #define IGU_BACKWARD_COMPATIBLE_ENABLE_INT_SHIFT 25 3524 #define IGU_BACKWARD_COMPATIBLE_RESERVED_0 (0x1F<<27) /* BitField sb_id_and_flags */ 3525 #define IGU_BACKWARD_COMPATIBLE_RESERVED_0_SHIFT 27 3526 uint32_t reserved_2; 3527 }; 3528 3529 3530 /* 3531 * IGU driver acknowledgement register 3532 */ 3533 struct igu_regular 3534 { 3535 uint32_t sb_id_and_flags; 3536 #define IGU_REGULAR_SB_INDEX (0xFFFFF<<0) /* BitField sb_id_and_flags */ 3537 #define IGU_REGULAR_SB_INDEX_SHIFT 0 3538 #define IGU_REGULAR_RESERVED0 (0x1<<20) /* BitField sb_id_and_flags */ 3539 #define IGU_REGULAR_RESERVED0_SHIFT 20 3540 #define IGU_REGULAR_SEGMENT_ACCESS (0x7<<21) /* BitField sb_id_and_flags 21-23 (use enum igu_seg_access) */ 3541 #define IGU_REGULAR_SEGMENT_ACCESS_SHIFT 21 3542 #define IGU_REGULAR_BUPDATE (0x1<<24) /* BitField sb_id_and_flags */ 3543 #define IGU_REGULAR_BUPDATE_SHIFT 24 3544 #define IGU_REGULAR_ENABLE_INT (0x3<<25) /* BitField sb_id_and_flags interrupt enable/disable/nop (use enum igu_int_cmd) */ 3545 #define IGU_REGULAR_ENABLE_INT_SHIFT 25 3546 #define IGU_REGULAR_RESERVED_1 (0x1<<27) /* BitField sb_id_and_flags */ 3547 #define IGU_REGULAR_RESERVED_1_SHIFT 27 3548 #define IGU_REGULAR_CLEANUP_TYPE (0x3<<28) /* BitField sb_id_and_flags */ 3549 #define IGU_REGULAR_CLEANUP_TYPE_SHIFT 28 3550 #define IGU_REGULAR_CLEANUP_SET (0x1<<30) /* BitField sb_id_and_flags */ 3551 #define IGU_REGULAR_CLEANUP_SET_SHIFT 30 3552 #define IGU_REGULAR_BCLEANUP (0x1<<31) /* BitField sb_id_and_flags */ 3553 #define IGU_REGULAR_BCLEANUP_SHIFT 31 3554 uint32_t reserved_2; 3555 }; 3556 3557 /* 3558 * IGU driver acknowledgement register 3559 */ 3560 union igu_consprod_reg 3561 { 3562 struct igu_regular regular; 3563 struct igu_backward_compatible backward_compatible; 3564 }; 3565 3566 3567 /* 3568 * Igu control commands 3569 */ 3570 enum igu_ctrl_cmd 3571 { 3572 IGU_CTRL_CMD_TYPE_RD, 3573 IGU_CTRL_CMD_TYPE_WR, 3574 MAX_IGU_CTRL_CMD}; 3575 3576 3577 /* 3578 * Control register for the IGU command register 3579 */ 3580 struct igu_ctrl_reg 3581 { 3582 uint32_t ctrl_data; 3583 #define IGU_CTRL_REG_ADDRESS (0xFFF<<0) /* BitField ctrl_data */ 3584 #define IGU_CTRL_REG_ADDRESS_SHIFT 0 3585 #define IGU_CTRL_REG_FID (0x7F<<12) /* BitField ctrl_data */ 3586 #define IGU_CTRL_REG_FID_SHIFT 12 3587 #define IGU_CTRL_REG_RESERVED (0x1<<19) /* BitField ctrl_data */ 3588 #define IGU_CTRL_REG_RESERVED_SHIFT 19 3589 #define IGU_CTRL_REG_TYPE (0x1<<20) /* BitField ctrl_data (use enum igu_ctrl_cmd) */ 3590 #define IGU_CTRL_REG_TYPE_SHIFT 20 3591 #define IGU_CTRL_REG_UNUSED (0x7FF<<21) /* BitField ctrl_data */ 3592 #define IGU_CTRL_REG_UNUSED_SHIFT 21 3593 }; 3594 3595 3596 /* 3597 * Igu interrupt command 3598 */ 3599 enum igu_int_cmd 3600 { 3601 IGU_INT_ENABLE, 3602 IGU_INT_DISABLE, 3603 IGU_INT_NOP, 3604 IGU_INT_NOP2, 3605 MAX_IGU_INT_CMD}; 3606 3607 3608 /* 3609 * Igu segments 3610 */ 3611 enum igu_seg_access 3612 { 3613 IGU_SEG_ACCESS_NORM, 3614 IGU_SEG_ACCESS_DEF, 3615 IGU_SEG_ACCESS_ATTN, 3616 MAX_IGU_SEG_ACCESS}; 3617 3618 3619 /* 3620 * Parser parsing flags field 3621 */ 3622 struct parsing_flags 3623 { 3624 uint16_t flags; 3625 #define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE (0x1<<0) /* BitField flagscontext flags 0=non-unicast, 1=unicast (use enum prs_flags_eth_addr_type) */ 3626 #define PARSING_FLAGS_ETHERNET_ADDRESS_TYPE_SHIFT 0 3627 #define PARSING_FLAGS_VLAN (0x1<<1) /* BitField flagscontext flags 0 or 1 */ 3628 #define PARSING_FLAGS_VLAN_SHIFT 1 3629 #define PARSING_FLAGS_EXTRA_VLAN (0x1<<2) /* BitField flagscontext flags 0 or 1 */ 3630 #define PARSING_FLAGS_EXTRA_VLAN_SHIFT 2 3631 #define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL (0x3<<3) /* BitField flagscontext flags 0=un-known, 1=Ipv4, 2=Ipv6,3=LLC SNAP un-known. LLC SNAP here refers only to LLC/SNAP packets that do not have Ipv4 or Ipv6 above them. Ipv4 and Ipv6 indications are even if they are over LLC/SNAP and not directly over Ethernet (use enum prs_flags_over_eth) */ 3632 #define PARSING_FLAGS_OVER_ETHERNET_PROTOCOL_SHIFT 3 3633 #define PARSING_FLAGS_IP_OPTIONS (0x1<<5) /* BitField flagscontext flags 0=no IP options / extension headers. 1=IP options / extension header exist */ 3634 #define PARSING_FLAGS_IP_OPTIONS_SHIFT 5 3635 #define PARSING_FLAGS_FRAGMENTATION_STATUS (0x1<<6) /* BitField flagscontext flags 0=non-fragmented, 1=fragmented */ 3636 #define PARSING_FLAGS_FRAGMENTATION_STATUS_SHIFT 6 3637 #define PARSING_FLAGS_OVER_IP_PROTOCOL (0x3<<7) /* BitField flagscontext flags 0=un-known, 1=TCP, 2=UDP (use enum prs_flags_over_ip) */ 3638 #define PARSING_FLAGS_OVER_IP_PROTOCOL_SHIFT 7 3639 #define PARSING_FLAGS_PURE_ACK_INDICATION (0x1<<9) /* BitField flagscontext flags 0=packet with data, 1=pure-ACK (use enum prs_flags_ack_type) */ 3640 #define PARSING_FLAGS_PURE_ACK_INDICATION_SHIFT 9 3641 #define PARSING_FLAGS_TCP_OPTIONS_EXIST (0x1<<10) /* BitField flagscontext flags 0=no TCP options. 1=TCP options */ 3642 #define PARSING_FLAGS_TCP_OPTIONS_EXIST_SHIFT 10 3643 #define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG (0x1<<11) /* BitField flagscontext flags According to the TCP header options parsing */ 3644 #define PARSING_FLAGS_TIME_STAMP_EXIST_FLAG_SHIFT 11 3645 #define PARSING_FLAGS_CONNECTION_MATCH (0x1<<12) /* BitField flagscontext flags connection match in searcher indication */ 3646 #define PARSING_FLAGS_CONNECTION_MATCH_SHIFT 12 3647 #define PARSING_FLAGS_LLC_SNAP (0x1<<13) /* BitField flagscontext flags LLC SNAP indication */ 3648 #define PARSING_FLAGS_LLC_SNAP_SHIFT 13 3649 #define PARSING_FLAGS_RESERVED0 (0x3<<14) /* BitField flagscontext flags */ 3650 #define PARSING_FLAGS_RESERVED0_SHIFT 14 3651 }; 3652 3653 3654 /* 3655 * Parsing flags for TCP ACK type 3656 */ 3657 enum prs_flags_ack_type 3658 { 3659 PRS_FLAG_PUREACK_PIGGY, 3660 PRS_FLAG_PUREACK_PURE, 3661 MAX_PRS_FLAGS_ACK_TYPE}; 3662 3663 3664 /* 3665 * Parsing flags for Ethernet address type 3666 */ 3667 enum prs_flags_eth_addr_type 3668 { 3669 PRS_FLAG_ETHTYPE_NON_UNICAST, 3670 PRS_FLAG_ETHTYPE_UNICAST, 3671 MAX_PRS_FLAGS_ETH_ADDR_TYPE}; 3672 3673 3674 /* 3675 * Parsing flags for over-ethernet protocol 3676 */ 3677 enum prs_flags_over_eth 3678 { 3679 PRS_FLAG_OVERETH_UNKNOWN, 3680 PRS_FLAG_OVERETH_IPV4, 3681 PRS_FLAG_OVERETH_IPV6, 3682 PRS_FLAG_OVERETH_LLCSNAP_UNKNOWN, 3683 MAX_PRS_FLAGS_OVER_ETH}; 3684 3685 3686 /* 3687 * Parsing flags for over-IP protocol 3688 */ 3689 enum prs_flags_over_ip 3690 { 3691 PRS_FLAG_OVERIP_UNKNOWN, 3692 PRS_FLAG_OVERIP_TCP, 3693 PRS_FLAG_OVERIP_UDP, 3694 MAX_PRS_FLAGS_OVER_IP}; 3695 3696 3697 /* 3698 * SDM operation gen command (generate aggregative interrupt) 3699 */ 3700 struct sdm_op_gen 3701 { 3702 uint32_t command; 3703 #define SDM_OP_GEN_COMP_PARAM (0x1F<<0) /* BitField commandcomp_param and comp_type thread ID/aggr interrupt number/counter depending on the completion type */ 3704 #define SDM_OP_GEN_COMP_PARAM_SHIFT 0 3705 #define SDM_OP_GEN_COMP_TYPE (0x7<<5) /* BitField commandcomp_param and comp_type Direct messages to CM / PCI switch are not supported in operation_gen completion */ 3706 #define SDM_OP_GEN_COMP_TYPE_SHIFT 5 3707 #define SDM_OP_GEN_AGG_VECT_IDX (0xFF<<8) /* BitField commandcomp_param and comp_type bit index in aggregated interrupt vector */ 3708 #define SDM_OP_GEN_AGG_VECT_IDX_SHIFT 8 3709 #define SDM_OP_GEN_AGG_VECT_IDX_VALID (0x1<<16) /* BitField commandcomp_param and comp_type */ 3710 #define SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT 16 3711 #define SDM_OP_GEN_RESERVED (0x7FFF<<17) /* BitField commandcomp_param and comp_type */ 3712 #define SDM_OP_GEN_RESERVED_SHIFT 17 3713 }; 3714 3715 3716 /* 3717 * Timers connection context 3718 */ 3719 struct timers_block_context 3720 { 3721 uint32_t __reserved_0 /* data of client 0 of the timers block*/; 3722 uint32_t __reserved_1 /* data of client 1 of the timers block*/; 3723 uint32_t __reserved_2 /* data of client 2 of the timers block*/; 3724 uint32_t flags; 3725 #define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS (0x3<<0) /* BitField flagscontext flags number of active timers running */ 3726 #define __TIMERS_BLOCK_CONTEXT_NUM_OF_ACTIVE_TIMERS_SHIFT 0 3727 #define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG (0x1<<2) /* BitField flagscontext flags flag: is connection valid (should be set by driver to 1 in toe/iscsi connections) */ 3728 #define TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG_SHIFT 2 3729 #define __TIMERS_BLOCK_CONTEXT_RESERVED0 (0x1FFFFFFF<<3) /* BitField flagscontext flags */ 3730 #define __TIMERS_BLOCK_CONTEXT_RESERVED0_SHIFT 3 3731 }; 3732 3733 3734 /* 3735 * The eth aggregative context of Tstorm 3736 */ 3737 struct tstorm_eth_ag_context 3738 { 3739 uint32_t __reserved0[14]; 3740 }; 3741 3742 3743 /* 3744 * The eth aggregative context of Ustorm 3745 */ 3746 struct ustorm_eth_ag_context 3747 { 3748 uint32_t __reserved0; 3749 #if defined(__BIG_ENDIAN) 3750 uint8_t cdu_usage /* Will be used by the CDU for validation of the CID/connection type on doorbells. */; 3751 uint8_t __reserved2; 3752 uint16_t __reserved1; 3753 #elif defined(__LITTLE_ENDIAN) 3754 uint16_t __reserved1; 3755 uint8_t __reserved2; 3756 uint8_t cdu_usage /* Will be used by the CDU for validation of the CID/connection type on doorbells. */; 3757 #endif 3758 uint32_t __reserved3[6]; 3759 }; 3760 3761 3762 /* 3763 * The eth aggregative context of Xstorm 3764 */ 3765 struct xstorm_eth_ag_context 3766 { 3767 uint32_t reserved0; 3768 #if defined(__BIG_ENDIAN) 3769 uint8_t cdu_reserved /* Used by the CDU for validation and debugging */; 3770 uint8_t reserved2; 3771 uint16_t reserved1; 3772 #elif defined(__LITTLE_ENDIAN) 3773 uint16_t reserved1; 3774 uint8_t reserved2; 3775 uint8_t cdu_reserved /* Used by the CDU for validation and debugging */; 3776 #endif 3777 uint32_t reserved3[30]; 3778 }; 3779 3780 3781 /* 3782 * doorbell message sent to the chip 3783 */ 3784 struct doorbell 3785 { 3786 #if defined(__BIG_ENDIAN) 3787 uint16_t zero_fill2 /* driver must zero this field! */; 3788 uint8_t zero_fill1 /* driver must zero this field! */; 3789 struct doorbell_hdr header; 3790 #elif defined(__LITTLE_ENDIAN) 3791 struct doorbell_hdr header; 3792 uint8_t zero_fill1 /* driver must zero this field! */; 3793 uint16_t zero_fill2 /* driver must zero this field! */; 3794 #endif 3795 }; 3796 3797 3798 /* 3799 * doorbell message sent to the chip 3800 */ 3801 struct doorbell_set_prod 3802 { 3803 #if defined(__BIG_ENDIAN) 3804 uint16_t prod /* Producer index to be set */; 3805 uint8_t zero_fill1 /* driver must zero this field! */; 3806 struct doorbell_hdr header; 3807 #elif defined(__LITTLE_ENDIAN) 3808 struct doorbell_hdr header; 3809 uint8_t zero_fill1 /* driver must zero this field! */; 3810 uint16_t prod /* Producer index to be set */; 3811 #endif 3812 }; 3813 3814 3815 struct regpair 3816 { 3817 uint32_t lo /* low word for reg-pair */; 3818 uint32_t hi /* high word for reg-pair */; 3819 }; 3820 3821 3822 struct regpair_native 3823 { 3824 uint32_t lo /* low word for reg-pair */; 3825 uint32_t hi /* high word for reg-pair */; 3826 }; 3827 3828 3829 /* 3830 * Classify rule opcodes in E2/E3 3831 */ 3832 enum classify_rule 3833 { 3834 CLASSIFY_RULE_OPCODE_MAC /* Add/remove a MAC address */, 3835 CLASSIFY_RULE_OPCODE_VLAN /* Add/remove a VLAN */, 3836 CLASSIFY_RULE_OPCODE_PAIR /* Add/remove a MAC-VLAN pair */, 3837 MAX_CLASSIFY_RULE}; 3838 3839 3840 /* 3841 * Classify rule types in E2/E3 3842 */ 3843 enum classify_rule_action_type 3844 { 3845 CLASSIFY_RULE_REMOVE, 3846 CLASSIFY_RULE_ADD, 3847 MAX_CLASSIFY_RULE_ACTION_TYPE}; 3848 3849 3850 /* 3851 * client init ramrod data $$KEEP_ENDIANNESS$$ 3852 */ 3853 struct client_init_general_data 3854 { 3855 uint8_t client_id /* client_id */; 3856 uint8_t statistics_counter_id /* statistics counter id */; 3857 uint8_t statistics_en_flg /* statistics en flg */; 3858 uint8_t is_fcoe_flg /* is this an fcoe connection. (1 bit is used) */; 3859 uint8_t activate_flg /* if 0 - the client is deactivate else the client is activate client (1 bit is used) */; 3860 uint8_t sp_client_id /* the slow path rings client Id. */; 3861 uint16_t mtu /* Host MTU from client config */; 3862 uint8_t statistics_zero_flg /* if set FW will reset the statistic counter of this client */; 3863 uint8_t func_id /* PCI function ID (0-71) */; 3864 uint8_t cos /* The connection cos, if applicable */; 3865 uint8_t traffic_type; 3866 uint32_t reserved0; 3867 }; 3868 3869 3870 /* 3871 * client init rx data $$KEEP_ENDIANNESS$$ 3872 */ 3873 struct client_init_rx_data 3874 { 3875 uint8_t tpa_en; 3876 #define CLIENT_INIT_RX_DATA_TPA_EN_IPV4 (0x1<<0) /* BitField tpa_entpa_enable tpa enable flg ipv4 */ 3877 #define CLIENT_INIT_RX_DATA_TPA_EN_IPV4_SHIFT 0 3878 #define CLIENT_INIT_RX_DATA_TPA_EN_IPV6 (0x1<<1) /* BitField tpa_entpa_enable tpa enable flg ipv6 */ 3879 #define CLIENT_INIT_RX_DATA_TPA_EN_IPV6_SHIFT 1 3880 #define CLIENT_INIT_RX_DATA_TPA_MODE (0x1<<2) /* BitField tpa_entpa_enable tpa mode (LRO or GRO) (use enum tpa_mode) */ 3881 #define CLIENT_INIT_RX_DATA_TPA_MODE_SHIFT 2 3882 #define CLIENT_INIT_RX_DATA_RESERVED5 (0x1F<<3) /* BitField tpa_entpa_enable */ 3883 #define CLIENT_INIT_RX_DATA_RESERVED5_SHIFT 3 3884 uint8_t vmqueue_mode_en_flg /* If set, working in VMQueue mode (always consume one sge) */; 3885 uint8_t extra_data_over_sgl_en_flg /* if set, put over sgl data from end of input message */; 3886 uint8_t cache_line_alignment_log_size /* The log size of cache line alignment in bytes. Must be a power of 2. */; 3887 uint8_t enable_dynamic_hc /* If set, dynamic HC is enabled */; 3888 uint8_t max_sges_for_packet /* The maximal number of SGEs that can be used for one packet. depends on MTU and SGE size. must be 0 if SGEs are disabled */; 3889 uint8_t client_qzone_id /* used in E2 only, to specify the HW queue zone ID used for this client rx producers */; 3890 uint8_t drop_ip_cs_err_flg /* If set, this client drops packets with IP checksum error */; 3891 uint8_t drop_tcp_cs_err_flg /* If set, this client drops packets with TCP checksum error */; 3892 uint8_t drop_ttl0_flg /* If set, this client drops packets with TTL=0 */; 3893 uint8_t drop_udp_cs_err_flg /* If set, this client drops packets with UDP checksum error */; 3894 uint8_t inner_vlan_removal_enable_flg /* If set, inner VLAN removal is enabled for this client */; 3895 uint8_t outer_vlan_removal_enable_flg /* If set, outer VLAN removal is enabled for this client */; 3896 uint8_t status_block_id /* rx status block id */; 3897 uint8_t rx_sb_index_number /* status block indices */; 3898 uint8_t dont_verify_rings_pause_thr_flg /* If set, the rings pause thresholds will not be verified by firmware. */; 3899 uint8_t max_tpa_queues /* maximal TPA queues allowed for this client */; 3900 uint8_t silent_vlan_removal_flg /* if set, and the vlan is equal to requested vlan according to mask, the vlan will be remove without notifying the driver */; 3901 uint16_t max_bytes_on_bd /* Maximum bytes that can be placed on a BD. The BD allocated size should include 2 more bytes (ip alignment) and alignment size (in case the address is not aligned) */; 3902 uint16_t sge_buff_size /* Size of the buffers pointed by SGEs */; 3903 uint8_t approx_mcast_engine_id /* In Everest2, if is_approx_mcast is set, this field specified which approximate multicast engine is associate with this client */; 3904 uint8_t rss_engine_id /* In Everest2, if rss_mode is set, this field specified which RSS engine is associate with this client */; 3905 struct regpair bd_page_base /* BD page base address at the host */; 3906 struct regpair sge_page_base /* SGE page base address at the host */; 3907 struct regpair cqe_page_base /* Completion queue base address */; 3908 uint8_t is_leading_rss; 3909 uint8_t is_approx_mcast; 3910 uint16_t max_agg_size /* maximal size for the aggregated TPA packets, reprted by the host */; 3911 uint16_t state; 3912 #define CLIENT_INIT_RX_DATA_UCAST_DROP_ALL (0x1<<0) /* BitField staterx filters state drop all unicast packets */ 3913 #define CLIENT_INIT_RX_DATA_UCAST_DROP_ALL_SHIFT 0 3914 #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_ALL (0x1<<1) /* BitField staterx filters state accept all unicast packets (subject to vlan) */ 3915 #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_ALL_SHIFT 1 3916 #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_UNMATCHED (0x1<<2) /* BitField staterx filters state accept all unmatched unicast packets (subject to vlan) */ 3917 #define CLIENT_INIT_RX_DATA_UCAST_ACCEPT_UNMATCHED_SHIFT 2 3918 #define CLIENT_INIT_RX_DATA_MCAST_DROP_ALL (0x1<<3) /* BitField staterx filters state drop all multicast packets */ 3919 #define CLIENT_INIT_RX_DATA_MCAST_DROP_ALL_SHIFT 3 3920 #define CLIENT_INIT_RX_DATA_MCAST_ACCEPT_ALL (0x1<<4) /* BitField staterx filters state accept all multicast packets (subject to vlan) */ 3921 #define CLIENT_INIT_RX_DATA_MCAST_ACCEPT_ALL_SHIFT 4 3922 #define CLIENT_INIT_RX_DATA_BCAST_ACCEPT_ALL (0x1<<5) /* BitField staterx filters state accept all broadcast packets (subject to vlan) */ 3923 #define CLIENT_INIT_RX_DATA_BCAST_ACCEPT_ALL_SHIFT 5 3924 #define CLIENT_INIT_RX_DATA_ACCEPT_ANY_VLAN (0x1<<6) /* BitField staterx filters state accept packets matched only by MAC (without checking vlan) */ 3925 #define CLIENT_INIT_RX_DATA_ACCEPT_ANY_VLAN_SHIFT 6 3926 #define CLIENT_INIT_RX_DATA_RESERVED2 (0x1FF<<7) /* BitField staterx filters state */ 3927 #define CLIENT_INIT_RX_DATA_RESERVED2_SHIFT 7 3928 uint16_t cqe_pause_thr_low /* number of remaining cqes under which, we send pause message */; 3929 uint16_t cqe_pause_thr_high /* number of remaining cqes above which, we send un-pause message */; 3930 uint16_t bd_pause_thr_low /* number of remaining bds under which, we send pause message */; 3931 uint16_t bd_pause_thr_high /* number of remaining bds above which, we send un-pause message */; 3932 uint16_t sge_pause_thr_low /* number of remaining sges under which, we send pause message */; 3933 uint16_t sge_pause_thr_high /* number of remaining sges above which, we send un-pause message */; 3934 uint16_t rx_cos_mask /* the bits that will be set on pfc/ safc paket whith will be genratet when this ring is full. for regular flow control set this to 1 */; 3935 uint16_t silent_vlan_value /* The vlan to compare, in case, silent vlan is set */; 3936 uint16_t silent_vlan_mask /* The vlan mask, in case, silent vlan is set */; 3937 uint32_t reserved6[2]; 3938 }; 3939 3940 /* 3941 * client init tx data $$KEEP_ENDIANNESS$$ 3942 */ 3943 struct client_init_tx_data 3944 { 3945 uint8_t enforce_security_flg /* if set, security checks will be made for this connection */; 3946 uint8_t tx_status_block_id /* the number of status block to update */; 3947 uint8_t tx_sb_index_number /* the index to use inside the status block */; 3948 uint8_t tss_leading_client_id /* client ID of the leading TSS client, for TX classification source knock out */; 3949 uint8_t tx_switching_flg /* if set, tx switching will be done to packets on this connection */; 3950 uint8_t anti_spoofing_flg /* if set, anti spoofing check will be done to packets on this connection */; 3951 uint16_t default_vlan /* default vlan tag (id+pri). (valid if default_vlan_flg is set) */; 3952 struct regpair tx_bd_page_base /* BD page base address at the host for TxBdCons */; 3953 uint16_t state; 3954 #define CLIENT_INIT_TX_DATA_UCAST_ACCEPT_ALL (0x1<<0) /* BitField statetx filters state accept all unicast packets (subject to vlan) */ 3955 #define CLIENT_INIT_TX_DATA_UCAST_ACCEPT_ALL_SHIFT 0 3956 #define CLIENT_INIT_TX_DATA_MCAST_ACCEPT_ALL (0x1<<1) /* BitField statetx filters state accept all multicast packets (subject to vlan) */ 3957 #define CLIENT_INIT_TX_DATA_MCAST_ACCEPT_ALL_SHIFT 1 3958 #define CLIENT_INIT_TX_DATA_BCAST_ACCEPT_ALL (0x1<<2) /* BitField statetx filters state accept all broadcast packets (subject to vlan) */ 3959 #define CLIENT_INIT_TX_DATA_BCAST_ACCEPT_ALL_SHIFT 2 3960 #define CLIENT_INIT_TX_DATA_ACCEPT_ANY_VLAN (0x1<<3) /* BitField statetx filters state accept packets matched only by MAC (without checking vlan) */ 3961 #define CLIENT_INIT_TX_DATA_ACCEPT_ANY_VLAN_SHIFT 3 3962 #define CLIENT_INIT_TX_DATA_RESERVED0 (0xFFF<<4) /* BitField statetx filters state */ 3963 #define CLIENT_INIT_TX_DATA_RESERVED0_SHIFT 4 3964 uint8_t default_vlan_flg /* is default vlan valid for this client. */; 3965 uint8_t force_default_pri_flg /* if set, force default priority */; 3966 uint8_t tunnel_lso_inc_ip_id /* In case of LSO over IPv4 tunnel, whether to increment IP ID on external IP header or internal IP header */; 3967 uint8_t refuse_outband_vlan_flg /* if set, the FW will not add outband vlan on packet (even if will exist on BD). */; 3968 uint8_t tunnel_non_lso_pcsum_location /* In case of non-Lso encapsulated packets with L4 checksum offload, the pseudo checksum location - on packet or on BD. */; 3969 uint8_t tunnel_non_lso_outer_ip_csum_location /* In case of non-Lso encapsulated packets with outer L3 ip checksum offload, the pseudo checksum location - on packet or on BD. */; 3970 }; 3971 3972 /* 3973 * client init ramrod data $$KEEP_ENDIANNESS$$ 3974 */ 3975 struct client_init_ramrod_data 3976 { 3977 struct client_init_general_data general /* client init general data */; 3978 struct client_init_rx_data rx /* client init rx data */; 3979 struct client_init_tx_data tx /* client init tx data */; 3980 }; 3981 3982 3983 /* 3984 * client update ramrod data $$KEEP_ENDIANNESS$$ 3985 */ 3986 struct client_update_ramrod_data 3987 { 3988 uint8_t client_id /* the client to update */; 3989 uint8_t func_id /* PCI function ID this client belongs to (0-71) */; 3990 uint8_t inner_vlan_removal_enable_flg /* If set, inner VLAN removal is enabled for this client, will be change according to change flag */; 3991 uint8_t inner_vlan_removal_change_flg /* If set, inner VLAN removal flag will be set according to the enable flag */; 3992 uint8_t outer_vlan_removal_enable_flg /* If set, outer VLAN removal is enabled for this client, will be change according to change flag */; 3993 uint8_t outer_vlan_removal_change_flg /* If set, outer VLAN removal flag will be set according to the enable flag */; 3994 uint8_t anti_spoofing_enable_flg /* If set, anti spoofing is enabled for this client, will be change according to change flag */; 3995 uint8_t anti_spoofing_change_flg /* If set, anti spoofing flag will be set according to anti spoofing flag */; 3996 uint8_t activate_flg /* if 0 - the client is deactivate else the client is activate client (1 bit is used) */; 3997 uint8_t activate_change_flg /* If set, activate_flg will be checked */; 3998 uint16_t default_vlan /* default vlan tag (id+pri). (valid if default_vlan_flg is set) */; 3999 uint8_t default_vlan_enable_flg; 4000 uint8_t default_vlan_change_flg; 4001 uint16_t silent_vlan_value /* The vlan to compare, in case, silent vlan is set */; 4002 uint16_t silent_vlan_mask /* The vlan mask, in case, silent vlan is set */; 4003 uint8_t silent_vlan_removal_flg /* if set, and the vlan is equal to requested vlan according to mask, the vlan will be remove without notifying the driver */; 4004 uint8_t silent_vlan_change_flg; 4005 uint8_t refuse_outband_vlan_flg /* If set, the FW will not add outband vlan on packet (even if will exist on BD). */; 4006 uint8_t refuse_outband_vlan_change_flg /* If set, refuse_outband_vlan_flg will be updated. */; 4007 uint8_t tx_switching_flg /* If set, tx switching will be done to packets on this connection. */; 4008 uint8_t tx_switching_change_flg /* If set, tx_switching_flg will be updated. */; 4009 uint32_t reserved1; 4010 uint32_t echo /* echo value to be sent to driver on event ring */; 4011 }; 4012 4013 4014 /* 4015 * The eth storm context of Cstorm 4016 */ 4017 struct cstorm_eth_st_context 4018 { 4019 uint32_t __reserved0[4]; 4020 }; 4021 4022 4023 struct double_regpair 4024 { 4025 uint32_t regpair0_lo /* low word for reg-pair0 */; 4026 uint32_t regpair0_hi /* high word for reg-pair0 */; 4027 uint32_t regpair1_lo /* low word for reg-pair1 */; 4028 uint32_t regpair1_hi /* high word for reg-pair1 */; 4029 }; 4030 4031 4032 /* 4033 * Ethernet address typesm used in ethernet tx BDs 4034 */ 4035 enum eth_addr_type 4036 { 4037 UNKNOWN_ADDRESS, 4038 UNICAST_ADDRESS, 4039 MULTICAST_ADDRESS, 4040 BROADCAST_ADDRESS, 4041 MAX_ETH_ADDR_TYPE}; 4042 4043 4044 /* 4045 * $$KEEP_ENDIANNESS$$ 4046 */ 4047 struct eth_classify_cmd_header 4048 { 4049 uint8_t cmd_general_data; 4050 #define ETH_CLASSIFY_CMD_HEADER_RX_CMD (0x1<<0) /* BitField cmd_general_data should this cmd be applied for Rx */ 4051 #define ETH_CLASSIFY_CMD_HEADER_RX_CMD_SHIFT 0 4052 #define ETH_CLASSIFY_CMD_HEADER_TX_CMD (0x1<<1) /* BitField cmd_general_data should this cmd be applied for Tx */ 4053 #define ETH_CLASSIFY_CMD_HEADER_TX_CMD_SHIFT 1 4054 #define ETH_CLASSIFY_CMD_HEADER_OPCODE (0x3<<2) /* BitField cmd_general_data command opcode for MAC/VLAN/PAIR (use enum classify_rule) */ 4055 #define ETH_CLASSIFY_CMD_HEADER_OPCODE_SHIFT 2 4056 #define ETH_CLASSIFY_CMD_HEADER_IS_ADD (0x1<<4) /* BitField cmd_general_data (use enum classify_rule_action_type) */ 4057 #define ETH_CLASSIFY_CMD_HEADER_IS_ADD_SHIFT 4 4058 #define ETH_CLASSIFY_CMD_HEADER_RESERVED0 (0x7<<5) /* BitField cmd_general_data */ 4059 #define ETH_CLASSIFY_CMD_HEADER_RESERVED0_SHIFT 5 4060 uint8_t func_id /* the function id */; 4061 uint8_t client_id; 4062 uint8_t reserved1; 4063 }; 4064 4065 4066 /* 4067 * header for eth classification config ramrod $$KEEP_ENDIANNESS$$ 4068 */ 4069 struct eth_classify_header 4070 { 4071 uint8_t rule_cnt /* number of rules in classification config ramrod */; 4072 uint8_t reserved0; 4073 uint16_t reserved1; 4074 uint32_t echo /* echo value to be sent to driver on event ring */; 4075 }; 4076 4077 4078 /* 4079 * Command for adding/removing a MAC classification rule $$KEEP_ENDIANNESS$$ 4080 */ 4081 struct eth_classify_mac_cmd 4082 { 4083 struct eth_classify_cmd_header header; 4084 uint16_t reserved0; 4085 uint16_t inner_mac; 4086 uint16_t mac_lsb; 4087 uint16_t mac_mid; 4088 uint16_t mac_msb; 4089 uint16_t reserved1; 4090 }; 4091 4092 4093 /* 4094 * Command for adding/removing a MAC-VLAN pair classification rule $$KEEP_ENDIANNESS$$ 4095 */ 4096 struct eth_classify_pair_cmd 4097 { 4098 struct eth_classify_cmd_header header; 4099 uint16_t reserved0; 4100 uint16_t inner_mac; 4101 uint16_t mac_lsb; 4102 uint16_t mac_mid; 4103 uint16_t mac_msb; 4104 uint16_t vlan; 4105 }; 4106 4107 4108 /* 4109 * Command for adding/removing a VLAN classification rule $$KEEP_ENDIANNESS$$ 4110 */ 4111 struct eth_classify_vlan_cmd 4112 { 4113 struct eth_classify_cmd_header header; 4114 uint32_t reserved0; 4115 uint32_t reserved1; 4116 uint16_t reserved2; 4117 uint16_t vlan; 4118 }; 4119 4120 /* 4121 * union for eth classification rule $$KEEP_ENDIANNESS$$ 4122 */ 4123 union eth_classify_rule_cmd 4124 { 4125 struct eth_classify_mac_cmd mac; 4126 struct eth_classify_vlan_cmd vlan; 4127 struct eth_classify_pair_cmd pair; 4128 }; 4129 4130 /* 4131 * parameters for eth classification configuration ramrod $$KEEP_ENDIANNESS$$ 4132 */ 4133 struct eth_classify_rules_ramrod_data 4134 { 4135 struct eth_classify_header header; 4136 union eth_classify_rule_cmd rules[CLASSIFY_RULES_COUNT]; 4137 }; 4138 4139 4140 /* 4141 * The data contain client ID need to the ramrod $$KEEP_ENDIANNESS$$ 4142 */ 4143 struct eth_common_ramrod_data 4144 { 4145 uint32_t client_id /* id of this client. (5 bits are used) */; 4146 uint32_t reserved1; 4147 }; 4148 4149 4150 /* 4151 * The eth storm context of Ustorm 4152 */ 4153 struct ustorm_eth_st_context 4154 { 4155 uint32_t reserved0[52]; 4156 }; 4157 4158 /* 4159 * The eth storm context of Tstorm 4160 */ 4161 struct tstorm_eth_st_context 4162 { 4163 uint32_t __reserved0[28]; 4164 }; 4165 4166 /* 4167 * The eth storm context of Xstorm 4168 */ 4169 struct xstorm_eth_st_context 4170 { 4171 uint32_t reserved0[60]; 4172 }; 4173 4174 /* 4175 * Ethernet connection context 4176 */ 4177 struct eth_context 4178 { 4179 struct ustorm_eth_st_context ustorm_st_context /* Ustorm storm context */; 4180 struct tstorm_eth_st_context tstorm_st_context /* Tstorm storm context */; 4181 struct xstorm_eth_ag_context xstorm_ag_context /* Xstorm aggregative context */; 4182 struct tstorm_eth_ag_context tstorm_ag_context /* Tstorm aggregative context */; 4183 struct cstorm_eth_ag_context cstorm_ag_context /* Cstorm aggregative context */; 4184 struct ustorm_eth_ag_context ustorm_ag_context /* Ustorm aggregative context */; 4185 struct timers_block_context timers_context /* Timers block context */; 4186 struct xstorm_eth_st_context xstorm_st_context /* Xstorm storm context */; 4187 struct cstorm_eth_st_context cstorm_st_context /* Cstorm storm context */; 4188 }; 4189 4190 4191 /* 4192 * union for sgl and raw data. 4193 */ 4194 union eth_sgl_or_raw_data 4195 { 4196 uint16_t sgl[8] /* Scatter-gather list of SGEs used by this packet. This list includes the indices of the SGEs. */; 4197 uint32_t raw_data[4] /* raw data from Tstorm to the driver. */; 4198 }; 4199 4200 /* 4201 * eth FP end aggregation CQE parameters struct $$KEEP_ENDIANNESS$$ 4202 */ 4203 struct eth_end_agg_rx_cqe 4204 { 4205 uint8_t type_error_flags; 4206 #define ETH_END_AGG_RX_CQE_TYPE (0x3<<0) /* BitField type_error_flags (use enum eth_rx_cqe_type) */ 4207 #define ETH_END_AGG_RX_CQE_TYPE_SHIFT 0 4208 #define ETH_END_AGG_RX_CQE_SGL_RAW_SEL (0x1<<2) /* BitField type_error_flags (use enum eth_rx_fp_sel) */ 4209 #define ETH_END_AGG_RX_CQE_SGL_RAW_SEL_SHIFT 2 4210 #define ETH_END_AGG_RX_CQE_RESERVED0 (0x1F<<3) /* BitField type_error_flags */ 4211 #define ETH_END_AGG_RX_CQE_RESERVED0_SHIFT 3 4212 uint8_t reserved1; 4213 uint8_t queue_index /* The aggregation queue index of this packet */; 4214 uint8_t reserved2; 4215 uint32_t timestamp_delta /* timestamp delta between first packet to last packet in aggregation */; 4216 uint16_t num_of_coalesced_segs /* Num of coalesced segments. */; 4217 uint16_t pkt_len /* Packet length */; 4218 uint8_t pure_ack_count /* Number of pure acks coalesced. */; 4219 uint8_t reserved3; 4220 uint16_t reserved4; 4221 union eth_sgl_or_raw_data sgl_or_raw_data /* union for sgl and raw data. */; 4222 uint32_t reserved5[8]; 4223 }; 4224 4225 4226 /* 4227 * regular eth FP CQE parameters struct $$KEEP_ENDIANNESS$$ 4228 */ 4229 struct eth_fast_path_rx_cqe 4230 { 4231 uint8_t type_error_flags; 4232 #define ETH_FAST_PATH_RX_CQE_TYPE (0x3<<0) /* BitField type_error_flags (use enum eth_rx_cqe_type) */ 4233 #define ETH_FAST_PATH_RX_CQE_TYPE_SHIFT 0 4234 #define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL (0x1<<2) /* BitField type_error_flags (use enum eth_rx_fp_sel) */ 4235 #define ETH_FAST_PATH_RX_CQE_SGL_RAW_SEL_SHIFT 2 4236 #define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG (0x1<<3) /* BitField type_error_flags Physical layer errors */ 4237 #define ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG_SHIFT 3 4238 #define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG (0x1<<4) /* BitField type_error_flags IP checksum error */ 4239 #define ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG_SHIFT 4 4240 #define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG (0x1<<5) /* BitField type_error_flags TCP/UDP checksum error */ 4241 #define ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG_SHIFT 5 4242 #define ETH_FAST_PATH_RX_CQE_RESERVED0 (0x3<<6) /* BitField type_error_flags */ 4243 #define ETH_FAST_PATH_RX_CQE_RESERVED0_SHIFT 6 4244 uint8_t status_flags; 4245 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE (0x7<<0) /* BitField status_flags (use enum eth_rss_hash_type) */ 4246 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_TYPE_SHIFT 0 4247 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG (0x1<<3) /* BitField status_flags RSS hashing on/off */ 4248 #define ETH_FAST_PATH_RX_CQE_RSS_HASH_FLG_SHIFT 3 4249 #define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG (0x1<<4) /* BitField status_flags if set to 1, this is a broadcast packet */ 4250 #define ETH_FAST_PATH_RX_CQE_BROADCAST_FLG_SHIFT 4 4251 #define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG (0x1<<5) /* BitField status_flags if set to 1, the MAC address was matched in the tstorm CAM search */ 4252 #define ETH_FAST_PATH_RX_CQE_MAC_MATCH_FLG_SHIFT 5 4253 #define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG (0x1<<6) /* BitField status_flags IP checksum validation was not performed (if packet is not IPv4) */ 4254 #define ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG_SHIFT 6 4255 #define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG (0x1<<7) /* BitField status_flags TCP/UDP checksum validation was not performed (if packet is not TCP/UDP or IPv6 extheaders exist) */ 4256 #define ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG_SHIFT 7 4257 uint8_t queue_index /* The aggregation queue index of this packet */; 4258 uint8_t placement_offset /* Placement offset from the start of the BD, in bytes */; 4259 uint32_t rss_hash_result /* RSS toeplitz hash result */; 4260 uint16_t vlan_tag /* Ethernet VLAN tag field */; 4261 uint16_t pkt_len_or_gro_seg_len /* Packet length (for non-TPA CQE) or GRO Segment Length (for TPA in GRO Mode) otherwise 0 */; 4262 uint16_t len_on_bd /* Number of bytes placed on the BD */; 4263 struct parsing_flags pars_flags; 4264 union eth_sgl_or_raw_data sgl_or_raw_data /* union for sgl and raw data. */; 4265 uint32_t reserved1[8]; 4266 }; 4267 4268 4269 /* 4270 * Command for setting classification flags for a client $$KEEP_ENDIANNESS$$ 4271 */ 4272 struct eth_filter_rules_cmd 4273 { 4274 uint8_t cmd_general_data; 4275 #define ETH_FILTER_RULES_CMD_RX_CMD (0x1<<0) /* BitField cmd_general_data should this cmd be applied for Rx */ 4276 #define ETH_FILTER_RULES_CMD_RX_CMD_SHIFT 0 4277 #define ETH_FILTER_RULES_CMD_TX_CMD (0x1<<1) /* BitField cmd_general_data should this cmd be applied for Tx */ 4278 #define ETH_FILTER_RULES_CMD_TX_CMD_SHIFT 1 4279 #define ETH_FILTER_RULES_CMD_RESERVED0 (0x3F<<2) /* BitField cmd_general_data */ 4280 #define ETH_FILTER_RULES_CMD_RESERVED0_SHIFT 2 4281 uint8_t func_id /* the function id */; 4282 uint8_t client_id /* the client id */; 4283 uint8_t reserved1; 4284 uint16_t state; 4285 #define ETH_FILTER_RULES_CMD_UCAST_DROP_ALL (0x1<<0) /* BitField state drop all unicast packets */ 4286 #define ETH_FILTER_RULES_CMD_UCAST_DROP_ALL_SHIFT 0 4287 #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL (0x1<<1) /* BitField state accept all unicast packets (subject to vlan) */ 4288 #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_ALL_SHIFT 1 4289 #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED (0x1<<2) /* BitField state accept all unmatched unicast packets */ 4290 #define ETH_FILTER_RULES_CMD_UCAST_ACCEPT_UNMATCHED_SHIFT 2 4291 #define ETH_FILTER_RULES_CMD_MCAST_DROP_ALL (0x1<<3) /* BitField state drop all multicast packets */ 4292 #define ETH_FILTER_RULES_CMD_MCAST_DROP_ALL_SHIFT 3 4293 #define ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL (0x1<<4) /* BitField state accept all multicast packets (subject to vlan) */ 4294 #define ETH_FILTER_RULES_CMD_MCAST_ACCEPT_ALL_SHIFT 4 4295 #define ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL (0x1<<5) /* BitField state accept all broadcast packets (subject to vlan) */ 4296 #define ETH_FILTER_RULES_CMD_BCAST_ACCEPT_ALL_SHIFT 5 4297 #define ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN (0x1<<6) /* BitField state accept packets matched only by MAC (without checking vlan) */ 4298 #define ETH_FILTER_RULES_CMD_ACCEPT_ANY_VLAN_SHIFT 6 4299 #define ETH_FILTER_RULES_CMD_RESERVED2 (0x1FF<<7) /* BitField state */ 4300 #define ETH_FILTER_RULES_CMD_RESERVED2_SHIFT 7 4301 uint16_t reserved3; 4302 struct regpair reserved4; 4303 }; 4304 4305 4306 /* 4307 * parameters for eth classification filters ramrod $$KEEP_ENDIANNESS$$ 4308 */ 4309 struct eth_filter_rules_ramrod_data 4310 { 4311 struct eth_classify_header header; 4312 struct eth_filter_rules_cmd rules[FILTER_RULES_COUNT]; 4313 }; 4314 4315 4316 /* 4317 * parameters for eth classification configuration ramrod $$KEEP_ENDIANNESS$$ 4318 */ 4319 struct eth_general_rules_ramrod_data 4320 { 4321 struct eth_classify_header header; 4322 union eth_classify_rule_cmd rules[CLASSIFY_RULES_COUNT]; 4323 }; 4324 4325 4326 /* 4327 * The data for Halt ramrod 4328 */ 4329 struct eth_halt_ramrod_data 4330 { 4331 uint32_t client_id /* id of this client. (5 bits are used) */; 4332 uint32_t reserved0; 4333 }; 4334 4335 4336 /* 4337 * destination and source mac address. 4338 */ 4339 struct eth_mac_addresses 4340 { 4341 #if defined(__BIG_ENDIAN) 4342 uint16_t dst_mid /* destination mac address 16 middle bits */; 4343 uint16_t dst_lo /* destination mac address 16 low bits */; 4344 #elif defined(__LITTLE_ENDIAN) 4345 uint16_t dst_lo /* destination mac address 16 low bits */; 4346 uint16_t dst_mid /* destination mac address 16 middle bits */; 4347 #endif 4348 #if defined(__BIG_ENDIAN) 4349 uint16_t src_lo /* source mac address 16 low bits */; 4350 uint16_t dst_hi /* destination mac address 16 high bits */; 4351 #elif defined(__LITTLE_ENDIAN) 4352 uint16_t dst_hi /* destination mac address 16 high bits */; 4353 uint16_t src_lo /* source mac address 16 low bits */; 4354 #endif 4355 #if defined(__BIG_ENDIAN) 4356 uint16_t src_hi /* source mac address 16 high bits */; 4357 uint16_t src_mid /* source mac address 16 middle bits */; 4358 #elif defined(__LITTLE_ENDIAN) 4359 uint16_t src_mid /* source mac address 16 middle bits */; 4360 uint16_t src_hi /* source mac address 16 high bits */; 4361 #endif 4362 }; 4363 4364 4365 /* 4366 * tunneling related data. 4367 */ 4368 struct eth_tunnel_data 4369 { 4370 #if defined(__BIG_ENDIAN) 4371 uint16_t dst_mid /* destination mac address 16 middle bits */; 4372 uint16_t dst_lo /* destination mac address 16 low bits */; 4373 #elif defined(__LITTLE_ENDIAN) 4374 uint16_t dst_lo /* destination mac address 16 low bits */; 4375 uint16_t dst_mid /* destination mac address 16 middle bits */; 4376 #endif 4377 #if defined(__BIG_ENDIAN) 4378 uint16_t fw_ip_hdr_csum /* Fw Ip header checksum (with ALL ip header fields) for the outer IP header */; 4379 uint16_t dst_hi /* destination mac address 16 high bits */; 4380 #elif defined(__LITTLE_ENDIAN) 4381 uint16_t dst_hi /* destination mac address 16 high bits */; 4382 uint16_t fw_ip_hdr_csum /* Fw Ip header checksum (with ALL ip header fields) for the outer IP header */; 4383 #endif 4384 #if defined(__BIG_ENDIAN) 4385 uint8_t flags; 4386 #define ETH_TUNNEL_DATA_IP_HDR_TYPE_OUTER (0x1<<0) /* BitField flags Set in case outer IP header is ipV6 */ 4387 #define ETH_TUNNEL_DATA_IP_HDR_TYPE_OUTER_SHIFT 0 4388 #define ETH_TUNNEL_DATA_RESERVED (0x7F<<1) /* BitField flags Should be set with 0 */ 4389 #define ETH_TUNNEL_DATA_RESERVED_SHIFT 1 4390 uint8_t ip_hdr_start_inner_w /* Inner IP header offset in WORDs (16-bit) from start of packet */; 4391 uint16_t pseudo_csum /* Pseudo checksum with length field=0 */; 4392 #elif defined(__LITTLE_ENDIAN) 4393 uint16_t pseudo_csum /* Pseudo checksum with length field=0 */; 4394 uint8_t ip_hdr_start_inner_w /* Inner IP header offset in WORDs (16-bit) from start of packet */; 4395 uint8_t flags; 4396 #define ETH_TUNNEL_DATA_IP_HDR_TYPE_OUTER (0x1<<0) /* BitField flags Set in case outer IP header is ipV6 */ 4397 #define ETH_TUNNEL_DATA_IP_HDR_TYPE_OUTER_SHIFT 0 4398 #define ETH_TUNNEL_DATA_RESERVED (0x7F<<1) /* BitField flags Should be set with 0 */ 4399 #define ETH_TUNNEL_DATA_RESERVED_SHIFT 1 4400 #endif 4401 }; 4402 4403 /* 4404 * union for mac addresses and for tunneling data. considered as tunneling data only if (tunnel_exist == 1). 4405 */ 4406 union eth_mac_addr_or_tunnel_data 4407 { 4408 struct eth_mac_addresses mac_addr /* destination and source mac addresses. */; 4409 struct eth_tunnel_data tunnel_data /* tunneling related data. */; 4410 }; 4411 4412 4413 /* 4414 * Command for setting multicast classification for a client $$KEEP_ENDIANNESS$$ 4415 */ 4416 struct eth_multicast_rules_cmd 4417 { 4418 uint8_t cmd_general_data; 4419 #define ETH_MULTICAST_RULES_CMD_RX_CMD (0x1<<0) /* BitField cmd_general_data should this cmd be applied for Rx */ 4420 #define ETH_MULTICAST_RULES_CMD_RX_CMD_SHIFT 0 4421 #define ETH_MULTICAST_RULES_CMD_TX_CMD (0x1<<1) /* BitField cmd_general_data should this cmd be applied for Tx */ 4422 #define ETH_MULTICAST_RULES_CMD_TX_CMD_SHIFT 1 4423 #define ETH_MULTICAST_RULES_CMD_IS_ADD (0x1<<2) /* BitField cmd_general_data 1 for add rule, 0 for remove rule */ 4424 #define ETH_MULTICAST_RULES_CMD_IS_ADD_SHIFT 2 4425 #define ETH_MULTICAST_RULES_CMD_RESERVED0 (0x1F<<3) /* BitField cmd_general_data */ 4426 #define ETH_MULTICAST_RULES_CMD_RESERVED0_SHIFT 3 4427 uint8_t func_id /* the function id */; 4428 uint8_t bin_id /* the bin to add this function to (0-255) */; 4429 uint8_t engine_id /* the approximate multicast engine id */; 4430 uint32_t reserved2; 4431 struct regpair reserved3; 4432 }; 4433 4434 4435 /* 4436 * parameters for multicast classification ramrod $$KEEP_ENDIANNESS$$ 4437 */ 4438 struct eth_multicast_rules_ramrod_data 4439 { 4440 struct eth_classify_header header; 4441 struct eth_multicast_rules_cmd rules[MULTICAST_RULES_COUNT]; 4442 }; 4443 4444 4445 /* 4446 * Place holder for ramrods protocol specific data 4447 */ 4448 struct ramrod_data 4449 { 4450 uint32_t data_lo; 4451 uint32_t data_hi; 4452 }; 4453 4454 /* 4455 * union for ramrod data for Ethernet protocol (CQE) (force size of 16 bits) 4456 */ 4457 union eth_ramrod_data 4458 { 4459 struct ramrod_data general; 4460 }; 4461 4462 4463 /* 4464 * RSS toeplitz hash type, as reported in CQE 4465 */ 4466 enum eth_rss_hash_type 4467 { 4468 DEFAULT_HASH_TYPE, 4469 IPV4_HASH_TYPE, 4470 TCP_IPV4_HASH_TYPE, 4471 IPV6_HASH_TYPE, 4472 TCP_IPV6_HASH_TYPE, 4473 VLAN_PRI_HASH_TYPE, 4474 E1HOV_PRI_HASH_TYPE, 4475 DSCP_HASH_TYPE, 4476 MAX_ETH_RSS_HASH_TYPE}; 4477 4478 4479 /* 4480 * Ethernet RSS mode 4481 */ 4482 enum eth_rss_mode 4483 { 4484 ETH_RSS_MODE_DISABLED, 4485 ETH_RSS_MODE_ESX51 /* RSS mode for Vmware ESX 5.1 (Only do RSS if packet is UDP with dst port that matches the UDP 4-tuble Destination Port mask and value) */, 4486 ETH_RSS_MODE_REGULAR /* Regular (ndis-like) RSS */, 4487 ETH_RSS_MODE_VLAN_PRI /* RSS based on inner-vlan priority field */, 4488 ETH_RSS_MODE_E1HOV_PRI /* RSS based on outer-vlan priority field */, 4489 ETH_RSS_MODE_IP_DSCP /* RSS based on IPv4 DSCP field */, 4490 MAX_ETH_RSS_MODE}; 4491 4492 4493 /* 4494 * parameters for RSS update ramrod (E2) $$KEEP_ENDIANNESS$$ 4495 */ 4496 struct eth_rss_update_ramrod_data 4497 { 4498 uint8_t rss_engine_id; 4499 uint8_t capabilities; 4500 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY (0x1<<0) /* BitField capabilitiesFunction RSS capabilities configuration of the IpV4 2-tupple capability */ 4501 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_CAPABILITY_SHIFT 0 4502 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY (0x1<<1) /* BitField capabilitiesFunction RSS capabilities configuration of the IpV4 4-tupple capability for TCP */ 4503 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_TCP_CAPABILITY_SHIFT 1 4504 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY (0x1<<2) /* BitField capabilitiesFunction RSS capabilities configuration of the IpV4 4-tupple capability for UDP */ 4505 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV4_UDP_CAPABILITY_SHIFT 2 4506 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY (0x1<<3) /* BitField capabilitiesFunction RSS capabilities configuration of the IpV6 2-tupple capability */ 4507 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_CAPABILITY_SHIFT 3 4508 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY (0x1<<4) /* BitField capabilitiesFunction RSS capabilities configuration of the IpV6 4-tupple capability for TCP */ 4509 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_TCP_CAPABILITY_SHIFT 4 4510 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY (0x1<<5) /* BitField capabilitiesFunction RSS capabilities configuration of the IpV6 4-tupple capability for UDP */ 4511 #define ETH_RSS_UPDATE_RAMROD_DATA_IPV6_UDP_CAPABILITY_SHIFT 5 4512 #define ETH_RSS_UPDATE_RAMROD_DATA_EN_5_TUPLE_CAPABILITY (0x1<<6) /* BitField capabilitiesFunction RSS capabilities configuration of the 5-tupple capability */ 4513 #define ETH_RSS_UPDATE_RAMROD_DATA_EN_5_TUPLE_CAPABILITY_SHIFT 6 4514 #define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY (0x1<<7) /* BitField capabilitiesFunction RSS capabilities if set update the rss keys */ 4515 #define ETH_RSS_UPDATE_RAMROD_DATA_UPDATE_RSS_KEY_SHIFT 7 4516 uint8_t rss_result_mask /* The mask for the lower byte of RSS result - defines which section of the indirection table will be used. To enable all table put here 0x7F */; 4517 uint8_t rss_mode /* The RSS mode for this function */; 4518 uint16_t udp_4tuple_dst_port_mask /* If UDP 4-tuple enabled, packets that match the mask and value are 4-tupled, the rest are 2-tupled. (Set to 0 to match all) */; 4519 uint16_t udp_4tuple_dst_port_value /* If UDP 4-tuple enabled, packets that match the mask and value are 4-tupled, the rest are 2-tupled. (Set to 0 to match all) */; 4520 uint8_t indirection_table[T_ETH_INDIRECTION_TABLE_SIZE] /* RSS indirection table */; 4521 uint32_t rss_key[T_ETH_RSS_KEY] /* RSS key supplied as by OS */; 4522 uint32_t echo; 4523 uint32_t reserved3; 4524 }; 4525 4526 4527 /* 4528 * The eth Rx Buffer Descriptor 4529 */ 4530 struct eth_rx_bd 4531 { 4532 uint32_t addr_lo /* Single continuous buffer low pointer */; 4533 uint32_t addr_hi /* Single continuous buffer high pointer */; 4534 }; 4535 4536 4537 /* 4538 * Eth Rx Cqe structure- general structure for ramrods $$KEEP_ENDIANNESS$$ 4539 */ 4540 struct common_ramrod_eth_rx_cqe 4541 { 4542 uint8_t ramrod_type; 4543 #define COMMON_RAMROD_ETH_RX_CQE_TYPE (0x3<<0) /* BitField ramrod_type (use enum eth_rx_cqe_type) */ 4544 #define COMMON_RAMROD_ETH_RX_CQE_TYPE_SHIFT 0 4545 #define COMMON_RAMROD_ETH_RX_CQE_ERROR (0x1<<2) /* BitField ramrod_type */ 4546 #define COMMON_RAMROD_ETH_RX_CQE_ERROR_SHIFT 2 4547 #define COMMON_RAMROD_ETH_RX_CQE_RESERVED0 (0x1F<<3) /* BitField ramrod_type */ 4548 #define COMMON_RAMROD_ETH_RX_CQE_RESERVED0_SHIFT 3 4549 uint8_t conn_type /* only 3 bits are used */; 4550 uint16_t reserved1 /* protocol specific data */; 4551 uint32_t conn_and_cmd_data; 4552 #define COMMON_RAMROD_ETH_RX_CQE_CID (0xFFFFFF<<0) /* BitField conn_and_cmd_data */ 4553 #define COMMON_RAMROD_ETH_RX_CQE_CID_SHIFT 0 4554 #define COMMON_RAMROD_ETH_RX_CQE_CMD_ID (0xFF<<24) /* BitField conn_and_cmd_data command id of the ramrod- use RamrodCommandIdEnum */ 4555 #define COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT 24 4556 struct ramrod_data protocol_data /* protocol specific data */; 4557 uint32_t echo; 4558 uint32_t reserved2[11]; 4559 }; 4560 4561 /* 4562 * Rx Last CQE in page (in ETH) 4563 */ 4564 struct eth_rx_cqe_next_page 4565 { 4566 uint32_t addr_lo /* Next page low pointer */; 4567 uint32_t addr_hi /* Next page high pointer */; 4568 uint32_t reserved[14]; 4569 }; 4570 4571 /* 4572 * union for all eth rx cqe types (fix their sizes) 4573 */ 4574 union eth_rx_cqe 4575 { 4576 struct eth_fast_path_rx_cqe fast_path_cqe; 4577 struct common_ramrod_eth_rx_cqe ramrod_cqe; 4578 struct eth_rx_cqe_next_page next_page_cqe; 4579 struct eth_end_agg_rx_cqe end_agg_cqe; 4580 }; 4581 4582 4583 /* 4584 * Values for RX ETH CQE type field 4585 */ 4586 enum eth_rx_cqe_type 4587 { 4588 RX_ETH_CQE_TYPE_ETH_FASTPATH /* Fast path CQE */, 4589 RX_ETH_CQE_TYPE_ETH_RAMROD /* Slow path CQE */, 4590 RX_ETH_CQE_TYPE_ETH_START_AGG /* Fast path CQE */, 4591 RX_ETH_CQE_TYPE_ETH_STOP_AGG /* Slow path CQE */, 4592 MAX_ETH_RX_CQE_TYPE}; 4593 4594 4595 /* 4596 * Type of SGL/Raw field in ETH RX fast path CQE 4597 */ 4598 enum eth_rx_fp_sel 4599 { 4600 ETH_FP_CQE_REGULAR /* Regular CQE- no extra data */, 4601 ETH_FP_CQE_RAW /* Extra data is raw data- iscsi OOO */, 4602 MAX_ETH_RX_FP_SEL}; 4603 4604 4605 /* 4606 * The eth Rx SGE Descriptor 4607 */ 4608 struct eth_rx_sge 4609 { 4610 uint32_t addr_lo /* Single continuous buffer low pointer */; 4611 uint32_t addr_hi /* Single continuous buffer high pointer */; 4612 }; 4613 4614 4615 /* 4616 * common data for all protocols $$KEEP_ENDIANNESS$$ 4617 */ 4618 struct spe_hdr 4619 { 4620 uint32_t conn_and_cmd_data; 4621 #define SPE_HDR_CID (0xFFFFFF<<0) /* BitField conn_and_cmd_data */ 4622 #define SPE_HDR_CID_SHIFT 0 4623 #define SPE_HDR_CMD_ID (0xFF<<24) /* BitField conn_and_cmd_data command id of the ramrod- use enum common_spqe_cmd_id/eth_spqe_cmd_id/toe_spqe_cmd_id */ 4624 #define SPE_HDR_CMD_ID_SHIFT 24 4625 uint16_t type; 4626 #define SPE_HDR_CONN_TYPE (0xFF<<0) /* BitField type connection type. (3 bits are used) (use enum connection_type) */ 4627 #define SPE_HDR_CONN_TYPE_SHIFT 0 4628 #define SPE_HDR_FUNCTION_ID (0xFF<<8) /* BitField type */ 4629 #define SPE_HDR_FUNCTION_ID_SHIFT 8 4630 uint16_t reserved1; 4631 }; 4632 4633 /* 4634 * specific data for ethernet slow path element 4635 */ 4636 union eth_specific_data 4637 { 4638 uint8_t protocol_data[8] /* to fix this structure size to 8 bytes */; 4639 struct regpair client_update_ramrod_data /* The address of the data for client update ramrod */; 4640 struct regpair client_init_ramrod_init_data /* The data for client setup ramrod */; 4641 struct eth_halt_ramrod_data halt_ramrod_data /* Includes the client id to be deleted */; 4642 struct regpair update_data_addr /* physical address of the eth_rss_update_ramrod_data struct, as allocated by the driver */; 4643 struct eth_common_ramrod_data common_ramrod_data /* The data contain client ID need to the ramrod */; 4644 struct regpair classify_cfg_addr /* physical address of the eth_classify_rules_ramrod_data struct, as allocated by the driver */; 4645 struct regpair filter_cfg_addr /* physical address of the eth_filter_cfg_ramrod_data struct, as allocated by the driver */; 4646 struct regpair mcast_cfg_addr /* physical address of the eth_mcast_cfg_ramrod_data struct, as allocated by the driver */; 4647 }; 4648 4649 /* 4650 * Ethernet slow path element 4651 */ 4652 struct eth_spe 4653 { 4654 struct spe_hdr hdr /* common data for all protocols */; 4655 union eth_specific_data data /* data specific to ethernet protocol */; 4656 }; 4657 4658 4659 /* 4660 * Ethernet command ID for slow path elements 4661 */ 4662 enum eth_spqe_cmd_id 4663 { 4664 RAMROD_CMD_ID_ETH_UNUSED, 4665 RAMROD_CMD_ID_ETH_CLIENT_SETUP /* Setup a new L2 client */, 4666 RAMROD_CMD_ID_ETH_HALT /* Halt an L2 client */, 4667 RAMROD_CMD_ID_ETH_FORWARD_SETUP /* Setup a new FW channel */, 4668 RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP /* Setup a new Tx only queue */, 4669 RAMROD_CMD_ID_ETH_CLIENT_UPDATE /* Update an L2 client configuration */, 4670 RAMROD_CMD_ID_ETH_EMPTY /* Empty ramrod - used to synchronize iSCSI OOO */, 4671 RAMROD_CMD_ID_ETH_TERMINATE /* Terminate an L2 client */, 4672 RAMROD_CMD_ID_ETH_TPA_UPDATE /* update the tpa roles in L2 client */, 4673 RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES /* Add/remove classification filters for L2 client (in E2/E3 only) */, 4674 RAMROD_CMD_ID_ETH_FILTER_RULES /* Add/remove classification filters for L2 client (in E2/E3 only) */, 4675 RAMROD_CMD_ID_ETH_MULTICAST_RULES /* Add/remove multicast classification bin (in E2/E3 only) */, 4676 RAMROD_CMD_ID_ETH_RSS_UPDATE /* Update RSS configuration */, 4677 RAMROD_CMD_ID_ETH_SET_MAC /* Update RSS configuration */, 4678 MAX_ETH_SPQE_CMD_ID}; 4679 4680 4681 /* 4682 * eth tpa update command 4683 */ 4684 enum eth_tpa_update_command 4685 { 4686 TPA_UPDATE_NONE_COMMAND /* nop command */, 4687 TPA_UPDATE_ENABLE_COMMAND /* enable command */, 4688 TPA_UPDATE_DISABLE_COMMAND /* disable command */, 4689 MAX_ETH_TPA_UPDATE_COMMAND}; 4690 4691 4692 /* 4693 * In case of LSO over IPv4 tunnel, whether to increment IP ID on external IP header or internal IP header 4694 */ 4695 enum eth_tunnel_lso_inc_ip_id 4696 { 4697 EXT_HEADER /* Increment IP ID of external header (HW works on external, FW works on internal */, 4698 INT_HEADER /* Increment IP ID of internal header (HW works on internal, FW works on external */, 4699 MAX_ETH_TUNNEL_LSO_INC_IP_ID}; 4700 4701 4702 /* 4703 * In case tunnel exist and L4 checksum offload (or outer ip header checksum), the pseudo checksum location, on packet or on BD. 4704 */ 4705 enum eth_tunnel_non_lso_csum_location 4706 { 4707 CSUM_ON_PKT /* checksum is on the packet. */, 4708 CSUM_ON_BD /* checksum is on the BD. */, 4709 MAX_ETH_TUNNEL_NON_LSO_CSUM_LOCATION}; 4710 4711 4712 /* 4713 * Tx regular BD structure $$KEEP_ENDIANNESS$$ 4714 */ 4715 struct eth_tx_bd 4716 { 4717 uint32_t addr_lo /* Single continuous buffer low pointer */; 4718 uint32_t addr_hi /* Single continuous buffer high pointer */; 4719 uint16_t total_pkt_bytes /* Size of the entire packet, valid for non-LSO packets */; 4720 uint16_t nbytes /* Size of the data represented by the BD */; 4721 uint8_t reserved[4] /* keeps same size as other eth tx bd types */; 4722 }; 4723 4724 4725 /* 4726 * structure for easy accessibility to assembler 4727 */ 4728 struct eth_tx_bd_flags 4729 { 4730 uint8_t as_bitfield; 4731 #define ETH_TX_BD_FLAGS_IP_CSUM (0x1<<0) /* BitField as_bitfield IP CKSUM flag,Relevant in START */ 4732 #define ETH_TX_BD_FLAGS_IP_CSUM_SHIFT 0 4733 #define ETH_TX_BD_FLAGS_L4_CSUM (0x1<<1) /* BitField as_bitfield L4 CKSUM flag,Relevant in START */ 4734 #define ETH_TX_BD_FLAGS_L4_CSUM_SHIFT 1 4735 #define ETH_TX_BD_FLAGS_VLAN_MODE (0x3<<2) /* BitField as_bitfield 00 - no vlan; 01 - inband Vlan; 10 outband Vlan (use enum eth_tx_vlan_type) */ 4736 #define ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT 2 4737 #define ETH_TX_BD_FLAGS_START_BD (0x1<<4) /* BitField as_bitfield Start of packet BD */ 4738 #define ETH_TX_BD_FLAGS_START_BD_SHIFT 4 4739 #define ETH_TX_BD_FLAGS_IS_UDP (0x1<<5) /* BitField as_bitfield flag that indicates that the current packet is a udp packet */ 4740 #define ETH_TX_BD_FLAGS_IS_UDP_SHIFT 5 4741 #define ETH_TX_BD_FLAGS_SW_LSO (0x1<<6) /* BitField as_bitfield LSO flag, Relevant in START */ 4742 #define ETH_TX_BD_FLAGS_SW_LSO_SHIFT 6 4743 #define ETH_TX_BD_FLAGS_IPV6 (0x1<<7) /* BitField as_bitfield set in case ipV6 packet, Relevant in START */ 4744 #define ETH_TX_BD_FLAGS_IPV6_SHIFT 7 4745 }; 4746 4747 /* 4748 * The eth Tx Buffer Descriptor $$KEEP_ENDIANNESS$$ 4749 */ 4750 struct eth_tx_start_bd 4751 { 4752 uint32_t addr_lo /* Single continuous buffer low pointer */; 4753 uint32_t addr_hi /* Single continuous buffer high pointer */; 4754 uint16_t nbd /* Num of BDs in packet: include parsInfoBD, Relevant in START(only in Everest) */; 4755 uint16_t nbytes /* Size of the data represented by the BD */; 4756 uint16_t vlan_or_ethertype /* Vlan structure: vlan_id is in lsb, then cfi and then priority vlan_id 12 bits (lsb), cfi 1 bit, priority 3 bits. In E2, this field should be set with etherType for VFs with no vlan */; 4757 struct eth_tx_bd_flags bd_flags; 4758 uint8_t general_data; 4759 #define ETH_TX_START_BD_HDR_NBDS (0xF<<0) /* BitField general_data contains the number of BDs that contain Ethernet/IP/TCP headers, for full/partial LSO modes */ 4760 #define ETH_TX_START_BD_HDR_NBDS_SHIFT 0 4761 #define ETH_TX_START_BD_FORCE_VLAN_MODE (0x1<<4) /* BitField general_data force vlan mode according to bds (vlan mode can change accroding to global configuration) */ 4762 #define ETH_TX_START_BD_FORCE_VLAN_MODE_SHIFT 4 4763 #define ETH_TX_START_BD_PARSE_NBDS (0x3<<5) /* BitField general_data Determines the number of parsing BDs in packet. Number of parsing BDs in packet is (parse_nbds+1). */ 4764 #define ETH_TX_START_BD_PARSE_NBDS_SHIFT 5 4765 #define ETH_TX_START_BD_TUNNEL_EXIST (0x1<<7) /* BitField general_data set in case of tunneling encapsulated packet */ 4766 #define ETH_TX_START_BD_TUNNEL_EXIST_SHIFT 7 4767 }; 4768 4769 /* 4770 * Tx parsing BD structure for ETH E1/E1h $$KEEP_ENDIANNESS$$ 4771 */ 4772 struct eth_tx_parse_bd_e1x 4773 { 4774 uint16_t global_data; 4775 #define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W (0xF<<0) /* BitField global_data IP header Offset in WORDs from start of packet */ 4776 #define ETH_TX_PARSE_BD_E1X_IP_HDR_START_OFFSET_W_SHIFT 0 4777 #define ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE (0x3<<4) /* BitField global_data marks ethernet address type (use enum eth_addr_type) */ 4778 #define ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE_SHIFT 4 4779 #define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN (0x1<<6) /* BitField global_data */ 4780 #define ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN_SHIFT 6 4781 #define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN (0x1<<7) /* BitField global_data */ 4782 #define ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN_SHIFT 7 4783 #define ETH_TX_PARSE_BD_E1X_NS_FLG (0x1<<8) /* BitField global_data an optional addition to ECN that protects against accidental or malicious concealment of marked packets from the TCP sender. */ 4784 #define ETH_TX_PARSE_BD_E1X_NS_FLG_SHIFT 8 4785 #define ETH_TX_PARSE_BD_E1X_RESERVED0 (0x7F<<9) /* BitField global_data reserved bit, should be set with 0 */ 4786 #define ETH_TX_PARSE_BD_E1X_RESERVED0_SHIFT 9 4787 uint8_t tcp_flags; 4788 #define ETH_TX_PARSE_BD_E1X_FIN_FLG (0x1<<0) /* BitField tcp_flagsState flags End of data flag */ 4789 #define ETH_TX_PARSE_BD_E1X_FIN_FLG_SHIFT 0 4790 #define ETH_TX_PARSE_BD_E1X_SYN_FLG (0x1<<1) /* BitField tcp_flagsState flags Synchronize sequence numbers flag */ 4791 #define ETH_TX_PARSE_BD_E1X_SYN_FLG_SHIFT 1 4792 #define ETH_TX_PARSE_BD_E1X_RST_FLG (0x1<<2) /* BitField tcp_flagsState flags Reset connection flag */ 4793 #define ETH_TX_PARSE_BD_E1X_RST_FLG_SHIFT 2 4794 #define ETH_TX_PARSE_BD_E1X_PSH_FLG (0x1<<3) /* BitField tcp_flagsState flags Push flag */ 4795 #define ETH_TX_PARSE_BD_E1X_PSH_FLG_SHIFT 3 4796 #define ETH_TX_PARSE_BD_E1X_ACK_FLG (0x1<<4) /* BitField tcp_flagsState flags Acknowledgment number valid flag */ 4797 #define ETH_TX_PARSE_BD_E1X_ACK_FLG_SHIFT 4 4798 #define ETH_TX_PARSE_BD_E1X_URG_FLG (0x1<<5) /* BitField tcp_flagsState flags Urgent pointer valid flag */ 4799 #define ETH_TX_PARSE_BD_E1X_URG_FLG_SHIFT 5 4800 #define ETH_TX_PARSE_BD_E1X_ECE_FLG (0x1<<6) /* BitField tcp_flagsState flags ECN-Echo */ 4801 #define ETH_TX_PARSE_BD_E1X_ECE_FLG_SHIFT 6 4802 #define ETH_TX_PARSE_BD_E1X_CWR_FLG (0x1<<7) /* BitField tcp_flagsState flags Congestion Window Reduced */ 4803 #define ETH_TX_PARSE_BD_E1X_CWR_FLG_SHIFT 7 4804 uint8_t ip_hlen_w /* IP header length in WORDs */; 4805 uint16_t total_hlen_w /* IP+TCP+ETH */; 4806 uint16_t tcp_pseudo_csum /* Checksum of pseudo header with length field=0 */; 4807 uint16_t lso_mss /* for LSO mode */; 4808 uint16_t ip_id /* for LSO mode */; 4809 uint32_t tcp_send_seq /* for LSO mode */; 4810 }; 4811 4812 /* 4813 * Tx parsing BD structure for ETH E2 $$KEEP_ENDIANNESS$$ 4814 */ 4815 struct eth_tx_parse_bd_e2 4816 { 4817 union eth_mac_addr_or_tunnel_data data /* union for mac addresses and for tunneling data. considered as tunneling data only if (tunnel_exist == 1). */; 4818 uint32_t parsing_data; 4819 #define ETH_TX_PARSE_BD_E2_L4_HDR_START_OFFSET_W (0x7FF<<0) /* BitField parsing_data TCP/UDP header Offset in WORDs from start of packet */ 4820 #define ETH_TX_PARSE_BD_E2_L4_HDR_START_OFFSET_W_SHIFT 0 4821 #define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW (0xF<<11) /* BitField parsing_data TCP header size in DOUBLE WORDS */ 4822 #define ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW_SHIFT 11 4823 #define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR (0x1<<15) /* BitField parsing_data a flag to indicate an ipv6 packet with extension headers. If set on LSO packet, pseudo CS should be placed in TCP CS field without length field */ 4824 #define ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR_SHIFT 15 4825 #define ETH_TX_PARSE_BD_E2_LSO_MSS (0x3FFF<<16) /* BitField parsing_data for LSO mode */ 4826 #define ETH_TX_PARSE_BD_E2_LSO_MSS_SHIFT 16 4827 #define ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE (0x3<<30) /* BitField parsing_data marks ethernet address type (use enum eth_addr_type) */ 4828 #define ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE_SHIFT 30 4829 }; 4830 4831 /* 4832 * Tx 2nd parsing BD structure for ETH packet $$KEEP_ENDIANNESS$$ 4833 */ 4834 struct eth_tx_parse_2nd_bd 4835 { 4836 uint16_t global_data; 4837 #define ETH_TX_PARSE_2ND_BD_IP_HDR_START_OUTER_W (0xF<<0) /* BitField global_data Outer IP header offset in WORDs (16-bit) from start of packet */ 4838 #define ETH_TX_PARSE_2ND_BD_IP_HDR_START_OUTER_W_SHIFT 0 4839 #define ETH_TX_PARSE_2ND_BD_RESERVED0 (0x1<<4) /* BitField global_data should be set with 0 */ 4840 #define ETH_TX_PARSE_2ND_BD_RESERVED0_SHIFT 4 4841 #define ETH_TX_PARSE_2ND_BD_LLC_SNAP_EN (0x1<<5) /* BitField global_data */ 4842 #define ETH_TX_PARSE_2ND_BD_LLC_SNAP_EN_SHIFT 5 4843 #define ETH_TX_PARSE_2ND_BD_NS_FLG (0x1<<6) /* BitField global_data an optional addition to ECN that protects against accidental or malicious concealment of marked packets from the TCP sender. */ 4844 #define ETH_TX_PARSE_2ND_BD_NS_FLG_SHIFT 6 4845 #define ETH_TX_PARSE_2ND_BD_TUNNEL_UDP_EXIST (0x1<<7) /* BitField global_data Set in case UDP header exists in tunnel outer hedears. */ 4846 #define ETH_TX_PARSE_2ND_BD_TUNNEL_UDP_EXIST_SHIFT 7 4847 #define ETH_TX_PARSE_2ND_BD_IP_HDR_LEN_OUTER_W (0x1F<<8) /* BitField global_data Outer IP header length in WORDs (16-bit). Valid only for IpV4. */ 4848 #define ETH_TX_PARSE_2ND_BD_IP_HDR_LEN_OUTER_W_SHIFT 8 4849 #define ETH_TX_PARSE_2ND_BD_RESERVED1 (0x7<<13) /* BitField global_data should be set with 0 */ 4850 #define ETH_TX_PARSE_2ND_BD_RESERVED1_SHIFT 13 4851 uint16_t reserved2; 4852 uint8_t tcp_flags; 4853 #define ETH_TX_PARSE_2ND_BD_FIN_FLG (0x1<<0) /* BitField tcp_flagsState flags End of data flag */ 4854 #define ETH_TX_PARSE_2ND_BD_FIN_FLG_SHIFT 0 4855 #define ETH_TX_PARSE_2ND_BD_SYN_FLG (0x1<<1) /* BitField tcp_flagsState flags Synchronize sequence numbers flag */ 4856 #define ETH_TX_PARSE_2ND_BD_SYN_FLG_SHIFT 1 4857 #define ETH_TX_PARSE_2ND_BD_RST_FLG (0x1<<2) /* BitField tcp_flagsState flags Reset connection flag */ 4858 #define ETH_TX_PARSE_2ND_BD_RST_FLG_SHIFT 2 4859 #define ETH_TX_PARSE_2ND_BD_PSH_FLG (0x1<<3) /* BitField tcp_flagsState flags Push flag */ 4860 #define ETH_TX_PARSE_2ND_BD_PSH_FLG_SHIFT 3 4861 #define ETH_TX_PARSE_2ND_BD_ACK_FLG (0x1<<4) /* BitField tcp_flagsState flags Acknowledgment number valid flag */ 4862 #define ETH_TX_PARSE_2ND_BD_ACK_FLG_SHIFT 4 4863 #define ETH_TX_PARSE_2ND_BD_URG_FLG (0x1<<5) /* BitField tcp_flagsState flags Urgent pointer valid flag */ 4864 #define ETH_TX_PARSE_2ND_BD_URG_FLG_SHIFT 5 4865 #define ETH_TX_PARSE_2ND_BD_ECE_FLG (0x1<<6) /* BitField tcp_flagsState flags ECN-Echo */ 4866 #define ETH_TX_PARSE_2ND_BD_ECE_FLG_SHIFT 6 4867 #define ETH_TX_PARSE_2ND_BD_CWR_FLG (0x1<<7) /* BitField tcp_flagsState flags Congestion Window Reduced */ 4868 #define ETH_TX_PARSE_2ND_BD_CWR_FLG_SHIFT 7 4869 uint8_t reserved3; 4870 uint8_t tunnel_udp_hdr_start_w /* Offset (in WORDs) from start of packet to tunnel UDP header. (if exist) */; 4871 uint8_t fw_ip_hdr_to_payload_w /* In IpV4, the length (in WORDs) from the FW IpV4 header start to the payload start. In IpV6, the length (in WORDs) from the FW IpV6 header end to the payload start. However, if extension headers are included, their length is counted here as well. */; 4872 uint16_t fw_ip_csum_wo_len_flags_frag /* For the IP header which is set by the FW, the IP checksum without length, flags and fragment offset. */; 4873 uint16_t hw_ip_id /* The IP ID to be set by HW for LSO packets in tunnel mode. */; 4874 uint32_t tcp_send_seq /* The TCP sequence number for LSO packets. */; 4875 }; 4876 4877 /* 4878 * The last BD in the BD memory will hold a pointer to the next BD memory 4879 */ 4880 struct eth_tx_next_bd 4881 { 4882 uint32_t addr_lo /* Single continuous buffer low pointer */; 4883 uint32_t addr_hi /* Single continuous buffer high pointer */; 4884 uint8_t reserved[8] /* keeps same size as other eth tx bd types */; 4885 }; 4886 4887 /* 4888 * union for 4 Bd types 4889 */ 4890 union eth_tx_bd_types 4891 { 4892 struct eth_tx_start_bd start_bd /* the first bd in a packets */; 4893 struct eth_tx_bd reg_bd /* the common bd */; 4894 struct eth_tx_parse_bd_e1x parse_bd_e1x /* parsing info BD for e1/e1h */; 4895 struct eth_tx_parse_bd_e2 parse_bd_e2 /* parsing info BD for e2 */; 4896 struct eth_tx_parse_2nd_bd parse_2nd_bd /* 2nd parsing info BD */; 4897 struct eth_tx_next_bd next_bd /* Bd that contains the address of the next page */; 4898 }; 4899 4900 /* 4901 * array of 13 bds as appears in the eth xstorm context 4902 */ 4903 struct eth_tx_bds_array 4904 { 4905 union eth_tx_bd_types bds[13]; 4906 }; 4907 4908 4909 /* 4910 * VLAN mode on TX BDs 4911 */ 4912 enum eth_tx_vlan_type 4913 { 4914 X_ETH_NO_VLAN, 4915 X_ETH_OUTBAND_VLAN, 4916 X_ETH_INBAND_VLAN, 4917 X_ETH_FW_ADDED_VLAN /* Driver should not use this! */, 4918 MAX_ETH_TX_VLAN_TYPE}; 4919 4920 4921 /* 4922 * Ethernet VLAN filtering mode in E1x 4923 */ 4924 enum eth_vlan_filter_mode 4925 { 4926 ETH_VLAN_FILTER_ANY_VLAN /* Dont filter by vlan */, 4927 ETH_VLAN_FILTER_SPECIFIC_VLAN /* Only the vlan_id is allowed */, 4928 ETH_VLAN_FILTER_CLASSIFY /* Vlan will be added to CAM for classification */, 4929 MAX_ETH_VLAN_FILTER_MODE}; 4930 4931 4932 /* 4933 * MAC filtering configuration command header $$KEEP_ENDIANNESS$$ 4934 */ 4935 struct mac_configuration_hdr 4936 { 4937 uint8_t length /* number of entries valid in this command (6 bits) */; 4938 uint8_t offset /* offset of the first entry in the list */; 4939 uint16_t client_id /* the client id which this ramrod is sent on. 5b is used. */; 4940 uint32_t echo /* echo value to be sent to driver on event ring */; 4941 }; 4942 4943 /* 4944 * MAC address in list for ramrod $$KEEP_ENDIANNESS$$ 4945 */ 4946 struct mac_configuration_entry 4947 { 4948 uint16_t lsb_mac_addr /* 2 LSB of MAC address (should be given in big endien - driver should do hton to this number!!!) */; 4949 uint16_t middle_mac_addr /* 2 middle bytes of MAC address (should be given in big endien - driver should do hton to this number!!!) */; 4950 uint16_t msb_mac_addr /* 2 MSB of MAC address (should be given in big endien - driver should do hton to this number!!!) */; 4951 uint16_t vlan_id /* The inner vlan id (12b). Used either in vlan_in_cam for mac_valn pair or for vlan filtering */; 4952 uint8_t pf_id /* The pf id, for multi function mode */; 4953 uint8_t flags; 4954 #define MAC_CONFIGURATION_ENTRY_ACTION_TYPE (0x1<<0) /* BitField flags configures the action to be done in cam (used only is slow path handlers) (use enum set_mac_action_type) */ 4955 #define MAC_CONFIGURATION_ENTRY_ACTION_TYPE_SHIFT 0 4956 #define MAC_CONFIGURATION_ENTRY_RDMA_MAC (0x1<<1) /* BitField flags If set, this MAC also belongs to RDMA client */ 4957 #define MAC_CONFIGURATION_ENTRY_RDMA_MAC_SHIFT 1 4958 #define MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE (0x3<<2) /* BitField flags (use enum eth_vlan_filter_mode) */ 4959 #define MAC_CONFIGURATION_ENTRY_VLAN_FILTERING_MODE_SHIFT 2 4960 #define MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL (0x1<<4) /* BitField flags BitField flags 0 - cant remove vlan 1 - can remove vlan. relevant only to everest1 */ 4961 #define MAC_CONFIGURATION_ENTRY_OVERRIDE_VLAN_REMOVAL_SHIFT 4 4962 #define MAC_CONFIGURATION_ENTRY_BROADCAST (0x1<<5) /* BitField flags BitField flags 0 - not broadcast 1 - broadcast. relevant only to everest1 */ 4963 #define MAC_CONFIGURATION_ENTRY_BROADCAST_SHIFT 5 4964 #define MAC_CONFIGURATION_ENTRY_RESERVED1 (0x3<<6) /* BitField flags */ 4965 #define MAC_CONFIGURATION_ENTRY_RESERVED1_SHIFT 6 4966 uint16_t reserved0; 4967 uint32_t clients_bit_vector /* Bit vector for the clients which should receive this MAC. */; 4968 }; 4969 4970 /* 4971 * MAC filtering configuration command 4972 */ 4973 struct mac_configuration_cmd 4974 { 4975 struct mac_configuration_hdr hdr /* header */; 4976 struct mac_configuration_entry config_table[64] /* table of 64 MAC configuration entries: addresses and target table entries */; 4977 }; 4978 4979 4980 /* 4981 * Set-MAC command type (in E1x) 4982 */ 4983 enum set_mac_action_type 4984 { 4985 T_ETH_MAC_COMMAND_INVALIDATE, 4986 T_ETH_MAC_COMMAND_SET, 4987 MAX_SET_MAC_ACTION_TYPE}; 4988 4989 4990 /* 4991 * Ethernet TPA Modes 4992 */ 4993 enum tpa_mode 4994 { 4995 TPA_LRO /* LRO mode TPA */, 4996 TPA_GRO /* GRO mode TPA */, 4997 MAX_TPA_MODE}; 4998 4999 5000 /* 5001 * tpa update ramrod data $$KEEP_ENDIANNESS$$ 5002 */ 5003 struct tpa_update_ramrod_data 5004 { 5005 uint8_t update_ipv4 /* none, enable or disable */; 5006 uint8_t update_ipv6 /* none, enable or disable */; 5007 uint8_t client_id /* client init flow control data */; 5008 uint8_t max_tpa_queues /* maximal TPA queues allowed for this client */; 5009 uint8_t max_sges_for_packet /* The maximal number of SGEs that can be used for one packet. depends on MTU and SGE size. must be 0 if SGEs are disabled */; 5010 uint8_t complete_on_both_clients /* If set and the client has different sp_client, completion will be sent to both rings */; 5011 uint8_t dont_verify_rings_pause_thr_flg /* If set, the rings pause thresholds will not be verified by firmware. */; 5012 uint8_t tpa_mode /* TPA mode to use (LRO or GRO) */; 5013 uint16_t sge_buff_size /* Size of the buffers pointed by SGEs */; 5014 uint16_t max_agg_size /* maximal size for the aggregated TPA packets, reprted by the host */; 5015 uint32_t sge_page_base_lo /* The address to fetch the next sges from (low) */; 5016 uint32_t sge_page_base_hi /* The address to fetch the next sges from (high) */; 5017 uint16_t sge_pause_thr_low /* number of remaining sges under which, we send pause message */; 5018 uint16_t sge_pause_thr_high /* number of remaining sges above which, we send un-pause message */; 5019 }; 5020 5021 5022 /* 5023 * approximate-match multicast filtering for E1H per function in Tstorm 5024 */ 5025 struct tstorm_eth_approximate_match_multicast_filtering 5026 { 5027 uint32_t mcast_add_hash_bit_array[8] /* Bit array for multicast hash filtering.Each bit supports a hash function result if to accept this multicast dst address. */; 5028 }; 5029 5030 5031 /* 5032 * Common configuration parameters per function in Tstorm $$KEEP_ENDIANNESS$$ 5033 */ 5034 struct tstorm_eth_function_common_config 5035 { 5036 uint16_t config_flags; 5037 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY (0x1<<0) /* BitField config_flagsGeneral configuration flags configuration of the port RSS IpV4 2-tupple capability */ 5038 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_CAPABILITY_SHIFT 0 5039 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY (0x1<<1) /* BitField config_flagsGeneral configuration flags configuration of the port RSS IpV4 4-tupple capability */ 5040 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV4_TCP_CAPABILITY_SHIFT 1 5041 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY (0x1<<2) /* BitField config_flagsGeneral configuration flags configuration of the port RSS IpV4 2-tupple capability */ 5042 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_CAPABILITY_SHIFT 2 5043 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY (0x1<<3) /* BitField config_flagsGeneral configuration flags configuration of the port RSS IpV6 4-tupple capability */ 5044 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_IPV6_TCP_CAPABILITY_SHIFT 3 5045 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE (0x7<<4) /* BitField config_flagsGeneral configuration flags RSS mode of operation (use enum eth_rss_mode) */ 5046 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_RSS_MODE_SHIFT 4 5047 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE (0x1<<7) /* BitField config_flagsGeneral configuration flags 0 - Dont filter by vlan, 1 - Filter according to the vlans specificied in mac_filter_config */ 5048 #define TSTORM_ETH_FUNCTION_COMMON_CONFIG_VLAN_FILTERING_ENABLE_SHIFT 7 5049 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0 (0xFF<<8) /* BitField config_flagsGeneral configuration flags */ 5050 #define __TSTORM_ETH_FUNCTION_COMMON_CONFIG_RESERVED0_SHIFT 8 5051 uint8_t rss_result_mask /* The mask for the lower byte of RSS result - defines which section of the indirection table will be used. To enable all table put here 0x7F */; 5052 uint8_t reserved1; 5053 uint16_t vlan_id[2] /* VLANs of this function. VLAN filtering is determine according to vlan_filtering_enable. */; 5054 }; 5055 5056 5057 /* 5058 * MAC filtering configuration parameters per port in Tstorm $$KEEP_ENDIANNESS$$ 5059 */ 5060 struct tstorm_eth_mac_filter_config 5061 { 5062 uint32_t ucast_drop_all /* bit vector in which the clients which drop all unicast packets are set */; 5063 uint32_t ucast_accept_all /* bit vector in which clients that accept all unicast packets are set */; 5064 uint32_t mcast_drop_all /* bit vector in which the clients which drop all multicast packets are set */; 5065 uint32_t mcast_accept_all /* bit vector in which clients that accept all multicast packets are set */; 5066 uint32_t bcast_accept_all /* bit vector in which clients that accept all broadcast packets are set */; 5067 uint32_t vlan_filter[2] /* bit vector for VLAN filtering. Clients which enforce filtering of vlan[x] should be marked in vlan_filter[x]. In E1 only vlan_filter[1] is checked. The primary vlan is taken from the CAM target table. */; 5068 uint32_t unmatched_unicast /* bit vector in which clients that accept unmatched unicast packets are set */; 5069 }; 5070 5071 5072 /* 5073 * tx only queue init ramrod data $$KEEP_ENDIANNESS$$ 5074 */ 5075 struct tx_queue_init_ramrod_data 5076 { 5077 struct client_init_general_data general /* client init general data */; 5078 struct client_init_tx_data tx /* client init tx data */; 5079 }; 5080 5081 5082 /* 5083 * Three RX producers for ETH 5084 */ 5085 struct ustorm_eth_rx_producers 5086 { 5087 #if defined(__BIG_ENDIAN) 5088 uint16_t bd_prod /* Producer of the RX BD ring */; 5089 uint16_t cqe_prod /* Producer of the RX CQE ring */; 5090 #elif defined(__LITTLE_ENDIAN) 5091 uint16_t cqe_prod /* Producer of the RX CQE ring */; 5092 uint16_t bd_prod /* Producer of the RX BD ring */; 5093 #endif 5094 #if defined(__BIG_ENDIAN) 5095 uint16_t reserved; 5096 uint16_t sge_prod /* Producer of the RX SGE ring */; 5097 #elif defined(__LITTLE_ENDIAN) 5098 uint16_t sge_prod /* Producer of the RX SGE ring */; 5099 uint16_t reserved; 5100 #endif 5101 }; 5102 5103 5104 /* 5105 * The data afex vif list ramrod need $$KEEP_ENDIANNESS$$ 5106 */ 5107 struct afex_vif_list_ramrod_data 5108 { 5109 uint8_t afex_vif_list_command /* set get, clear all a VIF list id defined by enum vif_list_rule_kind */; 5110 uint8_t func_bit_map /* the function bit map to set */; 5111 uint16_t vif_list_index /* the VIF list, in a per pf vector to add this function to */; 5112 uint8_t func_to_clear /* the func id to clear in case of clear func mode */; 5113 uint8_t echo; 5114 uint16_t reserved1; 5115 }; 5116 5117 5118 /* 5119 * cfc delete event data $$KEEP_ENDIANNESS$$ 5120 */ 5121 struct cfc_del_event_data 5122 { 5123 uint32_t cid /* cid of deleted connection */; 5124 uint32_t reserved0; 5125 uint32_t reserved1; 5126 }; 5127 5128 5129 /* 5130 * per-port SAFC demo variables 5131 */ 5132 struct cmng_flags_per_port 5133 { 5134 uint32_t cmng_enables; 5135 #define CMNG_FLAGS_PER_PORT_FAIRNESS_VN (0x1<<0) /* BitField cmng_enablesenables flag for fairness and rate shaping between protocols, vnics and COSes if set, enable fairness between vnics */ 5136 #define CMNG_FLAGS_PER_PORT_FAIRNESS_VN_SHIFT 0 5137 #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN (0x1<<1) /* BitField cmng_enablesenables flag for fairness and rate shaping between protocols, vnics and COSes if set, enable rate shaping between vnics */ 5138 #define CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN_SHIFT 1 5139 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS (0x1<<2) /* BitField cmng_enablesenables flag for fairness and rate shaping between protocols, vnics and COSes if set, enable fairness between COSes */ 5140 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_SHIFT 2 5141 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE (0x1<<3) /* BitField cmng_enablesenables flag for fairness and rate shaping between protocols, vnics and COSes (use enum fairness_mode) */ 5142 #define CMNG_FLAGS_PER_PORT_FAIRNESS_COS_MODE_SHIFT 3 5143 #define __CMNG_FLAGS_PER_PORT_RESERVED0 (0xFFFFFFF<<4) /* BitField cmng_enablesenables flag for fairness and rate shaping between protocols, vnics and COSes reserved */ 5144 #define __CMNG_FLAGS_PER_PORT_RESERVED0_SHIFT 4 5145 uint32_t __reserved1; 5146 }; 5147 5148 5149 /* 5150 * per-port rate shaping variables 5151 */ 5152 struct rate_shaping_vars_per_port 5153 { 5154 uint32_t rs_periodic_timeout /* timeout of periodic timer */; 5155 uint32_t rs_threshold /* threshold, below which we start to stop queues */; 5156 }; 5157 5158 /* 5159 * per-port fairness variables 5160 */ 5161 struct fairness_vars_per_port 5162 { 5163 uint32_t upper_bound /* Quota for a protocol/vnic */; 5164 uint32_t fair_threshold /* almost-empty threshold */; 5165 uint32_t fairness_timeout /* timeout of fairness timer */; 5166 uint32_t reserved0; 5167 }; 5168 5169 /* 5170 * per-port SAFC variables 5171 */ 5172 struct safc_struct_per_port 5173 { 5174 #if defined(__BIG_ENDIAN) 5175 uint16_t __reserved1; 5176 uint8_t __reserved0; 5177 uint8_t safc_timeout_usec /* timeout to stop queues on SAFC pause command */; 5178 #elif defined(__LITTLE_ENDIAN) 5179 uint8_t safc_timeout_usec /* timeout to stop queues on SAFC pause command */; 5180 uint8_t __reserved0; 5181 uint16_t __reserved1; 5182 #endif 5183 uint8_t cos_to_traffic_types[MAX_COS_NUMBER] /* translate cos to service traffics types */; 5184 uint16_t cos_to_pause_mask[NUM_OF_SAFC_BITS] /* QM pause mask for each class of service in the SAFC frame */; 5185 }; 5186 5187 /* 5188 * Per-port congestion management variables 5189 */ 5190 struct cmng_struct_per_port 5191 { 5192 struct rate_shaping_vars_per_port rs_vars; 5193 struct fairness_vars_per_port fair_vars; 5194 struct safc_struct_per_port safc_vars; 5195 struct cmng_flags_per_port flags; 5196 }; 5197 5198 /* 5199 * a single rate shaping counter. can be used as protocol or vnic counter 5200 */ 5201 struct rate_shaping_counter 5202 { 5203 uint32_t quota /* Quota for a protocol/vnic */; 5204 #if defined(__BIG_ENDIAN) 5205 uint16_t __reserved0; 5206 uint16_t rate /* Vnic/Protocol rate in units of Mega-bits/sec */; 5207 #elif defined(__LITTLE_ENDIAN) 5208 uint16_t rate /* Vnic/Protocol rate in units of Mega-bits/sec */; 5209 uint16_t __reserved0; 5210 #endif 5211 }; 5212 5213 /* 5214 * per-vnic rate shaping variables 5215 */ 5216 struct rate_shaping_vars_per_vn 5217 { 5218 struct rate_shaping_counter vn_counter /* per-vnic counter */; 5219 }; 5220 5221 /* 5222 * per-vnic fairness variables 5223 */ 5224 struct fairness_vars_per_vn 5225 { 5226 uint32_t cos_credit_delta[MAX_COS_NUMBER] /* used for incrementing the credit */; 5227 uint32_t vn_credit_delta /* used for incrementing the credit */; 5228 uint32_t __reserved0; 5229 }; 5230 5231 /* 5232 * cmng port init state 5233 */ 5234 struct cmng_vnic 5235 { 5236 struct rate_shaping_vars_per_vn vnic_max_rate[4]; 5237 struct fairness_vars_per_vn vnic_min_rate[4]; 5238 }; 5239 5240 /* 5241 * cmng port init state 5242 */ 5243 struct cmng_init 5244 { 5245 struct cmng_struct_per_port port; 5246 struct cmng_vnic vnic; 5247 }; 5248 5249 5250 /* 5251 * driver parameters for congestion management init, all rates are in Mbps 5252 */ 5253 struct cmng_init_input 5254 { 5255 uint32_t port_rate; 5256 uint16_t vnic_min_rate[4] /* rates are in Mbps */; 5257 uint16_t vnic_max_rate[4] /* rates are in Mbps */; 5258 uint16_t cos_min_rate[MAX_COS_NUMBER] /* rates are in Mbps */; 5259 uint16_t cos_to_pause_mask[MAX_COS_NUMBER]; 5260 struct cmng_flags_per_port flags; 5261 }; 5262 5263 5264 /* 5265 * Protocol-common command ID for slow path elements 5266 */ 5267 enum common_spqe_cmd_id 5268 { 5269 RAMROD_CMD_ID_COMMON_UNUSED, 5270 RAMROD_CMD_ID_COMMON_FUNCTION_START /* Start a function (for PFs only) */, 5271 RAMROD_CMD_ID_COMMON_FUNCTION_STOP /* Stop a function (for PFs only) */, 5272 RAMROD_CMD_ID_COMMON_FUNCTION_UPDATE /* niv update function */, 5273 RAMROD_CMD_ID_COMMON_CFC_DEL /* Delete a connection from CFC */, 5274 RAMROD_CMD_ID_COMMON_CFC_DEL_WB /* Delete a connection from CFC (with write back) */, 5275 RAMROD_CMD_ID_COMMON_STAT_QUERY /* Collect statistics counters */, 5276 RAMROD_CMD_ID_COMMON_STOP_TRAFFIC /* Stop Tx traffic (before DCB updates) */, 5277 RAMROD_CMD_ID_COMMON_START_TRAFFIC /* Start Tx traffic (after DCB updates) */, 5278 RAMROD_CMD_ID_COMMON_AFEX_VIF_LISTS /* niv vif lists */, 5279 RAMROD_CMD_ID_COMMON_SET_TIMESYNC /* Set Timesync Parameters (E3 Only) */, 5280 MAX_COMMON_SPQE_CMD_ID}; 5281 5282 5283 /* 5284 * Per-protocol connection types 5285 */ 5286 enum connection_type 5287 { 5288 ETH_CONNECTION_TYPE /* Ethernet */, 5289 TOE_CONNECTION_TYPE /* TOE */, 5290 RDMA_CONNECTION_TYPE /* RDMA */, 5291 ISCSI_CONNECTION_TYPE /* iSCSI */, 5292 FCOE_CONNECTION_TYPE /* FCoE */, 5293 RESERVED_CONNECTION_TYPE_0, 5294 RESERVED_CONNECTION_TYPE_1, 5295 RESERVED_CONNECTION_TYPE_2, 5296 NONE_CONNECTION_TYPE /* General- used for common slow path */, 5297 MAX_CONNECTION_TYPE}; 5298 5299 5300 /* 5301 * Cos modes 5302 */ 5303 enum cos_mode 5304 { 5305 OVERRIDE_COS /* Firmware deduce cos according to DCB */, 5306 STATIC_COS /* Firmware has constant queues per CoS */, 5307 FW_WRR /* Firmware keep fairness between different CoSes */, 5308 MAX_COS_MODE}; 5309 5310 5311 /* 5312 * Dynamic HC counters set by the driver 5313 */ 5314 struct hc_dynamic_drv_counter 5315 { 5316 uint32_t val[HC_SB_MAX_DYNAMIC_INDICES] /* 4 bytes * 4 indices = 2 lines */; 5317 }; 5318 5319 /* 5320 * zone A per-queue data 5321 */ 5322 struct cstorm_queue_zone_data 5323 { 5324 struct hc_dynamic_drv_counter hc_dyn_drv_cnt /* 4 bytes * 4 indices = 2 lines */; 5325 struct regpair reserved[2]; 5326 }; 5327 5328 5329 /* 5330 * Vf-PF channel data in cstorm ram (non-triggered zone) 5331 */ 5332 struct vf_pf_channel_zone_data 5333 { 5334 uint32_t msg_addr_lo /* the message address on VF memory */; 5335 uint32_t msg_addr_hi /* the message address on VF memory */; 5336 }; 5337 5338 /* 5339 * zone for VF non-triggered data 5340 */ 5341 struct non_trigger_vf_zone 5342 { 5343 struct vf_pf_channel_zone_data vf_pf_channel /* vf-pf channel zone data */; 5344 }; 5345 5346 /* 5347 * Vf-PF channel trigger zone in cstorm ram 5348 */ 5349 struct vf_pf_channel_zone_trigger 5350 { 5351 uint8_t addr_valid /* indicates that a vf-pf message is pending. MUST be set AFTER the message address. */; 5352 }; 5353 5354 /* 5355 * zone that triggers the in-bound interrupt 5356 */ 5357 struct trigger_vf_zone 5358 { 5359 #if defined(__BIG_ENDIAN) 5360 uint16_t reserved1; 5361 uint8_t reserved0; 5362 struct vf_pf_channel_zone_trigger vf_pf_channel; 5363 #elif defined(__LITTLE_ENDIAN) 5364 struct vf_pf_channel_zone_trigger vf_pf_channel; 5365 uint8_t reserved0; 5366 uint16_t reserved1; 5367 #endif 5368 uint32_t reserved2; 5369 }; 5370 5371 /* 5372 * zone B per-VF data 5373 */ 5374 struct cstorm_vf_zone_data 5375 { 5376 struct non_trigger_vf_zone non_trigger /* zone for VF non-triggered data */; 5377 struct trigger_vf_zone trigger /* zone that triggers the in-bound interrupt */; 5378 }; 5379 5380 5381 /* 5382 * Dynamic host coalescing init parameters, per state machine 5383 */ 5384 struct dynamic_hc_sm_config 5385 { 5386 uint32_t threshold[3] /* thresholds of number of outstanding bytes */; 5387 uint8_t shift_per_protocol[HC_SB_MAX_DYNAMIC_INDICES] /* bytes difference of each protocol is shifted right by this value */; 5388 uint8_t hc_timeout0[HC_SB_MAX_DYNAMIC_INDICES] /* timeout for level 0 for each protocol, in units of usec */; 5389 uint8_t hc_timeout1[HC_SB_MAX_DYNAMIC_INDICES] /* timeout for level 1 for each protocol, in units of usec */; 5390 uint8_t hc_timeout2[HC_SB_MAX_DYNAMIC_INDICES] /* timeout for level 2 for each protocol, in units of usec */; 5391 uint8_t hc_timeout3[HC_SB_MAX_DYNAMIC_INDICES] /* timeout for level 3 for each protocol, in units of usec */; 5392 }; 5393 5394 /* 5395 * Dynamic host coalescing init parameters 5396 */ 5397 struct dynamic_hc_config 5398 { 5399 struct dynamic_hc_sm_config sm_config[HC_SB_MAX_SM] /* Configuration per state machine */; 5400 }; 5401 5402 5403 struct e2_integ_data 5404 { 5405 #if defined(__BIG_ENDIAN) 5406 uint8_t flags; 5407 #define E2_INTEG_DATA_TESTING_EN (0x1<<0) /* BitField flags integration testing enabled */ 5408 #define E2_INTEG_DATA_TESTING_EN_SHIFT 0 5409 #define E2_INTEG_DATA_LB_TX (0x1<<1) /* BitField flags flag indicating this connection will transmit on loopback */ 5410 #define E2_INTEG_DATA_LB_TX_SHIFT 1 5411 #define E2_INTEG_DATA_COS_TX (0x1<<2) /* BitField flags flag indicating this connection will transmit according to cos field */ 5412 #define E2_INTEG_DATA_COS_TX_SHIFT 2 5413 #define E2_INTEG_DATA_OPPORTUNISTICQM (0x1<<3) /* BitField flags flag indicating this connection will activate the opportunistic QM credit flow */ 5414 #define E2_INTEG_DATA_OPPORTUNISTICQM_SHIFT 3 5415 #define E2_INTEG_DATA_DPMTESTRELEASEDQ (0x1<<4) /* BitField flags flag indicating this connection will release the door bell queue (DQ) */ 5416 #define E2_INTEG_DATA_DPMTESTRELEASEDQ_SHIFT 4 5417 #define E2_INTEG_DATA_RESERVED (0x7<<5) /* BitField flags */ 5418 #define E2_INTEG_DATA_RESERVED_SHIFT 5 5419 uint8_t cos /* cos of the connection (relevant only in cos transmitting connections, when cosTx is set */; 5420 uint8_t voq /* voq to return credit on. Normally equal to port (i.e. always 0 in E2 operational connections). in cos tests equal to cos. in loopback tests equal to LB_PORT (=4) */; 5421 uint8_t pbf_queue /* pbf queue to transmit on. Normally equal to port (i.e. always 0 in E2 operational connections). in cos tests equal to cos. in loopback tests equal to LB_PORT (=4) */; 5422 #elif defined(__LITTLE_ENDIAN) 5423 uint8_t pbf_queue /* pbf queue to transmit on. Normally equal to port (i.e. always 0 in E2 operational connections). in cos tests equal to cos. in loopback tests equal to LB_PORT (=4) */; 5424 uint8_t voq /* voq to return credit on. Normally equal to port (i.e. always 0 in E2 operational connections). in cos tests equal to cos. in loopback tests equal to LB_PORT (=4) */; 5425 uint8_t cos /* cos of the connection (relevant only in cos transmitting connections, when cosTx is set */; 5426 uint8_t flags; 5427 #define E2_INTEG_DATA_TESTING_EN (0x1<<0) /* BitField flags integration testing enabled */ 5428 #define E2_INTEG_DATA_TESTING_EN_SHIFT 0 5429 #define E2_INTEG_DATA_LB_TX (0x1<<1) /* BitField flags flag indicating this connection will transmit on loopback */ 5430 #define E2_INTEG_DATA_LB_TX_SHIFT 1 5431 #define E2_INTEG_DATA_COS_TX (0x1<<2) /* BitField flags flag indicating this connection will transmit according to cos field */ 5432 #define E2_INTEG_DATA_COS_TX_SHIFT 2 5433 #define E2_INTEG_DATA_OPPORTUNISTICQM (0x1<<3) /* BitField flags flag indicating this connection will activate the opportunistic QM credit flow */ 5434 #define E2_INTEG_DATA_OPPORTUNISTICQM_SHIFT 3 5435 #define E2_INTEG_DATA_DPMTESTRELEASEDQ (0x1<<4) /* BitField flags flag indicating this connection will release the door bell queue (DQ) */ 5436 #define E2_INTEG_DATA_DPMTESTRELEASEDQ_SHIFT 4 5437 #define E2_INTEG_DATA_RESERVED (0x7<<5) /* BitField flags */ 5438 #define E2_INTEG_DATA_RESERVED_SHIFT 5 5439 #endif 5440 #if defined(__BIG_ENDIAN) 5441 uint16_t reserved3; 5442 uint8_t reserved2; 5443 uint8_t ramEn /* context area reserved for reading enable bit from ram */; 5444 #elif defined(__LITTLE_ENDIAN) 5445 uint8_t ramEn /* context area reserved for reading enable bit from ram */; 5446 uint8_t reserved2; 5447 uint16_t reserved3; 5448 #endif 5449 }; 5450 5451 5452 /* 5453 * set mac event data $$KEEP_ENDIANNESS$$ 5454 */ 5455 struct eth_event_data 5456 { 5457 uint32_t echo /* set mac echo data to return to driver */; 5458 uint32_t reserved0; 5459 uint32_t reserved1; 5460 }; 5461 5462 5463 /* 5464 * pf-vf event data $$KEEP_ENDIANNESS$$ 5465 */ 5466 struct vf_pf_event_data 5467 { 5468 uint8_t vf_id /* VF ID (0-63) */; 5469 uint8_t reserved0; 5470 uint16_t reserved1; 5471 uint32_t msg_addr_lo /* message address on Vf (low 32 bits) */; 5472 uint32_t msg_addr_hi /* message address on Vf (high 32 bits) */; 5473 }; 5474 5475 /* 5476 * VF FLR event data $$KEEP_ENDIANNESS$$ 5477 */ 5478 struct vf_flr_event_data 5479 { 5480 uint8_t vf_id /* VF ID (0-63) */; 5481 uint8_t reserved0; 5482 uint16_t reserved1; 5483 uint32_t reserved2; 5484 uint32_t reserved3; 5485 }; 5486 5487 /* 5488 * malicious VF event data $$KEEP_ENDIANNESS$$ 5489 */ 5490 struct malicious_vf_event_data 5491 { 5492 uint8_t vf_id /* VF ID (0-63) */; 5493 uint8_t err_id /* reason for malicious notification */; 5494 uint16_t reserved1; 5495 uint32_t reserved2; 5496 uint32_t reserved3; 5497 }; 5498 5499 /* 5500 * vif list event data $$KEEP_ENDIANNESS$$ 5501 */ 5502 struct vif_list_event_data 5503 { 5504 uint8_t func_bit_map /* bit map of pf indice */; 5505 uint8_t echo; 5506 uint16_t reserved0; 5507 uint32_t reserved1; 5508 uint32_t reserved2; 5509 }; 5510 5511 /* 5512 * function update event data $$KEEP_ENDIANNESS$$ 5513 */ 5514 struct function_update_event_data 5515 { 5516 uint8_t echo; 5517 uint8_t reserved; 5518 uint16_t reserved0; 5519 uint32_t reserved1; 5520 uint32_t reserved2; 5521 }; 5522 5523 /* 5524 * union for all event ring message types 5525 */ 5526 union event_data 5527 { 5528 struct vf_pf_event_data vf_pf_event /* vf-pf event data */; 5529 struct eth_event_data eth_event /* set mac event data */; 5530 struct cfc_del_event_data cfc_del_event /* cfc delete event data */; 5531 struct vf_flr_event_data vf_flr_event /* vf flr event data */; 5532 struct malicious_vf_event_data malicious_vf_event /* malicious vf event data */; 5533 struct vif_list_event_data vif_list_event /* vif list event data */; 5534 struct function_update_event_data function_update_event /* function update event data */; 5535 }; 5536 5537 5538 /* 5539 * per PF event ring data 5540 */ 5541 struct event_ring_data 5542 { 5543 struct regpair_native base_addr /* ring base address */; 5544 #if defined(__BIG_ENDIAN) 5545 uint8_t index_id /* index ID within the status block */; 5546 uint8_t sb_id /* status block ID */; 5547 uint16_t producer /* event ring producer */; 5548 #elif defined(__LITTLE_ENDIAN) 5549 uint16_t producer /* event ring producer */; 5550 uint8_t sb_id /* status block ID */; 5551 uint8_t index_id /* index ID within the status block */; 5552 #endif 5553 uint32_t reserved0; 5554 }; 5555 5556 5557 /* 5558 * event ring message element (each element is 128 bits) $$KEEP_ENDIANNESS$$ 5559 */ 5560 struct event_ring_msg 5561 { 5562 uint8_t opcode; 5563 uint8_t error /* error on the mesasage */; 5564 uint16_t reserved1; 5565 union event_data data /* message data (96 bits data) */; 5566 }; 5567 5568 /* 5569 * event ring next page element (128 bits) 5570 */ 5571 struct event_ring_next 5572 { 5573 struct regpair addr /* Address of the next page of the ring */; 5574 uint32_t reserved[2]; 5575 }; 5576 5577 /* 5578 * union for event ring element types (each element is 128 bits) 5579 */ 5580 union event_ring_elem 5581 { 5582 struct event_ring_msg message /* event ring message */; 5583 struct event_ring_next next_page /* event ring next page */; 5584 }; 5585 5586 5587 /* 5588 * Common event ring opcodes 5589 */ 5590 enum event_ring_opcode 5591 { 5592 EVENT_RING_OPCODE_VF_PF_CHANNEL, 5593 EVENT_RING_OPCODE_FUNCTION_START /* Start a function (for PFs only) */, 5594 EVENT_RING_OPCODE_FUNCTION_STOP /* Stop a function (for PFs only) */, 5595 EVENT_RING_OPCODE_CFC_DEL /* Delete a connection from CFC */, 5596 EVENT_RING_OPCODE_CFC_DEL_WB /* Delete a connection from CFC (with write back) */, 5597 EVENT_RING_OPCODE_STAT_QUERY /* Collect statistics counters */, 5598 EVENT_RING_OPCODE_STOP_TRAFFIC /* Stop Tx traffic (before DCB updates) */, 5599 EVENT_RING_OPCODE_START_TRAFFIC /* Start Tx traffic (after DCB updates) */, 5600 EVENT_RING_OPCODE_VF_FLR /* VF FLR indication for PF */, 5601 EVENT_RING_OPCODE_MALICIOUS_VF /* Malicious VF operation detected */, 5602 EVENT_RING_OPCODE_FORWARD_SETUP /* Initialize forward channel */, 5603 EVENT_RING_OPCODE_RSS_UPDATE_RULES /* Update RSS configuration */, 5604 EVENT_RING_OPCODE_FUNCTION_UPDATE /* function update */, 5605 EVENT_RING_OPCODE_AFEX_VIF_LISTS /* event ring opcode niv vif lists */, 5606 EVENT_RING_OPCODE_SET_MAC /* Add/remove MAC (in E1x only) */, 5607 EVENT_RING_OPCODE_CLASSIFICATION_RULES /* Add/remove MAC or VLAN (in E2/E3 only) */, 5608 EVENT_RING_OPCODE_FILTERS_RULES /* Add/remove classification filters for L2 client (in E2/E3 only) */, 5609 EVENT_RING_OPCODE_MULTICAST_RULES /* Add/remove multicast classification bin (in E2/E3 only) */, 5610 EVENT_RING_OPCODE_SET_TIMESYNC /* Set Timesync Parameters (E3 Only) */, 5611 MAX_EVENT_RING_OPCODE}; 5612 5613 5614 /* 5615 * Modes for fairness algorithm 5616 */ 5617 enum fairness_mode 5618 { 5619 FAIRNESS_COS_WRR_MODE /* Weighted round robin mode (used in Google) */, 5620 FAIRNESS_COS_ETS_MODE /* ETS mode (used in FCoE) */, 5621 MAX_FAIRNESS_MODE}; 5622 5623 5624 /* 5625 * Priority and cos $$KEEP_ENDIANNESS$$ 5626 */ 5627 struct priority_cos 5628 { 5629 uint8_t priority /* Priority */; 5630 uint8_t cos /* Cos */; 5631 uint16_t reserved1; 5632 }; 5633 5634 /* 5635 * The data for flow control configuration $$KEEP_ENDIANNESS$$ 5636 */ 5637 struct flow_control_configuration 5638 { 5639 struct priority_cos traffic_type_to_priority_cos[MAX_TRAFFIC_TYPES] /* traffic_type to priority cos */; 5640 uint8_t dcb_enabled /* If DCB mode is enabled then traffic class to priority array is fully initialized and there must be inner VLAN */; 5641 uint8_t dcb_version /* DCB version Increase by one on each DCB update */; 5642 uint8_t dont_add_pri_0 /* In case, the priority is 0, and the packet has no vlan, the firmware wont add vlan */; 5643 uint8_t reserved1; 5644 uint32_t reserved2; 5645 }; 5646 5647 5648 /* 5649 * $$KEEP_ENDIANNESS$$ 5650 */ 5651 struct function_start_data 5652 { 5653 uint8_t function_mode /* the function mode */; 5654 uint8_t allow_npar_tx_switching /* If set, inter-pf tx switching is allowed in Switch Independant function mode. (E2/E3 Only) */; 5655 uint16_t sd_vlan_tag /* value of Vlan in case of switch depended multi-function mode */; 5656 uint16_t vif_id /* value of VIF id in case of NIV multi-function mode */; 5657 uint8_t path_id; 5658 uint8_t network_cos_mode /* The cos mode for network traffic. */; 5659 uint8_t dmae_cmd_id /* The DMAE command id to use for FW DMAE transactions */; 5660 uint8_t gre_tunnel_mode /* GRE Tunnel Mode to enable on the Function (E2/E3 Only) */; 5661 uint8_t gre_tunnel_rss /* Type of RSS to perform on GRE Tunneled packets */; 5662 uint8_t nvgre_clss_en /* If set, NVGRE tunneled packets are classified according to their inner MAC (gre_mode must be NVGRE_TUNNEL) */; 5663 uint16_t reserved1[2]; 5664 }; 5665 5666 5667 /* 5668 * $$KEEP_ENDIANNESS$$ 5669 */ 5670 struct function_update_data 5671 { 5672 uint8_t vif_id_change_flg /* If set, vif_id will be checked */; 5673 uint8_t afex_default_vlan_change_flg /* If set, afex_default_vlan will be checked */; 5674 uint8_t allowed_priorities_change_flg /* If set, allowed_priorities will be checked */; 5675 uint8_t network_cos_mode_change_flg /* If set, network_cos_mode will be checked */; 5676 uint16_t vif_id /* value of VIF id in case of NIV multi-function mode */; 5677 uint16_t afex_default_vlan /* value of default Vlan in case of NIV mf */; 5678 uint8_t allowed_priorities /* bit vector of allowed Vlan priorities for this VIF */; 5679 uint8_t network_cos_mode /* The cos mode for network traffic. */; 5680 uint8_t lb_mode_en_change_flg /* If set, lb_mode_en will be checked */; 5681 uint8_t lb_mode_en /* If set, niv loopback mode will be enabled */; 5682 uint8_t tx_switch_suspend_change_flg /* If set, tx_switch_suspend will be checked */; 5683 uint8_t tx_switch_suspend /* If set, TX switching TO this function will be disabled and packets will be dropped */; 5684 uint8_t echo; 5685 uint8_t reserved1; 5686 uint8_t update_gre_cfg_flg /* If set, GRE config for the function will be updated according to the gre_tunnel_rss and nvgre_clss_en fields */; 5687 uint8_t gre_tunnel_mode /* GRE Tunnel Mode to enable on the Function (E2/E3 Only) */; 5688 uint8_t gre_tunnel_rss /* Type of RSS to perform on GRE Tunneled packets */; 5689 uint8_t nvgre_clss_en /* If set, NVGRE tunneled packets are classified according to their inner MAC (gre_mode must be NVGRE_TUNNEL) */; 5690 uint32_t reserved3; 5691 }; 5692 5693 5694 /* 5695 * FW version stored in the Xstorm RAM 5696 */ 5697 struct fw_version 5698 { 5699 #if defined(__BIG_ENDIAN) 5700 uint8_t engineering /* firmware current engineering version */; 5701 uint8_t revision /* firmware current revision version */; 5702 uint8_t minor /* firmware current minor version */; 5703 uint8_t major /* firmware current major version */; 5704 #elif defined(__LITTLE_ENDIAN) 5705 uint8_t major /* firmware current major version */; 5706 uint8_t minor /* firmware current minor version */; 5707 uint8_t revision /* firmware current revision version */; 5708 uint8_t engineering /* firmware current engineering version */; 5709 #endif 5710 uint32_t flags; 5711 #define FW_VERSION_OPTIMIZED (0x1<<0) /* BitField flags if set, this is optimized ASM */ 5712 #define FW_VERSION_OPTIMIZED_SHIFT 0 5713 #define FW_VERSION_BIG_ENDIEN (0x1<<1) /* BitField flags if set, this is big-endien ASM */ 5714 #define FW_VERSION_BIG_ENDIEN_SHIFT 1 5715 #define FW_VERSION_CHIP_VERSION (0x3<<2) /* BitField flags 0 - E1, 1 - E1H */ 5716 #define FW_VERSION_CHIP_VERSION_SHIFT 2 5717 #define __FW_VERSION_RESERVED (0xFFFFFFF<<4) /* BitField flags */ 5718 #define __FW_VERSION_RESERVED_SHIFT 4 5719 }; 5720 5721 5722 /* 5723 * GRE RSS Mode 5724 */ 5725 enum gre_rss_mode 5726 { 5727 GRE_OUTER_HEADERS_RSS /* RSS for GRE Packets is performed on the outer headers */, 5728 GRE_INNER_HEADERS_RSS /* RSS for GRE Packets is performed on the inner headers */, 5729 NVGRE_KEY_ENTROPY_RSS /* RSS for NVGRE Packets is done based on a hash containing the entropy bits from the GRE Key Field (gre_tunnel must be NVGRE_TUNNEL) */, 5730 MAX_GRE_RSS_MODE}; 5731 5732 5733 /* 5734 * GRE Tunnel Mode 5735 */ 5736 enum gre_tunnel_type 5737 { 5738 NO_GRE_TUNNEL, 5739 NVGRE_TUNNEL /* NV-GRE Tunneling Microsoft L2 over GRE. GRE header contains mandatory Key Field. */, 5740 L2GRE_TUNNEL /* L2-GRE Tunneling General L2 over GRE. GRE can contain Key field with Tenant ID and Sequence Field */, 5741 IPGRE_TUNNEL /* IP-GRE Tunneling IP over GRE. GRE may contain Key field with Tenant ID, Sequence Field and/or Checksum Field */, 5742 MAX_GRE_TUNNEL_TYPE}; 5743 5744 5745 /* 5746 * Dynamic Host-Coalescing - Driver(host) counters 5747 */ 5748 struct hc_dynamic_sb_drv_counters 5749 { 5750 uint32_t dynamic_hc_drv_counter[HC_SB_MAX_DYNAMIC_INDICES] /* Dynamic HC counters written by drivers */; 5751 }; 5752 5753 5754 /* 5755 * 2 bytes. configuration/state parameters for a single protocol index 5756 */ 5757 struct hc_index_data 5758 { 5759 #if defined(__BIG_ENDIAN) 5760 uint8_t flags; 5761 #define HC_INDEX_DATA_SM_ID (0x1<<0) /* BitField flags Index to a state machine. Can be 0 or 1 */ 5762 #define HC_INDEX_DATA_SM_ID_SHIFT 0 5763 #define HC_INDEX_DATA_HC_ENABLED (0x1<<1) /* BitField flags if set, host coalescing would be done for this index */ 5764 #define HC_INDEX_DATA_HC_ENABLED_SHIFT 1 5765 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1<<2) /* BitField flags if set, dynamic HC will be done for this index */ 5766 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED_SHIFT 2 5767 #define HC_INDEX_DATA_RESERVE (0x1F<<3) /* BitField flags */ 5768 #define HC_INDEX_DATA_RESERVE_SHIFT 3 5769 uint8_t timeout /* the timeout values for this index. Units are 4 usec */; 5770 #elif defined(__LITTLE_ENDIAN) 5771 uint8_t timeout /* the timeout values for this index. Units are 4 usec */; 5772 uint8_t flags; 5773 #define HC_INDEX_DATA_SM_ID (0x1<<0) /* BitField flags Index to a state machine. Can be 0 or 1 */ 5774 #define HC_INDEX_DATA_SM_ID_SHIFT 0 5775 #define HC_INDEX_DATA_HC_ENABLED (0x1<<1) /* BitField flags if set, host coalescing would be done for this index */ 5776 #define HC_INDEX_DATA_HC_ENABLED_SHIFT 1 5777 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED (0x1<<2) /* BitField flags if set, dynamic HC will be done for this index */ 5778 #define HC_INDEX_DATA_DYNAMIC_HC_ENABLED_SHIFT 2 5779 #define HC_INDEX_DATA_RESERVE (0x1F<<3) /* BitField flags */ 5780 #define HC_INDEX_DATA_RESERVE_SHIFT 3 5781 #endif 5782 }; 5783 5784 5785 /* 5786 * HC state-machine 5787 */ 5788 struct hc_status_block_sm 5789 { 5790 #if defined(__BIG_ENDIAN) 5791 uint8_t igu_seg_id; 5792 uint8_t igu_sb_id /* sb_id within the IGU */; 5793 uint8_t timer_value /* Determines the time_to_expire */; 5794 uint8_t __flags; 5795 #elif defined(__LITTLE_ENDIAN) 5796 uint8_t __flags; 5797 uint8_t timer_value /* Determines the time_to_expire */; 5798 uint8_t igu_sb_id /* sb_id within the IGU */; 5799 uint8_t igu_seg_id; 5800 #endif 5801 uint32_t time_to_expire /* The time in which it expects to wake up */; 5802 }; 5803 5804 /* 5805 * hold PCI identification variables- used in various places in firmware 5806 */ 5807 struct pci_entity 5808 { 5809 #if defined(__BIG_ENDIAN) 5810 uint8_t vf_valid /* If set, this is a VF, otherwise it is PF */; 5811 uint8_t vf_id /* VF ID (0-63). Value of 0xFF means VF not valid */; 5812 uint8_t vnic_id /* Virtual NIC ID (0-3) */; 5813 uint8_t pf_id /* PCI physical function number (0-7). The LSB of this field is the port ID */; 5814 #elif defined(__LITTLE_ENDIAN) 5815 uint8_t pf_id /* PCI physical function number (0-7). The LSB of this field is the port ID */; 5816 uint8_t vnic_id /* Virtual NIC ID (0-3) */; 5817 uint8_t vf_id /* VF ID (0-63). Value of 0xFF means VF not valid */; 5818 uint8_t vf_valid /* If set, this is a VF, otherwise it is PF */; 5819 #endif 5820 }; 5821 5822 /* 5823 * The fast-path status block meta-data, common to all chips 5824 */ 5825 struct hc_sb_data 5826 { 5827 struct regpair_native host_sb_addr /* Host status block address */; 5828 struct hc_status_block_sm state_machine[HC_SB_MAX_SM] /* Holds the state machines of the status block */; 5829 struct pci_entity p_func /* vnic / port of the status block to be set by the driver */; 5830 #if defined(__BIG_ENDIAN) 5831 uint8_t rsrv0; 5832 uint8_t state; 5833 uint8_t dhc_qzone_id /* used in E2 only, to specify the HW queue zone ID used for this status block dynamic HC counters */; 5834 uint8_t same_igu_sb_1b /* Indicate that both state-machines acts like single sm */; 5835 #elif defined(__LITTLE_ENDIAN) 5836 uint8_t same_igu_sb_1b /* Indicate that both state-machines acts like single sm */; 5837 uint8_t dhc_qzone_id /* used in E2 only, to specify the HW queue zone ID used for this status block dynamic HC counters */; 5838 uint8_t state; 5839 uint8_t rsrv0; 5840 #endif 5841 struct regpair_native rsrv1[2]; 5842 }; 5843 5844 5845 /* 5846 * Segment types for host coaslescing 5847 */ 5848 enum hc_segment 5849 { 5850 HC_REGULAR_SEGMENT, 5851 HC_DEFAULT_SEGMENT, 5852 MAX_HC_SEGMENT}; 5853 5854 5855 /* 5856 * The fast-path status block meta-data 5857 */ 5858 struct hc_sp_status_block_data 5859 { 5860 struct regpair_native host_sb_addr /* Host status block address */; 5861 #if defined(__BIG_ENDIAN) 5862 uint8_t rsrv1; 5863 uint8_t state; 5864 uint8_t igu_seg_id /* segment id of the IGU */; 5865 uint8_t igu_sb_id /* sb_id within the IGU */; 5866 #elif defined(__LITTLE_ENDIAN) 5867 uint8_t igu_sb_id /* sb_id within the IGU */; 5868 uint8_t igu_seg_id /* segment id of the IGU */; 5869 uint8_t state; 5870 uint8_t rsrv1; 5871 #endif 5872 struct pci_entity p_func /* vnic / port of the status block to be set by the driver */; 5873 }; 5874 5875 5876 /* 5877 * The fast-path status block meta-data 5878 */ 5879 struct hc_status_block_data_e1x 5880 { 5881 struct hc_index_data index_data[HC_SB_MAX_INDICES_E1X] /* configuration/state parameters for a single protocol index */; 5882 struct hc_sb_data common /* The fast-path status block meta-data, common to all chips */; 5883 }; 5884 5885 5886 /* 5887 * The fast-path status block meta-data 5888 */ 5889 struct hc_status_block_data_e2 5890 { 5891 struct hc_index_data index_data[HC_SB_MAX_INDICES_E2] /* configuration/state parameters for a single protocol index */; 5892 struct hc_sb_data common /* The fast-path status block meta-data, common to all chips */; 5893 }; 5894 5895 5896 /* 5897 * IGU block operartion modes (in Everest2) 5898 */ 5899 enum igu_mode 5900 { 5901 HC_IGU_BC_MODE /* Backward compatible mode */, 5902 HC_IGU_NBC_MODE /* Non-backward compatible mode */, 5903 MAX_IGU_MODE}; 5904 5905 5906 /* 5907 * IP versions 5908 */ 5909 enum ip_ver 5910 { 5911 IP_V4, 5912 IP_V6, 5913 MAX_IP_VER}; 5914 5915 5916 /* 5917 * Malicious VF error ID 5918 */ 5919 enum malicious_vf_error_id 5920 { 5921 VF_PF_CHANNEL_NOT_READY /* Writing to VF/PF channel when it is not ready */, 5922 ETH_ILLEGAL_BD_LENGTHS /* TX BD lengths error was detected */, 5923 ETH_PACKET_TOO_SHORT /* TX packet is shorter then reported on BDs */, 5924 ETH_PAYLOAD_TOO_BIG /* TX packet is greater then MTU */, 5925 ETH_ILLEGAL_ETH_TYPE /* TX packet reported without VLAN but eth type is 0x8100 */, 5926 ETH_ILLEGAL_LSO_HDR_LEN /* LSO header length on BDs and on hdr_nbd do not match */, 5927 ETH_TOO_MANY_BDS /* Tx packet has too many BDs */, 5928 ETH_ZERO_HDR_NBDS /* hdr_nbds field is zero */, 5929 ETH_START_BD_NOT_SET /* start_bd should be set on first TX BD in packet */, 5930 ETH_ILLEGAL_PARSE_NBDS /* Tx packet with parse_nbds field which is not legal */, 5931 ETH_IPV6_AND_CHECKSUM /* Tx packet with IP checksum on IPv6 */, 5932 ETH_VLAN_FLG_INCORRECT /* Tx packet with incorrect VLAN flag */, 5933 ETH_ILLEGAL_LSO_MSS /* Tx LSO packet with illegal MSS value */, 5934 ETH_TUNNEL_NOT_SUPPORTED /* Tunneling packets are not supported in current connection */, 5935 MAX_MALICIOUS_VF_ERROR_ID}; 5936 5937 5938 /* 5939 * Multi-function modes 5940 */ 5941 enum mf_mode 5942 { 5943 SINGLE_FUNCTION, 5944 MULTI_FUNCTION_SD /* Switch dependent (vlan based) */, 5945 MULTI_FUNCTION_SI /* Switch independent (mac based) */, 5946 MULTI_FUNCTION_AFEX /* Switch dependent (niv based) */, 5947 MAX_MF_MODE}; 5948 5949 5950 /* 5951 * Protocol-common statistics collected by the Tstorm (per pf) $$KEEP_ENDIANNESS$$ 5952 */ 5953 struct tstorm_per_pf_stats 5954 { 5955 struct regpair rcv_error_bytes /* number of bytes received with errors */; 5956 }; 5957 5958 /* 5959 * $$KEEP_ENDIANNESS$$ 5960 */ 5961 struct per_pf_stats 5962 { 5963 struct tstorm_per_pf_stats tstorm_pf_statistics; 5964 }; 5965 5966 5967 /* 5968 * Protocol-common statistics collected by the Tstorm (per port) $$KEEP_ENDIANNESS$$ 5969 */ 5970 struct tstorm_per_port_stats 5971 { 5972 uint32_t mac_discard /* number of packets with mac errors */; 5973 uint32_t mac_filter_discard /* the number of good frames dropped because of no perfect match to MAC/VLAN address */; 5974 uint32_t brb_truncate_discard /* the number of packtes that were dropped because they were truncated in BRB */; 5975 uint32_t mf_tag_discard /* the number of good frames dropped because of no match to the outer vlan/VNtag */; 5976 uint32_t packet_drop /* general packet drop conter- incremented for every packet drop */; 5977 uint32_t reserved; 5978 }; 5979 5980 /* 5981 * $$KEEP_ENDIANNESS$$ 5982 */ 5983 struct per_port_stats 5984 { 5985 struct tstorm_per_port_stats tstorm_port_statistics; 5986 }; 5987 5988 5989 /* 5990 * Protocol-common statistics collected by the Tstorm (per client) $$KEEP_ENDIANNESS$$ 5991 */ 5992 struct tstorm_per_queue_stats 5993 { 5994 struct regpair rcv_ucast_bytes /* number of bytes in unicast packets received without errors and pass the filter */; 5995 uint32_t rcv_ucast_pkts /* number of unicast packets received without errors and pass the filter */; 5996 uint32_t checksum_discard /* number of total packets received with checksum error */; 5997 struct regpair rcv_bcast_bytes /* number of bytes in broadcast packets received without errors and pass the filter */; 5998 uint32_t rcv_bcast_pkts /* number of packets in broadcast packets received without errors and pass the filter */; 5999 uint32_t pkts_too_big_discard /* number of too long packets received */; 6000 struct regpair rcv_mcast_bytes /* number of bytes in multicast packets received without errors and pass the filter */; 6001 uint32_t rcv_mcast_pkts /* number of packets in multicast packets received without errors and pass the filter */; 6002 uint32_t ttl0_discard /* the number of good frames dropped because of TTL=0 */; 6003 uint16_t no_buff_discard; 6004 uint16_t reserved0; 6005 uint32_t reserved1; 6006 }; 6007 6008 /* 6009 * Protocol-common statistics collected by the Ustorm (per client) $$KEEP_ENDIANNESS$$ 6010 */ 6011 struct ustorm_per_queue_stats 6012 { 6013 struct regpair ucast_no_buff_bytes /* the number of unicast bytes received from network dropped because of no buffer at host */; 6014 struct regpair mcast_no_buff_bytes /* the number of multicast bytes received from network dropped because of no buffer at host */; 6015 struct regpair bcast_no_buff_bytes /* the number of broadcast bytes received from network dropped because of no buffer at host */; 6016 uint32_t ucast_no_buff_pkts /* the number of unicast frames received from network dropped because of no buffer at host */; 6017 uint32_t mcast_no_buff_pkts /* the number of unicast frames received from network dropped because of no buffer at host */; 6018 uint32_t bcast_no_buff_pkts /* the number of unicast frames received from network dropped because of no buffer at host */; 6019 uint32_t coalesced_pkts /* the number of packets coalesced in all aggregations */; 6020 struct regpair coalesced_bytes /* the number of bytes coalesced in all aggregations */; 6021 uint32_t coalesced_events /* the number of aggregations */; 6022 uint32_t coalesced_aborts /* the number of exception which avoid aggregation */; 6023 }; 6024 6025 /* 6026 * Protocol-common statistics collected by the Xstorm (per client) $$KEEP_ENDIANNESS$$ 6027 */ 6028 struct xstorm_per_queue_stats 6029 { 6030 struct regpair ucast_bytes_sent /* number of total bytes sent without errors */; 6031 struct regpair mcast_bytes_sent /* number of total bytes sent without errors */; 6032 struct regpair bcast_bytes_sent /* number of total bytes sent without errors */; 6033 uint32_t ucast_pkts_sent /* number of total packets sent without errors */; 6034 uint32_t mcast_pkts_sent /* number of total packets sent without errors */; 6035 uint32_t bcast_pkts_sent /* number of total packets sent without errors */; 6036 uint32_t error_drop_pkts /* number of total packets drooped due to errors */; 6037 }; 6038 6039 /* 6040 * $$KEEP_ENDIANNESS$$ 6041 */ 6042 struct per_queue_stats 6043 { 6044 struct tstorm_per_queue_stats tstorm_queue_statistics; 6045 struct ustorm_per_queue_stats ustorm_queue_statistics; 6046 struct xstorm_per_queue_stats xstorm_queue_statistics; 6047 }; 6048 6049 6050 /* 6051 * FW version stored in first line of pram $$KEEP_ENDIANNESS$$ 6052 */ 6053 struct pram_fw_version 6054 { 6055 uint8_t major /* firmware current major version */; 6056 uint8_t minor /* firmware current minor version */; 6057 uint8_t revision /* firmware current revision version */; 6058 uint8_t engineering /* firmware current engineering version */; 6059 uint8_t flags; 6060 #define PRAM_FW_VERSION_OPTIMIZED (0x1<<0) /* BitField flags if set, this is optimized ASM */ 6061 #define PRAM_FW_VERSION_OPTIMIZED_SHIFT 0 6062 #define PRAM_FW_VERSION_STORM_ID (0x3<<1) /* BitField flags storm_id identification */ 6063 #define PRAM_FW_VERSION_STORM_ID_SHIFT 1 6064 #define PRAM_FW_VERSION_BIG_ENDIEN (0x1<<3) /* BitField flags if set, this is big-endien ASM */ 6065 #define PRAM_FW_VERSION_BIG_ENDIEN_SHIFT 3 6066 #define PRAM_FW_VERSION_CHIP_VERSION (0x3<<4) /* BitField flags 0 - E1, 1 - E1H */ 6067 #define PRAM_FW_VERSION_CHIP_VERSION_SHIFT 4 6068 #define __PRAM_FW_VERSION_RESERVED0 (0x3<<6) /* BitField flags */ 6069 #define __PRAM_FW_VERSION_RESERVED0_SHIFT 6 6070 }; 6071 6072 6073 /* 6074 * Ethernet slow path element 6075 */ 6076 union protocol_common_specific_data 6077 { 6078 uint8_t protocol_data[8] /* to fix this structure size to 8 bytes */; 6079 struct regpair phy_address /* SPE physical address */; 6080 struct regpair mac_config_addr /* physical address of the MAC configuration command, as allocated by the driver */; 6081 struct afex_vif_list_ramrod_data afex_vif_list_data /* The data afex vif list ramrod need */; 6082 }; 6083 6084 /* 6085 * The send queue element 6086 */ 6087 struct protocol_common_spe 6088 { 6089 struct spe_hdr hdr /* SPE header */; 6090 union protocol_common_specific_data data /* data specific to common protocol */; 6091 }; 6092 6093 6094 /* 6095 * The data for the Set Timesync Ramrod $$KEEP_ENDIANNESS$$ 6096 */ 6097 struct set_timesync_ramrod_data 6098 { 6099 uint8_t drift_adjust_cmd /* Timesync Drift Adjust Command */; 6100 uint8_t offset_cmd /* Timesync Offset Command */; 6101 uint8_t add_sub_drift_adjust_value /* Whether to add(1)/subtract(0) Drift Adjust Value from the Offset */; 6102 uint8_t drift_adjust_value /* Drift Adjust Value (in ns) */; 6103 uint32_t drift_adjust_period /* Drift Adjust Period (in us) */; 6104 struct regpair offset_delta /* Timesync Offset Delta (in ns) */; 6105 }; 6106 6107 6108 /* 6109 * The send queue element 6110 */ 6111 struct slow_path_element 6112 { 6113 struct spe_hdr hdr /* common data for all protocols */; 6114 struct regpair protocol_data /* additional data specific to the protocol */; 6115 }; 6116 6117 6118 /* 6119 * Protocol-common statistics counter $$KEEP_ENDIANNESS$$ 6120 */ 6121 struct stats_counter 6122 { 6123 uint16_t xstats_counter /* xstorm statistics counter */; 6124 uint16_t reserved0; 6125 uint32_t reserved1; 6126 uint16_t tstats_counter /* tstorm statistics counter */; 6127 uint16_t reserved2; 6128 uint32_t reserved3; 6129 uint16_t ustats_counter /* ustorm statistics counter */; 6130 uint16_t reserved4; 6131 uint32_t reserved5; 6132 uint16_t cstats_counter /* ustorm statistics counter */; 6133 uint16_t reserved6; 6134 uint32_t reserved7; 6135 }; 6136 6137 6138 /* 6139 * $$KEEP_ENDIANNESS$$ 6140 */ 6141 struct stats_query_entry 6142 { 6143 uint8_t kind; 6144 uint8_t index /* queue index */; 6145 uint16_t funcID /* the func the statistic will send to */; 6146 uint32_t reserved; 6147 struct regpair address /* pxp address */; 6148 }; 6149 6150 /* 6151 * statistic command $$KEEP_ENDIANNESS$$ 6152 */ 6153 struct stats_query_cmd_group 6154 { 6155 struct stats_query_entry query[STATS_QUERY_CMD_COUNT]; 6156 }; 6157 6158 6159 /* 6160 * statistic command header $$KEEP_ENDIANNESS$$ 6161 */ 6162 struct stats_query_header 6163 { 6164 uint8_t cmd_num /* command number */; 6165 uint8_t reserved0; 6166 uint16_t drv_stats_counter; 6167 uint32_t reserved1; 6168 struct regpair stats_counters_addrs /* stats counter */; 6169 }; 6170 6171 6172 /* 6173 * Types of statistcis query entry 6174 */ 6175 enum stats_query_type 6176 { 6177 STATS_TYPE_QUEUE, 6178 STATS_TYPE_PORT, 6179 STATS_TYPE_PF, 6180 STATS_TYPE_TOE, 6181 STATS_TYPE_FCOE, 6182 MAX_STATS_QUERY_TYPE}; 6183 6184 6185 /* 6186 * Indicate of the function status block state 6187 */ 6188 enum status_block_state 6189 { 6190 SB_DISABLED, 6191 SB_ENABLED, 6192 SB_CLEANED, 6193 MAX_STATUS_BLOCK_STATE}; 6194 6195 6196 /* 6197 * Storm IDs (including attentions for IGU related enums) 6198 */ 6199 enum storm_id 6200 { 6201 USTORM_ID, 6202 CSTORM_ID, 6203 XSTORM_ID, 6204 TSTORM_ID, 6205 ATTENTION_ID, 6206 MAX_STORM_ID}; 6207 6208 6209 /* 6210 * Taffic types used in ETS and flow control algorithms 6211 */ 6212 enum traffic_type 6213 { 6214 LLFC_TRAFFIC_TYPE_NW /* Networking */, 6215 LLFC_TRAFFIC_TYPE_FCOE /* FCoE */, 6216 LLFC_TRAFFIC_TYPE_ISCSI /* iSCSI */, 6217 MAX_TRAFFIC_TYPE}; 6218 6219 6220 /* 6221 * zone A per-queue data 6222 */ 6223 struct tstorm_queue_zone_data 6224 { 6225 struct regpair reserved[4]; 6226 }; 6227 6228 6229 /* 6230 * zone B per-VF data 6231 */ 6232 struct tstorm_vf_zone_data 6233 { 6234 struct regpair reserved; 6235 }; 6236 6237 6238 /* 6239 * Add or Subtract Value for Set Timesync Ramrod 6240 */ 6241 enum ts_add_sub_value 6242 { 6243 TS_SUB_VALUE /* Subtract Value */, 6244 TS_ADD_VALUE /* Add Value */, 6245 MAX_TS_ADD_SUB_VALUE}; 6246 6247 6248 /* 6249 * Drift-Adjust Commands for Set Timesync Ramrod 6250 */ 6251 enum ts_drift_adjust_cmd 6252 { 6253 TS_DRIFT_ADJUST_KEEP /* Keep Drift-Adjust at current values */, 6254 TS_DRIFT_ADJUST_SET /* Set Drift-Adjust */, 6255 TS_DRIFT_ADJUST_RESET /* Reset Drift-Adjust */, 6256 MAX_TS_DRIFT_ADJUST_CMD}; 6257 6258 6259 /* 6260 * Offset Commands for Set Timesync Ramrod 6261 */ 6262 enum ts_offset_cmd 6263 { 6264 TS_OFFSET_KEEP /* Keep Offset at current values */, 6265 TS_OFFSET_INC /* Increase Offset by Offset Delta */, 6266 TS_OFFSET_DEC /* Decrease Offset by Offset Delta */, 6267 MAX_TS_OFFSET_CMD}; 6268 6269 6270 /* 6271 * zone A per-queue data 6272 */ 6273 struct ustorm_queue_zone_data 6274 { 6275 struct ustorm_eth_rx_producers eth_rx_producers /* ETH RX rings producers */; 6276 struct regpair reserved[3]; 6277 }; 6278 6279 6280 /* 6281 * zone B per-VF data 6282 */ 6283 struct ustorm_vf_zone_data 6284 { 6285 struct regpair reserved; 6286 }; 6287 6288 6289 /* 6290 * data per VF-PF channel 6291 */ 6292 struct vf_pf_channel_data 6293 { 6294 #if defined(__BIG_ENDIAN) 6295 uint16_t reserved0; 6296 uint8_t valid /* flag for channel validity. (cleared when identify a VF as malicious) */; 6297 uint8_t state /* channel state (ready / waiting for ack) */; 6298 #elif defined(__LITTLE_ENDIAN) 6299 uint8_t state /* channel state (ready / waiting for ack) */; 6300 uint8_t valid /* flag for channel validity. (cleared when identify a VF as malicious) */; 6301 uint16_t reserved0; 6302 #endif 6303 uint32_t reserved1; 6304 }; 6305 6306 6307 /* 6308 * State of VF-PF channel 6309 */ 6310 enum vf_pf_channel_state 6311 { 6312 VF_PF_CHANNEL_STATE_READY /* Channel is ready to accept a message from VF */, 6313 VF_PF_CHANNEL_STATE_WAITING_FOR_ACK /* Channel waits for an ACK from PF */, 6314 MAX_VF_PF_CHANNEL_STATE}; 6315 6316 6317 /* 6318 * vif_list_rule_kind 6319 */ 6320 enum vif_list_rule_kind 6321 { 6322 VIF_LIST_RULE_SET, 6323 VIF_LIST_RULE_GET, 6324 VIF_LIST_RULE_CLEAR_ALL, 6325 VIF_LIST_RULE_CLEAR_FUNC, 6326 MAX_VIF_LIST_RULE_KIND}; 6327 6328 6329 /* 6330 * zone A per-queue data 6331 */ 6332 struct xstorm_queue_zone_data 6333 { 6334 struct regpair reserved[4]; 6335 }; 6336 6337 6338 /* 6339 * zone B per-VF data 6340 */ 6341 struct xstorm_vf_zone_data 6342 { 6343 struct regpair reserved; 6344 }; 6345 6346 6347 #endif /* ECORE_HSI_H */ 6348 6349