1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2007-2017 QLogic Corporation. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 26 * THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #ifndef ECORE_FW_DEFS_H 33 #define ECORE_FW_DEFS_H 34 35 36 #define CSTORM_ASSERT_LIST_INDEX_OFFSET (IRO[152].base) 37 #define CSTORM_ASSERT_LIST_OFFSET(assertListEntry) \ 38 (IRO[151].base + ((assertListEntry) * IRO[151].m1)) 39 #define CSTORM_EVENT_RING_DATA_OFFSET(pfId) \ 40 (IRO[157].base + (((pfId)>>1) * IRO[157].m1) + (((pfId)&1) * \ 41 IRO[157].m2)) 42 #define CSTORM_EVENT_RING_PROD_OFFSET(pfId) \ 43 (IRO[158].base + (((pfId)>>1) * IRO[158].m1) + (((pfId)&1) * \ 44 IRO[158].m2)) 45 #define CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(funcId) \ 46 (IRO[163].base + ((funcId) * IRO[163].m1)) 47 #define CSTORM_FUNC_EN_OFFSET(funcId) \ 48 (IRO[153].base + ((funcId) * IRO[153].m1)) 49 #define CSTORM_HC_SYNC_LINE_INDEX_E1X_OFFSET(hcIndex, sbId) \ 50 (IRO[143].base + ((hcIndex) * IRO[143].m1) + ((sbId) * IRO[143].m2)) 51 #define CSTORM_HC_SYNC_LINE_INDEX_E2_OFFSET(hcIndex, sbId) \ 52 (IRO[142].base + (((hcIndex)>>2) * IRO[142].m1) + (((hcIndex)&3) \ 53 * IRO[142].m2) + ((sbId) * IRO[142].m3)) 54 #define CSTORM_IGU_MODE_OFFSET (IRO[161].base) 55 #define CSTORM_ISCSI_CQ_SIZE_OFFSET(pfId) \ 56 (IRO[323].base + ((pfId) * IRO[323].m1)) 57 #define CSTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfId) \ 58 (IRO[324].base + ((pfId) * IRO[324].m1)) 59 #define CSTORM_ISCSI_EQ_CONS_OFFSET(pfId, iscsiEqId) \ 60 (IRO[316].base + ((pfId) * IRO[316].m1) + ((iscsiEqId) * IRO[316].m2)) 61 #define CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(pfId, iscsiEqId) \ 62 (IRO[318].base + ((pfId) * IRO[318].m1) + ((iscsiEqId) * IRO[318].m2)) 63 #define CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(pfId, iscsiEqId) \ 64 (IRO[317].base + ((pfId) * IRO[317].m1) + ((iscsiEqId) * IRO[317].m2)) 65 #define CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_VALID_OFFSET(pfId, iscsiEqId) \ 66 (IRO[319].base + ((pfId) * IRO[319].m1) + ((iscsiEqId) * IRO[319].m2)) 67 #define CSTORM_ISCSI_EQ_PROD_OFFSET(pfId, iscsiEqId) \ 68 (IRO[315].base + ((pfId) * IRO[315].m1) + ((iscsiEqId) * IRO[315].m2)) 69 #define CSTORM_ISCSI_EQ_SB_INDEX_OFFSET(pfId, iscsiEqId) \ 70 (IRO[321].base + ((pfId) * IRO[321].m1) + ((iscsiEqId) * IRO[321].m2)) 71 #define CSTORM_ISCSI_EQ_SB_NUM_OFFSET(pfId, iscsiEqId) \ 72 (IRO[320].base + ((pfId) * IRO[320].m1) + ((iscsiEqId) * IRO[320].m2)) 73 #define CSTORM_ISCSI_HQ_SIZE_OFFSET(pfId) \ 74 (IRO[322].base + ((pfId) * IRO[322].m1)) 75 #define CSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId) \ 76 (IRO[314].base + ((pfId) * IRO[314].m1)) 77 #define CSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId) \ 78 (IRO[313].base + ((pfId) * IRO[313].m1)) 79 #define CSTORM_ISCSI_PAGE_SIZE_OFFSET(pfId) \ 80 (IRO[312].base + ((pfId) * IRO[312].m1)) 81 #define CSTORM_RECORD_SLOW_PATH_OFFSET(funcId) \ 82 (IRO[155].base + ((funcId) * IRO[155].m1)) 83 #define CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(pfId) \ 84 (IRO[146].base + ((pfId) * IRO[146].m1)) 85 #define CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(pfId) \ 86 (IRO[147].base + ((pfId) * IRO[147].m1)) 87 #define CSTORM_SP_STATUS_BLOCK_OFFSET(pfId) \ 88 (IRO[145].base + ((pfId) * IRO[145].m1)) 89 #define CSTORM_SP_STATUS_BLOCK_SIZE (IRO[145].size) 90 #define CSTORM_SP_SYNC_BLOCK_OFFSET(pfId) \ 91 (IRO[148].base + ((pfId) * IRO[148].m1)) 92 #define CSTORM_SP_SYNC_BLOCK_SIZE (IRO[148].size) 93 #define CSTORM_STATUS_BLOCK_DATA_FLAGS_OFFSET(sbId, hcIndex) \ 94 (IRO[140].base + ((sbId) * IRO[140].m1) + ((hcIndex) * IRO[140].m2)) 95 #define CSTORM_STATUS_BLOCK_DATA_OFFSET(sbId) \ 96 (IRO[137].base + ((sbId) * IRO[137].m1)) 97 #define CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(sbId) \ 98 (IRO[138].base + ((sbId) * IRO[138].m1)) 99 #define CSTORM_STATUS_BLOCK_DATA_TIMEOUT_OFFSET(sbId, hcIndex) \ 100 (IRO[139].base + ((sbId) * IRO[139].m1) + ((hcIndex) * IRO[139].m2)) 101 #define CSTORM_STATUS_BLOCK_OFFSET(sbId) \ 102 (IRO[136].base + ((sbId) * IRO[136].m1)) 103 #define CSTORM_STATUS_BLOCK_SIZE (IRO[136].size) 104 #define CSTORM_SYNC_BLOCK_OFFSET(sbId) \ 105 (IRO[141].base + ((sbId) * IRO[141].m1)) 106 #define CSTORM_SYNC_BLOCK_SIZE (IRO[141].size) 107 #define CSTORM_VF_TO_PF_OFFSET(funcId) \ 108 (IRO[154].base + ((funcId) * IRO[154].m1)) 109 #define TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET (IRO[208].base) 110 #define TSTORM_APPROXIMATE_MATCH_MULTICAST_FILTERING_OFFSET(pfId) \ 111 (IRO[207].base + ((pfId) * IRO[207].m1)) 112 #define TSTORM_ASSERT_LIST_INDEX_OFFSET (IRO[102].base) 113 #define TSTORM_ASSERT_LIST_OFFSET(assertListEntry) \ 114 (IRO[101].base + ((assertListEntry) * IRO[101].m1)) 115 #define TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(pfId) \ 116 (IRO[205].base + ((pfId) * IRO[205].m1)) 117 #define TSTORM_FUNC_EN_OFFSET(funcId) \ 118 (IRO[107].base + ((funcId) * IRO[107].m1)) 119 #define TSTORM_ISCSI_ERROR_BITMAP_OFFSET(pfId) \ 120 (IRO[278].base + ((pfId) * IRO[278].m1)) 121 #define TSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId) \ 122 (IRO[277].base + ((pfId) * IRO[277].m1)) 123 #define TSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId) \ 124 (IRO[276].base + ((pfId) * IRO[276].m1)) 125 #define TSTORM_ISCSI_PAGE_SIZE_OFFSET(pfId) \ 126 (IRO[275].base + ((pfId) * IRO[275].m1)) 127 #define TSTORM_ISCSI_RQ_SIZE_OFFSET(pfId) \ 128 (IRO[274].base + ((pfId) * IRO[274].m1)) 129 #define TSTORM_ISCSI_TCP_LOCAL_ADV_WND_OFFSET(pfId) \ 130 (IRO[284].base + ((pfId) * IRO[284].m1)) 131 #define TSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(pfId) \ 132 (IRO[270].base + ((pfId) * IRO[270].m1)) 133 #define TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(pfId) \ 134 (IRO[271].base + ((pfId) * IRO[271].m1)) 135 #define TSTORM_ISCSI_TCP_VARS_MID_LOCAL_MAC_ADDR_OFFSET(pfId) \ 136 (IRO[272].base + ((pfId) * IRO[272].m1)) 137 #define TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfId) \ 138 (IRO[273].base + ((pfId) * IRO[273].m1)) 139 #define TSTORM_MAC_FILTER_CONFIG_OFFSET(pfId) \ 140 (IRO[206].base + ((pfId) * IRO[206].m1)) 141 #define TSTORM_RECORD_SLOW_PATH_OFFSET(funcId) \ 142 (IRO[109].base + ((funcId) * IRO[109].m1)) 143 #define TSTORM_TCP_MAX_CWND_OFFSET(pfId) \ 144 (IRO[223].base + ((pfId) * IRO[223].m1)) 145 #define TSTORM_VF_TO_PF_OFFSET(funcId) \ 146 (IRO[108].base + ((funcId) * IRO[108].m1)) 147 #define USTORM_AGG_DATA_OFFSET (IRO[212].base) 148 #define USTORM_AGG_DATA_SIZE (IRO[212].size) 149 #define USTORM_ASSERT_LIST_INDEX_OFFSET (IRO[181].base) 150 #define USTORM_ASSERT_LIST_OFFSET(assertListEntry) \ 151 (IRO[180].base + ((assertListEntry) * IRO[180].m1)) 152 #define USTORM_ETH_PAUSE_ENABLED_OFFSET(portId) \ 153 (IRO[187].base + ((portId) * IRO[187].m1)) 154 #define USTORM_FCOE_EQ_PROD_OFFSET(pfId) \ 155 (IRO[325].base + ((pfId) * IRO[325].m1)) 156 #define USTORM_FUNC_EN_OFFSET(funcId) \ 157 (IRO[182].base + ((funcId) * IRO[182].m1)) 158 #define USTORM_ISCSI_CQ_SIZE_OFFSET(pfId) \ 159 (IRO[289].base + ((pfId) * IRO[289].m1)) 160 #define USTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfId) \ 161 (IRO[290].base + ((pfId) * IRO[290].m1)) 162 #define USTORM_ISCSI_ERROR_BITMAP_OFFSET(pfId) \ 163 (IRO[294].base + ((pfId) * IRO[294].m1)) 164 #define USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(pfId) \ 165 (IRO[291].base + ((pfId) * IRO[291].m1)) 166 #define USTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId) \ 167 (IRO[287].base + ((pfId) * IRO[287].m1)) 168 #define USTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId) \ 169 (IRO[286].base + ((pfId) * IRO[286].m1)) 170 #define USTORM_ISCSI_PAGE_SIZE_OFFSET(pfId) \ 171 (IRO[285].base + ((pfId) * IRO[285].m1)) 172 #define USTORM_ISCSI_R2TQ_SIZE_OFFSET(pfId) \ 173 (IRO[288].base + ((pfId) * IRO[288].m1)) 174 #define USTORM_ISCSI_RQ_BUFFER_SIZE_OFFSET(pfId) \ 175 (IRO[292].base + ((pfId) * IRO[292].m1)) 176 #define USTORM_ISCSI_RQ_SIZE_OFFSET(pfId) \ 177 (IRO[293].base + ((pfId) * IRO[293].m1)) 178 #define USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(pfId) \ 179 (IRO[186].base + ((pfId) * IRO[186].m1)) 180 #define USTORM_RECORD_SLOW_PATH_OFFSET(funcId) \ 181 (IRO[184].base + ((funcId) * IRO[184].m1)) 182 #define USTORM_RX_PRODS_E1X_OFFSET(portId, clientId) \ 183 (IRO[215].base + ((portId) * IRO[215].m1) + ((clientId) * \ 184 IRO[215].m2)) 185 #define USTORM_RX_PRODS_E2_OFFSET(qzoneId) \ 186 (IRO[216].base + ((qzoneId) * IRO[216].m1)) 187 #define USTORM_TPA_BTR_OFFSET (IRO[213].base) 188 #define USTORM_TPA_BTR_SIZE (IRO[213].size) 189 #define USTORM_VF_TO_PF_OFFSET(funcId) \ 190 (IRO[183].base + ((funcId) * IRO[183].m1)) 191 #define XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE (IRO[67].base) 192 #define XSTORM_AGG_INT_FINAL_CLEANUP_INDEX (IRO[66].base) 193 #define XSTORM_ASSERT_LIST_INDEX_OFFSET (IRO[51].base) 194 #define XSTORM_ASSERT_LIST_OFFSET(assertListEntry) \ 195 (IRO[50].base + ((assertListEntry) * IRO[50].m1)) 196 #define XSTORM_CMNG_PER_PORT_VARS_OFFSET(portId) \ 197 (IRO[43].base + ((portId) * IRO[43].m1)) 198 #define XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(pfId) \ 199 (IRO[45].base + ((pfId) * IRO[45].m1)) 200 #define XSTORM_FUNC_EN_OFFSET(funcId) \ 201 (IRO[47].base + ((funcId) * IRO[47].m1)) 202 #define XSTORM_ISCSI_HQ_SIZE_OFFSET(pfId) \ 203 (IRO[302].base + ((pfId) * IRO[302].m1)) 204 #define XSTORM_ISCSI_LOCAL_MAC_ADDR0_OFFSET(pfId) \ 205 (IRO[305].base + ((pfId) * IRO[305].m1)) 206 #define XSTORM_ISCSI_LOCAL_MAC_ADDR1_OFFSET(pfId) \ 207 (IRO[306].base + ((pfId) * IRO[306].m1)) 208 #define XSTORM_ISCSI_LOCAL_MAC_ADDR2_OFFSET(pfId) \ 209 (IRO[307].base + ((pfId) * IRO[307].m1)) 210 #define XSTORM_ISCSI_LOCAL_MAC_ADDR3_OFFSET(pfId) \ 211 (IRO[308].base + ((pfId) * IRO[308].m1)) 212 #define XSTORM_ISCSI_LOCAL_MAC_ADDR4_OFFSET(pfId) \ 213 (IRO[309].base + ((pfId) * IRO[309].m1)) 214 #define XSTORM_ISCSI_LOCAL_MAC_ADDR5_OFFSET(pfId) \ 215 (IRO[310].base + ((pfId) * IRO[310].m1)) 216 #define XSTORM_ISCSI_LOCAL_VLAN_OFFSET(pfId) \ 217 (IRO[311].base + ((pfId) * IRO[311].m1)) 218 #define XSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfId) \ 219 (IRO[301].base + ((pfId) * IRO[301].m1)) 220 #define XSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfId) \ 221 (IRO[300].base + ((pfId) * IRO[300].m1)) 222 #define XSTORM_ISCSI_PAGE_SIZE_OFFSET(pfId) \ 223 (IRO[299].base + ((pfId) * IRO[299].m1)) 224 #define XSTORM_ISCSI_R2TQ_SIZE_OFFSET(pfId) \ 225 (IRO[304].base + ((pfId) * IRO[304].m1)) 226 #define XSTORM_ISCSI_SQ_SIZE_OFFSET(pfId) \ 227 (IRO[303].base + ((pfId) * IRO[303].m1)) 228 #define XSTORM_ISCSI_TCP_VARS_ADV_WND_SCL_OFFSET(pfId) \ 229 (IRO[298].base + ((pfId) * IRO[298].m1)) 230 #define XSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(pfId) \ 231 (IRO[297].base + ((pfId) * IRO[297].m1)) 232 #define XSTORM_ISCSI_TCP_VARS_TOS_OFFSET(pfId) \ 233 (IRO[296].base + ((pfId) * IRO[296].m1)) 234 #define XSTORM_ISCSI_TCP_VARS_TTL_OFFSET(pfId) \ 235 (IRO[295].base + ((pfId) * IRO[295].m1)) 236 #define XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(pfId) \ 237 (IRO[44].base + ((pfId) * IRO[44].m1)) 238 #define XSTORM_RECORD_SLOW_PATH_OFFSET(funcId) \ 239 (IRO[49].base + ((funcId) * IRO[49].m1)) 240 #define XSTORM_SPQ_DATA_OFFSET(funcId) \ 241 (IRO[32].base + ((funcId) * IRO[32].m1)) 242 #define XSTORM_SPQ_DATA_SIZE (IRO[32].size) 243 #define XSTORM_SPQ_PAGE_BASE_OFFSET(funcId) \ 244 (IRO[30].base + ((funcId) * IRO[30].m1)) 245 #define XSTORM_SPQ_PROD_OFFSET(funcId) \ 246 (IRO[31].base + ((funcId) * IRO[31].m1)) 247 #define XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_ENABLED_OFFSET(portId) \ 248 (IRO[217].base + ((portId) * IRO[217].m1)) 249 #define XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_MAX_COUNT_OFFSET(portId) \ 250 (IRO[218].base + ((portId) * IRO[218].m1)) 251 #define XSTORM_TCP_TX_SWS_TIMER_VAL_OFFSET(pfId) \ 252 (IRO[220].base + (((pfId)>>1) * IRO[220].m1) + (((pfId)&1) * \ 253 IRO[220].m2)) 254 #define XSTORM_VF_TO_PF_OFFSET(funcId) \ 255 (IRO[48].base + ((funcId) * IRO[48].m1)) 256 #define COMMON_ASM_INVALID_ASSERT_OPCODE (IRO[7].base) 257 258 259 /* eth hsi version */ 260 #define ETH_FP_HSI_VERSION (ETH_FP_HSI_VER_2) 261 262 263 /* Ethernet Ring parameters */ 264 #define X_ETH_LOCAL_RING_SIZE 13 265 #define FIRST_BD_IN_PKT 0 266 #define PARSE_BD_INDEX 1 267 #define NUM_OF_ETH_BDS_IN_PAGE ((PAGE_SIZE)/(STRUCT_SIZE(eth_tx_bd)/8)) 268 #define U_ETH_NUM_OF_SGES_TO_FETCH 8 269 #define U_ETH_MAX_SGES_FOR_PACKET 3 270 271 /* Rx ring params */ 272 #define U_ETH_LOCAL_BD_RING_SIZE 8 273 #define U_ETH_LOCAL_SGE_RING_SIZE 10 274 #define U_ETH_SGL_SIZE 8 275 /* The fw will padd the buffer with this value, so the IP header \ 276 will be align to 4 Byte */ 277 #define IP_HEADER_ALIGNMENT_PADDING 2 278 279 #define U_ETH_SGES_PER_PAGE_INVERSE_MASK \ 280 (0xFFFF - ((PAGE_SIZE/((STRUCT_SIZE(eth_rx_sge))/8))-1)) 281 282 #define TU_ETH_CQES_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_cqe)/8)) 283 #define U_ETH_BDS_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_bd)/8)) 284 #define U_ETH_SGES_PER_PAGE (PAGE_SIZE/(STRUCT_SIZE(eth_rx_sge)/8)) 285 286 #define U_ETH_BDS_PER_PAGE_MASK (U_ETH_BDS_PER_PAGE-1) 287 #define U_ETH_CQE_PER_PAGE_MASK (TU_ETH_CQES_PER_PAGE-1) 288 #define U_ETH_SGES_PER_PAGE_MASK (U_ETH_SGES_PER_PAGE-1) 289 290 #define U_ETH_UNDEFINED_Q 0xFF 291 292 #define T_ETH_INDIRECTION_TABLE_SIZE 128 293 #define T_ETH_RSS_KEY 10 294 #define ETH_NUM_OF_RSS_ENGINES_E2 72 295 296 #define FILTER_RULES_COUNT 16 297 #define MULTICAST_RULES_COUNT 16 298 #define CLASSIFY_RULES_COUNT 16 299 300 /*The CRC32 seed, that is used for the hash(reduction) multicast address */ 301 #define ETH_CRC32_HASH_SEED 0x00000000 302 303 #define ETH_CRC32_HASH_BIT_SIZE (8) 304 #define ETH_CRC32_HASH_MASK EVAL((1<<ETH_CRC32_HASH_BIT_SIZE)-1) 305 306 /* Maximal L2 clients supported */ 307 #define ETH_MAX_RX_CLIENTS_E1 18 308 #define ETH_MAX_RX_CLIENTS_E1H 28 309 #define ETH_MAX_RX_CLIENTS_E2 152 310 311 /* Maximal statistics client Ids */ 312 #define MAX_STAT_COUNTER_ID_E1 36 313 #define MAX_STAT_COUNTER_ID_E1H 56 314 #define MAX_STAT_COUNTER_ID_E2 140 315 316 #define MAX_MAC_CREDIT_E1 192 /* Per Chip */ 317 #define MAX_MAC_CREDIT_E1H 256 /* Per Chip */ 318 #define MAX_MAC_CREDIT_E2 272 /* Per Path */ 319 #define MAX_VLAN_CREDIT_E1 0 /* Per Chip */ 320 #define MAX_VLAN_CREDIT_E1H 0 /* Per Chip */ 321 #define MAX_VLAN_CREDIT_E2 272 /* Per Path */ 322 323 324 /* Maximal aggregation queues supported */ 325 #define ETH_MAX_AGGREGATION_QUEUES_E1 32 326 #define ETH_MAX_AGGREGATION_QUEUES_E1H_E2 64 327 328 329 #define ETH_NUM_OF_MCAST_BINS 256 330 #define ETH_NUM_OF_MCAST_ENGINES_E2 72 331 332 #define ETH_MIN_RX_CQES_WITHOUT_TPA (MAX_RAMRODS_PER_PORT + 3) 333 #define ETH_MIN_RX_CQES_WITH_TPA_E1 \ 334 (ETH_MAX_AGGREGATION_QUEUES_E1 + ETH_MIN_RX_CQES_WITHOUT_TPA) 335 #define ETH_MIN_RX_CQES_WITH_TPA_E1H_E2 \ 336 (ETH_MAX_AGGREGATION_QUEUES_E1H_E2 + ETH_MIN_RX_CQES_WITHOUT_TPA) 337 338 #define DISABLE_STATISTIC_COUNTER_ID_VALUE 0 339 340 341 /* This file defines HSI constants common to all microcode flows */ 342 343 /* offset in bits of protocol in the state context parameter */ 344 #define PROTOCOL_STATE_BIT_OFFSET 6 345 346 #define ETH_STATE (ETH_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET) 347 #define TOE_STATE (TOE_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET) 348 #define RDMA_STATE (RDMA_CONNECTION_TYPE << PROTOCOL_STATE_BIT_OFFSET) 349 350 /* microcode fixed page page size 4K (chains and ring segments) */ 351 #define MC_PAGE_SIZE 4096 352 353 /* Number of indices per slow-path SB */ 354 #define HC_SP_SB_MAX_INDICES 16 /* The Maximum of all */ 355 356 /* Number of indices per SB */ 357 #define HC_SB_MAX_INDICES_E1X 8 /* Multiple of 4 */ 358 #define HC_SB_MAX_INDICES_E2 8 /* Multiple of 4 */ 359 360 /* Number of SB */ 361 #define HC_SB_MAX_SB_E1X 32 362 #define HC_SB_MAX_SB_E2 136 /* include PF */ 363 364 /* ID of slow path status block */ 365 #define HC_SP_SB_ID 0xde 366 367 /* Num of State machines */ 368 #define HC_SB_MAX_SM 2 /* Fixed */ 369 370 /* Num of dynamic indices */ 371 #define HC_SB_MAX_DYNAMIC_INDICES 4 /* 0..3 fixed */ 372 373 /* max number of slow path commands per port */ 374 #define MAX_RAMRODS_PER_PORT 8 375 376 377 /**** DEFINES FOR TIMERS/CLOCKS RESOLUTIONS ****/ 378 379 /* chip timers frequency constants */ 380 #define TIMERS_TICK_SIZE_CHIP (1e-3) 381 382 /* used in toe: TsRecentAge, MaxRt, and temporarily RTT */ 383 #define TSEMI_CLK1_RESUL_CHIP (1e-3) 384 385 /* temporarily used for RTT */ 386 #define XSEMI_CLK1_RESUL_CHIP (1e-3) 387 388 /* used for Host Coallescing */ 389 #define SDM_TIMER_TICK_RESUL_CHIP (4 * (1e-6)) 390 #define TSDM_TIMER_TICK_RESUL_CHIP (1 * (1e-6)) 391 392 /**** END DEFINES FOR TIMERS/CLOCKS RESOLUTIONS ****/ 393 394 #define XSTORM_IP_ID_ROLL_HALF 0x8000 395 #define XSTORM_IP_ID_ROLL_ALL 0 396 397 /* assert list: number of entries */ 398 #define FW_LOG_LIST_SIZE 50 399 400 #define NUM_OF_SAFC_BITS 16 401 #define MAX_COS_NUMBER 4 402 #define MAX_TRAFFIC_TYPES 8 403 #define MAX_PFC_PRIORITIES 8 404 #define MAX_VLAN_PRIORITIES 8 405 /* used by array traffic_type_to_priority[] to mark traffic type \ 406 that is not mapped to priority*/ 407 #define LLFC_TRAFFIC_TYPE_TO_PRIORITY_UNMAPPED 0xFF 408 409 /* Event Ring definitions */ 410 #define C_ERES_PER_PAGE \ 411 (PAGE_SIZE / BITS_TO_BYTES(STRUCT_SIZE(event_ring_elem))) 412 #define C_ERE_PER_PAGE_MASK (C_ERES_PER_PAGE - 1) 413 414 /* number of statistic command */ 415 #define STATS_QUERY_CMD_COUNT 16 416 417 /* niv list table size */ 418 #define AFEX_LIST_TABLE_SIZE 4096 419 420 /* invalid VNIC Id. used in VNIC classification */ 421 #define INVALID_VNIC_ID 0xFF 422 423 /* used for indicating an undefined RAM offset in the IRO arrays */ 424 #define UNDEF_IRO 0x80000000 425 426 /* used for defining the amount of FCoE tasks supported for PF */ 427 #define MAX_FCOE_FUNCS_PER_ENGINE 2 428 #define MAX_NUM_FCOE_TASKS_PER_ENGINE \ 429 4096 /*Each port can have at max 1 function*/ 430 431 432 #endif /* ECORE_FW_DEFS_H */ 433 434