1 /*- 2 * Copyright (c) 2007-2013 Broadcom Corporation. All rights reserved. 3 * 4 * Eric Davis <edavis@broadcom.com> 5 * David Christensen <davidch@broadcom.com> 6 * Gary Zambrano <zambrano@broadcom.com> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. Neither the name of Broadcom Corporation nor the name of its contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written consent. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' 22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/cdefs.h> 35 __FBSDID("$FreeBSD$"); 36 37 #include "bxe.h" 38 #include "bxe_elink.h" 39 #include "ecore_mfw_req.h" 40 #include "ecore_fw_defs.h" 41 #include "ecore_hsi.h" 42 #include "ecore_reg.h" 43 44 45 #define MDIO_REG_BANK_CL73_IEEEB0 0x0 46 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL 0x0 47 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN 0x0200 48 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN 0x1000 49 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_MAIN_RST 0x8000 50 51 #define MDIO_REG_BANK_CL73_IEEEB1 0x10 52 #define MDIO_CL73_IEEEB1_AN_ADV1 0x00 53 #define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE 0x0400 54 #define MDIO_CL73_IEEEB1_AN_ADV1_ASYMMETRIC 0x0800 55 #define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH 0x0C00 56 #define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK 0x0C00 57 #define MDIO_CL73_IEEEB1_AN_ADV2 0x01 58 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M 0x0000 59 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX 0x0020 60 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 0x0040 61 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR 0x0080 62 #define MDIO_CL73_IEEEB1_AN_LP_ADV1 0x03 63 #define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE 0x0400 64 #define MDIO_CL73_IEEEB1_AN_LP_ADV1_ASYMMETRIC 0x0800 65 #define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_BOTH 0x0C00 66 #define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK 0x0C00 67 #define MDIO_CL73_IEEEB1_AN_LP_ADV2 0x04 68 69 #define MDIO_REG_BANK_RX0 0x80b0 70 #define MDIO_RX0_RX_STATUS 0x10 71 #define MDIO_RX0_RX_STATUS_SIGDET 0x8000 72 #define MDIO_RX0_RX_STATUS_RX_SEQ_DONE 0x1000 73 #define MDIO_RX0_RX_EQ_BOOST 0x1c 74 #define MDIO_RX0_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7 75 #define MDIO_RX0_RX_EQ_BOOST_OFFSET_CTRL 0x10 76 77 #define MDIO_REG_BANK_RX1 0x80c0 78 #define MDIO_RX1_RX_EQ_BOOST 0x1c 79 #define MDIO_RX1_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7 80 #define MDIO_RX1_RX_EQ_BOOST_OFFSET_CTRL 0x10 81 82 #define MDIO_REG_BANK_RX2 0x80d0 83 #define MDIO_RX2_RX_EQ_BOOST 0x1c 84 #define MDIO_RX2_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7 85 #define MDIO_RX2_RX_EQ_BOOST_OFFSET_CTRL 0x10 86 87 #define MDIO_REG_BANK_RX3 0x80e0 88 #define MDIO_RX3_RX_EQ_BOOST 0x1c 89 #define MDIO_RX3_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7 90 #define MDIO_RX3_RX_EQ_BOOST_OFFSET_CTRL 0x10 91 92 #define MDIO_REG_BANK_RX_ALL 0x80f0 93 #define MDIO_RX_ALL_RX_EQ_BOOST 0x1c 94 #define MDIO_RX_ALL_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7 95 #define MDIO_RX_ALL_RX_EQ_BOOST_OFFSET_CTRL 0x10 96 97 #define MDIO_REG_BANK_TX0 0x8060 98 #define MDIO_TX0_TX_DRIVER 0x17 99 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000 100 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12 101 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00 102 #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8 103 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0 104 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4 105 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e 106 #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1 107 #define MDIO_TX0_TX_DRIVER_ICBUF1T 1 108 109 #define MDIO_REG_BANK_TX1 0x8070 110 #define MDIO_TX1_TX_DRIVER 0x17 111 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000 112 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12 113 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00 114 #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8 115 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0 116 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4 117 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e 118 #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1 119 #define MDIO_TX0_TX_DRIVER_ICBUF1T 1 120 121 #define MDIO_REG_BANK_TX2 0x8080 122 #define MDIO_TX2_TX_DRIVER 0x17 123 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000 124 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12 125 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00 126 #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8 127 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0 128 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4 129 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e 130 #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1 131 #define MDIO_TX0_TX_DRIVER_ICBUF1T 1 132 133 #define MDIO_REG_BANK_TX3 0x8090 134 #define MDIO_TX3_TX_DRIVER 0x17 135 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000 136 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12 137 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00 138 #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8 139 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0 140 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4 141 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e 142 #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1 143 #define MDIO_TX0_TX_DRIVER_ICBUF1T 1 144 145 #define MDIO_REG_BANK_XGXS_BLOCK0 0x8000 146 #define MDIO_BLOCK0_XGXS_CONTROL 0x10 147 148 #define MDIO_REG_BANK_XGXS_BLOCK1 0x8010 149 #define MDIO_BLOCK1_LANE_CTRL0 0x15 150 #define MDIO_BLOCK1_LANE_CTRL1 0x16 151 #define MDIO_BLOCK1_LANE_CTRL2 0x17 152 #define MDIO_BLOCK1_LANE_PRBS 0x19 153 154 #define MDIO_REG_BANK_XGXS_BLOCK2 0x8100 155 #define MDIO_XGXS_BLOCK2_RX_LN_SWAP 0x10 156 #define MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE 0x8000 157 #define MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE 0x4000 158 #define MDIO_XGXS_BLOCK2_TX_LN_SWAP 0x11 159 #define MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE 0x8000 160 #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G 0x14 161 #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS 0x0001 162 #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS 0x0010 163 #define MDIO_XGXS_BLOCK2_TEST_MODE_LANE 0x15 164 165 #define MDIO_REG_BANK_GP_STATUS 0x8120 166 #define MDIO_GP_STATUS_TOP_AN_STATUS1 0x1B 167 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE 0x0001 168 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE 0x0002 169 #define MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS 0x0004 170 #define MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS 0x0008 171 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE 0x0010 172 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_LP_NP_BAM_ABLE 0x0020 173 #define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE 0x0040 174 #define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE 0x0080 175 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK 0x3f00 176 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M 0x0000 177 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M 0x0100 178 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G 0x0200 179 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G 0x0300 180 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G 0x0400 181 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G 0x0500 182 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG 0x0600 183 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4 0x0700 184 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG 0x0800 185 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G 0x0900 186 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G 0x0A00 187 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G 0x0B00 188 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G 0x0C00 189 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX 0x0D00 190 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4 0x0E00 191 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR 0x0F00 192 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI 0x1B00 193 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS 0x1E00 194 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI 0x1F00 195 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_KR2 0x3900 196 197 198 #define MDIO_REG_BANK_10G_PARALLEL_DETECT 0x8130 199 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS 0x10 200 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK 0x8000 201 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL 0x11 202 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN 0x1 203 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK 0x13 204 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT (0xb71<<1) 205 206 #define MDIO_REG_BANK_SERDES_DIGITAL 0x8300 207 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1 0x10 208 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE 0x0001 209 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_TBI_IF 0x0002 210 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN 0x0004 211 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT 0x0008 212 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET 0x0010 213 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE 0x0020 214 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2 0x11 215 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN 0x0001 216 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_AN_FST_TMR 0x0040 217 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1 0x14 218 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SGMII 0x0001 219 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_LINK 0x0002 220 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_DUPLEX 0x0004 221 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_MASK 0x0018 222 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_SHIFT 3 223 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_2_5G 0x0018 224 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_1G 0x0010 225 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_100M 0x0008 226 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_10M 0x0000 227 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS2 0x15 228 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED 0x0002 229 #define MDIO_SERDES_DIGITAL_MISC1 0x18 230 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_MASK 0xE000 231 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_25M 0x0000 232 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_100M 0x2000 233 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_125M 0x4000 234 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M 0x6000 235 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_187_5M 0x8000 236 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL 0x0010 237 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK 0x000f 238 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_2_5G 0x0000 239 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_5G 0x0001 240 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_6G 0x0002 241 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_HIG 0x0003 242 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4 0x0004 243 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12G 0x0005 244 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12_5G 0x0006 245 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_13G 0x0007 246 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_15G 0x0008 247 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_16G 0x0009 248 249 #define MDIO_REG_BANK_OVER_1G 0x8320 250 #define MDIO_OVER_1G_DIGCTL_3_4 0x14 251 #define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_MASK 0xffe0 252 #define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_SHIFT 5 253 #define MDIO_OVER_1G_UP1 0x19 254 #define MDIO_OVER_1G_UP1_2_5G 0x0001 255 #define MDIO_OVER_1G_UP1_5G 0x0002 256 #define MDIO_OVER_1G_UP1_6G 0x0004 257 #define MDIO_OVER_1G_UP1_10G 0x0010 258 #define MDIO_OVER_1G_UP1_10GH 0x0008 259 #define MDIO_OVER_1G_UP1_12G 0x0020 260 #define MDIO_OVER_1G_UP1_12_5G 0x0040 261 #define MDIO_OVER_1G_UP1_13G 0x0080 262 #define MDIO_OVER_1G_UP1_15G 0x0100 263 #define MDIO_OVER_1G_UP1_16G 0x0200 264 #define MDIO_OVER_1G_UP2 0x1A 265 #define MDIO_OVER_1G_UP2_IPREDRIVER_MASK 0x0007 266 #define MDIO_OVER_1G_UP2_IDRIVER_MASK 0x0038 267 #define MDIO_OVER_1G_UP2_PREEMPHASIS_MASK 0x03C0 268 #define MDIO_OVER_1G_UP3 0x1B 269 #define MDIO_OVER_1G_UP3_HIGIG2 0x0001 270 #define MDIO_OVER_1G_LP_UP1 0x1C 271 #define MDIO_OVER_1G_LP_UP2 0x1D 272 #define MDIO_OVER_1G_LP_UP2_MR_ADV_OVER_1G_MASK 0x03ff 273 #define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK 0x0780 274 #define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT 7 275 #define MDIO_OVER_1G_LP_UP3 0x1E 276 277 #define MDIO_REG_BANK_REMOTE_PHY 0x8330 278 #define MDIO_REMOTE_PHY_MISC_RX_STATUS 0x10 279 #define MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG 0x0010 280 #define MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG 0x0600 281 282 #define MDIO_REG_BANK_BAM_NEXT_PAGE 0x8350 283 #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL 0x10 284 #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE 0x0001 285 #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN 0x0002 286 287 #define MDIO_REG_BANK_CL73_USERB0 0x8370 288 #define MDIO_CL73_USERB0_CL73_UCTRL 0x10 289 #define MDIO_CL73_USERB0_CL73_UCTRL_USTAT1_MUXSEL 0x0002 290 #define MDIO_CL73_USERB0_CL73_USTAT1 0x11 291 #define MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK 0x0100 292 #define MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37 0x0400 293 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1 0x12 294 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN 0x8000 295 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN 0x4000 296 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN 0x2000 297 #define MDIO_CL73_USERB0_CL73_BAM_CTRL3 0x14 298 #define MDIO_CL73_USERB0_CL73_BAM_CTRL3_USE_CL73_HCD_MR 0x0001 299 300 #define MDIO_REG_BANK_AER_BLOCK 0xFFD0 301 #define MDIO_AER_BLOCK_AER_REG 0x1E 302 303 #define MDIO_REG_BANK_COMBO_IEEE0 0xFFE0 304 #define MDIO_COMBO_IEEE0_MII_CONTROL 0x10 305 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK 0x2040 306 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_10 0x0000 307 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100 0x2000 308 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000 0x0040 309 #define MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX 0x0100 310 #define MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN 0x0200 311 #define MDIO_COMBO_IEEO_MII_CONTROL_AN_EN 0x1000 312 #define MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK 0x4000 313 #define MDIO_COMBO_IEEO_MII_CONTROL_RESET 0x8000 314 #define MDIO_COMBO_IEEE0_MII_STATUS 0x11 315 #define MDIO_COMBO_IEEE0_MII_STATUS_LINK_PASS 0x0004 316 #define MDIO_COMBO_IEEE0_MII_STATUS_AUTONEG_COMPLETE 0x0020 317 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV 0x14 318 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX 0x0020 319 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_HALF_DUPLEX 0x0040 320 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK 0x0180 321 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE 0x0000 322 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC 0x0080 323 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC 0x0100 324 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH 0x0180 325 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_NEXT_PAGE 0x8000 326 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1 0x15 327 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_NEXT_PAGE 0x8000 328 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_ACK 0x4000 329 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_MASK 0x0180 330 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_NONE 0x0000 331 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_BOTH 0x0180 332 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_HALF_DUP_CAP 0x0040 333 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_FULL_DUP_CAP 0x0020 334 /*WhenthelinkpartnerisinSGMIImode(bit0=1),then 335 bit15=link,bit12=duplex,bits11:10=speed,bit14=acknowledge. 336 Theotherbitsarereservedandshouldbezero*/ 337 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_SGMII_MODE 0x0001 338 339 340 #define MDIO_PMA_DEVAD 0x1 341 /*ieee*/ 342 #define MDIO_PMA_REG_CTRL 0x0 343 #define MDIO_PMA_REG_STATUS 0x1 344 #define MDIO_PMA_REG_10G_CTRL2 0x7 345 #define MDIO_PMA_REG_TX_DISABLE 0x0009 346 #define MDIO_PMA_REG_RX_SD 0xa 347 /*bcm*/ 348 #define MDIO_PMA_REG_BCM_CTRL 0x0096 349 #define MDIO_PMA_REG_FEC_CTRL 0x00ab 350 #define MDIO_PMA_LASI_RXCTRL 0x9000 351 #define MDIO_PMA_LASI_TXCTRL 0x9001 352 #define MDIO_PMA_LASI_CTRL 0x9002 353 #define MDIO_PMA_LASI_RXSTAT 0x9003 354 #define MDIO_PMA_LASI_TXSTAT 0x9004 355 #define MDIO_PMA_LASI_STAT 0x9005 356 #define MDIO_PMA_REG_PHY_IDENTIFIER 0xc800 357 #define MDIO_PMA_REG_DIGITAL_CTRL 0xc808 358 #define MDIO_PMA_REG_DIGITAL_STATUS 0xc809 359 #define MDIO_PMA_REG_TX_POWER_DOWN 0xca02 360 #define MDIO_PMA_REG_CMU_PLL_BYPASS 0xca09 361 #define MDIO_PMA_REG_MISC_CTRL 0xca0a 362 #define MDIO_PMA_REG_GEN_CTRL 0xca10 363 #define MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP 0x0188 364 #define MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET 0x018a 365 #define MDIO_PMA_REG_M8051_MSGIN_REG 0xca12 366 #define MDIO_PMA_REG_M8051_MSGOUT_REG 0xca13 367 #define MDIO_PMA_REG_ROM_VER1 0xca19 368 #define MDIO_PMA_REG_ROM_VER2 0xca1a 369 #define MDIO_PMA_REG_EDC_FFE_MAIN 0xca1b 370 #define MDIO_PMA_REG_PLL_BANDWIDTH 0xca1d 371 #define MDIO_PMA_REG_PLL_CTRL 0xca1e 372 #define MDIO_PMA_REG_MISC_CTRL0 0xca23 373 #define MDIO_PMA_REG_LRM_MODE 0xca3f 374 #define MDIO_PMA_REG_CDR_BANDWIDTH 0xca46 375 #define MDIO_PMA_REG_MISC_CTRL1 0xca85 376 377 #define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL 0x8000 378 #define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK 0x000c 379 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE 0x0000 380 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE 0x0004 381 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IN_PROGRESS 0x0008 382 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_FAILED 0x000c 383 #define MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT 0x8002 384 #define MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR 0x8003 385 #define MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF 0xc820 386 #define MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK 0xff 387 #define MDIO_PMA_REG_8726_TX_CTRL1 0xca01 388 #define MDIO_PMA_REG_8726_TX_CTRL2 0xca05 389 390 #define MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR 0x8005 391 #define MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF 0x8007 392 #define MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK 0xff 393 #define MDIO_PMA_REG_8727_MISC_CTRL 0x8309 394 #define MDIO_PMA_REG_8727_TX_CTRL1 0xca02 395 #define MDIO_PMA_REG_8727_TX_CTRL2 0xca05 396 #define MDIO_PMA_REG_8727_PCS_OPT_CTRL 0xc808 397 #define MDIO_PMA_REG_8727_GPIO_CTRL 0xc80e 398 #define MDIO_PMA_REG_8727_PCS_GP 0xc842 399 #define MDIO_PMA_REG_8727_OPT_CFG_REG 0xc8e4 400 401 #define MDIO_AN_REG_8727_MISC_CTRL 0x8309 402 #define MDIO_PMA_REG_8073_CHIP_REV 0xc801 403 #define MDIO_PMA_REG_8073_SPEED_LINK_STATUS 0xc820 404 #define MDIO_PMA_REG_8073_XAUI_WA 0xc841 405 #define MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL 0xcd08 406 407 #define MDIO_PMA_REG_7101_RESET 0xc000 408 #define MDIO_PMA_REG_7107_LED_CNTL 0xc007 409 #define MDIO_PMA_REG_7107_LINK_LED_CNTL 0xc009 410 #define MDIO_PMA_REG_7101_VER1 0xc026 411 #define MDIO_PMA_REG_7101_VER2 0xc027 412 413 #define MDIO_PMA_REG_8481_PMD_SIGNAL 0xa811 414 #define MDIO_PMA_REG_8481_LED1_MASK 0xa82c 415 #define MDIO_PMA_REG_8481_LED2_MASK 0xa82f 416 #define MDIO_PMA_REG_8481_LED3_MASK 0xa832 417 #define MDIO_PMA_REG_8481_LED3_BLINK 0xa834 418 #define MDIO_PMA_REG_8481_LED5_MASK 0xa838 419 #define MDIO_PMA_REG_8481_SIGNAL_MASK 0xa835 420 #define MDIO_PMA_REG_8481_LINK_SIGNAL 0xa83b 421 #define MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK 0x800 422 #define MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT 11 423 424 425 426 #define MDIO_WIS_DEVAD 0x2 427 /*bcm*/ 428 #define MDIO_WIS_REG_LASI_CNTL 0x9002 429 #define MDIO_WIS_REG_LASI_STATUS 0x9005 430 431 #define MDIO_PCS_DEVAD 0x3 432 #define MDIO_PCS_REG_STATUS 0x0020 433 #define MDIO_PCS_REG_LASI_STATUS 0x9005 434 #define MDIO_PCS_REG_7101_DSP_ACCESS 0xD000 435 #define MDIO_PCS_REG_7101_SPI_MUX 0xD008 436 #define MDIO_PCS_REG_7101_SPI_CTRL_ADDR 0xE12A 437 #define MDIO_PCS_REG_7101_SPI_RESET_BIT (5) 438 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR 0xE02A 439 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_WRITE_ENABLE_CMD (6) 440 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_BULK_ERASE_CMD (0xC7) 441 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_PAGE_PROGRAM_CMD (2) 442 #define MDIO_PCS_REG_7101_SPI_BYTES_TO_TRANSFER_ADDR 0xE028 443 444 445 446 #define MDIO_XS_DEVAD 0x4 447 #define MDIO_XS_REG_STATUS 0x0001 448 #define MDIO_XS_PLL_SEQUENCER 0x8000 449 #define MDIO_XS_SFX7101_XGXS_TEST1 0xc00a 450 451 #define MDIO_XS_8706_REG_BANK_RX0 0x80bc 452 #define MDIO_XS_8706_REG_BANK_RX1 0x80cc 453 #define MDIO_XS_8706_REG_BANK_RX2 0x80dc 454 #define MDIO_XS_8706_REG_BANK_RX3 0x80ec 455 #define MDIO_XS_8706_REG_BANK_RXA 0x80fc 456 457 #define MDIO_XS_REG_8073_RX_CTRL_PCIE 0x80FA 458 459 #define MDIO_AN_DEVAD 0x7 460 /*ieee*/ 461 #define MDIO_AN_REG_CTRL 0x0000 462 #define MDIO_AN_REG_STATUS 0x0001 463 #define MDIO_AN_REG_STATUS_AN_COMPLETE 0x0020 464 #define MDIO_AN_REG_ADV_PAUSE 0x0010 465 #define MDIO_AN_REG_ADV_PAUSE_PAUSE 0x0400 466 #define MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC 0x0800 467 #define MDIO_AN_REG_ADV_PAUSE_BOTH 0x0C00 468 #define MDIO_AN_REG_ADV_PAUSE_MASK 0x0C00 469 #define MDIO_AN_REG_ADV 0x0011 470 #define MDIO_AN_REG_ADV2 0x0012 471 #define MDIO_AN_REG_LP_AUTO_NEG 0x0013 472 #define MDIO_AN_REG_LP_AUTO_NEG2 0x0014 473 #define MDIO_AN_REG_MASTER_STATUS 0x0021 474 #define MDIO_AN_REG_EEE_ADV 0x003c 475 #define MDIO_AN_REG_LP_EEE_ADV 0x003d 476 /*bcm*/ 477 #define MDIO_AN_REG_LINK_STATUS 0x8304 478 #define MDIO_AN_REG_CL37_CL73 0x8370 479 #define MDIO_AN_REG_CL37_AN 0xffe0 480 #define MDIO_AN_REG_CL37_FC_LD 0xffe4 481 #define MDIO_AN_REG_CL37_FC_LP 0xffe5 482 #define MDIO_AN_REG_1000T_STATUS 0xffea 483 484 #define MDIO_AN_REG_8073_2_5G 0x8329 485 #define MDIO_AN_REG_8073_BAM 0x8350 486 487 #define MDIO_AN_REG_8481_10GBASE_T_AN_CTRL 0x0020 488 #define MDIO_AN_REG_8481_LEGACY_MII_CTRL 0xffe0 489 #define MDIO_AN_REG_8481_MII_CTRL_FORCE_1G 0x40 490 #define MDIO_AN_REG_8481_LEGACY_MII_STATUS 0xffe1 491 #define MDIO_AN_REG_8481_LEGACY_AN_ADV 0xffe4 492 #define MDIO_AN_REG_8481_LEGACY_AN_EXPANSION 0xffe6 493 #define MDIO_AN_REG_8481_1000T_CTRL 0xffe9 494 #define MDIO_AN_REG_8481_1G_100T_EXT_CTRL 0xfff0 495 #define MIDO_AN_REG_8481_EXT_CTRL_FORCE_LEDS_OFF 0x0008 496 #define MDIO_AN_REG_8481_EXPANSION_REG_RD_RW 0xfff5 497 #define MDIO_AN_REG_8481_EXPANSION_REG_ACCESS 0xfff7 498 #define MDIO_AN_REG_8481_AUX_CTRL 0xfff8 499 #define MDIO_AN_REG_8481_LEGACY_SHADOW 0xfffc 500 501 /* BCM84823 only */ 502 #define MDIO_CTL_DEVAD 0x1e 503 #define MDIO_CTL_REG_84823_MEDIA 0x401a 504 #define MDIO_CTL_REG_84823_MEDIA_MAC_MASK 0x0018 505 /* These pins configure the BCM84823 interface to MAC after reset. */ 506 #define MDIO_CTL_REG_84823_CTRL_MAC_XFI 0x0008 507 #define MDIO_CTL_REG_84823_MEDIA_MAC_XAUI_M 0x0010 508 /* These pins configure the BCM84823 interface to Line after reset. */ 509 #define MDIO_CTL_REG_84823_MEDIA_LINE_MASK 0x0060 510 #define MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L 0x0020 511 #define MDIO_CTL_REG_84823_MEDIA_LINE_XFI 0x0040 512 /* When this pin is active high during reset, 10GBASE-T core is power 513 * down, When it is active low the 10GBASE-T is power up 514 */ 515 #define MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN 0x0080 516 #define MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK 0x0100 517 #define MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER 0x0000 518 #define MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER 0x0100 519 #define MDIO_CTL_REG_84823_MEDIA_FIBER_1G 0x1000 520 #define MDIO_CTL_REG_84823_USER_CTRL_REG 0x4005 521 #define MDIO_CTL_REG_84823_USER_CTRL_CMS 0x0080 522 #define MDIO_PMA_REG_84823_CTL_SLOW_CLK_CNT_HIGH 0xa82b 523 #define MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ 0x2f 524 #define MDIO_PMA_REG_84823_CTL_LED_CTL_1 0xa8e3 525 #define MDIO_PMA_REG_84833_CTL_LED_CTL_1 0xa8ec 526 #define MDIO_PMA_REG_84823_LED3_STRETCH_EN 0x0080 527 528 /* BCM84833 only */ 529 #define MDIO_84833_TOP_CFG_FW_REV 0x400f 530 #define MDIO_84833_TOP_CFG_FW_EEE 0x10b1 531 #define MDIO_84833_TOP_CFG_FW_NO_EEE 0x1f81 532 #define MDIO_84833_TOP_CFG_XGPHY_STRAP1 0x401a 533 #define MDIO_84833_SUPER_ISOLATE 0x8000 534 /* These are mailbox register set used by 84833. */ 535 #define MDIO_84833_TOP_CFG_SCRATCH_REG0 0x4005 536 #define MDIO_84833_TOP_CFG_SCRATCH_REG1 0x4006 537 #define MDIO_84833_TOP_CFG_SCRATCH_REG2 0x4007 538 #define MDIO_84833_TOP_CFG_SCRATCH_REG3 0x4008 539 #define MDIO_84833_TOP_CFG_SCRATCH_REG4 0x4009 540 #define MDIO_84833_TOP_CFG_SCRATCH_REG26 0x4037 541 #define MDIO_84833_TOP_CFG_SCRATCH_REG27 0x4038 542 #define MDIO_84833_TOP_CFG_SCRATCH_REG28 0x4039 543 #define MDIO_84833_TOP_CFG_SCRATCH_REG29 0x403a 544 #define MDIO_84833_TOP_CFG_SCRATCH_REG30 0x403b 545 #define MDIO_84833_TOP_CFG_SCRATCH_REG31 0x403c 546 #define MDIO_84833_CMD_HDLR_COMMAND MDIO_84833_TOP_CFG_SCRATCH_REG0 547 #define MDIO_84833_CMD_HDLR_STATUS MDIO_84833_TOP_CFG_SCRATCH_REG26 548 #define MDIO_84833_CMD_HDLR_DATA1 MDIO_84833_TOP_CFG_SCRATCH_REG27 549 #define MDIO_84833_CMD_HDLR_DATA2 MDIO_84833_TOP_CFG_SCRATCH_REG28 550 #define MDIO_84833_CMD_HDLR_DATA3 MDIO_84833_TOP_CFG_SCRATCH_REG29 551 #define MDIO_84833_CMD_HDLR_DATA4 MDIO_84833_TOP_CFG_SCRATCH_REG30 552 #define MDIO_84833_CMD_HDLR_DATA5 MDIO_84833_TOP_CFG_SCRATCH_REG31 553 554 /* Mailbox command set used by 84833. */ 555 #define PHY84833_CMD_SET_PAIR_SWAP 0x8001 556 #define PHY84833_CMD_GET_EEE_MODE 0x8008 557 #define PHY84833_CMD_SET_EEE_MODE 0x8009 558 #define PHY84833_CMD_GET_CURRENT_TEMP 0x8031 559 /* Mailbox status set used by 84833. */ 560 #define PHY84833_STATUS_CMD_RECEIVED 0x0001 561 #define PHY84833_STATUS_CMD_IN_PROGRESS 0x0002 562 #define PHY84833_STATUS_CMD_COMPLETE_PASS 0x0004 563 #define PHY84833_STATUS_CMD_COMPLETE_ERROR 0x0008 564 #define PHY84833_STATUS_CMD_OPEN_FOR_CMDS 0x0010 565 #define PHY84833_STATUS_CMD_SYSTEM_BOOT 0x0020 566 #define PHY84833_STATUS_CMD_NOT_OPEN_FOR_CMDS 0x0040 567 #define PHY84833_STATUS_CMD_CLEAR_COMPLETE 0x0080 568 #define PHY84833_STATUS_CMD_OPEN_OVERRIDE 0xa5a5 569 570 571 /* Warpcore clause 45 addressing */ 572 #define MDIO_WC_DEVAD 0x3 573 #define MDIO_WC_REG_IEEE0BLK_MIICNTL 0x0 574 #define MDIO_WC_REG_IEEE0BLK_AUTONEGNP 0x7 575 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT0 0x10 576 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1 0x11 577 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT2 0x12 578 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_ABILITY 0x4000 579 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ 0x8000 580 #define MDIO_WC_REG_PCS_STATUS2 0x0021 581 #define MDIO_WC_REG_PMD_KR_CONTROL 0x0096 582 #define MDIO_WC_REG_XGXSBLK0_XGXSCONTROL 0x8000 583 #define MDIO_WC_REG_XGXSBLK0_MISCCONTROL1 0x800e 584 #define MDIO_WC_REG_XGXSBLK1_DESKEW 0x8010 585 #define MDIO_WC_REG_XGXSBLK1_LANECTRL0 0x8015 586 #define MDIO_WC_REG_XGXSBLK1_LANECTRL1 0x8016 587 #define MDIO_WC_REG_XGXSBLK1_LANECTRL2 0x8017 588 #define MDIO_WC_REG_XGXSBLK1_LANECTRL3 0x8018 589 #define MDIO_WC_REG_XGXSBLK1_LANETEST0 0x801a 590 #define MDIO_WC_REG_TX0_ANA_CTRL0 0x8061 591 #define MDIO_WC_REG_TX1_ANA_CTRL0 0x8071 592 #define MDIO_WC_REG_TX2_ANA_CTRL0 0x8081 593 #define MDIO_WC_REG_TX3_ANA_CTRL0 0x8091 594 #define MDIO_WC_REG_TX0_TX_DRIVER 0x8067 595 #define MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET 0x04 596 #define MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_MASK 0x00f0 597 #define MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET 0x08 598 #define MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00 599 #define MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET 0x0c 600 #define MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_MASK 0x7000 601 #define MDIO_WC_REG_TX1_TX_DRIVER 0x8077 602 #define MDIO_WC_REG_TX2_TX_DRIVER 0x8087 603 #define MDIO_WC_REG_TX3_TX_DRIVER 0x8097 604 #define MDIO_WC_REG_RX0_ANARXCONTROL1G 0x80b9 605 #define MDIO_WC_REG_RX2_ANARXCONTROL1G 0x80d9 606 #define MDIO_WC_REG_RX0_PCI_CTRL 0x80ba 607 #define MDIO_WC_REG_RX1_PCI_CTRL 0x80ca 608 #define MDIO_WC_REG_RX2_PCI_CTRL 0x80da 609 #define MDIO_WC_REG_RX3_PCI_CTRL 0x80ea 610 #define MDIO_WC_REG_XGXSBLK2_UNICORE_MODE_10G 0x8104 611 #define MDIO_WC_REG_XGXS_STATUS3 0x8129 612 #define MDIO_WC_REG_PAR_DET_10G_STATUS 0x8130 613 #define MDIO_WC_REG_PAR_DET_10G_CTRL 0x8131 614 #define MDIO_WC_REG_XGXS_STATUS4 0x813c 615 #define MDIO_WC_REG_XGXS_X2_CONTROL2 0x8141 616 #define MDIO_WC_REG_XGXS_X2_CONTROL3 0x8142 617 #define MDIO_WC_REG_XGXS_RX_LN_SWAP1 0x816B 618 #define MDIO_WC_REG_XGXS_TX_LN_SWAP1 0x8169 619 #define MDIO_WC_REG_GP2_STATUS_GP_2_0 0x81d0 620 #define MDIO_WC_REG_GP2_STATUS_GP_2_1 0x81d1 621 #define MDIO_WC_REG_GP2_STATUS_GP_2_2 0x81d2 622 #define MDIO_WC_REG_GP2_STATUS_GP_2_3 0x81d3 623 #define MDIO_WC_REG_GP2_STATUS_GP_2_4 0x81d4 624 #define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL73_AN_CMPL 0x1000 625 #define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_AN_CMPL 0x0100 626 #define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_LP_AN_CAP 0x0010 627 #define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_AN_CAP 0x1 628 #define MDIO_WC_REG_UC_INFO_B0_DEAD_TRAP 0x81EE 629 #define MDIO_WC_REG_UC_INFO_B1_VERSION 0x81F0 630 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE 0x81F2 631 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE0_OFFSET 0x0 632 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT 0x0 633 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_OPT_LR 0x1 634 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC 0x2 635 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_XLAUI 0x3 636 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_LONG_CH_6G 0x4 637 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE1_OFFSET 0x4 638 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE2_OFFSET 0x8 639 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE3_OFFSET 0xc 640 #define MDIO_WC_REG_UC_INFO_B1_CRC 0x81FE 641 #define MDIO_WC_REG_DSC1B0_UC_CTRL 0x820e 642 #define MDIO_WC_REG_DSC1B0_UC_CTRL_RDY4CMD (1<<7) 643 #define MDIO_WC_REG_DSC_SMC 0x8213 644 #define MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0 0x821e 645 #define MDIO_WC_REG_TX_FIR_TAP 0x82e2 646 #define MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET 0x00 647 #define MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_MASK 0x000f 648 #define MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET 0x04 649 #define MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_MASK 0x03f0 650 #define MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET 0x0a 651 #define MDIO_WC_REG_TX_FIR_TAP_POST_TAP_MASK 0x7c00 652 #define MDIO_WC_REG_TX_FIR_TAP_ENABLE 0x8000 653 #define MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP 0x82e2 654 #define MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL 0x82e3 655 #define MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL 0x82e6 656 #define MDIO_WC_REG_CL72_USERB0_CL72_BR_DEF_CTRL 0x82e7 657 #define MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL 0x82e8 658 #define MDIO_WC_REG_CL72_USERB0_CL72_MISC4_CONTROL 0x82ec 659 #define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1 0x8300 660 #define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2 0x8301 661 #define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3 0x8302 662 #define MDIO_WC_REG_SERDESDIGITAL_STATUS1000X1 0x8304 663 #define MDIO_WC_REG_SERDESDIGITAL_MISC1 0x8308 664 #define MDIO_WC_REG_SERDESDIGITAL_MISC2 0x8309 665 #define MDIO_WC_REG_DIGITAL3_UP1 0x8329 666 #define MDIO_WC_REG_DIGITAL3_LP_UP1 0x832c 667 #define MDIO_WC_REG_DIGITAL4_MISC3 0x833c 668 #define MDIO_WC_REG_DIGITAL4_MISC5 0x833e 669 #define MDIO_WC_REG_DIGITAL5_MISC6 0x8345 670 #define MDIO_WC_REG_DIGITAL5_MISC7 0x8349 671 #define MDIO_WC_REG_DIGITAL5_LINK_STATUS 0x834d 672 #define MDIO_WC_REG_DIGITAL5_ACTUAL_SPEED 0x834e 673 #define MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL 0x8350 674 #define MDIO_WC_REG_CL49_USERB0_CTRL 0x8368 675 #define MDIO_WC_REG_CL73_USERB0_CTRL 0x8370 676 #define MDIO_WC_REG_CL73_USERB0_USTAT 0x8371 677 #define MDIO_WC_REG_CL73_BAM_CTRL1 0x8372 678 #define MDIO_WC_REG_CL73_BAM_CTRL2 0x8373 679 #define MDIO_WC_REG_CL73_BAM_CTRL3 0x8374 680 #define MDIO_WC_REG_CL73_BAM_CODE_FIELD 0x837b 681 #define MDIO_WC_REG_EEE_COMBO_CONTROL0 0x8390 682 #define MDIO_WC_REG_TX66_CONTROL 0x83b0 683 #define MDIO_WC_REG_RX66_CONTROL 0x83c0 684 #define MDIO_WC_REG_RX66_SCW0 0x83c2 685 #define MDIO_WC_REG_RX66_SCW1 0x83c3 686 #define MDIO_WC_REG_RX66_SCW2 0x83c4 687 #define MDIO_WC_REG_RX66_SCW3 0x83c5 688 #define MDIO_WC_REG_RX66_SCW0_MASK 0x83c6 689 #define MDIO_WC_REG_RX66_SCW1_MASK 0x83c7 690 #define MDIO_WC_REG_RX66_SCW2_MASK 0x83c8 691 #define MDIO_WC_REG_RX66_SCW3_MASK 0x83c9 692 #define MDIO_WC_REG_FX100_CTRL1 0x8400 693 #define MDIO_WC_REG_FX100_CTRL3 0x8402 694 #define MDIO_WC_REG_CL82_USERB1_TX_CTRL5 0x8436 695 #define MDIO_WC_REG_CL82_USERB1_TX_CTRL6 0x8437 696 #define MDIO_WC_REG_CL82_USERB1_TX_CTRL7 0x8438 697 #define MDIO_WC_REG_CL82_USERB1_TX_CTRL9 0x8439 698 #define MDIO_WC_REG_CL82_USERB1_RX_CTRL10 0x843a 699 #define MDIO_WC_REG_CL82_USERB1_RX_CTRL11 0x843b 700 #define MDIO_WC_REG_ETA_CL73_OUI1 0x8453 701 #define MDIO_WC_REG_ETA_CL73_OUI2 0x8454 702 #define MDIO_WC_REG_ETA_CL73_OUI3 0x8455 703 #define MDIO_WC_REG_ETA_CL73_LD_BAM_CODE 0x8456 704 #define MDIO_WC_REG_ETA_CL73_LD_UD_CODE 0x8457 705 #define MDIO_WC_REG_MICROBLK_CMD 0xffc2 706 #define MDIO_WC_REG_MICROBLK_DL_STATUS 0xffc5 707 #define MDIO_WC_REG_MICROBLK_CMD3 0xffcc 708 709 #define MDIO_WC_REG_AERBLK_AER 0xffde 710 #define MDIO_WC_REG_COMBO_IEEE0_MIICTRL 0xffe0 711 #define MDIO_WC_REG_COMBO_IEEE0_MIIISTAT 0xffe1 712 713 #define MDIO_WC0_XGXS_BLK2_LANE_RESET 0x810A 714 #define MDIO_WC0_XGXS_BLK2_LANE_RESET_RX_BITSHIFT 0 715 #define MDIO_WC0_XGXS_BLK2_LANE_RESET_TX_BITSHIFT 4 716 717 #define MDIO_WC0_XGXS_BLK6_XGXS_X2_CONTROL2 0x8141 718 719 #define DIGITAL5_ACTUAL_SPEED_TX_MASK 0x003f 720 721 /* 54618se */ 722 #define MDIO_REG_GPHY_MII_STATUS 0x1 723 #define MDIO_REG_GPHY_PHYID_LSB 0x3 724 #define MDIO_REG_GPHY_CL45_ADDR_REG 0xd 725 #define MDIO_REG_GPHY_CL45_REG_WRITE 0x4000 726 #define MDIO_REG_GPHY_CL45_REG_READ 0xc000 727 #define MDIO_REG_GPHY_CL45_DATA_REG 0xe 728 #define MDIO_REG_GPHY_EEE_RESOLVED 0x803e 729 #define MDIO_REG_GPHY_EXP_ACCESS_GATE 0x15 730 #define MDIO_REG_GPHY_EXP_ACCESS 0x17 731 #define MDIO_REG_GPHY_EXP_ACCESS_TOP 0xd00 732 #define MDIO_REG_GPHY_EXP_TOP_2K_BUF 0x40 733 #define MDIO_REG_GPHY_AUX_STATUS 0x19 734 #define MDIO_REG_INTR_STATUS 0x1a 735 #define MDIO_REG_INTR_MASK 0x1b 736 #define MDIO_REG_INTR_MASK_LINK_STATUS (0x1 << 1) 737 #define MDIO_REG_GPHY_SHADOW 0x1c 738 #define MDIO_REG_GPHY_SHADOW_LED_SEL1 (0x0d << 10) 739 #define MDIO_REG_GPHY_SHADOW_LED_SEL2 (0x0e << 10) 740 #define MDIO_REG_GPHY_SHADOW_WR_ENA (0x1 << 15) 741 #define MDIO_REG_GPHY_SHADOW_AUTO_DET_MED (0x1e << 10) 742 #define MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD (0x1 << 8) 743 744 745 typedef elink_status_t (*read_sfp_module_eeprom_func_p)(struct elink_phy *phy, 746 struct elink_params *params, 747 uint8_t dev_addr, uint16_t addr, uint8_t byte_cnt, 748 uint8_t *o_buf, uint8_t); 749 /********************************************************/ 750 #define ELINK_ETH_HLEN 14 751 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */ 752 #define ELINK_ETH_OVREHEAD (ELINK_ETH_HLEN + 8 + 8) 753 #define ELINK_ETH_MIN_PACKET_SIZE 60 754 #define ELINK_ETH_MAX_PACKET_SIZE 1500 755 #define ELINK_ETH_MAX_JUMBO_PACKET_SIZE 9600 756 #define ELINK_MDIO_ACCESS_TIMEOUT 1000 757 #define WC_LANE_MAX 4 758 #define I2C_SWITCH_WIDTH 2 759 #define I2C_BSC0 0 760 #define I2C_BSC1 1 761 #define I2C_WA_RETRY_CNT 3 762 #define I2C_WA_PWR_ITER (I2C_WA_RETRY_CNT - 1) 763 #define MCPR_IMC_COMMAND_READ_OP 1 764 #define MCPR_IMC_COMMAND_WRITE_OP 2 765 766 /* LED Blink rate that will achieve ~15.9Hz */ 767 #define LED_BLINK_RATE_VAL_E3 354 768 #define LED_BLINK_RATE_VAL_E1X_E2 480 769 /***********************************************************/ 770 /* Shortcut definitions */ 771 /***********************************************************/ 772 773 #define ELINK_NIG_LATCH_BC_ENABLE_MI_INT 0 774 775 #define ELINK_NIG_STATUS_EMAC0_MI_INT \ 776 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT 777 #define ELINK_NIG_STATUS_XGXS0_LINK10G \ 778 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G 779 #define ELINK_NIG_STATUS_XGXS0_LINK_STATUS \ 780 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS 781 #define ELINK_NIG_STATUS_XGXS0_LINK_STATUS_SIZE \ 782 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE 783 #define ELINK_NIG_STATUS_SERDES0_LINK_STATUS \ 784 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS 785 #define ELINK_NIG_MASK_MI_INT \ 786 NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT 787 #define ELINK_NIG_MASK_XGXS0_LINK10G \ 788 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G 789 #define ELINK_NIG_MASK_XGXS0_LINK_STATUS \ 790 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS 791 #define ELINK_NIG_MASK_SERDES0_LINK_STATUS \ 792 NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS 793 794 #define ELINK_MDIO_AN_CL73_OR_37_COMPLETE \ 795 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \ 796 MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE) 797 798 #define ELINK_XGXS_RESET_BITS \ 799 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW | \ 800 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ | \ 801 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN | \ 802 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \ 803 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB) 804 805 #define ELINK_SERDES_RESET_BITS \ 806 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \ 807 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ | \ 808 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN | \ 809 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD) 810 811 #define ELINK_AUTONEG_CL37 SHARED_HW_CFG_AN_ENABLE_CL37 812 #define ELINK_AUTONEG_CL73 SHARED_HW_CFG_AN_ENABLE_CL73 813 #define ELINK_AUTONEG_BAM SHARED_HW_CFG_AN_ENABLE_BAM 814 #define ELINK_AUTONEG_PARALLEL \ 815 SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION 816 #define ELINK_AUTONEG_SGMII_FIBER_AUTODET \ 817 SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT 818 #define ELINK_AUTONEG_REMOTE_PHY SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY 819 820 #define ELINK_GP_STATUS_PAUSE_RSOLUTION_TXSIDE \ 821 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE 822 #define ELINK_GP_STATUS_PAUSE_RSOLUTION_RXSIDE \ 823 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE 824 #define ELINK_GP_STATUS_SPEED_MASK \ 825 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK 826 #define ELINK_GP_STATUS_10M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M 827 #define ELINK_GP_STATUS_100M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M 828 #define ELINK_GP_STATUS_1G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G 829 #define ELINK_GP_STATUS_2_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G 830 #define ELINK_GP_STATUS_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G 831 #define ELINK_GP_STATUS_6G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G 832 #define ELINK_GP_STATUS_10G_HIG \ 833 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG 834 #define ELINK_GP_STATUS_10G_CX4 \ 835 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4 836 #define ELINK_GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX 837 #define ELINK_GP_STATUS_10G_KX4 \ 838 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4 839 #define ELINK_GP_STATUS_10G_KR MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR 840 #define ELINK_GP_STATUS_10G_XFI MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI 841 #define ELINK_GP_STATUS_20G_DXGXS MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS 842 #define ELINK_GP_STATUS_10G_SFI MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI 843 #define ELINK_GP_STATUS_20G_KR2 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_KR2 844 #define ELINK_LINK_10THD LINK_STATUS_SPEED_AND_DUPLEX_10THD 845 #define ELINK_LINK_10TFD LINK_STATUS_SPEED_AND_DUPLEX_10TFD 846 #define ELINK_LINK_100TXHD LINK_STATUS_SPEED_AND_DUPLEX_100TXHD 847 #define ELINK_LINK_100T4 LINK_STATUS_SPEED_AND_DUPLEX_100T4 848 #define ELINK_LINK_100TXFD LINK_STATUS_SPEED_AND_DUPLEX_100TXFD 849 #define ELINK_LINK_1000THD LINK_STATUS_SPEED_AND_DUPLEX_1000THD 850 #define ELINK_LINK_1000TFD LINK_STATUS_SPEED_AND_DUPLEX_1000TFD 851 #define ELINK_LINK_1000XFD LINK_STATUS_SPEED_AND_DUPLEX_1000XFD 852 #define ELINK_LINK_2500THD LINK_STATUS_SPEED_AND_DUPLEX_2500THD 853 #define ELINK_LINK_2500TFD LINK_STATUS_SPEED_AND_DUPLEX_2500TFD 854 #define ELINK_LINK_2500XFD LINK_STATUS_SPEED_AND_DUPLEX_2500XFD 855 #define ELINK_LINK_10GTFD LINK_STATUS_SPEED_AND_DUPLEX_10GTFD 856 #define ELINK_LINK_10GXFD LINK_STATUS_SPEED_AND_DUPLEX_10GXFD 857 #define ELINK_LINK_20GTFD LINK_STATUS_SPEED_AND_DUPLEX_20GTFD 858 #define ELINK_LINK_20GXFD LINK_STATUS_SPEED_AND_DUPLEX_20GXFD 859 860 #define ELINK_LINK_UPDATE_MASK \ 861 (LINK_STATUS_SPEED_AND_DUPLEX_MASK | \ 862 LINK_STATUS_LINK_UP | \ 863 LINK_STATUS_PHYSICAL_LINK_FLAG | \ 864 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE | \ 865 LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK | \ 866 LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK | \ 867 LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK | \ 868 LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE | \ 869 LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE) 870 871 #define ELINK_SFP_EEPROM_CON_TYPE_ADDR 0x2 872 #define ELINK_SFP_EEPROM_CON_TYPE_VAL_LC 0x7 873 #define ELINK_SFP_EEPROM_CON_TYPE_VAL_COPPER 0x21 874 #define ELINK_SFP_EEPROM_CON_TYPE_VAL_RJ45 0x22 875 876 877 #define ELINK_SFP_EEPROM_COMP_CODE_ADDR 0x3 878 #define ELINK_SFP_EEPROM_COMP_CODE_SR_MASK (1<<4) 879 #define ELINK_SFP_EEPROM_COMP_CODE_LR_MASK (1<<5) 880 #define ELINK_SFP_EEPROM_COMP_CODE_LRM_MASK (1<<6) 881 882 #define ELINK_SFP_EEPROM_FC_TX_TECH_ADDR 0x8 883 #define ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4 884 #define ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE 0x8 885 886 #define ELINK_SFP_EEPROM_OPTIONS_ADDR 0x40 887 #define ELINK_SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1 888 #define ELINK_SFP_EEPROM_OPTIONS_SIZE 2 889 890 #define ELINK_EDC_MODE_LINEAR 0x0022 891 #define ELINK_EDC_MODE_LIMITING 0x0044 892 #define ELINK_EDC_MODE_PASSIVE_DAC 0x0055 893 #define ELINK_EDC_MODE_ACTIVE_DAC 0x0066 894 895 /* ETS defines*/ 896 #define DCBX_INVALID_COS (0xFF) 897 898 #define ELINK_ETS_BW_LIMIT_CREDIT_UPPER_BOUND (0x5000) 899 #define ELINK_ETS_BW_LIMIT_CREDIT_WEIGHT (0x5000) 900 #define ELINK_ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS (1360) 901 #define ELINK_ETS_E3B0_NIG_MIN_W_VAL_20GBPS (2720) 902 #define ELINK_ETS_E3B0_PBF_MIN_W_VAL (10000) 903 904 #define ELINK_MAX_PACKET_SIZE (9700) 905 #define MAX_KR_LINK_RETRY 4 906 907 /**********************************************************/ 908 /* INTERFACE */ 909 /**********************************************************/ 910 911 #define CL22_WR_OVER_CL45(_sc, _phy, _bank, _addr, _val) \ 912 elink_cl45_write(_sc, _phy, \ 913 (_phy)->def_md_devad, \ 914 (_bank + (_addr & 0xf)), \ 915 _val) 916 917 #define CL22_RD_OVER_CL45(_sc, _phy, _bank, _addr, _val) \ 918 elink_cl45_read(_sc, _phy, \ 919 (_phy)->def_md_devad, \ 920 (_bank + (_addr & 0xf)), \ 921 _val) 922 923 static uint32_t elink_bits_en(struct bxe_softc *sc, uint32_t reg, uint32_t bits) 924 { 925 uint32_t val = REG_RD(sc, reg); 926 927 val |= bits; 928 REG_WR(sc, reg, val); 929 return val; 930 } 931 932 static uint32_t elink_bits_dis(struct bxe_softc *sc, uint32_t reg, uint32_t bits) 933 { 934 uint32_t val = REG_RD(sc, reg); 935 936 val &= ~bits; 937 REG_WR(sc, reg, val); 938 return val; 939 } 940 941 /* 942 * elink_check_lfa - This function checks if link reinitialization is required, 943 * or link flap can be avoided. 944 * 945 * @params: link parameters 946 * Returns 0 if Link Flap Avoidance conditions are met otherwise, the failed 947 * condition code. 948 */ 949 static int elink_check_lfa(struct elink_params *params) 950 { 951 uint32_t link_status, cfg_idx, lfa_mask, cfg_size; 952 uint32_t cur_speed_cap_mask, cur_req_fc_auto_adv, additional_config; 953 uint32_t saved_val, req_val, eee_status; 954 struct bxe_softc *sc = params->sc; 955 956 additional_config = 957 REG_RD(sc, params->lfa_base + 958 offsetof(struct shmem_lfa, additional_config)); 959 960 /* NOTE: must be first condition checked - 961 * to verify DCC bit is cleared in any case! 962 */ 963 if (additional_config & NO_LFA_DUE_TO_DCC_MASK) { 964 ELINK_DEBUG_P0(sc, "No LFA due to DCC flap after clp exit\n"); 965 REG_WR(sc, params->lfa_base + 966 offsetof(struct shmem_lfa, additional_config), 967 additional_config & ~NO_LFA_DUE_TO_DCC_MASK); 968 return LFA_DCC_LFA_DISABLED; 969 } 970 971 /* Verify that link is up */ 972 link_status = REG_RD(sc, params->shmem_base + 973 offsetof(struct shmem_region, 974 port_mb[params->port].link_status)); 975 if (!(link_status & LINK_STATUS_LINK_UP)) 976 return LFA_LINK_DOWN; 977 978 /* if loaded after BOOT from SAN, don't flap the link in any case and 979 * rely on link set by preboot driver 980 */ 981 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_BOOT_FROM_SAN) 982 return 0; 983 984 /* Verify that loopback mode is not set */ 985 if (params->loopback_mode) 986 return LFA_LOOPBACK_ENABLED; 987 988 /* Verify that MFW supports LFA */ 989 if (!params->lfa_base) 990 return LFA_MFW_IS_TOO_OLD; 991 992 if (params->num_phys == 3) { 993 cfg_size = 2; 994 lfa_mask = 0xffffffff; 995 } else { 996 cfg_size = 1; 997 lfa_mask = 0xffff; 998 } 999 1000 /* Compare Duplex */ 1001 saved_val = REG_RD(sc, params->lfa_base + 1002 offsetof(struct shmem_lfa, req_duplex)); 1003 req_val = params->req_duplex[0] | (params->req_duplex[1] << 16); 1004 if ((saved_val & lfa_mask) != (req_val & lfa_mask)) { 1005 ELINK_DEBUG_P2(sc, "Duplex mismatch %x vs. %x\n", 1006 (saved_val & lfa_mask), (req_val & lfa_mask)); 1007 return LFA_DUPLEX_MISMATCH; 1008 } 1009 /* Compare Flow Control */ 1010 saved_val = REG_RD(sc, params->lfa_base + 1011 offsetof(struct shmem_lfa, req_flow_ctrl)); 1012 req_val = params->req_flow_ctrl[0] | (params->req_flow_ctrl[1] << 16); 1013 if ((saved_val & lfa_mask) != (req_val & lfa_mask)) { 1014 ELINK_DEBUG_P2(sc, "Flow control mismatch %x vs. %x\n", 1015 (saved_val & lfa_mask), (req_val & lfa_mask)); 1016 return LFA_FLOW_CTRL_MISMATCH; 1017 } 1018 /* Compare Link Speed */ 1019 saved_val = REG_RD(sc, params->lfa_base + 1020 offsetof(struct shmem_lfa, req_line_speed)); 1021 req_val = params->req_line_speed[0] | (params->req_line_speed[1] << 16); 1022 if ((saved_val & lfa_mask) != (req_val & lfa_mask)) { 1023 ELINK_DEBUG_P2(sc, "Link speed mismatch %x vs. %x\n", 1024 (saved_val & lfa_mask), (req_val & lfa_mask)); 1025 return LFA_LINK_SPEED_MISMATCH; 1026 } 1027 1028 for (cfg_idx = 0; cfg_idx < cfg_size; cfg_idx++) { 1029 cur_speed_cap_mask = REG_RD(sc, params->lfa_base + 1030 offsetof(struct shmem_lfa, 1031 speed_cap_mask[cfg_idx])); 1032 1033 if (cur_speed_cap_mask != params->speed_cap_mask[cfg_idx]) { 1034 ELINK_DEBUG_P2(sc, "Speed Cap mismatch %x vs. %x\n", 1035 cur_speed_cap_mask, 1036 params->speed_cap_mask[cfg_idx]); 1037 return LFA_SPEED_CAP_MISMATCH; 1038 } 1039 } 1040 1041 cur_req_fc_auto_adv = 1042 REG_RD(sc, params->lfa_base + 1043 offsetof(struct shmem_lfa, additional_config)) & 1044 REQ_FC_AUTO_ADV_MASK; 1045 1046 if ((uint16_t)cur_req_fc_auto_adv != params->req_fc_auto_adv) { 1047 ELINK_DEBUG_P2(sc, "Flow Ctrl AN mismatch %x vs. %x\n", 1048 cur_req_fc_auto_adv, params->req_fc_auto_adv); 1049 return LFA_FLOW_CTRL_MISMATCH; 1050 } 1051 1052 eee_status = REG_RD(sc, params->shmem2_base + 1053 offsetof(struct shmem2_region, 1054 eee_status[params->port])); 1055 1056 if (((eee_status & SHMEM_EEE_LPI_REQUESTED_BIT) ^ 1057 (params->eee_mode & ELINK_EEE_MODE_ENABLE_LPI)) || 1058 ((eee_status & SHMEM_EEE_REQUESTED_BIT) ^ 1059 (params->eee_mode & ELINK_EEE_MODE_ADV_LPI))) { 1060 ELINK_DEBUG_P2(sc, "EEE mismatch %x vs. %x\n", params->eee_mode, 1061 eee_status); 1062 return LFA_EEE_MISMATCH; 1063 } 1064 1065 /* LFA conditions are met */ 1066 return 0; 1067 } 1068 /******************************************************************/ 1069 /* EPIO/GPIO section */ 1070 /******************************************************************/ 1071 static void elink_get_epio(struct bxe_softc *sc, uint32_t epio_pin, uint32_t *en) 1072 { 1073 uint32_t epio_mask, gp_oenable; 1074 *en = 0; 1075 /* Sanity check */ 1076 if (epio_pin > 31) { 1077 ELINK_DEBUG_P1(sc, "Invalid EPIO pin %d to get\n", epio_pin); 1078 return; 1079 } 1080 1081 epio_mask = 1 << epio_pin; 1082 /* Set this EPIO to output */ 1083 gp_oenable = REG_RD(sc, MCP_REG_MCPR_GP_OENABLE); 1084 REG_WR(sc, MCP_REG_MCPR_GP_OENABLE, gp_oenable & ~epio_mask); 1085 1086 *en = (REG_RD(sc, MCP_REG_MCPR_GP_INPUTS) & epio_mask) >> epio_pin; 1087 } 1088 static void elink_set_epio(struct bxe_softc *sc, uint32_t epio_pin, uint32_t en) 1089 { 1090 uint32_t epio_mask, gp_output, gp_oenable; 1091 1092 /* Sanity check */ 1093 if (epio_pin > 31) { 1094 ELINK_DEBUG_P1(sc, "Invalid EPIO pin %d to set\n", epio_pin); 1095 return; 1096 } 1097 ELINK_DEBUG_P2(sc, "Setting EPIO pin %d to %d\n", epio_pin, en); 1098 epio_mask = 1 << epio_pin; 1099 /* Set this EPIO to output */ 1100 gp_output = REG_RD(sc, MCP_REG_MCPR_GP_OUTPUTS); 1101 if (en) 1102 gp_output |= epio_mask; 1103 else 1104 gp_output &= ~epio_mask; 1105 1106 REG_WR(sc, MCP_REG_MCPR_GP_OUTPUTS, gp_output); 1107 1108 /* Set the value for this EPIO */ 1109 gp_oenable = REG_RD(sc, MCP_REG_MCPR_GP_OENABLE); 1110 REG_WR(sc, MCP_REG_MCPR_GP_OENABLE, gp_oenable | epio_mask); 1111 } 1112 1113 static void elink_set_cfg_pin(struct bxe_softc *sc, uint32_t pin_cfg, uint32_t val) 1114 { 1115 if (pin_cfg == PIN_CFG_NA) 1116 return; 1117 if (pin_cfg >= PIN_CFG_EPIO0) { 1118 elink_set_epio(sc, pin_cfg - PIN_CFG_EPIO0, val); 1119 } else { 1120 uint8_t gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3; 1121 uint8_t gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2; 1122 elink_cb_gpio_write(sc, gpio_num, (uint8_t)val, gpio_port); 1123 } 1124 } 1125 1126 static uint32_t elink_get_cfg_pin(struct bxe_softc *sc, uint32_t pin_cfg, uint32_t *val) 1127 { 1128 if (pin_cfg == PIN_CFG_NA) 1129 return ELINK_STATUS_ERROR; 1130 if (pin_cfg >= PIN_CFG_EPIO0) { 1131 elink_get_epio(sc, pin_cfg - PIN_CFG_EPIO0, val); 1132 } else { 1133 uint8_t gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3; 1134 uint8_t gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2; 1135 *val = elink_cb_gpio_read(sc, gpio_num, gpio_port); 1136 } 1137 return ELINK_STATUS_OK; 1138 1139 } 1140 /******************************************************************/ 1141 /* ETS section */ 1142 /******************************************************************/ 1143 static void elink_ets_e2e3a0_disabled(struct elink_params *params) 1144 { 1145 /* ETS disabled configuration*/ 1146 struct bxe_softc *sc = params->sc; 1147 1148 ELINK_DEBUG_P0(sc, "ETS E2E3 disabled configuration\n"); 1149 1150 /* mapping between entry priority to client number (0,1,2 -debug and 1151 * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST) 1152 * 3bits client num. 1153 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0 1154 * cos1-100 cos0-011 dbg1-010 dbg0-001 MCP-000 1155 */ 1156 1157 REG_WR(sc, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, 0x4688); 1158 /* Bitmap of 5bits length. Each bit specifies whether the entry behaves 1159 * as strict. Bits 0,1,2 - debug and management entries, 3 - 1160 * COS0 entry, 4 - COS1 entry. 1161 * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT 1162 * bit4 bit3 bit2 bit1 bit0 1163 * MCP and debug are strict 1164 */ 1165 1166 REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7); 1167 /* defines which entries (clients) are subjected to WFQ arbitration */ 1168 REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0); 1169 /* For strict priority entries defines the number of consecutive 1170 * slots for the highest priority. 1171 */ 1172 REG_WR(sc, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100); 1173 /* mapping between the CREDIT_WEIGHT registers and actual client 1174 * numbers 1175 */ 1176 REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0); 1177 REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0); 1178 REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0); 1179 1180 REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, 0); 1181 REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, 0); 1182 REG_WR(sc, PBF_REG_HIGH_PRIORITY_COS_NUM, 0); 1183 /* ETS mode disable */ 1184 REG_WR(sc, PBF_REG_ETS_ENABLED, 0); 1185 /* If ETS mode is enabled (there is no strict priority) defines a WFQ 1186 * weight for COS0/COS1. 1187 */ 1188 REG_WR(sc, PBF_REG_COS0_WEIGHT, 0x2710); 1189 REG_WR(sc, PBF_REG_COS1_WEIGHT, 0x2710); 1190 /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter */ 1191 REG_WR(sc, PBF_REG_COS0_UPPER_BOUND, 0x989680); 1192 REG_WR(sc, PBF_REG_COS1_UPPER_BOUND, 0x989680); 1193 /* Defines the number of consecutive slots for the strict priority */ 1194 REG_WR(sc, PBF_REG_NUM_STRICT_ARB_SLOTS, 0); 1195 } 1196 /****************************************************************************** 1197 * Description: 1198 * Getting min_w_val will be set according to line speed . 1199 *. 1200 ******************************************************************************/ 1201 static uint32_t elink_ets_get_min_w_val_nig(const struct elink_vars *vars) 1202 { 1203 uint32_t min_w_val = 0; 1204 /* Calculate min_w_val.*/ 1205 if (vars->link_up) { 1206 if (vars->line_speed == ELINK_SPEED_20000) 1207 min_w_val = ELINK_ETS_E3B0_NIG_MIN_W_VAL_20GBPS; 1208 else 1209 min_w_val = ELINK_ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS; 1210 } else 1211 min_w_val = ELINK_ETS_E3B0_NIG_MIN_W_VAL_20GBPS; 1212 /* If the link isn't up (static configuration for example ) The 1213 * link will be according to 20GBPS. 1214 */ 1215 return min_w_val; 1216 } 1217 /****************************************************************************** 1218 * Description: 1219 * Getting credit upper bound form min_w_val. 1220 *. 1221 ******************************************************************************/ 1222 static uint32_t elink_ets_get_credit_upper_bound(const uint32_t min_w_val) 1223 { 1224 const uint32_t credit_upper_bound = (uint32_t)ELINK_MAXVAL((150 * min_w_val), 1225 ELINK_MAX_PACKET_SIZE); 1226 return credit_upper_bound; 1227 } 1228 /****************************************************************************** 1229 * Description: 1230 * Set credit upper bound for NIG. 1231 *. 1232 ******************************************************************************/ 1233 static void elink_ets_e3b0_set_credit_upper_bound_nig( 1234 const struct elink_params *params, 1235 const uint32_t min_w_val) 1236 { 1237 struct bxe_softc *sc = params->sc; 1238 const uint8_t port = params->port; 1239 const uint32_t credit_upper_bound = 1240 elink_ets_get_credit_upper_bound(min_w_val); 1241 1242 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_0 : 1243 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, credit_upper_bound); 1244 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_1 : 1245 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, credit_upper_bound); 1246 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_2 : 1247 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_2, credit_upper_bound); 1248 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_3 : 1249 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_3, credit_upper_bound); 1250 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_4 : 1251 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_4, credit_upper_bound); 1252 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_5 : 1253 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_5, credit_upper_bound); 1254 1255 if (!port) { 1256 REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_6, 1257 credit_upper_bound); 1258 REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_7, 1259 credit_upper_bound); 1260 REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_8, 1261 credit_upper_bound); 1262 } 1263 } 1264 /****************************************************************************** 1265 * Description: 1266 * Will return the NIG ETS registers to init values.Except 1267 * credit_upper_bound. 1268 * That isn't used in this configuration (No WFQ is enabled) and will be 1269 * configured acording to spec 1270 *. 1271 ******************************************************************************/ 1272 static void elink_ets_e3b0_nig_disabled(const struct elink_params *params, 1273 const struct elink_vars *vars) 1274 { 1275 struct bxe_softc *sc = params->sc; 1276 const uint8_t port = params->port; 1277 const uint32_t min_w_val = elink_ets_get_min_w_val_nig(vars); 1278 /* Mapping between entry priority to client number (0,1,2 -debug and 1279 * management clients, 3 - COS0 client, 4 - COS1, ... 8 - 1280 * COS5)(HIGHEST) 4bits client num.TODO_ETS - Should be done by 1281 * reset value or init tool 1282 */ 1283 if (port) { 1284 REG_WR(sc, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB, 0x543210); 1285 REG_WR(sc, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_MSB, 0x0); 1286 } else { 1287 REG_WR(sc, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB, 0x76543210); 1288 REG_WR(sc, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB, 0x8); 1289 } 1290 /* For strict priority entries defines the number of consecutive 1291 * slots for the highest priority. 1292 */ 1293 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS : 1294 NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100); 1295 /* Mapping between the CREDIT_WEIGHT registers and actual client 1296 * numbers 1297 */ 1298 if (port) { 1299 /*Port 1 has 6 COS*/ 1300 REG_WR(sc, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB, 0x210543); 1301 REG_WR(sc, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x0); 1302 } else { 1303 /*Port 0 has 9 COS*/ 1304 REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_LSB, 1305 0x43210876); 1306 REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x5); 1307 } 1308 1309 /* Bitmap of 5bits length. Each bit specifies whether the entry behaves 1310 * as strict. Bits 0,1,2 - debug and management entries, 3 - 1311 * COS0 entry, 4 - COS1 entry. 1312 * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT 1313 * bit4 bit3 bit2 bit1 bit0 1314 * MCP and debug are strict 1315 */ 1316 if (port) 1317 REG_WR(sc, NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT, 0x3f); 1318 else 1319 REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1ff); 1320 /* defines which entries (clients) are subjected to WFQ arbitration */ 1321 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ : 1322 NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0); 1323 1324 /* Please notice the register address are note continuous and a 1325 * for here is note appropriate.In 2 port mode port0 only COS0-5 1326 * can be used. DEBUG1,DEBUG1,MGMT are never used for WFQ* In 4 1327 * port mode port1 only COS0-2 can be used. DEBUG1,DEBUG1,MGMT 1328 * are never used for WFQ 1329 */ 1330 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 : 1331 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0x0); 1332 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 : 1333 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0x0); 1334 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 : 1335 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2, 0x0); 1336 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_3 : 1337 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3, 0x0); 1338 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_4 : 1339 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4, 0x0); 1340 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_5 : 1341 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5, 0x0); 1342 if (!port) { 1343 REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_6, 0x0); 1344 REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_7, 0x0); 1345 REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_8, 0x0); 1346 } 1347 1348 elink_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val); 1349 } 1350 /****************************************************************************** 1351 * Description: 1352 * Set credit upper bound for PBF. 1353 *. 1354 ******************************************************************************/ 1355 static void elink_ets_e3b0_set_credit_upper_bound_pbf( 1356 const struct elink_params *params, 1357 const uint32_t min_w_val) 1358 { 1359 struct bxe_softc *sc = params->sc; 1360 const uint32_t credit_upper_bound = 1361 elink_ets_get_credit_upper_bound(min_w_val); 1362 const uint8_t port = params->port; 1363 uint32_t base_upper_bound = 0; 1364 uint8_t max_cos = 0; 1365 uint8_t i = 0; 1366 /* In 2 port mode port0 has COS0-5 that can be used for WFQ.In 4 1367 * port mode port1 has COS0-2 that can be used for WFQ. 1368 */ 1369 if (!port) { 1370 base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P0; 1371 max_cos = ELINK_DCBX_E3B0_MAX_NUM_COS_PORT0; 1372 } else { 1373 base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P1; 1374 max_cos = ELINK_DCBX_E3B0_MAX_NUM_COS_PORT1; 1375 } 1376 1377 for (i = 0; i < max_cos; i++) 1378 REG_WR(sc, base_upper_bound + (i << 2), credit_upper_bound); 1379 } 1380 1381 /****************************************************************************** 1382 * Description: 1383 * Will return the PBF ETS registers to init values.Except 1384 * credit_upper_bound. 1385 * That isn't used in this configuration (No WFQ is enabled) and will be 1386 * configured acording to spec 1387 *. 1388 ******************************************************************************/ 1389 static void elink_ets_e3b0_pbf_disabled(const struct elink_params *params) 1390 { 1391 struct bxe_softc *sc = params->sc; 1392 const uint8_t port = params->port; 1393 const uint32_t min_w_val_pbf = ELINK_ETS_E3B0_PBF_MIN_W_VAL; 1394 uint8_t i = 0; 1395 uint32_t base_weight = 0; 1396 uint8_t max_cos = 0; 1397 1398 /* Mapping between entry priority to client number 0 - COS0 1399 * client, 2 - COS1, ... 5 - COS5)(HIGHEST) 4bits client num. 1400 * TODO_ETS - Should be done by reset value or init tool 1401 */ 1402 if (port) 1403 /* 0x688 (|011|0 10|00 1|000) */ 1404 REG_WR(sc, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , 0x688); 1405 else 1406 /* (10 1|100 |011|0 10|00 1|000) */ 1407 REG_WR(sc, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , 0x2C688); 1408 1409 /* TODO_ETS - Should be done by reset value or init tool */ 1410 if (port) 1411 /* 0x688 (|011|0 10|00 1|000)*/ 1412 REG_WR(sc, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1, 0x688); 1413 else 1414 /* 0x2C688 (10 1|100 |011|0 10|00 1|000) */ 1415 REG_WR(sc, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0, 0x2C688); 1416 1417 REG_WR(sc, (port) ? PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1 : 1418 PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P0 , 0x100); 1419 1420 1421 REG_WR(sc, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 : 1422 PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , 0); 1423 1424 REG_WR(sc, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 : 1425 PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0 , 0); 1426 /* In 2 port mode port0 has COS0-5 that can be used for WFQ. 1427 * In 4 port mode port1 has COS0-2 that can be used for WFQ. 1428 */ 1429 if (!port) { 1430 base_weight = PBF_REG_COS0_WEIGHT_P0; 1431 max_cos = ELINK_DCBX_E3B0_MAX_NUM_COS_PORT0; 1432 } else { 1433 base_weight = PBF_REG_COS0_WEIGHT_P1; 1434 max_cos = ELINK_DCBX_E3B0_MAX_NUM_COS_PORT1; 1435 } 1436 1437 for (i = 0; i < max_cos; i++) 1438 REG_WR(sc, base_weight + (0x4 * i), 0); 1439 1440 elink_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf); 1441 } 1442 /****************************************************************************** 1443 * Description: 1444 * E3B0 disable will return basicly the values to init values. 1445 *. 1446 ******************************************************************************/ 1447 static elink_status_t elink_ets_e3b0_disabled(const struct elink_params *params, 1448 const struct elink_vars *vars) 1449 { 1450 struct bxe_softc *sc = params->sc; 1451 1452 if (!CHIP_IS_E3B0(sc)) { 1453 ELINK_DEBUG_P0(sc, 1454 "elink_ets_e3b0_disabled the chip isn't E3B0\n"); 1455 return ELINK_STATUS_ERROR; 1456 } 1457 1458 elink_ets_e3b0_nig_disabled(params, vars); 1459 1460 elink_ets_e3b0_pbf_disabled(params); 1461 1462 return ELINK_STATUS_OK; 1463 } 1464 1465 /****************************************************************************** 1466 * Description: 1467 * Disable will return basicly the values to init values. 1468 * 1469 ******************************************************************************/ 1470 elink_status_t elink_ets_disabled(struct elink_params *params, 1471 struct elink_vars *vars) 1472 { 1473 struct bxe_softc *sc = params->sc; 1474 elink_status_t elink_status = ELINK_STATUS_OK; 1475 1476 if ((CHIP_IS_E2(sc)) || (CHIP_IS_E3A0(sc))) 1477 elink_ets_e2e3a0_disabled(params); 1478 else if (CHIP_IS_E3B0(sc)) 1479 elink_status = elink_ets_e3b0_disabled(params, vars); 1480 else { 1481 ELINK_DEBUG_P0(sc, "elink_ets_disabled - chip not supported\n"); 1482 return ELINK_STATUS_ERROR; 1483 } 1484 1485 return elink_status; 1486 } 1487 1488 /****************************************************************************** 1489 * Description 1490 * Set the COS mappimg to SP and BW until this point all the COS are not 1491 * set as SP or BW. 1492 ******************************************************************************/ 1493 static elink_status_t elink_ets_e3b0_cli_map(const struct elink_params *params, 1494 const struct elink_ets_params *ets_params, 1495 const uint8_t cos_sp_bitmap, 1496 const uint8_t cos_bw_bitmap) 1497 { 1498 struct bxe_softc *sc = params->sc; 1499 const uint8_t port = params->port; 1500 const uint8_t nig_cli_sp_bitmap = 0x7 | (cos_sp_bitmap << 3); 1501 const uint8_t pbf_cli_sp_bitmap = cos_sp_bitmap; 1502 const uint8_t nig_cli_subject2wfq_bitmap = cos_bw_bitmap << 3; 1503 const uint8_t pbf_cli_subject2wfq_bitmap = cos_bw_bitmap; 1504 1505 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT : 1506 NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, nig_cli_sp_bitmap); 1507 1508 REG_WR(sc, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 : 1509 PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , pbf_cli_sp_bitmap); 1510 1511 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ : 1512 NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 1513 nig_cli_subject2wfq_bitmap); 1514 1515 REG_WR(sc, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 : 1516 PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0, 1517 pbf_cli_subject2wfq_bitmap); 1518 1519 return ELINK_STATUS_OK; 1520 } 1521 1522 /****************************************************************************** 1523 * Description: 1524 * This function is needed because NIG ARB_CREDIT_WEIGHT_X are 1525 * not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable. 1526 ******************************************************************************/ 1527 static elink_status_t elink_ets_e3b0_set_cos_bw(struct bxe_softc *sc, 1528 const uint8_t cos_entry, 1529 const uint32_t min_w_val_nig, 1530 const uint32_t min_w_val_pbf, 1531 const uint16_t total_bw, 1532 const uint8_t bw, 1533 const uint8_t port) 1534 { 1535 uint32_t nig_reg_adress_crd_weight = 0; 1536 uint32_t pbf_reg_adress_crd_weight = 0; 1537 /* Calculate and set BW for this COS - use 1 instead of 0 for BW */ 1538 const uint32_t cos_bw_nig = ((bw ? bw : 1) * min_w_val_nig) / total_bw; 1539 const uint32_t cos_bw_pbf = ((bw ? bw : 1) * min_w_val_pbf) / total_bw; 1540 1541 switch (cos_entry) { 1542 case 0: 1543 nig_reg_adress_crd_weight = 1544 (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 : 1545 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0; 1546 pbf_reg_adress_crd_weight = (port) ? 1547 PBF_REG_COS0_WEIGHT_P1 : PBF_REG_COS0_WEIGHT_P0; 1548 break; 1549 case 1: 1550 nig_reg_adress_crd_weight = (port) ? 1551 NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 : 1552 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1; 1553 pbf_reg_adress_crd_weight = (port) ? 1554 PBF_REG_COS1_WEIGHT_P1 : PBF_REG_COS1_WEIGHT_P0; 1555 break; 1556 case 2: 1557 nig_reg_adress_crd_weight = (port) ? 1558 NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 : 1559 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2; 1560 1561 pbf_reg_adress_crd_weight = (port) ? 1562 PBF_REG_COS2_WEIGHT_P1 : PBF_REG_COS2_WEIGHT_P0; 1563 break; 1564 case 3: 1565 if (port) 1566 return ELINK_STATUS_ERROR; 1567 nig_reg_adress_crd_weight = 1568 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3; 1569 pbf_reg_adress_crd_weight = 1570 PBF_REG_COS3_WEIGHT_P0; 1571 break; 1572 case 4: 1573 if (port) 1574 return ELINK_STATUS_ERROR; 1575 nig_reg_adress_crd_weight = 1576 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4; 1577 pbf_reg_adress_crd_weight = PBF_REG_COS4_WEIGHT_P0; 1578 break; 1579 case 5: 1580 if (port) 1581 return ELINK_STATUS_ERROR; 1582 nig_reg_adress_crd_weight = 1583 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5; 1584 pbf_reg_adress_crd_weight = PBF_REG_COS5_WEIGHT_P0; 1585 break; 1586 } 1587 1588 REG_WR(sc, nig_reg_adress_crd_weight, cos_bw_nig); 1589 1590 REG_WR(sc, pbf_reg_adress_crd_weight, cos_bw_pbf); 1591 1592 return ELINK_STATUS_OK; 1593 } 1594 /****************************************************************************** 1595 * Description: 1596 * Calculate the total BW.A value of 0 isn't legal. 1597 * 1598 ******************************************************************************/ 1599 static elink_status_t elink_ets_e3b0_get_total_bw( 1600 const struct elink_params *params, 1601 struct elink_ets_params *ets_params, 1602 uint16_t *total_bw) 1603 { 1604 struct bxe_softc *sc = params->sc; 1605 uint8_t cos_idx = 0; 1606 uint8_t is_bw_cos_exist = 0; 1607 1608 *total_bw = 0 ; 1609 /* Calculate total BW requested */ 1610 for (cos_idx = 0; cos_idx < ets_params->num_of_cos; cos_idx++) { 1611 if (ets_params->cos[cos_idx].state == elink_cos_state_bw) { 1612 is_bw_cos_exist = 1; 1613 if (!ets_params->cos[cos_idx].params.bw_params.bw) { 1614 ELINK_DEBUG_P0(sc, "elink_ets_E3B0_config BW" 1615 "was set to 0\n"); 1616 /* This is to prevent a state when ramrods 1617 * can't be sent 1618 */ 1619 ets_params->cos[cos_idx].params.bw_params.bw 1620 = 1; 1621 } 1622 *total_bw += 1623 ets_params->cos[cos_idx].params.bw_params.bw; 1624 } 1625 } 1626 1627 /* Check total BW is valid */ 1628 if ((is_bw_cos_exist == 1) && (*total_bw != 100)) { 1629 if (*total_bw == 0) { 1630 ELINK_DEBUG_P0(sc, 1631 "elink_ets_E3B0_config total BW shouldn't be 0\n"); 1632 return ELINK_STATUS_ERROR; 1633 } 1634 ELINK_DEBUG_P0(sc, 1635 "elink_ets_E3B0_config total BW should be 100\n"); 1636 /* We can handle a case whre the BW isn't 100 this can happen 1637 * if the TC are joined. 1638 */ 1639 } 1640 return ELINK_STATUS_OK; 1641 } 1642 1643 /****************************************************************************** 1644 * Description: 1645 * Invalidate all the sp_pri_to_cos. 1646 * 1647 ******************************************************************************/ 1648 static void elink_ets_e3b0_sp_pri_to_cos_init(uint8_t *sp_pri_to_cos) 1649 { 1650 uint8_t pri = 0; 1651 for (pri = 0; pri < ELINK_DCBX_MAX_NUM_COS; pri++) 1652 sp_pri_to_cos[pri] = DCBX_INVALID_COS; 1653 } 1654 /****************************************************************************** 1655 * Description: 1656 * Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers 1657 * according to sp_pri_to_cos. 1658 * 1659 ******************************************************************************/ 1660 static elink_status_t elink_ets_e3b0_sp_pri_to_cos_set(const struct elink_params *params, 1661 uint8_t *sp_pri_to_cos, const uint8_t pri, 1662 const uint8_t cos_entry) 1663 { 1664 struct bxe_softc *sc = params->sc; 1665 const uint8_t port = params->port; 1666 const uint8_t max_num_of_cos = (port) ? ELINK_DCBX_E3B0_MAX_NUM_COS_PORT1 : 1667 ELINK_DCBX_E3B0_MAX_NUM_COS_PORT0; 1668 1669 if (pri >= max_num_of_cos) { 1670 ELINK_DEBUG_P0(sc, "elink_ets_e3b0_sp_pri_to_cos_set invalid " 1671 "parameter Illegal strict priority\n"); 1672 return ELINK_STATUS_ERROR; 1673 } 1674 1675 if (sp_pri_to_cos[pri] != DCBX_INVALID_COS) { 1676 ELINK_DEBUG_P0(sc, "elink_ets_e3b0_sp_pri_to_cos_set invalid " 1677 "parameter There can't be two COS's with " 1678 "the same strict pri\n"); 1679 return ELINK_STATUS_ERROR; 1680 } 1681 1682 sp_pri_to_cos[pri] = cos_entry; 1683 return ELINK_STATUS_OK; 1684 1685 } 1686 1687 /****************************************************************************** 1688 * Description: 1689 * Returns the correct value according to COS and priority in 1690 * the sp_pri_cli register. 1691 * 1692 ******************************************************************************/ 1693 static uint64_t elink_e3b0_sp_get_pri_cli_reg(const uint8_t cos, const uint8_t cos_offset, 1694 const uint8_t pri_set, 1695 const uint8_t pri_offset, 1696 const uint8_t entry_size) 1697 { 1698 uint64_t pri_cli_nig = 0; 1699 pri_cli_nig = ((uint64_t)(cos + cos_offset)) << (entry_size * 1700 (pri_set + pri_offset)); 1701 1702 return pri_cli_nig; 1703 } 1704 /****************************************************************************** 1705 * Description: 1706 * Returns the correct value according to COS and priority in the 1707 * sp_pri_cli register for NIG. 1708 * 1709 ******************************************************************************/ 1710 static uint64_t elink_e3b0_sp_get_pri_cli_reg_nig(const uint8_t cos, const uint8_t pri_set) 1711 { 1712 /* MCP Dbg0 and dbg1 are always with higher strict pri*/ 1713 const uint8_t nig_cos_offset = 3; 1714 const uint8_t nig_pri_offset = 3; 1715 1716 return elink_e3b0_sp_get_pri_cli_reg(cos, nig_cos_offset, pri_set, 1717 nig_pri_offset, 4); 1718 1719 } 1720 /****************************************************************************** 1721 * Description: 1722 * Returns the correct value according to COS and priority in the 1723 * sp_pri_cli register for PBF. 1724 * 1725 ******************************************************************************/ 1726 static uint64_t elink_e3b0_sp_get_pri_cli_reg_pbf(const uint8_t cos, const uint8_t pri_set) 1727 { 1728 const uint8_t pbf_cos_offset = 0; 1729 const uint8_t pbf_pri_offset = 0; 1730 1731 return elink_e3b0_sp_get_pri_cli_reg(cos, pbf_cos_offset, pri_set, 1732 pbf_pri_offset, 3); 1733 1734 } 1735 1736 /****************************************************************************** 1737 * Description: 1738 * Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers 1739 * according to sp_pri_to_cos.(which COS has higher priority) 1740 * 1741 ******************************************************************************/ 1742 static elink_status_t elink_ets_e3b0_sp_set_pri_cli_reg(const struct elink_params *params, 1743 uint8_t *sp_pri_to_cos) 1744 { 1745 struct bxe_softc *sc = params->sc; 1746 uint8_t i = 0; 1747 const uint8_t port = params->port; 1748 /* MCP Dbg0 and dbg1 are always with higher strict pri*/ 1749 uint64_t pri_cli_nig = 0x210; 1750 uint32_t pri_cli_pbf = 0x0; 1751 uint8_t pri_set = 0; 1752 uint8_t pri_bitmask = 0; 1753 const uint8_t max_num_of_cos = (port) ? ELINK_DCBX_E3B0_MAX_NUM_COS_PORT1 : 1754 ELINK_DCBX_E3B0_MAX_NUM_COS_PORT0; 1755 1756 uint8_t cos_bit_to_set = (1 << max_num_of_cos) - 1; 1757 1758 /* Set all the strict priority first */ 1759 for (i = 0; i < max_num_of_cos; i++) { 1760 if (sp_pri_to_cos[i] != DCBX_INVALID_COS) { 1761 if (sp_pri_to_cos[i] >= ELINK_DCBX_MAX_NUM_COS) { 1762 ELINK_DEBUG_P0(sc, 1763 "elink_ets_e3b0_sp_set_pri_cli_reg " 1764 "invalid cos entry\n"); 1765 return ELINK_STATUS_ERROR; 1766 } 1767 1768 pri_cli_nig |= elink_e3b0_sp_get_pri_cli_reg_nig( 1769 sp_pri_to_cos[i], pri_set); 1770 1771 pri_cli_pbf |= elink_e3b0_sp_get_pri_cli_reg_pbf( 1772 sp_pri_to_cos[i], pri_set); 1773 pri_bitmask = 1 << sp_pri_to_cos[i]; 1774 /* COS is used remove it from bitmap.*/ 1775 if (!(pri_bitmask & cos_bit_to_set)) { 1776 ELINK_DEBUG_P0(sc, 1777 "elink_ets_e3b0_sp_set_pri_cli_reg " 1778 "invalid There can't be two COS's with" 1779 " the same strict pri\n"); 1780 return ELINK_STATUS_ERROR; 1781 } 1782 cos_bit_to_set &= ~pri_bitmask; 1783 pri_set++; 1784 } 1785 } 1786 1787 /* Set all the Non strict priority i= COS*/ 1788 for (i = 0; i < max_num_of_cos; i++) { 1789 pri_bitmask = 1 << i; 1790 /* Check if COS was already used for SP */ 1791 if (pri_bitmask & cos_bit_to_set) { 1792 /* COS wasn't used for SP */ 1793 pri_cli_nig |= elink_e3b0_sp_get_pri_cli_reg_nig( 1794 i, pri_set); 1795 1796 pri_cli_pbf |= elink_e3b0_sp_get_pri_cli_reg_pbf( 1797 i, pri_set); 1798 /* COS is used remove it from bitmap.*/ 1799 cos_bit_to_set &= ~pri_bitmask; 1800 pri_set++; 1801 } 1802 } 1803 1804 if (pri_set != max_num_of_cos) { 1805 ELINK_DEBUG_P0(sc, "elink_ets_e3b0_sp_set_pri_cli_reg not all " 1806 "entries were set\n"); 1807 return ELINK_STATUS_ERROR; 1808 } 1809 1810 if (port) { 1811 /* Only 6 usable clients*/ 1812 REG_WR(sc, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB, 1813 (uint32_t)pri_cli_nig); 1814 1815 REG_WR(sc, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , pri_cli_pbf); 1816 } else { 1817 /* Only 9 usable clients*/ 1818 const uint32_t pri_cli_nig_lsb = (uint32_t) (pri_cli_nig); 1819 const uint32_t pri_cli_nig_msb = (uint32_t) ((pri_cli_nig >> 32) & 0xF); 1820 1821 REG_WR(sc, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB, 1822 pri_cli_nig_lsb); 1823 REG_WR(sc, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB, 1824 pri_cli_nig_msb); 1825 1826 REG_WR(sc, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , pri_cli_pbf); 1827 } 1828 return ELINK_STATUS_OK; 1829 } 1830 1831 /****************************************************************************** 1832 * Description: 1833 * Configure the COS to ETS according to BW and SP settings. 1834 ******************************************************************************/ 1835 elink_status_t elink_ets_e3b0_config(const struct elink_params *params, 1836 const struct elink_vars *vars, 1837 struct elink_ets_params *ets_params) 1838 { 1839 struct bxe_softc *sc = params->sc; 1840 elink_status_t elink_status = ELINK_STATUS_OK; 1841 const uint8_t port = params->port; 1842 uint16_t total_bw = 0; 1843 const uint32_t min_w_val_nig = elink_ets_get_min_w_val_nig(vars); 1844 const uint32_t min_w_val_pbf = ELINK_ETS_E3B0_PBF_MIN_W_VAL; 1845 uint8_t cos_bw_bitmap = 0; 1846 uint8_t cos_sp_bitmap = 0; 1847 uint8_t sp_pri_to_cos[ELINK_DCBX_MAX_NUM_COS] = {0}; 1848 const uint8_t max_num_of_cos = (port) ? ELINK_DCBX_E3B0_MAX_NUM_COS_PORT1 : 1849 ELINK_DCBX_E3B0_MAX_NUM_COS_PORT0; 1850 uint8_t cos_entry = 0; 1851 1852 if (!CHIP_IS_E3B0(sc)) { 1853 ELINK_DEBUG_P0(sc, 1854 "elink_ets_e3b0_disabled the chip isn't E3B0\n"); 1855 return ELINK_STATUS_ERROR; 1856 } 1857 1858 if ((ets_params->num_of_cos > max_num_of_cos)) { 1859 ELINK_DEBUG_P0(sc, "elink_ets_E3B0_config the number of COS " 1860 "isn't supported\n"); 1861 return ELINK_STATUS_ERROR; 1862 } 1863 1864 /* Prepare sp strict priority parameters*/ 1865 elink_ets_e3b0_sp_pri_to_cos_init(sp_pri_to_cos); 1866 1867 /* Prepare BW parameters*/ 1868 elink_status = elink_ets_e3b0_get_total_bw(params, ets_params, 1869 &total_bw); 1870 if (elink_status != ELINK_STATUS_OK) { 1871 ELINK_DEBUG_P0(sc, 1872 "elink_ets_E3B0_config get_total_bw failed\n"); 1873 return ELINK_STATUS_ERROR; 1874 } 1875 1876 /* Upper bound is set according to current link speed (min_w_val 1877 * should be the same for upper bound and COS credit val). 1878 */ 1879 elink_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val_nig); 1880 elink_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf); 1881 1882 1883 for (cos_entry = 0; cos_entry < ets_params->num_of_cos; cos_entry++) { 1884 if (elink_cos_state_bw == ets_params->cos[cos_entry].state) { 1885 cos_bw_bitmap |= (1 << cos_entry); 1886 /* The function also sets the BW in HW(not the mappin 1887 * yet) 1888 */ 1889 elink_status = elink_ets_e3b0_set_cos_bw( 1890 sc, cos_entry, min_w_val_nig, min_w_val_pbf, 1891 total_bw, 1892 ets_params->cos[cos_entry].params.bw_params.bw, 1893 port); 1894 } else if (elink_cos_state_strict == 1895 ets_params->cos[cos_entry].state){ 1896 cos_sp_bitmap |= (1 << cos_entry); 1897 1898 elink_status = elink_ets_e3b0_sp_pri_to_cos_set( 1899 params, 1900 sp_pri_to_cos, 1901 ets_params->cos[cos_entry].params.sp_params.pri, 1902 cos_entry); 1903 1904 } else { 1905 ELINK_DEBUG_P0(sc, 1906 "elink_ets_e3b0_config cos state not valid\n"); 1907 return ELINK_STATUS_ERROR; 1908 } 1909 if (elink_status != ELINK_STATUS_OK) { 1910 ELINK_DEBUG_P0(sc, 1911 "elink_ets_e3b0_config set cos bw failed\n"); 1912 return elink_status; 1913 } 1914 } 1915 1916 /* Set SP register (which COS has higher priority) */ 1917 elink_status = elink_ets_e3b0_sp_set_pri_cli_reg(params, 1918 sp_pri_to_cos); 1919 1920 if (elink_status != ELINK_STATUS_OK) { 1921 ELINK_DEBUG_P0(sc, 1922 "elink_ets_E3B0_config set_pri_cli_reg failed\n"); 1923 return elink_status; 1924 } 1925 1926 /* Set client mapping of BW and strict */ 1927 elink_status = elink_ets_e3b0_cli_map(params, ets_params, 1928 cos_sp_bitmap, 1929 cos_bw_bitmap); 1930 1931 if (elink_status != ELINK_STATUS_OK) { 1932 ELINK_DEBUG_P0(sc, "elink_ets_E3B0_config SP failed\n"); 1933 return elink_status; 1934 } 1935 return ELINK_STATUS_OK; 1936 } 1937 static void elink_ets_bw_limit_common(const struct elink_params *params) 1938 { 1939 /* ETS disabled configuration */ 1940 struct bxe_softc *sc = params->sc; 1941 ELINK_DEBUG_P0(sc, "ETS enabled BW limit configuration\n"); 1942 /* Defines which entries (clients) are subjected to WFQ arbitration 1943 * COS0 0x8 1944 * COS1 0x10 1945 */ 1946 REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0x18); 1947 /* Mapping between the ARB_CREDIT_WEIGHT registers and actual 1948 * client numbers (WEIGHT_0 does not actually have to represent 1949 * client 0) 1950 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0 1951 * cos1-001 cos0-000 dbg1-100 dbg0-011 MCP-010 1952 */ 1953 REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0x111A); 1954 1955 REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, 1956 ELINK_ETS_BW_LIMIT_CREDIT_UPPER_BOUND); 1957 REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, 1958 ELINK_ETS_BW_LIMIT_CREDIT_UPPER_BOUND); 1959 1960 /* ETS mode enabled*/ 1961 REG_WR(sc, PBF_REG_ETS_ENABLED, 1); 1962 1963 /* Defines the number of consecutive slots for the strict priority */ 1964 REG_WR(sc, PBF_REG_NUM_STRICT_ARB_SLOTS, 0); 1965 /* Bitmap of 5bits length. Each bit specifies whether the entry behaves 1966 * as strict. Bits 0,1,2 - debug and management entries, 3 - COS0 1967 * entry, 4 - COS1 entry. 1968 * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT 1969 * bit4 bit3 bit2 bit1 bit0 1970 * MCP and debug are strict 1971 */ 1972 REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7); 1973 1974 /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter.*/ 1975 REG_WR(sc, PBF_REG_COS0_UPPER_BOUND, 1976 ELINK_ETS_BW_LIMIT_CREDIT_UPPER_BOUND); 1977 REG_WR(sc, PBF_REG_COS1_UPPER_BOUND, 1978 ELINK_ETS_BW_LIMIT_CREDIT_UPPER_BOUND); 1979 } 1980 1981 void elink_ets_bw_limit(const struct elink_params *params, const uint32_t cos0_bw, 1982 const uint32_t cos1_bw) 1983 { 1984 /* ETS disabled configuration*/ 1985 struct bxe_softc *sc = params->sc; 1986 const uint32_t total_bw = cos0_bw + cos1_bw; 1987 uint32_t cos0_credit_weight = 0; 1988 uint32_t cos1_credit_weight = 0; 1989 1990 ELINK_DEBUG_P0(sc, "ETS enabled BW limit configuration\n"); 1991 1992 if ((!total_bw) || 1993 (!cos0_bw) || 1994 (!cos1_bw)) { 1995 ELINK_DEBUG_P0(sc, "Total BW can't be zero\n"); 1996 return; 1997 } 1998 1999 cos0_credit_weight = (cos0_bw * ELINK_ETS_BW_LIMIT_CREDIT_WEIGHT)/ 2000 total_bw; 2001 cos1_credit_weight = (cos1_bw * ELINK_ETS_BW_LIMIT_CREDIT_WEIGHT)/ 2002 total_bw; 2003 2004 elink_ets_bw_limit_common(params); 2005 2006 REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, cos0_credit_weight); 2007 REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, cos1_credit_weight); 2008 2009 REG_WR(sc, PBF_REG_COS0_WEIGHT, cos0_credit_weight); 2010 REG_WR(sc, PBF_REG_COS1_WEIGHT, cos1_credit_weight); 2011 } 2012 2013 elink_status_t elink_ets_strict(const struct elink_params *params, const uint8_t strict_cos) 2014 { 2015 /* ETS disabled configuration*/ 2016 struct bxe_softc *sc = params->sc; 2017 uint32_t val = 0; 2018 2019 ELINK_DEBUG_P0(sc, "ETS enabled strict configuration\n"); 2020 /* Bitmap of 5bits length. Each bit specifies whether the entry behaves 2021 * as strict. Bits 0,1,2 - debug and management entries, 2022 * 3 - COS0 entry, 4 - COS1 entry. 2023 * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT 2024 * bit4 bit3 bit2 bit1 bit0 2025 * MCP and debug are strict 2026 */ 2027 REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1F); 2028 /* For strict priority entries defines the number of consecutive slots 2029 * for the highest priority. 2030 */ 2031 REG_WR(sc, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100); 2032 /* ETS mode disable */ 2033 REG_WR(sc, PBF_REG_ETS_ENABLED, 0); 2034 /* Defines the number of consecutive slots for the strict priority */ 2035 REG_WR(sc, PBF_REG_NUM_STRICT_ARB_SLOTS, 0x100); 2036 2037 /* Defines the number of consecutive slots for the strict priority */ 2038 REG_WR(sc, PBF_REG_HIGH_PRIORITY_COS_NUM, strict_cos); 2039 2040 /* Mapping between entry priority to client number (0,1,2 -debug and 2041 * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST) 2042 * 3bits client num. 2043 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0 2044 * dbg0-010 dbg1-001 cos1-100 cos0-011 MCP-000 2045 * dbg0-010 dbg1-001 cos0-011 cos1-100 MCP-000 2046 */ 2047 val = (!strict_cos) ? 0x2318 : 0x22E0; 2048 REG_WR(sc, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, val); 2049 2050 return ELINK_STATUS_OK; 2051 } 2052 2053 /******************************************************************/ 2054 /* PFC section */ 2055 /******************************************************************/ 2056 static void elink_update_pfc_xmac(struct elink_params *params, 2057 struct elink_vars *vars, 2058 uint8_t is_lb) 2059 { 2060 struct bxe_softc *sc = params->sc; 2061 uint32_t xmac_base; 2062 uint32_t pause_val, pfc0_val, pfc1_val; 2063 2064 /* XMAC base adrr */ 2065 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; 2066 2067 /* Initialize pause and pfc registers */ 2068 pause_val = 0x18000; 2069 pfc0_val = 0xFFFF8000; 2070 pfc1_val = 0x2; 2071 2072 /* No PFC support */ 2073 if (!(params->feature_config_flags & 2074 ELINK_FEATURE_CONFIG_PFC_ENABLED)) { 2075 2076 /* RX flow control - Process pause frame in receive direction 2077 */ 2078 if (vars->flow_ctrl & ELINK_FLOW_CTRL_RX) 2079 pause_val |= XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN; 2080 2081 /* TX flow control - Send pause packet when buffer is full */ 2082 if (vars->flow_ctrl & ELINK_FLOW_CTRL_TX) 2083 pause_val |= XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN; 2084 } else {/* PFC support */ 2085 pfc1_val |= XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN | 2086 XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN | 2087 XMAC_PFC_CTRL_HI_REG_RX_PFC_EN | 2088 XMAC_PFC_CTRL_HI_REG_TX_PFC_EN | 2089 XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON; 2090 /* Write pause and PFC registers */ 2091 REG_WR(sc, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val); 2092 REG_WR(sc, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val); 2093 REG_WR(sc, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val); 2094 pfc1_val &= ~XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON; 2095 2096 } 2097 2098 /* Write pause and PFC registers */ 2099 REG_WR(sc, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val); 2100 REG_WR(sc, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val); 2101 REG_WR(sc, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val); 2102 2103 2104 /* Set MAC address for source TX Pause/PFC frames */ 2105 REG_WR(sc, xmac_base + XMAC_REG_CTRL_SA_LO, 2106 ((params->mac_addr[2] << 24) | 2107 (params->mac_addr[3] << 16) | 2108 (params->mac_addr[4] << 8) | 2109 (params->mac_addr[5]))); 2110 REG_WR(sc, xmac_base + XMAC_REG_CTRL_SA_HI, 2111 ((params->mac_addr[0] << 8) | 2112 (params->mac_addr[1]))); 2113 2114 DELAY(30); 2115 } 2116 2117 2118 static void elink_emac_get_pfc_stat(struct elink_params *params, 2119 uint32_t pfc_frames_sent[2], 2120 uint32_t pfc_frames_received[2]) 2121 { 2122 /* Read pfc statistic */ 2123 struct bxe_softc *sc = params->sc; 2124 uint32_t emac_base = params->port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; 2125 uint32_t val_xon = 0; 2126 uint32_t val_xoff = 0; 2127 2128 ELINK_DEBUG_P0(sc, "pfc statistic read from EMAC\n"); 2129 2130 /* PFC received frames */ 2131 val_xoff = REG_RD(sc, emac_base + 2132 EMAC_REG_RX_PFC_STATS_XOFF_RCVD); 2133 val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_RCVD_COUNT; 2134 val_xon = REG_RD(sc, emac_base + EMAC_REG_RX_PFC_STATS_XON_RCVD); 2135 val_xon &= EMAC_REG_RX_PFC_STATS_XON_RCVD_COUNT; 2136 2137 pfc_frames_received[0] = val_xon + val_xoff; 2138 2139 /* PFC received sent */ 2140 val_xoff = REG_RD(sc, emac_base + 2141 EMAC_REG_RX_PFC_STATS_XOFF_SENT); 2142 val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_SENT_COUNT; 2143 val_xon = REG_RD(sc, emac_base + EMAC_REG_RX_PFC_STATS_XON_SENT); 2144 val_xon &= EMAC_REG_RX_PFC_STATS_XON_SENT_COUNT; 2145 2146 pfc_frames_sent[0] = val_xon + val_xoff; 2147 } 2148 2149 /* Read pfc statistic*/ 2150 void elink_pfc_statistic(struct elink_params *params, struct elink_vars *vars, 2151 uint32_t pfc_frames_sent[2], 2152 uint32_t pfc_frames_received[2]) 2153 { 2154 /* Read pfc statistic */ 2155 struct bxe_softc *sc = params->sc; 2156 2157 ELINK_DEBUG_P0(sc, "pfc statistic\n"); 2158 2159 if (!vars->link_up) 2160 return; 2161 2162 if (vars->mac_type == ELINK_MAC_TYPE_EMAC) { 2163 ELINK_DEBUG_P0(sc, "About to read PFC stats from EMAC\n"); 2164 elink_emac_get_pfc_stat(params, pfc_frames_sent, 2165 pfc_frames_received); 2166 } 2167 } 2168 /******************************************************************/ 2169 /* MAC/PBF section */ 2170 /******************************************************************/ 2171 static void elink_set_mdio_clk(struct bxe_softc *sc, uint32_t chip_id, 2172 uint32_t emac_base) 2173 { 2174 uint32_t new_mode, cur_mode; 2175 uint32_t clc_cnt; 2176 /* Set clause 45 mode, slow down the MDIO clock to 2.5MHz 2177 * (a value of 49==0x31) and make sure that the AUTO poll is off 2178 */ 2179 cur_mode = REG_RD(sc, emac_base + EMAC_REG_EMAC_MDIO_MODE); 2180 2181 if (USES_WARPCORE(sc)) 2182 clc_cnt = 74L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT; 2183 else 2184 clc_cnt = 49L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT; 2185 2186 if (((cur_mode & EMAC_MDIO_MODE_CLOCK_CNT) == clc_cnt) && 2187 (cur_mode & (EMAC_MDIO_MODE_CLAUSE_45))) 2188 return; 2189 2190 new_mode = cur_mode & 2191 ~(EMAC_MDIO_MODE_AUTO_POLL | EMAC_MDIO_MODE_CLOCK_CNT); 2192 new_mode |= clc_cnt; 2193 new_mode |= (EMAC_MDIO_MODE_CLAUSE_45); 2194 2195 ELINK_DEBUG_P2(sc, "Changing emac_mode from 0x%x to 0x%x\n", 2196 cur_mode, new_mode); 2197 REG_WR(sc, emac_base + EMAC_REG_EMAC_MDIO_MODE, new_mode); 2198 DELAY(40); 2199 } 2200 2201 static void elink_set_mdio_emac_per_phy(struct bxe_softc *sc, 2202 struct elink_params *params) 2203 { 2204 uint8_t phy_index; 2205 /* Set mdio clock per phy */ 2206 for (phy_index = ELINK_INT_PHY; phy_index < params->num_phys; 2207 phy_index++) 2208 elink_set_mdio_clk(sc, params->chip_id, 2209 params->phy[phy_index].mdio_ctrl); 2210 } 2211 2212 static uint8_t elink_is_4_port_mode(struct bxe_softc *sc) 2213 { 2214 uint32_t port4mode_ovwr_val; 2215 /* Check 4-port override enabled */ 2216 port4mode_ovwr_val = REG_RD(sc, MISC_REG_PORT4MODE_EN_OVWR); 2217 if (port4mode_ovwr_val & (1<<0)) { 2218 /* Return 4-port mode override value */ 2219 return ((port4mode_ovwr_val & (1<<1)) == (1<<1)); 2220 } 2221 /* Return 4-port mode from input pin */ 2222 return (uint8_t)REG_RD(sc, MISC_REG_PORT4MODE_EN); 2223 } 2224 2225 static void elink_emac_init(struct elink_params *params, 2226 struct elink_vars *vars) 2227 { 2228 /* reset and unreset the emac core */ 2229 struct bxe_softc *sc = params->sc; 2230 uint8_t port = params->port; 2231 uint32_t emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; 2232 uint32_t val; 2233 uint16_t timeout; 2234 2235 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 2236 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port)); 2237 DELAY(5); 2238 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 2239 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port)); 2240 2241 /* init emac - use read-modify-write */ 2242 /* self clear reset */ 2243 val = REG_RD(sc, emac_base + EMAC_REG_EMAC_MODE); 2244 elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_MODE, (val | EMAC_MODE_RESET)); 2245 2246 timeout = 200; 2247 do { 2248 val = REG_RD(sc, emac_base + EMAC_REG_EMAC_MODE); 2249 ELINK_DEBUG_P1(sc, "EMAC reset reg is %u\n", val); 2250 if (!timeout) { 2251 ELINK_DEBUG_P0(sc, "EMAC timeout!\n"); 2252 return; 2253 } 2254 timeout--; 2255 } while (val & EMAC_MODE_RESET); 2256 2257 elink_set_mdio_emac_per_phy(sc, params); 2258 /* Set mac address */ 2259 val = ((params->mac_addr[0] << 8) | 2260 params->mac_addr[1]); 2261 elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_MAC_MATCH, val); 2262 2263 val = ((params->mac_addr[2] << 24) | 2264 (params->mac_addr[3] << 16) | 2265 (params->mac_addr[4] << 8) | 2266 params->mac_addr[5]); 2267 elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_MAC_MATCH + 4, val); 2268 } 2269 2270 static void elink_set_xumac_nig(struct elink_params *params, 2271 uint16_t tx_pause_en, 2272 uint8_t enable) 2273 { 2274 struct bxe_softc *sc = params->sc; 2275 2276 REG_WR(sc, params->port ? NIG_REG_P1_MAC_IN_EN : NIG_REG_P0_MAC_IN_EN, 2277 enable); 2278 REG_WR(sc, params->port ? NIG_REG_P1_MAC_OUT_EN : NIG_REG_P0_MAC_OUT_EN, 2279 enable); 2280 REG_WR(sc, params->port ? NIG_REG_P1_MAC_PAUSE_OUT_EN : 2281 NIG_REG_P0_MAC_PAUSE_OUT_EN, tx_pause_en); 2282 } 2283 2284 static void elink_set_umac_rxtx(struct elink_params *params, uint8_t en) 2285 { 2286 uint32_t umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0; 2287 uint32_t val; 2288 struct bxe_softc *sc = params->sc; 2289 if (!(REG_RD(sc, MISC_REG_RESET_REG_2) & 2290 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port))) 2291 return; 2292 val = REG_RD(sc, umac_base + UMAC_REG_COMMAND_CONFIG); 2293 if (en) 2294 val |= (UMAC_COMMAND_CONFIG_REG_TX_ENA | 2295 UMAC_COMMAND_CONFIG_REG_RX_ENA); 2296 else 2297 val &= ~(UMAC_COMMAND_CONFIG_REG_TX_ENA | 2298 UMAC_COMMAND_CONFIG_REG_RX_ENA); 2299 /* Disable RX and TX */ 2300 REG_WR(sc, umac_base + UMAC_REG_COMMAND_CONFIG, val); 2301 } 2302 2303 static void elink_umac_enable(struct elink_params *params, 2304 struct elink_vars *vars, uint8_t lb) 2305 { 2306 uint32_t val; 2307 uint32_t umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0; 2308 struct bxe_softc *sc = params->sc; 2309 /* Reset UMAC */ 2310 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 2311 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port)); 2312 DELAY(1000 * 1); 2313 2314 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 2315 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port)); 2316 2317 ELINK_DEBUG_P0(sc, "enabling UMAC\n"); 2318 2319 /* This register opens the gate for the UMAC despite its name */ 2320 REG_WR(sc, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1); 2321 2322 val = UMAC_COMMAND_CONFIG_REG_PROMIS_EN | 2323 UMAC_COMMAND_CONFIG_REG_PAD_EN | 2324 UMAC_COMMAND_CONFIG_REG_SW_RESET | 2325 UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK; 2326 switch (vars->line_speed) { 2327 case ELINK_SPEED_10: 2328 val |= (0<<2); 2329 break; 2330 case ELINK_SPEED_100: 2331 val |= (1<<2); 2332 break; 2333 case ELINK_SPEED_1000: 2334 val |= (2<<2); 2335 break; 2336 case ELINK_SPEED_2500: 2337 val |= (3<<2); 2338 break; 2339 default: 2340 ELINK_DEBUG_P1(sc, "Invalid speed for UMAC %d\n", 2341 vars->line_speed); 2342 break; 2343 } 2344 if (!(vars->flow_ctrl & ELINK_FLOW_CTRL_TX)) 2345 val |= UMAC_COMMAND_CONFIG_REG_IGNORE_TX_PAUSE; 2346 2347 if (!(vars->flow_ctrl & ELINK_FLOW_CTRL_RX)) 2348 val |= UMAC_COMMAND_CONFIG_REG_PAUSE_IGNORE; 2349 2350 if (vars->duplex == DUPLEX_HALF) 2351 val |= UMAC_COMMAND_CONFIG_REG_HD_ENA; 2352 2353 REG_WR(sc, umac_base + UMAC_REG_COMMAND_CONFIG, val); 2354 DELAY(50); 2355 2356 /* Configure UMAC for EEE */ 2357 if (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) { 2358 ELINK_DEBUG_P0(sc, "configured UMAC for EEE\n"); 2359 REG_WR(sc, umac_base + UMAC_REG_UMAC_EEE_CTRL, 2360 UMAC_UMAC_EEE_CTRL_REG_EEE_EN); 2361 REG_WR(sc, umac_base + UMAC_REG_EEE_WAKE_TIMER, 0x11); 2362 } else { 2363 REG_WR(sc, umac_base + UMAC_REG_UMAC_EEE_CTRL, 0x0); 2364 } 2365 2366 /* Set MAC address for source TX Pause/PFC frames (under SW reset) */ 2367 REG_WR(sc, umac_base + UMAC_REG_MAC_ADDR0, 2368 ((params->mac_addr[2] << 24) | 2369 (params->mac_addr[3] << 16) | 2370 (params->mac_addr[4] << 8) | 2371 (params->mac_addr[5]))); 2372 REG_WR(sc, umac_base + UMAC_REG_MAC_ADDR1, 2373 ((params->mac_addr[0] << 8) | 2374 (params->mac_addr[1]))); 2375 2376 /* Enable RX and TX */ 2377 val &= ~UMAC_COMMAND_CONFIG_REG_PAD_EN; 2378 val |= UMAC_COMMAND_CONFIG_REG_TX_ENA | 2379 UMAC_COMMAND_CONFIG_REG_RX_ENA; 2380 REG_WR(sc, umac_base + UMAC_REG_COMMAND_CONFIG, val); 2381 DELAY(50); 2382 2383 /* Remove SW Reset */ 2384 val &= ~UMAC_COMMAND_CONFIG_REG_SW_RESET; 2385 2386 /* Check loopback mode */ 2387 if (lb) 2388 val |= UMAC_COMMAND_CONFIG_REG_LOOP_ENA; 2389 REG_WR(sc, umac_base + UMAC_REG_COMMAND_CONFIG, val); 2390 2391 /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame 2392 * length used by the MAC receive logic to check frames. 2393 */ 2394 REG_WR(sc, umac_base + UMAC_REG_MAXFR, 0x2710); 2395 elink_set_xumac_nig(params, 2396 ((vars->flow_ctrl & ELINK_FLOW_CTRL_TX) != 0), 1); 2397 vars->mac_type = ELINK_MAC_TYPE_UMAC; 2398 2399 } 2400 2401 /* Define the XMAC mode */ 2402 static void elink_xmac_init(struct elink_params *params, uint32_t max_speed) 2403 { 2404 struct bxe_softc *sc = params->sc; 2405 uint32_t is_port4mode = elink_is_4_port_mode(sc); 2406 2407 /* In 4-port mode, need to set the mode only once, so if XMAC is 2408 * already out of reset, it means the mode has already been set, 2409 * and it must not* reset the XMAC again, since it controls both 2410 * ports of the path 2411 */ 2412 2413 if (((CHIP_NUM(sc) == CHIP_NUM_57840_4_10) || 2414 (CHIP_NUM(sc) == CHIP_NUM_57840_2_20) || 2415 (CHIP_NUM(sc) == CHIP_NUM_57840_OBS)) && 2416 is_port4mode && 2417 (REG_RD(sc, MISC_REG_RESET_REG_2) & 2418 MISC_REGISTERS_RESET_REG_2_XMAC)) { 2419 ELINK_DEBUG_P0(sc, 2420 "XMAC already out of reset in 4-port mode\n"); 2421 return; 2422 } 2423 2424 /* Hard reset */ 2425 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 2426 MISC_REGISTERS_RESET_REG_2_XMAC); 2427 DELAY(1000 * 1); 2428 2429 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 2430 MISC_REGISTERS_RESET_REG_2_XMAC); 2431 if (is_port4mode) { 2432 ELINK_DEBUG_P0(sc, "Init XMAC to 2 ports x 10G per path\n"); 2433 2434 /* Set the number of ports on the system side to up to 2 */ 2435 REG_WR(sc, MISC_REG_XMAC_CORE_PORT_MODE, 1); 2436 2437 /* Set the number of ports on the Warp Core to 10G */ 2438 REG_WR(sc, MISC_REG_XMAC_PHY_PORT_MODE, 3); 2439 } else { 2440 /* Set the number of ports on the system side to 1 */ 2441 REG_WR(sc, MISC_REG_XMAC_CORE_PORT_MODE, 0); 2442 if (max_speed == ELINK_SPEED_10000) { 2443 ELINK_DEBUG_P0(sc, 2444 "Init XMAC to 10G x 1 port per path\n"); 2445 /* Set the number of ports on the Warp Core to 10G */ 2446 REG_WR(sc, MISC_REG_XMAC_PHY_PORT_MODE, 3); 2447 } else { 2448 ELINK_DEBUG_P0(sc, 2449 "Init XMAC to 20G x 2 ports per path\n"); 2450 /* Set the number of ports on the Warp Core to 20G */ 2451 REG_WR(sc, MISC_REG_XMAC_PHY_PORT_MODE, 1); 2452 } 2453 } 2454 /* Soft reset */ 2455 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 2456 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT); 2457 DELAY(1000 * 1); 2458 2459 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 2460 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT); 2461 2462 } 2463 2464 static void elink_set_xmac_rxtx(struct elink_params *params, uint8_t en) 2465 { 2466 uint8_t port = params->port; 2467 struct bxe_softc *sc = params->sc; 2468 uint32_t pfc_ctrl, xmac_base = (port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; 2469 uint32_t val; 2470 2471 if (REG_RD(sc, MISC_REG_RESET_REG_2) & 2472 MISC_REGISTERS_RESET_REG_2_XMAC) { 2473 /* Send an indication to change the state in the NIG back to XON 2474 * Clearing this bit enables the next set of this bit to get 2475 * rising edge 2476 */ 2477 pfc_ctrl = REG_RD(sc, xmac_base + XMAC_REG_PFC_CTRL_HI); 2478 REG_WR(sc, xmac_base + XMAC_REG_PFC_CTRL_HI, 2479 (pfc_ctrl & ~(1<<1))); 2480 REG_WR(sc, xmac_base + XMAC_REG_PFC_CTRL_HI, 2481 (pfc_ctrl | (1<<1))); 2482 ELINK_DEBUG_P1(sc, "Disable XMAC on port %x\n", port); 2483 val = REG_RD(sc, xmac_base + XMAC_REG_CTRL); 2484 if (en) 2485 val |= (XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN); 2486 else 2487 val &= ~(XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN); 2488 REG_WR(sc, xmac_base + XMAC_REG_CTRL, val); 2489 } 2490 } 2491 2492 static elink_status_t elink_xmac_enable(struct elink_params *params, 2493 struct elink_vars *vars, uint8_t lb) 2494 { 2495 uint32_t val, xmac_base; 2496 struct bxe_softc *sc = params->sc; 2497 ELINK_DEBUG_P0(sc, "enabling XMAC\n"); 2498 2499 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; 2500 2501 elink_xmac_init(params, vars->line_speed); 2502 2503 /* This register determines on which events the MAC will assert 2504 * error on the i/f to the NIG along w/ EOP. 2505 */ 2506 2507 /* This register tells the NIG whether to send traffic to UMAC 2508 * or XMAC 2509 */ 2510 REG_WR(sc, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 0); 2511 2512 /* When XMAC is in XLGMII mode, disable sending idles for fault 2513 * detection. 2514 */ 2515 if (!(params->phy[ELINK_INT_PHY].flags & ELINK_FLAGS_TX_ERROR_CHECK)) { 2516 REG_WR(sc, xmac_base + XMAC_REG_RX_LSS_CTRL, 2517 (XMAC_RX_LSS_CTRL_REG_LOCAL_FAULT_DISABLE | 2518 XMAC_RX_LSS_CTRL_REG_REMOTE_FAULT_DISABLE)); 2519 REG_WR(sc, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0); 2520 REG_WR(sc, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 2521 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS | 2522 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS); 2523 } 2524 /* Set Max packet size */ 2525 REG_WR(sc, xmac_base + XMAC_REG_RX_MAX_SIZE, 0x2710); 2526 2527 /* CRC append for Tx packets */ 2528 REG_WR(sc, xmac_base + XMAC_REG_TX_CTRL, 0xC800); 2529 2530 /* update PFC */ 2531 elink_update_pfc_xmac(params, vars, 0); 2532 2533 if (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) { 2534 ELINK_DEBUG_P0(sc, "Setting XMAC for EEE\n"); 2535 REG_WR(sc, xmac_base + XMAC_REG_EEE_TIMERS_HI, 0x1380008); 2536 REG_WR(sc, xmac_base + XMAC_REG_EEE_CTRL, 0x1); 2537 } else { 2538 REG_WR(sc, xmac_base + XMAC_REG_EEE_CTRL, 0x0); 2539 } 2540 2541 /* Enable TX and RX */ 2542 val = XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN; 2543 2544 /* Set MAC in XLGMII mode for dual-mode */ 2545 if ((vars->line_speed == ELINK_SPEED_20000) && 2546 (params->phy[ELINK_INT_PHY].supported & 2547 ELINK_SUPPORTED_20000baseKR2_Full)) 2548 val |= XMAC_CTRL_REG_XLGMII_ALIGN_ENB; 2549 2550 /* Check loopback mode */ 2551 if (lb) 2552 val |= XMAC_CTRL_REG_LINE_LOCAL_LPBK; 2553 REG_WR(sc, xmac_base + XMAC_REG_CTRL, val); 2554 elink_set_xumac_nig(params, 2555 ((vars->flow_ctrl & ELINK_FLOW_CTRL_TX) != 0), 1); 2556 2557 vars->mac_type = ELINK_MAC_TYPE_XMAC; 2558 2559 return ELINK_STATUS_OK; 2560 } 2561 2562 static elink_status_t elink_emac_enable(struct elink_params *params, 2563 struct elink_vars *vars, uint8_t lb) 2564 { 2565 struct bxe_softc *sc = params->sc; 2566 uint8_t port = params->port; 2567 uint32_t emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; 2568 uint32_t val; 2569 2570 ELINK_DEBUG_P0(sc, "enabling EMAC\n"); 2571 2572 /* Disable BMAC */ 2573 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 2574 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); 2575 2576 /* enable emac and not bmac */ 2577 REG_WR(sc, NIG_REG_EGRESS_EMAC0_PORT + port*4, 1); 2578 2579 #ifdef ELINK_INCLUDE_EMUL 2580 /* for paladium */ 2581 if (CHIP_REV_IS_EMUL(sc)) { 2582 /* Use lane 1 (of lanes 0-3) */ 2583 REG_WR(sc, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 1); 2584 REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1); 2585 } 2586 /* for fpga */ 2587 else 2588 #endif 2589 #ifdef ELINK_INCLUDE_FPGA 2590 if (CHIP_REV_IS_FPGA(sc)) { 2591 /* Use lane 1 (of lanes 0-3) */ 2592 ELINK_DEBUG_P0(sc, "elink_emac_enable: Setting FPGA\n"); 2593 2594 REG_WR(sc, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 1); 2595 REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0); 2596 } else 2597 #endif 2598 /* ASIC */ 2599 if (vars->phy_flags & PHY_XGXS_FLAG) { 2600 uint32_t ser_lane = ((params->lane_config & 2601 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >> 2602 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT); 2603 2604 ELINK_DEBUG_P0(sc, "XGXS\n"); 2605 /* select the master lanes (out of 0-3) */ 2606 REG_WR(sc, NIG_REG_XGXS_LANE_SEL_P0 + port*4, ser_lane); 2607 /* select XGXS */ 2608 REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1); 2609 2610 } else { /* SerDes */ 2611 ELINK_DEBUG_P0(sc, "SerDes\n"); 2612 /* select SerDes */ 2613 REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0); 2614 } 2615 2616 elink_bits_en(sc, emac_base + EMAC_REG_EMAC_RX_MODE, 2617 EMAC_RX_MODE_RESET); 2618 elink_bits_en(sc, emac_base + EMAC_REG_EMAC_TX_MODE, 2619 EMAC_TX_MODE_RESET); 2620 2621 #if defined(ELINK_INCLUDE_EMUL) || defined(ELINK_INCLUDE_FPGA) 2622 if (CHIP_REV_IS_SLOW(sc)) { 2623 /* config GMII mode */ 2624 val = REG_RD(sc, emac_base + EMAC_REG_EMAC_MODE); 2625 elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_MODE, (val | EMAC_MODE_PORT_GMII)); 2626 } else { /* ASIC */ 2627 #endif 2628 /* pause enable/disable */ 2629 elink_bits_dis(sc, emac_base + EMAC_REG_EMAC_RX_MODE, 2630 EMAC_RX_MODE_FLOW_EN); 2631 2632 elink_bits_dis(sc, emac_base + EMAC_REG_EMAC_TX_MODE, 2633 (EMAC_TX_MODE_EXT_PAUSE_EN | 2634 EMAC_TX_MODE_FLOW_EN)); 2635 if (!(params->feature_config_flags & 2636 ELINK_FEATURE_CONFIG_PFC_ENABLED)) { 2637 if (vars->flow_ctrl & ELINK_FLOW_CTRL_RX) 2638 elink_bits_en(sc, emac_base + 2639 EMAC_REG_EMAC_RX_MODE, 2640 EMAC_RX_MODE_FLOW_EN); 2641 2642 if (vars->flow_ctrl & ELINK_FLOW_CTRL_TX) 2643 elink_bits_en(sc, emac_base + 2644 EMAC_REG_EMAC_TX_MODE, 2645 (EMAC_TX_MODE_EXT_PAUSE_EN | 2646 EMAC_TX_MODE_FLOW_EN)); 2647 } else 2648 elink_bits_en(sc, emac_base + EMAC_REG_EMAC_TX_MODE, 2649 EMAC_TX_MODE_FLOW_EN); 2650 #if defined(ELINK_INCLUDE_EMUL) || defined(ELINK_INCLUDE_FPGA) 2651 } 2652 #endif 2653 2654 /* KEEP_VLAN_TAG, promiscuous */ 2655 val = REG_RD(sc, emac_base + EMAC_REG_EMAC_RX_MODE); 2656 val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS; 2657 2658 /* Setting this bit causes MAC control frames (except for pause 2659 * frames) to be passed on for processing. This setting has no 2660 * affect on the operation of the pause frames. This bit effects 2661 * all packets regardless of RX Parser packet sorting logic. 2662 * Turn the PFC off to make sure we are in Xon state before 2663 * enabling it. 2664 */ 2665 elink_cb_reg_write(sc, emac_base + EMAC_REG_RX_PFC_MODE, 0); 2666 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED) { 2667 ELINK_DEBUG_P0(sc, "PFC is enabled\n"); 2668 /* Enable PFC again */ 2669 elink_cb_reg_write(sc, emac_base + EMAC_REG_RX_PFC_MODE, 2670 EMAC_REG_RX_PFC_MODE_RX_EN | 2671 EMAC_REG_RX_PFC_MODE_TX_EN | 2672 EMAC_REG_RX_PFC_MODE_PRIORITIES); 2673 2674 elink_cb_reg_write(sc, emac_base + EMAC_REG_RX_PFC_PARAM, 2675 ((0x0101 << 2676 EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT) | 2677 (0x00ff << 2678 EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT))); 2679 val |= EMAC_RX_MODE_KEEP_MAC_CONTROL; 2680 } 2681 elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_RX_MODE, val); 2682 2683 /* Set Loopback */ 2684 val = REG_RD(sc, emac_base + EMAC_REG_EMAC_MODE); 2685 if (lb) 2686 val |= 0x810; 2687 else 2688 val &= ~0x810; 2689 elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_MODE, val); 2690 2691 /* Enable emac */ 2692 REG_WR(sc, NIG_REG_NIG_EMAC0_EN + port*4, 1); 2693 2694 /* Enable emac for jumbo packets */ 2695 elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_RX_MTU_SIZE, 2696 (EMAC_RX_MTU_SIZE_JUMBO_ENA | 2697 (ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD))); 2698 2699 /* Strip CRC */ 2700 REG_WR(sc, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port*4, 0x1); 2701 2702 /* Disable the NIG in/out to the bmac */ 2703 REG_WR(sc, NIG_REG_BMAC0_IN_EN + port*4, 0x0); 2704 REG_WR(sc, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, 0x0); 2705 REG_WR(sc, NIG_REG_BMAC0_OUT_EN + port*4, 0x0); 2706 2707 /* Enable the NIG in/out to the emac */ 2708 REG_WR(sc, NIG_REG_EMAC0_IN_EN + port*4, 0x1); 2709 val = 0; 2710 if ((params->feature_config_flags & 2711 ELINK_FEATURE_CONFIG_PFC_ENABLED) || 2712 (vars->flow_ctrl & ELINK_FLOW_CTRL_TX)) 2713 val = 1; 2714 2715 REG_WR(sc, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, val); 2716 REG_WR(sc, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x1); 2717 2718 #ifdef ELINK_INCLUDE_EMUL 2719 if (CHIP_REV_IS_EMUL(sc)) { 2720 /* Take the BigMac out of reset */ 2721 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 2722 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); 2723 2724 /* Enable access for bmac registers */ 2725 REG_WR(sc, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1); 2726 } else 2727 #endif 2728 REG_WR(sc, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x0); 2729 2730 vars->mac_type = ELINK_MAC_TYPE_EMAC; 2731 return ELINK_STATUS_OK; 2732 } 2733 2734 static void elink_update_pfc_bmac1(struct elink_params *params, 2735 struct elink_vars *vars) 2736 { 2737 uint32_t wb_data[2]; 2738 struct bxe_softc *sc = params->sc; 2739 uint32_t bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM : 2740 NIG_REG_INGRESS_BMAC0_MEM; 2741 2742 uint32_t val = 0x14; 2743 if ((!(params->feature_config_flags & 2744 ELINK_FEATURE_CONFIG_PFC_ENABLED)) && 2745 (vars->flow_ctrl & ELINK_FLOW_CTRL_RX)) 2746 /* Enable BigMAC to react on received Pause packets */ 2747 val |= (1<<5); 2748 wb_data[0] = val; 2749 wb_data[1] = 0; 2750 REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_RX_CONTROL, wb_data, 2); 2751 2752 /* TX control */ 2753 val = 0xc0; 2754 if (!(params->feature_config_flags & 2755 ELINK_FEATURE_CONFIG_PFC_ENABLED) && 2756 (vars->flow_ctrl & ELINK_FLOW_CTRL_TX)) 2757 val |= 0x800000; 2758 wb_data[0] = val; 2759 wb_data[1] = 0; 2760 REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_TX_CONTROL, wb_data, 2); 2761 } 2762 2763 static void elink_update_pfc_bmac2(struct elink_params *params, 2764 struct elink_vars *vars, 2765 uint8_t is_lb) 2766 { 2767 /* Set rx control: Strip CRC and enable BigMAC to relay 2768 * control packets to the system as well 2769 */ 2770 uint32_t wb_data[2]; 2771 struct bxe_softc *sc = params->sc; 2772 uint32_t bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM : 2773 NIG_REG_INGRESS_BMAC0_MEM; 2774 uint32_t val = 0x14; 2775 2776 if ((!(params->feature_config_flags & 2777 ELINK_FEATURE_CONFIG_PFC_ENABLED)) && 2778 (vars->flow_ctrl & ELINK_FLOW_CTRL_RX)) 2779 /* Enable BigMAC to react on received Pause packets */ 2780 val |= (1<<5); 2781 wb_data[0] = val; 2782 wb_data[1] = 0; 2783 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_RX_CONTROL, wb_data, 2); 2784 DELAY(30); 2785 2786 /* Tx control */ 2787 val = 0xc0; 2788 if (!(params->feature_config_flags & 2789 ELINK_FEATURE_CONFIG_PFC_ENABLED) && 2790 (vars->flow_ctrl & ELINK_FLOW_CTRL_TX)) 2791 val |= 0x800000; 2792 wb_data[0] = val; 2793 wb_data[1] = 0; 2794 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_TX_CONTROL, wb_data, 2); 2795 2796 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED) { 2797 ELINK_DEBUG_P0(sc, "PFC is enabled\n"); 2798 /* Enable PFC RX & TX & STATS and set 8 COS */ 2799 wb_data[0] = 0x0; 2800 wb_data[0] |= (1<<0); /* RX */ 2801 wb_data[0] |= (1<<1); /* TX */ 2802 wb_data[0] |= (1<<2); /* Force initial Xon */ 2803 wb_data[0] |= (1<<3); /* 8 cos */ 2804 wb_data[0] |= (1<<5); /* STATS */ 2805 wb_data[1] = 0; 2806 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, 2807 wb_data, 2); 2808 /* Clear the force Xon */ 2809 wb_data[0] &= ~(1<<2); 2810 } else { 2811 ELINK_DEBUG_P0(sc, "PFC is disabled\n"); 2812 /* Disable PFC RX & TX & STATS and set 8 COS */ 2813 wb_data[0] = 0x8; 2814 wb_data[1] = 0; 2815 } 2816 2817 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, wb_data, 2); 2818 2819 /* Set Time (based unit is 512 bit time) between automatic 2820 * re-sending of PP packets amd enable automatic re-send of 2821 * Per-Priroity Packet as long as pp_gen is asserted and 2822 * pp_disable is low. 2823 */ 2824 val = 0x8000; 2825 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED) 2826 val |= (1<<16); /* enable automatic re-send */ 2827 2828 wb_data[0] = val; 2829 wb_data[1] = 0; 2830 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_TX_PAUSE_CONTROL, 2831 wb_data, 2); 2832 2833 /* mac control */ 2834 val = 0x3; /* Enable RX and TX */ 2835 if (is_lb) { 2836 val |= 0x4; /* Local loopback */ 2837 ELINK_DEBUG_P0(sc, "enable bmac loopback\n"); 2838 } 2839 /* When PFC enabled, Pass pause frames towards the NIG. */ 2840 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED) 2841 val |= ((1<<6)|(1<<5)); 2842 2843 wb_data[0] = val; 2844 wb_data[1] = 0; 2845 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2); 2846 } 2847 2848 /****************************************************************************** 2849 * Description: 2850 * This function is needed because NIG ARB_CREDIT_WEIGHT_X are 2851 * not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable. 2852 ******************************************************************************/ 2853 static elink_status_t elink_pfc_nig_rx_priority_mask(struct bxe_softc *sc, 2854 uint8_t cos_entry, 2855 uint32_t priority_mask, uint8_t port) 2856 { 2857 uint32_t nig_reg_rx_priority_mask_add = 0; 2858 2859 switch (cos_entry) { 2860 case 0: 2861 nig_reg_rx_priority_mask_add = (port) ? 2862 NIG_REG_P1_RX_COS0_PRIORITY_MASK : 2863 NIG_REG_P0_RX_COS0_PRIORITY_MASK; 2864 break; 2865 case 1: 2866 nig_reg_rx_priority_mask_add = (port) ? 2867 NIG_REG_P1_RX_COS1_PRIORITY_MASK : 2868 NIG_REG_P0_RX_COS1_PRIORITY_MASK; 2869 break; 2870 case 2: 2871 nig_reg_rx_priority_mask_add = (port) ? 2872 NIG_REG_P1_RX_COS2_PRIORITY_MASK : 2873 NIG_REG_P0_RX_COS2_PRIORITY_MASK; 2874 break; 2875 case 3: 2876 if (port) 2877 return ELINK_STATUS_ERROR; 2878 nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS3_PRIORITY_MASK; 2879 break; 2880 case 4: 2881 if (port) 2882 return ELINK_STATUS_ERROR; 2883 nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS4_PRIORITY_MASK; 2884 break; 2885 case 5: 2886 if (port) 2887 return ELINK_STATUS_ERROR; 2888 nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS5_PRIORITY_MASK; 2889 break; 2890 } 2891 2892 REG_WR(sc, nig_reg_rx_priority_mask_add, priority_mask); 2893 2894 return ELINK_STATUS_OK; 2895 } 2896 static void elink_update_mng(struct elink_params *params, uint32_t link_status) 2897 { 2898 struct bxe_softc *sc = params->sc; 2899 2900 REG_WR(sc, params->shmem_base + 2901 offsetof(struct shmem_region, 2902 port_mb[params->port].link_status), link_status); 2903 } 2904 2905 static void elink_update_link_attr(struct elink_params *params, uint32_t link_attr) 2906 { 2907 struct bxe_softc *sc = params->sc; 2908 2909 if (SHMEM2_HAS(sc, link_attr_sync)) 2910 REG_WR(sc, params->shmem2_base + 2911 offsetof(struct shmem2_region, 2912 link_attr_sync[params->port]), link_attr); 2913 } 2914 2915 static void elink_update_pfc_nig(struct elink_params *params, 2916 struct elink_vars *vars, 2917 struct elink_nig_brb_pfc_port_params *nig_params) 2918 { 2919 uint32_t xcm_mask = 0, ppp_enable = 0, pause_enable = 0, llfc_out_en = 0; 2920 uint32_t llfc_enable = 0, xcm_out_en = 0, hwpfc_enable = 0; 2921 uint32_t pkt_priority_to_cos = 0; 2922 struct bxe_softc *sc = params->sc; 2923 uint8_t port = params->port; 2924 2925 int set_pfc = params->feature_config_flags & 2926 ELINK_FEATURE_CONFIG_PFC_ENABLED; 2927 ELINK_DEBUG_P0(sc, "updating pfc nig parameters\n"); 2928 2929 /* When NIG_LLH0_XCM_MASK_REG_LLHX_XCM_MASK_BCN bit is set 2930 * MAC control frames (that are not pause packets) 2931 * will be forwarded to the XCM. 2932 */ 2933 xcm_mask = REG_RD(sc, port ? NIG_REG_LLH1_XCM_MASK : 2934 NIG_REG_LLH0_XCM_MASK); 2935 /* NIG params will override non PFC params, since it's possible to 2936 * do transition from PFC to SAFC 2937 */ 2938 if (set_pfc) { 2939 pause_enable = 0; 2940 llfc_out_en = 0; 2941 llfc_enable = 0; 2942 if (CHIP_IS_E3(sc)) 2943 ppp_enable = 0; 2944 else 2945 ppp_enable = 1; 2946 xcm_mask &= ~(port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN : 2947 NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN); 2948 xcm_out_en = 0; 2949 hwpfc_enable = 1; 2950 } else { 2951 if (nig_params) { 2952 llfc_out_en = nig_params->llfc_out_en; 2953 llfc_enable = nig_params->llfc_enable; 2954 pause_enable = nig_params->pause_enable; 2955 } else /* Default non PFC mode - PAUSE */ 2956 pause_enable = 1; 2957 2958 xcm_mask |= (port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN : 2959 NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN); 2960 xcm_out_en = 1; 2961 } 2962 2963 if (CHIP_IS_E3(sc)) 2964 REG_WR(sc, port ? NIG_REG_BRB1_PAUSE_IN_EN : 2965 NIG_REG_BRB0_PAUSE_IN_EN, pause_enable); 2966 REG_WR(sc, port ? NIG_REG_LLFC_OUT_EN_1 : 2967 NIG_REG_LLFC_OUT_EN_0, llfc_out_en); 2968 REG_WR(sc, port ? NIG_REG_LLFC_ENABLE_1 : 2969 NIG_REG_LLFC_ENABLE_0, llfc_enable); 2970 REG_WR(sc, port ? NIG_REG_PAUSE_ENABLE_1 : 2971 NIG_REG_PAUSE_ENABLE_0, pause_enable); 2972 2973 REG_WR(sc, port ? NIG_REG_PPP_ENABLE_1 : 2974 NIG_REG_PPP_ENABLE_0, ppp_enable); 2975 2976 REG_WR(sc, port ? NIG_REG_LLH1_XCM_MASK : 2977 NIG_REG_LLH0_XCM_MASK, xcm_mask); 2978 2979 REG_WR(sc, port ? NIG_REG_LLFC_EGRESS_SRC_ENABLE_1 : 2980 NIG_REG_LLFC_EGRESS_SRC_ENABLE_0, 0x7); 2981 2982 /* Output enable for RX_XCM # IF */ 2983 REG_WR(sc, port ? NIG_REG_XCM1_OUT_EN : 2984 NIG_REG_XCM0_OUT_EN, xcm_out_en); 2985 2986 /* HW PFC TX enable */ 2987 REG_WR(sc, port ? NIG_REG_P1_HWPFC_ENABLE : 2988 NIG_REG_P0_HWPFC_ENABLE, hwpfc_enable); 2989 2990 if (nig_params) { 2991 uint8_t i = 0; 2992 pkt_priority_to_cos = nig_params->pkt_priority_to_cos; 2993 2994 for (i = 0; i < nig_params->num_of_rx_cos_priority_mask; i++) 2995 elink_pfc_nig_rx_priority_mask(sc, i, 2996 nig_params->rx_cos_priority_mask[i], port); 2997 2998 REG_WR(sc, port ? NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 : 2999 NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0, 3000 nig_params->llfc_high_priority_classes); 3001 3002 REG_WR(sc, port ? NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 : 3003 NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0, 3004 nig_params->llfc_low_priority_classes); 3005 } 3006 REG_WR(sc, port ? NIG_REG_P1_PKT_PRIORITY_TO_COS : 3007 NIG_REG_P0_PKT_PRIORITY_TO_COS, 3008 pkt_priority_to_cos); 3009 } 3010 3011 elink_status_t elink_update_pfc(struct elink_params *params, 3012 struct elink_vars *vars, 3013 struct elink_nig_brb_pfc_port_params *pfc_params) 3014 { 3015 /* The PFC and pause are orthogonal to one another, meaning when 3016 * PFC is enabled, the pause are disabled, and when PFC is 3017 * disabled, pause are set according to the pause result. 3018 */ 3019 uint32_t val; 3020 struct bxe_softc *sc = params->sc; 3021 elink_status_t elink_status = ELINK_STATUS_OK; 3022 uint8_t bmac_loopback = (params->loopback_mode == ELINK_LOOPBACK_BMAC); 3023 3024 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED) 3025 vars->link_status |= LINK_STATUS_PFC_ENABLED; 3026 else 3027 vars->link_status &= ~LINK_STATUS_PFC_ENABLED; 3028 3029 elink_update_mng(params, vars->link_status); 3030 3031 /* Update NIG params */ 3032 elink_update_pfc_nig(params, vars, pfc_params); 3033 3034 if (!vars->link_up) 3035 return elink_status; 3036 3037 ELINK_DEBUG_P0(sc, "About to update PFC in BMAC\n"); 3038 3039 if (CHIP_IS_E3(sc)) { 3040 if (vars->mac_type == ELINK_MAC_TYPE_XMAC) 3041 elink_update_pfc_xmac(params, vars, 0); 3042 } else { 3043 val = REG_RD(sc, MISC_REG_RESET_REG_2); 3044 if ((val & 3045 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port)) 3046 == 0) { 3047 ELINK_DEBUG_P0(sc, "About to update PFC in EMAC\n"); 3048 elink_emac_enable(params, vars, 0); 3049 return elink_status; 3050 } 3051 if (CHIP_IS_E2(sc)) 3052 elink_update_pfc_bmac2(params, vars, bmac_loopback); 3053 else 3054 elink_update_pfc_bmac1(params, vars); 3055 3056 val = 0; 3057 if ((params->feature_config_flags & 3058 ELINK_FEATURE_CONFIG_PFC_ENABLED) || 3059 (vars->flow_ctrl & ELINK_FLOW_CTRL_TX)) 3060 val = 1; 3061 REG_WR(sc, NIG_REG_BMAC0_PAUSE_OUT_EN + params->port*4, val); 3062 } 3063 return elink_status; 3064 } 3065 3066 static elink_status_t elink_bmac1_enable(struct elink_params *params, 3067 struct elink_vars *vars, 3068 uint8_t is_lb) 3069 { 3070 struct bxe_softc *sc = params->sc; 3071 uint8_t port = params->port; 3072 uint32_t bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM : 3073 NIG_REG_INGRESS_BMAC0_MEM; 3074 uint32_t wb_data[2]; 3075 uint32_t val; 3076 3077 ELINK_DEBUG_P0(sc, "Enabling BigMAC1\n"); 3078 3079 /* XGXS control */ 3080 wb_data[0] = 0x3c; 3081 wb_data[1] = 0; 3082 REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_BMAC_XGXS_CONTROL, 3083 wb_data, 2); 3084 3085 /* TX MAC SA */ 3086 wb_data[0] = ((params->mac_addr[2] << 24) | 3087 (params->mac_addr[3] << 16) | 3088 (params->mac_addr[4] << 8) | 3089 params->mac_addr[5]); 3090 wb_data[1] = ((params->mac_addr[0] << 8) | 3091 params->mac_addr[1]); 3092 REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR, wb_data, 2); 3093 3094 /* MAC control */ 3095 val = 0x3; 3096 if (is_lb) { 3097 val |= 0x4; 3098 ELINK_DEBUG_P0(sc, "enable bmac loopback\n"); 3099 } 3100 wb_data[0] = val; 3101 wb_data[1] = 0; 3102 REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL, wb_data, 2); 3103 3104 /* Set rx mtu */ 3105 wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD; 3106 wb_data[1] = 0; 3107 REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE, wb_data, 2); 3108 3109 elink_update_pfc_bmac1(params, vars); 3110 3111 /* Set tx mtu */ 3112 wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD; 3113 wb_data[1] = 0; 3114 REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE, wb_data, 2); 3115 3116 /* Set cnt max size */ 3117 wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD; 3118 wb_data[1] = 0; 3119 REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE, wb_data, 2); 3120 3121 /* Configure SAFC */ 3122 wb_data[0] = 0x1000200; 3123 wb_data[1] = 0; 3124 REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS, 3125 wb_data, 2); 3126 #ifdef ELINK_INCLUDE_EMUL 3127 /* Fix for emulation */ 3128 if (CHIP_REV_IS_EMUL(sc)) { 3129 wb_data[0] = 0xf000; 3130 wb_data[1] = 0; 3131 REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_TX_PAUSE_THRESHOLD, 3132 wb_data, 2); 3133 } 3134 #endif 3135 3136 return ELINK_STATUS_OK; 3137 } 3138 3139 static elink_status_t elink_bmac2_enable(struct elink_params *params, 3140 struct elink_vars *vars, 3141 uint8_t is_lb) 3142 { 3143 struct bxe_softc *sc = params->sc; 3144 uint8_t port = params->port; 3145 uint32_t bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM : 3146 NIG_REG_INGRESS_BMAC0_MEM; 3147 uint32_t wb_data[2]; 3148 3149 ELINK_DEBUG_P0(sc, "Enabling BigMAC2\n"); 3150 3151 wb_data[0] = 0; 3152 wb_data[1] = 0; 3153 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2); 3154 DELAY(30); 3155 3156 /* XGXS control: Reset phy HW, MDIO registers, PHY PLL and BMAC */ 3157 wb_data[0] = 0x3c; 3158 wb_data[1] = 0; 3159 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_BMAC_XGXS_CONTROL, 3160 wb_data, 2); 3161 3162 DELAY(30); 3163 3164 /* TX MAC SA */ 3165 wb_data[0] = ((params->mac_addr[2] << 24) | 3166 (params->mac_addr[3] << 16) | 3167 (params->mac_addr[4] << 8) | 3168 params->mac_addr[5]); 3169 wb_data[1] = ((params->mac_addr[0] << 8) | 3170 params->mac_addr[1]); 3171 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_TX_SOURCE_ADDR, 3172 wb_data, 2); 3173 3174 DELAY(30); 3175 3176 /* Configure SAFC */ 3177 wb_data[0] = 0x1000200; 3178 wb_data[1] = 0; 3179 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS, 3180 wb_data, 2); 3181 DELAY(30); 3182 3183 /* Set RX MTU */ 3184 wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD; 3185 wb_data[1] = 0; 3186 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_RX_MAX_SIZE, wb_data, 2); 3187 DELAY(30); 3188 3189 /* Set TX MTU */ 3190 wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD; 3191 wb_data[1] = 0; 3192 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_TX_MAX_SIZE, wb_data, 2); 3193 DELAY(30); 3194 /* Set cnt max size */ 3195 wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD - 2; 3196 wb_data[1] = 0; 3197 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_CNT_MAX_SIZE, wb_data, 2); 3198 DELAY(30); 3199 elink_update_pfc_bmac2(params, vars, is_lb); 3200 3201 return ELINK_STATUS_OK; 3202 } 3203 3204 static elink_status_t elink_bmac_enable(struct elink_params *params, 3205 struct elink_vars *vars, 3206 uint8_t is_lb, uint8_t reset_bmac) 3207 { 3208 elink_status_t rc = ELINK_STATUS_OK; 3209 uint8_t port = params->port; 3210 struct bxe_softc *sc = params->sc; 3211 uint32_t val; 3212 /* Reset and unreset the BigMac */ 3213 if (reset_bmac) { 3214 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 3215 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); 3216 DELAY(1000 * 1); 3217 } 3218 3219 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 3220 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); 3221 3222 /* Enable access for bmac registers */ 3223 REG_WR(sc, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1); 3224 3225 /* Enable BMAC according to BMAC type*/ 3226 if (CHIP_IS_E2(sc)) 3227 rc = elink_bmac2_enable(params, vars, is_lb); 3228 else 3229 rc = elink_bmac1_enable(params, vars, is_lb); 3230 REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0x1); 3231 REG_WR(sc, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 0x0); 3232 REG_WR(sc, NIG_REG_EGRESS_EMAC0_PORT + port*4, 0x0); 3233 val = 0; 3234 if ((params->feature_config_flags & 3235 ELINK_FEATURE_CONFIG_PFC_ENABLED) || 3236 (vars->flow_ctrl & ELINK_FLOW_CTRL_TX)) 3237 val = 1; 3238 REG_WR(sc, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, val); 3239 REG_WR(sc, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x0); 3240 REG_WR(sc, NIG_REG_EMAC0_IN_EN + port*4, 0x0); 3241 REG_WR(sc, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, 0x0); 3242 REG_WR(sc, NIG_REG_BMAC0_IN_EN + port*4, 0x1); 3243 REG_WR(sc, NIG_REG_BMAC0_OUT_EN + port*4, 0x1); 3244 3245 vars->mac_type = ELINK_MAC_TYPE_BMAC; 3246 return rc; 3247 } 3248 3249 static void elink_set_bmac_rx(struct bxe_softc *sc, uint32_t chip_id, uint8_t port, uint8_t en) 3250 { 3251 uint32_t bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM : 3252 NIG_REG_INGRESS_BMAC0_MEM; 3253 uint32_t wb_data[2]; 3254 uint32_t nig_bmac_enable = REG_RD(sc, NIG_REG_BMAC0_REGS_OUT_EN + port*4); 3255 3256 if (CHIP_IS_E2(sc)) 3257 bmac_addr += BIGMAC2_REGISTER_BMAC_CONTROL; 3258 else 3259 bmac_addr += BIGMAC_REGISTER_BMAC_CONTROL; 3260 /* Only if the bmac is out of reset */ 3261 if (REG_RD(sc, MISC_REG_RESET_REG_2) & 3262 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port) && 3263 nig_bmac_enable) { 3264 /* Clear Rx Enable bit in BMAC_CONTROL register */ 3265 REG_RD_DMAE(sc, bmac_addr, wb_data, 2); 3266 if (en) 3267 wb_data[0] |= ELINK_BMAC_CONTROL_RX_ENABLE; 3268 else 3269 wb_data[0] &= ~ELINK_BMAC_CONTROL_RX_ENABLE; 3270 REG_WR_DMAE(sc, bmac_addr, wb_data, 2); 3271 DELAY(1000 * 1); 3272 } 3273 } 3274 3275 static elink_status_t elink_pbf_update(struct elink_params *params, uint32_t flow_ctrl, 3276 uint32_t line_speed) 3277 { 3278 struct bxe_softc *sc = params->sc; 3279 uint8_t port = params->port; 3280 uint32_t init_crd, crd; 3281 uint32_t count = 1000; 3282 3283 /* Disable port */ 3284 REG_WR(sc, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1); 3285 3286 /* Wait for init credit */ 3287 init_crd = REG_RD(sc, PBF_REG_P0_INIT_CRD + port*4); 3288 crd = REG_RD(sc, PBF_REG_P0_CREDIT + port*8); 3289 ELINK_DEBUG_P2(sc, "init_crd 0x%x crd 0x%x\n", init_crd, crd); 3290 3291 while ((init_crd != crd) && count) { 3292 DELAY(1000 * 5); 3293 crd = REG_RD(sc, PBF_REG_P0_CREDIT + port*8); 3294 count--; 3295 } 3296 crd = REG_RD(sc, PBF_REG_P0_CREDIT + port*8); 3297 if (init_crd != crd) { 3298 ELINK_DEBUG_P2(sc, "BUG! init_crd 0x%x != crd 0x%x\n", 3299 init_crd, crd); 3300 return ELINK_STATUS_ERROR; 3301 } 3302 3303 if (flow_ctrl & ELINK_FLOW_CTRL_RX || 3304 line_speed == ELINK_SPEED_10 || 3305 line_speed == ELINK_SPEED_100 || 3306 line_speed == ELINK_SPEED_1000 || 3307 line_speed == ELINK_SPEED_2500) { 3308 REG_WR(sc, PBF_REG_P0_PAUSE_ENABLE + port*4, 1); 3309 /* Update threshold */ 3310 REG_WR(sc, PBF_REG_P0_ARB_THRSH + port*4, 0); 3311 /* Update init credit */ 3312 init_crd = 778; /* (800-18-4) */ 3313 3314 } else { 3315 uint32_t thresh = (ELINK_ETH_MAX_JUMBO_PACKET_SIZE + 3316 ELINK_ETH_OVREHEAD)/16; 3317 REG_WR(sc, PBF_REG_P0_PAUSE_ENABLE + port*4, 0); 3318 /* Update threshold */ 3319 REG_WR(sc, PBF_REG_P0_ARB_THRSH + port*4, thresh); 3320 /* Update init credit */ 3321 switch (line_speed) { 3322 case ELINK_SPEED_10000: 3323 init_crd = thresh + 553 - 22; 3324 break; 3325 default: 3326 ELINK_DEBUG_P1(sc, "Invalid line_speed 0x%x\n", 3327 line_speed); 3328 return ELINK_STATUS_ERROR; 3329 } 3330 } 3331 REG_WR(sc, PBF_REG_P0_INIT_CRD + port*4, init_crd); 3332 ELINK_DEBUG_P2(sc, "PBF updated to speed %d credit %d\n", 3333 line_speed, init_crd); 3334 3335 /* Probe the credit changes */ 3336 REG_WR(sc, PBF_REG_INIT_P0 + port*4, 0x1); 3337 DELAY(1000 * 5); 3338 REG_WR(sc, PBF_REG_INIT_P0 + port*4, 0x0); 3339 3340 /* Enable port */ 3341 REG_WR(sc, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x0); 3342 return ELINK_STATUS_OK; 3343 } 3344 3345 /** 3346 * elink_get_emac_base - retrive emac base address 3347 * 3348 * @bp: driver handle 3349 * @mdc_mdio_access: access type 3350 * @port: port id 3351 * 3352 * This function selects the MDC/MDIO access (through emac0 or 3353 * emac1) depend on the mdc_mdio_access, port, port swapped. Each 3354 * phy has a default access mode, which could also be overridden 3355 * by nvram configuration. This parameter, whether this is the 3356 * default phy configuration, or the nvram overrun 3357 * configuration, is passed here as mdc_mdio_access and selects 3358 * the emac_base for the CL45 read/writes operations 3359 */ 3360 static uint32_t elink_get_emac_base(struct bxe_softc *sc, 3361 uint32_t mdc_mdio_access, uint8_t port) 3362 { 3363 uint32_t emac_base = 0; 3364 switch (mdc_mdio_access) { 3365 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE: 3366 break; 3367 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0: 3368 if (REG_RD(sc, NIG_REG_PORT_SWAP)) 3369 emac_base = GRCBASE_EMAC1; 3370 else 3371 emac_base = GRCBASE_EMAC0; 3372 break; 3373 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1: 3374 if (REG_RD(sc, NIG_REG_PORT_SWAP)) 3375 emac_base = GRCBASE_EMAC0; 3376 else 3377 emac_base = GRCBASE_EMAC1; 3378 break; 3379 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH: 3380 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0; 3381 break; 3382 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED: 3383 emac_base = (port) ? GRCBASE_EMAC0 : GRCBASE_EMAC1; 3384 break; 3385 default: 3386 break; 3387 } 3388 return emac_base; 3389 3390 } 3391 3392 /******************************************************************/ 3393 /* CL22 access functions */ 3394 /******************************************************************/ 3395 static elink_status_t elink_cl22_write(struct bxe_softc *sc, 3396 struct elink_phy *phy, 3397 uint16_t reg, uint16_t val) 3398 { 3399 uint32_t tmp, mode; 3400 uint8_t i; 3401 elink_status_t rc = ELINK_STATUS_OK; 3402 /* Switch to CL22 */ 3403 mode = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE); 3404 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, 3405 mode & ~EMAC_MDIO_MODE_CLAUSE_45); 3406 3407 /* Address */ 3408 tmp = ((phy->addr << 21) | (reg << 16) | val | 3409 EMAC_MDIO_COMM_COMMAND_WRITE_22 | 3410 EMAC_MDIO_COMM_START_BUSY); 3411 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp); 3412 3413 for (i = 0; i < 50; i++) { 3414 DELAY(10); 3415 3416 tmp = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); 3417 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) { 3418 DELAY(5); 3419 break; 3420 } 3421 } 3422 if (tmp & EMAC_MDIO_COMM_START_BUSY) { 3423 ELINK_DEBUG_P0(sc, "write phy register failed\n"); 3424 rc = ELINK_STATUS_TIMEOUT; 3425 } 3426 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode); 3427 return rc; 3428 } 3429 3430 static elink_status_t elink_cl22_read(struct bxe_softc *sc, 3431 struct elink_phy *phy, 3432 uint16_t reg, uint16_t *ret_val) 3433 { 3434 uint32_t val, mode; 3435 uint16_t i; 3436 elink_status_t rc = ELINK_STATUS_OK; 3437 3438 /* Switch to CL22 */ 3439 mode = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE); 3440 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, 3441 mode & ~EMAC_MDIO_MODE_CLAUSE_45); 3442 3443 /* Address */ 3444 val = ((phy->addr << 21) | (reg << 16) | 3445 EMAC_MDIO_COMM_COMMAND_READ_22 | 3446 EMAC_MDIO_COMM_START_BUSY); 3447 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val); 3448 3449 for (i = 0; i < 50; i++) { 3450 DELAY(10); 3451 3452 val = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); 3453 if (!(val & EMAC_MDIO_COMM_START_BUSY)) { 3454 *ret_val = (uint16_t)(val & EMAC_MDIO_COMM_DATA); 3455 DELAY(5); 3456 break; 3457 } 3458 } 3459 if (val & EMAC_MDIO_COMM_START_BUSY) { 3460 ELINK_DEBUG_P0(sc, "read phy register failed\n"); 3461 3462 *ret_val = 0; 3463 rc = ELINK_STATUS_TIMEOUT; 3464 } 3465 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode); 3466 return rc; 3467 } 3468 3469 /******************************************************************/ 3470 /* CL45 access functions */ 3471 /******************************************************************/ 3472 static elink_status_t elink_cl45_read(struct bxe_softc *sc, struct elink_phy *phy, 3473 uint8_t devad, uint16_t reg, uint16_t *ret_val) 3474 { 3475 uint32_t val; 3476 uint16_t i; 3477 elink_status_t rc = ELINK_STATUS_OK; 3478 uint32_t chip_id; 3479 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_G) { 3480 chip_id = (REG_RD(sc, MISC_REG_CHIP_NUM) << 16) | 3481 ((REG_RD(sc, MISC_REG_CHIP_REV) & 0xf) << 12); 3482 elink_set_mdio_clk(sc, chip_id, phy->mdio_ctrl); 3483 } 3484 3485 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_B0) 3486 elink_bits_en(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, 3487 EMAC_MDIO_STATUS_10MB); 3488 /* Address */ 3489 val = ((phy->addr << 21) | (devad << 16) | reg | 3490 EMAC_MDIO_COMM_COMMAND_ADDRESS | 3491 EMAC_MDIO_COMM_START_BUSY); 3492 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val); 3493 3494 for (i = 0; i < 50; i++) { 3495 DELAY(10); 3496 3497 val = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); 3498 if (!(val & EMAC_MDIO_COMM_START_BUSY)) { 3499 DELAY(5); 3500 break; 3501 } 3502 } 3503 if (val & EMAC_MDIO_COMM_START_BUSY) { 3504 ELINK_DEBUG_P0(sc, "read phy register failed\n"); 3505 elink_cb_event_log(sc, ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT); // "MDC/MDIO access timeout\n" 3506 3507 *ret_val = 0; 3508 rc = ELINK_STATUS_TIMEOUT; 3509 } else { 3510 /* Data */ 3511 val = ((phy->addr << 21) | (devad << 16) | 3512 EMAC_MDIO_COMM_COMMAND_READ_45 | 3513 EMAC_MDIO_COMM_START_BUSY); 3514 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val); 3515 3516 for (i = 0; i < 50; i++) { 3517 DELAY(10); 3518 3519 val = REG_RD(sc, phy->mdio_ctrl + 3520 EMAC_REG_EMAC_MDIO_COMM); 3521 if (!(val & EMAC_MDIO_COMM_START_BUSY)) { 3522 *ret_val = (uint16_t)(val & EMAC_MDIO_COMM_DATA); 3523 break; 3524 } 3525 } 3526 if (val & EMAC_MDIO_COMM_START_BUSY) { 3527 ELINK_DEBUG_P0(sc, "read phy register failed\n"); 3528 elink_cb_event_log(sc, ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT); // "MDC/MDIO access timeout\n" 3529 3530 *ret_val = 0; 3531 rc = ELINK_STATUS_TIMEOUT; 3532 } 3533 } 3534 /* Work around for E3 A0 */ 3535 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA) { 3536 phy->flags ^= ELINK_FLAGS_DUMMY_READ; 3537 if (phy->flags & ELINK_FLAGS_DUMMY_READ) { 3538 uint16_t temp_val; 3539 elink_cl45_read(sc, phy, devad, 0xf, &temp_val); 3540 } 3541 } 3542 3543 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_B0) 3544 elink_bits_dis(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, 3545 EMAC_MDIO_STATUS_10MB); 3546 return rc; 3547 } 3548 3549 static elink_status_t elink_cl45_write(struct bxe_softc *sc, struct elink_phy *phy, 3550 uint8_t devad, uint16_t reg, uint16_t val) 3551 { 3552 uint32_t tmp; 3553 uint8_t i; 3554 elink_status_t rc = ELINK_STATUS_OK; 3555 uint32_t chip_id; 3556 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_G) { 3557 chip_id = (REG_RD(sc, MISC_REG_CHIP_NUM) << 16) | 3558 ((REG_RD(sc, MISC_REG_CHIP_REV) & 0xf) << 12); 3559 elink_set_mdio_clk(sc, chip_id, phy->mdio_ctrl); 3560 } 3561 3562 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_B0) 3563 elink_bits_en(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, 3564 EMAC_MDIO_STATUS_10MB); 3565 3566 /* Address */ 3567 tmp = ((phy->addr << 21) | (devad << 16) | reg | 3568 EMAC_MDIO_COMM_COMMAND_ADDRESS | 3569 EMAC_MDIO_COMM_START_BUSY); 3570 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp); 3571 3572 for (i = 0; i < 50; i++) { 3573 DELAY(10); 3574 3575 tmp = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM); 3576 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) { 3577 DELAY(5); 3578 break; 3579 } 3580 } 3581 if (tmp & EMAC_MDIO_COMM_START_BUSY) { 3582 ELINK_DEBUG_P0(sc, "write phy register failed\n"); 3583 elink_cb_event_log(sc, ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT); // "MDC/MDIO access timeout\n" 3584 3585 rc = ELINK_STATUS_TIMEOUT; 3586 } else { 3587 /* Data */ 3588 tmp = ((phy->addr << 21) | (devad << 16) | val | 3589 EMAC_MDIO_COMM_COMMAND_WRITE_45 | 3590 EMAC_MDIO_COMM_START_BUSY); 3591 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp); 3592 3593 for (i = 0; i < 50; i++) { 3594 DELAY(10); 3595 3596 tmp = REG_RD(sc, phy->mdio_ctrl + 3597 EMAC_REG_EMAC_MDIO_COMM); 3598 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) { 3599 DELAY(5); 3600 break; 3601 } 3602 } 3603 if (tmp & EMAC_MDIO_COMM_START_BUSY) { 3604 ELINK_DEBUG_P0(sc, "write phy register failed\n"); 3605 elink_cb_event_log(sc, ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT); // "MDC/MDIO access timeout\n" 3606 3607 rc = ELINK_STATUS_TIMEOUT; 3608 } 3609 } 3610 /* Work around for E3 A0 */ 3611 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA) { 3612 phy->flags ^= ELINK_FLAGS_DUMMY_READ; 3613 if (phy->flags & ELINK_FLAGS_DUMMY_READ) { 3614 uint16_t temp_val; 3615 elink_cl45_read(sc, phy, devad, 0xf, &temp_val); 3616 } 3617 } 3618 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_B0) 3619 elink_bits_dis(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS, 3620 EMAC_MDIO_STATUS_10MB); 3621 return rc; 3622 } 3623 3624 /******************************************************************/ 3625 /* EEE section */ 3626 /******************************************************************/ 3627 static uint8_t elink_eee_has_cap(struct elink_params *params) 3628 { 3629 struct bxe_softc *sc = params->sc; 3630 3631 if (REG_RD(sc, params->shmem2_base) <= 3632 offsetof(struct shmem2_region, eee_status[params->port])) 3633 return 0; 3634 3635 return 1; 3636 } 3637 3638 static elink_status_t elink_eee_nvram_to_time(uint32_t nvram_mode, uint32_t *idle_timer) 3639 { 3640 switch (nvram_mode) { 3641 case PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED: 3642 *idle_timer = ELINK_EEE_MODE_NVRAM_BALANCED_TIME; 3643 break; 3644 case PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE: 3645 *idle_timer = ELINK_EEE_MODE_NVRAM_AGGRESSIVE_TIME; 3646 break; 3647 case PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY: 3648 *idle_timer = ELINK_EEE_MODE_NVRAM_LATENCY_TIME; 3649 break; 3650 default: 3651 *idle_timer = 0; 3652 break; 3653 } 3654 3655 return ELINK_STATUS_OK; 3656 } 3657 3658 static elink_status_t elink_eee_time_to_nvram(uint32_t idle_timer, uint32_t *nvram_mode) 3659 { 3660 switch (idle_timer) { 3661 case ELINK_EEE_MODE_NVRAM_BALANCED_TIME: 3662 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED; 3663 break; 3664 case ELINK_EEE_MODE_NVRAM_AGGRESSIVE_TIME: 3665 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE; 3666 break; 3667 case ELINK_EEE_MODE_NVRAM_LATENCY_TIME: 3668 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY; 3669 break; 3670 default: 3671 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED; 3672 break; 3673 } 3674 3675 return ELINK_STATUS_OK; 3676 } 3677 3678 static uint32_t elink_eee_calc_timer(struct elink_params *params) 3679 { 3680 uint32_t eee_mode, eee_idle; 3681 struct bxe_softc *sc = params->sc; 3682 3683 if (params->eee_mode & ELINK_EEE_MODE_OVERRIDE_NVRAM) { 3684 if (params->eee_mode & ELINK_EEE_MODE_OUTPUT_TIME) { 3685 /* time value in eee_mode --> used directly*/ 3686 eee_idle = params->eee_mode & ELINK_EEE_MODE_TIMER_MASK; 3687 } else { 3688 /* hsi value in eee_mode --> time */ 3689 if (elink_eee_nvram_to_time(params->eee_mode & 3690 ELINK_EEE_MODE_NVRAM_MASK, 3691 &eee_idle)) 3692 return 0; 3693 } 3694 } else { 3695 /* hsi values in nvram --> time*/ 3696 eee_mode = ((REG_RD(sc, params->shmem_base + 3697 offsetof(struct shmem_region, dev_info. 3698 port_feature_config[params->port]. 3699 eee_power_mode)) & 3700 PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >> 3701 PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT); 3702 3703 if (elink_eee_nvram_to_time(eee_mode, &eee_idle)) 3704 return 0; 3705 } 3706 3707 return eee_idle; 3708 } 3709 3710 static elink_status_t elink_eee_set_timers(struct elink_params *params, 3711 struct elink_vars *vars) 3712 { 3713 uint32_t eee_idle = 0, eee_mode; 3714 struct bxe_softc *sc = params->sc; 3715 3716 eee_idle = elink_eee_calc_timer(params); 3717 3718 if (eee_idle) { 3719 REG_WR(sc, MISC_REG_CPMU_LP_IDLE_THR_P0 + (params->port << 2), 3720 eee_idle); 3721 } else if ((params->eee_mode & ELINK_EEE_MODE_ENABLE_LPI) && 3722 (params->eee_mode & ELINK_EEE_MODE_OVERRIDE_NVRAM) && 3723 (params->eee_mode & ELINK_EEE_MODE_OUTPUT_TIME)) { 3724 ELINK_DEBUG_P0(sc, "Error: Tx LPI is enabled with timer 0\n"); 3725 return ELINK_STATUS_ERROR; 3726 } 3727 3728 vars->eee_status &= ~(SHMEM_EEE_TIMER_MASK | SHMEM_EEE_TIME_OUTPUT_BIT); 3729 if (params->eee_mode & ELINK_EEE_MODE_OUTPUT_TIME) { 3730 /* eee_idle in 1u --> eee_status in 16u */ 3731 eee_idle >>= 4; 3732 vars->eee_status |= (eee_idle & SHMEM_EEE_TIMER_MASK) | 3733 SHMEM_EEE_TIME_OUTPUT_BIT; 3734 } else { 3735 if (elink_eee_time_to_nvram(eee_idle, &eee_mode)) 3736 return ELINK_STATUS_ERROR; 3737 vars->eee_status |= eee_mode; 3738 } 3739 3740 return ELINK_STATUS_OK; 3741 } 3742 3743 static elink_status_t elink_eee_initial_config(struct elink_params *params, 3744 struct elink_vars *vars, uint8_t mode) 3745 { 3746 vars->eee_status |= ((uint32_t) mode) << SHMEM_EEE_SUPPORTED_SHIFT; 3747 3748 /* Propogate params' bits --> vars (for migration exposure) */ 3749 if (params->eee_mode & ELINK_EEE_MODE_ENABLE_LPI) 3750 vars->eee_status |= SHMEM_EEE_LPI_REQUESTED_BIT; 3751 else 3752 vars->eee_status &= ~SHMEM_EEE_LPI_REQUESTED_BIT; 3753 3754 if (params->eee_mode & ELINK_EEE_MODE_ADV_LPI) 3755 vars->eee_status |= SHMEM_EEE_REQUESTED_BIT; 3756 else 3757 vars->eee_status &= ~SHMEM_EEE_REQUESTED_BIT; 3758 3759 return elink_eee_set_timers(params, vars); 3760 } 3761 3762 static elink_status_t elink_eee_disable(struct elink_phy *phy, 3763 struct elink_params *params, 3764 struct elink_vars *vars) 3765 { 3766 struct bxe_softc *sc = params->sc; 3767 3768 /* Make Certain LPI is disabled */ 3769 REG_WR(sc, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2), 0); 3770 3771 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, 0x0); 3772 3773 vars->eee_status &= ~SHMEM_EEE_ADV_STATUS_MASK; 3774 3775 return ELINK_STATUS_OK; 3776 } 3777 3778 static elink_status_t elink_eee_advertise(struct elink_phy *phy, 3779 struct elink_params *params, 3780 struct elink_vars *vars, uint8_t modes) 3781 { 3782 struct bxe_softc *sc = params->sc; 3783 uint16_t val = 0; 3784 3785 /* Mask events preventing LPI generation */ 3786 REG_WR(sc, MISC_REG_CPMU_LP_MASK_EXT_P0 + (params->port << 2), 0xfc20); 3787 3788 if (modes & SHMEM_EEE_10G_ADV) { 3789 ELINK_DEBUG_P0(sc, "Advertise 10GBase-T EEE\n"); 3790 val |= 0x8; 3791 } 3792 if (modes & SHMEM_EEE_1G_ADV) { 3793 ELINK_DEBUG_P0(sc, "Advertise 1GBase-T EEE\n"); 3794 val |= 0x4; 3795 } 3796 3797 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, val); 3798 3799 vars->eee_status &= ~SHMEM_EEE_ADV_STATUS_MASK; 3800 vars->eee_status |= (modes << SHMEM_EEE_ADV_STATUS_SHIFT); 3801 3802 return ELINK_STATUS_OK; 3803 } 3804 3805 static void elink_update_mng_eee(struct elink_params *params, uint32_t eee_status) 3806 { 3807 struct bxe_softc *sc = params->sc; 3808 3809 if (elink_eee_has_cap(params)) 3810 REG_WR(sc, params->shmem2_base + 3811 offsetof(struct shmem2_region, 3812 eee_status[params->port]), eee_status); 3813 } 3814 3815 static void elink_eee_an_resolve(struct elink_phy *phy, 3816 struct elink_params *params, 3817 struct elink_vars *vars) 3818 { 3819 struct bxe_softc *sc = params->sc; 3820 uint16_t adv = 0, lp = 0; 3821 uint32_t lp_adv = 0; 3822 uint8_t neg = 0; 3823 3824 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, &adv); 3825 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_LP_EEE_ADV, &lp); 3826 3827 if (lp & 0x2) { 3828 lp_adv |= SHMEM_EEE_100M_ADV; 3829 if (adv & 0x2) { 3830 if (vars->line_speed == ELINK_SPEED_100) 3831 neg = 1; 3832 ELINK_DEBUG_P0(sc, "EEE negotiated - 100M\n"); 3833 } 3834 } 3835 if (lp & 0x14) { 3836 lp_adv |= SHMEM_EEE_1G_ADV; 3837 if (adv & 0x14) { 3838 if (vars->line_speed == ELINK_SPEED_1000) 3839 neg = 1; 3840 ELINK_DEBUG_P0(sc, "EEE negotiated - 1G\n"); 3841 } 3842 } 3843 if (lp & 0x68) { 3844 lp_adv |= SHMEM_EEE_10G_ADV; 3845 if (adv & 0x68) { 3846 if (vars->line_speed == ELINK_SPEED_10000) 3847 neg = 1; 3848 ELINK_DEBUG_P0(sc, "EEE negotiated - 10G\n"); 3849 } 3850 } 3851 3852 vars->eee_status &= ~SHMEM_EEE_LP_ADV_STATUS_MASK; 3853 vars->eee_status |= (lp_adv << SHMEM_EEE_LP_ADV_STATUS_SHIFT); 3854 3855 if (neg) { 3856 ELINK_DEBUG_P0(sc, "EEE is active\n"); 3857 vars->eee_status |= SHMEM_EEE_ACTIVE_BIT; 3858 } 3859 } 3860 3861 /******************************************************************/ 3862 /* BSC access functions from E3 */ 3863 /******************************************************************/ 3864 static void elink_bsc_module_sel(struct elink_params *params) 3865 { 3866 int idx; 3867 uint32_t board_cfg, sfp_ctrl; 3868 uint32_t i2c_pins[I2C_SWITCH_WIDTH], i2c_val[I2C_SWITCH_WIDTH]; 3869 struct bxe_softc *sc = params->sc; 3870 uint8_t port = params->port; 3871 /* Read I2C output PINs */ 3872 board_cfg = REG_RD(sc, params->shmem_base + 3873 offsetof(struct shmem_region, 3874 dev_info.shared_hw_config.board)); 3875 i2c_pins[I2C_BSC0] = board_cfg & SHARED_HW_CFG_E3_I2C_MUX0_MASK; 3876 i2c_pins[I2C_BSC1] = (board_cfg & SHARED_HW_CFG_E3_I2C_MUX1_MASK) >> 3877 SHARED_HW_CFG_E3_I2C_MUX1_SHIFT; 3878 3879 /* Read I2C output value */ 3880 sfp_ctrl = REG_RD(sc, params->shmem_base + 3881 offsetof(struct shmem_region, 3882 dev_info.port_hw_config[port].e3_cmn_pin_cfg)); 3883 i2c_val[I2C_BSC0] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX0_MASK) > 0; 3884 i2c_val[I2C_BSC1] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX1_MASK) > 0; 3885 ELINK_DEBUG_P0(sc, "Setting BSC switch\n"); 3886 for (idx = 0; idx < I2C_SWITCH_WIDTH; idx++) 3887 elink_set_cfg_pin(sc, i2c_pins[idx], i2c_val[idx]); 3888 } 3889 3890 static elink_status_t elink_bsc_read(struct elink_params *params, 3891 struct bxe_softc *sc, 3892 uint8_t sl_devid, 3893 uint16_t sl_addr, 3894 uint8_t lc_addr, 3895 uint8_t xfer_cnt, 3896 uint32_t *data_array) 3897 { 3898 uint32_t val, i; 3899 elink_status_t rc = ELINK_STATUS_OK; 3900 3901 if (xfer_cnt > 16) { 3902 ELINK_DEBUG_P1(sc, "invalid xfer_cnt %d. Max is 16 bytes\n", 3903 xfer_cnt); 3904 return ELINK_STATUS_ERROR; 3905 } 3906 if (params) 3907 elink_bsc_module_sel(params); 3908 3909 xfer_cnt = 16 - lc_addr; 3910 3911 /* Enable the engine */ 3912 val = REG_RD(sc, MCP_REG_MCPR_IMC_COMMAND); 3913 val |= MCPR_IMC_COMMAND_ENABLE; 3914 REG_WR(sc, MCP_REG_MCPR_IMC_COMMAND, val); 3915 3916 /* Program slave device ID */ 3917 val = (sl_devid << 16) | sl_addr; 3918 REG_WR(sc, MCP_REG_MCPR_IMC_SLAVE_CONTROL, val); 3919 3920 /* Start xfer with 0 byte to update the address pointer ???*/ 3921 val = (MCPR_IMC_COMMAND_ENABLE) | 3922 (MCPR_IMC_COMMAND_WRITE_OP << 3923 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) | 3924 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) | (0); 3925 REG_WR(sc, MCP_REG_MCPR_IMC_COMMAND, val); 3926 3927 /* Poll for completion */ 3928 i = 0; 3929 val = REG_RD(sc, MCP_REG_MCPR_IMC_COMMAND); 3930 while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) { 3931 DELAY(10); 3932 val = REG_RD(sc, MCP_REG_MCPR_IMC_COMMAND); 3933 if (i++ > 1000) { 3934 ELINK_DEBUG_P1(sc, "wr 0 byte timed out after %d try\n", 3935 i); 3936 rc = ELINK_STATUS_TIMEOUT; 3937 break; 3938 } 3939 } 3940 if (rc == ELINK_STATUS_TIMEOUT) 3941 return rc; 3942 3943 /* Start xfer with read op */ 3944 val = (MCPR_IMC_COMMAND_ENABLE) | 3945 (MCPR_IMC_COMMAND_READ_OP << 3946 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) | 3947 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) | 3948 (xfer_cnt); 3949 REG_WR(sc, MCP_REG_MCPR_IMC_COMMAND, val); 3950 3951 /* Poll for completion */ 3952 i = 0; 3953 val = REG_RD(sc, MCP_REG_MCPR_IMC_COMMAND); 3954 while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) { 3955 DELAY(10); 3956 val = REG_RD(sc, MCP_REG_MCPR_IMC_COMMAND); 3957 if (i++ > 1000) { 3958 ELINK_DEBUG_P1(sc, "rd op timed out after %d try\n", i); 3959 rc = ELINK_STATUS_TIMEOUT; 3960 break; 3961 } 3962 } 3963 if (rc == ELINK_STATUS_TIMEOUT) 3964 return rc; 3965 3966 for (i = (lc_addr >> 2); i < 4; i++) { 3967 data_array[i] = REG_RD(sc, (MCP_REG_MCPR_IMC_DATAREG0 + i*4)); 3968 #ifdef __BIG_ENDIAN 3969 data_array[i] = ((data_array[i] & 0x000000ff) << 24) | 3970 ((data_array[i] & 0x0000ff00) << 8) | 3971 ((data_array[i] & 0x00ff0000) >> 8) | 3972 ((data_array[i] & 0xff000000) >> 24); 3973 #endif 3974 } 3975 return rc; 3976 } 3977 3978 static void elink_cl45_read_or_write(struct bxe_softc *sc, struct elink_phy *phy, 3979 uint8_t devad, uint16_t reg, uint16_t or_val) 3980 { 3981 uint16_t val; 3982 elink_cl45_read(sc, phy, devad, reg, &val); 3983 elink_cl45_write(sc, phy, devad, reg, val | or_val); 3984 } 3985 3986 static void elink_cl45_read_and_write(struct bxe_softc *sc, 3987 struct elink_phy *phy, 3988 uint8_t devad, uint16_t reg, uint16_t and_val) 3989 { 3990 uint16_t val; 3991 elink_cl45_read(sc, phy, devad, reg, &val); 3992 elink_cl45_write(sc, phy, devad, reg, val & and_val); 3993 } 3994 3995 elink_status_t elink_phy_read(struct elink_params *params, uint8_t phy_addr, 3996 uint8_t devad, uint16_t reg, uint16_t *ret_val) 3997 { 3998 uint8_t phy_index; 3999 /* Probe for the phy according to the given phy_addr, and execute 4000 * the read request on it 4001 */ 4002 for (phy_index = 0; phy_index < params->num_phys; phy_index++) { 4003 if (params->phy[phy_index].addr == phy_addr) { 4004 return elink_cl45_read(params->sc, 4005 ¶ms->phy[phy_index], devad, 4006 reg, ret_val); 4007 } 4008 } 4009 return ELINK_STATUS_ERROR; 4010 } 4011 4012 elink_status_t elink_phy_write(struct elink_params *params, uint8_t phy_addr, 4013 uint8_t devad, uint16_t reg, uint16_t val) 4014 { 4015 uint8_t phy_index; 4016 /* Probe for the phy according to the given phy_addr, and execute 4017 * the write request on it 4018 */ 4019 for (phy_index = 0; phy_index < params->num_phys; phy_index++) { 4020 if (params->phy[phy_index].addr == phy_addr) { 4021 return elink_cl45_write(params->sc, 4022 ¶ms->phy[phy_index], devad, 4023 reg, val); 4024 } 4025 } 4026 return ELINK_STATUS_ERROR; 4027 } 4028 static uint8_t elink_get_warpcore_lane(struct elink_phy *phy, 4029 struct elink_params *params) 4030 { 4031 uint8_t lane = 0; 4032 struct bxe_softc *sc = params->sc; 4033 uint32_t path_swap, path_swap_ovr; 4034 uint8_t path, port; 4035 4036 path = SC_PATH(sc); 4037 port = params->port; 4038 4039 if (elink_is_4_port_mode(sc)) { 4040 uint32_t port_swap, port_swap_ovr; 4041 4042 /* Figure out path swap value */ 4043 path_swap_ovr = REG_RD(sc, MISC_REG_FOUR_PORT_PATH_SWAP_OVWR); 4044 if (path_swap_ovr & 0x1) 4045 path_swap = (path_swap_ovr & 0x2); 4046 else 4047 path_swap = REG_RD(sc, MISC_REG_FOUR_PORT_PATH_SWAP); 4048 4049 if (path_swap) 4050 path = path ^ 1; 4051 4052 /* Figure out port swap value */ 4053 port_swap_ovr = REG_RD(sc, MISC_REG_FOUR_PORT_PORT_SWAP_OVWR); 4054 if (port_swap_ovr & 0x1) 4055 port_swap = (port_swap_ovr & 0x2); 4056 else 4057 port_swap = REG_RD(sc, MISC_REG_FOUR_PORT_PORT_SWAP); 4058 4059 if (port_swap) 4060 port = port ^ 1; 4061 4062 lane = (port<<1) + path; 4063 } else { /* Two port mode - no port swap */ 4064 4065 /* Figure out path swap value */ 4066 path_swap_ovr = 4067 REG_RD(sc, MISC_REG_TWO_PORT_PATH_SWAP_OVWR); 4068 if (path_swap_ovr & 0x1) { 4069 path_swap = (path_swap_ovr & 0x2); 4070 } else { 4071 path_swap = 4072 REG_RD(sc, MISC_REG_TWO_PORT_PATH_SWAP); 4073 } 4074 if (path_swap) 4075 path = path ^ 1; 4076 4077 lane = path << 1 ; 4078 } 4079 return lane; 4080 } 4081 4082 static void elink_set_aer_mmd(struct elink_params *params, 4083 struct elink_phy *phy) 4084 { 4085 uint32_t ser_lane; 4086 uint16_t offset, aer_val; 4087 struct bxe_softc *sc = params->sc; 4088 ser_lane = ((params->lane_config & 4089 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >> 4090 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT); 4091 4092 offset = (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ? 4093 (phy->addr + ser_lane) : 0; 4094 4095 if (USES_WARPCORE(sc)) { 4096 aer_val = elink_get_warpcore_lane(phy, params); 4097 /* In Dual-lane mode, two lanes are joined together, 4098 * so in order to configure them, the AER broadcast method is 4099 * used here. 4100 * 0x200 is the broadcast address for lanes 0,1 4101 * 0x201 is the broadcast address for lanes 2,3 4102 */ 4103 if (phy->flags & ELINK_FLAGS_WC_DUAL_MODE) 4104 aer_val = (aer_val >> 1) | 0x200; 4105 } else if (CHIP_IS_E2(sc)) 4106 aer_val = 0x3800 + offset - 1; 4107 else 4108 aer_val = 0x3800 + offset; 4109 4110 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK, 4111 MDIO_AER_BLOCK_AER_REG, aer_val); 4112 4113 } 4114 4115 /******************************************************************/ 4116 /* Internal phy section */ 4117 /******************************************************************/ 4118 4119 static void elink_set_serdes_access(struct bxe_softc *sc, uint8_t port) 4120 { 4121 uint32_t emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0; 4122 4123 /* Set Clause 22 */ 4124 REG_WR(sc, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 1); 4125 REG_WR(sc, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000); 4126 DELAY(500); 4127 REG_WR(sc, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f); 4128 DELAY(500); 4129 /* Set Clause 45 */ 4130 REG_WR(sc, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 0); 4131 } 4132 4133 static void elink_serdes_deassert(struct bxe_softc *sc, uint8_t port) 4134 { 4135 uint32_t val; 4136 4137 ELINK_DEBUG_P0(sc, "elink_serdes_deassert\n"); 4138 4139 val = ELINK_SERDES_RESET_BITS << (port*16); 4140 4141 /* Reset and unreset the SerDes/XGXS */ 4142 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val); 4143 DELAY(500); 4144 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val); 4145 4146 elink_set_serdes_access(sc, port); 4147 4148 REG_WR(sc, NIG_REG_SERDES0_CTRL_MD_DEVAD + port*0x10, 4149 ELINK_DEFAULT_PHY_DEV_ADDR); 4150 } 4151 4152 static void elink_xgxs_specific_func(struct elink_phy *phy, 4153 struct elink_params *params, 4154 uint32_t action) 4155 { 4156 struct bxe_softc *sc = params->sc; 4157 switch (action) { 4158 case ELINK_PHY_INIT: 4159 /* Set correct devad */ 4160 REG_WR(sc, NIG_REG_XGXS0_CTRL_MD_ST + params->port*0x18, 0); 4161 REG_WR(sc, NIG_REG_XGXS0_CTRL_MD_DEVAD + params->port*0x18, 4162 phy->def_md_devad); 4163 break; 4164 } 4165 } 4166 4167 static void elink_xgxs_deassert(struct elink_params *params) 4168 { 4169 struct bxe_softc *sc = params->sc; 4170 uint8_t port; 4171 uint32_t val; 4172 ELINK_DEBUG_P0(sc, "elink_xgxs_deassert\n"); 4173 port = params->port; 4174 4175 val = ELINK_XGXS_RESET_BITS << (port*16); 4176 4177 /* Reset and unreset the SerDes/XGXS */ 4178 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val); 4179 DELAY(500); 4180 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val); 4181 elink_xgxs_specific_func(¶ms->phy[ELINK_INT_PHY], params, 4182 ELINK_PHY_INIT); 4183 } 4184 4185 static void elink_calc_ieee_aneg_adv(struct elink_phy *phy, 4186 struct elink_params *params, uint16_t *ieee_fc) 4187 { 4188 struct bxe_softc *sc = params->sc; 4189 *ieee_fc = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX; 4190 /* Resolve pause mode and advertisement Please refer to Table 4191 * 28B-3 of the 802.3ab-1999 spec 4192 */ 4193 4194 switch (phy->req_flow_ctrl) { 4195 case ELINK_FLOW_CTRL_AUTO: 4196 switch (params->req_fc_auto_adv) { 4197 case ELINK_FLOW_CTRL_BOTH: 4198 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH; 4199 break; 4200 case ELINK_FLOW_CTRL_RX: 4201 case ELINK_FLOW_CTRL_TX: 4202 *ieee_fc |= 4203 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC; 4204 break; 4205 default: 4206 break; 4207 } 4208 break; 4209 case ELINK_FLOW_CTRL_TX: 4210 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC; 4211 break; 4212 4213 case ELINK_FLOW_CTRL_RX: 4214 case ELINK_FLOW_CTRL_BOTH: 4215 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH; 4216 break; 4217 4218 case ELINK_FLOW_CTRL_NONE: 4219 default: 4220 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE; 4221 break; 4222 } 4223 ELINK_DEBUG_P1(sc, "ieee_fc = 0x%x\n", *ieee_fc); 4224 } 4225 4226 static void set_phy_vars(struct elink_params *params, 4227 struct elink_vars *vars) 4228 { 4229 struct bxe_softc *sc = params->sc; 4230 uint8_t actual_phy_idx, phy_index, link_cfg_idx; 4231 uint8_t phy_config_swapped = params->multi_phy_config & 4232 PORT_HW_CFG_PHY_SWAPPED_ENABLED; 4233 for (phy_index = ELINK_INT_PHY; phy_index < params->num_phys; 4234 phy_index++) { 4235 link_cfg_idx = ELINK_LINK_CONFIG_IDX(phy_index); 4236 actual_phy_idx = phy_index; 4237 if (phy_config_swapped) { 4238 if (phy_index == ELINK_EXT_PHY1) 4239 actual_phy_idx = ELINK_EXT_PHY2; 4240 else if (phy_index == ELINK_EXT_PHY2) 4241 actual_phy_idx = ELINK_EXT_PHY1; 4242 } 4243 params->phy[actual_phy_idx].req_flow_ctrl = 4244 params->req_flow_ctrl[link_cfg_idx]; 4245 4246 params->phy[actual_phy_idx].req_line_speed = 4247 params->req_line_speed[link_cfg_idx]; 4248 4249 params->phy[actual_phy_idx].speed_cap_mask = 4250 params->speed_cap_mask[link_cfg_idx]; 4251 4252 params->phy[actual_phy_idx].req_duplex = 4253 params->req_duplex[link_cfg_idx]; 4254 4255 if (params->req_line_speed[link_cfg_idx] == 4256 ELINK_SPEED_AUTO_NEG) 4257 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED; 4258 4259 ELINK_DEBUG_P3(sc, "req_flow_ctrl %x, req_line_speed %x," 4260 " speed_cap_mask %x\n", 4261 params->phy[actual_phy_idx].req_flow_ctrl, 4262 params->phy[actual_phy_idx].req_line_speed, 4263 params->phy[actual_phy_idx].speed_cap_mask); 4264 } 4265 } 4266 4267 static void elink_ext_phy_set_pause(struct elink_params *params, 4268 struct elink_phy *phy, 4269 struct elink_vars *vars) 4270 { 4271 uint16_t val; 4272 struct bxe_softc *sc = params->sc; 4273 /* Read modify write pause advertizing */ 4274 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, &val); 4275 4276 val &= ~MDIO_AN_REG_ADV_PAUSE_BOTH; 4277 4278 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */ 4279 elink_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc); 4280 if ((vars->ieee_fc & 4281 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) == 4282 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) { 4283 val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC; 4284 } 4285 if ((vars->ieee_fc & 4286 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) == 4287 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) { 4288 val |= MDIO_AN_REG_ADV_PAUSE_PAUSE; 4289 } 4290 ELINK_DEBUG_P1(sc, "Ext phy AN advertize 0x%x\n", val); 4291 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, val); 4292 } 4293 4294 static void elink_pause_resolve(struct elink_vars *vars, uint32_t pause_result) 4295 { /* LD LP */ 4296 switch (pause_result) { /* ASYM P ASYM P */ 4297 case 0xb: /* 1 0 1 1 */ 4298 vars->flow_ctrl = ELINK_FLOW_CTRL_TX; 4299 break; 4300 4301 case 0xe: /* 1 1 1 0 */ 4302 vars->flow_ctrl = ELINK_FLOW_CTRL_RX; 4303 break; 4304 4305 case 0x5: /* 0 1 0 1 */ 4306 case 0x7: /* 0 1 1 1 */ 4307 case 0xd: /* 1 1 0 1 */ 4308 case 0xf: /* 1 1 1 1 */ 4309 vars->flow_ctrl = ELINK_FLOW_CTRL_BOTH; 4310 break; 4311 4312 default: 4313 break; 4314 } 4315 if (pause_result & (1<<0)) 4316 vars->link_status |= LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE; 4317 if (pause_result & (1<<1)) 4318 vars->link_status |= LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE; 4319 4320 } 4321 4322 static void elink_ext_phy_update_adv_fc(struct elink_phy *phy, 4323 struct elink_params *params, 4324 struct elink_vars *vars) 4325 { 4326 uint16_t ld_pause; /* local */ 4327 uint16_t lp_pause; /* link partner */ 4328 uint16_t pause_result; 4329 struct bxe_softc *sc = params->sc; 4330 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) { 4331 elink_cl22_read(sc, phy, 0x4, &ld_pause); 4332 elink_cl22_read(sc, phy, 0x5, &lp_pause); 4333 } else if (CHIP_IS_E3(sc) && 4334 ELINK_SINGLE_MEDIA_DIRECT(params)) { 4335 uint8_t lane = elink_get_warpcore_lane(phy, params); 4336 uint16_t gp_status, gp_mask; 4337 elink_cl45_read(sc, phy, 4338 MDIO_AN_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_4, 4339 &gp_status); 4340 gp_mask = (MDIO_WC_REG_GP2_STATUS_GP_2_4_CL73_AN_CMPL | 4341 MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_LP_AN_CAP) << 4342 lane; 4343 if ((gp_status & gp_mask) == gp_mask) { 4344 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, 4345 MDIO_AN_REG_ADV_PAUSE, &ld_pause); 4346 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, 4347 MDIO_AN_REG_LP_AUTO_NEG, &lp_pause); 4348 } else { 4349 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, 4350 MDIO_AN_REG_CL37_FC_LD, &ld_pause); 4351 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, 4352 MDIO_AN_REG_CL37_FC_LP, &lp_pause); 4353 ld_pause = ((ld_pause & 4354 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) 4355 << 3); 4356 lp_pause = ((lp_pause & 4357 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) 4358 << 3); 4359 } 4360 } else { 4361 elink_cl45_read(sc, phy, 4362 MDIO_AN_DEVAD, 4363 MDIO_AN_REG_ADV_PAUSE, &ld_pause); 4364 elink_cl45_read(sc, phy, 4365 MDIO_AN_DEVAD, 4366 MDIO_AN_REG_LP_AUTO_NEG, &lp_pause); 4367 } 4368 pause_result = (ld_pause & 4369 MDIO_AN_REG_ADV_PAUSE_MASK) >> 8; 4370 pause_result |= (lp_pause & 4371 MDIO_AN_REG_ADV_PAUSE_MASK) >> 10; 4372 ELINK_DEBUG_P1(sc, "Ext PHY pause result 0x%x\n", pause_result); 4373 elink_pause_resolve(vars, pause_result); 4374 4375 } 4376 4377 static uint8_t elink_ext_phy_resolve_fc(struct elink_phy *phy, 4378 struct elink_params *params, 4379 struct elink_vars *vars) 4380 { 4381 uint8_t ret = 0; 4382 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE; 4383 if (phy->req_flow_ctrl != ELINK_FLOW_CTRL_AUTO) { 4384 /* Update the advertised flow-controled of LD/LP in AN */ 4385 if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG) 4386 elink_ext_phy_update_adv_fc(phy, params, vars); 4387 /* But set the flow-control result as the requested one */ 4388 vars->flow_ctrl = phy->req_flow_ctrl; 4389 } else if (phy->req_line_speed != ELINK_SPEED_AUTO_NEG) 4390 vars->flow_ctrl = params->req_fc_auto_adv; 4391 else if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) { 4392 ret = 1; 4393 elink_ext_phy_update_adv_fc(phy, params, vars); 4394 } 4395 return ret; 4396 } 4397 /******************************************************************/ 4398 /* Warpcore section */ 4399 /******************************************************************/ 4400 /* The init_internal_warpcore should mirror the xgxs, 4401 * i.e. reset the lane (if needed), set aer for the 4402 * init configuration, and set/clear SGMII flag. Internal 4403 * phy init is done purely in phy_init stage. 4404 */ 4405 #define WC_TX_DRIVER(post2, idriver, ipre) \ 4406 ((post2 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) | \ 4407 (idriver << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) | \ 4408 (ipre << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET)) 4409 4410 #define WC_TX_FIR(post, main, pre) \ 4411 ((post << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) | \ 4412 (main << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) | \ 4413 (pre << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET)) 4414 4415 static void elink_warpcore_enable_AN_KR2(struct elink_phy *phy, 4416 struct elink_params *params, 4417 struct elink_vars *vars) 4418 { 4419 struct bxe_softc *sc = params->sc; 4420 uint16_t i; 4421 static struct elink_reg_set reg_set[] = { 4422 /* Step 1 - Program the TX/RX alignment markers */ 4423 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL5, 0xa157}, 4424 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL7, 0xcbe2}, 4425 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL6, 0x7537}, 4426 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL9, 0xa157}, 4427 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL11, 0xcbe2}, 4428 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL10, 0x7537}, 4429 /* Step 2 - Configure the NP registers */ 4430 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_USERB0_CTRL, 0x000a}, 4431 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL1, 0x6400}, 4432 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL3, 0x0620}, 4433 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CODE_FIELD, 0x0157}, 4434 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI1, 0x6464}, 4435 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI2, 0x3150}, 4436 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI3, 0x3150}, 4437 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_BAM_CODE, 0x0157}, 4438 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_UD_CODE, 0x0620} 4439 }; 4440 ELINK_DEBUG_P0(sc, "Enabling 20G-KR2\n"); 4441 4442 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, 4443 MDIO_WC_REG_CL49_USERB0_CTRL, (3<<6)); 4444 4445 for (i = 0; i < ARRAY_SIZE(reg_set); i++) 4446 elink_cl45_write(sc, phy, reg_set[i].devad, reg_set[i].reg, 4447 reg_set[i].val); 4448 4449 /* Start KR2 work-around timer which handles BCM8073 link-parner */ 4450 vars->link_attr_sync |= LINK_ATTR_SYNC_KR2_ENABLE; 4451 elink_update_link_attr(params, vars->link_attr_sync); 4452 } 4453 4454 static void elink_disable_kr2(struct elink_params *params, 4455 struct elink_vars *vars, 4456 struct elink_phy *phy) 4457 { 4458 struct bxe_softc *sc = params->sc; 4459 int i; 4460 static struct elink_reg_set reg_set[] = { 4461 /* Step 1 - Program the TX/RX alignment markers */ 4462 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL5, 0x7690}, 4463 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL7, 0xe647}, 4464 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL6, 0xc4f0}, 4465 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL9, 0x7690}, 4466 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL11, 0xe647}, 4467 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL10, 0xc4f0}, 4468 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_USERB0_CTRL, 0x000c}, 4469 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL1, 0x6000}, 4470 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL3, 0x0000}, 4471 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CODE_FIELD, 0x0002}, 4472 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI1, 0x0000}, 4473 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI2, 0x0af7}, 4474 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI3, 0x0af7}, 4475 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_BAM_CODE, 0x0002}, 4476 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_UD_CODE, 0x0000} 4477 }; 4478 ELINK_DEBUG_P0(sc, "Disabling 20G-KR2\n"); 4479 4480 for (i = 0; i < ARRAY_SIZE(reg_set); i++) 4481 elink_cl45_write(sc, phy, reg_set[i].devad, reg_set[i].reg, 4482 reg_set[i].val); 4483 vars->link_attr_sync &= ~LINK_ATTR_SYNC_KR2_ENABLE; 4484 elink_update_link_attr(params, vars->link_attr_sync); 4485 4486 vars->check_kr2_recovery_cnt = ELINK_CHECK_KR2_RECOVERY_CNT; 4487 } 4488 4489 static void elink_warpcore_set_lpi_passthrough(struct elink_phy *phy, 4490 struct elink_params *params) 4491 { 4492 struct bxe_softc *sc = params->sc; 4493 4494 ELINK_DEBUG_P0(sc, "Configure WC for LPI pass through\n"); 4495 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, 4496 MDIO_WC_REG_EEE_COMBO_CONTROL0, 0x7c); 4497 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, 4498 MDIO_WC_REG_DIGITAL4_MISC5, 0xc000); 4499 } 4500 4501 static void elink_warpcore_restart_AN_KR(struct elink_phy *phy, 4502 struct elink_params *params) 4503 { 4504 /* Restart autoneg on the leading lane only */ 4505 struct bxe_softc *sc = params->sc; 4506 uint16_t lane = elink_get_warpcore_lane(phy, params); 4507 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK, 4508 MDIO_AER_BLOCK_AER_REG, lane); 4509 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, 4510 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200); 4511 4512 /* Restore AER */ 4513 elink_set_aer_mmd(params, phy); 4514 } 4515 4516 static void elink_warpcore_enable_AN_KR(struct elink_phy *phy, 4517 struct elink_params *params, 4518 struct elink_vars *vars) { 4519 uint16_t lane, i, cl72_ctrl, an_adv = 0; 4520 struct bxe_softc *sc = params->sc; 4521 static struct elink_reg_set reg_set[] = { 4522 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7}, 4523 {MDIO_PMA_DEVAD, MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0x0}, 4524 {MDIO_WC_DEVAD, MDIO_WC_REG_RX66_CONTROL, 0x7415}, 4525 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x6190}, 4526 /* Disable Autoneg: re-enable it after adv is done. */ 4527 {MDIO_AN_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0}, 4528 {MDIO_PMA_DEVAD, MDIO_WC_REG_PMD_KR_CONTROL, 0x2}, 4529 {MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP, 0}, 4530 }; 4531 ELINK_DEBUG_P0(sc, "Enable Auto Negotiation for KR\n"); 4532 /* Set to default registers that may be overriden by 10G force */ 4533 for (i = 0; i < ARRAY_SIZE(reg_set); i++) 4534 elink_cl45_write(sc, phy, reg_set[i].devad, reg_set[i].reg, 4535 reg_set[i].val); 4536 4537 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, 4538 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, &cl72_ctrl); 4539 cl72_ctrl &= 0x08ff; 4540 cl72_ctrl |= 0x3800; 4541 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, 4542 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, cl72_ctrl); 4543 4544 /* Check adding advertisement for 1G KX */ 4545 if (((vars->line_speed == ELINK_SPEED_AUTO_NEG) && 4546 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) || 4547 (vars->line_speed == ELINK_SPEED_1000)) { 4548 uint16_t addr = MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2; 4549 an_adv |= (1<<5); 4550 4551 /* Enable CL37 1G Parallel Detect */ 4552 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, addr, 0x1); 4553 ELINK_DEBUG_P0(sc, "Advertize 1G\n"); 4554 } 4555 if (((vars->line_speed == ELINK_SPEED_AUTO_NEG) && 4556 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) || 4557 (vars->line_speed == ELINK_SPEED_10000)) { 4558 /* Check adding advertisement for 10G KR */ 4559 an_adv |= (1<<7); 4560 /* Enable 10G Parallel Detect */ 4561 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK, 4562 MDIO_AER_BLOCK_AER_REG, 0); 4563 4564 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, 4565 MDIO_WC_REG_PAR_DET_10G_CTRL, 1); 4566 elink_set_aer_mmd(params, phy); 4567 ELINK_DEBUG_P0(sc, "Advertize 10G\n"); 4568 } 4569 4570 /* Set Transmit PMD settings */ 4571 lane = elink_get_warpcore_lane(phy, params); 4572 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, 4573 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, 4574 WC_TX_DRIVER(0x02, 0x06, 0x09)); 4575 /* Configure the next lane if dual mode */ 4576 if (phy->flags & ELINK_FLAGS_WC_DUAL_MODE) 4577 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, 4578 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*(lane+1), 4579 WC_TX_DRIVER(0x02, 0x06, 0x09)); 4580 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, 4581 MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL, 4582 0x03f0); 4583 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, 4584 MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL, 4585 0x03f0); 4586 4587 /* Advertised speeds */ 4588 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, 4589 MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, an_adv); 4590 4591 /* Advertised and set FEC (Forward Error Correction) */ 4592 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, 4593 MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT2, 4594 (MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_ABILITY | 4595 MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ)); 4596 4597 /* Enable CL37 BAM */ 4598 if (REG_RD(sc, params->shmem_base + 4599 offsetof(struct shmem_region, dev_info. 4600 port_hw_config[params->port].default_cfg)) & 4601 PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) { 4602 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, 4603 MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL, 4604 1); 4605 ELINK_DEBUG_P0(sc, "Enable CL37 BAM on KR\n"); 4606 } 4607 4608 /* Advertise pause */ 4609 elink_ext_phy_set_pause(params, phy, vars); 4610 vars->rx_tx_asic_rst = MAX_KR_LINK_RETRY; 4611 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, 4612 MDIO_WC_REG_DIGITAL5_MISC7, 0x100); 4613 4614 /* Over 1G - AN local device user page 1 */ 4615 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, 4616 MDIO_WC_REG_DIGITAL3_UP1, 0x1f); 4617 4618 if (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) && 4619 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) || 4620 (phy->req_line_speed == ELINK_SPEED_20000)) { 4621 4622 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK, 4623 MDIO_AER_BLOCK_AER_REG, lane); 4624 4625 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, 4626 MDIO_WC_REG_RX1_PCI_CTRL + (0x10*lane), 4627 (1<<11)); 4628 4629 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, 4630 MDIO_WC_REG_XGXS_X2_CONTROL3, 0x7); 4631 elink_set_aer_mmd(params, phy); 4632 4633 elink_warpcore_enable_AN_KR2(phy, params, vars); 4634 } else { 4635 elink_disable_kr2(params, vars, phy); 4636 } 4637 4638 /* Enable Autoneg: only on the main lane */ 4639 elink_warpcore_restart_AN_KR(phy, params); 4640 } 4641 4642 static void elink_warpcore_set_10G_KR(struct elink_phy *phy, 4643 struct elink_params *params, 4644 struct elink_vars *vars) 4645 { 4646 struct bxe_softc *sc = params->sc; 4647 uint16_t val16, i, lane; 4648 static struct elink_reg_set reg_set[] = { 4649 /* Disable Autoneg */ 4650 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7}, 4651 {MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, 4652 0x3f00}, 4653 {MDIO_AN_DEVAD, MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, 0}, 4654 {MDIO_AN_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0}, 4655 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL3_UP1, 0x1}, 4656 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL5_MISC7, 0xa}, 4657 /* Leave cl72 training enable, needed for KR */ 4658 {MDIO_PMA_DEVAD, MDIO_WC_REG_PMD_KR_CONTROL, 0x2} 4659 }; 4660 4661 for (i = 0; i < ARRAY_SIZE(reg_set); i++) 4662 elink_cl45_write(sc, phy, reg_set[i].devad, reg_set[i].reg, 4663 reg_set[i].val); 4664 4665 lane = elink_get_warpcore_lane(phy, params); 4666 /* Global registers */ 4667 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK, 4668 MDIO_AER_BLOCK_AER_REG, 0); 4669 /* Disable CL36 PCS Tx */ 4670 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, 4671 MDIO_WC_REG_XGXSBLK1_LANECTRL0, &val16); 4672 val16 &= ~(0x0011 << lane); 4673 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, 4674 MDIO_WC_REG_XGXSBLK1_LANECTRL0, val16); 4675 4676 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, 4677 MDIO_WC_REG_XGXSBLK1_LANECTRL1, &val16); 4678 val16 |= (0x0303 << (lane << 1)); 4679 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, 4680 MDIO_WC_REG_XGXSBLK1_LANECTRL1, val16); 4681 /* Restore AER */ 4682 elink_set_aer_mmd(params, phy); 4683 /* Set speed via PMA/PMD register */ 4684 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, 4685 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040); 4686 4687 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, 4688 MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0xB); 4689 4690 /* Enable encoded forced speed */ 4691 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, 4692 MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x30); 4693 4694 /* Turn TX scramble payload only the 64/66 scrambler */ 4695 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, 4696 MDIO_WC_REG_TX66_CONTROL, 0x9); 4697 4698 /* Turn RX scramble payload only the 64/66 scrambler */ 4699 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, 4700 MDIO_WC_REG_RX66_CONTROL, 0xF9); 4701 4702 /* Set and clear loopback to cause a reset to 64/66 decoder */ 4703 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, 4704 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x4000); 4705 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, 4706 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0); 4707 4708 } 4709 4710 static void elink_warpcore_set_10G_XFI(struct elink_phy *phy, 4711 struct elink_params *params, 4712 uint8_t is_xfi) 4713 { 4714 struct bxe_softc *sc = params->sc; 4715 uint16_t misc1_val, tap_val, tx_driver_val, lane, val; 4716 uint32_t cfg_tap_val, tx_drv_brdct, tx_equal; 4717 4718 /* Hold rxSeqStart */ 4719 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, 4720 MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, 0x8000); 4721 4722 /* Hold tx_fifo_reset */ 4723 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, 4724 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, 0x1); 4725 4726 /* Disable CL73 AN */ 4727 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0); 4728 4729 /* Disable 100FX Enable and Auto-Detect */ 4730 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD, 4731 MDIO_WC_REG_FX100_CTRL1, 0xFFFA); 4732 4733 /* Disable 100FX Idle detect */ 4734 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, 4735 MDIO_WC_REG_FX100_CTRL3, 0x0080); 4736 4737 /* Set Block address to Remote PHY & Clear forced_speed[5] */ 4738 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD, 4739 MDIO_WC_REG_DIGITAL4_MISC3, 0xFF7F); 4740 4741 /* Turn off auto-detect & fiber mode */ 4742 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD, 4743 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 4744 0xFFEE); 4745 4746 /* Set filter_force_link, disable_false_link and parallel_detect */ 4747 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, 4748 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &val); 4749 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, 4750 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 4751 ((val | 0x0006) & 0xFFFE)); 4752 4753 /* Set XFI / SFI */ 4754 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, 4755 MDIO_WC_REG_SERDESDIGITAL_MISC1, &misc1_val); 4756 4757 misc1_val &= ~(0x1f); 4758 4759 if (is_xfi) { 4760 misc1_val |= 0x5; 4761 tap_val = WC_TX_FIR(0x08, 0x37, 0x00); 4762 tx_driver_val = WC_TX_DRIVER(0x00, 0x02, 0x03); 4763 } else { 4764 cfg_tap_val = REG_RD(sc, params->shmem_base + 4765 offsetof(struct shmem_region, dev_info. 4766 port_hw_config[params->port]. 4767 sfi_tap_values)); 4768 4769 tx_equal = cfg_tap_val & PORT_HW_CFG_TX_EQUALIZATION_MASK; 4770 4771 tx_drv_brdct = (cfg_tap_val & 4772 PORT_HW_CFG_TX_DRV_BROADCAST_MASK) >> 4773 PORT_HW_CFG_TX_DRV_BROADCAST_SHIFT; 4774 4775 misc1_val |= 0x9; 4776 4777 /* TAP values are controlled by nvram, if value there isn't 0 */ 4778 if (tx_equal) 4779 tap_val = (uint16_t)tx_equal; 4780 else 4781 tap_val = WC_TX_FIR(0x0f, 0x2b, 0x02); 4782 4783 if (tx_drv_brdct) 4784 tx_driver_val = WC_TX_DRIVER(0x03, (uint16_t)tx_drv_brdct, 4785 0x06); 4786 else 4787 tx_driver_val = WC_TX_DRIVER(0x03, 0x02, 0x06); 4788 } 4789 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, 4790 MDIO_WC_REG_SERDESDIGITAL_MISC1, misc1_val); 4791 4792 /* Set Transmit PMD settings */ 4793 lane = elink_get_warpcore_lane(phy, params); 4794 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, 4795 MDIO_WC_REG_TX_FIR_TAP, 4796 tap_val | MDIO_WC_REG_TX_FIR_TAP_ENABLE); 4797 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, 4798 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, 4799 tx_driver_val); 4800 4801 /* Enable fiber mode, enable and invert sig_det */ 4802 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, 4803 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 0xd); 4804 4805 /* Set Block address to Remote PHY & Set forced_speed[5], 40bit mode */ 4806 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, 4807 MDIO_WC_REG_DIGITAL4_MISC3, 0x8080); 4808 4809 elink_warpcore_set_lpi_passthrough(phy, params); 4810 4811 /* 10G XFI Full Duplex */ 4812 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, 4813 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x100); 4814 4815 /* Release tx_fifo_reset */ 4816 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD, 4817 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, 4818 0xFFFE); 4819 /* Release rxSeqStart */ 4820 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD, 4821 MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, 0x7FFF); 4822 } 4823 4824 static void elink_warpcore_set_20G_force_KR2(struct elink_phy *phy, 4825 struct elink_params *params) 4826 { 4827 uint16_t val; 4828 struct bxe_softc *sc = params->sc; 4829 /* Set global registers, so set AER lane to 0 */ 4830 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK, 4831 MDIO_AER_BLOCK_AER_REG, 0); 4832 4833 /* Disable sequencer */ 4834 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD, 4835 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, ~(1<<13)); 4836 4837 elink_set_aer_mmd(params, phy); 4838 4839 elink_cl45_read_and_write(sc, phy, MDIO_PMA_DEVAD, 4840 MDIO_WC_REG_PMD_KR_CONTROL, ~(1<<1)); 4841 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, 4842 MDIO_AN_REG_CTRL, 0); 4843 /* Turn off CL73 */ 4844 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, 4845 MDIO_WC_REG_CL73_USERB0_CTRL, &val); 4846 val &= ~(1<<5); 4847 val |= (1<<6); 4848 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, 4849 MDIO_WC_REG_CL73_USERB0_CTRL, val); 4850 4851 /* Set 20G KR2 force speed */ 4852 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, 4853 MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x1f); 4854 4855 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, 4856 MDIO_WC_REG_DIGITAL4_MISC3, (1<<7)); 4857 4858 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, 4859 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, &val); 4860 val &= ~(3<<14); 4861 val |= (1<<15); 4862 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, 4863 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, val); 4864 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, 4865 MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP, 0x835A); 4866 4867 /* Enable sequencer (over lane 0) */ 4868 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK, 4869 MDIO_AER_BLOCK_AER_REG, 0); 4870 4871 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, 4872 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, (1<<13)); 4873 4874 elink_set_aer_mmd(params, phy); 4875 } 4876 4877 static void elink_warpcore_set_20G_DXGXS(struct bxe_softc *sc, 4878 struct elink_phy *phy, 4879 uint16_t lane) 4880 { 4881 /* Rx0 anaRxControl1G */ 4882 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, 4883 MDIO_WC_REG_RX0_ANARXCONTROL1G, 0x90); 4884 4885 /* Rx2 anaRxControl1G */ 4886 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, 4887 MDIO_WC_REG_RX2_ANARXCONTROL1G, 0x90); 4888 4889 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, 4890 MDIO_WC_REG_RX66_SCW0, 0xE070); 4891 4892 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, 4893 MDIO_WC_REG_RX66_SCW1, 0xC0D0); 4894 4895 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, 4896 MDIO_WC_REG_RX66_SCW2, 0xA0B0); 4897 4898 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, 4899 MDIO_WC_REG_RX66_SCW3, 0x8090); 4900 4901 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, 4902 MDIO_WC_REG_RX66_SCW0_MASK, 0xF0F0); 4903 4904 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, 4905 MDIO_WC_REG_RX66_SCW1_MASK, 0xF0F0); 4906 4907 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, 4908 MDIO_WC_REG_RX66_SCW2_MASK, 0xF0F0); 4909 4910 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, 4911 MDIO_WC_REG_RX66_SCW3_MASK, 0xF0F0); 4912 4913 /* Serdes Digital Misc1 */ 4914 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, 4915 MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6008); 4916 4917 /* Serdes Digital4 Misc3 */ 4918 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, 4919 MDIO_WC_REG_DIGITAL4_MISC3, 0x8088); 4920 4921 /* Set Transmit PMD settings */ 4922 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, 4923 MDIO_WC_REG_TX_FIR_TAP, 4924 (WC_TX_FIR(0x12, 0x2d, 0x00) | 4925 MDIO_WC_REG_TX_FIR_TAP_ENABLE)); 4926 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, 4927 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, 4928 WC_TX_DRIVER(0x02, 0x02, 0x02)); 4929 } 4930 4931 static void elink_warpcore_set_sgmii_speed(struct elink_phy *phy, 4932 struct elink_params *params, 4933 uint8_t fiber_mode, 4934 uint8_t always_autoneg) 4935 { 4936 struct bxe_softc *sc = params->sc; 4937 uint16_t val16, digctrl_kx1, digctrl_kx2; 4938 4939 /* Clear XFI clock comp in non-10G single lane mode. */ 4940 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD, 4941 MDIO_WC_REG_RX66_CONTROL, ~(3<<13)); 4942 4943 elink_warpcore_set_lpi_passthrough(phy, params); 4944 4945 if (always_autoneg || phy->req_line_speed == ELINK_SPEED_AUTO_NEG) { 4946 /* SGMII Autoneg */ 4947 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, 4948 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 4949 0x1000); 4950 ELINK_DEBUG_P0(sc, "set SGMII AUTONEG\n"); 4951 } else { 4952 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, 4953 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16); 4954 val16 &= 0xcebf; 4955 switch (phy->req_line_speed) { 4956 case ELINK_SPEED_10: 4957 break; 4958 case ELINK_SPEED_100: 4959 val16 |= 0x2000; 4960 break; 4961 case ELINK_SPEED_1000: 4962 val16 |= 0x0040; 4963 break; 4964 default: 4965 ELINK_DEBUG_P1(sc, 4966 "Speed not supported: 0x%x\n", phy->req_line_speed); 4967 return; 4968 } 4969 4970 if (phy->req_duplex == DUPLEX_FULL) 4971 val16 |= 0x0100; 4972 4973 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, 4974 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16); 4975 4976 ELINK_DEBUG_P1(sc, "set SGMII force speed %d\n", 4977 phy->req_line_speed); 4978 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, 4979 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16); 4980 ELINK_DEBUG_P1(sc, " (readback) %x\n", val16); 4981 } 4982 4983 /* SGMII Slave mode and disable signal detect */ 4984 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, 4985 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &digctrl_kx1); 4986 if (fiber_mode) 4987 digctrl_kx1 = 1; 4988 else 4989 digctrl_kx1 &= 0xff4a; 4990 4991 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, 4992 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 4993 digctrl_kx1); 4994 4995 /* Turn off parallel detect */ 4996 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, 4997 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &digctrl_kx2); 4998 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, 4999 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 5000 (digctrl_kx2 & ~(1<<2))); 5001 5002 /* Re-enable parallel detect */ 5003 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, 5004 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 5005 (digctrl_kx2 | (1<<2))); 5006 5007 /* Enable autodet */ 5008 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, 5009 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 5010 (digctrl_kx1 | 0x10)); 5011 } 5012 5013 5014 static void elink_warpcore_reset_lane(struct bxe_softc *sc, 5015 struct elink_phy *phy, 5016 uint8_t reset) 5017 { 5018 uint16_t val; 5019 /* Take lane out of reset after configuration is finished */ 5020 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, 5021 MDIO_WC_REG_DIGITAL5_MISC6, &val); 5022 if (reset) 5023 val |= 0xC000; 5024 else 5025 val &= 0x3FFF; 5026 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, 5027 MDIO_WC_REG_DIGITAL5_MISC6, val); 5028 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, 5029 MDIO_WC_REG_DIGITAL5_MISC6, &val); 5030 } 5031 5032 /* Clear SFI/XFI link settings registers */ 5033 static void elink_warpcore_clear_regs(struct elink_phy *phy, 5034 struct elink_params *params, 5035 uint16_t lane) 5036 { 5037 struct bxe_softc *sc = params->sc; 5038 uint16_t i; 5039 static struct elink_reg_set wc_regs[] = { 5040 {MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0}, 5041 {MDIO_WC_DEVAD, MDIO_WC_REG_FX100_CTRL1, 0x014a}, 5042 {MDIO_WC_DEVAD, MDIO_WC_REG_FX100_CTRL3, 0x0800}, 5043 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL4_MISC3, 0x8008}, 5044 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 5045 0x0195}, 5046 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 5047 0x0007}, 5048 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, 5049 0x0002}, 5050 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6000}, 5051 {MDIO_WC_DEVAD, MDIO_WC_REG_TX_FIR_TAP, 0x0000}, 5052 {MDIO_WC_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040}, 5053 {MDIO_WC_DEVAD, MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0x0140} 5054 }; 5055 /* Set XFI clock comp as default. */ 5056 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, 5057 MDIO_WC_REG_RX66_CONTROL, (3<<13)); 5058 5059 for (i = 0; i < ARRAY_SIZE(wc_regs); i++) 5060 elink_cl45_write(sc, phy, wc_regs[i].devad, wc_regs[i].reg, 5061 wc_regs[i].val); 5062 5063 lane = elink_get_warpcore_lane(phy, params); 5064 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, 5065 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, 0x0990); 5066 5067 } 5068 5069 static elink_status_t elink_get_mod_abs_int_cfg(struct bxe_softc *sc, 5070 uint32_t chip_id, 5071 uint32_t shmem_base, uint8_t port, 5072 uint8_t *gpio_num, uint8_t *gpio_port) 5073 { 5074 uint32_t cfg_pin; 5075 *gpio_num = 0; 5076 *gpio_port = 0; 5077 if (CHIP_IS_E3(sc)) { 5078 cfg_pin = (REG_RD(sc, shmem_base + 5079 offsetof(struct shmem_region, 5080 dev_info.port_hw_config[port].e3_sfp_ctrl)) & 5081 PORT_HW_CFG_E3_MOD_ABS_MASK) >> 5082 PORT_HW_CFG_E3_MOD_ABS_SHIFT; 5083 5084 /* Should not happen. This function called upon interrupt 5085 * triggered by GPIO ( since EPIO can only generate interrupts 5086 * to MCP). 5087 * So if this function was called and none of the GPIOs was set, 5088 * it means the shit hit the fan. 5089 */ 5090 if ((cfg_pin < PIN_CFG_GPIO0_P0) || 5091 (cfg_pin > PIN_CFG_GPIO3_P1)) { 5092 ELINK_DEBUG_P1(sc, 5093 "No cfg pin %x for module detect indication\n", 5094 cfg_pin); 5095 return ELINK_STATUS_ERROR; 5096 } 5097 5098 *gpio_num = (cfg_pin - PIN_CFG_GPIO0_P0) & 0x3; 5099 *gpio_port = (cfg_pin - PIN_CFG_GPIO0_P0) >> 2; 5100 } else { 5101 *gpio_num = MISC_REGISTERS_GPIO_3; 5102 *gpio_port = port; 5103 } 5104 5105 return ELINK_STATUS_OK; 5106 } 5107 5108 static int elink_is_sfp_module_plugged(struct elink_phy *phy, 5109 struct elink_params *params) 5110 { 5111 struct bxe_softc *sc = params->sc; 5112 uint8_t gpio_num, gpio_port; 5113 uint32_t gpio_val; 5114 if (elink_get_mod_abs_int_cfg(sc, params->chip_id, 5115 params->shmem_base, params->port, 5116 &gpio_num, &gpio_port) != ELINK_STATUS_OK) 5117 return 0; 5118 gpio_val = elink_cb_gpio_read(sc, gpio_num, gpio_port); 5119 5120 /* Call the handling function in case module is detected */ 5121 if (gpio_val == 0) 5122 return 1; 5123 else 5124 return 0; 5125 } 5126 static int elink_warpcore_get_sigdet(struct elink_phy *phy, 5127 struct elink_params *params) 5128 { 5129 uint16_t gp2_status_reg0, lane; 5130 struct bxe_softc *sc = params->sc; 5131 5132 lane = elink_get_warpcore_lane(phy, params); 5133 5134 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_0, 5135 &gp2_status_reg0); 5136 5137 return (gp2_status_reg0 >> (8+lane)) & 0x1; 5138 } 5139 5140 static void elink_warpcore_config_runtime(struct elink_phy *phy, 5141 struct elink_params *params, 5142 struct elink_vars *vars) 5143 { 5144 struct bxe_softc *sc = params->sc; 5145 uint32_t serdes_net_if; 5146 uint16_t gp_status1 = 0, lnkup = 0, lnkup_kr = 0; 5147 5148 vars->turn_to_run_wc_rt = vars->turn_to_run_wc_rt ? 0 : 1; 5149 5150 if (!vars->turn_to_run_wc_rt) 5151 return; 5152 5153 if (vars->rx_tx_asic_rst) { 5154 uint16_t lane = elink_get_warpcore_lane(phy, params); 5155 serdes_net_if = (REG_RD(sc, params->shmem_base + 5156 offsetof(struct shmem_region, dev_info. 5157 port_hw_config[params->port].default_cfg)) & 5158 PORT_HW_CFG_NET_SERDES_IF_MASK); 5159 5160 switch (serdes_net_if) { 5161 case PORT_HW_CFG_NET_SERDES_IF_KR: 5162 /* Do we get link yet? */ 5163 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, 0x81d1, 5164 &gp_status1); 5165 lnkup = (gp_status1 >> (8+lane)) & 0x1;/* 1G */ 5166 /*10G KR*/ 5167 lnkup_kr = (gp_status1 >> (12+lane)) & 0x1; 5168 5169 if (lnkup_kr || lnkup) { 5170 vars->rx_tx_asic_rst = 0; 5171 } else { 5172 /* Reset the lane to see if link comes up.*/ 5173 elink_warpcore_reset_lane(sc, phy, 1); 5174 elink_warpcore_reset_lane(sc, phy, 0); 5175 5176 /* Restart Autoneg */ 5177 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, 5178 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200); 5179 5180 vars->rx_tx_asic_rst--; 5181 ELINK_DEBUG_P1(sc, "0x%x retry left\n", 5182 vars->rx_tx_asic_rst); 5183 } 5184 break; 5185 5186 default: 5187 break; 5188 } 5189 5190 } /*params->rx_tx_asic_rst*/ 5191 5192 } 5193 static void elink_warpcore_config_sfi(struct elink_phy *phy, 5194 struct elink_params *params) 5195 { 5196 uint16_t lane = elink_get_warpcore_lane(phy, params); 5197 struct bxe_softc *sc = params->sc; 5198 elink_warpcore_clear_regs(phy, params, lane); 5199 if ((params->req_line_speed[ELINK_LINK_CONFIG_IDX(ELINK_INT_PHY)] == 5200 ELINK_SPEED_10000) && 5201 (phy->media_type != ELINK_ETH_PHY_SFP_1G_FIBER)) { 5202 ELINK_DEBUG_P0(sc, "Setting 10G SFI\n"); 5203 elink_warpcore_set_10G_XFI(phy, params, 0); 5204 } else { 5205 ELINK_DEBUG_P0(sc, "Setting 1G Fiber\n"); 5206 elink_warpcore_set_sgmii_speed(phy, params, 1, 0); 5207 } 5208 } 5209 5210 static void elink_sfp_e3_set_transmitter(struct elink_params *params, 5211 struct elink_phy *phy, 5212 uint8_t tx_en) 5213 { 5214 struct bxe_softc *sc = params->sc; 5215 uint32_t cfg_pin; 5216 uint8_t port = params->port; 5217 5218 cfg_pin = REG_RD(sc, params->shmem_base + 5219 offsetof(struct shmem_region, 5220 dev_info.port_hw_config[port].e3_sfp_ctrl)) & 5221 PORT_HW_CFG_E3_TX_LASER_MASK; 5222 /* Set the !tx_en since this pin is DISABLE_TX_LASER */ 5223 ELINK_DEBUG_P1(sc, "Setting WC TX to %d\n", tx_en); 5224 5225 /* For 20G, the expected pin to be used is 3 pins after the current */ 5226 elink_set_cfg_pin(sc, cfg_pin, tx_en ^ 1); 5227 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G) 5228 elink_set_cfg_pin(sc, cfg_pin + 3, tx_en ^ 1); 5229 } 5230 5231 static void elink_warpcore_config_init(struct elink_phy *phy, 5232 struct elink_params *params, 5233 struct elink_vars *vars) 5234 { 5235 struct bxe_softc *sc = params->sc; 5236 uint32_t serdes_net_if; 5237 uint8_t fiber_mode; 5238 uint16_t lane = elink_get_warpcore_lane(phy, params); 5239 serdes_net_if = (REG_RD(sc, params->shmem_base + 5240 offsetof(struct shmem_region, dev_info. 5241 port_hw_config[params->port].default_cfg)) & 5242 PORT_HW_CFG_NET_SERDES_IF_MASK); 5243 ELINK_DEBUG_P2(sc, "Begin Warpcore init, link_speed %d, " 5244 "serdes_net_if = 0x%x\n", 5245 vars->line_speed, serdes_net_if); 5246 elink_set_aer_mmd(params, phy); 5247 elink_warpcore_reset_lane(sc, phy, 1); 5248 vars->phy_flags |= PHY_XGXS_FLAG; 5249 if ((serdes_net_if == PORT_HW_CFG_NET_SERDES_IF_SGMII) || 5250 (phy->req_line_speed && 5251 ((phy->req_line_speed == ELINK_SPEED_100) || 5252 (phy->req_line_speed == ELINK_SPEED_10)))) { 5253 vars->phy_flags |= PHY_SGMII_FLAG; 5254 ELINK_DEBUG_P0(sc, "Setting SGMII mode\n"); 5255 elink_warpcore_clear_regs(phy, params, lane); 5256 elink_warpcore_set_sgmii_speed(phy, params, 0, 1); 5257 } else { 5258 switch (serdes_net_if) { 5259 case PORT_HW_CFG_NET_SERDES_IF_KR: 5260 /* Enable KR Auto Neg */ 5261 if (params->loopback_mode != ELINK_LOOPBACK_EXT) 5262 elink_warpcore_enable_AN_KR(phy, params, vars); 5263 else { 5264 ELINK_DEBUG_P0(sc, "Setting KR 10G-Force\n"); 5265 elink_warpcore_set_10G_KR(phy, params, vars); 5266 } 5267 break; 5268 5269 case PORT_HW_CFG_NET_SERDES_IF_XFI: 5270 elink_warpcore_clear_regs(phy, params, lane); 5271 if (vars->line_speed == ELINK_SPEED_10000) { 5272 ELINK_DEBUG_P0(sc, "Setting 10G XFI\n"); 5273 elink_warpcore_set_10G_XFI(phy, params, 1); 5274 } else { 5275 if (ELINK_SINGLE_MEDIA_DIRECT(params)) { 5276 ELINK_DEBUG_P0(sc, "1G Fiber\n"); 5277 fiber_mode = 1; 5278 } else { 5279 ELINK_DEBUG_P0(sc, "10/100/1G SGMII\n"); 5280 fiber_mode = 0; 5281 } 5282 elink_warpcore_set_sgmii_speed(phy, 5283 params, 5284 fiber_mode, 5285 0); 5286 } 5287 5288 break; 5289 5290 case PORT_HW_CFG_NET_SERDES_IF_SFI: 5291 /* Issue Module detection if module is plugged, or 5292 * enabled transmitter to avoid current leakage in case 5293 * no module is connected 5294 */ 5295 if ((params->loopback_mode == ELINK_LOOPBACK_NONE) || 5296 (params->loopback_mode == ELINK_LOOPBACK_EXT)) { 5297 if (elink_is_sfp_module_plugged(phy, params)) 5298 elink_sfp_module_detection(phy, params); 5299 else 5300 elink_sfp_e3_set_transmitter(params, 5301 phy, 1); 5302 } 5303 5304 elink_warpcore_config_sfi(phy, params); 5305 break; 5306 5307 case PORT_HW_CFG_NET_SERDES_IF_DXGXS: 5308 if (vars->line_speed != ELINK_SPEED_20000) { 5309 ELINK_DEBUG_P0(sc, "Speed not supported yet\n"); 5310 return; 5311 } 5312 ELINK_DEBUG_P0(sc, "Setting 20G DXGXS\n"); 5313 elink_warpcore_set_20G_DXGXS(sc, phy, lane); 5314 /* Issue Module detection */ 5315 5316 elink_sfp_module_detection(phy, params); 5317 break; 5318 case PORT_HW_CFG_NET_SERDES_IF_KR2: 5319 if (!params->loopback_mode) { 5320 elink_warpcore_enable_AN_KR(phy, params, vars); 5321 } else { 5322 ELINK_DEBUG_P0(sc, "Setting KR 20G-Force\n"); 5323 elink_warpcore_set_20G_force_KR2(phy, params); 5324 } 5325 break; 5326 default: 5327 ELINK_DEBUG_P1(sc, 5328 "Unsupported Serdes Net Interface 0x%x\n", 5329 serdes_net_if); 5330 return; 5331 } 5332 } 5333 5334 /* Take lane out of reset after configuration is finished */ 5335 elink_warpcore_reset_lane(sc, phy, 0); 5336 ELINK_DEBUG_P0(sc, "Exit config init\n"); 5337 } 5338 5339 static void elink_warpcore_link_reset(struct elink_phy *phy, 5340 struct elink_params *params) 5341 { 5342 struct bxe_softc *sc = params->sc; 5343 uint16_t val16, lane; 5344 elink_sfp_e3_set_transmitter(params, phy, 0); 5345 elink_set_mdio_emac_per_phy(sc, params); 5346 elink_set_aer_mmd(params, phy); 5347 /* Global register */ 5348 elink_warpcore_reset_lane(sc, phy, 1); 5349 5350 /* Clear loopback settings (if any) */ 5351 /* 10G & 20G */ 5352 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD, 5353 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0xBFFF); 5354 5355 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD, 5356 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0xfffe); 5357 5358 /* Update those 1-copy registers */ 5359 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK, 5360 MDIO_AER_BLOCK_AER_REG, 0); 5361 /* Enable 1G MDIO (1-copy) */ 5362 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD, 5363 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, 5364 ~0x10); 5365 5366 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD, 5367 MDIO_WC_REG_XGXSBLK1_LANECTRL2, 0xff00); 5368 lane = elink_get_warpcore_lane(phy, params); 5369 /* Disable CL36 PCS Tx */ 5370 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, 5371 MDIO_WC_REG_XGXSBLK1_LANECTRL0, &val16); 5372 val16 |= (0x11 << lane); 5373 if (phy->flags & ELINK_FLAGS_WC_DUAL_MODE) 5374 val16 |= (0x22 << lane); 5375 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, 5376 MDIO_WC_REG_XGXSBLK1_LANECTRL0, val16); 5377 5378 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, 5379 MDIO_WC_REG_XGXSBLK1_LANECTRL1, &val16); 5380 val16 &= ~(0x0303 << (lane << 1)); 5381 val16 |= (0x0101 << (lane << 1)); 5382 if (phy->flags & ELINK_FLAGS_WC_DUAL_MODE) { 5383 val16 &= ~(0x0c0c << (lane << 1)); 5384 val16 |= (0x0404 << (lane << 1)); 5385 } 5386 5387 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, 5388 MDIO_WC_REG_XGXSBLK1_LANECTRL1, val16); 5389 /* Restore AER */ 5390 elink_set_aer_mmd(params, phy); 5391 5392 } 5393 5394 static void elink_set_warpcore_loopback(struct elink_phy *phy, 5395 struct elink_params *params) 5396 { 5397 struct bxe_softc *sc = params->sc; 5398 uint16_t val16; 5399 uint32_t lane; 5400 ELINK_DEBUG_P2(sc, "Setting Warpcore loopback type %x, speed %d\n", 5401 params->loopback_mode, phy->req_line_speed); 5402 5403 if (phy->req_line_speed < ELINK_SPEED_10000 || 5404 phy->supported & ELINK_SUPPORTED_20000baseKR2_Full) { 5405 /* 10/100/1000/20G-KR2 */ 5406 5407 /* Update those 1-copy registers */ 5408 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK, 5409 MDIO_AER_BLOCK_AER_REG, 0); 5410 /* Enable 1G MDIO (1-copy) */ 5411 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, 5412 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, 5413 0x10); 5414 /* Set 1G loopback based on lane (1-copy) */ 5415 lane = elink_get_warpcore_lane(phy, params); 5416 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, 5417 MDIO_WC_REG_XGXSBLK1_LANECTRL2, &val16); 5418 val16 |= (1<<lane); 5419 if (phy->flags & ELINK_FLAGS_WC_DUAL_MODE) 5420 val16 |= (2<<lane); 5421 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, 5422 MDIO_WC_REG_XGXSBLK1_LANECTRL2, 5423 val16); 5424 5425 /* Switch back to 4-copy registers */ 5426 elink_set_aer_mmd(params, phy); 5427 } else { 5428 /* 10G / 20G-DXGXS */ 5429 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, 5430 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 5431 0x4000); 5432 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, 5433 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1); 5434 } 5435 } 5436 5437 5438 5439 static void elink_sync_link(struct elink_params *params, 5440 struct elink_vars *vars) 5441 { 5442 struct bxe_softc *sc = params->sc; 5443 uint8_t link_10g_plus; 5444 if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG) 5445 vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG; 5446 vars->link_up = (vars->link_status & LINK_STATUS_LINK_UP); 5447 if (vars->link_up) { 5448 ELINK_DEBUG_P0(sc, "phy link up\n"); 5449 5450 vars->phy_link_up = 1; 5451 vars->duplex = DUPLEX_FULL; 5452 switch (vars->link_status & 5453 LINK_STATUS_SPEED_AND_DUPLEX_MASK) { 5454 case ELINK_LINK_10THD: 5455 vars->duplex = DUPLEX_HALF; 5456 /* Fall thru */ 5457 case ELINK_LINK_10TFD: 5458 vars->line_speed = ELINK_SPEED_10; 5459 break; 5460 5461 case ELINK_LINK_100TXHD: 5462 vars->duplex = DUPLEX_HALF; 5463 /* Fall thru */ 5464 case ELINK_LINK_100T4: 5465 case ELINK_LINK_100TXFD: 5466 vars->line_speed = ELINK_SPEED_100; 5467 break; 5468 5469 case ELINK_LINK_1000THD: 5470 vars->duplex = DUPLEX_HALF; 5471 /* Fall thru */ 5472 case ELINK_LINK_1000TFD: 5473 vars->line_speed = ELINK_SPEED_1000; 5474 break; 5475 5476 case ELINK_LINK_2500THD: 5477 vars->duplex = DUPLEX_HALF; 5478 /* Fall thru */ 5479 case ELINK_LINK_2500TFD: 5480 vars->line_speed = ELINK_SPEED_2500; 5481 break; 5482 5483 case ELINK_LINK_10GTFD: 5484 vars->line_speed = ELINK_SPEED_10000; 5485 break; 5486 case ELINK_LINK_20GTFD: 5487 vars->line_speed = ELINK_SPEED_20000; 5488 break; 5489 default: 5490 break; 5491 } 5492 vars->flow_ctrl = 0; 5493 if (vars->link_status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED) 5494 vars->flow_ctrl |= ELINK_FLOW_CTRL_TX; 5495 5496 if (vars->link_status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED) 5497 vars->flow_ctrl |= ELINK_FLOW_CTRL_RX; 5498 5499 if (!vars->flow_ctrl) 5500 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE; 5501 5502 if (vars->line_speed && 5503 ((vars->line_speed == ELINK_SPEED_10) || 5504 (vars->line_speed == ELINK_SPEED_100))) { 5505 vars->phy_flags |= PHY_SGMII_FLAG; 5506 } else { 5507 vars->phy_flags &= ~PHY_SGMII_FLAG; 5508 } 5509 if (vars->line_speed && 5510 USES_WARPCORE(sc) && 5511 (vars->line_speed == ELINK_SPEED_1000)) 5512 vars->phy_flags |= PHY_SGMII_FLAG; 5513 /* Anything 10 and over uses the bmac */ 5514 link_10g_plus = (vars->line_speed >= ELINK_SPEED_10000); 5515 5516 if (link_10g_plus) { 5517 if (USES_WARPCORE(sc)) 5518 vars->mac_type = ELINK_MAC_TYPE_XMAC; 5519 else 5520 vars->mac_type = ELINK_MAC_TYPE_BMAC; 5521 } else { 5522 if (USES_WARPCORE(sc)) 5523 vars->mac_type = ELINK_MAC_TYPE_UMAC; 5524 else 5525 vars->mac_type = ELINK_MAC_TYPE_EMAC; 5526 } 5527 } else { /* Link down */ 5528 ELINK_DEBUG_P0(sc, "phy link down\n"); 5529 5530 vars->phy_link_up = 0; 5531 5532 vars->line_speed = 0; 5533 vars->duplex = DUPLEX_FULL; 5534 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE; 5535 5536 /* Indicate no mac active */ 5537 vars->mac_type = ELINK_MAC_TYPE_NONE; 5538 if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG) 5539 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG; 5540 if (vars->link_status & LINK_STATUS_SFP_TX_FAULT) 5541 vars->phy_flags |= PHY_SFP_TX_FAULT_FLAG; 5542 } 5543 } 5544 5545 void elink_link_status_update(struct elink_params *params, 5546 struct elink_vars *vars) 5547 { 5548 struct bxe_softc *sc = params->sc; 5549 uint8_t port = params->port; 5550 uint32_t sync_offset, media_types; 5551 /* Update PHY configuration */ 5552 set_phy_vars(params, vars); 5553 5554 vars->link_status = REG_RD(sc, params->shmem_base + 5555 offsetof(struct shmem_region, 5556 port_mb[port].link_status)); 5557 5558 /* Force link UP in non LOOPBACK_EXT loopback mode(s) */ 5559 if (params->loopback_mode != ELINK_LOOPBACK_NONE && 5560 params->loopback_mode != ELINK_LOOPBACK_EXT) 5561 vars->link_status |= LINK_STATUS_LINK_UP; 5562 5563 if (elink_eee_has_cap(params)) 5564 vars->eee_status = REG_RD(sc, params->shmem2_base + 5565 offsetof(struct shmem2_region, 5566 eee_status[params->port])); 5567 5568 vars->phy_flags = PHY_XGXS_FLAG; 5569 elink_sync_link(params, vars); 5570 /* Sync media type */ 5571 sync_offset = params->shmem_base + 5572 offsetof(struct shmem_region, 5573 dev_info.port_hw_config[port].media_type); 5574 media_types = REG_RD(sc, sync_offset); 5575 5576 params->phy[ELINK_INT_PHY].media_type = 5577 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) >> 5578 PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT; 5579 params->phy[ELINK_EXT_PHY1].media_type = 5580 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK) >> 5581 PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT; 5582 params->phy[ELINK_EXT_PHY2].media_type = 5583 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK) >> 5584 PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT; 5585 ELINK_DEBUG_P1(sc, "media_types = 0x%x\n", media_types); 5586 5587 /* Sync AEU offset */ 5588 sync_offset = params->shmem_base + 5589 offsetof(struct shmem_region, 5590 dev_info.port_hw_config[port].aeu_int_mask); 5591 5592 vars->aeu_int_mask = REG_RD(sc, sync_offset); 5593 5594 /* Sync PFC status */ 5595 if (vars->link_status & LINK_STATUS_PFC_ENABLED) 5596 params->feature_config_flags |= 5597 ELINK_FEATURE_CONFIG_PFC_ENABLED; 5598 else 5599 params->feature_config_flags &= 5600 ~ELINK_FEATURE_CONFIG_PFC_ENABLED; 5601 5602 if (SHMEM2_HAS(sc, link_attr_sync)) 5603 vars->link_attr_sync = SHMEM2_RD(sc, 5604 link_attr_sync[params->port]); 5605 5606 ELINK_DEBUG_P3(sc, "link_status 0x%x phy_link_up %x int_mask 0x%x\n", 5607 vars->link_status, vars->phy_link_up, vars->aeu_int_mask); 5608 ELINK_DEBUG_P3(sc, "line_speed %x duplex %x flow_ctrl 0x%x\n", 5609 vars->line_speed, vars->duplex, vars->flow_ctrl); 5610 } 5611 5612 static void elink_set_master_ln(struct elink_params *params, 5613 struct elink_phy *phy) 5614 { 5615 struct bxe_softc *sc = params->sc; 5616 uint16_t new_master_ln, ser_lane; 5617 ser_lane = ((params->lane_config & 5618 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >> 5619 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT); 5620 5621 /* Set the master_ln for AN */ 5622 CL22_RD_OVER_CL45(sc, phy, 5623 MDIO_REG_BANK_XGXS_BLOCK2, 5624 MDIO_XGXS_BLOCK2_TEST_MODE_LANE, 5625 &new_master_ln); 5626 5627 CL22_WR_OVER_CL45(sc, phy, 5628 MDIO_REG_BANK_XGXS_BLOCK2 , 5629 MDIO_XGXS_BLOCK2_TEST_MODE_LANE, 5630 (new_master_ln | ser_lane)); 5631 } 5632 5633 static elink_status_t elink_reset_unicore(struct elink_params *params, 5634 struct elink_phy *phy, 5635 uint8_t set_serdes) 5636 { 5637 struct bxe_softc *sc = params->sc; 5638 uint16_t mii_control; 5639 uint16_t i; 5640 CL22_RD_OVER_CL45(sc, phy, 5641 MDIO_REG_BANK_COMBO_IEEE0, 5642 MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control); 5643 5644 /* Reset the unicore */ 5645 CL22_WR_OVER_CL45(sc, phy, 5646 MDIO_REG_BANK_COMBO_IEEE0, 5647 MDIO_COMBO_IEEE0_MII_CONTROL, 5648 (mii_control | 5649 MDIO_COMBO_IEEO_MII_CONTROL_RESET)); 5650 if (set_serdes) 5651 elink_set_serdes_access(sc, params->port); 5652 5653 /* Wait for the reset to self clear */ 5654 for (i = 0; i < ELINK_MDIO_ACCESS_TIMEOUT; i++) { 5655 DELAY(5); 5656 5657 /* The reset erased the previous bank value */ 5658 CL22_RD_OVER_CL45(sc, phy, 5659 MDIO_REG_BANK_COMBO_IEEE0, 5660 MDIO_COMBO_IEEE0_MII_CONTROL, 5661 &mii_control); 5662 5663 if (!(mii_control & MDIO_COMBO_IEEO_MII_CONTROL_RESET)) { 5664 DELAY(5); 5665 return ELINK_STATUS_OK; 5666 } 5667 } 5668 5669 elink_cb_event_log(sc, ELINK_LOG_ID_PHY_UNINITIALIZED, params->port); // "Warning: PHY was not initialized," 5670 // " Port %d\n", 5671 5672 ELINK_DEBUG_P0(sc, "BUG! XGXS is still in reset!\n"); 5673 return ELINK_STATUS_ERROR; 5674 5675 } 5676 5677 static void elink_set_swap_lanes(struct elink_params *params, 5678 struct elink_phy *phy) 5679 { 5680 struct bxe_softc *sc = params->sc; 5681 /* Each two bits represents a lane number: 5682 * No swap is 0123 => 0x1b no need to enable the swap 5683 */ 5684 uint16_t rx_lane_swap, tx_lane_swap; 5685 5686 rx_lane_swap = ((params->lane_config & 5687 PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK) >> 5688 PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT); 5689 tx_lane_swap = ((params->lane_config & 5690 PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK) >> 5691 PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT); 5692 5693 if (rx_lane_swap != 0x1b) { 5694 CL22_WR_OVER_CL45(sc, phy, 5695 MDIO_REG_BANK_XGXS_BLOCK2, 5696 MDIO_XGXS_BLOCK2_RX_LN_SWAP, 5697 (rx_lane_swap | 5698 MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE | 5699 MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE)); 5700 } else { 5701 CL22_WR_OVER_CL45(sc, phy, 5702 MDIO_REG_BANK_XGXS_BLOCK2, 5703 MDIO_XGXS_BLOCK2_RX_LN_SWAP, 0); 5704 } 5705 5706 if (tx_lane_swap != 0x1b) { 5707 CL22_WR_OVER_CL45(sc, phy, 5708 MDIO_REG_BANK_XGXS_BLOCK2, 5709 MDIO_XGXS_BLOCK2_TX_LN_SWAP, 5710 (tx_lane_swap | 5711 MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE)); 5712 } else { 5713 CL22_WR_OVER_CL45(sc, phy, 5714 MDIO_REG_BANK_XGXS_BLOCK2, 5715 MDIO_XGXS_BLOCK2_TX_LN_SWAP, 0); 5716 } 5717 } 5718 5719 static void elink_set_parallel_detection(struct elink_phy *phy, 5720 struct elink_params *params) 5721 { 5722 struct bxe_softc *sc = params->sc; 5723 uint16_t control2; 5724 CL22_RD_OVER_CL45(sc, phy, 5725 MDIO_REG_BANK_SERDES_DIGITAL, 5726 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2, 5727 &control2); 5728 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) 5729 control2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN; 5730 else 5731 control2 &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN; 5732 ELINK_DEBUG_P2(sc, "phy->speed_cap_mask = 0x%x, control2 = 0x%x\n", 5733 phy->speed_cap_mask, control2); 5734 CL22_WR_OVER_CL45(sc, phy, 5735 MDIO_REG_BANK_SERDES_DIGITAL, 5736 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2, 5737 control2); 5738 5739 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) && 5740 (phy->speed_cap_mask & 5741 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) { 5742 ELINK_DEBUG_P0(sc, "XGXS\n"); 5743 5744 CL22_WR_OVER_CL45(sc, phy, 5745 MDIO_REG_BANK_10G_PARALLEL_DETECT, 5746 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK, 5747 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT); 5748 5749 CL22_RD_OVER_CL45(sc, phy, 5750 MDIO_REG_BANK_10G_PARALLEL_DETECT, 5751 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL, 5752 &control2); 5753 5754 5755 control2 |= 5756 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN; 5757 5758 CL22_WR_OVER_CL45(sc, phy, 5759 MDIO_REG_BANK_10G_PARALLEL_DETECT, 5760 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL, 5761 control2); 5762 5763 /* Disable parallel detection of HiG */ 5764 CL22_WR_OVER_CL45(sc, phy, 5765 MDIO_REG_BANK_XGXS_BLOCK2, 5766 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G, 5767 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS | 5768 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS); 5769 } 5770 } 5771 5772 static void elink_set_autoneg(struct elink_phy *phy, 5773 struct elink_params *params, 5774 struct elink_vars *vars, 5775 uint8_t enable_cl73) 5776 { 5777 struct bxe_softc *sc = params->sc; 5778 uint16_t reg_val; 5779 5780 /* CL37 Autoneg */ 5781 CL22_RD_OVER_CL45(sc, phy, 5782 MDIO_REG_BANK_COMBO_IEEE0, 5783 MDIO_COMBO_IEEE0_MII_CONTROL, ®_val); 5784 5785 /* CL37 Autoneg Enabled */ 5786 if (vars->line_speed == ELINK_SPEED_AUTO_NEG) 5787 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN; 5788 else /* CL37 Autoneg Disabled */ 5789 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN | 5790 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN); 5791 5792 CL22_WR_OVER_CL45(sc, phy, 5793 MDIO_REG_BANK_COMBO_IEEE0, 5794 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val); 5795 5796 /* Enable/Disable Autodetection */ 5797 5798 CL22_RD_OVER_CL45(sc, phy, 5799 MDIO_REG_BANK_SERDES_DIGITAL, 5800 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, ®_val); 5801 reg_val &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN | 5802 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT); 5803 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE; 5804 if (vars->line_speed == ELINK_SPEED_AUTO_NEG) 5805 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET; 5806 else 5807 reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET; 5808 5809 CL22_WR_OVER_CL45(sc, phy, 5810 MDIO_REG_BANK_SERDES_DIGITAL, 5811 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, reg_val); 5812 5813 /* Enable TetonII and BAM autoneg */ 5814 CL22_RD_OVER_CL45(sc, phy, 5815 MDIO_REG_BANK_BAM_NEXT_PAGE, 5816 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL, 5817 ®_val); 5818 if (vars->line_speed == ELINK_SPEED_AUTO_NEG) { 5819 /* Enable BAM aneg Mode and TetonII aneg Mode */ 5820 reg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE | 5821 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN); 5822 } else { 5823 /* TetonII and BAM Autoneg Disabled */ 5824 reg_val &= ~(MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE | 5825 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN); 5826 } 5827 CL22_WR_OVER_CL45(sc, phy, 5828 MDIO_REG_BANK_BAM_NEXT_PAGE, 5829 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL, 5830 reg_val); 5831 5832 if (enable_cl73) { 5833 /* Enable Cl73 FSM status bits */ 5834 CL22_WR_OVER_CL45(sc, phy, 5835 MDIO_REG_BANK_CL73_USERB0, 5836 MDIO_CL73_USERB0_CL73_UCTRL, 5837 0xe); 5838 5839 /* Enable BAM Station Manager*/ 5840 CL22_WR_OVER_CL45(sc, phy, 5841 MDIO_REG_BANK_CL73_USERB0, 5842 MDIO_CL73_USERB0_CL73_BAM_CTRL1, 5843 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN | 5844 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN | 5845 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN); 5846 5847 /* Advertise CL73 link speeds */ 5848 CL22_RD_OVER_CL45(sc, phy, 5849 MDIO_REG_BANK_CL73_IEEEB1, 5850 MDIO_CL73_IEEEB1_AN_ADV2, 5851 ®_val); 5852 if (phy->speed_cap_mask & 5853 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) 5854 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4; 5855 if (phy->speed_cap_mask & 5856 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) 5857 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX; 5858 5859 CL22_WR_OVER_CL45(sc, phy, 5860 MDIO_REG_BANK_CL73_IEEEB1, 5861 MDIO_CL73_IEEEB1_AN_ADV2, 5862 reg_val); 5863 5864 /* CL73 Autoneg Enabled */ 5865 reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN; 5866 5867 } else /* CL73 Autoneg Disabled */ 5868 reg_val = 0; 5869 5870 CL22_WR_OVER_CL45(sc, phy, 5871 MDIO_REG_BANK_CL73_IEEEB0, 5872 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, reg_val); 5873 } 5874 5875 /* Program SerDes, forced speed */ 5876 static void elink_program_serdes(struct elink_phy *phy, 5877 struct elink_params *params, 5878 struct elink_vars *vars) 5879 { 5880 struct bxe_softc *sc = params->sc; 5881 uint16_t reg_val; 5882 5883 /* Program duplex, disable autoneg and sgmii*/ 5884 CL22_RD_OVER_CL45(sc, phy, 5885 MDIO_REG_BANK_COMBO_IEEE0, 5886 MDIO_COMBO_IEEE0_MII_CONTROL, ®_val); 5887 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX | 5888 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN | 5889 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK); 5890 if (phy->req_duplex == DUPLEX_FULL) 5891 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX; 5892 CL22_WR_OVER_CL45(sc, phy, 5893 MDIO_REG_BANK_COMBO_IEEE0, 5894 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val); 5895 5896 /* Program speed 5897 * - needed only if the speed is greater than 1G (2.5G or 10G) 5898 */ 5899 CL22_RD_OVER_CL45(sc, phy, 5900 MDIO_REG_BANK_SERDES_DIGITAL, 5901 MDIO_SERDES_DIGITAL_MISC1, ®_val); 5902 /* Clearing the speed value before setting the right speed */ 5903 ELINK_DEBUG_P1(sc, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x\n", reg_val); 5904 5905 reg_val &= ~(MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK | 5906 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL); 5907 5908 if (!((vars->line_speed == ELINK_SPEED_1000) || 5909 (vars->line_speed == ELINK_SPEED_100) || 5910 (vars->line_speed == ELINK_SPEED_10))) { 5911 5912 reg_val |= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M | 5913 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL); 5914 if (vars->line_speed == ELINK_SPEED_10000) 5915 reg_val |= 5916 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4; 5917 } 5918 5919 CL22_WR_OVER_CL45(sc, phy, 5920 MDIO_REG_BANK_SERDES_DIGITAL, 5921 MDIO_SERDES_DIGITAL_MISC1, reg_val); 5922 5923 } 5924 5925 static void elink_set_brcm_cl37_advertisement(struct elink_phy *phy, 5926 struct elink_params *params) 5927 { 5928 struct bxe_softc *sc = params->sc; 5929 uint16_t val = 0; 5930 5931 /* Set extended capabilities */ 5932 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) 5933 val |= MDIO_OVER_1G_UP1_2_5G; 5934 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) 5935 val |= MDIO_OVER_1G_UP1_10G; 5936 CL22_WR_OVER_CL45(sc, phy, 5937 MDIO_REG_BANK_OVER_1G, 5938 MDIO_OVER_1G_UP1, val); 5939 5940 CL22_WR_OVER_CL45(sc, phy, 5941 MDIO_REG_BANK_OVER_1G, 5942 MDIO_OVER_1G_UP3, 0x400); 5943 } 5944 5945 static void elink_set_ieee_aneg_advertisement(struct elink_phy *phy, 5946 struct elink_params *params, 5947 uint16_t ieee_fc) 5948 { 5949 struct bxe_softc *sc = params->sc; 5950 uint16_t val; 5951 /* For AN, we are always publishing full duplex */ 5952 5953 CL22_WR_OVER_CL45(sc, phy, 5954 MDIO_REG_BANK_COMBO_IEEE0, 5955 MDIO_COMBO_IEEE0_AUTO_NEG_ADV, ieee_fc); 5956 CL22_RD_OVER_CL45(sc, phy, 5957 MDIO_REG_BANK_CL73_IEEEB1, 5958 MDIO_CL73_IEEEB1_AN_ADV1, &val); 5959 val &= ~MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH; 5960 val |= ((ieee_fc<<3) & MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK); 5961 CL22_WR_OVER_CL45(sc, phy, 5962 MDIO_REG_BANK_CL73_IEEEB1, 5963 MDIO_CL73_IEEEB1_AN_ADV1, val); 5964 } 5965 5966 static void elink_restart_autoneg(struct elink_phy *phy, 5967 struct elink_params *params, 5968 uint8_t enable_cl73) 5969 { 5970 struct bxe_softc *sc = params->sc; 5971 uint16_t mii_control; 5972 5973 ELINK_DEBUG_P0(sc, "elink_restart_autoneg\n"); 5974 /* Enable and restart BAM/CL37 aneg */ 5975 5976 if (enable_cl73) { 5977 CL22_RD_OVER_CL45(sc, phy, 5978 MDIO_REG_BANK_CL73_IEEEB0, 5979 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, 5980 &mii_control); 5981 5982 CL22_WR_OVER_CL45(sc, phy, 5983 MDIO_REG_BANK_CL73_IEEEB0, 5984 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, 5985 (mii_control | 5986 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN | 5987 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN)); 5988 } else { 5989 5990 CL22_RD_OVER_CL45(sc, phy, 5991 MDIO_REG_BANK_COMBO_IEEE0, 5992 MDIO_COMBO_IEEE0_MII_CONTROL, 5993 &mii_control); 5994 ELINK_DEBUG_P1(sc, 5995 "elink_restart_autoneg mii_control before = 0x%x\n", 5996 mii_control); 5997 CL22_WR_OVER_CL45(sc, phy, 5998 MDIO_REG_BANK_COMBO_IEEE0, 5999 MDIO_COMBO_IEEE0_MII_CONTROL, 6000 (mii_control | 6001 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN | 6002 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN)); 6003 } 6004 } 6005 6006 static void elink_initialize_sgmii_process(struct elink_phy *phy, 6007 struct elink_params *params, 6008 struct elink_vars *vars) 6009 { 6010 struct bxe_softc *sc = params->sc; 6011 uint16_t control1; 6012 6013 /* In SGMII mode, the unicore is always slave */ 6014 6015 CL22_RD_OVER_CL45(sc, phy, 6016 MDIO_REG_BANK_SERDES_DIGITAL, 6017 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, 6018 &control1); 6019 control1 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT; 6020 /* Set sgmii mode (and not fiber) */ 6021 control1 &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE | 6022 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET | 6023 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE); 6024 CL22_WR_OVER_CL45(sc, phy, 6025 MDIO_REG_BANK_SERDES_DIGITAL, 6026 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, 6027 control1); 6028 6029 /* If forced speed */ 6030 if (!(vars->line_speed == ELINK_SPEED_AUTO_NEG)) { 6031 /* Set speed, disable autoneg */ 6032 uint16_t mii_control; 6033 6034 CL22_RD_OVER_CL45(sc, phy, 6035 MDIO_REG_BANK_COMBO_IEEE0, 6036 MDIO_COMBO_IEEE0_MII_CONTROL, 6037 &mii_control); 6038 mii_control &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN | 6039 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK| 6040 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX); 6041 6042 switch (vars->line_speed) { 6043 case ELINK_SPEED_100: 6044 mii_control |= 6045 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100; 6046 break; 6047 case ELINK_SPEED_1000: 6048 mii_control |= 6049 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000; 6050 break; 6051 case ELINK_SPEED_10: 6052 /* There is nothing to set for 10M */ 6053 break; 6054 default: 6055 /* Invalid speed for SGMII */ 6056 ELINK_DEBUG_P1(sc, "Invalid line_speed 0x%x\n", 6057 vars->line_speed); 6058 break; 6059 } 6060 6061 /* Setting the full duplex */ 6062 if (phy->req_duplex == DUPLEX_FULL) 6063 mii_control |= 6064 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX; 6065 CL22_WR_OVER_CL45(sc, phy, 6066 MDIO_REG_BANK_COMBO_IEEE0, 6067 MDIO_COMBO_IEEE0_MII_CONTROL, 6068 mii_control); 6069 6070 } else { /* AN mode */ 6071 /* Enable and restart AN */ 6072 elink_restart_autoneg(phy, params, 0); 6073 } 6074 } 6075 6076 /* Link management 6077 */ 6078 static elink_status_t elink_direct_parallel_detect_used(struct elink_phy *phy, 6079 struct elink_params *params) 6080 { 6081 struct bxe_softc *sc = params->sc; 6082 uint16_t pd_10g, status2_1000x; 6083 if (phy->req_line_speed != ELINK_SPEED_AUTO_NEG) 6084 return ELINK_STATUS_OK; 6085 CL22_RD_OVER_CL45(sc, phy, 6086 MDIO_REG_BANK_SERDES_DIGITAL, 6087 MDIO_SERDES_DIGITAL_A_1000X_STATUS2, 6088 &status2_1000x); 6089 CL22_RD_OVER_CL45(sc, phy, 6090 MDIO_REG_BANK_SERDES_DIGITAL, 6091 MDIO_SERDES_DIGITAL_A_1000X_STATUS2, 6092 &status2_1000x); 6093 if (status2_1000x & MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED) { 6094 ELINK_DEBUG_P1(sc, "1G parallel detect link on port %d\n", 6095 params->port); 6096 return 1; 6097 } 6098 6099 CL22_RD_OVER_CL45(sc, phy, 6100 MDIO_REG_BANK_10G_PARALLEL_DETECT, 6101 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS, 6102 &pd_10g); 6103 6104 if (pd_10g & MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK) { 6105 ELINK_DEBUG_P1(sc, "10G parallel detect link on port %d\n", 6106 params->port); 6107 return 1; 6108 } 6109 return ELINK_STATUS_OK; 6110 } 6111 6112 static void elink_update_adv_fc(struct elink_phy *phy, 6113 struct elink_params *params, 6114 struct elink_vars *vars, 6115 uint32_t gp_status) 6116 { 6117 uint16_t ld_pause; /* local driver */ 6118 uint16_t lp_pause; /* link partner */ 6119 uint16_t pause_result; 6120 struct bxe_softc *sc = params->sc; 6121 if ((gp_status & 6122 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | 6123 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) == 6124 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | 6125 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) { 6126 6127 CL22_RD_OVER_CL45(sc, phy, 6128 MDIO_REG_BANK_CL73_IEEEB1, 6129 MDIO_CL73_IEEEB1_AN_ADV1, 6130 &ld_pause); 6131 CL22_RD_OVER_CL45(sc, phy, 6132 MDIO_REG_BANK_CL73_IEEEB1, 6133 MDIO_CL73_IEEEB1_AN_LP_ADV1, 6134 &lp_pause); 6135 pause_result = (ld_pause & 6136 MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK) >> 8; 6137 pause_result |= (lp_pause & 6138 MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK) >> 10; 6139 ELINK_DEBUG_P1(sc, "pause_result CL73 0x%x\n", pause_result); 6140 } else { 6141 CL22_RD_OVER_CL45(sc, phy, 6142 MDIO_REG_BANK_COMBO_IEEE0, 6143 MDIO_COMBO_IEEE0_AUTO_NEG_ADV, 6144 &ld_pause); 6145 CL22_RD_OVER_CL45(sc, phy, 6146 MDIO_REG_BANK_COMBO_IEEE0, 6147 MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1, 6148 &lp_pause); 6149 pause_result = (ld_pause & 6150 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>5; 6151 pause_result |= (lp_pause & 6152 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>7; 6153 ELINK_DEBUG_P1(sc, "pause_result CL37 0x%x\n", pause_result); 6154 } 6155 elink_pause_resolve(vars, pause_result); 6156 6157 } 6158 6159 static void elink_flow_ctrl_resolve(struct elink_phy *phy, 6160 struct elink_params *params, 6161 struct elink_vars *vars, 6162 uint32_t gp_status) 6163 { 6164 struct bxe_softc *sc = params->sc; 6165 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE; 6166 6167 /* Resolve from gp_status in case of AN complete and not sgmii */ 6168 if (phy->req_flow_ctrl != ELINK_FLOW_CTRL_AUTO) { 6169 /* Update the advertised flow-controled of LD/LP in AN */ 6170 if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG) 6171 elink_update_adv_fc(phy, params, vars, gp_status); 6172 /* But set the flow-control result as the requested one */ 6173 vars->flow_ctrl = phy->req_flow_ctrl; 6174 } else if (phy->req_line_speed != ELINK_SPEED_AUTO_NEG) 6175 vars->flow_ctrl = params->req_fc_auto_adv; 6176 else if ((gp_status & ELINK_MDIO_AN_CL73_OR_37_COMPLETE) && 6177 (!(vars->phy_flags & PHY_SGMII_FLAG))) { 6178 if (elink_direct_parallel_detect_used(phy, params)) { 6179 vars->flow_ctrl = params->req_fc_auto_adv; 6180 return; 6181 } 6182 elink_update_adv_fc(phy, params, vars, gp_status); 6183 } 6184 ELINK_DEBUG_P1(sc, "flow_ctrl 0x%x\n", vars->flow_ctrl); 6185 } 6186 6187 static void elink_check_fallback_to_cl37(struct elink_phy *phy, 6188 struct elink_params *params) 6189 { 6190 struct bxe_softc *sc = params->sc; 6191 uint16_t rx_status, ustat_val, cl37_fsm_received; 6192 ELINK_DEBUG_P0(sc, "elink_check_fallback_to_cl37\n"); 6193 /* Step 1: Make sure signal is detected */ 6194 CL22_RD_OVER_CL45(sc, phy, 6195 MDIO_REG_BANK_RX0, 6196 MDIO_RX0_RX_STATUS, 6197 &rx_status); 6198 if ((rx_status & MDIO_RX0_RX_STATUS_SIGDET) != 6199 (MDIO_RX0_RX_STATUS_SIGDET)) { 6200 ELINK_DEBUG_P1(sc, "Signal is not detected. Restoring CL73." 6201 "rx_status(0x80b0) = 0x%x\n", rx_status); 6202 CL22_WR_OVER_CL45(sc, phy, 6203 MDIO_REG_BANK_CL73_IEEEB0, 6204 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, 6205 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN); 6206 return; 6207 } 6208 /* Step 2: Check CL73 state machine */ 6209 CL22_RD_OVER_CL45(sc, phy, 6210 MDIO_REG_BANK_CL73_USERB0, 6211 MDIO_CL73_USERB0_CL73_USTAT1, 6212 &ustat_val); 6213 if ((ustat_val & 6214 (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK | 6215 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) != 6216 (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK | 6217 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) { 6218 ELINK_DEBUG_P1(sc, "CL73 state-machine is not stable. " 6219 "ustat_val(0x8371) = 0x%x\n", ustat_val); 6220 return; 6221 } 6222 /* Step 3: Check CL37 Message Pages received to indicate LP 6223 * supports only CL37 6224 */ 6225 CL22_RD_OVER_CL45(sc, phy, 6226 MDIO_REG_BANK_REMOTE_PHY, 6227 MDIO_REMOTE_PHY_MISC_RX_STATUS, 6228 &cl37_fsm_received); 6229 if ((cl37_fsm_received & 6230 (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG | 6231 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) != 6232 (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG | 6233 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) { 6234 ELINK_DEBUG_P1(sc, "No CL37 FSM were received. " 6235 "misc_rx_status(0x8330) = 0x%x\n", 6236 cl37_fsm_received); 6237 return; 6238 } 6239 /* The combined cl37/cl73 fsm state information indicating that 6240 * we are connected to a device which does not support cl73, but 6241 * does support cl37 BAM. In this case we disable cl73 and 6242 * restart cl37 auto-neg 6243 */ 6244 6245 /* Disable CL73 */ 6246 CL22_WR_OVER_CL45(sc, phy, 6247 MDIO_REG_BANK_CL73_IEEEB0, 6248 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, 6249 0); 6250 /* Restart CL37 autoneg */ 6251 elink_restart_autoneg(phy, params, 0); 6252 ELINK_DEBUG_P0(sc, "Disabling CL73, and restarting CL37 autoneg\n"); 6253 } 6254 6255 static void elink_xgxs_an_resolve(struct elink_phy *phy, 6256 struct elink_params *params, 6257 struct elink_vars *vars, 6258 uint32_t gp_status) 6259 { 6260 if (gp_status & ELINK_MDIO_AN_CL73_OR_37_COMPLETE) 6261 vars->link_status |= 6262 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; 6263 6264 if (elink_direct_parallel_detect_used(phy, params)) 6265 vars->link_status |= 6266 LINK_STATUS_PARALLEL_DETECTION_USED; 6267 } 6268 static elink_status_t elink_get_link_speed_duplex(struct elink_phy *phy, 6269 struct elink_params *params, 6270 struct elink_vars *vars, 6271 uint16_t is_link_up, 6272 uint16_t speed_mask, 6273 uint16_t is_duplex) 6274 { 6275 struct bxe_softc *sc = params->sc; 6276 if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG) 6277 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED; 6278 if (is_link_up) { 6279 ELINK_DEBUG_P0(sc, "phy link up\n"); 6280 6281 vars->phy_link_up = 1; 6282 vars->link_status |= LINK_STATUS_LINK_UP; 6283 6284 switch (speed_mask) { 6285 case ELINK_GP_STATUS_10M: 6286 vars->line_speed = ELINK_SPEED_10; 6287 if (is_duplex == DUPLEX_FULL) 6288 vars->link_status |= ELINK_LINK_10TFD; 6289 else 6290 vars->link_status |= ELINK_LINK_10THD; 6291 break; 6292 6293 case ELINK_GP_STATUS_100M: 6294 vars->line_speed = ELINK_SPEED_100; 6295 if (is_duplex == DUPLEX_FULL) 6296 vars->link_status |= ELINK_LINK_100TXFD; 6297 else 6298 vars->link_status |= ELINK_LINK_100TXHD; 6299 break; 6300 6301 case ELINK_GP_STATUS_1G: 6302 case ELINK_GP_STATUS_1G_KX: 6303 vars->line_speed = ELINK_SPEED_1000; 6304 if (is_duplex == DUPLEX_FULL) 6305 vars->link_status |= ELINK_LINK_1000TFD; 6306 else 6307 vars->link_status |= ELINK_LINK_1000THD; 6308 break; 6309 6310 case ELINK_GP_STATUS_2_5G: 6311 vars->line_speed = ELINK_SPEED_2500; 6312 if (is_duplex == DUPLEX_FULL) 6313 vars->link_status |= ELINK_LINK_2500TFD; 6314 else 6315 vars->link_status |= ELINK_LINK_2500THD; 6316 break; 6317 6318 case ELINK_GP_STATUS_5G: 6319 case ELINK_GP_STATUS_6G: 6320 ELINK_DEBUG_P1(sc, 6321 "link speed unsupported gp_status 0x%x\n", 6322 speed_mask); 6323 return ELINK_STATUS_ERROR; 6324 6325 case ELINK_GP_STATUS_10G_KX4: 6326 case ELINK_GP_STATUS_10G_HIG: 6327 case ELINK_GP_STATUS_10G_CX4: 6328 case ELINK_GP_STATUS_10G_KR: 6329 case ELINK_GP_STATUS_10G_SFI: 6330 case ELINK_GP_STATUS_10G_XFI: 6331 vars->line_speed = ELINK_SPEED_10000; 6332 vars->link_status |= ELINK_LINK_10GTFD; 6333 break; 6334 case ELINK_GP_STATUS_20G_DXGXS: 6335 case ELINK_GP_STATUS_20G_KR2: 6336 vars->line_speed = ELINK_SPEED_20000; 6337 vars->link_status |= ELINK_LINK_20GTFD; 6338 break; 6339 default: 6340 ELINK_DEBUG_P1(sc, 6341 "link speed unsupported gp_status 0x%x\n", 6342 speed_mask); 6343 return ELINK_STATUS_ERROR; 6344 } 6345 } else { /* link_down */ 6346 ELINK_DEBUG_P0(sc, "phy link down\n"); 6347 6348 vars->phy_link_up = 0; 6349 6350 vars->duplex = DUPLEX_FULL; 6351 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE; 6352 vars->mac_type = ELINK_MAC_TYPE_NONE; 6353 } 6354 ELINK_DEBUG_P2(sc, " phy_link_up %x line_speed %d\n", 6355 vars->phy_link_up, vars->line_speed); 6356 return ELINK_STATUS_OK; 6357 } 6358 6359 static elink_status_t elink_link_settings_status(struct elink_phy *phy, 6360 struct elink_params *params, 6361 struct elink_vars *vars) 6362 { 6363 struct bxe_softc *sc = params->sc; 6364 6365 uint16_t gp_status, duplex = DUPLEX_HALF, link_up = 0, speed_mask; 6366 elink_status_t rc = ELINK_STATUS_OK; 6367 6368 /* Read gp_status */ 6369 CL22_RD_OVER_CL45(sc, phy, 6370 MDIO_REG_BANK_GP_STATUS, 6371 MDIO_GP_STATUS_TOP_AN_STATUS1, 6372 &gp_status); 6373 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS) 6374 duplex = DUPLEX_FULL; 6375 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) 6376 link_up = 1; 6377 speed_mask = gp_status & ELINK_GP_STATUS_SPEED_MASK; 6378 ELINK_DEBUG_P3(sc, "gp_status 0x%x, is_link_up %d, speed_mask 0x%x\n", 6379 gp_status, link_up, speed_mask); 6380 rc = elink_get_link_speed_duplex(phy, params, vars, link_up, speed_mask, 6381 duplex); 6382 if (rc == ELINK_STATUS_ERROR) 6383 return rc; 6384 6385 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) { 6386 if (ELINK_SINGLE_MEDIA_DIRECT(params)) { 6387 vars->duplex = duplex; 6388 elink_flow_ctrl_resolve(phy, params, vars, gp_status); 6389 if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG) 6390 elink_xgxs_an_resolve(phy, params, vars, 6391 gp_status); 6392 } 6393 } else { /* Link_down */ 6394 if ((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) && 6395 ELINK_SINGLE_MEDIA_DIRECT(params)) { 6396 /* Check signal is detected */ 6397 elink_check_fallback_to_cl37(phy, params); 6398 } 6399 } 6400 6401 /* Read LP advertised speeds*/ 6402 if (ELINK_SINGLE_MEDIA_DIRECT(params) && 6403 (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)) { 6404 uint16_t val; 6405 6406 CL22_RD_OVER_CL45(sc, phy, MDIO_REG_BANK_CL73_IEEEB1, 6407 MDIO_CL73_IEEEB1_AN_LP_ADV2, &val); 6408 6409 if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX) 6410 vars->link_status |= 6411 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE; 6412 if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 | 6413 MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR)) 6414 vars->link_status |= 6415 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; 6416 6417 CL22_RD_OVER_CL45(sc, phy, MDIO_REG_BANK_OVER_1G, 6418 MDIO_OVER_1G_LP_UP1, &val); 6419 6420 if (val & MDIO_OVER_1G_UP1_2_5G) 6421 vars->link_status |= 6422 LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE; 6423 if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH)) 6424 vars->link_status |= 6425 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; 6426 } 6427 6428 ELINK_DEBUG_P3(sc, "duplex %x flow_ctrl 0x%x link_status 0x%x\n", 6429 vars->duplex, vars->flow_ctrl, vars->link_status); 6430 return rc; 6431 } 6432 6433 static elink_status_t elink_warpcore_read_status(struct elink_phy *phy, 6434 struct elink_params *params, 6435 struct elink_vars *vars) 6436 { 6437 struct bxe_softc *sc = params->sc; 6438 uint8_t lane; 6439 uint16_t gp_status1, gp_speed, link_up, duplex = DUPLEX_FULL; 6440 elink_status_t rc = ELINK_STATUS_OK; 6441 lane = elink_get_warpcore_lane(phy, params); 6442 /* Read gp_status */ 6443 if ((params->loopback_mode) && 6444 (phy->flags & ELINK_FLAGS_WC_DUAL_MODE)) { 6445 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, 6446 MDIO_WC_REG_DIGITAL5_LINK_STATUS, &link_up); 6447 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, 6448 MDIO_WC_REG_DIGITAL5_LINK_STATUS, &link_up); 6449 link_up &= 0x1; 6450 } else if ((phy->req_line_speed > ELINK_SPEED_10000) && 6451 (phy->supported & ELINK_SUPPORTED_20000baseMLD2_Full)) { 6452 uint16_t temp_link_up; 6453 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, 6454 1, &temp_link_up); 6455 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, 6456 1, &link_up); 6457 ELINK_DEBUG_P2(sc, "PCS RX link status = 0x%x-->0x%x\n", 6458 temp_link_up, link_up); 6459 link_up &= (1<<2); 6460 if (link_up) 6461 elink_ext_phy_resolve_fc(phy, params, vars); 6462 } else { 6463 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, 6464 MDIO_WC_REG_GP2_STATUS_GP_2_1, 6465 &gp_status1); 6466 ELINK_DEBUG_P1(sc, "0x81d1 = 0x%x\n", gp_status1); 6467 /* Check for either KR, 1G, or AN up. */ 6468 link_up = ((gp_status1 >> 8) | 6469 (gp_status1 >> 12) | 6470 (gp_status1)) & 6471 (1 << lane); 6472 if (phy->supported & ELINK_SUPPORTED_20000baseKR2_Full) { 6473 uint16_t an_link; 6474 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, 6475 MDIO_AN_REG_STATUS, &an_link); 6476 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, 6477 MDIO_AN_REG_STATUS, &an_link); 6478 link_up |= (an_link & (1<<2)); 6479 } 6480 if (link_up && ELINK_SINGLE_MEDIA_DIRECT(params)) { 6481 uint16_t pd, gp_status4; 6482 if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG) { 6483 /* Check Autoneg complete */ 6484 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, 6485 MDIO_WC_REG_GP2_STATUS_GP_2_4, 6486 &gp_status4); 6487 if (gp_status4 & ((1<<12)<<lane)) 6488 vars->link_status |= 6489 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; 6490 6491 /* Check parallel detect used */ 6492 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, 6493 MDIO_WC_REG_PAR_DET_10G_STATUS, 6494 &pd); 6495 if (pd & (1<<15)) 6496 vars->link_status |= 6497 LINK_STATUS_PARALLEL_DETECTION_USED; 6498 } 6499 elink_ext_phy_resolve_fc(phy, params, vars); 6500 vars->duplex = duplex; 6501 } 6502 } 6503 6504 if ((vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) && 6505 ELINK_SINGLE_MEDIA_DIRECT(params)) { 6506 uint16_t val; 6507 6508 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, 6509 MDIO_AN_REG_LP_AUTO_NEG2, &val); 6510 6511 if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX) 6512 vars->link_status |= 6513 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE; 6514 if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 | 6515 MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR)) 6516 vars->link_status |= 6517 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; 6518 6519 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, 6520 MDIO_WC_REG_DIGITAL3_LP_UP1, &val); 6521 6522 if (val & MDIO_OVER_1G_UP1_2_5G) 6523 vars->link_status |= 6524 LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE; 6525 if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH)) 6526 vars->link_status |= 6527 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; 6528 6529 } 6530 6531 6532 if (lane < 2) { 6533 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, 6534 MDIO_WC_REG_GP2_STATUS_GP_2_2, &gp_speed); 6535 } else { 6536 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, 6537 MDIO_WC_REG_GP2_STATUS_GP_2_3, &gp_speed); 6538 } 6539 ELINK_DEBUG_P2(sc, "lane %d gp_speed 0x%x\n", lane, gp_speed); 6540 6541 if ((lane & 1) == 0) 6542 gp_speed <<= 8; 6543 gp_speed &= 0x3f00; 6544 link_up = !!link_up; 6545 6546 /* Reset the TX FIFO to fix SGMII issue */ 6547 rc = elink_get_link_speed_duplex(phy, params, vars, link_up, gp_speed, 6548 duplex); 6549 6550 /* In case of KR link down, start up the recovering procedure */ 6551 if ((!link_up) && (phy->media_type == ELINK_ETH_PHY_KR) && 6552 (!(phy->flags & ELINK_FLAGS_WC_DUAL_MODE))) 6553 vars->rx_tx_asic_rst = MAX_KR_LINK_RETRY; 6554 6555 ELINK_DEBUG_P3(sc, "duplex %x flow_ctrl 0x%x link_status 0x%x\n", 6556 vars->duplex, vars->flow_ctrl, vars->link_status); 6557 return rc; 6558 } 6559 static void elink_set_gmii_tx_driver(struct elink_params *params) 6560 { 6561 struct bxe_softc *sc = params->sc; 6562 struct elink_phy *phy = ¶ms->phy[ELINK_INT_PHY]; 6563 uint16_t lp_up2; 6564 uint16_t tx_driver; 6565 uint16_t bank; 6566 6567 /* Read precomp */ 6568 CL22_RD_OVER_CL45(sc, phy, 6569 MDIO_REG_BANK_OVER_1G, 6570 MDIO_OVER_1G_LP_UP2, &lp_up2); 6571 6572 /* Bits [10:7] at lp_up2, positioned at [15:12] */ 6573 lp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >> 6574 MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT) << 6575 MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT); 6576 6577 if (lp_up2 == 0) 6578 return; 6579 6580 for (bank = MDIO_REG_BANK_TX0; bank <= MDIO_REG_BANK_TX3; 6581 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) { 6582 CL22_RD_OVER_CL45(sc, phy, 6583 bank, 6584 MDIO_TX0_TX_DRIVER, &tx_driver); 6585 6586 /* Replace tx_driver bits [15:12] */ 6587 if (lp_up2 != 6588 (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK)) { 6589 tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK; 6590 tx_driver |= lp_up2; 6591 CL22_WR_OVER_CL45(sc, phy, 6592 bank, 6593 MDIO_TX0_TX_DRIVER, tx_driver); 6594 } 6595 } 6596 } 6597 6598 static elink_status_t elink_emac_program(struct elink_params *params, 6599 struct elink_vars *vars) 6600 { 6601 struct bxe_softc *sc = params->sc; 6602 uint8_t port = params->port; 6603 uint16_t mode = 0; 6604 6605 ELINK_DEBUG_P0(sc, "setting link speed & duplex\n"); 6606 elink_bits_dis(sc, GRCBASE_EMAC0 + port*0x400 + 6607 EMAC_REG_EMAC_MODE, 6608 (EMAC_MODE_25G_MODE | 6609 EMAC_MODE_PORT_MII_10M | 6610 EMAC_MODE_HALF_DUPLEX)); 6611 switch (vars->line_speed) { 6612 case ELINK_SPEED_10: 6613 mode |= EMAC_MODE_PORT_MII_10M; 6614 break; 6615 6616 case ELINK_SPEED_100: 6617 mode |= EMAC_MODE_PORT_MII; 6618 break; 6619 6620 case ELINK_SPEED_1000: 6621 mode |= EMAC_MODE_PORT_GMII; 6622 break; 6623 6624 case ELINK_SPEED_2500: 6625 mode |= (EMAC_MODE_25G_MODE | EMAC_MODE_PORT_GMII); 6626 break; 6627 6628 default: 6629 /* 10G not valid for EMAC */ 6630 ELINK_DEBUG_P1(sc, "Invalid line_speed 0x%x\n", 6631 vars->line_speed); 6632 return ELINK_STATUS_ERROR; 6633 } 6634 6635 if (vars->duplex == DUPLEX_HALF) 6636 mode |= EMAC_MODE_HALF_DUPLEX; 6637 elink_bits_en(sc, 6638 GRCBASE_EMAC0 + port*0x400 + EMAC_REG_EMAC_MODE, 6639 mode); 6640 6641 elink_set_led(params, vars, ELINK_LED_MODE_OPER, vars->line_speed); 6642 return ELINK_STATUS_OK; 6643 } 6644 6645 static void elink_set_preemphasis(struct elink_phy *phy, 6646 struct elink_params *params) 6647 { 6648 6649 uint16_t bank, i = 0; 6650 struct bxe_softc *sc = params->sc; 6651 6652 for (bank = MDIO_REG_BANK_RX0, i = 0; bank <= MDIO_REG_BANK_RX3; 6653 bank += (MDIO_REG_BANK_RX1-MDIO_REG_BANK_RX0), i++) { 6654 CL22_WR_OVER_CL45(sc, phy, 6655 bank, 6656 MDIO_RX0_RX_EQ_BOOST, 6657 phy->rx_preemphasis[i]); 6658 } 6659 6660 for (bank = MDIO_REG_BANK_TX0, i = 0; bank <= MDIO_REG_BANK_TX3; 6661 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0), i++) { 6662 CL22_WR_OVER_CL45(sc, phy, 6663 bank, 6664 MDIO_TX0_TX_DRIVER, 6665 phy->tx_preemphasis[i]); 6666 } 6667 } 6668 6669 static void elink_xgxs_config_init(struct elink_phy *phy, 6670 struct elink_params *params, 6671 struct elink_vars *vars) 6672 { 6673 struct bxe_softc *sc = params->sc; 6674 uint8_t enable_cl73 = (ELINK_SINGLE_MEDIA_DIRECT(params) || 6675 (params->loopback_mode == ELINK_LOOPBACK_XGXS)); 6676 if (!(vars->phy_flags & PHY_SGMII_FLAG)) { 6677 if (ELINK_SINGLE_MEDIA_DIRECT(params) && 6678 (params->feature_config_flags & 6679 ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) 6680 elink_set_preemphasis(phy, params); 6681 6682 /* Forced speed requested? */ 6683 if (vars->line_speed != ELINK_SPEED_AUTO_NEG || 6684 (ELINK_SINGLE_MEDIA_DIRECT(params) && 6685 params->loopback_mode == ELINK_LOOPBACK_EXT)) { 6686 ELINK_DEBUG_P0(sc, "not SGMII, no AN\n"); 6687 6688 /* Disable autoneg */ 6689 elink_set_autoneg(phy, params, vars, 0); 6690 6691 /* Program speed and duplex */ 6692 elink_program_serdes(phy, params, vars); 6693 6694 } else { /* AN_mode */ 6695 ELINK_DEBUG_P0(sc, "not SGMII, AN\n"); 6696 6697 /* AN enabled */ 6698 elink_set_brcm_cl37_advertisement(phy, params); 6699 6700 /* Program duplex & pause advertisement (for aneg) */ 6701 elink_set_ieee_aneg_advertisement(phy, params, 6702 vars->ieee_fc); 6703 6704 /* Enable autoneg */ 6705 elink_set_autoneg(phy, params, vars, enable_cl73); 6706 6707 /* Enable and restart AN */ 6708 elink_restart_autoneg(phy, params, enable_cl73); 6709 } 6710 6711 } else { /* SGMII mode */ 6712 ELINK_DEBUG_P0(sc, "SGMII\n"); 6713 6714 elink_initialize_sgmii_process(phy, params, vars); 6715 } 6716 } 6717 6718 static elink_status_t elink_prepare_xgxs(struct elink_phy *phy, 6719 struct elink_params *params, 6720 struct elink_vars *vars) 6721 { 6722 elink_status_t rc; 6723 vars->phy_flags |= PHY_XGXS_FLAG; 6724 if ((phy->req_line_speed && 6725 ((phy->req_line_speed == ELINK_SPEED_100) || 6726 (phy->req_line_speed == ELINK_SPEED_10))) || 6727 (!phy->req_line_speed && 6728 (phy->speed_cap_mask >= 6729 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) && 6730 (phy->speed_cap_mask < 6731 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) || 6732 (phy->type == PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD)) 6733 vars->phy_flags |= PHY_SGMII_FLAG; 6734 else 6735 vars->phy_flags &= ~PHY_SGMII_FLAG; 6736 6737 elink_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc); 6738 elink_set_aer_mmd(params, phy); 6739 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) 6740 elink_set_master_ln(params, phy); 6741 6742 rc = elink_reset_unicore(params, phy, 0); 6743 /* Reset the SerDes and wait for reset bit return low */ 6744 if (rc != ELINK_STATUS_OK) 6745 return rc; 6746 6747 elink_set_aer_mmd(params, phy); 6748 /* Setting the masterLn_def again after the reset */ 6749 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) { 6750 elink_set_master_ln(params, phy); 6751 elink_set_swap_lanes(params, phy); 6752 } 6753 6754 return rc; 6755 } 6756 6757 static uint16_t elink_wait_reset_complete(struct bxe_softc *sc, 6758 struct elink_phy *phy, 6759 struct elink_params *params) 6760 { 6761 uint16_t cnt, ctrl; 6762 /* Wait for soft reset to get cleared up to 1 sec */ 6763 for (cnt = 0; cnt < 1000; cnt++) { 6764 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) 6765 elink_cl22_read(sc, phy, 6766 MDIO_PMA_REG_CTRL, &ctrl); 6767 else 6768 elink_cl45_read(sc, phy, 6769 MDIO_PMA_DEVAD, 6770 MDIO_PMA_REG_CTRL, &ctrl); 6771 if (!(ctrl & (1<<15))) 6772 break; 6773 DELAY(1000 * 1); 6774 } 6775 6776 if (cnt == 1000) 6777 elink_cb_event_log(sc, ELINK_LOG_ID_PHY_UNINITIALIZED, params->port); // "Warning: PHY was not initialized," 6778 // " Port %d\n", 6779 6780 ELINK_DEBUG_P2(sc, "control reg 0x%x (after %d ms)\n", ctrl, cnt); 6781 return cnt; 6782 } 6783 6784 static void elink_link_int_enable(struct elink_params *params) 6785 { 6786 uint8_t port = params->port; 6787 uint32_t mask; 6788 struct bxe_softc *sc = params->sc; 6789 6790 /* Setting the status to report on link up for either XGXS or SerDes */ 6791 if (CHIP_IS_E3(sc)) { 6792 mask = ELINK_NIG_MASK_XGXS0_LINK_STATUS; 6793 if (!(ELINK_SINGLE_MEDIA_DIRECT(params))) 6794 mask |= ELINK_NIG_MASK_MI_INT; 6795 } else if (params->switch_cfg == ELINK_SWITCH_CFG_10G) { 6796 mask = (ELINK_NIG_MASK_XGXS0_LINK10G | 6797 ELINK_NIG_MASK_XGXS0_LINK_STATUS); 6798 ELINK_DEBUG_P0(sc, "enabled XGXS interrupt\n"); 6799 if (!(ELINK_SINGLE_MEDIA_DIRECT(params)) && 6800 params->phy[ELINK_INT_PHY].type != 6801 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) { 6802 mask |= ELINK_NIG_MASK_MI_INT; 6803 ELINK_DEBUG_P0(sc, "enabled external phy int\n"); 6804 } 6805 6806 } else { /* SerDes */ 6807 mask = ELINK_NIG_MASK_SERDES0_LINK_STATUS; 6808 ELINK_DEBUG_P0(sc, "enabled SerDes interrupt\n"); 6809 if (!(ELINK_SINGLE_MEDIA_DIRECT(params)) && 6810 params->phy[ELINK_INT_PHY].type != 6811 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN) { 6812 mask |= ELINK_NIG_MASK_MI_INT; 6813 ELINK_DEBUG_P0(sc, "enabled external phy int\n"); 6814 } 6815 } 6816 elink_bits_en(sc, 6817 NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 6818 mask); 6819 6820 ELINK_DEBUG_P3(sc, "port %x, is_xgxs %x, int_status 0x%x\n", port, 6821 (params->switch_cfg == ELINK_SWITCH_CFG_10G), 6822 REG_RD(sc, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4)); 6823 ELINK_DEBUG_P3(sc, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x\n", 6824 REG_RD(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port*4), 6825 REG_RD(sc, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18), 6826 REG_RD(sc, NIG_REG_SERDES0_STATUS_LINK_STATUS+port*0x3c)); 6827 ELINK_DEBUG_P2(sc, " 10G %x, XGXS_LINK %x\n", 6828 REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68), 6829 REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68)); 6830 } 6831 6832 static void elink_rearm_latch_signal(struct bxe_softc *sc, uint8_t port, 6833 uint8_t exp_mi_int) 6834 { 6835 uint32_t latch_status = 0; 6836 6837 /* Disable the MI INT ( external phy int ) by writing 1 to the 6838 * status register. Link down indication is high-active-signal, 6839 * so in this case we need to write the status to clear the XOR 6840 */ 6841 /* Read Latched signals */ 6842 latch_status = REG_RD(sc, 6843 NIG_REG_LATCH_STATUS_0 + port*8); 6844 ELINK_DEBUG_P1(sc, "latch_status = 0x%x\n", latch_status); 6845 /* Handle only those with latched-signal=up.*/ 6846 if (exp_mi_int) 6847 elink_bits_en(sc, 6848 NIG_REG_STATUS_INTERRUPT_PORT0 6849 + port*4, 6850 ELINK_NIG_STATUS_EMAC0_MI_INT); 6851 else 6852 elink_bits_dis(sc, 6853 NIG_REG_STATUS_INTERRUPT_PORT0 6854 + port*4, 6855 ELINK_NIG_STATUS_EMAC0_MI_INT); 6856 6857 if (latch_status & 1) { 6858 6859 /* For all latched-signal=up : Re-Arm Latch signals */ 6860 REG_WR(sc, NIG_REG_LATCH_STATUS_0 + port*8, 6861 (latch_status & 0xfffe) | (latch_status & 1)); 6862 } 6863 /* For all latched-signal=up,Write original_signal to status */ 6864 } 6865 6866 static void elink_link_int_ack(struct elink_params *params, 6867 struct elink_vars *vars, uint8_t is_10g_plus) 6868 { 6869 struct bxe_softc *sc = params->sc; 6870 uint8_t port = params->port; 6871 uint32_t mask; 6872 /* First reset all status we assume only one line will be 6873 * change at a time 6874 */ 6875 elink_bits_dis(sc, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4, 6876 (ELINK_NIG_STATUS_XGXS0_LINK10G | 6877 ELINK_NIG_STATUS_XGXS0_LINK_STATUS | 6878 ELINK_NIG_STATUS_SERDES0_LINK_STATUS)); 6879 if (vars->phy_link_up) { 6880 if (USES_WARPCORE(sc)) 6881 mask = ELINK_NIG_STATUS_XGXS0_LINK_STATUS; 6882 else { 6883 if (is_10g_plus) 6884 mask = ELINK_NIG_STATUS_XGXS0_LINK10G; 6885 else if (params->switch_cfg == ELINK_SWITCH_CFG_10G) { 6886 /* Disable the link interrupt by writing 1 to 6887 * the relevant lane in the status register 6888 */ 6889 uint32_t ser_lane = 6890 ((params->lane_config & 6891 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >> 6892 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT); 6893 mask = ((1 << ser_lane) << 6894 ELINK_NIG_STATUS_XGXS0_LINK_STATUS_SIZE); 6895 } else 6896 mask = ELINK_NIG_STATUS_SERDES0_LINK_STATUS; 6897 } 6898 ELINK_DEBUG_P1(sc, "Ack link up interrupt with mask 0x%x\n", 6899 mask); 6900 elink_bits_en(sc, 6901 NIG_REG_STATUS_INTERRUPT_PORT0 + port*4, 6902 mask); 6903 } 6904 } 6905 6906 static elink_status_t elink_format_ver(uint32_t num, uint8_t *str, uint16_t *len) 6907 { 6908 uint8_t *str_ptr = str; 6909 uint32_t mask = 0xf0000000; 6910 uint8_t shift = 8*4; 6911 uint8_t digit; 6912 uint8_t remove_leading_zeros = 1; 6913 if (*len < 10) { 6914 /* Need more than 10chars for this format */ 6915 *str_ptr = '\0'; 6916 (*len)--; 6917 return ELINK_STATUS_ERROR; 6918 } 6919 while (shift > 0) { 6920 6921 shift -= 4; 6922 digit = ((num & mask) >> shift); 6923 if (digit == 0 && remove_leading_zeros) { 6924 mask = mask >> 4; 6925 continue; 6926 } else if (digit < 0xa) 6927 *str_ptr = digit + '0'; 6928 else 6929 *str_ptr = digit - 0xa + 'a'; 6930 remove_leading_zeros = 0; 6931 str_ptr++; 6932 (*len)--; 6933 mask = mask >> 4; 6934 if (shift == 4*4) { 6935 *str_ptr = '.'; 6936 str_ptr++; 6937 (*len)--; 6938 remove_leading_zeros = 1; 6939 } 6940 } 6941 return ELINK_STATUS_OK; 6942 } 6943 6944 6945 static elink_status_t elink_null_format_ver(uint32_t spirom_ver, uint8_t *str, uint16_t *len) 6946 { 6947 str[0] = '\0'; 6948 (*len)--; 6949 return ELINK_STATUS_OK; 6950 } 6951 6952 elink_status_t elink_get_ext_phy_fw_version(struct elink_params *params, uint8_t *version, 6953 uint16_t len) 6954 { 6955 struct bxe_softc *sc; 6956 uint32_t spirom_ver = 0; 6957 elink_status_t status = ELINK_STATUS_OK; 6958 uint8_t *ver_p = version; 6959 uint16_t remain_len = len; 6960 if (version == NULL || params == NULL) 6961 return ELINK_STATUS_ERROR; 6962 sc = params->sc; 6963 6964 /* Extract first external phy*/ 6965 version[0] = '\0'; 6966 spirom_ver = REG_RD(sc, params->phy[ELINK_EXT_PHY1].ver_addr); 6967 6968 if (params->phy[ELINK_EXT_PHY1].format_fw_ver) { 6969 status |= params->phy[ELINK_EXT_PHY1].format_fw_ver(spirom_ver, 6970 ver_p, 6971 &remain_len); 6972 ver_p += (len - remain_len); 6973 } 6974 if ((params->num_phys == ELINK_MAX_PHYS) && 6975 (params->phy[ELINK_EXT_PHY2].ver_addr != 0)) { 6976 spirom_ver = REG_RD(sc, params->phy[ELINK_EXT_PHY2].ver_addr); 6977 if (params->phy[ELINK_EXT_PHY2].format_fw_ver) { 6978 *ver_p = '/'; 6979 ver_p++; 6980 remain_len--; 6981 status |= params->phy[ELINK_EXT_PHY2].format_fw_ver( 6982 spirom_ver, 6983 ver_p, 6984 &remain_len); 6985 ver_p = version + (len - remain_len); 6986 } 6987 } 6988 *ver_p = '\0'; 6989 return status; 6990 } 6991 6992 static void elink_set_xgxs_loopback(struct elink_phy *phy, 6993 struct elink_params *params) 6994 { 6995 uint8_t port = params->port; 6996 struct bxe_softc *sc = params->sc; 6997 6998 if (phy->req_line_speed != ELINK_SPEED_1000) { 6999 uint32_t md_devad = 0; 7000 7001 ELINK_DEBUG_P0(sc, "XGXS 10G loopback enable\n"); 7002 7003 if (!CHIP_IS_E3(sc)) { 7004 /* Change the uni_phy_addr in the nig */ 7005 md_devad = REG_RD(sc, (NIG_REG_XGXS0_CTRL_MD_DEVAD + 7006 port*0x18)); 7007 7008 REG_WR(sc, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, 7009 0x5); 7010 } 7011 7012 elink_cl45_write(sc, phy, 7013 5, 7014 (MDIO_REG_BANK_AER_BLOCK + 7015 (MDIO_AER_BLOCK_AER_REG & 0xf)), 7016 0x2800); 7017 7018 elink_cl45_write(sc, phy, 7019 5, 7020 (MDIO_REG_BANK_CL73_IEEEB0 + 7021 (MDIO_CL73_IEEEB0_CL73_AN_CONTROL & 0xf)), 7022 0x6041); 7023 DELAY(1000 * 200); 7024 /* Set aer mmd back */ 7025 elink_set_aer_mmd(params, phy); 7026 7027 if (!CHIP_IS_E3(sc)) { 7028 /* And md_devad */ 7029 REG_WR(sc, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18, 7030 md_devad); 7031 } 7032 } else { 7033 uint16_t mii_ctrl; 7034 ELINK_DEBUG_P0(sc, "XGXS 1G loopback enable\n"); 7035 elink_cl45_read(sc, phy, 5, 7036 (MDIO_REG_BANK_COMBO_IEEE0 + 7037 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)), 7038 &mii_ctrl); 7039 elink_cl45_write(sc, phy, 5, 7040 (MDIO_REG_BANK_COMBO_IEEE0 + 7041 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)), 7042 mii_ctrl | 7043 MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK); 7044 } 7045 } 7046 7047 elink_status_t elink_set_led(struct elink_params *params, 7048 struct elink_vars *vars, uint8_t mode, uint32_t speed) 7049 { 7050 uint8_t port = params->port; 7051 uint16_t hw_led_mode = params->hw_led_mode; 7052 elink_status_t rc = ELINK_STATUS_OK; 7053 uint8_t phy_idx; 7054 uint32_t tmp; 7055 uint32_t emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; 7056 struct bxe_softc *sc = params->sc; 7057 ELINK_DEBUG_P2(sc, "elink_set_led: port %x, mode %d\n", port, mode); 7058 ELINK_DEBUG_P2(sc, "speed 0x%x, hw_led_mode 0x%x\n", 7059 speed, hw_led_mode); 7060 /* In case */ 7061 for (phy_idx = ELINK_EXT_PHY1; phy_idx < ELINK_MAX_PHYS; phy_idx++) { 7062 if (params->phy[phy_idx].set_link_led) { 7063 params->phy[phy_idx].set_link_led( 7064 ¶ms->phy[phy_idx], params, mode); 7065 } 7066 } 7067 #ifdef ELINK_INCLUDE_EMUL 7068 if (params->feature_config_flags & 7069 ELINK_FEATURE_CONFIG_EMUL_DISABLE_EMAC) 7070 return rc; 7071 #endif 7072 7073 switch (mode) { 7074 case ELINK_LED_MODE_FRONT_PANEL_OFF: 7075 case ELINK_LED_MODE_OFF: 7076 REG_WR(sc, NIG_REG_LED_10G_P0 + port*4, 0); 7077 REG_WR(sc, NIG_REG_LED_MODE_P0 + port*4, 7078 SHARED_HW_CFG_LED_MAC1); 7079 7080 tmp = elink_cb_reg_read(sc, emac_base + EMAC_REG_EMAC_LED); 7081 if (params->phy[ELINK_EXT_PHY1].type == 7082 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) 7083 tmp &= ~(EMAC_LED_1000MB_OVERRIDE | 7084 EMAC_LED_100MB_OVERRIDE | 7085 EMAC_LED_10MB_OVERRIDE); 7086 else 7087 tmp |= EMAC_LED_OVERRIDE; 7088 7089 elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_LED, tmp); 7090 break; 7091 7092 case ELINK_LED_MODE_OPER: 7093 /* For all other phys, OPER mode is same as ON, so in case 7094 * link is down, do nothing 7095 */ 7096 if (!vars->link_up) 7097 break; 7098 case ELINK_LED_MODE_ON: 7099 if (((params->phy[ELINK_EXT_PHY1].type == 7100 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) || 7101 (params->phy[ELINK_EXT_PHY1].type == 7102 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722)) && 7103 CHIP_IS_E2(sc) && params->num_phys == 2) { 7104 /* This is a work-around for E2+8727 Configurations */ 7105 if (mode == ELINK_LED_MODE_ON || 7106 speed == ELINK_SPEED_10000){ 7107 REG_WR(sc, NIG_REG_LED_MODE_P0 + port*4, 0); 7108 REG_WR(sc, NIG_REG_LED_10G_P0 + port*4, 1); 7109 7110 tmp = elink_cb_reg_read(sc, emac_base + EMAC_REG_EMAC_LED); 7111 elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_LED, 7112 (tmp | EMAC_LED_OVERRIDE)); 7113 /* Return here without enabling traffic 7114 * LED blink and setting rate in ON mode. 7115 * In oper mode, enabling LED blink 7116 * and setting rate is needed. 7117 */ 7118 if (mode == ELINK_LED_MODE_ON) 7119 return rc; 7120 } 7121 } else if (ELINK_SINGLE_MEDIA_DIRECT(params)) { 7122 /* This is a work-around for HW issue found when link 7123 * is up in CL73 7124 */ 7125 if ((!CHIP_IS_E3(sc)) || 7126 (CHIP_IS_E3(sc) && 7127 mode == ELINK_LED_MODE_ON)) 7128 REG_WR(sc, NIG_REG_LED_10G_P0 + port*4, 1); 7129 7130 if (CHIP_IS_E1x(sc) || 7131 CHIP_IS_E2(sc) || 7132 (mode == ELINK_LED_MODE_ON)) 7133 REG_WR(sc, NIG_REG_LED_MODE_P0 + port*4, 0); 7134 else 7135 REG_WR(sc, NIG_REG_LED_MODE_P0 + port*4, 7136 hw_led_mode); 7137 } else if ((params->phy[ELINK_EXT_PHY1].type == 7138 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) && 7139 (mode == ELINK_LED_MODE_ON)) { 7140 REG_WR(sc, NIG_REG_LED_MODE_P0 + port*4, 0); 7141 tmp = elink_cb_reg_read(sc, emac_base + EMAC_REG_EMAC_LED); 7142 elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_LED, tmp | 7143 EMAC_LED_OVERRIDE | EMAC_LED_1000MB_OVERRIDE); 7144 /* Break here; otherwise, it'll disable the 7145 * intended override. 7146 */ 7147 break; 7148 } else { 7149 uint32_t nig_led_mode = ((params->hw_led_mode << 7150 SHARED_HW_CFG_LED_MODE_SHIFT) == 7151 SHARED_HW_CFG_LED_EXTPHY2) ? 7152 (SHARED_HW_CFG_LED_PHY1 >> 7153 SHARED_HW_CFG_LED_MODE_SHIFT) : hw_led_mode; 7154 REG_WR(sc, NIG_REG_LED_MODE_P0 + port*4, 7155 nig_led_mode); 7156 } 7157 7158 REG_WR(sc, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + port*4, 0); 7159 /* Set blinking rate to ~15.9Hz */ 7160 if (CHIP_IS_E3(sc)) 7161 REG_WR(sc, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4, 7162 LED_BLINK_RATE_VAL_E3); 7163 else 7164 REG_WR(sc, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4, 7165 LED_BLINK_RATE_VAL_E1X_E2); 7166 REG_WR(sc, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 + 7167 port*4, 1); 7168 tmp = elink_cb_reg_read(sc, emac_base + EMAC_REG_EMAC_LED); 7169 elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_LED, 7170 (tmp & (~EMAC_LED_OVERRIDE))); 7171 7172 if (CHIP_IS_E1(sc) && 7173 ((speed == ELINK_SPEED_2500) || 7174 (speed == ELINK_SPEED_1000) || 7175 (speed == ELINK_SPEED_100) || 7176 (speed == ELINK_SPEED_10))) { 7177 /* For speeds less than 10G LED scheme is different */ 7178 REG_WR(sc, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 7179 + port*4, 1); 7180 REG_WR(sc, NIG_REG_LED_CONTROL_TRAFFIC_P0 + 7181 port*4, 0); 7182 REG_WR(sc, NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 + 7183 port*4, 1); 7184 } 7185 break; 7186 7187 default: 7188 rc = ELINK_STATUS_ERROR; 7189 ELINK_DEBUG_P1(sc, "elink_set_led: Invalid led mode %d\n", 7190 mode); 7191 break; 7192 } 7193 return rc; 7194 7195 } 7196 7197 /* This function comes to reflect the actual link state read DIRECTLY from the 7198 * HW 7199 */ 7200 elink_status_t elink_test_link(struct elink_params *params, struct elink_vars *vars, 7201 uint8_t is_serdes) 7202 { 7203 struct bxe_softc *sc = params->sc; 7204 uint16_t gp_status = 0, phy_index = 0; 7205 uint8_t ext_phy_link_up = 0, serdes_phy_type; 7206 struct elink_vars temp_vars; 7207 struct elink_phy *int_phy = ¶ms->phy[ELINK_INT_PHY]; 7208 #ifdef ELINK_INCLUDE_FPGA 7209 if (CHIP_REV_IS_FPGA(sc)) 7210 return ELINK_STATUS_OK; 7211 #endif 7212 #ifdef ELINK_INCLUDE_EMUL 7213 if (CHIP_REV_IS_EMUL(sc)) 7214 return ELINK_STATUS_OK; 7215 #endif 7216 7217 if (CHIP_IS_E3(sc)) { 7218 uint16_t link_up; 7219 if (params->req_line_speed[ELINK_LINK_CONFIG_IDX(ELINK_INT_PHY)] 7220 > ELINK_SPEED_10000) { 7221 /* Check 20G link */ 7222 elink_cl45_read(sc, int_phy, MDIO_WC_DEVAD, 7223 1, &link_up); 7224 elink_cl45_read(sc, int_phy, MDIO_WC_DEVAD, 7225 1, &link_up); 7226 link_up &= (1<<2); 7227 } else { 7228 /* Check 10G link and below*/ 7229 uint8_t lane = elink_get_warpcore_lane(int_phy, params); 7230 elink_cl45_read(sc, int_phy, MDIO_WC_DEVAD, 7231 MDIO_WC_REG_GP2_STATUS_GP_2_1, 7232 &gp_status); 7233 gp_status = ((gp_status >> 8) & 0xf) | 7234 ((gp_status >> 12) & 0xf); 7235 link_up = gp_status & (1 << lane); 7236 } 7237 if (!link_up) 7238 return ELINK_STATUS_NO_LINK; 7239 } else { 7240 CL22_RD_OVER_CL45(sc, int_phy, 7241 MDIO_REG_BANK_GP_STATUS, 7242 MDIO_GP_STATUS_TOP_AN_STATUS1, 7243 &gp_status); 7244 /* Link is up only if both local phy and external phy are up */ 7245 if (!(gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS)) 7246 return ELINK_STATUS_NO_LINK; 7247 } 7248 /* In XGXS loopback mode, do not check external PHY */ 7249 if (params->loopback_mode == ELINK_LOOPBACK_XGXS) 7250 return ELINK_STATUS_OK; 7251 7252 switch (params->num_phys) { 7253 case 1: 7254 /* No external PHY */ 7255 return ELINK_STATUS_OK; 7256 case 2: 7257 ext_phy_link_up = params->phy[ELINK_EXT_PHY1].read_status( 7258 ¶ms->phy[ELINK_EXT_PHY1], 7259 params, &temp_vars); 7260 break; 7261 case 3: /* Dual Media */ 7262 for (phy_index = ELINK_EXT_PHY1; phy_index < params->num_phys; 7263 phy_index++) { 7264 serdes_phy_type = ((params->phy[phy_index].media_type == 7265 ELINK_ETH_PHY_SFPP_10G_FIBER) || 7266 (params->phy[phy_index].media_type == 7267 ELINK_ETH_PHY_SFP_1G_FIBER) || 7268 (params->phy[phy_index].media_type == 7269 ELINK_ETH_PHY_XFP_FIBER) || 7270 (params->phy[phy_index].media_type == 7271 ELINK_ETH_PHY_DA_TWINAX)); 7272 7273 if (is_serdes != serdes_phy_type) 7274 continue; 7275 if (params->phy[phy_index].read_status) { 7276 ext_phy_link_up |= 7277 params->phy[phy_index].read_status( 7278 ¶ms->phy[phy_index], 7279 params, &temp_vars); 7280 } 7281 } 7282 break; 7283 } 7284 if (ext_phy_link_up) 7285 return ELINK_STATUS_OK; 7286 return ELINK_STATUS_NO_LINK; 7287 } 7288 7289 static elink_status_t elink_link_initialize(struct elink_params *params, 7290 struct elink_vars *vars) 7291 { 7292 elink_status_t rc = ELINK_STATUS_OK; 7293 uint8_t phy_index, non_ext_phy; 7294 struct bxe_softc *sc = params->sc; 7295 /* In case of external phy existence, the line speed would be the 7296 * line speed linked up by the external phy. In case it is direct 7297 * only, then the line_speed during initialization will be 7298 * equal to the req_line_speed 7299 */ 7300 vars->line_speed = params->phy[ELINK_INT_PHY].req_line_speed; 7301 7302 /* Initialize the internal phy in case this is a direct board 7303 * (no external phys), or this board has external phy which requires 7304 * to first. 7305 */ 7306 if (!USES_WARPCORE(sc)) 7307 elink_prepare_xgxs(¶ms->phy[ELINK_INT_PHY], params, vars); 7308 /* init ext phy and enable link state int */ 7309 non_ext_phy = (ELINK_SINGLE_MEDIA_DIRECT(params) || 7310 (params->loopback_mode == ELINK_LOOPBACK_XGXS)); 7311 7312 if (non_ext_phy || 7313 (params->phy[ELINK_EXT_PHY1].flags & ELINK_FLAGS_INIT_XGXS_FIRST) || 7314 (params->loopback_mode == ELINK_LOOPBACK_EXT_PHY)) { 7315 struct elink_phy *phy = ¶ms->phy[ELINK_INT_PHY]; 7316 if (vars->line_speed == ELINK_SPEED_AUTO_NEG && 7317 (CHIP_IS_E1x(sc) || 7318 CHIP_IS_E2(sc))) 7319 elink_set_parallel_detection(phy, params); 7320 if (params->phy[ELINK_INT_PHY].config_init) 7321 params->phy[ELINK_INT_PHY].config_init(phy, 7322 params, 7323 vars); 7324 } 7325 7326 /* Re-read this value in case it was changed inside config_init due to 7327 * limitations of optic module 7328 */ 7329 vars->line_speed = params->phy[ELINK_INT_PHY].req_line_speed; 7330 7331 /* Init external phy*/ 7332 if (non_ext_phy) { 7333 if (params->phy[ELINK_INT_PHY].supported & 7334 ELINK_SUPPORTED_FIBRE) 7335 vars->link_status |= LINK_STATUS_SERDES_LINK; 7336 } else { 7337 for (phy_index = ELINK_EXT_PHY1; phy_index < params->num_phys; 7338 phy_index++) { 7339 /* No need to initialize second phy in case of first 7340 * phy only selection. In case of second phy, we do 7341 * need to initialize the first phy, since they are 7342 * connected. 7343 */ 7344 if (params->phy[phy_index].supported & 7345 ELINK_SUPPORTED_FIBRE) 7346 vars->link_status |= LINK_STATUS_SERDES_LINK; 7347 7348 if (phy_index == ELINK_EXT_PHY2 && 7349 (elink_phy_selection(params) == 7350 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY)) { 7351 ELINK_DEBUG_P0(sc, 7352 "Not initializing second phy\n"); 7353 continue; 7354 } 7355 params->phy[phy_index].config_init( 7356 ¶ms->phy[phy_index], 7357 params, vars); 7358 } 7359 } 7360 /* Reset the interrupt indication after phy was initialized */ 7361 elink_bits_dis(sc, NIG_REG_STATUS_INTERRUPT_PORT0 + 7362 params->port*4, 7363 (ELINK_NIG_STATUS_XGXS0_LINK10G | 7364 ELINK_NIG_STATUS_XGXS0_LINK_STATUS | 7365 ELINK_NIG_STATUS_SERDES0_LINK_STATUS | 7366 ELINK_NIG_MASK_MI_INT)); 7367 return rc; 7368 } 7369 7370 static void elink_int_link_reset(struct elink_phy *phy, 7371 struct elink_params *params) 7372 { 7373 /* Reset the SerDes/XGXS */ 7374 REG_WR(params->sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, 7375 (0x1ff << (params->port*16))); 7376 } 7377 7378 static void elink_common_ext_link_reset(struct elink_phy *phy, 7379 struct elink_params *params) 7380 { 7381 struct bxe_softc *sc = params->sc; 7382 uint8_t gpio_port; 7383 /* HW reset */ 7384 if (CHIP_IS_E2(sc)) 7385 gpio_port = SC_PATH(sc); 7386 else 7387 gpio_port = params->port; 7388 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_1, 7389 MISC_REGISTERS_GPIO_OUTPUT_LOW, 7390 gpio_port); 7391 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2, 7392 MISC_REGISTERS_GPIO_OUTPUT_LOW, 7393 gpio_port); 7394 ELINK_DEBUG_P0(sc, "reset external PHY\n"); 7395 } 7396 7397 static elink_status_t elink_update_link_down(struct elink_params *params, 7398 struct elink_vars *vars) 7399 { 7400 struct bxe_softc *sc = params->sc; 7401 uint8_t port = params->port; 7402 7403 ELINK_DEBUG_P1(sc, "Port %x: Link is down\n", port); 7404 elink_set_led(params, vars, ELINK_LED_MODE_OFF, 0); 7405 vars->phy_flags &= ~PHY_PHYSICAL_LINK_FLAG; 7406 /* Indicate no mac active */ 7407 vars->mac_type = ELINK_MAC_TYPE_NONE; 7408 7409 /* Update shared memory */ 7410 vars->link_status &= ~ELINK_LINK_UPDATE_MASK; 7411 vars->line_speed = 0; 7412 elink_update_mng(params, vars->link_status); 7413 7414 /* Activate nig drain */ 7415 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1); 7416 7417 /* Disable emac */ 7418 if (!CHIP_IS_E3(sc)) 7419 REG_WR(sc, NIG_REG_NIG_EMAC0_EN + port*4, 0); 7420 7421 DELAY(1000 * 10); 7422 /* Reset BigMac/Xmac */ 7423 if (CHIP_IS_E1x(sc) || 7424 CHIP_IS_E2(sc)) 7425 elink_set_bmac_rx(sc, params->chip_id, params->port, 0); 7426 7427 if (CHIP_IS_E3(sc)) { 7428 /* Prevent LPI Generation by chip */ 7429 REG_WR(sc, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2), 7430 0); 7431 REG_WR(sc, MISC_REG_CPMU_LP_MASK_ENT_P0 + (params->port << 2), 7432 0); 7433 vars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK | 7434 SHMEM_EEE_ACTIVE_BIT); 7435 7436 elink_update_mng_eee(params, vars->eee_status); 7437 elink_set_xmac_rxtx(params, 0); 7438 elink_set_umac_rxtx(params, 0); 7439 } 7440 7441 return ELINK_STATUS_OK; 7442 } 7443 7444 static elink_status_t elink_update_link_up(struct elink_params *params, 7445 struct elink_vars *vars, 7446 uint8_t link_10g) 7447 { 7448 struct bxe_softc *sc = params->sc; 7449 uint8_t phy_idx, port = params->port; 7450 elink_status_t rc = ELINK_STATUS_OK; 7451 7452 vars->link_status |= (LINK_STATUS_LINK_UP | 7453 LINK_STATUS_PHYSICAL_LINK_FLAG); 7454 vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG; 7455 7456 if (vars->flow_ctrl & ELINK_FLOW_CTRL_TX) 7457 vars->link_status |= 7458 LINK_STATUS_TX_FLOW_CONTROL_ENABLED; 7459 7460 if (vars->flow_ctrl & ELINK_FLOW_CTRL_RX) 7461 vars->link_status |= 7462 LINK_STATUS_RX_FLOW_CONTROL_ENABLED; 7463 if (USES_WARPCORE(sc)) { 7464 if (link_10g) { 7465 if (elink_xmac_enable(params, vars, 0) == 7466 ELINK_STATUS_NO_LINK) { 7467 ELINK_DEBUG_P0(sc, "Found errors on XMAC\n"); 7468 vars->link_up = 0; 7469 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG; 7470 vars->link_status &= ~LINK_STATUS_LINK_UP; 7471 } 7472 } else 7473 elink_umac_enable(params, vars, 0); 7474 elink_set_led(params, vars, 7475 ELINK_LED_MODE_OPER, vars->line_speed); 7476 7477 if ((vars->eee_status & SHMEM_EEE_ACTIVE_BIT) && 7478 (vars->eee_status & SHMEM_EEE_LPI_REQUESTED_BIT)) { 7479 ELINK_DEBUG_P0(sc, "Enabling LPI assertion\n"); 7480 REG_WR(sc, MISC_REG_CPMU_LP_FW_ENABLE_P0 + 7481 (params->port << 2), 1); 7482 REG_WR(sc, MISC_REG_CPMU_LP_DR_ENABLE, 1); 7483 REG_WR(sc, MISC_REG_CPMU_LP_MASK_ENT_P0 + 7484 (params->port << 2), 0xfc20); 7485 } 7486 } 7487 if ((CHIP_IS_E1x(sc) || 7488 CHIP_IS_E2(sc))) { 7489 if (link_10g) { 7490 if (elink_bmac_enable(params, vars, 0, 1) == 7491 ELINK_STATUS_NO_LINK) { 7492 ELINK_DEBUG_P0(sc, "Found errors on BMAC\n"); 7493 vars->link_up = 0; 7494 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG; 7495 vars->link_status &= ~LINK_STATUS_LINK_UP; 7496 } 7497 7498 elink_set_led(params, vars, 7499 ELINK_LED_MODE_OPER, ELINK_SPEED_10000); 7500 } else { 7501 rc = elink_emac_program(params, vars); 7502 elink_emac_enable(params, vars, 0); 7503 7504 /* AN complete? */ 7505 if ((vars->link_status & 7506 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) 7507 && (!(vars->phy_flags & PHY_SGMII_FLAG)) && 7508 ELINK_SINGLE_MEDIA_DIRECT(params)) 7509 elink_set_gmii_tx_driver(params); 7510 } 7511 } 7512 7513 /* PBF - link up */ 7514 if (CHIP_IS_E1x(sc)) 7515 rc |= elink_pbf_update(params, vars->flow_ctrl, 7516 vars->line_speed); 7517 7518 /* Disable drain */ 7519 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0); 7520 7521 /* Update shared memory */ 7522 elink_update_mng(params, vars->link_status); 7523 elink_update_mng_eee(params, vars->eee_status); 7524 /* Check remote fault */ 7525 for (phy_idx = ELINK_INT_PHY; phy_idx < ELINK_MAX_PHYS; phy_idx++) { 7526 if (params->phy[phy_idx].flags & ELINK_FLAGS_TX_ERROR_CHECK) { 7527 elink_check_half_open_conn(params, vars, 0); 7528 break; 7529 } 7530 } 7531 DELAY(1000 * 20); 7532 return rc; 7533 } 7534 /* The elink_link_update function should be called upon link 7535 * interrupt. 7536 * Link is considered up as follows: 7537 * - DIRECT_SINGLE_MEDIA - Only XGXS link (internal link) needs 7538 * to be up 7539 * - SINGLE_MEDIA - The link between the 577xx and the external 7540 * phy (XGXS) need to up as well as the external link of the 7541 * phy (PHY_EXT1) 7542 * - DUAL_MEDIA - The link between the 577xx and the first 7543 * external phy needs to be up, and at least one of the 2 7544 * external phy link must be up. 7545 */ 7546 elink_status_t elink_link_update(struct elink_params *params, struct elink_vars *vars) 7547 { 7548 struct bxe_softc *sc = params->sc; 7549 struct elink_vars phy_vars[ELINK_MAX_PHYS]; 7550 uint8_t port = params->port; 7551 uint8_t link_10g_plus, phy_index; 7552 uint8_t ext_phy_link_up = 0, cur_link_up; 7553 elink_status_t rc = ELINK_STATUS_OK; 7554 uint8_t is_mi_int = 0; 7555 uint16_t ext_phy_line_speed = 0, prev_line_speed = vars->line_speed; 7556 uint8_t active_external_phy = ELINK_INT_PHY; 7557 vars->phy_flags &= ~PHY_HALF_OPEN_CONN_FLAG; 7558 vars->link_status &= ~ELINK_LINK_UPDATE_MASK; 7559 for (phy_index = ELINK_INT_PHY; phy_index < params->num_phys; 7560 phy_index++) { 7561 phy_vars[phy_index].flow_ctrl = 0; 7562 phy_vars[phy_index].link_status = 0; 7563 phy_vars[phy_index].line_speed = 0; 7564 phy_vars[phy_index].duplex = DUPLEX_FULL; 7565 phy_vars[phy_index].phy_link_up = 0; 7566 phy_vars[phy_index].link_up = 0; 7567 phy_vars[phy_index].fault_detected = 0; 7568 /* different consideration, since vars holds inner state */ 7569 phy_vars[phy_index].eee_status = vars->eee_status; 7570 } 7571 7572 if (USES_WARPCORE(sc)) 7573 elink_set_aer_mmd(params, ¶ms->phy[ELINK_INT_PHY]); 7574 7575 ELINK_DEBUG_P3(sc, "port %x, XGXS?%x, int_status 0x%x\n", 7576 port, (vars->phy_flags & PHY_XGXS_FLAG), 7577 REG_RD(sc, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4)); 7578 7579 is_mi_int = (uint8_t)(REG_RD(sc, NIG_REG_EMAC0_STATUS_MISC_MI_INT + 7580 port*0x18) > 0); 7581 ELINK_DEBUG_P3(sc, "int_mask 0x%x MI_INT %x, SERDES_LINK %x\n", 7582 REG_RD(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port*4), 7583 is_mi_int, 7584 REG_RD(sc, NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c)); 7585 7586 ELINK_DEBUG_P2(sc, " 10G %x, XGXS_LINK %x\n", 7587 REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68), 7588 REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68)); 7589 7590 /* Disable emac */ 7591 if (!CHIP_IS_E3(sc)) 7592 REG_WR(sc, NIG_REG_NIG_EMAC0_EN + port*4, 0); 7593 7594 /* Step 1: 7595 * Check external link change only for external phys, and apply 7596 * priority selection between them in case the link on both phys 7597 * is up. Note that instead of the common vars, a temporary 7598 * vars argument is used since each phy may have different link/ 7599 * speed/duplex result 7600 */ 7601 for (phy_index = ELINK_EXT_PHY1; phy_index < params->num_phys; 7602 phy_index++) { 7603 struct elink_phy *phy = ¶ms->phy[phy_index]; 7604 if (!phy->read_status) 7605 continue; 7606 /* Read link status and params of this ext phy */ 7607 cur_link_up = phy->read_status(phy, params, 7608 &phy_vars[phy_index]); 7609 if (cur_link_up) { 7610 ELINK_DEBUG_P1(sc, "phy in index %d link is up\n", 7611 phy_index); 7612 } else { 7613 ELINK_DEBUG_P1(sc, "phy in index %d link is down\n", 7614 phy_index); 7615 continue; 7616 } 7617 7618 if (!ext_phy_link_up) { 7619 ext_phy_link_up = 1; 7620 active_external_phy = phy_index; 7621 } else { 7622 switch (elink_phy_selection(params)) { 7623 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT: 7624 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY: 7625 /* In this option, the first PHY makes sure to pass the 7626 * traffic through itself only. 7627 * Its not clear how to reset the link on the second phy 7628 */ 7629 active_external_phy = ELINK_EXT_PHY1; 7630 break; 7631 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY: 7632 /* In this option, the first PHY makes sure to pass the 7633 * traffic through the second PHY. 7634 */ 7635 active_external_phy = ELINK_EXT_PHY2; 7636 break; 7637 default: 7638 /* Link indication on both PHYs with the following cases 7639 * is invalid: 7640 * - FIRST_PHY means that second phy wasn't initialized, 7641 * hence its link is expected to be down 7642 * - SECOND_PHY means that first phy should not be able 7643 * to link up by itself (using configuration) 7644 * - DEFAULT should be overriden during initialiazation 7645 */ 7646 ELINK_DEBUG_P1(sc, "Invalid link indication" 7647 "mpc=0x%x. DISABLING LINK !!!\n", 7648 params->multi_phy_config); 7649 ext_phy_link_up = 0; 7650 break; 7651 } 7652 } 7653 } 7654 prev_line_speed = vars->line_speed; 7655 /* Step 2: 7656 * Read the status of the internal phy. In case of 7657 * DIRECT_SINGLE_MEDIA board, this link is the external link, 7658 * otherwise this is the link between the 577xx and the first 7659 * external phy 7660 */ 7661 if (params->phy[ELINK_INT_PHY].read_status) 7662 params->phy[ELINK_INT_PHY].read_status( 7663 ¶ms->phy[ELINK_INT_PHY], 7664 params, vars); 7665 /* The INT_PHY flow control reside in the vars. This include the 7666 * case where the speed or flow control are not set to AUTO. 7667 * Otherwise, the active external phy flow control result is set 7668 * to the vars. The ext_phy_line_speed is needed to check if the 7669 * speed is different between the internal phy and external phy. 7670 * This case may be result of intermediate link speed change. 7671 */ 7672 if (active_external_phy > ELINK_INT_PHY) { 7673 vars->flow_ctrl = phy_vars[active_external_phy].flow_ctrl; 7674 /* Link speed is taken from the XGXS. AN and FC result from 7675 * the external phy. 7676 */ 7677 vars->link_status |= phy_vars[active_external_phy].link_status; 7678 7679 /* if active_external_phy is first PHY and link is up - disable 7680 * disable TX on second external PHY 7681 */ 7682 if (active_external_phy == ELINK_EXT_PHY1) { 7683 if (params->phy[ELINK_EXT_PHY2].phy_specific_func) { 7684 ELINK_DEBUG_P0(sc, 7685 "Disabling TX on EXT_PHY2\n"); 7686 params->phy[ELINK_EXT_PHY2].phy_specific_func( 7687 ¶ms->phy[ELINK_EXT_PHY2], 7688 params, ELINK_DISABLE_TX); 7689 } 7690 } 7691 7692 ext_phy_line_speed = phy_vars[active_external_phy].line_speed; 7693 vars->duplex = phy_vars[active_external_phy].duplex; 7694 if (params->phy[active_external_phy].supported & 7695 ELINK_SUPPORTED_FIBRE) 7696 vars->link_status |= LINK_STATUS_SERDES_LINK; 7697 else 7698 vars->link_status &= ~LINK_STATUS_SERDES_LINK; 7699 7700 vars->eee_status = phy_vars[active_external_phy].eee_status; 7701 7702 ELINK_DEBUG_P1(sc, "Active external phy selected: %x\n", 7703 active_external_phy); 7704 } 7705 7706 for (phy_index = ELINK_EXT_PHY1; phy_index < params->num_phys; 7707 phy_index++) { 7708 if (params->phy[phy_index].flags & 7709 ELINK_FLAGS_REARM_LATCH_SIGNAL) { 7710 elink_rearm_latch_signal(sc, port, 7711 phy_index == 7712 active_external_phy); 7713 break; 7714 } 7715 } 7716 ELINK_DEBUG_P3(sc, "vars->flow_ctrl = 0x%x, vars->link_status = 0x%x," 7717 " ext_phy_line_speed = %d\n", vars->flow_ctrl, 7718 vars->link_status, ext_phy_line_speed); 7719 /* Upon link speed change set the NIG into drain mode. Comes to 7720 * deals with possible FIFO glitch due to clk change when speed 7721 * is decreased without link down indicator 7722 */ 7723 7724 if (vars->phy_link_up) { 7725 if (!(ELINK_SINGLE_MEDIA_DIRECT(params)) && ext_phy_link_up && 7726 (ext_phy_line_speed != vars->line_speed)) { 7727 ELINK_DEBUG_P2(sc, "Internal link speed %d is" 7728 " different than the external" 7729 " link speed %d\n", vars->line_speed, 7730 ext_phy_line_speed); 7731 vars->phy_link_up = 0; 7732 } else if (prev_line_speed != vars->line_speed) { 7733 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 7734 0); 7735 DELAY(1000 * 1); 7736 } 7737 } 7738 7739 /* Anything 10 and over uses the bmac */ 7740 link_10g_plus = (vars->line_speed >= ELINK_SPEED_10000); 7741 7742 elink_link_int_ack(params, vars, link_10g_plus); 7743 7744 /* In case external phy link is up, and internal link is down 7745 * (not initialized yet probably after link initialization, it 7746 * needs to be initialized. 7747 * Note that after link down-up as result of cable plug, the xgxs 7748 * link would probably become up again without the need 7749 * initialize it 7750 */ 7751 if (!(ELINK_SINGLE_MEDIA_DIRECT(params))) { 7752 ELINK_DEBUG_P3(sc, "ext_phy_link_up = %d, int_link_up = %d," 7753 " init_preceding = %d\n", ext_phy_link_up, 7754 vars->phy_link_up, 7755 params->phy[ELINK_EXT_PHY1].flags & 7756 ELINK_FLAGS_INIT_XGXS_FIRST); 7757 if (!(params->phy[ELINK_EXT_PHY1].flags & 7758 ELINK_FLAGS_INIT_XGXS_FIRST) 7759 && ext_phy_link_up && !vars->phy_link_up) { 7760 vars->line_speed = ext_phy_line_speed; 7761 if (vars->line_speed < ELINK_SPEED_1000) 7762 vars->phy_flags |= PHY_SGMII_FLAG; 7763 else 7764 vars->phy_flags &= ~PHY_SGMII_FLAG; 7765 7766 if (params->phy[ELINK_INT_PHY].config_init) 7767 params->phy[ELINK_INT_PHY].config_init( 7768 ¶ms->phy[ELINK_INT_PHY], params, 7769 vars); 7770 } 7771 } 7772 /* Link is up only if both local phy and external phy (in case of 7773 * non-direct board) are up and no fault detected on active PHY. 7774 */ 7775 vars->link_up = (vars->phy_link_up && 7776 (ext_phy_link_up || 7777 ELINK_SINGLE_MEDIA_DIRECT(params)) && 7778 (phy_vars[active_external_phy].fault_detected == 0)); 7779 7780 /* Update the PFC configuration in case it was changed */ 7781 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED) 7782 vars->link_status |= LINK_STATUS_PFC_ENABLED; 7783 else 7784 vars->link_status &= ~LINK_STATUS_PFC_ENABLED; 7785 7786 if (vars->link_up) 7787 rc = elink_update_link_up(params, vars, link_10g_plus); 7788 else 7789 rc = elink_update_link_down(params, vars); 7790 7791 /* Update MCP link status was changed */ 7792 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_BC_SUPPORTS_AFEX) 7793 elink_cb_fw_command(sc, DRV_MSG_CODE_LINK_STATUS_CHANGED, 0); 7794 7795 return rc; 7796 } 7797 7798 /*****************************************************************************/ 7799 /* External Phy section */ 7800 /*****************************************************************************/ 7801 void elink_ext_phy_hw_reset(struct bxe_softc *sc, uint8_t port) 7802 { 7803 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_1, 7804 MISC_REGISTERS_GPIO_OUTPUT_LOW, port); 7805 DELAY(1000 * 1); 7806 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_1, 7807 MISC_REGISTERS_GPIO_OUTPUT_HIGH, port); 7808 } 7809 7810 static void elink_save_spirom_version(struct bxe_softc *sc, uint8_t port, 7811 uint32_t spirom_ver, uint32_t ver_addr) 7812 { 7813 ELINK_DEBUG_P3(sc, "FW version 0x%x:0x%x for port %d\n", 7814 (uint16_t)(spirom_ver>>16), (uint16_t)spirom_ver, port); 7815 7816 if (ver_addr) 7817 REG_WR(sc, ver_addr, spirom_ver); 7818 } 7819 7820 static void elink_save_bcm_spirom_ver(struct bxe_softc *sc, 7821 struct elink_phy *phy, 7822 uint8_t port) 7823 { 7824 uint16_t fw_ver1, fw_ver2; 7825 7826 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, 7827 MDIO_PMA_REG_ROM_VER1, &fw_ver1); 7828 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, 7829 MDIO_PMA_REG_ROM_VER2, &fw_ver2); 7830 elink_save_spirom_version(sc, port, (uint32_t)(fw_ver1<<16 | fw_ver2), 7831 phy->ver_addr); 7832 } 7833 7834 static void elink_ext_phy_10G_an_resolve(struct bxe_softc *sc, 7835 struct elink_phy *phy, 7836 struct elink_vars *vars) 7837 { 7838 uint16_t val; 7839 elink_cl45_read(sc, phy, 7840 MDIO_AN_DEVAD, 7841 MDIO_AN_REG_STATUS, &val); 7842 elink_cl45_read(sc, phy, 7843 MDIO_AN_DEVAD, 7844 MDIO_AN_REG_STATUS, &val); 7845 if (val & (1<<5)) 7846 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; 7847 if ((val & (1<<0)) == 0) 7848 vars->link_status |= LINK_STATUS_PARALLEL_DETECTION_USED; 7849 } 7850 7851 /******************************************************************/ 7852 /* common BCM8073/BCM8727 PHY SECTION */ 7853 /******************************************************************/ 7854 static void elink_8073_resolve_fc(struct elink_phy *phy, 7855 struct elink_params *params, 7856 struct elink_vars *vars) 7857 { 7858 struct bxe_softc *sc = params->sc; 7859 if (phy->req_line_speed == ELINK_SPEED_10 || 7860 phy->req_line_speed == ELINK_SPEED_100) { 7861 vars->flow_ctrl = phy->req_flow_ctrl; 7862 return; 7863 } 7864 7865 if (elink_ext_phy_resolve_fc(phy, params, vars) && 7866 (vars->flow_ctrl == ELINK_FLOW_CTRL_NONE)) { 7867 uint16_t pause_result; 7868 uint16_t ld_pause; /* local */ 7869 uint16_t lp_pause; /* link partner */ 7870 elink_cl45_read(sc, phy, 7871 MDIO_AN_DEVAD, 7872 MDIO_AN_REG_CL37_FC_LD, &ld_pause); 7873 7874 elink_cl45_read(sc, phy, 7875 MDIO_AN_DEVAD, 7876 MDIO_AN_REG_CL37_FC_LP, &lp_pause); 7877 pause_result = (ld_pause & 7878 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 5; 7879 pause_result |= (lp_pause & 7880 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 7; 7881 7882 elink_pause_resolve(vars, pause_result); 7883 ELINK_DEBUG_P1(sc, "Ext PHY CL37 pause result 0x%x\n", 7884 pause_result); 7885 } 7886 } 7887 static elink_status_t elink_8073_8727_external_rom_boot(struct bxe_softc *sc, 7888 struct elink_phy *phy, 7889 uint8_t port) 7890 { 7891 uint32_t count = 0; 7892 uint16_t fw_ver1, fw_msgout; 7893 elink_status_t rc = ELINK_STATUS_OK; 7894 7895 /* Boot port from external ROM */ 7896 /* EDC grst */ 7897 elink_cl45_write(sc, phy, 7898 MDIO_PMA_DEVAD, 7899 MDIO_PMA_REG_GEN_CTRL, 7900 0x0001); 7901 7902 /* Ucode reboot and rst */ 7903 elink_cl45_write(sc, phy, 7904 MDIO_PMA_DEVAD, 7905 MDIO_PMA_REG_GEN_CTRL, 7906 0x008c); 7907 7908 elink_cl45_write(sc, phy, 7909 MDIO_PMA_DEVAD, 7910 MDIO_PMA_REG_MISC_CTRL1, 0x0001); 7911 7912 /* Reset internal microprocessor */ 7913 elink_cl45_write(sc, phy, 7914 MDIO_PMA_DEVAD, 7915 MDIO_PMA_REG_GEN_CTRL, 7916 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET); 7917 7918 /* Release srst bit */ 7919 elink_cl45_write(sc, phy, 7920 MDIO_PMA_DEVAD, 7921 MDIO_PMA_REG_GEN_CTRL, 7922 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP); 7923 7924 /* Delay 100ms per the PHY specifications */ 7925 DELAY(1000 * 100); 7926 7927 /* 8073 sometimes taking longer to download */ 7928 do { 7929 count++; 7930 if (count > 300) { 7931 ELINK_DEBUG_P2(sc, 7932 "elink_8073_8727_external_rom_boot port %x:" 7933 "Download failed. fw version = 0x%x\n", 7934 port, fw_ver1); 7935 rc = ELINK_STATUS_ERROR; 7936 break; 7937 } 7938 7939 elink_cl45_read(sc, phy, 7940 MDIO_PMA_DEVAD, 7941 MDIO_PMA_REG_ROM_VER1, &fw_ver1); 7942 elink_cl45_read(sc, phy, 7943 MDIO_PMA_DEVAD, 7944 MDIO_PMA_REG_M8051_MSGOUT_REG, &fw_msgout); 7945 7946 DELAY(1000 * 1); 7947 } while (fw_ver1 == 0 || fw_ver1 == 0x4321 || 7948 ((fw_msgout & 0xff) != 0x03 && (phy->type == 7949 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073))); 7950 7951 /* Clear ser_boot_ctl bit */ 7952 elink_cl45_write(sc, phy, 7953 MDIO_PMA_DEVAD, 7954 MDIO_PMA_REG_MISC_CTRL1, 0x0000); 7955 elink_save_bcm_spirom_ver(sc, phy, port); 7956 7957 ELINK_DEBUG_P2(sc, 7958 "elink_8073_8727_external_rom_boot port %x:" 7959 "Download complete. fw version = 0x%x\n", 7960 port, fw_ver1); 7961 7962 return rc; 7963 } 7964 7965 /******************************************************************/ 7966 /* BCM8073 PHY SECTION */ 7967 /******************************************************************/ 7968 static elink_status_t elink_8073_is_snr_needed(struct bxe_softc *sc, struct elink_phy *phy) 7969 { 7970 /* This is only required for 8073A1, version 102 only */ 7971 uint16_t val; 7972 7973 /* Read 8073 HW revision*/ 7974 elink_cl45_read(sc, phy, 7975 MDIO_PMA_DEVAD, 7976 MDIO_PMA_REG_8073_CHIP_REV, &val); 7977 7978 if (val != 1) { 7979 /* No need to workaround in 8073 A1 */ 7980 return ELINK_STATUS_OK; 7981 } 7982 7983 elink_cl45_read(sc, phy, 7984 MDIO_PMA_DEVAD, 7985 MDIO_PMA_REG_ROM_VER2, &val); 7986 7987 /* SNR should be applied only for version 0x102 */ 7988 if (val != 0x102) 7989 return ELINK_STATUS_OK; 7990 7991 return 1; 7992 } 7993 7994 static elink_status_t elink_8073_xaui_wa(struct bxe_softc *sc, struct elink_phy *phy) 7995 { 7996 uint16_t val, cnt, cnt1 ; 7997 7998 elink_cl45_read(sc, phy, 7999 MDIO_PMA_DEVAD, 8000 MDIO_PMA_REG_8073_CHIP_REV, &val); 8001 8002 if (val > 0) { 8003 /* No need to workaround in 8073 A1 */ 8004 return ELINK_STATUS_OK; 8005 } 8006 /* XAUI workaround in 8073 A0: */ 8007 8008 /* After loading the boot ROM and restarting Autoneg, poll 8009 * Dev1, Reg $C820: 8010 */ 8011 8012 for (cnt = 0; cnt < 1000; cnt++) { 8013 elink_cl45_read(sc, phy, 8014 MDIO_PMA_DEVAD, 8015 MDIO_PMA_REG_8073_SPEED_LINK_STATUS, 8016 &val); 8017 /* If bit [14] = 0 or bit [13] = 0, continue on with 8018 * system initialization (XAUI work-around not required, as 8019 * these bits indicate 2.5G or 1G link up). 8020 */ 8021 if (!(val & (1<<14)) || !(val & (1<<13))) { 8022 ELINK_DEBUG_P0(sc, "XAUI work-around not required\n"); 8023 return ELINK_STATUS_OK; 8024 } else if (!(val & (1<<15))) { 8025 ELINK_DEBUG_P0(sc, "bit 15 went off\n"); 8026 /* If bit 15 is 0, then poll Dev1, Reg $C841 until it's 8027 * MSB (bit15) goes to 1 (indicating that the XAUI 8028 * workaround has completed), then continue on with 8029 * system initialization. 8030 */ 8031 for (cnt1 = 0; cnt1 < 1000; cnt1++) { 8032 elink_cl45_read(sc, phy, 8033 MDIO_PMA_DEVAD, 8034 MDIO_PMA_REG_8073_XAUI_WA, &val); 8035 if (val & (1<<15)) { 8036 ELINK_DEBUG_P0(sc, 8037 "XAUI workaround has completed\n"); 8038 return ELINK_STATUS_OK; 8039 } 8040 DELAY(1000 * 3); 8041 } 8042 break; 8043 } 8044 DELAY(1000 * 3); 8045 } 8046 ELINK_DEBUG_P0(sc, "Warning: XAUI work-around timeout !!!\n"); 8047 return ELINK_STATUS_ERROR; 8048 } 8049 8050 static void elink_807x_force_10G(struct bxe_softc *sc, struct elink_phy *phy) 8051 { 8052 /* Force KR or KX */ 8053 elink_cl45_write(sc, phy, 8054 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040); 8055 elink_cl45_write(sc, phy, 8056 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0x000b); 8057 elink_cl45_write(sc, phy, 8058 MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0000); 8059 elink_cl45_write(sc, phy, 8060 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000); 8061 } 8062 8063 static void elink_8073_set_pause_cl37(struct elink_params *params, 8064 struct elink_phy *phy, 8065 struct elink_vars *vars) 8066 { 8067 uint16_t cl37_val; 8068 struct bxe_softc *sc = params->sc; 8069 elink_cl45_read(sc, phy, 8070 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &cl37_val); 8071 8072 cl37_val &= ~MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH; 8073 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */ 8074 elink_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc); 8075 if ((vars->ieee_fc & 8076 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) == 8077 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) { 8078 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC; 8079 } 8080 if ((vars->ieee_fc & 8081 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) == 8082 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) { 8083 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC; 8084 } 8085 if ((vars->ieee_fc & 8086 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) == 8087 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) { 8088 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH; 8089 } 8090 ELINK_DEBUG_P1(sc, 8091 "Ext phy AN advertize cl37 0x%x\n", cl37_val); 8092 8093 elink_cl45_write(sc, phy, 8094 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, cl37_val); 8095 DELAY(1000 * 500); 8096 } 8097 8098 static void elink_8073_specific_func(struct elink_phy *phy, 8099 struct elink_params *params, 8100 uint32_t action) 8101 { 8102 struct bxe_softc *sc = params->sc; 8103 switch (action) { 8104 case ELINK_PHY_INIT: 8105 /* Enable LASI */ 8106 elink_cl45_write(sc, phy, 8107 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, (1<<2)); 8108 elink_cl45_write(sc, phy, 8109 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x0004); 8110 break; 8111 } 8112 } 8113 8114 static elink_status_t elink_8073_config_init(struct elink_phy *phy, 8115 struct elink_params *params, 8116 struct elink_vars *vars) 8117 { 8118 struct bxe_softc *sc = params->sc; 8119 uint16_t val = 0, tmp1; 8120 uint8_t gpio_port; 8121 ELINK_DEBUG_P0(sc, "Init 8073\n"); 8122 8123 if (CHIP_IS_E2(sc)) 8124 gpio_port = SC_PATH(sc); 8125 else 8126 gpio_port = params->port; 8127 /* Restore normal power mode*/ 8128 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2, 8129 MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port); 8130 8131 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_1, 8132 MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port); 8133 8134 elink_8073_specific_func(phy, params, ELINK_PHY_INIT); 8135 elink_8073_set_pause_cl37(params, phy, vars); 8136 8137 elink_cl45_read(sc, phy, 8138 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1); 8139 8140 elink_cl45_read(sc, phy, 8141 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1); 8142 8143 ELINK_DEBUG_P1(sc, "Before rom RX_ALARM(port1): 0x%x\n", tmp1); 8144 8145 /* Swap polarity if required - Must be done only in non-1G mode */ 8146 if (params->lane_config & PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) { 8147 /* Configure the 8073 to swap _P and _N of the KR lines */ 8148 ELINK_DEBUG_P0(sc, "Swapping polarity for the 8073\n"); 8149 /* 10G Rx/Tx and 1G Tx signal polarity swap */ 8150 elink_cl45_read(sc, phy, 8151 MDIO_PMA_DEVAD, 8152 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL, &val); 8153 elink_cl45_write(sc, phy, 8154 MDIO_PMA_DEVAD, 8155 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL, 8156 (val | (3<<9))); 8157 } 8158 8159 8160 /* Enable CL37 BAM */ 8161 if (REG_RD(sc, params->shmem_base + 8162 offsetof(struct shmem_region, dev_info. 8163 port_hw_config[params->port].default_cfg)) & 8164 PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) { 8165 8166 elink_cl45_read(sc, phy, 8167 MDIO_AN_DEVAD, 8168 MDIO_AN_REG_8073_BAM, &val); 8169 elink_cl45_write(sc, phy, 8170 MDIO_AN_DEVAD, 8171 MDIO_AN_REG_8073_BAM, val | 1); 8172 ELINK_DEBUG_P0(sc, "Enable CL37 BAM on KR\n"); 8173 } 8174 if (params->loopback_mode == ELINK_LOOPBACK_EXT) { 8175 elink_807x_force_10G(sc, phy); 8176 ELINK_DEBUG_P0(sc, "Forced speed 10G on 807X\n"); 8177 return ELINK_STATUS_OK; 8178 } else { 8179 elink_cl45_write(sc, phy, 8180 MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0002); 8181 } 8182 if (phy->req_line_speed != ELINK_SPEED_AUTO_NEG) { 8183 if (phy->req_line_speed == ELINK_SPEED_10000) { 8184 val = (1<<7); 8185 } else if (phy->req_line_speed == ELINK_SPEED_2500) { 8186 val = (1<<5); 8187 /* Note that 2.5G works only when used with 1G 8188 * advertisement 8189 */ 8190 } else 8191 val = (1<<5); 8192 } else { 8193 val = 0; 8194 if (phy->speed_cap_mask & 8195 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) 8196 val |= (1<<7); 8197 8198 /* Note that 2.5G works only when used with 1G advertisement */ 8199 if (phy->speed_cap_mask & 8200 (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G | 8201 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)) 8202 val |= (1<<5); 8203 ELINK_DEBUG_P1(sc, "807x autoneg val = 0x%x\n", val); 8204 } 8205 8206 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, val); 8207 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, &tmp1); 8208 8209 if (((phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) && 8210 (phy->req_line_speed == ELINK_SPEED_AUTO_NEG)) || 8211 (phy->req_line_speed == ELINK_SPEED_2500)) { 8212 uint16_t phy_ver; 8213 /* Allow 2.5G for A1 and above */ 8214 elink_cl45_read(sc, phy, 8215 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV, 8216 &phy_ver); 8217 ELINK_DEBUG_P0(sc, "Add 2.5G\n"); 8218 if (phy_ver > 0) 8219 tmp1 |= 1; 8220 else 8221 tmp1 &= 0xfffe; 8222 } else { 8223 ELINK_DEBUG_P0(sc, "Disable 2.5G\n"); 8224 tmp1 &= 0xfffe; 8225 } 8226 8227 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, tmp1); 8228 /* Add support for CL37 (passive mode) II */ 8229 8230 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &tmp1); 8231 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, 8232 (tmp1 | ((phy->req_duplex == DUPLEX_FULL) ? 8233 0x20 : 0x40))); 8234 8235 /* Add support for CL37 (passive mode) III */ 8236 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000); 8237 8238 /* The SNR will improve about 2db by changing BW and FEE main 8239 * tap. Rest commands are executed after link is up 8240 * Change FFE main cursor to 5 in EDC register 8241 */ 8242 if (elink_8073_is_snr_needed(sc, phy)) 8243 elink_cl45_write(sc, phy, 8244 MDIO_PMA_DEVAD, MDIO_PMA_REG_EDC_FFE_MAIN, 8245 0xFB0C); 8246 8247 /* Enable FEC (Forware Error Correction) Request in the AN */ 8248 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, &tmp1); 8249 tmp1 |= (1<<15); 8250 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, tmp1); 8251 8252 elink_ext_phy_set_pause(params, phy, vars); 8253 8254 /* Restart autoneg */ 8255 DELAY(1000 * 500); 8256 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200); 8257 ELINK_DEBUG_P2(sc, "807x Autoneg Restart: Advertise 1G=%x, 10G=%x\n", 8258 ((val & (1<<5)) > 0), ((val & (1<<7)) > 0)); 8259 return ELINK_STATUS_OK; 8260 } 8261 8262 static uint8_t elink_8073_read_status(struct elink_phy *phy, 8263 struct elink_params *params, 8264 struct elink_vars *vars) 8265 { 8266 struct bxe_softc *sc = params->sc; 8267 uint8_t link_up = 0; 8268 uint16_t val1, val2; 8269 uint16_t link_status = 0; 8270 uint16_t an1000_status = 0; 8271 8272 elink_cl45_read(sc, phy, 8273 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1); 8274 8275 ELINK_DEBUG_P1(sc, "8703 LASI status 0x%x\n", val1); 8276 8277 /* Clear the interrupt LASI status register */ 8278 elink_cl45_read(sc, phy, 8279 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2); 8280 elink_cl45_read(sc, phy, 8281 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val1); 8282 ELINK_DEBUG_P2(sc, "807x PCS status 0x%x->0x%x\n", val2, val1); 8283 /* Clear MSG-OUT */ 8284 elink_cl45_read(sc, phy, 8285 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1); 8286 8287 /* Check the LASI */ 8288 elink_cl45_read(sc, phy, 8289 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2); 8290 8291 ELINK_DEBUG_P1(sc, "KR 0x9003 0x%x\n", val2); 8292 8293 /* Check the link status */ 8294 elink_cl45_read(sc, phy, 8295 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2); 8296 ELINK_DEBUG_P1(sc, "KR PCS status 0x%x\n", val2); 8297 8298 elink_cl45_read(sc, phy, 8299 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2); 8300 elink_cl45_read(sc, phy, 8301 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1); 8302 link_up = ((val1 & 4) == 4); 8303 ELINK_DEBUG_P1(sc, "PMA_REG_STATUS=0x%x\n", val1); 8304 8305 if (link_up && 8306 ((phy->req_line_speed != ELINK_SPEED_10000))) { 8307 if (elink_8073_xaui_wa(sc, phy) != 0) 8308 return 0; 8309 } 8310 elink_cl45_read(sc, phy, 8311 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status); 8312 elink_cl45_read(sc, phy, 8313 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status); 8314 8315 /* Check the link status on 1.1.2 */ 8316 elink_cl45_read(sc, phy, 8317 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2); 8318 elink_cl45_read(sc, phy, 8319 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1); 8320 ELINK_DEBUG_P3(sc, "KR PMA status 0x%x->0x%x," 8321 "an_link_status=0x%x\n", val2, val1, an1000_status); 8322 8323 link_up = (((val1 & 4) == 4) || (an1000_status & (1<<1))); 8324 if (link_up && elink_8073_is_snr_needed(sc, phy)) { 8325 /* The SNR will improve about 2dbby changing the BW and FEE main 8326 * tap. The 1st write to change FFE main tap is set before 8327 * restart AN. Change PLL Bandwidth in EDC register 8328 */ 8329 elink_cl45_write(sc, phy, 8330 MDIO_PMA_DEVAD, MDIO_PMA_REG_PLL_BANDWIDTH, 8331 0x26BC); 8332 8333 /* Change CDR Bandwidth in EDC register */ 8334 elink_cl45_write(sc, phy, 8335 MDIO_PMA_DEVAD, MDIO_PMA_REG_CDR_BANDWIDTH, 8336 0x0333); 8337 } 8338 elink_cl45_read(sc, phy, 8339 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_SPEED_LINK_STATUS, 8340 &link_status); 8341 8342 /* Bits 0..2 --> speed detected, bits 13..15--> link is down */ 8343 if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) { 8344 link_up = 1; 8345 vars->line_speed = ELINK_SPEED_10000; 8346 ELINK_DEBUG_P1(sc, "port %x: External link up in 10G\n", 8347 params->port); 8348 } else if ((link_status & (1<<1)) && (!(link_status & (1<<14)))) { 8349 link_up = 1; 8350 vars->line_speed = ELINK_SPEED_2500; 8351 ELINK_DEBUG_P1(sc, "port %x: External link up in 2.5G\n", 8352 params->port); 8353 } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) { 8354 link_up = 1; 8355 vars->line_speed = ELINK_SPEED_1000; 8356 ELINK_DEBUG_P1(sc, "port %x: External link up in 1G\n", 8357 params->port); 8358 } else { 8359 link_up = 0; 8360 ELINK_DEBUG_P1(sc, "port %x: External link is down\n", 8361 params->port); 8362 } 8363 8364 if (link_up) { 8365 /* Swap polarity if required */ 8366 if (params->lane_config & 8367 PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) { 8368 /* Configure the 8073 to swap P and N of the KR lines */ 8369 elink_cl45_read(sc, phy, 8370 MDIO_XS_DEVAD, 8371 MDIO_XS_REG_8073_RX_CTRL_PCIE, &val1); 8372 /* Set bit 3 to invert Rx in 1G mode and clear this bit 8373 * when it`s in 10G mode. 8374 */ 8375 if (vars->line_speed == ELINK_SPEED_1000) { 8376 ELINK_DEBUG_P0(sc, "Swapping 1G polarity for" 8377 "the 8073\n"); 8378 val1 |= (1<<3); 8379 } else 8380 val1 &= ~(1<<3); 8381 8382 elink_cl45_write(sc, phy, 8383 MDIO_XS_DEVAD, 8384 MDIO_XS_REG_8073_RX_CTRL_PCIE, 8385 val1); 8386 } 8387 elink_ext_phy_10G_an_resolve(sc, phy, vars); 8388 elink_8073_resolve_fc(phy, params, vars); 8389 vars->duplex = DUPLEX_FULL; 8390 } 8391 8392 if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) { 8393 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, 8394 MDIO_AN_REG_LP_AUTO_NEG2, &val1); 8395 8396 if (val1 & (1<<5)) 8397 vars->link_status |= 8398 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE; 8399 if (val1 & (1<<7)) 8400 vars->link_status |= 8401 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; 8402 } 8403 8404 return link_up; 8405 } 8406 8407 static void elink_8073_link_reset(struct elink_phy *phy, 8408 struct elink_params *params) 8409 { 8410 struct bxe_softc *sc = params->sc; 8411 uint8_t gpio_port; 8412 if (CHIP_IS_E2(sc)) 8413 gpio_port = SC_PATH(sc); 8414 else 8415 gpio_port = params->port; 8416 ELINK_DEBUG_P1(sc, "Setting 8073 port %d into low power mode\n", 8417 gpio_port); 8418 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2, 8419 MISC_REGISTERS_GPIO_OUTPUT_LOW, 8420 gpio_port); 8421 } 8422 8423 /******************************************************************/ 8424 /* BCM8705 PHY SECTION */ 8425 /******************************************************************/ 8426 static elink_status_t elink_8705_config_init(struct elink_phy *phy, 8427 struct elink_params *params, 8428 struct elink_vars *vars) 8429 { 8430 struct bxe_softc *sc = params->sc; 8431 ELINK_DEBUG_P0(sc, "init 8705\n"); 8432 /* Restore normal power mode*/ 8433 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2, 8434 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port); 8435 /* HW reset */ 8436 elink_ext_phy_hw_reset(sc, params->port); 8437 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040); 8438 elink_wait_reset_complete(sc, phy, params); 8439 8440 elink_cl45_write(sc, phy, 8441 MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL, 0x8288); 8442 elink_cl45_write(sc, phy, 8443 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 0x7fbf); 8444 elink_cl45_write(sc, phy, 8445 MDIO_PMA_DEVAD, MDIO_PMA_REG_CMU_PLL_BYPASS, 0x0100); 8446 elink_cl45_write(sc, phy, 8447 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_CNTL, 0x1); 8448 /* BCM8705 doesn't have microcode, hence the 0 */ 8449 elink_save_spirom_version(sc, params->port, params->shmem_base, 0); 8450 return ELINK_STATUS_OK; 8451 } 8452 8453 static uint8_t elink_8705_read_status(struct elink_phy *phy, 8454 struct elink_params *params, 8455 struct elink_vars *vars) 8456 { 8457 uint8_t link_up = 0; 8458 uint16_t val1, rx_sd; 8459 struct bxe_softc *sc = params->sc; 8460 ELINK_DEBUG_P0(sc, "read status 8705\n"); 8461 elink_cl45_read(sc, phy, 8462 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1); 8463 ELINK_DEBUG_P1(sc, "8705 LASI status 0x%x\n", val1); 8464 8465 elink_cl45_read(sc, phy, 8466 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1); 8467 ELINK_DEBUG_P1(sc, "8705 LASI status 0x%x\n", val1); 8468 8469 elink_cl45_read(sc, phy, 8470 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd); 8471 8472 elink_cl45_read(sc, phy, 8473 MDIO_PMA_DEVAD, 0xc809, &val1); 8474 elink_cl45_read(sc, phy, 8475 MDIO_PMA_DEVAD, 0xc809, &val1); 8476 8477 ELINK_DEBUG_P1(sc, "8705 1.c809 val=0x%x\n", val1); 8478 link_up = ((rx_sd & 0x1) && (val1 & (1<<9)) && ((val1 & (1<<8)) == 0)); 8479 if (link_up) { 8480 vars->line_speed = ELINK_SPEED_10000; 8481 elink_ext_phy_resolve_fc(phy, params, vars); 8482 } 8483 return link_up; 8484 } 8485 8486 /******************************************************************/ 8487 /* SFP+ module Section */ 8488 /******************************************************************/ 8489 static void elink_set_disable_pmd_transmit(struct elink_params *params, 8490 struct elink_phy *phy, 8491 uint8_t pmd_dis) 8492 { 8493 struct bxe_softc *sc = params->sc; 8494 /* Disable transmitter only for bootcodes which can enable it afterwards 8495 * (for D3 link) 8496 */ 8497 if (pmd_dis) { 8498 if (params->feature_config_flags & 8499 ELINK_FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED) { 8500 ELINK_DEBUG_P0(sc, "Disabling PMD transmitter\n"); 8501 } else { 8502 ELINK_DEBUG_P0(sc, "NOT disabling PMD transmitter\n"); 8503 return; 8504 } 8505 } else 8506 ELINK_DEBUG_P0(sc, "Enabling PMD transmitter\n"); 8507 elink_cl45_write(sc, phy, 8508 MDIO_PMA_DEVAD, 8509 MDIO_PMA_REG_TX_DISABLE, pmd_dis); 8510 } 8511 8512 static uint8_t elink_get_gpio_port(struct elink_params *params) 8513 { 8514 uint8_t gpio_port; 8515 uint32_t swap_val, swap_override; 8516 struct bxe_softc *sc = params->sc; 8517 if (CHIP_IS_E2(sc)) 8518 gpio_port = SC_PATH(sc); 8519 else 8520 gpio_port = params->port; 8521 swap_val = REG_RD(sc, NIG_REG_PORT_SWAP); 8522 swap_override = REG_RD(sc, NIG_REG_STRAP_OVERRIDE); 8523 return gpio_port ^ (swap_val && swap_override); 8524 } 8525 8526 static void elink_sfp_e1e2_set_transmitter(struct elink_params *params, 8527 struct elink_phy *phy, 8528 uint8_t tx_en) 8529 { 8530 uint16_t val; 8531 uint8_t port = params->port; 8532 struct bxe_softc *sc = params->sc; 8533 uint32_t tx_en_mode; 8534 8535 /* Disable/Enable transmitter ( TX laser of the SFP+ module.)*/ 8536 tx_en_mode = REG_RD(sc, params->shmem_base + 8537 offsetof(struct shmem_region, 8538 dev_info.port_hw_config[port].sfp_ctrl)) & 8539 PORT_HW_CFG_TX_LASER_MASK; 8540 ELINK_DEBUG_P3(sc, "Setting transmitter tx_en=%x for port %x " 8541 "mode = %x\n", tx_en, port, tx_en_mode); 8542 switch (tx_en_mode) { 8543 case PORT_HW_CFG_TX_LASER_MDIO: 8544 8545 elink_cl45_read(sc, phy, 8546 MDIO_PMA_DEVAD, 8547 MDIO_PMA_REG_PHY_IDENTIFIER, 8548 &val); 8549 8550 if (tx_en) 8551 val &= ~(1<<15); 8552 else 8553 val |= (1<<15); 8554 8555 elink_cl45_write(sc, phy, 8556 MDIO_PMA_DEVAD, 8557 MDIO_PMA_REG_PHY_IDENTIFIER, 8558 val); 8559 break; 8560 case PORT_HW_CFG_TX_LASER_GPIO0: 8561 case PORT_HW_CFG_TX_LASER_GPIO1: 8562 case PORT_HW_CFG_TX_LASER_GPIO2: 8563 case PORT_HW_CFG_TX_LASER_GPIO3: 8564 { 8565 uint16_t gpio_pin; 8566 uint8_t gpio_port, gpio_mode; 8567 if (tx_en) 8568 gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_HIGH; 8569 else 8570 gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_LOW; 8571 8572 gpio_pin = tx_en_mode - PORT_HW_CFG_TX_LASER_GPIO0; 8573 gpio_port = elink_get_gpio_port(params); 8574 elink_cb_gpio_write(sc, gpio_pin, gpio_mode, gpio_port); 8575 break; 8576 } 8577 default: 8578 ELINK_DEBUG_P1(sc, "Invalid TX_LASER_MDIO 0x%x\n", tx_en_mode); 8579 break; 8580 } 8581 } 8582 8583 static void elink_sfp_set_transmitter(struct elink_params *params, 8584 struct elink_phy *phy, 8585 uint8_t tx_en) 8586 { 8587 struct bxe_softc *sc = params->sc; 8588 ELINK_DEBUG_P1(sc, "Setting SFP+ transmitter to %d\n", tx_en); 8589 if (CHIP_IS_E3(sc)) 8590 elink_sfp_e3_set_transmitter(params, phy, tx_en); 8591 else 8592 elink_sfp_e1e2_set_transmitter(params, phy, tx_en); 8593 } 8594 8595 static elink_status_t elink_8726_read_sfp_module_eeprom(struct elink_phy *phy, 8596 struct elink_params *params, 8597 uint8_t dev_addr, uint16_t addr, uint8_t byte_cnt, 8598 uint8_t *o_buf, uint8_t is_init) 8599 { 8600 struct bxe_softc *sc = params->sc; 8601 uint16_t val = 0; 8602 uint16_t i; 8603 if (byte_cnt > ELINK_SFP_EEPROM_PAGE_SIZE) { 8604 ELINK_DEBUG_P0(sc, 8605 "Reading from eeprom is limited to 0xf\n"); 8606 return ELINK_STATUS_ERROR; 8607 } 8608 /* Set the read command byte count */ 8609 elink_cl45_write(sc, phy, 8610 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT, 8611 (byte_cnt | (dev_addr << 8))); 8612 8613 /* Set the read command address */ 8614 elink_cl45_write(sc, phy, 8615 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR, 8616 addr); 8617 8618 /* Activate read command */ 8619 elink_cl45_write(sc, phy, 8620 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, 8621 0x2c0f); 8622 8623 /* Wait up to 500us for command complete status */ 8624 for (i = 0; i < 100; i++) { 8625 elink_cl45_read(sc, phy, 8626 MDIO_PMA_DEVAD, 8627 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val); 8628 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) == 8629 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) 8630 break; 8631 DELAY(5); 8632 } 8633 8634 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) != 8635 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) { 8636 ELINK_DEBUG_P1(sc, 8637 "Got bad status 0x%x when reading from SFP+ EEPROM\n", 8638 (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK)); 8639 return ELINK_STATUS_ERROR; 8640 } 8641 8642 /* Read the buffer */ 8643 for (i = 0; i < byte_cnt; i++) { 8644 elink_cl45_read(sc, phy, 8645 MDIO_PMA_DEVAD, 8646 MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF + i, &val); 8647 o_buf[i] = (uint8_t)(val & MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK); 8648 } 8649 8650 for (i = 0; i < 100; i++) { 8651 elink_cl45_read(sc, phy, 8652 MDIO_PMA_DEVAD, 8653 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val); 8654 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) == 8655 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE) 8656 return ELINK_STATUS_OK; 8657 DELAY(1000 * 1); 8658 } 8659 return ELINK_STATUS_ERROR; 8660 } 8661 8662 static void elink_warpcore_power_module(struct elink_params *params, 8663 uint8_t power) 8664 { 8665 uint32_t pin_cfg; 8666 struct bxe_softc *sc = params->sc; 8667 8668 pin_cfg = (REG_RD(sc, params->shmem_base + 8669 offsetof(struct shmem_region, 8670 dev_info.port_hw_config[params->port].e3_sfp_ctrl)) & 8671 PORT_HW_CFG_E3_PWR_DIS_MASK) >> 8672 PORT_HW_CFG_E3_PWR_DIS_SHIFT; 8673 8674 if (pin_cfg == PIN_CFG_NA) 8675 return; 8676 ELINK_DEBUG_P2(sc, "Setting SFP+ module power to %d using pin cfg %d\n", 8677 power, pin_cfg); 8678 /* Low ==> corresponding SFP+ module is powered 8679 * high ==> the SFP+ module is powered down 8680 */ 8681 elink_set_cfg_pin(sc, pin_cfg, power ^ 1); 8682 } 8683 static elink_status_t elink_warpcore_read_sfp_module_eeprom(struct elink_phy *phy, 8684 struct elink_params *params, 8685 uint8_t dev_addr, 8686 uint16_t addr, uint8_t byte_cnt, 8687 uint8_t *o_buf, uint8_t is_init) 8688 { 8689 elink_status_t rc = ELINK_STATUS_OK; 8690 uint8_t i, j = 0, cnt = 0; 8691 uint32_t data_array[4]; 8692 uint16_t addr32; 8693 struct bxe_softc *sc = params->sc; 8694 8695 if (byte_cnt > ELINK_SFP_EEPROM_PAGE_SIZE) { 8696 ELINK_DEBUG_P0(sc, 8697 "Reading from eeprom is limited to 16 bytes\n"); 8698 return ELINK_STATUS_ERROR; 8699 } 8700 8701 /* 4 byte aligned address */ 8702 addr32 = addr & (~0x3); 8703 do { 8704 if ((!is_init) && (cnt == I2C_WA_PWR_ITER)) { 8705 elink_warpcore_power_module(params, 0); 8706 /* Note that 100us are not enough here */ 8707 DELAY(1000 * 1); 8708 elink_warpcore_power_module(params, 1); 8709 } 8710 rc = elink_bsc_read(params, sc, dev_addr, addr32, 0, byte_cnt, 8711 data_array); 8712 } while ((rc != ELINK_STATUS_OK) && (++cnt < I2C_WA_RETRY_CNT)); 8713 8714 if (rc == ELINK_STATUS_OK) { 8715 for (i = (addr - addr32); i < byte_cnt + (addr - addr32); i++) { 8716 o_buf[j] = *((uint8_t *)data_array + i); 8717 j++; 8718 } 8719 } 8720 8721 return rc; 8722 } 8723 8724 static elink_status_t elink_8727_read_sfp_module_eeprom(struct elink_phy *phy, 8725 struct elink_params *params, 8726 uint8_t dev_addr, uint16_t addr, uint8_t byte_cnt, 8727 uint8_t *o_buf, uint8_t is_init) 8728 { 8729 struct bxe_softc *sc = params->sc; 8730 uint16_t val, i; 8731 8732 if (byte_cnt > ELINK_SFP_EEPROM_PAGE_SIZE) { 8733 ELINK_DEBUG_P0(sc, 8734 "Reading from eeprom is limited to 0xf\n"); 8735 return ELINK_STATUS_ERROR; 8736 } 8737 8738 /* Set 2-wire transfer rate of SFP+ module EEPROM 8739 * to 100Khz since some DACs(direct attached cables) do 8740 * not work at 400Khz. 8741 */ 8742 elink_cl45_write(sc, phy, 8743 MDIO_PMA_DEVAD, 8744 MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR, 8745 ((dev_addr << 8) | 1)); 8746 8747 /* Need to read from 1.8000 to clear it */ 8748 elink_cl45_read(sc, phy, 8749 MDIO_PMA_DEVAD, 8750 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, 8751 &val); 8752 8753 /* Set the read command byte count */ 8754 elink_cl45_write(sc, phy, 8755 MDIO_PMA_DEVAD, 8756 MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT, 8757 ((byte_cnt < 2) ? 2 : byte_cnt)); 8758 8759 /* Set the read command address */ 8760 elink_cl45_write(sc, phy, 8761 MDIO_PMA_DEVAD, 8762 MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR, 8763 addr); 8764 /* Set the destination address */ 8765 elink_cl45_write(sc, phy, 8766 MDIO_PMA_DEVAD, 8767 0x8004, 8768 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF); 8769 8770 /* Activate read command */ 8771 elink_cl45_write(sc, phy, 8772 MDIO_PMA_DEVAD, 8773 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, 8774 0x8002); 8775 /* Wait appropriate time for two-wire command to finish before 8776 * polling the status register 8777 */ 8778 DELAY(1000 * 1); 8779 8780 /* Wait up to 500us for command complete status */ 8781 for (i = 0; i < 100; i++) { 8782 elink_cl45_read(sc, phy, 8783 MDIO_PMA_DEVAD, 8784 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val); 8785 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) == 8786 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) 8787 break; 8788 DELAY(5); 8789 } 8790 8791 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) != 8792 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) { 8793 ELINK_DEBUG_P1(sc, 8794 "Got bad status 0x%x when reading from SFP+ EEPROM\n", 8795 (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK)); 8796 return ELINK_STATUS_TIMEOUT; 8797 } 8798 8799 /* Read the buffer */ 8800 for (i = 0; i < byte_cnt; i++) { 8801 elink_cl45_read(sc, phy, 8802 MDIO_PMA_DEVAD, 8803 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF + i, &val); 8804 o_buf[i] = (uint8_t)(val & MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK); 8805 } 8806 8807 for (i = 0; i < 100; i++) { 8808 elink_cl45_read(sc, phy, 8809 MDIO_PMA_DEVAD, 8810 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val); 8811 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) == 8812 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE) 8813 return ELINK_STATUS_OK; 8814 DELAY(1000 * 1); 8815 } 8816 8817 return ELINK_STATUS_ERROR; 8818 } 8819 elink_status_t elink_read_sfp_module_eeprom(struct elink_phy *phy, 8820 struct elink_params *params, uint8_t dev_addr, 8821 uint16_t addr, uint16_t byte_cnt, uint8_t *o_buf) 8822 { 8823 elink_status_t rc = 0; 8824 struct bxe_softc *sc = params->sc; 8825 uint8_t xfer_size; 8826 uint8_t *user_data = o_buf; 8827 read_sfp_module_eeprom_func_p read_func; 8828 if ((dev_addr != 0xa0) && (dev_addr != 0xa2)) { 8829 ELINK_DEBUG_P1(sc, "invalid dev_addr 0x%x\n", dev_addr); 8830 return ELINK_STATUS_ERROR; 8831 } 8832 8833 switch (phy->type) { 8834 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726: 8835 read_func = elink_8726_read_sfp_module_eeprom; 8836 break; 8837 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: 8838 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722: 8839 read_func = elink_8727_read_sfp_module_eeprom; 8840 break; 8841 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT: 8842 read_func = elink_warpcore_read_sfp_module_eeprom; 8843 break; 8844 default: 8845 return ELINK_OP_NOT_SUPPORTED; 8846 } 8847 8848 while (!rc && (byte_cnt > 0)) { 8849 xfer_size = (byte_cnt > ELINK_SFP_EEPROM_PAGE_SIZE) ? 8850 ELINK_SFP_EEPROM_PAGE_SIZE : byte_cnt; 8851 rc = read_func(phy, params, dev_addr, addr, xfer_size, 8852 user_data, 0); 8853 byte_cnt -= xfer_size; 8854 user_data += xfer_size; 8855 addr += xfer_size; 8856 } 8857 return rc; 8858 } 8859 8860 static elink_status_t elink_get_edc_mode(struct elink_phy *phy, 8861 struct elink_params *params, 8862 uint16_t *edc_mode) 8863 { 8864 struct bxe_softc *sc = params->sc; 8865 uint32_t sync_offset = 0, phy_idx, media_types; 8866 uint8_t gport, val[2], check_limiting_mode = 0; 8867 *edc_mode = ELINK_EDC_MODE_LIMITING; 8868 phy->media_type = ELINK_ETH_PHY_UNSPECIFIED; 8869 /* First check for copper cable */ 8870 if (elink_read_sfp_module_eeprom(phy, 8871 params, 8872 ELINK_I2C_DEV_ADDR_A0, 8873 ELINK_SFP_EEPROM_CON_TYPE_ADDR, 8874 2, 8875 (uint8_t *)val) != 0) { 8876 ELINK_DEBUG_P0(sc, "Failed to read from SFP+ module EEPROM\n"); 8877 return ELINK_STATUS_ERROR; 8878 } 8879 8880 switch (val[0]) { 8881 case ELINK_SFP_EEPROM_CON_TYPE_VAL_COPPER: 8882 { 8883 uint8_t copper_module_type; 8884 phy->media_type = ELINK_ETH_PHY_DA_TWINAX; 8885 /* Check if its active cable (includes SFP+ module) 8886 * of passive cable 8887 */ 8888 if (elink_read_sfp_module_eeprom(phy, 8889 params, 8890 ELINK_I2C_DEV_ADDR_A0, 8891 ELINK_SFP_EEPROM_FC_TX_TECH_ADDR, 8892 1, 8893 &copper_module_type) != 0) { 8894 ELINK_DEBUG_P0(sc, 8895 "Failed to read copper-cable-type" 8896 " from SFP+ EEPROM\n"); 8897 return ELINK_STATUS_ERROR; 8898 } 8899 8900 if (copper_module_type & 8901 ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) { 8902 ELINK_DEBUG_P0(sc, "Active Copper cable detected\n"); 8903 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) 8904 *edc_mode = ELINK_EDC_MODE_ACTIVE_DAC; 8905 else 8906 check_limiting_mode = 1; 8907 } else if (copper_module_type & 8908 ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE) { 8909 ELINK_DEBUG_P0(sc, 8910 "Passive Copper cable detected\n"); 8911 *edc_mode = 8912 ELINK_EDC_MODE_PASSIVE_DAC; 8913 } else { 8914 ELINK_DEBUG_P1(sc, 8915 "Unknown copper-cable-type 0x%x !!!\n", 8916 copper_module_type); 8917 return ELINK_STATUS_ERROR; 8918 } 8919 break; 8920 } 8921 case ELINK_SFP_EEPROM_CON_TYPE_VAL_LC: 8922 case ELINK_SFP_EEPROM_CON_TYPE_VAL_RJ45: 8923 check_limiting_mode = 1; 8924 if ((val[1] & (ELINK_SFP_EEPROM_COMP_CODE_SR_MASK | 8925 ELINK_SFP_EEPROM_COMP_CODE_LR_MASK | 8926 ELINK_SFP_EEPROM_COMP_CODE_LRM_MASK)) == 0) { 8927 ELINK_DEBUG_P0(sc, "1G SFP module detected\n"); 8928 gport = params->port; 8929 phy->media_type = ELINK_ETH_PHY_SFP_1G_FIBER; 8930 if (phy->req_line_speed != ELINK_SPEED_1000) { 8931 phy->req_line_speed = ELINK_SPEED_1000; 8932 if (!CHIP_IS_E1x(sc)) { 8933 gport = SC_PATH(sc) + 8934 (params->port << 1); 8935 } 8936 elink_cb_event_log(sc, ELINK_LOG_ID_NON_10G_MODULE, gport); //"Warning: Link speed was forced to 1000Mbps." 8937 // " Current SFP module in port %d is not" 8938 // " compliant with 10G Ethernet\n", 8939 8940 } 8941 } else { 8942 int idx, cfg_idx = 0; 8943 ELINK_DEBUG_P0(sc, "10G Optic module detected\n"); 8944 for (idx = ELINK_INT_PHY; idx < ELINK_MAX_PHYS; idx++) { 8945 if (params->phy[idx].type == phy->type) { 8946 cfg_idx = ELINK_LINK_CONFIG_IDX(idx); 8947 break; 8948 } 8949 } 8950 phy->media_type = ELINK_ETH_PHY_SFPP_10G_FIBER; 8951 phy->req_line_speed = params->req_line_speed[cfg_idx]; 8952 } 8953 break; 8954 default: 8955 ELINK_DEBUG_P1(sc, "Unable to determine module type 0x%x !!!\n", 8956 val[0]); 8957 return ELINK_STATUS_ERROR; 8958 } 8959 sync_offset = params->shmem_base + 8960 offsetof(struct shmem_region, 8961 dev_info.port_hw_config[params->port].media_type); 8962 media_types = REG_RD(sc, sync_offset); 8963 /* Update media type for non-PMF sync */ 8964 for (phy_idx = ELINK_INT_PHY; phy_idx < ELINK_MAX_PHYS; phy_idx++) { 8965 if (&(params->phy[phy_idx]) == phy) { 8966 media_types &= ~(PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK << 8967 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx)); 8968 media_types |= ((phy->media_type & 8969 PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) << 8970 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx)); 8971 break; 8972 } 8973 } 8974 REG_WR(sc, sync_offset, media_types); 8975 if (check_limiting_mode) { 8976 uint8_t options[ELINK_SFP_EEPROM_OPTIONS_SIZE]; 8977 if (elink_read_sfp_module_eeprom(phy, 8978 params, 8979 ELINK_I2C_DEV_ADDR_A0, 8980 ELINK_SFP_EEPROM_OPTIONS_ADDR, 8981 ELINK_SFP_EEPROM_OPTIONS_SIZE, 8982 options) != 0) { 8983 ELINK_DEBUG_P0(sc, 8984 "Failed to read Option field from module EEPROM\n"); 8985 return ELINK_STATUS_ERROR; 8986 } 8987 if ((options[0] & ELINK_SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK)) 8988 *edc_mode = ELINK_EDC_MODE_LINEAR; 8989 else 8990 *edc_mode = ELINK_EDC_MODE_LIMITING; 8991 } 8992 ELINK_DEBUG_P1(sc, "EDC mode is set to 0x%x\n", *edc_mode); 8993 return ELINK_STATUS_OK; 8994 } 8995 /* This function read the relevant field from the module (SFP+), and verify it 8996 * is compliant with this board 8997 */ 8998 static elink_status_t elink_verify_sfp_module(struct elink_phy *phy, 8999 struct elink_params *params) 9000 { 9001 struct bxe_softc *sc = params->sc; 9002 uint32_t val, cmd; 9003 uint32_t fw_resp, fw_cmd_param; 9004 char vendor_name[ELINK_SFP_EEPROM_VENDOR_NAME_SIZE+1]; 9005 char vendor_pn[ELINK_SFP_EEPROM_PART_NO_SIZE+1]; 9006 phy->flags &= ~ELINK_FLAGS_SFP_NOT_APPROVED; 9007 val = REG_RD(sc, params->shmem_base + 9008 offsetof(struct shmem_region, dev_info. 9009 port_feature_config[params->port].config)); 9010 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) == 9011 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT) { 9012 ELINK_DEBUG_P0(sc, "NOT enforcing module verification\n"); 9013 return ELINK_STATUS_OK; 9014 } 9015 9016 if (params->feature_config_flags & 9017 ELINK_FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY) { 9018 /* Use specific phy request */ 9019 cmd = DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL; 9020 } else if (params->feature_config_flags & 9021 ELINK_FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY) { 9022 /* Use first phy request only in case of non-dual media*/ 9023 if (ELINK_DUAL_MEDIA(params)) { 9024 ELINK_DEBUG_P0(sc, 9025 "FW does not support OPT MDL verification\n"); 9026 return ELINK_STATUS_ERROR; 9027 } 9028 cmd = DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL; 9029 } else { 9030 /* No support in OPT MDL detection */ 9031 ELINK_DEBUG_P0(sc, 9032 "FW does not support OPT MDL verification\n"); 9033 return ELINK_STATUS_ERROR; 9034 } 9035 9036 fw_cmd_param = ELINK_FW_PARAM_SET(phy->addr, phy->type, phy->mdio_ctrl); 9037 fw_resp = elink_cb_fw_command(sc, cmd, fw_cmd_param); 9038 if (fw_resp == FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS) { 9039 ELINK_DEBUG_P0(sc, "Approved module\n"); 9040 return ELINK_STATUS_OK; 9041 } 9042 9043 /* Format the warning message */ 9044 if (elink_read_sfp_module_eeprom(phy, 9045 params, 9046 ELINK_I2C_DEV_ADDR_A0, 9047 ELINK_SFP_EEPROM_VENDOR_NAME_ADDR, 9048 ELINK_SFP_EEPROM_VENDOR_NAME_SIZE, 9049 (uint8_t *)vendor_name)) 9050 vendor_name[0] = '\0'; 9051 else 9052 vendor_name[ELINK_SFP_EEPROM_VENDOR_NAME_SIZE] = '\0'; 9053 if (elink_read_sfp_module_eeprom(phy, 9054 params, 9055 ELINK_I2C_DEV_ADDR_A0, 9056 ELINK_SFP_EEPROM_PART_NO_ADDR, 9057 ELINK_SFP_EEPROM_PART_NO_SIZE, 9058 (uint8_t *)vendor_pn)) 9059 vendor_pn[0] = '\0'; 9060 else 9061 vendor_pn[ELINK_SFP_EEPROM_PART_NO_SIZE] = '\0'; 9062 9063 elink_cb_event_log(sc, ELINK_LOG_ID_UNQUAL_IO_MODULE, params->port, vendor_name, vendor_pn); // "Warning: Unqualified SFP+ module detected," 9064 // " Port %d from %s part number %s\n", 9065 9066 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) != 9067 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG) 9068 phy->flags |= ELINK_FLAGS_SFP_NOT_APPROVED; 9069 return ELINK_STATUS_ERROR; 9070 } 9071 9072 static elink_status_t elink_wait_for_sfp_module_initialized(struct elink_phy *phy, 9073 struct elink_params *params) 9074 9075 { 9076 uint8_t val; 9077 elink_status_t rc; 9078 struct bxe_softc *sc = params->sc; 9079 uint16_t timeout; 9080 /* Initialization time after hot-plug may take up to 300ms for 9081 * some phys type ( e.g. JDSU ) 9082 */ 9083 9084 for (timeout = 0; timeout < 60; timeout++) { 9085 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) 9086 rc = elink_warpcore_read_sfp_module_eeprom( 9087 phy, params, ELINK_I2C_DEV_ADDR_A0, 1, 1, &val, 9088 1); 9089 else 9090 rc = elink_read_sfp_module_eeprom(phy, params, 9091 ELINK_I2C_DEV_ADDR_A0, 9092 1, 1, &val); 9093 if (rc == 0) { 9094 ELINK_DEBUG_P1(sc, 9095 "SFP+ module initialization took %d ms\n", 9096 timeout * 5); 9097 return ELINK_STATUS_OK; 9098 } 9099 DELAY(1000 * 5); 9100 } 9101 rc = elink_read_sfp_module_eeprom(phy, params, ELINK_I2C_DEV_ADDR_A0, 9102 1, 1, &val); 9103 return rc; 9104 } 9105 9106 static void elink_8727_power_module(struct bxe_softc *sc, 9107 struct elink_phy *phy, 9108 uint8_t is_power_up) { 9109 /* Make sure GPIOs are not using for LED mode */ 9110 uint16_t val; 9111 /* In the GPIO register, bit 4 is use to determine if the GPIOs are 9112 * operating as INPUT or as OUTPUT. Bit 1 is for input, and 0 for 9113 * output 9114 * Bits 0-1 determine the GPIOs value for OUTPUT in case bit 4 val is 0 9115 * Bits 8-9 determine the GPIOs value for INPUT in case bit 4 val is 1 9116 * where the 1st bit is the over-current(only input), and 2nd bit is 9117 * for power( only output ) 9118 * 9119 * In case of NOC feature is disabled and power is up, set GPIO control 9120 * as input to enable listening of over-current indication 9121 */ 9122 if (phy->flags & ELINK_FLAGS_NOC) 9123 return; 9124 if (is_power_up) 9125 val = (1<<4); 9126 else 9127 /* Set GPIO control to OUTPUT, and set the power bit 9128 * to according to the is_power_up 9129 */ 9130 val = (1<<1); 9131 9132 elink_cl45_write(sc, phy, 9133 MDIO_PMA_DEVAD, 9134 MDIO_PMA_REG_8727_GPIO_CTRL, 9135 val); 9136 } 9137 9138 static elink_status_t elink_8726_set_limiting_mode(struct bxe_softc *sc, 9139 struct elink_phy *phy, 9140 uint16_t edc_mode) 9141 { 9142 uint16_t cur_limiting_mode; 9143 9144 elink_cl45_read(sc, phy, 9145 MDIO_PMA_DEVAD, 9146 MDIO_PMA_REG_ROM_VER2, 9147 &cur_limiting_mode); 9148 ELINK_DEBUG_P1(sc, "Current Limiting mode is 0x%x\n", 9149 cur_limiting_mode); 9150 9151 if (edc_mode == ELINK_EDC_MODE_LIMITING) { 9152 ELINK_DEBUG_P0(sc, "Setting LIMITING MODE\n"); 9153 elink_cl45_write(sc, phy, 9154 MDIO_PMA_DEVAD, 9155 MDIO_PMA_REG_ROM_VER2, 9156 ELINK_EDC_MODE_LIMITING); 9157 } else { /* LRM mode ( default )*/ 9158 9159 ELINK_DEBUG_P0(sc, "Setting LRM MODE\n"); 9160 9161 /* Changing to LRM mode takes quite few seconds. So do it only 9162 * if current mode is limiting (default is LRM) 9163 */ 9164 if (cur_limiting_mode != ELINK_EDC_MODE_LIMITING) 9165 return ELINK_STATUS_OK; 9166 9167 elink_cl45_write(sc, phy, 9168 MDIO_PMA_DEVAD, 9169 MDIO_PMA_REG_LRM_MODE, 9170 0); 9171 elink_cl45_write(sc, phy, 9172 MDIO_PMA_DEVAD, 9173 MDIO_PMA_REG_ROM_VER2, 9174 0x128); 9175 elink_cl45_write(sc, phy, 9176 MDIO_PMA_DEVAD, 9177 MDIO_PMA_REG_MISC_CTRL0, 9178 0x4008); 9179 elink_cl45_write(sc, phy, 9180 MDIO_PMA_DEVAD, 9181 MDIO_PMA_REG_LRM_MODE, 9182 0xaaaa); 9183 } 9184 return ELINK_STATUS_OK; 9185 } 9186 9187 static elink_status_t elink_8727_set_limiting_mode(struct bxe_softc *sc, 9188 struct elink_phy *phy, 9189 uint16_t edc_mode) 9190 { 9191 uint16_t phy_identifier; 9192 uint16_t rom_ver2_val; 9193 elink_cl45_read(sc, phy, 9194 MDIO_PMA_DEVAD, 9195 MDIO_PMA_REG_PHY_IDENTIFIER, 9196 &phy_identifier); 9197 9198 elink_cl45_write(sc, phy, 9199 MDIO_PMA_DEVAD, 9200 MDIO_PMA_REG_PHY_IDENTIFIER, 9201 (phy_identifier & ~(1<<9))); 9202 9203 elink_cl45_read(sc, phy, 9204 MDIO_PMA_DEVAD, 9205 MDIO_PMA_REG_ROM_VER2, 9206 &rom_ver2_val); 9207 /* Keep the MSB 8-bits, and set the LSB 8-bits with the edc_mode */ 9208 elink_cl45_write(sc, phy, 9209 MDIO_PMA_DEVAD, 9210 MDIO_PMA_REG_ROM_VER2, 9211 (rom_ver2_val & 0xff00) | (edc_mode & 0x00ff)); 9212 9213 elink_cl45_write(sc, phy, 9214 MDIO_PMA_DEVAD, 9215 MDIO_PMA_REG_PHY_IDENTIFIER, 9216 (phy_identifier | (1<<9))); 9217 9218 return ELINK_STATUS_OK; 9219 } 9220 9221 static void elink_8727_specific_func(struct elink_phy *phy, 9222 struct elink_params *params, 9223 uint32_t action) 9224 { 9225 struct bxe_softc *sc = params->sc; 9226 uint16_t val; 9227 switch (action) { 9228 case ELINK_DISABLE_TX: 9229 elink_sfp_set_transmitter(params, phy, 0); 9230 break; 9231 case ELINK_ENABLE_TX: 9232 if (!(phy->flags & ELINK_FLAGS_SFP_NOT_APPROVED)) 9233 elink_sfp_set_transmitter(params, phy, 1); 9234 break; 9235 case ELINK_PHY_INIT: 9236 elink_cl45_write(sc, phy, 9237 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, 9238 (1<<2) | (1<<5)); 9239 elink_cl45_write(sc, phy, 9240 MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL, 9241 0); 9242 elink_cl45_write(sc, phy, 9243 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x0006); 9244 /* Make MOD_ABS give interrupt on change */ 9245 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, 9246 MDIO_PMA_REG_8727_PCS_OPT_CTRL, 9247 &val); 9248 val |= (1<<12); 9249 if (phy->flags & ELINK_FLAGS_NOC) 9250 val |= (3<<5); 9251 /* Set 8727 GPIOs to input to allow reading from the 8727 GPIO0 9252 * status which reflect SFP+ module over-current 9253 */ 9254 if (!(phy->flags & ELINK_FLAGS_NOC)) 9255 val &= 0xff8f; /* Reset bits 4-6 */ 9256 elink_cl45_write(sc, phy, 9257 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL, 9258 val); 9259 break; 9260 default: 9261 ELINK_DEBUG_P1(sc, "Function 0x%x not supported by 8727\n", 9262 action); 9263 return; 9264 } 9265 } 9266 9267 static void elink_set_e1e2_module_fault_led(struct elink_params *params, 9268 uint8_t gpio_mode) 9269 { 9270 struct bxe_softc *sc = params->sc; 9271 9272 uint32_t fault_led_gpio = REG_RD(sc, params->shmem_base + 9273 offsetof(struct shmem_region, 9274 dev_info.port_hw_config[params->port].sfp_ctrl)) & 9275 PORT_HW_CFG_FAULT_MODULE_LED_MASK; 9276 switch (fault_led_gpio) { 9277 case PORT_HW_CFG_FAULT_MODULE_LED_DISABLED: 9278 return; 9279 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO0: 9280 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO1: 9281 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO2: 9282 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO3: 9283 { 9284 uint8_t gpio_port = elink_get_gpio_port(params); 9285 uint16_t gpio_pin = fault_led_gpio - 9286 PORT_HW_CFG_FAULT_MODULE_LED_GPIO0; 9287 ELINK_DEBUG_P3(sc, "Set fault module-detected led " 9288 "pin %x port %x mode %x\n", 9289 gpio_pin, gpio_port, gpio_mode); 9290 elink_cb_gpio_write(sc, gpio_pin, gpio_mode, gpio_port); 9291 } 9292 break; 9293 default: 9294 ELINK_DEBUG_P1(sc, "Error: Invalid fault led mode 0x%x\n", 9295 fault_led_gpio); 9296 } 9297 } 9298 9299 static void elink_set_e3_module_fault_led(struct elink_params *params, 9300 uint8_t gpio_mode) 9301 { 9302 uint32_t pin_cfg; 9303 uint8_t port = params->port; 9304 struct bxe_softc *sc = params->sc; 9305 pin_cfg = (REG_RD(sc, params->shmem_base + 9306 offsetof(struct shmem_region, 9307 dev_info.port_hw_config[port].e3_sfp_ctrl)) & 9308 PORT_HW_CFG_E3_FAULT_MDL_LED_MASK) >> 9309 PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT; 9310 ELINK_DEBUG_P2(sc, "Setting Fault LED to %d using pin cfg %d\n", 9311 gpio_mode, pin_cfg); 9312 elink_set_cfg_pin(sc, pin_cfg, gpio_mode); 9313 } 9314 9315 static void elink_set_sfp_module_fault_led(struct elink_params *params, 9316 uint8_t gpio_mode) 9317 { 9318 struct bxe_softc *sc = params->sc; 9319 ELINK_DEBUG_P1(sc, "Setting SFP+ module fault LED to %d\n", gpio_mode); 9320 if (CHIP_IS_E3(sc)) { 9321 /* Low ==> if SFP+ module is supported otherwise 9322 * High ==> if SFP+ module is not on the approved vendor list 9323 */ 9324 elink_set_e3_module_fault_led(params, gpio_mode); 9325 } else 9326 elink_set_e1e2_module_fault_led(params, gpio_mode); 9327 } 9328 9329 static void elink_warpcore_hw_reset(struct elink_phy *phy, 9330 struct elink_params *params) 9331 { 9332 struct bxe_softc *sc = params->sc; 9333 elink_warpcore_power_module(params, 0); 9334 /* Put Warpcore in low power mode */ 9335 REG_WR(sc, MISC_REG_WC0_RESET, 0x0c0e); 9336 9337 /* Put LCPLL in low power mode */ 9338 REG_WR(sc, MISC_REG_LCPLL_E40_PWRDWN, 1); 9339 REG_WR(sc, MISC_REG_LCPLL_E40_RESETB_ANA, 0); 9340 REG_WR(sc, MISC_REG_LCPLL_E40_RESETB_DIG, 0); 9341 } 9342 9343 static void elink_power_sfp_module(struct elink_params *params, 9344 struct elink_phy *phy, 9345 uint8_t power) 9346 { 9347 struct bxe_softc *sc = params->sc; 9348 ELINK_DEBUG_P1(sc, "Setting SFP+ power to %x\n", power); 9349 9350 switch (phy->type) { 9351 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: 9352 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722: 9353 elink_8727_power_module(params->sc, phy, power); 9354 break; 9355 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT: 9356 elink_warpcore_power_module(params, power); 9357 break; 9358 default: 9359 break; 9360 } 9361 } 9362 static void elink_warpcore_set_limiting_mode(struct elink_params *params, 9363 struct elink_phy *phy, 9364 uint16_t edc_mode) 9365 { 9366 uint16_t val = 0; 9367 uint16_t mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT; 9368 struct bxe_softc *sc = params->sc; 9369 9370 uint8_t lane = elink_get_warpcore_lane(phy, params); 9371 /* This is a global register which controls all lanes */ 9372 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, 9373 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val); 9374 val &= ~(0xf << (lane << 2)); 9375 9376 switch (edc_mode) { 9377 case ELINK_EDC_MODE_LINEAR: 9378 case ELINK_EDC_MODE_LIMITING: 9379 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT; 9380 break; 9381 case ELINK_EDC_MODE_PASSIVE_DAC: 9382 case ELINK_EDC_MODE_ACTIVE_DAC: 9383 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC; 9384 break; 9385 default: 9386 break; 9387 } 9388 9389 val |= (mode << (lane << 2)); 9390 elink_cl45_write(sc, phy, MDIO_WC_DEVAD, 9391 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, val); 9392 /* A must read */ 9393 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, 9394 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val); 9395 9396 /* Restart microcode to re-read the new mode */ 9397 elink_warpcore_reset_lane(sc, phy, 1); 9398 elink_warpcore_reset_lane(sc, phy, 0); 9399 9400 } 9401 9402 static void elink_set_limiting_mode(struct elink_params *params, 9403 struct elink_phy *phy, 9404 uint16_t edc_mode) 9405 { 9406 switch (phy->type) { 9407 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726: 9408 elink_8726_set_limiting_mode(params->sc, phy, edc_mode); 9409 break; 9410 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: 9411 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722: 9412 elink_8727_set_limiting_mode(params->sc, phy, edc_mode); 9413 break; 9414 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT: 9415 elink_warpcore_set_limiting_mode(params, phy, edc_mode); 9416 break; 9417 } 9418 } 9419 9420 elink_status_t elink_sfp_module_detection(struct elink_phy *phy, 9421 struct elink_params *params) 9422 { 9423 struct bxe_softc *sc = params->sc; 9424 uint16_t edc_mode; 9425 elink_status_t rc = ELINK_STATUS_OK; 9426 9427 uint32_t val = REG_RD(sc, params->shmem_base + 9428 offsetof(struct shmem_region, dev_info. 9429 port_feature_config[params->port].config)); 9430 /* Enabled transmitter by default */ 9431 elink_sfp_set_transmitter(params, phy, 1); 9432 ELINK_DEBUG_P1(sc, "SFP+ module plugged in/out detected on port %d\n", 9433 params->port); 9434 /* Power up module */ 9435 elink_power_sfp_module(params, phy, 1); 9436 if (elink_get_edc_mode(phy, params, &edc_mode) != 0) { 9437 ELINK_DEBUG_P0(sc, "Failed to get valid module type\n"); 9438 return ELINK_STATUS_ERROR; 9439 } else if (elink_verify_sfp_module(phy, params) != 0) { 9440 /* Check SFP+ module compatibility */ 9441 ELINK_DEBUG_P0(sc, "Module verification failed!!\n"); 9442 rc = ELINK_STATUS_ERROR; 9443 /* Turn on fault module-detected led */ 9444 elink_set_sfp_module_fault_led(params, 9445 MISC_REGISTERS_GPIO_HIGH); 9446 9447 /* Check if need to power down the SFP+ module */ 9448 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) == 9449 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN) { 9450 ELINK_DEBUG_P0(sc, "Shutdown SFP+ module!!\n"); 9451 elink_power_sfp_module(params, phy, 0); 9452 return rc; 9453 } 9454 } else { 9455 /* Turn off fault module-detected led */ 9456 elink_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_LOW); 9457 } 9458 9459 /* Check and set limiting mode / LRM mode on 8726. On 8727 it 9460 * is done automatically 9461 */ 9462 elink_set_limiting_mode(params, phy, edc_mode); 9463 9464 /* Disable transmit for this module if the module is not approved, and 9465 * laser needs to be disabled. 9466 */ 9467 if ((rc != 0) && 9468 ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) == 9469 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)) 9470 elink_sfp_set_transmitter(params, phy, 0); 9471 9472 return rc; 9473 } 9474 9475 void elink_handle_module_detect_int(struct elink_params *params) 9476 { 9477 struct bxe_softc *sc = params->sc; 9478 struct elink_phy *phy; 9479 uint32_t gpio_val; 9480 uint8_t gpio_num, gpio_port; 9481 if (CHIP_IS_E3(sc)) { 9482 phy = ¶ms->phy[ELINK_INT_PHY]; 9483 /* Always enable TX laser,will be disabled in case of fault */ 9484 elink_sfp_set_transmitter(params, phy, 1); 9485 } else { 9486 phy = ¶ms->phy[ELINK_EXT_PHY1]; 9487 } 9488 if (elink_get_mod_abs_int_cfg(sc, params->chip_id, params->shmem_base, 9489 params->port, &gpio_num, &gpio_port) == 9490 ELINK_STATUS_ERROR) { 9491 ELINK_DEBUG_P0(sc, "Failed to get MOD_ABS interrupt config\n"); 9492 return; 9493 } 9494 9495 /* Set valid module led off */ 9496 elink_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_HIGH); 9497 9498 /* Get current gpio val reflecting module plugged in / out*/ 9499 gpio_val = elink_cb_gpio_read(sc, gpio_num, gpio_port); 9500 9501 /* Call the handling function in case module is detected */ 9502 if (gpio_val == 0) { 9503 elink_set_mdio_emac_per_phy(sc, params); 9504 elink_set_aer_mmd(params, phy); 9505 9506 elink_power_sfp_module(params, phy, 1); 9507 elink_cb_gpio_int_write(sc, gpio_num, 9508 MISC_REGISTERS_GPIO_INT_OUTPUT_CLR, 9509 gpio_port); 9510 if (elink_wait_for_sfp_module_initialized(phy, params) == 0) { 9511 elink_sfp_module_detection(phy, params); 9512 if (CHIP_IS_E3(sc)) { 9513 uint16_t rx_tx_in_reset; 9514 /* In case WC is out of reset, reconfigure the 9515 * link speed while taking into account 1G 9516 * module limitation. 9517 */ 9518 elink_cl45_read(sc, phy, 9519 MDIO_WC_DEVAD, 9520 MDIO_WC_REG_DIGITAL5_MISC6, 9521 &rx_tx_in_reset); 9522 if ((!rx_tx_in_reset) && 9523 (params->link_flags & 9524 ELINK_PHY_INITIALIZED)) { 9525 elink_warpcore_reset_lane(sc, phy, 1); 9526 elink_warpcore_config_sfi(phy, params); 9527 elink_warpcore_reset_lane(sc, phy, 0); 9528 } 9529 } 9530 } else { 9531 ELINK_DEBUG_P0(sc, "SFP+ module is not initialized\n"); 9532 } 9533 } else { 9534 elink_cb_gpio_int_write(sc, gpio_num, 9535 MISC_REGISTERS_GPIO_INT_OUTPUT_SET, 9536 gpio_port); 9537 /* Module was plugged out. 9538 * Disable transmit for this module 9539 */ 9540 phy->media_type = ELINK_ETH_PHY_NOT_PRESENT; 9541 } 9542 } 9543 9544 /******************************************************************/ 9545 /* Used by 8706 and 8727 */ 9546 /******************************************************************/ 9547 static void elink_sfp_mask_fault(struct bxe_softc *sc, 9548 struct elink_phy *phy, 9549 uint16_t alarm_status_offset, 9550 uint16_t alarm_ctrl_offset) 9551 { 9552 uint16_t alarm_status, val; 9553 elink_cl45_read(sc, phy, 9554 MDIO_PMA_DEVAD, alarm_status_offset, 9555 &alarm_status); 9556 elink_cl45_read(sc, phy, 9557 MDIO_PMA_DEVAD, alarm_status_offset, 9558 &alarm_status); 9559 /* Mask or enable the fault event. */ 9560 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, &val); 9561 if (alarm_status & (1<<0)) 9562 val &= ~(1<<0); 9563 else 9564 val |= (1<<0); 9565 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, val); 9566 } 9567 /******************************************************************/ 9568 /* common BCM8706/BCM8726 PHY SECTION */ 9569 /******************************************************************/ 9570 static uint8_t elink_8706_8726_read_status(struct elink_phy *phy, 9571 struct elink_params *params, 9572 struct elink_vars *vars) 9573 { 9574 uint8_t link_up = 0; 9575 uint16_t val1, val2, rx_sd, pcs_status; 9576 struct bxe_softc *sc = params->sc; 9577 ELINK_DEBUG_P0(sc, "XGXS 8706/8726\n"); 9578 /* Clear RX Alarm*/ 9579 elink_cl45_read(sc, phy, 9580 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2); 9581 9582 elink_sfp_mask_fault(sc, phy, MDIO_PMA_LASI_TXSTAT, 9583 MDIO_PMA_LASI_TXCTRL); 9584 9585 /* Clear LASI indication*/ 9586 elink_cl45_read(sc, phy, 9587 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1); 9588 elink_cl45_read(sc, phy, 9589 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2); 9590 ELINK_DEBUG_P2(sc, "8706/8726 LASI status 0x%x--> 0x%x\n", val1, val2); 9591 9592 elink_cl45_read(sc, phy, 9593 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd); 9594 elink_cl45_read(sc, phy, 9595 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &pcs_status); 9596 elink_cl45_read(sc, phy, 9597 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2); 9598 elink_cl45_read(sc, phy, 9599 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2); 9600 9601 ELINK_DEBUG_P3(sc, "8706/8726 rx_sd 0x%x pcs_status 0x%x 1Gbps" 9602 " link_status 0x%x\n", rx_sd, pcs_status, val2); 9603 /* Link is up if both bit 0 of pmd_rx_sd and bit 0 of pcs_status 9604 * are set, or if the autoneg bit 1 is set 9605 */ 9606 link_up = ((rx_sd & pcs_status & 0x1) || (val2 & (1<<1))); 9607 if (link_up) { 9608 if (val2 & (1<<1)) 9609 vars->line_speed = ELINK_SPEED_1000; 9610 else 9611 vars->line_speed = ELINK_SPEED_10000; 9612 elink_ext_phy_resolve_fc(phy, params, vars); 9613 vars->duplex = DUPLEX_FULL; 9614 } 9615 9616 /* Capture 10G link fault. Read twice to clear stale value. */ 9617 if (vars->line_speed == ELINK_SPEED_10000) { 9618 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, 9619 MDIO_PMA_LASI_TXSTAT, &val1); 9620 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, 9621 MDIO_PMA_LASI_TXSTAT, &val1); 9622 if (val1 & (1<<0)) 9623 vars->fault_detected = 1; 9624 } 9625 9626 return link_up; 9627 } 9628 9629 /******************************************************************/ 9630 /* BCM8706 PHY SECTION */ 9631 /******************************************************************/ 9632 static uint8_t elink_8706_config_init(struct elink_phy *phy, 9633 struct elink_params *params, 9634 struct elink_vars *vars) 9635 { 9636 uint32_t tx_en_mode; 9637 uint16_t cnt, val, tmp1; 9638 struct bxe_softc *sc = params->sc; 9639 9640 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2, 9641 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port); 9642 /* HW reset */ 9643 elink_ext_phy_hw_reset(sc, params->port); 9644 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040); 9645 elink_wait_reset_complete(sc, phy, params); 9646 9647 /* Wait until fw is loaded */ 9648 for (cnt = 0; cnt < 100; cnt++) { 9649 elink_cl45_read(sc, phy, 9650 MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER1, &val); 9651 if (val) 9652 break; 9653 DELAY(1000 * 10); 9654 } 9655 ELINK_DEBUG_P1(sc, "XGXS 8706 is initialized after %d ms\n", cnt); 9656 if ((params->feature_config_flags & 9657 ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) { 9658 uint8_t i; 9659 uint16_t reg; 9660 for (i = 0; i < 4; i++) { 9661 reg = MDIO_XS_8706_REG_BANK_RX0 + 9662 i*(MDIO_XS_8706_REG_BANK_RX1 - 9663 MDIO_XS_8706_REG_BANK_RX0); 9664 elink_cl45_read(sc, phy, MDIO_XS_DEVAD, reg, &val); 9665 /* Clear first 3 bits of the control */ 9666 val &= ~0x7; 9667 /* Set control bits according to configuration */ 9668 val |= (phy->rx_preemphasis[i] & 0x7); 9669 ELINK_DEBUG_P2(sc, "Setting RX Equalizer to BCM8706" 9670 " reg 0x%x <-- val 0x%x\n", reg, val); 9671 elink_cl45_write(sc, phy, MDIO_XS_DEVAD, reg, val); 9672 } 9673 } 9674 /* Force speed */ 9675 if (phy->req_line_speed == ELINK_SPEED_10000) { 9676 ELINK_DEBUG_P0(sc, "XGXS 8706 force 10Gbps\n"); 9677 9678 elink_cl45_write(sc, phy, 9679 MDIO_PMA_DEVAD, 9680 MDIO_PMA_REG_DIGITAL_CTRL, 0x400); 9681 elink_cl45_write(sc, phy, 9682 MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL, 9683 0); 9684 /* Arm LASI for link and Tx fault. */ 9685 elink_cl45_write(sc, phy, 9686 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 3); 9687 } else { 9688 /* Force 1Gbps using autoneg with 1G advertisement */ 9689 9690 /* Allow CL37 through CL73 */ 9691 ELINK_DEBUG_P0(sc, "XGXS 8706 AutoNeg\n"); 9692 elink_cl45_write(sc, phy, 9693 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c); 9694 9695 /* Enable Full-Duplex advertisement on CL37 */ 9696 elink_cl45_write(sc, phy, 9697 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LP, 0x0020); 9698 /* Enable CL37 AN */ 9699 elink_cl45_write(sc, phy, 9700 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000); 9701 /* 1G support */ 9702 elink_cl45_write(sc, phy, 9703 MDIO_AN_DEVAD, MDIO_AN_REG_ADV, (1<<5)); 9704 9705 /* Enable clause 73 AN */ 9706 elink_cl45_write(sc, phy, 9707 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200); 9708 elink_cl45_write(sc, phy, 9709 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, 9710 0x0400); 9711 elink_cl45_write(sc, phy, 9712 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 9713 0x0004); 9714 } 9715 elink_save_bcm_spirom_ver(sc, phy, params->port); 9716 9717 /* If TX Laser is controlled by GPIO_0, do not let PHY go into low 9718 * power mode, if TX Laser is disabled 9719 */ 9720 9721 tx_en_mode = REG_RD(sc, params->shmem_base + 9722 offsetof(struct shmem_region, 9723 dev_info.port_hw_config[params->port].sfp_ctrl)) 9724 & PORT_HW_CFG_TX_LASER_MASK; 9725 9726 if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) { 9727 ELINK_DEBUG_P0(sc, "Enabling TXONOFF_PWRDN_DIS\n"); 9728 elink_cl45_read(sc, phy, 9729 MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, &tmp1); 9730 tmp1 |= 0x1; 9731 elink_cl45_write(sc, phy, 9732 MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, tmp1); 9733 } 9734 9735 return ELINK_STATUS_OK; 9736 } 9737 9738 static elink_status_t elink_8706_read_status(struct elink_phy *phy, 9739 struct elink_params *params, 9740 struct elink_vars *vars) 9741 { 9742 return elink_8706_8726_read_status(phy, params, vars); 9743 } 9744 9745 /******************************************************************/ 9746 /* BCM8726 PHY SECTION */ 9747 /******************************************************************/ 9748 static void elink_8726_config_loopback(struct elink_phy *phy, 9749 struct elink_params *params) 9750 { 9751 struct bxe_softc *sc = params->sc; 9752 ELINK_DEBUG_P0(sc, "PMA/PMD ext_phy_loopback: 8726\n"); 9753 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0001); 9754 } 9755 9756 static void elink_8726_external_rom_boot(struct elink_phy *phy, 9757 struct elink_params *params) 9758 { 9759 struct bxe_softc *sc = params->sc; 9760 /* Need to wait 100ms after reset */ 9761 DELAY(1000 * 100); 9762 9763 /* Micro controller re-boot */ 9764 elink_cl45_write(sc, phy, 9765 MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x018B); 9766 9767 /* Set soft reset */ 9768 elink_cl45_write(sc, phy, 9769 MDIO_PMA_DEVAD, 9770 MDIO_PMA_REG_GEN_CTRL, 9771 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET); 9772 9773 elink_cl45_write(sc, phy, 9774 MDIO_PMA_DEVAD, 9775 MDIO_PMA_REG_MISC_CTRL1, 0x0001); 9776 9777 elink_cl45_write(sc, phy, 9778 MDIO_PMA_DEVAD, 9779 MDIO_PMA_REG_GEN_CTRL, 9780 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP); 9781 9782 /* Wait for 150ms for microcode load */ 9783 DELAY(1000 * 150); 9784 9785 /* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */ 9786 elink_cl45_write(sc, phy, 9787 MDIO_PMA_DEVAD, 9788 MDIO_PMA_REG_MISC_CTRL1, 0x0000); 9789 9790 DELAY(1000 * 200); 9791 elink_save_bcm_spirom_ver(sc, phy, params->port); 9792 } 9793 9794 static uint8_t elink_8726_read_status(struct elink_phy *phy, 9795 struct elink_params *params, 9796 struct elink_vars *vars) 9797 { 9798 struct bxe_softc *sc = params->sc; 9799 uint16_t val1; 9800 uint8_t link_up = elink_8706_8726_read_status(phy, params, vars); 9801 if (link_up) { 9802 elink_cl45_read(sc, phy, 9803 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 9804 &val1); 9805 if (val1 & (1<<15)) { 9806 ELINK_DEBUG_P0(sc, "Tx is disabled\n"); 9807 link_up = 0; 9808 vars->line_speed = 0; 9809 } 9810 } 9811 return link_up; 9812 } 9813 9814 9815 static elink_status_t elink_8726_config_init(struct elink_phy *phy, 9816 struct elink_params *params, 9817 struct elink_vars *vars) 9818 { 9819 struct bxe_softc *sc = params->sc; 9820 ELINK_DEBUG_P0(sc, "Initializing BCM8726\n"); 9821 9822 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15); 9823 elink_wait_reset_complete(sc, phy, params); 9824 9825 elink_8726_external_rom_boot(phy, params); 9826 9827 /* Need to call module detected on initialization since the module 9828 * detection triggered by actual module insertion might occur before 9829 * driver is loaded, and when driver is loaded, it reset all 9830 * registers, including the transmitter 9831 */ 9832 elink_sfp_module_detection(phy, params); 9833 9834 if (phy->req_line_speed == ELINK_SPEED_1000) { 9835 ELINK_DEBUG_P0(sc, "Setting 1G force\n"); 9836 elink_cl45_write(sc, phy, 9837 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40); 9838 elink_cl45_write(sc, phy, 9839 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD); 9840 elink_cl45_write(sc, phy, 9841 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x5); 9842 elink_cl45_write(sc, phy, 9843 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, 9844 0x400); 9845 } else if ((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) && 9846 (phy->speed_cap_mask & 9847 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) && 9848 ((phy->speed_cap_mask & 9849 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) != 9850 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) { 9851 ELINK_DEBUG_P0(sc, "Setting 1G clause37\n"); 9852 /* Set Flow control */ 9853 elink_ext_phy_set_pause(params, phy, vars); 9854 elink_cl45_write(sc, phy, 9855 MDIO_AN_DEVAD, MDIO_AN_REG_ADV, 0x20); 9856 elink_cl45_write(sc, phy, 9857 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c); 9858 elink_cl45_write(sc, phy, 9859 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, 0x0020); 9860 elink_cl45_write(sc, phy, 9861 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000); 9862 elink_cl45_write(sc, phy, 9863 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200); 9864 /* Enable RX-ALARM control to receive interrupt for 1G speed 9865 * change 9866 */ 9867 elink_cl45_write(sc, phy, 9868 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x4); 9869 elink_cl45_write(sc, phy, 9870 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, 9871 0x400); 9872 9873 } else { /* Default 10G. Set only LASI control */ 9874 elink_cl45_write(sc, phy, 9875 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 1); 9876 } 9877 9878 /* Set TX PreEmphasis if needed */ 9879 if ((params->feature_config_flags & 9880 ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) { 9881 ELINK_DEBUG_P2(sc, 9882 "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n", 9883 phy->tx_preemphasis[0], 9884 phy->tx_preemphasis[1]); 9885 elink_cl45_write(sc, phy, 9886 MDIO_PMA_DEVAD, 9887 MDIO_PMA_REG_8726_TX_CTRL1, 9888 phy->tx_preemphasis[0]); 9889 9890 elink_cl45_write(sc, phy, 9891 MDIO_PMA_DEVAD, 9892 MDIO_PMA_REG_8726_TX_CTRL2, 9893 phy->tx_preemphasis[1]); 9894 } 9895 9896 return ELINK_STATUS_OK; 9897 9898 } 9899 9900 static void elink_8726_link_reset(struct elink_phy *phy, 9901 struct elink_params *params) 9902 { 9903 struct bxe_softc *sc = params->sc; 9904 ELINK_DEBUG_P1(sc, "elink_8726_link_reset port %d\n", params->port); 9905 /* Set serial boot control for external load */ 9906 elink_cl45_write(sc, phy, 9907 MDIO_PMA_DEVAD, 9908 MDIO_PMA_REG_GEN_CTRL, 0x0001); 9909 } 9910 9911 /******************************************************************/ 9912 /* BCM8727 PHY SECTION */ 9913 /******************************************************************/ 9914 9915 static void elink_8727_set_link_led(struct elink_phy *phy, 9916 struct elink_params *params, uint8_t mode) 9917 { 9918 struct bxe_softc *sc = params->sc; 9919 uint16_t led_mode_bitmask = 0; 9920 uint16_t gpio_pins_bitmask = 0; 9921 uint16_t val; 9922 /* Only NOC flavor requires to set the LED specifically */ 9923 if (!(phy->flags & ELINK_FLAGS_NOC)) 9924 return; 9925 switch (mode) { 9926 case ELINK_LED_MODE_FRONT_PANEL_OFF: 9927 case ELINK_LED_MODE_OFF: 9928 led_mode_bitmask = 0; 9929 gpio_pins_bitmask = 0x03; 9930 break; 9931 case ELINK_LED_MODE_ON: 9932 led_mode_bitmask = 0; 9933 gpio_pins_bitmask = 0x02; 9934 break; 9935 case ELINK_LED_MODE_OPER: 9936 led_mode_bitmask = 0x60; 9937 gpio_pins_bitmask = 0x11; 9938 break; 9939 } 9940 elink_cl45_read(sc, phy, 9941 MDIO_PMA_DEVAD, 9942 MDIO_PMA_REG_8727_PCS_OPT_CTRL, 9943 &val); 9944 val &= 0xff8f; 9945 val |= led_mode_bitmask; 9946 elink_cl45_write(sc, phy, 9947 MDIO_PMA_DEVAD, 9948 MDIO_PMA_REG_8727_PCS_OPT_CTRL, 9949 val); 9950 elink_cl45_read(sc, phy, 9951 MDIO_PMA_DEVAD, 9952 MDIO_PMA_REG_8727_GPIO_CTRL, 9953 &val); 9954 val &= 0xffe0; 9955 val |= gpio_pins_bitmask; 9956 elink_cl45_write(sc, phy, 9957 MDIO_PMA_DEVAD, 9958 MDIO_PMA_REG_8727_GPIO_CTRL, 9959 val); 9960 } 9961 static void elink_8727_hw_reset(struct elink_phy *phy, 9962 struct elink_params *params) { 9963 uint32_t swap_val, swap_override; 9964 uint8_t port; 9965 /* The PHY reset is controlled by GPIO 1. Fake the port number 9966 * to cancel the swap done in set_gpio() 9967 */ 9968 struct bxe_softc *sc = params->sc; 9969 swap_val = REG_RD(sc, NIG_REG_PORT_SWAP); 9970 swap_override = REG_RD(sc, NIG_REG_STRAP_OVERRIDE); 9971 port = (swap_val && swap_override) ^ 1; 9972 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_1, 9973 MISC_REGISTERS_GPIO_OUTPUT_LOW, port); 9974 } 9975 9976 static void elink_8727_config_speed(struct elink_phy *phy, 9977 struct elink_params *params) 9978 { 9979 struct bxe_softc *sc = params->sc; 9980 uint16_t tmp1, val; 9981 /* Set option 1G speed */ 9982 if ((phy->req_line_speed == ELINK_SPEED_1000) || 9983 (phy->media_type == ELINK_ETH_PHY_SFP_1G_FIBER)) { 9984 ELINK_DEBUG_P0(sc, "Setting 1G force\n"); 9985 elink_cl45_write(sc, phy, 9986 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40); 9987 elink_cl45_write(sc, phy, 9988 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD); 9989 elink_cl45_read(sc, phy, 9990 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, &tmp1); 9991 ELINK_DEBUG_P1(sc, "1.7 = 0x%x\n", tmp1); 9992 /* Power down the XAUI until link is up in case of dual-media 9993 * and 1G 9994 */ 9995 if (ELINK_DUAL_MEDIA(params)) { 9996 elink_cl45_read(sc, phy, 9997 MDIO_PMA_DEVAD, 9998 MDIO_PMA_REG_8727_PCS_GP, &val); 9999 val |= (3<<10); 10000 elink_cl45_write(sc, phy, 10001 MDIO_PMA_DEVAD, 10002 MDIO_PMA_REG_8727_PCS_GP, val); 10003 } 10004 } else if ((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) && 10005 ((phy->speed_cap_mask & 10006 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) && 10007 ((phy->speed_cap_mask & 10008 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) != 10009 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) { 10010 10011 ELINK_DEBUG_P0(sc, "Setting 1G clause37\n"); 10012 elink_cl45_write(sc, phy, 10013 MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, 0); 10014 elink_cl45_write(sc, phy, 10015 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1300); 10016 } else { 10017 /* Since the 8727 has only single reset pin, need to set the 10G 10018 * registers although it is default 10019 */ 10020 elink_cl45_write(sc, phy, 10021 MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, 10022 0x0020); 10023 elink_cl45_write(sc, phy, 10024 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x0100); 10025 elink_cl45_write(sc, phy, 10026 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040); 10027 elink_cl45_write(sc, phy, 10028 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 10029 0x0008); 10030 } 10031 } 10032 10033 static elink_status_t elink_8727_config_init(struct elink_phy *phy, 10034 struct elink_params *params, 10035 struct elink_vars *vars) 10036 { 10037 uint32_t tx_en_mode; 10038 uint16_t tmp1, mod_abs, tmp2; 10039 struct bxe_softc *sc = params->sc; 10040 /* Enable PMD link, MOD_ABS_FLT, and 1G link alarm */ 10041 10042 elink_wait_reset_complete(sc, phy, params); 10043 10044 ELINK_DEBUG_P0(sc, "Initializing BCM8727\n"); 10045 10046 elink_8727_specific_func(phy, params, ELINK_PHY_INIT); 10047 /* Initially configure MOD_ABS to interrupt when module is 10048 * presence( bit 8) 10049 */ 10050 elink_cl45_read(sc, phy, 10051 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs); 10052 /* Set EDC off by setting OPTXLOS signal input to low (bit 9). 10053 * When the EDC is off it locks onto a reference clock and avoids 10054 * becoming 'lost' 10055 */ 10056 mod_abs &= ~(1<<8); 10057 if (!(phy->flags & ELINK_FLAGS_NOC)) 10058 mod_abs &= ~(1<<9); 10059 elink_cl45_write(sc, phy, 10060 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs); 10061 10062 /* Enable/Disable PHY transmitter output */ 10063 elink_set_disable_pmd_transmit(params, phy, 0); 10064 10065 elink_8727_power_module(sc, phy, 1); 10066 10067 elink_cl45_read(sc, phy, 10068 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1); 10069 10070 elink_cl45_read(sc, phy, 10071 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1); 10072 10073 elink_8727_config_speed(phy, params); 10074 10075 10076 /* Set TX PreEmphasis if needed */ 10077 if ((params->feature_config_flags & 10078 ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) { 10079 ELINK_DEBUG_P2(sc, "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n", 10080 phy->tx_preemphasis[0], 10081 phy->tx_preemphasis[1]); 10082 elink_cl45_write(sc, phy, 10083 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL1, 10084 phy->tx_preemphasis[0]); 10085 10086 elink_cl45_write(sc, phy, 10087 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL2, 10088 phy->tx_preemphasis[1]); 10089 } 10090 10091 /* If TX Laser is controlled by GPIO_0, do not let PHY go into low 10092 * power mode, if TX Laser is disabled 10093 */ 10094 tx_en_mode = REG_RD(sc, params->shmem_base + 10095 offsetof(struct shmem_region, 10096 dev_info.port_hw_config[params->port].sfp_ctrl)) 10097 & PORT_HW_CFG_TX_LASER_MASK; 10098 10099 if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) { 10100 10101 ELINK_DEBUG_P0(sc, "Enabling TXONOFF_PWRDN_DIS\n"); 10102 elink_cl45_read(sc, phy, 10103 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, &tmp2); 10104 tmp2 |= 0x1000; 10105 tmp2 &= 0xFFEF; 10106 elink_cl45_write(sc, phy, 10107 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, tmp2); 10108 elink_cl45_read(sc, phy, 10109 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 10110 &tmp2); 10111 elink_cl45_write(sc, phy, 10112 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 10113 (tmp2 & 0x7fff)); 10114 } 10115 10116 return ELINK_STATUS_OK; 10117 } 10118 10119 static void elink_8727_handle_mod_abs(struct elink_phy *phy, 10120 struct elink_params *params) 10121 { 10122 struct bxe_softc *sc = params->sc; 10123 uint16_t mod_abs, rx_alarm_status; 10124 uint32_t val = REG_RD(sc, params->shmem_base + 10125 offsetof(struct shmem_region, dev_info. 10126 port_feature_config[params->port]. 10127 config)); 10128 elink_cl45_read(sc, phy, 10129 MDIO_PMA_DEVAD, 10130 MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs); 10131 if (mod_abs & (1<<8)) { 10132 10133 /* Module is absent */ 10134 ELINK_DEBUG_P0(sc, 10135 "MOD_ABS indication show module is absent\n"); 10136 phy->media_type = ELINK_ETH_PHY_NOT_PRESENT; 10137 /* 1. Set mod_abs to detect next module 10138 * presence event 10139 * 2. Set EDC off by setting OPTXLOS signal input to low 10140 * (bit 9). 10141 * When the EDC is off it locks onto a reference clock and 10142 * avoids becoming 'lost'. 10143 */ 10144 mod_abs &= ~(1<<8); 10145 if (!(phy->flags & ELINK_FLAGS_NOC)) 10146 mod_abs &= ~(1<<9); 10147 elink_cl45_write(sc, phy, 10148 MDIO_PMA_DEVAD, 10149 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs); 10150 10151 /* Clear RX alarm since it stays up as long as 10152 * the mod_abs wasn't changed 10153 */ 10154 elink_cl45_read(sc, phy, 10155 MDIO_PMA_DEVAD, 10156 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status); 10157 10158 } else { 10159 /* Module is present */ 10160 ELINK_DEBUG_P0(sc, 10161 "MOD_ABS indication show module is present\n"); 10162 /* First disable transmitter, and if the module is ok, the 10163 * module_detection will enable it 10164 * 1. Set mod_abs to detect next module absent event ( bit 8) 10165 * 2. Restore the default polarity of the OPRXLOS signal and 10166 * this signal will then correctly indicate the presence or 10167 * absence of the Rx signal. (bit 9) 10168 */ 10169 mod_abs |= (1<<8); 10170 if (!(phy->flags & ELINK_FLAGS_NOC)) 10171 mod_abs |= (1<<9); 10172 elink_cl45_write(sc, phy, 10173 MDIO_PMA_DEVAD, 10174 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs); 10175 10176 /* Clear RX alarm since it stays up as long as the mod_abs 10177 * wasn't changed. This is need to be done before calling the 10178 * module detection, otherwise it will clear* the link update 10179 * alarm 10180 */ 10181 elink_cl45_read(sc, phy, 10182 MDIO_PMA_DEVAD, 10183 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status); 10184 10185 10186 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) == 10187 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER) 10188 elink_sfp_set_transmitter(params, phy, 0); 10189 10190 if (elink_wait_for_sfp_module_initialized(phy, params) == 0) 10191 elink_sfp_module_detection(phy, params); 10192 else 10193 ELINK_DEBUG_P0(sc, "SFP+ module is not initialized\n"); 10194 10195 /* Reconfigure link speed based on module type limitations */ 10196 elink_8727_config_speed(phy, params); 10197 } 10198 10199 ELINK_DEBUG_P1(sc, "8727 RX_ALARM_STATUS 0x%x\n", 10200 rx_alarm_status); 10201 /* No need to check link status in case of module plugged in/out */ 10202 } 10203 10204 static uint8_t elink_8727_read_status(struct elink_phy *phy, 10205 struct elink_params *params, 10206 struct elink_vars *vars) 10207 10208 { 10209 struct bxe_softc *sc = params->sc; 10210 uint8_t link_up = 0, oc_port = params->port; 10211 uint16_t link_status = 0; 10212 uint16_t rx_alarm_status, lasi_ctrl, val1; 10213 10214 /* If PHY is not initialized, do not check link status */ 10215 elink_cl45_read(sc, phy, 10216 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 10217 &lasi_ctrl); 10218 if (!lasi_ctrl) 10219 return 0; 10220 10221 /* Check the LASI on Rx */ 10222 elink_cl45_read(sc, phy, 10223 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, 10224 &rx_alarm_status); 10225 vars->line_speed = 0; 10226 ELINK_DEBUG_P1(sc, "8727 RX_ALARM_STATUS 0x%x\n", rx_alarm_status); 10227 10228 elink_sfp_mask_fault(sc, phy, MDIO_PMA_LASI_TXSTAT, 10229 MDIO_PMA_LASI_TXCTRL); 10230 10231 elink_cl45_read(sc, phy, 10232 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1); 10233 10234 ELINK_DEBUG_P1(sc, "8727 LASI status 0x%x\n", val1); 10235 10236 /* Clear MSG-OUT */ 10237 elink_cl45_read(sc, phy, 10238 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1); 10239 10240 /* If a module is present and there is need to check 10241 * for over current 10242 */ 10243 if (!(phy->flags & ELINK_FLAGS_NOC) && !(rx_alarm_status & (1<<5))) { 10244 /* Check over-current using 8727 GPIO0 input*/ 10245 elink_cl45_read(sc, phy, 10246 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL, 10247 &val1); 10248 10249 if ((val1 & (1<<8)) == 0) { 10250 if (!CHIP_IS_E1x(sc)) 10251 oc_port = SC_PATH(sc) + (params->port << 1); 10252 ELINK_DEBUG_P1(sc, 10253 "8727 Power fault has been detected on port %d\n", 10254 oc_port); 10255 elink_cb_event_log(sc, ELINK_LOG_ID_OVER_CURRENT, oc_port); //"Error: Power fault on Port %d has " 10256 // "been detected and the power to " 10257 // "that SFP+ module has been removed " 10258 // "to prevent failure of the card. " 10259 // "Please remove the SFP+ module and " 10260 // "restart the system to clear this " 10261 // "error.\n", 10262 /* Disable all RX_ALARMs except for mod_abs */ 10263 elink_cl45_write(sc, phy, 10264 MDIO_PMA_DEVAD, 10265 MDIO_PMA_LASI_RXCTRL, (1<<5)); 10266 10267 elink_cl45_read(sc, phy, 10268 MDIO_PMA_DEVAD, 10269 MDIO_PMA_REG_PHY_IDENTIFIER, &val1); 10270 /* Wait for module_absent_event */ 10271 val1 |= (1<<8); 10272 elink_cl45_write(sc, phy, 10273 MDIO_PMA_DEVAD, 10274 MDIO_PMA_REG_PHY_IDENTIFIER, val1); 10275 /* Clear RX alarm */ 10276 elink_cl45_read(sc, phy, 10277 MDIO_PMA_DEVAD, 10278 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status); 10279 elink_8727_power_module(params->sc, phy, 0); 10280 return 0; 10281 } 10282 } /* Over current check */ 10283 10284 /* When module absent bit is set, check module */ 10285 if (rx_alarm_status & (1<<5)) { 10286 elink_8727_handle_mod_abs(phy, params); 10287 /* Enable all mod_abs and link detection bits */ 10288 elink_cl45_write(sc, phy, 10289 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, 10290 ((1<<5) | (1<<2))); 10291 } 10292 10293 if (!(phy->flags & ELINK_FLAGS_SFP_NOT_APPROVED)) { 10294 ELINK_DEBUG_P0(sc, "Enabling 8727 TX laser\n"); 10295 elink_sfp_set_transmitter(params, phy, 1); 10296 } else { 10297 ELINK_DEBUG_P0(sc, "Tx is disabled\n"); 10298 return 0; 10299 } 10300 10301 elink_cl45_read(sc, phy, 10302 MDIO_PMA_DEVAD, 10303 MDIO_PMA_REG_8073_SPEED_LINK_STATUS, &link_status); 10304 10305 /* Bits 0..2 --> speed detected, 10306 * Bits 13..15--> link is down 10307 */ 10308 if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) { 10309 link_up = 1; 10310 vars->line_speed = ELINK_SPEED_10000; 10311 ELINK_DEBUG_P1(sc, "port %x: External link up in 10G\n", 10312 params->port); 10313 } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) { 10314 link_up = 1; 10315 vars->line_speed = ELINK_SPEED_1000; 10316 ELINK_DEBUG_P1(sc, "port %x: External link up in 1G\n", 10317 params->port); 10318 } else { 10319 link_up = 0; 10320 ELINK_DEBUG_P1(sc, "port %x: External link is down\n", 10321 params->port); 10322 } 10323 10324 /* Capture 10G link fault. */ 10325 if (vars->line_speed == ELINK_SPEED_10000) { 10326 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, 10327 MDIO_PMA_LASI_TXSTAT, &val1); 10328 10329 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, 10330 MDIO_PMA_LASI_TXSTAT, &val1); 10331 10332 if (val1 & (1<<0)) { 10333 vars->fault_detected = 1; 10334 } 10335 } 10336 10337 if (link_up) { 10338 elink_ext_phy_resolve_fc(phy, params, vars); 10339 vars->duplex = DUPLEX_FULL; 10340 ELINK_DEBUG_P1(sc, "duplex = 0x%x\n", vars->duplex); 10341 } 10342 10343 if ((ELINK_DUAL_MEDIA(params)) && 10344 (phy->req_line_speed == ELINK_SPEED_1000)) { 10345 elink_cl45_read(sc, phy, 10346 MDIO_PMA_DEVAD, 10347 MDIO_PMA_REG_8727_PCS_GP, &val1); 10348 /* In case of dual-media board and 1G, power up the XAUI side, 10349 * otherwise power it down. For 10G it is done automatically 10350 */ 10351 if (link_up) 10352 val1 &= ~(3<<10); 10353 else 10354 val1 |= (3<<10); 10355 elink_cl45_write(sc, phy, 10356 MDIO_PMA_DEVAD, 10357 MDIO_PMA_REG_8727_PCS_GP, val1); 10358 } 10359 return link_up; 10360 } 10361 10362 static void elink_8727_link_reset(struct elink_phy *phy, 10363 struct elink_params *params) 10364 { 10365 struct bxe_softc *sc = params->sc; 10366 10367 /* Enable/Disable PHY transmitter output */ 10368 elink_set_disable_pmd_transmit(params, phy, 1); 10369 10370 /* Disable Transmitter */ 10371 elink_sfp_set_transmitter(params, phy, 0); 10372 /* Clear LASI */ 10373 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0); 10374 10375 } 10376 10377 /******************************************************************/ 10378 /* BCM8481/BCM84823/BCM84833 PHY SECTION */ 10379 /******************************************************************/ 10380 static void elink_save_848xx_spirom_version(struct elink_phy *phy, 10381 struct bxe_softc *sc, 10382 uint8_t port) 10383 { 10384 uint16_t val, fw_ver2, cnt, i; 10385 static struct elink_reg_set reg_set[] = { 10386 {MDIO_PMA_DEVAD, 0xA819, 0x0014}, 10387 {MDIO_PMA_DEVAD, 0xA81A, 0xc200}, 10388 {MDIO_PMA_DEVAD, 0xA81B, 0x0000}, 10389 {MDIO_PMA_DEVAD, 0xA81C, 0x0300}, 10390 {MDIO_PMA_DEVAD, 0xA817, 0x0009} 10391 }; 10392 uint16_t fw_ver1; 10393 10394 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) || 10395 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) { 10396 elink_cl45_read(sc, phy, MDIO_CTL_DEVAD, 0x400f, &fw_ver1); 10397 elink_save_spirom_version(sc, port, fw_ver1 & 0xfff, 10398 phy->ver_addr); 10399 } else { 10400 /* For 32-bit registers in 848xx, access via MDIO2ARM i/f. */ 10401 /* (1) set reg 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */ 10402 for (i = 0; i < ARRAY_SIZE(reg_set); i++) 10403 elink_cl45_write(sc, phy, reg_set[i].devad, 10404 reg_set[i].reg, reg_set[i].val); 10405 10406 for (cnt = 0; cnt < 100; cnt++) { 10407 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, 0xA818, &val); 10408 if (val & 1) 10409 break; 10410 DELAY(5); 10411 } 10412 if (cnt == 100) { 10413 ELINK_DEBUG_P0(sc, "Unable to read 848xx " 10414 "phy fw version(1)\n"); 10415 elink_save_spirom_version(sc, port, 0, 10416 phy->ver_addr); 10417 return; 10418 } 10419 10420 10421 /* 2) read register 0xc200_0000 (SPI_FW_STATUS) */ 10422 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, 0xA819, 0x0000); 10423 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200); 10424 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, 0xA817, 0x000A); 10425 for (cnt = 0; cnt < 100; cnt++) { 10426 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, 0xA818, &val); 10427 if (val & 1) 10428 break; 10429 DELAY(5); 10430 } 10431 if (cnt == 100) { 10432 ELINK_DEBUG_P0(sc, "Unable to read 848xx phy fw " 10433 "version(2)\n"); 10434 elink_save_spirom_version(sc, port, 0, 10435 phy->ver_addr); 10436 return; 10437 } 10438 10439 /* lower 16 bits of the register SPI_FW_STATUS */ 10440 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, 0xA81B, &fw_ver1); 10441 /* upper 16 bits of register SPI_FW_STATUS */ 10442 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, 0xA81C, &fw_ver2); 10443 10444 elink_save_spirom_version(sc, port, (fw_ver2<<16) | fw_ver1, 10445 phy->ver_addr); 10446 } 10447 10448 } 10449 static void elink_848xx_set_led(struct bxe_softc *sc, 10450 struct elink_phy *phy) 10451 { 10452 uint16_t val, offset, i; 10453 static struct elink_reg_set reg_set[] = { 10454 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED1_MASK, 0x0080}, 10455 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED2_MASK, 0x0018}, 10456 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED3_MASK, 0x0006}, 10457 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED3_BLINK, 0x0000}, 10458 {MDIO_PMA_DEVAD, MDIO_PMA_REG_84823_CTL_SLOW_CLK_CNT_HIGH, 10459 MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ}, 10460 {MDIO_AN_DEVAD, 0xFFFB, 0xFFFD} 10461 }; 10462 /* PHYC_CTL_LED_CTL */ 10463 elink_cl45_read(sc, phy, 10464 MDIO_PMA_DEVAD, 10465 MDIO_PMA_REG_8481_LINK_SIGNAL, &val); 10466 val &= 0xFE00; 10467 val |= 0x0092; 10468 10469 elink_cl45_write(sc, phy, 10470 MDIO_PMA_DEVAD, 10471 MDIO_PMA_REG_8481_LINK_SIGNAL, val); 10472 10473 for (i = 0; i < ARRAY_SIZE(reg_set); i++) 10474 elink_cl45_write(sc, phy, reg_set[i].devad, reg_set[i].reg, 10475 reg_set[i].val); 10476 10477 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) || 10478 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) 10479 offset = MDIO_PMA_REG_84833_CTL_LED_CTL_1; 10480 else 10481 offset = MDIO_PMA_REG_84823_CTL_LED_CTL_1; 10482 10483 /* stretch_en for LED3*/ 10484 elink_cl45_read_or_write(sc, phy, 10485 MDIO_PMA_DEVAD, offset, 10486 MDIO_PMA_REG_84823_LED3_STRETCH_EN); 10487 } 10488 10489 static void elink_848xx_specific_func(struct elink_phy *phy, 10490 struct elink_params *params, 10491 uint32_t action) 10492 { 10493 struct bxe_softc *sc = params->sc; 10494 switch (action) { 10495 case ELINK_PHY_INIT: 10496 if ((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) && 10497 (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) { 10498 /* Save spirom version */ 10499 elink_save_848xx_spirom_version(phy, sc, params->port); 10500 } 10501 /* This phy uses the NIG latch mechanism since link indication 10502 * arrives through its LED4 and not via its LASI signal, so we 10503 * get steady signal instead of clear on read 10504 */ 10505 elink_bits_en(sc, NIG_REG_LATCH_BC_0 + params->port*4, 10506 1 << ELINK_NIG_LATCH_BC_ENABLE_MI_INT); 10507 10508 elink_848xx_set_led(sc, phy); 10509 break; 10510 } 10511 } 10512 10513 static elink_status_t elink_848xx_cmn_config_init(struct elink_phy *phy, 10514 struct elink_params *params, 10515 struct elink_vars *vars) 10516 { 10517 struct bxe_softc *sc = params->sc; 10518 uint16_t autoneg_val, an_1000_val, an_10_100_val; 10519 10520 elink_848xx_specific_func(phy, params, ELINK_PHY_INIT); 10521 elink_cl45_write(sc, phy, 10522 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0000); 10523 10524 /* set 1000 speed advertisement */ 10525 elink_cl45_read(sc, phy, 10526 MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL, 10527 &an_1000_val); 10528 10529 elink_ext_phy_set_pause(params, phy, vars); 10530 elink_cl45_read(sc, phy, 10531 MDIO_AN_DEVAD, 10532 MDIO_AN_REG_8481_LEGACY_AN_ADV, 10533 &an_10_100_val); 10534 elink_cl45_read(sc, phy, 10535 MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_MII_CTRL, 10536 &autoneg_val); 10537 /* Disable forced speed */ 10538 autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13)); 10539 an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8)); 10540 10541 if (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) && 10542 (phy->speed_cap_mask & 10543 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) || 10544 (phy->req_line_speed == ELINK_SPEED_1000)) { 10545 an_1000_val |= (1<<8); 10546 autoneg_val |= (1<<9 | 1<<12); 10547 if (phy->req_duplex == DUPLEX_FULL) 10548 an_1000_val |= (1<<9); 10549 ELINK_DEBUG_P0(sc, "Advertising 1G\n"); 10550 } else 10551 an_1000_val &= ~((1<<8) | (1<<9)); 10552 10553 elink_cl45_write(sc, phy, 10554 MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL, 10555 an_1000_val); 10556 10557 /* Set 10/100 speed advertisement */ 10558 if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG) { 10559 if (phy->speed_cap_mask & 10560 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL) { 10561 /* Enable autoneg and restart autoneg for legacy speeds 10562 */ 10563 autoneg_val |= (1<<9 | 1<<12); 10564 an_10_100_val |= (1<<8); 10565 ELINK_DEBUG_P0(sc, "Advertising 100M-FD\n"); 10566 } 10567 10568 if (phy->speed_cap_mask & 10569 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF) { 10570 /* Enable autoneg and restart autoneg for legacy speeds 10571 */ 10572 autoneg_val |= (1<<9 | 1<<12); 10573 an_10_100_val |= (1<<7); 10574 ELINK_DEBUG_P0(sc, "Advertising 100M-HD\n"); 10575 } 10576 10577 if ((phy->speed_cap_mask & 10578 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) && 10579 (phy->supported & ELINK_SUPPORTED_10baseT_Full)) { 10580 an_10_100_val |= (1<<6); 10581 autoneg_val |= (1<<9 | 1<<12); 10582 ELINK_DEBUG_P0(sc, "Advertising 10M-FD\n"); 10583 } 10584 10585 if ((phy->speed_cap_mask & 10586 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF) && 10587 (phy->supported & ELINK_SUPPORTED_10baseT_Half)) { 10588 an_10_100_val |= (1<<5); 10589 autoneg_val |= (1<<9 | 1<<12); 10590 ELINK_DEBUG_P0(sc, "Advertising 10M-HD\n"); 10591 } 10592 } 10593 10594 /* Only 10/100 are allowed to work in FORCE mode */ 10595 if ((phy->req_line_speed == ELINK_SPEED_100) && 10596 (phy->supported & 10597 (ELINK_SUPPORTED_100baseT_Half | 10598 ELINK_SUPPORTED_100baseT_Full))) { 10599 autoneg_val |= (1<<13); 10600 /* Enabled AUTO-MDIX when autoneg is disabled */ 10601 elink_cl45_write(sc, phy, 10602 MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL, 10603 (1<<15 | 1<<9 | 7<<0)); 10604 /* The PHY needs this set even for forced link. */ 10605 an_10_100_val |= (1<<8) | (1<<7); 10606 ELINK_DEBUG_P0(sc, "Setting 100M force\n"); 10607 } 10608 if ((phy->req_line_speed == ELINK_SPEED_10) && 10609 (phy->supported & 10610 (ELINK_SUPPORTED_10baseT_Half | 10611 ELINK_SUPPORTED_10baseT_Full))) { 10612 /* Enabled AUTO-MDIX when autoneg is disabled */ 10613 elink_cl45_write(sc, phy, 10614 MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL, 10615 (1<<15 | 1<<9 | 7<<0)); 10616 ELINK_DEBUG_P0(sc, "Setting 10M force\n"); 10617 } 10618 10619 elink_cl45_write(sc, phy, 10620 MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_AN_ADV, 10621 an_10_100_val); 10622 10623 if (phy->req_duplex == DUPLEX_FULL) 10624 autoneg_val |= (1<<8); 10625 10626 /* Always write this if this is not 84833/4. 10627 * For 84833/4, write it only when it's a forced speed. 10628 */ 10629 if (((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) && 10630 (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) || 10631 ((autoneg_val & (1<<12)) == 0)) 10632 elink_cl45_write(sc, phy, 10633 MDIO_AN_DEVAD, 10634 MDIO_AN_REG_8481_LEGACY_MII_CTRL, autoneg_val); 10635 10636 if (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) && 10637 (phy->speed_cap_mask & 10638 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) || 10639 (phy->req_line_speed == ELINK_SPEED_10000)) { 10640 ELINK_DEBUG_P0(sc, "Advertising 10G\n"); 10641 /* Restart autoneg for 10G*/ 10642 10643 elink_cl45_read_or_write( 10644 sc, phy, 10645 MDIO_AN_DEVAD, 10646 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL, 10647 0x1000); 10648 elink_cl45_write(sc, phy, 10649 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 10650 0x3200); 10651 } else 10652 elink_cl45_write(sc, phy, 10653 MDIO_AN_DEVAD, 10654 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL, 10655 1); 10656 10657 return ELINK_STATUS_OK; 10658 } 10659 10660 static elink_status_t elink_8481_config_init(struct elink_phy *phy, 10661 struct elink_params *params, 10662 struct elink_vars *vars) 10663 { 10664 struct bxe_softc *sc = params->sc; 10665 /* Restore normal power mode*/ 10666 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2, 10667 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port); 10668 10669 /* HW reset */ 10670 elink_ext_phy_hw_reset(sc, params->port); 10671 elink_wait_reset_complete(sc, phy, params); 10672 10673 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15); 10674 return elink_848xx_cmn_config_init(phy, params, vars); 10675 } 10676 10677 #define PHY84833_CMDHDLR_WAIT 300 10678 #define PHY84833_CMDHDLR_MAX_ARGS 5 10679 static elink_status_t elink_84833_cmd_hdlr(struct elink_phy *phy, 10680 struct elink_params *params, uint16_t fw_cmd, 10681 uint16_t cmd_args[], int argc) 10682 { 10683 int idx; 10684 uint16_t val; 10685 struct bxe_softc *sc = params->sc; 10686 /* Write CMD_OPEN_OVERRIDE to STATUS reg */ 10687 elink_cl45_write(sc, phy, MDIO_CTL_DEVAD, 10688 MDIO_84833_CMD_HDLR_STATUS, 10689 PHY84833_STATUS_CMD_OPEN_OVERRIDE); 10690 for (idx = 0; idx < PHY84833_CMDHDLR_WAIT; idx++) { 10691 elink_cl45_read(sc, phy, MDIO_CTL_DEVAD, 10692 MDIO_84833_CMD_HDLR_STATUS, &val); 10693 if (val == PHY84833_STATUS_CMD_OPEN_FOR_CMDS) 10694 break; 10695 DELAY(1000 * 1); 10696 } 10697 if (idx >= PHY84833_CMDHDLR_WAIT) { 10698 ELINK_DEBUG_P0(sc, "FW cmd: FW not ready.\n"); 10699 return ELINK_STATUS_ERROR; 10700 } 10701 10702 /* Prepare argument(s) and issue command */ 10703 for (idx = 0; idx < argc; idx++) { 10704 elink_cl45_write(sc, phy, MDIO_CTL_DEVAD, 10705 MDIO_84833_CMD_HDLR_DATA1 + idx, 10706 cmd_args[idx]); 10707 } 10708 elink_cl45_write(sc, phy, MDIO_CTL_DEVAD, 10709 MDIO_84833_CMD_HDLR_COMMAND, fw_cmd); 10710 for (idx = 0; idx < PHY84833_CMDHDLR_WAIT; idx++) { 10711 elink_cl45_read(sc, phy, MDIO_CTL_DEVAD, 10712 MDIO_84833_CMD_HDLR_STATUS, &val); 10713 if ((val == PHY84833_STATUS_CMD_COMPLETE_PASS) || 10714 (val == PHY84833_STATUS_CMD_COMPLETE_ERROR)) 10715 break; 10716 DELAY(1000 * 1); 10717 } 10718 if ((idx >= PHY84833_CMDHDLR_WAIT) || 10719 (val == PHY84833_STATUS_CMD_COMPLETE_ERROR)) { 10720 ELINK_DEBUG_P0(sc, "FW cmd failed.\n"); 10721 return ELINK_STATUS_ERROR; 10722 } 10723 /* Gather returning data */ 10724 for (idx = 0; idx < argc; idx++) { 10725 elink_cl45_read(sc, phy, MDIO_CTL_DEVAD, 10726 MDIO_84833_CMD_HDLR_DATA1 + idx, 10727 &cmd_args[idx]); 10728 } 10729 elink_cl45_write(sc, phy, MDIO_CTL_DEVAD, 10730 MDIO_84833_CMD_HDLR_STATUS, 10731 PHY84833_STATUS_CMD_CLEAR_COMPLETE); 10732 return ELINK_STATUS_OK; 10733 } 10734 10735 static elink_status_t elink_84833_pair_swap_cfg(struct elink_phy *phy, 10736 struct elink_params *params, 10737 struct elink_vars *vars) 10738 { 10739 uint32_t pair_swap; 10740 uint16_t data[PHY84833_CMDHDLR_MAX_ARGS]; 10741 elink_status_t status; 10742 struct bxe_softc *sc = params->sc; 10743 10744 /* Check for configuration. */ 10745 pair_swap = REG_RD(sc, params->shmem_base + 10746 offsetof(struct shmem_region, 10747 dev_info.port_hw_config[params->port].xgbt_phy_cfg)) & 10748 PORT_HW_CFG_RJ45_PAIR_SWAP_MASK; 10749 10750 if (pair_swap == 0) 10751 return ELINK_STATUS_OK; 10752 10753 /* Only the second argument is used for this command */ 10754 data[1] = (uint16_t)pair_swap; 10755 10756 status = elink_84833_cmd_hdlr(phy, params, 10757 PHY84833_CMD_SET_PAIR_SWAP, data, PHY84833_CMDHDLR_MAX_ARGS); 10758 if (status == ELINK_STATUS_OK) 10759 ELINK_DEBUG_P1(sc, "Pairswap OK, val=0x%x\n", data[1]); 10760 10761 return status; 10762 } 10763 10764 static uint8_t elink_84833_get_reset_gpios(struct bxe_softc *sc, 10765 uint32_t shmem_base_path[], 10766 uint32_t chip_id) 10767 { 10768 uint32_t reset_pin[2]; 10769 uint32_t idx; 10770 uint8_t reset_gpios; 10771 if (CHIP_IS_E3(sc)) { 10772 /* Assume that these will be GPIOs, not EPIOs. */ 10773 for (idx = 0; idx < 2; idx++) { 10774 /* Map config param to register bit. */ 10775 reset_pin[idx] = REG_RD(sc, shmem_base_path[idx] + 10776 offsetof(struct shmem_region, 10777 dev_info.port_hw_config[0].e3_cmn_pin_cfg)); 10778 reset_pin[idx] = (reset_pin[idx] & 10779 PORT_HW_CFG_E3_PHY_RESET_MASK) >> 10780 PORT_HW_CFG_E3_PHY_RESET_SHIFT; 10781 reset_pin[idx] -= PIN_CFG_GPIO0_P0; 10782 reset_pin[idx] = (1 << reset_pin[idx]); 10783 } 10784 reset_gpios = (uint8_t)(reset_pin[0] | reset_pin[1]); 10785 } else { 10786 /* E2, look from diff place of shmem. */ 10787 for (idx = 0; idx < 2; idx++) { 10788 reset_pin[idx] = REG_RD(sc, shmem_base_path[idx] + 10789 offsetof(struct shmem_region, 10790 dev_info.port_hw_config[0].default_cfg)); 10791 reset_pin[idx] &= PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK; 10792 reset_pin[idx] -= PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0; 10793 reset_pin[idx] >>= PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT; 10794 reset_pin[idx] = (1 << reset_pin[idx]); 10795 } 10796 reset_gpios = (uint8_t)(reset_pin[0] | reset_pin[1]); 10797 } 10798 10799 return reset_gpios; 10800 } 10801 10802 static elink_status_t elink_84833_hw_reset_phy(struct elink_phy *phy, 10803 struct elink_params *params) 10804 { 10805 struct bxe_softc *sc = params->sc; 10806 uint8_t reset_gpios; 10807 uint32_t other_shmem_base_addr = REG_RD(sc, params->shmem2_base + 10808 offsetof(struct shmem2_region, 10809 other_shmem_base_addr)); 10810 10811 uint32_t shmem_base_path[2]; 10812 10813 /* Work around for 84833 LED failure inside RESET status */ 10814 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, 10815 MDIO_AN_REG_8481_LEGACY_MII_CTRL, 10816 MDIO_AN_REG_8481_MII_CTRL_FORCE_1G); 10817 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, 10818 MDIO_AN_REG_8481_1G_100T_EXT_CTRL, 10819 MIDO_AN_REG_8481_EXT_CTRL_FORCE_LEDS_OFF); 10820 10821 shmem_base_path[0] = params->shmem_base; 10822 shmem_base_path[1] = other_shmem_base_addr; 10823 10824 reset_gpios = elink_84833_get_reset_gpios(sc, shmem_base_path, 10825 params->chip_id); 10826 10827 elink_cb_gpio_mult_write(sc, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW); 10828 DELAY(10); 10829 ELINK_DEBUG_P1(sc, "84833 hw reset on pin values 0x%x\n", 10830 reset_gpios); 10831 10832 return ELINK_STATUS_OK; 10833 } 10834 10835 static elink_status_t elink_8483x_disable_eee(struct elink_phy *phy, 10836 struct elink_params *params, 10837 struct elink_vars *vars) 10838 { 10839 elink_status_t rc; 10840 struct bxe_softc *sc = params->sc; 10841 uint16_t cmd_args = 0; 10842 10843 ELINK_DEBUG_P0(sc, "Don't Advertise 10GBase-T EEE\n"); 10844 10845 /* Prevent Phy from working in EEE and advertising it */ 10846 rc = elink_84833_cmd_hdlr(phy, params, 10847 PHY84833_CMD_SET_EEE_MODE, &cmd_args, 1); 10848 if (rc != ELINK_STATUS_OK) { 10849 ELINK_DEBUG_P0(sc, "EEE disable failed.\n"); 10850 return rc; 10851 } 10852 10853 return elink_eee_disable(phy, params, vars); 10854 } 10855 10856 static elink_status_t elink_8483x_enable_eee(struct elink_phy *phy, 10857 struct elink_params *params, 10858 struct elink_vars *vars) 10859 { 10860 elink_status_t rc; 10861 struct bxe_softc *sc = params->sc; 10862 uint16_t cmd_args = 1; 10863 10864 rc = elink_84833_cmd_hdlr(phy, params, 10865 PHY84833_CMD_SET_EEE_MODE, &cmd_args, 1); 10866 if (rc != ELINK_STATUS_OK) { 10867 ELINK_DEBUG_P0(sc, "EEE enable failed.\n"); 10868 return rc; 10869 } 10870 10871 return elink_eee_advertise(phy, params, vars, SHMEM_EEE_10G_ADV); 10872 } 10873 10874 #define PHY84833_CONSTANT_LATENCY 1193 10875 static elink_status_t elink_848x3_config_init(struct elink_phy *phy, 10876 struct elink_params *params, 10877 struct elink_vars *vars) 10878 { 10879 struct bxe_softc *sc = params->sc; 10880 uint8_t port, initialize = 1; 10881 uint16_t val; 10882 uint32_t actual_phy_selection; 10883 uint16_t cmd_args[PHY84833_CMDHDLR_MAX_ARGS]; 10884 elink_status_t rc = ELINK_STATUS_OK; 10885 10886 DELAY(1000 * 1); 10887 10888 if (!(CHIP_IS_E1x(sc))) 10889 port = SC_PATH(sc); 10890 else 10891 port = params->port; 10892 10893 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) { 10894 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_3, 10895 MISC_REGISTERS_GPIO_OUTPUT_HIGH, 10896 port); 10897 } else { 10898 /* MDIO reset */ 10899 elink_cl45_write(sc, phy, 10900 MDIO_PMA_DEVAD, 10901 MDIO_PMA_REG_CTRL, 0x8000); 10902 } 10903 10904 elink_wait_reset_complete(sc, phy, params); 10905 10906 /* Wait for GPHY to come out of reset */ 10907 DELAY(1000 * 50); 10908 if ((phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) && 10909 (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) { 10910 /* BCM84823 requires that XGXS links up first @ 10G for normal 10911 * behavior. 10912 */ 10913 uint16_t temp; 10914 temp = vars->line_speed; 10915 vars->line_speed = ELINK_SPEED_10000; 10916 elink_set_autoneg(¶ms->phy[ELINK_INT_PHY], params, vars, 0); 10917 elink_program_serdes(¶ms->phy[ELINK_INT_PHY], params, vars); 10918 vars->line_speed = temp; 10919 } 10920 10921 elink_cl45_read(sc, phy, MDIO_CTL_DEVAD, 10922 MDIO_CTL_REG_84823_MEDIA, &val); 10923 val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK | 10924 MDIO_CTL_REG_84823_MEDIA_LINE_MASK | 10925 MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN | 10926 MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK | 10927 MDIO_CTL_REG_84823_MEDIA_FIBER_1G); 10928 10929 if (CHIP_IS_E3(sc)) { 10930 val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK | 10931 MDIO_CTL_REG_84823_MEDIA_LINE_MASK); 10932 } else { 10933 val |= (MDIO_CTL_REG_84823_CTRL_MAC_XFI | 10934 MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L); 10935 } 10936 10937 actual_phy_selection = elink_phy_selection(params); 10938 10939 switch (actual_phy_selection) { 10940 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT: 10941 /* Do nothing. Essentially this is like the priority copper */ 10942 break; 10943 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY: 10944 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER; 10945 break; 10946 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY: 10947 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER; 10948 break; 10949 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY: 10950 /* Do nothing here. The first PHY won't be initialized at all */ 10951 break; 10952 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY: 10953 val |= MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN; 10954 initialize = 0; 10955 break; 10956 } 10957 if (params->phy[ELINK_EXT_PHY2].req_line_speed == ELINK_SPEED_1000) 10958 val |= MDIO_CTL_REG_84823_MEDIA_FIBER_1G; 10959 10960 elink_cl45_write(sc, phy, MDIO_CTL_DEVAD, 10961 MDIO_CTL_REG_84823_MEDIA, val); 10962 ELINK_DEBUG_P2(sc, "Multi_phy config = 0x%x, Media control = 0x%x\n", 10963 params->multi_phy_config, val); 10964 10965 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) || 10966 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) { 10967 elink_84833_pair_swap_cfg(phy, params, vars); 10968 10969 /* Keep AutogrEEEn disabled. */ 10970 cmd_args[0] = 0x0; 10971 cmd_args[1] = 0x0; 10972 cmd_args[2] = PHY84833_CONSTANT_LATENCY + 1; 10973 cmd_args[3] = PHY84833_CONSTANT_LATENCY; 10974 rc = elink_84833_cmd_hdlr(phy, params, 10975 PHY84833_CMD_SET_EEE_MODE, cmd_args, 10976 PHY84833_CMDHDLR_MAX_ARGS); 10977 if (rc != ELINK_STATUS_OK) 10978 ELINK_DEBUG_P0(sc, "Cfg AutogrEEEn failed.\n"); 10979 } 10980 if (initialize) 10981 rc = elink_848xx_cmn_config_init(phy, params, vars); 10982 else 10983 elink_save_848xx_spirom_version(phy, sc, params->port); 10984 /* 84833 PHY has a better feature and doesn't need to support this. */ 10985 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) { 10986 uint32_t cms_enable = REG_RD(sc, params->shmem_base + 10987 offsetof(struct shmem_region, 10988 dev_info.port_hw_config[params->port].default_cfg)) & 10989 PORT_HW_CFG_ENABLE_CMS_MASK; 10990 10991 elink_cl45_read(sc, phy, MDIO_CTL_DEVAD, 10992 MDIO_CTL_REG_84823_USER_CTRL_REG, &val); 10993 if (cms_enable) 10994 val |= MDIO_CTL_REG_84823_USER_CTRL_CMS; 10995 else 10996 val &= ~MDIO_CTL_REG_84823_USER_CTRL_CMS; 10997 elink_cl45_write(sc, phy, MDIO_CTL_DEVAD, 10998 MDIO_CTL_REG_84823_USER_CTRL_REG, val); 10999 } 11000 11001 elink_cl45_read(sc, phy, MDIO_CTL_DEVAD, 11002 MDIO_84833_TOP_CFG_FW_REV, &val); 11003 11004 /* Configure EEE support */ 11005 if ((val >= MDIO_84833_TOP_CFG_FW_EEE) && 11006 (val != MDIO_84833_TOP_CFG_FW_NO_EEE) && 11007 elink_eee_has_cap(params)) { 11008 rc = elink_eee_initial_config(params, vars, SHMEM_EEE_10G_ADV); 11009 if (rc != ELINK_STATUS_OK) { 11010 ELINK_DEBUG_P0(sc, "Failed to configure EEE timers\n"); 11011 elink_8483x_disable_eee(phy, params, vars); 11012 return rc; 11013 } 11014 11015 if ((phy->req_duplex == DUPLEX_FULL) && 11016 (params->eee_mode & ELINK_EEE_MODE_ADV_LPI) && 11017 (elink_eee_calc_timer(params) || 11018 !(params->eee_mode & ELINK_EEE_MODE_ENABLE_LPI))) 11019 rc = elink_8483x_enable_eee(phy, params, vars); 11020 else 11021 rc = elink_8483x_disable_eee(phy, params, vars); 11022 if (rc != ELINK_STATUS_OK) { 11023 ELINK_DEBUG_P0(sc, "Failed to set EEE advertisement\n"); 11024 return rc; 11025 } 11026 } else { 11027 vars->eee_status &= ~SHMEM_EEE_SUPPORTED_MASK; 11028 } 11029 11030 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) || 11031 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) { 11032 /* Bring PHY out of super isolate mode as the final step. */ 11033 elink_cl45_read_and_write(sc, phy, 11034 MDIO_CTL_DEVAD, 11035 MDIO_84833_TOP_CFG_XGPHY_STRAP1, 11036 (uint16_t)~MDIO_84833_SUPER_ISOLATE); 11037 } 11038 return rc; 11039 } 11040 11041 static uint8_t elink_848xx_read_status(struct elink_phy *phy, 11042 struct elink_params *params, 11043 struct elink_vars *vars) 11044 { 11045 struct bxe_softc *sc = params->sc; 11046 uint16_t val, val1, val2; 11047 uint8_t link_up = 0; 11048 11049 11050 /* Check 10G-BaseT link status */ 11051 /* Check PMD signal ok */ 11052 elink_cl45_read(sc, phy, 11053 MDIO_AN_DEVAD, 0xFFFA, &val1); 11054 elink_cl45_read(sc, phy, 11055 MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_PMD_SIGNAL, 11056 &val2); 11057 ELINK_DEBUG_P1(sc, "BCM848xx: PMD_SIGNAL 1.a811 = 0x%x\n", val2); 11058 11059 /* Check link 10G */ 11060 if (val2 & (1<<11)) { 11061 vars->line_speed = ELINK_SPEED_10000; 11062 vars->duplex = DUPLEX_FULL; 11063 link_up = 1; 11064 elink_ext_phy_10G_an_resolve(sc, phy, vars); 11065 } else { /* Check Legacy speed link */ 11066 uint16_t legacy_status, legacy_speed, mii_ctrl; 11067 11068 /* Enable expansion register 0x42 (Operation mode status) */ 11069 elink_cl45_write(sc, phy, 11070 MDIO_AN_DEVAD, 11071 MDIO_AN_REG_8481_EXPANSION_REG_ACCESS, 0xf42); 11072 11073 /* Get legacy speed operation status */ 11074 elink_cl45_read(sc, phy, 11075 MDIO_AN_DEVAD, 11076 MDIO_AN_REG_8481_EXPANSION_REG_RD_RW, 11077 &legacy_status); 11078 11079 ELINK_DEBUG_P1(sc, "Legacy speed status = 0x%x\n", 11080 legacy_status); 11081 link_up = ((legacy_status & (1<<11)) == (1<<11)); 11082 legacy_speed = (legacy_status & (3<<9)); 11083 if (legacy_speed == (0<<9)) 11084 vars->line_speed = ELINK_SPEED_10; 11085 else if (legacy_speed == (1<<9)) 11086 vars->line_speed = ELINK_SPEED_100; 11087 else if (legacy_speed == (2<<9)) 11088 vars->line_speed = ELINK_SPEED_1000; 11089 else { /* Should not happen: Treat as link down */ 11090 vars->line_speed = 0; 11091 link_up = 0; 11092 } 11093 11094 if (params->feature_config_flags & 11095 ELINK_FEATURE_CONFIG_IEEE_PHY_TEST) { 11096 elink_cl45_read(sc, phy, 11097 MDIO_AN_DEVAD, 11098 MDIO_AN_REG_8481_LEGACY_MII_CTRL, 11099 &mii_ctrl); 11100 /* For IEEE testing, check for a fake link. */ 11101 link_up |= ((mii_ctrl & 0x3040) == 0x40); 11102 } 11103 11104 if (link_up) { 11105 if (legacy_status & (1<<8)) 11106 vars->duplex = DUPLEX_FULL; 11107 else 11108 vars->duplex = DUPLEX_HALF; 11109 11110 ELINK_DEBUG_P2(sc, 11111 "Link is up in %dMbps, is_duplex_full= %d\n", 11112 vars->line_speed, 11113 (vars->duplex == DUPLEX_FULL)); 11114 /* Check legacy speed AN resolution */ 11115 elink_cl45_read(sc, phy, 11116 MDIO_AN_DEVAD, 11117 MDIO_AN_REG_8481_LEGACY_MII_STATUS, 11118 &val); 11119 if (val & (1<<5)) 11120 vars->link_status |= 11121 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; 11122 elink_cl45_read(sc, phy, 11123 MDIO_AN_DEVAD, 11124 MDIO_AN_REG_8481_LEGACY_AN_EXPANSION, 11125 &val); 11126 if ((val & (1<<0)) == 0) 11127 vars->link_status |= 11128 LINK_STATUS_PARALLEL_DETECTION_USED; 11129 } 11130 } 11131 if (link_up) { 11132 ELINK_DEBUG_P1(sc, "BCM848x3: link speed is %d\n", 11133 vars->line_speed); 11134 elink_ext_phy_resolve_fc(phy, params, vars); 11135 11136 /* Read LP advertised speeds */ 11137 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, 11138 MDIO_AN_REG_CL37_FC_LP, &val); 11139 if (val & (1<<5)) 11140 vars->link_status |= 11141 LINK_STATUS_LINK_PARTNER_10THD_CAPABLE; 11142 if (val & (1<<6)) 11143 vars->link_status |= 11144 LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE; 11145 if (val & (1<<7)) 11146 vars->link_status |= 11147 LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE; 11148 if (val & (1<<8)) 11149 vars->link_status |= 11150 LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE; 11151 if (val & (1<<9)) 11152 vars->link_status |= 11153 LINK_STATUS_LINK_PARTNER_100T4_CAPABLE; 11154 11155 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, 11156 MDIO_AN_REG_1000T_STATUS, &val); 11157 11158 if (val & (1<<10)) 11159 vars->link_status |= 11160 LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE; 11161 if (val & (1<<11)) 11162 vars->link_status |= 11163 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE; 11164 11165 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, 11166 MDIO_AN_REG_MASTER_STATUS, &val); 11167 11168 if (val & (1<<11)) 11169 vars->link_status |= 11170 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; 11171 11172 /* Determine if EEE was negotiated */ 11173 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) || 11174 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) 11175 elink_eee_an_resolve(phy, params, vars); 11176 } 11177 11178 return link_up; 11179 } 11180 11181 static elink_status_t elink_848xx_format_ver(uint32_t raw_ver, uint8_t *str, uint16_t *len) 11182 { 11183 elink_status_t status = ELINK_STATUS_OK; 11184 uint32_t spirom_ver; 11185 spirom_ver = ((raw_ver & 0xF80) >> 7) << 16 | (raw_ver & 0x7F); 11186 status = elink_format_ver(spirom_ver, str, len); 11187 return status; 11188 } 11189 11190 static void elink_8481_hw_reset(struct elink_phy *phy, 11191 struct elink_params *params) 11192 { 11193 elink_cb_gpio_write(params->sc, MISC_REGISTERS_GPIO_1, 11194 MISC_REGISTERS_GPIO_OUTPUT_LOW, 0); 11195 elink_cb_gpio_write(params->sc, MISC_REGISTERS_GPIO_1, 11196 MISC_REGISTERS_GPIO_OUTPUT_LOW, 1); 11197 } 11198 11199 static void elink_8481_link_reset(struct elink_phy *phy, 11200 struct elink_params *params) 11201 { 11202 elink_cl45_write(params->sc, phy, 11203 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000); 11204 elink_cl45_write(params->sc, phy, 11205 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1); 11206 } 11207 11208 static void elink_848x3_link_reset(struct elink_phy *phy, 11209 struct elink_params *params) 11210 { 11211 struct bxe_softc *sc = params->sc; 11212 uint8_t port; 11213 uint16_t val16; 11214 11215 if (!(CHIP_IS_E1x(sc))) 11216 port = SC_PATH(sc); 11217 else 11218 port = params->port; 11219 11220 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) { 11221 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_3, 11222 MISC_REGISTERS_GPIO_OUTPUT_LOW, 11223 port); 11224 } else { 11225 elink_cl45_read(sc, phy, 11226 MDIO_CTL_DEVAD, 11227 MDIO_84833_TOP_CFG_XGPHY_STRAP1, &val16); 11228 val16 |= MDIO_84833_SUPER_ISOLATE; 11229 elink_cl45_write(sc, phy, 11230 MDIO_CTL_DEVAD, 11231 MDIO_84833_TOP_CFG_XGPHY_STRAP1, val16); 11232 } 11233 } 11234 11235 static void elink_848xx_set_link_led(struct elink_phy *phy, 11236 struct elink_params *params, uint8_t mode) 11237 { 11238 struct bxe_softc *sc = params->sc; 11239 uint16_t val; 11240 uint8_t port; 11241 11242 if (!(CHIP_IS_E1x(sc))) 11243 port = SC_PATH(sc); 11244 else 11245 port = params->port; 11246 11247 switch (mode) { 11248 case ELINK_LED_MODE_OFF: 11249 11250 ELINK_DEBUG_P1(sc, "Port 0x%x: LED MODE OFF\n", port); 11251 11252 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) == 11253 SHARED_HW_CFG_LED_EXTPHY1) { 11254 11255 /* Set LED masks */ 11256 elink_cl45_write(sc, phy, 11257 MDIO_PMA_DEVAD, 11258 MDIO_PMA_REG_8481_LED1_MASK, 11259 0x0); 11260 11261 elink_cl45_write(sc, phy, 11262 MDIO_PMA_DEVAD, 11263 MDIO_PMA_REG_8481_LED2_MASK, 11264 0x0); 11265 11266 elink_cl45_write(sc, phy, 11267 MDIO_PMA_DEVAD, 11268 MDIO_PMA_REG_8481_LED3_MASK, 11269 0x0); 11270 11271 elink_cl45_write(sc, phy, 11272 MDIO_PMA_DEVAD, 11273 MDIO_PMA_REG_8481_LED5_MASK, 11274 0x0); 11275 11276 } else { 11277 elink_cl45_write(sc, phy, 11278 MDIO_PMA_DEVAD, 11279 MDIO_PMA_REG_8481_LED1_MASK, 11280 0x0); 11281 } 11282 break; 11283 case ELINK_LED_MODE_FRONT_PANEL_OFF: 11284 11285 ELINK_DEBUG_P1(sc, "Port 0x%x: LED MODE FRONT PANEL OFF\n", 11286 port); 11287 11288 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) == 11289 SHARED_HW_CFG_LED_EXTPHY1) { 11290 11291 /* Set LED masks */ 11292 elink_cl45_write(sc, phy, 11293 MDIO_PMA_DEVAD, 11294 MDIO_PMA_REG_8481_LED1_MASK, 11295 0x0); 11296 11297 elink_cl45_write(sc, phy, 11298 MDIO_PMA_DEVAD, 11299 MDIO_PMA_REG_8481_LED2_MASK, 11300 0x0); 11301 11302 elink_cl45_write(sc, phy, 11303 MDIO_PMA_DEVAD, 11304 MDIO_PMA_REG_8481_LED3_MASK, 11305 0x0); 11306 11307 elink_cl45_write(sc, phy, 11308 MDIO_PMA_DEVAD, 11309 MDIO_PMA_REG_8481_LED5_MASK, 11310 0x20); 11311 11312 } else { 11313 elink_cl45_write(sc, phy, 11314 MDIO_PMA_DEVAD, 11315 MDIO_PMA_REG_8481_LED1_MASK, 11316 0x0); 11317 if (phy->type == 11318 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) { 11319 /* Disable MI_INT interrupt before setting LED4 11320 * source to constant off. 11321 */ 11322 if (REG_RD(sc, NIG_REG_MASK_INTERRUPT_PORT0 + 11323 params->port*4) & 11324 ELINK_NIG_MASK_MI_INT) { 11325 params->link_flags |= 11326 ELINK_LINK_FLAGS_INT_DISABLED; 11327 11328 elink_bits_dis( 11329 sc, 11330 NIG_REG_MASK_INTERRUPT_PORT0 + 11331 params->port*4, 11332 ELINK_NIG_MASK_MI_INT); 11333 } 11334 elink_cl45_write(sc, phy, 11335 MDIO_PMA_DEVAD, 11336 MDIO_PMA_REG_8481_SIGNAL_MASK, 11337 0x0); 11338 } 11339 } 11340 break; 11341 case ELINK_LED_MODE_ON: 11342 11343 ELINK_DEBUG_P1(sc, "Port 0x%x: LED MODE ON\n", port); 11344 11345 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) == 11346 SHARED_HW_CFG_LED_EXTPHY1) { 11347 /* Set control reg */ 11348 elink_cl45_read(sc, phy, 11349 MDIO_PMA_DEVAD, 11350 MDIO_PMA_REG_8481_LINK_SIGNAL, 11351 &val); 11352 val &= 0x8000; 11353 val |= 0x2492; 11354 11355 elink_cl45_write(sc, phy, 11356 MDIO_PMA_DEVAD, 11357 MDIO_PMA_REG_8481_LINK_SIGNAL, 11358 val); 11359 11360 /* Set LED masks */ 11361 elink_cl45_write(sc, phy, 11362 MDIO_PMA_DEVAD, 11363 MDIO_PMA_REG_8481_LED1_MASK, 11364 0x0); 11365 11366 elink_cl45_write(sc, phy, 11367 MDIO_PMA_DEVAD, 11368 MDIO_PMA_REG_8481_LED2_MASK, 11369 0x20); 11370 11371 elink_cl45_write(sc, phy, 11372 MDIO_PMA_DEVAD, 11373 MDIO_PMA_REG_8481_LED3_MASK, 11374 0x20); 11375 11376 elink_cl45_write(sc, phy, 11377 MDIO_PMA_DEVAD, 11378 MDIO_PMA_REG_8481_LED5_MASK, 11379 0x0); 11380 } else { 11381 elink_cl45_write(sc, phy, 11382 MDIO_PMA_DEVAD, 11383 MDIO_PMA_REG_8481_LED1_MASK, 11384 0x20); 11385 if (phy->type == 11386 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) { 11387 /* Disable MI_INT interrupt before setting LED4 11388 * source to constant on. 11389 */ 11390 if (REG_RD(sc, NIG_REG_MASK_INTERRUPT_PORT0 + 11391 params->port*4) & 11392 ELINK_NIG_MASK_MI_INT) { 11393 params->link_flags |= 11394 ELINK_LINK_FLAGS_INT_DISABLED; 11395 11396 elink_bits_dis( 11397 sc, 11398 NIG_REG_MASK_INTERRUPT_PORT0 + 11399 params->port*4, 11400 ELINK_NIG_MASK_MI_INT); 11401 } 11402 elink_cl45_write(sc, phy, 11403 MDIO_PMA_DEVAD, 11404 MDIO_PMA_REG_8481_SIGNAL_MASK, 11405 0x20); 11406 } 11407 } 11408 break; 11409 11410 case ELINK_LED_MODE_OPER: 11411 11412 ELINK_DEBUG_P1(sc, "Port 0x%x: LED MODE OPER\n", port); 11413 11414 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) == 11415 SHARED_HW_CFG_LED_EXTPHY1) { 11416 11417 /* Set control reg */ 11418 elink_cl45_read(sc, phy, 11419 MDIO_PMA_DEVAD, 11420 MDIO_PMA_REG_8481_LINK_SIGNAL, 11421 &val); 11422 11423 if (!((val & 11424 MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK) 11425 >> MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT)) { 11426 ELINK_DEBUG_P0(sc, "Setting LINK_SIGNAL\n"); 11427 elink_cl45_write(sc, phy, 11428 MDIO_PMA_DEVAD, 11429 MDIO_PMA_REG_8481_LINK_SIGNAL, 11430 0xa492); 11431 } 11432 11433 /* Set LED masks */ 11434 elink_cl45_write(sc, phy, 11435 MDIO_PMA_DEVAD, 11436 MDIO_PMA_REG_8481_LED1_MASK, 11437 0x10); 11438 11439 elink_cl45_write(sc, phy, 11440 MDIO_PMA_DEVAD, 11441 MDIO_PMA_REG_8481_LED2_MASK, 11442 0x80); 11443 11444 elink_cl45_write(sc, phy, 11445 MDIO_PMA_DEVAD, 11446 MDIO_PMA_REG_8481_LED3_MASK, 11447 0x98); 11448 11449 elink_cl45_write(sc, phy, 11450 MDIO_PMA_DEVAD, 11451 MDIO_PMA_REG_8481_LED5_MASK, 11452 0x40); 11453 11454 } else { 11455 /* EXTPHY2 LED mode indicate that the 100M/1G/10G LED 11456 * sources are all wired through LED1, rather than only 11457 * 10G in other modes. 11458 */ 11459 val = ((params->hw_led_mode << 11460 SHARED_HW_CFG_LED_MODE_SHIFT) == 11461 SHARED_HW_CFG_LED_EXTPHY2) ? 0x98 : 0x80; 11462 11463 elink_cl45_write(sc, phy, 11464 MDIO_PMA_DEVAD, 11465 MDIO_PMA_REG_8481_LED1_MASK, 11466 val); 11467 11468 /* Tell LED3 to blink on source */ 11469 elink_cl45_read(sc, phy, 11470 MDIO_PMA_DEVAD, 11471 MDIO_PMA_REG_8481_LINK_SIGNAL, 11472 &val); 11473 val &= ~(7<<6); 11474 val |= (1<<6); /* A83B[8:6]= 1 */ 11475 elink_cl45_write(sc, phy, 11476 MDIO_PMA_DEVAD, 11477 MDIO_PMA_REG_8481_LINK_SIGNAL, 11478 val); 11479 if (phy->type == 11480 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) { 11481 /* Restore LED4 source to external link, 11482 * and re-enable interrupts. 11483 */ 11484 elink_cl45_write(sc, phy, 11485 MDIO_PMA_DEVAD, 11486 MDIO_PMA_REG_8481_SIGNAL_MASK, 11487 0x40); 11488 if (params->link_flags & 11489 ELINK_LINK_FLAGS_INT_DISABLED) { 11490 elink_link_int_enable(params); 11491 params->link_flags &= 11492 ~ELINK_LINK_FLAGS_INT_DISABLED; 11493 } 11494 } 11495 } 11496 break; 11497 } 11498 11499 /* This is a workaround for E3+84833 until autoneg 11500 * restart is fixed in f/w 11501 */ 11502 if (CHIP_IS_E3(sc)) { 11503 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, 11504 MDIO_WC_REG_GP2_STATUS_GP_2_1, &val); 11505 } 11506 } 11507 11508 /******************************************************************/ 11509 /* 54618SE PHY SECTION */ 11510 /******************************************************************/ 11511 static void elink_54618se_specific_func(struct elink_phy *phy, 11512 struct elink_params *params, 11513 uint32_t action) 11514 { 11515 struct bxe_softc *sc = params->sc; 11516 uint16_t temp; 11517 switch (action) { 11518 case ELINK_PHY_INIT: 11519 /* Configure LED4: set to INTR (0x6). */ 11520 /* Accessing shadow register 0xe. */ 11521 elink_cl22_write(sc, phy, 11522 MDIO_REG_GPHY_SHADOW, 11523 MDIO_REG_GPHY_SHADOW_LED_SEL2); 11524 elink_cl22_read(sc, phy, 11525 MDIO_REG_GPHY_SHADOW, 11526 &temp); 11527 temp &= ~(0xf << 4); 11528 temp |= (0x6 << 4); 11529 elink_cl22_write(sc, phy, 11530 MDIO_REG_GPHY_SHADOW, 11531 MDIO_REG_GPHY_SHADOW_WR_ENA | temp); 11532 /* Configure INTR based on link status change. */ 11533 elink_cl22_write(sc, phy, 11534 MDIO_REG_INTR_MASK, 11535 ~MDIO_REG_INTR_MASK_LINK_STATUS); 11536 break; 11537 } 11538 } 11539 11540 static elink_status_t elink_54618se_config_init(struct elink_phy *phy, 11541 struct elink_params *params, 11542 struct elink_vars *vars) 11543 { 11544 struct bxe_softc *sc = params->sc; 11545 uint8_t port; 11546 uint16_t autoneg_val, an_1000_val, an_10_100_val, fc_val, temp; 11547 uint32_t cfg_pin; 11548 11549 ELINK_DEBUG_P0(sc, "54618SE cfg init\n"); 11550 DELAY(1000 * 1); 11551 11552 /* This works with E3 only, no need to check the chip 11553 * before determining the port. 11554 */ 11555 port = params->port; 11556 11557 cfg_pin = (REG_RD(sc, params->shmem_base + 11558 offsetof(struct shmem_region, 11559 dev_info.port_hw_config[port].e3_cmn_pin_cfg)) & 11560 PORT_HW_CFG_E3_PHY_RESET_MASK) >> 11561 PORT_HW_CFG_E3_PHY_RESET_SHIFT; 11562 11563 /* Drive pin high to bring the GPHY out of reset. */ 11564 elink_set_cfg_pin(sc, cfg_pin, 1); 11565 11566 /* wait for GPHY to reset */ 11567 DELAY(1000 * 50); 11568 11569 /* reset phy */ 11570 elink_cl22_write(sc, phy, 11571 MDIO_PMA_REG_CTRL, 0x8000); 11572 elink_wait_reset_complete(sc, phy, params); 11573 11574 /* Wait for GPHY to reset */ 11575 DELAY(1000 * 50); 11576 11577 11578 elink_54618se_specific_func(phy, params, ELINK_PHY_INIT); 11579 /* Flip the signal detect polarity (set 0x1c.0x1e[8]). */ 11580 elink_cl22_write(sc, phy, 11581 MDIO_REG_GPHY_SHADOW, 11582 MDIO_REG_GPHY_SHADOW_AUTO_DET_MED); 11583 elink_cl22_read(sc, phy, 11584 MDIO_REG_GPHY_SHADOW, 11585 &temp); 11586 temp |= MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD; 11587 elink_cl22_write(sc, phy, 11588 MDIO_REG_GPHY_SHADOW, 11589 MDIO_REG_GPHY_SHADOW_WR_ENA | temp); 11590 11591 /* Set up fc */ 11592 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */ 11593 elink_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc); 11594 fc_val = 0; 11595 if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) == 11596 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) 11597 fc_val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC; 11598 11599 if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) == 11600 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) 11601 fc_val |= MDIO_AN_REG_ADV_PAUSE_PAUSE; 11602 11603 /* Read all advertisement */ 11604 elink_cl22_read(sc, phy, 11605 0x09, 11606 &an_1000_val); 11607 11608 elink_cl22_read(sc, phy, 11609 0x04, 11610 &an_10_100_val); 11611 11612 elink_cl22_read(sc, phy, 11613 MDIO_PMA_REG_CTRL, 11614 &autoneg_val); 11615 11616 /* Disable forced speed */ 11617 autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13)); 11618 an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8) | (1<<10) | 11619 (1<<11)); 11620 11621 if (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) && 11622 (phy->speed_cap_mask & 11623 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) || 11624 (phy->req_line_speed == ELINK_SPEED_1000)) { 11625 an_1000_val |= (1<<8); 11626 autoneg_val |= (1<<9 | 1<<12); 11627 if (phy->req_duplex == DUPLEX_FULL) 11628 an_1000_val |= (1<<9); 11629 ELINK_DEBUG_P0(sc, "Advertising 1G\n"); 11630 } else 11631 an_1000_val &= ~((1<<8) | (1<<9)); 11632 11633 elink_cl22_write(sc, phy, 11634 0x09, 11635 an_1000_val); 11636 elink_cl22_read(sc, phy, 11637 0x09, 11638 &an_1000_val); 11639 11640 /* Advertise 10/100 link speed */ 11641 if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG) { 11642 if (phy->speed_cap_mask & 11643 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF) { 11644 an_10_100_val |= (1<<5); 11645 autoneg_val |= (1<<9 | 1<<12); 11646 ELINK_DEBUG_P0(sc, "Advertising 10M-HD\n"); 11647 } 11648 if (phy->speed_cap_mask & 11649 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF) { 11650 an_10_100_val |= (1<<6); 11651 autoneg_val |= (1<<9 | 1<<12); 11652 ELINK_DEBUG_P0(sc, "Advertising 10M-FD\n"); 11653 } 11654 if (phy->speed_cap_mask & 11655 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF) { 11656 an_10_100_val |= (1<<7); 11657 autoneg_val |= (1<<9 | 1<<12); 11658 ELINK_DEBUG_P0(sc, "Advertising 100M-HD\n"); 11659 } 11660 if (phy->speed_cap_mask & 11661 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL) { 11662 an_10_100_val |= (1<<8); 11663 autoneg_val |= (1<<9 | 1<<12); 11664 ELINK_DEBUG_P0(sc, "Advertising 100M-FD\n"); 11665 } 11666 } 11667 11668 /* Only 10/100 are allowed to work in FORCE mode */ 11669 if (phy->req_line_speed == ELINK_SPEED_100) { 11670 autoneg_val |= (1<<13); 11671 /* Enabled AUTO-MDIX when autoneg is disabled */ 11672 elink_cl22_write(sc, phy, 11673 0x18, 11674 (1<<15 | 1<<9 | 7<<0)); 11675 ELINK_DEBUG_P0(sc, "Setting 100M force\n"); 11676 } 11677 if (phy->req_line_speed == ELINK_SPEED_10) { 11678 /* Enabled AUTO-MDIX when autoneg is disabled */ 11679 elink_cl22_write(sc, phy, 11680 0x18, 11681 (1<<15 | 1<<9 | 7<<0)); 11682 ELINK_DEBUG_P0(sc, "Setting 10M force\n"); 11683 } 11684 11685 if ((phy->flags & ELINK_FLAGS_EEE) && elink_eee_has_cap(params)) { 11686 elink_status_t rc; 11687 11688 elink_cl22_write(sc, phy, MDIO_REG_GPHY_EXP_ACCESS, 11689 MDIO_REG_GPHY_EXP_ACCESS_TOP | 11690 MDIO_REG_GPHY_EXP_TOP_2K_BUF); 11691 elink_cl22_read(sc, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, &temp); 11692 temp &= 0xfffe; 11693 elink_cl22_write(sc, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, temp); 11694 11695 rc = elink_eee_initial_config(params, vars, SHMEM_EEE_1G_ADV); 11696 if (rc != ELINK_STATUS_OK) { 11697 ELINK_DEBUG_P0(sc, "Failed to configure EEE timers\n"); 11698 elink_eee_disable(phy, params, vars); 11699 } else if ((params->eee_mode & ELINK_EEE_MODE_ADV_LPI) && 11700 (phy->req_duplex == DUPLEX_FULL) && 11701 (elink_eee_calc_timer(params) || 11702 !(params->eee_mode & ELINK_EEE_MODE_ENABLE_LPI))) { 11703 /* Need to advertise EEE only when requested, 11704 * and either no LPI assertion was requested, 11705 * or it was requested and a valid timer was set. 11706 * Also notice full duplex is required for EEE. 11707 */ 11708 elink_eee_advertise(phy, params, vars, 11709 SHMEM_EEE_1G_ADV); 11710 } else { 11711 ELINK_DEBUG_P0(sc, "Don't Advertise 1GBase-T EEE\n"); 11712 elink_eee_disable(phy, params, vars); 11713 } 11714 } else { 11715 vars->eee_status &= ~SHMEM_EEE_1G_ADV << 11716 SHMEM_EEE_SUPPORTED_SHIFT; 11717 11718 if (phy->flags & ELINK_FLAGS_EEE) { 11719 /* Handle legacy auto-grEEEn */ 11720 if (params->feature_config_flags & 11721 ELINK_FEATURE_CONFIG_AUTOGREEEN_ENABLED) { 11722 temp = 6; 11723 ELINK_DEBUG_P0(sc, "Enabling Auto-GrEEEn\n"); 11724 } else { 11725 temp = 0; 11726 ELINK_DEBUG_P0(sc, "Don't Adv. EEE\n"); 11727 } 11728 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, 11729 MDIO_AN_REG_EEE_ADV, temp); 11730 } 11731 } 11732 11733 elink_cl22_write(sc, phy, 11734 0x04, 11735 an_10_100_val | fc_val); 11736 11737 if (phy->req_duplex == DUPLEX_FULL) 11738 autoneg_val |= (1<<8); 11739 11740 elink_cl22_write(sc, phy, 11741 MDIO_PMA_REG_CTRL, autoneg_val); 11742 11743 return ELINK_STATUS_OK; 11744 } 11745 11746 11747 static void elink_5461x_set_link_led(struct elink_phy *phy, 11748 struct elink_params *params, uint8_t mode) 11749 { 11750 struct bxe_softc *sc = params->sc; 11751 uint16_t temp; 11752 11753 elink_cl22_write(sc, phy, 11754 MDIO_REG_GPHY_SHADOW, 11755 MDIO_REG_GPHY_SHADOW_LED_SEL1); 11756 elink_cl22_read(sc, phy, 11757 MDIO_REG_GPHY_SHADOW, 11758 &temp); 11759 temp &= 0xff00; 11760 11761 ELINK_DEBUG_P1(sc, "54618x set link led (mode=%x)\n", mode); 11762 switch (mode) { 11763 case ELINK_LED_MODE_FRONT_PANEL_OFF: 11764 case ELINK_LED_MODE_OFF: 11765 temp |= 0x00ee; 11766 break; 11767 case ELINK_LED_MODE_OPER: 11768 temp |= 0x0001; 11769 break; 11770 case ELINK_LED_MODE_ON: 11771 temp |= 0x00ff; 11772 break; 11773 default: 11774 break; 11775 } 11776 elink_cl22_write(sc, phy, 11777 MDIO_REG_GPHY_SHADOW, 11778 MDIO_REG_GPHY_SHADOW_WR_ENA | temp); 11779 return; 11780 } 11781 11782 11783 static void elink_54618se_link_reset(struct elink_phy *phy, 11784 struct elink_params *params) 11785 { 11786 struct bxe_softc *sc = params->sc; 11787 uint32_t cfg_pin; 11788 uint8_t port; 11789 11790 /* In case of no EPIO routed to reset the GPHY, put it 11791 * in low power mode. 11792 */ 11793 elink_cl22_write(sc, phy, MDIO_PMA_REG_CTRL, 0x800); 11794 /* This works with E3 only, no need to check the chip 11795 * before determining the port. 11796 */ 11797 port = params->port; 11798 cfg_pin = (REG_RD(sc, params->shmem_base + 11799 offsetof(struct shmem_region, 11800 dev_info.port_hw_config[port].e3_cmn_pin_cfg)) & 11801 PORT_HW_CFG_E3_PHY_RESET_MASK) >> 11802 PORT_HW_CFG_E3_PHY_RESET_SHIFT; 11803 11804 /* Drive pin low to put GPHY in reset. */ 11805 elink_set_cfg_pin(sc, cfg_pin, 0); 11806 } 11807 11808 static uint8_t elink_54618se_read_status(struct elink_phy *phy, 11809 struct elink_params *params, 11810 struct elink_vars *vars) 11811 { 11812 struct bxe_softc *sc = params->sc; 11813 uint16_t val; 11814 uint8_t link_up = 0; 11815 uint16_t legacy_status, legacy_speed; 11816 11817 /* Get speed operation status */ 11818 elink_cl22_read(sc, phy, 11819 MDIO_REG_GPHY_AUX_STATUS, 11820 &legacy_status); 11821 ELINK_DEBUG_P1(sc, "54618SE read_status: 0x%x\n", legacy_status); 11822 11823 /* Read status to clear the PHY interrupt. */ 11824 elink_cl22_read(sc, phy, 11825 MDIO_REG_INTR_STATUS, 11826 &val); 11827 11828 link_up = ((legacy_status & (1<<2)) == (1<<2)); 11829 11830 if (link_up) { 11831 legacy_speed = (legacy_status & (7<<8)); 11832 if (legacy_speed == (7<<8)) { 11833 vars->line_speed = ELINK_SPEED_1000; 11834 vars->duplex = DUPLEX_FULL; 11835 } else if (legacy_speed == (6<<8)) { 11836 vars->line_speed = ELINK_SPEED_1000; 11837 vars->duplex = DUPLEX_HALF; 11838 } else if (legacy_speed == (5<<8)) { 11839 vars->line_speed = ELINK_SPEED_100; 11840 vars->duplex = DUPLEX_FULL; 11841 } 11842 /* Omitting 100Base-T4 for now */ 11843 else if (legacy_speed == (3<<8)) { 11844 vars->line_speed = ELINK_SPEED_100; 11845 vars->duplex = DUPLEX_HALF; 11846 } else if (legacy_speed == (2<<8)) { 11847 vars->line_speed = ELINK_SPEED_10; 11848 vars->duplex = DUPLEX_FULL; 11849 } else if (legacy_speed == (1<<8)) { 11850 vars->line_speed = ELINK_SPEED_10; 11851 vars->duplex = DUPLEX_HALF; 11852 } else /* Should not happen */ 11853 vars->line_speed = 0; 11854 11855 ELINK_DEBUG_P2(sc, 11856 "Link is up in %dMbps, is_duplex_full= %d\n", 11857 vars->line_speed, 11858 (vars->duplex == DUPLEX_FULL)); 11859 11860 /* Check legacy speed AN resolution */ 11861 elink_cl22_read(sc, phy, 11862 0x01, 11863 &val); 11864 if (val & (1<<5)) 11865 vars->link_status |= 11866 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE; 11867 elink_cl22_read(sc, phy, 11868 0x06, 11869 &val); 11870 if ((val & (1<<0)) == 0) 11871 vars->link_status |= 11872 LINK_STATUS_PARALLEL_DETECTION_USED; 11873 11874 ELINK_DEBUG_P1(sc, "BCM54618SE: link speed is %d\n", 11875 vars->line_speed); 11876 11877 elink_ext_phy_resolve_fc(phy, params, vars); 11878 11879 if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) { 11880 /* Report LP advertised speeds */ 11881 elink_cl22_read(sc, phy, 0x5, &val); 11882 11883 if (val & (1<<5)) 11884 vars->link_status |= 11885 LINK_STATUS_LINK_PARTNER_10THD_CAPABLE; 11886 if (val & (1<<6)) 11887 vars->link_status |= 11888 LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE; 11889 if (val & (1<<7)) 11890 vars->link_status |= 11891 LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE; 11892 if (val & (1<<8)) 11893 vars->link_status |= 11894 LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE; 11895 if (val & (1<<9)) 11896 vars->link_status |= 11897 LINK_STATUS_LINK_PARTNER_100T4_CAPABLE; 11898 11899 elink_cl22_read(sc, phy, 0xa, &val); 11900 if (val & (1<<10)) 11901 vars->link_status |= 11902 LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE; 11903 if (val & (1<<11)) 11904 vars->link_status |= 11905 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE; 11906 11907 if ((phy->flags & ELINK_FLAGS_EEE) && 11908 elink_eee_has_cap(params)) 11909 elink_eee_an_resolve(phy, params, vars); 11910 } 11911 } 11912 return link_up; 11913 } 11914 11915 static void elink_54618se_config_loopback(struct elink_phy *phy, 11916 struct elink_params *params) 11917 { 11918 struct bxe_softc *sc = params->sc; 11919 uint16_t val; 11920 uint32_t umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0; 11921 11922 ELINK_DEBUG_P0(sc, "2PMA/PMD ext_phy_loopback: 54618se\n"); 11923 11924 /* Enable master/slave manual mmode and set to master */ 11925 /* mii write 9 [bits set 11 12] */ 11926 elink_cl22_write(sc, phy, 0x09, 3<<11); 11927 11928 /* forced 1G and disable autoneg */ 11929 /* set val [mii read 0] */ 11930 /* set val [expr $val & [bits clear 6 12 13]] */ 11931 /* set val [expr $val | [bits set 6 8]] */ 11932 /* mii write 0 $val */ 11933 elink_cl22_read(sc, phy, 0x00, &val); 11934 val &= ~((1<<6) | (1<<12) | (1<<13)); 11935 val |= (1<<6) | (1<<8); 11936 elink_cl22_write(sc, phy, 0x00, val); 11937 11938 /* Set external loopback and Tx using 6dB coding */ 11939 /* mii write 0x18 7 */ 11940 /* set val [mii read 0x18] */ 11941 /* mii write 0x18 [expr $val | [bits set 10 15]] */ 11942 elink_cl22_write(sc, phy, 0x18, 7); 11943 elink_cl22_read(sc, phy, 0x18, &val); 11944 elink_cl22_write(sc, phy, 0x18, val | (1<<10) | (1<<15)); 11945 11946 /* This register opens the gate for the UMAC despite its name */ 11947 REG_WR(sc, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1); 11948 11949 /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame 11950 * length used by the MAC receive logic to check frames. 11951 */ 11952 REG_WR(sc, umac_base + UMAC_REG_MAXFR, 0x2710); 11953 } 11954 11955 /******************************************************************/ 11956 /* SFX7101 PHY SECTION */ 11957 /******************************************************************/ 11958 static void elink_7101_config_loopback(struct elink_phy *phy, 11959 struct elink_params *params) 11960 { 11961 struct bxe_softc *sc = params->sc; 11962 /* SFX7101_XGXS_TEST1 */ 11963 elink_cl45_write(sc, phy, 11964 MDIO_XS_DEVAD, MDIO_XS_SFX7101_XGXS_TEST1, 0x100); 11965 } 11966 11967 static elink_status_t elink_7101_config_init(struct elink_phy *phy, 11968 struct elink_params *params, 11969 struct elink_vars *vars) 11970 { 11971 uint16_t fw_ver1, fw_ver2, val; 11972 struct bxe_softc *sc = params->sc; 11973 ELINK_DEBUG_P0(sc, "Setting the SFX7101 LASI indication\n"); 11974 11975 /* Restore normal power mode*/ 11976 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2, 11977 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port); 11978 /* HW reset */ 11979 elink_ext_phy_hw_reset(sc, params->port); 11980 elink_wait_reset_complete(sc, phy, params); 11981 11982 elink_cl45_write(sc, phy, 11983 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x1); 11984 ELINK_DEBUG_P0(sc, "Setting the SFX7101 LED to blink on traffic\n"); 11985 elink_cl45_write(sc, phy, 11986 MDIO_PMA_DEVAD, MDIO_PMA_REG_7107_LED_CNTL, (1<<3)); 11987 11988 elink_ext_phy_set_pause(params, phy, vars); 11989 /* Restart autoneg */ 11990 elink_cl45_read(sc, phy, 11991 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, &val); 11992 val |= 0x200; 11993 elink_cl45_write(sc, phy, 11994 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, val); 11995 11996 /* Save spirom version */ 11997 elink_cl45_read(sc, phy, 11998 MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER1, &fw_ver1); 11999 12000 elink_cl45_read(sc, phy, 12001 MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER2, &fw_ver2); 12002 elink_save_spirom_version(sc, params->port, 12003 (uint32_t)(fw_ver1<<16 | fw_ver2), phy->ver_addr); 12004 return ELINK_STATUS_OK; 12005 } 12006 12007 static uint8_t elink_7101_read_status(struct elink_phy *phy, 12008 struct elink_params *params, 12009 struct elink_vars *vars) 12010 { 12011 struct bxe_softc *sc = params->sc; 12012 uint8_t link_up; 12013 uint16_t val1, val2; 12014 elink_cl45_read(sc, phy, 12015 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2); 12016 elink_cl45_read(sc, phy, 12017 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1); 12018 ELINK_DEBUG_P2(sc, "10G-base-T LASI status 0x%x->0x%x\n", 12019 val2, val1); 12020 elink_cl45_read(sc, phy, 12021 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2); 12022 elink_cl45_read(sc, phy, 12023 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1); 12024 ELINK_DEBUG_P2(sc, "10G-base-T PMA status 0x%x->0x%x\n", 12025 val2, val1); 12026 link_up = ((val1 & 4) == 4); 12027 /* If link is up print the AN outcome of the SFX7101 PHY */ 12028 if (link_up) { 12029 elink_cl45_read(sc, phy, 12030 MDIO_AN_DEVAD, MDIO_AN_REG_MASTER_STATUS, 12031 &val2); 12032 vars->line_speed = ELINK_SPEED_10000; 12033 vars->duplex = DUPLEX_FULL; 12034 ELINK_DEBUG_P2(sc, "SFX7101 AN status 0x%x->Master=%x\n", 12035 val2, (val2 & (1<<14))); 12036 elink_ext_phy_10G_an_resolve(sc, phy, vars); 12037 elink_ext_phy_resolve_fc(phy, params, vars); 12038 12039 /* Read LP advertised speeds */ 12040 if (val2 & (1<<11)) 12041 vars->link_status |= 12042 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE; 12043 } 12044 return link_up; 12045 } 12046 12047 static elink_status_t elink_7101_format_ver(uint32_t spirom_ver, uint8_t *str, uint16_t *len) 12048 { 12049 if (*len < 5) 12050 return ELINK_STATUS_ERROR; 12051 str[0] = (spirom_ver & 0xFF); 12052 str[1] = (spirom_ver & 0xFF00) >> 8; 12053 str[2] = (spirom_ver & 0xFF0000) >> 16; 12054 str[3] = (spirom_ver & 0xFF000000) >> 24; 12055 str[4] = '\0'; 12056 *len -= 5; 12057 return ELINK_STATUS_OK; 12058 } 12059 12060 void elink_sfx7101_sp_sw_reset(struct bxe_softc *sc, struct elink_phy *phy) 12061 { 12062 uint16_t val, cnt; 12063 12064 elink_cl45_read(sc, phy, 12065 MDIO_PMA_DEVAD, 12066 MDIO_PMA_REG_7101_RESET, &val); 12067 12068 for (cnt = 0; cnt < 10; cnt++) { 12069 DELAY(1000 * 50); 12070 /* Writes a self-clearing reset */ 12071 elink_cl45_write(sc, phy, 12072 MDIO_PMA_DEVAD, 12073 MDIO_PMA_REG_7101_RESET, 12074 (val | (1<<15))); 12075 /* Wait for clear */ 12076 elink_cl45_read(sc, phy, 12077 MDIO_PMA_DEVAD, 12078 MDIO_PMA_REG_7101_RESET, &val); 12079 12080 if ((val & (1<<15)) == 0) 12081 break; 12082 } 12083 } 12084 12085 static void elink_7101_hw_reset(struct elink_phy *phy, 12086 struct elink_params *params) { 12087 /* Low power mode is controlled by GPIO 2 */ 12088 elink_cb_gpio_write(params->sc, MISC_REGISTERS_GPIO_2, 12089 MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port); 12090 /* The PHY reset is controlled by GPIO 1 */ 12091 elink_cb_gpio_write(params->sc, MISC_REGISTERS_GPIO_1, 12092 MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port); 12093 } 12094 12095 static void elink_7101_set_link_led(struct elink_phy *phy, 12096 struct elink_params *params, uint8_t mode) 12097 { 12098 uint16_t val = 0; 12099 struct bxe_softc *sc = params->sc; 12100 switch (mode) { 12101 case ELINK_LED_MODE_FRONT_PANEL_OFF: 12102 case ELINK_LED_MODE_OFF: 12103 val = 2; 12104 break; 12105 case ELINK_LED_MODE_ON: 12106 val = 1; 12107 break; 12108 case ELINK_LED_MODE_OPER: 12109 val = 0; 12110 break; 12111 } 12112 elink_cl45_write(sc, phy, 12113 MDIO_PMA_DEVAD, 12114 MDIO_PMA_REG_7107_LINK_LED_CNTL, 12115 val); 12116 } 12117 12118 /******************************************************************/ 12119 /* STATIC PHY DECLARATION */ 12120 /******************************************************************/ 12121 12122 static const struct elink_phy phy_null = { 12123 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN, 12124 .addr = 0, 12125 .def_md_devad = 0, 12126 .flags = ELINK_FLAGS_INIT_XGXS_FIRST, 12127 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 12128 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 12129 .mdio_ctrl = 0, 12130 .supported = 0, 12131 .media_type = ELINK_ETH_PHY_NOT_PRESENT, 12132 .ver_addr = 0, 12133 .req_flow_ctrl = 0, 12134 .req_line_speed = 0, 12135 .speed_cap_mask = 0, 12136 .req_duplex = 0, 12137 .rsrv = 0, 12138 .config_init = (config_init_t)NULL, 12139 .read_status = (read_status_t)NULL, 12140 .link_reset = (link_reset_t)NULL, 12141 .config_loopback = (config_loopback_t)NULL, 12142 .format_fw_ver = (format_fw_ver_t)NULL, 12143 .hw_reset = (hw_reset_t)NULL, 12144 .set_link_led = (set_link_led_t)NULL, 12145 .phy_specific_func = (phy_specific_func_t)NULL 12146 }; 12147 12148 static const struct elink_phy phy_serdes = { 12149 .type = PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT, 12150 .addr = 0xff, 12151 .def_md_devad = 0, 12152 .flags = 0, 12153 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 12154 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 12155 .mdio_ctrl = 0, 12156 .supported = (ELINK_SUPPORTED_10baseT_Half | 12157 ELINK_SUPPORTED_10baseT_Full | 12158 ELINK_SUPPORTED_100baseT_Half | 12159 ELINK_SUPPORTED_100baseT_Full | 12160 ELINK_SUPPORTED_1000baseT_Full | 12161 ELINK_SUPPORTED_2500baseX_Full | 12162 ELINK_SUPPORTED_TP | 12163 ELINK_SUPPORTED_Autoneg | 12164 ELINK_SUPPORTED_Pause | 12165 ELINK_SUPPORTED_Asym_Pause), 12166 .media_type = ELINK_ETH_PHY_BASE_T, 12167 .ver_addr = 0, 12168 .req_flow_ctrl = 0, 12169 .req_line_speed = 0, 12170 .speed_cap_mask = 0, 12171 .req_duplex = 0, 12172 .rsrv = 0, 12173 .config_init = (config_init_t)elink_xgxs_config_init, 12174 .read_status = (read_status_t)elink_link_settings_status, 12175 .link_reset = (link_reset_t)elink_int_link_reset, 12176 .config_loopback = (config_loopback_t)NULL, 12177 .format_fw_ver = (format_fw_ver_t)NULL, 12178 .hw_reset = (hw_reset_t)NULL, 12179 .set_link_led = (set_link_led_t)NULL, 12180 .phy_specific_func = (phy_specific_func_t)NULL 12181 }; 12182 12183 static const struct elink_phy phy_xgxs = { 12184 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT, 12185 .addr = 0xff, 12186 .def_md_devad = 0, 12187 .flags = 0, 12188 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 12189 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 12190 .mdio_ctrl = 0, 12191 .supported = (ELINK_SUPPORTED_10baseT_Half | 12192 ELINK_SUPPORTED_10baseT_Full | 12193 ELINK_SUPPORTED_100baseT_Half | 12194 ELINK_SUPPORTED_100baseT_Full | 12195 ELINK_SUPPORTED_1000baseT_Full | 12196 ELINK_SUPPORTED_2500baseX_Full | 12197 ELINK_SUPPORTED_10000baseT_Full | 12198 ELINK_SUPPORTED_FIBRE | 12199 ELINK_SUPPORTED_Autoneg | 12200 ELINK_SUPPORTED_Pause | 12201 ELINK_SUPPORTED_Asym_Pause), 12202 .media_type = ELINK_ETH_PHY_CX4, 12203 .ver_addr = 0, 12204 .req_flow_ctrl = 0, 12205 .req_line_speed = 0, 12206 .speed_cap_mask = 0, 12207 .req_duplex = 0, 12208 .rsrv = 0, 12209 .config_init = (config_init_t)elink_xgxs_config_init, 12210 .read_status = (read_status_t)elink_link_settings_status, 12211 .link_reset = (link_reset_t)elink_int_link_reset, 12212 .config_loopback = (config_loopback_t)elink_set_xgxs_loopback, 12213 .format_fw_ver = (format_fw_ver_t)NULL, 12214 .hw_reset = (hw_reset_t)NULL, 12215 .set_link_led = (set_link_led_t)NULL, 12216 .phy_specific_func = (phy_specific_func_t)elink_xgxs_specific_func 12217 }; 12218 static const struct elink_phy phy_warpcore = { 12219 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT, 12220 .addr = 0xff, 12221 .def_md_devad = 0, 12222 .flags = ELINK_FLAGS_TX_ERROR_CHECK, 12223 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 12224 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 12225 .mdio_ctrl = 0, 12226 .supported = (ELINK_SUPPORTED_10baseT_Half | 12227 ELINK_SUPPORTED_10baseT_Full | 12228 ELINK_SUPPORTED_100baseT_Half | 12229 ELINK_SUPPORTED_100baseT_Full | 12230 ELINK_SUPPORTED_1000baseT_Full | 12231 ELINK_SUPPORTED_10000baseT_Full | 12232 ELINK_SUPPORTED_20000baseKR2_Full | 12233 ELINK_SUPPORTED_20000baseMLD2_Full | 12234 ELINK_SUPPORTED_FIBRE | 12235 ELINK_SUPPORTED_Autoneg | 12236 ELINK_SUPPORTED_Pause | 12237 ELINK_SUPPORTED_Asym_Pause), 12238 .media_type = ELINK_ETH_PHY_UNSPECIFIED, 12239 .ver_addr = 0, 12240 .req_flow_ctrl = 0, 12241 .req_line_speed = 0, 12242 .speed_cap_mask = 0, 12243 /* req_duplex = */0, 12244 /* rsrv = */0, 12245 .config_init = (config_init_t)elink_warpcore_config_init, 12246 .read_status = (read_status_t)elink_warpcore_read_status, 12247 .link_reset = (link_reset_t)elink_warpcore_link_reset, 12248 .config_loopback = (config_loopback_t)elink_set_warpcore_loopback, 12249 .format_fw_ver = (format_fw_ver_t)NULL, 12250 .hw_reset = (hw_reset_t)elink_warpcore_hw_reset, 12251 .set_link_led = (set_link_led_t)NULL, 12252 .phy_specific_func = (phy_specific_func_t)NULL 12253 }; 12254 12255 12256 static const struct elink_phy phy_7101 = { 12257 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101, 12258 .addr = 0xff, 12259 .def_md_devad = 0, 12260 .flags = ELINK_FLAGS_FAN_FAILURE_DET_REQ, 12261 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 12262 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 12263 .mdio_ctrl = 0, 12264 .supported = (ELINK_SUPPORTED_10000baseT_Full | 12265 ELINK_SUPPORTED_TP | 12266 ELINK_SUPPORTED_Autoneg | 12267 ELINK_SUPPORTED_Pause | 12268 ELINK_SUPPORTED_Asym_Pause), 12269 .media_type = ELINK_ETH_PHY_BASE_T, 12270 .ver_addr = 0, 12271 .req_flow_ctrl = 0, 12272 .req_line_speed = 0, 12273 .speed_cap_mask = 0, 12274 .req_duplex = 0, 12275 .rsrv = 0, 12276 .config_init = (config_init_t)elink_7101_config_init, 12277 .read_status = (read_status_t)elink_7101_read_status, 12278 .link_reset = (link_reset_t)elink_common_ext_link_reset, 12279 .config_loopback = (config_loopback_t)elink_7101_config_loopback, 12280 .format_fw_ver = (format_fw_ver_t)elink_7101_format_ver, 12281 .hw_reset = (hw_reset_t)elink_7101_hw_reset, 12282 .set_link_led = (set_link_led_t)elink_7101_set_link_led, 12283 .phy_specific_func = (phy_specific_func_t)NULL 12284 }; 12285 static const struct elink_phy phy_8073 = { 12286 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073, 12287 .addr = 0xff, 12288 .def_md_devad = 0, 12289 .flags = 0, 12290 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 12291 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 12292 .mdio_ctrl = 0, 12293 .supported = (ELINK_SUPPORTED_10000baseT_Full | 12294 ELINK_SUPPORTED_2500baseX_Full | 12295 ELINK_SUPPORTED_1000baseT_Full | 12296 ELINK_SUPPORTED_FIBRE | 12297 ELINK_SUPPORTED_Autoneg | 12298 ELINK_SUPPORTED_Pause | 12299 ELINK_SUPPORTED_Asym_Pause), 12300 .media_type = ELINK_ETH_PHY_KR, 12301 .ver_addr = 0, 12302 .req_flow_ctrl = 0, 12303 .req_line_speed = 0, 12304 .speed_cap_mask = 0, 12305 .req_duplex = 0, 12306 .rsrv = 0, 12307 .config_init = (config_init_t)elink_8073_config_init, 12308 .read_status = (read_status_t)elink_8073_read_status, 12309 .link_reset = (link_reset_t)elink_8073_link_reset, 12310 .config_loopback = (config_loopback_t)NULL, 12311 .format_fw_ver = (format_fw_ver_t)elink_format_ver, 12312 .hw_reset = (hw_reset_t)NULL, 12313 .set_link_led = (set_link_led_t)NULL, 12314 .phy_specific_func = (phy_specific_func_t)elink_8073_specific_func 12315 }; 12316 static const struct elink_phy phy_8705 = { 12317 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705, 12318 .addr = 0xff, 12319 .def_md_devad = 0, 12320 .flags = ELINK_FLAGS_INIT_XGXS_FIRST, 12321 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 12322 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 12323 .mdio_ctrl = 0, 12324 .supported = (ELINK_SUPPORTED_10000baseT_Full | 12325 ELINK_SUPPORTED_FIBRE | 12326 ELINK_SUPPORTED_Pause | 12327 ELINK_SUPPORTED_Asym_Pause), 12328 .media_type = ELINK_ETH_PHY_XFP_FIBER, 12329 .ver_addr = 0, 12330 .req_flow_ctrl = 0, 12331 .req_line_speed = 0, 12332 .speed_cap_mask = 0, 12333 .req_duplex = 0, 12334 .rsrv = 0, 12335 .config_init = (config_init_t)elink_8705_config_init, 12336 .read_status = (read_status_t)elink_8705_read_status, 12337 .link_reset = (link_reset_t)elink_common_ext_link_reset, 12338 .config_loopback = (config_loopback_t)NULL, 12339 .format_fw_ver = (format_fw_ver_t)elink_null_format_ver, 12340 .hw_reset = (hw_reset_t)NULL, 12341 .set_link_led = (set_link_led_t)NULL, 12342 .phy_specific_func = (phy_specific_func_t)NULL 12343 }; 12344 static const struct elink_phy phy_8706 = { 12345 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706, 12346 .addr = 0xff, 12347 .def_md_devad = 0, 12348 .flags = ELINK_FLAGS_INIT_XGXS_FIRST, 12349 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 12350 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 12351 .mdio_ctrl = 0, 12352 .supported = (ELINK_SUPPORTED_10000baseT_Full | 12353 ELINK_SUPPORTED_1000baseT_Full | 12354 ELINK_SUPPORTED_FIBRE | 12355 ELINK_SUPPORTED_Pause | 12356 ELINK_SUPPORTED_Asym_Pause), 12357 .media_type = ELINK_ETH_PHY_SFPP_10G_FIBER, 12358 .ver_addr = 0, 12359 .req_flow_ctrl = 0, 12360 .req_line_speed = 0, 12361 .speed_cap_mask = 0, 12362 .req_duplex = 0, 12363 .rsrv = 0, 12364 .config_init = (config_init_t)elink_8706_config_init, 12365 .read_status = (read_status_t)elink_8706_read_status, 12366 .link_reset = (link_reset_t)elink_common_ext_link_reset, 12367 .config_loopback = (config_loopback_t)NULL, 12368 .format_fw_ver = (format_fw_ver_t)elink_format_ver, 12369 .hw_reset = (hw_reset_t)NULL, 12370 .set_link_led = (set_link_led_t)NULL, 12371 .phy_specific_func = (phy_specific_func_t)NULL 12372 }; 12373 12374 static const struct elink_phy phy_8726 = { 12375 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726, 12376 .addr = 0xff, 12377 .def_md_devad = 0, 12378 .flags = (ELINK_FLAGS_INIT_XGXS_FIRST | 12379 ELINK_FLAGS_TX_ERROR_CHECK), 12380 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 12381 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 12382 .mdio_ctrl = 0, 12383 .supported = (ELINK_SUPPORTED_10000baseT_Full | 12384 ELINK_SUPPORTED_1000baseT_Full | 12385 ELINK_SUPPORTED_Autoneg | 12386 ELINK_SUPPORTED_FIBRE | 12387 ELINK_SUPPORTED_Pause | 12388 ELINK_SUPPORTED_Asym_Pause), 12389 .media_type = ELINK_ETH_PHY_NOT_PRESENT, 12390 .ver_addr = 0, 12391 .req_flow_ctrl = 0, 12392 .req_line_speed = 0, 12393 .speed_cap_mask = 0, 12394 .req_duplex = 0, 12395 .rsrv = 0, 12396 .config_init = (config_init_t)elink_8726_config_init, 12397 .read_status = (read_status_t)elink_8726_read_status, 12398 .link_reset = (link_reset_t)elink_8726_link_reset, 12399 .config_loopback = (config_loopback_t)elink_8726_config_loopback, 12400 .format_fw_ver = (format_fw_ver_t)elink_format_ver, 12401 .hw_reset = (hw_reset_t)NULL, 12402 .set_link_led = (set_link_led_t)NULL, 12403 .phy_specific_func = (phy_specific_func_t)NULL 12404 }; 12405 12406 static const struct elink_phy phy_8727 = { 12407 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727, 12408 .addr = 0xff, 12409 .def_md_devad = 0, 12410 .flags = (ELINK_FLAGS_FAN_FAILURE_DET_REQ | 12411 ELINK_FLAGS_TX_ERROR_CHECK), 12412 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 12413 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 12414 .mdio_ctrl = 0, 12415 .supported = (ELINK_SUPPORTED_10000baseT_Full | 12416 ELINK_SUPPORTED_1000baseT_Full | 12417 ELINK_SUPPORTED_FIBRE | 12418 ELINK_SUPPORTED_Pause | 12419 ELINK_SUPPORTED_Asym_Pause), 12420 .media_type = ELINK_ETH_PHY_NOT_PRESENT, 12421 .ver_addr = 0, 12422 .req_flow_ctrl = 0, 12423 .req_line_speed = 0, 12424 .speed_cap_mask = 0, 12425 .req_duplex = 0, 12426 .rsrv = 0, 12427 .config_init = (config_init_t)elink_8727_config_init, 12428 .read_status = (read_status_t)elink_8727_read_status, 12429 .link_reset = (link_reset_t)elink_8727_link_reset, 12430 .config_loopback = (config_loopback_t)NULL, 12431 .format_fw_ver = (format_fw_ver_t)elink_format_ver, 12432 .hw_reset = (hw_reset_t)elink_8727_hw_reset, 12433 .set_link_led = (set_link_led_t)elink_8727_set_link_led, 12434 .phy_specific_func = (phy_specific_func_t)elink_8727_specific_func 12435 }; 12436 static const struct elink_phy phy_8481 = { 12437 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481, 12438 .addr = 0xff, 12439 .def_md_devad = 0, 12440 .flags = ELINK_FLAGS_FAN_FAILURE_DET_REQ | 12441 ELINK_FLAGS_REARM_LATCH_SIGNAL, 12442 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 12443 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 12444 .mdio_ctrl = 0, 12445 .supported = (ELINK_SUPPORTED_10baseT_Half | 12446 ELINK_SUPPORTED_10baseT_Full | 12447 ELINK_SUPPORTED_100baseT_Half | 12448 ELINK_SUPPORTED_100baseT_Full | 12449 ELINK_SUPPORTED_1000baseT_Full | 12450 ELINK_SUPPORTED_10000baseT_Full | 12451 ELINK_SUPPORTED_TP | 12452 ELINK_SUPPORTED_Autoneg | 12453 ELINK_SUPPORTED_Pause | 12454 ELINK_SUPPORTED_Asym_Pause), 12455 .media_type = ELINK_ETH_PHY_BASE_T, 12456 .ver_addr = 0, 12457 .req_flow_ctrl = 0, 12458 .req_line_speed = 0, 12459 .speed_cap_mask = 0, 12460 .req_duplex = 0, 12461 .rsrv = 0, 12462 .config_init = (config_init_t)elink_8481_config_init, 12463 .read_status = (read_status_t)elink_848xx_read_status, 12464 .link_reset = (link_reset_t)elink_8481_link_reset, 12465 .config_loopback = (config_loopback_t)NULL, 12466 .format_fw_ver = (format_fw_ver_t)elink_848xx_format_ver, 12467 .hw_reset = (hw_reset_t)elink_8481_hw_reset, 12468 .set_link_led = (set_link_led_t)elink_848xx_set_link_led, 12469 .phy_specific_func = (phy_specific_func_t)NULL 12470 }; 12471 12472 static const struct elink_phy phy_84823 = { 12473 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823, 12474 .addr = 0xff, 12475 .def_md_devad = 0, 12476 .flags = (ELINK_FLAGS_FAN_FAILURE_DET_REQ | 12477 ELINK_FLAGS_REARM_LATCH_SIGNAL | 12478 ELINK_FLAGS_TX_ERROR_CHECK), 12479 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 12480 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 12481 .mdio_ctrl = 0, 12482 .supported = (ELINK_SUPPORTED_10baseT_Half | 12483 ELINK_SUPPORTED_10baseT_Full | 12484 ELINK_SUPPORTED_100baseT_Half | 12485 ELINK_SUPPORTED_100baseT_Full | 12486 ELINK_SUPPORTED_1000baseT_Full | 12487 ELINK_SUPPORTED_10000baseT_Full | 12488 ELINK_SUPPORTED_TP | 12489 ELINK_SUPPORTED_Autoneg | 12490 ELINK_SUPPORTED_Pause | 12491 ELINK_SUPPORTED_Asym_Pause), 12492 .media_type = ELINK_ETH_PHY_BASE_T, 12493 .ver_addr = 0, 12494 .req_flow_ctrl = 0, 12495 .req_line_speed = 0, 12496 .speed_cap_mask = 0, 12497 .req_duplex = 0, 12498 .rsrv = 0, 12499 .config_init = (config_init_t)elink_848x3_config_init, 12500 .read_status = (read_status_t)elink_848xx_read_status, 12501 .link_reset = (link_reset_t)elink_848x3_link_reset, 12502 .config_loopback = (config_loopback_t)NULL, 12503 .format_fw_ver = (format_fw_ver_t)elink_848xx_format_ver, 12504 .hw_reset = (hw_reset_t)NULL, 12505 .set_link_led = (set_link_led_t)elink_848xx_set_link_led, 12506 .phy_specific_func = (phy_specific_func_t)elink_848xx_specific_func 12507 }; 12508 12509 static const struct elink_phy phy_84833 = { 12510 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833, 12511 .addr = 0xff, 12512 .def_md_devad = 0, 12513 .flags = (ELINK_FLAGS_FAN_FAILURE_DET_REQ | 12514 ELINK_FLAGS_REARM_LATCH_SIGNAL | 12515 ELINK_FLAGS_TX_ERROR_CHECK | 12516 ELINK_FLAGS_TEMPERATURE), 12517 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 12518 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 12519 .mdio_ctrl = 0, 12520 .supported = (ELINK_SUPPORTED_100baseT_Half | 12521 ELINK_SUPPORTED_100baseT_Full | 12522 ELINK_SUPPORTED_1000baseT_Full | 12523 ELINK_SUPPORTED_10000baseT_Full | 12524 ELINK_SUPPORTED_TP | 12525 ELINK_SUPPORTED_Autoneg | 12526 ELINK_SUPPORTED_Pause | 12527 ELINK_SUPPORTED_Asym_Pause), 12528 .media_type = ELINK_ETH_PHY_BASE_T, 12529 .ver_addr = 0, 12530 .req_flow_ctrl = 0, 12531 .req_line_speed = 0, 12532 .speed_cap_mask = 0, 12533 .req_duplex = 0, 12534 .rsrv = 0, 12535 .config_init = (config_init_t)elink_848x3_config_init, 12536 .read_status = (read_status_t)elink_848xx_read_status, 12537 .link_reset = (link_reset_t)elink_848x3_link_reset, 12538 .config_loopback = (config_loopback_t)NULL, 12539 .format_fw_ver = (format_fw_ver_t)elink_848xx_format_ver, 12540 .hw_reset = (hw_reset_t)elink_84833_hw_reset_phy, 12541 .set_link_led = (set_link_led_t)elink_848xx_set_link_led, 12542 .phy_specific_func = (phy_specific_func_t)elink_848xx_specific_func 12543 }; 12544 12545 static const struct elink_phy phy_84834 = { 12546 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834, 12547 .addr = 0xff, 12548 .def_md_devad = 0, 12549 .flags = ELINK_FLAGS_FAN_FAILURE_DET_REQ | 12550 ELINK_FLAGS_REARM_LATCH_SIGNAL, 12551 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 12552 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 12553 .mdio_ctrl = 0, 12554 .supported = (ELINK_SUPPORTED_100baseT_Half | 12555 ELINK_SUPPORTED_100baseT_Full | 12556 ELINK_SUPPORTED_1000baseT_Full | 12557 ELINK_SUPPORTED_10000baseT_Full | 12558 ELINK_SUPPORTED_TP | 12559 ELINK_SUPPORTED_Autoneg | 12560 ELINK_SUPPORTED_Pause | 12561 ELINK_SUPPORTED_Asym_Pause), 12562 .media_type = ELINK_ETH_PHY_BASE_T, 12563 .ver_addr = 0, 12564 .req_flow_ctrl = 0, 12565 .req_line_speed = 0, 12566 .speed_cap_mask = 0, 12567 .req_duplex = 0, 12568 .rsrv = 0, 12569 .config_init = (config_init_t)elink_848x3_config_init, 12570 .read_status = (read_status_t)elink_848xx_read_status, 12571 .link_reset = (link_reset_t)elink_848x3_link_reset, 12572 .config_loopback = (config_loopback_t)NULL, 12573 .format_fw_ver = (format_fw_ver_t)elink_848xx_format_ver, 12574 .hw_reset = (hw_reset_t)elink_84833_hw_reset_phy, 12575 .set_link_led = (set_link_led_t)elink_848xx_set_link_led, 12576 .phy_specific_func = (phy_specific_func_t)elink_848xx_specific_func 12577 }; 12578 12579 static const struct elink_phy phy_54618se = { 12580 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE, 12581 .addr = 0xff, 12582 .def_md_devad = 0, 12583 .flags = ELINK_FLAGS_INIT_XGXS_FIRST, 12584 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 12585 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff}, 12586 .mdio_ctrl = 0, 12587 .supported = (ELINK_SUPPORTED_10baseT_Half | 12588 ELINK_SUPPORTED_10baseT_Full | 12589 ELINK_SUPPORTED_100baseT_Half | 12590 ELINK_SUPPORTED_100baseT_Full | 12591 ELINK_SUPPORTED_1000baseT_Full | 12592 ELINK_SUPPORTED_TP | 12593 ELINK_SUPPORTED_Autoneg | 12594 ELINK_SUPPORTED_Pause | 12595 ELINK_SUPPORTED_Asym_Pause), 12596 .media_type = ELINK_ETH_PHY_BASE_T, 12597 .ver_addr = 0, 12598 .req_flow_ctrl = 0, 12599 .req_line_speed = 0, 12600 .speed_cap_mask = 0, 12601 /* req_duplex = */0, 12602 /* rsrv = */0, 12603 .config_init = (config_init_t)elink_54618se_config_init, 12604 .read_status = (read_status_t)elink_54618se_read_status, 12605 .link_reset = (link_reset_t)elink_54618se_link_reset, 12606 .config_loopback = (config_loopback_t)elink_54618se_config_loopback, 12607 .format_fw_ver = (format_fw_ver_t)NULL, 12608 .hw_reset = (hw_reset_t)NULL, 12609 .set_link_led = (set_link_led_t)elink_5461x_set_link_led, 12610 .phy_specific_func = (phy_specific_func_t)elink_54618se_specific_func 12611 }; 12612 /*****************************************************************/ 12613 /* */ 12614 /* Populate the phy according. Main function: elink_populate_phy */ 12615 /* */ 12616 /*****************************************************************/ 12617 12618 static void elink_populate_preemphasis(struct bxe_softc *sc, uint32_t shmem_base, 12619 struct elink_phy *phy, uint8_t port, 12620 uint8_t phy_index) 12621 { 12622 /* Get the 4 lanes xgxs config rx and tx */ 12623 uint32_t rx = 0, tx = 0, i; 12624 for (i = 0; i < 2; i++) { 12625 /* INT_PHY and ELINK_EXT_PHY1 share the same value location in 12626 * the shmem. When num_phys is greater than 1, than this value 12627 * applies only to ELINK_EXT_PHY1 12628 */ 12629 if (phy_index == ELINK_INT_PHY || phy_index == ELINK_EXT_PHY1) { 12630 rx = REG_RD(sc, shmem_base + 12631 offsetof(struct shmem_region, 12632 dev_info.port_hw_config[port].xgxs_config_rx[i<<1])); 12633 12634 tx = REG_RD(sc, shmem_base + 12635 offsetof(struct shmem_region, 12636 dev_info.port_hw_config[port].xgxs_config_tx[i<<1])); 12637 } else { 12638 rx = REG_RD(sc, shmem_base + 12639 offsetof(struct shmem_region, 12640 dev_info.port_hw_config[port].xgxs_config2_rx[i<<1])); 12641 12642 tx = REG_RD(sc, shmem_base + 12643 offsetof(struct shmem_region, 12644 dev_info.port_hw_config[port].xgxs_config2_rx[i<<1])); 12645 } 12646 12647 phy->rx_preemphasis[i << 1] = ((rx>>16) & 0xffff); 12648 phy->rx_preemphasis[(i << 1) + 1] = (rx & 0xffff); 12649 12650 phy->tx_preemphasis[i << 1] = ((tx>>16) & 0xffff); 12651 phy->tx_preemphasis[(i << 1) + 1] = (tx & 0xffff); 12652 } 12653 } 12654 12655 static uint32_t elink_get_ext_phy_config(struct bxe_softc *sc, uint32_t shmem_base, 12656 uint8_t phy_index, uint8_t port) 12657 { 12658 uint32_t ext_phy_config = 0; 12659 switch (phy_index) { 12660 case ELINK_EXT_PHY1: 12661 ext_phy_config = REG_RD(sc, shmem_base + 12662 offsetof(struct shmem_region, 12663 dev_info.port_hw_config[port].external_phy_config)); 12664 break; 12665 case ELINK_EXT_PHY2: 12666 ext_phy_config = REG_RD(sc, shmem_base + 12667 offsetof(struct shmem_region, 12668 dev_info.port_hw_config[port].external_phy_config2)); 12669 break; 12670 default: 12671 ELINK_DEBUG_P1(sc, "Invalid phy_index %d\n", phy_index); 12672 return ELINK_STATUS_ERROR; 12673 } 12674 12675 return ext_phy_config; 12676 } 12677 static elink_status_t elink_populate_int_phy(struct bxe_softc *sc, uint32_t shmem_base, uint8_t port, 12678 struct elink_phy *phy) 12679 { 12680 uint32_t phy_addr; 12681 uint32_t chip_id; 12682 uint32_t switch_cfg = (REG_RD(sc, shmem_base + 12683 offsetof(struct shmem_region, 12684 dev_info.port_feature_config[port].link_config)) & 12685 PORT_FEATURE_CONNECTED_SWITCH_MASK); 12686 chip_id = (REG_RD(sc, MISC_REG_CHIP_NUM) << 16) | 12687 ((REG_RD(sc, MISC_REG_CHIP_REV) & 0xf) << 12); 12688 12689 ELINK_DEBUG_P1(sc, ":chip_id = 0x%x\n", chip_id); 12690 if (USES_WARPCORE(sc)) { 12691 uint32_t serdes_net_if; 12692 phy_addr = REG_RD(sc, 12693 MISC_REG_WC0_CTRL_PHY_ADDR); 12694 *phy = phy_warpcore; 12695 if (REG_RD(sc, MISC_REG_PORT4MODE_EN_OVWR) == 0x3) 12696 phy->flags |= ELINK_FLAGS_4_PORT_MODE; 12697 else 12698 phy->flags &= ~ELINK_FLAGS_4_PORT_MODE; 12699 /* Check Dual mode */ 12700 serdes_net_if = (REG_RD(sc, shmem_base + 12701 offsetof(struct shmem_region, dev_info. 12702 port_hw_config[port].default_cfg)) & 12703 PORT_HW_CFG_NET_SERDES_IF_MASK); 12704 /* Set the appropriate supported and flags indications per 12705 * interface type of the chip 12706 */ 12707 switch (serdes_net_if) { 12708 case PORT_HW_CFG_NET_SERDES_IF_SGMII: 12709 phy->supported &= (ELINK_SUPPORTED_10baseT_Half | 12710 ELINK_SUPPORTED_10baseT_Full | 12711 ELINK_SUPPORTED_100baseT_Half | 12712 ELINK_SUPPORTED_100baseT_Full | 12713 ELINK_SUPPORTED_1000baseT_Full | 12714 ELINK_SUPPORTED_FIBRE | 12715 ELINK_SUPPORTED_Autoneg | 12716 ELINK_SUPPORTED_Pause | 12717 ELINK_SUPPORTED_Asym_Pause); 12718 phy->media_type = ELINK_ETH_PHY_BASE_T; 12719 break; 12720 case PORT_HW_CFG_NET_SERDES_IF_XFI: 12721 phy->supported &= (ELINK_SUPPORTED_1000baseT_Full | 12722 ELINK_SUPPORTED_10000baseT_Full | 12723 ELINK_SUPPORTED_FIBRE | 12724 ELINK_SUPPORTED_Pause | 12725 ELINK_SUPPORTED_Asym_Pause); 12726 phy->media_type = ELINK_ETH_PHY_XFP_FIBER; 12727 break; 12728 case PORT_HW_CFG_NET_SERDES_IF_SFI: 12729 phy->supported &= (ELINK_SUPPORTED_1000baseT_Full | 12730 ELINK_SUPPORTED_10000baseT_Full | 12731 ELINK_SUPPORTED_FIBRE | 12732 ELINK_SUPPORTED_Pause | 12733 ELINK_SUPPORTED_Asym_Pause); 12734 phy->media_type = ELINK_ETH_PHY_SFPP_10G_FIBER; 12735 break; 12736 case PORT_HW_CFG_NET_SERDES_IF_KR: 12737 phy->media_type = ELINK_ETH_PHY_KR; 12738 phy->supported &= (ELINK_SUPPORTED_1000baseT_Full | 12739 ELINK_SUPPORTED_10000baseT_Full | 12740 ELINK_SUPPORTED_FIBRE | 12741 ELINK_SUPPORTED_Autoneg | 12742 ELINK_SUPPORTED_Pause | 12743 ELINK_SUPPORTED_Asym_Pause); 12744 break; 12745 case PORT_HW_CFG_NET_SERDES_IF_DXGXS: 12746 phy->media_type = ELINK_ETH_PHY_KR; 12747 phy->flags |= ELINK_FLAGS_WC_DUAL_MODE; 12748 phy->supported &= (ELINK_SUPPORTED_20000baseMLD2_Full | 12749 ELINK_SUPPORTED_FIBRE | 12750 ELINK_SUPPORTED_Pause | 12751 ELINK_SUPPORTED_Asym_Pause); 12752 break; 12753 case PORT_HW_CFG_NET_SERDES_IF_KR2: 12754 phy->media_type = ELINK_ETH_PHY_KR; 12755 phy->flags |= ELINK_FLAGS_WC_DUAL_MODE; 12756 phy->supported &= (ELINK_SUPPORTED_20000baseKR2_Full | 12757 ELINK_SUPPORTED_10000baseT_Full | 12758 ELINK_SUPPORTED_1000baseT_Full | 12759 ELINK_SUPPORTED_Autoneg | 12760 ELINK_SUPPORTED_FIBRE | 12761 ELINK_SUPPORTED_Pause | 12762 ELINK_SUPPORTED_Asym_Pause); 12763 phy->flags &= ~ELINK_FLAGS_TX_ERROR_CHECK; 12764 break; 12765 default: 12766 ELINK_DEBUG_P1(sc, "Unknown WC interface type 0x%x\n", 12767 serdes_net_if); 12768 break; 12769 } 12770 12771 /* Enable MDC/MDIO work-around for E3 A0 since free running MDC 12772 * was not set as expected. For B0, ECO will be enabled so there 12773 * won't be an issue there 12774 */ 12775 if (CHIP_REV(sc) == CHIP_REV_Ax) 12776 phy->flags |= ELINK_FLAGS_MDC_MDIO_WA; 12777 else 12778 phy->flags |= ELINK_FLAGS_MDC_MDIO_WA_B0; 12779 } else 12780 { 12781 switch (switch_cfg) { 12782 case ELINK_SWITCH_CFG_1G: 12783 phy_addr = REG_RD(sc, 12784 NIG_REG_SERDES0_CTRL_PHY_ADDR + 12785 port * 0x10); 12786 *phy = phy_serdes; 12787 break; 12788 case ELINK_SWITCH_CFG_10G: 12789 phy_addr = REG_RD(sc, 12790 NIG_REG_XGXS0_CTRL_PHY_ADDR + 12791 port * 0x18); 12792 *phy = phy_xgxs; 12793 break; 12794 default: 12795 ELINK_DEBUG_P0(sc, "Invalid switch_cfg\n"); 12796 return ELINK_STATUS_ERROR; 12797 } 12798 } 12799 phy->addr = (uint8_t)phy_addr; 12800 phy->mdio_ctrl = elink_get_emac_base(sc, 12801 SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH, 12802 port); 12803 if (CHIP_IS_E2(sc)) 12804 phy->def_md_devad = ELINK_E2_DEFAULT_PHY_DEV_ADDR; 12805 else 12806 phy->def_md_devad = ELINK_DEFAULT_PHY_DEV_ADDR; 12807 12808 ELINK_DEBUG_P3(sc, "Internal phy port=%d, addr=0x%x, mdio_ctl=0x%x\n", 12809 port, phy->addr, phy->mdio_ctrl); 12810 12811 elink_populate_preemphasis(sc, shmem_base, phy, port, ELINK_INT_PHY); 12812 return ELINK_STATUS_OK; 12813 } 12814 12815 static elink_status_t elink_populate_ext_phy(struct bxe_softc *sc, 12816 uint8_t phy_index, 12817 uint32_t shmem_base, 12818 uint32_t shmem2_base, 12819 uint8_t port, 12820 struct elink_phy *phy) 12821 { 12822 uint32_t ext_phy_config, phy_type, config2; 12823 uint32_t mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH; 12824 ext_phy_config = elink_get_ext_phy_config(sc, shmem_base, 12825 phy_index, port); 12826 phy_type = ELINK_XGXS_EXT_PHY_TYPE(ext_phy_config); 12827 /* Select the phy type */ 12828 switch (phy_type) { 12829 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073: 12830 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED; 12831 *phy = phy_8073; 12832 break; 12833 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705: 12834 *phy = phy_8705; 12835 break; 12836 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706: 12837 *phy = phy_8706; 12838 break; 12839 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726: 12840 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1; 12841 *phy = phy_8726; 12842 break; 12843 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC: 12844 /* BCM8727_NOC => BCM8727 no over current */ 12845 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1; 12846 *phy = phy_8727; 12847 phy->flags |= ELINK_FLAGS_NOC; 12848 break; 12849 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722: 12850 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: 12851 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1; 12852 *phy = phy_8727; 12853 break; 12854 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481: 12855 *phy = phy_8481; 12856 break; 12857 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823: 12858 *phy = phy_84823; 12859 break; 12860 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833: 12861 *phy = phy_84833; 12862 break; 12863 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834: 12864 *phy = phy_84834; 12865 break; 12866 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616: 12867 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE: 12868 *phy = phy_54618se; 12869 if (phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) 12870 phy->flags |= ELINK_FLAGS_EEE; 12871 break; 12872 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101: 12873 *phy = phy_7101; 12874 break; 12875 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE: 12876 *phy = phy_null; 12877 return ELINK_STATUS_ERROR; 12878 default: 12879 *phy = phy_null; 12880 /* In case external PHY wasn't found */ 12881 if ((phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) && 12882 (phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)) 12883 return ELINK_STATUS_ERROR; 12884 return ELINK_STATUS_OK; 12885 } 12886 12887 phy->addr = ELINK_XGXS_EXT_PHY_ADDR(ext_phy_config); 12888 elink_populate_preemphasis(sc, shmem_base, phy, port, phy_index); 12889 12890 /* The shmem address of the phy version is located on different 12891 * structures. In case this structure is too old, do not set 12892 * the address 12893 */ 12894 config2 = REG_RD(sc, shmem_base + offsetof(struct shmem_region, 12895 dev_info.shared_hw_config.config2)); 12896 if (phy_index == ELINK_EXT_PHY1) { 12897 phy->ver_addr = shmem_base + offsetof(struct shmem_region, 12898 port_mb[port].ext_phy_fw_version); 12899 12900 /* Check specific mdc mdio settings */ 12901 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK) 12902 mdc_mdio_access = config2 & 12903 SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK; 12904 } else { 12905 uint32_t size = REG_RD(sc, shmem2_base); 12906 12907 if (size > 12908 offsetof(struct shmem2_region, ext_phy_fw_version2)) { 12909 phy->ver_addr = shmem2_base + 12910 offsetof(struct shmem2_region, 12911 ext_phy_fw_version2[port]); 12912 } 12913 /* Check specific mdc mdio settings */ 12914 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK) 12915 mdc_mdio_access = (config2 & 12916 SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK) >> 12917 (SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT - 12918 SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT); 12919 } 12920 phy->mdio_ctrl = elink_get_emac_base(sc, mdc_mdio_access, port); 12921 12922 if (((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) || 12923 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834)) && 12924 (phy->ver_addr)) { 12925 /* Remove 100Mb link supported for BCM84833/4 when phy fw 12926 * version lower than or equal to 1.39 12927 */ 12928 uint32_t raw_ver = REG_RD(sc, phy->ver_addr); 12929 if (((raw_ver & 0x7F) <= 39) && 12930 (((raw_ver & 0xF80) >> 7) <= 1)) 12931 phy->supported &= ~(ELINK_SUPPORTED_100baseT_Half | 12932 ELINK_SUPPORTED_100baseT_Full); 12933 } 12934 12935 ELINK_DEBUG_P3(sc, "phy_type 0x%x port %d found in index %d\n", 12936 phy_type, port, phy_index); 12937 ELINK_DEBUG_P2(sc, " addr=0x%x, mdio_ctl=0x%x\n", 12938 phy->addr, phy->mdio_ctrl); 12939 return ELINK_STATUS_OK; 12940 } 12941 12942 static elink_status_t elink_populate_phy(struct bxe_softc *sc, uint8_t phy_index, uint32_t shmem_base, 12943 uint32_t shmem2_base, uint8_t port, struct elink_phy *phy) 12944 { 12945 elink_status_t status = ELINK_STATUS_OK; 12946 phy->type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN; 12947 if (phy_index == ELINK_INT_PHY) 12948 return elink_populate_int_phy(sc, shmem_base, port, phy); 12949 status = elink_populate_ext_phy(sc, phy_index, shmem_base, shmem2_base, 12950 port, phy); 12951 return status; 12952 } 12953 12954 static void elink_phy_def_cfg(struct elink_params *params, 12955 struct elink_phy *phy, 12956 uint8_t phy_index) 12957 { 12958 struct bxe_softc *sc = params->sc; 12959 uint32_t link_config; 12960 /* Populate the default phy configuration for MF mode */ 12961 if (phy_index == ELINK_EXT_PHY2) { 12962 link_config = REG_RD(sc, params->shmem_base + 12963 offsetof(struct shmem_region, dev_info. 12964 port_feature_config[params->port].link_config2)); 12965 phy->speed_cap_mask = REG_RD(sc, params->shmem_base + 12966 offsetof(struct shmem_region, 12967 dev_info. 12968 port_hw_config[params->port].speed_capability_mask2)); 12969 } else { 12970 link_config = REG_RD(sc, params->shmem_base + 12971 offsetof(struct shmem_region, dev_info. 12972 port_feature_config[params->port].link_config)); 12973 phy->speed_cap_mask = REG_RD(sc, params->shmem_base + 12974 offsetof(struct shmem_region, 12975 dev_info. 12976 port_hw_config[params->port].speed_capability_mask)); 12977 } 12978 ELINK_DEBUG_P3(sc, 12979 "Default config phy idx %x cfg 0x%x speed_cap_mask 0x%x\n", 12980 phy_index, link_config, phy->speed_cap_mask); 12981 12982 phy->req_duplex = DUPLEX_FULL; 12983 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) { 12984 case PORT_FEATURE_LINK_SPEED_10M_HALF: 12985 phy->req_duplex = DUPLEX_HALF; 12986 case PORT_FEATURE_LINK_SPEED_10M_FULL: 12987 phy->req_line_speed = ELINK_SPEED_10; 12988 break; 12989 case PORT_FEATURE_LINK_SPEED_100M_HALF: 12990 phy->req_duplex = DUPLEX_HALF; 12991 case PORT_FEATURE_LINK_SPEED_100M_FULL: 12992 phy->req_line_speed = ELINK_SPEED_100; 12993 break; 12994 case PORT_FEATURE_LINK_SPEED_1G: 12995 phy->req_line_speed = ELINK_SPEED_1000; 12996 break; 12997 case PORT_FEATURE_LINK_SPEED_2_5G: 12998 phy->req_line_speed = ELINK_SPEED_2500; 12999 break; 13000 case PORT_FEATURE_LINK_SPEED_10G_CX4: 13001 phy->req_line_speed = ELINK_SPEED_10000; 13002 break; 13003 default: 13004 phy->req_line_speed = ELINK_SPEED_AUTO_NEG; 13005 break; 13006 } 13007 13008 switch (link_config & PORT_FEATURE_FLOW_CONTROL_MASK) { 13009 case PORT_FEATURE_FLOW_CONTROL_AUTO: 13010 phy->req_flow_ctrl = ELINK_FLOW_CTRL_AUTO; 13011 break; 13012 case PORT_FEATURE_FLOW_CONTROL_TX: 13013 phy->req_flow_ctrl = ELINK_FLOW_CTRL_TX; 13014 break; 13015 case PORT_FEATURE_FLOW_CONTROL_RX: 13016 phy->req_flow_ctrl = ELINK_FLOW_CTRL_RX; 13017 break; 13018 case PORT_FEATURE_FLOW_CONTROL_BOTH: 13019 phy->req_flow_ctrl = ELINK_FLOW_CTRL_BOTH; 13020 break; 13021 default: 13022 phy->req_flow_ctrl = ELINK_FLOW_CTRL_NONE; 13023 break; 13024 } 13025 } 13026 13027 uint32_t elink_phy_selection(struct elink_params *params) 13028 { 13029 uint32_t phy_config_swapped, prio_cfg; 13030 uint32_t return_cfg = PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT; 13031 13032 phy_config_swapped = params->multi_phy_config & 13033 PORT_HW_CFG_PHY_SWAPPED_ENABLED; 13034 13035 prio_cfg = params->multi_phy_config & 13036 PORT_HW_CFG_PHY_SELECTION_MASK; 13037 13038 if (phy_config_swapped) { 13039 switch (prio_cfg) { 13040 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY: 13041 return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY; 13042 break; 13043 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY: 13044 return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY; 13045 break; 13046 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY: 13047 return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY; 13048 break; 13049 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY: 13050 return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY; 13051 break; 13052 } 13053 } else 13054 return_cfg = prio_cfg; 13055 13056 return return_cfg; 13057 } 13058 13059 elink_status_t elink_phy_probe(struct elink_params *params) 13060 { 13061 uint8_t phy_index, actual_phy_idx; 13062 uint32_t phy_config_swapped, sync_offset, media_types; 13063 struct bxe_softc *sc = params->sc; 13064 struct elink_phy *phy; 13065 params->num_phys = 0; 13066 ELINK_DEBUG_P0(sc, "Begin phy probe\n"); 13067 #ifdef ELINK_INCLUDE_EMUL 13068 if (CHIP_REV_IS_EMUL(sc)) 13069 return ELINK_STATUS_OK; 13070 #endif 13071 phy_config_swapped = params->multi_phy_config & 13072 PORT_HW_CFG_PHY_SWAPPED_ENABLED; 13073 13074 for (phy_index = ELINK_INT_PHY; phy_index < ELINK_MAX_PHYS; 13075 phy_index++) { 13076 actual_phy_idx = phy_index; 13077 if (phy_config_swapped) { 13078 if (phy_index == ELINK_EXT_PHY1) 13079 actual_phy_idx = ELINK_EXT_PHY2; 13080 else if (phy_index == ELINK_EXT_PHY2) 13081 actual_phy_idx = ELINK_EXT_PHY1; 13082 } 13083 ELINK_DEBUG_P3(sc, "phy_config_swapped %x, phy_index %x," 13084 " actual_phy_idx %x\n", phy_config_swapped, 13085 phy_index, actual_phy_idx); 13086 phy = ¶ms->phy[actual_phy_idx]; 13087 if (elink_populate_phy(sc, phy_index, params->shmem_base, 13088 params->shmem2_base, params->port, 13089 phy) != ELINK_STATUS_OK) { 13090 params->num_phys = 0; 13091 ELINK_DEBUG_P1(sc, "phy probe failed in phy index %d\n", 13092 phy_index); 13093 for (phy_index = ELINK_INT_PHY; 13094 phy_index < ELINK_MAX_PHYS; 13095 phy_index++) 13096 *phy = phy_null; 13097 return ELINK_STATUS_ERROR; 13098 } 13099 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN) 13100 break; 13101 13102 if (params->feature_config_flags & 13103 ELINK_FEATURE_CONFIG_DISABLE_REMOTE_FAULT_DET) 13104 phy->flags &= ~ELINK_FLAGS_TX_ERROR_CHECK; 13105 13106 if (!(params->feature_config_flags & 13107 ELINK_FEATURE_CONFIG_MT_SUPPORT)) 13108 phy->flags |= ELINK_FLAGS_MDC_MDIO_WA_G; 13109 13110 sync_offset = params->shmem_base + 13111 offsetof(struct shmem_region, 13112 dev_info.port_hw_config[params->port].media_type); 13113 media_types = REG_RD(sc, sync_offset); 13114 13115 /* Update media type for non-PMF sync only for the first time 13116 * In case the media type changes afterwards, it will be updated 13117 * using the update_status function 13118 */ 13119 if ((media_types & (PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK << 13120 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * 13121 actual_phy_idx))) == 0) { 13122 media_types |= ((phy->media_type & 13123 PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) << 13124 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * 13125 actual_phy_idx)); 13126 } 13127 REG_WR(sc, sync_offset, media_types); 13128 13129 elink_phy_def_cfg(params, phy, phy_index); 13130 params->num_phys++; 13131 } 13132 13133 ELINK_DEBUG_P1(sc, "End phy probe. #phys found %x\n", params->num_phys); 13134 return ELINK_STATUS_OK; 13135 } 13136 13137 #ifdef ELINK_INCLUDE_EMUL 13138 static elink_status_t elink_init_e3_emul_mac(struct elink_params *params, 13139 struct elink_vars *vars) 13140 { 13141 struct bxe_softc *sc = params->sc; 13142 vars->line_speed = params->req_line_speed[0]; 13143 /* In case link speed is auto, set speed the highest as possible */ 13144 if (params->req_line_speed[0] == ELINK_SPEED_AUTO_NEG) { 13145 if (params->feature_config_flags & 13146 ELINK_FEATURE_CONFIG_EMUL_DISABLE_XMAC) 13147 vars->line_speed = ELINK_SPEED_2500; 13148 else if (elink_is_4_port_mode(sc)) 13149 vars->line_speed = ELINK_SPEED_10000; 13150 else 13151 vars->line_speed = ELINK_SPEED_20000; 13152 } 13153 if (vars->line_speed < ELINK_SPEED_10000) { 13154 if ((params->feature_config_flags & 13155 ELINK_FEATURE_CONFIG_EMUL_DISABLE_UMAC)) { 13156 ELINK_DEBUG_P1(sc, "Invalid line speed %d while UMAC is" 13157 " disabled!\n", params->req_line_speed[0]); 13158 return ELINK_STATUS_ERROR; 13159 } 13160 switch (vars->line_speed) { 13161 case ELINK_SPEED_10: 13162 vars->link_status = ELINK_LINK_10TFD; 13163 break; 13164 case ELINK_SPEED_100: 13165 vars->link_status = ELINK_LINK_100TXFD; 13166 break; 13167 case ELINK_SPEED_1000: 13168 vars->link_status = ELINK_LINK_1000TFD; 13169 break; 13170 case ELINK_SPEED_2500: 13171 vars->link_status = ELINK_LINK_2500TFD; 13172 break; 13173 default: 13174 ELINK_DEBUG_P1(sc, "Invalid line speed %d for UMAC\n", 13175 vars->line_speed); 13176 return ELINK_STATUS_ERROR; 13177 } 13178 vars->link_status |= LINK_STATUS_LINK_UP; 13179 13180 if (params->loopback_mode == ELINK_LOOPBACK_UMAC) 13181 elink_umac_enable(params, vars, 1); 13182 else 13183 elink_umac_enable(params, vars, 0); 13184 } else { 13185 /* Link speed >= 10000 requires XMAC enabled */ 13186 if (params->feature_config_flags & 13187 ELINK_FEATURE_CONFIG_EMUL_DISABLE_XMAC) { 13188 ELINK_DEBUG_P1(sc, "Invalid line speed %d while XMAC is" 13189 " disabled!\n", params->req_line_speed[0]); 13190 return ELINK_STATUS_ERROR; 13191 } 13192 /* Check link speed */ 13193 switch (vars->line_speed) { 13194 case ELINK_SPEED_10000: 13195 vars->link_status = ELINK_LINK_10GTFD; 13196 break; 13197 case ELINK_SPEED_20000: 13198 vars->link_status = ELINK_LINK_20GTFD; 13199 break; 13200 default: 13201 ELINK_DEBUG_P1(sc, "Invalid line speed %d for XMAC\n", 13202 vars->line_speed); 13203 return ELINK_STATUS_ERROR; 13204 } 13205 vars->link_status |= LINK_STATUS_LINK_UP; 13206 if (params->loopback_mode == ELINK_LOOPBACK_XMAC) 13207 elink_xmac_enable(params, vars, 1); 13208 else 13209 elink_xmac_enable(params, vars, 0); 13210 } 13211 return ELINK_STATUS_OK; 13212 } 13213 13214 static elink_status_t elink_init_emul(struct elink_params *params, 13215 struct elink_vars *vars) 13216 { 13217 struct bxe_softc *sc = params->sc; 13218 if (CHIP_IS_E3(sc)) { 13219 if (elink_init_e3_emul_mac(params, vars) != 13220 ELINK_STATUS_OK) 13221 return ELINK_STATUS_ERROR; 13222 } else { 13223 if (params->feature_config_flags & 13224 ELINK_FEATURE_CONFIG_EMUL_DISABLE_BMAC) { 13225 vars->line_speed = ELINK_SPEED_1000; 13226 vars->link_status = (LINK_STATUS_LINK_UP | 13227 ELINK_LINK_1000XFD); 13228 if (params->loopback_mode == 13229 ELINK_LOOPBACK_EMAC) 13230 elink_emac_enable(params, vars, 1); 13231 else 13232 elink_emac_enable(params, vars, 0); 13233 } else { 13234 vars->line_speed = ELINK_SPEED_10000; 13235 vars->link_status = (LINK_STATUS_LINK_UP | 13236 ELINK_LINK_10GTFD); 13237 if (params->loopback_mode == 13238 ELINK_LOOPBACK_BMAC) 13239 elink_bmac_enable(params, vars, 1, 1); 13240 else 13241 elink_bmac_enable(params, vars, 0, 1); 13242 } 13243 } 13244 vars->link_up = 1; 13245 vars->duplex = DUPLEX_FULL; 13246 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE; 13247 13248 if (CHIP_IS_E1x(sc)) 13249 elink_pbf_update(params, vars->flow_ctrl, 13250 vars->line_speed); 13251 /* Disable drain */ 13252 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); 13253 13254 /* update shared memory */ 13255 elink_update_mng(params, vars->link_status); 13256 return ELINK_STATUS_OK; 13257 } 13258 #endif 13259 #ifdef ELINK_INCLUDE_FPGA 13260 static elink_status_t elink_init_fpga(struct elink_params *params, 13261 struct elink_vars *vars) 13262 { 13263 /* Enable on E1.5 FPGA */ 13264 struct bxe_softc *sc = params->sc; 13265 vars->duplex = DUPLEX_FULL; 13266 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE; 13267 if (!(CHIP_IS_E1(sc))) { 13268 vars->flow_ctrl = (ELINK_FLOW_CTRL_TX | 13269 ELINK_FLOW_CTRL_RX); 13270 vars->link_status |= (LINK_STATUS_TX_FLOW_CONTROL_ENABLED | 13271 LINK_STATUS_RX_FLOW_CONTROL_ENABLED); 13272 } 13273 if (CHIP_IS_E3(sc)) { 13274 vars->line_speed = params->req_line_speed[0]; 13275 switch (vars->line_speed) { 13276 case ELINK_SPEED_AUTO_NEG: 13277 vars->line_speed = ELINK_SPEED_2500; 13278 case ELINK_SPEED_2500: 13279 vars->link_status = ELINK_LINK_2500TFD; 13280 break; 13281 case ELINK_SPEED_1000: 13282 vars->link_status = ELINK_LINK_1000XFD; 13283 break; 13284 case ELINK_SPEED_100: 13285 vars->link_status = ELINK_LINK_100TXFD; 13286 break; 13287 case ELINK_SPEED_10: 13288 vars->link_status = ELINK_LINK_10TFD; 13289 break; 13290 default: 13291 ELINK_DEBUG_P1(sc, "Invalid link speed %d\n", 13292 params->req_line_speed[0]); 13293 return ELINK_STATUS_ERROR; 13294 } 13295 vars->link_status |= LINK_STATUS_LINK_UP; 13296 if (params->loopback_mode == ELINK_LOOPBACK_UMAC) 13297 elink_umac_enable(params, vars, 1); 13298 else 13299 elink_umac_enable(params, vars, 0); 13300 } else { 13301 vars->line_speed = ELINK_SPEED_10000; 13302 vars->link_status = (LINK_STATUS_LINK_UP | ELINK_LINK_10GTFD); 13303 if (params->loopback_mode == ELINK_LOOPBACK_EMAC) 13304 elink_emac_enable(params, vars, 1); 13305 else 13306 elink_emac_enable(params, vars, 0); 13307 } 13308 vars->link_up = 1; 13309 13310 if (CHIP_IS_E1x(sc)) 13311 elink_pbf_update(params, vars->flow_ctrl, 13312 vars->line_speed); 13313 /* Disable drain */ 13314 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); 13315 13316 /* Update shared memory */ 13317 elink_update_mng(params, vars->link_status); 13318 return ELINK_STATUS_OK; 13319 } 13320 #endif 13321 static void elink_init_bmac_loopback(struct elink_params *params, 13322 struct elink_vars *vars) 13323 { 13324 struct bxe_softc *sc = params->sc; 13325 vars->link_up = 1; 13326 vars->line_speed = ELINK_SPEED_10000; 13327 vars->duplex = DUPLEX_FULL; 13328 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE; 13329 vars->mac_type = ELINK_MAC_TYPE_BMAC; 13330 13331 vars->phy_flags = PHY_XGXS_FLAG; 13332 13333 elink_xgxs_deassert(params); 13334 13335 /* Set bmac loopback */ 13336 elink_bmac_enable(params, vars, 1, 1); 13337 13338 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); 13339 } 13340 13341 static void elink_init_emac_loopback(struct elink_params *params, 13342 struct elink_vars *vars) 13343 { 13344 struct bxe_softc *sc = params->sc; 13345 vars->link_up = 1; 13346 vars->line_speed = ELINK_SPEED_1000; 13347 vars->duplex = DUPLEX_FULL; 13348 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE; 13349 vars->mac_type = ELINK_MAC_TYPE_EMAC; 13350 13351 vars->phy_flags = PHY_XGXS_FLAG; 13352 13353 elink_xgxs_deassert(params); 13354 /* Set bmac loopback */ 13355 elink_emac_enable(params, vars, 1); 13356 elink_emac_program(params, vars); 13357 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); 13358 } 13359 13360 static void elink_init_xmac_loopback(struct elink_params *params, 13361 struct elink_vars *vars) 13362 { 13363 struct bxe_softc *sc = params->sc; 13364 vars->link_up = 1; 13365 if (!params->req_line_speed[0]) 13366 vars->line_speed = ELINK_SPEED_10000; 13367 else 13368 vars->line_speed = params->req_line_speed[0]; 13369 vars->duplex = DUPLEX_FULL; 13370 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE; 13371 vars->mac_type = ELINK_MAC_TYPE_XMAC; 13372 vars->phy_flags = PHY_XGXS_FLAG; 13373 /* Set WC to loopback mode since link is required to provide clock 13374 * to the XMAC in 20G mode 13375 */ 13376 elink_set_aer_mmd(params, ¶ms->phy[0]); 13377 elink_warpcore_reset_lane(sc, ¶ms->phy[0], 0); 13378 params->phy[ELINK_INT_PHY].config_loopback( 13379 ¶ms->phy[ELINK_INT_PHY], 13380 params); 13381 13382 elink_xmac_enable(params, vars, 1); 13383 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); 13384 } 13385 13386 static void elink_init_umac_loopback(struct elink_params *params, 13387 struct elink_vars *vars) 13388 { 13389 struct bxe_softc *sc = params->sc; 13390 vars->link_up = 1; 13391 vars->line_speed = ELINK_SPEED_1000; 13392 vars->duplex = DUPLEX_FULL; 13393 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE; 13394 vars->mac_type = ELINK_MAC_TYPE_UMAC; 13395 vars->phy_flags = PHY_XGXS_FLAG; 13396 elink_umac_enable(params, vars, 1); 13397 13398 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); 13399 } 13400 13401 static void elink_init_xgxs_loopback(struct elink_params *params, 13402 struct elink_vars *vars) 13403 { 13404 struct bxe_softc *sc = params->sc; 13405 struct elink_phy *int_phy = ¶ms->phy[ELINK_INT_PHY]; 13406 vars->link_up = 1; 13407 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE; 13408 vars->duplex = DUPLEX_FULL; 13409 if (params->req_line_speed[0] == ELINK_SPEED_1000) 13410 vars->line_speed = ELINK_SPEED_1000; 13411 else if ((params->req_line_speed[0] == ELINK_SPEED_20000) || 13412 (int_phy->flags & ELINK_FLAGS_WC_DUAL_MODE)) 13413 vars->line_speed = ELINK_SPEED_20000; 13414 else 13415 vars->line_speed = ELINK_SPEED_10000; 13416 13417 if (!USES_WARPCORE(sc)) 13418 elink_xgxs_deassert(params); 13419 elink_link_initialize(params, vars); 13420 13421 if (params->req_line_speed[0] == ELINK_SPEED_1000) { 13422 if (USES_WARPCORE(sc)) 13423 elink_umac_enable(params, vars, 0); 13424 else { 13425 elink_emac_program(params, vars); 13426 elink_emac_enable(params, vars, 0); 13427 } 13428 } else { 13429 if (USES_WARPCORE(sc)) 13430 elink_xmac_enable(params, vars, 0); 13431 else 13432 elink_bmac_enable(params, vars, 0, 1); 13433 } 13434 13435 if (params->loopback_mode == ELINK_LOOPBACK_XGXS) { 13436 /* Set 10G XGXS loopback */ 13437 int_phy->config_loopback(int_phy, params); 13438 } else { 13439 /* Set external phy loopback */ 13440 uint8_t phy_index; 13441 for (phy_index = ELINK_EXT_PHY1; 13442 phy_index < params->num_phys; phy_index++) 13443 if (params->phy[phy_index].config_loopback) 13444 params->phy[phy_index].config_loopback( 13445 ¶ms->phy[phy_index], 13446 params); 13447 } 13448 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); 13449 13450 elink_set_led(params, vars, ELINK_LED_MODE_OPER, vars->line_speed); 13451 } 13452 13453 void elink_set_rx_filter(struct elink_params *params, uint8_t en) 13454 { 13455 struct bxe_softc *sc = params->sc; 13456 uint8_t val = en * 0x1F; 13457 13458 /* Open / close the gate between the NIG and the BRB */ 13459 if (!CHIP_IS_E1x(sc)) 13460 val |= en * 0x20; 13461 REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK + params->port*4, val); 13462 13463 if (!CHIP_IS_E1(sc)) { 13464 REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK_MF + params->port*4, 13465 en*0x3); 13466 } 13467 13468 REG_WR(sc, (params->port ? NIG_REG_LLH1_BRB1_NOT_MCP : 13469 NIG_REG_LLH0_BRB1_NOT_MCP), en); 13470 } 13471 static elink_status_t elink_avoid_link_flap(struct elink_params *params, 13472 struct elink_vars *vars) 13473 { 13474 uint32_t phy_idx; 13475 uint32_t dont_clear_stat, lfa_sts; 13476 struct bxe_softc *sc = params->sc; 13477 13478 /* Sync the link parameters */ 13479 elink_link_status_update(params, vars); 13480 13481 /* 13482 * The module verification was already done by previous link owner, 13483 * so this call is meant only to get warning message 13484 */ 13485 13486 for (phy_idx = ELINK_INT_PHY; phy_idx < params->num_phys; phy_idx++) { 13487 struct elink_phy *phy = ¶ms->phy[phy_idx]; 13488 if (phy->phy_specific_func) { 13489 ELINK_DEBUG_P0(sc, "Calling PHY specific func\n"); 13490 phy->phy_specific_func(phy, params, ELINK_PHY_INIT); 13491 } 13492 if ((phy->media_type == ELINK_ETH_PHY_SFPP_10G_FIBER) || 13493 (phy->media_type == ELINK_ETH_PHY_SFP_1G_FIBER) || 13494 (phy->media_type == ELINK_ETH_PHY_DA_TWINAX)) 13495 elink_verify_sfp_module(phy, params); 13496 } 13497 lfa_sts = REG_RD(sc, params->lfa_base + 13498 offsetof(struct shmem_lfa, 13499 lfa_sts)); 13500 13501 dont_clear_stat = lfa_sts & SHMEM_LFA_DONT_CLEAR_STAT; 13502 13503 /* Re-enable the NIG/MAC */ 13504 if (CHIP_IS_E3(sc)) { 13505 if (!dont_clear_stat) { 13506 REG_WR(sc, GRCBASE_MISC + 13507 MISC_REGISTERS_RESET_REG_2_CLEAR, 13508 (MISC_REGISTERS_RESET_REG_2_MSTAT0 << 13509 params->port)); 13510 REG_WR(sc, GRCBASE_MISC + 13511 MISC_REGISTERS_RESET_REG_2_SET, 13512 (MISC_REGISTERS_RESET_REG_2_MSTAT0 << 13513 params->port)); 13514 } 13515 if (vars->line_speed < ELINK_SPEED_10000) 13516 elink_umac_enable(params, vars, 0); 13517 else 13518 elink_xmac_enable(params, vars, 0); 13519 } else { 13520 if (vars->line_speed < ELINK_SPEED_10000) 13521 elink_emac_enable(params, vars, 0); 13522 else 13523 elink_bmac_enable(params, vars, 0, !dont_clear_stat); 13524 } 13525 13526 /* Increment LFA count */ 13527 lfa_sts = ((lfa_sts & ~LINK_FLAP_AVOIDANCE_COUNT_MASK) | 13528 (((((lfa_sts & LINK_FLAP_AVOIDANCE_COUNT_MASK) >> 13529 LINK_FLAP_AVOIDANCE_COUNT_OFFSET) + 1) & 0xff) 13530 << LINK_FLAP_AVOIDANCE_COUNT_OFFSET)); 13531 /* Clear link flap reason */ 13532 lfa_sts &= ~LFA_LINK_FLAP_REASON_MASK; 13533 13534 REG_WR(sc, params->lfa_base + 13535 offsetof(struct shmem_lfa, lfa_sts), lfa_sts); 13536 13537 /* Disable NIG DRAIN */ 13538 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); 13539 13540 /* Enable interrupts */ 13541 elink_link_int_enable(params); 13542 return ELINK_STATUS_OK; 13543 } 13544 13545 static void elink_cannot_avoid_link_flap(struct elink_params *params, 13546 struct elink_vars *vars, 13547 int lfa_status) 13548 { 13549 uint32_t lfa_sts, cfg_idx, tmp_val; 13550 struct bxe_softc *sc = params->sc; 13551 13552 elink_link_reset(params, vars, 1); 13553 13554 if (!params->lfa_base) 13555 return; 13556 /* Store the new link parameters */ 13557 REG_WR(sc, params->lfa_base + 13558 offsetof(struct shmem_lfa, req_duplex), 13559 params->req_duplex[0] | (params->req_duplex[1] << 16)); 13560 13561 REG_WR(sc, params->lfa_base + 13562 offsetof(struct shmem_lfa, req_flow_ctrl), 13563 params->req_flow_ctrl[0] | (params->req_flow_ctrl[1] << 16)); 13564 13565 REG_WR(sc, params->lfa_base + 13566 offsetof(struct shmem_lfa, req_line_speed), 13567 params->req_line_speed[0] | (params->req_line_speed[1] << 16)); 13568 13569 for (cfg_idx = 0; cfg_idx < SHMEM_LINK_CONFIG_SIZE; cfg_idx++) { 13570 REG_WR(sc, params->lfa_base + 13571 offsetof(struct shmem_lfa, 13572 speed_cap_mask[cfg_idx]), 13573 params->speed_cap_mask[cfg_idx]); 13574 } 13575 13576 tmp_val = REG_RD(sc, params->lfa_base + 13577 offsetof(struct shmem_lfa, additional_config)); 13578 tmp_val &= ~REQ_FC_AUTO_ADV_MASK; 13579 tmp_val |= params->req_fc_auto_adv; 13580 13581 REG_WR(sc, params->lfa_base + 13582 offsetof(struct shmem_lfa, additional_config), tmp_val); 13583 13584 lfa_sts = REG_RD(sc, params->lfa_base + 13585 offsetof(struct shmem_lfa, lfa_sts)); 13586 13587 /* Clear the "Don't Clear Statistics" bit, and set reason */ 13588 lfa_sts &= ~SHMEM_LFA_DONT_CLEAR_STAT; 13589 13590 /* Set link flap reason */ 13591 lfa_sts &= ~LFA_LINK_FLAP_REASON_MASK; 13592 lfa_sts |= ((lfa_status & LFA_LINK_FLAP_REASON_MASK) << 13593 LFA_LINK_FLAP_REASON_OFFSET); 13594 13595 /* Increment link flap counter */ 13596 lfa_sts = ((lfa_sts & ~LINK_FLAP_COUNT_MASK) | 13597 (((((lfa_sts & LINK_FLAP_COUNT_MASK) >> 13598 LINK_FLAP_COUNT_OFFSET) + 1) & 0xff) 13599 << LINK_FLAP_COUNT_OFFSET)); 13600 REG_WR(sc, params->lfa_base + 13601 offsetof(struct shmem_lfa, lfa_sts), lfa_sts); 13602 /* Proceed with regular link initialization */ 13603 } 13604 13605 elink_status_t elink_phy_init(struct elink_params *params, struct elink_vars *vars) 13606 { 13607 int lfa_status; 13608 struct bxe_softc *sc = params->sc; 13609 ELINK_DEBUG_P0(sc, "Phy Initialization started\n"); 13610 ELINK_DEBUG_P2(sc, "(1) req_speed %d, req_flowctrl %d\n", 13611 params->req_line_speed[0], params->req_flow_ctrl[0]); 13612 ELINK_DEBUG_P2(sc, "(2) req_speed %d, req_flowctrl %d\n", 13613 params->req_line_speed[1], params->req_flow_ctrl[1]); 13614 ELINK_DEBUG_P1(sc, "req_adv_flow_ctrl 0x%x\n", params->req_fc_auto_adv); 13615 vars->link_status = 0; 13616 vars->phy_link_up = 0; 13617 vars->link_up = 0; 13618 vars->line_speed = 0; 13619 vars->duplex = DUPLEX_FULL; 13620 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE; 13621 vars->mac_type = ELINK_MAC_TYPE_NONE; 13622 vars->phy_flags = 0; 13623 vars->check_kr2_recovery_cnt = 0; 13624 params->link_flags = ELINK_PHY_INITIALIZED; 13625 /* Driver opens NIG-BRB filters */ 13626 elink_set_rx_filter(params, 1); 13627 /* Check if link flap can be avoided */ 13628 lfa_status = elink_check_lfa(params); 13629 13630 if (lfa_status == 0) { 13631 ELINK_DEBUG_P0(sc, "Link Flap Avoidance in progress\n"); 13632 return elink_avoid_link_flap(params, vars); 13633 } 13634 13635 ELINK_DEBUG_P1(sc, "Cannot avoid link flap lfa_sta=0x%x\n", 13636 lfa_status); 13637 elink_cannot_avoid_link_flap(params, vars, lfa_status); 13638 13639 /* Disable attentions */ 13640 elink_bits_dis(sc, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4, 13641 (ELINK_NIG_MASK_XGXS0_LINK_STATUS | 13642 ELINK_NIG_MASK_XGXS0_LINK10G | 13643 ELINK_NIG_MASK_SERDES0_LINK_STATUS | 13644 ELINK_NIG_MASK_MI_INT)); 13645 #ifdef ELINK_INCLUDE_EMUL 13646 if (!(params->feature_config_flags & 13647 ELINK_FEATURE_CONFIG_EMUL_DISABLE_EMAC)) 13648 #endif 13649 13650 elink_emac_init(params, vars); 13651 13652 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED) 13653 vars->link_status |= LINK_STATUS_PFC_ENABLED; 13654 13655 if ((params->num_phys == 0) && 13656 !CHIP_REV_IS_SLOW(sc)) { 13657 ELINK_DEBUG_P0(sc, "No phy found for initialization !!\n"); 13658 return ELINK_STATUS_ERROR; 13659 } 13660 set_phy_vars(params, vars); 13661 13662 ELINK_DEBUG_P1(sc, "Num of phys on board: %d\n", params->num_phys); 13663 #ifdef ELINK_INCLUDE_FPGA 13664 if (CHIP_REV_IS_FPGA(sc)) { 13665 return elink_init_fpga(params, vars); 13666 } else 13667 #endif 13668 #ifdef ELINK_INCLUDE_EMUL 13669 if (CHIP_REV_IS_EMUL(sc)) { 13670 return elink_init_emul(params, vars); 13671 } else 13672 #endif 13673 switch (params->loopback_mode) { 13674 case ELINK_LOOPBACK_BMAC: 13675 elink_init_bmac_loopback(params, vars); 13676 break; 13677 case ELINK_LOOPBACK_EMAC: 13678 elink_init_emac_loopback(params, vars); 13679 break; 13680 case ELINK_LOOPBACK_XMAC: 13681 elink_init_xmac_loopback(params, vars); 13682 break; 13683 case ELINK_LOOPBACK_UMAC: 13684 elink_init_umac_loopback(params, vars); 13685 break; 13686 case ELINK_LOOPBACK_XGXS: 13687 case ELINK_LOOPBACK_EXT_PHY: 13688 elink_init_xgxs_loopback(params, vars); 13689 break; 13690 default: 13691 if (!CHIP_IS_E3(sc)) { 13692 if (params->switch_cfg == ELINK_SWITCH_CFG_10G) 13693 elink_xgxs_deassert(params); 13694 else 13695 elink_serdes_deassert(sc, params->port); 13696 } 13697 elink_link_initialize(params, vars); 13698 DELAY(1000 * 30); 13699 elink_link_int_enable(params); 13700 break; 13701 } 13702 elink_update_mng(params, vars->link_status); 13703 13704 elink_update_mng_eee(params, vars->eee_status); 13705 return ELINK_STATUS_OK; 13706 } 13707 13708 elink_status_t elink_link_reset(struct elink_params *params, struct elink_vars *vars, 13709 uint8_t reset_ext_phy) 13710 { 13711 struct bxe_softc *sc = params->sc; 13712 uint8_t phy_index, port = params->port, clear_latch_ind = 0; 13713 ELINK_DEBUG_P1(sc, "Resetting the link of port %d\n", port); 13714 /* Disable attentions */ 13715 vars->link_status = 0; 13716 elink_update_mng(params, vars->link_status); 13717 vars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK | 13718 SHMEM_EEE_ACTIVE_BIT); 13719 elink_update_mng_eee(params, vars->eee_status); 13720 elink_bits_dis(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 13721 (ELINK_NIG_MASK_XGXS0_LINK_STATUS | 13722 ELINK_NIG_MASK_XGXS0_LINK10G | 13723 ELINK_NIG_MASK_SERDES0_LINK_STATUS | 13724 ELINK_NIG_MASK_MI_INT)); 13725 13726 /* Activate nig drain */ 13727 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1); 13728 13729 /* Disable nig egress interface */ 13730 if (!CHIP_IS_E3(sc)) { 13731 REG_WR(sc, NIG_REG_BMAC0_OUT_EN + port*4, 0); 13732 REG_WR(sc, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0); 13733 } 13734 13735 #ifdef ELINK_INCLUDE_EMUL 13736 /* Stop BigMac rx */ 13737 if (!(params->feature_config_flags & 13738 ELINK_FEATURE_CONFIG_EMUL_DISABLE_BMAC)) 13739 #endif 13740 if (!CHIP_IS_E3(sc)) 13741 elink_set_bmac_rx(sc, params->chip_id, port, 0); 13742 #ifdef ELINK_INCLUDE_EMUL 13743 /* Stop XMAC/UMAC rx */ 13744 if (!(params->feature_config_flags & 13745 ELINK_FEATURE_CONFIG_EMUL_DISABLE_XMAC)) 13746 #endif 13747 if (CHIP_IS_E3(sc) && 13748 !CHIP_REV_IS_FPGA(sc)) { 13749 elink_set_xmac_rxtx(params, 0); 13750 elink_set_umac_rxtx(params, 0); 13751 } 13752 /* Disable emac */ 13753 if (!CHIP_IS_E3(sc)) 13754 REG_WR(sc, NIG_REG_NIG_EMAC0_EN + port*4, 0); 13755 13756 DELAY(1000 * 10); 13757 /* The PHY reset is controlled by GPIO 1 13758 * Hold it as vars low 13759 */ 13760 /* Clear link led */ 13761 elink_set_mdio_emac_per_phy(sc, params); 13762 elink_set_led(params, vars, ELINK_LED_MODE_OFF, 0); 13763 13764 if (reset_ext_phy && (!CHIP_REV_IS_SLOW(sc))) { 13765 for (phy_index = ELINK_EXT_PHY1; phy_index < params->num_phys; 13766 phy_index++) { 13767 if (params->phy[phy_index].link_reset) { 13768 elink_set_aer_mmd(params, 13769 ¶ms->phy[phy_index]); 13770 params->phy[phy_index].link_reset( 13771 ¶ms->phy[phy_index], 13772 params); 13773 } 13774 if (params->phy[phy_index].flags & 13775 ELINK_FLAGS_REARM_LATCH_SIGNAL) 13776 clear_latch_ind = 1; 13777 } 13778 } 13779 13780 if (clear_latch_ind) { 13781 /* Clear latching indication */ 13782 elink_rearm_latch_signal(sc, port, 0); 13783 elink_bits_dis(sc, NIG_REG_LATCH_BC_0 + port*4, 13784 1 << ELINK_NIG_LATCH_BC_ENABLE_MI_INT); 13785 } 13786 #if defined(ELINK_INCLUDE_EMUL) || defined(ELINK_INCLUDE_FPGA) 13787 if (!CHIP_REV_IS_SLOW(sc)) 13788 #endif 13789 if (params->phy[ELINK_INT_PHY].link_reset) 13790 params->phy[ELINK_INT_PHY].link_reset( 13791 ¶ms->phy[ELINK_INT_PHY], params); 13792 13793 /* Disable nig ingress interface */ 13794 if (!CHIP_IS_E3(sc)) { 13795 /* Reset BigMac */ 13796 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 13797 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port)); 13798 REG_WR(sc, NIG_REG_BMAC0_IN_EN + port*4, 0); 13799 REG_WR(sc, NIG_REG_EMAC0_IN_EN + port*4, 0); 13800 } else { 13801 uint32_t xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; 13802 elink_set_xumac_nig(params, 0, 0); 13803 if (REG_RD(sc, MISC_REG_RESET_REG_2) & 13804 MISC_REGISTERS_RESET_REG_2_XMAC) 13805 REG_WR(sc, xmac_base + XMAC_REG_CTRL, 13806 XMAC_CTRL_REG_SOFT_RESET); 13807 } 13808 vars->link_up = 0; 13809 vars->phy_flags = 0; 13810 return ELINK_STATUS_OK; 13811 } 13812 elink_status_t elink_lfa_reset(struct elink_params *params, 13813 struct elink_vars *vars) 13814 { 13815 struct bxe_softc *sc = params->sc; 13816 vars->link_up = 0; 13817 vars->phy_flags = 0; 13818 params->link_flags &= ~ELINK_PHY_INITIALIZED; 13819 if (!params->lfa_base) 13820 return elink_link_reset(params, vars, 1); 13821 /* 13822 * Activate NIG drain so that during this time the device won't send 13823 * anything while it is unable to response. 13824 */ 13825 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1); 13826 13827 /* 13828 * Close gracefully the gate from BMAC to NIG such that no half packets 13829 * are passed. 13830 */ 13831 if (!CHIP_IS_E3(sc)) 13832 elink_set_bmac_rx(sc, params->chip_id, params->port, 0); 13833 13834 if (CHIP_IS_E3(sc)) { 13835 elink_set_xmac_rxtx(params, 0); 13836 elink_set_umac_rxtx(params, 0); 13837 } 13838 /* Wait 10ms for the pipe to clean up*/ 13839 DELAY(1000 * 10); 13840 13841 /* Clean the NIG-BRB using the network filters in a way that will 13842 * not cut a packet in the middle. 13843 */ 13844 elink_set_rx_filter(params, 0); 13845 13846 /* 13847 * Re-open the gate between the BMAC and the NIG, after verifying the 13848 * gate to the BRB is closed, otherwise packets may arrive to the 13849 * firmware before driver had initialized it. The target is to achieve 13850 * minimum management protocol down time. 13851 */ 13852 if (!CHIP_IS_E3(sc)) 13853 elink_set_bmac_rx(sc, params->chip_id, params->port, 1); 13854 13855 if (CHIP_IS_E3(sc)) { 13856 elink_set_xmac_rxtx(params, 1); 13857 elink_set_umac_rxtx(params, 1); 13858 } 13859 /* Disable NIG drain */ 13860 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); 13861 return ELINK_STATUS_OK; 13862 } 13863 13864 /****************************************************************************/ 13865 /* Common function */ 13866 /****************************************************************************/ 13867 static elink_status_t elink_8073_common_init_phy(struct bxe_softc *sc, 13868 uint32_t shmem_base_path[], 13869 uint32_t shmem2_base_path[], uint8_t phy_index, 13870 uint32_t chip_id) 13871 { 13872 struct elink_phy phy[PORT_MAX]; 13873 struct elink_phy *phy_blk[PORT_MAX]; 13874 uint16_t val; 13875 int8_t port = 0; 13876 int8_t port_of_path = 0; 13877 uint32_t swap_val, swap_override; 13878 swap_val = REG_RD(sc, NIG_REG_PORT_SWAP); 13879 swap_override = REG_RD(sc, NIG_REG_STRAP_OVERRIDE); 13880 port ^= (swap_val && swap_override); 13881 elink_ext_phy_hw_reset(sc, port); 13882 /* PART1 - Reset both phys */ 13883 for (port = PORT_MAX - 1; port >= PORT_0; port--) { 13884 uint32_t shmem_base, shmem2_base; 13885 /* In E2, same phy is using for port0 of the two paths */ 13886 if (CHIP_IS_E1x(sc)) { 13887 shmem_base = shmem_base_path[0]; 13888 shmem2_base = shmem2_base_path[0]; 13889 port_of_path = port; 13890 } else { 13891 shmem_base = shmem_base_path[port]; 13892 shmem2_base = shmem2_base_path[port]; 13893 port_of_path = 0; 13894 } 13895 13896 /* Extract the ext phy address for the port */ 13897 if (elink_populate_phy(sc, phy_index, shmem_base, shmem2_base, 13898 port_of_path, &phy[port]) != 13899 ELINK_STATUS_OK) { 13900 ELINK_DEBUG_P0(sc, "populate_phy failed\n"); 13901 return ELINK_STATUS_ERROR; 13902 } 13903 /* Disable attentions */ 13904 elink_bits_dis(sc, NIG_REG_MASK_INTERRUPT_PORT0 + 13905 port_of_path*4, 13906 (ELINK_NIG_MASK_XGXS0_LINK_STATUS | 13907 ELINK_NIG_MASK_XGXS0_LINK10G | 13908 ELINK_NIG_MASK_SERDES0_LINK_STATUS | 13909 ELINK_NIG_MASK_MI_INT)); 13910 13911 /* Need to take the phy out of low power mode in order 13912 * to write to access its registers 13913 */ 13914 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2, 13915 MISC_REGISTERS_GPIO_OUTPUT_HIGH, 13916 port); 13917 13918 /* Reset the phy */ 13919 elink_cl45_write(sc, &phy[port], 13920 MDIO_PMA_DEVAD, 13921 MDIO_PMA_REG_CTRL, 13922 1<<15); 13923 } 13924 13925 /* Add delay of 150ms after reset */ 13926 DELAY(1000 * 150); 13927 13928 if (phy[PORT_0].addr & 0x1) { 13929 phy_blk[PORT_0] = &(phy[PORT_1]); 13930 phy_blk[PORT_1] = &(phy[PORT_0]); 13931 } else { 13932 phy_blk[PORT_0] = &(phy[PORT_0]); 13933 phy_blk[PORT_1] = &(phy[PORT_1]); 13934 } 13935 13936 /* PART2 - Download firmware to both phys */ 13937 for (port = PORT_MAX - 1; port >= PORT_0; port--) { 13938 if (CHIP_IS_E1x(sc)) 13939 port_of_path = port; 13940 else 13941 port_of_path = 0; 13942 13943 ELINK_DEBUG_P1(sc, "Loading spirom for phy address 0x%x\n", 13944 phy_blk[port]->addr); 13945 if (elink_8073_8727_external_rom_boot(sc, phy_blk[port], 13946 port_of_path)) 13947 return ELINK_STATUS_ERROR; 13948 13949 /* Only set bit 10 = 1 (Tx power down) */ 13950 elink_cl45_read(sc, phy_blk[port], 13951 MDIO_PMA_DEVAD, 13952 MDIO_PMA_REG_TX_POWER_DOWN, &val); 13953 13954 /* Phase1 of TX_POWER_DOWN reset */ 13955 elink_cl45_write(sc, phy_blk[port], 13956 MDIO_PMA_DEVAD, 13957 MDIO_PMA_REG_TX_POWER_DOWN, 13958 (val | 1<<10)); 13959 } 13960 13961 /* Toggle Transmitter: Power down and then up with 600ms delay 13962 * between 13963 */ 13964 DELAY(1000 * 600); 13965 13966 /* PART3 - complete TX_POWER_DOWN process, and set GPIO2 back to low */ 13967 for (port = PORT_MAX - 1; port >= PORT_0; port--) { 13968 /* Phase2 of POWER_DOWN_RESET */ 13969 /* Release bit 10 (Release Tx power down) */ 13970 elink_cl45_read(sc, phy_blk[port], 13971 MDIO_PMA_DEVAD, 13972 MDIO_PMA_REG_TX_POWER_DOWN, &val); 13973 13974 elink_cl45_write(sc, phy_blk[port], 13975 MDIO_PMA_DEVAD, 13976 MDIO_PMA_REG_TX_POWER_DOWN, (val & (~(1<<10)))); 13977 DELAY(1000 * 15); 13978 13979 /* Read modify write the SPI-ROM version select register */ 13980 elink_cl45_read(sc, phy_blk[port], 13981 MDIO_PMA_DEVAD, 13982 MDIO_PMA_REG_EDC_FFE_MAIN, &val); 13983 elink_cl45_write(sc, phy_blk[port], 13984 MDIO_PMA_DEVAD, 13985 MDIO_PMA_REG_EDC_FFE_MAIN, (val | (1<<12))); 13986 13987 /* set GPIO2 back to LOW */ 13988 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2, 13989 MISC_REGISTERS_GPIO_OUTPUT_LOW, port); 13990 } 13991 return ELINK_STATUS_OK; 13992 } 13993 static elink_status_t elink_8726_common_init_phy(struct bxe_softc *sc, 13994 uint32_t shmem_base_path[], 13995 uint32_t shmem2_base_path[], uint8_t phy_index, 13996 uint32_t chip_id) 13997 { 13998 uint32_t val; 13999 int8_t port; 14000 struct elink_phy phy; 14001 /* Use port1 because of the static port-swap */ 14002 /* Enable the module detection interrupt */ 14003 val = REG_RD(sc, MISC_REG_GPIO_EVENT_EN); 14004 val |= ((1<<MISC_REGISTERS_GPIO_3)| 14005 (1<<(MISC_REGISTERS_GPIO_3 + MISC_REGISTERS_GPIO_PORT_SHIFT))); 14006 REG_WR(sc, MISC_REG_GPIO_EVENT_EN, val); 14007 14008 elink_ext_phy_hw_reset(sc, 0); 14009 DELAY(1000 * 5); 14010 for (port = 0; port < PORT_MAX; port++) { 14011 uint32_t shmem_base, shmem2_base; 14012 14013 /* In E2, same phy is using for port0 of the two paths */ 14014 if (CHIP_IS_E1x(sc)) { 14015 shmem_base = shmem_base_path[0]; 14016 shmem2_base = shmem2_base_path[0]; 14017 } else { 14018 shmem_base = shmem_base_path[port]; 14019 shmem2_base = shmem2_base_path[port]; 14020 } 14021 /* Extract the ext phy address for the port */ 14022 if (elink_populate_phy(sc, phy_index, shmem_base, shmem2_base, 14023 port, &phy) != 14024 ELINK_STATUS_OK) { 14025 ELINK_DEBUG_P0(sc, "populate phy failed\n"); 14026 return ELINK_STATUS_ERROR; 14027 } 14028 14029 /* Reset phy*/ 14030 elink_cl45_write(sc, &phy, 14031 MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001); 14032 14033 14034 /* Set fault module detected LED on */ 14035 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_0, 14036 MISC_REGISTERS_GPIO_HIGH, 14037 port); 14038 } 14039 14040 return ELINK_STATUS_OK; 14041 } 14042 static void elink_get_ext_phy_reset_gpio(struct bxe_softc *sc, uint32_t shmem_base, 14043 uint8_t *io_gpio, uint8_t *io_port) 14044 { 14045 14046 uint32_t phy_gpio_reset = REG_RD(sc, shmem_base + 14047 offsetof(struct shmem_region, 14048 dev_info.port_hw_config[PORT_0].default_cfg)); 14049 switch (phy_gpio_reset) { 14050 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0: 14051 *io_gpio = 0; 14052 *io_port = 0; 14053 break; 14054 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0: 14055 *io_gpio = 1; 14056 *io_port = 0; 14057 break; 14058 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0: 14059 *io_gpio = 2; 14060 *io_port = 0; 14061 break; 14062 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0: 14063 *io_gpio = 3; 14064 *io_port = 0; 14065 break; 14066 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1: 14067 *io_gpio = 0; 14068 *io_port = 1; 14069 break; 14070 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1: 14071 *io_gpio = 1; 14072 *io_port = 1; 14073 break; 14074 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1: 14075 *io_gpio = 2; 14076 *io_port = 1; 14077 break; 14078 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1: 14079 *io_gpio = 3; 14080 *io_port = 1; 14081 break; 14082 default: 14083 /* Don't override the io_gpio and io_port */ 14084 break; 14085 } 14086 } 14087 14088 static elink_status_t elink_8727_common_init_phy(struct bxe_softc *sc, 14089 uint32_t shmem_base_path[], 14090 uint32_t shmem2_base_path[], uint8_t phy_index, 14091 uint32_t chip_id) 14092 { 14093 int8_t port, reset_gpio; 14094 uint32_t swap_val, swap_override; 14095 struct elink_phy phy[PORT_MAX]; 14096 struct elink_phy *phy_blk[PORT_MAX]; 14097 int8_t port_of_path; 14098 swap_val = REG_RD(sc, NIG_REG_PORT_SWAP); 14099 swap_override = REG_RD(sc, NIG_REG_STRAP_OVERRIDE); 14100 14101 reset_gpio = MISC_REGISTERS_GPIO_1; 14102 port = 1; 14103 14104 /* Retrieve the reset gpio/port which control the reset. 14105 * Default is GPIO1, PORT1 14106 */ 14107 elink_get_ext_phy_reset_gpio(sc, shmem_base_path[0], 14108 (uint8_t *)&reset_gpio, (uint8_t *)&port); 14109 14110 /* Calculate the port based on port swap */ 14111 port ^= (swap_val && swap_override); 14112 14113 /* Initiate PHY reset*/ 14114 elink_cb_gpio_write(sc, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_LOW, 14115 port); 14116 DELAY(1000 * 1); 14117 elink_cb_gpio_write(sc, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_HIGH, 14118 port); 14119 14120 DELAY(1000 * 5); 14121 14122 /* PART1 - Reset both phys */ 14123 for (port = PORT_MAX - 1; port >= PORT_0; port--) { 14124 uint32_t shmem_base, shmem2_base; 14125 14126 /* In E2, same phy is using for port0 of the two paths */ 14127 if (CHIP_IS_E1x(sc)) { 14128 shmem_base = shmem_base_path[0]; 14129 shmem2_base = shmem2_base_path[0]; 14130 port_of_path = port; 14131 } else { 14132 shmem_base = shmem_base_path[port]; 14133 shmem2_base = shmem2_base_path[port]; 14134 port_of_path = 0; 14135 } 14136 14137 /* Extract the ext phy address for the port */ 14138 if (elink_populate_phy(sc, phy_index, shmem_base, shmem2_base, 14139 port_of_path, &phy[port]) != 14140 ELINK_STATUS_OK) { 14141 ELINK_DEBUG_P0(sc, "populate phy failed\n"); 14142 return ELINK_STATUS_ERROR; 14143 } 14144 /* disable attentions */ 14145 elink_bits_dis(sc, NIG_REG_MASK_INTERRUPT_PORT0 + 14146 port_of_path*4, 14147 (ELINK_NIG_MASK_XGXS0_LINK_STATUS | 14148 ELINK_NIG_MASK_XGXS0_LINK10G | 14149 ELINK_NIG_MASK_SERDES0_LINK_STATUS | 14150 ELINK_NIG_MASK_MI_INT)); 14151 14152 14153 /* Reset the phy */ 14154 elink_cl45_write(sc, &phy[port], 14155 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15); 14156 } 14157 14158 /* Add delay of 150ms after reset */ 14159 DELAY(1000 * 150); 14160 if (phy[PORT_0].addr & 0x1) { 14161 phy_blk[PORT_0] = &(phy[PORT_1]); 14162 phy_blk[PORT_1] = &(phy[PORT_0]); 14163 } else { 14164 phy_blk[PORT_0] = &(phy[PORT_0]); 14165 phy_blk[PORT_1] = &(phy[PORT_1]); 14166 } 14167 /* PART2 - Download firmware to both phys */ 14168 for (port = PORT_MAX - 1; port >= PORT_0; port--) { 14169 if (CHIP_IS_E1x(sc)) 14170 port_of_path = port; 14171 else 14172 port_of_path = 0; 14173 ELINK_DEBUG_P1(sc, "Loading spirom for phy address 0x%x\n", 14174 phy_blk[port]->addr); 14175 if (elink_8073_8727_external_rom_boot(sc, phy_blk[port], 14176 port_of_path)) 14177 return ELINK_STATUS_ERROR; 14178 /* Disable PHY transmitter output */ 14179 elink_cl45_write(sc, phy_blk[port], 14180 MDIO_PMA_DEVAD, 14181 MDIO_PMA_REG_TX_DISABLE, 1); 14182 14183 } 14184 return ELINK_STATUS_OK; 14185 } 14186 14187 static elink_status_t elink_84833_common_init_phy(struct bxe_softc *sc, 14188 uint32_t shmem_base_path[], 14189 uint32_t shmem2_base_path[], 14190 uint8_t phy_index, 14191 uint32_t chip_id) 14192 { 14193 uint8_t reset_gpios; 14194 reset_gpios = elink_84833_get_reset_gpios(sc, shmem_base_path, chip_id); 14195 elink_cb_gpio_mult_write(sc, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW); 14196 DELAY(10); 14197 elink_cb_gpio_mult_write(sc, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_HIGH); 14198 ELINK_DEBUG_P1(sc, "84833 reset pulse on pin values 0x%x\n", 14199 reset_gpios); 14200 return ELINK_STATUS_OK; 14201 } 14202 static elink_status_t elink_ext_phy_common_init(struct bxe_softc *sc, uint32_t shmem_base_path[], 14203 uint32_t shmem2_base_path[], uint8_t phy_index, 14204 uint32_t ext_phy_type, uint32_t chip_id) 14205 { 14206 elink_status_t rc = ELINK_STATUS_OK; 14207 14208 switch (ext_phy_type) { 14209 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073: 14210 rc = elink_8073_common_init_phy(sc, shmem_base_path, 14211 shmem2_base_path, 14212 phy_index, chip_id); 14213 break; 14214 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722: 14215 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727: 14216 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC: 14217 rc = elink_8727_common_init_phy(sc, shmem_base_path, 14218 shmem2_base_path, 14219 phy_index, chip_id); 14220 break; 14221 14222 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726: 14223 /* GPIO1 affects both ports, so there's need to pull 14224 * it for single port alone 14225 */ 14226 rc = elink_8726_common_init_phy(sc, shmem_base_path, 14227 shmem2_base_path, 14228 phy_index, chip_id); 14229 break; 14230 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833: 14231 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834: 14232 /* GPIO3's are linked, and so both need to be toggled 14233 * to obtain required 2us pulse. 14234 */ 14235 rc = elink_84833_common_init_phy(sc, shmem_base_path, 14236 shmem2_base_path, 14237 phy_index, chip_id); 14238 break; 14239 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE: 14240 rc = ELINK_STATUS_ERROR; 14241 break; 14242 default: 14243 ELINK_DEBUG_P1(sc, 14244 "ext_phy 0x%x common init not required\n", 14245 ext_phy_type); 14246 break; 14247 } 14248 14249 if (rc != ELINK_STATUS_OK) 14250 elink_cb_event_log(sc, ELINK_LOG_ID_PHY_UNINITIALIZED, 0); // "Warning: PHY was not initialized," 14251 // " Port %d\n", 14252 14253 return rc; 14254 } 14255 14256 elink_status_t elink_common_init_phy(struct bxe_softc *sc, uint32_t shmem_base_path[], 14257 uint32_t shmem2_base_path[], uint32_t chip_id, 14258 uint8_t one_port_enabled) 14259 { 14260 elink_status_t rc = ELINK_STATUS_OK; 14261 uint32_t phy_ver, val; 14262 uint8_t phy_index = 0; 14263 uint32_t ext_phy_type, ext_phy_config; 14264 #if defined(ELINK_INCLUDE_EMUL) || defined(ELINK_INCLUDE_FPGA) 14265 if (CHIP_REV_IS_EMUL(sc) || CHIP_REV_IS_FPGA(sc)) 14266 return ELINK_STATUS_OK; 14267 #endif 14268 14269 elink_set_mdio_clk(sc, chip_id, GRCBASE_EMAC0); 14270 elink_set_mdio_clk(sc, chip_id, GRCBASE_EMAC1); 14271 ELINK_DEBUG_P0(sc, "Begin common phy init\n"); 14272 if (CHIP_IS_E3(sc)) { 14273 /* Enable EPIO */ 14274 val = REG_RD(sc, MISC_REG_GEN_PURP_HWG); 14275 REG_WR(sc, MISC_REG_GEN_PURP_HWG, val | 1); 14276 } 14277 /* Check if common init was already done */ 14278 phy_ver = REG_RD(sc, shmem_base_path[0] + 14279 offsetof(struct shmem_region, 14280 port_mb[PORT_0].ext_phy_fw_version)); 14281 if (phy_ver) { 14282 ELINK_DEBUG_P1(sc, "Not doing common init; phy ver is 0x%x\n", 14283 phy_ver); 14284 return ELINK_STATUS_OK; 14285 } 14286 14287 /* Read the ext_phy_type for arbitrary port(0) */ 14288 for (phy_index = ELINK_EXT_PHY1; phy_index < ELINK_MAX_PHYS; 14289 phy_index++) { 14290 ext_phy_config = elink_get_ext_phy_config(sc, 14291 shmem_base_path[0], 14292 phy_index, 0); 14293 ext_phy_type = ELINK_XGXS_EXT_PHY_TYPE(ext_phy_config); 14294 rc |= elink_ext_phy_common_init(sc, shmem_base_path, 14295 shmem2_base_path, 14296 phy_index, ext_phy_type, 14297 chip_id); 14298 } 14299 return rc; 14300 } 14301 14302 static void elink_check_over_curr(struct elink_params *params, 14303 struct elink_vars *vars) 14304 { 14305 struct bxe_softc *sc = params->sc; 14306 uint32_t cfg_pin; 14307 uint8_t port = params->port; 14308 uint32_t pin_val; 14309 14310 cfg_pin = (REG_RD(sc, params->shmem_base + 14311 offsetof(struct shmem_region, 14312 dev_info.port_hw_config[port].e3_cmn_pin_cfg1)) & 14313 PORT_HW_CFG_E3_OVER_CURRENT_MASK) >> 14314 PORT_HW_CFG_E3_OVER_CURRENT_SHIFT; 14315 14316 /* Ignore check if no external input PIN available */ 14317 if (elink_get_cfg_pin(sc, cfg_pin, &pin_val) != ELINK_STATUS_OK) 14318 return; 14319 14320 if (!pin_val) { 14321 if ((vars->phy_flags & PHY_OVER_CURRENT_FLAG) == 0) { 14322 elink_cb_event_log(sc, ELINK_LOG_ID_OVER_CURRENT, params->port); //"Error: Power fault on Port %d has" 14323 // " been detected and the power to " 14324 // "that SFP+ module has been removed" 14325 // " to prevent failure of the card." 14326 // " Please remove the SFP+ module and" 14327 // " restart the system to clear this" 14328 // " error.\n", 14329 vars->phy_flags |= PHY_OVER_CURRENT_FLAG; 14330 elink_warpcore_power_module(params, 0); 14331 } 14332 } else 14333 vars->phy_flags &= ~PHY_OVER_CURRENT_FLAG; 14334 } 14335 14336 /* Returns 0 if no change occured since last check; 1 otherwise. */ 14337 static uint8_t elink_analyze_link_error(struct elink_params *params, 14338 struct elink_vars *vars, uint32_t status, 14339 uint32_t phy_flag, uint32_t link_flag, uint8_t notify) 14340 { 14341 struct bxe_softc *sc = params->sc; 14342 /* Compare new value with previous value */ 14343 uint8_t led_mode; 14344 uint32_t old_status = (vars->phy_flags & phy_flag) ? 1 : 0; 14345 14346 if ((status ^ old_status) == 0) 14347 return 0; 14348 14349 /* If values differ */ 14350 switch (phy_flag) { 14351 case PHY_HALF_OPEN_CONN_FLAG: 14352 ELINK_DEBUG_P0(sc, "Analyze Remote Fault\n"); 14353 break; 14354 case PHY_SFP_TX_FAULT_FLAG: 14355 ELINK_DEBUG_P0(sc, "Analyze TX Fault\n"); 14356 break; 14357 default: 14358 ELINK_DEBUG_P0(sc, "Analyze UNKNOWN\n"); 14359 } 14360 ELINK_DEBUG_P3(sc, "Link changed:[%x %x]->%x\n", vars->link_up, 14361 old_status, status); 14362 14363 /* a. Update shmem->link_status accordingly 14364 * b. Update elink_vars->link_up 14365 */ 14366 if (status) { 14367 vars->link_status &= ~LINK_STATUS_LINK_UP; 14368 vars->link_status |= link_flag; 14369 vars->link_up = 0; 14370 vars->phy_flags |= phy_flag; 14371 14372 /* activate nig drain */ 14373 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1); 14374 /* Set LED mode to off since the PHY doesn't know about these 14375 * errors 14376 */ 14377 led_mode = ELINK_LED_MODE_OFF; 14378 } else { 14379 vars->link_status |= LINK_STATUS_LINK_UP; 14380 vars->link_status &= ~link_flag; 14381 vars->link_up = 1; 14382 vars->phy_flags &= ~phy_flag; 14383 led_mode = ELINK_LED_MODE_OPER; 14384 14385 /* Clear nig drain */ 14386 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0); 14387 } 14388 elink_sync_link(params, vars); 14389 /* Update the LED according to the link state */ 14390 elink_set_led(params, vars, led_mode, ELINK_SPEED_10000); 14391 14392 /* Update link status in the shared memory */ 14393 elink_update_mng(params, vars->link_status); 14394 14395 /* C. Trigger General Attention */ 14396 vars->periodic_flags |= ELINK_PERIODIC_FLAGS_LINK_EVENT; 14397 if (notify) 14398 elink_cb_notify_link_changed(sc); 14399 14400 return 1; 14401 } 14402 14403 /****************************************************************************** 14404 * Description: 14405 * This function checks for half opened connection change indication. 14406 * When such change occurs, it calls the elink_analyze_link_error 14407 * to check if Remote Fault is set or cleared. Reception of remote fault 14408 * status message in the MAC indicates that the peer's MAC has detected 14409 * a fault, for example, due to break in the TX side of fiber. 14410 * 14411 ******************************************************************************/ 14412 elink_status_t elink_check_half_open_conn(struct elink_params *params, 14413 struct elink_vars *vars, 14414 uint8_t notify) 14415 { 14416 struct bxe_softc *sc = params->sc; 14417 uint32_t lss_status = 0; 14418 uint32_t mac_base; 14419 /* In case link status is physically up @ 10G do */ 14420 if (((vars->phy_flags & PHY_PHYSICAL_LINK_FLAG) == 0) || 14421 (REG_RD(sc, NIG_REG_EGRESS_EMAC0_PORT + params->port*4))) 14422 return ELINK_STATUS_OK; 14423 14424 if (CHIP_IS_E3(sc) && 14425 (REG_RD(sc, MISC_REG_RESET_REG_2) & 14426 (MISC_REGISTERS_RESET_REG_2_XMAC))) { 14427 /* Check E3 XMAC */ 14428 /* Note that link speed cannot be queried here, since it may be 14429 * zero while link is down. In case UMAC is active, LSS will 14430 * simply not be set 14431 */ 14432 mac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; 14433 14434 /* Clear stick bits (Requires rising edge) */ 14435 REG_WR(sc, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0); 14436 REG_WR(sc, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 14437 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS | 14438 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS); 14439 if (REG_RD(sc, mac_base + XMAC_REG_RX_LSS_STATUS)) 14440 lss_status = 1; 14441 14442 elink_analyze_link_error(params, vars, lss_status, 14443 PHY_HALF_OPEN_CONN_FLAG, 14444 LINK_STATUS_NONE, notify); 14445 } else if (REG_RD(sc, MISC_REG_RESET_REG_2) & 14446 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port)) { 14447 /* Check E1X / E2 BMAC */ 14448 uint32_t lss_status_reg; 14449 uint32_t wb_data[2]; 14450 mac_base = params->port ? NIG_REG_INGRESS_BMAC1_MEM : 14451 NIG_REG_INGRESS_BMAC0_MEM; 14452 /* Read BIGMAC_REGISTER_RX_LSS_STATUS */ 14453 if (CHIP_IS_E2(sc)) 14454 lss_status_reg = BIGMAC2_REGISTER_RX_LSS_STAT; 14455 else 14456 lss_status_reg = BIGMAC_REGISTER_RX_LSS_STATUS; 14457 14458 REG_RD_DMAE(sc, mac_base + lss_status_reg, wb_data, 2); 14459 lss_status = (wb_data[0] > 0); 14460 14461 elink_analyze_link_error(params, vars, lss_status, 14462 PHY_HALF_OPEN_CONN_FLAG, 14463 LINK_STATUS_NONE, notify); 14464 } 14465 return ELINK_STATUS_OK; 14466 } 14467 static void elink_sfp_tx_fault_detection(struct elink_phy *phy, 14468 struct elink_params *params, 14469 struct elink_vars *vars) 14470 { 14471 struct bxe_softc *sc = params->sc; 14472 uint32_t cfg_pin, value = 0; 14473 uint8_t led_change, port = params->port; 14474 14475 /* Get The SFP+ TX_Fault controlling pin ([eg]pio) */ 14476 cfg_pin = (REG_RD(sc, params->shmem_base + offsetof(struct shmem_region, 14477 dev_info.port_hw_config[port].e3_cmn_pin_cfg)) & 14478 PORT_HW_CFG_E3_TX_FAULT_MASK) >> 14479 PORT_HW_CFG_E3_TX_FAULT_SHIFT; 14480 14481 if (elink_get_cfg_pin(sc, cfg_pin, &value)) { 14482 ELINK_DEBUG_P1(sc, "Failed to read pin 0x%02x\n", cfg_pin); 14483 return; 14484 } 14485 14486 led_change = elink_analyze_link_error(params, vars, value, 14487 PHY_SFP_TX_FAULT_FLAG, 14488 LINK_STATUS_SFP_TX_FAULT, 1); 14489 14490 if (led_change) { 14491 /* Change TX_Fault led, set link status for further syncs */ 14492 uint8_t led_mode; 14493 14494 if (vars->phy_flags & PHY_SFP_TX_FAULT_FLAG) { 14495 led_mode = MISC_REGISTERS_GPIO_HIGH; 14496 vars->link_status |= LINK_STATUS_SFP_TX_FAULT; 14497 } else { 14498 led_mode = MISC_REGISTERS_GPIO_LOW; 14499 vars->link_status &= ~LINK_STATUS_SFP_TX_FAULT; 14500 } 14501 14502 /* If module is unapproved, led should be on regardless */ 14503 if (!(phy->flags & ELINK_FLAGS_SFP_NOT_APPROVED)) { 14504 ELINK_DEBUG_P1(sc, "Change TX_Fault LED: ->%x\n", 14505 led_mode); 14506 elink_set_e3_module_fault_led(params, led_mode); 14507 } 14508 } 14509 } 14510 static void elink_kr2_recovery(struct elink_params *params, 14511 struct elink_vars *vars, 14512 struct elink_phy *phy) 14513 { 14514 struct bxe_softc *sc = params->sc; 14515 ELINK_DEBUG_P0(sc, "KR2 recovery\n"); 14516 elink_warpcore_enable_AN_KR2(phy, params, vars); 14517 elink_warpcore_restart_AN_KR(phy, params); 14518 } 14519 14520 static void elink_check_kr2_wa(struct elink_params *params, 14521 struct elink_vars *vars, 14522 struct elink_phy *phy) 14523 { 14524 struct bxe_softc *sc = params->sc; 14525 uint16_t base_page, next_page, not_kr2_device, lane; 14526 int sigdet; 14527 14528 /* Once KR2 was disabled, wait 5 seconds before checking KR2 recovery 14529 * Since some switches tend to reinit the AN process and clear the 14530 * the advertised BP/NP after ~2 seconds causing the KR2 to be disabled 14531 * and recovered many times 14532 */ 14533 if (vars->check_kr2_recovery_cnt > 0) { 14534 vars->check_kr2_recovery_cnt--; 14535 return; 14536 } 14537 14538 sigdet = elink_warpcore_get_sigdet(phy, params); 14539 if (!sigdet) { 14540 if (!(vars->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) { 14541 elink_kr2_recovery(params, vars, phy); 14542 ELINK_DEBUG_P0(sc, "No sigdet\n"); 14543 } 14544 return; 14545 } 14546 14547 lane = elink_get_warpcore_lane(phy, params); 14548 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK, 14549 MDIO_AER_BLOCK_AER_REG, lane); 14550 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, 14551 MDIO_AN_REG_LP_AUTO_NEG, &base_page); 14552 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, 14553 MDIO_AN_REG_LP_AUTO_NEG2, &next_page); 14554 elink_set_aer_mmd(params, phy); 14555 14556 /* CL73 has not begun yet */ 14557 if (base_page == 0) { 14558 if (!(vars->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) { 14559 elink_kr2_recovery(params, vars, phy); 14560 ELINK_DEBUG_P0(sc, "No BP\n"); 14561 } 14562 return; 14563 } 14564 14565 /* In case NP bit is not set in the BasePage, or it is set, 14566 * but only KX is advertised, declare this link partner as non-KR2 14567 * device. 14568 */ 14569 not_kr2_device = (((base_page & 0x8000) == 0) || 14570 (((base_page & 0x8000) && 14571 ((next_page & 0xe0) == 0x2)))); 14572 14573 /* In case KR2 is already disabled, check if we need to re-enable it */ 14574 if (!(vars->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) { 14575 if (!not_kr2_device) { 14576 ELINK_DEBUG_P2(sc, "BP=0x%x, NP=0x%x\n", base_page, 14577 next_page); 14578 elink_kr2_recovery(params, vars, phy); 14579 } 14580 return; 14581 } 14582 /* KR2 is enabled, but not KR2 device */ 14583 if (not_kr2_device) { 14584 /* Disable KR2 on both lanes */ 14585 ELINK_DEBUG_P2(sc, "BP=0x%x, NP=0x%x\n", base_page, next_page); 14586 elink_disable_kr2(params, vars, phy); 14587 /* Restart AN on leading lane */ 14588 elink_warpcore_restart_AN_KR(phy, params); 14589 return; 14590 } 14591 } 14592 14593 void elink_period_func(struct elink_params *params, struct elink_vars *vars) 14594 { 14595 uint16_t phy_idx; 14596 struct bxe_softc *sc = params->sc; 14597 for (phy_idx = ELINK_INT_PHY; phy_idx < ELINK_MAX_PHYS; phy_idx++) { 14598 if (params->phy[phy_idx].flags & ELINK_FLAGS_TX_ERROR_CHECK) { 14599 elink_set_aer_mmd(params, ¶ms->phy[phy_idx]); 14600 if (elink_check_half_open_conn(params, vars, 1) != 14601 ELINK_STATUS_OK) 14602 ELINK_DEBUG_P0(sc, "Fault detection failed\n"); 14603 break; 14604 } 14605 } 14606 14607 if (CHIP_IS_E3(sc)) { 14608 struct elink_phy *phy = ¶ms->phy[ELINK_INT_PHY]; 14609 elink_set_aer_mmd(params, phy); 14610 if ((phy->supported & ELINK_SUPPORTED_20000baseKR2_Full) && 14611 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) 14612 elink_check_kr2_wa(params, vars, phy); 14613 elink_check_over_curr(params, vars); 14614 if (vars->rx_tx_asic_rst) 14615 elink_warpcore_config_runtime(phy, params, vars); 14616 14617 if ((REG_RD(sc, params->shmem_base + 14618 offsetof(struct shmem_region, dev_info. 14619 port_hw_config[params->port].default_cfg)) 14620 & PORT_HW_CFG_NET_SERDES_IF_MASK) == 14621 PORT_HW_CFG_NET_SERDES_IF_SFI) { 14622 if (elink_is_sfp_module_plugged(phy, params)) { 14623 elink_sfp_tx_fault_detection(phy, params, vars); 14624 } else if (vars->link_status & 14625 LINK_STATUS_SFP_TX_FAULT) { 14626 /* Clean trail, interrupt corrects the leds */ 14627 vars->link_status &= ~LINK_STATUS_SFP_TX_FAULT; 14628 vars->phy_flags &= ~PHY_SFP_TX_FAULT_FLAG; 14629 /* Update link status in the shared memory */ 14630 elink_update_mng(params, vars->link_status); 14631 } 14632 } 14633 } 14634 } 14635 14636 uint8_t elink_fan_failure_det_req(struct bxe_softc *sc, 14637 uint32_t shmem_base, 14638 uint32_t shmem2_base, 14639 uint8_t port) 14640 { 14641 uint8_t phy_index, fan_failure_det_req = 0; 14642 struct elink_phy phy; 14643 for (phy_index = ELINK_EXT_PHY1; phy_index < ELINK_MAX_PHYS; 14644 phy_index++) { 14645 if (elink_populate_phy(sc, phy_index, shmem_base, shmem2_base, 14646 port, &phy) 14647 != ELINK_STATUS_OK) { 14648 ELINK_DEBUG_P0(sc, "populate phy failed\n"); 14649 return 0; 14650 } 14651 fan_failure_det_req |= (phy.flags & 14652 ELINK_FLAGS_FAN_FAILURE_DET_REQ); 14653 } 14654 return fan_failure_det_req; 14655 } 14656 14657 void elink_hw_reset_phy(struct elink_params *params) 14658 { 14659 uint8_t phy_index; 14660 struct bxe_softc *sc = params->sc; 14661 elink_update_mng(params, 0); 14662 elink_bits_dis(sc, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4, 14663 (ELINK_NIG_MASK_XGXS0_LINK_STATUS | 14664 ELINK_NIG_MASK_XGXS0_LINK10G | 14665 ELINK_NIG_MASK_SERDES0_LINK_STATUS | 14666 ELINK_NIG_MASK_MI_INT)); 14667 14668 for (phy_index = ELINK_INT_PHY; phy_index < ELINK_MAX_PHYS; 14669 phy_index++) { 14670 if (params->phy[phy_index].hw_reset) { 14671 params->phy[phy_index].hw_reset( 14672 ¶ms->phy[phy_index], 14673 params); 14674 params->phy[phy_index] = phy_null; 14675 } 14676 } 14677 } 14678 14679 void elink_init_mod_abs_int(struct bxe_softc *sc, struct elink_vars *vars, 14680 uint32_t chip_id, uint32_t shmem_base, uint32_t shmem2_base, 14681 uint8_t port) 14682 { 14683 uint8_t gpio_num = 0xff, gpio_port = 0xff, phy_index; 14684 uint32_t val; 14685 uint32_t offset, aeu_mask, swap_val, swap_override, sync_offset; 14686 if (CHIP_IS_E3(sc)) { 14687 if (elink_get_mod_abs_int_cfg(sc, chip_id, 14688 shmem_base, 14689 port, 14690 &gpio_num, 14691 &gpio_port) != ELINK_STATUS_OK) 14692 return; 14693 } else { 14694 struct elink_phy phy; 14695 for (phy_index = ELINK_EXT_PHY1; phy_index < ELINK_MAX_PHYS; 14696 phy_index++) { 14697 if (elink_populate_phy(sc, phy_index, shmem_base, 14698 shmem2_base, port, &phy) 14699 != ELINK_STATUS_OK) { 14700 ELINK_DEBUG_P0(sc, "populate phy failed\n"); 14701 return; 14702 } 14703 if (phy.type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) { 14704 gpio_num = MISC_REGISTERS_GPIO_3; 14705 gpio_port = port; 14706 break; 14707 } 14708 } 14709 } 14710 14711 if (gpio_num == 0xff) 14712 return; 14713 14714 /* Set GPIO3 to trigger SFP+ module insertion/removal */ 14715 elink_cb_gpio_write(sc, gpio_num, MISC_REGISTERS_GPIO_INPUT_HI_Z, gpio_port); 14716 14717 swap_val = REG_RD(sc, NIG_REG_PORT_SWAP); 14718 swap_override = REG_RD(sc, NIG_REG_STRAP_OVERRIDE); 14719 gpio_port ^= (swap_val && swap_override); 14720 14721 vars->aeu_int_mask = AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 << 14722 (gpio_num + (gpio_port << 2)); 14723 14724 sync_offset = shmem_base + 14725 offsetof(struct shmem_region, 14726 dev_info.port_hw_config[port].aeu_int_mask); 14727 REG_WR(sc, sync_offset, vars->aeu_int_mask); 14728 14729 ELINK_DEBUG_P3(sc, "Setting MOD_ABS (GPIO%d_P%d) AEU to 0x%x\n", 14730 gpio_num, gpio_port, vars->aeu_int_mask); 14731 14732 if (port == 0) 14733 offset = MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0; 14734 else 14735 offset = MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0; 14736 14737 /* Open appropriate AEU for interrupts */ 14738 aeu_mask = REG_RD(sc, offset); 14739 aeu_mask |= vars->aeu_int_mask; 14740 REG_WR(sc, offset, aeu_mask); 14741 14742 /* Enable the GPIO to trigger interrupt */ 14743 val = REG_RD(sc, MISC_REG_GPIO_EVENT_EN); 14744 val |= 1 << (gpio_num + (gpio_port << 2)); 14745 REG_WR(sc, MISC_REG_GPIO_EVENT_EN, val); 14746 } 14747 14748