1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2007-2014 QLogic Corporation. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 26 * THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #ifndef __BXE_H__ 30 #define __BXE_H__ 31 32 #include <sys/cdefs.h> 33 __FBSDID("$FreeBSD$"); 34 35 #include <sys/param.h> 36 #include <sys/kernel.h> 37 #include <sys/systm.h> 38 #include <sys/lock.h> 39 #include <sys/mutex.h> 40 #include <sys/sx.h> 41 #include <sys/module.h> 42 #include <sys/endian.h> 43 #include <sys/types.h> 44 #include <sys/malloc.h> 45 #include <sys/kobj.h> 46 #include <sys/bus.h> 47 #include <sys/rman.h> 48 #include <sys/socket.h> 49 #include <sys/sockio.h> 50 #include <sys/sysctl.h> 51 #include <sys/smp.h> 52 #include <sys/bitstring.h> 53 #include <sys/limits.h> 54 #include <sys/queue.h> 55 #include <sys/taskqueue.h> 56 #include <contrib/zlib/zlib.h> 57 58 #include <net/debugnet.h> 59 #include <net/if.h> 60 #include <net/if_types.h> 61 #include <net/if_arp.h> 62 #include <net/ethernet.h> 63 #include <net/if_dl.h> 64 #include <net/if_var.h> 65 #include <net/if_media.h> 66 #include <net/if_vlan_var.h> 67 #include <net/bpf.h> 68 69 #include <netinet/in.h> 70 #include <netinet/ip.h> 71 #include <netinet/ip6.h> 72 #include <netinet/tcp.h> 73 #include <netinet/udp.h> 74 75 #include <dev/pci/pcireg.h> 76 #include <dev/pci/pcivar.h> 77 78 #include <machine/atomic.h> 79 #include <machine/resource.h> 80 #include <machine/endian.h> 81 #include <machine/bus.h> 82 #include <machine/in_cksum.h> 83 84 #include "device_if.h" 85 #include "bus_if.h" 86 #include "pci_if.h" 87 88 #if _BYTE_ORDER == _LITTLE_ENDIAN 89 #ifndef LITTLE_ENDIAN 90 #define LITTLE_ENDIAN 91 #endif 92 #ifndef __LITTLE_ENDIAN 93 #define __LITTLE_ENDIAN 94 #endif 95 #undef BIG_ENDIAN 96 #undef __BIG_ENDIAN 97 #else /* _BIG_ENDIAN */ 98 #ifndef BIG_ENDIAN 99 #define BIG_ENDIAN 100 #endif 101 #ifndef __BIG_ENDIAN 102 #define __BIG_ENDIAN 103 #endif 104 #undef LITTLE_ENDIAN 105 #undef __LITTLE_ENDIAN 106 #endif 107 108 #include "ecore_mfw_req.h" 109 #include "ecore_fw_defs.h" 110 #include "ecore_hsi.h" 111 #include "ecore_reg.h" 112 #include "bxe_dcb.h" 113 #include "bxe_stats.h" 114 115 #include "bxe_elink.h" 116 117 #define VF_MAC_CREDIT_CNT 0 118 #define VF_VLAN_CREDIT_CNT (0) 119 120 #ifndef ARRAY_SIZE 121 #define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0])) 122 #endif 123 #ifndef ARRSIZE 124 #define ARRSIZE(arr) (sizeof(arr) / sizeof((arr)[0])) 125 #endif 126 #ifndef DIV_ROUND_UP 127 #define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d)) 128 #endif 129 #ifndef roundup 130 #define roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y)) 131 #endif 132 #ifndef ilog2 133 static inline 134 int bxe_ilog2(int x) 135 { 136 int log = 0; 137 while (x >>= 1) log++; 138 return (log); 139 } 140 #define ilog2(x) bxe_ilog2(x) 141 #endif 142 143 #include "ecore_sp.h" 144 145 #define BRCM_VENDORID 0x14e4 146 #define QLOGIC_VENDORID 0x1077 147 #define PCI_ANY_ID (uint16_t)(~0U) 148 149 struct bxe_device_type 150 { 151 uint16_t bxe_vid; 152 uint16_t bxe_did; 153 uint16_t bxe_svid; 154 uint16_t bxe_sdid; 155 char *bxe_name; 156 }; 157 158 #define BCM_PAGE_SHIFT 12 159 #define BCM_PAGE_SIZE (1 << BCM_PAGE_SHIFT) 160 #define BCM_PAGE_MASK (~(BCM_PAGE_SIZE - 1)) 161 #define BCM_PAGE_ALIGN(addr) ((addr + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK) 162 163 #if BCM_PAGE_SIZE != 4096 164 #error Page sizes other than 4KB are unsupported! 165 #endif 166 167 #if (BUS_SPACE_MAXADDR > 0xFFFFFFFF) 168 #define U64_LO(addr) ((uint32_t)(((uint64_t)(addr)) & 0xFFFFFFFF)) 169 #define U64_HI(addr) ((uint32_t)(((uint64_t)(addr)) >> 32)) 170 #else 171 #define U64_LO(addr) ((uint32_t)(addr)) 172 #define U64_HI(addr) (0) 173 #endif 174 #define HILO_U64(hi, lo) ((((uint64_t)(hi)) << 32) + (lo)) 175 176 #define SET_FLAG(value, mask, flag) \ 177 do { \ 178 (value) &= ~(mask); \ 179 (value) |= ((flag) << (mask##_SHIFT)); \ 180 } while (0) 181 182 #define GET_FLAG(value, mask) \ 183 (((value) & (mask)) >> (mask##_SHIFT)) 184 185 #define GET_FIELD(value, fname) \ 186 (((value) & (fname##_MASK)) >> (fname##_SHIFT)) 187 188 #define BXE_MAX_SEGMENTS 12 /* 13-1 for parsing buffer */ 189 #define BXE_TSO_MAX_SEGMENTS 32 190 #define BXE_TSO_MAX_SIZE (65535 + sizeof(struct ether_vlan_header)) 191 #define BXE_TSO_MAX_SEG_SIZE 4096 192 193 /* dropless fc FW/HW related params */ 194 #define BRB_SIZE(sc) (CHIP_IS_E3(sc) ? 1024 : 512) 195 #define MAX_AGG_QS(sc) (CHIP_IS_E1(sc) ? \ 196 ETH_MAX_AGGREGATION_QUEUES_E1 : \ 197 ETH_MAX_AGGREGATION_QUEUES_E1H_E2) 198 #define FW_DROP_LEVEL(sc) (3 + MAX_SPQ_PENDING + MAX_AGG_QS(sc)) 199 #define FW_PREFETCH_CNT 16 200 #define DROPLESS_FC_HEADROOM 100 201 202 /******************/ 203 /* RX SGE defines */ 204 /******************/ 205 206 #define RX_SGE_NUM_PAGES 2 /* must be a power of 2 */ 207 #define RX_SGE_TOTAL_PER_PAGE (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge)) 208 #define RX_SGE_NEXT_PAGE_DESC_CNT 2 209 #define RX_SGE_USABLE_PER_PAGE (RX_SGE_TOTAL_PER_PAGE - RX_SGE_NEXT_PAGE_DESC_CNT) 210 #define RX_SGE_PER_PAGE_MASK (RX_SGE_TOTAL_PER_PAGE - 1) 211 #define RX_SGE_TOTAL (RX_SGE_TOTAL_PER_PAGE * RX_SGE_NUM_PAGES) 212 #define RX_SGE_USABLE (RX_SGE_USABLE_PER_PAGE * RX_SGE_NUM_PAGES) 213 #define RX_SGE_MAX (RX_SGE_TOTAL - 1) 214 #define RX_SGE(x) ((x) & RX_SGE_MAX) 215 216 #define RX_SGE_NEXT(x) \ 217 ((((x) & RX_SGE_PER_PAGE_MASK) == (RX_SGE_USABLE_PER_PAGE - 1)) \ 218 ? (x) + 1 + RX_SGE_NEXT_PAGE_DESC_CNT : (x) + 1) 219 220 #define RX_SGE_MASK_ELEM_SZ 64 221 #define RX_SGE_MASK_ELEM_SHIFT 6 222 #define RX_SGE_MASK_ELEM_MASK ((uint64_t)RX_SGE_MASK_ELEM_SZ - 1) 223 224 /* 225 * Creates a bitmask of all ones in less significant bits. 226 * idx - index of the most significant bit in the created mask. 227 */ 228 #define RX_SGE_ONES_MASK(idx) \ 229 (((uint64_t)0x1 << (((idx) & RX_SGE_MASK_ELEM_MASK) + 1)) - 1) 230 #define RX_SGE_MASK_ELEM_ONE_MASK ((uint64_t)(~0)) 231 232 /* Number of uint64_t elements in SGE mask array. */ 233 #define RX_SGE_MASK_LEN \ 234 ((RX_SGE_NUM_PAGES * RX_SGE_TOTAL_PER_PAGE) / RX_SGE_MASK_ELEM_SZ) 235 #define RX_SGE_MASK_LEN_MASK (RX_SGE_MASK_LEN - 1) 236 #define RX_SGE_NEXT_MASK_ELEM(el) (((el) + 1) & RX_SGE_MASK_LEN_MASK) 237 238 /* 239 * dropless fc calculations for SGEs 240 * Number of required SGEs is the sum of two: 241 * 1. Number of possible opened aggregations (next packet for 242 * these aggregations will probably consume SGE immidiatelly) 243 * 2. Rest of BRB blocks divided by 2 (block will consume new SGE only 244 * after placement on BD for new TPA aggregation) 245 * Takes into account RX_SGE_NEXT_PAGE_DESC_CNT "next" elements on each page 246 */ 247 #define NUM_SGE_REQ(sc) \ 248 (MAX_AGG_QS(sc) + (BRB_SIZE(sc) - MAX_AGG_QS(sc)) / 2) 249 #define NUM_SGE_PG_REQ(sc) \ 250 ((NUM_SGE_REQ(sc) + RX_SGE_USABLE_PER_PAGE - 1) / RX_SGE_USABLE_PER_PAGE) 251 #define SGE_TH_LO(sc) \ 252 (NUM_SGE_REQ(sc) + NUM_SGE_PG_REQ(sc) * RX_SGE_NEXT_PAGE_DESC_CNT) 253 #define SGE_TH_HI(sc) \ 254 (SGE_TH_LO(sc) + DROPLESS_FC_HEADROOM) 255 256 #define PAGES_PER_SGE_SHIFT 0 257 #define PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT) 258 #define SGE_PAGE_SIZE BCM_PAGE_SIZE 259 #define SGE_PAGE_SHIFT BCM_PAGE_SHIFT 260 #define SGE_PAGE_ALIGN(addr) BCM_PAGE_ALIGN(addr) 261 #define SGE_PAGES (SGE_PAGE_SIZE * PAGES_PER_SGE) 262 #define TPA_AGG_SIZE min((8 * SGE_PAGES), 0xffff) 263 264 /*****************/ 265 /* TX BD defines */ 266 /*****************/ 267 268 #define TX_BD_NUM_PAGES 16 /* must be a power of 2 */ 269 #define TX_BD_TOTAL_PER_PAGE (BCM_PAGE_SIZE / sizeof(union eth_tx_bd_types)) 270 #define TX_BD_USABLE_PER_PAGE (TX_BD_TOTAL_PER_PAGE - 1) 271 #define TX_BD_TOTAL (TX_BD_TOTAL_PER_PAGE * TX_BD_NUM_PAGES) 272 #define TX_BD_USABLE (TX_BD_USABLE_PER_PAGE * TX_BD_NUM_PAGES) 273 #define TX_BD_MAX (TX_BD_TOTAL - 1) 274 275 #define TX_BD_NEXT(x) \ 276 ((((x) & TX_BD_USABLE_PER_PAGE) == (TX_BD_USABLE_PER_PAGE - 1)) ? \ 277 ((x) + 2) : ((x) + 1)) 278 #define TX_BD(x) ((x) & TX_BD_MAX) 279 #define TX_BD_PAGE(x) (((x) & ~TX_BD_USABLE_PER_PAGE) >> 8) 280 #define TX_BD_IDX(x) ((x) & TX_BD_USABLE_PER_PAGE) 281 282 /* 283 * Trigger pending transmits when the number of available BDs is greater 284 * than 1/8 of the total number of usable BDs. 285 */ 286 #define BXE_TX_CLEANUP_THRESHOLD (TX_BD_USABLE / 8) 287 #define BXE_TX_TIMEOUT 5 288 289 /*****************/ 290 /* RX BD defines */ 291 /*****************/ 292 293 #define RX_BD_NUM_PAGES 8 /* power of 2 */ 294 #define RX_BD_TOTAL_PER_PAGE (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd)) 295 #define RX_BD_NEXT_PAGE_DESC_CNT 2 296 #define RX_BD_USABLE_PER_PAGE (RX_BD_TOTAL_PER_PAGE - RX_BD_NEXT_PAGE_DESC_CNT) 297 #define RX_BD_PER_PAGE_MASK (RX_BD_TOTAL_PER_PAGE - 1) 298 #define RX_BD_TOTAL (RX_BD_TOTAL_PER_PAGE * RX_BD_NUM_PAGES) 299 #define RX_BD_USABLE (RX_BD_USABLE_PER_PAGE * RX_BD_NUM_PAGES) 300 #define RX_BD_MAX (RX_BD_TOTAL - 1) 301 302 #define RX_BD_NEXT(x) \ 303 ((((x) & RX_BD_PER_PAGE_MASK) == (RX_BD_USABLE_PER_PAGE - 1)) ? \ 304 ((x) + 3) : ((x) + 1)) 305 #define RX_BD(x) ((x) & RX_BD_MAX) 306 #define RX_BD_PAGE(x) (((x) & ~RX_BD_PER_PAGE_MASK) >> 9) 307 #define RX_BD_IDX(x) ((x) & RX_BD_PER_PAGE_MASK) 308 309 /* 310 * dropless fc calculations for BDs 311 * Number of BDs should be as number of buffers in BRB: 312 * Low threshold takes into account RX_BD_NEXT_PAGE_DESC_CNT 313 * "next" elements on each page 314 */ 315 #define NUM_BD_REQ(sc) \ 316 BRB_SIZE(sc) 317 #define NUM_BD_PG_REQ(sc) \ 318 ((NUM_BD_REQ(sc) + RX_BD_USABLE_PER_PAGE - 1) / RX_BD_USABLE_PER_PAGE) 319 #define BD_TH_LO(sc) \ 320 (NUM_BD_REQ(sc) + \ 321 NUM_BD_PG_REQ(sc) * RX_BD_NEXT_PAGE_DESC_CNT + \ 322 FW_DROP_LEVEL(sc)) 323 #define BD_TH_HI(sc) \ 324 (BD_TH_LO(sc) + DROPLESS_FC_HEADROOM) 325 #define MIN_RX_AVAIL(sc) \ 326 ((sc)->dropless_fc ? BD_TH_HI(sc) + 128 : 128) 327 #define MIN_RX_SIZE_TPA_HW(sc) \ 328 (CHIP_IS_E1(sc) ? ETH_MIN_RX_CQES_WITH_TPA_E1 : \ 329 ETH_MIN_RX_CQES_WITH_TPA_E1H_E2) 330 #define MIN_RX_SIZE_NONTPA_HW ETH_MIN_RX_CQES_WITHOUT_TPA 331 #define MIN_RX_SIZE_TPA(sc) \ 332 (max(MIN_RX_SIZE_TPA_HW(sc), MIN_RX_AVAIL(sc))) 333 #define MIN_RX_SIZE_NONTPA(sc) \ 334 (max(MIN_RX_SIZE_NONTPA_HW, MIN_RX_AVAIL(sc))) 335 336 /***************/ 337 /* RCQ defines */ 338 /***************/ 339 340 /* 341 * As long as CQE is X times bigger than BD entry we have to allocate X times 342 * more pages for CQ ring in order to keep it balanced with BD ring 343 */ 344 #define CQE_BD_REL (sizeof(union eth_rx_cqe) / \ 345 sizeof(struct eth_rx_bd)) 346 #define RCQ_NUM_PAGES (RX_BD_NUM_PAGES * CQE_BD_REL) /* power of 2 */ 347 #define RCQ_TOTAL_PER_PAGE (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe)) 348 #define RCQ_NEXT_PAGE_DESC_CNT 1 349 #define RCQ_USABLE_PER_PAGE (RCQ_TOTAL_PER_PAGE - RCQ_NEXT_PAGE_DESC_CNT) 350 #define RCQ_TOTAL (RCQ_TOTAL_PER_PAGE * RCQ_NUM_PAGES) 351 #define RCQ_USABLE (RCQ_USABLE_PER_PAGE * RCQ_NUM_PAGES) 352 #define RCQ_MAX (RCQ_TOTAL - 1) 353 354 #define RCQ_NEXT(x) \ 355 ((((x) & RCQ_USABLE_PER_PAGE) == (RCQ_USABLE_PER_PAGE - 1)) ? \ 356 ((x) + 1 + RCQ_NEXT_PAGE_DESC_CNT) : ((x) + 1)) 357 #define RCQ(x) ((x) & RCQ_MAX) 358 #define RCQ_PAGE(x) (((x) & ~RCQ_USABLE_PER_PAGE) >> 7) 359 #define RCQ_IDX(x) ((x) & RCQ_USABLE_PER_PAGE) 360 361 /* 362 * dropless fc calculations for RCQs 363 * Number of RCQs should be as number of buffers in BRB: 364 * Low threshold takes into account RCQ_NEXT_PAGE_DESC_CNT 365 * "next" elements on each page 366 */ 367 #define NUM_RCQ_REQ(sc) \ 368 BRB_SIZE(sc) 369 #define NUM_RCQ_PG_REQ(sc) \ 370 ((NUM_RCQ_REQ(sc) + RCQ_USABLE_PER_PAGE - 1) / RCQ_USABLE_PER_PAGE) 371 #define RCQ_TH_LO(sc) \ 372 (NUM_RCQ_REQ(sc) + \ 373 NUM_RCQ_PG_REQ(sc) * RCQ_NEXT_PAGE_DESC_CNT + \ 374 FW_DROP_LEVEL(sc)) 375 #define RCQ_TH_HI(sc) \ 376 (RCQ_TH_LO(sc) + DROPLESS_FC_HEADROOM) 377 378 /* This is needed for determening of last_max */ 379 #define SUB_S16(a, b) (int16_t)((int16_t)(a) - (int16_t)(b)) 380 381 #define __SGE_MASK_SET_BIT(el, bit) \ 382 do { \ 383 (el) = ((el) | ((uint64_t)0x1 << (bit))); \ 384 } while (0) 385 386 #define __SGE_MASK_CLEAR_BIT(el, bit) \ 387 do { \ 388 (el) = ((el) & (~((uint64_t)0x1 << (bit)))); \ 389 } while (0) 390 391 #define SGE_MASK_SET_BIT(fp, idx) \ 392 __SGE_MASK_SET_BIT((fp)->sge_mask[(idx) >> RX_SGE_MASK_ELEM_SHIFT], \ 393 ((idx) & RX_SGE_MASK_ELEM_MASK)) 394 395 #define SGE_MASK_CLEAR_BIT(fp, idx) \ 396 __SGE_MASK_CLEAR_BIT((fp)->sge_mask[(idx) >> RX_SGE_MASK_ELEM_SHIFT], \ 397 ((idx) & RX_SGE_MASK_ELEM_MASK)) 398 399 /* Load / Unload modes */ 400 #define LOAD_NORMAL 0 401 #define LOAD_OPEN 1 402 #define LOAD_DIAG 2 403 #define LOAD_LOOPBACK_EXT 3 404 #define UNLOAD_NORMAL 0 405 #define UNLOAD_CLOSE 1 406 #define UNLOAD_RECOVERY 2 407 408 /* Some constants... */ 409 //#define MAX_PATH_NUM 2 410 //#define E2_MAX_NUM_OF_VFS 64 411 //#define E1H_FUNC_MAX 8 412 //#define E2_FUNC_MAX 4 /* per path */ 413 #define MAX_VNIC_NUM 4 414 #define MAX_FUNC_NUM 8 /* common to all chips */ 415 //#define MAX_NDSB HC_SB_MAX_SB_E2 /* max non-default status block */ 416 #define MAX_RSS_CHAINS 16 /* a constant for HW limit */ 417 #define MAX_MSI_VECTOR 8 /* a constant for HW limit */ 418 419 #define ILT_NUM_PAGE_ENTRIES 3072 420 /* 421 * 57710/11 we use whole table since we have 8 functions. 422 * 57712 we have only 4 functions, but use same size per func, so only half 423 * of the table is used. 424 */ 425 #define ILT_PER_FUNC (ILT_NUM_PAGE_ENTRIES / 8) 426 #define FUNC_ILT_BASE(func) (func * ILT_PER_FUNC) 427 /* 428 * the phys address is shifted right 12 bits and has an added 429 * 1=valid bit added to the 53rd bit 430 * then since this is a wide register(TM) 431 * we split it into two 32 bit writes 432 */ 433 #define ONCHIP_ADDR1(x) ((uint32_t)(((uint64_t)x >> 12) & 0xFFFFFFFF)) 434 #define ONCHIP_ADDR2(x) ((uint32_t)((1 << 20) | ((uint64_t)x >> 44))) 435 436 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */ 437 #define ETH_HLEN 14 438 #define ETH_OVERHEAD (ETH_HLEN + 8 + 8) 439 #define ETH_MIN_PACKET_SIZE 60 440 #define ETH_MAX_PACKET_SIZE ETHERMTU /* 1500 */ 441 #define ETH_MAX_JUMBO_PACKET_SIZE 9600 442 /* TCP with Timestamp Option (32) + IPv6 (40) */ 443 #define ETH_MAX_TPA_HEADER_SIZE 72 444 445 /* max supported alignment is 256 (8 shift) */ 446 //#define BXE_RX_ALIGN_SHIFT ((CACHE_LINE_SHIFT < 8) ? CACHE_LINE_SHIFT : 8) 447 #define BXE_RX_ALIGN_SHIFT 8 448 /* FW uses 2 cache lines alignment for start packet and size */ 449 #define BXE_FW_RX_ALIGN_START (1 << BXE_RX_ALIGN_SHIFT) 450 #define BXE_FW_RX_ALIGN_END (1 << BXE_RX_ALIGN_SHIFT) 451 452 #define BXE_PXP_DRAM_ALIGN (BXE_RX_ALIGN_SHIFT - 5) /* XXX ??? */ 453 #define BXE_SET_ERROR_BIT(sc, error) \ 454 { \ 455 (sc)->error_status |= (error); \ 456 } 457 458 struct bxe_bar { 459 struct resource *resource; 460 int rid; 461 bus_space_tag_t tag; 462 bus_space_handle_t handle; 463 vm_offset_t kva; 464 }; 465 466 struct bxe_intr { 467 struct resource *resource; 468 int rid; 469 void *tag; 470 }; 471 472 /* Used to manage DMA allocations. */ 473 struct bxe_dma { 474 struct bxe_softc *sc; 475 bus_addr_t paddr; 476 void *vaddr; 477 bus_dma_tag_t tag; 478 bus_dmamap_t map; 479 bus_dma_segment_t seg; 480 bus_size_t size; 481 int nseg; 482 char msg[32]; 483 }; 484 485 /* attn group wiring */ 486 #define MAX_DYNAMIC_ATTN_GRPS 8 487 488 struct attn_route { 489 uint32_t sig[5]; 490 }; 491 492 struct iro { 493 uint32_t base; 494 uint16_t m1; 495 uint16_t m2; 496 uint16_t m3; 497 uint16_t size; 498 }; 499 500 union bxe_host_hc_status_block { 501 /* pointer to fp status block e2 */ 502 struct host_hc_status_block_e2 *e2_sb; 503 /* pointer to fp status block e1x */ 504 struct host_hc_status_block_e1x *e1x_sb; 505 }; 506 507 union bxe_db_prod { 508 struct doorbell_set_prod data; 509 uint32_t raw; 510 }; 511 512 struct bxe_sw_tx_bd { 513 struct mbuf *m; 514 bus_dmamap_t m_map; 515 uint16_t first_bd; 516 uint8_t flags; 517 /* set on the first BD descriptor when there is a split BD */ 518 #define BXE_TSO_SPLIT_BD (1 << 0) 519 }; 520 521 struct bxe_sw_rx_bd { 522 struct mbuf *m; 523 bus_dmamap_t m_map; 524 }; 525 526 struct bxe_sw_tpa_info { 527 struct bxe_sw_rx_bd bd; 528 bus_dma_segment_t seg; 529 uint8_t state; 530 #define BXE_TPA_STATE_START 1 531 #define BXE_TPA_STATE_STOP 2 532 uint8_t placement_offset; 533 uint16_t parsing_flags; 534 uint16_t vlan_tag; 535 uint16_t len_on_bd; 536 }; 537 538 /* 539 * This is the HSI fastpath data structure. There can be up to MAX_RSS_CHAIN 540 * instances of the fastpath structure when using multiple queues. 541 */ 542 struct bxe_fastpath { 543 /* pointer back to parent structure */ 544 struct bxe_softc *sc; 545 546 struct mtx tx_mtx; 547 char tx_mtx_name[32]; 548 struct mtx rx_mtx; 549 char rx_mtx_name[32]; 550 551 #define BXE_FP_TX_LOCK(fp) mtx_lock(&fp->tx_mtx) 552 #define BXE_FP_TX_UNLOCK(fp) mtx_unlock(&fp->tx_mtx) 553 #define BXE_FP_TX_LOCK_ASSERT(fp) mtx_assert(&fp->tx_mtx, MA_OWNED) 554 #define BXE_FP_TX_TRYLOCK(fp) mtx_trylock(&fp->tx_mtx) 555 556 #define BXE_FP_RX_LOCK(fp) mtx_lock(&fp->rx_mtx) 557 #define BXE_FP_RX_UNLOCK(fp) mtx_unlock(&fp->rx_mtx) 558 #define BXE_FP_RX_LOCK_ASSERT(fp) mtx_assert(&fp->rx_mtx, MA_OWNED) 559 560 /* status block */ 561 struct bxe_dma sb_dma; 562 union bxe_host_hc_status_block status_block; 563 564 /* transmit chain (tx bds) */ 565 struct bxe_dma tx_dma; 566 union eth_tx_bd_types *tx_chain; 567 568 /* receive chain (rx bds) */ 569 struct bxe_dma rx_dma; 570 struct eth_rx_bd *rx_chain; 571 572 /* receive completion queue chain (rcq bds) */ 573 struct bxe_dma rcq_dma; 574 union eth_rx_cqe *rcq_chain; 575 576 /* receive scatter/gather entry chain (for TPA) */ 577 struct bxe_dma rx_sge_dma; 578 struct eth_rx_sge *rx_sge_chain; 579 580 /* tx mbufs */ 581 bus_dma_tag_t tx_mbuf_tag; 582 struct bxe_sw_tx_bd tx_mbuf_chain[TX_BD_TOTAL]; 583 584 /* rx mbufs */ 585 bus_dma_tag_t rx_mbuf_tag; 586 struct bxe_sw_rx_bd rx_mbuf_chain[RX_BD_TOTAL]; 587 bus_dmamap_t rx_mbuf_spare_map; 588 589 /* rx sge mbufs */ 590 bus_dma_tag_t rx_sge_mbuf_tag; 591 struct bxe_sw_rx_bd rx_sge_mbuf_chain[RX_SGE_TOTAL]; 592 bus_dmamap_t rx_sge_mbuf_spare_map; 593 594 /* rx tpa mbufs (use the larger size for TPA queue length) */ 595 int tpa_enable; /* disabled per fastpath upon error */ 596 struct bxe_sw_tpa_info rx_tpa_info[ETH_MAX_AGGREGATION_QUEUES_E1H_E2]; 597 bus_dmamap_t rx_tpa_info_mbuf_spare_map; 598 uint64_t rx_tpa_queue_used; 599 600 uint16_t *sb_index_values; 601 uint16_t *sb_running_index; 602 uint32_t ustorm_rx_prods_offset; 603 604 uint8_t igu_sb_id; /* status block number in HW */ 605 uint8_t fw_sb_id; /* status block number in FW */ 606 607 uint32_t rx_buf_size; 608 int mbuf_alloc_size; 609 610 int state; 611 #define BXE_FP_STATE_CLOSED 0x01 612 #define BXE_FP_STATE_IRQ 0x02 613 #define BXE_FP_STATE_OPENING 0x04 614 #define BXE_FP_STATE_OPEN 0x08 615 #define BXE_FP_STATE_HALTING 0x10 616 #define BXE_FP_STATE_HALTED 0x20 617 618 /* reference back to this fastpath queue number */ 619 uint8_t index; /* this is also the 'cid' */ 620 #define FP_IDX(fp) (fp->index) 621 622 /* interrupt taskqueue (fast) */ 623 struct task tq_task; 624 struct taskqueue *tq; 625 char tq_name[32]; 626 627 struct task tx_task; 628 struct timeout_task tx_timeout_task; 629 630 /* ethernet client ID (each fastpath set of RX/TX/CQE is a client) */ 631 uint8_t cl_id; 632 #define FP_CL_ID(fp) (fp->cl_id) 633 uint8_t cl_qzone_id; 634 635 uint16_t fp_hc_idx; 636 637 /* driver copy of the receive buffer descriptor prod/cons indices */ 638 uint16_t rx_bd_prod; 639 uint16_t rx_bd_cons; 640 641 /* driver copy of the receive completion queue prod/cons indices */ 642 uint16_t rx_cq_prod; 643 uint16_t rx_cq_cons; 644 645 union bxe_db_prod tx_db; 646 647 /* Transmit packet producer index (used in eth_tx_bd). */ 648 uint16_t tx_pkt_prod; 649 uint16_t tx_pkt_cons; 650 651 /* Transmit buffer descriptor producer index. */ 652 uint16_t tx_bd_prod; 653 uint16_t tx_bd_cons; 654 655 uint64_t sge_mask[RX_SGE_MASK_LEN]; 656 uint16_t rx_sge_prod; 657 658 struct tstorm_per_queue_stats old_tclient; 659 struct ustorm_per_queue_stats old_uclient; 660 struct xstorm_per_queue_stats old_xclient; 661 struct bxe_eth_q_stats eth_q_stats; 662 struct bxe_eth_q_stats_old eth_q_stats_old; 663 664 /* Pointer to the receive consumer in the status block */ 665 uint16_t *rx_cq_cons_sb; 666 667 /* Pointer to the transmit consumer in the status block */ 668 uint16_t *tx_cons_sb; 669 670 /* transmit timeout until chip reset */ 671 int watchdog_timer; 672 673 /* Free/used buffer descriptor counters. */ 674 //uint16_t used_tx_bd; 675 676 /* Last maximal completed SGE */ 677 uint16_t last_max_sge; 678 679 //uint16_t rx_sge_free_idx; 680 681 //uint8_t segs; 682 683 #define BXE_BR_SIZE 4096 684 struct buf_ring *tx_br; 685 }; /* struct bxe_fastpath */ 686 687 /* sriov XXX */ 688 #define BXE_MAX_NUM_OF_VFS 64 689 #define BXE_VF_CID_WND 0 690 #define BXE_CIDS_PER_VF (1 << BXE_VF_CID_WND) 691 #define BXE_CLIENTS_PER_VF 1 692 #define BXE_FIRST_VF_CID 256 693 #define BXE_VF_CIDS (BXE_MAX_NUM_OF_VFS * BXE_CIDS_PER_VF) 694 #define BXE_VF_ID_INVALID 0xFF 695 #define IS_SRIOV(sc) 0 696 697 #define GET_NUM_VFS_PER_PATH(sc) 0 698 #define GET_NUM_VFS_PER_PF(sc) 0 699 700 /* maximum number of fast-path interrupt contexts */ 701 #define FP_SB_MAX_E1x 16 702 #define FP_SB_MAX_E2 HC_SB_MAX_SB_E2 703 704 union cdu_context { 705 struct eth_context eth; 706 char pad[1024]; 707 }; 708 709 /* CDU host DB constants */ 710 #define CDU_ILT_PAGE_SZ_HW 2 711 #define CDU_ILT_PAGE_SZ (8192 << CDU_ILT_PAGE_SZ_HW) /* 32K */ 712 #define ILT_PAGE_CIDS (CDU_ILT_PAGE_SZ / sizeof(union cdu_context)) 713 714 #define CNIC_ISCSI_CID_MAX 256 715 #define CNIC_FCOE_CID_MAX 2048 716 #define CNIC_CID_MAX (CNIC_ISCSI_CID_MAX + CNIC_FCOE_CID_MAX) 717 #define CNIC_ILT_LINES DIV_ROUND_UP(CNIC_CID_MAX, ILT_PAGE_CIDS) 718 719 #define QM_ILT_PAGE_SZ_HW 0 720 #define QM_ILT_PAGE_SZ (4096 << QM_ILT_PAGE_SZ_HW) /* 4K */ 721 #define QM_CID_ROUND 1024 722 723 /* TM (timers) host DB constants */ 724 #define TM_ILT_PAGE_SZ_HW 0 725 #define TM_ILT_PAGE_SZ (4096 << TM_ILT_PAGE_SZ_HW) /* 4K */ 726 /*#define TM_CONN_NUM (CNIC_STARTING_CID+CNIC_ISCSI_CXT_MAX) */ 727 #define TM_CONN_NUM 1024 728 #define TM_ILT_SZ (8 * TM_CONN_NUM) 729 #define TM_ILT_LINES DIV_ROUND_UP(TM_ILT_SZ, TM_ILT_PAGE_SZ) 730 731 /* SRC (Searcher) host DB constants */ 732 #define SRC_ILT_PAGE_SZ_HW 0 733 #define SRC_ILT_PAGE_SZ (4096 << SRC_ILT_PAGE_SZ_HW) /* 4K */ 734 #define SRC_HASH_BITS 10 735 #define SRC_CONN_NUM (1 << SRC_HASH_BITS) /* 1024 */ 736 #define SRC_ILT_SZ (sizeof(struct src_ent) * SRC_CONN_NUM) 737 #define SRC_T2_SZ SRC_ILT_SZ 738 #define SRC_ILT_LINES DIV_ROUND_UP(SRC_ILT_SZ, SRC_ILT_PAGE_SZ) 739 740 struct hw_context { 741 struct bxe_dma vcxt_dma; 742 union cdu_context *vcxt; 743 //bus_addr_t cxt_mapping; 744 size_t size; 745 }; 746 747 #define SM_RX_ID 0 748 #define SM_TX_ID 1 749 750 /* defines for multiple tx priority indices */ 751 #define FIRST_TX_ONLY_COS_INDEX 1 752 #define FIRST_TX_COS_INDEX 0 753 754 #define CID_TO_FP(cid, sc) ((cid) % BXE_NUM_NON_CNIC_QUEUES(sc)) 755 756 #define HC_INDEX_ETH_RX_CQ_CONS 1 757 #define HC_INDEX_OOO_TX_CQ_CONS 4 758 #define HC_INDEX_ETH_TX_CQ_CONS_COS0 5 759 #define HC_INDEX_ETH_TX_CQ_CONS_COS1 6 760 #define HC_INDEX_ETH_TX_CQ_CONS_COS2 7 761 #define HC_INDEX_ETH_FIRST_TX_CQ_CONS HC_INDEX_ETH_TX_CQ_CONS_COS0 762 763 /* congestion management fairness mode */ 764 #define CMNG_FNS_NONE 0 765 #define CMNG_FNS_MINMAX 1 766 767 /* CMNG constants, as derived from system spec calculations */ 768 /* default MIN rate in case VNIC min rate is configured to zero - 100Mbps */ 769 #define DEF_MIN_RATE 100 770 /* resolution of the rate shaping timer - 400 usec */ 771 #define RS_PERIODIC_TIMEOUT_USEC 400 772 /* number of bytes in single QM arbitration cycle - 773 * coefficient for calculating the fairness timer */ 774 #define QM_ARB_BYTES 160000 775 /* resolution of Min algorithm 1:100 */ 776 #define MIN_RES 100 777 /* how many bytes above threshold for the minimal credit of Min algorithm*/ 778 #define MIN_ABOVE_THRESH 32768 779 /* fairness algorithm integration time coefficient - 780 * for calculating the actual Tfair */ 781 #define T_FAIR_COEF ((MIN_ABOVE_THRESH + QM_ARB_BYTES) * 8 * MIN_RES) 782 /* memory of fairness algorithm - 2 cycles */ 783 #define FAIR_MEM 2 784 785 #define HC_SEG_ACCESS_DEF 0 /* Driver decision 0-3 */ 786 #define HC_SEG_ACCESS_ATTN 4 787 #define HC_SEG_ACCESS_NORM 0 /* Driver decision 0-1 */ 788 789 /* 790 * The total number of L2 queues, MSIX vectors and HW contexts (CIDs) is 791 * control by the number of fast-path status blocks supported by the 792 * device (HW/FW). Each fast-path status block (FP-SB) aka non-default 793 * status block represents an independent interrupts context that can 794 * serve a regular L2 networking queue. However special L2 queues such 795 * as the FCoE queue do not require a FP-SB and other components like 796 * the CNIC may consume FP-SB reducing the number of possible L2 queues 797 * 798 * If the maximum number of FP-SB available is X then: 799 * a. If CNIC is supported it consumes 1 FP-SB thus the max number of 800 * regular L2 queues is Y=X-1 801 * b. in MF mode the actual number of L2 queues is Y= (X-1/MF_factor) 802 * c. If the FCoE L2 queue is supported the actual number of L2 queues 803 * is Y+1 804 * d. The number of irqs (MSIX vectors) is either Y+1 (one extra for 805 * slow-path interrupts) or Y+2 if CNIC is supported (one additional 806 * FP interrupt context for the CNIC). 807 * e. The number of HW context (CID count) is always X or X+1 if FCoE 808 * L2 queue is supported. the cid for the FCoE L2 queue is always X. 809 * 810 * So this is quite simple for now as no ULPs are supported yet. :-) 811 */ 812 #define BXE_NUM_QUEUES(sc) ((sc)->num_queues) 813 #define BXE_NUM_ETH_QUEUES(sc) BXE_NUM_QUEUES(sc) 814 #define BXE_NUM_NON_CNIC_QUEUES(sc) BXE_NUM_QUEUES(sc) 815 #define BXE_NUM_RX_QUEUES(sc) BXE_NUM_QUEUES(sc) 816 817 #define FOR_EACH_QUEUE(sc, var) \ 818 for ((var) = 0; (var) < BXE_NUM_QUEUES(sc); (var)++) 819 820 #define FOR_EACH_NONDEFAULT_QUEUE(sc, var) \ 821 for ((var) = 1; (var) < BXE_NUM_QUEUES(sc); (var)++) 822 823 #define FOR_EACH_ETH_QUEUE(sc, var) \ 824 for ((var) = 0; (var) < BXE_NUM_ETH_QUEUES(sc); (var)++) 825 826 #define FOR_EACH_NONDEFAULT_ETH_QUEUE(sc, var) \ 827 for ((var) = 1; (var) < BXE_NUM_ETH_QUEUES(sc); (var)++) 828 829 #define FOR_EACH_COS_IN_TX_QUEUE(sc, var) \ 830 for ((var) = 0; (var) < (sc)->max_cos; (var)++) 831 832 #define FOR_EACH_CNIC_QUEUE(sc, var) \ 833 for ((var) = BXE_NUM_ETH_QUEUES(sc); \ 834 (var) < BXE_NUM_QUEUES(sc); \ 835 (var)++) 836 837 enum { 838 OOO_IDX_OFFSET, 839 FCOE_IDX_OFFSET, 840 FWD_IDX_OFFSET, 841 }; 842 843 #define FCOE_IDX(sc) (BXE_NUM_NON_CNIC_QUEUES(sc) + FCOE_IDX_OFFSET) 844 #define bxe_fcoe_fp(sc) (&sc->fp[FCOE_IDX(sc)]) 845 #define bxe_fcoe(sc, var) (bxe_fcoe_fp(sc)->var) 846 #define bxe_fcoe_inner_sp_obj(sc) (&sc->sp_objs[FCOE_IDX(sc)]) 847 #define bxe_fcoe_sp_obj(sc, var) (bxe_fcoe_inner_sp_obj(sc)->var) 848 #define bxe_fcoe_tx(sc, var) (bxe_fcoe_fp(sc)->txdata_ptr[FIRST_TX_COS_INDEX]->var) 849 850 #define OOO_IDX(sc) (BXE_NUM_NON_CNIC_QUEUES(sc) + OOO_IDX_OFFSET) 851 #define bxe_ooo_fp(sc) (&sc->fp[OOO_IDX(sc)]) 852 #define bxe_ooo(sc, var) (bxe_ooo_fp(sc)->var) 853 #define bxe_ooo_inner_sp_obj(sc) (&sc->sp_objs[OOO_IDX(sc)]) 854 #define bxe_ooo_sp_obj(sc, var) (bxe_ooo_inner_sp_obj(sc)->var) 855 856 #define FWD_IDX(sc) (BXE_NUM_NON_CNIC_QUEUES(sc) + FWD_IDX_OFFSET) 857 #define bxe_fwd_fp(sc) (&sc->fp[FWD_IDX(sc)]) 858 #define bxe_fwd(sc, var) (bxe_fwd_fp(sc)->var) 859 #define bxe_fwd_inner_sp_obj(sc) (&sc->sp_objs[FWD_IDX(sc)]) 860 #define bxe_fwd_sp_obj(sc, var) (bxe_fwd_inner_sp_obj(sc)->var) 861 #define bxe_fwd_txdata(fp) (fp->txdata_ptr[FIRST_TX_COS_INDEX]) 862 863 #define IS_ETH_FP(fp) ((fp)->index < BXE_NUM_ETH_QUEUES((fp)->sc)) 864 #define IS_FCOE_FP(fp) ((fp)->index == FCOE_IDX((fp)->sc)) 865 #define IS_FCOE_IDX(idx) ((idx) == FCOE_IDX(sc)) 866 #define IS_FWD_FP(fp) ((fp)->index == FWD_IDX((fp)->sc)) 867 #define IS_FWD_IDX(idx) ((idx) == FWD_IDX(sc)) 868 #define IS_OOO_FP(fp) ((fp)->index == OOO_IDX((fp)->sc)) 869 #define IS_OOO_IDX(idx) ((idx) == OOO_IDX(sc)) 870 871 enum { 872 BXE_PORT_QUERY_IDX, 873 BXE_PF_QUERY_IDX, 874 BXE_FCOE_QUERY_IDX, 875 BXE_FIRST_QUEUE_QUERY_IDX, 876 }; 877 878 struct bxe_fw_stats_req { 879 struct stats_query_header hdr; 880 struct stats_query_entry query[FP_SB_MAX_E1x + 881 BXE_FIRST_QUEUE_QUERY_IDX]; 882 }; 883 884 struct bxe_fw_stats_data { 885 struct stats_counter storm_counters; 886 struct per_port_stats port; 887 struct per_pf_stats pf; 888 //struct fcoe_statistics_params fcoe; 889 struct per_queue_stats queue_stats[1]; 890 }; 891 892 /* IGU MSIX STATISTICS on 57712: 64 for VFs; 4 for PFs; 4 for Attentions */ 893 #define BXE_IGU_STAS_MSG_VF_CNT 64 894 #define BXE_IGU_STAS_MSG_PF_CNT 4 895 896 #define MAX_DMAE_C 8 897 898 /* 899 * For the main interface up/down code paths, a not-so-fine-grained CORE 900 * mutex lock is used. Inside this code are various calls to kernel routines 901 * that can cause a sleep to occur. Namely memory allocations and taskqueue 902 * handling. If using an MTX lock we are *not* allowed to sleep but we can 903 * with an SX lock. This define forces the CORE lock to use and SX lock. 904 * Undefine this and an MTX lock will be used instead. Note that the IOCTL 905 * path can cause problems since it's called by a non-sleepable thread. To 906 * alleviate a potential sleep, any IOCTL processing that results in the 907 * chip/interface being started/stopped/reinitialized, the actual work is 908 * offloaded to a taskqueue. 909 */ 910 #define BXE_CORE_LOCK_SX 911 912 /* 913 * This is the slowpath data structure. It is mapped into non-paged memory 914 * so that the hardware can access it's contents directly and must be page 915 * aligned. 916 */ 917 struct bxe_slowpath { 918 919 /* used by the DMAE command executer */ 920 struct dmae_cmd dmae[MAX_DMAE_C]; 921 922 /* statistics completion */ 923 uint32_t stats_comp; 924 925 /* firmware defined statistics blocks */ 926 union mac_stats mac_stats; 927 struct nig_stats nig_stats; 928 struct host_port_stats port_stats; 929 struct host_func_stats func_stats; 930 //struct host_func_stats func_stats_base; 931 932 /* DMAE completion value and data source/sink */ 933 uint32_t wb_comp; 934 uint32_t wb_data[4]; 935 936 union { 937 struct mac_configuration_cmd e1x; 938 struct eth_classify_rules_ramrod_data e2; 939 } mac_rdata; 940 941 union { 942 struct tstorm_eth_mac_filter_config e1x; 943 struct eth_filter_rules_ramrod_data e2; 944 } rx_mode_rdata; 945 946 struct eth_rss_update_ramrod_data rss_rdata; 947 948 union { 949 struct mac_configuration_cmd e1; 950 struct eth_multicast_rules_ramrod_data e2; 951 } mcast_rdata; 952 953 union { 954 struct function_start_data func_start; 955 struct flow_control_configuration pfc_config; /* for DCBX ramrod */ 956 } func_rdata; 957 958 /* Queue State related ramrods */ 959 union { 960 struct client_init_ramrod_data init_data; 961 struct client_update_ramrod_data update_data; 962 } q_rdata; 963 964 /* 965 * AFEX ramrod can not be a part of func_rdata union because these 966 * events might arrive in parallel to other events from func_rdata. 967 * If they were defined in the same union the data can get corrupted. 968 */ 969 struct afex_vif_list_ramrod_data func_afex_rdata; 970 971 union drv_info_to_mcp drv_info_to_mcp; 972 }; /* struct bxe_slowpath */ 973 974 /* 975 * Port specifc data structure. 976 */ 977 struct bxe_port { 978 /* 979 * Port Management Function (for 57711E only). 980 * When this field is set the driver instance is 981 * responsible for managing port specifc 982 * configurations such as handling link attentions. 983 */ 984 uint32_t pmf; 985 986 /* Ethernet maximum transmission unit. */ 987 uint16_t ether_mtu; 988 989 uint32_t link_config[ELINK_LINK_CONFIG_SIZE]; 990 991 uint32_t ext_phy_config; 992 993 /* Port feature config.*/ 994 uint32_t config; 995 996 /* Defines the features supported by the PHY. */ 997 uint32_t supported[ELINK_LINK_CONFIG_SIZE]; 998 999 /* Defines the features advertised by the PHY. */ 1000 uint32_t advertising[ELINK_LINK_CONFIG_SIZE]; 1001 #define ADVERTISED_10baseT_Half (1 << 1) 1002 #define ADVERTISED_10baseT_Full (1 << 2) 1003 #define ADVERTISED_100baseT_Half (1 << 3) 1004 #define ADVERTISED_100baseT_Full (1 << 4) 1005 #define ADVERTISED_1000baseT_Half (1 << 5) 1006 #define ADVERTISED_1000baseT_Full (1 << 6) 1007 #define ADVERTISED_TP (1 << 7) 1008 #define ADVERTISED_FIBRE (1 << 8) 1009 #define ADVERTISED_Autoneg (1 << 9) 1010 #define ADVERTISED_Asym_Pause (1 << 10) 1011 #define ADVERTISED_Pause (1 << 11) 1012 #define ADVERTISED_2500baseX_Full (1 << 15) 1013 #define ADVERTISED_10000baseT_Full (1 << 16) 1014 1015 uint32_t phy_addr; 1016 1017 /* Used to synchronize phy accesses. */ 1018 struct mtx phy_mtx; 1019 char phy_mtx_name[32]; 1020 1021 #define BXE_PHY_LOCK(sc) mtx_lock(&sc->port.phy_mtx) 1022 #define BXE_PHY_UNLOCK(sc) mtx_unlock(&sc->port.phy_mtx) 1023 #define BXE_PHY_LOCK_ASSERT(sc) mtx_assert(&sc->port.phy_mtx, MA_OWNED) 1024 1025 /* 1026 * MCP scratchpad address for port specific statistics. 1027 * The device is responsible for writing statistcss 1028 * back to the MCP for use with management firmware such 1029 * as UMP/NC-SI. 1030 */ 1031 uint32_t port_stx; 1032 1033 struct nig_stats old_nig_stats; 1034 }; /* struct bxe_port */ 1035 1036 struct bxe_mf_info { 1037 uint32_t mf_config[E1HVN_MAX]; 1038 1039 uint32_t vnics_per_port; /* 1, 2 or 4 */ 1040 uint32_t multi_vnics_mode; /* can be set even if vnics_per_port = 1 */ 1041 uint32_t path_has_ovlan; /* MF mode in the path (can be different than the MF mode of the function */ 1042 1043 #define IS_MULTI_VNIC(sc) ((sc)->devinfo.mf_info.multi_vnics_mode) 1044 #define VNICS_PER_PORT(sc) ((sc)->devinfo.mf_info.vnics_per_port) 1045 #define VNICS_PER_PATH(sc) \ 1046 ((sc)->devinfo.mf_info.vnics_per_port * \ 1047 ((CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 1 )) 1048 1049 uint8_t min_bw[MAX_VNIC_NUM]; 1050 uint8_t max_bw[MAX_VNIC_NUM]; 1051 1052 uint16_t ext_id; /* vnic outer vlan or VIF ID */ 1053 #define VALID_OVLAN(ovlan) ((ovlan) <= 4096) 1054 #define INVALID_VIF_ID 0xFFFF 1055 #define OVLAN(sc) ((sc)->devinfo.mf_info.ext_id) 1056 #define VIF_ID(sc) ((sc)->devinfo.mf_info.ext_id) 1057 1058 uint16_t default_vlan; 1059 #define NIV_DEFAULT_VLAN(sc) ((sc)->devinfo.mf_info.default_vlan) 1060 1061 uint8_t niv_allowed_priorities; 1062 #define NIV_ALLOWED_PRIORITIES(sc) ((sc)->devinfo.mf_info.niv_allowed_priorities) 1063 1064 uint8_t niv_default_cos; 1065 #define NIV_DEFAULT_COS(sc) ((sc)->devinfo.mf_info.niv_default_cos) 1066 1067 uint8_t niv_mba_enabled; 1068 1069 enum mf_cfg_afex_vlan_mode afex_vlan_mode; 1070 #define AFEX_VLAN_MODE(sc) ((sc)->devinfo.mf_info.afex_vlan_mode) 1071 int afex_def_vlan_tag; 1072 uint32_t pending_max; 1073 1074 uint16_t flags; 1075 #define MF_INFO_VALID_MAC 0x0001 1076 1077 uint8_t mf_mode; /* Switch-Dependent or Switch-Independent */ 1078 #define IS_MF(sc) \ 1079 (IS_MULTI_VNIC(sc) && \ 1080 ((sc)->devinfo.mf_info.mf_mode != 0)) 1081 #define IS_MF_SD(sc) \ 1082 (IS_MULTI_VNIC(sc) && \ 1083 ((sc)->devinfo.mf_info.mf_mode == MULTI_FUNCTION_SD)) 1084 #define IS_MF_SI(sc) \ 1085 (IS_MULTI_VNIC(sc) && \ 1086 ((sc)->devinfo.mf_info.mf_mode == MULTI_FUNCTION_SI)) 1087 #define IS_MF_AFEX(sc) \ 1088 (IS_MULTI_VNIC(sc) && \ 1089 ((sc)->devinfo.mf_info.mf_mode == MULTI_FUNCTION_AFEX)) 1090 #define IS_MF_SD_MODE(sc) IS_MF_SD(sc) 1091 #define IS_MF_SI_MODE(sc) IS_MF_SI(sc) 1092 #define IS_MF_AFEX_MODE(sc) IS_MF_AFEX(sc) 1093 1094 uint32_t mf_protos_supported; 1095 #define MF_PROTO_SUPPORT_ETHERNET 0x1 1096 #define MF_PROTO_SUPPORT_ISCSI 0x2 1097 #define MF_PROTO_SUPPORT_FCOE 0x4 1098 }; /* struct bxe_mf_info */ 1099 1100 /* Device information data structure. */ 1101 struct bxe_devinfo { 1102 /* PCIe info */ 1103 uint16_t vendor_id; 1104 uint16_t device_id; 1105 uint16_t subvendor_id; 1106 uint16_t subdevice_id; 1107 1108 /* 1109 * chip_id = 0b'CCCCCCCCCCCCCCCCRRRRMMMMMMMMBBBB' 1110 * C = Chip Number (bits 16-31) 1111 * R = Chip Revision (bits 12-15) 1112 * M = Chip Metal (bits 4-11) 1113 * B = Chip Bond ID (bits 0-3) 1114 */ 1115 uint32_t chip_id; 1116 #define CHIP_ID(sc) ((sc)->devinfo.chip_id & 0xffff0000) 1117 #define CHIP_NUM(sc) ((sc)->devinfo.chip_id >> 16) 1118 /* device ids */ 1119 #define CHIP_NUM_57710 0x164e 1120 #define CHIP_NUM_57711 0x164f 1121 #define CHIP_NUM_57711E 0x1650 1122 #define CHIP_NUM_57712 0x1662 1123 #define CHIP_NUM_57712_MF 0x1663 1124 #define CHIP_NUM_57712_VF 0x166f 1125 #define CHIP_NUM_57800 0x168a 1126 #define CHIP_NUM_57800_MF 0x16a5 1127 #define CHIP_NUM_57800_VF 0x16a9 1128 #define CHIP_NUM_57810 0x168e 1129 #define CHIP_NUM_57810_MF 0x16ae 1130 #define CHIP_NUM_57810_VF 0x16af 1131 #define CHIP_NUM_57811 0x163d 1132 #define CHIP_NUM_57811_MF 0x163e 1133 #define CHIP_NUM_57811_VF 0x163f 1134 #define CHIP_NUM_57840_OBS 0x168d 1135 #define CHIP_NUM_57840_OBS_MF 0x16ab 1136 #define CHIP_NUM_57840_4_10 0x16a1 1137 #define CHIP_NUM_57840_2_20 0x16a2 1138 #define CHIP_NUM_57840_MF 0x16a4 1139 #define CHIP_NUM_57840_VF 0x16ad 1140 1141 #define CHIP_REV_SHIFT 12 1142 #define CHIP_REV_MASK (0xF << CHIP_REV_SHIFT) 1143 #define CHIP_REV(sc) ((sc)->devinfo.chip_id & CHIP_REV_MASK) 1144 1145 #define CHIP_REV_Ax (0x0 << CHIP_REV_SHIFT) 1146 #define CHIP_REV_Bx (0x1 << CHIP_REV_SHIFT) 1147 #define CHIP_REV_Cx (0x2 << CHIP_REV_SHIFT) 1148 1149 #define CHIP_REV_IS_SLOW(sc) \ 1150 (CHIP_REV(sc) > 0x00005000) 1151 #define CHIP_REV_IS_FPGA(sc) \ 1152 (CHIP_REV_IS_SLOW(sc) && (CHIP_REV(sc) & 0x00001000)) 1153 #define CHIP_REV_IS_EMUL(sc) \ 1154 (CHIP_REV_IS_SLOW(sc) && !(CHIP_REV(sc) & 0x00001000)) 1155 #define CHIP_REV_IS_ASIC(sc) \ 1156 (!CHIP_REV_IS_SLOW(sc)) 1157 1158 #define CHIP_METAL(sc) ((sc->devinfo.chip_id) & 0x00000ff0) 1159 #define CHIP_BOND_ID(sc) ((sc->devinfo.chip_id) & 0x0000000f) 1160 1161 #define CHIP_IS_E1(sc) (CHIP_NUM(sc) == CHIP_NUM_57710) 1162 #define CHIP_IS_57710(sc) (CHIP_NUM(sc) == CHIP_NUM_57710) 1163 #define CHIP_IS_57711(sc) (CHIP_NUM(sc) == CHIP_NUM_57711) 1164 #define CHIP_IS_57711E(sc) (CHIP_NUM(sc) == CHIP_NUM_57711E) 1165 #define CHIP_IS_E1H(sc) ((CHIP_IS_57711(sc)) || \ 1166 (CHIP_IS_57711E(sc))) 1167 #define CHIP_IS_E1x(sc) (CHIP_IS_E1((sc)) || \ 1168 CHIP_IS_E1H((sc))) 1169 1170 #define CHIP_IS_57712(sc) (CHIP_NUM(sc) == CHIP_NUM_57712) 1171 #define CHIP_IS_57712_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57712_MF) 1172 #define CHIP_IS_57712_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57712_VF) 1173 #define CHIP_IS_E2(sc) (CHIP_IS_57712(sc) || \ 1174 CHIP_IS_57712_MF(sc)) 1175 1176 #define CHIP_IS_57800(sc) (CHIP_NUM(sc) == CHIP_NUM_57800) 1177 #define CHIP_IS_57800_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57800_MF) 1178 #define CHIP_IS_57800_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57800_VF) 1179 #define CHIP_IS_57810(sc) (CHIP_NUM(sc) == CHIP_NUM_57810) 1180 #define CHIP_IS_57810_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57810_MF) 1181 #define CHIP_IS_57810_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57810_VF) 1182 #define CHIP_IS_57811(sc) (CHIP_NUM(sc) == CHIP_NUM_57811) 1183 #define CHIP_IS_57811_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57811_MF) 1184 #define CHIP_IS_57811_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57811_VF) 1185 #define CHIP_IS_57840(sc) ((CHIP_NUM(sc) == CHIP_NUM_57840_OBS) || \ 1186 (CHIP_NUM(sc) == CHIP_NUM_57840_4_10) || \ 1187 (CHIP_NUM(sc) == CHIP_NUM_57840_2_20)) 1188 #define CHIP_IS_57840_MF(sc) ((CHIP_NUM(sc) == CHIP_NUM_57840_OBS_MF) || \ 1189 (CHIP_NUM(sc) == CHIP_NUM_57840_MF)) 1190 #define CHIP_IS_57840_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57840_VF) 1191 1192 #define CHIP_IS_E3(sc) (CHIP_IS_57800(sc) || \ 1193 CHIP_IS_57800_MF(sc) || \ 1194 CHIP_IS_57800_VF(sc) || \ 1195 CHIP_IS_57810(sc) || \ 1196 CHIP_IS_57810_MF(sc) || \ 1197 CHIP_IS_57810_VF(sc) || \ 1198 CHIP_IS_57811(sc) || \ 1199 CHIP_IS_57811_MF(sc) || \ 1200 CHIP_IS_57811_VF(sc) || \ 1201 CHIP_IS_57840(sc) || \ 1202 CHIP_IS_57840_MF(sc) || \ 1203 CHIP_IS_57840_VF(sc)) 1204 #define CHIP_IS_E3A0(sc) (CHIP_IS_E3(sc) && \ 1205 (CHIP_REV(sc) == CHIP_REV_Ax)) 1206 #define CHIP_IS_E3B0(sc) (CHIP_IS_E3(sc) && \ 1207 (CHIP_REV(sc) == CHIP_REV_Bx)) 1208 1209 #define USES_WARPCORE(sc) (CHIP_IS_E3(sc)) 1210 #define CHIP_IS_E2E3(sc) (CHIP_IS_E2(sc) || \ 1211 CHIP_IS_E3(sc)) 1212 1213 #define CHIP_IS_MF_CAP(sc) (CHIP_IS_57711E(sc) || \ 1214 CHIP_IS_57712_MF(sc) || \ 1215 CHIP_IS_E3(sc)) 1216 1217 #define IS_VF(sc) (CHIP_IS_57712_VF(sc) || \ 1218 CHIP_IS_57800_VF(sc) || \ 1219 CHIP_IS_57810_VF(sc) || \ 1220 CHIP_IS_57840_VF(sc)) 1221 #define IS_PF(sc) (!IS_VF(sc)) 1222 1223 /* 1224 * This define is used in two main places: 1225 * 1. In the early stages of nic_load, to know if to configure Parser/Searcher 1226 * to nic-only mode or to offload mode. Offload mode is configured if either 1227 * the chip is E1x (where NIC_MODE register is not applicable), or if cnic 1228 * already registered for this port (which means that the user wants storage 1229 * services). 1230 * 2. During cnic-related load, to know if offload mode is already configured 1231 * in the HW or needs to be configrued. Since the transition from nic-mode to 1232 * offload-mode in HW causes traffic coruption, nic-mode is configured only 1233 * in ports on which storage services where never requested. 1234 */ 1235 #define CONFIGURE_NIC_MODE(sc) (!CHIP_IS_E1x(sc) && !CNIC_ENABLED(sc)) 1236 1237 uint8_t chip_port_mode; 1238 #define CHIP_4_PORT_MODE 0x0 1239 #define CHIP_2_PORT_MODE 0x1 1240 #define CHIP_PORT_MODE_NONE 0x2 1241 #define CHIP_PORT_MODE(sc) ((sc)->devinfo.chip_port_mode) 1242 #define CHIP_IS_MODE_4_PORT(sc) (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) 1243 1244 uint8_t int_block; 1245 #define INT_BLOCK_HC 0 1246 #define INT_BLOCK_IGU 1 1247 #define INT_BLOCK_MODE_NORMAL 0 1248 #define INT_BLOCK_MODE_BW_COMP 2 1249 #define CHIP_INT_MODE_IS_NBC(sc) \ 1250 (!CHIP_IS_E1x(sc) && \ 1251 !((sc)->devinfo.int_block & INT_BLOCK_MODE_BW_COMP)) 1252 #define CHIP_INT_MODE_IS_BC(sc) (!CHIP_INT_MODE_IS_NBC(sc)) 1253 1254 uint32_t shmem_base; 1255 uint32_t shmem2_base; 1256 uint32_t bc_ver; 1257 char bc_ver_str[32]; 1258 uint32_t mf_cfg_base; /* bootcode shmem address in BAR memory */ 1259 struct bxe_mf_info mf_info; 1260 1261 int flash_size; 1262 #define NVRAM_1MB_SIZE 0x20000 1263 #define NVRAM_TIMEOUT_COUNT 30000 1264 #define NVRAM_PAGE_SIZE 256 1265 1266 /* PCIe capability information */ 1267 uint32_t pcie_cap_flags; 1268 #define BXE_PM_CAPABLE_FLAG 0x00000001 1269 #define BXE_PCIE_CAPABLE_FLAG 0x00000002 1270 #define BXE_MSI_CAPABLE_FLAG 0x00000004 1271 #define BXE_MSIX_CAPABLE_FLAG 0x00000008 1272 uint16_t pcie_pm_cap_reg; 1273 uint16_t pcie_pcie_cap_reg; 1274 //uint16_t pcie_devctl; 1275 uint16_t pcie_link_width; 1276 uint16_t pcie_link_speed; 1277 uint16_t pcie_msi_cap_reg; 1278 uint16_t pcie_msix_cap_reg; 1279 1280 /* device configuration read from bootcode shared memory */ 1281 uint32_t hw_config; 1282 uint32_t hw_config2; 1283 }; /* struct bxe_devinfo */ 1284 1285 struct bxe_sp_objs { 1286 struct ecore_vlan_mac_obj mac_obj; /* MACs object */ 1287 struct ecore_queue_sp_obj q_obj; /* Queue State object */ 1288 }; /* struct bxe_sp_objs */ 1289 1290 /* 1291 * Data that will be used to create a link report message. We will keep the 1292 * data used for the last link report in order to prevent reporting the same 1293 * link parameters twice. 1294 */ 1295 struct bxe_link_report_data { 1296 uint16_t line_speed; /* Effective line speed */ 1297 unsigned long link_report_flags; /* BXE_LINK_REPORT_XXX flags */ 1298 }; 1299 enum { 1300 BXE_LINK_REPORT_FULL_DUPLEX, 1301 BXE_LINK_REPORT_LINK_DOWN, 1302 BXE_LINK_REPORT_RX_FC_ON, 1303 BXE_LINK_REPORT_TX_FC_ON 1304 }; 1305 1306 /* Top level device private data structure. */ 1307 struct bxe_softc { 1308 /* 1309 * First entry must be a pointer to the BSD ifnet struct which 1310 * has a first element of 'void *if_softc' (which is us). XXX 1311 */ 1312 if_t ifp; 1313 struct ifmedia ifmedia; /* network interface media structure */ 1314 int media; 1315 1316 volatile int state; /* device state */ 1317 #define BXE_STATE_CLOSED 0x0000 1318 #define BXE_STATE_OPENING_WAITING_LOAD 0x1000 1319 #define BXE_STATE_OPENING_WAITING_PORT 0x2000 1320 #define BXE_STATE_OPEN 0x3000 1321 #define BXE_STATE_CLOSING_WAITING_HALT 0x4000 1322 #define BXE_STATE_CLOSING_WAITING_DELETE 0x5000 1323 #define BXE_STATE_CLOSING_WAITING_UNLOAD 0x6000 1324 #define BXE_STATE_DISABLED 0xD000 1325 #define BXE_STATE_DIAG 0xE000 1326 #define BXE_STATE_ERROR 0xF000 1327 1328 int flags; 1329 #define BXE_ONE_PORT_FLAG 0x00000001 1330 #define BXE_NO_ISCSI 0x00000002 1331 #define BXE_NO_FCOE 0x00000004 1332 #define BXE_ONE_PORT(sc) (sc->flags & BXE_ONE_PORT_FLAG) 1333 //#define BXE_NO_WOL_FLAG 0x00000008 1334 //#define BXE_USING_DAC_FLAG 0x00000010 1335 //#define BXE_USING_MSIX_FLAG 0x00000020 1336 //#define BXE_USING_MSI_FLAG 0x00000040 1337 //#define BXE_DISABLE_MSI_FLAG 0x00000080 1338 #define BXE_NO_MCP_FLAG 0x00000200 1339 #define BXE_NOMCP(sc) (sc->flags & BXE_NO_MCP_FLAG) 1340 //#define BXE_SAFC_TX_FLAG 0x00000400 1341 #define BXE_MF_FUNC_DIS 0x00000800 1342 #define BXE_TX_SWITCHING 0x00001000 1343 #define BXE_NO_PULSE 0x00002000 1344 1345 unsigned long debug; /* per-instance debug logging config */ 1346 1347 #define MAX_BARS 5 1348 struct bxe_bar bar[MAX_BARS]; /* map BARs 0, 2, 4 */ 1349 1350 uint16_t doorbell_size; 1351 1352 /* periodic timer callout */ 1353 #define PERIODIC_STOP 0 1354 #define PERIODIC_GO 1 1355 volatile unsigned long periodic_flags; 1356 struct callout periodic_callout; 1357 1358 /* chip start/stop/reset taskqueue */ 1359 #define CHIP_TQ_NONE 0 1360 #define CHIP_TQ_START 1 1361 #define CHIP_TQ_STOP 2 1362 #define CHIP_TQ_REINIT 3 1363 volatile unsigned long chip_tq_flags; 1364 struct task chip_tq_task; 1365 struct taskqueue *chip_tq; 1366 char chip_tq_name[32]; 1367 1368 struct timeout_task sp_err_timeout_task; 1369 1370 /* slowpath interrupt taskqueue */ 1371 struct task sp_tq_task; 1372 struct taskqueue *sp_tq; 1373 char sp_tq_name[32]; 1374 1375 struct bxe_fastpath fp[MAX_RSS_CHAINS]; 1376 struct bxe_sp_objs sp_objs[MAX_RSS_CHAINS]; 1377 1378 device_t dev; /* parent device handle */ 1379 uint8_t unit; /* driver instance number */ 1380 1381 int pcie_bus; /* PCIe bus number */ 1382 int pcie_device; /* PCIe device/slot number */ 1383 int pcie_func; /* PCIe function number */ 1384 1385 uint8_t pfunc_rel; /* function relative */ 1386 uint8_t pfunc_abs; /* function absolute */ 1387 uint8_t path_id; /* function absolute */ 1388 #define SC_PATH(sc) (sc->path_id) 1389 #define SC_PORT(sc) (sc->pfunc_rel & 1) 1390 #define SC_FUNC(sc) (sc->pfunc_rel) 1391 #define SC_ABS_FUNC(sc) (sc->pfunc_abs) 1392 #define SC_VN(sc) (sc->pfunc_rel >> 1) 1393 #define SC_L_ID(sc) (SC_VN(sc) << 2) 1394 #define PORT_ID(sc) SC_PORT(sc) 1395 #define PATH_ID(sc) SC_PATH(sc) 1396 #define VNIC_ID(sc) SC_VN(sc) 1397 #define FUNC_ID(sc) SC_FUNC(sc) 1398 #define ABS_FUNC_ID(sc) SC_ABS_FUNC(sc) 1399 #define SC_FW_MB_IDX_VN(sc, vn) \ 1400 (SC_PORT(sc) + (vn) * \ 1401 ((CHIP_IS_E1x(sc) || (CHIP_IS_MODE_4_PORT(sc))) ? 2 : 1)) 1402 #define SC_FW_MB_IDX(sc) SC_FW_MB_IDX_VN(sc, SC_VN(sc)) 1403 1404 int if_capen; /* enabled interface capabilities */ 1405 1406 struct bxe_devinfo devinfo; 1407 char fw_ver_str[32]; 1408 char mf_mode_str[32]; 1409 char pci_link_str[32]; 1410 1411 const struct iro *iro_array; 1412 1413 #ifdef BXE_CORE_LOCK_SX 1414 struct sx core_sx; 1415 char core_sx_name[32]; 1416 #else 1417 struct mtx core_mtx; 1418 char core_mtx_name[32]; 1419 #endif 1420 struct mtx sp_mtx; 1421 char sp_mtx_name[32]; 1422 struct mtx dmae_mtx; 1423 char dmae_mtx_name[32]; 1424 struct mtx fwmb_mtx; 1425 char fwmb_mtx_name[32]; 1426 struct mtx print_mtx; 1427 char print_mtx_name[32]; 1428 struct mtx stats_mtx; 1429 char stats_mtx_name[32]; 1430 struct mtx mcast_mtx; 1431 char mcast_mtx_name[32]; 1432 1433 #ifdef BXE_CORE_LOCK_SX 1434 #define BXE_CORE_TRYLOCK(sc) sx_try_xlock(&sc->core_sx) 1435 #define BXE_CORE_LOCK(sc) sx_xlock(&sc->core_sx) 1436 #define BXE_CORE_UNLOCK(sc) sx_xunlock(&sc->core_sx) 1437 #define BXE_CORE_LOCK_ASSERT(sc) sx_assert(&sc->core_sx, SA_XLOCKED) 1438 #else 1439 #define BXE_CORE_TRYLOCK(sc) mtx_trylock(&sc->core_mtx) 1440 #define BXE_CORE_LOCK(sc) mtx_lock(&sc->core_mtx) 1441 #define BXE_CORE_UNLOCK(sc) mtx_unlock(&sc->core_mtx) 1442 #define BXE_CORE_LOCK_ASSERT(sc) mtx_assert(&sc->core_mtx, MA_OWNED) 1443 #endif 1444 1445 #define BXE_SP_LOCK(sc) mtx_lock(&sc->sp_mtx) 1446 #define BXE_SP_UNLOCK(sc) mtx_unlock(&sc->sp_mtx) 1447 #define BXE_SP_LOCK_ASSERT(sc) mtx_assert(&sc->sp_mtx, MA_OWNED) 1448 1449 #define BXE_DMAE_LOCK(sc) mtx_lock(&sc->dmae_mtx) 1450 #define BXE_DMAE_UNLOCK(sc) mtx_unlock(&sc->dmae_mtx) 1451 #define BXE_DMAE_LOCK_ASSERT(sc) mtx_assert(&sc->dmae_mtx, MA_OWNED) 1452 1453 #define BXE_FWMB_LOCK(sc) mtx_lock(&sc->fwmb_mtx) 1454 #define BXE_FWMB_UNLOCK(sc) mtx_unlock(&sc->fwmb_mtx) 1455 #define BXE_FWMB_LOCK_ASSERT(sc) mtx_assert(&sc->fwmb_mtx, MA_OWNED) 1456 1457 #define BXE_PRINT_LOCK(sc) mtx_lock(&sc->print_mtx) 1458 #define BXE_PRINT_UNLOCK(sc) mtx_unlock(&sc->print_mtx) 1459 #define BXE_PRINT_LOCK_ASSERT(sc) mtx_assert(&sc->print_mtx, MA_OWNED) 1460 1461 #define BXE_STATS_LOCK(sc) mtx_lock(&sc->stats_mtx) 1462 #define BXE_STATS_UNLOCK(sc) mtx_unlock(&sc->stats_mtx) 1463 #define BXE_STATS_LOCK_ASSERT(sc) mtx_assert(&sc->stats_mtx, MA_OWNED) 1464 1465 #define BXE_MCAST_LOCK(sc) mtx_lock(&sc->mcast_mtx); 1466 #define BXE_MCAST_UNLOCK(sc) mtx_unlock(&sc->mcast_mtx); 1467 #define BXE_MCAST_LOCK_ASSERT(sc) mtx_assert(&sc->mcast_mtx, MA_OWNED) 1468 1469 int dmae_ready; 1470 #define DMAE_READY(sc) (sc->dmae_ready) 1471 1472 struct ecore_credit_pool_obj vlans_pool; 1473 struct ecore_credit_pool_obj macs_pool; 1474 struct ecore_rx_mode_obj rx_mode_obj; 1475 struct ecore_mcast_obj mcast_obj; 1476 struct ecore_rss_config_obj rss_conf_obj; 1477 struct ecore_func_sp_obj func_obj; 1478 1479 uint16_t fw_seq; 1480 uint16_t fw_drv_pulse_wr_seq; 1481 uint32_t func_stx; 1482 1483 struct elink_params link_params; 1484 struct elink_vars link_vars; 1485 uint32_t link_cnt; 1486 struct bxe_link_report_data last_reported_link; 1487 char mac_addr_str[32]; 1488 1489 int last_reported_link_state; 1490 1491 int tx_ring_size; 1492 int rx_ring_size; 1493 int wol; 1494 1495 int is_leader; 1496 int recovery_state; 1497 #define BXE_RECOVERY_DONE 1 1498 #define BXE_RECOVERY_INIT 2 1499 #define BXE_RECOVERY_WAIT 3 1500 #define BXE_RECOVERY_FAILED 4 1501 #define BXE_RECOVERY_NIC_LOADING 5 1502 1503 #define BXE_ERR_TXQ_STUCK 0x1 /* Tx queue stuck detected by driver. */ 1504 #define BXE_ERR_MISC 0x2 /* MISC ERR */ 1505 #define BXE_ERR_PARITY 0x4 /* Parity error detected. */ 1506 #define BXE_ERR_STATS_TO 0x8 /* Statistics timeout detected. */ 1507 #define BXE_ERR_MC_ASSERT 0x10 /* MC assert attention received. */ 1508 #define BXE_ERR_PANIC 0x20 /* Driver asserted. */ 1509 #define BXE_ERR_MCP_ASSERT 0x40 /* MCP assert attention received. No Recovery*/ 1510 #define BXE_ERR_GLOBAL 0x80 /* PCIe/PXP/IGU/MISC/NIG device blocks error- needs PCIe/Fundamental reset */ 1511 uint32_t error_status; 1512 1513 uint32_t rx_mode; 1514 #define BXE_RX_MODE_NONE 0 1515 #define BXE_RX_MODE_NORMAL 1 1516 #define BXE_RX_MODE_ALLMULTI 2 1517 #define BXE_RX_MODE_PROMISC 3 1518 #define BXE_MAX_MULTICAST 64 1519 1520 struct bxe_port port; 1521 1522 struct cmng_init cmng; 1523 1524 /* user configs */ 1525 int num_queues; 1526 int max_rx_bufs; 1527 int hc_rx_ticks; 1528 int hc_tx_ticks; 1529 int rx_budget; 1530 int max_aggregation_size; 1531 int mrrs; 1532 int autogreeen; 1533 #define AUTO_GREEN_HW_DEFAULT 0 1534 #define AUTO_GREEN_FORCE_ON 1 1535 #define AUTO_GREEN_FORCE_OFF 2 1536 int interrupt_mode; 1537 #define INTR_MODE_INTX 0 1538 #define INTR_MODE_MSI 1 1539 #define INTR_MODE_MSIX 2 1540 int udp_rss; 1541 1542 /* interrupt allocations */ 1543 struct bxe_intr intr[MAX_RSS_CHAINS+1]; 1544 int intr_count; 1545 uint8_t igu_dsb_id; 1546 uint8_t igu_base_sb; 1547 uint8_t igu_sb_cnt; 1548 //uint8_t min_msix_vec_cnt; 1549 uint32_t igu_base_addr; 1550 //bus_addr_t def_status_blk_mapping; 1551 uint8_t base_fw_ndsb; 1552 #define DEF_SB_IGU_ID 16 1553 #define DEF_SB_ID HC_SP_SB_ID 1554 1555 /* parent bus DMA tag */ 1556 bus_dma_tag_t parent_dma_tag; 1557 1558 /* default status block */ 1559 struct bxe_dma def_sb_dma; 1560 struct host_sp_status_block *def_sb; 1561 uint16_t def_idx; 1562 uint16_t def_att_idx; 1563 uint32_t attn_state; 1564 struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS]; 1565 1566 /* general SP events - stats query, cfc delete, etc */ 1567 #define HC_SP_INDEX_ETH_DEF_CONS 3 1568 /* EQ completions */ 1569 #define HC_SP_INDEX_EQ_CONS 7 1570 /* FCoE L2 connection completions */ 1571 #define HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS 6 1572 #define HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS 4 1573 /* iSCSI L2 */ 1574 #define HC_SP_INDEX_ETH_ISCSI_CQ_CONS 5 1575 #define HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS 1 1576 1577 /* event queue */ 1578 struct bxe_dma eq_dma; 1579 union event_ring_elem *eq; 1580 uint16_t eq_prod; 1581 uint16_t eq_cons; 1582 uint16_t *eq_cons_sb; 1583 #define NUM_EQ_PAGES 1 /* must be a power of 2 */ 1584 #define EQ_DESC_CNT_PAGE (BCM_PAGE_SIZE / sizeof(union event_ring_elem)) 1585 #define EQ_DESC_MAX_PAGE (EQ_DESC_CNT_PAGE - 1) 1586 #define NUM_EQ_DESC (EQ_DESC_CNT_PAGE * NUM_EQ_PAGES) 1587 #define EQ_DESC_MASK (NUM_EQ_DESC - 1) 1588 #define MAX_EQ_AVAIL (EQ_DESC_MAX_PAGE * NUM_EQ_PAGES - 2) 1589 /* depends on EQ_DESC_CNT_PAGE being a power of 2 */ 1590 #define NEXT_EQ_IDX(x) \ 1591 ((((x) & EQ_DESC_MAX_PAGE) == (EQ_DESC_MAX_PAGE - 1)) ? \ 1592 ((x) + 2) : ((x) + 1)) 1593 /* depends on the above and on NUM_EQ_PAGES being a power of 2 */ 1594 #define EQ_DESC(x) ((x) & EQ_DESC_MASK) 1595 1596 /* slow path */ 1597 struct bxe_dma sp_dma; 1598 struct bxe_slowpath *sp; 1599 unsigned long sp_state; 1600 1601 /* slow path queue */ 1602 struct bxe_dma spq_dma; 1603 struct eth_spe *spq; 1604 #define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe)) 1605 #define MAX_SP_DESC_CNT (SP_DESC_CNT - 1) 1606 #define MAX_SPQ_PENDING 8 1607 1608 uint16_t spq_prod_idx; 1609 struct eth_spe *spq_prod_bd; 1610 struct eth_spe *spq_last_bd; 1611 uint16_t *dsb_sp_prod; 1612 //uint16_t *spq_hw_con; 1613 //uint16_t spq_left; 1614 1615 volatile unsigned long eq_spq_left; /* COMMON_xxx ramrod credit */ 1616 volatile unsigned long cq_spq_left; /* ETH_xxx ramrod credit */ 1617 1618 /* fw decompression buffer */ 1619 struct bxe_dma gz_buf_dma; 1620 void *gz_buf; 1621 z_streamp gz_strm; 1622 uint32_t gz_outlen; 1623 #define GUNZIP_BUF(sc) (sc->gz_buf) 1624 #define GUNZIP_OUTLEN(sc) (sc->gz_outlen) 1625 #define GUNZIP_PHYS(sc) (sc->gz_buf_dma.paddr) 1626 #define FW_BUF_SIZE 0x40000 1627 1628 const struct raw_op *init_ops; 1629 const uint16_t *init_ops_offsets; /* init block offsets inside init_ops */ 1630 const uint32_t *init_data; /* data blob, 32 bit granularity */ 1631 uint32_t init_mode_flags; 1632 #define INIT_MODE_FLAGS(sc) (sc->init_mode_flags) 1633 /* PRAM blobs - raw data */ 1634 const uint8_t *tsem_int_table_data; 1635 const uint8_t *tsem_pram_data; 1636 const uint8_t *usem_int_table_data; 1637 const uint8_t *usem_pram_data; 1638 const uint8_t *xsem_int_table_data; 1639 const uint8_t *xsem_pram_data; 1640 const uint8_t *csem_int_table_data; 1641 const uint8_t *csem_pram_data; 1642 #define INIT_OPS(sc) (sc->init_ops) 1643 #define INIT_OPS_OFFSETS(sc) (sc->init_ops_offsets) 1644 #define INIT_DATA(sc) (sc->init_data) 1645 #define INIT_TSEM_INT_TABLE_DATA(sc) (sc->tsem_int_table_data) 1646 #define INIT_TSEM_PRAM_DATA(sc) (sc->tsem_pram_data) 1647 #define INIT_USEM_INT_TABLE_DATA(sc) (sc->usem_int_table_data) 1648 #define INIT_USEM_PRAM_DATA(sc) (sc->usem_pram_data) 1649 #define INIT_XSEM_INT_TABLE_DATA(sc) (sc->xsem_int_table_data) 1650 #define INIT_XSEM_PRAM_DATA(sc) (sc->xsem_pram_data) 1651 #define INIT_CSEM_INT_TABLE_DATA(sc) (sc->csem_int_table_data) 1652 #define INIT_CSEM_PRAM_DATA(sc) (sc->csem_pram_data) 1653 1654 /* ILT 1655 * For max 196 cids (64*3 + non-eth), 32KB ILT page size and 1KB 1656 * context size we need 8 ILT entries. 1657 */ 1658 #define ILT_MAX_L2_LINES 8 1659 struct hw_context context[ILT_MAX_L2_LINES]; 1660 struct ecore_ilt *ilt; 1661 #define ILT_MAX_LINES 256 1662 1663 /* max supported number of RSS queues: IGU SBs minus one for CNIC */ 1664 #define BXE_MAX_RSS_COUNT(sc) ((sc)->igu_sb_cnt - CNIC_SUPPORT(sc)) 1665 /* max CID count: Max RSS * Max_Tx_Multi_Cos + FCoE + iSCSI */ 1666 #if 1 1667 #define BXE_L2_MAX_CID(sc) \ 1668 (BXE_MAX_RSS_COUNT(sc) * ECORE_MULTI_TX_COS + 2 * CNIC_SUPPORT(sc)) 1669 #else 1670 #define BXE_L2_MAX_CID(sc) /* OOO + FWD */ \ 1671 (BXE_MAX_RSS_COUNT(sc) * ECORE_MULTI_TX_COS + 4 * CNIC_SUPPORT(sc)) 1672 #endif 1673 #if 1 1674 #define BXE_L2_CID_COUNT(sc) \ 1675 (BXE_NUM_ETH_QUEUES(sc) * ECORE_MULTI_TX_COS + 2 * CNIC_SUPPORT(sc)) 1676 #else 1677 #define BXE_L2_CID_COUNT(sc) /* OOO + FWD */ \ 1678 (BXE_NUM_ETH_QUEUES(sc) * ECORE_MULTI_TX_COS + 4 * CNIC_SUPPORT(sc)) 1679 #endif 1680 #define L2_ILT_LINES(sc) \ 1681 (DIV_ROUND_UP(BXE_L2_CID_COUNT(sc), ILT_PAGE_CIDS)) 1682 1683 int qm_cid_count; 1684 1685 uint8_t dropless_fc; 1686 1687 /* total number of FW statistics requests */ 1688 uint8_t fw_stats_num; 1689 /* 1690 * This is a memory buffer that will contain both statistics ramrod 1691 * request and data. 1692 */ 1693 struct bxe_dma fw_stats_dma; 1694 /* 1695 * FW statistics request shortcut (points at the beginning of fw_stats 1696 * buffer). 1697 */ 1698 int fw_stats_req_size; 1699 struct bxe_fw_stats_req *fw_stats_req; 1700 bus_addr_t fw_stats_req_mapping; 1701 /* 1702 * FW statistics data shortcut (points at the beginning of fw_stats 1703 * buffer + fw_stats_req_size). 1704 */ 1705 int fw_stats_data_size; 1706 struct bxe_fw_stats_data *fw_stats_data; 1707 bus_addr_t fw_stats_data_mapping; 1708 1709 /* tracking a pending STAT_QUERY ramrod */ 1710 uint16_t stats_pending; 1711 /* number of completed statistics ramrods */ 1712 uint16_t stats_comp; 1713 uint16_t stats_counter; 1714 uint8_t stats_init; 1715 int stats_state; 1716 1717 struct bxe_eth_stats eth_stats; 1718 struct host_func_stats func_stats; 1719 struct bxe_eth_stats_old eth_stats_old; 1720 struct bxe_net_stats_old net_stats_old; 1721 struct bxe_fw_port_stats_old fw_stats_old; 1722 1723 struct dmae_cmd stats_dmae; /* used by dmae command loader */ 1724 int executer_idx; 1725 1726 int mtu; 1727 1728 /* LLDP params */ 1729 struct bxe_config_lldp_params lldp_config_params; 1730 /* DCB support on/off */ 1731 int dcb_state; 1732 #define BXE_DCB_STATE_OFF 0 1733 #define BXE_DCB_STATE_ON 1 1734 /* DCBX engine mode */ 1735 int dcbx_enabled; 1736 #define BXE_DCBX_ENABLED_OFF 0 1737 #define BXE_DCBX_ENABLED_ON_NEG_OFF 1 1738 #define BXE_DCBX_ENABLED_ON_NEG_ON 2 1739 #define BXE_DCBX_ENABLED_INVALID -1 1740 uint8_t dcbx_mode_uset; 1741 struct bxe_config_dcbx_params dcbx_config_params; 1742 struct bxe_dcbx_port_params dcbx_port_params; 1743 int dcb_version; 1744 1745 uint8_t cnic_support; 1746 uint8_t cnic_enabled; 1747 uint8_t cnic_loaded; 1748 #define CNIC_SUPPORT(sc) 0 /* ((sc)->cnic_support) */ 1749 #define CNIC_ENABLED(sc) 0 /* ((sc)->cnic_enabled) */ 1750 #define CNIC_LOADED(sc) 0 /* ((sc)->cnic_loaded) */ 1751 1752 /* multiple tx classes of service */ 1753 uint8_t max_cos; 1754 #define BXE_MAX_PRIORITY 8 1755 /* priority to cos mapping */ 1756 uint8_t prio_to_cos[BXE_MAX_PRIORITY]; 1757 1758 int panic; 1759 1760 struct cdev *ioctl_dev; 1761 1762 void *grc_dump; 1763 unsigned int trigger_grcdump; 1764 unsigned int grcdump_done; 1765 unsigned int grcdump_started; 1766 int bxe_pause_param; 1767 void *eeprom; 1768 }; /* struct bxe_softc */ 1769 1770 /* IOCTL sub-commands for edebug and firmware upgrade */ 1771 #define BXE_IOC_RD_NVRAM 1 1772 #define BXE_IOC_WR_NVRAM 2 1773 #define BXE_IOC_STATS_SHOW_NUM 3 1774 #define BXE_IOC_STATS_SHOW_STR 4 1775 #define BXE_IOC_STATS_SHOW_CNT 5 1776 1777 struct bxe_nvram_data { 1778 uint32_t op; /* ioctl sub-command */ 1779 uint32_t offset; 1780 uint32_t len; 1781 uint32_t value[1]; /* variable */ 1782 }; 1783 1784 union bxe_stats_show_data { 1785 uint32_t op; /* ioctl sub-command */ 1786 1787 struct { 1788 uint32_t num; /* return number of stats */ 1789 uint32_t len; /* length of each string item */ 1790 } desc; 1791 1792 /* variable length... */ 1793 char str[1]; /* holds names of desc.num stats, each desc.len in length */ 1794 1795 /* variable length... */ 1796 uint64_t stats[1]; /* holds all stats */ 1797 }; 1798 1799 /* function init flags */ 1800 #define FUNC_FLG_RSS 0x0001 1801 #define FUNC_FLG_STATS 0x0002 1802 /* FUNC_FLG_UNMATCHED 0x0004 */ 1803 #define FUNC_FLG_TPA 0x0008 1804 #define FUNC_FLG_SPQ 0x0010 1805 #define FUNC_FLG_LEADING 0x0020 /* PF only */ 1806 1807 struct bxe_func_init_params { 1808 bus_addr_t fw_stat_map; /* (dma) valid if FUNC_FLG_STATS */ 1809 bus_addr_t spq_map; /* (dma) valid if FUNC_FLG_SPQ */ 1810 uint16_t func_flgs; 1811 uint16_t func_id; /* abs function id */ 1812 uint16_t pf_id; 1813 uint16_t spq_prod; /* valid if FUNC_FLG_SPQ */ 1814 }; 1815 1816 /* memory resources reside at BARs 0, 2, 4 */ 1817 /* Run `pciconf -lb` to see mappings */ 1818 #define BAR0 0 1819 #define BAR1 2 1820 #define BAR2 4 1821 1822 #ifdef BXE_REG_NO_INLINE 1823 1824 uint8_t bxe_reg_read8(struct bxe_softc *sc, bus_size_t offset); 1825 uint16_t bxe_reg_read16(struct bxe_softc *sc, bus_size_t offset); 1826 uint32_t bxe_reg_read32(struct bxe_softc *sc, bus_size_t offset); 1827 1828 void bxe_reg_write8(struct bxe_softc *sc, bus_size_t offset, uint8_t val); 1829 void bxe_reg_write16(struct bxe_softc *sc, bus_size_t offset, uint16_t val); 1830 void bxe_reg_write32(struct bxe_softc *sc, bus_size_t offset, uint32_t val); 1831 1832 #define REG_RD8(sc, offset) bxe_reg_read8(sc, offset) 1833 #define REG_RD16(sc, offset) bxe_reg_read16(sc, offset) 1834 #define REG_RD32(sc, offset) bxe_reg_read32(sc, offset) 1835 1836 #define REG_WR8(sc, offset, val) bxe_reg_write8(sc, offset, val) 1837 #define REG_WR16(sc, offset, val) bxe_reg_write16(sc, offset, val) 1838 #define REG_WR32(sc, offset, val) bxe_reg_write32(sc, offset, val) 1839 1840 #else /* not BXE_REG_NO_INLINE */ 1841 1842 #define REG_WR8(sc, offset, val) \ 1843 bus_space_write_1(sc->bar[BAR0].tag, \ 1844 sc->bar[BAR0].handle, \ 1845 offset, val) 1846 1847 #define REG_WR16(sc, offset, val) \ 1848 bus_space_write_2(sc->bar[BAR0].tag, \ 1849 sc->bar[BAR0].handle, \ 1850 offset, val) 1851 1852 #define REG_WR32(sc, offset, val) \ 1853 bus_space_write_4(sc->bar[BAR0].tag, \ 1854 sc->bar[BAR0].handle, \ 1855 offset, val) 1856 1857 #define REG_RD8(sc, offset) \ 1858 bus_space_read_1(sc->bar[BAR0].tag, \ 1859 sc->bar[BAR0].handle, \ 1860 offset) 1861 1862 #define REG_RD16(sc, offset) \ 1863 bus_space_read_2(sc->bar[BAR0].tag, \ 1864 sc->bar[BAR0].handle, \ 1865 offset) 1866 1867 #define REG_RD32(sc, offset) \ 1868 bus_space_read_4(sc->bar[BAR0].tag, \ 1869 sc->bar[BAR0].handle, \ 1870 offset) 1871 1872 #endif /* BXE_REG_NO_INLINE */ 1873 1874 #define REG_RD(sc, offset) REG_RD32(sc, offset) 1875 #define REG_WR(sc, offset, val) REG_WR32(sc, offset, val) 1876 1877 #define REG_RD_IND(sc, offset) bxe_reg_rd_ind(sc, offset) 1878 #define REG_WR_IND(sc, offset, val) bxe_reg_wr_ind(sc, offset, val) 1879 1880 #define BXE_SP(sc, var) (&(sc)->sp->var) 1881 #define BXE_SP_MAPPING(sc, var) \ 1882 (sc->sp_dma.paddr + offsetof(struct bxe_slowpath, var)) 1883 1884 #define BXE_FP(sc, nr, var) ((sc)->fp[(nr)].var) 1885 #define BXE_SP_OBJ(sc, fp) ((sc)->sp_objs[(fp)->index]) 1886 1887 #define REG_RD_DMAE(sc, offset, valp, len32) \ 1888 do { \ 1889 bxe_read_dmae(sc, offset, len32); \ 1890 memcpy(valp, BXE_SP(sc, wb_data[0]), (len32) * 4); \ 1891 } while (0) 1892 1893 #define REG_WR_DMAE(sc, offset, valp, len32) \ 1894 do { \ 1895 memcpy(BXE_SP(sc, wb_data[0]), valp, (len32) * 4); \ 1896 bxe_write_dmae(sc, BXE_SP_MAPPING(sc, wb_data), offset, len32); \ 1897 } while (0) 1898 1899 #define REG_WR_DMAE_LEN(sc, offset, valp, len32) \ 1900 REG_WR_DMAE(sc, offset, valp, len32) 1901 1902 #define REG_RD_DMAE_LEN(sc, offset, valp, len32) \ 1903 REG_RD_DMAE(sc, offset, valp, len32) 1904 1905 #define VIRT_WR_DMAE_LEN(sc, data, addr, len32, le32_swap) \ 1906 do { \ 1907 /* if (le32_swap) { */ \ 1908 /* BLOGW(sc, "VIRT_WR_DMAE_LEN with le32_swap=1\n"); */ \ 1909 /* } */ \ 1910 memcpy(GUNZIP_BUF(sc), data, len32 * 4); \ 1911 ecore_write_big_buf_wb(sc, addr, len32); \ 1912 } while (0) 1913 1914 #define BXE_DB_MIN_SHIFT 3 /* 8 bytes */ 1915 #define BXE_DB_SHIFT 7 /* 128 bytes */ 1916 #if (BXE_DB_SHIFT < BXE_DB_MIN_SHIFT) 1917 #error "Minimum DB doorbell stride is 8" 1918 #endif 1919 #define DPM_TRIGGER_TYPE 0x40 1920 #define DOORBELL(sc, cid, val) \ 1921 do { \ 1922 bus_space_write_4(sc->bar[BAR1].tag, sc->bar[BAR1].handle, \ 1923 ((sc->doorbell_size * (cid)) + DPM_TRIGGER_TYPE), \ 1924 (uint32_t)val); \ 1925 } while(0) 1926 1927 #define SHMEM_ADDR(sc, field) \ 1928 (sc->devinfo.shmem_base + offsetof(struct shmem_region, field)) 1929 #define SHMEM_RD(sc, field) REG_RD(sc, SHMEM_ADDR(sc, field)) 1930 #define SHMEM_RD16(sc, field) REG_RD16(sc, SHMEM_ADDR(sc, field)) 1931 #define SHMEM_WR(sc, field, val) REG_WR(sc, SHMEM_ADDR(sc, field), val) 1932 1933 #define SHMEM2_ADDR(sc, field) \ 1934 (sc->devinfo.shmem2_base + offsetof(struct shmem2_region, field)) 1935 #define SHMEM2_HAS(sc, field) \ 1936 (sc->devinfo.shmem2_base && (REG_RD(sc, SHMEM2_ADDR(sc, size)) > \ 1937 offsetof(struct shmem2_region, field))) 1938 #define SHMEM2_RD(sc, field) REG_RD(sc, SHMEM2_ADDR(sc, field)) 1939 #define SHMEM2_WR(sc, field, val) REG_WR(sc, SHMEM2_ADDR(sc, field), val) 1940 1941 #define MFCFG_ADDR(sc, field) \ 1942 (sc->devinfo.mf_cfg_base + offsetof(struct mf_cfg, field)) 1943 #define MFCFG_RD(sc, field) REG_RD(sc, MFCFG_ADDR(sc, field)) 1944 #define MFCFG_RD16(sc, field) REG_RD16(sc, MFCFG_ADDR(sc, field)) 1945 #define MFCFG_WR(sc, field, val) REG_WR(sc, MFCFG_ADDR(sc, field), val) 1946 1947 /* DMAE command defines */ 1948 1949 #define DMAE_TIMEOUT -1 1950 #define DMAE_PCI_ERROR -2 /* E2 and onward */ 1951 #define DMAE_NOT_RDY -3 1952 #define DMAE_PCI_ERR_FLAG 0x80000000 1953 1954 #define DMAE_SRC_PCI 0 1955 #define DMAE_SRC_GRC 1 1956 1957 #define DMAE_DST_NONE 0 1958 #define DMAE_DST_PCI 1 1959 #define DMAE_DST_GRC 2 1960 1961 #define DMAE_COMP_PCI 0 1962 #define DMAE_COMP_GRC 1 1963 1964 #define DMAE_COMP_REGULAR 0 1965 #define DMAE_COM_SET_ERR 1 1966 1967 #define DMAE_CMD_SRC_PCI (DMAE_SRC_PCI << DMAE_CMD_SRC_SHIFT) 1968 #define DMAE_CMD_SRC_GRC (DMAE_SRC_GRC << DMAE_CMD_SRC_SHIFT) 1969 #define DMAE_CMD_DST_PCI (DMAE_DST_PCI << DMAE_CMD_DST_SHIFT) 1970 #define DMAE_CMD_DST_GRC (DMAE_DST_GRC << DMAE_CMD_DST_SHIFT) 1971 1972 #define DMAE_CMD_C_DST_PCI (DMAE_COMP_PCI << DMAE_CMD_C_DST_SHIFT) 1973 #define DMAE_CMD_C_DST_GRC (DMAE_COMP_GRC << DMAE_CMD_C_DST_SHIFT) 1974 1975 #define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_CMD_ENDIANITY_SHIFT) 1976 #define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_CMD_ENDIANITY_SHIFT) 1977 #define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_CMD_ENDIANITY_SHIFT) 1978 #define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_CMD_ENDIANITY_SHIFT) 1979 1980 #define DMAE_CMD_PORT_0 0 1981 #define DMAE_CMD_PORT_1 DMAE_CMD_PORT 1982 1983 #define DMAE_SRC_PF 0 1984 #define DMAE_SRC_VF 1 1985 1986 #define DMAE_DST_PF 0 1987 #define DMAE_DST_VF 1 1988 1989 #define DMAE_C_SRC 0 1990 #define DMAE_C_DST 1 1991 1992 #define DMAE_LEN32_RD_MAX 0x80 1993 #define DMAE_LEN32_WR_MAX(sc) (CHIP_IS_E1(sc) ? 0x400 : 0x2000) 1994 1995 #define DMAE_COMP_VAL 0x60d0d0ae /* E2 and beyond, upper bit indicates error */ 1996 1997 #define MAX_DMAE_C_PER_PORT 8 1998 #define INIT_DMAE_C(sc) ((SC_PORT(sc) * MAX_DMAE_C_PER_PORT) + SC_VN(sc)) 1999 #define PMF_DMAE_C(sc) ((SC_PORT(sc) * MAX_DMAE_C_PER_PORT) + E1HVN_MAX) 2000 2001 static const uint32_t dmae_reg_go_c[] = { 2002 DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3, 2003 DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7, 2004 DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11, 2005 DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15 2006 }; 2007 2008 #define ATTN_NIG_FOR_FUNC (1L << 8) 2009 #define ATTN_SW_TIMER_4_FUNC (1L << 9) 2010 #define GPIO_2_FUNC (1L << 10) 2011 #define GPIO_3_FUNC (1L << 11) 2012 #define GPIO_4_FUNC (1L << 12) 2013 #define ATTN_GENERAL_ATTN_1 (1L << 13) 2014 #define ATTN_GENERAL_ATTN_2 (1L << 14) 2015 #define ATTN_GENERAL_ATTN_3 (1L << 15) 2016 #define ATTN_GENERAL_ATTN_4 (1L << 13) 2017 #define ATTN_GENERAL_ATTN_5 (1L << 14) 2018 #define ATTN_GENERAL_ATTN_6 (1L << 15) 2019 #define ATTN_HARD_WIRED_MASK 0xff00 2020 #define ATTENTION_ID 4 2021 2022 #define AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR \ 2023 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR 2024 2025 #define MAX_IGU_ATTN_ACK_TO 100 2026 2027 #define STORM_ASSERT_ARRAY_SIZE 50 2028 2029 #define BXE_PMF_LINK_ASSERT(sc) \ 2030 GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + SC_FUNC(sc)) 2031 2032 #define BXE_MC_ASSERT_BITS \ 2033 (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \ 2034 GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \ 2035 GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \ 2036 GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT)) 2037 2038 #define BXE_MCP_ASSERT \ 2039 GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT) 2040 2041 #define BXE_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC) 2042 #define BXE_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \ 2043 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \ 2044 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \ 2045 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \ 2046 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \ 2047 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC)) 2048 2049 #define MULTI_MASK 0x7f 2050 2051 #define PFS_PER_PORT(sc) \ 2052 ((CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4) 2053 #define SC_MAX_VN_NUM(sc) PFS_PER_PORT(sc) 2054 2055 #define FIRST_ABS_FUNC_IN_PORT(sc) \ 2056 ((CHIP_PORT_MODE(sc) == CHIP_PORT_MODE_NONE) ? \ 2057 PORT_ID(sc) : (PATH_ID(sc) + (2 * PORT_ID(sc)))) 2058 2059 #define FOREACH_ABS_FUNC_IN_PORT(sc, i) \ 2060 for ((i) = FIRST_ABS_FUNC_IN_PORT(sc); \ 2061 (i) < MAX_FUNC_NUM; \ 2062 (i) += (MAX_FUNC_NUM / PFS_PER_PORT(sc))) 2063 2064 #define BXE_SWCID_SHIFT 17 2065 #define BXE_SWCID_MASK ((0x1 << BXE_SWCID_SHIFT) - 1) 2066 2067 #define SW_CID(x) (le32toh(x) & BXE_SWCID_MASK) 2068 #define CQE_CMD(x) (le32toh(x) >> COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT) 2069 2070 #define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE) 2071 #define CQE_TYPE_START(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_START_AGG) 2072 #define CQE_TYPE_STOP(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_STOP_AGG) 2073 #define CQE_TYPE_SLOW(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_RAMROD) 2074 #define CQE_TYPE_FAST(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_FASTPATH) 2075 2076 /* must be used on a CID before placing it on a HW ring */ 2077 #define HW_CID(sc, x) \ 2078 ((SC_PORT(sc) << 23) | (SC_VN(sc) << BXE_SWCID_SHIFT) | (x)) 2079 2080 #define SPEED_10 10 2081 #define SPEED_100 100 2082 #define SPEED_1000 1000 2083 #define SPEED_2500 2500 2084 #define SPEED_10000 10000 2085 2086 #define PCI_PM_D0 1 2087 #define PCI_PM_D3hot 2 2088 2089 #ifndef DUPLEX_UNKNOWN 2090 #define DUPLEX_UNKNOWN (0xff) 2091 #endif 2092 2093 #ifndef SPEED_UNKNOWN 2094 #define SPEED_UNKNOWN (-1) 2095 #endif 2096 2097 /* Enable or disable autonegotiation. */ 2098 #define AUTONEG_DISABLE 0x00 2099 #define AUTONEG_ENABLE 0x01 2100 2101 /* Which connector port. */ 2102 #define PORT_TP 0x00 2103 #define PORT_AUI 0x01 2104 #define PORT_MII 0x02 2105 #define PORT_FIBRE 0x03 2106 #define PORT_BNC 0x04 2107 #define PORT_DA 0x05 2108 #define PORT_NONE 0xef 2109 #define PORT_OTHER 0xff 2110 2111 int bxe_test_bit(int nr, volatile unsigned long * addr); 2112 void bxe_set_bit(unsigned int nr, volatile unsigned long * addr); 2113 void bxe_clear_bit(int nr, volatile unsigned long * addr); 2114 int bxe_test_and_set_bit(int nr, volatile unsigned long * addr); 2115 int bxe_test_and_clear_bit(int nr, volatile unsigned long * addr); 2116 int bxe_cmpxchg(volatile int *addr, int old, int new); 2117 2118 void bxe_reg_wr_ind(struct bxe_softc *sc, uint32_t addr, 2119 uint32_t val); 2120 uint32_t bxe_reg_rd_ind(struct bxe_softc *sc, uint32_t addr); 2121 2122 2123 int bxe_dma_alloc(struct bxe_softc *sc, bus_size_t size, 2124 struct bxe_dma *dma, const char *msg); 2125 void bxe_dma_free(struct bxe_softc *sc, struct bxe_dma *dma); 2126 2127 uint32_t bxe_dmae_opcode_add_comp(uint32_t opcode, uint8_t comp_type); 2128 uint32_t bxe_dmae_opcode_clr_src_reset(uint32_t opcode); 2129 uint32_t bxe_dmae_opcode(struct bxe_softc *sc, uint8_t src_type, 2130 uint8_t dst_type, uint8_t with_comp, 2131 uint8_t comp_type); 2132 void bxe_post_dmae(struct bxe_softc *sc, struct dmae_cmd *dmae, int idx); 2133 void bxe_read_dmae(struct bxe_softc *sc, uint32_t src_addr, uint32_t len32); 2134 void bxe_write_dmae(struct bxe_softc *sc, bus_addr_t dma_addr, 2135 uint32_t dst_addr, uint32_t len32); 2136 void bxe_write_dmae_phys_len(struct bxe_softc *sc, bus_addr_t phys_addr, 2137 uint32_t addr, uint32_t len); 2138 2139 void bxe_set_ctx_validation(struct bxe_softc *sc, struct eth_context *cxt, 2140 uint32_t cid); 2141 void bxe_update_coalesce_sb_index(struct bxe_softc *sc, uint8_t fw_sb_id, 2142 uint8_t sb_index, uint8_t disable, 2143 uint16_t usec); 2144 2145 int bxe_sp_post(struct bxe_softc *sc, int command, int cid, 2146 uint32_t data_hi, uint32_t data_lo, int cmd_type); 2147 2148 void bxe_igu_ack_sb(struct bxe_softc *sc, uint8_t igu_sb_id, 2149 uint8_t segment, uint16_t index, uint8_t op, 2150 uint8_t update); 2151 2152 void ecore_init_e1_firmware(struct bxe_softc *sc); 2153 void ecore_init_e1h_firmware(struct bxe_softc *sc); 2154 void ecore_init_e2_firmware(struct bxe_softc *sc); 2155 2156 void ecore_storm_memset_struct(struct bxe_softc *sc, uint32_t addr, 2157 size_t size, uint32_t *data); 2158 2159 /*********************/ 2160 /* LOGGING AND DEBUG */ 2161 /*********************/ 2162 2163 /* debug logging codepaths */ 2164 #define DBG_LOAD 0x00000001 /* load and unload */ 2165 #define DBG_INTR 0x00000002 /* interrupt handling */ 2166 #define DBG_SP 0x00000004 /* slowpath handling */ 2167 #define DBG_STATS 0x00000008 /* stats updates */ 2168 #define DBG_TX 0x00000010 /* packet transmit */ 2169 #define DBG_RX 0x00000020 /* packet receive */ 2170 #define DBG_PHY 0x00000040 /* phy/link handling */ 2171 #define DBG_IOCTL 0x00000080 /* ioctl handling */ 2172 #define DBG_MBUF 0x00000100 /* dumping mbuf info */ 2173 #define DBG_REGS 0x00000200 /* register access */ 2174 #define DBG_LRO 0x00000400 /* lro processing */ 2175 #define DBG_ASSERT 0x80000000 /* debug assert */ 2176 #define DBG_ALL 0xFFFFFFFF /* flying monkeys */ 2177 2178 #define DBASSERT(sc, exp, msg) \ 2179 do { \ 2180 if (__predict_false(sc->debug & DBG_ASSERT)) { \ 2181 if (__predict_false(!(exp))) { \ 2182 panic msg; \ 2183 } \ 2184 } \ 2185 } while (0) 2186 2187 /* log a debug message */ 2188 #define BLOGD(sc, codepath, format, args...) \ 2189 do { \ 2190 if (__predict_false(sc->debug & (codepath))) { \ 2191 device_printf((sc)->dev, \ 2192 "%s(%s:%d) " format, \ 2193 __FUNCTION__, \ 2194 __FILE__, \ 2195 __LINE__, \ 2196 ## args); \ 2197 } \ 2198 } while(0) 2199 2200 /* log a info message */ 2201 #define BLOGI(sc, format, args...) \ 2202 do { \ 2203 if (__predict_false(sc->debug)) { \ 2204 device_printf((sc)->dev, \ 2205 "%s(%s:%d) " format, \ 2206 __FUNCTION__, \ 2207 __FILE__, \ 2208 __LINE__, \ 2209 ## args); \ 2210 } else { \ 2211 device_printf((sc)->dev, \ 2212 format, \ 2213 ## args); \ 2214 } \ 2215 } while(0) 2216 2217 /* log a warning message */ 2218 #define BLOGW(sc, format, args...) \ 2219 do { \ 2220 if (__predict_false(sc->debug)) { \ 2221 device_printf((sc)->dev, \ 2222 "%s(%s:%d) WARNING: " format, \ 2223 __FUNCTION__, \ 2224 __FILE__, \ 2225 __LINE__, \ 2226 ## args); \ 2227 } else { \ 2228 device_printf((sc)->dev, \ 2229 "WARNING: " format, \ 2230 ## args); \ 2231 } \ 2232 } while(0) 2233 2234 /* log a error message */ 2235 #define BLOGE(sc, format, args...) \ 2236 do { \ 2237 if (__predict_false(sc->debug)) { \ 2238 device_printf((sc)->dev, \ 2239 "%s(%s:%d) ERROR: " format, \ 2240 __FUNCTION__, \ 2241 __FILE__, \ 2242 __LINE__, \ 2243 ## args); \ 2244 } else { \ 2245 device_printf((sc)->dev, \ 2246 "ERROR: " format, \ 2247 ## args); \ 2248 } \ 2249 } while(0) 2250 2251 #ifdef ECORE_STOP_ON_ERROR 2252 2253 #define bxe_panic(sc, msg) \ 2254 do { \ 2255 panic msg; \ 2256 } while (0) 2257 2258 #else 2259 2260 #define bxe_panic(sc, msg) \ 2261 device_printf((sc)->dev, "%s (%s,%d)\n", __FUNCTION__, __FILE__, __LINE__); 2262 2263 #endif 2264 2265 #define CATC_TRIGGER(sc, data) REG_WR((sc), 0x2000, (data)); 2266 #define CATC_TRIGGER_START(sc) CATC_TRIGGER((sc), 0xcafecafe) 2267 2268 void bxe_dump_mem(struct bxe_softc *sc, char *tag, 2269 uint8_t *mem, uint32_t len); 2270 void bxe_dump_mbuf_data(struct bxe_softc *sc, char *pTag, 2271 struct mbuf *m, uint8_t contents); 2272 2273 #define BXE_SET_FLOWID(m) M_HASHTYPE_SET(m, M_HASHTYPE_OPAQUE) 2274 #define BXE_VALID_FLOWID(m) (M_HASHTYPE_GET(m) != M_HASHTYPE_NONE) 2275 2276 /***********/ 2277 /* INLINES */ 2278 /***********/ 2279 2280 static inline uint32_t 2281 reg_poll(struct bxe_softc *sc, 2282 uint32_t reg, 2283 uint32_t expected, 2284 int ms, 2285 int wait) 2286 { 2287 uint32_t val; 2288 2289 do { 2290 val = REG_RD(sc, reg); 2291 if (val == expected) { 2292 break; 2293 } 2294 ms -= wait; 2295 DELAY(wait * 1000); 2296 } while (ms > 0); 2297 2298 return (val); 2299 } 2300 2301 static inline void 2302 bxe_update_fp_sb_idx(struct bxe_fastpath *fp) 2303 { 2304 mb(); /* status block is written to by the chip */ 2305 fp->fp_hc_idx = fp->sb_running_index[SM_RX_ID]; 2306 } 2307 2308 static inline void 2309 bxe_igu_ack_sb_gen(struct bxe_softc *sc, 2310 uint8_t igu_sb_id, 2311 uint8_t segment, 2312 uint16_t index, 2313 uint8_t op, 2314 uint8_t update, 2315 uint32_t igu_addr) 2316 { 2317 struct igu_regular cmd_data = {0}; 2318 2319 cmd_data.sb_id_and_flags = 2320 ((index << IGU_REGULAR_SB_INDEX_SHIFT) | 2321 (segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) | 2322 (update << IGU_REGULAR_BUPDATE_SHIFT) | 2323 (op << IGU_REGULAR_ENABLE_INT_SHIFT)); 2324 2325 BLOGD(sc, DBG_INTR, "write 0x%08x to IGU addr 0x%x\n", 2326 cmd_data.sb_id_and_flags, igu_addr); 2327 REG_WR(sc, igu_addr, cmd_data.sb_id_and_flags); 2328 2329 /* Make sure that ACK is written */ 2330 bus_space_barrier(sc->bar[0].tag, sc->bar[0].handle, 0, 0, 2331 BUS_SPACE_BARRIER_WRITE); 2332 mb(); 2333 } 2334 2335 static inline void 2336 bxe_hc_ack_sb(struct bxe_softc *sc, 2337 uint8_t sb_id, 2338 uint8_t storm, 2339 uint16_t index, 2340 uint8_t op, 2341 uint8_t update) 2342 { 2343 uint32_t hc_addr = (HC_REG_COMMAND_REG + SC_PORT(sc)*32 + 2344 COMMAND_REG_INT_ACK); 2345 struct igu_ack_register igu_ack; 2346 2347 igu_ack.status_block_index = index; 2348 igu_ack.sb_id_and_flags = 2349 ((sb_id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) | 2350 (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) | 2351 (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) | 2352 (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT)); 2353 2354 REG_WR(sc, hc_addr, (*(uint32_t *)&igu_ack)); 2355 2356 /* Make sure that ACK is written */ 2357 bus_space_barrier(sc->bar[0].tag, sc->bar[0].handle, 0, 0, 2358 BUS_SPACE_BARRIER_WRITE); 2359 mb(); 2360 } 2361 2362 static inline void 2363 bxe_ack_sb(struct bxe_softc *sc, 2364 uint8_t igu_sb_id, 2365 uint8_t storm, 2366 uint16_t index, 2367 uint8_t op, 2368 uint8_t update) 2369 { 2370 if (sc->devinfo.int_block == INT_BLOCK_HC) 2371 bxe_hc_ack_sb(sc, igu_sb_id, storm, index, op, update); 2372 else { 2373 uint8_t segment; 2374 if (CHIP_INT_MODE_IS_BC(sc)) { 2375 segment = storm; 2376 } else if (igu_sb_id != sc->igu_dsb_id) { 2377 segment = IGU_SEG_ACCESS_DEF; 2378 } else if (storm == ATTENTION_ID) { 2379 segment = IGU_SEG_ACCESS_ATTN; 2380 } else { 2381 segment = IGU_SEG_ACCESS_DEF; 2382 } 2383 bxe_igu_ack_sb(sc, igu_sb_id, segment, index, op, update); 2384 } 2385 } 2386 2387 static inline uint16_t 2388 bxe_hc_ack_int(struct bxe_softc *sc) 2389 { 2390 uint32_t hc_addr = (HC_REG_COMMAND_REG + SC_PORT(sc)*32 + 2391 COMMAND_REG_SIMD_MASK); 2392 uint32_t result = REG_RD(sc, hc_addr); 2393 2394 mb(); 2395 return (result); 2396 } 2397 2398 static inline uint16_t 2399 bxe_igu_ack_int(struct bxe_softc *sc) 2400 { 2401 uint32_t igu_addr = (BAR_IGU_INTMEM + IGU_REG_SISR_MDPC_WMASK_LSB_UPPER*8); 2402 uint32_t result = REG_RD(sc, igu_addr); 2403 2404 BLOGD(sc, DBG_INTR, "read 0x%08x from IGU addr 0x%x\n", 2405 result, igu_addr); 2406 2407 mb(); 2408 return (result); 2409 } 2410 2411 static inline uint16_t 2412 bxe_ack_int(struct bxe_softc *sc) 2413 { 2414 mb(); 2415 if (sc->devinfo.int_block == INT_BLOCK_HC) { 2416 return (bxe_hc_ack_int(sc)); 2417 } else { 2418 return (bxe_igu_ack_int(sc)); 2419 } 2420 } 2421 2422 static inline int 2423 func_by_vn(struct bxe_softc *sc, 2424 int vn) 2425 { 2426 return (2 * vn + SC_PORT(sc)); 2427 } 2428 2429 /* 2430 * Statistics ID are global per chip/path, while Client IDs for E1x 2431 * are per port. 2432 */ 2433 static inline uint8_t 2434 bxe_stats_id(struct bxe_fastpath *fp) 2435 { 2436 struct bxe_softc *sc = fp->sc; 2437 2438 if (!CHIP_IS_E1x(sc)) { 2439 return (fp->cl_id); 2440 } 2441 2442 return (fp->cl_id + SC_PORT(sc) * FP_SB_MAX_E1x); 2443 } 2444 2445 #endif /* __BXE_H__ */ 2446 2447