1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2007-2014 QLogic Corporation. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 26 * THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #ifndef __BXE_H__ 30 #define __BXE_H__ 31 32 #include <sys/param.h> 33 #include <sys/kernel.h> 34 #include <sys/systm.h> 35 #include <sys/lock.h> 36 #include <sys/mutex.h> 37 #include <sys/sx.h> 38 #include <sys/module.h> 39 #include <sys/endian.h> 40 #include <sys/types.h> 41 #include <sys/malloc.h> 42 #include <sys/kobj.h> 43 #include <sys/bus.h> 44 #include <sys/rman.h> 45 #include <sys/socket.h> 46 #include <sys/sockio.h> 47 #include <sys/sysctl.h> 48 #include <sys/smp.h> 49 #include <sys/bitstring.h> 50 #include <sys/limits.h> 51 #include <sys/queue.h> 52 #include <sys/taskqueue.h> 53 #include <contrib/zlib/zlib.h> 54 55 #include <net/debugnet.h> 56 #include <net/if.h> 57 #include <net/if_types.h> 58 #include <net/if_arp.h> 59 #include <net/ethernet.h> 60 #include <net/if_dl.h> 61 #include <net/if_var.h> 62 #include <net/if_media.h> 63 #include <net/if_vlan_var.h> 64 #include <net/bpf.h> 65 66 #include <netinet/in.h> 67 #include <netinet/ip.h> 68 #include <netinet/ip6.h> 69 #include <netinet/tcp.h> 70 #include <netinet/udp.h> 71 72 #include <dev/pci/pcireg.h> 73 #include <dev/pci/pcivar.h> 74 75 #include <machine/atomic.h> 76 #include <machine/resource.h> 77 #include <machine/endian.h> 78 #include <machine/bus.h> 79 #include <machine/in_cksum.h> 80 81 #include "device_if.h" 82 #include "bus_if.h" 83 #include "pci_if.h" 84 85 #if _BYTE_ORDER == _LITTLE_ENDIAN 86 #ifndef LITTLE_ENDIAN 87 #define LITTLE_ENDIAN 88 #endif 89 #ifndef __LITTLE_ENDIAN 90 #define __LITTLE_ENDIAN 91 #endif 92 #undef BIG_ENDIAN 93 #undef __BIG_ENDIAN 94 #else /* _BIG_ENDIAN */ 95 #ifndef BIG_ENDIAN 96 #define BIG_ENDIAN 97 #endif 98 #ifndef __BIG_ENDIAN 99 #define __BIG_ENDIAN 100 #endif 101 #undef LITTLE_ENDIAN 102 #undef __LITTLE_ENDIAN 103 #endif 104 105 #include "ecore_mfw_req.h" 106 #include "ecore_fw_defs.h" 107 #include "ecore_hsi.h" 108 #include "ecore_reg.h" 109 #include "bxe_dcb.h" 110 #include "bxe_stats.h" 111 112 #include "bxe_elink.h" 113 114 #define VF_MAC_CREDIT_CNT 0 115 #define VF_VLAN_CREDIT_CNT (0) 116 117 #ifndef ARRAY_SIZE 118 #define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0])) 119 #endif 120 #ifndef ARRSIZE 121 #define ARRSIZE(arr) (sizeof(arr) / sizeof((arr)[0])) 122 #endif 123 #ifndef DIV_ROUND_UP 124 #define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d)) 125 #endif 126 #ifndef roundup 127 #define roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y)) 128 #endif 129 #ifndef ilog2 130 static inline 131 int bxe_ilog2(int x) 132 { 133 int log = 0; 134 while (x >>= 1) log++; 135 return (log); 136 } 137 #define ilog2(x) bxe_ilog2(x) 138 #endif 139 140 #include "ecore_sp.h" 141 142 #define BRCM_VENDORID 0x14e4 143 #define QLOGIC_VENDORID 0x1077 144 #define PCI_ANY_ID (uint16_t)(~0U) 145 146 struct bxe_device_type 147 { 148 uint16_t bxe_vid; 149 uint16_t bxe_did; 150 uint16_t bxe_svid; 151 uint16_t bxe_sdid; 152 char *bxe_name; 153 }; 154 155 #define BCM_PAGE_SHIFT 12 156 #define BCM_PAGE_SIZE (1 << BCM_PAGE_SHIFT) 157 #define BCM_PAGE_MASK (~(BCM_PAGE_SIZE - 1)) 158 #define BCM_PAGE_ALIGN(addr) ((addr + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK) 159 160 #if BCM_PAGE_SIZE != 4096 161 #error Page sizes other than 4KB are unsupported! 162 #endif 163 164 #if (BUS_SPACE_MAXADDR > 0xFFFFFFFF) 165 #define U64_LO(addr) ((uint32_t)(((uint64_t)(addr)) & 0xFFFFFFFF)) 166 #define U64_HI(addr) ((uint32_t)(((uint64_t)(addr)) >> 32)) 167 #else 168 #define U64_LO(addr) ((uint32_t)(addr)) 169 #define U64_HI(addr) (0) 170 #endif 171 #define HILO_U64(hi, lo) ((((uint64_t)(hi)) << 32) + (lo)) 172 173 #define SET_FLAG(value, mask, flag) \ 174 do { \ 175 (value) &= ~(mask); \ 176 (value) |= ((flag) << (mask##_SHIFT)); \ 177 } while (0) 178 179 #define GET_FLAG(value, mask) \ 180 (((value) & (mask)) >> (mask##_SHIFT)) 181 182 #define GET_FIELD(value, fname) \ 183 (((value) & (fname##_MASK)) >> (fname##_SHIFT)) 184 185 #define BXE_MAX_SEGMENTS 12 /* 13-1 for parsing buffer */ 186 #define BXE_TSO_MAX_SEGMENTS 32 187 #define BXE_TSO_MAX_SIZE (65535 + sizeof(struct ether_vlan_header)) 188 #define BXE_TSO_MAX_SEG_SIZE 4096 189 190 /* dropless fc FW/HW related params */ 191 #define BRB_SIZE(sc) (CHIP_IS_E3(sc) ? 1024 : 512) 192 #define MAX_AGG_QS(sc) (CHIP_IS_E1(sc) ? \ 193 ETH_MAX_AGGREGATION_QUEUES_E1 : \ 194 ETH_MAX_AGGREGATION_QUEUES_E1H_E2) 195 #define FW_DROP_LEVEL(sc) (3 + MAX_SPQ_PENDING + MAX_AGG_QS(sc)) 196 #define FW_PREFETCH_CNT 16 197 #define DROPLESS_FC_HEADROOM 100 198 199 /******************/ 200 /* RX SGE defines */ 201 /******************/ 202 203 #define RX_SGE_NUM_PAGES 2 /* must be a power of 2 */ 204 #define RX_SGE_TOTAL_PER_PAGE (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge)) 205 #define RX_SGE_NEXT_PAGE_DESC_CNT 2 206 #define RX_SGE_USABLE_PER_PAGE (RX_SGE_TOTAL_PER_PAGE - RX_SGE_NEXT_PAGE_DESC_CNT) 207 #define RX_SGE_PER_PAGE_MASK (RX_SGE_TOTAL_PER_PAGE - 1) 208 #define RX_SGE_TOTAL (RX_SGE_TOTAL_PER_PAGE * RX_SGE_NUM_PAGES) 209 #define RX_SGE_USABLE (RX_SGE_USABLE_PER_PAGE * RX_SGE_NUM_PAGES) 210 #define RX_SGE_MAX (RX_SGE_TOTAL - 1) 211 #define RX_SGE(x) ((x) & RX_SGE_MAX) 212 213 #define RX_SGE_NEXT(x) \ 214 ((((x) & RX_SGE_PER_PAGE_MASK) == (RX_SGE_USABLE_PER_PAGE - 1)) \ 215 ? (x) + 1 + RX_SGE_NEXT_PAGE_DESC_CNT : (x) + 1) 216 217 #define RX_SGE_MASK_ELEM_SZ 64 218 #define RX_SGE_MASK_ELEM_SHIFT 6 219 #define RX_SGE_MASK_ELEM_MASK ((uint64_t)RX_SGE_MASK_ELEM_SZ - 1) 220 221 /* 222 * Creates a bitmask of all ones in less significant bits. 223 * idx - index of the most significant bit in the created mask. 224 */ 225 #define RX_SGE_ONES_MASK(idx) \ 226 (((uint64_t)0x1 << (((idx) & RX_SGE_MASK_ELEM_MASK) + 1)) - 1) 227 #define RX_SGE_MASK_ELEM_ONE_MASK ((uint64_t)(~0)) 228 229 /* Number of uint64_t elements in SGE mask array. */ 230 #define RX_SGE_MASK_LEN \ 231 ((RX_SGE_NUM_PAGES * RX_SGE_TOTAL_PER_PAGE) / RX_SGE_MASK_ELEM_SZ) 232 #define RX_SGE_MASK_LEN_MASK (RX_SGE_MASK_LEN - 1) 233 #define RX_SGE_NEXT_MASK_ELEM(el) (((el) + 1) & RX_SGE_MASK_LEN_MASK) 234 235 /* 236 * dropless fc calculations for SGEs 237 * Number of required SGEs is the sum of two: 238 * 1. Number of possible opened aggregations (next packet for 239 * these aggregations will probably consume SGE immidiatelly) 240 * 2. Rest of BRB blocks divided by 2 (block will consume new SGE only 241 * after placement on BD for new TPA aggregation) 242 * Takes into account RX_SGE_NEXT_PAGE_DESC_CNT "next" elements on each page 243 */ 244 #define NUM_SGE_REQ(sc) \ 245 (MAX_AGG_QS(sc) + (BRB_SIZE(sc) - MAX_AGG_QS(sc)) / 2) 246 #define NUM_SGE_PG_REQ(sc) \ 247 ((NUM_SGE_REQ(sc) + RX_SGE_USABLE_PER_PAGE - 1) / RX_SGE_USABLE_PER_PAGE) 248 #define SGE_TH_LO(sc) \ 249 (NUM_SGE_REQ(sc) + NUM_SGE_PG_REQ(sc) * RX_SGE_NEXT_PAGE_DESC_CNT) 250 #define SGE_TH_HI(sc) \ 251 (SGE_TH_LO(sc) + DROPLESS_FC_HEADROOM) 252 253 #define PAGES_PER_SGE_SHIFT 0 254 #define PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT) 255 #define SGE_PAGE_SIZE BCM_PAGE_SIZE 256 #define SGE_PAGE_SHIFT BCM_PAGE_SHIFT 257 #define SGE_PAGE_ALIGN(addr) BCM_PAGE_ALIGN(addr) 258 #define SGE_PAGES (SGE_PAGE_SIZE * PAGES_PER_SGE) 259 #define TPA_AGG_SIZE min((8 * SGE_PAGES), 0xffff) 260 261 /*****************/ 262 /* TX BD defines */ 263 /*****************/ 264 265 #define TX_BD_NUM_PAGES 16 /* must be a power of 2 */ 266 #define TX_BD_TOTAL_PER_PAGE (BCM_PAGE_SIZE / sizeof(union eth_tx_bd_types)) 267 #define TX_BD_USABLE_PER_PAGE (TX_BD_TOTAL_PER_PAGE - 1) 268 #define TX_BD_TOTAL (TX_BD_TOTAL_PER_PAGE * TX_BD_NUM_PAGES) 269 #define TX_BD_USABLE (TX_BD_USABLE_PER_PAGE * TX_BD_NUM_PAGES) 270 #define TX_BD_MAX (TX_BD_TOTAL - 1) 271 272 #define TX_BD_NEXT(x) \ 273 ((((x) & TX_BD_USABLE_PER_PAGE) == (TX_BD_USABLE_PER_PAGE - 1)) ? \ 274 ((x) + 2) : ((x) + 1)) 275 #define TX_BD(x) ((x) & TX_BD_MAX) 276 #define TX_BD_PAGE(x) (((x) & ~TX_BD_USABLE_PER_PAGE) >> 8) 277 #define TX_BD_IDX(x) ((x) & TX_BD_USABLE_PER_PAGE) 278 279 /* 280 * Trigger pending transmits when the number of available BDs is greater 281 * than 1/8 of the total number of usable BDs. 282 */ 283 #define BXE_TX_CLEANUP_THRESHOLD (TX_BD_USABLE / 8) 284 #define BXE_TX_TIMEOUT 5 285 286 /*****************/ 287 /* RX BD defines */ 288 /*****************/ 289 290 #define RX_BD_NUM_PAGES 8 /* power of 2 */ 291 #define RX_BD_TOTAL_PER_PAGE (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd)) 292 #define RX_BD_NEXT_PAGE_DESC_CNT 2 293 #define RX_BD_USABLE_PER_PAGE (RX_BD_TOTAL_PER_PAGE - RX_BD_NEXT_PAGE_DESC_CNT) 294 #define RX_BD_PER_PAGE_MASK (RX_BD_TOTAL_PER_PAGE - 1) 295 #define RX_BD_TOTAL (RX_BD_TOTAL_PER_PAGE * RX_BD_NUM_PAGES) 296 #define RX_BD_USABLE (RX_BD_USABLE_PER_PAGE * RX_BD_NUM_PAGES) 297 #define RX_BD_MAX (RX_BD_TOTAL - 1) 298 299 #define RX_BD_NEXT(x) \ 300 ((((x) & RX_BD_PER_PAGE_MASK) == (RX_BD_USABLE_PER_PAGE - 1)) ? \ 301 ((x) + 3) : ((x) + 1)) 302 #define RX_BD(x) ((x) & RX_BD_MAX) 303 #define RX_BD_PAGE(x) (((x) & ~RX_BD_PER_PAGE_MASK) >> 9) 304 #define RX_BD_IDX(x) ((x) & RX_BD_PER_PAGE_MASK) 305 306 /* 307 * dropless fc calculations for BDs 308 * Number of BDs should be as number of buffers in BRB: 309 * Low threshold takes into account RX_BD_NEXT_PAGE_DESC_CNT 310 * "next" elements on each page 311 */ 312 #define NUM_BD_REQ(sc) \ 313 BRB_SIZE(sc) 314 #define NUM_BD_PG_REQ(sc) \ 315 ((NUM_BD_REQ(sc) + RX_BD_USABLE_PER_PAGE - 1) / RX_BD_USABLE_PER_PAGE) 316 #define BD_TH_LO(sc) \ 317 (NUM_BD_REQ(sc) + \ 318 NUM_BD_PG_REQ(sc) * RX_BD_NEXT_PAGE_DESC_CNT + \ 319 FW_DROP_LEVEL(sc)) 320 #define BD_TH_HI(sc) \ 321 (BD_TH_LO(sc) + DROPLESS_FC_HEADROOM) 322 #define MIN_RX_AVAIL(sc) \ 323 ((sc)->dropless_fc ? BD_TH_HI(sc) + 128 : 128) 324 #define MIN_RX_SIZE_TPA_HW(sc) \ 325 (CHIP_IS_E1(sc) ? ETH_MIN_RX_CQES_WITH_TPA_E1 : \ 326 ETH_MIN_RX_CQES_WITH_TPA_E1H_E2) 327 #define MIN_RX_SIZE_NONTPA_HW ETH_MIN_RX_CQES_WITHOUT_TPA 328 #define MIN_RX_SIZE_TPA(sc) \ 329 (max(MIN_RX_SIZE_TPA_HW(sc), MIN_RX_AVAIL(sc))) 330 #define MIN_RX_SIZE_NONTPA(sc) \ 331 (max(MIN_RX_SIZE_NONTPA_HW, MIN_RX_AVAIL(sc))) 332 333 /***************/ 334 /* RCQ defines */ 335 /***************/ 336 337 /* 338 * As long as CQE is X times bigger than BD entry we have to allocate X times 339 * more pages for CQ ring in order to keep it balanced with BD ring 340 */ 341 #define CQE_BD_REL (sizeof(union eth_rx_cqe) / \ 342 sizeof(struct eth_rx_bd)) 343 #define RCQ_NUM_PAGES (RX_BD_NUM_PAGES * CQE_BD_REL) /* power of 2 */ 344 #define RCQ_TOTAL_PER_PAGE (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe)) 345 #define RCQ_NEXT_PAGE_DESC_CNT 1 346 #define RCQ_USABLE_PER_PAGE (RCQ_TOTAL_PER_PAGE - RCQ_NEXT_PAGE_DESC_CNT) 347 #define RCQ_TOTAL (RCQ_TOTAL_PER_PAGE * RCQ_NUM_PAGES) 348 #define RCQ_USABLE (RCQ_USABLE_PER_PAGE * RCQ_NUM_PAGES) 349 #define RCQ_MAX (RCQ_TOTAL - 1) 350 351 #define RCQ_NEXT(x) \ 352 ((((x) & RCQ_USABLE_PER_PAGE) == (RCQ_USABLE_PER_PAGE - 1)) ? \ 353 ((x) + 1 + RCQ_NEXT_PAGE_DESC_CNT) : ((x) + 1)) 354 #define RCQ(x) ((x) & RCQ_MAX) 355 #define RCQ_PAGE(x) (((x) & ~RCQ_USABLE_PER_PAGE) >> 7) 356 #define RCQ_IDX(x) ((x) & RCQ_USABLE_PER_PAGE) 357 358 /* 359 * dropless fc calculations for RCQs 360 * Number of RCQs should be as number of buffers in BRB: 361 * Low threshold takes into account RCQ_NEXT_PAGE_DESC_CNT 362 * "next" elements on each page 363 */ 364 #define NUM_RCQ_REQ(sc) \ 365 BRB_SIZE(sc) 366 #define NUM_RCQ_PG_REQ(sc) \ 367 ((NUM_RCQ_REQ(sc) + RCQ_USABLE_PER_PAGE - 1) / RCQ_USABLE_PER_PAGE) 368 #define RCQ_TH_LO(sc) \ 369 (NUM_RCQ_REQ(sc) + \ 370 NUM_RCQ_PG_REQ(sc) * RCQ_NEXT_PAGE_DESC_CNT + \ 371 FW_DROP_LEVEL(sc)) 372 #define RCQ_TH_HI(sc) \ 373 (RCQ_TH_LO(sc) + DROPLESS_FC_HEADROOM) 374 375 /* This is needed for determening of last_max */ 376 #define SUB_S16(a, b) (int16_t)((int16_t)(a) - (int16_t)(b)) 377 378 #define __SGE_MASK_SET_BIT(el, bit) \ 379 do { \ 380 (el) = ((el) | ((uint64_t)0x1 << (bit))); \ 381 } while (0) 382 383 #define __SGE_MASK_CLEAR_BIT(el, bit) \ 384 do { \ 385 (el) = ((el) & (~((uint64_t)0x1 << (bit)))); \ 386 } while (0) 387 388 #define SGE_MASK_SET_BIT(fp, idx) \ 389 __SGE_MASK_SET_BIT((fp)->sge_mask[(idx) >> RX_SGE_MASK_ELEM_SHIFT], \ 390 ((idx) & RX_SGE_MASK_ELEM_MASK)) 391 392 #define SGE_MASK_CLEAR_BIT(fp, idx) \ 393 __SGE_MASK_CLEAR_BIT((fp)->sge_mask[(idx) >> RX_SGE_MASK_ELEM_SHIFT], \ 394 ((idx) & RX_SGE_MASK_ELEM_MASK)) 395 396 /* Load / Unload modes */ 397 #define LOAD_NORMAL 0 398 #define LOAD_OPEN 1 399 #define LOAD_DIAG 2 400 #define LOAD_LOOPBACK_EXT 3 401 #define UNLOAD_NORMAL 0 402 #define UNLOAD_CLOSE 1 403 #define UNLOAD_RECOVERY 2 404 405 /* Some constants... */ 406 //#define MAX_PATH_NUM 2 407 //#define E2_MAX_NUM_OF_VFS 64 408 //#define E1H_FUNC_MAX 8 409 //#define E2_FUNC_MAX 4 /* per path */ 410 #define MAX_VNIC_NUM 4 411 #define MAX_FUNC_NUM 8 /* common to all chips */ 412 //#define MAX_NDSB HC_SB_MAX_SB_E2 /* max non-default status block */ 413 #define MAX_RSS_CHAINS 16 /* a constant for HW limit */ 414 #define MAX_MSI_VECTOR 8 /* a constant for HW limit */ 415 416 #define ILT_NUM_PAGE_ENTRIES 3072 417 /* 418 * 57710/11 we use whole table since we have 8 functions. 419 * 57712 we have only 4 functions, but use same size per func, so only half 420 * of the table is used. 421 */ 422 #define ILT_PER_FUNC (ILT_NUM_PAGE_ENTRIES / 8) 423 #define FUNC_ILT_BASE(func) (func * ILT_PER_FUNC) 424 /* 425 * the phys address is shifted right 12 bits and has an added 426 * 1=valid bit added to the 53rd bit 427 * then since this is a wide register(TM) 428 * we split it into two 32 bit writes 429 */ 430 #define ONCHIP_ADDR1(x) ((uint32_t)(((uint64_t)x >> 12) & 0xFFFFFFFF)) 431 #define ONCHIP_ADDR2(x) ((uint32_t)((1 << 20) | ((uint64_t)x >> 44))) 432 433 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */ 434 #define ETH_HLEN 14 435 #define ETH_OVERHEAD (ETH_HLEN + 8 + 8) 436 #define ETH_MIN_PACKET_SIZE 60 437 #define ETH_MAX_PACKET_SIZE ETHERMTU /* 1500 */ 438 #define ETH_MAX_JUMBO_PACKET_SIZE 9600 439 /* TCP with Timestamp Option (32) + IPv6 (40) */ 440 #define ETH_MAX_TPA_HEADER_SIZE 72 441 442 /* max supported alignment is 256 (8 shift) */ 443 //#define BXE_RX_ALIGN_SHIFT ((CACHE_LINE_SHIFT < 8) ? CACHE_LINE_SHIFT : 8) 444 #define BXE_RX_ALIGN_SHIFT 8 445 /* FW uses 2 cache lines alignment for start packet and size */ 446 #define BXE_FW_RX_ALIGN_START (1 << BXE_RX_ALIGN_SHIFT) 447 #define BXE_FW_RX_ALIGN_END (1 << BXE_RX_ALIGN_SHIFT) 448 449 #define BXE_PXP_DRAM_ALIGN (BXE_RX_ALIGN_SHIFT - 5) /* XXX ??? */ 450 #define BXE_SET_ERROR_BIT(sc, error) \ 451 { \ 452 (sc)->error_status |= (error); \ 453 } 454 455 struct bxe_bar { 456 struct resource *resource; 457 int rid; 458 bus_space_tag_t tag; 459 bus_space_handle_t handle; 460 vm_offset_t kva; 461 }; 462 463 struct bxe_intr { 464 struct resource *resource; 465 int rid; 466 void *tag; 467 }; 468 469 /* Used to manage DMA allocations. */ 470 struct bxe_dma { 471 struct bxe_softc *sc; 472 bus_addr_t paddr; 473 void *vaddr; 474 bus_dma_tag_t tag; 475 bus_dmamap_t map; 476 bus_dma_segment_t seg; 477 bus_size_t size; 478 int nseg; 479 char msg[32]; 480 }; 481 482 /* attn group wiring */ 483 #define MAX_DYNAMIC_ATTN_GRPS 8 484 485 struct attn_route { 486 uint32_t sig[5]; 487 }; 488 489 struct iro { 490 uint32_t base; 491 uint16_t m1; 492 uint16_t m2; 493 uint16_t m3; 494 uint16_t size; 495 }; 496 497 union bxe_host_hc_status_block { 498 /* pointer to fp status block e2 */ 499 struct host_hc_status_block_e2 *e2_sb; 500 /* pointer to fp status block e1x */ 501 struct host_hc_status_block_e1x *e1x_sb; 502 }; 503 504 union bxe_db_prod { 505 struct doorbell_set_prod data; 506 uint32_t raw; 507 }; 508 509 struct bxe_sw_tx_bd { 510 struct mbuf *m; 511 bus_dmamap_t m_map; 512 uint16_t first_bd; 513 uint8_t flags; 514 /* set on the first BD descriptor when there is a split BD */ 515 #define BXE_TSO_SPLIT_BD (1 << 0) 516 }; 517 518 struct bxe_sw_rx_bd { 519 struct mbuf *m; 520 bus_dmamap_t m_map; 521 }; 522 523 struct bxe_sw_tpa_info { 524 struct bxe_sw_rx_bd bd; 525 bus_dma_segment_t seg; 526 uint8_t state; 527 #define BXE_TPA_STATE_START 1 528 #define BXE_TPA_STATE_STOP 2 529 uint8_t placement_offset; 530 uint16_t parsing_flags; 531 uint16_t vlan_tag; 532 uint16_t len_on_bd; 533 }; 534 535 /* 536 * This is the HSI fastpath data structure. There can be up to MAX_RSS_CHAIN 537 * instances of the fastpath structure when using multiple queues. 538 */ 539 struct bxe_fastpath { 540 /* pointer back to parent structure */ 541 struct bxe_softc *sc; 542 543 struct mtx tx_mtx; 544 char tx_mtx_name[32]; 545 struct mtx rx_mtx; 546 char rx_mtx_name[32]; 547 548 #define BXE_FP_TX_LOCK(fp) mtx_lock(&fp->tx_mtx) 549 #define BXE_FP_TX_UNLOCK(fp) mtx_unlock(&fp->tx_mtx) 550 #define BXE_FP_TX_LOCK_ASSERT(fp) mtx_assert(&fp->tx_mtx, MA_OWNED) 551 #define BXE_FP_TX_TRYLOCK(fp) mtx_trylock(&fp->tx_mtx) 552 553 #define BXE_FP_RX_LOCK(fp) mtx_lock(&fp->rx_mtx) 554 #define BXE_FP_RX_UNLOCK(fp) mtx_unlock(&fp->rx_mtx) 555 #define BXE_FP_RX_LOCK_ASSERT(fp) mtx_assert(&fp->rx_mtx, MA_OWNED) 556 557 /* status block */ 558 struct bxe_dma sb_dma; 559 union bxe_host_hc_status_block status_block; 560 561 /* transmit chain (tx bds) */ 562 struct bxe_dma tx_dma; 563 union eth_tx_bd_types *tx_chain; 564 565 /* receive chain (rx bds) */ 566 struct bxe_dma rx_dma; 567 struct eth_rx_bd *rx_chain; 568 569 /* receive completion queue chain (rcq bds) */ 570 struct bxe_dma rcq_dma; 571 union eth_rx_cqe *rcq_chain; 572 573 /* receive scatter/gather entry chain (for TPA) */ 574 struct bxe_dma rx_sge_dma; 575 struct eth_rx_sge *rx_sge_chain; 576 577 /* tx mbufs */ 578 bus_dma_tag_t tx_mbuf_tag; 579 struct bxe_sw_tx_bd tx_mbuf_chain[TX_BD_TOTAL]; 580 581 /* rx mbufs */ 582 bus_dma_tag_t rx_mbuf_tag; 583 struct bxe_sw_rx_bd rx_mbuf_chain[RX_BD_TOTAL]; 584 bus_dmamap_t rx_mbuf_spare_map; 585 586 /* rx sge mbufs */ 587 bus_dma_tag_t rx_sge_mbuf_tag; 588 struct bxe_sw_rx_bd rx_sge_mbuf_chain[RX_SGE_TOTAL]; 589 bus_dmamap_t rx_sge_mbuf_spare_map; 590 591 /* rx tpa mbufs (use the larger size for TPA queue length) */ 592 int tpa_enable; /* disabled per fastpath upon error */ 593 struct bxe_sw_tpa_info rx_tpa_info[ETH_MAX_AGGREGATION_QUEUES_E1H_E2]; 594 bus_dmamap_t rx_tpa_info_mbuf_spare_map; 595 uint64_t rx_tpa_queue_used; 596 597 uint16_t *sb_index_values; 598 uint16_t *sb_running_index; 599 uint32_t ustorm_rx_prods_offset; 600 601 uint8_t igu_sb_id; /* status block number in HW */ 602 uint8_t fw_sb_id; /* status block number in FW */ 603 604 uint32_t rx_buf_size; 605 int mbuf_alloc_size; 606 607 int state; 608 #define BXE_FP_STATE_CLOSED 0x01 609 #define BXE_FP_STATE_IRQ 0x02 610 #define BXE_FP_STATE_OPENING 0x04 611 #define BXE_FP_STATE_OPEN 0x08 612 #define BXE_FP_STATE_HALTING 0x10 613 #define BXE_FP_STATE_HALTED 0x20 614 615 /* reference back to this fastpath queue number */ 616 uint8_t index; /* this is also the 'cid' */ 617 #define FP_IDX(fp) (fp->index) 618 619 /* interrupt taskqueue (fast) */ 620 struct task tq_task; 621 struct taskqueue *tq; 622 char tq_name[32]; 623 624 struct task tx_task; 625 struct timeout_task tx_timeout_task; 626 627 /* ethernet client ID (each fastpath set of RX/TX/CQE is a client) */ 628 uint8_t cl_id; 629 #define FP_CL_ID(fp) (fp->cl_id) 630 uint8_t cl_qzone_id; 631 632 uint16_t fp_hc_idx; 633 634 /* driver copy of the receive buffer descriptor prod/cons indices */ 635 uint16_t rx_bd_prod; 636 uint16_t rx_bd_cons; 637 638 /* driver copy of the receive completion queue prod/cons indices */ 639 uint16_t rx_cq_prod; 640 uint16_t rx_cq_cons; 641 642 union bxe_db_prod tx_db; 643 644 /* Transmit packet producer index (used in eth_tx_bd). */ 645 uint16_t tx_pkt_prod; 646 uint16_t tx_pkt_cons; 647 648 /* Transmit buffer descriptor producer index. */ 649 uint16_t tx_bd_prod; 650 uint16_t tx_bd_cons; 651 652 uint64_t sge_mask[RX_SGE_MASK_LEN]; 653 uint16_t rx_sge_prod; 654 655 struct tstorm_per_queue_stats old_tclient; 656 struct ustorm_per_queue_stats old_uclient; 657 struct xstorm_per_queue_stats old_xclient; 658 struct bxe_eth_q_stats eth_q_stats; 659 struct bxe_eth_q_stats_old eth_q_stats_old; 660 661 /* Pointer to the receive consumer in the status block */ 662 uint16_t *rx_cq_cons_sb; 663 664 /* Pointer to the transmit consumer in the status block */ 665 uint16_t *tx_cons_sb; 666 667 /* transmit timeout until chip reset */ 668 int watchdog_timer; 669 670 /* Free/used buffer descriptor counters. */ 671 //uint16_t used_tx_bd; 672 673 /* Last maximal completed SGE */ 674 uint16_t last_max_sge; 675 676 //uint16_t rx_sge_free_idx; 677 678 //uint8_t segs; 679 680 #define BXE_BR_SIZE 4096 681 struct buf_ring *tx_br; 682 }; /* struct bxe_fastpath */ 683 684 /* sriov XXX */ 685 #define BXE_MAX_NUM_OF_VFS 64 686 #define BXE_VF_CID_WND 0 687 #define BXE_CIDS_PER_VF (1 << BXE_VF_CID_WND) 688 #define BXE_CLIENTS_PER_VF 1 689 #define BXE_FIRST_VF_CID 256 690 #define BXE_VF_CIDS (BXE_MAX_NUM_OF_VFS * BXE_CIDS_PER_VF) 691 #define BXE_VF_ID_INVALID 0xFF 692 #define IS_SRIOV(sc) 0 693 694 #define GET_NUM_VFS_PER_PATH(sc) 0 695 #define GET_NUM_VFS_PER_PF(sc) 0 696 697 /* maximum number of fast-path interrupt contexts */ 698 #define FP_SB_MAX_E1x 16 699 #define FP_SB_MAX_E2 HC_SB_MAX_SB_E2 700 701 union cdu_context { 702 struct eth_context eth; 703 char pad[1024]; 704 }; 705 706 /* CDU host DB constants */ 707 #define CDU_ILT_PAGE_SZ_HW 2 708 #define CDU_ILT_PAGE_SZ (8192 << CDU_ILT_PAGE_SZ_HW) /* 32K */ 709 #define ILT_PAGE_CIDS (CDU_ILT_PAGE_SZ / sizeof(union cdu_context)) 710 711 #define CNIC_ISCSI_CID_MAX 256 712 #define CNIC_FCOE_CID_MAX 2048 713 #define CNIC_CID_MAX (CNIC_ISCSI_CID_MAX + CNIC_FCOE_CID_MAX) 714 #define CNIC_ILT_LINES DIV_ROUND_UP(CNIC_CID_MAX, ILT_PAGE_CIDS) 715 716 #define QM_ILT_PAGE_SZ_HW 0 717 #define QM_ILT_PAGE_SZ (4096 << QM_ILT_PAGE_SZ_HW) /* 4K */ 718 #define QM_CID_ROUND 1024 719 720 /* TM (timers) host DB constants */ 721 #define TM_ILT_PAGE_SZ_HW 0 722 #define TM_ILT_PAGE_SZ (4096 << TM_ILT_PAGE_SZ_HW) /* 4K */ 723 /*#define TM_CONN_NUM (CNIC_STARTING_CID+CNIC_ISCSI_CXT_MAX) */ 724 #define TM_CONN_NUM 1024 725 #define TM_ILT_SZ (8 * TM_CONN_NUM) 726 #define TM_ILT_LINES DIV_ROUND_UP(TM_ILT_SZ, TM_ILT_PAGE_SZ) 727 728 /* SRC (Searcher) host DB constants */ 729 #define SRC_ILT_PAGE_SZ_HW 0 730 #define SRC_ILT_PAGE_SZ (4096 << SRC_ILT_PAGE_SZ_HW) /* 4K */ 731 #define SRC_HASH_BITS 10 732 #define SRC_CONN_NUM (1 << SRC_HASH_BITS) /* 1024 */ 733 #define SRC_ILT_SZ (sizeof(struct src_ent) * SRC_CONN_NUM) 734 #define SRC_T2_SZ SRC_ILT_SZ 735 #define SRC_ILT_LINES DIV_ROUND_UP(SRC_ILT_SZ, SRC_ILT_PAGE_SZ) 736 737 struct hw_context { 738 struct bxe_dma vcxt_dma; 739 union cdu_context *vcxt; 740 //bus_addr_t cxt_mapping; 741 size_t size; 742 }; 743 744 #define SM_RX_ID 0 745 #define SM_TX_ID 1 746 747 /* defines for multiple tx priority indices */ 748 #define FIRST_TX_ONLY_COS_INDEX 1 749 #define FIRST_TX_COS_INDEX 0 750 751 #define CID_TO_FP(cid, sc) ((cid) % BXE_NUM_NON_CNIC_QUEUES(sc)) 752 753 #define HC_INDEX_ETH_RX_CQ_CONS 1 754 #define HC_INDEX_OOO_TX_CQ_CONS 4 755 #define HC_INDEX_ETH_TX_CQ_CONS_COS0 5 756 #define HC_INDEX_ETH_TX_CQ_CONS_COS1 6 757 #define HC_INDEX_ETH_TX_CQ_CONS_COS2 7 758 #define HC_INDEX_ETH_FIRST_TX_CQ_CONS HC_INDEX_ETH_TX_CQ_CONS_COS0 759 760 /* congestion management fairness mode */ 761 #define CMNG_FNS_NONE 0 762 #define CMNG_FNS_MINMAX 1 763 764 /* CMNG constants, as derived from system spec calculations */ 765 /* default MIN rate in case VNIC min rate is configured to zero - 100Mbps */ 766 #define DEF_MIN_RATE 100 767 /* resolution of the rate shaping timer - 400 usec */ 768 #define RS_PERIODIC_TIMEOUT_USEC 400 769 /* number of bytes in single QM arbitration cycle - 770 * coefficient for calculating the fairness timer */ 771 #define QM_ARB_BYTES 160000 772 /* resolution of Min algorithm 1:100 */ 773 #define MIN_RES 100 774 /* how many bytes above threshold for the minimal credit of Min algorithm*/ 775 #define MIN_ABOVE_THRESH 32768 776 /* fairness algorithm integration time coefficient - 777 * for calculating the actual Tfair */ 778 #define T_FAIR_COEF ((MIN_ABOVE_THRESH + QM_ARB_BYTES) * 8 * MIN_RES) 779 /* memory of fairness algorithm - 2 cycles */ 780 #define FAIR_MEM 2 781 782 #define HC_SEG_ACCESS_DEF 0 /* Driver decision 0-3 */ 783 #define HC_SEG_ACCESS_ATTN 4 784 #define HC_SEG_ACCESS_NORM 0 /* Driver decision 0-1 */ 785 786 /* 787 * The total number of L2 queues, MSIX vectors and HW contexts (CIDs) is 788 * control by the number of fast-path status blocks supported by the 789 * device (HW/FW). Each fast-path status block (FP-SB) aka non-default 790 * status block represents an independent interrupts context that can 791 * serve a regular L2 networking queue. However special L2 queues such 792 * as the FCoE queue do not require a FP-SB and other components like 793 * the CNIC may consume FP-SB reducing the number of possible L2 queues 794 * 795 * If the maximum number of FP-SB available is X then: 796 * a. If CNIC is supported it consumes 1 FP-SB thus the max number of 797 * regular L2 queues is Y=X-1 798 * b. in MF mode the actual number of L2 queues is Y= (X-1/MF_factor) 799 * c. If the FCoE L2 queue is supported the actual number of L2 queues 800 * is Y+1 801 * d. The number of irqs (MSIX vectors) is either Y+1 (one extra for 802 * slow-path interrupts) or Y+2 if CNIC is supported (one additional 803 * FP interrupt context for the CNIC). 804 * e. The number of HW context (CID count) is always X or X+1 if FCoE 805 * L2 queue is supported. the cid for the FCoE L2 queue is always X. 806 * 807 * So this is quite simple for now as no ULPs are supported yet. :-) 808 */ 809 #define BXE_NUM_QUEUES(sc) ((sc)->num_queues) 810 #define BXE_NUM_ETH_QUEUES(sc) BXE_NUM_QUEUES(sc) 811 #define BXE_NUM_NON_CNIC_QUEUES(sc) BXE_NUM_QUEUES(sc) 812 #define BXE_NUM_RX_QUEUES(sc) BXE_NUM_QUEUES(sc) 813 814 #define FOR_EACH_QUEUE(sc, var) \ 815 for ((var) = 0; (var) < BXE_NUM_QUEUES(sc); (var)++) 816 817 #define FOR_EACH_NONDEFAULT_QUEUE(sc, var) \ 818 for ((var) = 1; (var) < BXE_NUM_QUEUES(sc); (var)++) 819 820 #define FOR_EACH_ETH_QUEUE(sc, var) \ 821 for ((var) = 0; (var) < BXE_NUM_ETH_QUEUES(sc); (var)++) 822 823 #define FOR_EACH_NONDEFAULT_ETH_QUEUE(sc, var) \ 824 for ((var) = 1; (var) < BXE_NUM_ETH_QUEUES(sc); (var)++) 825 826 #define FOR_EACH_COS_IN_TX_QUEUE(sc, var) \ 827 for ((var) = 0; (var) < (sc)->max_cos; (var)++) 828 829 #define FOR_EACH_CNIC_QUEUE(sc, var) \ 830 for ((var) = BXE_NUM_ETH_QUEUES(sc); \ 831 (var) < BXE_NUM_QUEUES(sc); \ 832 (var)++) 833 834 enum { 835 OOO_IDX_OFFSET, 836 FCOE_IDX_OFFSET, 837 FWD_IDX_OFFSET, 838 }; 839 840 #define FCOE_IDX(sc) (BXE_NUM_NON_CNIC_QUEUES(sc) + FCOE_IDX_OFFSET) 841 #define bxe_fcoe_fp(sc) (&sc->fp[FCOE_IDX(sc)]) 842 #define bxe_fcoe(sc, var) (bxe_fcoe_fp(sc)->var) 843 #define bxe_fcoe_inner_sp_obj(sc) (&sc->sp_objs[FCOE_IDX(sc)]) 844 #define bxe_fcoe_sp_obj(sc, var) (bxe_fcoe_inner_sp_obj(sc)->var) 845 #define bxe_fcoe_tx(sc, var) (bxe_fcoe_fp(sc)->txdata_ptr[FIRST_TX_COS_INDEX]->var) 846 847 #define OOO_IDX(sc) (BXE_NUM_NON_CNIC_QUEUES(sc) + OOO_IDX_OFFSET) 848 #define bxe_ooo_fp(sc) (&sc->fp[OOO_IDX(sc)]) 849 #define bxe_ooo(sc, var) (bxe_ooo_fp(sc)->var) 850 #define bxe_ooo_inner_sp_obj(sc) (&sc->sp_objs[OOO_IDX(sc)]) 851 #define bxe_ooo_sp_obj(sc, var) (bxe_ooo_inner_sp_obj(sc)->var) 852 853 #define FWD_IDX(sc) (BXE_NUM_NON_CNIC_QUEUES(sc) + FWD_IDX_OFFSET) 854 #define bxe_fwd_fp(sc) (&sc->fp[FWD_IDX(sc)]) 855 #define bxe_fwd(sc, var) (bxe_fwd_fp(sc)->var) 856 #define bxe_fwd_inner_sp_obj(sc) (&sc->sp_objs[FWD_IDX(sc)]) 857 #define bxe_fwd_sp_obj(sc, var) (bxe_fwd_inner_sp_obj(sc)->var) 858 #define bxe_fwd_txdata(fp) (fp->txdata_ptr[FIRST_TX_COS_INDEX]) 859 860 #define IS_ETH_FP(fp) ((fp)->index < BXE_NUM_ETH_QUEUES((fp)->sc)) 861 #define IS_FCOE_FP(fp) ((fp)->index == FCOE_IDX((fp)->sc)) 862 #define IS_FCOE_IDX(idx) ((idx) == FCOE_IDX(sc)) 863 #define IS_FWD_FP(fp) ((fp)->index == FWD_IDX((fp)->sc)) 864 #define IS_FWD_IDX(idx) ((idx) == FWD_IDX(sc)) 865 #define IS_OOO_FP(fp) ((fp)->index == OOO_IDX((fp)->sc)) 866 #define IS_OOO_IDX(idx) ((idx) == OOO_IDX(sc)) 867 868 enum { 869 BXE_PORT_QUERY_IDX, 870 BXE_PF_QUERY_IDX, 871 BXE_FCOE_QUERY_IDX, 872 BXE_FIRST_QUEUE_QUERY_IDX, 873 }; 874 875 struct bxe_fw_stats_req { 876 struct stats_query_header hdr; 877 struct stats_query_entry query[FP_SB_MAX_E1x + 878 BXE_FIRST_QUEUE_QUERY_IDX]; 879 }; 880 881 struct bxe_fw_stats_data { 882 struct stats_counter storm_counters; 883 struct per_port_stats port; 884 struct per_pf_stats pf; 885 //struct fcoe_statistics_params fcoe; 886 struct per_queue_stats queue_stats[1]; 887 }; 888 889 /* IGU MSIX STATISTICS on 57712: 64 for VFs; 4 for PFs; 4 for Attentions */ 890 #define BXE_IGU_STAS_MSG_VF_CNT 64 891 #define BXE_IGU_STAS_MSG_PF_CNT 4 892 893 #define MAX_DMAE_C 8 894 895 /* 896 * For the main interface up/down code paths, a not-so-fine-grained CORE 897 * mutex lock is used. Inside this code are various calls to kernel routines 898 * that can cause a sleep to occur. Namely memory allocations and taskqueue 899 * handling. If using an MTX lock we are *not* allowed to sleep but we can 900 * with an SX lock. This define forces the CORE lock to use and SX lock. 901 * Undefine this and an MTX lock will be used instead. Note that the IOCTL 902 * path can cause problems since it's called by a non-sleepable thread. To 903 * alleviate a potential sleep, any IOCTL processing that results in the 904 * chip/interface being started/stopped/reinitialized, the actual work is 905 * offloaded to a taskqueue. 906 */ 907 #define BXE_CORE_LOCK_SX 908 909 /* 910 * This is the slowpath data structure. It is mapped into non-paged memory 911 * so that the hardware can access it's contents directly and must be page 912 * aligned. 913 */ 914 struct bxe_slowpath { 915 916 /* used by the DMAE command executer */ 917 struct dmae_cmd dmae[MAX_DMAE_C]; 918 919 /* statistics completion */ 920 uint32_t stats_comp; 921 922 /* firmware defined statistics blocks */ 923 union mac_stats mac_stats; 924 struct nig_stats nig_stats; 925 struct host_port_stats port_stats; 926 struct host_func_stats func_stats; 927 //struct host_func_stats func_stats_base; 928 929 /* DMAE completion value and data source/sink */ 930 uint32_t wb_comp; 931 uint32_t wb_data[4]; 932 933 union { 934 struct mac_configuration_cmd e1x; 935 struct eth_classify_rules_ramrod_data e2; 936 } mac_rdata; 937 938 union { 939 struct tstorm_eth_mac_filter_config e1x; 940 struct eth_filter_rules_ramrod_data e2; 941 } rx_mode_rdata; 942 943 struct eth_rss_update_ramrod_data rss_rdata; 944 945 union { 946 struct mac_configuration_cmd e1; 947 struct eth_multicast_rules_ramrod_data e2; 948 } mcast_rdata; 949 950 union { 951 struct function_start_data func_start; 952 struct flow_control_configuration pfc_config; /* for DCBX ramrod */ 953 } func_rdata; 954 955 /* Queue State related ramrods */ 956 union { 957 struct client_init_ramrod_data init_data; 958 struct client_update_ramrod_data update_data; 959 } q_rdata; 960 961 /* 962 * AFEX ramrod can not be a part of func_rdata union because these 963 * events might arrive in parallel to other events from func_rdata. 964 * If they were defined in the same union the data can get corrupted. 965 */ 966 struct afex_vif_list_ramrod_data func_afex_rdata; 967 968 union drv_info_to_mcp drv_info_to_mcp; 969 }; /* struct bxe_slowpath */ 970 971 /* 972 * Port specifc data structure. 973 */ 974 struct bxe_port { 975 /* 976 * Port Management Function (for 57711E only). 977 * When this field is set the driver instance is 978 * responsible for managing port specifc 979 * configurations such as handling link attentions. 980 */ 981 uint32_t pmf; 982 983 /* Ethernet maximum transmission unit. */ 984 uint16_t ether_mtu; 985 986 uint32_t link_config[ELINK_LINK_CONFIG_SIZE]; 987 988 uint32_t ext_phy_config; 989 990 /* Port feature config.*/ 991 uint32_t config; 992 993 /* Defines the features supported by the PHY. */ 994 uint32_t supported[ELINK_LINK_CONFIG_SIZE]; 995 996 /* Defines the features advertised by the PHY. */ 997 uint32_t advertising[ELINK_LINK_CONFIG_SIZE]; 998 #define ADVERTISED_10baseT_Half (1 << 1) 999 #define ADVERTISED_10baseT_Full (1 << 2) 1000 #define ADVERTISED_100baseT_Half (1 << 3) 1001 #define ADVERTISED_100baseT_Full (1 << 4) 1002 #define ADVERTISED_1000baseT_Half (1 << 5) 1003 #define ADVERTISED_1000baseT_Full (1 << 6) 1004 #define ADVERTISED_TP (1 << 7) 1005 #define ADVERTISED_FIBRE (1 << 8) 1006 #define ADVERTISED_Autoneg (1 << 9) 1007 #define ADVERTISED_Asym_Pause (1 << 10) 1008 #define ADVERTISED_Pause (1 << 11) 1009 #define ADVERTISED_2500baseX_Full (1 << 15) 1010 #define ADVERTISED_10000baseT_Full (1 << 16) 1011 1012 uint32_t phy_addr; 1013 1014 /* Used to synchronize phy accesses. */ 1015 struct mtx phy_mtx; 1016 char phy_mtx_name[32]; 1017 1018 #define BXE_PHY_LOCK(sc) mtx_lock(&sc->port.phy_mtx) 1019 #define BXE_PHY_UNLOCK(sc) mtx_unlock(&sc->port.phy_mtx) 1020 #define BXE_PHY_LOCK_ASSERT(sc) mtx_assert(&sc->port.phy_mtx, MA_OWNED) 1021 1022 /* 1023 * MCP scratchpad address for port specific statistics. 1024 * The device is responsible for writing statistcss 1025 * back to the MCP for use with management firmware such 1026 * as UMP/NC-SI. 1027 */ 1028 uint32_t port_stx; 1029 1030 struct nig_stats old_nig_stats; 1031 }; /* struct bxe_port */ 1032 1033 struct bxe_mf_info { 1034 uint32_t mf_config[E1HVN_MAX]; 1035 1036 uint32_t vnics_per_port; /* 1, 2 or 4 */ 1037 uint32_t multi_vnics_mode; /* can be set even if vnics_per_port = 1 */ 1038 uint32_t path_has_ovlan; /* MF mode in the path (can be different than the MF mode of the function */ 1039 1040 #define IS_MULTI_VNIC(sc) ((sc)->devinfo.mf_info.multi_vnics_mode) 1041 #define VNICS_PER_PORT(sc) ((sc)->devinfo.mf_info.vnics_per_port) 1042 #define VNICS_PER_PATH(sc) \ 1043 ((sc)->devinfo.mf_info.vnics_per_port * \ 1044 ((CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 1 )) 1045 1046 uint8_t min_bw[MAX_VNIC_NUM]; 1047 uint8_t max_bw[MAX_VNIC_NUM]; 1048 1049 uint16_t ext_id; /* vnic outer vlan or VIF ID */ 1050 #define VALID_OVLAN(ovlan) ((ovlan) <= 4096) 1051 #define INVALID_VIF_ID 0xFFFF 1052 #define OVLAN(sc) ((sc)->devinfo.mf_info.ext_id) 1053 #define VIF_ID(sc) ((sc)->devinfo.mf_info.ext_id) 1054 1055 uint16_t default_vlan; 1056 #define NIV_DEFAULT_VLAN(sc) ((sc)->devinfo.mf_info.default_vlan) 1057 1058 uint8_t niv_allowed_priorities; 1059 #define NIV_ALLOWED_PRIORITIES(sc) ((sc)->devinfo.mf_info.niv_allowed_priorities) 1060 1061 uint8_t niv_default_cos; 1062 #define NIV_DEFAULT_COS(sc) ((sc)->devinfo.mf_info.niv_default_cos) 1063 1064 uint8_t niv_mba_enabled; 1065 1066 enum mf_cfg_afex_vlan_mode afex_vlan_mode; 1067 #define AFEX_VLAN_MODE(sc) ((sc)->devinfo.mf_info.afex_vlan_mode) 1068 int afex_def_vlan_tag; 1069 uint32_t pending_max; 1070 1071 uint16_t flags; 1072 #define MF_INFO_VALID_MAC 0x0001 1073 1074 uint8_t mf_mode; /* Switch-Dependent or Switch-Independent */ 1075 #define IS_MF(sc) \ 1076 (IS_MULTI_VNIC(sc) && \ 1077 ((sc)->devinfo.mf_info.mf_mode != 0)) 1078 #define IS_MF_SD(sc) \ 1079 (IS_MULTI_VNIC(sc) && \ 1080 ((sc)->devinfo.mf_info.mf_mode == MULTI_FUNCTION_SD)) 1081 #define IS_MF_SI(sc) \ 1082 (IS_MULTI_VNIC(sc) && \ 1083 ((sc)->devinfo.mf_info.mf_mode == MULTI_FUNCTION_SI)) 1084 #define IS_MF_AFEX(sc) \ 1085 (IS_MULTI_VNIC(sc) && \ 1086 ((sc)->devinfo.mf_info.mf_mode == MULTI_FUNCTION_AFEX)) 1087 #define IS_MF_SD_MODE(sc) IS_MF_SD(sc) 1088 #define IS_MF_SI_MODE(sc) IS_MF_SI(sc) 1089 #define IS_MF_AFEX_MODE(sc) IS_MF_AFEX(sc) 1090 1091 uint32_t mf_protos_supported; 1092 #define MF_PROTO_SUPPORT_ETHERNET 0x1 1093 #define MF_PROTO_SUPPORT_ISCSI 0x2 1094 #define MF_PROTO_SUPPORT_FCOE 0x4 1095 }; /* struct bxe_mf_info */ 1096 1097 /* Device information data structure. */ 1098 struct bxe_devinfo { 1099 /* PCIe info */ 1100 uint16_t vendor_id; 1101 uint16_t device_id; 1102 uint16_t subvendor_id; 1103 uint16_t subdevice_id; 1104 1105 /* 1106 * chip_id = 0b'CCCCCCCCCCCCCCCCRRRRMMMMMMMMBBBB' 1107 * C = Chip Number (bits 16-31) 1108 * R = Chip Revision (bits 12-15) 1109 * M = Chip Metal (bits 4-11) 1110 * B = Chip Bond ID (bits 0-3) 1111 */ 1112 uint32_t chip_id; 1113 #define CHIP_ID(sc) ((sc)->devinfo.chip_id & 0xffff0000) 1114 #define CHIP_NUM(sc) ((sc)->devinfo.chip_id >> 16) 1115 /* device ids */ 1116 #define CHIP_NUM_57710 0x164e 1117 #define CHIP_NUM_57711 0x164f 1118 #define CHIP_NUM_57711E 0x1650 1119 #define CHIP_NUM_57712 0x1662 1120 #define CHIP_NUM_57712_MF 0x1663 1121 #define CHIP_NUM_57712_VF 0x166f 1122 #define CHIP_NUM_57800 0x168a 1123 #define CHIP_NUM_57800_MF 0x16a5 1124 #define CHIP_NUM_57800_VF 0x16a9 1125 #define CHIP_NUM_57810 0x168e 1126 #define CHIP_NUM_57810_MF 0x16ae 1127 #define CHIP_NUM_57810_VF 0x16af 1128 #define CHIP_NUM_57811 0x163d 1129 #define CHIP_NUM_57811_MF 0x163e 1130 #define CHIP_NUM_57811_VF 0x163f 1131 #define CHIP_NUM_57840_OBS 0x168d 1132 #define CHIP_NUM_57840_OBS_MF 0x16ab 1133 #define CHIP_NUM_57840_4_10 0x16a1 1134 #define CHIP_NUM_57840_2_20 0x16a2 1135 #define CHIP_NUM_57840_MF 0x16a4 1136 #define CHIP_NUM_57840_VF 0x16ad 1137 1138 #define CHIP_REV_SHIFT 12 1139 #define CHIP_REV_MASK (0xF << CHIP_REV_SHIFT) 1140 #define CHIP_REV(sc) ((sc)->devinfo.chip_id & CHIP_REV_MASK) 1141 1142 #define CHIP_REV_Ax (0x0 << CHIP_REV_SHIFT) 1143 #define CHIP_REV_Bx (0x1 << CHIP_REV_SHIFT) 1144 #define CHIP_REV_Cx (0x2 << CHIP_REV_SHIFT) 1145 1146 #define CHIP_REV_IS_SLOW(sc) \ 1147 (CHIP_REV(sc) > 0x00005000) 1148 #define CHIP_REV_IS_FPGA(sc) \ 1149 (CHIP_REV_IS_SLOW(sc) && (CHIP_REV(sc) & 0x00001000)) 1150 #define CHIP_REV_IS_EMUL(sc) \ 1151 (CHIP_REV_IS_SLOW(sc) && !(CHIP_REV(sc) & 0x00001000)) 1152 #define CHIP_REV_IS_ASIC(sc) \ 1153 (!CHIP_REV_IS_SLOW(sc)) 1154 1155 #define CHIP_METAL(sc) ((sc->devinfo.chip_id) & 0x00000ff0) 1156 #define CHIP_BOND_ID(sc) ((sc->devinfo.chip_id) & 0x0000000f) 1157 1158 #define CHIP_IS_E1(sc) (CHIP_NUM(sc) == CHIP_NUM_57710) 1159 #define CHIP_IS_57710(sc) (CHIP_NUM(sc) == CHIP_NUM_57710) 1160 #define CHIP_IS_57711(sc) (CHIP_NUM(sc) == CHIP_NUM_57711) 1161 #define CHIP_IS_57711E(sc) (CHIP_NUM(sc) == CHIP_NUM_57711E) 1162 #define CHIP_IS_E1H(sc) ((CHIP_IS_57711(sc)) || \ 1163 (CHIP_IS_57711E(sc))) 1164 #define CHIP_IS_E1x(sc) (CHIP_IS_E1((sc)) || \ 1165 CHIP_IS_E1H((sc))) 1166 1167 #define CHIP_IS_57712(sc) (CHIP_NUM(sc) == CHIP_NUM_57712) 1168 #define CHIP_IS_57712_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57712_MF) 1169 #define CHIP_IS_57712_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57712_VF) 1170 #define CHIP_IS_E2(sc) (CHIP_IS_57712(sc) || \ 1171 CHIP_IS_57712_MF(sc)) 1172 1173 #define CHIP_IS_57800(sc) (CHIP_NUM(sc) == CHIP_NUM_57800) 1174 #define CHIP_IS_57800_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57800_MF) 1175 #define CHIP_IS_57800_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57800_VF) 1176 #define CHIP_IS_57810(sc) (CHIP_NUM(sc) == CHIP_NUM_57810) 1177 #define CHIP_IS_57810_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57810_MF) 1178 #define CHIP_IS_57810_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57810_VF) 1179 #define CHIP_IS_57811(sc) (CHIP_NUM(sc) == CHIP_NUM_57811) 1180 #define CHIP_IS_57811_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57811_MF) 1181 #define CHIP_IS_57811_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57811_VF) 1182 #define CHIP_IS_57840(sc) ((CHIP_NUM(sc) == CHIP_NUM_57840_OBS) || \ 1183 (CHIP_NUM(sc) == CHIP_NUM_57840_4_10) || \ 1184 (CHIP_NUM(sc) == CHIP_NUM_57840_2_20)) 1185 #define CHIP_IS_57840_MF(sc) ((CHIP_NUM(sc) == CHIP_NUM_57840_OBS_MF) || \ 1186 (CHIP_NUM(sc) == CHIP_NUM_57840_MF)) 1187 #define CHIP_IS_57840_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57840_VF) 1188 1189 #define CHIP_IS_E3(sc) (CHIP_IS_57800(sc) || \ 1190 CHIP_IS_57800_MF(sc) || \ 1191 CHIP_IS_57800_VF(sc) || \ 1192 CHIP_IS_57810(sc) || \ 1193 CHIP_IS_57810_MF(sc) || \ 1194 CHIP_IS_57810_VF(sc) || \ 1195 CHIP_IS_57811(sc) || \ 1196 CHIP_IS_57811_MF(sc) || \ 1197 CHIP_IS_57811_VF(sc) || \ 1198 CHIP_IS_57840(sc) || \ 1199 CHIP_IS_57840_MF(sc) || \ 1200 CHIP_IS_57840_VF(sc)) 1201 #define CHIP_IS_E3A0(sc) (CHIP_IS_E3(sc) && \ 1202 (CHIP_REV(sc) == CHIP_REV_Ax)) 1203 #define CHIP_IS_E3B0(sc) (CHIP_IS_E3(sc) && \ 1204 (CHIP_REV(sc) == CHIP_REV_Bx)) 1205 1206 #define USES_WARPCORE(sc) (CHIP_IS_E3(sc)) 1207 #define CHIP_IS_E2E3(sc) (CHIP_IS_E2(sc) || \ 1208 CHIP_IS_E3(sc)) 1209 1210 #define CHIP_IS_MF_CAP(sc) (CHIP_IS_57711E(sc) || \ 1211 CHIP_IS_57712_MF(sc) || \ 1212 CHIP_IS_E3(sc)) 1213 1214 #define IS_VF(sc) (CHIP_IS_57712_VF(sc) || \ 1215 CHIP_IS_57800_VF(sc) || \ 1216 CHIP_IS_57810_VF(sc) || \ 1217 CHIP_IS_57840_VF(sc)) 1218 #define IS_PF(sc) (!IS_VF(sc)) 1219 1220 /* 1221 * This define is used in two main places: 1222 * 1. In the early stages of nic_load, to know if to configure Parser/Searcher 1223 * to nic-only mode or to offload mode. Offload mode is configured if either 1224 * the chip is E1x (where NIC_MODE register is not applicable), or if cnic 1225 * already registered for this port (which means that the user wants storage 1226 * services). 1227 * 2. During cnic-related load, to know if offload mode is already configured 1228 * in the HW or needs to be configrued. Since the transition from nic-mode to 1229 * offload-mode in HW causes traffic coruption, nic-mode is configured only 1230 * in ports on which storage services where never requested. 1231 */ 1232 #define CONFIGURE_NIC_MODE(sc) (!CHIP_IS_E1x(sc) && !CNIC_ENABLED(sc)) 1233 1234 uint8_t chip_port_mode; 1235 #define CHIP_4_PORT_MODE 0x0 1236 #define CHIP_2_PORT_MODE 0x1 1237 #define CHIP_PORT_MODE_NONE 0x2 1238 #define CHIP_PORT_MODE(sc) ((sc)->devinfo.chip_port_mode) 1239 #define CHIP_IS_MODE_4_PORT(sc) (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) 1240 1241 uint8_t int_block; 1242 #define INT_BLOCK_HC 0 1243 #define INT_BLOCK_IGU 1 1244 #define INT_BLOCK_MODE_NORMAL 0 1245 #define INT_BLOCK_MODE_BW_COMP 2 1246 #define CHIP_INT_MODE_IS_NBC(sc) \ 1247 (!CHIP_IS_E1x(sc) && \ 1248 !((sc)->devinfo.int_block & INT_BLOCK_MODE_BW_COMP)) 1249 #define CHIP_INT_MODE_IS_BC(sc) (!CHIP_INT_MODE_IS_NBC(sc)) 1250 1251 uint32_t shmem_base; 1252 uint32_t shmem2_base; 1253 uint32_t bc_ver; 1254 char bc_ver_str[32]; 1255 uint32_t mf_cfg_base; /* bootcode shmem address in BAR memory */ 1256 struct bxe_mf_info mf_info; 1257 1258 int flash_size; 1259 #define NVRAM_1MB_SIZE 0x20000 1260 #define NVRAM_TIMEOUT_COUNT 30000 1261 #define NVRAM_PAGE_SIZE 256 1262 1263 /* PCIe capability information */ 1264 uint32_t pcie_cap_flags; 1265 #define BXE_PM_CAPABLE_FLAG 0x00000001 1266 #define BXE_PCIE_CAPABLE_FLAG 0x00000002 1267 #define BXE_MSI_CAPABLE_FLAG 0x00000004 1268 #define BXE_MSIX_CAPABLE_FLAG 0x00000008 1269 uint16_t pcie_pm_cap_reg; 1270 uint16_t pcie_pcie_cap_reg; 1271 //uint16_t pcie_devctl; 1272 uint16_t pcie_link_width; 1273 uint16_t pcie_link_speed; 1274 uint16_t pcie_msi_cap_reg; 1275 uint16_t pcie_msix_cap_reg; 1276 1277 /* device configuration read from bootcode shared memory */ 1278 uint32_t hw_config; 1279 uint32_t hw_config2; 1280 }; /* struct bxe_devinfo */ 1281 1282 struct bxe_sp_objs { 1283 struct ecore_vlan_mac_obj mac_obj; /* MACs object */ 1284 struct ecore_queue_sp_obj q_obj; /* Queue State object */ 1285 }; /* struct bxe_sp_objs */ 1286 1287 /* 1288 * Data that will be used to create a link report message. We will keep the 1289 * data used for the last link report in order to prevent reporting the same 1290 * link parameters twice. 1291 */ 1292 struct bxe_link_report_data { 1293 uint16_t line_speed; /* Effective line speed */ 1294 unsigned long link_report_flags; /* BXE_LINK_REPORT_XXX flags */ 1295 }; 1296 enum { 1297 BXE_LINK_REPORT_FULL_DUPLEX, 1298 BXE_LINK_REPORT_LINK_DOWN, 1299 BXE_LINK_REPORT_RX_FC_ON, 1300 BXE_LINK_REPORT_TX_FC_ON 1301 }; 1302 1303 /* Top level device private data structure. */ 1304 struct bxe_softc { 1305 /* 1306 * First entry must be a pointer to the BSD ifnet struct which 1307 * has a first element of 'void *if_softc' (which is us). XXX 1308 */ 1309 if_t ifp; 1310 struct ifmedia ifmedia; /* network interface media structure */ 1311 int media; 1312 1313 volatile int state; /* device state */ 1314 #define BXE_STATE_CLOSED 0x0000 1315 #define BXE_STATE_OPENING_WAITING_LOAD 0x1000 1316 #define BXE_STATE_OPENING_WAITING_PORT 0x2000 1317 #define BXE_STATE_OPEN 0x3000 1318 #define BXE_STATE_CLOSING_WAITING_HALT 0x4000 1319 #define BXE_STATE_CLOSING_WAITING_DELETE 0x5000 1320 #define BXE_STATE_CLOSING_WAITING_UNLOAD 0x6000 1321 #define BXE_STATE_DISABLED 0xD000 1322 #define BXE_STATE_DIAG 0xE000 1323 #define BXE_STATE_ERROR 0xF000 1324 1325 int flags; 1326 #define BXE_ONE_PORT_FLAG 0x00000001 1327 #define BXE_NO_ISCSI 0x00000002 1328 #define BXE_NO_FCOE 0x00000004 1329 #define BXE_ONE_PORT(sc) (sc->flags & BXE_ONE_PORT_FLAG) 1330 //#define BXE_NO_WOL_FLAG 0x00000008 1331 //#define BXE_USING_DAC_FLAG 0x00000010 1332 //#define BXE_USING_MSIX_FLAG 0x00000020 1333 //#define BXE_USING_MSI_FLAG 0x00000040 1334 //#define BXE_DISABLE_MSI_FLAG 0x00000080 1335 #define BXE_NO_MCP_FLAG 0x00000200 1336 #define BXE_NOMCP(sc) (sc->flags & BXE_NO_MCP_FLAG) 1337 //#define BXE_SAFC_TX_FLAG 0x00000400 1338 #define BXE_MF_FUNC_DIS 0x00000800 1339 #define BXE_TX_SWITCHING 0x00001000 1340 #define BXE_NO_PULSE 0x00002000 1341 1342 unsigned long debug; /* per-instance debug logging config */ 1343 1344 #define MAX_BARS 5 1345 struct bxe_bar bar[MAX_BARS]; /* map BARs 0, 2, 4 */ 1346 1347 uint16_t doorbell_size; 1348 1349 /* periodic timer callout */ 1350 #define PERIODIC_STOP 0 1351 #define PERIODIC_GO 1 1352 volatile unsigned long periodic_flags; 1353 struct callout periodic_callout; 1354 1355 /* chip start/stop/reset taskqueue */ 1356 #define CHIP_TQ_NONE 0 1357 #define CHIP_TQ_START 1 1358 #define CHIP_TQ_STOP 2 1359 #define CHIP_TQ_REINIT 3 1360 volatile unsigned long chip_tq_flags; 1361 struct task chip_tq_task; 1362 struct taskqueue *chip_tq; 1363 char chip_tq_name[32]; 1364 1365 struct timeout_task sp_err_timeout_task; 1366 1367 /* slowpath interrupt taskqueue */ 1368 struct task sp_tq_task; 1369 struct taskqueue *sp_tq; 1370 char sp_tq_name[32]; 1371 1372 struct bxe_fastpath fp[MAX_RSS_CHAINS]; 1373 struct bxe_sp_objs sp_objs[MAX_RSS_CHAINS]; 1374 1375 device_t dev; /* parent device handle */ 1376 uint8_t unit; /* driver instance number */ 1377 1378 int pcie_bus; /* PCIe bus number */ 1379 int pcie_device; /* PCIe device/slot number */ 1380 int pcie_func; /* PCIe function number */ 1381 1382 uint8_t pfunc_rel; /* function relative */ 1383 uint8_t pfunc_abs; /* function absolute */ 1384 uint8_t path_id; /* function absolute */ 1385 #define SC_PATH(sc) (sc->path_id) 1386 #define SC_PORT(sc) (sc->pfunc_rel & 1) 1387 #define SC_FUNC(sc) (sc->pfunc_rel) 1388 #define SC_ABS_FUNC(sc) (sc->pfunc_abs) 1389 #define SC_VN(sc) (sc->pfunc_rel >> 1) 1390 #define SC_L_ID(sc) (SC_VN(sc) << 2) 1391 #define PORT_ID(sc) SC_PORT(sc) 1392 #define PATH_ID(sc) SC_PATH(sc) 1393 #define VNIC_ID(sc) SC_VN(sc) 1394 #define FUNC_ID(sc) SC_FUNC(sc) 1395 #define ABS_FUNC_ID(sc) SC_ABS_FUNC(sc) 1396 #define SC_FW_MB_IDX_VN(sc, vn) \ 1397 (SC_PORT(sc) + (vn) * \ 1398 ((CHIP_IS_E1x(sc) || (CHIP_IS_MODE_4_PORT(sc))) ? 2 : 1)) 1399 #define SC_FW_MB_IDX(sc) SC_FW_MB_IDX_VN(sc, SC_VN(sc)) 1400 1401 int if_capen; /* enabled interface capabilities */ 1402 1403 struct bxe_devinfo devinfo; 1404 char fw_ver_str[32]; 1405 char mf_mode_str[32]; 1406 char pci_link_str[32]; 1407 1408 const struct iro *iro_array; 1409 1410 #ifdef BXE_CORE_LOCK_SX 1411 struct sx core_sx; 1412 char core_sx_name[32]; 1413 #else 1414 struct mtx core_mtx; 1415 char core_mtx_name[32]; 1416 #endif 1417 struct mtx sp_mtx; 1418 char sp_mtx_name[32]; 1419 struct mtx dmae_mtx; 1420 char dmae_mtx_name[32]; 1421 struct mtx fwmb_mtx; 1422 char fwmb_mtx_name[32]; 1423 struct mtx print_mtx; 1424 char print_mtx_name[32]; 1425 struct mtx stats_mtx; 1426 char stats_mtx_name[32]; 1427 struct mtx mcast_mtx; 1428 char mcast_mtx_name[32]; 1429 1430 #ifdef BXE_CORE_LOCK_SX 1431 #define BXE_CORE_TRYLOCK(sc) sx_try_xlock(&sc->core_sx) 1432 #define BXE_CORE_LOCK(sc) sx_xlock(&sc->core_sx) 1433 #define BXE_CORE_UNLOCK(sc) sx_xunlock(&sc->core_sx) 1434 #define BXE_CORE_LOCK_ASSERT(sc) sx_assert(&sc->core_sx, SA_XLOCKED) 1435 #else 1436 #define BXE_CORE_TRYLOCK(sc) mtx_trylock(&sc->core_mtx) 1437 #define BXE_CORE_LOCK(sc) mtx_lock(&sc->core_mtx) 1438 #define BXE_CORE_UNLOCK(sc) mtx_unlock(&sc->core_mtx) 1439 #define BXE_CORE_LOCK_ASSERT(sc) mtx_assert(&sc->core_mtx, MA_OWNED) 1440 #endif 1441 1442 #define BXE_SP_LOCK(sc) mtx_lock(&sc->sp_mtx) 1443 #define BXE_SP_UNLOCK(sc) mtx_unlock(&sc->sp_mtx) 1444 #define BXE_SP_LOCK_ASSERT(sc) mtx_assert(&sc->sp_mtx, MA_OWNED) 1445 1446 #define BXE_DMAE_LOCK(sc) mtx_lock(&sc->dmae_mtx) 1447 #define BXE_DMAE_UNLOCK(sc) mtx_unlock(&sc->dmae_mtx) 1448 #define BXE_DMAE_LOCK_ASSERT(sc) mtx_assert(&sc->dmae_mtx, MA_OWNED) 1449 1450 #define BXE_FWMB_LOCK(sc) mtx_lock(&sc->fwmb_mtx) 1451 #define BXE_FWMB_UNLOCK(sc) mtx_unlock(&sc->fwmb_mtx) 1452 #define BXE_FWMB_LOCK_ASSERT(sc) mtx_assert(&sc->fwmb_mtx, MA_OWNED) 1453 1454 #define BXE_PRINT_LOCK(sc) mtx_lock(&sc->print_mtx) 1455 #define BXE_PRINT_UNLOCK(sc) mtx_unlock(&sc->print_mtx) 1456 #define BXE_PRINT_LOCK_ASSERT(sc) mtx_assert(&sc->print_mtx, MA_OWNED) 1457 1458 #define BXE_STATS_LOCK(sc) mtx_lock(&sc->stats_mtx) 1459 #define BXE_STATS_UNLOCK(sc) mtx_unlock(&sc->stats_mtx) 1460 #define BXE_STATS_LOCK_ASSERT(sc) mtx_assert(&sc->stats_mtx, MA_OWNED) 1461 1462 #define BXE_MCAST_LOCK(sc) mtx_lock(&sc->mcast_mtx); 1463 #define BXE_MCAST_UNLOCK(sc) mtx_unlock(&sc->mcast_mtx); 1464 #define BXE_MCAST_LOCK_ASSERT(sc) mtx_assert(&sc->mcast_mtx, MA_OWNED) 1465 1466 int dmae_ready; 1467 #define DMAE_READY(sc) (sc->dmae_ready) 1468 1469 struct ecore_credit_pool_obj vlans_pool; 1470 struct ecore_credit_pool_obj macs_pool; 1471 struct ecore_rx_mode_obj rx_mode_obj; 1472 struct ecore_mcast_obj mcast_obj; 1473 struct ecore_rss_config_obj rss_conf_obj; 1474 struct ecore_func_sp_obj func_obj; 1475 1476 uint16_t fw_seq; 1477 uint16_t fw_drv_pulse_wr_seq; 1478 uint32_t func_stx; 1479 1480 struct elink_params link_params; 1481 struct elink_vars link_vars; 1482 uint32_t link_cnt; 1483 struct bxe_link_report_data last_reported_link; 1484 char mac_addr_str[32]; 1485 1486 int last_reported_link_state; 1487 1488 int tx_ring_size; 1489 int rx_ring_size; 1490 int wol; 1491 1492 int is_leader; 1493 int recovery_state; 1494 #define BXE_RECOVERY_DONE 1 1495 #define BXE_RECOVERY_INIT 2 1496 #define BXE_RECOVERY_WAIT 3 1497 #define BXE_RECOVERY_FAILED 4 1498 #define BXE_RECOVERY_NIC_LOADING 5 1499 1500 #define BXE_ERR_TXQ_STUCK 0x1 /* Tx queue stuck detected by driver. */ 1501 #define BXE_ERR_MISC 0x2 /* MISC ERR */ 1502 #define BXE_ERR_PARITY 0x4 /* Parity error detected. */ 1503 #define BXE_ERR_STATS_TO 0x8 /* Statistics timeout detected. */ 1504 #define BXE_ERR_MC_ASSERT 0x10 /* MC assert attention received. */ 1505 #define BXE_ERR_PANIC 0x20 /* Driver asserted. */ 1506 #define BXE_ERR_MCP_ASSERT 0x40 /* MCP assert attention received. No Recovery*/ 1507 #define BXE_ERR_GLOBAL 0x80 /* PCIe/PXP/IGU/MISC/NIG device blocks error- needs PCIe/Fundamental reset */ 1508 uint32_t error_status; 1509 1510 uint32_t rx_mode; 1511 #define BXE_RX_MODE_NONE 0 1512 #define BXE_RX_MODE_NORMAL 1 1513 #define BXE_RX_MODE_ALLMULTI 2 1514 #define BXE_RX_MODE_PROMISC 3 1515 #define BXE_MAX_MULTICAST 64 1516 1517 struct bxe_port port; 1518 1519 struct cmng_init cmng; 1520 1521 /* user configs */ 1522 int num_queues; 1523 int max_rx_bufs; 1524 int hc_rx_ticks; 1525 int hc_tx_ticks; 1526 int rx_budget; 1527 int max_aggregation_size; 1528 int mrrs; 1529 int autogreeen; 1530 #define AUTO_GREEN_HW_DEFAULT 0 1531 #define AUTO_GREEN_FORCE_ON 1 1532 #define AUTO_GREEN_FORCE_OFF 2 1533 int interrupt_mode; 1534 #define INTR_MODE_INTX 0 1535 #define INTR_MODE_MSI 1 1536 #define INTR_MODE_MSIX 2 1537 int udp_rss; 1538 1539 /* interrupt allocations */ 1540 struct bxe_intr intr[MAX_RSS_CHAINS+1]; 1541 int intr_count; 1542 uint8_t igu_dsb_id; 1543 uint8_t igu_base_sb; 1544 uint8_t igu_sb_cnt; 1545 //uint8_t min_msix_vec_cnt; 1546 uint32_t igu_base_addr; 1547 //bus_addr_t def_status_blk_mapping; 1548 uint8_t base_fw_ndsb; 1549 #define DEF_SB_IGU_ID 16 1550 #define DEF_SB_ID HC_SP_SB_ID 1551 1552 /* parent bus DMA tag */ 1553 bus_dma_tag_t parent_dma_tag; 1554 1555 /* default status block */ 1556 struct bxe_dma def_sb_dma; 1557 struct host_sp_status_block *def_sb; 1558 uint16_t def_idx; 1559 uint16_t def_att_idx; 1560 uint32_t attn_state; 1561 struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS]; 1562 1563 /* general SP events - stats query, cfc delete, etc */ 1564 #define HC_SP_INDEX_ETH_DEF_CONS 3 1565 /* EQ completions */ 1566 #define HC_SP_INDEX_EQ_CONS 7 1567 /* FCoE L2 connection completions */ 1568 #define HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS 6 1569 #define HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS 4 1570 /* iSCSI L2 */ 1571 #define HC_SP_INDEX_ETH_ISCSI_CQ_CONS 5 1572 #define HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS 1 1573 1574 /* event queue */ 1575 struct bxe_dma eq_dma; 1576 union event_ring_elem *eq; 1577 uint16_t eq_prod; 1578 uint16_t eq_cons; 1579 uint16_t *eq_cons_sb; 1580 #define NUM_EQ_PAGES 1 /* must be a power of 2 */ 1581 #define EQ_DESC_CNT_PAGE (BCM_PAGE_SIZE / sizeof(union event_ring_elem)) 1582 #define EQ_DESC_MAX_PAGE (EQ_DESC_CNT_PAGE - 1) 1583 #define NUM_EQ_DESC (EQ_DESC_CNT_PAGE * NUM_EQ_PAGES) 1584 #define EQ_DESC_MASK (NUM_EQ_DESC - 1) 1585 #define MAX_EQ_AVAIL (EQ_DESC_MAX_PAGE * NUM_EQ_PAGES - 2) 1586 /* depends on EQ_DESC_CNT_PAGE being a power of 2 */ 1587 #define NEXT_EQ_IDX(x) \ 1588 ((((x) & EQ_DESC_MAX_PAGE) == (EQ_DESC_MAX_PAGE - 1)) ? \ 1589 ((x) + 2) : ((x) + 1)) 1590 /* depends on the above and on NUM_EQ_PAGES being a power of 2 */ 1591 #define EQ_DESC(x) ((x) & EQ_DESC_MASK) 1592 1593 /* slow path */ 1594 struct bxe_dma sp_dma; 1595 struct bxe_slowpath *sp; 1596 unsigned long sp_state; 1597 1598 /* slow path queue */ 1599 struct bxe_dma spq_dma; 1600 struct eth_spe *spq; 1601 #define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe)) 1602 #define MAX_SP_DESC_CNT (SP_DESC_CNT - 1) 1603 #define MAX_SPQ_PENDING 8 1604 1605 uint16_t spq_prod_idx; 1606 struct eth_spe *spq_prod_bd; 1607 struct eth_spe *spq_last_bd; 1608 uint16_t *dsb_sp_prod; 1609 //uint16_t *spq_hw_con; 1610 //uint16_t spq_left; 1611 1612 volatile unsigned long eq_spq_left; /* COMMON_xxx ramrod credit */ 1613 volatile unsigned long cq_spq_left; /* ETH_xxx ramrod credit */ 1614 1615 /* fw decompression buffer */ 1616 struct bxe_dma gz_buf_dma; 1617 void *gz_buf; 1618 z_streamp gz_strm; 1619 uint32_t gz_outlen; 1620 #define GUNZIP_BUF(sc) (sc->gz_buf) 1621 #define GUNZIP_OUTLEN(sc) (sc->gz_outlen) 1622 #define GUNZIP_PHYS(sc) (sc->gz_buf_dma.paddr) 1623 #define FW_BUF_SIZE 0x40000 1624 1625 const struct raw_op *init_ops; 1626 const uint16_t *init_ops_offsets; /* init block offsets inside init_ops */ 1627 const uint32_t *init_data; /* data blob, 32 bit granularity */ 1628 uint32_t init_mode_flags; 1629 #define INIT_MODE_FLAGS(sc) (sc->init_mode_flags) 1630 /* PRAM blobs - raw data */ 1631 const uint8_t *tsem_int_table_data; 1632 const uint8_t *tsem_pram_data; 1633 const uint8_t *usem_int_table_data; 1634 const uint8_t *usem_pram_data; 1635 const uint8_t *xsem_int_table_data; 1636 const uint8_t *xsem_pram_data; 1637 const uint8_t *csem_int_table_data; 1638 const uint8_t *csem_pram_data; 1639 #define INIT_OPS(sc) (sc->init_ops) 1640 #define INIT_OPS_OFFSETS(sc) (sc->init_ops_offsets) 1641 #define INIT_DATA(sc) (sc->init_data) 1642 #define INIT_TSEM_INT_TABLE_DATA(sc) (sc->tsem_int_table_data) 1643 #define INIT_TSEM_PRAM_DATA(sc) (sc->tsem_pram_data) 1644 #define INIT_USEM_INT_TABLE_DATA(sc) (sc->usem_int_table_data) 1645 #define INIT_USEM_PRAM_DATA(sc) (sc->usem_pram_data) 1646 #define INIT_XSEM_INT_TABLE_DATA(sc) (sc->xsem_int_table_data) 1647 #define INIT_XSEM_PRAM_DATA(sc) (sc->xsem_pram_data) 1648 #define INIT_CSEM_INT_TABLE_DATA(sc) (sc->csem_int_table_data) 1649 #define INIT_CSEM_PRAM_DATA(sc) (sc->csem_pram_data) 1650 1651 /* ILT 1652 * For max 196 cids (64*3 + non-eth), 32KB ILT page size and 1KB 1653 * context size we need 8 ILT entries. 1654 */ 1655 #define ILT_MAX_L2_LINES 8 1656 struct hw_context context[ILT_MAX_L2_LINES]; 1657 struct ecore_ilt *ilt; 1658 #define ILT_MAX_LINES 256 1659 1660 /* max supported number of RSS queues: IGU SBs minus one for CNIC */ 1661 #define BXE_MAX_RSS_COUNT(sc) ((sc)->igu_sb_cnt - CNIC_SUPPORT(sc)) 1662 /* max CID count: Max RSS * Max_Tx_Multi_Cos + FCoE + iSCSI */ 1663 #if 1 1664 #define BXE_L2_MAX_CID(sc) \ 1665 (BXE_MAX_RSS_COUNT(sc) * ECORE_MULTI_TX_COS + 2 * CNIC_SUPPORT(sc)) 1666 #else 1667 #define BXE_L2_MAX_CID(sc) /* OOO + FWD */ \ 1668 (BXE_MAX_RSS_COUNT(sc) * ECORE_MULTI_TX_COS + 4 * CNIC_SUPPORT(sc)) 1669 #endif 1670 #if 1 1671 #define BXE_L2_CID_COUNT(sc) \ 1672 (BXE_NUM_ETH_QUEUES(sc) * ECORE_MULTI_TX_COS + 2 * CNIC_SUPPORT(sc)) 1673 #else 1674 #define BXE_L2_CID_COUNT(sc) /* OOO + FWD */ \ 1675 (BXE_NUM_ETH_QUEUES(sc) * ECORE_MULTI_TX_COS + 4 * CNIC_SUPPORT(sc)) 1676 #endif 1677 #define L2_ILT_LINES(sc) \ 1678 (DIV_ROUND_UP(BXE_L2_CID_COUNT(sc), ILT_PAGE_CIDS)) 1679 1680 int qm_cid_count; 1681 1682 uint8_t dropless_fc; 1683 1684 /* total number of FW statistics requests */ 1685 uint8_t fw_stats_num; 1686 /* 1687 * This is a memory buffer that will contain both statistics ramrod 1688 * request and data. 1689 */ 1690 struct bxe_dma fw_stats_dma; 1691 /* 1692 * FW statistics request shortcut (points at the beginning of fw_stats 1693 * buffer). 1694 */ 1695 int fw_stats_req_size; 1696 struct bxe_fw_stats_req *fw_stats_req; 1697 bus_addr_t fw_stats_req_mapping; 1698 /* 1699 * FW statistics data shortcut (points at the beginning of fw_stats 1700 * buffer + fw_stats_req_size). 1701 */ 1702 int fw_stats_data_size; 1703 struct bxe_fw_stats_data *fw_stats_data; 1704 bus_addr_t fw_stats_data_mapping; 1705 1706 /* tracking a pending STAT_QUERY ramrod */ 1707 uint16_t stats_pending; 1708 /* number of completed statistics ramrods */ 1709 uint16_t stats_comp; 1710 uint16_t stats_counter; 1711 uint8_t stats_init; 1712 int stats_state; 1713 1714 struct bxe_eth_stats eth_stats; 1715 struct host_func_stats func_stats; 1716 struct bxe_eth_stats_old eth_stats_old; 1717 struct bxe_net_stats_old net_stats_old; 1718 struct bxe_fw_port_stats_old fw_stats_old; 1719 1720 struct dmae_cmd stats_dmae; /* used by dmae command loader */ 1721 int executer_idx; 1722 1723 int mtu; 1724 1725 /* LLDP params */ 1726 struct bxe_config_lldp_params lldp_config_params; 1727 /* DCB support on/off */ 1728 int dcb_state; 1729 #define BXE_DCB_STATE_OFF 0 1730 #define BXE_DCB_STATE_ON 1 1731 /* DCBX engine mode */ 1732 int dcbx_enabled; 1733 #define BXE_DCBX_ENABLED_OFF 0 1734 #define BXE_DCBX_ENABLED_ON_NEG_OFF 1 1735 #define BXE_DCBX_ENABLED_ON_NEG_ON 2 1736 #define BXE_DCBX_ENABLED_INVALID -1 1737 uint8_t dcbx_mode_uset; 1738 struct bxe_config_dcbx_params dcbx_config_params; 1739 struct bxe_dcbx_port_params dcbx_port_params; 1740 int dcb_version; 1741 1742 uint8_t cnic_support; 1743 uint8_t cnic_enabled; 1744 uint8_t cnic_loaded; 1745 #define CNIC_SUPPORT(sc) 0 /* ((sc)->cnic_support) */ 1746 #define CNIC_ENABLED(sc) 0 /* ((sc)->cnic_enabled) */ 1747 #define CNIC_LOADED(sc) 0 /* ((sc)->cnic_loaded) */ 1748 1749 /* multiple tx classes of service */ 1750 uint8_t max_cos; 1751 #define BXE_MAX_PRIORITY 8 1752 /* priority to cos mapping */ 1753 uint8_t prio_to_cos[BXE_MAX_PRIORITY]; 1754 1755 int panic; 1756 1757 struct cdev *ioctl_dev; 1758 1759 void *grc_dump; 1760 unsigned int trigger_grcdump; 1761 unsigned int grcdump_done; 1762 unsigned int grcdump_started; 1763 int bxe_pause_param; 1764 void *eeprom; 1765 }; /* struct bxe_softc */ 1766 1767 /* IOCTL sub-commands for edebug and firmware upgrade */ 1768 #define BXE_IOC_RD_NVRAM 1 1769 #define BXE_IOC_WR_NVRAM 2 1770 #define BXE_IOC_STATS_SHOW_NUM 3 1771 #define BXE_IOC_STATS_SHOW_STR 4 1772 #define BXE_IOC_STATS_SHOW_CNT 5 1773 1774 struct bxe_nvram_data { 1775 uint32_t op; /* ioctl sub-command */ 1776 uint32_t offset; 1777 uint32_t len; 1778 uint32_t value[1]; /* variable */ 1779 }; 1780 1781 union bxe_stats_show_data { 1782 uint32_t op; /* ioctl sub-command */ 1783 1784 struct { 1785 uint32_t num; /* return number of stats */ 1786 uint32_t len; /* length of each string item */ 1787 } desc; 1788 1789 /* variable length... */ 1790 char str[1]; /* holds names of desc.num stats, each desc.len in length */ 1791 1792 /* variable length... */ 1793 uint64_t stats[1]; /* holds all stats */ 1794 }; 1795 1796 /* function init flags */ 1797 #define FUNC_FLG_RSS 0x0001 1798 #define FUNC_FLG_STATS 0x0002 1799 /* FUNC_FLG_UNMATCHED 0x0004 */ 1800 #define FUNC_FLG_TPA 0x0008 1801 #define FUNC_FLG_SPQ 0x0010 1802 #define FUNC_FLG_LEADING 0x0020 /* PF only */ 1803 1804 struct bxe_func_init_params { 1805 bus_addr_t fw_stat_map; /* (dma) valid if FUNC_FLG_STATS */ 1806 bus_addr_t spq_map; /* (dma) valid if FUNC_FLG_SPQ */ 1807 uint16_t func_flgs; 1808 uint16_t func_id; /* abs function id */ 1809 uint16_t pf_id; 1810 uint16_t spq_prod; /* valid if FUNC_FLG_SPQ */ 1811 }; 1812 1813 /* memory resources reside at BARs 0, 2, 4 */ 1814 /* Run `pciconf -lb` to see mappings */ 1815 #define BAR0 0 1816 #define BAR1 2 1817 #define BAR2 4 1818 1819 #ifdef BXE_REG_NO_INLINE 1820 1821 uint8_t bxe_reg_read8(struct bxe_softc *sc, bus_size_t offset); 1822 uint16_t bxe_reg_read16(struct bxe_softc *sc, bus_size_t offset); 1823 uint32_t bxe_reg_read32(struct bxe_softc *sc, bus_size_t offset); 1824 1825 void bxe_reg_write8(struct bxe_softc *sc, bus_size_t offset, uint8_t val); 1826 void bxe_reg_write16(struct bxe_softc *sc, bus_size_t offset, uint16_t val); 1827 void bxe_reg_write32(struct bxe_softc *sc, bus_size_t offset, uint32_t val); 1828 1829 #define REG_RD8(sc, offset) bxe_reg_read8(sc, offset) 1830 #define REG_RD16(sc, offset) bxe_reg_read16(sc, offset) 1831 #define REG_RD32(sc, offset) bxe_reg_read32(sc, offset) 1832 1833 #define REG_WR8(sc, offset, val) bxe_reg_write8(sc, offset, val) 1834 #define REG_WR16(sc, offset, val) bxe_reg_write16(sc, offset, val) 1835 #define REG_WR32(sc, offset, val) bxe_reg_write32(sc, offset, val) 1836 1837 #else /* not BXE_REG_NO_INLINE */ 1838 1839 #define REG_WR8(sc, offset, val) \ 1840 bus_space_write_1(sc->bar[BAR0].tag, \ 1841 sc->bar[BAR0].handle, \ 1842 offset, val) 1843 1844 #define REG_WR16(sc, offset, val) \ 1845 bus_space_write_2(sc->bar[BAR0].tag, \ 1846 sc->bar[BAR0].handle, \ 1847 offset, val) 1848 1849 #define REG_WR32(sc, offset, val) \ 1850 bus_space_write_4(sc->bar[BAR0].tag, \ 1851 sc->bar[BAR0].handle, \ 1852 offset, val) 1853 1854 #define REG_RD8(sc, offset) \ 1855 bus_space_read_1(sc->bar[BAR0].tag, \ 1856 sc->bar[BAR0].handle, \ 1857 offset) 1858 1859 #define REG_RD16(sc, offset) \ 1860 bus_space_read_2(sc->bar[BAR0].tag, \ 1861 sc->bar[BAR0].handle, \ 1862 offset) 1863 1864 #define REG_RD32(sc, offset) \ 1865 bus_space_read_4(sc->bar[BAR0].tag, \ 1866 sc->bar[BAR0].handle, \ 1867 offset) 1868 1869 #endif /* BXE_REG_NO_INLINE */ 1870 1871 #define REG_RD(sc, offset) REG_RD32(sc, offset) 1872 #define REG_WR(sc, offset, val) REG_WR32(sc, offset, val) 1873 1874 #define REG_RD_IND(sc, offset) bxe_reg_rd_ind(sc, offset) 1875 #define REG_WR_IND(sc, offset, val) bxe_reg_wr_ind(sc, offset, val) 1876 1877 #define BXE_SP(sc, var) (&(sc)->sp->var) 1878 #define BXE_SP_MAPPING(sc, var) \ 1879 (sc->sp_dma.paddr + offsetof(struct bxe_slowpath, var)) 1880 1881 #define BXE_FP(sc, nr, var) ((sc)->fp[(nr)].var) 1882 #define BXE_SP_OBJ(sc, fp) ((sc)->sp_objs[(fp)->index]) 1883 1884 #define REG_RD_DMAE(sc, offset, valp, len32) \ 1885 do { \ 1886 bxe_read_dmae(sc, offset, len32); \ 1887 memcpy(valp, BXE_SP(sc, wb_data[0]), (len32) * 4); \ 1888 } while (0) 1889 1890 #define REG_WR_DMAE(sc, offset, valp, len32) \ 1891 do { \ 1892 memcpy(BXE_SP(sc, wb_data[0]), valp, (len32) * 4); \ 1893 bxe_write_dmae(sc, BXE_SP_MAPPING(sc, wb_data), offset, len32); \ 1894 } while (0) 1895 1896 #define REG_WR_DMAE_LEN(sc, offset, valp, len32) \ 1897 REG_WR_DMAE(sc, offset, valp, len32) 1898 1899 #define REG_RD_DMAE_LEN(sc, offset, valp, len32) \ 1900 REG_RD_DMAE(sc, offset, valp, len32) 1901 1902 #define VIRT_WR_DMAE_LEN(sc, data, addr, len32, le32_swap) \ 1903 do { \ 1904 /* if (le32_swap) { */ \ 1905 /* BLOGW(sc, "VIRT_WR_DMAE_LEN with le32_swap=1\n"); */ \ 1906 /* } */ \ 1907 memcpy(GUNZIP_BUF(sc), data, len32 * 4); \ 1908 ecore_write_big_buf_wb(sc, addr, len32); \ 1909 } while (0) 1910 1911 #define BXE_DB_MIN_SHIFT 3 /* 8 bytes */ 1912 #define BXE_DB_SHIFT 7 /* 128 bytes */ 1913 #if (BXE_DB_SHIFT < BXE_DB_MIN_SHIFT) 1914 #error "Minimum DB doorbell stride is 8" 1915 #endif 1916 #define DPM_TRIGGER_TYPE 0x40 1917 #define DOORBELL(sc, cid, val) \ 1918 do { \ 1919 bus_space_write_4(sc->bar[BAR1].tag, sc->bar[BAR1].handle, \ 1920 ((sc->doorbell_size * (cid)) + DPM_TRIGGER_TYPE), \ 1921 (uint32_t)val); \ 1922 } while(0) 1923 1924 #define SHMEM_ADDR(sc, field) \ 1925 (sc->devinfo.shmem_base + offsetof(struct shmem_region, field)) 1926 #define SHMEM_RD(sc, field) REG_RD(sc, SHMEM_ADDR(sc, field)) 1927 #define SHMEM_RD16(sc, field) REG_RD16(sc, SHMEM_ADDR(sc, field)) 1928 #define SHMEM_WR(sc, field, val) REG_WR(sc, SHMEM_ADDR(sc, field), val) 1929 1930 #define SHMEM2_ADDR(sc, field) \ 1931 (sc->devinfo.shmem2_base + offsetof(struct shmem2_region, field)) 1932 #define SHMEM2_HAS(sc, field) \ 1933 (sc->devinfo.shmem2_base && (REG_RD(sc, SHMEM2_ADDR(sc, size)) > \ 1934 offsetof(struct shmem2_region, field))) 1935 #define SHMEM2_RD(sc, field) REG_RD(sc, SHMEM2_ADDR(sc, field)) 1936 #define SHMEM2_WR(sc, field, val) REG_WR(sc, SHMEM2_ADDR(sc, field), val) 1937 1938 #define MFCFG_ADDR(sc, field) \ 1939 (sc->devinfo.mf_cfg_base + offsetof(struct mf_cfg, field)) 1940 #define MFCFG_RD(sc, field) REG_RD(sc, MFCFG_ADDR(sc, field)) 1941 #define MFCFG_RD16(sc, field) REG_RD16(sc, MFCFG_ADDR(sc, field)) 1942 #define MFCFG_WR(sc, field, val) REG_WR(sc, MFCFG_ADDR(sc, field), val) 1943 1944 /* DMAE command defines */ 1945 1946 #define DMAE_TIMEOUT -1 1947 #define DMAE_PCI_ERROR -2 /* E2 and onward */ 1948 #define DMAE_NOT_RDY -3 1949 #define DMAE_PCI_ERR_FLAG 0x80000000 1950 1951 #define DMAE_SRC_PCI 0 1952 #define DMAE_SRC_GRC 1 1953 1954 #define DMAE_DST_NONE 0 1955 #define DMAE_DST_PCI 1 1956 #define DMAE_DST_GRC 2 1957 1958 #define DMAE_COMP_PCI 0 1959 #define DMAE_COMP_GRC 1 1960 1961 #define DMAE_COMP_REGULAR 0 1962 #define DMAE_COM_SET_ERR 1 1963 1964 #define DMAE_CMD_SRC_PCI (DMAE_SRC_PCI << DMAE_CMD_SRC_SHIFT) 1965 #define DMAE_CMD_SRC_GRC (DMAE_SRC_GRC << DMAE_CMD_SRC_SHIFT) 1966 #define DMAE_CMD_DST_PCI (DMAE_DST_PCI << DMAE_CMD_DST_SHIFT) 1967 #define DMAE_CMD_DST_GRC (DMAE_DST_GRC << DMAE_CMD_DST_SHIFT) 1968 1969 #define DMAE_CMD_C_DST_PCI (DMAE_COMP_PCI << DMAE_CMD_C_DST_SHIFT) 1970 #define DMAE_CMD_C_DST_GRC (DMAE_COMP_GRC << DMAE_CMD_C_DST_SHIFT) 1971 1972 #define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_CMD_ENDIANITY_SHIFT) 1973 #define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_CMD_ENDIANITY_SHIFT) 1974 #define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_CMD_ENDIANITY_SHIFT) 1975 #define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_CMD_ENDIANITY_SHIFT) 1976 1977 #define DMAE_CMD_PORT_0 0 1978 #define DMAE_CMD_PORT_1 DMAE_CMD_PORT 1979 1980 #define DMAE_SRC_PF 0 1981 #define DMAE_SRC_VF 1 1982 1983 #define DMAE_DST_PF 0 1984 #define DMAE_DST_VF 1 1985 1986 #define DMAE_C_SRC 0 1987 #define DMAE_C_DST 1 1988 1989 #define DMAE_LEN32_RD_MAX 0x80 1990 #define DMAE_LEN32_WR_MAX(sc) (CHIP_IS_E1(sc) ? 0x400 : 0x2000) 1991 1992 #define DMAE_COMP_VAL 0x60d0d0ae /* E2 and beyond, upper bit indicates error */ 1993 1994 #define MAX_DMAE_C_PER_PORT 8 1995 #define INIT_DMAE_C(sc) ((SC_PORT(sc) * MAX_DMAE_C_PER_PORT) + SC_VN(sc)) 1996 #define PMF_DMAE_C(sc) ((SC_PORT(sc) * MAX_DMAE_C_PER_PORT) + E1HVN_MAX) 1997 1998 static const uint32_t dmae_reg_go_c[] = { 1999 DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3, 2000 DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7, 2001 DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11, 2002 DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15 2003 }; 2004 2005 #define ATTN_NIG_FOR_FUNC (1L << 8) 2006 #define ATTN_SW_TIMER_4_FUNC (1L << 9) 2007 #define GPIO_2_FUNC (1L << 10) 2008 #define GPIO_3_FUNC (1L << 11) 2009 #define GPIO_4_FUNC (1L << 12) 2010 #define ATTN_GENERAL_ATTN_1 (1L << 13) 2011 #define ATTN_GENERAL_ATTN_2 (1L << 14) 2012 #define ATTN_GENERAL_ATTN_3 (1L << 15) 2013 #define ATTN_GENERAL_ATTN_4 (1L << 13) 2014 #define ATTN_GENERAL_ATTN_5 (1L << 14) 2015 #define ATTN_GENERAL_ATTN_6 (1L << 15) 2016 #define ATTN_HARD_WIRED_MASK 0xff00 2017 #define ATTENTION_ID 4 2018 2019 #define AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR \ 2020 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR 2021 2022 #define MAX_IGU_ATTN_ACK_TO 100 2023 2024 #define STORM_ASSERT_ARRAY_SIZE 50 2025 2026 #define BXE_PMF_LINK_ASSERT(sc) \ 2027 GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + SC_FUNC(sc)) 2028 2029 #define BXE_MC_ASSERT_BITS \ 2030 (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \ 2031 GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \ 2032 GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \ 2033 GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT)) 2034 2035 #define BXE_MCP_ASSERT \ 2036 GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT) 2037 2038 #define BXE_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC) 2039 #define BXE_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \ 2040 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \ 2041 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \ 2042 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \ 2043 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \ 2044 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC)) 2045 2046 #define MULTI_MASK 0x7f 2047 2048 #define PFS_PER_PORT(sc) \ 2049 ((CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4) 2050 #define SC_MAX_VN_NUM(sc) PFS_PER_PORT(sc) 2051 2052 #define FIRST_ABS_FUNC_IN_PORT(sc) \ 2053 ((CHIP_PORT_MODE(sc) == CHIP_PORT_MODE_NONE) ? \ 2054 PORT_ID(sc) : (PATH_ID(sc) + (2 * PORT_ID(sc)))) 2055 2056 #define FOREACH_ABS_FUNC_IN_PORT(sc, i) \ 2057 for ((i) = FIRST_ABS_FUNC_IN_PORT(sc); \ 2058 (i) < MAX_FUNC_NUM; \ 2059 (i) += (MAX_FUNC_NUM / PFS_PER_PORT(sc))) 2060 2061 #define BXE_SWCID_SHIFT 17 2062 #define BXE_SWCID_MASK ((0x1 << BXE_SWCID_SHIFT) - 1) 2063 2064 #define SW_CID(x) (le32toh(x) & BXE_SWCID_MASK) 2065 #define CQE_CMD(x) (le32toh(x) >> COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT) 2066 2067 #define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE) 2068 #define CQE_TYPE_START(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_START_AGG) 2069 #define CQE_TYPE_STOP(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_STOP_AGG) 2070 #define CQE_TYPE_SLOW(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_RAMROD) 2071 #define CQE_TYPE_FAST(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_FASTPATH) 2072 2073 /* must be used on a CID before placing it on a HW ring */ 2074 #define HW_CID(sc, x) \ 2075 ((SC_PORT(sc) << 23) | (SC_VN(sc) << BXE_SWCID_SHIFT) | (x)) 2076 2077 #define SPEED_10 10 2078 #define SPEED_100 100 2079 #define SPEED_1000 1000 2080 #define SPEED_2500 2500 2081 #define SPEED_10000 10000 2082 2083 #define PCI_PM_D0 1 2084 #define PCI_PM_D3hot 2 2085 2086 #ifndef DUPLEX_UNKNOWN 2087 #define DUPLEX_UNKNOWN (0xff) 2088 #endif 2089 2090 #ifndef SPEED_UNKNOWN 2091 #define SPEED_UNKNOWN (-1) 2092 #endif 2093 2094 /* Enable or disable autonegotiation. */ 2095 #define AUTONEG_DISABLE 0x00 2096 #define AUTONEG_ENABLE 0x01 2097 2098 /* Which connector port. */ 2099 #define PORT_TP 0x00 2100 #define PORT_AUI 0x01 2101 #define PORT_MII 0x02 2102 #define PORT_FIBRE 0x03 2103 #define PORT_BNC 0x04 2104 #define PORT_DA 0x05 2105 #define PORT_NONE 0xef 2106 #define PORT_OTHER 0xff 2107 2108 int bxe_test_bit(int nr, volatile unsigned long * addr); 2109 void bxe_set_bit(unsigned int nr, volatile unsigned long * addr); 2110 void bxe_clear_bit(int nr, volatile unsigned long * addr); 2111 int bxe_test_and_set_bit(int nr, volatile unsigned long * addr); 2112 int bxe_test_and_clear_bit(int nr, volatile unsigned long * addr); 2113 int bxe_cmpxchg(volatile int *addr, int old, int new); 2114 2115 void bxe_reg_wr_ind(struct bxe_softc *sc, uint32_t addr, 2116 uint32_t val); 2117 uint32_t bxe_reg_rd_ind(struct bxe_softc *sc, uint32_t addr); 2118 2119 2120 int bxe_dma_alloc(struct bxe_softc *sc, bus_size_t size, 2121 struct bxe_dma *dma, const char *msg); 2122 void bxe_dma_free(struct bxe_softc *sc, struct bxe_dma *dma); 2123 2124 uint32_t bxe_dmae_opcode_add_comp(uint32_t opcode, uint8_t comp_type); 2125 uint32_t bxe_dmae_opcode_clr_src_reset(uint32_t opcode); 2126 uint32_t bxe_dmae_opcode(struct bxe_softc *sc, uint8_t src_type, 2127 uint8_t dst_type, uint8_t with_comp, 2128 uint8_t comp_type); 2129 void bxe_post_dmae(struct bxe_softc *sc, struct dmae_cmd *dmae, int idx); 2130 void bxe_read_dmae(struct bxe_softc *sc, uint32_t src_addr, uint32_t len32); 2131 void bxe_write_dmae(struct bxe_softc *sc, bus_addr_t dma_addr, 2132 uint32_t dst_addr, uint32_t len32); 2133 void bxe_write_dmae_phys_len(struct bxe_softc *sc, bus_addr_t phys_addr, 2134 uint32_t addr, uint32_t len); 2135 2136 void bxe_set_ctx_validation(struct bxe_softc *sc, struct eth_context *cxt, 2137 uint32_t cid); 2138 void bxe_update_coalesce_sb_index(struct bxe_softc *sc, uint8_t fw_sb_id, 2139 uint8_t sb_index, uint8_t disable, 2140 uint16_t usec); 2141 2142 int bxe_sp_post(struct bxe_softc *sc, int command, int cid, 2143 uint32_t data_hi, uint32_t data_lo, int cmd_type); 2144 2145 void bxe_igu_ack_sb(struct bxe_softc *sc, uint8_t igu_sb_id, 2146 uint8_t segment, uint16_t index, uint8_t op, 2147 uint8_t update); 2148 2149 void ecore_init_e1_firmware(struct bxe_softc *sc); 2150 void ecore_init_e1h_firmware(struct bxe_softc *sc); 2151 void ecore_init_e2_firmware(struct bxe_softc *sc); 2152 2153 void ecore_storm_memset_struct(struct bxe_softc *sc, uint32_t addr, 2154 size_t size, uint32_t *data); 2155 2156 /*********************/ 2157 /* LOGGING AND DEBUG */ 2158 /*********************/ 2159 2160 /* debug logging codepaths */ 2161 #define DBG_LOAD 0x00000001 /* load and unload */ 2162 #define DBG_INTR 0x00000002 /* interrupt handling */ 2163 #define DBG_SP 0x00000004 /* slowpath handling */ 2164 #define DBG_STATS 0x00000008 /* stats updates */ 2165 #define DBG_TX 0x00000010 /* packet transmit */ 2166 #define DBG_RX 0x00000020 /* packet receive */ 2167 #define DBG_PHY 0x00000040 /* phy/link handling */ 2168 #define DBG_IOCTL 0x00000080 /* ioctl handling */ 2169 #define DBG_MBUF 0x00000100 /* dumping mbuf info */ 2170 #define DBG_REGS 0x00000200 /* register access */ 2171 #define DBG_LRO 0x00000400 /* lro processing */ 2172 #define DBG_ASSERT 0x80000000 /* debug assert */ 2173 #define DBG_ALL 0xFFFFFFFF /* flying monkeys */ 2174 2175 #define DBASSERT(sc, exp, msg) \ 2176 do { \ 2177 if (__predict_false(sc->debug & DBG_ASSERT)) { \ 2178 if (__predict_false(!(exp))) { \ 2179 panic msg; \ 2180 } \ 2181 } \ 2182 } while (0) 2183 2184 /* log a debug message */ 2185 #define BLOGD(sc, codepath, format, args...) \ 2186 do { \ 2187 if (__predict_false(sc->debug & (codepath))) { \ 2188 device_printf((sc)->dev, \ 2189 "%s(%s:%d) " format, \ 2190 __FUNCTION__, \ 2191 __FILE__, \ 2192 __LINE__, \ 2193 ## args); \ 2194 } \ 2195 } while(0) 2196 2197 /* log a info message */ 2198 #define BLOGI(sc, format, args...) \ 2199 do { \ 2200 if (__predict_false(sc->debug)) { \ 2201 device_printf((sc)->dev, \ 2202 "%s(%s:%d) " format, \ 2203 __FUNCTION__, \ 2204 __FILE__, \ 2205 __LINE__, \ 2206 ## args); \ 2207 } else { \ 2208 device_printf((sc)->dev, \ 2209 format, \ 2210 ## args); \ 2211 } \ 2212 } while(0) 2213 2214 /* log a warning message */ 2215 #define BLOGW(sc, format, args...) \ 2216 do { \ 2217 if (__predict_false(sc->debug)) { \ 2218 device_printf((sc)->dev, \ 2219 "%s(%s:%d) WARNING: " format, \ 2220 __FUNCTION__, \ 2221 __FILE__, \ 2222 __LINE__, \ 2223 ## args); \ 2224 } else { \ 2225 device_printf((sc)->dev, \ 2226 "WARNING: " format, \ 2227 ## args); \ 2228 } \ 2229 } while(0) 2230 2231 /* log a error message */ 2232 #define BLOGE(sc, format, args...) \ 2233 do { \ 2234 if (__predict_false(sc->debug)) { \ 2235 device_printf((sc)->dev, \ 2236 "%s(%s:%d) ERROR: " format, \ 2237 __FUNCTION__, \ 2238 __FILE__, \ 2239 __LINE__, \ 2240 ## args); \ 2241 } else { \ 2242 device_printf((sc)->dev, \ 2243 "ERROR: " format, \ 2244 ## args); \ 2245 } \ 2246 } while(0) 2247 2248 #ifdef ECORE_STOP_ON_ERROR 2249 2250 #define bxe_panic(sc, msg) \ 2251 do { \ 2252 panic msg; \ 2253 } while (0) 2254 2255 #else 2256 2257 #define bxe_panic(sc, msg) \ 2258 device_printf((sc)->dev, "%s (%s,%d)\n", __FUNCTION__, __FILE__, __LINE__); 2259 2260 #endif 2261 2262 #define CATC_TRIGGER(sc, data) REG_WR((sc), 0x2000, (data)); 2263 #define CATC_TRIGGER_START(sc) CATC_TRIGGER((sc), 0xcafecafe) 2264 2265 void bxe_dump_mem(struct bxe_softc *sc, char *tag, 2266 uint8_t *mem, uint32_t len); 2267 void bxe_dump_mbuf_data(struct bxe_softc *sc, char *pTag, 2268 struct mbuf *m, uint8_t contents); 2269 2270 #define BXE_SET_FLOWID(m) M_HASHTYPE_SET(m, M_HASHTYPE_OPAQUE) 2271 #define BXE_VALID_FLOWID(m) (M_HASHTYPE_GET(m) != M_HASHTYPE_NONE) 2272 2273 /***********/ 2274 /* INLINES */ 2275 /***********/ 2276 2277 static inline uint32_t 2278 reg_poll(struct bxe_softc *sc, 2279 uint32_t reg, 2280 uint32_t expected, 2281 int ms, 2282 int wait) 2283 { 2284 uint32_t val; 2285 2286 do { 2287 val = REG_RD(sc, reg); 2288 if (val == expected) { 2289 break; 2290 } 2291 ms -= wait; 2292 DELAY(wait * 1000); 2293 } while (ms > 0); 2294 2295 return (val); 2296 } 2297 2298 static inline void 2299 bxe_update_fp_sb_idx(struct bxe_fastpath *fp) 2300 { 2301 mb(); /* status block is written to by the chip */ 2302 fp->fp_hc_idx = fp->sb_running_index[SM_RX_ID]; 2303 } 2304 2305 static inline void 2306 bxe_igu_ack_sb_gen(struct bxe_softc *sc, 2307 uint8_t igu_sb_id, 2308 uint8_t segment, 2309 uint16_t index, 2310 uint8_t op, 2311 uint8_t update, 2312 uint32_t igu_addr) 2313 { 2314 struct igu_regular cmd_data = {0}; 2315 2316 cmd_data.sb_id_and_flags = 2317 ((index << IGU_REGULAR_SB_INDEX_SHIFT) | 2318 (segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) | 2319 (update << IGU_REGULAR_BUPDATE_SHIFT) | 2320 (op << IGU_REGULAR_ENABLE_INT_SHIFT)); 2321 2322 BLOGD(sc, DBG_INTR, "write 0x%08x to IGU addr 0x%x\n", 2323 cmd_data.sb_id_and_flags, igu_addr); 2324 REG_WR(sc, igu_addr, cmd_data.sb_id_and_flags); 2325 2326 /* Make sure that ACK is written */ 2327 bus_space_barrier(sc->bar[0].tag, sc->bar[0].handle, 0, 0, 2328 BUS_SPACE_BARRIER_WRITE); 2329 mb(); 2330 } 2331 2332 static inline void 2333 bxe_hc_ack_sb(struct bxe_softc *sc, 2334 uint8_t sb_id, 2335 uint8_t storm, 2336 uint16_t index, 2337 uint8_t op, 2338 uint8_t update) 2339 { 2340 uint32_t hc_addr = (HC_REG_COMMAND_REG + SC_PORT(sc)*32 + 2341 COMMAND_REG_INT_ACK); 2342 struct igu_ack_register igu_ack; 2343 2344 igu_ack.status_block_index = index; 2345 igu_ack.sb_id_and_flags = 2346 ((sb_id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) | 2347 (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) | 2348 (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) | 2349 (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT)); 2350 2351 REG_WR(sc, hc_addr, (*(uint32_t *)&igu_ack)); 2352 2353 /* Make sure that ACK is written */ 2354 bus_space_barrier(sc->bar[0].tag, sc->bar[0].handle, 0, 0, 2355 BUS_SPACE_BARRIER_WRITE); 2356 mb(); 2357 } 2358 2359 static inline void 2360 bxe_ack_sb(struct bxe_softc *sc, 2361 uint8_t igu_sb_id, 2362 uint8_t storm, 2363 uint16_t index, 2364 uint8_t op, 2365 uint8_t update) 2366 { 2367 if (sc->devinfo.int_block == INT_BLOCK_HC) 2368 bxe_hc_ack_sb(sc, igu_sb_id, storm, index, op, update); 2369 else { 2370 uint8_t segment; 2371 if (CHIP_INT_MODE_IS_BC(sc)) { 2372 segment = storm; 2373 } else if (igu_sb_id != sc->igu_dsb_id) { 2374 segment = IGU_SEG_ACCESS_DEF; 2375 } else if (storm == ATTENTION_ID) { 2376 segment = IGU_SEG_ACCESS_ATTN; 2377 } else { 2378 segment = IGU_SEG_ACCESS_DEF; 2379 } 2380 bxe_igu_ack_sb(sc, igu_sb_id, segment, index, op, update); 2381 } 2382 } 2383 2384 static inline uint16_t 2385 bxe_hc_ack_int(struct bxe_softc *sc) 2386 { 2387 uint32_t hc_addr = (HC_REG_COMMAND_REG + SC_PORT(sc)*32 + 2388 COMMAND_REG_SIMD_MASK); 2389 uint32_t result = REG_RD(sc, hc_addr); 2390 2391 mb(); 2392 return (result); 2393 } 2394 2395 static inline uint16_t 2396 bxe_igu_ack_int(struct bxe_softc *sc) 2397 { 2398 uint32_t igu_addr = (BAR_IGU_INTMEM + IGU_REG_SISR_MDPC_WMASK_LSB_UPPER*8); 2399 uint32_t result = REG_RD(sc, igu_addr); 2400 2401 BLOGD(sc, DBG_INTR, "read 0x%08x from IGU addr 0x%x\n", 2402 result, igu_addr); 2403 2404 mb(); 2405 return (result); 2406 } 2407 2408 static inline uint16_t 2409 bxe_ack_int(struct bxe_softc *sc) 2410 { 2411 mb(); 2412 if (sc->devinfo.int_block == INT_BLOCK_HC) { 2413 return (bxe_hc_ack_int(sc)); 2414 } else { 2415 return (bxe_igu_ack_int(sc)); 2416 } 2417 } 2418 2419 static inline int 2420 func_by_vn(struct bxe_softc *sc, 2421 int vn) 2422 { 2423 return (2 * vn + SC_PORT(sc)); 2424 } 2425 2426 /* 2427 * Statistics ID are global per chip/path, while Client IDs for E1x 2428 * are per port. 2429 */ 2430 static inline uint8_t 2431 bxe_stats_id(struct bxe_fastpath *fp) 2432 { 2433 struct bxe_softc *sc = fp->sc; 2434 2435 if (!CHIP_IS_E1x(sc)) { 2436 return (fp->cl_id); 2437 } 2438 2439 return (fp->cl_id + SC_PORT(sc) * FP_SB_MAX_E1x); 2440 } 2441 2442 #endif /* __BXE_H__ */ 2443 2444