1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2007-2014 QLogic Corporation. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 26 * THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #ifndef __BXE_H__ 30 #define __BXE_H__ 31 32 #include <sys/cdefs.h> 33 #include <sys/param.h> 34 #include <sys/kernel.h> 35 #include <sys/systm.h> 36 #include <sys/lock.h> 37 #include <sys/mutex.h> 38 #include <sys/sx.h> 39 #include <sys/module.h> 40 #include <sys/endian.h> 41 #include <sys/types.h> 42 #include <sys/malloc.h> 43 #include <sys/kobj.h> 44 #include <sys/bus.h> 45 #include <sys/rman.h> 46 #include <sys/socket.h> 47 #include <sys/sockio.h> 48 #include <sys/sysctl.h> 49 #include <sys/smp.h> 50 #include <sys/bitstring.h> 51 #include <sys/limits.h> 52 #include <sys/queue.h> 53 #include <sys/taskqueue.h> 54 #include <contrib/zlib/zlib.h> 55 56 #include <net/debugnet.h> 57 #include <net/if.h> 58 #include <net/if_types.h> 59 #include <net/if_arp.h> 60 #include <net/ethernet.h> 61 #include <net/if_dl.h> 62 #include <net/if_var.h> 63 #include <net/if_media.h> 64 #include <net/if_vlan_var.h> 65 #include <net/bpf.h> 66 67 #include <netinet/in.h> 68 #include <netinet/ip.h> 69 #include <netinet/ip6.h> 70 #include <netinet/tcp.h> 71 #include <netinet/udp.h> 72 73 #include <dev/pci/pcireg.h> 74 #include <dev/pci/pcivar.h> 75 76 #include <machine/atomic.h> 77 #include <machine/resource.h> 78 #include <machine/endian.h> 79 #include <machine/bus.h> 80 #include <machine/in_cksum.h> 81 82 #include "device_if.h" 83 #include "bus_if.h" 84 #include "pci_if.h" 85 86 #if _BYTE_ORDER == _LITTLE_ENDIAN 87 #ifndef LITTLE_ENDIAN 88 #define LITTLE_ENDIAN 89 #endif 90 #ifndef __LITTLE_ENDIAN 91 #define __LITTLE_ENDIAN 92 #endif 93 #undef BIG_ENDIAN 94 #undef __BIG_ENDIAN 95 #else /* _BIG_ENDIAN */ 96 #ifndef BIG_ENDIAN 97 #define BIG_ENDIAN 98 #endif 99 #ifndef __BIG_ENDIAN 100 #define __BIG_ENDIAN 101 #endif 102 #undef LITTLE_ENDIAN 103 #undef __LITTLE_ENDIAN 104 #endif 105 106 #include "ecore_mfw_req.h" 107 #include "ecore_fw_defs.h" 108 #include "ecore_hsi.h" 109 #include "ecore_reg.h" 110 #include "bxe_dcb.h" 111 #include "bxe_stats.h" 112 113 #include "bxe_elink.h" 114 115 #define VF_MAC_CREDIT_CNT 0 116 #define VF_VLAN_CREDIT_CNT (0) 117 118 #ifndef ARRAY_SIZE 119 #define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0])) 120 #endif 121 #ifndef ARRSIZE 122 #define ARRSIZE(arr) (sizeof(arr) / sizeof((arr)[0])) 123 #endif 124 #ifndef DIV_ROUND_UP 125 #define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d)) 126 #endif 127 #ifndef roundup 128 #define roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y)) 129 #endif 130 #ifndef ilog2 131 static inline 132 int bxe_ilog2(int x) 133 { 134 int log = 0; 135 while (x >>= 1) log++; 136 return (log); 137 } 138 #define ilog2(x) bxe_ilog2(x) 139 #endif 140 141 #include "ecore_sp.h" 142 143 #define BRCM_VENDORID 0x14e4 144 #define QLOGIC_VENDORID 0x1077 145 #define PCI_ANY_ID (uint16_t)(~0U) 146 147 struct bxe_device_type 148 { 149 uint16_t bxe_vid; 150 uint16_t bxe_did; 151 uint16_t bxe_svid; 152 uint16_t bxe_sdid; 153 char *bxe_name; 154 }; 155 156 #define BCM_PAGE_SHIFT 12 157 #define BCM_PAGE_SIZE (1 << BCM_PAGE_SHIFT) 158 #define BCM_PAGE_MASK (~(BCM_PAGE_SIZE - 1)) 159 #define BCM_PAGE_ALIGN(addr) ((addr + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK) 160 161 #if BCM_PAGE_SIZE != 4096 162 #error Page sizes other than 4KB are unsupported! 163 #endif 164 165 #if (BUS_SPACE_MAXADDR > 0xFFFFFFFF) 166 #define U64_LO(addr) ((uint32_t)(((uint64_t)(addr)) & 0xFFFFFFFF)) 167 #define U64_HI(addr) ((uint32_t)(((uint64_t)(addr)) >> 32)) 168 #else 169 #define U64_LO(addr) ((uint32_t)(addr)) 170 #define U64_HI(addr) (0) 171 #endif 172 #define HILO_U64(hi, lo) ((((uint64_t)(hi)) << 32) + (lo)) 173 174 #define SET_FLAG(value, mask, flag) \ 175 do { \ 176 (value) &= ~(mask); \ 177 (value) |= ((flag) << (mask##_SHIFT)); \ 178 } while (0) 179 180 #define GET_FLAG(value, mask) \ 181 (((value) & (mask)) >> (mask##_SHIFT)) 182 183 #define GET_FIELD(value, fname) \ 184 (((value) & (fname##_MASK)) >> (fname##_SHIFT)) 185 186 #define BXE_MAX_SEGMENTS 12 /* 13-1 for parsing buffer */ 187 #define BXE_TSO_MAX_SEGMENTS 32 188 #define BXE_TSO_MAX_SIZE (65535 + sizeof(struct ether_vlan_header)) 189 #define BXE_TSO_MAX_SEG_SIZE 4096 190 191 /* dropless fc FW/HW related params */ 192 #define BRB_SIZE(sc) (CHIP_IS_E3(sc) ? 1024 : 512) 193 #define MAX_AGG_QS(sc) (CHIP_IS_E1(sc) ? \ 194 ETH_MAX_AGGREGATION_QUEUES_E1 : \ 195 ETH_MAX_AGGREGATION_QUEUES_E1H_E2) 196 #define FW_DROP_LEVEL(sc) (3 + MAX_SPQ_PENDING + MAX_AGG_QS(sc)) 197 #define FW_PREFETCH_CNT 16 198 #define DROPLESS_FC_HEADROOM 100 199 200 /******************/ 201 /* RX SGE defines */ 202 /******************/ 203 204 #define RX_SGE_NUM_PAGES 2 /* must be a power of 2 */ 205 #define RX_SGE_TOTAL_PER_PAGE (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge)) 206 #define RX_SGE_NEXT_PAGE_DESC_CNT 2 207 #define RX_SGE_USABLE_PER_PAGE (RX_SGE_TOTAL_PER_PAGE - RX_SGE_NEXT_PAGE_DESC_CNT) 208 #define RX_SGE_PER_PAGE_MASK (RX_SGE_TOTAL_PER_PAGE - 1) 209 #define RX_SGE_TOTAL (RX_SGE_TOTAL_PER_PAGE * RX_SGE_NUM_PAGES) 210 #define RX_SGE_USABLE (RX_SGE_USABLE_PER_PAGE * RX_SGE_NUM_PAGES) 211 #define RX_SGE_MAX (RX_SGE_TOTAL - 1) 212 #define RX_SGE(x) ((x) & RX_SGE_MAX) 213 214 #define RX_SGE_NEXT(x) \ 215 ((((x) & RX_SGE_PER_PAGE_MASK) == (RX_SGE_USABLE_PER_PAGE - 1)) \ 216 ? (x) + 1 + RX_SGE_NEXT_PAGE_DESC_CNT : (x) + 1) 217 218 #define RX_SGE_MASK_ELEM_SZ 64 219 #define RX_SGE_MASK_ELEM_SHIFT 6 220 #define RX_SGE_MASK_ELEM_MASK ((uint64_t)RX_SGE_MASK_ELEM_SZ - 1) 221 222 /* 223 * Creates a bitmask of all ones in less significant bits. 224 * idx - index of the most significant bit in the created mask. 225 */ 226 #define RX_SGE_ONES_MASK(idx) \ 227 (((uint64_t)0x1 << (((idx) & RX_SGE_MASK_ELEM_MASK) + 1)) - 1) 228 #define RX_SGE_MASK_ELEM_ONE_MASK ((uint64_t)(~0)) 229 230 /* Number of uint64_t elements in SGE mask array. */ 231 #define RX_SGE_MASK_LEN \ 232 ((RX_SGE_NUM_PAGES * RX_SGE_TOTAL_PER_PAGE) / RX_SGE_MASK_ELEM_SZ) 233 #define RX_SGE_MASK_LEN_MASK (RX_SGE_MASK_LEN - 1) 234 #define RX_SGE_NEXT_MASK_ELEM(el) (((el) + 1) & RX_SGE_MASK_LEN_MASK) 235 236 /* 237 * dropless fc calculations for SGEs 238 * Number of required SGEs is the sum of two: 239 * 1. Number of possible opened aggregations (next packet for 240 * these aggregations will probably consume SGE immidiatelly) 241 * 2. Rest of BRB blocks divided by 2 (block will consume new SGE only 242 * after placement on BD for new TPA aggregation) 243 * Takes into account RX_SGE_NEXT_PAGE_DESC_CNT "next" elements on each page 244 */ 245 #define NUM_SGE_REQ(sc) \ 246 (MAX_AGG_QS(sc) + (BRB_SIZE(sc) - MAX_AGG_QS(sc)) / 2) 247 #define NUM_SGE_PG_REQ(sc) \ 248 ((NUM_SGE_REQ(sc) + RX_SGE_USABLE_PER_PAGE - 1) / RX_SGE_USABLE_PER_PAGE) 249 #define SGE_TH_LO(sc) \ 250 (NUM_SGE_REQ(sc) + NUM_SGE_PG_REQ(sc) * RX_SGE_NEXT_PAGE_DESC_CNT) 251 #define SGE_TH_HI(sc) \ 252 (SGE_TH_LO(sc) + DROPLESS_FC_HEADROOM) 253 254 #define PAGES_PER_SGE_SHIFT 0 255 #define PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT) 256 #define SGE_PAGE_SIZE BCM_PAGE_SIZE 257 #define SGE_PAGE_SHIFT BCM_PAGE_SHIFT 258 #define SGE_PAGE_ALIGN(addr) BCM_PAGE_ALIGN(addr) 259 #define SGE_PAGES (SGE_PAGE_SIZE * PAGES_PER_SGE) 260 #define TPA_AGG_SIZE min((8 * SGE_PAGES), 0xffff) 261 262 /*****************/ 263 /* TX BD defines */ 264 /*****************/ 265 266 #define TX_BD_NUM_PAGES 16 /* must be a power of 2 */ 267 #define TX_BD_TOTAL_PER_PAGE (BCM_PAGE_SIZE / sizeof(union eth_tx_bd_types)) 268 #define TX_BD_USABLE_PER_PAGE (TX_BD_TOTAL_PER_PAGE - 1) 269 #define TX_BD_TOTAL (TX_BD_TOTAL_PER_PAGE * TX_BD_NUM_PAGES) 270 #define TX_BD_USABLE (TX_BD_USABLE_PER_PAGE * TX_BD_NUM_PAGES) 271 #define TX_BD_MAX (TX_BD_TOTAL - 1) 272 273 #define TX_BD_NEXT(x) \ 274 ((((x) & TX_BD_USABLE_PER_PAGE) == (TX_BD_USABLE_PER_PAGE - 1)) ? \ 275 ((x) + 2) : ((x) + 1)) 276 #define TX_BD(x) ((x) & TX_BD_MAX) 277 #define TX_BD_PAGE(x) (((x) & ~TX_BD_USABLE_PER_PAGE) >> 8) 278 #define TX_BD_IDX(x) ((x) & TX_BD_USABLE_PER_PAGE) 279 280 /* 281 * Trigger pending transmits when the number of available BDs is greater 282 * than 1/8 of the total number of usable BDs. 283 */ 284 #define BXE_TX_CLEANUP_THRESHOLD (TX_BD_USABLE / 8) 285 #define BXE_TX_TIMEOUT 5 286 287 /*****************/ 288 /* RX BD defines */ 289 /*****************/ 290 291 #define RX_BD_NUM_PAGES 8 /* power of 2 */ 292 #define RX_BD_TOTAL_PER_PAGE (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd)) 293 #define RX_BD_NEXT_PAGE_DESC_CNT 2 294 #define RX_BD_USABLE_PER_PAGE (RX_BD_TOTAL_PER_PAGE - RX_BD_NEXT_PAGE_DESC_CNT) 295 #define RX_BD_PER_PAGE_MASK (RX_BD_TOTAL_PER_PAGE - 1) 296 #define RX_BD_TOTAL (RX_BD_TOTAL_PER_PAGE * RX_BD_NUM_PAGES) 297 #define RX_BD_USABLE (RX_BD_USABLE_PER_PAGE * RX_BD_NUM_PAGES) 298 #define RX_BD_MAX (RX_BD_TOTAL - 1) 299 300 #define RX_BD_NEXT(x) \ 301 ((((x) & RX_BD_PER_PAGE_MASK) == (RX_BD_USABLE_PER_PAGE - 1)) ? \ 302 ((x) + 3) : ((x) + 1)) 303 #define RX_BD(x) ((x) & RX_BD_MAX) 304 #define RX_BD_PAGE(x) (((x) & ~RX_BD_PER_PAGE_MASK) >> 9) 305 #define RX_BD_IDX(x) ((x) & RX_BD_PER_PAGE_MASK) 306 307 /* 308 * dropless fc calculations for BDs 309 * Number of BDs should be as number of buffers in BRB: 310 * Low threshold takes into account RX_BD_NEXT_PAGE_DESC_CNT 311 * "next" elements on each page 312 */ 313 #define NUM_BD_REQ(sc) \ 314 BRB_SIZE(sc) 315 #define NUM_BD_PG_REQ(sc) \ 316 ((NUM_BD_REQ(sc) + RX_BD_USABLE_PER_PAGE - 1) / RX_BD_USABLE_PER_PAGE) 317 #define BD_TH_LO(sc) \ 318 (NUM_BD_REQ(sc) + \ 319 NUM_BD_PG_REQ(sc) * RX_BD_NEXT_PAGE_DESC_CNT + \ 320 FW_DROP_LEVEL(sc)) 321 #define BD_TH_HI(sc) \ 322 (BD_TH_LO(sc) + DROPLESS_FC_HEADROOM) 323 #define MIN_RX_AVAIL(sc) \ 324 ((sc)->dropless_fc ? BD_TH_HI(sc) + 128 : 128) 325 #define MIN_RX_SIZE_TPA_HW(sc) \ 326 (CHIP_IS_E1(sc) ? ETH_MIN_RX_CQES_WITH_TPA_E1 : \ 327 ETH_MIN_RX_CQES_WITH_TPA_E1H_E2) 328 #define MIN_RX_SIZE_NONTPA_HW ETH_MIN_RX_CQES_WITHOUT_TPA 329 #define MIN_RX_SIZE_TPA(sc) \ 330 (max(MIN_RX_SIZE_TPA_HW(sc), MIN_RX_AVAIL(sc))) 331 #define MIN_RX_SIZE_NONTPA(sc) \ 332 (max(MIN_RX_SIZE_NONTPA_HW, MIN_RX_AVAIL(sc))) 333 334 /***************/ 335 /* RCQ defines */ 336 /***************/ 337 338 /* 339 * As long as CQE is X times bigger than BD entry we have to allocate X times 340 * more pages for CQ ring in order to keep it balanced with BD ring 341 */ 342 #define CQE_BD_REL (sizeof(union eth_rx_cqe) / \ 343 sizeof(struct eth_rx_bd)) 344 #define RCQ_NUM_PAGES (RX_BD_NUM_PAGES * CQE_BD_REL) /* power of 2 */ 345 #define RCQ_TOTAL_PER_PAGE (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe)) 346 #define RCQ_NEXT_PAGE_DESC_CNT 1 347 #define RCQ_USABLE_PER_PAGE (RCQ_TOTAL_PER_PAGE - RCQ_NEXT_PAGE_DESC_CNT) 348 #define RCQ_TOTAL (RCQ_TOTAL_PER_PAGE * RCQ_NUM_PAGES) 349 #define RCQ_USABLE (RCQ_USABLE_PER_PAGE * RCQ_NUM_PAGES) 350 #define RCQ_MAX (RCQ_TOTAL - 1) 351 352 #define RCQ_NEXT(x) \ 353 ((((x) & RCQ_USABLE_PER_PAGE) == (RCQ_USABLE_PER_PAGE - 1)) ? \ 354 ((x) + 1 + RCQ_NEXT_PAGE_DESC_CNT) : ((x) + 1)) 355 #define RCQ(x) ((x) & RCQ_MAX) 356 #define RCQ_PAGE(x) (((x) & ~RCQ_USABLE_PER_PAGE) >> 7) 357 #define RCQ_IDX(x) ((x) & RCQ_USABLE_PER_PAGE) 358 359 /* 360 * dropless fc calculations for RCQs 361 * Number of RCQs should be as number of buffers in BRB: 362 * Low threshold takes into account RCQ_NEXT_PAGE_DESC_CNT 363 * "next" elements on each page 364 */ 365 #define NUM_RCQ_REQ(sc) \ 366 BRB_SIZE(sc) 367 #define NUM_RCQ_PG_REQ(sc) \ 368 ((NUM_RCQ_REQ(sc) + RCQ_USABLE_PER_PAGE - 1) / RCQ_USABLE_PER_PAGE) 369 #define RCQ_TH_LO(sc) \ 370 (NUM_RCQ_REQ(sc) + \ 371 NUM_RCQ_PG_REQ(sc) * RCQ_NEXT_PAGE_DESC_CNT + \ 372 FW_DROP_LEVEL(sc)) 373 #define RCQ_TH_HI(sc) \ 374 (RCQ_TH_LO(sc) + DROPLESS_FC_HEADROOM) 375 376 /* This is needed for determening of last_max */ 377 #define SUB_S16(a, b) (int16_t)((int16_t)(a) - (int16_t)(b)) 378 379 #define __SGE_MASK_SET_BIT(el, bit) \ 380 do { \ 381 (el) = ((el) | ((uint64_t)0x1 << (bit))); \ 382 } while (0) 383 384 #define __SGE_MASK_CLEAR_BIT(el, bit) \ 385 do { \ 386 (el) = ((el) & (~((uint64_t)0x1 << (bit)))); \ 387 } while (0) 388 389 #define SGE_MASK_SET_BIT(fp, idx) \ 390 __SGE_MASK_SET_BIT((fp)->sge_mask[(idx) >> RX_SGE_MASK_ELEM_SHIFT], \ 391 ((idx) & RX_SGE_MASK_ELEM_MASK)) 392 393 #define SGE_MASK_CLEAR_BIT(fp, idx) \ 394 __SGE_MASK_CLEAR_BIT((fp)->sge_mask[(idx) >> RX_SGE_MASK_ELEM_SHIFT], \ 395 ((idx) & RX_SGE_MASK_ELEM_MASK)) 396 397 /* Load / Unload modes */ 398 #define LOAD_NORMAL 0 399 #define LOAD_OPEN 1 400 #define LOAD_DIAG 2 401 #define LOAD_LOOPBACK_EXT 3 402 #define UNLOAD_NORMAL 0 403 #define UNLOAD_CLOSE 1 404 #define UNLOAD_RECOVERY 2 405 406 /* Some constants... */ 407 //#define MAX_PATH_NUM 2 408 //#define E2_MAX_NUM_OF_VFS 64 409 //#define E1H_FUNC_MAX 8 410 //#define E2_FUNC_MAX 4 /* per path */ 411 #define MAX_VNIC_NUM 4 412 #define MAX_FUNC_NUM 8 /* common to all chips */ 413 //#define MAX_NDSB HC_SB_MAX_SB_E2 /* max non-default status block */ 414 #define MAX_RSS_CHAINS 16 /* a constant for HW limit */ 415 #define MAX_MSI_VECTOR 8 /* a constant for HW limit */ 416 417 #define ILT_NUM_PAGE_ENTRIES 3072 418 /* 419 * 57710/11 we use whole table since we have 8 functions. 420 * 57712 we have only 4 functions, but use same size per func, so only half 421 * of the table is used. 422 */ 423 #define ILT_PER_FUNC (ILT_NUM_PAGE_ENTRIES / 8) 424 #define FUNC_ILT_BASE(func) (func * ILT_PER_FUNC) 425 /* 426 * the phys address is shifted right 12 bits and has an added 427 * 1=valid bit added to the 53rd bit 428 * then since this is a wide register(TM) 429 * we split it into two 32 bit writes 430 */ 431 #define ONCHIP_ADDR1(x) ((uint32_t)(((uint64_t)x >> 12) & 0xFFFFFFFF)) 432 #define ONCHIP_ADDR2(x) ((uint32_t)((1 << 20) | ((uint64_t)x >> 44))) 433 434 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */ 435 #define ETH_HLEN 14 436 #define ETH_OVERHEAD (ETH_HLEN + 8 + 8) 437 #define ETH_MIN_PACKET_SIZE 60 438 #define ETH_MAX_PACKET_SIZE ETHERMTU /* 1500 */ 439 #define ETH_MAX_JUMBO_PACKET_SIZE 9600 440 /* TCP with Timestamp Option (32) + IPv6 (40) */ 441 #define ETH_MAX_TPA_HEADER_SIZE 72 442 443 /* max supported alignment is 256 (8 shift) */ 444 //#define BXE_RX_ALIGN_SHIFT ((CACHE_LINE_SHIFT < 8) ? CACHE_LINE_SHIFT : 8) 445 #define BXE_RX_ALIGN_SHIFT 8 446 /* FW uses 2 cache lines alignment for start packet and size */ 447 #define BXE_FW_RX_ALIGN_START (1 << BXE_RX_ALIGN_SHIFT) 448 #define BXE_FW_RX_ALIGN_END (1 << BXE_RX_ALIGN_SHIFT) 449 450 #define BXE_PXP_DRAM_ALIGN (BXE_RX_ALIGN_SHIFT - 5) /* XXX ??? */ 451 #define BXE_SET_ERROR_BIT(sc, error) \ 452 { \ 453 (sc)->error_status |= (error); \ 454 } 455 456 struct bxe_bar { 457 struct resource *resource; 458 int rid; 459 bus_space_tag_t tag; 460 bus_space_handle_t handle; 461 vm_offset_t kva; 462 }; 463 464 struct bxe_intr { 465 struct resource *resource; 466 int rid; 467 void *tag; 468 }; 469 470 /* Used to manage DMA allocations. */ 471 struct bxe_dma { 472 struct bxe_softc *sc; 473 bus_addr_t paddr; 474 void *vaddr; 475 bus_dma_tag_t tag; 476 bus_dmamap_t map; 477 bus_dma_segment_t seg; 478 bus_size_t size; 479 int nseg; 480 char msg[32]; 481 }; 482 483 /* attn group wiring */ 484 #define MAX_DYNAMIC_ATTN_GRPS 8 485 486 struct attn_route { 487 uint32_t sig[5]; 488 }; 489 490 struct iro { 491 uint32_t base; 492 uint16_t m1; 493 uint16_t m2; 494 uint16_t m3; 495 uint16_t size; 496 }; 497 498 union bxe_host_hc_status_block { 499 /* pointer to fp status block e2 */ 500 struct host_hc_status_block_e2 *e2_sb; 501 /* pointer to fp status block e1x */ 502 struct host_hc_status_block_e1x *e1x_sb; 503 }; 504 505 union bxe_db_prod { 506 struct doorbell_set_prod data; 507 uint32_t raw; 508 }; 509 510 struct bxe_sw_tx_bd { 511 struct mbuf *m; 512 bus_dmamap_t m_map; 513 uint16_t first_bd; 514 uint8_t flags; 515 /* set on the first BD descriptor when there is a split BD */ 516 #define BXE_TSO_SPLIT_BD (1 << 0) 517 }; 518 519 struct bxe_sw_rx_bd { 520 struct mbuf *m; 521 bus_dmamap_t m_map; 522 }; 523 524 struct bxe_sw_tpa_info { 525 struct bxe_sw_rx_bd bd; 526 bus_dma_segment_t seg; 527 uint8_t state; 528 #define BXE_TPA_STATE_START 1 529 #define BXE_TPA_STATE_STOP 2 530 uint8_t placement_offset; 531 uint16_t parsing_flags; 532 uint16_t vlan_tag; 533 uint16_t len_on_bd; 534 }; 535 536 /* 537 * This is the HSI fastpath data structure. There can be up to MAX_RSS_CHAIN 538 * instances of the fastpath structure when using multiple queues. 539 */ 540 struct bxe_fastpath { 541 /* pointer back to parent structure */ 542 struct bxe_softc *sc; 543 544 struct mtx tx_mtx; 545 char tx_mtx_name[32]; 546 struct mtx rx_mtx; 547 char rx_mtx_name[32]; 548 549 #define BXE_FP_TX_LOCK(fp) mtx_lock(&fp->tx_mtx) 550 #define BXE_FP_TX_UNLOCK(fp) mtx_unlock(&fp->tx_mtx) 551 #define BXE_FP_TX_LOCK_ASSERT(fp) mtx_assert(&fp->tx_mtx, MA_OWNED) 552 #define BXE_FP_TX_TRYLOCK(fp) mtx_trylock(&fp->tx_mtx) 553 554 #define BXE_FP_RX_LOCK(fp) mtx_lock(&fp->rx_mtx) 555 #define BXE_FP_RX_UNLOCK(fp) mtx_unlock(&fp->rx_mtx) 556 #define BXE_FP_RX_LOCK_ASSERT(fp) mtx_assert(&fp->rx_mtx, MA_OWNED) 557 558 /* status block */ 559 struct bxe_dma sb_dma; 560 union bxe_host_hc_status_block status_block; 561 562 /* transmit chain (tx bds) */ 563 struct bxe_dma tx_dma; 564 union eth_tx_bd_types *tx_chain; 565 566 /* receive chain (rx bds) */ 567 struct bxe_dma rx_dma; 568 struct eth_rx_bd *rx_chain; 569 570 /* receive completion queue chain (rcq bds) */ 571 struct bxe_dma rcq_dma; 572 union eth_rx_cqe *rcq_chain; 573 574 /* receive scatter/gather entry chain (for TPA) */ 575 struct bxe_dma rx_sge_dma; 576 struct eth_rx_sge *rx_sge_chain; 577 578 /* tx mbufs */ 579 bus_dma_tag_t tx_mbuf_tag; 580 struct bxe_sw_tx_bd tx_mbuf_chain[TX_BD_TOTAL]; 581 582 /* rx mbufs */ 583 bus_dma_tag_t rx_mbuf_tag; 584 struct bxe_sw_rx_bd rx_mbuf_chain[RX_BD_TOTAL]; 585 bus_dmamap_t rx_mbuf_spare_map; 586 587 /* rx sge mbufs */ 588 bus_dma_tag_t rx_sge_mbuf_tag; 589 struct bxe_sw_rx_bd rx_sge_mbuf_chain[RX_SGE_TOTAL]; 590 bus_dmamap_t rx_sge_mbuf_spare_map; 591 592 /* rx tpa mbufs (use the larger size for TPA queue length) */ 593 int tpa_enable; /* disabled per fastpath upon error */ 594 struct bxe_sw_tpa_info rx_tpa_info[ETH_MAX_AGGREGATION_QUEUES_E1H_E2]; 595 bus_dmamap_t rx_tpa_info_mbuf_spare_map; 596 uint64_t rx_tpa_queue_used; 597 598 uint16_t *sb_index_values; 599 uint16_t *sb_running_index; 600 uint32_t ustorm_rx_prods_offset; 601 602 uint8_t igu_sb_id; /* status block number in HW */ 603 uint8_t fw_sb_id; /* status block number in FW */ 604 605 uint32_t rx_buf_size; 606 int mbuf_alloc_size; 607 608 int state; 609 #define BXE_FP_STATE_CLOSED 0x01 610 #define BXE_FP_STATE_IRQ 0x02 611 #define BXE_FP_STATE_OPENING 0x04 612 #define BXE_FP_STATE_OPEN 0x08 613 #define BXE_FP_STATE_HALTING 0x10 614 #define BXE_FP_STATE_HALTED 0x20 615 616 /* reference back to this fastpath queue number */ 617 uint8_t index; /* this is also the 'cid' */ 618 #define FP_IDX(fp) (fp->index) 619 620 /* interrupt taskqueue (fast) */ 621 struct task tq_task; 622 struct taskqueue *tq; 623 char tq_name[32]; 624 625 struct task tx_task; 626 struct timeout_task tx_timeout_task; 627 628 /* ethernet client ID (each fastpath set of RX/TX/CQE is a client) */ 629 uint8_t cl_id; 630 #define FP_CL_ID(fp) (fp->cl_id) 631 uint8_t cl_qzone_id; 632 633 uint16_t fp_hc_idx; 634 635 /* driver copy of the receive buffer descriptor prod/cons indices */ 636 uint16_t rx_bd_prod; 637 uint16_t rx_bd_cons; 638 639 /* driver copy of the receive completion queue prod/cons indices */ 640 uint16_t rx_cq_prod; 641 uint16_t rx_cq_cons; 642 643 union bxe_db_prod tx_db; 644 645 /* Transmit packet producer index (used in eth_tx_bd). */ 646 uint16_t tx_pkt_prod; 647 uint16_t tx_pkt_cons; 648 649 /* Transmit buffer descriptor producer index. */ 650 uint16_t tx_bd_prod; 651 uint16_t tx_bd_cons; 652 653 uint64_t sge_mask[RX_SGE_MASK_LEN]; 654 uint16_t rx_sge_prod; 655 656 struct tstorm_per_queue_stats old_tclient; 657 struct ustorm_per_queue_stats old_uclient; 658 struct xstorm_per_queue_stats old_xclient; 659 struct bxe_eth_q_stats eth_q_stats; 660 struct bxe_eth_q_stats_old eth_q_stats_old; 661 662 /* Pointer to the receive consumer in the status block */ 663 uint16_t *rx_cq_cons_sb; 664 665 /* Pointer to the transmit consumer in the status block */ 666 uint16_t *tx_cons_sb; 667 668 /* transmit timeout until chip reset */ 669 int watchdog_timer; 670 671 /* Free/used buffer descriptor counters. */ 672 //uint16_t used_tx_bd; 673 674 /* Last maximal completed SGE */ 675 uint16_t last_max_sge; 676 677 //uint16_t rx_sge_free_idx; 678 679 //uint8_t segs; 680 681 #define BXE_BR_SIZE 4096 682 struct buf_ring *tx_br; 683 }; /* struct bxe_fastpath */ 684 685 /* sriov XXX */ 686 #define BXE_MAX_NUM_OF_VFS 64 687 #define BXE_VF_CID_WND 0 688 #define BXE_CIDS_PER_VF (1 << BXE_VF_CID_WND) 689 #define BXE_CLIENTS_PER_VF 1 690 #define BXE_FIRST_VF_CID 256 691 #define BXE_VF_CIDS (BXE_MAX_NUM_OF_VFS * BXE_CIDS_PER_VF) 692 #define BXE_VF_ID_INVALID 0xFF 693 #define IS_SRIOV(sc) 0 694 695 #define GET_NUM_VFS_PER_PATH(sc) 0 696 #define GET_NUM_VFS_PER_PF(sc) 0 697 698 /* maximum number of fast-path interrupt contexts */ 699 #define FP_SB_MAX_E1x 16 700 #define FP_SB_MAX_E2 HC_SB_MAX_SB_E2 701 702 union cdu_context { 703 struct eth_context eth; 704 char pad[1024]; 705 }; 706 707 /* CDU host DB constants */ 708 #define CDU_ILT_PAGE_SZ_HW 2 709 #define CDU_ILT_PAGE_SZ (8192 << CDU_ILT_PAGE_SZ_HW) /* 32K */ 710 #define ILT_PAGE_CIDS (CDU_ILT_PAGE_SZ / sizeof(union cdu_context)) 711 712 #define CNIC_ISCSI_CID_MAX 256 713 #define CNIC_FCOE_CID_MAX 2048 714 #define CNIC_CID_MAX (CNIC_ISCSI_CID_MAX + CNIC_FCOE_CID_MAX) 715 #define CNIC_ILT_LINES DIV_ROUND_UP(CNIC_CID_MAX, ILT_PAGE_CIDS) 716 717 #define QM_ILT_PAGE_SZ_HW 0 718 #define QM_ILT_PAGE_SZ (4096 << QM_ILT_PAGE_SZ_HW) /* 4K */ 719 #define QM_CID_ROUND 1024 720 721 /* TM (timers) host DB constants */ 722 #define TM_ILT_PAGE_SZ_HW 0 723 #define TM_ILT_PAGE_SZ (4096 << TM_ILT_PAGE_SZ_HW) /* 4K */ 724 /*#define TM_CONN_NUM (CNIC_STARTING_CID+CNIC_ISCSI_CXT_MAX) */ 725 #define TM_CONN_NUM 1024 726 #define TM_ILT_SZ (8 * TM_CONN_NUM) 727 #define TM_ILT_LINES DIV_ROUND_UP(TM_ILT_SZ, TM_ILT_PAGE_SZ) 728 729 /* SRC (Searcher) host DB constants */ 730 #define SRC_ILT_PAGE_SZ_HW 0 731 #define SRC_ILT_PAGE_SZ (4096 << SRC_ILT_PAGE_SZ_HW) /* 4K */ 732 #define SRC_HASH_BITS 10 733 #define SRC_CONN_NUM (1 << SRC_HASH_BITS) /* 1024 */ 734 #define SRC_ILT_SZ (sizeof(struct src_ent) * SRC_CONN_NUM) 735 #define SRC_T2_SZ SRC_ILT_SZ 736 #define SRC_ILT_LINES DIV_ROUND_UP(SRC_ILT_SZ, SRC_ILT_PAGE_SZ) 737 738 struct hw_context { 739 struct bxe_dma vcxt_dma; 740 union cdu_context *vcxt; 741 //bus_addr_t cxt_mapping; 742 size_t size; 743 }; 744 745 #define SM_RX_ID 0 746 #define SM_TX_ID 1 747 748 /* defines for multiple tx priority indices */ 749 #define FIRST_TX_ONLY_COS_INDEX 1 750 #define FIRST_TX_COS_INDEX 0 751 752 #define CID_TO_FP(cid, sc) ((cid) % BXE_NUM_NON_CNIC_QUEUES(sc)) 753 754 #define HC_INDEX_ETH_RX_CQ_CONS 1 755 #define HC_INDEX_OOO_TX_CQ_CONS 4 756 #define HC_INDEX_ETH_TX_CQ_CONS_COS0 5 757 #define HC_INDEX_ETH_TX_CQ_CONS_COS1 6 758 #define HC_INDEX_ETH_TX_CQ_CONS_COS2 7 759 #define HC_INDEX_ETH_FIRST_TX_CQ_CONS HC_INDEX_ETH_TX_CQ_CONS_COS0 760 761 /* congestion management fairness mode */ 762 #define CMNG_FNS_NONE 0 763 #define CMNG_FNS_MINMAX 1 764 765 /* CMNG constants, as derived from system spec calculations */ 766 /* default MIN rate in case VNIC min rate is configured to zero - 100Mbps */ 767 #define DEF_MIN_RATE 100 768 /* resolution of the rate shaping timer - 400 usec */ 769 #define RS_PERIODIC_TIMEOUT_USEC 400 770 /* number of bytes in single QM arbitration cycle - 771 * coefficient for calculating the fairness timer */ 772 #define QM_ARB_BYTES 160000 773 /* resolution of Min algorithm 1:100 */ 774 #define MIN_RES 100 775 /* how many bytes above threshold for the minimal credit of Min algorithm*/ 776 #define MIN_ABOVE_THRESH 32768 777 /* fairness algorithm integration time coefficient - 778 * for calculating the actual Tfair */ 779 #define T_FAIR_COEF ((MIN_ABOVE_THRESH + QM_ARB_BYTES) * 8 * MIN_RES) 780 /* memory of fairness algorithm - 2 cycles */ 781 #define FAIR_MEM 2 782 783 #define HC_SEG_ACCESS_DEF 0 /* Driver decision 0-3 */ 784 #define HC_SEG_ACCESS_ATTN 4 785 #define HC_SEG_ACCESS_NORM 0 /* Driver decision 0-1 */ 786 787 /* 788 * The total number of L2 queues, MSIX vectors and HW contexts (CIDs) is 789 * control by the number of fast-path status blocks supported by the 790 * device (HW/FW). Each fast-path status block (FP-SB) aka non-default 791 * status block represents an independent interrupts context that can 792 * serve a regular L2 networking queue. However special L2 queues such 793 * as the FCoE queue do not require a FP-SB and other components like 794 * the CNIC may consume FP-SB reducing the number of possible L2 queues 795 * 796 * If the maximum number of FP-SB available is X then: 797 * a. If CNIC is supported it consumes 1 FP-SB thus the max number of 798 * regular L2 queues is Y=X-1 799 * b. in MF mode the actual number of L2 queues is Y= (X-1/MF_factor) 800 * c. If the FCoE L2 queue is supported the actual number of L2 queues 801 * is Y+1 802 * d. The number of irqs (MSIX vectors) is either Y+1 (one extra for 803 * slow-path interrupts) or Y+2 if CNIC is supported (one additional 804 * FP interrupt context for the CNIC). 805 * e. The number of HW context (CID count) is always X or X+1 if FCoE 806 * L2 queue is supported. the cid for the FCoE L2 queue is always X. 807 * 808 * So this is quite simple for now as no ULPs are supported yet. :-) 809 */ 810 #define BXE_NUM_QUEUES(sc) ((sc)->num_queues) 811 #define BXE_NUM_ETH_QUEUES(sc) BXE_NUM_QUEUES(sc) 812 #define BXE_NUM_NON_CNIC_QUEUES(sc) BXE_NUM_QUEUES(sc) 813 #define BXE_NUM_RX_QUEUES(sc) BXE_NUM_QUEUES(sc) 814 815 #define FOR_EACH_QUEUE(sc, var) \ 816 for ((var) = 0; (var) < BXE_NUM_QUEUES(sc); (var)++) 817 818 #define FOR_EACH_NONDEFAULT_QUEUE(sc, var) \ 819 for ((var) = 1; (var) < BXE_NUM_QUEUES(sc); (var)++) 820 821 #define FOR_EACH_ETH_QUEUE(sc, var) \ 822 for ((var) = 0; (var) < BXE_NUM_ETH_QUEUES(sc); (var)++) 823 824 #define FOR_EACH_NONDEFAULT_ETH_QUEUE(sc, var) \ 825 for ((var) = 1; (var) < BXE_NUM_ETH_QUEUES(sc); (var)++) 826 827 #define FOR_EACH_COS_IN_TX_QUEUE(sc, var) \ 828 for ((var) = 0; (var) < (sc)->max_cos; (var)++) 829 830 #define FOR_EACH_CNIC_QUEUE(sc, var) \ 831 for ((var) = BXE_NUM_ETH_QUEUES(sc); \ 832 (var) < BXE_NUM_QUEUES(sc); \ 833 (var)++) 834 835 enum { 836 OOO_IDX_OFFSET, 837 FCOE_IDX_OFFSET, 838 FWD_IDX_OFFSET, 839 }; 840 841 #define FCOE_IDX(sc) (BXE_NUM_NON_CNIC_QUEUES(sc) + FCOE_IDX_OFFSET) 842 #define bxe_fcoe_fp(sc) (&sc->fp[FCOE_IDX(sc)]) 843 #define bxe_fcoe(sc, var) (bxe_fcoe_fp(sc)->var) 844 #define bxe_fcoe_inner_sp_obj(sc) (&sc->sp_objs[FCOE_IDX(sc)]) 845 #define bxe_fcoe_sp_obj(sc, var) (bxe_fcoe_inner_sp_obj(sc)->var) 846 #define bxe_fcoe_tx(sc, var) (bxe_fcoe_fp(sc)->txdata_ptr[FIRST_TX_COS_INDEX]->var) 847 848 #define OOO_IDX(sc) (BXE_NUM_NON_CNIC_QUEUES(sc) + OOO_IDX_OFFSET) 849 #define bxe_ooo_fp(sc) (&sc->fp[OOO_IDX(sc)]) 850 #define bxe_ooo(sc, var) (bxe_ooo_fp(sc)->var) 851 #define bxe_ooo_inner_sp_obj(sc) (&sc->sp_objs[OOO_IDX(sc)]) 852 #define bxe_ooo_sp_obj(sc, var) (bxe_ooo_inner_sp_obj(sc)->var) 853 854 #define FWD_IDX(sc) (BXE_NUM_NON_CNIC_QUEUES(sc) + FWD_IDX_OFFSET) 855 #define bxe_fwd_fp(sc) (&sc->fp[FWD_IDX(sc)]) 856 #define bxe_fwd(sc, var) (bxe_fwd_fp(sc)->var) 857 #define bxe_fwd_inner_sp_obj(sc) (&sc->sp_objs[FWD_IDX(sc)]) 858 #define bxe_fwd_sp_obj(sc, var) (bxe_fwd_inner_sp_obj(sc)->var) 859 #define bxe_fwd_txdata(fp) (fp->txdata_ptr[FIRST_TX_COS_INDEX]) 860 861 #define IS_ETH_FP(fp) ((fp)->index < BXE_NUM_ETH_QUEUES((fp)->sc)) 862 #define IS_FCOE_FP(fp) ((fp)->index == FCOE_IDX((fp)->sc)) 863 #define IS_FCOE_IDX(idx) ((idx) == FCOE_IDX(sc)) 864 #define IS_FWD_FP(fp) ((fp)->index == FWD_IDX((fp)->sc)) 865 #define IS_FWD_IDX(idx) ((idx) == FWD_IDX(sc)) 866 #define IS_OOO_FP(fp) ((fp)->index == OOO_IDX((fp)->sc)) 867 #define IS_OOO_IDX(idx) ((idx) == OOO_IDX(sc)) 868 869 enum { 870 BXE_PORT_QUERY_IDX, 871 BXE_PF_QUERY_IDX, 872 BXE_FCOE_QUERY_IDX, 873 BXE_FIRST_QUEUE_QUERY_IDX, 874 }; 875 876 struct bxe_fw_stats_req { 877 struct stats_query_header hdr; 878 struct stats_query_entry query[FP_SB_MAX_E1x + 879 BXE_FIRST_QUEUE_QUERY_IDX]; 880 }; 881 882 struct bxe_fw_stats_data { 883 struct stats_counter storm_counters; 884 struct per_port_stats port; 885 struct per_pf_stats pf; 886 //struct fcoe_statistics_params fcoe; 887 struct per_queue_stats queue_stats[1]; 888 }; 889 890 /* IGU MSIX STATISTICS on 57712: 64 for VFs; 4 for PFs; 4 for Attentions */ 891 #define BXE_IGU_STAS_MSG_VF_CNT 64 892 #define BXE_IGU_STAS_MSG_PF_CNT 4 893 894 #define MAX_DMAE_C 8 895 896 /* 897 * For the main interface up/down code paths, a not-so-fine-grained CORE 898 * mutex lock is used. Inside this code are various calls to kernel routines 899 * that can cause a sleep to occur. Namely memory allocations and taskqueue 900 * handling. If using an MTX lock we are *not* allowed to sleep but we can 901 * with an SX lock. This define forces the CORE lock to use and SX lock. 902 * Undefine this and an MTX lock will be used instead. Note that the IOCTL 903 * path can cause problems since it's called by a non-sleepable thread. To 904 * alleviate a potential sleep, any IOCTL processing that results in the 905 * chip/interface being started/stopped/reinitialized, the actual work is 906 * offloaded to a taskqueue. 907 */ 908 #define BXE_CORE_LOCK_SX 909 910 /* 911 * This is the slowpath data structure. It is mapped into non-paged memory 912 * so that the hardware can access it's contents directly and must be page 913 * aligned. 914 */ 915 struct bxe_slowpath { 916 917 /* used by the DMAE command executer */ 918 struct dmae_cmd dmae[MAX_DMAE_C]; 919 920 /* statistics completion */ 921 uint32_t stats_comp; 922 923 /* firmware defined statistics blocks */ 924 union mac_stats mac_stats; 925 struct nig_stats nig_stats; 926 struct host_port_stats port_stats; 927 struct host_func_stats func_stats; 928 //struct host_func_stats func_stats_base; 929 930 /* DMAE completion value and data source/sink */ 931 uint32_t wb_comp; 932 uint32_t wb_data[4]; 933 934 union { 935 struct mac_configuration_cmd e1x; 936 struct eth_classify_rules_ramrod_data e2; 937 } mac_rdata; 938 939 union { 940 struct tstorm_eth_mac_filter_config e1x; 941 struct eth_filter_rules_ramrod_data e2; 942 } rx_mode_rdata; 943 944 struct eth_rss_update_ramrod_data rss_rdata; 945 946 union { 947 struct mac_configuration_cmd e1; 948 struct eth_multicast_rules_ramrod_data e2; 949 } mcast_rdata; 950 951 union { 952 struct function_start_data func_start; 953 struct flow_control_configuration pfc_config; /* for DCBX ramrod */ 954 } func_rdata; 955 956 /* Queue State related ramrods */ 957 union { 958 struct client_init_ramrod_data init_data; 959 struct client_update_ramrod_data update_data; 960 } q_rdata; 961 962 /* 963 * AFEX ramrod can not be a part of func_rdata union because these 964 * events might arrive in parallel to other events from func_rdata. 965 * If they were defined in the same union the data can get corrupted. 966 */ 967 struct afex_vif_list_ramrod_data func_afex_rdata; 968 969 union drv_info_to_mcp drv_info_to_mcp; 970 }; /* struct bxe_slowpath */ 971 972 /* 973 * Port specifc data structure. 974 */ 975 struct bxe_port { 976 /* 977 * Port Management Function (for 57711E only). 978 * When this field is set the driver instance is 979 * responsible for managing port specifc 980 * configurations such as handling link attentions. 981 */ 982 uint32_t pmf; 983 984 /* Ethernet maximum transmission unit. */ 985 uint16_t ether_mtu; 986 987 uint32_t link_config[ELINK_LINK_CONFIG_SIZE]; 988 989 uint32_t ext_phy_config; 990 991 /* Port feature config.*/ 992 uint32_t config; 993 994 /* Defines the features supported by the PHY. */ 995 uint32_t supported[ELINK_LINK_CONFIG_SIZE]; 996 997 /* Defines the features advertised by the PHY. */ 998 uint32_t advertising[ELINK_LINK_CONFIG_SIZE]; 999 #define ADVERTISED_10baseT_Half (1 << 1) 1000 #define ADVERTISED_10baseT_Full (1 << 2) 1001 #define ADVERTISED_100baseT_Half (1 << 3) 1002 #define ADVERTISED_100baseT_Full (1 << 4) 1003 #define ADVERTISED_1000baseT_Half (1 << 5) 1004 #define ADVERTISED_1000baseT_Full (1 << 6) 1005 #define ADVERTISED_TP (1 << 7) 1006 #define ADVERTISED_FIBRE (1 << 8) 1007 #define ADVERTISED_Autoneg (1 << 9) 1008 #define ADVERTISED_Asym_Pause (1 << 10) 1009 #define ADVERTISED_Pause (1 << 11) 1010 #define ADVERTISED_2500baseX_Full (1 << 15) 1011 #define ADVERTISED_10000baseT_Full (1 << 16) 1012 1013 uint32_t phy_addr; 1014 1015 /* Used to synchronize phy accesses. */ 1016 struct mtx phy_mtx; 1017 char phy_mtx_name[32]; 1018 1019 #define BXE_PHY_LOCK(sc) mtx_lock(&sc->port.phy_mtx) 1020 #define BXE_PHY_UNLOCK(sc) mtx_unlock(&sc->port.phy_mtx) 1021 #define BXE_PHY_LOCK_ASSERT(sc) mtx_assert(&sc->port.phy_mtx, MA_OWNED) 1022 1023 /* 1024 * MCP scratchpad address for port specific statistics. 1025 * The device is responsible for writing statistcss 1026 * back to the MCP for use with management firmware such 1027 * as UMP/NC-SI. 1028 */ 1029 uint32_t port_stx; 1030 1031 struct nig_stats old_nig_stats; 1032 }; /* struct bxe_port */ 1033 1034 struct bxe_mf_info { 1035 uint32_t mf_config[E1HVN_MAX]; 1036 1037 uint32_t vnics_per_port; /* 1, 2 or 4 */ 1038 uint32_t multi_vnics_mode; /* can be set even if vnics_per_port = 1 */ 1039 uint32_t path_has_ovlan; /* MF mode in the path (can be different than the MF mode of the function */ 1040 1041 #define IS_MULTI_VNIC(sc) ((sc)->devinfo.mf_info.multi_vnics_mode) 1042 #define VNICS_PER_PORT(sc) ((sc)->devinfo.mf_info.vnics_per_port) 1043 #define VNICS_PER_PATH(sc) \ 1044 ((sc)->devinfo.mf_info.vnics_per_port * \ 1045 ((CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 1 )) 1046 1047 uint8_t min_bw[MAX_VNIC_NUM]; 1048 uint8_t max_bw[MAX_VNIC_NUM]; 1049 1050 uint16_t ext_id; /* vnic outer vlan or VIF ID */ 1051 #define VALID_OVLAN(ovlan) ((ovlan) <= 4096) 1052 #define INVALID_VIF_ID 0xFFFF 1053 #define OVLAN(sc) ((sc)->devinfo.mf_info.ext_id) 1054 #define VIF_ID(sc) ((sc)->devinfo.mf_info.ext_id) 1055 1056 uint16_t default_vlan; 1057 #define NIV_DEFAULT_VLAN(sc) ((sc)->devinfo.mf_info.default_vlan) 1058 1059 uint8_t niv_allowed_priorities; 1060 #define NIV_ALLOWED_PRIORITIES(sc) ((sc)->devinfo.mf_info.niv_allowed_priorities) 1061 1062 uint8_t niv_default_cos; 1063 #define NIV_DEFAULT_COS(sc) ((sc)->devinfo.mf_info.niv_default_cos) 1064 1065 uint8_t niv_mba_enabled; 1066 1067 enum mf_cfg_afex_vlan_mode afex_vlan_mode; 1068 #define AFEX_VLAN_MODE(sc) ((sc)->devinfo.mf_info.afex_vlan_mode) 1069 int afex_def_vlan_tag; 1070 uint32_t pending_max; 1071 1072 uint16_t flags; 1073 #define MF_INFO_VALID_MAC 0x0001 1074 1075 uint8_t mf_mode; /* Switch-Dependent or Switch-Independent */ 1076 #define IS_MF(sc) \ 1077 (IS_MULTI_VNIC(sc) && \ 1078 ((sc)->devinfo.mf_info.mf_mode != 0)) 1079 #define IS_MF_SD(sc) \ 1080 (IS_MULTI_VNIC(sc) && \ 1081 ((sc)->devinfo.mf_info.mf_mode == MULTI_FUNCTION_SD)) 1082 #define IS_MF_SI(sc) \ 1083 (IS_MULTI_VNIC(sc) && \ 1084 ((sc)->devinfo.mf_info.mf_mode == MULTI_FUNCTION_SI)) 1085 #define IS_MF_AFEX(sc) \ 1086 (IS_MULTI_VNIC(sc) && \ 1087 ((sc)->devinfo.mf_info.mf_mode == MULTI_FUNCTION_AFEX)) 1088 #define IS_MF_SD_MODE(sc) IS_MF_SD(sc) 1089 #define IS_MF_SI_MODE(sc) IS_MF_SI(sc) 1090 #define IS_MF_AFEX_MODE(sc) IS_MF_AFEX(sc) 1091 1092 uint32_t mf_protos_supported; 1093 #define MF_PROTO_SUPPORT_ETHERNET 0x1 1094 #define MF_PROTO_SUPPORT_ISCSI 0x2 1095 #define MF_PROTO_SUPPORT_FCOE 0x4 1096 }; /* struct bxe_mf_info */ 1097 1098 /* Device information data structure. */ 1099 struct bxe_devinfo { 1100 /* PCIe info */ 1101 uint16_t vendor_id; 1102 uint16_t device_id; 1103 uint16_t subvendor_id; 1104 uint16_t subdevice_id; 1105 1106 /* 1107 * chip_id = 0b'CCCCCCCCCCCCCCCCRRRRMMMMMMMMBBBB' 1108 * C = Chip Number (bits 16-31) 1109 * R = Chip Revision (bits 12-15) 1110 * M = Chip Metal (bits 4-11) 1111 * B = Chip Bond ID (bits 0-3) 1112 */ 1113 uint32_t chip_id; 1114 #define CHIP_ID(sc) ((sc)->devinfo.chip_id & 0xffff0000) 1115 #define CHIP_NUM(sc) ((sc)->devinfo.chip_id >> 16) 1116 /* device ids */ 1117 #define CHIP_NUM_57710 0x164e 1118 #define CHIP_NUM_57711 0x164f 1119 #define CHIP_NUM_57711E 0x1650 1120 #define CHIP_NUM_57712 0x1662 1121 #define CHIP_NUM_57712_MF 0x1663 1122 #define CHIP_NUM_57712_VF 0x166f 1123 #define CHIP_NUM_57800 0x168a 1124 #define CHIP_NUM_57800_MF 0x16a5 1125 #define CHIP_NUM_57800_VF 0x16a9 1126 #define CHIP_NUM_57810 0x168e 1127 #define CHIP_NUM_57810_MF 0x16ae 1128 #define CHIP_NUM_57810_VF 0x16af 1129 #define CHIP_NUM_57811 0x163d 1130 #define CHIP_NUM_57811_MF 0x163e 1131 #define CHIP_NUM_57811_VF 0x163f 1132 #define CHIP_NUM_57840_OBS 0x168d 1133 #define CHIP_NUM_57840_OBS_MF 0x16ab 1134 #define CHIP_NUM_57840_4_10 0x16a1 1135 #define CHIP_NUM_57840_2_20 0x16a2 1136 #define CHIP_NUM_57840_MF 0x16a4 1137 #define CHIP_NUM_57840_VF 0x16ad 1138 1139 #define CHIP_REV_SHIFT 12 1140 #define CHIP_REV_MASK (0xF << CHIP_REV_SHIFT) 1141 #define CHIP_REV(sc) ((sc)->devinfo.chip_id & CHIP_REV_MASK) 1142 1143 #define CHIP_REV_Ax (0x0 << CHIP_REV_SHIFT) 1144 #define CHIP_REV_Bx (0x1 << CHIP_REV_SHIFT) 1145 #define CHIP_REV_Cx (0x2 << CHIP_REV_SHIFT) 1146 1147 #define CHIP_REV_IS_SLOW(sc) \ 1148 (CHIP_REV(sc) > 0x00005000) 1149 #define CHIP_REV_IS_FPGA(sc) \ 1150 (CHIP_REV_IS_SLOW(sc) && (CHIP_REV(sc) & 0x00001000)) 1151 #define CHIP_REV_IS_EMUL(sc) \ 1152 (CHIP_REV_IS_SLOW(sc) && !(CHIP_REV(sc) & 0x00001000)) 1153 #define CHIP_REV_IS_ASIC(sc) \ 1154 (!CHIP_REV_IS_SLOW(sc)) 1155 1156 #define CHIP_METAL(sc) ((sc->devinfo.chip_id) & 0x00000ff0) 1157 #define CHIP_BOND_ID(sc) ((sc->devinfo.chip_id) & 0x0000000f) 1158 1159 #define CHIP_IS_E1(sc) (CHIP_NUM(sc) == CHIP_NUM_57710) 1160 #define CHIP_IS_57710(sc) (CHIP_NUM(sc) == CHIP_NUM_57710) 1161 #define CHIP_IS_57711(sc) (CHIP_NUM(sc) == CHIP_NUM_57711) 1162 #define CHIP_IS_57711E(sc) (CHIP_NUM(sc) == CHIP_NUM_57711E) 1163 #define CHIP_IS_E1H(sc) ((CHIP_IS_57711(sc)) || \ 1164 (CHIP_IS_57711E(sc))) 1165 #define CHIP_IS_E1x(sc) (CHIP_IS_E1((sc)) || \ 1166 CHIP_IS_E1H((sc))) 1167 1168 #define CHIP_IS_57712(sc) (CHIP_NUM(sc) == CHIP_NUM_57712) 1169 #define CHIP_IS_57712_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57712_MF) 1170 #define CHIP_IS_57712_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57712_VF) 1171 #define CHIP_IS_E2(sc) (CHIP_IS_57712(sc) || \ 1172 CHIP_IS_57712_MF(sc)) 1173 1174 #define CHIP_IS_57800(sc) (CHIP_NUM(sc) == CHIP_NUM_57800) 1175 #define CHIP_IS_57800_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57800_MF) 1176 #define CHIP_IS_57800_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57800_VF) 1177 #define CHIP_IS_57810(sc) (CHIP_NUM(sc) == CHIP_NUM_57810) 1178 #define CHIP_IS_57810_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57810_MF) 1179 #define CHIP_IS_57810_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57810_VF) 1180 #define CHIP_IS_57811(sc) (CHIP_NUM(sc) == CHIP_NUM_57811) 1181 #define CHIP_IS_57811_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57811_MF) 1182 #define CHIP_IS_57811_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57811_VF) 1183 #define CHIP_IS_57840(sc) ((CHIP_NUM(sc) == CHIP_NUM_57840_OBS) || \ 1184 (CHIP_NUM(sc) == CHIP_NUM_57840_4_10) || \ 1185 (CHIP_NUM(sc) == CHIP_NUM_57840_2_20)) 1186 #define CHIP_IS_57840_MF(sc) ((CHIP_NUM(sc) == CHIP_NUM_57840_OBS_MF) || \ 1187 (CHIP_NUM(sc) == CHIP_NUM_57840_MF)) 1188 #define CHIP_IS_57840_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57840_VF) 1189 1190 #define CHIP_IS_E3(sc) (CHIP_IS_57800(sc) || \ 1191 CHIP_IS_57800_MF(sc) || \ 1192 CHIP_IS_57800_VF(sc) || \ 1193 CHIP_IS_57810(sc) || \ 1194 CHIP_IS_57810_MF(sc) || \ 1195 CHIP_IS_57810_VF(sc) || \ 1196 CHIP_IS_57811(sc) || \ 1197 CHIP_IS_57811_MF(sc) || \ 1198 CHIP_IS_57811_VF(sc) || \ 1199 CHIP_IS_57840(sc) || \ 1200 CHIP_IS_57840_MF(sc) || \ 1201 CHIP_IS_57840_VF(sc)) 1202 #define CHIP_IS_E3A0(sc) (CHIP_IS_E3(sc) && \ 1203 (CHIP_REV(sc) == CHIP_REV_Ax)) 1204 #define CHIP_IS_E3B0(sc) (CHIP_IS_E3(sc) && \ 1205 (CHIP_REV(sc) == CHIP_REV_Bx)) 1206 1207 #define USES_WARPCORE(sc) (CHIP_IS_E3(sc)) 1208 #define CHIP_IS_E2E3(sc) (CHIP_IS_E2(sc) || \ 1209 CHIP_IS_E3(sc)) 1210 1211 #define CHIP_IS_MF_CAP(sc) (CHIP_IS_57711E(sc) || \ 1212 CHIP_IS_57712_MF(sc) || \ 1213 CHIP_IS_E3(sc)) 1214 1215 #define IS_VF(sc) (CHIP_IS_57712_VF(sc) || \ 1216 CHIP_IS_57800_VF(sc) || \ 1217 CHIP_IS_57810_VF(sc) || \ 1218 CHIP_IS_57840_VF(sc)) 1219 #define IS_PF(sc) (!IS_VF(sc)) 1220 1221 /* 1222 * This define is used in two main places: 1223 * 1. In the early stages of nic_load, to know if to configure Parser/Searcher 1224 * to nic-only mode or to offload mode. Offload mode is configured if either 1225 * the chip is E1x (where NIC_MODE register is not applicable), or if cnic 1226 * already registered for this port (which means that the user wants storage 1227 * services). 1228 * 2. During cnic-related load, to know if offload mode is already configured 1229 * in the HW or needs to be configrued. Since the transition from nic-mode to 1230 * offload-mode in HW causes traffic coruption, nic-mode is configured only 1231 * in ports on which storage services where never requested. 1232 */ 1233 #define CONFIGURE_NIC_MODE(sc) (!CHIP_IS_E1x(sc) && !CNIC_ENABLED(sc)) 1234 1235 uint8_t chip_port_mode; 1236 #define CHIP_4_PORT_MODE 0x0 1237 #define CHIP_2_PORT_MODE 0x1 1238 #define CHIP_PORT_MODE_NONE 0x2 1239 #define CHIP_PORT_MODE(sc) ((sc)->devinfo.chip_port_mode) 1240 #define CHIP_IS_MODE_4_PORT(sc) (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) 1241 1242 uint8_t int_block; 1243 #define INT_BLOCK_HC 0 1244 #define INT_BLOCK_IGU 1 1245 #define INT_BLOCK_MODE_NORMAL 0 1246 #define INT_BLOCK_MODE_BW_COMP 2 1247 #define CHIP_INT_MODE_IS_NBC(sc) \ 1248 (!CHIP_IS_E1x(sc) && \ 1249 !((sc)->devinfo.int_block & INT_BLOCK_MODE_BW_COMP)) 1250 #define CHIP_INT_MODE_IS_BC(sc) (!CHIP_INT_MODE_IS_NBC(sc)) 1251 1252 uint32_t shmem_base; 1253 uint32_t shmem2_base; 1254 uint32_t bc_ver; 1255 char bc_ver_str[32]; 1256 uint32_t mf_cfg_base; /* bootcode shmem address in BAR memory */ 1257 struct bxe_mf_info mf_info; 1258 1259 int flash_size; 1260 #define NVRAM_1MB_SIZE 0x20000 1261 #define NVRAM_TIMEOUT_COUNT 30000 1262 #define NVRAM_PAGE_SIZE 256 1263 1264 /* PCIe capability information */ 1265 uint32_t pcie_cap_flags; 1266 #define BXE_PM_CAPABLE_FLAG 0x00000001 1267 #define BXE_PCIE_CAPABLE_FLAG 0x00000002 1268 #define BXE_MSI_CAPABLE_FLAG 0x00000004 1269 #define BXE_MSIX_CAPABLE_FLAG 0x00000008 1270 uint16_t pcie_pm_cap_reg; 1271 uint16_t pcie_pcie_cap_reg; 1272 //uint16_t pcie_devctl; 1273 uint16_t pcie_link_width; 1274 uint16_t pcie_link_speed; 1275 uint16_t pcie_msi_cap_reg; 1276 uint16_t pcie_msix_cap_reg; 1277 1278 /* device configuration read from bootcode shared memory */ 1279 uint32_t hw_config; 1280 uint32_t hw_config2; 1281 }; /* struct bxe_devinfo */ 1282 1283 struct bxe_sp_objs { 1284 struct ecore_vlan_mac_obj mac_obj; /* MACs object */ 1285 struct ecore_queue_sp_obj q_obj; /* Queue State object */ 1286 }; /* struct bxe_sp_objs */ 1287 1288 /* 1289 * Data that will be used to create a link report message. We will keep the 1290 * data used for the last link report in order to prevent reporting the same 1291 * link parameters twice. 1292 */ 1293 struct bxe_link_report_data { 1294 uint16_t line_speed; /* Effective line speed */ 1295 unsigned long link_report_flags; /* BXE_LINK_REPORT_XXX flags */ 1296 }; 1297 enum { 1298 BXE_LINK_REPORT_FULL_DUPLEX, 1299 BXE_LINK_REPORT_LINK_DOWN, 1300 BXE_LINK_REPORT_RX_FC_ON, 1301 BXE_LINK_REPORT_TX_FC_ON 1302 }; 1303 1304 /* Top level device private data structure. */ 1305 struct bxe_softc { 1306 /* 1307 * First entry must be a pointer to the BSD ifnet struct which 1308 * has a first element of 'void *if_softc' (which is us). XXX 1309 */ 1310 if_t ifp; 1311 struct ifmedia ifmedia; /* network interface media structure */ 1312 int media; 1313 1314 volatile int state; /* device state */ 1315 #define BXE_STATE_CLOSED 0x0000 1316 #define BXE_STATE_OPENING_WAITING_LOAD 0x1000 1317 #define BXE_STATE_OPENING_WAITING_PORT 0x2000 1318 #define BXE_STATE_OPEN 0x3000 1319 #define BXE_STATE_CLOSING_WAITING_HALT 0x4000 1320 #define BXE_STATE_CLOSING_WAITING_DELETE 0x5000 1321 #define BXE_STATE_CLOSING_WAITING_UNLOAD 0x6000 1322 #define BXE_STATE_DISABLED 0xD000 1323 #define BXE_STATE_DIAG 0xE000 1324 #define BXE_STATE_ERROR 0xF000 1325 1326 int flags; 1327 #define BXE_ONE_PORT_FLAG 0x00000001 1328 #define BXE_NO_ISCSI 0x00000002 1329 #define BXE_NO_FCOE 0x00000004 1330 #define BXE_ONE_PORT(sc) (sc->flags & BXE_ONE_PORT_FLAG) 1331 //#define BXE_NO_WOL_FLAG 0x00000008 1332 //#define BXE_USING_DAC_FLAG 0x00000010 1333 //#define BXE_USING_MSIX_FLAG 0x00000020 1334 //#define BXE_USING_MSI_FLAG 0x00000040 1335 //#define BXE_DISABLE_MSI_FLAG 0x00000080 1336 #define BXE_NO_MCP_FLAG 0x00000200 1337 #define BXE_NOMCP(sc) (sc->flags & BXE_NO_MCP_FLAG) 1338 //#define BXE_SAFC_TX_FLAG 0x00000400 1339 #define BXE_MF_FUNC_DIS 0x00000800 1340 #define BXE_TX_SWITCHING 0x00001000 1341 #define BXE_NO_PULSE 0x00002000 1342 1343 unsigned long debug; /* per-instance debug logging config */ 1344 1345 #define MAX_BARS 5 1346 struct bxe_bar bar[MAX_BARS]; /* map BARs 0, 2, 4 */ 1347 1348 uint16_t doorbell_size; 1349 1350 /* periodic timer callout */ 1351 #define PERIODIC_STOP 0 1352 #define PERIODIC_GO 1 1353 volatile unsigned long periodic_flags; 1354 struct callout periodic_callout; 1355 1356 /* chip start/stop/reset taskqueue */ 1357 #define CHIP_TQ_NONE 0 1358 #define CHIP_TQ_START 1 1359 #define CHIP_TQ_STOP 2 1360 #define CHIP_TQ_REINIT 3 1361 volatile unsigned long chip_tq_flags; 1362 struct task chip_tq_task; 1363 struct taskqueue *chip_tq; 1364 char chip_tq_name[32]; 1365 1366 struct timeout_task sp_err_timeout_task; 1367 1368 /* slowpath interrupt taskqueue */ 1369 struct task sp_tq_task; 1370 struct taskqueue *sp_tq; 1371 char sp_tq_name[32]; 1372 1373 struct bxe_fastpath fp[MAX_RSS_CHAINS]; 1374 struct bxe_sp_objs sp_objs[MAX_RSS_CHAINS]; 1375 1376 device_t dev; /* parent device handle */ 1377 uint8_t unit; /* driver instance number */ 1378 1379 int pcie_bus; /* PCIe bus number */ 1380 int pcie_device; /* PCIe device/slot number */ 1381 int pcie_func; /* PCIe function number */ 1382 1383 uint8_t pfunc_rel; /* function relative */ 1384 uint8_t pfunc_abs; /* function absolute */ 1385 uint8_t path_id; /* function absolute */ 1386 #define SC_PATH(sc) (sc->path_id) 1387 #define SC_PORT(sc) (sc->pfunc_rel & 1) 1388 #define SC_FUNC(sc) (sc->pfunc_rel) 1389 #define SC_ABS_FUNC(sc) (sc->pfunc_abs) 1390 #define SC_VN(sc) (sc->pfunc_rel >> 1) 1391 #define SC_L_ID(sc) (SC_VN(sc) << 2) 1392 #define PORT_ID(sc) SC_PORT(sc) 1393 #define PATH_ID(sc) SC_PATH(sc) 1394 #define VNIC_ID(sc) SC_VN(sc) 1395 #define FUNC_ID(sc) SC_FUNC(sc) 1396 #define ABS_FUNC_ID(sc) SC_ABS_FUNC(sc) 1397 #define SC_FW_MB_IDX_VN(sc, vn) \ 1398 (SC_PORT(sc) + (vn) * \ 1399 ((CHIP_IS_E1x(sc) || (CHIP_IS_MODE_4_PORT(sc))) ? 2 : 1)) 1400 #define SC_FW_MB_IDX(sc) SC_FW_MB_IDX_VN(sc, SC_VN(sc)) 1401 1402 int if_capen; /* enabled interface capabilities */ 1403 1404 struct bxe_devinfo devinfo; 1405 char fw_ver_str[32]; 1406 char mf_mode_str[32]; 1407 char pci_link_str[32]; 1408 1409 const struct iro *iro_array; 1410 1411 #ifdef BXE_CORE_LOCK_SX 1412 struct sx core_sx; 1413 char core_sx_name[32]; 1414 #else 1415 struct mtx core_mtx; 1416 char core_mtx_name[32]; 1417 #endif 1418 struct mtx sp_mtx; 1419 char sp_mtx_name[32]; 1420 struct mtx dmae_mtx; 1421 char dmae_mtx_name[32]; 1422 struct mtx fwmb_mtx; 1423 char fwmb_mtx_name[32]; 1424 struct mtx print_mtx; 1425 char print_mtx_name[32]; 1426 struct mtx stats_mtx; 1427 char stats_mtx_name[32]; 1428 struct mtx mcast_mtx; 1429 char mcast_mtx_name[32]; 1430 1431 #ifdef BXE_CORE_LOCK_SX 1432 #define BXE_CORE_TRYLOCK(sc) sx_try_xlock(&sc->core_sx) 1433 #define BXE_CORE_LOCK(sc) sx_xlock(&sc->core_sx) 1434 #define BXE_CORE_UNLOCK(sc) sx_xunlock(&sc->core_sx) 1435 #define BXE_CORE_LOCK_ASSERT(sc) sx_assert(&sc->core_sx, SA_XLOCKED) 1436 #else 1437 #define BXE_CORE_TRYLOCK(sc) mtx_trylock(&sc->core_mtx) 1438 #define BXE_CORE_LOCK(sc) mtx_lock(&sc->core_mtx) 1439 #define BXE_CORE_UNLOCK(sc) mtx_unlock(&sc->core_mtx) 1440 #define BXE_CORE_LOCK_ASSERT(sc) mtx_assert(&sc->core_mtx, MA_OWNED) 1441 #endif 1442 1443 #define BXE_SP_LOCK(sc) mtx_lock(&sc->sp_mtx) 1444 #define BXE_SP_UNLOCK(sc) mtx_unlock(&sc->sp_mtx) 1445 #define BXE_SP_LOCK_ASSERT(sc) mtx_assert(&sc->sp_mtx, MA_OWNED) 1446 1447 #define BXE_DMAE_LOCK(sc) mtx_lock(&sc->dmae_mtx) 1448 #define BXE_DMAE_UNLOCK(sc) mtx_unlock(&sc->dmae_mtx) 1449 #define BXE_DMAE_LOCK_ASSERT(sc) mtx_assert(&sc->dmae_mtx, MA_OWNED) 1450 1451 #define BXE_FWMB_LOCK(sc) mtx_lock(&sc->fwmb_mtx) 1452 #define BXE_FWMB_UNLOCK(sc) mtx_unlock(&sc->fwmb_mtx) 1453 #define BXE_FWMB_LOCK_ASSERT(sc) mtx_assert(&sc->fwmb_mtx, MA_OWNED) 1454 1455 #define BXE_PRINT_LOCK(sc) mtx_lock(&sc->print_mtx) 1456 #define BXE_PRINT_UNLOCK(sc) mtx_unlock(&sc->print_mtx) 1457 #define BXE_PRINT_LOCK_ASSERT(sc) mtx_assert(&sc->print_mtx, MA_OWNED) 1458 1459 #define BXE_STATS_LOCK(sc) mtx_lock(&sc->stats_mtx) 1460 #define BXE_STATS_UNLOCK(sc) mtx_unlock(&sc->stats_mtx) 1461 #define BXE_STATS_LOCK_ASSERT(sc) mtx_assert(&sc->stats_mtx, MA_OWNED) 1462 1463 #define BXE_MCAST_LOCK(sc) mtx_lock(&sc->mcast_mtx); 1464 #define BXE_MCAST_UNLOCK(sc) mtx_unlock(&sc->mcast_mtx); 1465 #define BXE_MCAST_LOCK_ASSERT(sc) mtx_assert(&sc->mcast_mtx, MA_OWNED) 1466 1467 int dmae_ready; 1468 #define DMAE_READY(sc) (sc->dmae_ready) 1469 1470 struct ecore_credit_pool_obj vlans_pool; 1471 struct ecore_credit_pool_obj macs_pool; 1472 struct ecore_rx_mode_obj rx_mode_obj; 1473 struct ecore_mcast_obj mcast_obj; 1474 struct ecore_rss_config_obj rss_conf_obj; 1475 struct ecore_func_sp_obj func_obj; 1476 1477 uint16_t fw_seq; 1478 uint16_t fw_drv_pulse_wr_seq; 1479 uint32_t func_stx; 1480 1481 struct elink_params link_params; 1482 struct elink_vars link_vars; 1483 uint32_t link_cnt; 1484 struct bxe_link_report_data last_reported_link; 1485 char mac_addr_str[32]; 1486 1487 int last_reported_link_state; 1488 1489 int tx_ring_size; 1490 int rx_ring_size; 1491 int wol; 1492 1493 int is_leader; 1494 int recovery_state; 1495 #define BXE_RECOVERY_DONE 1 1496 #define BXE_RECOVERY_INIT 2 1497 #define BXE_RECOVERY_WAIT 3 1498 #define BXE_RECOVERY_FAILED 4 1499 #define BXE_RECOVERY_NIC_LOADING 5 1500 1501 #define BXE_ERR_TXQ_STUCK 0x1 /* Tx queue stuck detected by driver. */ 1502 #define BXE_ERR_MISC 0x2 /* MISC ERR */ 1503 #define BXE_ERR_PARITY 0x4 /* Parity error detected. */ 1504 #define BXE_ERR_STATS_TO 0x8 /* Statistics timeout detected. */ 1505 #define BXE_ERR_MC_ASSERT 0x10 /* MC assert attention received. */ 1506 #define BXE_ERR_PANIC 0x20 /* Driver asserted. */ 1507 #define BXE_ERR_MCP_ASSERT 0x40 /* MCP assert attention received. No Recovery*/ 1508 #define BXE_ERR_GLOBAL 0x80 /* PCIe/PXP/IGU/MISC/NIG device blocks error- needs PCIe/Fundamental reset */ 1509 uint32_t error_status; 1510 1511 uint32_t rx_mode; 1512 #define BXE_RX_MODE_NONE 0 1513 #define BXE_RX_MODE_NORMAL 1 1514 #define BXE_RX_MODE_ALLMULTI 2 1515 #define BXE_RX_MODE_PROMISC 3 1516 #define BXE_MAX_MULTICAST 64 1517 1518 struct bxe_port port; 1519 1520 struct cmng_init cmng; 1521 1522 /* user configs */ 1523 int num_queues; 1524 int max_rx_bufs; 1525 int hc_rx_ticks; 1526 int hc_tx_ticks; 1527 int rx_budget; 1528 int max_aggregation_size; 1529 int mrrs; 1530 int autogreeen; 1531 #define AUTO_GREEN_HW_DEFAULT 0 1532 #define AUTO_GREEN_FORCE_ON 1 1533 #define AUTO_GREEN_FORCE_OFF 2 1534 int interrupt_mode; 1535 #define INTR_MODE_INTX 0 1536 #define INTR_MODE_MSI 1 1537 #define INTR_MODE_MSIX 2 1538 int udp_rss; 1539 1540 /* interrupt allocations */ 1541 struct bxe_intr intr[MAX_RSS_CHAINS+1]; 1542 int intr_count; 1543 uint8_t igu_dsb_id; 1544 uint8_t igu_base_sb; 1545 uint8_t igu_sb_cnt; 1546 //uint8_t min_msix_vec_cnt; 1547 uint32_t igu_base_addr; 1548 //bus_addr_t def_status_blk_mapping; 1549 uint8_t base_fw_ndsb; 1550 #define DEF_SB_IGU_ID 16 1551 #define DEF_SB_ID HC_SP_SB_ID 1552 1553 /* parent bus DMA tag */ 1554 bus_dma_tag_t parent_dma_tag; 1555 1556 /* default status block */ 1557 struct bxe_dma def_sb_dma; 1558 struct host_sp_status_block *def_sb; 1559 uint16_t def_idx; 1560 uint16_t def_att_idx; 1561 uint32_t attn_state; 1562 struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS]; 1563 1564 /* general SP events - stats query, cfc delete, etc */ 1565 #define HC_SP_INDEX_ETH_DEF_CONS 3 1566 /* EQ completions */ 1567 #define HC_SP_INDEX_EQ_CONS 7 1568 /* FCoE L2 connection completions */ 1569 #define HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS 6 1570 #define HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS 4 1571 /* iSCSI L2 */ 1572 #define HC_SP_INDEX_ETH_ISCSI_CQ_CONS 5 1573 #define HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS 1 1574 1575 /* event queue */ 1576 struct bxe_dma eq_dma; 1577 union event_ring_elem *eq; 1578 uint16_t eq_prod; 1579 uint16_t eq_cons; 1580 uint16_t *eq_cons_sb; 1581 #define NUM_EQ_PAGES 1 /* must be a power of 2 */ 1582 #define EQ_DESC_CNT_PAGE (BCM_PAGE_SIZE / sizeof(union event_ring_elem)) 1583 #define EQ_DESC_MAX_PAGE (EQ_DESC_CNT_PAGE - 1) 1584 #define NUM_EQ_DESC (EQ_DESC_CNT_PAGE * NUM_EQ_PAGES) 1585 #define EQ_DESC_MASK (NUM_EQ_DESC - 1) 1586 #define MAX_EQ_AVAIL (EQ_DESC_MAX_PAGE * NUM_EQ_PAGES - 2) 1587 /* depends on EQ_DESC_CNT_PAGE being a power of 2 */ 1588 #define NEXT_EQ_IDX(x) \ 1589 ((((x) & EQ_DESC_MAX_PAGE) == (EQ_DESC_MAX_PAGE - 1)) ? \ 1590 ((x) + 2) : ((x) + 1)) 1591 /* depends on the above and on NUM_EQ_PAGES being a power of 2 */ 1592 #define EQ_DESC(x) ((x) & EQ_DESC_MASK) 1593 1594 /* slow path */ 1595 struct bxe_dma sp_dma; 1596 struct bxe_slowpath *sp; 1597 unsigned long sp_state; 1598 1599 /* slow path queue */ 1600 struct bxe_dma spq_dma; 1601 struct eth_spe *spq; 1602 #define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe)) 1603 #define MAX_SP_DESC_CNT (SP_DESC_CNT - 1) 1604 #define MAX_SPQ_PENDING 8 1605 1606 uint16_t spq_prod_idx; 1607 struct eth_spe *spq_prod_bd; 1608 struct eth_spe *spq_last_bd; 1609 uint16_t *dsb_sp_prod; 1610 //uint16_t *spq_hw_con; 1611 //uint16_t spq_left; 1612 1613 volatile unsigned long eq_spq_left; /* COMMON_xxx ramrod credit */ 1614 volatile unsigned long cq_spq_left; /* ETH_xxx ramrod credit */ 1615 1616 /* fw decompression buffer */ 1617 struct bxe_dma gz_buf_dma; 1618 void *gz_buf; 1619 z_streamp gz_strm; 1620 uint32_t gz_outlen; 1621 #define GUNZIP_BUF(sc) (sc->gz_buf) 1622 #define GUNZIP_OUTLEN(sc) (sc->gz_outlen) 1623 #define GUNZIP_PHYS(sc) (sc->gz_buf_dma.paddr) 1624 #define FW_BUF_SIZE 0x40000 1625 1626 const struct raw_op *init_ops; 1627 const uint16_t *init_ops_offsets; /* init block offsets inside init_ops */ 1628 const uint32_t *init_data; /* data blob, 32 bit granularity */ 1629 uint32_t init_mode_flags; 1630 #define INIT_MODE_FLAGS(sc) (sc->init_mode_flags) 1631 /* PRAM blobs - raw data */ 1632 const uint8_t *tsem_int_table_data; 1633 const uint8_t *tsem_pram_data; 1634 const uint8_t *usem_int_table_data; 1635 const uint8_t *usem_pram_data; 1636 const uint8_t *xsem_int_table_data; 1637 const uint8_t *xsem_pram_data; 1638 const uint8_t *csem_int_table_data; 1639 const uint8_t *csem_pram_data; 1640 #define INIT_OPS(sc) (sc->init_ops) 1641 #define INIT_OPS_OFFSETS(sc) (sc->init_ops_offsets) 1642 #define INIT_DATA(sc) (sc->init_data) 1643 #define INIT_TSEM_INT_TABLE_DATA(sc) (sc->tsem_int_table_data) 1644 #define INIT_TSEM_PRAM_DATA(sc) (sc->tsem_pram_data) 1645 #define INIT_USEM_INT_TABLE_DATA(sc) (sc->usem_int_table_data) 1646 #define INIT_USEM_PRAM_DATA(sc) (sc->usem_pram_data) 1647 #define INIT_XSEM_INT_TABLE_DATA(sc) (sc->xsem_int_table_data) 1648 #define INIT_XSEM_PRAM_DATA(sc) (sc->xsem_pram_data) 1649 #define INIT_CSEM_INT_TABLE_DATA(sc) (sc->csem_int_table_data) 1650 #define INIT_CSEM_PRAM_DATA(sc) (sc->csem_pram_data) 1651 1652 /* ILT 1653 * For max 196 cids (64*3 + non-eth), 32KB ILT page size and 1KB 1654 * context size we need 8 ILT entries. 1655 */ 1656 #define ILT_MAX_L2_LINES 8 1657 struct hw_context context[ILT_MAX_L2_LINES]; 1658 struct ecore_ilt *ilt; 1659 #define ILT_MAX_LINES 256 1660 1661 /* max supported number of RSS queues: IGU SBs minus one for CNIC */ 1662 #define BXE_MAX_RSS_COUNT(sc) ((sc)->igu_sb_cnt - CNIC_SUPPORT(sc)) 1663 /* max CID count: Max RSS * Max_Tx_Multi_Cos + FCoE + iSCSI */ 1664 #if 1 1665 #define BXE_L2_MAX_CID(sc) \ 1666 (BXE_MAX_RSS_COUNT(sc) * ECORE_MULTI_TX_COS + 2 * CNIC_SUPPORT(sc)) 1667 #else 1668 #define BXE_L2_MAX_CID(sc) /* OOO + FWD */ \ 1669 (BXE_MAX_RSS_COUNT(sc) * ECORE_MULTI_TX_COS + 4 * CNIC_SUPPORT(sc)) 1670 #endif 1671 #if 1 1672 #define BXE_L2_CID_COUNT(sc) \ 1673 (BXE_NUM_ETH_QUEUES(sc) * ECORE_MULTI_TX_COS + 2 * CNIC_SUPPORT(sc)) 1674 #else 1675 #define BXE_L2_CID_COUNT(sc) /* OOO + FWD */ \ 1676 (BXE_NUM_ETH_QUEUES(sc) * ECORE_MULTI_TX_COS + 4 * CNIC_SUPPORT(sc)) 1677 #endif 1678 #define L2_ILT_LINES(sc) \ 1679 (DIV_ROUND_UP(BXE_L2_CID_COUNT(sc), ILT_PAGE_CIDS)) 1680 1681 int qm_cid_count; 1682 1683 uint8_t dropless_fc; 1684 1685 /* total number of FW statistics requests */ 1686 uint8_t fw_stats_num; 1687 /* 1688 * This is a memory buffer that will contain both statistics ramrod 1689 * request and data. 1690 */ 1691 struct bxe_dma fw_stats_dma; 1692 /* 1693 * FW statistics request shortcut (points at the beginning of fw_stats 1694 * buffer). 1695 */ 1696 int fw_stats_req_size; 1697 struct bxe_fw_stats_req *fw_stats_req; 1698 bus_addr_t fw_stats_req_mapping; 1699 /* 1700 * FW statistics data shortcut (points at the beginning of fw_stats 1701 * buffer + fw_stats_req_size). 1702 */ 1703 int fw_stats_data_size; 1704 struct bxe_fw_stats_data *fw_stats_data; 1705 bus_addr_t fw_stats_data_mapping; 1706 1707 /* tracking a pending STAT_QUERY ramrod */ 1708 uint16_t stats_pending; 1709 /* number of completed statistics ramrods */ 1710 uint16_t stats_comp; 1711 uint16_t stats_counter; 1712 uint8_t stats_init; 1713 int stats_state; 1714 1715 struct bxe_eth_stats eth_stats; 1716 struct host_func_stats func_stats; 1717 struct bxe_eth_stats_old eth_stats_old; 1718 struct bxe_net_stats_old net_stats_old; 1719 struct bxe_fw_port_stats_old fw_stats_old; 1720 1721 struct dmae_cmd stats_dmae; /* used by dmae command loader */ 1722 int executer_idx; 1723 1724 int mtu; 1725 1726 /* LLDP params */ 1727 struct bxe_config_lldp_params lldp_config_params; 1728 /* DCB support on/off */ 1729 int dcb_state; 1730 #define BXE_DCB_STATE_OFF 0 1731 #define BXE_DCB_STATE_ON 1 1732 /* DCBX engine mode */ 1733 int dcbx_enabled; 1734 #define BXE_DCBX_ENABLED_OFF 0 1735 #define BXE_DCBX_ENABLED_ON_NEG_OFF 1 1736 #define BXE_DCBX_ENABLED_ON_NEG_ON 2 1737 #define BXE_DCBX_ENABLED_INVALID -1 1738 uint8_t dcbx_mode_uset; 1739 struct bxe_config_dcbx_params dcbx_config_params; 1740 struct bxe_dcbx_port_params dcbx_port_params; 1741 int dcb_version; 1742 1743 uint8_t cnic_support; 1744 uint8_t cnic_enabled; 1745 uint8_t cnic_loaded; 1746 #define CNIC_SUPPORT(sc) 0 /* ((sc)->cnic_support) */ 1747 #define CNIC_ENABLED(sc) 0 /* ((sc)->cnic_enabled) */ 1748 #define CNIC_LOADED(sc) 0 /* ((sc)->cnic_loaded) */ 1749 1750 /* multiple tx classes of service */ 1751 uint8_t max_cos; 1752 #define BXE_MAX_PRIORITY 8 1753 /* priority to cos mapping */ 1754 uint8_t prio_to_cos[BXE_MAX_PRIORITY]; 1755 1756 int panic; 1757 1758 struct cdev *ioctl_dev; 1759 1760 void *grc_dump; 1761 unsigned int trigger_grcdump; 1762 unsigned int grcdump_done; 1763 unsigned int grcdump_started; 1764 int bxe_pause_param; 1765 void *eeprom; 1766 }; /* struct bxe_softc */ 1767 1768 /* IOCTL sub-commands for edebug and firmware upgrade */ 1769 #define BXE_IOC_RD_NVRAM 1 1770 #define BXE_IOC_WR_NVRAM 2 1771 #define BXE_IOC_STATS_SHOW_NUM 3 1772 #define BXE_IOC_STATS_SHOW_STR 4 1773 #define BXE_IOC_STATS_SHOW_CNT 5 1774 1775 struct bxe_nvram_data { 1776 uint32_t op; /* ioctl sub-command */ 1777 uint32_t offset; 1778 uint32_t len; 1779 uint32_t value[1]; /* variable */ 1780 }; 1781 1782 union bxe_stats_show_data { 1783 uint32_t op; /* ioctl sub-command */ 1784 1785 struct { 1786 uint32_t num; /* return number of stats */ 1787 uint32_t len; /* length of each string item */ 1788 } desc; 1789 1790 /* variable length... */ 1791 char str[1]; /* holds names of desc.num stats, each desc.len in length */ 1792 1793 /* variable length... */ 1794 uint64_t stats[1]; /* holds all stats */ 1795 }; 1796 1797 /* function init flags */ 1798 #define FUNC_FLG_RSS 0x0001 1799 #define FUNC_FLG_STATS 0x0002 1800 /* FUNC_FLG_UNMATCHED 0x0004 */ 1801 #define FUNC_FLG_TPA 0x0008 1802 #define FUNC_FLG_SPQ 0x0010 1803 #define FUNC_FLG_LEADING 0x0020 /* PF only */ 1804 1805 struct bxe_func_init_params { 1806 bus_addr_t fw_stat_map; /* (dma) valid if FUNC_FLG_STATS */ 1807 bus_addr_t spq_map; /* (dma) valid if FUNC_FLG_SPQ */ 1808 uint16_t func_flgs; 1809 uint16_t func_id; /* abs function id */ 1810 uint16_t pf_id; 1811 uint16_t spq_prod; /* valid if FUNC_FLG_SPQ */ 1812 }; 1813 1814 /* memory resources reside at BARs 0, 2, 4 */ 1815 /* Run `pciconf -lb` to see mappings */ 1816 #define BAR0 0 1817 #define BAR1 2 1818 #define BAR2 4 1819 1820 #ifdef BXE_REG_NO_INLINE 1821 1822 uint8_t bxe_reg_read8(struct bxe_softc *sc, bus_size_t offset); 1823 uint16_t bxe_reg_read16(struct bxe_softc *sc, bus_size_t offset); 1824 uint32_t bxe_reg_read32(struct bxe_softc *sc, bus_size_t offset); 1825 1826 void bxe_reg_write8(struct bxe_softc *sc, bus_size_t offset, uint8_t val); 1827 void bxe_reg_write16(struct bxe_softc *sc, bus_size_t offset, uint16_t val); 1828 void bxe_reg_write32(struct bxe_softc *sc, bus_size_t offset, uint32_t val); 1829 1830 #define REG_RD8(sc, offset) bxe_reg_read8(sc, offset) 1831 #define REG_RD16(sc, offset) bxe_reg_read16(sc, offset) 1832 #define REG_RD32(sc, offset) bxe_reg_read32(sc, offset) 1833 1834 #define REG_WR8(sc, offset, val) bxe_reg_write8(sc, offset, val) 1835 #define REG_WR16(sc, offset, val) bxe_reg_write16(sc, offset, val) 1836 #define REG_WR32(sc, offset, val) bxe_reg_write32(sc, offset, val) 1837 1838 #else /* not BXE_REG_NO_INLINE */ 1839 1840 #define REG_WR8(sc, offset, val) \ 1841 bus_space_write_1(sc->bar[BAR0].tag, \ 1842 sc->bar[BAR0].handle, \ 1843 offset, val) 1844 1845 #define REG_WR16(sc, offset, val) \ 1846 bus_space_write_2(sc->bar[BAR0].tag, \ 1847 sc->bar[BAR0].handle, \ 1848 offset, val) 1849 1850 #define REG_WR32(sc, offset, val) \ 1851 bus_space_write_4(sc->bar[BAR0].tag, \ 1852 sc->bar[BAR0].handle, \ 1853 offset, val) 1854 1855 #define REG_RD8(sc, offset) \ 1856 bus_space_read_1(sc->bar[BAR0].tag, \ 1857 sc->bar[BAR0].handle, \ 1858 offset) 1859 1860 #define REG_RD16(sc, offset) \ 1861 bus_space_read_2(sc->bar[BAR0].tag, \ 1862 sc->bar[BAR0].handle, \ 1863 offset) 1864 1865 #define REG_RD32(sc, offset) \ 1866 bus_space_read_4(sc->bar[BAR0].tag, \ 1867 sc->bar[BAR0].handle, \ 1868 offset) 1869 1870 #endif /* BXE_REG_NO_INLINE */ 1871 1872 #define REG_RD(sc, offset) REG_RD32(sc, offset) 1873 #define REG_WR(sc, offset, val) REG_WR32(sc, offset, val) 1874 1875 #define REG_RD_IND(sc, offset) bxe_reg_rd_ind(sc, offset) 1876 #define REG_WR_IND(sc, offset, val) bxe_reg_wr_ind(sc, offset, val) 1877 1878 #define BXE_SP(sc, var) (&(sc)->sp->var) 1879 #define BXE_SP_MAPPING(sc, var) \ 1880 (sc->sp_dma.paddr + offsetof(struct bxe_slowpath, var)) 1881 1882 #define BXE_FP(sc, nr, var) ((sc)->fp[(nr)].var) 1883 #define BXE_SP_OBJ(sc, fp) ((sc)->sp_objs[(fp)->index]) 1884 1885 #define REG_RD_DMAE(sc, offset, valp, len32) \ 1886 do { \ 1887 bxe_read_dmae(sc, offset, len32); \ 1888 memcpy(valp, BXE_SP(sc, wb_data[0]), (len32) * 4); \ 1889 } while (0) 1890 1891 #define REG_WR_DMAE(sc, offset, valp, len32) \ 1892 do { \ 1893 memcpy(BXE_SP(sc, wb_data[0]), valp, (len32) * 4); \ 1894 bxe_write_dmae(sc, BXE_SP_MAPPING(sc, wb_data), offset, len32); \ 1895 } while (0) 1896 1897 #define REG_WR_DMAE_LEN(sc, offset, valp, len32) \ 1898 REG_WR_DMAE(sc, offset, valp, len32) 1899 1900 #define REG_RD_DMAE_LEN(sc, offset, valp, len32) \ 1901 REG_RD_DMAE(sc, offset, valp, len32) 1902 1903 #define VIRT_WR_DMAE_LEN(sc, data, addr, len32, le32_swap) \ 1904 do { \ 1905 /* if (le32_swap) { */ \ 1906 /* BLOGW(sc, "VIRT_WR_DMAE_LEN with le32_swap=1\n"); */ \ 1907 /* } */ \ 1908 memcpy(GUNZIP_BUF(sc), data, len32 * 4); \ 1909 ecore_write_big_buf_wb(sc, addr, len32); \ 1910 } while (0) 1911 1912 #define BXE_DB_MIN_SHIFT 3 /* 8 bytes */ 1913 #define BXE_DB_SHIFT 7 /* 128 bytes */ 1914 #if (BXE_DB_SHIFT < BXE_DB_MIN_SHIFT) 1915 #error "Minimum DB doorbell stride is 8" 1916 #endif 1917 #define DPM_TRIGGER_TYPE 0x40 1918 #define DOORBELL(sc, cid, val) \ 1919 do { \ 1920 bus_space_write_4(sc->bar[BAR1].tag, sc->bar[BAR1].handle, \ 1921 ((sc->doorbell_size * (cid)) + DPM_TRIGGER_TYPE), \ 1922 (uint32_t)val); \ 1923 } while(0) 1924 1925 #define SHMEM_ADDR(sc, field) \ 1926 (sc->devinfo.shmem_base + offsetof(struct shmem_region, field)) 1927 #define SHMEM_RD(sc, field) REG_RD(sc, SHMEM_ADDR(sc, field)) 1928 #define SHMEM_RD16(sc, field) REG_RD16(sc, SHMEM_ADDR(sc, field)) 1929 #define SHMEM_WR(sc, field, val) REG_WR(sc, SHMEM_ADDR(sc, field), val) 1930 1931 #define SHMEM2_ADDR(sc, field) \ 1932 (sc->devinfo.shmem2_base + offsetof(struct shmem2_region, field)) 1933 #define SHMEM2_HAS(sc, field) \ 1934 (sc->devinfo.shmem2_base && (REG_RD(sc, SHMEM2_ADDR(sc, size)) > \ 1935 offsetof(struct shmem2_region, field))) 1936 #define SHMEM2_RD(sc, field) REG_RD(sc, SHMEM2_ADDR(sc, field)) 1937 #define SHMEM2_WR(sc, field, val) REG_WR(sc, SHMEM2_ADDR(sc, field), val) 1938 1939 #define MFCFG_ADDR(sc, field) \ 1940 (sc->devinfo.mf_cfg_base + offsetof(struct mf_cfg, field)) 1941 #define MFCFG_RD(sc, field) REG_RD(sc, MFCFG_ADDR(sc, field)) 1942 #define MFCFG_RD16(sc, field) REG_RD16(sc, MFCFG_ADDR(sc, field)) 1943 #define MFCFG_WR(sc, field, val) REG_WR(sc, MFCFG_ADDR(sc, field), val) 1944 1945 /* DMAE command defines */ 1946 1947 #define DMAE_TIMEOUT -1 1948 #define DMAE_PCI_ERROR -2 /* E2 and onward */ 1949 #define DMAE_NOT_RDY -3 1950 #define DMAE_PCI_ERR_FLAG 0x80000000 1951 1952 #define DMAE_SRC_PCI 0 1953 #define DMAE_SRC_GRC 1 1954 1955 #define DMAE_DST_NONE 0 1956 #define DMAE_DST_PCI 1 1957 #define DMAE_DST_GRC 2 1958 1959 #define DMAE_COMP_PCI 0 1960 #define DMAE_COMP_GRC 1 1961 1962 #define DMAE_COMP_REGULAR 0 1963 #define DMAE_COM_SET_ERR 1 1964 1965 #define DMAE_CMD_SRC_PCI (DMAE_SRC_PCI << DMAE_CMD_SRC_SHIFT) 1966 #define DMAE_CMD_SRC_GRC (DMAE_SRC_GRC << DMAE_CMD_SRC_SHIFT) 1967 #define DMAE_CMD_DST_PCI (DMAE_DST_PCI << DMAE_CMD_DST_SHIFT) 1968 #define DMAE_CMD_DST_GRC (DMAE_DST_GRC << DMAE_CMD_DST_SHIFT) 1969 1970 #define DMAE_CMD_C_DST_PCI (DMAE_COMP_PCI << DMAE_CMD_C_DST_SHIFT) 1971 #define DMAE_CMD_C_DST_GRC (DMAE_COMP_GRC << DMAE_CMD_C_DST_SHIFT) 1972 1973 #define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_CMD_ENDIANITY_SHIFT) 1974 #define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_CMD_ENDIANITY_SHIFT) 1975 #define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_CMD_ENDIANITY_SHIFT) 1976 #define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_CMD_ENDIANITY_SHIFT) 1977 1978 #define DMAE_CMD_PORT_0 0 1979 #define DMAE_CMD_PORT_1 DMAE_CMD_PORT 1980 1981 #define DMAE_SRC_PF 0 1982 #define DMAE_SRC_VF 1 1983 1984 #define DMAE_DST_PF 0 1985 #define DMAE_DST_VF 1 1986 1987 #define DMAE_C_SRC 0 1988 #define DMAE_C_DST 1 1989 1990 #define DMAE_LEN32_RD_MAX 0x80 1991 #define DMAE_LEN32_WR_MAX(sc) (CHIP_IS_E1(sc) ? 0x400 : 0x2000) 1992 1993 #define DMAE_COMP_VAL 0x60d0d0ae /* E2 and beyond, upper bit indicates error */ 1994 1995 #define MAX_DMAE_C_PER_PORT 8 1996 #define INIT_DMAE_C(sc) ((SC_PORT(sc) * MAX_DMAE_C_PER_PORT) + SC_VN(sc)) 1997 #define PMF_DMAE_C(sc) ((SC_PORT(sc) * MAX_DMAE_C_PER_PORT) + E1HVN_MAX) 1998 1999 static const uint32_t dmae_reg_go_c[] = { 2000 DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3, 2001 DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7, 2002 DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11, 2003 DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15 2004 }; 2005 2006 #define ATTN_NIG_FOR_FUNC (1L << 8) 2007 #define ATTN_SW_TIMER_4_FUNC (1L << 9) 2008 #define GPIO_2_FUNC (1L << 10) 2009 #define GPIO_3_FUNC (1L << 11) 2010 #define GPIO_4_FUNC (1L << 12) 2011 #define ATTN_GENERAL_ATTN_1 (1L << 13) 2012 #define ATTN_GENERAL_ATTN_2 (1L << 14) 2013 #define ATTN_GENERAL_ATTN_3 (1L << 15) 2014 #define ATTN_GENERAL_ATTN_4 (1L << 13) 2015 #define ATTN_GENERAL_ATTN_5 (1L << 14) 2016 #define ATTN_GENERAL_ATTN_6 (1L << 15) 2017 #define ATTN_HARD_WIRED_MASK 0xff00 2018 #define ATTENTION_ID 4 2019 2020 #define AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR \ 2021 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR 2022 2023 #define MAX_IGU_ATTN_ACK_TO 100 2024 2025 #define STORM_ASSERT_ARRAY_SIZE 50 2026 2027 #define BXE_PMF_LINK_ASSERT(sc) \ 2028 GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + SC_FUNC(sc)) 2029 2030 #define BXE_MC_ASSERT_BITS \ 2031 (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \ 2032 GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \ 2033 GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \ 2034 GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT)) 2035 2036 #define BXE_MCP_ASSERT \ 2037 GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT) 2038 2039 #define BXE_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC) 2040 #define BXE_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \ 2041 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \ 2042 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \ 2043 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \ 2044 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \ 2045 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC)) 2046 2047 #define MULTI_MASK 0x7f 2048 2049 #define PFS_PER_PORT(sc) \ 2050 ((CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4) 2051 #define SC_MAX_VN_NUM(sc) PFS_PER_PORT(sc) 2052 2053 #define FIRST_ABS_FUNC_IN_PORT(sc) \ 2054 ((CHIP_PORT_MODE(sc) == CHIP_PORT_MODE_NONE) ? \ 2055 PORT_ID(sc) : (PATH_ID(sc) + (2 * PORT_ID(sc)))) 2056 2057 #define FOREACH_ABS_FUNC_IN_PORT(sc, i) \ 2058 for ((i) = FIRST_ABS_FUNC_IN_PORT(sc); \ 2059 (i) < MAX_FUNC_NUM; \ 2060 (i) += (MAX_FUNC_NUM / PFS_PER_PORT(sc))) 2061 2062 #define BXE_SWCID_SHIFT 17 2063 #define BXE_SWCID_MASK ((0x1 << BXE_SWCID_SHIFT) - 1) 2064 2065 #define SW_CID(x) (le32toh(x) & BXE_SWCID_MASK) 2066 #define CQE_CMD(x) (le32toh(x) >> COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT) 2067 2068 #define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE) 2069 #define CQE_TYPE_START(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_START_AGG) 2070 #define CQE_TYPE_STOP(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_STOP_AGG) 2071 #define CQE_TYPE_SLOW(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_RAMROD) 2072 #define CQE_TYPE_FAST(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_FASTPATH) 2073 2074 /* must be used on a CID before placing it on a HW ring */ 2075 #define HW_CID(sc, x) \ 2076 ((SC_PORT(sc) << 23) | (SC_VN(sc) << BXE_SWCID_SHIFT) | (x)) 2077 2078 #define SPEED_10 10 2079 #define SPEED_100 100 2080 #define SPEED_1000 1000 2081 #define SPEED_2500 2500 2082 #define SPEED_10000 10000 2083 2084 #define PCI_PM_D0 1 2085 #define PCI_PM_D3hot 2 2086 2087 #ifndef DUPLEX_UNKNOWN 2088 #define DUPLEX_UNKNOWN (0xff) 2089 #endif 2090 2091 #ifndef SPEED_UNKNOWN 2092 #define SPEED_UNKNOWN (-1) 2093 #endif 2094 2095 /* Enable or disable autonegotiation. */ 2096 #define AUTONEG_DISABLE 0x00 2097 #define AUTONEG_ENABLE 0x01 2098 2099 /* Which connector port. */ 2100 #define PORT_TP 0x00 2101 #define PORT_AUI 0x01 2102 #define PORT_MII 0x02 2103 #define PORT_FIBRE 0x03 2104 #define PORT_BNC 0x04 2105 #define PORT_DA 0x05 2106 #define PORT_NONE 0xef 2107 #define PORT_OTHER 0xff 2108 2109 int bxe_test_bit(int nr, volatile unsigned long * addr); 2110 void bxe_set_bit(unsigned int nr, volatile unsigned long * addr); 2111 void bxe_clear_bit(int nr, volatile unsigned long * addr); 2112 int bxe_test_and_set_bit(int nr, volatile unsigned long * addr); 2113 int bxe_test_and_clear_bit(int nr, volatile unsigned long * addr); 2114 int bxe_cmpxchg(volatile int *addr, int old, int new); 2115 2116 void bxe_reg_wr_ind(struct bxe_softc *sc, uint32_t addr, 2117 uint32_t val); 2118 uint32_t bxe_reg_rd_ind(struct bxe_softc *sc, uint32_t addr); 2119 2120 2121 int bxe_dma_alloc(struct bxe_softc *sc, bus_size_t size, 2122 struct bxe_dma *dma, const char *msg); 2123 void bxe_dma_free(struct bxe_softc *sc, struct bxe_dma *dma); 2124 2125 uint32_t bxe_dmae_opcode_add_comp(uint32_t opcode, uint8_t comp_type); 2126 uint32_t bxe_dmae_opcode_clr_src_reset(uint32_t opcode); 2127 uint32_t bxe_dmae_opcode(struct bxe_softc *sc, uint8_t src_type, 2128 uint8_t dst_type, uint8_t with_comp, 2129 uint8_t comp_type); 2130 void bxe_post_dmae(struct bxe_softc *sc, struct dmae_cmd *dmae, int idx); 2131 void bxe_read_dmae(struct bxe_softc *sc, uint32_t src_addr, uint32_t len32); 2132 void bxe_write_dmae(struct bxe_softc *sc, bus_addr_t dma_addr, 2133 uint32_t dst_addr, uint32_t len32); 2134 void bxe_write_dmae_phys_len(struct bxe_softc *sc, bus_addr_t phys_addr, 2135 uint32_t addr, uint32_t len); 2136 2137 void bxe_set_ctx_validation(struct bxe_softc *sc, struct eth_context *cxt, 2138 uint32_t cid); 2139 void bxe_update_coalesce_sb_index(struct bxe_softc *sc, uint8_t fw_sb_id, 2140 uint8_t sb_index, uint8_t disable, 2141 uint16_t usec); 2142 2143 int bxe_sp_post(struct bxe_softc *sc, int command, int cid, 2144 uint32_t data_hi, uint32_t data_lo, int cmd_type); 2145 2146 void bxe_igu_ack_sb(struct bxe_softc *sc, uint8_t igu_sb_id, 2147 uint8_t segment, uint16_t index, uint8_t op, 2148 uint8_t update); 2149 2150 void ecore_init_e1_firmware(struct bxe_softc *sc); 2151 void ecore_init_e1h_firmware(struct bxe_softc *sc); 2152 void ecore_init_e2_firmware(struct bxe_softc *sc); 2153 2154 void ecore_storm_memset_struct(struct bxe_softc *sc, uint32_t addr, 2155 size_t size, uint32_t *data); 2156 2157 /*********************/ 2158 /* LOGGING AND DEBUG */ 2159 /*********************/ 2160 2161 /* debug logging codepaths */ 2162 #define DBG_LOAD 0x00000001 /* load and unload */ 2163 #define DBG_INTR 0x00000002 /* interrupt handling */ 2164 #define DBG_SP 0x00000004 /* slowpath handling */ 2165 #define DBG_STATS 0x00000008 /* stats updates */ 2166 #define DBG_TX 0x00000010 /* packet transmit */ 2167 #define DBG_RX 0x00000020 /* packet receive */ 2168 #define DBG_PHY 0x00000040 /* phy/link handling */ 2169 #define DBG_IOCTL 0x00000080 /* ioctl handling */ 2170 #define DBG_MBUF 0x00000100 /* dumping mbuf info */ 2171 #define DBG_REGS 0x00000200 /* register access */ 2172 #define DBG_LRO 0x00000400 /* lro processing */ 2173 #define DBG_ASSERT 0x80000000 /* debug assert */ 2174 #define DBG_ALL 0xFFFFFFFF /* flying monkeys */ 2175 2176 #define DBASSERT(sc, exp, msg) \ 2177 do { \ 2178 if (__predict_false(sc->debug & DBG_ASSERT)) { \ 2179 if (__predict_false(!(exp))) { \ 2180 panic msg; \ 2181 } \ 2182 } \ 2183 } while (0) 2184 2185 /* log a debug message */ 2186 #define BLOGD(sc, codepath, format, args...) \ 2187 do { \ 2188 if (__predict_false(sc->debug & (codepath))) { \ 2189 device_printf((sc)->dev, \ 2190 "%s(%s:%d) " format, \ 2191 __FUNCTION__, \ 2192 __FILE__, \ 2193 __LINE__, \ 2194 ## args); \ 2195 } \ 2196 } while(0) 2197 2198 /* log a info message */ 2199 #define BLOGI(sc, format, args...) \ 2200 do { \ 2201 if (__predict_false(sc->debug)) { \ 2202 device_printf((sc)->dev, \ 2203 "%s(%s:%d) " format, \ 2204 __FUNCTION__, \ 2205 __FILE__, \ 2206 __LINE__, \ 2207 ## args); \ 2208 } else { \ 2209 device_printf((sc)->dev, \ 2210 format, \ 2211 ## args); \ 2212 } \ 2213 } while(0) 2214 2215 /* log a warning message */ 2216 #define BLOGW(sc, format, args...) \ 2217 do { \ 2218 if (__predict_false(sc->debug)) { \ 2219 device_printf((sc)->dev, \ 2220 "%s(%s:%d) WARNING: " format, \ 2221 __FUNCTION__, \ 2222 __FILE__, \ 2223 __LINE__, \ 2224 ## args); \ 2225 } else { \ 2226 device_printf((sc)->dev, \ 2227 "WARNING: " format, \ 2228 ## args); \ 2229 } \ 2230 } while(0) 2231 2232 /* log a error message */ 2233 #define BLOGE(sc, format, args...) \ 2234 do { \ 2235 if (__predict_false(sc->debug)) { \ 2236 device_printf((sc)->dev, \ 2237 "%s(%s:%d) ERROR: " format, \ 2238 __FUNCTION__, \ 2239 __FILE__, \ 2240 __LINE__, \ 2241 ## args); \ 2242 } else { \ 2243 device_printf((sc)->dev, \ 2244 "ERROR: " format, \ 2245 ## args); \ 2246 } \ 2247 } while(0) 2248 2249 #ifdef ECORE_STOP_ON_ERROR 2250 2251 #define bxe_panic(sc, msg) \ 2252 do { \ 2253 panic msg; \ 2254 } while (0) 2255 2256 #else 2257 2258 #define bxe_panic(sc, msg) \ 2259 device_printf((sc)->dev, "%s (%s,%d)\n", __FUNCTION__, __FILE__, __LINE__); 2260 2261 #endif 2262 2263 #define CATC_TRIGGER(sc, data) REG_WR((sc), 0x2000, (data)); 2264 #define CATC_TRIGGER_START(sc) CATC_TRIGGER((sc), 0xcafecafe) 2265 2266 void bxe_dump_mem(struct bxe_softc *sc, char *tag, 2267 uint8_t *mem, uint32_t len); 2268 void bxe_dump_mbuf_data(struct bxe_softc *sc, char *pTag, 2269 struct mbuf *m, uint8_t contents); 2270 2271 #define BXE_SET_FLOWID(m) M_HASHTYPE_SET(m, M_HASHTYPE_OPAQUE) 2272 #define BXE_VALID_FLOWID(m) (M_HASHTYPE_GET(m) != M_HASHTYPE_NONE) 2273 2274 /***********/ 2275 /* INLINES */ 2276 /***********/ 2277 2278 static inline uint32_t 2279 reg_poll(struct bxe_softc *sc, 2280 uint32_t reg, 2281 uint32_t expected, 2282 int ms, 2283 int wait) 2284 { 2285 uint32_t val; 2286 2287 do { 2288 val = REG_RD(sc, reg); 2289 if (val == expected) { 2290 break; 2291 } 2292 ms -= wait; 2293 DELAY(wait * 1000); 2294 } while (ms > 0); 2295 2296 return (val); 2297 } 2298 2299 static inline void 2300 bxe_update_fp_sb_idx(struct bxe_fastpath *fp) 2301 { 2302 mb(); /* status block is written to by the chip */ 2303 fp->fp_hc_idx = fp->sb_running_index[SM_RX_ID]; 2304 } 2305 2306 static inline void 2307 bxe_igu_ack_sb_gen(struct bxe_softc *sc, 2308 uint8_t igu_sb_id, 2309 uint8_t segment, 2310 uint16_t index, 2311 uint8_t op, 2312 uint8_t update, 2313 uint32_t igu_addr) 2314 { 2315 struct igu_regular cmd_data = {0}; 2316 2317 cmd_data.sb_id_and_flags = 2318 ((index << IGU_REGULAR_SB_INDEX_SHIFT) | 2319 (segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) | 2320 (update << IGU_REGULAR_BUPDATE_SHIFT) | 2321 (op << IGU_REGULAR_ENABLE_INT_SHIFT)); 2322 2323 BLOGD(sc, DBG_INTR, "write 0x%08x to IGU addr 0x%x\n", 2324 cmd_data.sb_id_and_flags, igu_addr); 2325 REG_WR(sc, igu_addr, cmd_data.sb_id_and_flags); 2326 2327 /* Make sure that ACK is written */ 2328 bus_space_barrier(sc->bar[0].tag, sc->bar[0].handle, 0, 0, 2329 BUS_SPACE_BARRIER_WRITE); 2330 mb(); 2331 } 2332 2333 static inline void 2334 bxe_hc_ack_sb(struct bxe_softc *sc, 2335 uint8_t sb_id, 2336 uint8_t storm, 2337 uint16_t index, 2338 uint8_t op, 2339 uint8_t update) 2340 { 2341 uint32_t hc_addr = (HC_REG_COMMAND_REG + SC_PORT(sc)*32 + 2342 COMMAND_REG_INT_ACK); 2343 struct igu_ack_register igu_ack; 2344 2345 igu_ack.status_block_index = index; 2346 igu_ack.sb_id_and_flags = 2347 ((sb_id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) | 2348 (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) | 2349 (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) | 2350 (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT)); 2351 2352 REG_WR(sc, hc_addr, (*(uint32_t *)&igu_ack)); 2353 2354 /* Make sure that ACK is written */ 2355 bus_space_barrier(sc->bar[0].tag, sc->bar[0].handle, 0, 0, 2356 BUS_SPACE_BARRIER_WRITE); 2357 mb(); 2358 } 2359 2360 static inline void 2361 bxe_ack_sb(struct bxe_softc *sc, 2362 uint8_t igu_sb_id, 2363 uint8_t storm, 2364 uint16_t index, 2365 uint8_t op, 2366 uint8_t update) 2367 { 2368 if (sc->devinfo.int_block == INT_BLOCK_HC) 2369 bxe_hc_ack_sb(sc, igu_sb_id, storm, index, op, update); 2370 else { 2371 uint8_t segment; 2372 if (CHIP_INT_MODE_IS_BC(sc)) { 2373 segment = storm; 2374 } else if (igu_sb_id != sc->igu_dsb_id) { 2375 segment = IGU_SEG_ACCESS_DEF; 2376 } else if (storm == ATTENTION_ID) { 2377 segment = IGU_SEG_ACCESS_ATTN; 2378 } else { 2379 segment = IGU_SEG_ACCESS_DEF; 2380 } 2381 bxe_igu_ack_sb(sc, igu_sb_id, segment, index, op, update); 2382 } 2383 } 2384 2385 static inline uint16_t 2386 bxe_hc_ack_int(struct bxe_softc *sc) 2387 { 2388 uint32_t hc_addr = (HC_REG_COMMAND_REG + SC_PORT(sc)*32 + 2389 COMMAND_REG_SIMD_MASK); 2390 uint32_t result = REG_RD(sc, hc_addr); 2391 2392 mb(); 2393 return (result); 2394 } 2395 2396 static inline uint16_t 2397 bxe_igu_ack_int(struct bxe_softc *sc) 2398 { 2399 uint32_t igu_addr = (BAR_IGU_INTMEM + IGU_REG_SISR_MDPC_WMASK_LSB_UPPER*8); 2400 uint32_t result = REG_RD(sc, igu_addr); 2401 2402 BLOGD(sc, DBG_INTR, "read 0x%08x from IGU addr 0x%x\n", 2403 result, igu_addr); 2404 2405 mb(); 2406 return (result); 2407 } 2408 2409 static inline uint16_t 2410 bxe_ack_int(struct bxe_softc *sc) 2411 { 2412 mb(); 2413 if (sc->devinfo.int_block == INT_BLOCK_HC) { 2414 return (bxe_hc_ack_int(sc)); 2415 } else { 2416 return (bxe_igu_ack_int(sc)); 2417 } 2418 } 2419 2420 static inline int 2421 func_by_vn(struct bxe_softc *sc, 2422 int vn) 2423 { 2424 return (2 * vn + SC_PORT(sc)); 2425 } 2426 2427 /* 2428 * Statistics ID are global per chip/path, while Client IDs for E1x 2429 * are per port. 2430 */ 2431 static inline uint8_t 2432 bxe_stats_id(struct bxe_fastpath *fp) 2433 { 2434 struct bxe_softc *sc = fp->sc; 2435 2436 if (!CHIP_IS_E1x(sc)) { 2437 return (fp->cl_id); 2438 } 2439 2440 return (fp->cl_id + SC_PORT(sc) * FP_SB_MAX_E1x); 2441 } 2442 2443 #endif /* __BXE_H__ */ 2444 2445