1 /*- 2 * Copyright (c) 2007-2014 QLogic Corporation. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' 15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS 18 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 19 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 20 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 21 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 22 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 23 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 24 * THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #ifndef __BXE_H__ 28 #define __BXE_H__ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include <sys/param.h> 34 #include <sys/kernel.h> 35 #include <sys/systm.h> 36 #include <sys/lock.h> 37 #include <sys/mutex.h> 38 #include <sys/sx.h> 39 #include <sys/module.h> 40 #include <sys/endian.h> 41 #include <sys/types.h> 42 #include <sys/malloc.h> 43 #include <sys/kobj.h> 44 #include <sys/bus.h> 45 #include <sys/rman.h> 46 #include <sys/socket.h> 47 #include <sys/sockio.h> 48 #include <sys/sysctl.h> 49 #include <sys/smp.h> 50 #include <sys/bitstring.h> 51 #include <sys/limits.h> 52 #include <sys/queue.h> 53 #include <sys/taskqueue.h> 54 #include <sys/zlib.h> 55 56 #include <net/if.h> 57 #include <net/if_types.h> 58 #include <net/if_arp.h> 59 #include <net/ethernet.h> 60 #include <net/if_dl.h> 61 #include <net/if_var.h> 62 #include <net/if_media.h> 63 #include <net/if_vlan_var.h> 64 #include <net/bpf.h> 65 66 #include <netinet/in.h> 67 #include <netinet/ip.h> 68 #include <netinet/ip6.h> 69 #include <netinet/tcp.h> 70 #include <netinet/udp.h> 71 72 #include <dev/pci/pcireg.h> 73 #include <dev/pci/pcivar.h> 74 75 #include <machine/atomic.h> 76 #include <machine/resource.h> 77 #include <machine/endian.h> 78 #include <machine/bus.h> 79 #include <machine/in_cksum.h> 80 81 #include "device_if.h" 82 #include "bus_if.h" 83 #include "pci_if.h" 84 85 #if _BYTE_ORDER == _LITTLE_ENDIAN 86 #ifndef LITTLE_ENDIAN 87 #define LITTLE_ENDIAN 88 #endif 89 #ifndef __LITTLE_ENDIAN 90 #define __LITTLE_ENDIAN 91 #endif 92 #undef BIG_ENDIAN 93 #undef __BIG_ENDIAN 94 #else /* _BIG_ENDIAN */ 95 #ifndef BIG_ENDIAN 96 #define BIG_ENDIAN 97 #endif 98 #ifndef __BIG_ENDIAN 99 #define __BIG_ENDIAN 100 #endif 101 #undef LITTLE_ENDIAN 102 #undef __LITTLE_ENDIAN 103 #endif 104 105 #include "ecore_mfw_req.h" 106 #include "ecore_fw_defs.h" 107 #include "ecore_hsi.h" 108 #include "ecore_reg.h" 109 #include "bxe_dcb.h" 110 #include "bxe_stats.h" 111 112 #include "bxe_elink.h" 113 114 #if __FreeBSD_version < 800054 115 #if defined(__i386__) || defined(__amd64__) 116 #define mb() __asm volatile("mfence;" : : : "memory") 117 #define wmb() __asm volatile("sfence;" : : : "memory") 118 #define rmb() __asm volatile("lfence;" : : : "memory") 119 static __inline void prefetch(void *x) 120 { 121 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x)); 122 } 123 #else 124 #define mb() 125 #define rmb() 126 #define wmb() 127 #define prefetch(x) 128 #endif 129 #endif 130 131 #if __FreeBSD_version >= 1000000 132 #define PCIR_EXPRESS_DEVICE_STA PCIER_DEVICE_STA 133 #define PCIM_EXP_STA_TRANSACTION_PND PCIEM_STA_TRANSACTION_PND 134 #define PCIR_EXPRESS_LINK_STA PCIER_LINK_STA 135 #define PCIM_LINK_STA_WIDTH PCIEM_LINK_STA_WIDTH 136 #define PCIM_LINK_STA_SPEED PCIEM_LINK_STA_SPEED 137 #define PCIR_EXPRESS_DEVICE_CTL PCIER_DEVICE_CTL 138 #define PCIM_EXP_CTL_MAX_PAYLOAD PCIEM_CTL_MAX_PAYLOAD 139 #define PCIM_EXP_CTL_MAX_READ_REQUEST PCIEM_CTL_MAX_READ_REQUEST 140 #endif 141 142 #ifndef ARRAY_SIZE 143 #define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0])) 144 #endif 145 #ifndef ARRSIZE 146 #define ARRSIZE(arr) (sizeof(arr) / sizeof((arr)[0])) 147 #endif 148 #ifndef DIV_ROUND_UP 149 #define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d)) 150 #endif 151 #ifndef roundup 152 #define roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y)) 153 #endif 154 #ifndef ilog2 155 static inline 156 int bxe_ilog2(int x) 157 { 158 int log = 0; 159 while (x >>= 1) log++; 160 return (log); 161 } 162 #define ilog2(x) bxe_ilog2(x) 163 #endif 164 165 #include "ecore_sp.h" 166 167 #define BRCM_VENDORID 0x14e4 168 #define PCI_ANY_ID (uint16_t)(~0U) 169 170 struct bxe_device_type 171 { 172 uint16_t bxe_vid; 173 uint16_t bxe_did; 174 uint16_t bxe_svid; 175 uint16_t bxe_sdid; 176 char *bxe_name; 177 }; 178 179 #define BCM_PAGE_SHIFT 12 180 #define BCM_PAGE_SIZE (1 << BCM_PAGE_SHIFT) 181 #define BCM_PAGE_MASK (~(BCM_PAGE_SIZE - 1)) 182 #define BCM_PAGE_ALIGN(addr) ((addr + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK) 183 184 #if BCM_PAGE_SIZE != 4096 185 #error Page sizes other than 4KB are unsupported! 186 #endif 187 188 #if (BUS_SPACE_MAXADDR > 0xFFFFFFFF) 189 #define U64_LO(addr) ((uint32_t)(((uint64_t)(addr)) & 0xFFFFFFFF)) 190 #define U64_HI(addr) ((uint32_t)(((uint64_t)(addr)) >> 32)) 191 #else 192 #define U64_LO(addr) ((uint32_t)(addr)) 193 #define U64_HI(addr) (0) 194 #endif 195 #define HILO_U64(hi, lo) ((((uint64_t)(hi)) << 32) + (lo)) 196 197 #define SET_FLAG(value, mask, flag) \ 198 do { \ 199 (value) &= ~(mask); \ 200 (value) |= ((flag) << (mask##_SHIFT)); \ 201 } while (0) 202 203 #define GET_FLAG(value, mask) \ 204 (((value) & (mask)) >> (mask##_SHIFT)) 205 206 #define GET_FIELD(value, fname) \ 207 (((value) & (fname##_MASK)) >> (fname##_SHIFT)) 208 209 #define BXE_MAX_SEGMENTS 12 /* 13-1 for parsing buffer */ 210 #define BXE_TSO_MAX_SEGMENTS 32 211 #define BXE_TSO_MAX_SIZE (65535 + sizeof(struct ether_vlan_header)) 212 #define BXE_TSO_MAX_SEG_SIZE 4096 213 214 /* dropless fc FW/HW related params */ 215 #define BRB_SIZE(sc) (CHIP_IS_E3(sc) ? 1024 : 512) 216 #define MAX_AGG_QS(sc) (CHIP_IS_E1(sc) ? \ 217 ETH_MAX_AGGREGATION_QUEUES_E1 : \ 218 ETH_MAX_AGGREGATION_QUEUES_E1H_E2) 219 #define FW_DROP_LEVEL(sc) (3 + MAX_SPQ_PENDING + MAX_AGG_QS(sc)) 220 #define FW_PREFETCH_CNT 16 221 #define DROPLESS_FC_HEADROOM 100 222 223 /******************/ 224 /* RX SGE defines */ 225 /******************/ 226 227 #define RX_SGE_NUM_PAGES 2 /* must be a power of 2 */ 228 #define RX_SGE_TOTAL_PER_PAGE (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge)) 229 #define RX_SGE_NEXT_PAGE_DESC_CNT 2 230 #define RX_SGE_USABLE_PER_PAGE (RX_SGE_TOTAL_PER_PAGE - RX_SGE_NEXT_PAGE_DESC_CNT) 231 #define RX_SGE_PER_PAGE_MASK (RX_SGE_TOTAL_PER_PAGE - 1) 232 #define RX_SGE_TOTAL (RX_SGE_TOTAL_PER_PAGE * RX_SGE_NUM_PAGES) 233 #define RX_SGE_USABLE (RX_SGE_USABLE_PER_PAGE * RX_SGE_NUM_PAGES) 234 #define RX_SGE_MAX (RX_SGE_TOTAL - 1) 235 #define RX_SGE(x) ((x) & RX_SGE_MAX) 236 237 #define RX_SGE_NEXT(x) \ 238 ((((x) & RX_SGE_PER_PAGE_MASK) == (RX_SGE_USABLE_PER_PAGE - 1)) \ 239 ? (x) + 1 + RX_SGE_NEXT_PAGE_DESC_CNT : (x) + 1) 240 241 #define RX_SGE_MASK_ELEM_SZ 64 242 #define RX_SGE_MASK_ELEM_SHIFT 6 243 #define RX_SGE_MASK_ELEM_MASK ((uint64_t)RX_SGE_MASK_ELEM_SZ - 1) 244 245 /* 246 * Creates a bitmask of all ones in less significant bits. 247 * idx - index of the most significant bit in the created mask. 248 */ 249 #define RX_SGE_ONES_MASK(idx) \ 250 (((uint64_t)0x1 << (((idx) & RX_SGE_MASK_ELEM_MASK) + 1)) - 1) 251 #define RX_SGE_MASK_ELEM_ONE_MASK ((uint64_t)(~0)) 252 253 /* Number of uint64_t elements in SGE mask array. */ 254 #define RX_SGE_MASK_LEN \ 255 ((RX_SGE_NUM_PAGES * RX_SGE_TOTAL_PER_PAGE) / RX_SGE_MASK_ELEM_SZ) 256 #define RX_SGE_MASK_LEN_MASK (RX_SGE_MASK_LEN - 1) 257 #define RX_SGE_NEXT_MASK_ELEM(el) (((el) + 1) & RX_SGE_MASK_LEN_MASK) 258 259 /* 260 * dropless fc calculations for SGEs 261 * Number of required SGEs is the sum of two: 262 * 1. Number of possible opened aggregations (next packet for 263 * these aggregations will probably consume SGE immidiatelly) 264 * 2. Rest of BRB blocks divided by 2 (block will consume new SGE only 265 * after placement on BD for new TPA aggregation) 266 * Takes into account RX_SGE_NEXT_PAGE_DESC_CNT "next" elements on each page 267 */ 268 #define NUM_SGE_REQ(sc) \ 269 (MAX_AGG_QS(sc) + (BRB_SIZE(sc) - MAX_AGG_QS(sc)) / 2) 270 #define NUM_SGE_PG_REQ(sc) \ 271 ((NUM_SGE_REQ(sc) + RX_SGE_USABLE_PER_PAGE - 1) / RX_SGE_USABLE_PER_PAGE) 272 #define SGE_TH_LO(sc) \ 273 (NUM_SGE_REQ(sc) + NUM_SGE_PG_REQ(sc) * RX_SGE_NEXT_PAGE_DESC_CNT) 274 #define SGE_TH_HI(sc) \ 275 (SGE_TH_LO(sc) + DROPLESS_FC_HEADROOM) 276 277 #define PAGES_PER_SGE_SHIFT 0 278 #define PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT) 279 #define SGE_PAGE_SIZE BCM_PAGE_SIZE 280 #define SGE_PAGE_SHIFT BCM_PAGE_SHIFT 281 #define SGE_PAGE_ALIGN(addr) BCM_PAGE_ALIGN(addr) 282 #define SGE_PAGES (SGE_PAGE_SIZE * PAGES_PER_SGE) 283 #define TPA_AGG_SIZE min((8 * SGE_PAGES), 0xffff) 284 285 /*****************/ 286 /* TX BD defines */ 287 /*****************/ 288 289 #define TX_BD_NUM_PAGES 16 /* must be a power of 2 */ 290 #define TX_BD_TOTAL_PER_PAGE (BCM_PAGE_SIZE / sizeof(union eth_tx_bd_types)) 291 #define TX_BD_USABLE_PER_PAGE (TX_BD_TOTAL_PER_PAGE - 1) 292 #define TX_BD_TOTAL (TX_BD_TOTAL_PER_PAGE * TX_BD_NUM_PAGES) 293 #define TX_BD_USABLE (TX_BD_USABLE_PER_PAGE * TX_BD_NUM_PAGES) 294 #define TX_BD_MAX (TX_BD_TOTAL - 1) 295 296 #define TX_BD_NEXT(x) \ 297 ((((x) & TX_BD_USABLE_PER_PAGE) == (TX_BD_USABLE_PER_PAGE - 1)) ? \ 298 ((x) + 2) : ((x) + 1)) 299 #define TX_BD(x) ((x) & TX_BD_MAX) 300 #define TX_BD_PAGE(x) (((x) & ~TX_BD_USABLE_PER_PAGE) >> 8) 301 #define TX_BD_IDX(x) ((x) & TX_BD_USABLE_PER_PAGE) 302 303 /* 304 * Trigger pending transmits when the number of available BDs is greater 305 * than 1/8 of the total number of usable BDs. 306 */ 307 #define BXE_TX_CLEANUP_THRESHOLD (TX_BD_USABLE / 8) 308 #define BXE_TX_TIMEOUT 5 309 310 /*****************/ 311 /* RX BD defines */ 312 /*****************/ 313 314 #define RX_BD_NUM_PAGES 8 /* power of 2 */ 315 #define RX_BD_TOTAL_PER_PAGE (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd)) 316 #define RX_BD_NEXT_PAGE_DESC_CNT 2 317 #define RX_BD_USABLE_PER_PAGE (RX_BD_TOTAL_PER_PAGE - RX_BD_NEXT_PAGE_DESC_CNT) 318 #define RX_BD_PER_PAGE_MASK (RX_BD_TOTAL_PER_PAGE - 1) 319 #define RX_BD_TOTAL (RX_BD_TOTAL_PER_PAGE * RX_BD_NUM_PAGES) 320 #define RX_BD_USABLE (RX_BD_USABLE_PER_PAGE * RX_BD_NUM_PAGES) 321 #define RX_BD_MAX (RX_BD_TOTAL - 1) 322 323 #if 0 324 #define NUM_RX_RINGS RX_BD_NUM_PAGES 325 #define NUM_RX_BD RX_BD_TOTAL 326 #define MAX_RX_BD RX_BD_MAX 327 #define MAX_RX_AVAIL RX_BD_USABLE 328 #endif 329 330 #define RX_BD_NEXT(x) \ 331 ((((x) & RX_BD_PER_PAGE_MASK) == (RX_BD_USABLE_PER_PAGE - 1)) ? \ 332 ((x) + 3) : ((x) + 1)) 333 #define RX_BD(x) ((x) & RX_BD_MAX) 334 #define RX_BD_PAGE(x) (((x) & ~RX_BD_PER_PAGE_MASK) >> 9) 335 #define RX_BD_IDX(x) ((x) & RX_BD_PER_PAGE_MASK) 336 337 /* 338 * dropless fc calculations for BDs 339 * Number of BDs should be as number of buffers in BRB: 340 * Low threshold takes into account RX_BD_NEXT_PAGE_DESC_CNT 341 * "next" elements on each page 342 */ 343 #define NUM_BD_REQ(sc) \ 344 BRB_SIZE(sc) 345 #define NUM_BD_PG_REQ(sc) \ 346 ((NUM_BD_REQ(sc) + RX_BD_USABLE_PER_PAGE - 1) / RX_BD_USABLE_PER_PAGE) 347 #define BD_TH_LO(sc) \ 348 (NUM_BD_REQ(sc) + \ 349 NUM_BD_PG_REQ(sc) * RX_BD_NEXT_PAGE_DESC_CNT + \ 350 FW_DROP_LEVEL(sc)) 351 #define BD_TH_HI(sc) \ 352 (BD_TH_LO(sc) + DROPLESS_FC_HEADROOM) 353 #define MIN_RX_AVAIL(sc) \ 354 ((sc)->dropless_fc ? BD_TH_HI(sc) + 128 : 128) 355 #define MIN_RX_SIZE_TPA_HW(sc) \ 356 (CHIP_IS_E1(sc) ? ETH_MIN_RX_CQES_WITH_TPA_E1 : \ 357 ETH_MIN_RX_CQES_WITH_TPA_E1H_E2) 358 #define MIN_RX_SIZE_NONTPA_HW ETH_MIN_RX_CQES_WITHOUT_TPA 359 #define MIN_RX_SIZE_TPA(sc) \ 360 (max(MIN_RX_SIZE_TPA_HW(sc), MIN_RX_AVAIL(sc))) 361 #define MIN_RX_SIZE_NONTPA(sc) \ 362 (max(MIN_RX_SIZE_NONTPA_HW, MIN_RX_AVAIL(sc))) 363 364 /***************/ 365 /* RCQ defines */ 366 /***************/ 367 368 /* 369 * As long as CQE is X times bigger than BD entry we have to allocate X times 370 * more pages for CQ ring in order to keep it balanced with BD ring 371 */ 372 #define CQE_BD_REL (sizeof(union eth_rx_cqe) / \ 373 sizeof(struct eth_rx_bd)) 374 #define RCQ_NUM_PAGES (RX_BD_NUM_PAGES * CQE_BD_REL) /* power of 2 */ 375 #define RCQ_TOTAL_PER_PAGE (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe)) 376 #define RCQ_NEXT_PAGE_DESC_CNT 1 377 #define RCQ_USABLE_PER_PAGE (RCQ_TOTAL_PER_PAGE - RCQ_NEXT_PAGE_DESC_CNT) 378 #define RCQ_TOTAL (RCQ_TOTAL_PER_PAGE * RCQ_NUM_PAGES) 379 #define RCQ_USABLE (RCQ_USABLE_PER_PAGE * RCQ_NUM_PAGES) 380 #define RCQ_MAX (RCQ_TOTAL - 1) 381 382 #define RCQ_NEXT(x) \ 383 ((((x) & RCQ_USABLE_PER_PAGE) == (RCQ_USABLE_PER_PAGE - 1)) ? \ 384 ((x) + 1 + RCQ_NEXT_PAGE_DESC_CNT) : ((x) + 1)) 385 #define RCQ(x) ((x) & RCQ_MAX) 386 #define RCQ_PAGE(x) (((x) & ~RCQ_USABLE_PER_PAGE) >> 7) 387 #define RCQ_IDX(x) ((x) & RCQ_USABLE_PER_PAGE) 388 389 #if 0 390 #define NUM_RCQ_RINGS RCQ_NUM_PAGES 391 #define NUM_RCQ_BD RCQ_TOTAL 392 #define MAX_RCQ_BD RCQ_MAX 393 #define MAX_RCQ_AVAIL RCQ_USABLE 394 #endif 395 396 /* 397 * dropless fc calculations for RCQs 398 * Number of RCQs should be as number of buffers in BRB: 399 * Low threshold takes into account RCQ_NEXT_PAGE_DESC_CNT 400 * "next" elements on each page 401 */ 402 #define NUM_RCQ_REQ(sc) \ 403 BRB_SIZE(sc) 404 #define NUM_RCQ_PG_REQ(sc) \ 405 ((NUM_RCQ_REQ(sc) + RCQ_USABLE_PER_PAGE - 1) / RCQ_USABLE_PER_PAGE) 406 #define RCQ_TH_LO(sc) \ 407 (NUM_RCQ_REQ(sc) + \ 408 NUM_RCQ_PG_REQ(sc) * RCQ_NEXT_PAGE_DESC_CNT + \ 409 FW_DROP_LEVEL(sc)) 410 #define RCQ_TH_HI(sc) \ 411 (RCQ_TH_LO(sc) + DROPLESS_FC_HEADROOM) 412 413 /* This is needed for determening of last_max */ 414 #define SUB_S16(a, b) (int16_t)((int16_t)(a) - (int16_t)(b)) 415 416 #define __SGE_MASK_SET_BIT(el, bit) \ 417 do { \ 418 (el) = ((el) | ((uint64_t)0x1 << (bit))); \ 419 } while (0) 420 421 #define __SGE_MASK_CLEAR_BIT(el, bit) \ 422 do { \ 423 (el) = ((el) & (~((uint64_t)0x1 << (bit)))); \ 424 } while (0) 425 426 #define SGE_MASK_SET_BIT(fp, idx) \ 427 __SGE_MASK_SET_BIT((fp)->sge_mask[(idx) >> RX_SGE_MASK_ELEM_SHIFT], \ 428 ((idx) & RX_SGE_MASK_ELEM_MASK)) 429 430 #define SGE_MASK_CLEAR_BIT(fp, idx) \ 431 __SGE_MASK_CLEAR_BIT((fp)->sge_mask[(idx) >> RX_SGE_MASK_ELEM_SHIFT], \ 432 ((idx) & RX_SGE_MASK_ELEM_MASK)) 433 434 /* Load / Unload modes */ 435 #define LOAD_NORMAL 0 436 #define LOAD_OPEN 1 437 #define LOAD_DIAG 2 438 #define LOAD_LOOPBACK_EXT 3 439 #define UNLOAD_NORMAL 0 440 #define UNLOAD_CLOSE 1 441 #define UNLOAD_RECOVERY 2 442 443 /* Some constants... */ 444 //#define MAX_PATH_NUM 2 445 //#define E2_MAX_NUM_OF_VFS 64 446 //#define E1H_FUNC_MAX 8 447 //#define E2_FUNC_MAX 4 /* per path */ 448 #define MAX_VNIC_NUM 4 449 #define MAX_FUNC_NUM 8 /* common to all chips */ 450 //#define MAX_NDSB HC_SB_MAX_SB_E2 /* max non-default status block */ 451 #define MAX_RSS_CHAINS 16 /* a constant for HW limit */ 452 #define MAX_MSI_VECTOR 8 /* a constant for HW limit */ 453 454 #define ILT_NUM_PAGE_ENTRIES 3072 455 /* 456 * 57710/11 we use whole table since we have 8 functions. 457 * 57712 we have only 4 functions, but use same size per func, so only half 458 * of the table is used. 459 */ 460 #define ILT_PER_FUNC (ILT_NUM_PAGE_ENTRIES / 8) 461 #define FUNC_ILT_BASE(func) (func * ILT_PER_FUNC) 462 /* 463 * the phys address is shifted right 12 bits and has an added 464 * 1=valid bit added to the 53rd bit 465 * then since this is a wide register(TM) 466 * we split it into two 32 bit writes 467 */ 468 #define ONCHIP_ADDR1(x) ((uint32_t)(((uint64_t)x >> 12) & 0xFFFFFFFF)) 469 #define ONCHIP_ADDR2(x) ((uint32_t)((1 << 20) | ((uint64_t)x >> 44))) 470 471 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */ 472 #define ETH_HLEN 14 473 #define ETH_OVERHEAD (ETH_HLEN + 8 + 8) 474 #define ETH_MIN_PACKET_SIZE 60 475 #define ETH_MAX_PACKET_SIZE ETHERMTU /* 1500 */ 476 #define ETH_MAX_JUMBO_PACKET_SIZE 9600 477 /* TCP with Timestamp Option (32) + IPv6 (40) */ 478 #define ETH_MAX_TPA_HEADER_SIZE 72 479 480 /* max supported alignment is 256 (8 shift) */ 481 //#define BXE_RX_ALIGN_SHIFT ((CACHE_LINE_SHIFT < 8) ? CACHE_LINE_SHIFT : 8) 482 #define BXE_RX_ALIGN_SHIFT 8 483 /* FW uses 2 cache lines alignment for start packet and size */ 484 #define BXE_FW_RX_ALIGN_START (1 << BXE_RX_ALIGN_SHIFT) 485 #define BXE_FW_RX_ALIGN_END (1 << BXE_RX_ALIGN_SHIFT) 486 487 #define BXE_PXP_DRAM_ALIGN (BXE_RX_ALIGN_SHIFT - 5) /* XXX ??? */ 488 489 struct bxe_bar { 490 struct resource *resource; 491 int rid; 492 bus_space_tag_t tag; 493 bus_space_handle_t handle; 494 vm_offset_t kva; 495 }; 496 497 struct bxe_intr { 498 struct resource *resource; 499 int rid; 500 void *tag; 501 }; 502 503 /* Used to manage DMA allocations. */ 504 struct bxe_dma { 505 struct bxe_softc *sc; 506 bus_addr_t paddr; 507 void *vaddr; 508 bus_dma_tag_t tag; 509 bus_dmamap_t map; 510 bus_dma_segment_t seg; 511 bus_size_t size; 512 int nseg; 513 char msg[32]; 514 }; 515 516 /* attn group wiring */ 517 #define MAX_DYNAMIC_ATTN_GRPS 8 518 519 struct attn_route { 520 uint32_t sig[5]; 521 }; 522 523 struct iro { 524 uint32_t base; 525 uint16_t m1; 526 uint16_t m2; 527 uint16_t m3; 528 uint16_t size; 529 }; 530 531 union bxe_host_hc_status_block { 532 /* pointer to fp status block e2 */ 533 struct host_hc_status_block_e2 *e2_sb; 534 /* pointer to fp status block e1x */ 535 struct host_hc_status_block_e1x *e1x_sb; 536 }; 537 538 union bxe_db_prod { 539 struct doorbell_set_prod data; 540 uint32_t raw; 541 }; 542 543 struct bxe_sw_tx_bd { 544 struct mbuf *m; 545 bus_dmamap_t m_map; 546 uint16_t first_bd; 547 uint8_t flags; 548 /* set on the first BD descriptor when there is a split BD */ 549 #define BXE_TSO_SPLIT_BD (1 << 0) 550 }; 551 552 struct bxe_sw_rx_bd { 553 struct mbuf *m; 554 bus_dmamap_t m_map; 555 }; 556 557 struct bxe_sw_tpa_info { 558 struct bxe_sw_rx_bd bd; 559 bus_dma_segment_t seg; 560 uint8_t state; 561 #define BXE_TPA_STATE_START 1 562 #define BXE_TPA_STATE_STOP 2 563 uint8_t placement_offset; 564 uint16_t parsing_flags; 565 uint16_t vlan_tag; 566 uint16_t len_on_bd; 567 }; 568 569 /* 570 * This is the HSI fastpath data structure. There can be up to MAX_RSS_CHAIN 571 * instances of the fastpath structure when using multiple queues. 572 */ 573 struct bxe_fastpath { 574 /* pointer back to parent structure */ 575 struct bxe_softc *sc; 576 577 struct mtx tx_mtx; 578 char tx_mtx_name[32]; 579 struct mtx rx_mtx; 580 char rx_mtx_name[32]; 581 582 #define BXE_FP_TX_LOCK(fp) mtx_lock(&fp->tx_mtx) 583 #define BXE_FP_TX_UNLOCK(fp) mtx_unlock(&fp->tx_mtx) 584 #define BXE_FP_TX_LOCK_ASSERT(fp) mtx_assert(&fp->tx_mtx, MA_OWNED) 585 #define BXE_FP_TX_TRYLOCK(fp) mtx_trylock(&fp->tx_mtx) 586 587 #define BXE_FP_RX_LOCK(fp) mtx_lock(&fp->rx_mtx) 588 #define BXE_FP_RX_UNLOCK(fp) mtx_unlock(&fp->rx_mtx) 589 #define BXE_FP_RX_LOCK_ASSERT(fp) mtx_assert(&fp->rx_mtx, MA_OWNED) 590 591 /* status block */ 592 struct bxe_dma sb_dma; 593 union bxe_host_hc_status_block status_block; 594 595 /* transmit chain (tx bds) */ 596 struct bxe_dma tx_dma; 597 union eth_tx_bd_types *tx_chain; 598 599 /* receive chain (rx bds) */ 600 struct bxe_dma rx_dma; 601 struct eth_rx_bd *rx_chain; 602 603 /* receive completion queue chain (rcq bds) */ 604 struct bxe_dma rcq_dma; 605 union eth_rx_cqe *rcq_chain; 606 607 /* receive scatter/gather entry chain (for TPA) */ 608 struct bxe_dma rx_sge_dma; 609 struct eth_rx_sge *rx_sge_chain; 610 611 /* tx mbufs */ 612 bus_dma_tag_t tx_mbuf_tag; 613 struct bxe_sw_tx_bd tx_mbuf_chain[TX_BD_TOTAL]; 614 615 /* rx mbufs */ 616 bus_dma_tag_t rx_mbuf_tag; 617 struct bxe_sw_rx_bd rx_mbuf_chain[RX_BD_TOTAL]; 618 bus_dmamap_t rx_mbuf_spare_map; 619 620 /* rx sge mbufs */ 621 bus_dma_tag_t rx_sge_mbuf_tag; 622 struct bxe_sw_rx_bd rx_sge_mbuf_chain[RX_SGE_TOTAL]; 623 bus_dmamap_t rx_sge_mbuf_spare_map; 624 625 /* rx tpa mbufs (use the larger size for TPA queue length) */ 626 int tpa_enable; /* disabled per fastpath upon error */ 627 struct bxe_sw_tpa_info rx_tpa_info[ETH_MAX_AGGREGATION_QUEUES_E1H_E2]; 628 bus_dmamap_t rx_tpa_info_mbuf_spare_map; 629 uint64_t rx_tpa_queue_used; 630 #if 0 631 bus_dmamap_t rx_tpa_mbuf_map[ETH_MAX_AGGREGATION_QUEUES_E1H_E2]; 632 bus_dmamap_t rx_tpa_mbuf_spare_map; 633 struct mbuf *rx_tpa_mbuf_ptr[ETH_MAX_AGGREGATION_QUEUES_E1H_E2]; 634 bus_dma_segment_t rx_tpa_mbuf_segs[ETH_MAX_AGGREGATION_QUEUES_E1H_E2]; 635 636 uint8_t tpa_state[ETH_MAX_AGGREGATION_QUEUES_E1H_E2]; 637 #endif 638 639 uint16_t *sb_index_values; 640 uint16_t *sb_running_index; 641 uint32_t ustorm_rx_prods_offset; 642 643 uint8_t igu_sb_id; /* status block number in HW */ 644 uint8_t fw_sb_id; /* status block number in FW */ 645 646 uint32_t rx_buf_size; 647 int mbuf_alloc_size; 648 649 int state; 650 #define BXE_FP_STATE_CLOSED 0x01 651 #define BXE_FP_STATE_IRQ 0x02 652 #define BXE_FP_STATE_OPENING 0x04 653 #define BXE_FP_STATE_OPEN 0x08 654 #define BXE_FP_STATE_HALTING 0x10 655 #define BXE_FP_STATE_HALTED 0x20 656 657 /* reference back to this fastpath queue number */ 658 uint8_t index; /* this is also the 'cid' */ 659 #define FP_IDX(fp) (fp->index) 660 661 /* interrupt taskqueue (fast) */ 662 struct task tq_task; 663 struct taskqueue *tq; 664 char tq_name[32]; 665 666 /* ethernet client ID (each fastpath set of RX/TX/CQE is a client) */ 667 uint8_t cl_id; 668 #define FP_CL_ID(fp) (fp->cl_id) 669 uint8_t cl_qzone_id; 670 671 uint16_t fp_hc_idx; 672 673 /* driver copy of the receive buffer descriptor prod/cons indices */ 674 uint16_t rx_bd_prod; 675 uint16_t rx_bd_cons; 676 677 /* driver copy of the receive completion queue prod/cons indices */ 678 uint16_t rx_cq_prod; 679 uint16_t rx_cq_cons; 680 681 union bxe_db_prod tx_db; 682 683 /* Transmit packet producer index (used in eth_tx_bd). */ 684 uint16_t tx_pkt_prod; 685 uint16_t tx_pkt_cons; 686 687 /* Transmit buffer descriptor producer index. */ 688 uint16_t tx_bd_prod; 689 uint16_t tx_bd_cons; 690 691 #if 0 692 /* status block number in hardware */ 693 uint8_t sb_id; 694 #define FP_SB_ID(fp) (fp->sb_id) 695 696 /* driver copy of the fastpath CSTORM/USTORM indices */ 697 uint16_t fp_c_idx; 698 uint16_t fp_u_idx; 699 #endif 700 701 uint64_t sge_mask[RX_SGE_MASK_LEN]; 702 uint16_t rx_sge_prod; 703 704 struct tstorm_per_queue_stats old_tclient; 705 struct ustorm_per_queue_stats old_uclient; 706 struct xstorm_per_queue_stats old_xclient; 707 struct bxe_eth_q_stats eth_q_stats; 708 struct bxe_eth_q_stats_old eth_q_stats_old; 709 710 /* Pointer to the receive consumer in the status block */ 711 uint16_t *rx_cq_cons_sb; 712 713 /* Pointer to the transmit consumer in the status block */ 714 uint16_t *tx_cons_sb; 715 716 /* transmit timeout until chip reset */ 717 int watchdog_timer; 718 719 /* Free/used buffer descriptor counters. */ 720 //uint16_t used_tx_bd; 721 722 /* Last maximal completed SGE */ 723 uint16_t last_max_sge; 724 725 //uint16_t rx_sge_free_idx; 726 727 //uint8_t segs; 728 729 #if __FreeBSD_version >= 800000 730 #define BXE_BR_SIZE 4096 731 struct buf_ring *tx_br; 732 #endif 733 }; /* struct bxe_fastpath */ 734 735 /* sriov XXX */ 736 #define BXE_MAX_NUM_OF_VFS 64 737 #define BXE_VF_CID_WND 0 738 #define BXE_CIDS_PER_VF (1 << BXE_VF_CID_WND) 739 #define BXE_CLIENTS_PER_VF 1 740 #define BXE_FIRST_VF_CID 256 741 #define BXE_VF_CIDS (BXE_MAX_NUM_OF_VFS * BXE_CIDS_PER_VF) 742 #define BXE_VF_ID_INVALID 0xFF 743 #define IS_SRIOV(sc) 0 744 745 #define GET_NUM_VFS_PER_PATH(sc) 0 746 #define GET_NUM_VFS_PER_PF(sc) 0 747 748 /* maximum number of fast-path interrupt contexts */ 749 #define FP_SB_MAX_E1x 16 750 #define FP_SB_MAX_E2 HC_SB_MAX_SB_E2 751 752 union cdu_context { 753 struct eth_context eth; 754 char pad[1024]; 755 }; 756 757 /* CDU host DB constants */ 758 #define CDU_ILT_PAGE_SZ_HW 2 759 #define CDU_ILT_PAGE_SZ (8192 << CDU_ILT_PAGE_SZ_HW) /* 32K */ 760 #define ILT_PAGE_CIDS (CDU_ILT_PAGE_SZ / sizeof(union cdu_context)) 761 762 #define CNIC_ISCSI_CID_MAX 256 763 #define CNIC_FCOE_CID_MAX 2048 764 #define CNIC_CID_MAX (CNIC_ISCSI_CID_MAX + CNIC_FCOE_CID_MAX) 765 #define CNIC_ILT_LINES DIV_ROUND_UP(CNIC_CID_MAX, ILT_PAGE_CIDS) 766 767 #define QM_ILT_PAGE_SZ_HW 0 768 #define QM_ILT_PAGE_SZ (4096 << QM_ILT_PAGE_SZ_HW) /* 4K */ 769 #define QM_CID_ROUND 1024 770 771 /* TM (timers) host DB constants */ 772 #define TM_ILT_PAGE_SZ_HW 0 773 #define TM_ILT_PAGE_SZ (4096 << TM_ILT_PAGE_SZ_HW) /* 4K */ 774 /*#define TM_CONN_NUM (CNIC_STARTING_CID+CNIC_ISCSI_CXT_MAX) */ 775 #define TM_CONN_NUM 1024 776 #define TM_ILT_SZ (8 * TM_CONN_NUM) 777 #define TM_ILT_LINES DIV_ROUND_UP(TM_ILT_SZ, TM_ILT_PAGE_SZ) 778 779 /* SRC (Searcher) host DB constants */ 780 #define SRC_ILT_PAGE_SZ_HW 0 781 #define SRC_ILT_PAGE_SZ (4096 << SRC_ILT_PAGE_SZ_HW) /* 4K */ 782 #define SRC_HASH_BITS 10 783 #define SRC_CONN_NUM (1 << SRC_HASH_BITS) /* 1024 */ 784 #define SRC_ILT_SZ (sizeof(struct src_ent) * SRC_CONN_NUM) 785 #define SRC_T2_SZ SRC_ILT_SZ 786 #define SRC_ILT_LINES DIV_ROUND_UP(SRC_ILT_SZ, SRC_ILT_PAGE_SZ) 787 788 struct hw_context { 789 struct bxe_dma vcxt_dma; 790 union cdu_context *vcxt; 791 //bus_addr_t cxt_mapping; 792 size_t size; 793 }; 794 795 #define SM_RX_ID 0 796 #define SM_TX_ID 1 797 798 /* defines for multiple tx priority indices */ 799 #define FIRST_TX_ONLY_COS_INDEX 1 800 #define FIRST_TX_COS_INDEX 0 801 802 #define CID_TO_FP(cid, sc) ((cid) % BXE_NUM_NON_CNIC_QUEUES(sc)) 803 804 #define HC_INDEX_ETH_RX_CQ_CONS 1 805 #define HC_INDEX_OOO_TX_CQ_CONS 4 806 #define HC_INDEX_ETH_TX_CQ_CONS_COS0 5 807 #define HC_INDEX_ETH_TX_CQ_CONS_COS1 6 808 #define HC_INDEX_ETH_TX_CQ_CONS_COS2 7 809 #define HC_INDEX_ETH_FIRST_TX_CQ_CONS HC_INDEX_ETH_TX_CQ_CONS_COS0 810 811 /* congestion management fairness mode */ 812 #define CMNG_FNS_NONE 0 813 #define CMNG_FNS_MINMAX 1 814 815 /* CMNG constants, as derived from system spec calculations */ 816 /* default MIN rate in case VNIC min rate is configured to zero - 100Mbps */ 817 #define DEF_MIN_RATE 100 818 /* resolution of the rate shaping timer - 400 usec */ 819 #define RS_PERIODIC_TIMEOUT_USEC 400 820 /* number of bytes in single QM arbitration cycle - 821 * coefficient for calculating the fairness timer */ 822 #define QM_ARB_BYTES 160000 823 /* resolution of Min algorithm 1:100 */ 824 #define MIN_RES 100 825 /* how many bytes above threshold for the minimal credit of Min algorithm*/ 826 #define MIN_ABOVE_THRESH 32768 827 /* fairness algorithm integration time coefficient - 828 * for calculating the actual Tfair */ 829 #define T_FAIR_COEF ((MIN_ABOVE_THRESH + QM_ARB_BYTES) * 8 * MIN_RES) 830 /* memory of fairness algorithm - 2 cycles */ 831 #define FAIR_MEM 2 832 833 #define HC_SEG_ACCESS_DEF 0 /* Driver decision 0-3 */ 834 #define HC_SEG_ACCESS_ATTN 4 835 #define HC_SEG_ACCESS_NORM 0 /* Driver decision 0-1 */ 836 837 /* 838 * The total number of L2 queues, MSIX vectors and HW contexts (CIDs) is 839 * control by the number of fast-path status blocks supported by the 840 * device (HW/FW). Each fast-path status block (FP-SB) aka non-default 841 * status block represents an independent interrupts context that can 842 * serve a regular L2 networking queue. However special L2 queues such 843 * as the FCoE queue do not require a FP-SB and other components like 844 * the CNIC may consume FP-SB reducing the number of possible L2 queues 845 * 846 * If the maximum number of FP-SB available is X then: 847 * a. If CNIC is supported it consumes 1 FP-SB thus the max number of 848 * regular L2 queues is Y=X-1 849 * b. in MF mode the actual number of L2 queues is Y= (X-1/MF_factor) 850 * c. If the FCoE L2 queue is supported the actual number of L2 queues 851 * is Y+1 852 * d. The number of irqs (MSIX vectors) is either Y+1 (one extra for 853 * slow-path interrupts) or Y+2 if CNIC is supported (one additional 854 * FP interrupt context for the CNIC). 855 * e. The number of HW context (CID count) is always X or X+1 if FCoE 856 * L2 queue is supported. the cid for the FCoE L2 queue is always X. 857 * 858 * So this is quite simple for now as no ULPs are supported yet. :-) 859 */ 860 #define BXE_NUM_QUEUES(sc) ((sc)->num_queues) 861 #define BXE_NUM_ETH_QUEUES(sc) BXE_NUM_QUEUES(sc) 862 #define BXE_NUM_NON_CNIC_QUEUES(sc) BXE_NUM_QUEUES(sc) 863 #define BXE_NUM_RX_QUEUES(sc) BXE_NUM_QUEUES(sc) 864 865 #define FOR_EACH_QUEUE(sc, var) \ 866 for ((var) = 0; (var) < BXE_NUM_QUEUES(sc); (var)++) 867 868 #define FOR_EACH_NONDEFAULT_QUEUE(sc, var) \ 869 for ((var) = 1; (var) < BXE_NUM_QUEUES(sc); (var)++) 870 871 #define FOR_EACH_ETH_QUEUE(sc, var) \ 872 for ((var) = 0; (var) < BXE_NUM_ETH_QUEUES(sc); (var)++) 873 874 #define FOR_EACH_NONDEFAULT_ETH_QUEUE(sc, var) \ 875 for ((var) = 1; (var) < BXE_NUM_ETH_QUEUES(sc); (var)++) 876 877 #define FOR_EACH_COS_IN_TX_QUEUE(sc, var) \ 878 for ((var) = 0; (var) < (sc)->max_cos; (var)++) 879 880 #define FOR_EACH_CNIC_QUEUE(sc, var) \ 881 for ((var) = BXE_NUM_ETH_QUEUES(sc); \ 882 (var) < BXE_NUM_QUEUES(sc); \ 883 (var)++) 884 885 enum { 886 OOO_IDX_OFFSET, 887 FCOE_IDX_OFFSET, 888 FWD_IDX_OFFSET, 889 }; 890 891 #define FCOE_IDX(sc) (BXE_NUM_NON_CNIC_QUEUES(sc) + FCOE_IDX_OFFSET) 892 #define bxe_fcoe_fp(sc) (&sc->fp[FCOE_IDX(sc)]) 893 #define bxe_fcoe(sc, var) (bxe_fcoe_fp(sc)->var) 894 #define bxe_fcoe_inner_sp_obj(sc) (&sc->sp_objs[FCOE_IDX(sc)]) 895 #define bxe_fcoe_sp_obj(sc, var) (bxe_fcoe_inner_sp_obj(sc)->var) 896 #define bxe_fcoe_tx(sc, var) (bxe_fcoe_fp(sc)->txdata_ptr[FIRST_TX_COS_INDEX]->var) 897 898 #define OOO_IDX(sc) (BXE_NUM_NON_CNIC_QUEUES(sc) + OOO_IDX_OFFSET) 899 #define bxe_ooo_fp(sc) (&sc->fp[OOO_IDX(sc)]) 900 #define bxe_ooo(sc, var) (bxe_ooo_fp(sc)->var) 901 #define bxe_ooo_inner_sp_obj(sc) (&sc->sp_objs[OOO_IDX(sc)]) 902 #define bxe_ooo_sp_obj(sc, var) (bxe_ooo_inner_sp_obj(sc)->var) 903 904 #define FWD_IDX(sc) (BXE_NUM_NON_CNIC_QUEUES(sc) + FWD_IDX_OFFSET) 905 #define bxe_fwd_fp(sc) (&sc->fp[FWD_IDX(sc)]) 906 #define bxe_fwd(sc, var) (bxe_fwd_fp(sc)->var) 907 #define bxe_fwd_inner_sp_obj(sc) (&sc->sp_objs[FWD_IDX(sc)]) 908 #define bxe_fwd_sp_obj(sc, var) (bxe_fwd_inner_sp_obj(sc)->var) 909 #define bxe_fwd_txdata(fp) (fp->txdata_ptr[FIRST_TX_COS_INDEX]) 910 911 #define IS_ETH_FP(fp) ((fp)->index < BXE_NUM_ETH_QUEUES((fp)->sc)) 912 #define IS_FCOE_FP(fp) ((fp)->index == FCOE_IDX((fp)->sc)) 913 #define IS_FCOE_IDX(idx) ((idx) == FCOE_IDX(sc)) 914 #define IS_FWD_FP(fp) ((fp)->index == FWD_IDX((fp)->sc)) 915 #define IS_FWD_IDX(idx) ((idx) == FWD_IDX(sc)) 916 #define IS_OOO_FP(fp) ((fp)->index == OOO_IDX((fp)->sc)) 917 #define IS_OOO_IDX(idx) ((idx) == OOO_IDX(sc)) 918 919 enum { 920 BXE_PORT_QUERY_IDX, 921 BXE_PF_QUERY_IDX, 922 BXE_FCOE_QUERY_IDX, 923 BXE_FIRST_QUEUE_QUERY_IDX, 924 }; 925 926 struct bxe_fw_stats_req { 927 struct stats_query_header hdr; 928 struct stats_query_entry query[FP_SB_MAX_E1x + 929 BXE_FIRST_QUEUE_QUERY_IDX]; 930 }; 931 932 struct bxe_fw_stats_data { 933 struct stats_counter storm_counters; 934 struct per_port_stats port; 935 struct per_pf_stats pf; 936 //struct fcoe_statistics_params fcoe; 937 struct per_queue_stats queue_stats[1]; 938 }; 939 940 /* IGU MSIX STATISTICS on 57712: 64 for VFs; 4 for PFs; 4 for Attentions */ 941 #define BXE_IGU_STAS_MSG_VF_CNT 64 942 #define BXE_IGU_STAS_MSG_PF_CNT 4 943 944 #define MAX_DMAE_C 8 945 946 /* 947 * For the main interface up/down code paths, a not-so-fine-grained CORE 948 * mutex lock is used. Inside this code are various calls to kernel routines 949 * that can cause a sleep to occur. Namely memory allocations and taskqueue 950 * handling. If using an MTX lock we are *not* allowed to sleep but we can 951 * with an SX lock. This define forces the CORE lock to use and SX lock. 952 * Undefine this and an MTX lock will be used instead. Note that the IOCTL 953 * path can cause problems since it's called by a non-sleepable thread. To 954 * alleviate a potential sleep, any IOCTL processing that results in the 955 * chip/interface being started/stopped/reinitialized, the actual work is 956 * offloaded to a taskqueue. 957 */ 958 #define BXE_CORE_LOCK_SX 959 960 /* 961 * This is the slowpath data structure. It is mapped into non-paged memory 962 * so that the hardware can access it's contents directly and must be page 963 * aligned. 964 */ 965 struct bxe_slowpath { 966 967 #if 0 968 /* 969 * The cdu_context array MUST be the first element in this 970 * structure. It is used during the leading edge ramrod 971 * operation. 972 */ 973 union cdu_context context[MAX_CONTEXT]; 974 975 /* Used as a DMA source for MAC configuration. */ 976 struct mac_configuration_cmd mac_config; 977 struct mac_configuration_cmd mcast_config; 978 #endif 979 980 /* used by the DMAE command executer */ 981 struct dmae_command dmae[MAX_DMAE_C]; 982 983 /* statistics completion */ 984 uint32_t stats_comp; 985 986 /* firmware defined statistics blocks */ 987 union mac_stats mac_stats; 988 struct nig_stats nig_stats; 989 struct host_port_stats port_stats; 990 struct host_func_stats func_stats; 991 //struct host_func_stats func_stats_base; 992 993 /* DMAE completion value and data source/sink */ 994 uint32_t wb_comp; 995 uint32_t wb_data[4]; 996 997 union { 998 struct mac_configuration_cmd e1x; 999 struct eth_classify_rules_ramrod_data e2; 1000 } mac_rdata; 1001 1002 union { 1003 struct tstorm_eth_mac_filter_config e1x; 1004 struct eth_filter_rules_ramrod_data e2; 1005 } rx_mode_rdata; 1006 1007 struct eth_rss_update_ramrod_data rss_rdata; 1008 1009 union { 1010 struct mac_configuration_cmd e1; 1011 struct eth_multicast_rules_ramrod_data e2; 1012 } mcast_rdata; 1013 1014 union { 1015 struct function_start_data func_start; 1016 struct flow_control_configuration pfc_config; /* for DCBX ramrod */ 1017 } func_rdata; 1018 1019 /* Queue State related ramrods */ 1020 union { 1021 struct client_init_ramrod_data init_data; 1022 struct client_update_ramrod_data update_data; 1023 } q_rdata; 1024 1025 /* 1026 * AFEX ramrod can not be a part of func_rdata union because these 1027 * events might arrive in parallel to other events from func_rdata. 1028 * If they were defined in the same union the data can get corrupted. 1029 */ 1030 struct afex_vif_list_ramrod_data func_afex_rdata; 1031 1032 union drv_info_to_mcp drv_info_to_mcp; 1033 }; /* struct bxe_slowpath */ 1034 1035 /* 1036 * Port specifc data structure. 1037 */ 1038 struct bxe_port { 1039 /* 1040 * Port Management Function (for 57711E only). 1041 * When this field is set the driver instance is 1042 * responsible for managing port specifc 1043 * configurations such as handling link attentions. 1044 */ 1045 uint32_t pmf; 1046 1047 /* Ethernet maximum transmission unit. */ 1048 uint16_t ether_mtu; 1049 1050 uint32_t link_config[ELINK_LINK_CONFIG_SIZE]; 1051 1052 uint32_t ext_phy_config; 1053 1054 /* Port feature config.*/ 1055 uint32_t config; 1056 1057 /* Defines the features supported by the PHY. */ 1058 uint32_t supported[ELINK_LINK_CONFIG_SIZE]; 1059 1060 /* Defines the features advertised by the PHY. */ 1061 uint32_t advertising[ELINK_LINK_CONFIG_SIZE]; 1062 #define ADVERTISED_10baseT_Half (1 << 1) 1063 #define ADVERTISED_10baseT_Full (1 << 2) 1064 #define ADVERTISED_100baseT_Half (1 << 3) 1065 #define ADVERTISED_100baseT_Full (1 << 4) 1066 #define ADVERTISED_1000baseT_Half (1 << 5) 1067 #define ADVERTISED_1000baseT_Full (1 << 6) 1068 #define ADVERTISED_TP (1 << 7) 1069 #define ADVERTISED_FIBRE (1 << 8) 1070 #define ADVERTISED_Autoneg (1 << 9) 1071 #define ADVERTISED_Asym_Pause (1 << 10) 1072 #define ADVERTISED_Pause (1 << 11) 1073 #define ADVERTISED_2500baseX_Full (1 << 15) 1074 #define ADVERTISED_10000baseT_Full (1 << 16) 1075 1076 uint32_t phy_addr; 1077 1078 /* Used to synchronize phy accesses. */ 1079 struct mtx phy_mtx; 1080 char phy_mtx_name[32]; 1081 1082 #define BXE_PHY_LOCK(sc) mtx_lock(&sc->port.phy_mtx) 1083 #define BXE_PHY_UNLOCK(sc) mtx_unlock(&sc->port.phy_mtx) 1084 #define BXE_PHY_LOCK_ASSERT(sc) mtx_assert(&sc->port.phy_mtx, MA_OWNED) 1085 1086 /* 1087 * MCP scratchpad address for port specific statistics. 1088 * The device is responsible for writing statistcss 1089 * back to the MCP for use with management firmware such 1090 * as UMP/NC-SI. 1091 */ 1092 uint32_t port_stx; 1093 1094 struct nig_stats old_nig_stats; 1095 }; /* struct bxe_port */ 1096 1097 struct bxe_mf_info { 1098 uint32_t mf_config[E1HVN_MAX]; 1099 1100 uint32_t vnics_per_port; /* 1, 2 or 4 */ 1101 uint32_t multi_vnics_mode; /* can be set even if vnics_per_port = 1 */ 1102 uint32_t path_has_ovlan; /* MF mode in the path (can be different than the MF mode of the function */ 1103 1104 #define IS_MULTI_VNIC(sc) ((sc)->devinfo.mf_info.multi_vnics_mode) 1105 #define VNICS_PER_PORT(sc) ((sc)->devinfo.mf_info.vnics_per_port) 1106 #define VNICS_PER_PATH(sc) \ 1107 ((sc)->devinfo.mf_info.vnics_per_port * \ 1108 ((CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 1 )) 1109 1110 uint8_t min_bw[MAX_VNIC_NUM]; 1111 uint8_t max_bw[MAX_VNIC_NUM]; 1112 1113 uint16_t ext_id; /* vnic outer vlan or VIF ID */ 1114 #define VALID_OVLAN(ovlan) ((ovlan) <= 4096) 1115 #define INVALID_VIF_ID 0xFFFF 1116 #define OVLAN(sc) ((sc)->devinfo.mf_info.ext_id) 1117 #define VIF_ID(sc) ((sc)->devinfo.mf_info.ext_id) 1118 1119 uint16_t default_vlan; 1120 #define NIV_DEFAULT_VLAN(sc) ((sc)->devinfo.mf_info.default_vlan) 1121 1122 uint8_t niv_allowed_priorities; 1123 #define NIV_ALLOWED_PRIORITIES(sc) ((sc)->devinfo.mf_info.niv_allowed_priorities) 1124 1125 uint8_t niv_default_cos; 1126 #define NIV_DEFAULT_COS(sc) ((sc)->devinfo.mf_info.niv_default_cos) 1127 1128 uint8_t niv_mba_enabled; 1129 1130 enum mf_cfg_afex_vlan_mode afex_vlan_mode; 1131 #define AFEX_VLAN_MODE(sc) ((sc)->devinfo.mf_info.afex_vlan_mode) 1132 int afex_def_vlan_tag; 1133 uint32_t pending_max; 1134 1135 uint16_t flags; 1136 #define MF_INFO_VALID_MAC 0x0001 1137 1138 uint8_t mf_mode; /* Switch-Dependent or Switch-Independent */ 1139 #define IS_MF(sc) \ 1140 (IS_MULTI_VNIC(sc) && \ 1141 ((sc)->devinfo.mf_info.mf_mode != 0)) 1142 #define IS_MF_SD(sc) \ 1143 (IS_MULTI_VNIC(sc) && \ 1144 ((sc)->devinfo.mf_info.mf_mode == MULTI_FUNCTION_SD)) 1145 #define IS_MF_SI(sc) \ 1146 (IS_MULTI_VNIC(sc) && \ 1147 ((sc)->devinfo.mf_info.mf_mode == MULTI_FUNCTION_SI)) 1148 #define IS_MF_AFEX(sc) \ 1149 (IS_MULTI_VNIC(sc) && \ 1150 ((sc)->devinfo.mf_info.mf_mode == MULTI_FUNCTION_AFEX)) 1151 #define IS_MF_SD_MODE(sc) IS_MF_SD(sc) 1152 #define IS_MF_SI_MODE(sc) IS_MF_SI(sc) 1153 #define IS_MF_AFEX_MODE(sc) IS_MF_AFEX(sc) 1154 1155 uint32_t mf_protos_supported; 1156 #define MF_PROTO_SUPPORT_ETHERNET 0x1 1157 #define MF_PROTO_SUPPORT_ISCSI 0x2 1158 #define MF_PROTO_SUPPORT_FCOE 0x4 1159 }; /* struct bxe_mf_info */ 1160 1161 /* Device information data structure. */ 1162 struct bxe_devinfo { 1163 /* PCIe info */ 1164 uint16_t vendor_id; 1165 uint16_t device_id; 1166 uint16_t subvendor_id; 1167 uint16_t subdevice_id; 1168 1169 /* 1170 * chip_id = 0b'CCCCCCCCCCCCCCCCRRRRMMMMMMMMBBBB' 1171 * C = Chip Number (bits 16-31) 1172 * R = Chip Revision (bits 12-15) 1173 * M = Chip Metal (bits 4-11) 1174 * B = Chip Bond ID (bits 0-3) 1175 */ 1176 uint32_t chip_id; 1177 #define CHIP_ID(sc) ((sc)->devinfo.chip_id & 0xffff0000) 1178 #define CHIP_NUM(sc) ((sc)->devinfo.chip_id >> 16) 1179 /* device ids */ 1180 #define CHIP_NUM_57710 0x164e 1181 #define CHIP_NUM_57711 0x164f 1182 #define CHIP_NUM_57711E 0x1650 1183 #define CHIP_NUM_57712 0x1662 1184 #define CHIP_NUM_57712_MF 0x1663 1185 #define CHIP_NUM_57712_VF 0x166f 1186 #define CHIP_NUM_57800 0x168a 1187 #define CHIP_NUM_57800_MF 0x16a5 1188 #define CHIP_NUM_57800_VF 0x16a9 1189 #define CHIP_NUM_57810 0x168e 1190 #define CHIP_NUM_57810_MF 0x16ae 1191 #define CHIP_NUM_57810_VF 0x16af 1192 #define CHIP_NUM_57811 0x163d 1193 #define CHIP_NUM_57811_MF 0x163e 1194 #define CHIP_NUM_57811_VF 0x163f 1195 #define CHIP_NUM_57840_OBS 0x168d 1196 #define CHIP_NUM_57840_OBS_MF 0x16ab 1197 #define CHIP_NUM_57840_4_10 0x16a1 1198 #define CHIP_NUM_57840_2_20 0x16a2 1199 #define CHIP_NUM_57840_MF 0x16a4 1200 #define CHIP_NUM_57840_VF 0x16ad 1201 1202 #define CHIP_REV_SHIFT 12 1203 #define CHIP_REV_MASK (0xF << CHIP_REV_SHIFT) 1204 #define CHIP_REV(sc) ((sc)->devinfo.chip_id & CHIP_REV_MASK) 1205 1206 #define CHIP_REV_Ax (0x0 << CHIP_REV_SHIFT) 1207 #define CHIP_REV_Bx (0x1 << CHIP_REV_SHIFT) 1208 #define CHIP_REV_Cx (0x2 << CHIP_REV_SHIFT) 1209 1210 #define CHIP_REV_IS_SLOW(sc) \ 1211 (CHIP_REV(sc) > 0x00005000) 1212 #define CHIP_REV_IS_FPGA(sc) \ 1213 (CHIP_REV_IS_SLOW(sc) && (CHIP_REV(sc) & 0x00001000)) 1214 #define CHIP_REV_IS_EMUL(sc) \ 1215 (CHIP_REV_IS_SLOW(sc) && !(CHIP_REV(sc) & 0x00001000)) 1216 #define CHIP_REV_IS_ASIC(sc) \ 1217 (!CHIP_REV_IS_SLOW(sc)) 1218 1219 #define CHIP_METAL(sc) ((sc->devinfo.chip_id) & 0x00000ff0) 1220 #define CHIP_BOND_ID(sc) ((sc->devinfo.chip_id) & 0x0000000f) 1221 1222 #define CHIP_IS_E1(sc) (CHIP_NUM(sc) == CHIP_NUM_57710) 1223 #define CHIP_IS_57710(sc) (CHIP_NUM(sc) == CHIP_NUM_57710) 1224 #define CHIP_IS_57711(sc) (CHIP_NUM(sc) == CHIP_NUM_57711) 1225 #define CHIP_IS_57711E(sc) (CHIP_NUM(sc) == CHIP_NUM_57711E) 1226 #define CHIP_IS_E1H(sc) ((CHIP_IS_57711(sc)) || \ 1227 (CHIP_IS_57711E(sc))) 1228 #define CHIP_IS_E1x(sc) (CHIP_IS_E1((sc)) || \ 1229 CHIP_IS_E1H((sc))) 1230 1231 #define CHIP_IS_57712(sc) (CHIP_NUM(sc) == CHIP_NUM_57712) 1232 #define CHIP_IS_57712_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57712_MF) 1233 #define CHIP_IS_57712_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57712_VF) 1234 #define CHIP_IS_E2(sc) (CHIP_IS_57712(sc) || \ 1235 CHIP_IS_57712_MF(sc)) 1236 1237 #define CHIP_IS_57800(sc) (CHIP_NUM(sc) == CHIP_NUM_57800) 1238 #define CHIP_IS_57800_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57800_MF) 1239 #define CHIP_IS_57800_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57800_VF) 1240 #define CHIP_IS_57810(sc) (CHIP_NUM(sc) == CHIP_NUM_57810) 1241 #define CHIP_IS_57810_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57810_MF) 1242 #define CHIP_IS_57810_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57810_VF) 1243 #define CHIP_IS_57811(sc) (CHIP_NUM(sc) == CHIP_NUM_57811) 1244 #define CHIP_IS_57811_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57811_MF) 1245 #define CHIP_IS_57811_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57811_VF) 1246 #define CHIP_IS_57840(sc) ((CHIP_NUM(sc) == CHIP_NUM_57840_OBS) || \ 1247 (CHIP_NUM(sc) == CHIP_NUM_57840_4_10) || \ 1248 (CHIP_NUM(sc) == CHIP_NUM_57840_2_20)) 1249 #define CHIP_IS_57840_MF(sc) ((CHIP_NUM(sc) == CHIP_NUM_57840_OBS_MF) || \ 1250 (CHIP_NUM(sc) == CHIP_NUM_57840_MF)) 1251 #define CHIP_IS_57840_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57840_VF) 1252 1253 #define CHIP_IS_E3(sc) (CHIP_IS_57800(sc) || \ 1254 CHIP_IS_57800_MF(sc) || \ 1255 CHIP_IS_57800_VF(sc) || \ 1256 CHIP_IS_57810(sc) || \ 1257 CHIP_IS_57810_MF(sc) || \ 1258 CHIP_IS_57810_VF(sc) || \ 1259 CHIP_IS_57811(sc) || \ 1260 CHIP_IS_57811_MF(sc) || \ 1261 CHIP_IS_57811_VF(sc) || \ 1262 CHIP_IS_57840(sc) || \ 1263 CHIP_IS_57840_MF(sc) || \ 1264 CHIP_IS_57840_VF(sc)) 1265 #define CHIP_IS_E3A0(sc) (CHIP_IS_E3(sc) && \ 1266 (CHIP_REV(sc) == CHIP_REV_Ax)) 1267 #define CHIP_IS_E3B0(sc) (CHIP_IS_E3(sc) && \ 1268 (CHIP_REV(sc) == CHIP_REV_Bx)) 1269 1270 #define USES_WARPCORE(sc) (CHIP_IS_E3(sc)) 1271 #define CHIP_IS_E2E3(sc) (CHIP_IS_E2(sc) || \ 1272 CHIP_IS_E3(sc)) 1273 1274 #define CHIP_IS_MF_CAP(sc) (CHIP_IS_57711E(sc) || \ 1275 CHIP_IS_57712_MF(sc) || \ 1276 CHIP_IS_E3(sc)) 1277 1278 #define IS_VF(sc) (CHIP_IS_57712_VF(sc) || \ 1279 CHIP_IS_57800_VF(sc) || \ 1280 CHIP_IS_57810_VF(sc) || \ 1281 CHIP_IS_57840_VF(sc)) 1282 #define IS_PF(sc) (!IS_VF(sc)) 1283 1284 /* 1285 * This define is used in two main places: 1286 * 1. In the early stages of nic_load, to know if to configure Parser/Searcher 1287 * to nic-only mode or to offload mode. Offload mode is configured if either 1288 * the chip is E1x (where NIC_MODE register is not applicable), or if cnic 1289 * already registered for this port (which means that the user wants storage 1290 * services). 1291 * 2. During cnic-related load, to know if offload mode is already configured 1292 * in the HW or needs to be configrued. Since the transition from nic-mode to 1293 * offload-mode in HW causes traffic coruption, nic-mode is configured only 1294 * in ports on which storage services where never requested. 1295 */ 1296 #define CONFIGURE_NIC_MODE(sc) (!CHIP_IS_E1x(sc) && !CNIC_ENABLED(sc)) 1297 1298 uint8_t chip_port_mode; 1299 #define CHIP_4_PORT_MODE 0x0 1300 #define CHIP_2_PORT_MODE 0x1 1301 #define CHIP_PORT_MODE_NONE 0x2 1302 #define CHIP_PORT_MODE(sc) ((sc)->devinfo.chip_port_mode) 1303 #define CHIP_IS_MODE_4_PORT(sc) (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) 1304 1305 uint8_t int_block; 1306 #define INT_BLOCK_HC 0 1307 #define INT_BLOCK_IGU 1 1308 #define INT_BLOCK_MODE_NORMAL 0 1309 #define INT_BLOCK_MODE_BW_COMP 2 1310 #define CHIP_INT_MODE_IS_NBC(sc) \ 1311 (!CHIP_IS_E1x(sc) && \ 1312 !((sc)->devinfo.int_block & INT_BLOCK_MODE_BW_COMP)) 1313 #define CHIP_INT_MODE_IS_BC(sc) (!CHIP_INT_MODE_IS_NBC(sc)) 1314 1315 uint32_t shmem_base; 1316 uint32_t shmem2_base; 1317 uint32_t bc_ver; 1318 char bc_ver_str[32]; 1319 uint32_t mf_cfg_base; /* bootcode shmem address in BAR memory */ 1320 struct bxe_mf_info mf_info; 1321 1322 int flash_size; 1323 #define NVRAM_1MB_SIZE 0x20000 1324 #define NVRAM_TIMEOUT_COUNT 30000 1325 #define NVRAM_PAGE_SIZE 256 1326 1327 /* PCIe capability information */ 1328 uint32_t pcie_cap_flags; 1329 #define BXE_PM_CAPABLE_FLAG 0x00000001 1330 #define BXE_PCIE_CAPABLE_FLAG 0x00000002 1331 #define BXE_MSI_CAPABLE_FLAG 0x00000004 1332 #define BXE_MSIX_CAPABLE_FLAG 0x00000008 1333 uint16_t pcie_pm_cap_reg; 1334 uint16_t pcie_pcie_cap_reg; 1335 //uint16_t pcie_devctl; 1336 uint16_t pcie_link_width; 1337 uint16_t pcie_link_speed; 1338 uint16_t pcie_msi_cap_reg; 1339 uint16_t pcie_msix_cap_reg; 1340 1341 /* device configuration read from bootcode shared memory */ 1342 uint32_t hw_config; 1343 uint32_t hw_config2; 1344 }; /* struct bxe_devinfo */ 1345 1346 struct bxe_sp_objs { 1347 struct ecore_vlan_mac_obj mac_obj; /* MACs object */ 1348 struct ecore_queue_sp_obj q_obj; /* Queue State object */ 1349 }; /* struct bxe_sp_objs */ 1350 1351 /* 1352 * Data that will be used to create a link report message. We will keep the 1353 * data used for the last link report in order to prevent reporting the same 1354 * link parameters twice. 1355 */ 1356 struct bxe_link_report_data { 1357 uint16_t line_speed; /* Effective line speed */ 1358 unsigned long link_report_flags; /* BXE_LINK_REPORT_XXX flags */ 1359 }; 1360 enum { 1361 BXE_LINK_REPORT_FULL_DUPLEX, 1362 BXE_LINK_REPORT_LINK_DOWN, 1363 BXE_LINK_REPORT_RX_FC_ON, 1364 BXE_LINK_REPORT_TX_FC_ON 1365 }; 1366 1367 /* Top level device private data structure. */ 1368 struct bxe_softc { 1369 /* 1370 * First entry must be a pointer to the BSD ifnet struct which 1371 * has a first element of 'void *if_softc' (which is us). XXX 1372 */ 1373 if_t ifp; 1374 struct ifmedia ifmedia; /* network interface media structure */ 1375 int media; 1376 1377 int state; /* device state */ 1378 #define BXE_STATE_CLOSED 0x0000 1379 #define BXE_STATE_OPENING_WAITING_LOAD 0x1000 1380 #define BXE_STATE_OPENING_WAITING_PORT 0x2000 1381 #define BXE_STATE_OPEN 0x3000 1382 #define BXE_STATE_CLOSING_WAITING_HALT 0x4000 1383 #define BXE_STATE_CLOSING_WAITING_DELETE 0x5000 1384 #define BXE_STATE_CLOSING_WAITING_UNLOAD 0x6000 1385 #define BXE_STATE_DISABLED 0xD000 1386 #define BXE_STATE_DIAG 0xE000 1387 #define BXE_STATE_ERROR 0xF000 1388 1389 int flags; 1390 #define BXE_ONE_PORT_FLAG 0x00000001 1391 #define BXE_NO_ISCSI 0x00000002 1392 #define BXE_NO_FCOE 0x00000004 1393 #define BXE_ONE_PORT(sc) (sc->flags & BXE_ONE_PORT_FLAG) 1394 //#define BXE_NO_WOL_FLAG 0x00000008 1395 //#define BXE_USING_DAC_FLAG 0x00000010 1396 //#define BXE_USING_MSIX_FLAG 0x00000020 1397 //#define BXE_USING_MSI_FLAG 0x00000040 1398 //#define BXE_DISABLE_MSI_FLAG 0x00000080 1399 #define BXE_NO_MCP_FLAG 0x00000200 1400 #define BXE_NOMCP(sc) (sc->flags & BXE_NO_MCP_FLAG) 1401 //#define BXE_SAFC_TX_FLAG 0x00000400 1402 #define BXE_MF_FUNC_DIS 0x00000800 1403 #define BXE_TX_SWITCHING 0x00001000 1404 #define BXE_NO_PULSE 0x00002000 1405 1406 unsigned long debug; /* per-instance debug logging config */ 1407 1408 #define MAX_BARS 5 1409 struct bxe_bar bar[MAX_BARS]; /* map BARs 0, 2, 4 */ 1410 1411 uint16_t doorbell_size; 1412 1413 /* periodic timer callout */ 1414 #define PERIODIC_STOP 0 1415 #define PERIODIC_GO 1 1416 volatile unsigned long periodic_flags; 1417 struct callout periodic_callout; 1418 1419 /* chip start/stop/reset taskqueue */ 1420 #define CHIP_TQ_NONE 0 1421 #define CHIP_TQ_START 1 1422 #define CHIP_TQ_STOP 2 1423 #define CHIP_TQ_REINIT 3 1424 volatile unsigned long chip_tq_flags; 1425 struct task chip_tq_task; 1426 struct taskqueue *chip_tq; 1427 char chip_tq_name[32]; 1428 1429 /* slowpath interrupt taskqueue */ 1430 struct task sp_tq_task; 1431 struct taskqueue *sp_tq; 1432 char sp_tq_name[32]; 1433 1434 struct bxe_fastpath fp[MAX_RSS_CHAINS]; 1435 struct bxe_sp_objs sp_objs[MAX_RSS_CHAINS]; 1436 1437 device_t dev; /* parent device handle */ 1438 uint8_t unit; /* driver instance number */ 1439 1440 int pcie_bus; /* PCIe bus number */ 1441 int pcie_device; /* PCIe device/slot number */ 1442 int pcie_func; /* PCIe function number */ 1443 1444 uint8_t pfunc_rel; /* function relative */ 1445 uint8_t pfunc_abs; /* function absolute */ 1446 uint8_t path_id; /* function absolute */ 1447 #define SC_PATH(sc) (sc->path_id) 1448 #define SC_PORT(sc) (sc->pfunc_rel & 1) 1449 #define SC_FUNC(sc) (sc->pfunc_rel) 1450 #define SC_ABS_FUNC(sc) (sc->pfunc_abs) 1451 #define SC_VN(sc) (sc->pfunc_rel >> 1) 1452 #define SC_L_ID(sc) (SC_VN(sc) << 2) 1453 #define PORT_ID(sc) SC_PORT(sc) 1454 #define PATH_ID(sc) SC_PATH(sc) 1455 #define VNIC_ID(sc) SC_VN(sc) 1456 #define FUNC_ID(sc) SC_FUNC(sc) 1457 #define ABS_FUNC_ID(sc) SC_ABS_FUNC(sc) 1458 #define SC_FW_MB_IDX_VN(sc, vn) \ 1459 (SC_PORT(sc) + (vn) * \ 1460 ((CHIP_IS_E1x(sc) || (CHIP_IS_MODE_4_PORT(sc))) ? 2 : 1)) 1461 #define SC_FW_MB_IDX(sc) SC_FW_MB_IDX_VN(sc, SC_VN(sc)) 1462 1463 int if_capen; /* enabled interface capabilities */ 1464 1465 struct bxe_devinfo devinfo; 1466 char fw_ver_str[32]; 1467 char mf_mode_str[32]; 1468 char pci_link_str[32]; 1469 1470 const struct iro *iro_array; 1471 1472 #ifdef BXE_CORE_LOCK_SX 1473 struct sx core_sx; 1474 char core_sx_name[32]; 1475 #else 1476 struct mtx core_mtx; 1477 char core_mtx_name[32]; 1478 #endif 1479 struct mtx sp_mtx; 1480 char sp_mtx_name[32]; 1481 struct mtx dmae_mtx; 1482 char dmae_mtx_name[32]; 1483 struct mtx fwmb_mtx; 1484 char fwmb_mtx_name[32]; 1485 struct mtx print_mtx; 1486 char print_mtx_name[32]; 1487 struct mtx stats_mtx; 1488 char stats_mtx_name[32]; 1489 struct mtx mcast_mtx; 1490 char mcast_mtx_name[32]; 1491 1492 #ifdef BXE_CORE_LOCK_SX 1493 #define BXE_CORE_TRYLOCK(sc) sx_try_xlock(&sc->core_sx) 1494 #define BXE_CORE_LOCK(sc) sx_xlock(&sc->core_sx) 1495 #define BXE_CORE_UNLOCK(sc) sx_xunlock(&sc->core_sx) 1496 #define BXE_CORE_LOCK_ASSERT(sc) sx_assert(&sc->core_sx, SA_XLOCKED) 1497 #else 1498 #define BXE_CORE_TRYLOCK(sc) mtx_trylock(&sc->core_mtx) 1499 #define BXE_CORE_LOCK(sc) mtx_lock(&sc->core_mtx) 1500 #define BXE_CORE_UNLOCK(sc) mtx_unlock(&sc->core_mtx) 1501 #define BXE_CORE_LOCK_ASSERT(sc) mtx_assert(&sc->core_mtx, MA_OWNED) 1502 #endif 1503 1504 #define BXE_SP_LOCK(sc) mtx_lock(&sc->sp_mtx) 1505 #define BXE_SP_UNLOCK(sc) mtx_unlock(&sc->sp_mtx) 1506 #define BXE_SP_LOCK_ASSERT(sc) mtx_assert(&sc->sp_mtx, MA_OWNED) 1507 1508 #define BXE_DMAE_LOCK(sc) mtx_lock(&sc->dmae_mtx) 1509 #define BXE_DMAE_UNLOCK(sc) mtx_unlock(&sc->dmae_mtx) 1510 #define BXE_DMAE_LOCK_ASSERT(sc) mtx_assert(&sc->dmae_mtx, MA_OWNED) 1511 1512 #define BXE_FWMB_LOCK(sc) mtx_lock(&sc->fwmb_mtx) 1513 #define BXE_FWMB_UNLOCK(sc) mtx_unlock(&sc->fwmb_mtx) 1514 #define BXE_FWMB_LOCK_ASSERT(sc) mtx_assert(&sc->fwmb_mtx, MA_OWNED) 1515 1516 #define BXE_PRINT_LOCK(sc) mtx_lock(&sc->print_mtx) 1517 #define BXE_PRINT_UNLOCK(sc) mtx_unlock(&sc->print_mtx) 1518 #define BXE_PRINT_LOCK_ASSERT(sc) mtx_assert(&sc->print_mtx, MA_OWNED) 1519 1520 #define BXE_STATS_LOCK(sc) mtx_lock(&sc->stats_mtx) 1521 #define BXE_STATS_UNLOCK(sc) mtx_unlock(&sc->stats_mtx) 1522 #define BXE_STATS_LOCK_ASSERT(sc) mtx_assert(&sc->stats_mtx, MA_OWNED) 1523 1524 #if __FreeBSD_version < 800000 1525 #define BXE_MCAST_LOCK(sc) \ 1526 do { \ 1527 mtx_lock(&sc->mcast_mtx); \ 1528 IF_ADDR_LOCK(sc->ifp); \ 1529 } while (0) 1530 #define BXE_MCAST_UNLOCK(sc) \ 1531 do { \ 1532 IF_ADDR_UNLOCK(sc->ifp); \ 1533 mtx_unlock(&sc->mcast_mtx); \ 1534 } while (0) 1535 #else 1536 #define BXE_MCAST_LOCK(sc) \ 1537 do { \ 1538 mtx_lock(&sc->mcast_mtx); \ 1539 if_maddr_rlock(sc->ifp); \ 1540 } while (0) 1541 #define BXE_MCAST_UNLOCK(sc) \ 1542 do { \ 1543 if_maddr_runlock(sc->ifp); \ 1544 mtx_unlock(&sc->mcast_mtx); \ 1545 } while (0) 1546 #endif 1547 #define BXE_MCAST_LOCK_ASSERT(sc) mtx_assert(&sc->mcast_mtx, MA_OWNED) 1548 1549 int dmae_ready; 1550 #define DMAE_READY(sc) (sc->dmae_ready) 1551 1552 struct ecore_credit_pool_obj vlans_pool; 1553 struct ecore_credit_pool_obj macs_pool; 1554 struct ecore_rx_mode_obj rx_mode_obj; 1555 struct ecore_mcast_obj mcast_obj; 1556 struct ecore_rss_config_obj rss_conf_obj; 1557 struct ecore_func_sp_obj func_obj; 1558 1559 uint16_t fw_seq; 1560 uint16_t fw_drv_pulse_wr_seq; 1561 uint32_t func_stx; 1562 1563 struct elink_params link_params; 1564 struct elink_vars link_vars; 1565 uint32_t link_cnt; 1566 struct bxe_link_report_data last_reported_link; 1567 char mac_addr_str[32]; 1568 1569 int last_reported_link_state; 1570 1571 int tx_ring_size; 1572 int rx_ring_size; 1573 int wol; 1574 1575 int is_leader; 1576 int recovery_state; 1577 #define BXE_RECOVERY_DONE 1 1578 #define BXE_RECOVERY_INIT 2 1579 #define BXE_RECOVERY_WAIT 3 1580 #define BXE_RECOVERY_FAILED 4 1581 #define BXE_RECOVERY_NIC_LOADING 5 1582 1583 uint32_t rx_mode; 1584 #define BXE_RX_MODE_NONE 0 1585 #define BXE_RX_MODE_NORMAL 1 1586 #define BXE_RX_MODE_ALLMULTI 2 1587 #define BXE_RX_MODE_PROMISC 3 1588 #define BXE_MAX_MULTICAST 64 1589 1590 struct bxe_port port; 1591 1592 struct cmng_init cmng; 1593 1594 /* user configs */ 1595 int num_queues; 1596 int max_rx_bufs; 1597 int hc_rx_ticks; 1598 int hc_tx_ticks; 1599 int rx_budget; 1600 int max_aggregation_size; 1601 int mrrs; 1602 int autogreeen; 1603 #define AUTO_GREEN_HW_DEFAULT 0 1604 #define AUTO_GREEN_FORCE_ON 1 1605 #define AUTO_GREEN_FORCE_OFF 2 1606 int interrupt_mode; 1607 #define INTR_MODE_INTX 0 1608 #define INTR_MODE_MSI 1 1609 #define INTR_MODE_MSIX 2 1610 int udp_rss; 1611 1612 /* interrupt allocations */ 1613 struct bxe_intr intr[MAX_RSS_CHAINS+1]; 1614 int intr_count; 1615 uint8_t igu_dsb_id; 1616 uint8_t igu_base_sb; 1617 uint8_t igu_sb_cnt; 1618 //uint8_t min_msix_vec_cnt; 1619 uint32_t igu_base_addr; 1620 //bus_addr_t def_status_blk_mapping; 1621 uint8_t base_fw_ndsb; 1622 #define DEF_SB_IGU_ID 16 1623 #define DEF_SB_ID HC_SP_SB_ID 1624 1625 /* parent bus DMA tag */ 1626 bus_dma_tag_t parent_dma_tag; 1627 1628 /* default status block */ 1629 struct bxe_dma def_sb_dma; 1630 struct host_sp_status_block *def_sb; 1631 uint16_t def_idx; 1632 uint16_t def_att_idx; 1633 uint32_t attn_state; 1634 struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS]; 1635 1636 /* general SP events - stats query, cfc delete, etc */ 1637 #define HC_SP_INDEX_ETH_DEF_CONS 3 1638 /* EQ completions */ 1639 #define HC_SP_INDEX_EQ_CONS 7 1640 /* FCoE L2 connection completions */ 1641 #define HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS 6 1642 #define HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS 4 1643 /* iSCSI L2 */ 1644 #define HC_SP_INDEX_ETH_ISCSI_CQ_CONS 5 1645 #define HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS 1 1646 1647 /* event queue */ 1648 struct bxe_dma eq_dma; 1649 union event_ring_elem *eq; 1650 uint16_t eq_prod; 1651 uint16_t eq_cons; 1652 uint16_t *eq_cons_sb; 1653 #define NUM_EQ_PAGES 1 /* must be a power of 2 */ 1654 #define EQ_DESC_CNT_PAGE (BCM_PAGE_SIZE / sizeof(union event_ring_elem)) 1655 #define EQ_DESC_MAX_PAGE (EQ_DESC_CNT_PAGE - 1) 1656 #define NUM_EQ_DESC (EQ_DESC_CNT_PAGE * NUM_EQ_PAGES) 1657 #define EQ_DESC_MASK (NUM_EQ_DESC - 1) 1658 #define MAX_EQ_AVAIL (EQ_DESC_MAX_PAGE * NUM_EQ_PAGES - 2) 1659 /* depends on EQ_DESC_CNT_PAGE being a power of 2 */ 1660 #define NEXT_EQ_IDX(x) \ 1661 ((((x) & EQ_DESC_MAX_PAGE) == (EQ_DESC_MAX_PAGE - 1)) ? \ 1662 ((x) + 2) : ((x) + 1)) 1663 /* depends on the above and on NUM_EQ_PAGES being a power of 2 */ 1664 #define EQ_DESC(x) ((x) & EQ_DESC_MASK) 1665 1666 /* slow path */ 1667 struct bxe_dma sp_dma; 1668 struct bxe_slowpath *sp; 1669 unsigned long sp_state; 1670 1671 /* slow path queue */ 1672 struct bxe_dma spq_dma; 1673 struct eth_spe *spq; 1674 #define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe)) 1675 #define MAX_SP_DESC_CNT (SP_DESC_CNT - 1) 1676 #define MAX_SPQ_PENDING 8 1677 1678 uint16_t spq_prod_idx; 1679 struct eth_spe *spq_prod_bd; 1680 struct eth_spe *spq_last_bd; 1681 uint16_t *dsb_sp_prod; 1682 //uint16_t *spq_hw_con; 1683 //uint16_t spq_left; 1684 1685 volatile unsigned long eq_spq_left; /* COMMON_xxx ramrod credit */ 1686 volatile unsigned long cq_spq_left; /* ETH_xxx ramrod credit */ 1687 1688 /* fw decompression buffer */ 1689 struct bxe_dma gz_buf_dma; 1690 void *gz_buf; 1691 z_streamp gz_strm; 1692 uint32_t gz_outlen; 1693 #define GUNZIP_BUF(sc) (sc->gz_buf) 1694 #define GUNZIP_OUTLEN(sc) (sc->gz_outlen) 1695 #define GUNZIP_PHYS(sc) (sc->gz_buf_dma.paddr) 1696 #define FW_BUF_SIZE 0x40000 1697 1698 const struct raw_op *init_ops; 1699 const uint16_t *init_ops_offsets; /* init block offsets inside init_ops */ 1700 const uint32_t *init_data; /* data blob, 32 bit granularity */ 1701 uint32_t init_mode_flags; 1702 #define INIT_MODE_FLAGS(sc) (sc->init_mode_flags) 1703 /* PRAM blobs - raw data */ 1704 const uint8_t *tsem_int_table_data; 1705 const uint8_t *tsem_pram_data; 1706 const uint8_t *usem_int_table_data; 1707 const uint8_t *usem_pram_data; 1708 const uint8_t *xsem_int_table_data; 1709 const uint8_t *xsem_pram_data; 1710 const uint8_t *csem_int_table_data; 1711 const uint8_t *csem_pram_data; 1712 #define INIT_OPS(sc) (sc->init_ops) 1713 #define INIT_OPS_OFFSETS(sc) (sc->init_ops_offsets) 1714 #define INIT_DATA(sc) (sc->init_data) 1715 #define INIT_TSEM_INT_TABLE_DATA(sc) (sc->tsem_int_table_data) 1716 #define INIT_TSEM_PRAM_DATA(sc) (sc->tsem_pram_data) 1717 #define INIT_USEM_INT_TABLE_DATA(sc) (sc->usem_int_table_data) 1718 #define INIT_USEM_PRAM_DATA(sc) (sc->usem_pram_data) 1719 #define INIT_XSEM_INT_TABLE_DATA(sc) (sc->xsem_int_table_data) 1720 #define INIT_XSEM_PRAM_DATA(sc) (sc->xsem_pram_data) 1721 #define INIT_CSEM_INT_TABLE_DATA(sc) (sc->csem_int_table_data) 1722 #define INIT_CSEM_PRAM_DATA(sc) (sc->csem_pram_data) 1723 1724 /* ILT 1725 * For max 196 cids (64*3 + non-eth), 32KB ILT page size and 1KB 1726 * context size we need 8 ILT entries. 1727 */ 1728 #define ILT_MAX_L2_LINES 8 1729 struct hw_context context[ILT_MAX_L2_LINES]; 1730 struct ecore_ilt *ilt; 1731 #define ILT_MAX_LINES 256 1732 1733 /* max supported number of RSS queues: IGU SBs minus one for CNIC */ 1734 #define BXE_MAX_RSS_COUNT(sc) ((sc)->igu_sb_cnt - CNIC_SUPPORT(sc)) 1735 /* max CID count: Max RSS * Max_Tx_Multi_Cos + FCoE + iSCSI */ 1736 #if 1 1737 #define BXE_L2_MAX_CID(sc) \ 1738 (BXE_MAX_RSS_COUNT(sc) * ECORE_MULTI_TX_COS + 2 * CNIC_SUPPORT(sc)) 1739 #else 1740 #define BXE_L2_MAX_CID(sc) /* OOO + FWD */ \ 1741 (BXE_MAX_RSS_COUNT(sc) * ECORE_MULTI_TX_COS + 4 * CNIC_SUPPORT(sc)) 1742 #endif 1743 #if 1 1744 #define BXE_L2_CID_COUNT(sc) \ 1745 (BXE_NUM_ETH_QUEUES(sc) * ECORE_MULTI_TX_COS + 2 * CNIC_SUPPORT(sc)) 1746 #else 1747 #define BXE_L2_CID_COUNT(sc) /* OOO + FWD */ \ 1748 (BXE_NUM_ETH_QUEUES(sc) * ECORE_MULTI_TX_COS + 4 * CNIC_SUPPORT(sc)) 1749 #endif 1750 #define L2_ILT_LINES(sc) \ 1751 (DIV_ROUND_UP(BXE_L2_CID_COUNT(sc), ILT_PAGE_CIDS)) 1752 1753 int qm_cid_count; 1754 1755 uint8_t dropless_fc; 1756 1757 #if 0 1758 struct bxe_dma *t2; 1759 #endif 1760 1761 /* total number of FW statistics requests */ 1762 uint8_t fw_stats_num; 1763 /* 1764 * This is a memory buffer that will contain both statistics ramrod 1765 * request and data. 1766 */ 1767 struct bxe_dma fw_stats_dma; 1768 /* 1769 * FW statistics request shortcut (points at the beginning of fw_stats 1770 * buffer). 1771 */ 1772 int fw_stats_req_size; 1773 struct bxe_fw_stats_req *fw_stats_req; 1774 bus_addr_t fw_stats_req_mapping; 1775 /* 1776 * FW statistics data shortcut (points at the beginning of fw_stats 1777 * buffer + fw_stats_req_size). 1778 */ 1779 int fw_stats_data_size; 1780 struct bxe_fw_stats_data *fw_stats_data; 1781 bus_addr_t fw_stats_data_mapping; 1782 1783 /* tracking a pending STAT_QUERY ramrod */ 1784 uint16_t stats_pending; 1785 /* number of completed statistics ramrods */ 1786 uint16_t stats_comp; 1787 uint16_t stats_counter; 1788 uint8_t stats_init; 1789 int stats_state; 1790 1791 struct bxe_eth_stats eth_stats; 1792 struct host_func_stats func_stats; 1793 struct bxe_eth_stats_old eth_stats_old; 1794 struct bxe_net_stats_old net_stats_old; 1795 struct bxe_fw_port_stats_old fw_stats_old; 1796 1797 struct dmae_command stats_dmae; /* used by dmae command loader */ 1798 int executer_idx; 1799 1800 int mtu; 1801 1802 /* LLDP params */ 1803 struct bxe_config_lldp_params lldp_config_params; 1804 /* DCB support on/off */ 1805 int dcb_state; 1806 #define BXE_DCB_STATE_OFF 0 1807 #define BXE_DCB_STATE_ON 1 1808 /* DCBX engine mode */ 1809 int dcbx_enabled; 1810 #define BXE_DCBX_ENABLED_OFF 0 1811 #define BXE_DCBX_ENABLED_ON_NEG_OFF 1 1812 #define BXE_DCBX_ENABLED_ON_NEG_ON 2 1813 #define BXE_DCBX_ENABLED_INVALID -1 1814 uint8_t dcbx_mode_uset; 1815 struct bxe_config_dcbx_params dcbx_config_params; 1816 struct bxe_dcbx_port_params dcbx_port_params; 1817 int dcb_version; 1818 1819 uint8_t cnic_support; 1820 uint8_t cnic_enabled; 1821 uint8_t cnic_loaded; 1822 #define CNIC_SUPPORT(sc) 0 /* ((sc)->cnic_support) */ 1823 #define CNIC_ENABLED(sc) 0 /* ((sc)->cnic_enabled) */ 1824 #define CNIC_LOADED(sc) 0 /* ((sc)->cnic_loaded) */ 1825 1826 /* multiple tx classes of service */ 1827 uint8_t max_cos; 1828 #define BXE_MAX_PRIORITY 8 1829 /* priority to cos mapping */ 1830 uint8_t prio_to_cos[BXE_MAX_PRIORITY]; 1831 1832 int panic; 1833 1834 struct cdev *ioctl_dev; 1835 void *grc_dump; 1836 int trigger_grcdump; 1837 int grcdump_done; 1838 }; /* struct bxe_softc */ 1839 1840 /* IOCTL sub-commands for edebug and firmware upgrade */ 1841 #define BXE_IOC_RD_NVRAM 1 1842 #define BXE_IOC_WR_NVRAM 2 1843 #define BXE_IOC_STATS_SHOW_NUM 3 1844 #define BXE_IOC_STATS_SHOW_STR 4 1845 #define BXE_IOC_STATS_SHOW_CNT 5 1846 1847 struct bxe_nvram_data { 1848 uint32_t op; /* ioctl sub-command */ 1849 uint32_t offset; 1850 uint32_t len; 1851 uint32_t value[1]; /* variable */ 1852 }; 1853 1854 union bxe_stats_show_data { 1855 uint32_t op; /* ioctl sub-command */ 1856 1857 struct { 1858 uint32_t num; /* return number of stats */ 1859 uint32_t len; /* length of each string item */ 1860 } desc; 1861 1862 /* variable length... */ 1863 char str[1]; /* holds names of desc.num stats, each desc.len in length */ 1864 1865 /* variable length... */ 1866 uint64_t stats[1]; /* holds all stats */ 1867 }; 1868 1869 /* function init flags */ 1870 #define FUNC_FLG_RSS 0x0001 1871 #define FUNC_FLG_STATS 0x0002 1872 /* FUNC_FLG_UNMATCHED 0x0004 */ 1873 #define FUNC_FLG_TPA 0x0008 1874 #define FUNC_FLG_SPQ 0x0010 1875 #define FUNC_FLG_LEADING 0x0020 /* PF only */ 1876 1877 struct bxe_func_init_params { 1878 bus_addr_t fw_stat_map; /* (dma) valid if FUNC_FLG_STATS */ 1879 bus_addr_t spq_map; /* (dma) valid if FUNC_FLG_SPQ */ 1880 uint16_t func_flgs; 1881 uint16_t func_id; /* abs function id */ 1882 uint16_t pf_id; 1883 uint16_t spq_prod; /* valid if FUNC_FLG_SPQ */ 1884 }; 1885 1886 /* memory resources reside at BARs 0, 2, 4 */ 1887 /* Run `pciconf -lb` to see mappings */ 1888 #define BAR0 0 1889 #define BAR1 2 1890 #define BAR2 4 1891 1892 #ifdef BXE_REG_NO_INLINE 1893 1894 uint8_t bxe_reg_read8(struct bxe_softc *sc, bus_size_t offset); 1895 uint16_t bxe_reg_read16(struct bxe_softc *sc, bus_size_t offset); 1896 uint32_t bxe_reg_read32(struct bxe_softc *sc, bus_size_t offset); 1897 1898 void bxe_reg_write8(struct bxe_softc *sc, bus_size_t offset, uint8_t val); 1899 void bxe_reg_write16(struct bxe_softc *sc, bus_size_t offset, uint16_t val); 1900 void bxe_reg_write32(struct bxe_softc *sc, bus_size_t offset, uint32_t val); 1901 1902 #define REG_RD8(sc, offset) bxe_reg_read8(sc, offset) 1903 #define REG_RD16(sc, offset) bxe_reg_read16(sc, offset) 1904 #define REG_RD32(sc, offset) bxe_reg_read32(sc, offset) 1905 1906 #define REG_WR8(sc, offset, val) bxe_reg_write8(sc, offset, val) 1907 #define REG_WR16(sc, offset, val) bxe_reg_write16(sc, offset, val) 1908 #define REG_WR32(sc, offset, val) bxe_reg_write32(sc, offset, val) 1909 1910 #else /* not BXE_REG_NO_INLINE */ 1911 1912 #define REG_WR8(sc, offset, val) \ 1913 bus_space_write_1(sc->bar[BAR0].tag, \ 1914 sc->bar[BAR0].handle, \ 1915 offset, val) 1916 1917 #define REG_WR16(sc, offset, val) \ 1918 bus_space_write_2(sc->bar[BAR0].tag, \ 1919 sc->bar[BAR0].handle, \ 1920 offset, val) 1921 1922 #define REG_WR32(sc, offset, val) \ 1923 bus_space_write_4(sc->bar[BAR0].tag, \ 1924 sc->bar[BAR0].handle, \ 1925 offset, val) 1926 1927 #define REG_RD8(sc, offset) \ 1928 bus_space_read_1(sc->bar[BAR0].tag, \ 1929 sc->bar[BAR0].handle, \ 1930 offset) 1931 1932 #define REG_RD16(sc, offset) \ 1933 bus_space_read_2(sc->bar[BAR0].tag, \ 1934 sc->bar[BAR0].handle, \ 1935 offset) 1936 1937 #define REG_RD32(sc, offset) \ 1938 bus_space_read_4(sc->bar[BAR0].tag, \ 1939 sc->bar[BAR0].handle, \ 1940 offset) 1941 1942 #endif /* BXE_REG_NO_INLINE */ 1943 1944 #define REG_RD(sc, offset) REG_RD32(sc, offset) 1945 #define REG_WR(sc, offset, val) REG_WR32(sc, offset, val) 1946 1947 #define REG_RD_IND(sc, offset) bxe_reg_rd_ind(sc, offset) 1948 #define REG_WR_IND(sc, offset, val) bxe_reg_wr_ind(sc, offset, val) 1949 1950 #define BXE_SP(sc, var) (&(sc)->sp->var) 1951 #define BXE_SP_MAPPING(sc, var) \ 1952 (sc->sp_dma.paddr + offsetof(struct bxe_slowpath, var)) 1953 1954 #define BXE_FP(sc, nr, var) ((sc)->fp[(nr)].var) 1955 #define BXE_SP_OBJ(sc, fp) ((sc)->sp_objs[(fp)->index]) 1956 1957 #if 0 1958 #define bxe_fp(sc, nr, var) ((sc)->fp[nr].var) 1959 #define bxe_sp_obj(sc, fp) ((sc)->sp_objs[(fp)->index]) 1960 #define bxe_fp_stats(sc, fp) (&(sc)->fp_stats[(fp)->index]) 1961 #define bxe_fp_qstats(sc, fp) (&(sc)->fp_stats[(fp)->index].eth_q_stats) 1962 #endif 1963 1964 #define REG_RD_DMAE(sc, offset, valp, len32) \ 1965 do { \ 1966 bxe_read_dmae(sc, offset, len32); \ 1967 memcpy(valp, BXE_SP(sc, wb_data[0]), (len32) * 4); \ 1968 } while (0) 1969 1970 #define REG_WR_DMAE(sc, offset, valp, len32) \ 1971 do { \ 1972 memcpy(BXE_SP(sc, wb_data[0]), valp, (len32) * 4); \ 1973 bxe_write_dmae(sc, BXE_SP_MAPPING(sc, wb_data), offset, len32); \ 1974 } while (0) 1975 1976 #define REG_WR_DMAE_LEN(sc, offset, valp, len32) \ 1977 REG_WR_DMAE(sc, offset, valp, len32) 1978 1979 #define REG_RD_DMAE_LEN(sc, offset, valp, len32) \ 1980 REG_RD_DMAE(sc, offset, valp, len32) 1981 1982 #define VIRT_WR_DMAE_LEN(sc, data, addr, len32, le32_swap) \ 1983 do { \ 1984 /* if (le32_swap) { */ \ 1985 /* BLOGW(sc, "VIRT_WR_DMAE_LEN with le32_swap=1\n"); */ \ 1986 /* } */ \ 1987 memcpy(GUNZIP_BUF(sc), data, len32 * 4); \ 1988 ecore_write_big_buf_wb(sc, addr, len32); \ 1989 } while (0) 1990 1991 #define BXE_DB_MIN_SHIFT 3 /* 8 bytes */ 1992 #define BXE_DB_SHIFT 7 /* 128 bytes */ 1993 #if (BXE_DB_SHIFT < BXE_DB_MIN_SHIFT) 1994 #error "Minimum DB doorbell stride is 8" 1995 #endif 1996 #define DPM_TRIGGER_TYPE 0x40 1997 #define DOORBELL(sc, cid, val) \ 1998 do { \ 1999 bus_space_write_4(sc->bar[BAR1].tag, sc->bar[BAR1].handle, \ 2000 ((sc->doorbell_size * (cid)) + DPM_TRIGGER_TYPE), \ 2001 (uint32_t)val); \ 2002 } while(0) 2003 2004 #define SHMEM_ADDR(sc, field) \ 2005 (sc->devinfo.shmem_base + offsetof(struct shmem_region, field)) 2006 #define SHMEM_RD(sc, field) REG_RD(sc, SHMEM_ADDR(sc, field)) 2007 #define SHMEM_RD16(sc, field) REG_RD16(sc, SHMEM_ADDR(sc, field)) 2008 #define SHMEM_WR(sc, field, val) REG_WR(sc, SHMEM_ADDR(sc, field), val) 2009 2010 #define SHMEM2_ADDR(sc, field) \ 2011 (sc->devinfo.shmem2_base + offsetof(struct shmem2_region, field)) 2012 #define SHMEM2_HAS(sc, field) \ 2013 (sc->devinfo.shmem2_base && (REG_RD(sc, SHMEM2_ADDR(sc, size)) > \ 2014 offsetof(struct shmem2_region, field))) 2015 #define SHMEM2_RD(sc, field) REG_RD(sc, SHMEM2_ADDR(sc, field)) 2016 #define SHMEM2_WR(sc, field, val) REG_WR(sc, SHMEM2_ADDR(sc, field), val) 2017 2018 #define MFCFG_ADDR(sc, field) \ 2019 (sc->devinfo.mf_cfg_base + offsetof(struct mf_cfg, field)) 2020 #define MFCFG_RD(sc, field) REG_RD(sc, MFCFG_ADDR(sc, field)) 2021 #define MFCFG_RD16(sc, field) REG_RD16(sc, MFCFG_ADDR(sc, field)) 2022 #define MFCFG_WR(sc, field, val) REG_WR(sc, MFCFG_ADDR(sc, field), val) 2023 2024 /* DMAE command defines */ 2025 2026 #define DMAE_TIMEOUT -1 2027 #define DMAE_PCI_ERROR -2 /* E2 and onward */ 2028 #define DMAE_NOT_RDY -3 2029 #define DMAE_PCI_ERR_FLAG 0x80000000 2030 2031 #define DMAE_SRC_PCI 0 2032 #define DMAE_SRC_GRC 1 2033 2034 #define DMAE_DST_NONE 0 2035 #define DMAE_DST_PCI 1 2036 #define DMAE_DST_GRC 2 2037 2038 #define DMAE_COMP_PCI 0 2039 #define DMAE_COMP_GRC 1 2040 2041 #define DMAE_COMP_REGULAR 0 2042 #define DMAE_COM_SET_ERR 1 2043 2044 #define DMAE_CMD_SRC_PCI (DMAE_SRC_PCI << DMAE_COMMAND_SRC_SHIFT) 2045 #define DMAE_CMD_SRC_GRC (DMAE_SRC_GRC << DMAE_COMMAND_SRC_SHIFT) 2046 #define DMAE_CMD_DST_PCI (DMAE_DST_PCI << DMAE_COMMAND_DST_SHIFT) 2047 #define DMAE_CMD_DST_GRC (DMAE_DST_GRC << DMAE_COMMAND_DST_SHIFT) 2048 2049 #define DMAE_CMD_C_DST_PCI (DMAE_COMP_PCI << DMAE_COMMAND_C_DST_SHIFT) 2050 #define DMAE_CMD_C_DST_GRC (DMAE_COMP_GRC << DMAE_COMMAND_C_DST_SHIFT) 2051 2052 #define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT) 2053 #define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_COMMAND_ENDIANITY_SHIFT) 2054 #define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_COMMAND_ENDIANITY_SHIFT) 2055 #define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT) 2056 2057 #define DMAE_CMD_PORT_0 0 2058 #define DMAE_CMD_PORT_1 DMAE_COMMAND_PORT 2059 2060 #define DMAE_SRC_PF 0 2061 #define DMAE_SRC_VF 1 2062 2063 #define DMAE_DST_PF 0 2064 #define DMAE_DST_VF 1 2065 2066 #define DMAE_C_SRC 0 2067 #define DMAE_C_DST 1 2068 2069 #define DMAE_LEN32_RD_MAX 0x80 2070 #define DMAE_LEN32_WR_MAX(sc) (CHIP_IS_E1(sc) ? 0x400 : 0x2000) 2071 2072 #define DMAE_COMP_VAL 0x60d0d0ae /* E2 and beyond, upper bit indicates error */ 2073 2074 #define MAX_DMAE_C_PER_PORT 8 2075 #define INIT_DMAE_C(sc) ((SC_PORT(sc) * MAX_DMAE_C_PER_PORT) + SC_VN(sc)) 2076 #define PMF_DMAE_C(sc) ((SC_PORT(sc) * MAX_DMAE_C_PER_PORT) + E1HVN_MAX) 2077 2078 static const uint32_t dmae_reg_go_c[] = { 2079 DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3, 2080 DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7, 2081 DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11, 2082 DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15 2083 }; 2084 2085 #define ATTN_NIG_FOR_FUNC (1L << 8) 2086 #define ATTN_SW_TIMER_4_FUNC (1L << 9) 2087 #define GPIO_2_FUNC (1L << 10) 2088 #define GPIO_3_FUNC (1L << 11) 2089 #define GPIO_4_FUNC (1L << 12) 2090 #define ATTN_GENERAL_ATTN_1 (1L << 13) 2091 #define ATTN_GENERAL_ATTN_2 (1L << 14) 2092 #define ATTN_GENERAL_ATTN_3 (1L << 15) 2093 #define ATTN_GENERAL_ATTN_4 (1L << 13) 2094 #define ATTN_GENERAL_ATTN_5 (1L << 14) 2095 #define ATTN_GENERAL_ATTN_6 (1L << 15) 2096 #define ATTN_HARD_WIRED_MASK 0xff00 2097 #define ATTENTION_ID 4 2098 2099 #define AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR \ 2100 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR 2101 2102 #define MAX_IGU_ATTN_ACK_TO 100 2103 2104 #define STORM_ASSERT_ARRAY_SIZE 50 2105 2106 #define BXE_PMF_LINK_ASSERT(sc) \ 2107 GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + SC_FUNC(sc)) 2108 2109 #define BXE_MC_ASSERT_BITS \ 2110 (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \ 2111 GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \ 2112 GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \ 2113 GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT)) 2114 2115 #define BXE_MCP_ASSERT \ 2116 GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT) 2117 2118 #define BXE_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC) 2119 #define BXE_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \ 2120 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \ 2121 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \ 2122 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \ 2123 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \ 2124 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC)) 2125 2126 #define MULTI_MASK 0x7f 2127 2128 #define PFS_PER_PORT(sc) \ 2129 ((CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4) 2130 #define SC_MAX_VN_NUM(sc) PFS_PER_PORT(sc) 2131 2132 #define FIRST_ABS_FUNC_IN_PORT(sc) \ 2133 ((CHIP_PORT_MODE(sc) == CHIP_PORT_MODE_NONE) ? \ 2134 PORT_ID(sc) : (PATH_ID(sc) + (2 * PORT_ID(sc)))) 2135 2136 #define FOREACH_ABS_FUNC_IN_PORT(sc, i) \ 2137 for ((i) = FIRST_ABS_FUNC_IN_PORT(sc); \ 2138 (i) < MAX_FUNC_NUM; \ 2139 (i) += (MAX_FUNC_NUM / PFS_PER_PORT(sc))) 2140 2141 #define BXE_SWCID_SHIFT 17 2142 #define BXE_SWCID_MASK ((0x1 << BXE_SWCID_SHIFT) - 1) 2143 2144 #define SW_CID(x) (le32toh(x) & BXE_SWCID_MASK) 2145 #define CQE_CMD(x) (le32toh(x) >> COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT) 2146 2147 #define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE) 2148 #define CQE_TYPE_START(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_START_AGG) 2149 #define CQE_TYPE_STOP(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_STOP_AGG) 2150 #define CQE_TYPE_SLOW(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_RAMROD) 2151 #define CQE_TYPE_FAST(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_FASTPATH) 2152 2153 /* must be used on a CID before placing it on a HW ring */ 2154 #define HW_CID(sc, x) \ 2155 ((SC_PORT(sc) << 23) | (SC_VN(sc) << BXE_SWCID_SHIFT) | (x)) 2156 2157 #define SPEED_10 10 2158 #define SPEED_100 100 2159 #define SPEED_1000 1000 2160 #define SPEED_2500 2500 2161 #define SPEED_10000 10000 2162 2163 #define PCI_PM_D0 1 2164 #define PCI_PM_D3hot 2 2165 2166 int bxe_test_bit(int nr, volatile unsigned long * addr); 2167 void bxe_set_bit(unsigned int nr, volatile unsigned long * addr); 2168 void bxe_clear_bit(int nr, volatile unsigned long * addr); 2169 int bxe_test_and_set_bit(int nr, volatile unsigned long * addr); 2170 int bxe_test_and_clear_bit(int nr, volatile unsigned long * addr); 2171 int bxe_cmpxchg(volatile int *addr, int old, int new); 2172 2173 void bxe_reg_wr_ind(struct bxe_softc *sc, uint32_t addr, 2174 uint32_t val); 2175 uint32_t bxe_reg_rd_ind(struct bxe_softc *sc, uint32_t addr); 2176 2177 2178 int bxe_dma_alloc(struct bxe_softc *sc, bus_size_t size, 2179 struct bxe_dma *dma, const char *msg); 2180 void bxe_dma_free(struct bxe_softc *sc, struct bxe_dma *dma); 2181 2182 uint32_t bxe_dmae_opcode_add_comp(uint32_t opcode, uint8_t comp_type); 2183 uint32_t bxe_dmae_opcode_clr_src_reset(uint32_t opcode); 2184 uint32_t bxe_dmae_opcode(struct bxe_softc *sc, uint8_t src_type, 2185 uint8_t dst_type, uint8_t with_comp, 2186 uint8_t comp_type); 2187 void bxe_post_dmae(struct bxe_softc *sc, struct dmae_command *dmae, int idx); 2188 void bxe_read_dmae(struct bxe_softc *sc, uint32_t src_addr, uint32_t len32); 2189 void bxe_write_dmae(struct bxe_softc *sc, bus_addr_t dma_addr, 2190 uint32_t dst_addr, uint32_t len32); 2191 void bxe_write_dmae_phys_len(struct bxe_softc *sc, bus_addr_t phys_addr, 2192 uint32_t addr, uint32_t len); 2193 2194 void bxe_set_ctx_validation(struct bxe_softc *sc, struct eth_context *cxt, 2195 uint32_t cid); 2196 void bxe_update_coalesce_sb_index(struct bxe_softc *sc, uint8_t fw_sb_id, 2197 uint8_t sb_index, uint8_t disable, 2198 uint16_t usec); 2199 2200 int bxe_sp_post(struct bxe_softc *sc, int command, int cid, 2201 uint32_t data_hi, uint32_t data_lo, int cmd_type); 2202 2203 void bxe_igu_ack_sb(struct bxe_softc *sc, uint8_t igu_sb_id, 2204 uint8_t segment, uint16_t index, uint8_t op, 2205 uint8_t update); 2206 2207 void ecore_init_e1_firmware(struct bxe_softc *sc); 2208 void ecore_init_e1h_firmware(struct bxe_softc *sc); 2209 void ecore_init_e2_firmware(struct bxe_softc *sc); 2210 2211 void ecore_storm_memset_struct(struct bxe_softc *sc, uint32_t addr, 2212 size_t size, uint32_t *data); 2213 2214 /*********************/ 2215 /* LOGGING AND DEBUG */ 2216 /*********************/ 2217 2218 /* debug logging codepaths */ 2219 #define DBG_LOAD 0x00000001 /* load and unload */ 2220 #define DBG_INTR 0x00000002 /* interrupt handling */ 2221 #define DBG_SP 0x00000004 /* slowpath handling */ 2222 #define DBG_STATS 0x00000008 /* stats updates */ 2223 #define DBG_TX 0x00000010 /* packet transmit */ 2224 #define DBG_RX 0x00000020 /* packet receive */ 2225 #define DBG_PHY 0x00000040 /* phy/link handling */ 2226 #define DBG_IOCTL 0x00000080 /* ioctl handling */ 2227 #define DBG_MBUF 0x00000100 /* dumping mbuf info */ 2228 #define DBG_REGS 0x00000200 /* register access */ 2229 #define DBG_LRO 0x00000400 /* lro processing */ 2230 #define DBG_ASSERT 0x80000000 /* debug assert */ 2231 #define DBG_ALL 0xFFFFFFFF /* flying monkeys */ 2232 2233 #define DBASSERT(sc, exp, msg) \ 2234 do { \ 2235 if (__predict_false(sc->debug & DBG_ASSERT)) { \ 2236 if (__predict_false(!(exp))) { \ 2237 panic msg; \ 2238 } \ 2239 } \ 2240 } while (0) 2241 2242 /* log a debug message */ 2243 #define BLOGD(sc, codepath, format, args...) \ 2244 do { \ 2245 if (__predict_false(sc->debug & (codepath))) { \ 2246 device_printf((sc)->dev, \ 2247 "%s(%s:%d) " format, \ 2248 __FUNCTION__, \ 2249 __FILE__, \ 2250 __LINE__, \ 2251 ## args); \ 2252 } \ 2253 } while(0) 2254 2255 /* log a info message */ 2256 #define BLOGI(sc, format, args...) \ 2257 do { \ 2258 if (__predict_false(sc->debug)) { \ 2259 device_printf((sc)->dev, \ 2260 "%s(%s:%d) " format, \ 2261 __FUNCTION__, \ 2262 __FILE__, \ 2263 __LINE__, \ 2264 ## args); \ 2265 } else { \ 2266 device_printf((sc)->dev, \ 2267 format, \ 2268 ## args); \ 2269 } \ 2270 } while(0) 2271 2272 /* log a warning message */ 2273 #define BLOGW(sc, format, args...) \ 2274 do { \ 2275 if (__predict_false(sc->debug)) { \ 2276 device_printf((sc)->dev, \ 2277 "%s(%s:%d) WARNING: " format, \ 2278 __FUNCTION__, \ 2279 __FILE__, \ 2280 __LINE__, \ 2281 ## args); \ 2282 } else { \ 2283 device_printf((sc)->dev, \ 2284 "WARNING: " format, \ 2285 ## args); \ 2286 } \ 2287 } while(0) 2288 2289 /* log a error message */ 2290 #define BLOGE(sc, format, args...) \ 2291 do { \ 2292 if (__predict_false(sc->debug)) { \ 2293 device_printf((sc)->dev, \ 2294 "%s(%s:%d) ERROR: " format, \ 2295 __FUNCTION__, \ 2296 __FILE__, \ 2297 __LINE__, \ 2298 ## args); \ 2299 } else { \ 2300 device_printf((sc)->dev, \ 2301 "ERROR: " format, \ 2302 ## args); \ 2303 } \ 2304 sc->trigger_grcdump |= 0x1; \ 2305 } while(0) 2306 2307 #ifdef ECORE_STOP_ON_ERROR 2308 2309 #define bxe_panic(sc, msg) \ 2310 do { \ 2311 panic msg; \ 2312 } while (0) 2313 2314 #else 2315 2316 #define bxe_panic(sc, msg) \ 2317 device_printf((sc)->dev, "%s (%s,%d)\n", __FUNCTION__, __FILE__, __LINE__); 2318 2319 #endif 2320 2321 #define CATC_TRIGGER(sc, data) REG_WR((sc), 0x2000, (data)); 2322 #define CATC_TRIGGER_START(sc) CATC_TRIGGER((sc), 0xcafecafe) 2323 2324 void bxe_dump_mem(struct bxe_softc *sc, char *tag, 2325 uint8_t *mem, uint32_t len); 2326 void bxe_dump_mbuf_data(struct bxe_softc *sc, char *pTag, 2327 struct mbuf *m, uint8_t contents); 2328 2329 /***********/ 2330 /* INLINES */ 2331 /***********/ 2332 2333 static inline uint32_t 2334 reg_poll(struct bxe_softc *sc, 2335 uint32_t reg, 2336 uint32_t expected, 2337 int ms, 2338 int wait) 2339 { 2340 uint32_t val; 2341 2342 do { 2343 val = REG_RD(sc, reg); 2344 if (val == expected) { 2345 break; 2346 } 2347 ms -= wait; 2348 DELAY(wait * 1000); 2349 } while (ms > 0); 2350 2351 return (val); 2352 } 2353 2354 static inline void 2355 bxe_update_fp_sb_idx(struct bxe_fastpath *fp) 2356 { 2357 mb(); /* status block is written to by the chip */ 2358 fp->fp_hc_idx = fp->sb_running_index[SM_RX_ID]; 2359 } 2360 2361 static inline void 2362 bxe_igu_ack_sb_gen(struct bxe_softc *sc, 2363 uint8_t igu_sb_id, 2364 uint8_t segment, 2365 uint16_t index, 2366 uint8_t op, 2367 uint8_t update, 2368 uint32_t igu_addr) 2369 { 2370 struct igu_regular cmd_data = {0}; 2371 2372 cmd_data.sb_id_and_flags = 2373 ((index << IGU_REGULAR_SB_INDEX_SHIFT) | 2374 (segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) | 2375 (update << IGU_REGULAR_BUPDATE_SHIFT) | 2376 (op << IGU_REGULAR_ENABLE_INT_SHIFT)); 2377 2378 BLOGD(sc, DBG_INTR, "write 0x%08x to IGU addr 0x%x\n", 2379 cmd_data.sb_id_and_flags, igu_addr); 2380 REG_WR(sc, igu_addr, cmd_data.sb_id_and_flags); 2381 2382 /* Make sure that ACK is written */ 2383 bus_space_barrier(sc->bar[0].tag, sc->bar[0].handle, 0, 0, 2384 BUS_SPACE_BARRIER_WRITE); 2385 mb(); 2386 } 2387 2388 static inline void 2389 bxe_hc_ack_sb(struct bxe_softc *sc, 2390 uint8_t sb_id, 2391 uint8_t storm, 2392 uint16_t index, 2393 uint8_t op, 2394 uint8_t update) 2395 { 2396 uint32_t hc_addr = (HC_REG_COMMAND_REG + SC_PORT(sc)*32 + 2397 COMMAND_REG_INT_ACK); 2398 struct igu_ack_register igu_ack; 2399 2400 igu_ack.status_block_index = index; 2401 igu_ack.sb_id_and_flags = 2402 ((sb_id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) | 2403 (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) | 2404 (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) | 2405 (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT)); 2406 2407 REG_WR(sc, hc_addr, (*(uint32_t *)&igu_ack)); 2408 2409 /* Make sure that ACK is written */ 2410 bus_space_barrier(sc->bar[0].tag, sc->bar[0].handle, 0, 0, 2411 BUS_SPACE_BARRIER_WRITE); 2412 mb(); 2413 } 2414 2415 static inline void 2416 bxe_ack_sb(struct bxe_softc *sc, 2417 uint8_t igu_sb_id, 2418 uint8_t storm, 2419 uint16_t index, 2420 uint8_t op, 2421 uint8_t update) 2422 { 2423 if (sc->devinfo.int_block == INT_BLOCK_HC) 2424 bxe_hc_ack_sb(sc, igu_sb_id, storm, index, op, update); 2425 else { 2426 uint8_t segment; 2427 if (CHIP_INT_MODE_IS_BC(sc)) { 2428 segment = storm; 2429 } else if (igu_sb_id != sc->igu_dsb_id) { 2430 segment = IGU_SEG_ACCESS_DEF; 2431 } else if (storm == ATTENTION_ID) { 2432 segment = IGU_SEG_ACCESS_ATTN; 2433 } else { 2434 segment = IGU_SEG_ACCESS_DEF; 2435 } 2436 bxe_igu_ack_sb(sc, igu_sb_id, segment, index, op, update); 2437 } 2438 } 2439 2440 static inline uint16_t 2441 bxe_hc_ack_int(struct bxe_softc *sc) 2442 { 2443 uint32_t hc_addr = (HC_REG_COMMAND_REG + SC_PORT(sc)*32 + 2444 COMMAND_REG_SIMD_MASK); 2445 uint32_t result = REG_RD(sc, hc_addr); 2446 2447 mb(); 2448 return (result); 2449 } 2450 2451 static inline uint16_t 2452 bxe_igu_ack_int(struct bxe_softc *sc) 2453 { 2454 uint32_t igu_addr = (BAR_IGU_INTMEM + IGU_REG_SISR_MDPC_WMASK_LSB_UPPER*8); 2455 uint32_t result = REG_RD(sc, igu_addr); 2456 2457 BLOGD(sc, DBG_INTR, "read 0x%08x from IGU addr 0x%x\n", 2458 result, igu_addr); 2459 2460 mb(); 2461 return (result); 2462 } 2463 2464 static inline uint16_t 2465 bxe_ack_int(struct bxe_softc *sc) 2466 { 2467 mb(); 2468 if (sc->devinfo.int_block == INT_BLOCK_HC) { 2469 return (bxe_hc_ack_int(sc)); 2470 } else { 2471 return (bxe_igu_ack_int(sc)); 2472 } 2473 } 2474 2475 static inline int 2476 func_by_vn(struct bxe_softc *sc, 2477 int vn) 2478 { 2479 return (2 * vn + SC_PORT(sc)); 2480 } 2481 2482 /* 2483 * Statistics ID are global per chip/path, while Client IDs for E1x 2484 * are per port. 2485 */ 2486 static inline uint8_t 2487 bxe_stats_id(struct bxe_fastpath *fp) 2488 { 2489 struct bxe_softc *sc = fp->sc; 2490 2491 if (!CHIP_IS_E1x(sc)) { 2492 #if 0 2493 /* there are special statistics counters for FCoE 136..140 */ 2494 if (IS_FCOE_FP(fp)) { 2495 return (sc->cnic_base_cl_id + (sc->pf_num >> 1)); 2496 } 2497 #endif 2498 return (fp->cl_id); 2499 } 2500 2501 return (fp->cl_id + SC_PORT(sc) * FP_SB_MAX_E1x); 2502 } 2503 2504 #endif /* __BXE_H__ */ 2505 2506