1 /*- 2 * Copyright (c) 2007-2014 QLogic Corporation. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' 15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS 18 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 19 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 20 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 21 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 22 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 23 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 24 * THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #define BXE_DRIVER_VERSION "1.78.78" 31 32 #include "bxe.h" 33 #include "ecore_sp.h" 34 #include "ecore_init.h" 35 #include "ecore_init_ops.h" 36 37 #include "57710_int_offsets.h" 38 #include "57711_int_offsets.h" 39 #include "57712_int_offsets.h" 40 41 /* 42 * CTLTYPE_U64 and sysctl_handle_64 were added in r217616. Define these 43 * explicitly here for older kernels that don't include this changeset. 44 */ 45 #ifndef CTLTYPE_U64 46 #define CTLTYPE_U64 CTLTYPE_QUAD 47 #define sysctl_handle_64 sysctl_handle_quad 48 #endif 49 50 /* 51 * CSUM_TCP_IPV6 and CSUM_UDP_IPV6 were added in r236170. Define these 52 * here as zero(0) for older kernels that don't include this changeset 53 * thereby masking the functionality. 54 */ 55 #ifndef CSUM_TCP_IPV6 56 #define CSUM_TCP_IPV6 0 57 #define CSUM_UDP_IPV6 0 58 #endif 59 60 /* 61 * pci_find_cap was added in r219865. Re-define this at pci_find_extcap 62 * for older kernels that don't include this changeset. 63 */ 64 #if __FreeBSD_version < 900035 65 #define pci_find_cap pci_find_extcap 66 #endif 67 68 #define BXE_DEF_SB_ATT_IDX 0x0001 69 #define BXE_DEF_SB_IDX 0x0002 70 71 /* 72 * FLR Support - bxe_pf_flr_clnup() is called during nic_load in the per 73 * function HW initialization. 74 */ 75 #define FLR_WAIT_USEC 10000 /* 10 msecs */ 76 #define FLR_WAIT_INTERVAL 50 /* usecs */ 77 #define FLR_POLL_CNT (FLR_WAIT_USEC / FLR_WAIT_INTERVAL) /* 200 */ 78 79 struct pbf_pN_buf_regs { 80 int pN; 81 uint32_t init_crd; 82 uint32_t crd; 83 uint32_t crd_freed; 84 }; 85 86 struct pbf_pN_cmd_regs { 87 int pN; 88 uint32_t lines_occup; 89 uint32_t lines_freed; 90 }; 91 92 /* 93 * PCI Device ID Table used by bxe_probe(). 94 */ 95 #define BXE_DEVDESC_MAX 64 96 static struct bxe_device_type bxe_devs[] = { 97 { 98 BRCM_VENDORID, 99 CHIP_NUM_57710, 100 PCI_ANY_ID, PCI_ANY_ID, 101 "QLogic NetXtreme II BCM57710 10GbE" 102 }, 103 { 104 BRCM_VENDORID, 105 CHIP_NUM_57711, 106 PCI_ANY_ID, PCI_ANY_ID, 107 "QLogic NetXtreme II BCM57711 10GbE" 108 }, 109 { 110 BRCM_VENDORID, 111 CHIP_NUM_57711E, 112 PCI_ANY_ID, PCI_ANY_ID, 113 "QLogic NetXtreme II BCM57711E 10GbE" 114 }, 115 { 116 BRCM_VENDORID, 117 CHIP_NUM_57712, 118 PCI_ANY_ID, PCI_ANY_ID, 119 "QLogic NetXtreme II BCM57712 10GbE" 120 }, 121 { 122 BRCM_VENDORID, 123 CHIP_NUM_57712_MF, 124 PCI_ANY_ID, PCI_ANY_ID, 125 "QLogic NetXtreme II BCM57712 MF 10GbE" 126 }, 127 #if 0 128 { 129 BRCM_VENDORID, 130 CHIP_NUM_57712_VF, 131 PCI_ANY_ID, PCI_ANY_ID, 132 "QLogic NetXtreme II BCM57712 VF 10GbE" 133 }, 134 #endif 135 { 136 BRCM_VENDORID, 137 CHIP_NUM_57800, 138 PCI_ANY_ID, PCI_ANY_ID, 139 "QLogic NetXtreme II BCM57800 10GbE" 140 }, 141 { 142 BRCM_VENDORID, 143 CHIP_NUM_57800_MF, 144 PCI_ANY_ID, PCI_ANY_ID, 145 "QLogic NetXtreme II BCM57800 MF 10GbE" 146 }, 147 #if 0 148 { 149 BRCM_VENDORID, 150 CHIP_NUM_57800_VF, 151 PCI_ANY_ID, PCI_ANY_ID, 152 "QLogic NetXtreme II BCM57800 VF 10GbE" 153 }, 154 #endif 155 { 156 BRCM_VENDORID, 157 CHIP_NUM_57810, 158 PCI_ANY_ID, PCI_ANY_ID, 159 "QLogic NetXtreme II BCM57810 10GbE" 160 }, 161 { 162 BRCM_VENDORID, 163 CHIP_NUM_57810_MF, 164 PCI_ANY_ID, PCI_ANY_ID, 165 "QLogic NetXtreme II BCM57810 MF 10GbE" 166 }, 167 #if 0 168 { 169 BRCM_VENDORID, 170 CHIP_NUM_57810_VF, 171 PCI_ANY_ID, PCI_ANY_ID, 172 "QLogic NetXtreme II BCM57810 VF 10GbE" 173 }, 174 #endif 175 { 176 BRCM_VENDORID, 177 CHIP_NUM_57811, 178 PCI_ANY_ID, PCI_ANY_ID, 179 "QLogic NetXtreme II BCM57811 10GbE" 180 }, 181 { 182 BRCM_VENDORID, 183 CHIP_NUM_57811_MF, 184 PCI_ANY_ID, PCI_ANY_ID, 185 "QLogic NetXtreme II BCM57811 MF 10GbE" 186 }, 187 #if 0 188 { 189 BRCM_VENDORID, 190 CHIP_NUM_57811_VF, 191 PCI_ANY_ID, PCI_ANY_ID, 192 "QLogic NetXtreme II BCM57811 VF 10GbE" 193 }, 194 #endif 195 { 196 BRCM_VENDORID, 197 CHIP_NUM_57840_4_10, 198 PCI_ANY_ID, PCI_ANY_ID, 199 "QLogic NetXtreme II BCM57840 4x10GbE" 200 }, 201 #if 0 202 { 203 BRCM_VENDORID, 204 CHIP_NUM_57840_2_20, 205 PCI_ANY_ID, PCI_ANY_ID, 206 "QLogic NetXtreme II BCM57840 2x20GbE" 207 }, 208 #endif 209 { 210 BRCM_VENDORID, 211 CHIP_NUM_57840_MF, 212 PCI_ANY_ID, PCI_ANY_ID, 213 "QLogic NetXtreme II BCM57840 MF 10GbE" 214 }, 215 #if 0 216 { 217 BRCM_VENDORID, 218 CHIP_NUM_57840_VF, 219 PCI_ANY_ID, PCI_ANY_ID, 220 "QLogic NetXtreme II BCM57840 VF 10GbE" 221 }, 222 #endif 223 { 224 0, 0, 0, 0, NULL 225 } 226 }; 227 228 MALLOC_DECLARE(M_BXE_ILT); 229 MALLOC_DEFINE(M_BXE_ILT, "bxe_ilt", "bxe ILT pointer"); 230 231 /* 232 * FreeBSD device entry points. 233 */ 234 static int bxe_probe(device_t); 235 static int bxe_attach(device_t); 236 static int bxe_detach(device_t); 237 static int bxe_shutdown(device_t); 238 239 /* 240 * FreeBSD KLD module/device interface event handler method. 241 */ 242 static device_method_t bxe_methods[] = { 243 /* Device interface (device_if.h) */ 244 DEVMETHOD(device_probe, bxe_probe), 245 DEVMETHOD(device_attach, bxe_attach), 246 DEVMETHOD(device_detach, bxe_detach), 247 DEVMETHOD(device_shutdown, bxe_shutdown), 248 #if 0 249 DEVMETHOD(device_suspend, bxe_suspend), 250 DEVMETHOD(device_resume, bxe_resume), 251 #endif 252 /* Bus interface (bus_if.h) */ 253 DEVMETHOD(bus_print_child, bus_generic_print_child), 254 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 255 KOBJMETHOD_END 256 }; 257 258 /* 259 * FreeBSD KLD Module data declaration 260 */ 261 static driver_t bxe_driver = { 262 "bxe", /* module name */ 263 bxe_methods, /* event handler */ 264 sizeof(struct bxe_softc) /* extra data */ 265 }; 266 267 /* 268 * FreeBSD dev class is needed to manage dev instances and 269 * to associate with a bus type 270 */ 271 static devclass_t bxe_devclass; 272 273 MODULE_DEPEND(bxe, pci, 1, 1, 1); 274 MODULE_DEPEND(bxe, ether, 1, 1, 1); 275 DRIVER_MODULE(bxe, pci, bxe_driver, bxe_devclass, 0, 0); 276 277 /* resources needed for unloading a previously loaded device */ 278 279 #define BXE_PREV_WAIT_NEEDED 1 280 struct mtx bxe_prev_mtx; 281 MTX_SYSINIT(bxe_prev_mtx, &bxe_prev_mtx, "bxe_prev_lock", MTX_DEF); 282 struct bxe_prev_list_node { 283 LIST_ENTRY(bxe_prev_list_node) node; 284 uint8_t bus; 285 uint8_t slot; 286 uint8_t path; 287 uint8_t aer; /* XXX automatic error recovery */ 288 uint8_t undi; 289 }; 290 static LIST_HEAD(, bxe_prev_list_node) bxe_prev_list = LIST_HEAD_INITIALIZER(bxe_prev_list); 291 292 static int load_count[2][3] = { {0} }; /* per-path: 0-common, 1-port0, 2-port1 */ 293 294 /* Tunable device values... */ 295 296 SYSCTL_NODE(_hw, OID_AUTO, bxe, CTLFLAG_RD, 0, "bxe driver parameters"); 297 298 /* Debug */ 299 unsigned long bxe_debug = 0; 300 TUNABLE_ULONG("hw.bxe.debug", &bxe_debug); 301 SYSCTL_ULONG(_hw_bxe, OID_AUTO, debug, (CTLFLAG_RDTUN), 302 &bxe_debug, 0, "Debug logging mode"); 303 304 /* Interrupt Mode: 0 (IRQ), 1 (MSI/IRQ), and 2 (MSI-X/MSI/IRQ) */ 305 static int bxe_interrupt_mode = INTR_MODE_MSIX; 306 TUNABLE_INT("hw.bxe.interrupt_mode", &bxe_interrupt_mode); 307 SYSCTL_INT(_hw_bxe, OID_AUTO, interrupt_mode, CTLFLAG_RDTUN, 308 &bxe_interrupt_mode, 0, "Interrupt (MSI-X/MSI/INTx) mode"); 309 310 /* Number of Queues: 0 (Auto) or 1 to 16 (fixed queue number) */ 311 static int bxe_queue_count = 4; 312 TUNABLE_INT("hw.bxe.queue_count", &bxe_queue_count); 313 SYSCTL_INT(_hw_bxe, OID_AUTO, queue_count, CTLFLAG_RDTUN, 314 &bxe_queue_count, 0, "Multi-Queue queue count"); 315 316 /* max number of buffers per queue (default RX_BD_USABLE) */ 317 static int bxe_max_rx_bufs = 0; 318 TUNABLE_INT("hw.bxe.max_rx_bufs", &bxe_max_rx_bufs); 319 SYSCTL_INT(_hw_bxe, OID_AUTO, max_rx_bufs, CTLFLAG_RDTUN, 320 &bxe_max_rx_bufs, 0, "Maximum Number of Rx Buffers Per Queue"); 321 322 /* Host interrupt coalescing RX tick timer (usecs) */ 323 static int bxe_hc_rx_ticks = 25; 324 TUNABLE_INT("hw.bxe.hc_rx_ticks", &bxe_hc_rx_ticks); 325 SYSCTL_INT(_hw_bxe, OID_AUTO, hc_rx_ticks, CTLFLAG_RDTUN, 326 &bxe_hc_rx_ticks, 0, "Host Coalescing Rx ticks"); 327 328 /* Host interrupt coalescing TX tick timer (usecs) */ 329 static int bxe_hc_tx_ticks = 50; 330 TUNABLE_INT("hw.bxe.hc_tx_ticks", &bxe_hc_tx_ticks); 331 SYSCTL_INT(_hw_bxe, OID_AUTO, hc_tx_ticks, CTLFLAG_RDTUN, 332 &bxe_hc_tx_ticks, 0, "Host Coalescing Tx ticks"); 333 334 /* Maximum number of Rx packets to process at a time */ 335 static int bxe_rx_budget = 0xffffffff; 336 TUNABLE_INT("hw.bxe.rx_budget", &bxe_rx_budget); 337 SYSCTL_INT(_hw_bxe, OID_AUTO, rx_budget, CTLFLAG_TUN, 338 &bxe_rx_budget, 0, "Rx processing budget"); 339 340 /* Maximum LRO aggregation size */ 341 static int bxe_max_aggregation_size = 0; 342 TUNABLE_INT("hw.bxe.max_aggregation_size", &bxe_max_aggregation_size); 343 SYSCTL_INT(_hw_bxe, OID_AUTO, max_aggregation_size, CTLFLAG_TUN, 344 &bxe_max_aggregation_size, 0, "max aggregation size"); 345 346 /* PCI MRRS: -1 (Auto), 0 (128B), 1 (256B), 2 (512B), 3 (1KB) */ 347 static int bxe_mrrs = -1; 348 TUNABLE_INT("hw.bxe.mrrs", &bxe_mrrs); 349 SYSCTL_INT(_hw_bxe, OID_AUTO, mrrs, CTLFLAG_RDTUN, 350 &bxe_mrrs, 0, "PCIe maximum read request size"); 351 352 /* AutoGrEEEn: 0 (hardware default), 1 (force on), 2 (force off) */ 353 static int bxe_autogreeen = 0; 354 TUNABLE_INT("hw.bxe.autogreeen", &bxe_autogreeen); 355 SYSCTL_INT(_hw_bxe, OID_AUTO, autogreeen, CTLFLAG_RDTUN, 356 &bxe_autogreeen, 0, "AutoGrEEEn support"); 357 358 /* 4-tuple RSS support for UDP: 0 (disabled), 1 (enabled) */ 359 static int bxe_udp_rss = 0; 360 TUNABLE_INT("hw.bxe.udp_rss", &bxe_udp_rss); 361 SYSCTL_INT(_hw_bxe, OID_AUTO, udp_rss, CTLFLAG_RDTUN, 362 &bxe_udp_rss, 0, "UDP RSS support"); 363 364 365 #define STAT_NAME_LEN 32 /* no stat names below can be longer than this */ 366 367 #define STATS_OFFSET32(stat_name) \ 368 (offsetof(struct bxe_eth_stats, stat_name) / 4) 369 370 #define Q_STATS_OFFSET32(stat_name) \ 371 (offsetof(struct bxe_eth_q_stats, stat_name) / 4) 372 373 static const struct { 374 uint32_t offset; 375 uint32_t size; 376 uint32_t flags; 377 #define STATS_FLAGS_PORT 1 378 #define STATS_FLAGS_FUNC 2 /* MF only cares about function stats */ 379 #define STATS_FLAGS_BOTH (STATS_FLAGS_FUNC | STATS_FLAGS_PORT) 380 char string[STAT_NAME_LEN]; 381 } bxe_eth_stats_arr[] = { 382 { STATS_OFFSET32(total_bytes_received_hi), 383 8, STATS_FLAGS_BOTH, "rx_bytes" }, 384 { STATS_OFFSET32(error_bytes_received_hi), 385 8, STATS_FLAGS_BOTH, "rx_error_bytes" }, 386 { STATS_OFFSET32(total_unicast_packets_received_hi), 387 8, STATS_FLAGS_BOTH, "rx_ucast_packets" }, 388 { STATS_OFFSET32(total_multicast_packets_received_hi), 389 8, STATS_FLAGS_BOTH, "rx_mcast_packets" }, 390 { STATS_OFFSET32(total_broadcast_packets_received_hi), 391 8, STATS_FLAGS_BOTH, "rx_bcast_packets" }, 392 { STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi), 393 8, STATS_FLAGS_PORT, "rx_crc_errors" }, 394 { STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi), 395 8, STATS_FLAGS_PORT, "rx_align_errors" }, 396 { STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi), 397 8, STATS_FLAGS_PORT, "rx_undersize_packets" }, 398 { STATS_OFFSET32(etherstatsoverrsizepkts_hi), 399 8, STATS_FLAGS_PORT, "rx_oversize_packets" }, 400 { STATS_OFFSET32(rx_stat_etherstatsfragments_hi), 401 8, STATS_FLAGS_PORT, "rx_fragments" }, 402 { STATS_OFFSET32(rx_stat_etherstatsjabbers_hi), 403 8, STATS_FLAGS_PORT, "rx_jabbers" }, 404 { STATS_OFFSET32(no_buff_discard_hi), 405 8, STATS_FLAGS_BOTH, "rx_discards" }, 406 { STATS_OFFSET32(mac_filter_discard), 407 4, STATS_FLAGS_PORT, "rx_filtered_packets" }, 408 { STATS_OFFSET32(mf_tag_discard), 409 4, STATS_FLAGS_PORT, "rx_mf_tag_discard" }, 410 { STATS_OFFSET32(pfc_frames_received_hi), 411 8, STATS_FLAGS_PORT, "pfc_frames_received" }, 412 { STATS_OFFSET32(pfc_frames_sent_hi), 413 8, STATS_FLAGS_PORT, "pfc_frames_sent" }, 414 { STATS_OFFSET32(brb_drop_hi), 415 8, STATS_FLAGS_PORT, "rx_brb_discard" }, 416 { STATS_OFFSET32(brb_truncate_hi), 417 8, STATS_FLAGS_PORT, "rx_brb_truncate" }, 418 { STATS_OFFSET32(pause_frames_received_hi), 419 8, STATS_FLAGS_PORT, "rx_pause_frames" }, 420 { STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi), 421 8, STATS_FLAGS_PORT, "rx_mac_ctrl_frames" }, 422 { STATS_OFFSET32(nig_timer_max), 423 4, STATS_FLAGS_PORT, "rx_constant_pause_events" }, 424 { STATS_OFFSET32(total_bytes_transmitted_hi), 425 8, STATS_FLAGS_BOTH, "tx_bytes" }, 426 { STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi), 427 8, STATS_FLAGS_PORT, "tx_error_bytes" }, 428 { STATS_OFFSET32(total_unicast_packets_transmitted_hi), 429 8, STATS_FLAGS_BOTH, "tx_ucast_packets" }, 430 { STATS_OFFSET32(total_multicast_packets_transmitted_hi), 431 8, STATS_FLAGS_BOTH, "tx_mcast_packets" }, 432 { STATS_OFFSET32(total_broadcast_packets_transmitted_hi), 433 8, STATS_FLAGS_BOTH, "tx_bcast_packets" }, 434 { STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi), 435 8, STATS_FLAGS_PORT, "tx_mac_errors" }, 436 { STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi), 437 8, STATS_FLAGS_PORT, "tx_carrier_errors" }, 438 { STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi), 439 8, STATS_FLAGS_PORT, "tx_single_collisions" }, 440 { STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi), 441 8, STATS_FLAGS_PORT, "tx_multi_collisions" }, 442 { STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi), 443 8, STATS_FLAGS_PORT, "tx_deferred" }, 444 { STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi), 445 8, STATS_FLAGS_PORT, "tx_excess_collisions" }, 446 { STATS_OFFSET32(tx_stat_dot3statslatecollisions_hi), 447 8, STATS_FLAGS_PORT, "tx_late_collisions" }, 448 { STATS_OFFSET32(tx_stat_etherstatscollisions_hi), 449 8, STATS_FLAGS_PORT, "tx_total_collisions" }, 450 { STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi), 451 8, STATS_FLAGS_PORT, "tx_64_byte_packets" }, 452 { STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi), 453 8, STATS_FLAGS_PORT, "tx_65_to_127_byte_packets" }, 454 { STATS_OFFSET32(tx_stat_etherstatspkts128octetsto255octets_hi), 455 8, STATS_FLAGS_PORT, "tx_128_to_255_byte_packets" }, 456 { STATS_OFFSET32(tx_stat_etherstatspkts256octetsto511octets_hi), 457 8, STATS_FLAGS_PORT, "tx_256_to_511_byte_packets" }, 458 { STATS_OFFSET32(tx_stat_etherstatspkts512octetsto1023octets_hi), 459 8, STATS_FLAGS_PORT, "tx_512_to_1023_byte_packets" }, 460 { STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi), 461 8, STATS_FLAGS_PORT, "tx_1024_to_1522_byte_packets" }, 462 { STATS_OFFSET32(etherstatspktsover1522octets_hi), 463 8, STATS_FLAGS_PORT, "tx_1523_to_9022_byte_packets" }, 464 { STATS_OFFSET32(pause_frames_sent_hi), 465 8, STATS_FLAGS_PORT, "tx_pause_frames" }, 466 { STATS_OFFSET32(total_tpa_aggregations_hi), 467 8, STATS_FLAGS_FUNC, "tpa_aggregations" }, 468 { STATS_OFFSET32(total_tpa_aggregated_frames_hi), 469 8, STATS_FLAGS_FUNC, "tpa_aggregated_frames"}, 470 { STATS_OFFSET32(total_tpa_bytes_hi), 471 8, STATS_FLAGS_FUNC, "tpa_bytes"}, 472 #if 0 473 { STATS_OFFSET32(recoverable_error), 474 4, STATS_FLAGS_FUNC, "recoverable_errors" }, 475 { STATS_OFFSET32(unrecoverable_error), 476 4, STATS_FLAGS_FUNC, "unrecoverable_errors" }, 477 #endif 478 { STATS_OFFSET32(eee_tx_lpi), 479 4, STATS_FLAGS_PORT, "eee_tx_lpi"}, 480 { STATS_OFFSET32(rx_calls), 481 4, STATS_FLAGS_FUNC, "rx_calls"}, 482 { STATS_OFFSET32(rx_pkts), 483 4, STATS_FLAGS_FUNC, "rx_pkts"}, 484 { STATS_OFFSET32(rx_tpa_pkts), 485 4, STATS_FLAGS_FUNC, "rx_tpa_pkts"}, 486 { STATS_OFFSET32(rx_soft_errors), 487 4, STATS_FLAGS_FUNC, "rx_soft_errors"}, 488 { STATS_OFFSET32(rx_hw_csum_errors), 489 4, STATS_FLAGS_FUNC, "rx_hw_csum_errors"}, 490 { STATS_OFFSET32(rx_ofld_frames_csum_ip), 491 4, STATS_FLAGS_FUNC, "rx_ofld_frames_csum_ip"}, 492 { STATS_OFFSET32(rx_ofld_frames_csum_tcp_udp), 493 4, STATS_FLAGS_FUNC, "rx_ofld_frames_csum_tcp_udp"}, 494 { STATS_OFFSET32(rx_budget_reached), 495 4, STATS_FLAGS_FUNC, "rx_budget_reached"}, 496 { STATS_OFFSET32(tx_pkts), 497 4, STATS_FLAGS_FUNC, "tx_pkts"}, 498 { STATS_OFFSET32(tx_soft_errors), 499 4, STATS_FLAGS_FUNC, "tx_soft_errors"}, 500 { STATS_OFFSET32(tx_ofld_frames_csum_ip), 501 4, STATS_FLAGS_FUNC, "tx_ofld_frames_csum_ip"}, 502 { STATS_OFFSET32(tx_ofld_frames_csum_tcp), 503 4, STATS_FLAGS_FUNC, "tx_ofld_frames_csum_tcp"}, 504 { STATS_OFFSET32(tx_ofld_frames_csum_udp), 505 4, STATS_FLAGS_FUNC, "tx_ofld_frames_csum_udp"}, 506 { STATS_OFFSET32(tx_ofld_frames_lso), 507 4, STATS_FLAGS_FUNC, "tx_ofld_frames_lso"}, 508 { STATS_OFFSET32(tx_ofld_frames_lso_hdr_splits), 509 4, STATS_FLAGS_FUNC, "tx_ofld_frames_lso_hdr_splits"}, 510 { STATS_OFFSET32(tx_encap_failures), 511 4, STATS_FLAGS_FUNC, "tx_encap_failures"}, 512 { STATS_OFFSET32(tx_hw_queue_full), 513 4, STATS_FLAGS_FUNC, "tx_hw_queue_full"}, 514 { STATS_OFFSET32(tx_hw_max_queue_depth), 515 4, STATS_FLAGS_FUNC, "tx_hw_max_queue_depth"}, 516 { STATS_OFFSET32(tx_dma_mapping_failure), 517 4, STATS_FLAGS_FUNC, "tx_dma_mapping_failure"}, 518 { STATS_OFFSET32(tx_max_drbr_queue_depth), 519 4, STATS_FLAGS_FUNC, "tx_max_drbr_queue_depth"}, 520 { STATS_OFFSET32(tx_window_violation_std), 521 4, STATS_FLAGS_FUNC, "tx_window_violation_std"}, 522 { STATS_OFFSET32(tx_window_violation_tso), 523 4, STATS_FLAGS_FUNC, "tx_window_violation_tso"}, 524 #if 0 525 { STATS_OFFSET32(tx_unsupported_tso_request_ipv6), 526 4, STATS_FLAGS_FUNC, "tx_unsupported_tso_request_ipv6"}, 527 { STATS_OFFSET32(tx_unsupported_tso_request_not_tcp), 528 4, STATS_FLAGS_FUNC, "tx_unsupported_tso_request_not_tcp"}, 529 #endif 530 { STATS_OFFSET32(tx_chain_lost_mbuf), 531 4, STATS_FLAGS_FUNC, "tx_chain_lost_mbuf"}, 532 { STATS_OFFSET32(tx_frames_deferred), 533 4, STATS_FLAGS_FUNC, "tx_frames_deferred"}, 534 { STATS_OFFSET32(tx_queue_xoff), 535 4, STATS_FLAGS_FUNC, "tx_queue_xoff"}, 536 { STATS_OFFSET32(mbuf_defrag_attempts), 537 4, STATS_FLAGS_FUNC, "mbuf_defrag_attempts"}, 538 { STATS_OFFSET32(mbuf_defrag_failures), 539 4, STATS_FLAGS_FUNC, "mbuf_defrag_failures"}, 540 { STATS_OFFSET32(mbuf_rx_bd_alloc_failed), 541 4, STATS_FLAGS_FUNC, "mbuf_rx_bd_alloc_failed"}, 542 { STATS_OFFSET32(mbuf_rx_bd_mapping_failed), 543 4, STATS_FLAGS_FUNC, "mbuf_rx_bd_mapping_failed"}, 544 { STATS_OFFSET32(mbuf_rx_tpa_alloc_failed), 545 4, STATS_FLAGS_FUNC, "mbuf_rx_tpa_alloc_failed"}, 546 { STATS_OFFSET32(mbuf_rx_tpa_mapping_failed), 547 4, STATS_FLAGS_FUNC, "mbuf_rx_tpa_mapping_failed"}, 548 { STATS_OFFSET32(mbuf_rx_sge_alloc_failed), 549 4, STATS_FLAGS_FUNC, "mbuf_rx_sge_alloc_failed"}, 550 { STATS_OFFSET32(mbuf_rx_sge_mapping_failed), 551 4, STATS_FLAGS_FUNC, "mbuf_rx_sge_mapping_failed"}, 552 { STATS_OFFSET32(mbuf_alloc_tx), 553 4, STATS_FLAGS_FUNC, "mbuf_alloc_tx"}, 554 { STATS_OFFSET32(mbuf_alloc_rx), 555 4, STATS_FLAGS_FUNC, "mbuf_alloc_rx"}, 556 { STATS_OFFSET32(mbuf_alloc_sge), 557 4, STATS_FLAGS_FUNC, "mbuf_alloc_sge"}, 558 { STATS_OFFSET32(mbuf_alloc_tpa), 559 4, STATS_FLAGS_FUNC, "mbuf_alloc_tpa"} 560 }; 561 562 static const struct { 563 uint32_t offset; 564 uint32_t size; 565 char string[STAT_NAME_LEN]; 566 } bxe_eth_q_stats_arr[] = { 567 { Q_STATS_OFFSET32(total_bytes_received_hi), 568 8, "rx_bytes" }, 569 { Q_STATS_OFFSET32(total_unicast_packets_received_hi), 570 8, "rx_ucast_packets" }, 571 { Q_STATS_OFFSET32(total_multicast_packets_received_hi), 572 8, "rx_mcast_packets" }, 573 { Q_STATS_OFFSET32(total_broadcast_packets_received_hi), 574 8, "rx_bcast_packets" }, 575 { Q_STATS_OFFSET32(no_buff_discard_hi), 576 8, "rx_discards" }, 577 { Q_STATS_OFFSET32(total_bytes_transmitted_hi), 578 8, "tx_bytes" }, 579 { Q_STATS_OFFSET32(total_unicast_packets_transmitted_hi), 580 8, "tx_ucast_packets" }, 581 { Q_STATS_OFFSET32(total_multicast_packets_transmitted_hi), 582 8, "tx_mcast_packets" }, 583 { Q_STATS_OFFSET32(total_broadcast_packets_transmitted_hi), 584 8, "tx_bcast_packets" }, 585 { Q_STATS_OFFSET32(total_tpa_aggregations_hi), 586 8, "tpa_aggregations" }, 587 { Q_STATS_OFFSET32(total_tpa_aggregated_frames_hi), 588 8, "tpa_aggregated_frames"}, 589 { Q_STATS_OFFSET32(total_tpa_bytes_hi), 590 8, "tpa_bytes"}, 591 { Q_STATS_OFFSET32(rx_calls), 592 4, "rx_calls"}, 593 { Q_STATS_OFFSET32(rx_pkts), 594 4, "rx_pkts"}, 595 { Q_STATS_OFFSET32(rx_tpa_pkts), 596 4, "rx_tpa_pkts"}, 597 { Q_STATS_OFFSET32(rx_soft_errors), 598 4, "rx_soft_errors"}, 599 { Q_STATS_OFFSET32(rx_hw_csum_errors), 600 4, "rx_hw_csum_errors"}, 601 { Q_STATS_OFFSET32(rx_ofld_frames_csum_ip), 602 4, "rx_ofld_frames_csum_ip"}, 603 { Q_STATS_OFFSET32(rx_ofld_frames_csum_tcp_udp), 604 4, "rx_ofld_frames_csum_tcp_udp"}, 605 { Q_STATS_OFFSET32(rx_budget_reached), 606 4, "rx_budget_reached"}, 607 { Q_STATS_OFFSET32(tx_pkts), 608 4, "tx_pkts"}, 609 { Q_STATS_OFFSET32(tx_soft_errors), 610 4, "tx_soft_errors"}, 611 { Q_STATS_OFFSET32(tx_ofld_frames_csum_ip), 612 4, "tx_ofld_frames_csum_ip"}, 613 { Q_STATS_OFFSET32(tx_ofld_frames_csum_tcp), 614 4, "tx_ofld_frames_csum_tcp"}, 615 { Q_STATS_OFFSET32(tx_ofld_frames_csum_udp), 616 4, "tx_ofld_frames_csum_udp"}, 617 { Q_STATS_OFFSET32(tx_ofld_frames_lso), 618 4, "tx_ofld_frames_lso"}, 619 { Q_STATS_OFFSET32(tx_ofld_frames_lso_hdr_splits), 620 4, "tx_ofld_frames_lso_hdr_splits"}, 621 { Q_STATS_OFFSET32(tx_encap_failures), 622 4, "tx_encap_failures"}, 623 { Q_STATS_OFFSET32(tx_hw_queue_full), 624 4, "tx_hw_queue_full"}, 625 { Q_STATS_OFFSET32(tx_hw_max_queue_depth), 626 4, "tx_hw_max_queue_depth"}, 627 { Q_STATS_OFFSET32(tx_dma_mapping_failure), 628 4, "tx_dma_mapping_failure"}, 629 { Q_STATS_OFFSET32(tx_max_drbr_queue_depth), 630 4, "tx_max_drbr_queue_depth"}, 631 { Q_STATS_OFFSET32(tx_window_violation_std), 632 4, "tx_window_violation_std"}, 633 { Q_STATS_OFFSET32(tx_window_violation_tso), 634 4, "tx_window_violation_tso"}, 635 #if 0 636 { Q_STATS_OFFSET32(tx_unsupported_tso_request_ipv6), 637 4, "tx_unsupported_tso_request_ipv6"}, 638 { Q_STATS_OFFSET32(tx_unsupported_tso_request_not_tcp), 639 4, "tx_unsupported_tso_request_not_tcp"}, 640 #endif 641 { Q_STATS_OFFSET32(tx_chain_lost_mbuf), 642 4, "tx_chain_lost_mbuf"}, 643 { Q_STATS_OFFSET32(tx_frames_deferred), 644 4, "tx_frames_deferred"}, 645 { Q_STATS_OFFSET32(tx_queue_xoff), 646 4, "tx_queue_xoff"}, 647 { Q_STATS_OFFSET32(mbuf_defrag_attempts), 648 4, "mbuf_defrag_attempts"}, 649 { Q_STATS_OFFSET32(mbuf_defrag_failures), 650 4, "mbuf_defrag_failures"}, 651 { Q_STATS_OFFSET32(mbuf_rx_bd_alloc_failed), 652 4, "mbuf_rx_bd_alloc_failed"}, 653 { Q_STATS_OFFSET32(mbuf_rx_bd_mapping_failed), 654 4, "mbuf_rx_bd_mapping_failed"}, 655 { Q_STATS_OFFSET32(mbuf_rx_tpa_alloc_failed), 656 4, "mbuf_rx_tpa_alloc_failed"}, 657 { Q_STATS_OFFSET32(mbuf_rx_tpa_mapping_failed), 658 4, "mbuf_rx_tpa_mapping_failed"}, 659 { Q_STATS_OFFSET32(mbuf_rx_sge_alloc_failed), 660 4, "mbuf_rx_sge_alloc_failed"}, 661 { Q_STATS_OFFSET32(mbuf_rx_sge_mapping_failed), 662 4, "mbuf_rx_sge_mapping_failed"}, 663 { Q_STATS_OFFSET32(mbuf_alloc_tx), 664 4, "mbuf_alloc_tx"}, 665 { Q_STATS_OFFSET32(mbuf_alloc_rx), 666 4, "mbuf_alloc_rx"}, 667 { Q_STATS_OFFSET32(mbuf_alloc_sge), 668 4, "mbuf_alloc_sge"}, 669 { Q_STATS_OFFSET32(mbuf_alloc_tpa), 670 4, "mbuf_alloc_tpa"} 671 }; 672 673 #define BXE_NUM_ETH_STATS ARRAY_SIZE(bxe_eth_stats_arr) 674 #define BXE_NUM_ETH_Q_STATS ARRAY_SIZE(bxe_eth_q_stats_arr) 675 676 677 static void bxe_cmng_fns_init(struct bxe_softc *sc, 678 uint8_t read_cfg, 679 uint8_t cmng_type); 680 static int bxe_get_cmng_fns_mode(struct bxe_softc *sc); 681 static void storm_memset_cmng(struct bxe_softc *sc, 682 struct cmng_init *cmng, 683 uint8_t port); 684 static void bxe_set_reset_global(struct bxe_softc *sc); 685 static void bxe_set_reset_in_progress(struct bxe_softc *sc); 686 static uint8_t bxe_reset_is_done(struct bxe_softc *sc, 687 int engine); 688 static uint8_t bxe_clear_pf_load(struct bxe_softc *sc); 689 static uint8_t bxe_chk_parity_attn(struct bxe_softc *sc, 690 uint8_t *global, 691 uint8_t print); 692 static void bxe_int_disable(struct bxe_softc *sc); 693 static int bxe_release_leader_lock(struct bxe_softc *sc); 694 static void bxe_pf_disable(struct bxe_softc *sc); 695 static void bxe_free_fp_buffers(struct bxe_softc *sc); 696 static inline void bxe_update_rx_prod(struct bxe_softc *sc, 697 struct bxe_fastpath *fp, 698 uint16_t rx_bd_prod, 699 uint16_t rx_cq_prod, 700 uint16_t rx_sge_prod); 701 static void bxe_link_report_locked(struct bxe_softc *sc); 702 static void bxe_link_report(struct bxe_softc *sc); 703 static void bxe_link_status_update(struct bxe_softc *sc); 704 static void bxe_periodic_callout_func(void *xsc); 705 static void bxe_periodic_start(struct bxe_softc *sc); 706 static void bxe_periodic_stop(struct bxe_softc *sc); 707 static int bxe_alloc_rx_bd_mbuf(struct bxe_fastpath *fp, 708 uint16_t prev_index, 709 uint16_t index); 710 static int bxe_alloc_rx_tpa_mbuf(struct bxe_fastpath *fp, 711 int queue); 712 static int bxe_alloc_rx_sge_mbuf(struct bxe_fastpath *fp, 713 uint16_t index); 714 static uint8_t bxe_txeof(struct bxe_softc *sc, 715 struct bxe_fastpath *fp); 716 static void bxe_task_fp(struct bxe_fastpath *fp); 717 static __noinline void bxe_dump_mbuf(struct bxe_softc *sc, 718 struct mbuf *m, 719 uint8_t contents); 720 static int bxe_alloc_mem(struct bxe_softc *sc); 721 static void bxe_free_mem(struct bxe_softc *sc); 722 static int bxe_alloc_fw_stats_mem(struct bxe_softc *sc); 723 static void bxe_free_fw_stats_mem(struct bxe_softc *sc); 724 static int bxe_interrupt_attach(struct bxe_softc *sc); 725 static void bxe_interrupt_detach(struct bxe_softc *sc); 726 static void bxe_set_rx_mode(struct bxe_softc *sc); 727 static int bxe_init_locked(struct bxe_softc *sc); 728 static int bxe_stop_locked(struct bxe_softc *sc); 729 static __noinline int bxe_nic_load(struct bxe_softc *sc, 730 int load_mode); 731 static __noinline int bxe_nic_unload(struct bxe_softc *sc, 732 uint32_t unload_mode, 733 uint8_t keep_link); 734 735 static void bxe_handle_sp_tq(void *context, int pending); 736 static void bxe_handle_rx_mode_tq(void *context, int pending); 737 static void bxe_handle_fp_tq(void *context, int pending); 738 739 740 /* calculate crc32 on a buffer (NOTE: crc32_length MUST be aligned to 8) */ 741 uint32_t 742 calc_crc32(uint8_t *crc32_packet, 743 uint32_t crc32_length, 744 uint32_t crc32_seed, 745 uint8_t complement) 746 { 747 uint32_t byte = 0; 748 uint32_t bit = 0; 749 uint8_t msb = 0; 750 uint32_t temp = 0; 751 uint32_t shft = 0; 752 uint8_t current_byte = 0; 753 uint32_t crc32_result = crc32_seed; 754 const uint32_t CRC32_POLY = 0x1edc6f41; 755 756 if ((crc32_packet == NULL) || 757 (crc32_length == 0) || 758 ((crc32_length % 8) != 0)) 759 { 760 return (crc32_result); 761 } 762 763 for (byte = 0; byte < crc32_length; byte = byte + 1) 764 { 765 current_byte = crc32_packet[byte]; 766 for (bit = 0; bit < 8; bit = bit + 1) 767 { 768 /* msb = crc32_result[31]; */ 769 msb = (uint8_t)(crc32_result >> 31); 770 771 crc32_result = crc32_result << 1; 772 773 /* it (msb != current_byte[bit]) */ 774 if (msb != (0x1 & (current_byte >> bit))) 775 { 776 crc32_result = crc32_result ^ CRC32_POLY; 777 /* crc32_result[0] = 1 */ 778 crc32_result |= 1; 779 } 780 } 781 } 782 783 /* Last step is to: 784 * 1. "mirror" every bit 785 * 2. swap the 4 bytes 786 * 3. complement each bit 787 */ 788 789 /* Mirror */ 790 temp = crc32_result; 791 shft = sizeof(crc32_result) * 8 - 1; 792 793 for (crc32_result >>= 1; crc32_result; crc32_result >>= 1) 794 { 795 temp <<= 1; 796 temp |= crc32_result & 1; 797 shft-- ; 798 } 799 800 /* temp[31-bit] = crc32_result[bit] */ 801 temp <<= shft; 802 803 /* Swap */ 804 /* crc32_result = {temp[7:0], temp[15:8], temp[23:16], temp[31:24]} */ 805 { 806 uint32_t t0, t1, t2, t3; 807 t0 = (0x000000ff & (temp >> 24)); 808 t1 = (0x0000ff00 & (temp >> 8)); 809 t2 = (0x00ff0000 & (temp << 8)); 810 t3 = (0xff000000 & (temp << 24)); 811 crc32_result = t0 | t1 | t2 | t3; 812 } 813 814 /* Complement */ 815 if (complement) 816 { 817 crc32_result = ~crc32_result; 818 } 819 820 return (crc32_result); 821 } 822 823 int 824 bxe_test_bit(int nr, 825 volatile unsigned long *addr) 826 { 827 return ((atomic_load_acq_long(addr) & (1 << nr)) != 0); 828 } 829 830 void 831 bxe_set_bit(unsigned int nr, 832 volatile unsigned long *addr) 833 { 834 atomic_set_acq_long(addr, (1 << nr)); 835 } 836 837 void 838 bxe_clear_bit(int nr, 839 volatile unsigned long *addr) 840 { 841 atomic_clear_acq_long(addr, (1 << nr)); 842 } 843 844 int 845 bxe_test_and_set_bit(int nr, 846 volatile unsigned long *addr) 847 { 848 unsigned long x; 849 nr = (1 << nr); 850 do { 851 x = *addr; 852 } while (atomic_cmpset_acq_long(addr, x, x | nr) == 0); 853 // if (x & nr) bit_was_set; else bit_was_not_set; 854 return (x & nr); 855 } 856 857 int 858 bxe_test_and_clear_bit(int nr, 859 volatile unsigned long *addr) 860 { 861 unsigned long x; 862 nr = (1 << nr); 863 do { 864 x = *addr; 865 } while (atomic_cmpset_acq_long(addr, x, x & ~nr) == 0); 866 // if (x & nr) bit_was_set; else bit_was_not_set; 867 return (x & nr); 868 } 869 870 int 871 bxe_cmpxchg(volatile int *addr, 872 int old, 873 int new) 874 { 875 int x; 876 do { 877 x = *addr; 878 } while (atomic_cmpset_acq_int(addr, old, new) == 0); 879 return (x); 880 } 881 882 /* 883 * Get DMA memory from the OS. 884 * 885 * Validates that the OS has provided DMA buffers in response to a 886 * bus_dmamap_load call and saves the physical address of those buffers. 887 * When the callback is used the OS will return 0 for the mapping function 888 * (bus_dmamap_load) so we use the value of map_arg->maxsegs to pass any 889 * failures back to the caller. 890 * 891 * Returns: 892 * Nothing. 893 */ 894 static void 895 bxe_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 896 { 897 struct bxe_dma *dma = arg; 898 899 if (error) { 900 dma->paddr = 0; 901 dma->nseg = 0; 902 BLOGE(dma->sc, "Failed DMA alloc '%s' (%d)!\n", dma->msg, error); 903 } else { 904 dma->paddr = segs->ds_addr; 905 dma->nseg = nseg; 906 #if 0 907 BLOGD(dma->sc, DBG_LOAD, 908 "DMA alloc '%s': vaddr=%p paddr=%p nseg=%d size=%lu\n", 909 dma->msg, dma->vaddr, (void *)dma->paddr, 910 dma->nseg, dma->size); 911 #endif 912 } 913 } 914 915 /* 916 * Allocate a block of memory and map it for DMA. No partial completions 917 * allowed and release any resources acquired if we can't acquire all 918 * resources. 919 * 920 * Returns: 921 * 0 = Success, !0 = Failure 922 */ 923 int 924 bxe_dma_alloc(struct bxe_softc *sc, 925 bus_size_t size, 926 struct bxe_dma *dma, 927 const char *msg) 928 { 929 int rc; 930 931 if (dma->size > 0) { 932 BLOGE(sc, "dma block '%s' already has size %lu\n", msg, 933 (unsigned long)dma->size); 934 return (1); 935 } 936 937 memset(dma, 0, sizeof(*dma)); /* sanity */ 938 dma->sc = sc; 939 dma->size = size; 940 snprintf(dma->msg, sizeof(dma->msg), "%s", msg); 941 942 rc = bus_dma_tag_create(sc->parent_dma_tag, /* parent tag */ 943 BCM_PAGE_SIZE, /* alignment */ 944 0, /* boundary limit */ 945 BUS_SPACE_MAXADDR, /* restricted low */ 946 BUS_SPACE_MAXADDR, /* restricted hi */ 947 NULL, /* addr filter() */ 948 NULL, /* addr filter() arg */ 949 size, /* max map size */ 950 1, /* num discontinuous */ 951 size, /* max seg size */ 952 BUS_DMA_ALLOCNOW, /* flags */ 953 NULL, /* lock() */ 954 NULL, /* lock() arg */ 955 &dma->tag); /* returned dma tag */ 956 if (rc != 0) { 957 BLOGE(sc, "Failed to create dma tag for '%s' (%d)\n", msg, rc); 958 memset(dma, 0, sizeof(*dma)); 959 return (1); 960 } 961 962 rc = bus_dmamem_alloc(dma->tag, 963 (void **)&dma->vaddr, 964 (BUS_DMA_NOWAIT | BUS_DMA_ZERO), 965 &dma->map); 966 if (rc != 0) { 967 BLOGE(sc, "Failed to alloc dma mem for '%s' (%d)\n", msg, rc); 968 bus_dma_tag_destroy(dma->tag); 969 memset(dma, 0, sizeof(*dma)); 970 return (1); 971 } 972 973 rc = bus_dmamap_load(dma->tag, 974 dma->map, 975 dma->vaddr, 976 size, 977 bxe_dma_map_addr, /* BLOGD in here */ 978 dma, 979 BUS_DMA_NOWAIT); 980 if (rc != 0) { 981 BLOGE(sc, "Failed to load dma map for '%s' (%d)\n", msg, rc); 982 bus_dmamem_free(dma->tag, dma->vaddr, dma->map); 983 bus_dma_tag_destroy(dma->tag); 984 memset(dma, 0, sizeof(*dma)); 985 return (1); 986 } 987 988 return (0); 989 } 990 991 void 992 bxe_dma_free(struct bxe_softc *sc, 993 struct bxe_dma *dma) 994 { 995 if (dma->size > 0) { 996 #if 0 997 BLOGD(sc, DBG_LOAD, 998 "DMA free '%s': vaddr=%p paddr=%p nseg=%d size=%lu\n", 999 dma->msg, dma->vaddr, (void *)dma->paddr, 1000 dma->nseg, dma->size); 1001 #endif 1002 1003 DBASSERT(sc, (dma->tag != NULL), ("dma tag is NULL")); 1004 1005 bus_dmamap_sync(dma->tag, dma->map, 1006 (BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE)); 1007 bus_dmamap_unload(dma->tag, dma->map); 1008 bus_dmamem_free(dma->tag, dma->vaddr, dma->map); 1009 bus_dma_tag_destroy(dma->tag); 1010 } 1011 1012 memset(dma, 0, sizeof(*dma)); 1013 } 1014 1015 /* 1016 * These indirect read and write routines are only during init. 1017 * The locking is handled by the MCP. 1018 */ 1019 1020 void 1021 bxe_reg_wr_ind(struct bxe_softc *sc, 1022 uint32_t addr, 1023 uint32_t val) 1024 { 1025 pci_write_config(sc->dev, PCICFG_GRC_ADDRESS, addr, 4); 1026 pci_write_config(sc->dev, PCICFG_GRC_DATA, val, 4); 1027 pci_write_config(sc->dev, PCICFG_GRC_ADDRESS, 0, 4); 1028 } 1029 1030 uint32_t 1031 bxe_reg_rd_ind(struct bxe_softc *sc, 1032 uint32_t addr) 1033 { 1034 uint32_t val; 1035 1036 pci_write_config(sc->dev, PCICFG_GRC_ADDRESS, addr, 4); 1037 val = pci_read_config(sc->dev, PCICFG_GRC_DATA, 4); 1038 pci_write_config(sc->dev, PCICFG_GRC_ADDRESS, 0, 4); 1039 1040 return (val); 1041 } 1042 1043 #if 0 1044 void bxe_dp_dmae(struct bxe_softc *sc, struct dmae_command *dmae, int msglvl) 1045 { 1046 uint32_t src_type = dmae->opcode & DMAE_COMMAND_SRC; 1047 1048 switch (dmae->opcode & DMAE_COMMAND_DST) { 1049 case DMAE_CMD_DST_PCI: 1050 if (src_type == DMAE_CMD_SRC_PCI) 1051 DP(msglvl, "DMAE: opcode 0x%08x\n" 1052 "src [%x:%08x], len [%d*4], dst [%x:%08x]\n" 1053 "comp_addr [%x:%08x], comp_val 0x%08x\n", 1054 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo, 1055 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo, 1056 dmae->comp_addr_hi, dmae->comp_addr_lo, 1057 dmae->comp_val); 1058 else 1059 DP(msglvl, "DMAE: opcode 0x%08x\n" 1060 "src [%08x], len [%d*4], dst [%x:%08x]\n" 1061 "comp_addr [%x:%08x], comp_val 0x%08x\n", 1062 dmae->opcode, dmae->src_addr_lo >> 2, 1063 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo, 1064 dmae->comp_addr_hi, dmae->comp_addr_lo, 1065 dmae->comp_val); 1066 break; 1067 case DMAE_CMD_DST_GRC: 1068 if (src_type == DMAE_CMD_SRC_PCI) 1069 DP(msglvl, "DMAE: opcode 0x%08x\n" 1070 "src [%x:%08x], len [%d*4], dst_addr [%08x]\n" 1071 "comp_addr [%x:%08x], comp_val 0x%08x\n", 1072 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo, 1073 dmae->len, dmae->dst_addr_lo >> 2, 1074 dmae->comp_addr_hi, dmae->comp_addr_lo, 1075 dmae->comp_val); 1076 else 1077 DP(msglvl, "DMAE: opcode 0x%08x\n" 1078 "src [%08x], len [%d*4], dst [%08x]\n" 1079 "comp_addr [%x:%08x], comp_val 0x%08x\n", 1080 dmae->opcode, dmae->src_addr_lo >> 2, 1081 dmae->len, dmae->dst_addr_lo >> 2, 1082 dmae->comp_addr_hi, dmae->comp_addr_lo, 1083 dmae->comp_val); 1084 break; 1085 default: 1086 if (src_type == DMAE_CMD_SRC_PCI) 1087 DP(msglvl, "DMAE: opcode 0x%08x\n" 1088 "src_addr [%x:%08x] len [%d * 4] dst_addr [none]\n" 1089 "comp_addr [%x:%08x] comp_val 0x%08x\n", 1090 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo, 1091 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo, 1092 dmae->comp_val); 1093 else 1094 DP(msglvl, "DMAE: opcode 0x%08x\n" 1095 "src_addr [%08x] len [%d * 4] dst_addr [none]\n" 1096 "comp_addr [%x:%08x] comp_val 0x%08x\n", 1097 dmae->opcode, dmae->src_addr_lo >> 2, 1098 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo, 1099 dmae->comp_val); 1100 break; 1101 } 1102 1103 } 1104 #endif 1105 1106 static int 1107 bxe_acquire_hw_lock(struct bxe_softc *sc, 1108 uint32_t resource) 1109 { 1110 uint32_t lock_status; 1111 uint32_t resource_bit = (1 << resource); 1112 int func = SC_FUNC(sc); 1113 uint32_t hw_lock_control_reg; 1114 int cnt; 1115 1116 /* validate the resource is within range */ 1117 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { 1118 BLOGE(sc, "resource 0x%x > HW_LOCK_MAX_RESOURCE_VALUE\n", resource); 1119 return (-1); 1120 } 1121 1122 if (func <= 5) { 1123 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + (func * 8)); 1124 } else { 1125 hw_lock_control_reg = 1126 (MISC_REG_DRIVER_CONTROL_7 + ((func - 6) * 8)); 1127 } 1128 1129 /* validate the resource is not already taken */ 1130 lock_status = REG_RD(sc, hw_lock_control_reg); 1131 if (lock_status & resource_bit) { 1132 BLOGE(sc, "resource in use (status 0x%x bit 0x%x)\n", 1133 lock_status, resource_bit); 1134 return (-1); 1135 } 1136 1137 /* try every 5ms for 5 seconds */ 1138 for (cnt = 0; cnt < 1000; cnt++) { 1139 REG_WR(sc, (hw_lock_control_reg + 4), resource_bit); 1140 lock_status = REG_RD(sc, hw_lock_control_reg); 1141 if (lock_status & resource_bit) { 1142 return (0); 1143 } 1144 DELAY(5000); 1145 } 1146 1147 BLOGE(sc, "Resource lock timeout!\n"); 1148 return (-1); 1149 } 1150 1151 static int 1152 bxe_release_hw_lock(struct bxe_softc *sc, 1153 uint32_t resource) 1154 { 1155 uint32_t lock_status; 1156 uint32_t resource_bit = (1 << resource); 1157 int func = SC_FUNC(sc); 1158 uint32_t hw_lock_control_reg; 1159 1160 /* validate the resource is within range */ 1161 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { 1162 BLOGE(sc, "resource 0x%x > HW_LOCK_MAX_RESOURCE_VALUE\n", resource); 1163 return (-1); 1164 } 1165 1166 if (func <= 5) { 1167 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + (func * 8)); 1168 } else { 1169 hw_lock_control_reg = 1170 (MISC_REG_DRIVER_CONTROL_7 + ((func - 6) * 8)); 1171 } 1172 1173 /* validate the resource is currently taken */ 1174 lock_status = REG_RD(sc, hw_lock_control_reg); 1175 if (!(lock_status & resource_bit)) { 1176 BLOGE(sc, "resource not in use (status 0x%x bit 0x%x)\n", 1177 lock_status, resource_bit); 1178 return (-1); 1179 } 1180 1181 REG_WR(sc, hw_lock_control_reg, resource_bit); 1182 return (0); 1183 } 1184 1185 /* 1186 * Per pf misc lock must be acquired before the per port mcp lock. Otherwise, 1187 * had we done things the other way around, if two pfs from the same port 1188 * would attempt to access nvram at the same time, we could run into a 1189 * scenario such as: 1190 * pf A takes the port lock. 1191 * pf B succeeds in taking the same lock since they are from the same port. 1192 * pf A takes the per pf misc lock. Performs eeprom access. 1193 * pf A finishes. Unlocks the per pf misc lock. 1194 * Pf B takes the lock and proceeds to perform it's own access. 1195 * pf A unlocks the per port lock, while pf B is still working (!). 1196 * mcp takes the per port lock and corrupts pf B's access (and/or has it's own 1197 * access corrupted by pf B).* 1198 */ 1199 static int 1200 bxe_acquire_nvram_lock(struct bxe_softc *sc) 1201 { 1202 int port = SC_PORT(sc); 1203 int count, i; 1204 uint32_t val = 0; 1205 1206 /* acquire HW lock: protect against other PFs in PF Direct Assignment */ 1207 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_NVRAM); 1208 1209 /* adjust timeout for emulation/FPGA */ 1210 count = NVRAM_TIMEOUT_COUNT; 1211 if (CHIP_REV_IS_SLOW(sc)) { 1212 count *= 100; 1213 } 1214 1215 /* request access to nvram interface */ 1216 REG_WR(sc, MCP_REG_MCPR_NVM_SW_ARB, 1217 (MCPR_NVM_SW_ARB_ARB_REQ_SET1 << port)); 1218 1219 for (i = 0; i < count*10; i++) { 1220 val = REG_RD(sc, MCP_REG_MCPR_NVM_SW_ARB); 1221 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) { 1222 break; 1223 } 1224 1225 DELAY(5); 1226 } 1227 1228 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) { 1229 BLOGE(sc, "Cannot get access to nvram interface\n"); 1230 return (-1); 1231 } 1232 1233 return (0); 1234 } 1235 1236 static int 1237 bxe_release_nvram_lock(struct bxe_softc *sc) 1238 { 1239 int port = SC_PORT(sc); 1240 int count, i; 1241 uint32_t val = 0; 1242 1243 /* adjust timeout for emulation/FPGA */ 1244 count = NVRAM_TIMEOUT_COUNT; 1245 if (CHIP_REV_IS_SLOW(sc)) { 1246 count *= 100; 1247 } 1248 1249 /* relinquish nvram interface */ 1250 REG_WR(sc, MCP_REG_MCPR_NVM_SW_ARB, 1251 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << port)); 1252 1253 for (i = 0; i < count*10; i++) { 1254 val = REG_RD(sc, MCP_REG_MCPR_NVM_SW_ARB); 1255 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) { 1256 break; 1257 } 1258 1259 DELAY(5); 1260 } 1261 1262 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) { 1263 BLOGE(sc, "Cannot free access to nvram interface\n"); 1264 return (-1); 1265 } 1266 1267 /* release HW lock: protect against other PFs in PF Direct Assignment */ 1268 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_NVRAM); 1269 1270 return (0); 1271 } 1272 1273 static void 1274 bxe_enable_nvram_access(struct bxe_softc *sc) 1275 { 1276 uint32_t val; 1277 1278 val = REG_RD(sc, MCP_REG_MCPR_NVM_ACCESS_ENABLE); 1279 1280 /* enable both bits, even on read */ 1281 REG_WR(sc, MCP_REG_MCPR_NVM_ACCESS_ENABLE, 1282 (val | MCPR_NVM_ACCESS_ENABLE_EN | MCPR_NVM_ACCESS_ENABLE_WR_EN)); 1283 } 1284 1285 static void 1286 bxe_disable_nvram_access(struct bxe_softc *sc) 1287 { 1288 uint32_t val; 1289 1290 val = REG_RD(sc, MCP_REG_MCPR_NVM_ACCESS_ENABLE); 1291 1292 /* disable both bits, even after read */ 1293 REG_WR(sc, MCP_REG_MCPR_NVM_ACCESS_ENABLE, 1294 (val & ~(MCPR_NVM_ACCESS_ENABLE_EN | 1295 MCPR_NVM_ACCESS_ENABLE_WR_EN))); 1296 } 1297 1298 static int 1299 bxe_nvram_read_dword(struct bxe_softc *sc, 1300 uint32_t offset, 1301 uint32_t *ret_val, 1302 uint32_t cmd_flags) 1303 { 1304 int count, i, rc; 1305 uint32_t val; 1306 1307 /* build the command word */ 1308 cmd_flags |= MCPR_NVM_COMMAND_DOIT; 1309 1310 /* need to clear DONE bit separately */ 1311 REG_WR(sc, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE); 1312 1313 /* address of the NVRAM to read from */ 1314 REG_WR(sc, MCP_REG_MCPR_NVM_ADDR, 1315 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE)); 1316 1317 /* issue a read command */ 1318 REG_WR(sc, MCP_REG_MCPR_NVM_COMMAND, cmd_flags); 1319 1320 /* adjust timeout for emulation/FPGA */ 1321 count = NVRAM_TIMEOUT_COUNT; 1322 if (CHIP_REV_IS_SLOW(sc)) { 1323 count *= 100; 1324 } 1325 1326 /* wait for completion */ 1327 *ret_val = 0; 1328 rc = -1; 1329 for (i = 0; i < count; i++) { 1330 DELAY(5); 1331 val = REG_RD(sc, MCP_REG_MCPR_NVM_COMMAND); 1332 1333 if (val & MCPR_NVM_COMMAND_DONE) { 1334 val = REG_RD(sc, MCP_REG_MCPR_NVM_READ); 1335 /* we read nvram data in cpu order 1336 * but ethtool sees it as an array of bytes 1337 * converting to big-endian will do the work 1338 */ 1339 *ret_val = htobe32(val); 1340 rc = 0; 1341 break; 1342 } 1343 } 1344 1345 if (rc == -1) { 1346 BLOGE(sc, "nvram read timeout expired\n"); 1347 } 1348 1349 return (rc); 1350 } 1351 1352 static int 1353 bxe_nvram_read(struct bxe_softc *sc, 1354 uint32_t offset, 1355 uint8_t *ret_buf, 1356 int buf_size) 1357 { 1358 uint32_t cmd_flags; 1359 uint32_t val; 1360 int rc; 1361 1362 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) { 1363 BLOGE(sc, "Invalid parameter, offset 0x%x buf_size 0x%x\n", 1364 offset, buf_size); 1365 return (-1); 1366 } 1367 1368 if ((offset + buf_size) > sc->devinfo.flash_size) { 1369 BLOGE(sc, "Invalid parameter, " 1370 "offset 0x%x + buf_size 0x%x > flash_size 0x%x\n", 1371 offset, buf_size, sc->devinfo.flash_size); 1372 return (-1); 1373 } 1374 1375 /* request access to nvram interface */ 1376 rc = bxe_acquire_nvram_lock(sc); 1377 if (rc) { 1378 return (rc); 1379 } 1380 1381 /* enable access to nvram interface */ 1382 bxe_enable_nvram_access(sc); 1383 1384 /* read the first word(s) */ 1385 cmd_flags = MCPR_NVM_COMMAND_FIRST; 1386 while ((buf_size > sizeof(uint32_t)) && (rc == 0)) { 1387 rc = bxe_nvram_read_dword(sc, offset, &val, cmd_flags); 1388 memcpy(ret_buf, &val, 4); 1389 1390 /* advance to the next dword */ 1391 offset += sizeof(uint32_t); 1392 ret_buf += sizeof(uint32_t); 1393 buf_size -= sizeof(uint32_t); 1394 cmd_flags = 0; 1395 } 1396 1397 if (rc == 0) { 1398 cmd_flags |= MCPR_NVM_COMMAND_LAST; 1399 rc = bxe_nvram_read_dword(sc, offset, &val, cmd_flags); 1400 memcpy(ret_buf, &val, 4); 1401 } 1402 1403 /* disable access to nvram interface */ 1404 bxe_disable_nvram_access(sc); 1405 bxe_release_nvram_lock(sc); 1406 1407 return (rc); 1408 } 1409 1410 static int 1411 bxe_nvram_write_dword(struct bxe_softc *sc, 1412 uint32_t offset, 1413 uint32_t val, 1414 uint32_t cmd_flags) 1415 { 1416 int count, i, rc; 1417 1418 /* build the command word */ 1419 cmd_flags |= (MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WR); 1420 1421 /* need to clear DONE bit separately */ 1422 REG_WR(sc, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE); 1423 1424 /* write the data */ 1425 REG_WR(sc, MCP_REG_MCPR_NVM_WRITE, val); 1426 1427 /* address of the NVRAM to write to */ 1428 REG_WR(sc, MCP_REG_MCPR_NVM_ADDR, 1429 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE)); 1430 1431 /* issue the write command */ 1432 REG_WR(sc, MCP_REG_MCPR_NVM_COMMAND, cmd_flags); 1433 1434 /* adjust timeout for emulation/FPGA */ 1435 count = NVRAM_TIMEOUT_COUNT; 1436 if (CHIP_REV_IS_SLOW(sc)) { 1437 count *= 100; 1438 } 1439 1440 /* wait for completion */ 1441 rc = -1; 1442 for (i = 0; i < count; i++) { 1443 DELAY(5); 1444 val = REG_RD(sc, MCP_REG_MCPR_NVM_COMMAND); 1445 if (val & MCPR_NVM_COMMAND_DONE) { 1446 rc = 0; 1447 break; 1448 } 1449 } 1450 1451 if (rc == -1) { 1452 BLOGE(sc, "nvram write timeout expired\n"); 1453 } 1454 1455 return (rc); 1456 } 1457 1458 #define BYTE_OFFSET(offset) (8 * (offset & 0x03)) 1459 1460 static int 1461 bxe_nvram_write1(struct bxe_softc *sc, 1462 uint32_t offset, 1463 uint8_t *data_buf, 1464 int buf_size) 1465 { 1466 uint32_t cmd_flags; 1467 uint32_t align_offset; 1468 uint32_t val; 1469 int rc; 1470 1471 if ((offset + buf_size) > sc->devinfo.flash_size) { 1472 BLOGE(sc, "Invalid parameter, " 1473 "offset 0x%x + buf_size 0x%x > flash_size 0x%x\n", 1474 offset, buf_size, sc->devinfo.flash_size); 1475 return (-1); 1476 } 1477 1478 /* request access to nvram interface */ 1479 rc = bxe_acquire_nvram_lock(sc); 1480 if (rc) { 1481 return (rc); 1482 } 1483 1484 /* enable access to nvram interface */ 1485 bxe_enable_nvram_access(sc); 1486 1487 cmd_flags = (MCPR_NVM_COMMAND_FIRST | MCPR_NVM_COMMAND_LAST); 1488 align_offset = (offset & ~0x03); 1489 rc = bxe_nvram_read_dword(sc, align_offset, &val, cmd_flags); 1490 1491 if (rc == 0) { 1492 val &= ~(0xff << BYTE_OFFSET(offset)); 1493 val |= (*data_buf << BYTE_OFFSET(offset)); 1494 1495 /* nvram data is returned as an array of bytes 1496 * convert it back to cpu order 1497 */ 1498 val = be32toh(val); 1499 1500 rc = bxe_nvram_write_dword(sc, align_offset, val, cmd_flags); 1501 } 1502 1503 /* disable access to nvram interface */ 1504 bxe_disable_nvram_access(sc); 1505 bxe_release_nvram_lock(sc); 1506 1507 return (rc); 1508 } 1509 1510 static int 1511 bxe_nvram_write(struct bxe_softc *sc, 1512 uint32_t offset, 1513 uint8_t *data_buf, 1514 int buf_size) 1515 { 1516 uint32_t cmd_flags; 1517 uint32_t val; 1518 uint32_t written_so_far; 1519 int rc; 1520 1521 if (buf_size == 1) { 1522 return (bxe_nvram_write1(sc, offset, data_buf, buf_size)); 1523 } 1524 1525 if ((offset & 0x03) || (buf_size & 0x03) /* || (buf_size == 0) */) { 1526 BLOGE(sc, "Invalid parameter, offset 0x%x buf_size 0x%x\n", 1527 offset, buf_size); 1528 return (-1); 1529 } 1530 1531 if (buf_size == 0) { 1532 return (0); /* nothing to do */ 1533 } 1534 1535 if ((offset + buf_size) > sc->devinfo.flash_size) { 1536 BLOGE(sc, "Invalid parameter, " 1537 "offset 0x%x + buf_size 0x%x > flash_size 0x%x\n", 1538 offset, buf_size, sc->devinfo.flash_size); 1539 return (-1); 1540 } 1541 1542 /* request access to nvram interface */ 1543 rc = bxe_acquire_nvram_lock(sc); 1544 if (rc) { 1545 return (rc); 1546 } 1547 1548 /* enable access to nvram interface */ 1549 bxe_enable_nvram_access(sc); 1550 1551 written_so_far = 0; 1552 cmd_flags = MCPR_NVM_COMMAND_FIRST; 1553 while ((written_so_far < buf_size) && (rc == 0)) { 1554 if (written_so_far == (buf_size - sizeof(uint32_t))) { 1555 cmd_flags |= MCPR_NVM_COMMAND_LAST; 1556 } else if (((offset + 4) % NVRAM_PAGE_SIZE) == 0) { 1557 cmd_flags |= MCPR_NVM_COMMAND_LAST; 1558 } else if ((offset % NVRAM_PAGE_SIZE) == 0) { 1559 cmd_flags |= MCPR_NVM_COMMAND_FIRST; 1560 } 1561 1562 memcpy(&val, data_buf, 4); 1563 1564 rc = bxe_nvram_write_dword(sc, offset, val, cmd_flags); 1565 1566 /* advance to the next dword */ 1567 offset += sizeof(uint32_t); 1568 data_buf += sizeof(uint32_t); 1569 written_so_far += sizeof(uint32_t); 1570 cmd_flags = 0; 1571 } 1572 1573 /* disable access to nvram interface */ 1574 bxe_disable_nvram_access(sc); 1575 bxe_release_nvram_lock(sc); 1576 1577 return (rc); 1578 } 1579 1580 /* copy command into DMAE command memory and set DMAE command Go */ 1581 void 1582 bxe_post_dmae(struct bxe_softc *sc, 1583 struct dmae_command *dmae, 1584 int idx) 1585 { 1586 uint32_t cmd_offset; 1587 int i; 1588 1589 cmd_offset = (DMAE_REG_CMD_MEM + (sizeof(struct dmae_command) * idx)); 1590 for (i = 0; i < ((sizeof(struct dmae_command) / 4)); i++) { 1591 REG_WR(sc, (cmd_offset + (i * 4)), *(((uint32_t *)dmae) + i)); 1592 } 1593 1594 REG_WR(sc, dmae_reg_go_c[idx], 1); 1595 } 1596 1597 uint32_t 1598 bxe_dmae_opcode_add_comp(uint32_t opcode, 1599 uint8_t comp_type) 1600 { 1601 return (opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) | 1602 DMAE_COMMAND_C_TYPE_ENABLE)); 1603 } 1604 1605 uint32_t 1606 bxe_dmae_opcode_clr_src_reset(uint32_t opcode) 1607 { 1608 return (opcode & ~DMAE_COMMAND_SRC_RESET); 1609 } 1610 1611 uint32_t 1612 bxe_dmae_opcode(struct bxe_softc *sc, 1613 uint8_t src_type, 1614 uint8_t dst_type, 1615 uint8_t with_comp, 1616 uint8_t comp_type) 1617 { 1618 uint32_t opcode = 0; 1619 1620 opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) | 1621 (dst_type << DMAE_COMMAND_DST_SHIFT)); 1622 1623 opcode |= (DMAE_COMMAND_SRC_RESET | DMAE_COMMAND_DST_RESET); 1624 1625 opcode |= (SC_PORT(sc) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0); 1626 1627 opcode |= ((SC_VN(sc) << DMAE_COMMAND_E1HVN_SHIFT) | 1628 (SC_VN(sc) << DMAE_COMMAND_DST_VN_SHIFT)); 1629 1630 opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT); 1631 1632 #ifdef __BIG_ENDIAN 1633 opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP; 1634 #else 1635 opcode |= DMAE_CMD_ENDIANITY_DW_SWAP; 1636 #endif 1637 1638 if (with_comp) { 1639 opcode = bxe_dmae_opcode_add_comp(opcode, comp_type); 1640 } 1641 1642 return (opcode); 1643 } 1644 1645 static void 1646 bxe_prep_dmae_with_comp(struct bxe_softc *sc, 1647 struct dmae_command *dmae, 1648 uint8_t src_type, 1649 uint8_t dst_type) 1650 { 1651 memset(dmae, 0, sizeof(struct dmae_command)); 1652 1653 /* set the opcode */ 1654 dmae->opcode = bxe_dmae_opcode(sc, src_type, dst_type, 1655 TRUE, DMAE_COMP_PCI); 1656 1657 /* fill in the completion parameters */ 1658 dmae->comp_addr_lo = U64_LO(BXE_SP_MAPPING(sc, wb_comp)); 1659 dmae->comp_addr_hi = U64_HI(BXE_SP_MAPPING(sc, wb_comp)); 1660 dmae->comp_val = DMAE_COMP_VAL; 1661 } 1662 1663 /* issue a DMAE command over the init channel and wait for completion */ 1664 static int 1665 bxe_issue_dmae_with_comp(struct bxe_softc *sc, 1666 struct dmae_command *dmae) 1667 { 1668 uint32_t *wb_comp = BXE_SP(sc, wb_comp); 1669 int timeout = CHIP_REV_IS_SLOW(sc) ? 400000 : 4000; 1670 1671 BXE_DMAE_LOCK(sc); 1672 1673 /* reset completion */ 1674 *wb_comp = 0; 1675 1676 /* post the command on the channel used for initializations */ 1677 bxe_post_dmae(sc, dmae, INIT_DMAE_C(sc)); 1678 1679 /* wait for completion */ 1680 DELAY(5); 1681 1682 while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) { 1683 if (!timeout || 1684 (sc->recovery_state != BXE_RECOVERY_DONE && 1685 sc->recovery_state != BXE_RECOVERY_NIC_LOADING)) { 1686 BLOGE(sc, "DMAE timeout!\n"); 1687 BXE_DMAE_UNLOCK(sc); 1688 return (DMAE_TIMEOUT); 1689 } 1690 1691 timeout--; 1692 DELAY(50); 1693 } 1694 1695 if (*wb_comp & DMAE_PCI_ERR_FLAG) { 1696 BLOGE(sc, "DMAE PCI error!\n"); 1697 BXE_DMAE_UNLOCK(sc); 1698 return (DMAE_PCI_ERROR); 1699 } 1700 1701 BXE_DMAE_UNLOCK(sc); 1702 return (0); 1703 } 1704 1705 void 1706 bxe_read_dmae(struct bxe_softc *sc, 1707 uint32_t src_addr, 1708 uint32_t len32) 1709 { 1710 struct dmae_command dmae; 1711 uint32_t *data; 1712 int i, rc; 1713 1714 DBASSERT(sc, (len32 <= 4), ("DMAE read length is %d", len32)); 1715 1716 if (!sc->dmae_ready) { 1717 data = BXE_SP(sc, wb_data[0]); 1718 1719 for (i = 0; i < len32; i++) { 1720 data[i] = (CHIP_IS_E1(sc)) ? 1721 bxe_reg_rd_ind(sc, (src_addr + (i * 4))) : 1722 REG_RD(sc, (src_addr + (i * 4))); 1723 } 1724 1725 return; 1726 } 1727 1728 /* set opcode and fixed command fields */ 1729 bxe_prep_dmae_with_comp(sc, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI); 1730 1731 /* fill in addresses and len */ 1732 dmae.src_addr_lo = (src_addr >> 2); /* GRC addr has dword resolution */ 1733 dmae.src_addr_hi = 0; 1734 dmae.dst_addr_lo = U64_LO(BXE_SP_MAPPING(sc, wb_data)); 1735 dmae.dst_addr_hi = U64_HI(BXE_SP_MAPPING(sc, wb_data)); 1736 dmae.len = len32; 1737 1738 /* issue the command and wait for completion */ 1739 if ((rc = bxe_issue_dmae_with_comp(sc, &dmae)) != 0) { 1740 bxe_panic(sc, ("DMAE failed (%d)\n", rc)); 1741 }; 1742 } 1743 1744 void 1745 bxe_write_dmae(struct bxe_softc *sc, 1746 bus_addr_t dma_addr, 1747 uint32_t dst_addr, 1748 uint32_t len32) 1749 { 1750 struct dmae_command dmae; 1751 int rc; 1752 1753 if (!sc->dmae_ready) { 1754 DBASSERT(sc, (len32 <= 4), ("DMAE not ready and length is %d", len32)); 1755 1756 if (CHIP_IS_E1(sc)) { 1757 ecore_init_ind_wr(sc, dst_addr, BXE_SP(sc, wb_data[0]), len32); 1758 } else { 1759 ecore_init_str_wr(sc, dst_addr, BXE_SP(sc, wb_data[0]), len32); 1760 } 1761 1762 return; 1763 } 1764 1765 /* set opcode and fixed command fields */ 1766 bxe_prep_dmae_with_comp(sc, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC); 1767 1768 /* fill in addresses and len */ 1769 dmae.src_addr_lo = U64_LO(dma_addr); 1770 dmae.src_addr_hi = U64_HI(dma_addr); 1771 dmae.dst_addr_lo = (dst_addr >> 2); /* GRC addr has dword resolution */ 1772 dmae.dst_addr_hi = 0; 1773 dmae.len = len32; 1774 1775 /* issue the command and wait for completion */ 1776 if ((rc = bxe_issue_dmae_with_comp(sc, &dmae)) != 0) { 1777 bxe_panic(sc, ("DMAE failed (%d)\n", rc)); 1778 } 1779 } 1780 1781 void 1782 bxe_write_dmae_phys_len(struct bxe_softc *sc, 1783 bus_addr_t phys_addr, 1784 uint32_t addr, 1785 uint32_t len) 1786 { 1787 int dmae_wr_max = DMAE_LEN32_WR_MAX(sc); 1788 int offset = 0; 1789 1790 while (len > dmae_wr_max) { 1791 bxe_write_dmae(sc, 1792 (phys_addr + offset), /* src DMA address */ 1793 (addr + offset), /* dst GRC address */ 1794 dmae_wr_max); 1795 offset += (dmae_wr_max * 4); 1796 len -= dmae_wr_max; 1797 } 1798 1799 bxe_write_dmae(sc, 1800 (phys_addr + offset), /* src DMA address */ 1801 (addr + offset), /* dst GRC address */ 1802 len); 1803 } 1804 1805 void 1806 bxe_set_ctx_validation(struct bxe_softc *sc, 1807 struct eth_context *cxt, 1808 uint32_t cid) 1809 { 1810 /* ustorm cxt validation */ 1811 cxt->ustorm_ag_context.cdu_usage = 1812 CDU_RSRVD_VALUE_TYPE_A(HW_CID(sc, cid), 1813 CDU_REGION_NUMBER_UCM_AG, ETH_CONNECTION_TYPE); 1814 /* xcontext validation */ 1815 cxt->xstorm_ag_context.cdu_reserved = 1816 CDU_RSRVD_VALUE_TYPE_A(HW_CID(sc, cid), 1817 CDU_REGION_NUMBER_XCM_AG, ETH_CONNECTION_TYPE); 1818 } 1819 1820 static void 1821 bxe_storm_memset_hc_timeout(struct bxe_softc *sc, 1822 uint8_t port, 1823 uint8_t fw_sb_id, 1824 uint8_t sb_index, 1825 uint8_t ticks) 1826 { 1827 uint32_t addr = 1828 (BAR_CSTRORM_INTMEM + 1829 CSTORM_STATUS_BLOCK_DATA_TIMEOUT_OFFSET(fw_sb_id, sb_index)); 1830 1831 REG_WR8(sc, addr, ticks); 1832 1833 BLOGD(sc, DBG_LOAD, 1834 "port %d fw_sb_id %d sb_index %d ticks %d\n", 1835 port, fw_sb_id, sb_index, ticks); 1836 } 1837 1838 static void 1839 bxe_storm_memset_hc_disable(struct bxe_softc *sc, 1840 uint8_t port, 1841 uint16_t fw_sb_id, 1842 uint8_t sb_index, 1843 uint8_t disable) 1844 { 1845 uint32_t enable_flag = 1846 (disable) ? 0 : (1 << HC_INDEX_DATA_HC_ENABLED_SHIFT); 1847 uint32_t addr = 1848 (BAR_CSTRORM_INTMEM + 1849 CSTORM_STATUS_BLOCK_DATA_FLAGS_OFFSET(fw_sb_id, sb_index)); 1850 uint8_t flags; 1851 1852 /* clear and set */ 1853 flags = REG_RD8(sc, addr); 1854 flags &= ~HC_INDEX_DATA_HC_ENABLED; 1855 flags |= enable_flag; 1856 REG_WR8(sc, addr, flags); 1857 1858 BLOGD(sc, DBG_LOAD, 1859 "port %d fw_sb_id %d sb_index %d disable %d\n", 1860 port, fw_sb_id, sb_index, disable); 1861 } 1862 1863 void 1864 bxe_update_coalesce_sb_index(struct bxe_softc *sc, 1865 uint8_t fw_sb_id, 1866 uint8_t sb_index, 1867 uint8_t disable, 1868 uint16_t usec) 1869 { 1870 int port = SC_PORT(sc); 1871 uint8_t ticks = (usec / 4); /* XXX ??? */ 1872 1873 bxe_storm_memset_hc_timeout(sc, port, fw_sb_id, sb_index, ticks); 1874 1875 disable = (disable) ? 1 : ((usec) ? 0 : 1); 1876 bxe_storm_memset_hc_disable(sc, port, fw_sb_id, sb_index, disable); 1877 } 1878 1879 void 1880 elink_cb_udelay(struct bxe_softc *sc, 1881 uint32_t usecs) 1882 { 1883 DELAY(usecs); 1884 } 1885 1886 uint32_t 1887 elink_cb_reg_read(struct bxe_softc *sc, 1888 uint32_t reg_addr) 1889 { 1890 return (REG_RD(sc, reg_addr)); 1891 } 1892 1893 void 1894 elink_cb_reg_write(struct bxe_softc *sc, 1895 uint32_t reg_addr, 1896 uint32_t val) 1897 { 1898 REG_WR(sc, reg_addr, val); 1899 } 1900 1901 void 1902 elink_cb_reg_wb_write(struct bxe_softc *sc, 1903 uint32_t offset, 1904 uint32_t *wb_write, 1905 uint16_t len) 1906 { 1907 REG_WR_DMAE(sc, offset, wb_write, len); 1908 } 1909 1910 void 1911 elink_cb_reg_wb_read(struct bxe_softc *sc, 1912 uint32_t offset, 1913 uint32_t *wb_write, 1914 uint16_t len) 1915 { 1916 REG_RD_DMAE(sc, offset, wb_write, len); 1917 } 1918 1919 uint8_t 1920 elink_cb_path_id(struct bxe_softc *sc) 1921 { 1922 return (SC_PATH(sc)); 1923 } 1924 1925 void 1926 elink_cb_event_log(struct bxe_softc *sc, 1927 const elink_log_id_t elink_log_id, 1928 ...) 1929 { 1930 /* XXX */ 1931 #if 0 1932 //va_list ap; 1933 va_start(ap, elink_log_id); 1934 _XXX_(sc, lm_log_id, ap); 1935 va_end(ap); 1936 #endif 1937 BLOGI(sc, "ELINK EVENT LOG (%d)\n", elink_log_id); 1938 } 1939 1940 static int 1941 bxe_set_spio(struct bxe_softc *sc, 1942 int spio, 1943 uint32_t mode) 1944 { 1945 uint32_t spio_reg; 1946 1947 /* Only 2 SPIOs are configurable */ 1948 if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) { 1949 BLOGE(sc, "Invalid SPIO 0x%x\n", spio); 1950 return (-1); 1951 } 1952 1953 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_SPIO); 1954 1955 /* read SPIO and mask except the float bits */ 1956 spio_reg = (REG_RD(sc, MISC_REG_SPIO) & MISC_SPIO_FLOAT); 1957 1958 switch (mode) { 1959 case MISC_SPIO_OUTPUT_LOW: 1960 BLOGD(sc, DBG_LOAD, "Set SPIO 0x%x -> output low\n", spio); 1961 /* clear FLOAT and set CLR */ 1962 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS); 1963 spio_reg |= (spio << MISC_SPIO_CLR_POS); 1964 break; 1965 1966 case MISC_SPIO_OUTPUT_HIGH: 1967 BLOGD(sc, DBG_LOAD, "Set SPIO 0x%x -> output high\n", spio); 1968 /* clear FLOAT and set SET */ 1969 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS); 1970 spio_reg |= (spio << MISC_SPIO_SET_POS); 1971 break; 1972 1973 case MISC_SPIO_INPUT_HI_Z: 1974 BLOGD(sc, DBG_LOAD, "Set SPIO 0x%x -> input\n", spio); 1975 /* set FLOAT */ 1976 spio_reg |= (spio << MISC_SPIO_FLOAT_POS); 1977 break; 1978 1979 default: 1980 break; 1981 } 1982 1983 REG_WR(sc, MISC_REG_SPIO, spio_reg); 1984 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_SPIO); 1985 1986 return (0); 1987 } 1988 1989 static int 1990 bxe_gpio_read(struct bxe_softc *sc, 1991 int gpio_num, 1992 uint8_t port) 1993 { 1994 /* The GPIO should be swapped if swap register is set and active */ 1995 int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) && 1996 REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port); 1997 int gpio_shift = (gpio_num + 1998 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0)); 1999 uint32_t gpio_mask = (1 << gpio_shift); 2000 uint32_t gpio_reg; 2001 2002 if (gpio_num > MISC_REGISTERS_GPIO_3) { 2003 BLOGE(sc, "Invalid GPIO %d\n", gpio_num); 2004 return (-1); 2005 } 2006 2007 /* read GPIO value */ 2008 gpio_reg = REG_RD(sc, MISC_REG_GPIO); 2009 2010 /* get the requested pin value */ 2011 return ((gpio_reg & gpio_mask) == gpio_mask) ? 1 : 0; 2012 } 2013 2014 static int 2015 bxe_gpio_write(struct bxe_softc *sc, 2016 int gpio_num, 2017 uint32_t mode, 2018 uint8_t port) 2019 { 2020 /* The GPIO should be swapped if swap register is set and active */ 2021 int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) && 2022 REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port); 2023 int gpio_shift = (gpio_num + 2024 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0)); 2025 uint32_t gpio_mask = (1 << gpio_shift); 2026 uint32_t gpio_reg; 2027 2028 if (gpio_num > MISC_REGISTERS_GPIO_3) { 2029 BLOGE(sc, "Invalid GPIO %d\n", gpio_num); 2030 return (-1); 2031 } 2032 2033 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO); 2034 2035 /* read GPIO and mask except the float bits */ 2036 gpio_reg = (REG_RD(sc, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT); 2037 2038 switch (mode) { 2039 case MISC_REGISTERS_GPIO_OUTPUT_LOW: 2040 BLOGD(sc, DBG_PHY, 2041 "Set GPIO %d (shift %d) -> output low\n", 2042 gpio_num, gpio_shift); 2043 /* clear FLOAT and set CLR */ 2044 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); 2045 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS); 2046 break; 2047 2048 case MISC_REGISTERS_GPIO_OUTPUT_HIGH: 2049 BLOGD(sc, DBG_PHY, 2050 "Set GPIO %d (shift %d) -> output high\n", 2051 gpio_num, gpio_shift); 2052 /* clear FLOAT and set SET */ 2053 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); 2054 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS); 2055 break; 2056 2057 case MISC_REGISTERS_GPIO_INPUT_HI_Z: 2058 BLOGD(sc, DBG_PHY, 2059 "Set GPIO %d (shift %d) -> input\n", 2060 gpio_num, gpio_shift); 2061 /* set FLOAT */ 2062 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); 2063 break; 2064 2065 default: 2066 break; 2067 } 2068 2069 REG_WR(sc, MISC_REG_GPIO, gpio_reg); 2070 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO); 2071 2072 return (0); 2073 } 2074 2075 static int 2076 bxe_gpio_mult_write(struct bxe_softc *sc, 2077 uint8_t pins, 2078 uint32_t mode) 2079 { 2080 uint32_t gpio_reg; 2081 2082 /* any port swapping should be handled by caller */ 2083 2084 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO); 2085 2086 /* read GPIO and mask except the float bits */ 2087 gpio_reg = REG_RD(sc, MISC_REG_GPIO); 2088 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS); 2089 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS); 2090 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS); 2091 2092 switch (mode) { 2093 case MISC_REGISTERS_GPIO_OUTPUT_LOW: 2094 BLOGD(sc, DBG_PHY, "Set GPIO 0x%x -> output low\n", pins); 2095 /* set CLR */ 2096 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS); 2097 break; 2098 2099 case MISC_REGISTERS_GPIO_OUTPUT_HIGH: 2100 BLOGD(sc, DBG_PHY, "Set GPIO 0x%x -> output high\n", pins); 2101 /* set SET */ 2102 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS); 2103 break; 2104 2105 case MISC_REGISTERS_GPIO_INPUT_HI_Z: 2106 BLOGD(sc, DBG_PHY, "Set GPIO 0x%x -> input\n", pins); 2107 /* set FLOAT */ 2108 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS); 2109 break; 2110 2111 default: 2112 BLOGE(sc, "Invalid GPIO mode assignment %d\n", mode); 2113 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO); 2114 return (-1); 2115 } 2116 2117 REG_WR(sc, MISC_REG_GPIO, gpio_reg); 2118 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO); 2119 2120 return (0); 2121 } 2122 2123 static int 2124 bxe_gpio_int_write(struct bxe_softc *sc, 2125 int gpio_num, 2126 uint32_t mode, 2127 uint8_t port) 2128 { 2129 /* The GPIO should be swapped if swap register is set and active */ 2130 int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) && 2131 REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port); 2132 int gpio_shift = (gpio_num + 2133 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0)); 2134 uint32_t gpio_mask = (1 << gpio_shift); 2135 uint32_t gpio_reg; 2136 2137 if (gpio_num > MISC_REGISTERS_GPIO_3) { 2138 BLOGE(sc, "Invalid GPIO %d\n", gpio_num); 2139 return (-1); 2140 } 2141 2142 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO); 2143 2144 /* read GPIO int */ 2145 gpio_reg = REG_RD(sc, MISC_REG_GPIO_INT); 2146 2147 switch (mode) { 2148 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR: 2149 BLOGD(sc, DBG_PHY, 2150 "Clear GPIO INT %d (shift %d) -> output low\n", 2151 gpio_num, gpio_shift); 2152 /* clear SET and set CLR */ 2153 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS); 2154 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS); 2155 break; 2156 2157 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET: 2158 BLOGD(sc, DBG_PHY, 2159 "Set GPIO INT %d (shift %d) -> output high\n", 2160 gpio_num, gpio_shift); 2161 /* clear CLR and set SET */ 2162 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS); 2163 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS); 2164 break; 2165 2166 default: 2167 break; 2168 } 2169 2170 REG_WR(sc, MISC_REG_GPIO_INT, gpio_reg); 2171 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO); 2172 2173 return (0); 2174 } 2175 2176 uint32_t 2177 elink_cb_gpio_read(struct bxe_softc *sc, 2178 uint16_t gpio_num, 2179 uint8_t port) 2180 { 2181 return (bxe_gpio_read(sc, gpio_num, port)); 2182 } 2183 2184 uint8_t 2185 elink_cb_gpio_write(struct bxe_softc *sc, 2186 uint16_t gpio_num, 2187 uint8_t mode, /* 0=low 1=high */ 2188 uint8_t port) 2189 { 2190 return (bxe_gpio_write(sc, gpio_num, mode, port)); 2191 } 2192 2193 uint8_t 2194 elink_cb_gpio_mult_write(struct bxe_softc *sc, 2195 uint8_t pins, 2196 uint8_t mode) /* 0=low 1=high */ 2197 { 2198 return (bxe_gpio_mult_write(sc, pins, mode)); 2199 } 2200 2201 uint8_t 2202 elink_cb_gpio_int_write(struct bxe_softc *sc, 2203 uint16_t gpio_num, 2204 uint8_t mode, /* 0=low 1=high */ 2205 uint8_t port) 2206 { 2207 return (bxe_gpio_int_write(sc, gpio_num, mode, port)); 2208 } 2209 2210 void 2211 elink_cb_notify_link_changed(struct bxe_softc *sc) 2212 { 2213 REG_WR(sc, (MISC_REG_AEU_GENERAL_ATTN_12 + 2214 (SC_FUNC(sc) * sizeof(uint32_t))), 1); 2215 } 2216 2217 /* send the MCP a request, block until there is a reply */ 2218 uint32_t 2219 elink_cb_fw_command(struct bxe_softc *sc, 2220 uint32_t command, 2221 uint32_t param) 2222 { 2223 int mb_idx = SC_FW_MB_IDX(sc); 2224 uint32_t seq; 2225 uint32_t rc = 0; 2226 uint32_t cnt = 1; 2227 uint8_t delay = CHIP_REV_IS_SLOW(sc) ? 100 : 10; 2228 2229 BXE_FWMB_LOCK(sc); 2230 2231 seq = ++sc->fw_seq; 2232 SHMEM_WR(sc, func_mb[mb_idx].drv_mb_param, param); 2233 SHMEM_WR(sc, func_mb[mb_idx].drv_mb_header, (command | seq)); 2234 2235 BLOGD(sc, DBG_PHY, 2236 "wrote command 0x%08x to FW MB param 0x%08x\n", 2237 (command | seq), param); 2238 2239 /* Let the FW do it's magic. GIve it up to 5 seconds... */ 2240 do { 2241 DELAY(delay * 1000); 2242 rc = SHMEM_RD(sc, func_mb[mb_idx].fw_mb_header); 2243 } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500)); 2244 2245 BLOGD(sc, DBG_PHY, 2246 "[after %d ms] read 0x%x seq 0x%x from FW MB\n", 2247 cnt*delay, rc, seq); 2248 2249 /* is this a reply to our command? */ 2250 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK)) { 2251 rc &= FW_MSG_CODE_MASK; 2252 } else { 2253 /* Ruh-roh! */ 2254 BLOGE(sc, "FW failed to respond!\n"); 2255 // XXX bxe_fw_dump(sc); 2256 rc = 0; 2257 } 2258 2259 BXE_FWMB_UNLOCK(sc); 2260 return (rc); 2261 } 2262 2263 static uint32_t 2264 bxe_fw_command(struct bxe_softc *sc, 2265 uint32_t command, 2266 uint32_t param) 2267 { 2268 return (elink_cb_fw_command(sc, command, param)); 2269 } 2270 2271 static void 2272 __storm_memset_dma_mapping(struct bxe_softc *sc, 2273 uint32_t addr, 2274 bus_addr_t mapping) 2275 { 2276 REG_WR(sc, addr, U64_LO(mapping)); 2277 REG_WR(sc, (addr + 4), U64_HI(mapping)); 2278 } 2279 2280 static void 2281 storm_memset_spq_addr(struct bxe_softc *sc, 2282 bus_addr_t mapping, 2283 uint16_t abs_fid) 2284 { 2285 uint32_t addr = (XSEM_REG_FAST_MEMORY + 2286 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid)); 2287 __storm_memset_dma_mapping(sc, addr, mapping); 2288 } 2289 2290 static void 2291 storm_memset_vf_to_pf(struct bxe_softc *sc, 2292 uint16_t abs_fid, 2293 uint16_t pf_id) 2294 { 2295 REG_WR8(sc, (BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid)), pf_id); 2296 REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid)), pf_id); 2297 REG_WR8(sc, (BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid)), pf_id); 2298 REG_WR8(sc, (BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid)), pf_id); 2299 } 2300 2301 static void 2302 storm_memset_func_en(struct bxe_softc *sc, 2303 uint16_t abs_fid, 2304 uint8_t enable) 2305 { 2306 REG_WR8(sc, (BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid)), enable); 2307 REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid)), enable); 2308 REG_WR8(sc, (BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid)), enable); 2309 REG_WR8(sc, (BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid)), enable); 2310 } 2311 2312 static void 2313 storm_memset_eq_data(struct bxe_softc *sc, 2314 struct event_ring_data *eq_data, 2315 uint16_t pfid) 2316 { 2317 uint32_t addr; 2318 size_t size; 2319 2320 addr = (BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid)); 2321 size = sizeof(struct event_ring_data); 2322 ecore_storm_memset_struct(sc, addr, size, (uint32_t *)eq_data); 2323 } 2324 2325 static void 2326 storm_memset_eq_prod(struct bxe_softc *sc, 2327 uint16_t eq_prod, 2328 uint16_t pfid) 2329 { 2330 uint32_t addr = (BAR_CSTRORM_INTMEM + 2331 CSTORM_EVENT_RING_PROD_OFFSET(pfid)); 2332 REG_WR16(sc, addr, eq_prod); 2333 } 2334 2335 /* 2336 * Post a slowpath command. 2337 * 2338 * A slowpath command is used to propogate a configuration change through 2339 * the controller in a controlled manner, allowing each STORM processor and 2340 * other H/W blocks to phase in the change. The commands sent on the 2341 * slowpath are referred to as ramrods. Depending on the ramrod used the 2342 * completion of the ramrod will occur in different ways. Here's a 2343 * breakdown of ramrods and how they complete: 2344 * 2345 * RAMROD_CMD_ID_ETH_PORT_SETUP 2346 * Used to setup the leading connection on a port. Completes on the 2347 * Receive Completion Queue (RCQ) of that port (typically fp[0]). 2348 * 2349 * RAMROD_CMD_ID_ETH_CLIENT_SETUP 2350 * Used to setup an additional connection on a port. Completes on the 2351 * RCQ of the multi-queue/RSS connection being initialized. 2352 * 2353 * RAMROD_CMD_ID_ETH_STAT_QUERY 2354 * Used to force the storm processors to update the statistics database 2355 * in host memory. This ramrod is send on the leading connection CID and 2356 * completes as an index increment of the CSTORM on the default status 2357 * block. 2358 * 2359 * RAMROD_CMD_ID_ETH_UPDATE 2360 * Used to update the state of the leading connection, usually to udpate 2361 * the RSS indirection table. Completes on the RCQ of the leading 2362 * connection. (Not currently used under FreeBSD until OS support becomes 2363 * available.) 2364 * 2365 * RAMROD_CMD_ID_ETH_HALT 2366 * Used when tearing down a connection prior to driver unload. Completes 2367 * on the RCQ of the multi-queue/RSS connection being torn down. Don't 2368 * use this on the leading connection. 2369 * 2370 * RAMROD_CMD_ID_ETH_SET_MAC 2371 * Sets the Unicast/Broadcast/Multicast used by the port. Completes on 2372 * the RCQ of the leading connection. 2373 * 2374 * RAMROD_CMD_ID_ETH_CFC_DEL 2375 * Used when tearing down a conneciton prior to driver unload. Completes 2376 * on the RCQ of the leading connection (since the current connection 2377 * has been completely removed from controller memory). 2378 * 2379 * RAMROD_CMD_ID_ETH_PORT_DEL 2380 * Used to tear down the leading connection prior to driver unload, 2381 * typically fp[0]. Completes as an index increment of the CSTORM on the 2382 * default status block. 2383 * 2384 * RAMROD_CMD_ID_ETH_FORWARD_SETUP 2385 * Used for connection offload. Completes on the RCQ of the multi-queue 2386 * RSS connection that is being offloaded. (Not currently used under 2387 * FreeBSD.) 2388 * 2389 * There can only be one command pending per function. 2390 * 2391 * Returns: 2392 * 0 = Success, !0 = Failure. 2393 */ 2394 2395 /* must be called under the spq lock */ 2396 static inline 2397 struct eth_spe *bxe_sp_get_next(struct bxe_softc *sc) 2398 { 2399 struct eth_spe *next_spe = sc->spq_prod_bd; 2400 2401 if (sc->spq_prod_bd == sc->spq_last_bd) { 2402 /* wrap back to the first eth_spq */ 2403 sc->spq_prod_bd = sc->spq; 2404 sc->spq_prod_idx = 0; 2405 } else { 2406 sc->spq_prod_bd++; 2407 sc->spq_prod_idx++; 2408 } 2409 2410 return (next_spe); 2411 } 2412 2413 /* must be called under the spq lock */ 2414 static inline 2415 void bxe_sp_prod_update(struct bxe_softc *sc) 2416 { 2417 int func = SC_FUNC(sc); 2418 2419 /* 2420 * Make sure that BD data is updated before writing the producer. 2421 * BD data is written to the memory, the producer is read from the 2422 * memory, thus we need a full memory barrier to ensure the ordering. 2423 */ 2424 mb(); 2425 2426 REG_WR16(sc, (BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func)), 2427 sc->spq_prod_idx); 2428 2429 bus_space_barrier(sc->bar[BAR0].tag, sc->bar[BAR0].handle, 0, 0, 2430 BUS_SPACE_BARRIER_WRITE); 2431 } 2432 2433 /** 2434 * bxe_is_contextless_ramrod - check if the current command ends on EQ 2435 * 2436 * @cmd: command to check 2437 * @cmd_type: command type 2438 */ 2439 static inline 2440 int bxe_is_contextless_ramrod(int cmd, 2441 int cmd_type) 2442 { 2443 if ((cmd_type == NONE_CONNECTION_TYPE) || 2444 (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) || 2445 (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) || 2446 (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) || 2447 (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) || 2448 (cmd == RAMROD_CMD_ID_ETH_SET_MAC) || 2449 (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE)) { 2450 return (TRUE); 2451 } else { 2452 return (FALSE); 2453 } 2454 } 2455 2456 /** 2457 * bxe_sp_post - place a single command on an SP ring 2458 * 2459 * @sc: driver handle 2460 * @command: command to place (e.g. SETUP, FILTER_RULES, etc.) 2461 * @cid: SW CID the command is related to 2462 * @data_hi: command private data address (high 32 bits) 2463 * @data_lo: command private data address (low 32 bits) 2464 * @cmd_type: command type (e.g. NONE, ETH) 2465 * 2466 * SP data is handled as if it's always an address pair, thus data fields are 2467 * not swapped to little endian in upper functions. Instead this function swaps 2468 * data as if it's two uint32 fields. 2469 */ 2470 int 2471 bxe_sp_post(struct bxe_softc *sc, 2472 int command, 2473 int cid, 2474 uint32_t data_hi, 2475 uint32_t data_lo, 2476 int cmd_type) 2477 { 2478 struct eth_spe *spe; 2479 uint16_t type; 2480 int common; 2481 2482 common = bxe_is_contextless_ramrod(command, cmd_type); 2483 2484 BXE_SP_LOCK(sc); 2485 2486 if (common) { 2487 if (!atomic_load_acq_long(&sc->eq_spq_left)) { 2488 BLOGE(sc, "EQ ring is full!\n"); 2489 BXE_SP_UNLOCK(sc); 2490 return (-1); 2491 } 2492 } else { 2493 if (!atomic_load_acq_long(&sc->cq_spq_left)) { 2494 BLOGE(sc, "SPQ ring is full!\n"); 2495 BXE_SP_UNLOCK(sc); 2496 return (-1); 2497 } 2498 } 2499 2500 spe = bxe_sp_get_next(sc); 2501 2502 /* CID needs port number to be encoded int it */ 2503 spe->hdr.conn_and_cmd_data = 2504 htole32((command << SPE_HDR_CMD_ID_SHIFT) | HW_CID(sc, cid)); 2505 2506 type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE; 2507 2508 /* TBD: Check if it works for VFs */ 2509 type |= ((SC_FUNC(sc) << SPE_HDR_FUNCTION_ID_SHIFT) & 2510 SPE_HDR_FUNCTION_ID); 2511 2512 spe->hdr.type = htole16(type); 2513 2514 spe->data.update_data_addr.hi = htole32(data_hi); 2515 spe->data.update_data_addr.lo = htole32(data_lo); 2516 2517 /* 2518 * It's ok if the actual decrement is issued towards the memory 2519 * somewhere between the lock and unlock. Thus no more explict 2520 * memory barrier is needed. 2521 */ 2522 if (common) { 2523 atomic_subtract_acq_long(&sc->eq_spq_left, 1); 2524 } else { 2525 atomic_subtract_acq_long(&sc->cq_spq_left, 1); 2526 } 2527 2528 BLOGD(sc, DBG_SP, "SPQE -> %#jx\n", (uintmax_t)sc->spq_dma.paddr); 2529 BLOGD(sc, DBG_SP, "FUNC_RDATA -> %p / %#jx\n", 2530 BXE_SP(sc, func_rdata), (uintmax_t)BXE_SP_MAPPING(sc, func_rdata)); 2531 BLOGD(sc, DBG_SP, 2532 "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x data (%x:%x) type(0x%x) left (CQ, EQ) (%lx,%lx)\n", 2533 sc->spq_prod_idx, 2534 (uint32_t)U64_HI(sc->spq_dma.paddr), 2535 (uint32_t)(U64_LO(sc->spq_dma.paddr) + (uint8_t *)sc->spq_prod_bd - (uint8_t *)sc->spq), 2536 command, 2537 common, 2538 HW_CID(sc, cid), 2539 data_hi, 2540 data_lo, 2541 type, 2542 atomic_load_acq_long(&sc->cq_spq_left), 2543 atomic_load_acq_long(&sc->eq_spq_left)); 2544 2545 bxe_sp_prod_update(sc); 2546 2547 BXE_SP_UNLOCK(sc); 2548 return (0); 2549 } 2550 2551 /** 2552 * bxe_debug_print_ind_table - prints the indirection table configuration. 2553 * 2554 * @sc: driver hanlde 2555 * @p: pointer to rss configuration 2556 */ 2557 #if 0 2558 static void 2559 bxe_debug_print_ind_table(struct bxe_softc *sc, 2560 struct ecore_config_rss_params *p) 2561 { 2562 int i; 2563 2564 BLOGD(sc, DBG_LOAD, "Setting indirection table to:\n"); 2565 BLOGD(sc, DBG_LOAD, " 0x0000: "); 2566 for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++) { 2567 BLOGD(sc, DBG_LOAD, "0x%02x ", p->ind_table[i]); 2568 2569 /* Print 4 bytes in a line */ 2570 if ((i + 1 < T_ETH_INDIRECTION_TABLE_SIZE) && 2571 (((i + 1) & 0x3) == 0)) { 2572 BLOGD(sc, DBG_LOAD, "\n"); 2573 BLOGD(sc, DBG_LOAD, "0x%04x: ", i + 1); 2574 } 2575 } 2576 2577 BLOGD(sc, DBG_LOAD, "\n"); 2578 } 2579 #endif 2580 2581 /* 2582 * FreeBSD Device probe function. 2583 * 2584 * Compares the device found to the driver's list of supported devices and 2585 * reports back to the bsd loader whether this is the right driver for the device. 2586 * This is the driver entry function called from the "kldload" command. 2587 * 2588 * Returns: 2589 * BUS_PROBE_DEFAULT on success, positive value on failure. 2590 */ 2591 static int 2592 bxe_probe(device_t dev) 2593 { 2594 struct bxe_softc *sc; 2595 struct bxe_device_type *t; 2596 char *descbuf; 2597 uint16_t did, sdid, svid, vid; 2598 2599 /* Find our device structure */ 2600 sc = device_get_softc(dev); 2601 sc->dev = dev; 2602 t = bxe_devs; 2603 2604 /* Get the data for the device to be probed. */ 2605 vid = pci_get_vendor(dev); 2606 did = pci_get_device(dev); 2607 svid = pci_get_subvendor(dev); 2608 sdid = pci_get_subdevice(dev); 2609 2610 BLOGD(sc, DBG_LOAD, 2611 "%s(); VID = 0x%04X, DID = 0x%04X, SVID = 0x%04X, " 2612 "SDID = 0x%04X\n", __FUNCTION__, vid, did, svid, sdid); 2613 2614 /* Look through the list of known devices for a match. */ 2615 while (t->bxe_name != NULL) { 2616 if ((vid == t->bxe_vid) && (did == t->bxe_did) && 2617 ((svid == t->bxe_svid) || (t->bxe_svid == PCI_ANY_ID)) && 2618 ((sdid == t->bxe_sdid) || (t->bxe_sdid == PCI_ANY_ID))) { 2619 descbuf = malloc(BXE_DEVDESC_MAX, M_TEMP, M_NOWAIT); 2620 if (descbuf == NULL) 2621 return (ENOMEM); 2622 2623 /* Print out the device identity. */ 2624 snprintf(descbuf, BXE_DEVDESC_MAX, 2625 "%s (%c%d) BXE v:%s\n", t->bxe_name, 2626 (((pci_read_config(dev, PCIR_REVID, 4) & 2627 0xf0) >> 4) + 'A'), 2628 (pci_read_config(dev, PCIR_REVID, 4) & 0xf), 2629 BXE_DRIVER_VERSION); 2630 2631 device_set_desc_copy(dev, descbuf); 2632 free(descbuf, M_TEMP); 2633 return (BUS_PROBE_DEFAULT); 2634 } 2635 t++; 2636 } 2637 2638 return (ENXIO); 2639 } 2640 2641 static void 2642 bxe_init_mutexes(struct bxe_softc *sc) 2643 { 2644 #ifdef BXE_CORE_LOCK_SX 2645 snprintf(sc->core_sx_name, sizeof(sc->core_sx_name), 2646 "bxe%d_core_lock", sc->unit); 2647 sx_init(&sc->core_sx, sc->core_sx_name); 2648 #else 2649 snprintf(sc->core_mtx_name, sizeof(sc->core_mtx_name), 2650 "bxe%d_core_lock", sc->unit); 2651 mtx_init(&sc->core_mtx, sc->core_mtx_name, NULL, MTX_DEF); 2652 #endif 2653 2654 snprintf(sc->sp_mtx_name, sizeof(sc->sp_mtx_name), 2655 "bxe%d_sp_lock", sc->unit); 2656 mtx_init(&sc->sp_mtx, sc->sp_mtx_name, NULL, MTX_DEF); 2657 2658 snprintf(sc->dmae_mtx_name, sizeof(sc->dmae_mtx_name), 2659 "bxe%d_dmae_lock", sc->unit); 2660 mtx_init(&sc->dmae_mtx, sc->dmae_mtx_name, NULL, MTX_DEF); 2661 2662 snprintf(sc->port.phy_mtx_name, sizeof(sc->port.phy_mtx_name), 2663 "bxe%d_phy_lock", sc->unit); 2664 mtx_init(&sc->port.phy_mtx, sc->port.phy_mtx_name, NULL, MTX_DEF); 2665 2666 snprintf(sc->fwmb_mtx_name, sizeof(sc->fwmb_mtx_name), 2667 "bxe%d_fwmb_lock", sc->unit); 2668 mtx_init(&sc->fwmb_mtx, sc->fwmb_mtx_name, NULL, MTX_DEF); 2669 2670 snprintf(sc->print_mtx_name, sizeof(sc->print_mtx_name), 2671 "bxe%d_print_lock", sc->unit); 2672 mtx_init(&(sc->print_mtx), sc->print_mtx_name, NULL, MTX_DEF); 2673 2674 snprintf(sc->stats_mtx_name, sizeof(sc->stats_mtx_name), 2675 "bxe%d_stats_lock", sc->unit); 2676 mtx_init(&(sc->stats_mtx), sc->stats_mtx_name, NULL, MTX_DEF); 2677 2678 snprintf(sc->mcast_mtx_name, sizeof(sc->mcast_mtx_name), 2679 "bxe%d_mcast_lock", sc->unit); 2680 mtx_init(&(sc->mcast_mtx), sc->mcast_mtx_name, NULL, MTX_DEF); 2681 } 2682 2683 static void 2684 bxe_release_mutexes(struct bxe_softc *sc) 2685 { 2686 #ifdef BXE_CORE_LOCK_SX 2687 sx_destroy(&sc->core_sx); 2688 #else 2689 if (mtx_initialized(&sc->core_mtx)) { 2690 mtx_destroy(&sc->core_mtx); 2691 } 2692 #endif 2693 2694 if (mtx_initialized(&sc->sp_mtx)) { 2695 mtx_destroy(&sc->sp_mtx); 2696 } 2697 2698 if (mtx_initialized(&sc->dmae_mtx)) { 2699 mtx_destroy(&sc->dmae_mtx); 2700 } 2701 2702 if (mtx_initialized(&sc->port.phy_mtx)) { 2703 mtx_destroy(&sc->port.phy_mtx); 2704 } 2705 2706 if (mtx_initialized(&sc->fwmb_mtx)) { 2707 mtx_destroy(&sc->fwmb_mtx); 2708 } 2709 2710 if (mtx_initialized(&sc->print_mtx)) { 2711 mtx_destroy(&sc->print_mtx); 2712 } 2713 2714 if (mtx_initialized(&sc->stats_mtx)) { 2715 mtx_destroy(&sc->stats_mtx); 2716 } 2717 2718 if (mtx_initialized(&sc->mcast_mtx)) { 2719 mtx_destroy(&sc->mcast_mtx); 2720 } 2721 } 2722 2723 static void 2724 bxe_tx_disable(struct bxe_softc* sc) 2725 { 2726 struct ifnet *ifp = sc->ifnet; 2727 2728 /* tell the stack the driver is stopped and TX queue is full */ 2729 if (ifp != NULL) { 2730 ifp->if_drv_flags = 0; 2731 } 2732 } 2733 2734 static void 2735 bxe_drv_pulse(struct bxe_softc *sc) 2736 { 2737 SHMEM_WR(sc, func_mb[SC_FW_MB_IDX(sc)].drv_pulse_mb, 2738 sc->fw_drv_pulse_wr_seq); 2739 } 2740 2741 static inline uint16_t 2742 bxe_tx_avail(struct bxe_softc *sc, 2743 struct bxe_fastpath *fp) 2744 { 2745 int16_t used; 2746 uint16_t prod; 2747 uint16_t cons; 2748 2749 prod = fp->tx_bd_prod; 2750 cons = fp->tx_bd_cons; 2751 2752 used = SUB_S16(prod, cons); 2753 2754 #if 0 2755 KASSERT((used < 0), ("used tx bds < 0")); 2756 KASSERT((used > sc->tx_ring_size), ("used tx bds > tx_ring_size")); 2757 KASSERT(((sc->tx_ring_size - used) > MAX_TX_AVAIL), 2758 ("invalid number of tx bds used")); 2759 #endif 2760 2761 return (int16_t)(sc->tx_ring_size) - used; 2762 } 2763 2764 static inline int 2765 bxe_tx_queue_has_work(struct bxe_fastpath *fp) 2766 { 2767 uint16_t hw_cons; 2768 2769 mb(); /* status block fields can change */ 2770 hw_cons = le16toh(*fp->tx_cons_sb); 2771 return (hw_cons != fp->tx_pkt_cons); 2772 } 2773 2774 static inline uint8_t 2775 bxe_has_tx_work(struct bxe_fastpath *fp) 2776 { 2777 /* expand this for multi-cos if ever supported */ 2778 return (bxe_tx_queue_has_work(fp)) ? TRUE : FALSE; 2779 } 2780 2781 static inline int 2782 bxe_has_rx_work(struct bxe_fastpath *fp) 2783 { 2784 uint16_t rx_cq_cons_sb; 2785 2786 mb(); /* status block fields can change */ 2787 rx_cq_cons_sb = le16toh(*fp->rx_cq_cons_sb); 2788 if ((rx_cq_cons_sb & RCQ_MAX) == RCQ_MAX) 2789 rx_cq_cons_sb++; 2790 return (fp->rx_cq_cons != rx_cq_cons_sb); 2791 } 2792 2793 static void 2794 bxe_sp_event(struct bxe_softc *sc, 2795 struct bxe_fastpath *fp, 2796 union eth_rx_cqe *rr_cqe) 2797 { 2798 int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data); 2799 int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data); 2800 enum ecore_queue_cmd drv_cmd = ECORE_Q_CMD_MAX; 2801 struct ecore_queue_sp_obj *q_obj = &BXE_SP_OBJ(sc, fp).q_obj; 2802 2803 BLOGD(sc, DBG_SP, "fp=%d cid=%d got ramrod #%d state is %x type is %d\n", 2804 fp->index, cid, command, sc->state, rr_cqe->ramrod_cqe.ramrod_type); 2805 2806 #if 0 2807 /* 2808 * If cid is within VF range, replace the slowpath object with the 2809 * one corresponding to this VF 2810 */ 2811 if ((cid >= BXE_FIRST_VF_CID) && (cid < BXE_FIRST_VF_CID + BXE_VF_CIDS)) { 2812 bxe_iov_set_queue_sp_obj(sc, cid, &q_obj); 2813 } 2814 #endif 2815 2816 switch (command) { 2817 case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE): 2818 BLOGD(sc, DBG_SP, "got UPDATE ramrod. CID %d\n", cid); 2819 drv_cmd = ECORE_Q_CMD_UPDATE; 2820 break; 2821 2822 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP): 2823 BLOGD(sc, DBG_SP, "got MULTI[%d] setup ramrod\n", cid); 2824 drv_cmd = ECORE_Q_CMD_SETUP; 2825 break; 2826 2827 case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP): 2828 BLOGD(sc, DBG_SP, "got MULTI[%d] tx-only setup ramrod\n", cid); 2829 drv_cmd = ECORE_Q_CMD_SETUP_TX_ONLY; 2830 break; 2831 2832 case (RAMROD_CMD_ID_ETH_HALT): 2833 BLOGD(sc, DBG_SP, "got MULTI[%d] halt ramrod\n", cid); 2834 drv_cmd = ECORE_Q_CMD_HALT; 2835 break; 2836 2837 case (RAMROD_CMD_ID_ETH_TERMINATE): 2838 BLOGD(sc, DBG_SP, "got MULTI[%d] teminate ramrod\n", cid); 2839 drv_cmd = ECORE_Q_CMD_TERMINATE; 2840 break; 2841 2842 case (RAMROD_CMD_ID_ETH_EMPTY): 2843 BLOGD(sc, DBG_SP, "got MULTI[%d] empty ramrod\n", cid); 2844 drv_cmd = ECORE_Q_CMD_EMPTY; 2845 break; 2846 2847 default: 2848 BLOGD(sc, DBG_SP, "ERROR: unexpected MC reply (%d) on fp[%d]\n", 2849 command, fp->index); 2850 return; 2851 } 2852 2853 if ((drv_cmd != ECORE_Q_CMD_MAX) && 2854 q_obj->complete_cmd(sc, q_obj, drv_cmd)) { 2855 /* 2856 * q_obj->complete_cmd() failure means that this was 2857 * an unexpected completion. 2858 * 2859 * In this case we don't want to increase the sc->spq_left 2860 * because apparently we haven't sent this command the first 2861 * place. 2862 */ 2863 // bxe_panic(sc, ("Unexpected SP completion\n")); 2864 return; 2865 } 2866 2867 #if 0 2868 /* SRIOV: reschedule any 'in_progress' operations */ 2869 bxe_iov_sp_event(sc, cid, TRUE); 2870 #endif 2871 2872 atomic_add_acq_long(&sc->cq_spq_left, 1); 2873 2874 BLOGD(sc, DBG_SP, "sc->cq_spq_left 0x%lx\n", 2875 atomic_load_acq_long(&sc->cq_spq_left)); 2876 2877 #if 0 2878 if ((drv_cmd == ECORE_Q_CMD_UPDATE) && (IS_FCOE_FP(fp)) && 2879 (!!bxe_test_bit(ECORE_AFEX_FCOE_Q_UPDATE_PENDING, &sc->sp_state))) { 2880 /* 2881 * If Queue update ramrod is completed for last Queue in AFEX VIF set 2882 * flow, then ACK MCP at the end. Mark pending ACK to MCP bit to 2883 * prevent case that both bits are cleared. At the end of load/unload 2884 * driver checks that sp_state is cleared and this order prevents 2885 * races. 2886 */ 2887 bxe_set_bit(ECORE_AFEX_PENDING_VIFSET_MCP_ACK, &sc->sp_state); 2888 wmb(); 2889 bxe_clear_bit(ECORE_AFEX_FCOE_Q_UPDATE_PENDING, &sc->sp_state); 2890 2891 /* schedule the sp task as MCP ack is required */ 2892 bxe_schedule_sp_task(sc); 2893 } 2894 #endif 2895 } 2896 2897 /* 2898 * The current mbuf is part of an aggregation. Move the mbuf into the TPA 2899 * aggregation queue, put an empty mbuf back onto the receive chain, and mark 2900 * the current aggregation queue as in-progress. 2901 */ 2902 static void 2903 bxe_tpa_start(struct bxe_softc *sc, 2904 struct bxe_fastpath *fp, 2905 uint16_t queue, 2906 uint16_t cons, 2907 uint16_t prod, 2908 struct eth_fast_path_rx_cqe *cqe) 2909 { 2910 struct bxe_sw_rx_bd tmp_bd; 2911 struct bxe_sw_rx_bd *rx_buf; 2912 struct eth_rx_bd *rx_bd; 2913 int max_agg_queues; 2914 struct bxe_sw_tpa_info *tpa_info = &fp->rx_tpa_info[queue]; 2915 uint16_t index; 2916 2917 BLOGD(sc, DBG_LRO, "fp[%02d].tpa[%02d] TPA START " 2918 "cons=%d prod=%d\n", 2919 fp->index, queue, cons, prod); 2920 2921 max_agg_queues = MAX_AGG_QS(sc); 2922 2923 KASSERT((queue < max_agg_queues), 2924 ("fp[%02d] invalid aggr queue (%d >= %d)!", 2925 fp->index, queue, max_agg_queues)); 2926 2927 KASSERT((tpa_info->state == BXE_TPA_STATE_STOP), 2928 ("fp[%02d].tpa[%02d] starting aggr on queue not stopped!", 2929 fp->index, queue)); 2930 2931 /* copy the existing mbuf and mapping from the TPA pool */ 2932 tmp_bd = tpa_info->bd; 2933 2934 if (tmp_bd.m == NULL) { 2935 BLOGE(sc, "fp[%02d].tpa[%02d] mbuf not allocated!\n", 2936 fp->index, queue); 2937 /* XXX Error handling? */ 2938 return; 2939 } 2940 2941 /* change the TPA queue to the start state */ 2942 tpa_info->state = BXE_TPA_STATE_START; 2943 tpa_info->placement_offset = cqe->placement_offset; 2944 tpa_info->parsing_flags = le16toh(cqe->pars_flags.flags); 2945 tpa_info->vlan_tag = le16toh(cqe->vlan_tag); 2946 tpa_info->len_on_bd = le16toh(cqe->len_on_bd); 2947 2948 fp->rx_tpa_queue_used |= (1 << queue); 2949 2950 /* 2951 * If all the buffer descriptors are filled with mbufs then fill in 2952 * the current consumer index with a new BD. Else if a maximum Rx 2953 * buffer limit is imposed then fill in the next producer index. 2954 */ 2955 index = (sc->max_rx_bufs != RX_BD_USABLE) ? 2956 prod : cons; 2957 2958 /* move the received mbuf and mapping to TPA pool */ 2959 tpa_info->bd = fp->rx_mbuf_chain[cons]; 2960 2961 /* release any existing RX BD mbuf mappings */ 2962 if (cons != index) { 2963 rx_buf = &fp->rx_mbuf_chain[cons]; 2964 2965 if (rx_buf->m_map != NULL) { 2966 bus_dmamap_sync(fp->rx_mbuf_tag, rx_buf->m_map, 2967 BUS_DMASYNC_POSTREAD); 2968 bus_dmamap_unload(fp->rx_mbuf_tag, rx_buf->m_map); 2969 } 2970 2971 /* 2972 * We get here when the maximum number of rx buffers is less than 2973 * RX_BD_USABLE. The mbuf is already saved above so it's OK to NULL 2974 * it out here without concern of a memory leak. 2975 */ 2976 fp->rx_mbuf_chain[cons].m = NULL; 2977 } 2978 2979 /* update the Rx SW BD with the mbuf info from the TPA pool */ 2980 fp->rx_mbuf_chain[index] = tmp_bd; 2981 2982 /* update the Rx BD with the empty mbuf phys address from the TPA pool */ 2983 rx_bd = &fp->rx_chain[index]; 2984 rx_bd->addr_hi = htole32(U64_HI(tpa_info->seg.ds_addr)); 2985 rx_bd->addr_lo = htole32(U64_LO(tpa_info->seg.ds_addr)); 2986 } 2987 2988 /* 2989 * When a TPA aggregation is completed, loop through the individual mbufs 2990 * of the aggregation, combining them into a single mbuf which will be sent 2991 * up the stack. Refill all freed SGEs with mbufs as we go along. 2992 */ 2993 static int 2994 bxe_fill_frag_mbuf(struct bxe_softc *sc, 2995 struct bxe_fastpath *fp, 2996 struct bxe_sw_tpa_info *tpa_info, 2997 uint16_t queue, 2998 uint16_t pages, 2999 struct mbuf *m, 3000 struct eth_end_agg_rx_cqe *cqe, 3001 uint16_t cqe_idx) 3002 { 3003 struct mbuf *m_frag; 3004 uint32_t frag_len, frag_size, i; 3005 uint16_t sge_idx; 3006 int rc = 0; 3007 int j; 3008 3009 frag_size = le16toh(cqe->pkt_len) - tpa_info->len_on_bd; 3010 3011 BLOGD(sc, DBG_LRO, 3012 "fp[%02d].tpa[%02d] TPA fill len_on_bd=%d frag_size=%d pages=%d\n", 3013 fp->index, queue, tpa_info->len_on_bd, frag_size, pages); 3014 3015 /* make sure the aggregated frame is not too big to handle */ 3016 if (pages > 8 * PAGES_PER_SGE) { 3017 BLOGE(sc, "fp[%02d].sge[0x%04x] has too many pages (%d)! " 3018 "pkt_len=%d len_on_bd=%d frag_size=%d\n", 3019 fp->index, cqe_idx, pages, le16toh(cqe->pkt_len), 3020 tpa_info->len_on_bd, frag_size); 3021 bxe_panic(sc, ("sge page count error\n")); 3022 return (EINVAL); 3023 } 3024 3025 /* 3026 * Scan through the scatter gather list pulling individual mbufs into a 3027 * single mbuf for the host stack. 3028 */ 3029 for (i = 0, j = 0; i < pages; i += PAGES_PER_SGE, j++) { 3030 sge_idx = RX_SGE(le16toh(cqe->sgl_or_raw_data.sgl[j])); 3031 3032 /* 3033 * Firmware gives the indices of the SGE as if the ring is an array 3034 * (meaning that the "next" element will consume 2 indices). 3035 */ 3036 frag_len = min(frag_size, (uint32_t)(SGE_PAGES)); 3037 3038 BLOGD(sc, DBG_LRO, "fp[%02d].tpa[%02d] TPA fill i=%d j=%d " 3039 "sge_idx=%d frag_size=%d frag_len=%d\n", 3040 fp->index, queue, i, j, sge_idx, frag_size, frag_len); 3041 3042 m_frag = fp->rx_sge_mbuf_chain[sge_idx].m; 3043 3044 /* allocate a new mbuf for the SGE */ 3045 rc = bxe_alloc_rx_sge_mbuf(fp, sge_idx); 3046 if (rc) { 3047 /* Leave all remaining SGEs in the ring! */ 3048 return (rc); 3049 } 3050 3051 /* update the fragment length */ 3052 m_frag->m_len = frag_len; 3053 3054 /* concatenate the fragment to the head mbuf */ 3055 m_cat(m, m_frag); 3056 fp->eth_q_stats.mbuf_alloc_sge--; 3057 3058 /* update the TPA mbuf size and remaining fragment size */ 3059 m->m_pkthdr.len += frag_len; 3060 frag_size -= frag_len; 3061 } 3062 3063 BLOGD(sc, DBG_LRO, 3064 "fp[%02d].tpa[%02d] TPA fill done frag_size=%d\n", 3065 fp->index, queue, frag_size); 3066 3067 return (rc); 3068 } 3069 3070 static inline void 3071 bxe_clear_sge_mask_next_elems(struct bxe_fastpath *fp) 3072 { 3073 int i, j; 3074 3075 for (i = 1; i <= RX_SGE_NUM_PAGES; i++) { 3076 int idx = RX_SGE_TOTAL_PER_PAGE * i - 1; 3077 3078 for (j = 0; j < 2; j++) { 3079 BIT_VEC64_CLEAR_BIT(fp->sge_mask, idx); 3080 idx--; 3081 } 3082 } 3083 } 3084 3085 static inline void 3086 bxe_init_sge_ring_bit_mask(struct bxe_fastpath *fp) 3087 { 3088 /* set the mask to all 1's, it's faster to compare to 0 than to 0xf's */ 3089 memset(fp->sge_mask, 0xff, sizeof(fp->sge_mask)); 3090 3091 /* 3092 * Clear the two last indices in the page to 1. These are the indices that 3093 * correspond to the "next" element, hence will never be indicated and 3094 * should be removed from the calculations. 3095 */ 3096 bxe_clear_sge_mask_next_elems(fp); 3097 } 3098 3099 static inline void 3100 bxe_update_last_max_sge(struct bxe_fastpath *fp, 3101 uint16_t idx) 3102 { 3103 uint16_t last_max = fp->last_max_sge; 3104 3105 if (SUB_S16(idx, last_max) > 0) { 3106 fp->last_max_sge = idx; 3107 } 3108 } 3109 3110 static inline void 3111 bxe_update_sge_prod(struct bxe_softc *sc, 3112 struct bxe_fastpath *fp, 3113 uint16_t sge_len, 3114 struct eth_end_agg_rx_cqe *cqe) 3115 { 3116 uint16_t last_max, last_elem, first_elem; 3117 uint16_t delta = 0; 3118 uint16_t i; 3119 3120 if (!sge_len) { 3121 return; 3122 } 3123 3124 /* first mark all used pages */ 3125 for (i = 0; i < sge_len; i++) { 3126 BIT_VEC64_CLEAR_BIT(fp->sge_mask, 3127 RX_SGE(le16toh(cqe->sgl_or_raw_data.sgl[i]))); 3128 } 3129 3130 BLOGD(sc, DBG_LRO, 3131 "fp[%02d] fp_cqe->sgl[%d] = %d\n", 3132 fp->index, sge_len - 1, 3133 le16toh(cqe->sgl_or_raw_data.sgl[sge_len - 1])); 3134 3135 /* assume that the last SGE index is the biggest */ 3136 bxe_update_last_max_sge(fp, 3137 le16toh(cqe->sgl_or_raw_data.sgl[sge_len - 1])); 3138 3139 last_max = RX_SGE(fp->last_max_sge); 3140 last_elem = last_max >> BIT_VEC64_ELEM_SHIFT; 3141 first_elem = RX_SGE(fp->rx_sge_prod) >> BIT_VEC64_ELEM_SHIFT; 3142 3143 /* if ring is not full */ 3144 if (last_elem + 1 != first_elem) { 3145 last_elem++; 3146 } 3147 3148 /* now update the prod */ 3149 for (i = first_elem; i != last_elem; i = RX_SGE_NEXT_MASK_ELEM(i)) { 3150 if (__predict_true(fp->sge_mask[i])) { 3151 break; 3152 } 3153 3154 fp->sge_mask[i] = BIT_VEC64_ELEM_ONE_MASK; 3155 delta += BIT_VEC64_ELEM_SZ; 3156 } 3157 3158 if (delta > 0) { 3159 fp->rx_sge_prod += delta; 3160 /* clear page-end entries */ 3161 bxe_clear_sge_mask_next_elems(fp); 3162 } 3163 3164 BLOGD(sc, DBG_LRO, 3165 "fp[%02d] fp->last_max_sge=%d fp->rx_sge_prod=%d\n", 3166 fp->index, fp->last_max_sge, fp->rx_sge_prod); 3167 } 3168 3169 /* 3170 * The aggregation on the current TPA queue has completed. Pull the individual 3171 * mbuf fragments together into a single mbuf, perform all necessary checksum 3172 * calculations, and send the resuting mbuf to the stack. 3173 */ 3174 static void 3175 bxe_tpa_stop(struct bxe_softc *sc, 3176 struct bxe_fastpath *fp, 3177 struct bxe_sw_tpa_info *tpa_info, 3178 uint16_t queue, 3179 uint16_t pages, 3180 struct eth_end_agg_rx_cqe *cqe, 3181 uint16_t cqe_idx) 3182 { 3183 struct ifnet *ifp = sc->ifnet; 3184 struct mbuf *m; 3185 int rc = 0; 3186 3187 BLOGD(sc, DBG_LRO, 3188 "fp[%02d].tpa[%02d] pad=%d pkt_len=%d pages=%d vlan=%d\n", 3189 fp->index, queue, tpa_info->placement_offset, 3190 le16toh(cqe->pkt_len), pages, tpa_info->vlan_tag); 3191 3192 m = tpa_info->bd.m; 3193 3194 /* allocate a replacement before modifying existing mbuf */ 3195 rc = bxe_alloc_rx_tpa_mbuf(fp, queue); 3196 if (rc) { 3197 /* drop the frame and log an error */ 3198 fp->eth_q_stats.rx_soft_errors++; 3199 goto bxe_tpa_stop_exit; 3200 } 3201 3202 /* we have a replacement, fixup the current mbuf */ 3203 m_adj(m, tpa_info->placement_offset); 3204 m->m_pkthdr.len = m->m_len = tpa_info->len_on_bd; 3205 3206 /* mark the checksums valid (taken care of by the firmware) */ 3207 fp->eth_q_stats.rx_ofld_frames_csum_ip++; 3208 fp->eth_q_stats.rx_ofld_frames_csum_tcp_udp++; 3209 m->m_pkthdr.csum_data = 0xffff; 3210 m->m_pkthdr.csum_flags |= (CSUM_IP_CHECKED | 3211 CSUM_IP_VALID | 3212 CSUM_DATA_VALID | 3213 CSUM_PSEUDO_HDR); 3214 3215 /* aggregate all of the SGEs into a single mbuf */ 3216 rc = bxe_fill_frag_mbuf(sc, fp, tpa_info, queue, pages, m, cqe, cqe_idx); 3217 if (rc) { 3218 /* drop the packet and log an error */ 3219 fp->eth_q_stats.rx_soft_errors++; 3220 m_freem(m); 3221 } else { 3222 if (tpa_info->parsing_flags & PARSING_FLAGS_VLAN) { 3223 m->m_pkthdr.ether_vtag = tpa_info->vlan_tag; 3224 m->m_flags |= M_VLANTAG; 3225 } 3226 3227 /* assign packet to this interface interface */ 3228 m->m_pkthdr.rcvif = ifp; 3229 3230 #if __FreeBSD_version >= 800000 3231 /* specify what RSS queue was used for this flow */ 3232 m->m_pkthdr.flowid = fp->index; 3233 m->m_flags |= M_FLOWID; 3234 #endif 3235 3236 ifp->if_ipackets++; 3237 fp->eth_q_stats.rx_tpa_pkts++; 3238 3239 /* pass the frame to the stack */ 3240 (*ifp->if_input)(ifp, m); 3241 } 3242 3243 /* we passed an mbuf up the stack or dropped the frame */ 3244 fp->eth_q_stats.mbuf_alloc_tpa--; 3245 3246 bxe_tpa_stop_exit: 3247 3248 fp->rx_tpa_info[queue].state = BXE_TPA_STATE_STOP; 3249 fp->rx_tpa_queue_used &= ~(1 << queue); 3250 } 3251 3252 static uint8_t 3253 bxe_rxeof(struct bxe_softc *sc, 3254 struct bxe_fastpath *fp) 3255 { 3256 struct ifnet *ifp = sc->ifnet; 3257 uint16_t bd_cons, bd_prod, bd_prod_fw, comp_ring_cons; 3258 uint16_t hw_cq_cons, sw_cq_cons, sw_cq_prod; 3259 int rx_pkts = 0; 3260 int rc; 3261 3262 BXE_FP_RX_LOCK(fp); 3263 3264 /* CQ "next element" is of the size of the regular element */ 3265 hw_cq_cons = le16toh(*fp->rx_cq_cons_sb); 3266 if ((hw_cq_cons & RCQ_USABLE_PER_PAGE) == RCQ_USABLE_PER_PAGE) { 3267 hw_cq_cons++; 3268 } 3269 3270 bd_cons = fp->rx_bd_cons; 3271 bd_prod = fp->rx_bd_prod; 3272 bd_prod_fw = bd_prod; 3273 sw_cq_cons = fp->rx_cq_cons; 3274 sw_cq_prod = fp->rx_cq_prod; 3275 3276 /* 3277 * Memory barrier necessary as speculative reads of the rx 3278 * buffer can be ahead of the index in the status block 3279 */ 3280 rmb(); 3281 3282 BLOGD(sc, DBG_RX, 3283 "fp[%02d] Rx START hw_cq_cons=%u sw_cq_cons=%u\n", 3284 fp->index, hw_cq_cons, sw_cq_cons); 3285 3286 while (sw_cq_cons != hw_cq_cons) { 3287 struct bxe_sw_rx_bd *rx_buf = NULL; 3288 union eth_rx_cqe *cqe; 3289 struct eth_fast_path_rx_cqe *cqe_fp; 3290 uint8_t cqe_fp_flags; 3291 enum eth_rx_cqe_type cqe_fp_type; 3292 uint16_t len, pad; 3293 struct mbuf *m = NULL; 3294 3295 comp_ring_cons = RCQ(sw_cq_cons); 3296 bd_prod = RX_BD(bd_prod); 3297 bd_cons = RX_BD(bd_cons); 3298 3299 cqe = &fp->rcq_chain[comp_ring_cons]; 3300 cqe_fp = &cqe->fast_path_cqe; 3301 cqe_fp_flags = cqe_fp->type_error_flags; 3302 cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE; 3303 3304 BLOGD(sc, DBG_RX, 3305 "fp[%02d] Rx hw_cq_cons=%d hw_sw_cons=%d " 3306 "BD prod=%d cons=%d CQE type=0x%x err=0x%x " 3307 "status=0x%x rss_hash=0x%x vlan=0x%x len=%u\n", 3308 fp->index, 3309 hw_cq_cons, 3310 sw_cq_cons, 3311 bd_prod, 3312 bd_cons, 3313 CQE_TYPE(cqe_fp_flags), 3314 cqe_fp_flags, 3315 cqe_fp->status_flags, 3316 le32toh(cqe_fp->rss_hash_result), 3317 le16toh(cqe_fp->vlan_tag), 3318 le16toh(cqe_fp->pkt_len_or_gro_seg_len)); 3319 3320 /* is this a slowpath msg? */ 3321 if (__predict_false(CQE_TYPE_SLOW(cqe_fp_type))) { 3322 bxe_sp_event(sc, fp, cqe); 3323 goto next_cqe; 3324 } 3325 3326 rx_buf = &fp->rx_mbuf_chain[bd_cons]; 3327 3328 if (!CQE_TYPE_FAST(cqe_fp_type)) { 3329 struct bxe_sw_tpa_info *tpa_info; 3330 uint16_t frag_size, pages; 3331 uint8_t queue; 3332 3333 #if 0 3334 /* sanity check */ 3335 if (!fp->tpa_enable && 3336 (CQE_TYPE_START(cqe_fp_type) || CQE_TYPE_STOP(cqe_fp_type))) { 3337 BLOGE(sc, "START/STOP packet while !tpa_enable type (0x%x)\n", 3338 CQE_TYPE(cqe_fp_type)); 3339 } 3340 #endif 3341 3342 if (CQE_TYPE_START(cqe_fp_type)) { 3343 bxe_tpa_start(sc, fp, cqe_fp->queue_index, 3344 bd_cons, bd_prod, cqe_fp); 3345 m = NULL; /* packet not ready yet */ 3346 goto next_rx; 3347 } 3348 3349 KASSERT(CQE_TYPE_STOP(cqe_fp_type), 3350 ("CQE type is not STOP! (0x%x)\n", cqe_fp_type)); 3351 3352 queue = cqe->end_agg_cqe.queue_index; 3353 tpa_info = &fp->rx_tpa_info[queue]; 3354 3355 BLOGD(sc, DBG_LRO, "fp[%02d].tpa[%02d] TPA STOP\n", 3356 fp->index, queue); 3357 3358 frag_size = (le16toh(cqe->end_agg_cqe.pkt_len) - 3359 tpa_info->len_on_bd); 3360 pages = SGE_PAGE_ALIGN(frag_size) >> SGE_PAGE_SHIFT; 3361 3362 bxe_tpa_stop(sc, fp, tpa_info, queue, pages, 3363 &cqe->end_agg_cqe, comp_ring_cons); 3364 3365 bxe_update_sge_prod(sc, fp, pages, &cqe->end_agg_cqe); 3366 3367 goto next_cqe; 3368 } 3369 3370 /* non TPA */ 3371 3372 /* is this an error packet? */ 3373 if (__predict_false(cqe_fp_flags & 3374 ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG)) { 3375 BLOGE(sc, "flags 0x%x rx packet %u\n", cqe_fp_flags, sw_cq_cons); 3376 fp->eth_q_stats.rx_soft_errors++; 3377 goto next_rx; 3378 } 3379 3380 len = le16toh(cqe_fp->pkt_len_or_gro_seg_len); 3381 pad = cqe_fp->placement_offset; 3382 3383 m = rx_buf->m; 3384 3385 if (__predict_false(m == NULL)) { 3386 BLOGE(sc, "No mbuf in rx chain descriptor %d for fp[%02d]\n", 3387 bd_cons, fp->index); 3388 goto next_rx; 3389 } 3390 3391 /* XXX double copy if packet length under a threshold */ 3392 3393 /* 3394 * If all the buffer descriptors are filled with mbufs then fill in 3395 * the current consumer index with a new BD. Else if a maximum Rx 3396 * buffer limit is imposed then fill in the next producer index. 3397 */ 3398 rc = bxe_alloc_rx_bd_mbuf(fp, bd_cons, 3399 (sc->max_rx_bufs != RX_BD_USABLE) ? 3400 bd_prod : bd_cons); 3401 if (rc != 0) { 3402 BLOGE(sc, "mbuf alloc fail for fp[%02d] rx chain (%d)\n", 3403 fp->index, rc); 3404 fp->eth_q_stats.rx_soft_errors++; 3405 3406 if (sc->max_rx_bufs != RX_BD_USABLE) { 3407 /* copy this consumer index to the producer index */ 3408 memcpy(&fp->rx_mbuf_chain[bd_prod], rx_buf, 3409 sizeof(struct bxe_sw_rx_bd)); 3410 memset(rx_buf, 0, sizeof(struct bxe_sw_rx_bd)); 3411 } 3412 3413 goto next_rx; 3414 } 3415 3416 /* current mbuf was detached from the bd */ 3417 fp->eth_q_stats.mbuf_alloc_rx--; 3418 3419 /* we allocated a replacement mbuf, fixup the current one */ 3420 m_adj(m, pad); 3421 m->m_pkthdr.len = m->m_len = len; 3422 3423 /* assign packet to this interface interface */ 3424 m->m_pkthdr.rcvif = ifp; 3425 3426 /* assume no hardware checksum has complated */ 3427 m->m_pkthdr.csum_flags = 0; 3428 3429 /* validate checksum if offload enabled */ 3430 if (ifp->if_capenable & IFCAP_RXCSUM) { 3431 /* check for a valid IP frame */ 3432 if (!(cqe->fast_path_cqe.status_flags & 3433 ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG)) { 3434 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 3435 if (__predict_false(cqe_fp_flags & 3436 ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG)) { 3437 fp->eth_q_stats.rx_hw_csum_errors++; 3438 } else { 3439 fp->eth_q_stats.rx_ofld_frames_csum_ip++; 3440 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 3441 } 3442 } 3443 3444 /* check for a valid TCP/UDP frame */ 3445 if (!(cqe->fast_path_cqe.status_flags & 3446 ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG)) { 3447 if (__predict_false(cqe_fp_flags & 3448 ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG)) { 3449 fp->eth_q_stats.rx_hw_csum_errors++; 3450 } else { 3451 fp->eth_q_stats.rx_ofld_frames_csum_tcp_udp++; 3452 m->m_pkthdr.csum_data = 0xFFFF; 3453 m->m_pkthdr.csum_flags |= (CSUM_DATA_VALID | 3454 CSUM_PSEUDO_HDR); 3455 } 3456 } 3457 } 3458 3459 /* if there is a VLAN tag then flag that info */ 3460 if (cqe->fast_path_cqe.pars_flags.flags & PARSING_FLAGS_VLAN) { 3461 m->m_pkthdr.ether_vtag = cqe->fast_path_cqe.vlan_tag; 3462 m->m_flags |= M_VLANTAG; 3463 } 3464 3465 #if __FreeBSD_version >= 800000 3466 /* specify what RSS queue was used for this flow */ 3467 m->m_pkthdr.flowid = fp->index; 3468 m->m_flags |= M_FLOWID; 3469 #endif 3470 3471 next_rx: 3472 3473 bd_cons = RX_BD_NEXT(bd_cons); 3474 bd_prod = RX_BD_NEXT(bd_prod); 3475 bd_prod_fw = RX_BD_NEXT(bd_prod_fw); 3476 3477 /* pass the frame to the stack */ 3478 if (__predict_true(m != NULL)) { 3479 ifp->if_ipackets++; 3480 rx_pkts++; 3481 (*ifp->if_input)(ifp, m); 3482 } 3483 3484 next_cqe: 3485 3486 sw_cq_prod = RCQ_NEXT(sw_cq_prod); 3487 sw_cq_cons = RCQ_NEXT(sw_cq_cons); 3488 3489 /* limit spinning on the queue */ 3490 if (rx_pkts == sc->rx_budget) { 3491 fp->eth_q_stats.rx_budget_reached++; 3492 break; 3493 } 3494 } /* while work to do */ 3495 3496 fp->rx_bd_cons = bd_cons; 3497 fp->rx_bd_prod = bd_prod_fw; 3498 fp->rx_cq_cons = sw_cq_cons; 3499 fp->rx_cq_prod = sw_cq_prod; 3500 3501 /* Update producers */ 3502 bxe_update_rx_prod(sc, fp, bd_prod_fw, sw_cq_prod, fp->rx_sge_prod); 3503 3504 fp->eth_q_stats.rx_pkts += rx_pkts; 3505 fp->eth_q_stats.rx_calls++; 3506 3507 BXE_FP_RX_UNLOCK(fp); 3508 3509 return (sw_cq_cons != hw_cq_cons); 3510 } 3511 3512 static uint16_t 3513 bxe_free_tx_pkt(struct bxe_softc *sc, 3514 struct bxe_fastpath *fp, 3515 uint16_t idx) 3516 { 3517 struct bxe_sw_tx_bd *tx_buf = &fp->tx_mbuf_chain[idx]; 3518 struct eth_tx_start_bd *tx_start_bd; 3519 uint16_t bd_idx = TX_BD(tx_buf->first_bd); 3520 uint16_t new_cons; 3521 int nbd; 3522 3523 /* unmap the mbuf from non-paged memory */ 3524 bus_dmamap_unload(fp->tx_mbuf_tag, tx_buf->m_map); 3525 3526 tx_start_bd = &fp->tx_chain[bd_idx].start_bd; 3527 nbd = le16toh(tx_start_bd->nbd) - 1; 3528 3529 #if 0 3530 if ((nbd - 1) > (MAX_MBUF_FRAGS + 2)) { 3531 bxe_panic(sc, ("BAD nbd!\n")); 3532 } 3533 #endif 3534 3535 new_cons = (tx_buf->first_bd + nbd); 3536 3537 #if 0 3538 struct eth_tx_bd *tx_data_bd; 3539 3540 /* 3541 * The following code doesn't do anything but is left here 3542 * for clarity on what the new value of new_cons skipped. 3543 */ 3544 3545 /* get the next bd */ 3546 bd_idx = TX_BD(TX_BD_NEXT(bd_idx)); 3547 3548 /* skip the parse bd */ 3549 --nbd; 3550 bd_idx = TX_BD(TX_BD_NEXT(bd_idx)); 3551 3552 /* skip the TSO split header bd since they have no mapping */ 3553 if (tx_buf->flags & BXE_TSO_SPLIT_BD) { 3554 --nbd; 3555 bd_idx = TX_BD(TX_BD_NEXT(bd_idx)); 3556 } 3557 3558 /* now free frags */ 3559 while (nbd > 0) { 3560 tx_data_bd = &fp->tx_chain[bd_idx].reg_bd; 3561 if (--nbd) { 3562 bd_idx = TX_BD(TX_BD_NEXT(bd_idx)); 3563 } 3564 } 3565 #endif 3566 3567 /* free the mbuf */ 3568 if (__predict_true(tx_buf->m != NULL)) { 3569 m_freem(tx_buf->m); 3570 fp->eth_q_stats.mbuf_alloc_tx--; 3571 } else { 3572 fp->eth_q_stats.tx_chain_lost_mbuf++; 3573 } 3574 3575 tx_buf->m = NULL; 3576 tx_buf->first_bd = 0; 3577 3578 return (new_cons); 3579 } 3580 3581 /* transmit timeout watchdog */ 3582 static int 3583 bxe_watchdog(struct bxe_softc *sc, 3584 struct bxe_fastpath *fp) 3585 { 3586 BXE_FP_TX_LOCK(fp); 3587 3588 if ((fp->watchdog_timer == 0) || (--fp->watchdog_timer)) { 3589 BXE_FP_TX_UNLOCK(fp); 3590 return (0); 3591 } 3592 3593 BLOGE(sc, "TX watchdog timeout on fp[%02d], resetting!\n", fp->index); 3594 3595 BXE_FP_TX_UNLOCK(fp); 3596 3597 atomic_store_rel_long(&sc->chip_tq_flags, CHIP_TQ_REINIT); 3598 taskqueue_enqueue(sc->chip_tq, &sc->chip_tq_task); 3599 3600 return (-1); 3601 } 3602 3603 /* processes transmit completions */ 3604 static uint8_t 3605 bxe_txeof(struct bxe_softc *sc, 3606 struct bxe_fastpath *fp) 3607 { 3608 struct ifnet *ifp = sc->ifnet; 3609 uint16_t bd_cons, hw_cons, sw_cons, pkt_cons; 3610 uint16_t tx_bd_avail; 3611 3612 BXE_FP_TX_LOCK_ASSERT(fp); 3613 3614 bd_cons = fp->tx_bd_cons; 3615 hw_cons = le16toh(*fp->tx_cons_sb); 3616 sw_cons = fp->tx_pkt_cons; 3617 3618 while (sw_cons != hw_cons) { 3619 pkt_cons = TX_BD(sw_cons); 3620 3621 BLOGD(sc, DBG_TX, 3622 "TX: fp[%d]: hw_cons=%u sw_cons=%u pkt_cons=%u\n", 3623 fp->index, hw_cons, sw_cons, pkt_cons); 3624 3625 bd_cons = bxe_free_tx_pkt(sc, fp, pkt_cons); 3626 3627 sw_cons++; 3628 } 3629 3630 fp->tx_pkt_cons = sw_cons; 3631 fp->tx_bd_cons = bd_cons; 3632 3633 BLOGD(sc, DBG_TX, 3634 "TX done: fp[%d]: hw_cons=%u sw_cons=%u sw_prod=%u\n", 3635 fp->index, hw_cons, fp->tx_pkt_cons, fp->tx_pkt_prod); 3636 3637 mb(); 3638 3639 tx_bd_avail = bxe_tx_avail(sc, fp); 3640 3641 if (tx_bd_avail < BXE_TX_CLEANUP_THRESHOLD) { 3642 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 3643 } else { 3644 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3645 } 3646 3647 if (fp->tx_pkt_prod != fp->tx_pkt_cons) { 3648 /* reset the watchdog timer if there are pending transmits */ 3649 fp->watchdog_timer = BXE_TX_TIMEOUT; 3650 return (TRUE); 3651 } else { 3652 /* clear watchdog when there are no pending transmits */ 3653 fp->watchdog_timer = 0; 3654 return (FALSE); 3655 } 3656 } 3657 3658 static void 3659 bxe_drain_tx_queues(struct bxe_softc *sc) 3660 { 3661 struct bxe_fastpath *fp; 3662 int i, count; 3663 3664 /* wait until all TX fastpath tasks have completed */ 3665 for (i = 0; i < sc->num_queues; i++) { 3666 fp = &sc->fp[i]; 3667 3668 count = 1000; 3669 3670 while (bxe_has_tx_work(fp)) { 3671 3672 BXE_FP_TX_LOCK(fp); 3673 bxe_txeof(sc, fp); 3674 BXE_FP_TX_UNLOCK(fp); 3675 3676 if (count == 0) { 3677 BLOGE(sc, "Timeout waiting for fp[%d] " 3678 "transmits to complete!\n", i); 3679 bxe_panic(sc, ("tx drain failure\n")); 3680 return; 3681 } 3682 3683 count--; 3684 DELAY(1000); 3685 rmb(); 3686 } 3687 } 3688 3689 return; 3690 } 3691 3692 static int 3693 bxe_del_all_macs(struct bxe_softc *sc, 3694 struct ecore_vlan_mac_obj *mac_obj, 3695 int mac_type, 3696 uint8_t wait_for_comp) 3697 { 3698 unsigned long ramrod_flags = 0, vlan_mac_flags = 0; 3699 int rc; 3700 3701 /* wait for completion of requested */ 3702 if (wait_for_comp) { 3703 bxe_set_bit(RAMROD_COMP_WAIT, &ramrod_flags); 3704 } 3705 3706 /* Set the mac type of addresses we want to clear */ 3707 bxe_set_bit(mac_type, &vlan_mac_flags); 3708 3709 rc = mac_obj->delete_all(sc, mac_obj, &vlan_mac_flags, &ramrod_flags); 3710 if (rc < 0) { 3711 BLOGE(sc, "Failed to delete MACs (%d)\n", rc); 3712 } 3713 3714 return (rc); 3715 } 3716 3717 static int 3718 bxe_fill_accept_flags(struct bxe_softc *sc, 3719 uint32_t rx_mode, 3720 unsigned long *rx_accept_flags, 3721 unsigned long *tx_accept_flags) 3722 { 3723 /* Clear the flags first */ 3724 *rx_accept_flags = 0; 3725 *tx_accept_flags = 0; 3726 3727 switch (rx_mode) { 3728 case BXE_RX_MODE_NONE: 3729 /* 3730 * 'drop all' supersedes any accept flags that may have been 3731 * passed to the function. 3732 */ 3733 break; 3734 3735 case BXE_RX_MODE_NORMAL: 3736 bxe_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags); 3737 bxe_set_bit(ECORE_ACCEPT_MULTICAST, rx_accept_flags); 3738 bxe_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags); 3739 3740 /* internal switching mode */ 3741 bxe_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags); 3742 bxe_set_bit(ECORE_ACCEPT_MULTICAST, tx_accept_flags); 3743 bxe_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags); 3744 3745 break; 3746 3747 case BXE_RX_MODE_ALLMULTI: 3748 bxe_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags); 3749 bxe_set_bit(ECORE_ACCEPT_ALL_MULTICAST, rx_accept_flags); 3750 bxe_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags); 3751 3752 /* internal switching mode */ 3753 bxe_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags); 3754 bxe_set_bit(ECORE_ACCEPT_ALL_MULTICAST, tx_accept_flags); 3755 bxe_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags); 3756 3757 break; 3758 3759 case BXE_RX_MODE_PROMISC: 3760 /* 3761 * According to deffinition of SI mode, iface in promisc mode 3762 * should receive matched and unmatched (in resolution of port) 3763 * unicast packets. 3764 */ 3765 bxe_set_bit(ECORE_ACCEPT_UNMATCHED, rx_accept_flags); 3766 bxe_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags); 3767 bxe_set_bit(ECORE_ACCEPT_ALL_MULTICAST, rx_accept_flags); 3768 bxe_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags); 3769 3770 /* internal switching mode */ 3771 bxe_set_bit(ECORE_ACCEPT_ALL_MULTICAST, tx_accept_flags); 3772 bxe_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags); 3773 3774 if (IS_MF_SI(sc)) { 3775 bxe_set_bit(ECORE_ACCEPT_ALL_UNICAST, tx_accept_flags); 3776 } else { 3777 bxe_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags); 3778 } 3779 3780 break; 3781 3782 default: 3783 BLOGE(sc, "Unknown rx_mode (%d)\n", rx_mode); 3784 return (-1); 3785 } 3786 3787 /* Set ACCEPT_ANY_VLAN as we do not enable filtering by VLAN */ 3788 if (rx_mode != BXE_RX_MODE_NONE) { 3789 bxe_set_bit(ECORE_ACCEPT_ANY_VLAN, rx_accept_flags); 3790 bxe_set_bit(ECORE_ACCEPT_ANY_VLAN, tx_accept_flags); 3791 } 3792 3793 return (0); 3794 } 3795 3796 static int 3797 bxe_set_q_rx_mode(struct bxe_softc *sc, 3798 uint8_t cl_id, 3799 unsigned long rx_mode_flags, 3800 unsigned long rx_accept_flags, 3801 unsigned long tx_accept_flags, 3802 unsigned long ramrod_flags) 3803 { 3804 struct ecore_rx_mode_ramrod_params ramrod_param; 3805 int rc; 3806 3807 memset(&ramrod_param, 0, sizeof(ramrod_param)); 3808 3809 /* Prepare ramrod parameters */ 3810 ramrod_param.cid = 0; 3811 ramrod_param.cl_id = cl_id; 3812 ramrod_param.rx_mode_obj = &sc->rx_mode_obj; 3813 ramrod_param.func_id = SC_FUNC(sc); 3814 3815 ramrod_param.pstate = &sc->sp_state; 3816 ramrod_param.state = ECORE_FILTER_RX_MODE_PENDING; 3817 3818 ramrod_param.rdata = BXE_SP(sc, rx_mode_rdata); 3819 ramrod_param.rdata_mapping = BXE_SP_MAPPING(sc, rx_mode_rdata); 3820 3821 bxe_set_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state); 3822 3823 ramrod_param.ramrod_flags = ramrod_flags; 3824 ramrod_param.rx_mode_flags = rx_mode_flags; 3825 3826 ramrod_param.rx_accept_flags = rx_accept_flags; 3827 ramrod_param.tx_accept_flags = tx_accept_flags; 3828 3829 rc = ecore_config_rx_mode(sc, &ramrod_param); 3830 if (rc < 0) { 3831 BLOGE(sc, "Set rx_mode %d failed\n", sc->rx_mode); 3832 return (rc); 3833 } 3834 3835 return (0); 3836 } 3837 3838 static int 3839 bxe_set_storm_rx_mode(struct bxe_softc *sc) 3840 { 3841 unsigned long rx_mode_flags = 0, ramrod_flags = 0; 3842 unsigned long rx_accept_flags = 0, tx_accept_flags = 0; 3843 int rc; 3844 3845 rc = bxe_fill_accept_flags(sc, sc->rx_mode, &rx_accept_flags, 3846 &tx_accept_flags); 3847 if (rc) { 3848 return (rc); 3849 } 3850 3851 bxe_set_bit(RAMROD_RX, &ramrod_flags); 3852 bxe_set_bit(RAMROD_TX, &ramrod_flags); 3853 3854 /* XXX ensure all fastpath have same cl_id and/or move it to bxe_softc */ 3855 return (bxe_set_q_rx_mode(sc, sc->fp[0].cl_id, rx_mode_flags, 3856 rx_accept_flags, tx_accept_flags, 3857 ramrod_flags)); 3858 } 3859 3860 /* returns the "mcp load_code" according to global load_count array */ 3861 static int 3862 bxe_nic_load_no_mcp(struct bxe_softc *sc) 3863 { 3864 int path = SC_PATH(sc); 3865 int port = SC_PORT(sc); 3866 3867 BLOGI(sc, "NO MCP - load counts[%d] %d, %d, %d\n", 3868 path, load_count[path][0], load_count[path][1], 3869 load_count[path][2]); 3870 load_count[path][0]++; 3871 load_count[path][1 + port]++; 3872 BLOGI(sc, "NO MCP - new load counts[%d] %d, %d, %d\n", 3873 path, load_count[path][0], load_count[path][1], 3874 load_count[path][2]); 3875 if (load_count[path][0] == 1) { 3876 return (FW_MSG_CODE_DRV_LOAD_COMMON); 3877 } else if (load_count[path][1 + port] == 1) { 3878 return (FW_MSG_CODE_DRV_LOAD_PORT); 3879 } else { 3880 return (FW_MSG_CODE_DRV_LOAD_FUNCTION); 3881 } 3882 } 3883 3884 /* returns the "mcp load_code" according to global load_count array */ 3885 static int 3886 bxe_nic_unload_no_mcp(struct bxe_softc *sc) 3887 { 3888 int port = SC_PORT(sc); 3889 int path = SC_PATH(sc); 3890 3891 BLOGI(sc, "NO MCP - load counts[%d] %d, %d, %d\n", 3892 path, load_count[path][0], load_count[path][1], 3893 load_count[path][2]); 3894 load_count[path][0]--; 3895 load_count[path][1 + port]--; 3896 BLOGI(sc, "NO MCP - new load counts[%d] %d, %d, %d\n", 3897 path, load_count[path][0], load_count[path][1], 3898 load_count[path][2]); 3899 if (load_count[path][0] == 0) { 3900 return (FW_MSG_CODE_DRV_UNLOAD_COMMON); 3901 } else if (load_count[path][1 + port] == 0) { 3902 return (FW_MSG_CODE_DRV_UNLOAD_PORT); 3903 } else { 3904 return (FW_MSG_CODE_DRV_UNLOAD_FUNCTION); 3905 } 3906 } 3907 3908 /* request unload mode from the MCP: COMMON, PORT or FUNCTION */ 3909 static uint32_t 3910 bxe_send_unload_req(struct bxe_softc *sc, 3911 int unload_mode) 3912 { 3913 uint32_t reset_code = 0; 3914 #if 0 3915 int port = SC_PORT(sc); 3916 int path = SC_PATH(sc); 3917 #endif 3918 3919 /* Select the UNLOAD request mode */ 3920 if (unload_mode == UNLOAD_NORMAL) { 3921 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; 3922 } 3923 #if 0 3924 else if (sc->flags & BXE_NO_WOL_FLAG) { 3925 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP; 3926 } else if (sc->wol) { 3927 uint32_t emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; 3928 uint8_t *mac_addr = sc->dev->dev_addr; 3929 uint32_t val; 3930 uint16_t pmc; 3931 3932 /* 3933 * The mac address is written to entries 1-4 to 3934 * preserve entry 0 which is used by the PMF 3935 */ 3936 uint8_t entry = (SC_VN(sc) + 1)*8; 3937 3938 val = (mac_addr[0] << 8) | mac_addr[1]; 3939 EMAC_WR(sc, EMAC_REG_EMAC_MAC_MATCH + entry, val); 3940 3941 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) | 3942 (mac_addr[4] << 8) | mac_addr[5]; 3943 EMAC_WR(sc, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val); 3944 3945 /* Enable the PME and clear the status */ 3946 pmc = pci_read_config(sc->dev, 3947 (sc->devinfo.pcie_pm_cap_reg + 3948 PCIR_POWER_STATUS), 3949 2); 3950 pmc |= PCIM_PSTAT_PMEENABLE | PCIM_PSTAT_PME; 3951 pci_write_config(sc->dev, 3952 (sc->devinfo.pcie_pm_cap_reg + 3953 PCIR_POWER_STATUS), 3954 pmc, 4); 3955 3956 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN; 3957 } 3958 #endif 3959 else { 3960 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; 3961 } 3962 3963 /* Send the request to the MCP */ 3964 if (!BXE_NOMCP(sc)) { 3965 reset_code = bxe_fw_command(sc, reset_code, 0); 3966 } else { 3967 reset_code = bxe_nic_unload_no_mcp(sc); 3968 } 3969 3970 return (reset_code); 3971 } 3972 3973 /* send UNLOAD_DONE command to the MCP */ 3974 static void 3975 bxe_send_unload_done(struct bxe_softc *sc, 3976 uint8_t keep_link) 3977 { 3978 uint32_t reset_param = 3979 keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0; 3980 3981 /* Report UNLOAD_DONE to MCP */ 3982 if (!BXE_NOMCP(sc)) { 3983 bxe_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, reset_param); 3984 } 3985 } 3986 3987 static int 3988 bxe_func_wait_started(struct bxe_softc *sc) 3989 { 3990 int tout = 50; 3991 3992 if (!sc->port.pmf) { 3993 return (0); 3994 } 3995 3996 /* 3997 * (assumption: No Attention from MCP at this stage) 3998 * PMF probably in the middle of TX disable/enable transaction 3999 * 1. Sync IRS for default SB 4000 * 2. Sync SP queue - this guarantees us that attention handling started 4001 * 3. Wait, that TX disable/enable transaction completes 4002 * 4003 * 1+2 guarantee that if DCBX attention was scheduled it already changed 4004 * pending bit of transaction from STARTED-->TX_STOPPED, if we already 4005 * received completion for the transaction the state is TX_STOPPED. 4006 * State will return to STARTED after completion of TX_STOPPED-->STARTED 4007 * transaction. 4008 */ 4009 4010 /* XXX make sure default SB ISR is done */ 4011 /* need a way to synchronize an irq (intr_mtx?) */ 4012 4013 /* XXX flush any work queues */ 4014 4015 while (ecore_func_get_state(sc, &sc->func_obj) != 4016 ECORE_F_STATE_STARTED && tout--) { 4017 DELAY(20000); 4018 } 4019 4020 if (ecore_func_get_state(sc, &sc->func_obj) != ECORE_F_STATE_STARTED) { 4021 /* 4022 * Failed to complete the transaction in a "good way" 4023 * Force both transactions with CLR bit. 4024 */ 4025 struct ecore_func_state_params func_params = { NULL }; 4026 4027 BLOGE(sc, "Unexpected function state! " 4028 "Forcing STARTED-->TX_STOPPED-->STARTED\n"); 4029 4030 func_params.f_obj = &sc->func_obj; 4031 bxe_set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags); 4032 4033 /* STARTED-->TX_STOPPED */ 4034 func_params.cmd = ECORE_F_CMD_TX_STOP; 4035 ecore_func_state_change(sc, &func_params); 4036 4037 /* TX_STOPPED-->STARTED */ 4038 func_params.cmd = ECORE_F_CMD_TX_START; 4039 return (ecore_func_state_change(sc, &func_params)); 4040 } 4041 4042 return (0); 4043 } 4044 4045 static int 4046 bxe_stop_queue(struct bxe_softc *sc, 4047 int index) 4048 { 4049 struct bxe_fastpath *fp = &sc->fp[index]; 4050 struct ecore_queue_state_params q_params = { NULL }; 4051 int rc; 4052 4053 BLOGD(sc, DBG_LOAD, "stopping queue %d cid %d\n", index, fp->index); 4054 4055 q_params.q_obj = &sc->sp_objs[fp->index].q_obj; 4056 /* We want to wait for completion in this context */ 4057 bxe_set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags); 4058 4059 /* Stop the primary connection: */ 4060 4061 /* ...halt the connection */ 4062 q_params.cmd = ECORE_Q_CMD_HALT; 4063 rc = ecore_queue_state_change(sc, &q_params); 4064 if (rc) { 4065 return (rc); 4066 } 4067 4068 /* ...terminate the connection */ 4069 q_params.cmd = ECORE_Q_CMD_TERMINATE; 4070 memset(&q_params.params.terminate, 0, sizeof(q_params.params.terminate)); 4071 q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX; 4072 rc = ecore_queue_state_change(sc, &q_params); 4073 if (rc) { 4074 return (rc); 4075 } 4076 4077 /* ...delete cfc entry */ 4078 q_params.cmd = ECORE_Q_CMD_CFC_DEL; 4079 memset(&q_params.params.cfc_del, 0, sizeof(q_params.params.cfc_del)); 4080 q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX; 4081 return (ecore_queue_state_change(sc, &q_params)); 4082 } 4083 4084 /* wait for the outstanding SP commands */ 4085 static inline uint8_t 4086 bxe_wait_sp_comp(struct bxe_softc *sc, 4087 unsigned long mask) 4088 { 4089 unsigned long tmp; 4090 int tout = 5000; /* wait for 5 secs tops */ 4091 4092 while (tout--) { 4093 mb(); 4094 if (!(atomic_load_acq_long(&sc->sp_state) & mask)) { 4095 return (TRUE); 4096 } 4097 4098 DELAY(1000); 4099 } 4100 4101 mb(); 4102 4103 tmp = atomic_load_acq_long(&sc->sp_state); 4104 if (tmp & mask) { 4105 BLOGE(sc, "Filtering completion timed out: " 4106 "sp_state 0x%lx, mask 0x%lx\n", 4107 tmp, mask); 4108 return (FALSE); 4109 } 4110 4111 return (FALSE); 4112 } 4113 4114 static int 4115 bxe_func_stop(struct bxe_softc *sc) 4116 { 4117 struct ecore_func_state_params func_params = { NULL }; 4118 int rc; 4119 4120 /* prepare parameters for function state transitions */ 4121 bxe_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); 4122 func_params.f_obj = &sc->func_obj; 4123 func_params.cmd = ECORE_F_CMD_STOP; 4124 4125 /* 4126 * Try to stop the function the 'good way'. If it fails (in case 4127 * of a parity error during bxe_chip_cleanup()) and we are 4128 * not in a debug mode, perform a state transaction in order to 4129 * enable further HW_RESET transaction. 4130 */ 4131 rc = ecore_func_state_change(sc, &func_params); 4132 if (rc) { 4133 BLOGE(sc, "FUNC_STOP ramrod failed. " 4134 "Running a dry transaction\n"); 4135 bxe_set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags); 4136 return (ecore_func_state_change(sc, &func_params)); 4137 } 4138 4139 return (0); 4140 } 4141 4142 static int 4143 bxe_reset_hw(struct bxe_softc *sc, 4144 uint32_t load_code) 4145 { 4146 struct ecore_func_state_params func_params = { NULL }; 4147 4148 /* Prepare parameters for function state transitions */ 4149 bxe_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); 4150 4151 func_params.f_obj = &sc->func_obj; 4152 func_params.cmd = ECORE_F_CMD_HW_RESET; 4153 4154 func_params.params.hw_init.load_phase = load_code; 4155 4156 return (ecore_func_state_change(sc, &func_params)); 4157 } 4158 4159 static void 4160 bxe_int_disable_sync(struct bxe_softc *sc, 4161 int disable_hw) 4162 { 4163 if (disable_hw) { 4164 /* prevent the HW from sending interrupts */ 4165 bxe_int_disable(sc); 4166 } 4167 4168 /* XXX need a way to synchronize ALL irqs (intr_mtx?) */ 4169 /* make sure all ISRs are done */ 4170 4171 /* XXX make sure sp_task is not running */ 4172 /* cancel and flush work queues */ 4173 } 4174 4175 static void 4176 bxe_chip_cleanup(struct bxe_softc *sc, 4177 uint32_t unload_mode, 4178 uint8_t keep_link) 4179 { 4180 int port = SC_PORT(sc); 4181 struct ecore_mcast_ramrod_params rparam = { NULL }; 4182 uint32_t reset_code; 4183 int i, rc = 0; 4184 4185 bxe_drain_tx_queues(sc); 4186 4187 /* give HW time to discard old tx messages */ 4188 DELAY(1000); 4189 4190 /* Clean all ETH MACs */ 4191 rc = bxe_del_all_macs(sc, &sc->sp_objs[0].mac_obj, ECORE_ETH_MAC, FALSE); 4192 if (rc < 0) { 4193 BLOGE(sc, "Failed to delete all ETH MACs (%d)\n", rc); 4194 } 4195 4196 /* Clean up UC list */ 4197 rc = bxe_del_all_macs(sc, &sc->sp_objs[0].mac_obj, ECORE_UC_LIST_MAC, TRUE); 4198 if (rc < 0) { 4199 BLOGE(sc, "Failed to delete UC MACs list (%d)\n", rc); 4200 } 4201 4202 /* Disable LLH */ 4203 if (!CHIP_IS_E1(sc)) { 4204 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port*8, 0); 4205 } 4206 4207 /* Set "drop all" to stop Rx */ 4208 4209 /* 4210 * We need to take the BXE_MCAST_LOCK() here in order to prevent 4211 * a race between the completion code and this code. 4212 */ 4213 BXE_MCAST_LOCK(sc); 4214 4215 if (bxe_test_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state)) { 4216 bxe_set_bit(ECORE_FILTER_RX_MODE_SCHED, &sc->sp_state); 4217 } else { 4218 bxe_set_storm_rx_mode(sc); 4219 } 4220 4221 /* Clean up multicast configuration */ 4222 rparam.mcast_obj = &sc->mcast_obj; 4223 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_DEL); 4224 if (rc < 0) { 4225 BLOGE(sc, "Failed to send DEL MCAST command (%d)\n", rc); 4226 } 4227 4228 BXE_MCAST_UNLOCK(sc); 4229 4230 // XXX bxe_iov_chip_cleanup(sc); 4231 4232 /* 4233 * Send the UNLOAD_REQUEST to the MCP. This will return if 4234 * this function should perform FUNCTION, PORT, or COMMON HW 4235 * reset. 4236 */ 4237 reset_code = bxe_send_unload_req(sc, unload_mode); 4238 4239 /* 4240 * (assumption: No Attention from MCP at this stage) 4241 * PMF probably in the middle of TX disable/enable transaction 4242 */ 4243 rc = bxe_func_wait_started(sc); 4244 if (rc) { 4245 BLOGE(sc, "bxe_func_wait_started failed\n"); 4246 } 4247 4248 /* 4249 * Close multi and leading connections 4250 * Completions for ramrods are collected in a synchronous way 4251 */ 4252 for (i = 0; i < sc->num_queues; i++) { 4253 if (bxe_stop_queue(sc, i)) { 4254 goto unload_error; 4255 } 4256 } 4257 4258 /* 4259 * If SP settings didn't get completed so far - something 4260 * very wrong has happen. 4261 */ 4262 if (!bxe_wait_sp_comp(sc, ~0x0UL)) { 4263 BLOGE(sc, "Common slow path ramrods got stuck!\n"); 4264 } 4265 4266 unload_error: 4267 4268 rc = bxe_func_stop(sc); 4269 if (rc) { 4270 BLOGE(sc, "Function stop failed!\n"); 4271 } 4272 4273 /* disable HW interrupts */ 4274 bxe_int_disable_sync(sc, TRUE); 4275 4276 /* detach interrupts */ 4277 bxe_interrupt_detach(sc); 4278 4279 /* Reset the chip */ 4280 rc = bxe_reset_hw(sc, reset_code); 4281 if (rc) { 4282 BLOGE(sc, "Hardware reset failed\n"); 4283 } 4284 4285 /* Report UNLOAD_DONE to MCP */ 4286 bxe_send_unload_done(sc, keep_link); 4287 } 4288 4289 static void 4290 bxe_disable_close_the_gate(struct bxe_softc *sc) 4291 { 4292 uint32_t val; 4293 int port = SC_PORT(sc); 4294 4295 BLOGD(sc, DBG_LOAD, 4296 "Disabling 'close the gates'\n"); 4297 4298 if (CHIP_IS_E1(sc)) { 4299 uint32_t addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : 4300 MISC_REG_AEU_MASK_ATTN_FUNC_0; 4301 val = REG_RD(sc, addr); 4302 val &= ~(0x300); 4303 REG_WR(sc, addr, val); 4304 } else { 4305 val = REG_RD(sc, MISC_REG_AEU_GENERAL_MASK); 4306 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK | 4307 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK); 4308 REG_WR(sc, MISC_REG_AEU_GENERAL_MASK, val); 4309 } 4310 } 4311 4312 /* 4313 * Cleans the object that have internal lists without sending 4314 * ramrods. Should be run when interrutps are disabled. 4315 */ 4316 static void 4317 bxe_squeeze_objects(struct bxe_softc *sc) 4318 { 4319 unsigned long ramrod_flags = 0, vlan_mac_flags = 0; 4320 struct ecore_mcast_ramrod_params rparam = { NULL }; 4321 struct ecore_vlan_mac_obj *mac_obj = &sc->sp_objs->mac_obj; 4322 int rc; 4323 4324 /* Cleanup MACs' object first... */ 4325 4326 /* Wait for completion of requested */ 4327 bxe_set_bit(RAMROD_COMP_WAIT, &ramrod_flags); 4328 /* Perform a dry cleanup */ 4329 bxe_set_bit(RAMROD_DRV_CLR_ONLY, &ramrod_flags); 4330 4331 /* Clean ETH primary MAC */ 4332 bxe_set_bit(ECORE_ETH_MAC, &vlan_mac_flags); 4333 rc = mac_obj->delete_all(sc, &sc->sp_objs->mac_obj, &vlan_mac_flags, 4334 &ramrod_flags); 4335 if (rc != 0) { 4336 BLOGE(sc, "Failed to clean ETH MACs (%d)\n", rc); 4337 } 4338 4339 /* Cleanup UC list */ 4340 vlan_mac_flags = 0; 4341 bxe_set_bit(ECORE_UC_LIST_MAC, &vlan_mac_flags); 4342 rc = mac_obj->delete_all(sc, mac_obj, &vlan_mac_flags, 4343 &ramrod_flags); 4344 if (rc != 0) { 4345 BLOGE(sc, "Failed to clean UC list MACs (%d)\n", rc); 4346 } 4347 4348 /* Now clean mcast object... */ 4349 4350 rparam.mcast_obj = &sc->mcast_obj; 4351 bxe_set_bit(RAMROD_DRV_CLR_ONLY, &rparam.ramrod_flags); 4352 4353 /* Add a DEL command... */ 4354 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_DEL); 4355 if (rc < 0) { 4356 BLOGE(sc, "Failed to send DEL MCAST command (%d)\n", rc); 4357 } 4358 4359 /* now wait until all pending commands are cleared */ 4360 4361 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT); 4362 while (rc != 0) { 4363 if (rc < 0) { 4364 BLOGE(sc, "Failed to clean MCAST object (%d)\n", rc); 4365 return; 4366 } 4367 4368 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT); 4369 } 4370 } 4371 4372 /* stop the controller */ 4373 static __noinline int 4374 bxe_nic_unload(struct bxe_softc *sc, 4375 uint32_t unload_mode, 4376 uint8_t keep_link) 4377 { 4378 uint8_t global = FALSE; 4379 uint32_t val; 4380 4381 BXE_CORE_LOCK_ASSERT(sc); 4382 4383 BLOGD(sc, DBG_LOAD, "Starting NIC unload...\n"); 4384 4385 /* mark driver as unloaded in shmem2 */ 4386 if (IS_PF(sc) && SHMEM2_HAS(sc, drv_capabilities_flag)) { 4387 val = SHMEM2_RD(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)]); 4388 SHMEM2_WR(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)], 4389 val & ~DRV_FLAGS_CAPABILITIES_LOADED_L2); 4390 } 4391 4392 if (IS_PF(sc) && sc->recovery_state != BXE_RECOVERY_DONE && 4393 (sc->state == BXE_STATE_CLOSED || sc->state == BXE_STATE_ERROR)) { 4394 /* 4395 * We can get here if the driver has been unloaded 4396 * during parity error recovery and is either waiting for a 4397 * leader to complete or for other functions to unload and 4398 * then ifconfig down has been issued. In this case we want to 4399 * unload and let other functions to complete a recovery 4400 * process. 4401 */ 4402 sc->recovery_state = BXE_RECOVERY_DONE; 4403 sc->is_leader = 0; 4404 bxe_release_leader_lock(sc); 4405 mb(); 4406 4407 BLOGD(sc, DBG_LOAD, "Releasing a leadership...\n"); 4408 BLOGE(sc, "Can't unload in closed or error state\n"); 4409 return (-1); 4410 } 4411 4412 /* 4413 * Nothing to do during unload if previous bxe_nic_load() 4414 * did not completed succesfully - all resourses are released. 4415 */ 4416 if ((sc->state == BXE_STATE_CLOSED) || 4417 (sc->state == BXE_STATE_ERROR)) { 4418 return (0); 4419 } 4420 4421 sc->state = BXE_STATE_CLOSING_WAITING_HALT; 4422 mb(); 4423 4424 /* stop tx */ 4425 bxe_tx_disable(sc); 4426 4427 sc->rx_mode = BXE_RX_MODE_NONE; 4428 /* XXX set rx mode ??? */ 4429 4430 if (IS_PF(sc)) { 4431 /* set ALWAYS_ALIVE bit in shmem */ 4432 sc->fw_drv_pulse_wr_seq |= DRV_PULSE_ALWAYS_ALIVE; 4433 4434 bxe_drv_pulse(sc); 4435 4436 bxe_stats_handle(sc, STATS_EVENT_STOP); 4437 bxe_save_statistics(sc); 4438 } 4439 4440 /* wait till consumers catch up with producers in all queues */ 4441 bxe_drain_tx_queues(sc); 4442 4443 /* if VF indicate to PF this function is going down (PF will delete sp 4444 * elements and clear initializations 4445 */ 4446 if (IS_VF(sc)) { 4447 ; /* bxe_vfpf_close_vf(sc); */ 4448 } else if (unload_mode != UNLOAD_RECOVERY) { 4449 /* if this is a normal/close unload need to clean up chip */ 4450 bxe_chip_cleanup(sc, unload_mode, keep_link); 4451 } else { 4452 /* Send the UNLOAD_REQUEST to the MCP */ 4453 bxe_send_unload_req(sc, unload_mode); 4454 4455 /* 4456 * Prevent transactions to host from the functions on the 4457 * engine that doesn't reset global blocks in case of global 4458 * attention once gloabl blocks are reset and gates are opened 4459 * (the engine which leader will perform the recovery 4460 * last). 4461 */ 4462 if (!CHIP_IS_E1x(sc)) { 4463 bxe_pf_disable(sc); 4464 } 4465 4466 /* disable HW interrupts */ 4467 bxe_int_disable_sync(sc, TRUE); 4468 4469 /* detach interrupts */ 4470 bxe_interrupt_detach(sc); 4471 4472 /* Report UNLOAD_DONE to MCP */ 4473 bxe_send_unload_done(sc, FALSE); 4474 } 4475 4476 /* 4477 * At this stage no more interrupts will arrive so we may safely clean 4478 * the queue'able objects here in case they failed to get cleaned so far. 4479 */ 4480 if (IS_PF(sc)) { 4481 bxe_squeeze_objects(sc); 4482 } 4483 4484 /* There should be no more pending SP commands at this stage */ 4485 sc->sp_state = 0; 4486 4487 sc->port.pmf = 0; 4488 4489 bxe_free_fp_buffers(sc); 4490 4491 if (IS_PF(sc)) { 4492 bxe_free_mem(sc); 4493 } 4494 4495 bxe_free_fw_stats_mem(sc); 4496 4497 sc->state = BXE_STATE_CLOSED; 4498 4499 /* 4500 * Check if there are pending parity attentions. If there are - set 4501 * RECOVERY_IN_PROGRESS. 4502 */ 4503 if (IS_PF(sc) && bxe_chk_parity_attn(sc, &global, FALSE)) { 4504 bxe_set_reset_in_progress(sc); 4505 4506 /* Set RESET_IS_GLOBAL if needed */ 4507 if (global) { 4508 bxe_set_reset_global(sc); 4509 } 4510 } 4511 4512 /* 4513 * The last driver must disable a "close the gate" if there is no 4514 * parity attention or "process kill" pending. 4515 */ 4516 if (IS_PF(sc) && !bxe_clear_pf_load(sc) && 4517 bxe_reset_is_done(sc, SC_PATH(sc))) { 4518 bxe_disable_close_the_gate(sc); 4519 } 4520 4521 BLOGD(sc, DBG_LOAD, "Ended NIC unload\n"); 4522 4523 return (0); 4524 } 4525 4526 /* 4527 * Called by the OS to set various media options (i.e. link, speed, etc.) when 4528 * the user runs "ifconfig bxe media ..." or "ifconfig bxe mediaopt ...". 4529 */ 4530 static int 4531 bxe_ifmedia_update(struct ifnet *ifp) 4532 { 4533 struct bxe_softc *sc = (struct bxe_softc *)ifp->if_softc; 4534 struct ifmedia *ifm; 4535 4536 ifm = &sc->ifmedia; 4537 4538 /* We only support Ethernet media type. */ 4539 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) { 4540 return (EINVAL); 4541 } 4542 4543 switch (IFM_SUBTYPE(ifm->ifm_media)) { 4544 case IFM_AUTO: 4545 break; 4546 case IFM_10G_CX4: 4547 case IFM_10G_SR: 4548 case IFM_10G_T: 4549 case IFM_10G_TWINAX: 4550 default: 4551 /* We don't support changing the media type. */ 4552 BLOGD(sc, DBG_LOAD, "Invalid media type (%d)\n", 4553 IFM_SUBTYPE(ifm->ifm_media)); 4554 return (EINVAL); 4555 } 4556 4557 return (0); 4558 } 4559 4560 /* 4561 * Called by the OS to get the current media status (i.e. link, speed, etc.). 4562 */ 4563 static void 4564 bxe_ifmedia_status(struct ifnet *ifp, struct ifmediareq *ifmr) 4565 { 4566 struct bxe_softc *sc = ifp->if_softc; 4567 4568 /* Report link down if the driver isn't running. */ 4569 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 4570 ifmr->ifm_active |= IFM_NONE; 4571 return; 4572 } 4573 4574 /* Setup the default interface info. */ 4575 ifmr->ifm_status = IFM_AVALID; 4576 ifmr->ifm_active = IFM_ETHER; 4577 4578 if (sc->link_vars.link_up) { 4579 ifmr->ifm_status |= IFM_ACTIVE; 4580 } else { 4581 ifmr->ifm_active |= IFM_NONE; 4582 return; 4583 } 4584 4585 ifmr->ifm_active |= sc->media; 4586 4587 if (sc->link_vars.duplex == DUPLEX_FULL) { 4588 ifmr->ifm_active |= IFM_FDX; 4589 } else { 4590 ifmr->ifm_active |= IFM_HDX; 4591 } 4592 } 4593 4594 static int 4595 bxe_ioctl_nvram(struct bxe_softc *sc, 4596 uint32_t priv_op, 4597 struct ifreq *ifr) 4598 { 4599 struct bxe_nvram_data nvdata_base; 4600 struct bxe_nvram_data *nvdata; 4601 int len; 4602 int error = 0; 4603 4604 copyin(ifr->ifr_data, &nvdata_base, sizeof(nvdata_base)); 4605 4606 len = (sizeof(struct bxe_nvram_data) + 4607 nvdata_base.len - 4608 sizeof(uint32_t)); 4609 4610 if (len > sizeof(struct bxe_nvram_data)) { 4611 if ((nvdata = (struct bxe_nvram_data *) 4612 malloc(len, M_DEVBUF, 4613 (M_NOWAIT | M_ZERO))) == NULL) { 4614 BLOGE(sc, "BXE_IOC_RD_NVRAM malloc failed\n"); 4615 return (1); 4616 } 4617 memcpy(nvdata, &nvdata_base, sizeof(struct bxe_nvram_data)); 4618 } else { 4619 nvdata = &nvdata_base; 4620 } 4621 4622 if (priv_op == BXE_IOC_RD_NVRAM) { 4623 BLOGD(sc, DBG_IOCTL, "IOC_RD_NVRAM 0x%x %d\n", 4624 nvdata->offset, nvdata->len); 4625 error = bxe_nvram_read(sc, 4626 nvdata->offset, 4627 (uint8_t *)nvdata->value, 4628 nvdata->len); 4629 copyout(nvdata, ifr->ifr_data, len); 4630 } else { /* BXE_IOC_WR_NVRAM */ 4631 BLOGD(sc, DBG_IOCTL, "IOC_WR_NVRAM 0x%x %d\n", 4632 nvdata->offset, nvdata->len); 4633 copyin(ifr->ifr_data, nvdata, len); 4634 error = bxe_nvram_write(sc, 4635 nvdata->offset, 4636 (uint8_t *)nvdata->value, 4637 nvdata->len); 4638 } 4639 4640 if (len > sizeof(struct bxe_nvram_data)) { 4641 free(nvdata, M_DEVBUF); 4642 } 4643 4644 return (error); 4645 } 4646 4647 static int 4648 bxe_ioctl_stats_show(struct bxe_softc *sc, 4649 uint32_t priv_op, 4650 struct ifreq *ifr) 4651 { 4652 const size_t str_size = (BXE_NUM_ETH_STATS * STAT_NAME_LEN); 4653 const size_t stats_size = (BXE_NUM_ETH_STATS * sizeof(uint64_t)); 4654 caddr_t p_tmp; 4655 uint32_t *offset; 4656 int i; 4657 4658 switch (priv_op) 4659 { 4660 case BXE_IOC_STATS_SHOW_NUM: 4661 memset(ifr->ifr_data, 0, sizeof(union bxe_stats_show_data)); 4662 ((union bxe_stats_show_data *)ifr->ifr_data)->desc.num = 4663 BXE_NUM_ETH_STATS; 4664 ((union bxe_stats_show_data *)ifr->ifr_data)->desc.len = 4665 STAT_NAME_LEN; 4666 return (0); 4667 4668 case BXE_IOC_STATS_SHOW_STR: 4669 memset(ifr->ifr_data, 0, str_size); 4670 p_tmp = ifr->ifr_data; 4671 for (i = 0; i < BXE_NUM_ETH_STATS; i++) { 4672 strcpy(p_tmp, bxe_eth_stats_arr[i].string); 4673 p_tmp += STAT_NAME_LEN; 4674 } 4675 return (0); 4676 4677 case BXE_IOC_STATS_SHOW_CNT: 4678 memset(ifr->ifr_data, 0, stats_size); 4679 p_tmp = ifr->ifr_data; 4680 for (i = 0; i < BXE_NUM_ETH_STATS; i++) { 4681 offset = ((uint32_t *)&sc->eth_stats + 4682 bxe_eth_stats_arr[i].offset); 4683 switch (bxe_eth_stats_arr[i].size) { 4684 case 4: 4685 *((uint64_t *)p_tmp) = (uint64_t)*offset; 4686 break; 4687 case 8: 4688 *((uint64_t *)p_tmp) = HILO_U64(*offset, *(offset + 1)); 4689 break; 4690 default: 4691 *((uint64_t *)p_tmp) = 0; 4692 } 4693 p_tmp += sizeof(uint64_t); 4694 } 4695 return (0); 4696 4697 default: 4698 return (-1); 4699 } 4700 } 4701 4702 static void 4703 bxe_handle_chip_tq(void *context, 4704 int pending) 4705 { 4706 struct bxe_softc *sc = (struct bxe_softc *)context; 4707 long work = atomic_load_acq_long(&sc->chip_tq_flags); 4708 4709 switch (work) 4710 { 4711 case CHIP_TQ_START: 4712 if ((sc->ifnet->if_flags & IFF_UP) && 4713 !(sc->ifnet->if_drv_flags & IFF_DRV_RUNNING)) { 4714 /* start the interface */ 4715 BLOGD(sc, DBG_LOAD, "Starting the interface...\n"); 4716 BXE_CORE_LOCK(sc); 4717 bxe_init_locked(sc); 4718 BXE_CORE_UNLOCK(sc); 4719 } 4720 break; 4721 4722 case CHIP_TQ_STOP: 4723 if (!(sc->ifnet->if_flags & IFF_UP) && 4724 (sc->ifnet->if_drv_flags & IFF_DRV_RUNNING)) { 4725 /* bring down the interface */ 4726 BLOGD(sc, DBG_LOAD, "Stopping the interface...\n"); 4727 bxe_periodic_stop(sc); 4728 BXE_CORE_LOCK(sc); 4729 bxe_stop_locked(sc); 4730 BXE_CORE_UNLOCK(sc); 4731 } 4732 break; 4733 4734 case CHIP_TQ_REINIT: 4735 if (sc->ifnet->if_drv_flags & IFF_DRV_RUNNING) { 4736 /* restart the interface */ 4737 BLOGD(sc, DBG_LOAD, "Restarting the interface...\n"); 4738 bxe_periodic_stop(sc); 4739 BXE_CORE_LOCK(sc); 4740 bxe_stop_locked(sc); 4741 bxe_init_locked(sc); 4742 BXE_CORE_UNLOCK(sc); 4743 } 4744 break; 4745 4746 default: 4747 break; 4748 } 4749 } 4750 4751 /* 4752 * Handles any IOCTL calls from the operating system. 4753 * 4754 * Returns: 4755 * 0 = Success, >0 Failure 4756 */ 4757 static int 4758 bxe_ioctl(struct ifnet *ifp, 4759 u_long command, 4760 caddr_t data) 4761 { 4762 struct bxe_softc *sc = ifp->if_softc; 4763 struct ifreq *ifr = (struct ifreq *)data; 4764 struct bxe_nvram_data *nvdata; 4765 uint32_t priv_op; 4766 int mask = 0; 4767 int reinit = 0; 4768 int error = 0; 4769 4770 int mtu_min = (ETH_MIN_PACKET_SIZE - ETH_HLEN); 4771 int mtu_max = (MJUM9BYTES - ETH_OVERHEAD - IP_HEADER_ALIGNMENT_PADDING); 4772 4773 switch (command) 4774 { 4775 case SIOCSIFMTU: 4776 BLOGD(sc, DBG_IOCTL, "Received SIOCSIFMTU ioctl (mtu=%d)\n", 4777 ifr->ifr_mtu); 4778 4779 if (sc->mtu == ifr->ifr_mtu) { 4780 /* nothing to change */ 4781 break; 4782 } 4783 4784 if ((ifr->ifr_mtu < mtu_min) || (ifr->ifr_mtu > mtu_max)) { 4785 BLOGE(sc, "Unsupported MTU size %d (range is %d-%d)\n", 4786 ifr->ifr_mtu, mtu_min, mtu_max); 4787 error = EINVAL; 4788 break; 4789 } 4790 4791 atomic_store_rel_int((volatile unsigned int *)&sc->mtu, 4792 (unsigned long)ifr->ifr_mtu); 4793 atomic_store_rel_long((volatile unsigned long *)&ifp->if_mtu, 4794 (unsigned long)ifr->ifr_mtu); 4795 4796 reinit = 1; 4797 break; 4798 4799 case SIOCSIFFLAGS: 4800 /* toggle the interface state up or down */ 4801 BLOGD(sc, DBG_IOCTL, "Received SIOCSIFFLAGS ioctl\n"); 4802 4803 /* check if the interface is up */ 4804 if (ifp->if_flags & IFF_UP) { 4805 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 4806 /* set the receive mode flags */ 4807 bxe_set_rx_mode(sc); 4808 } else { 4809 atomic_store_rel_long(&sc->chip_tq_flags, CHIP_TQ_START); 4810 taskqueue_enqueue(sc->chip_tq, &sc->chip_tq_task); 4811 } 4812 } else { 4813 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 4814 atomic_store_rel_long(&sc->chip_tq_flags, CHIP_TQ_STOP); 4815 taskqueue_enqueue(sc->chip_tq, &sc->chip_tq_task); 4816 } 4817 } 4818 4819 break; 4820 4821 case SIOCADDMULTI: 4822 case SIOCDELMULTI: 4823 /* add/delete multicast addresses */ 4824 BLOGD(sc, DBG_IOCTL, "Received SIOCADDMULTI/SIOCDELMULTI ioctl\n"); 4825 4826 /* check if the interface is up */ 4827 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 4828 /* set the receive mode flags */ 4829 bxe_set_rx_mode(sc); 4830 } 4831 4832 break; 4833 4834 case SIOCSIFCAP: 4835 /* find out which capabilities have changed */ 4836 mask = (ifr->ifr_reqcap ^ ifp->if_capenable); 4837 4838 BLOGD(sc, DBG_IOCTL, "Received SIOCSIFCAP ioctl (mask=0x%08x)\n", 4839 mask); 4840 4841 /* toggle the LRO capabilites enable flag */ 4842 if (mask & IFCAP_LRO) { 4843 ifp->if_capenable ^= IFCAP_LRO; 4844 BLOGD(sc, DBG_IOCTL, "Turning LRO %s\n", 4845 (ifp->if_capenable & IFCAP_LRO) ? "ON" : "OFF"); 4846 reinit = 1; 4847 } 4848 4849 /* toggle the TXCSUM checksum capabilites enable flag */ 4850 if (mask & IFCAP_TXCSUM) { 4851 ifp->if_capenable ^= IFCAP_TXCSUM; 4852 BLOGD(sc, DBG_IOCTL, "Turning TXCSUM %s\n", 4853 (ifp->if_capenable & IFCAP_TXCSUM) ? "ON" : "OFF"); 4854 if (ifp->if_capenable & IFCAP_TXCSUM) { 4855 ifp->if_hwassist = (CSUM_IP | 4856 CSUM_TCP | 4857 CSUM_UDP | 4858 CSUM_TSO | 4859 CSUM_TCP_IPV6 | 4860 CSUM_UDP_IPV6); 4861 } else { 4862 ifp->if_hwassist = 0; 4863 } 4864 } 4865 4866 /* toggle the RXCSUM checksum capabilities enable flag */ 4867 if (mask & IFCAP_RXCSUM) { 4868 ifp->if_capenable ^= IFCAP_RXCSUM; 4869 BLOGD(sc, DBG_IOCTL, "Turning RXCSUM %s\n", 4870 (ifp->if_capenable & IFCAP_RXCSUM) ? "ON" : "OFF"); 4871 if (ifp->if_capenable & IFCAP_RXCSUM) { 4872 ifp->if_hwassist = (CSUM_IP | 4873 CSUM_TCP | 4874 CSUM_UDP | 4875 CSUM_TSO | 4876 CSUM_TCP_IPV6 | 4877 CSUM_UDP_IPV6); 4878 } else { 4879 ifp->if_hwassist = 0; 4880 } 4881 } 4882 4883 /* toggle TSO4 capabilities enabled flag */ 4884 if (mask & IFCAP_TSO4) { 4885 ifp->if_capenable ^= IFCAP_TSO4; 4886 BLOGD(sc, DBG_IOCTL, "Turning TSO4 %s\n", 4887 (ifp->if_capenable & IFCAP_TSO4) ? "ON" : "OFF"); 4888 } 4889 4890 /* toggle TSO6 capabilities enabled flag */ 4891 if (mask & IFCAP_TSO6) { 4892 ifp->if_capenable ^= IFCAP_TSO6; 4893 BLOGD(sc, DBG_IOCTL, "Turning TSO6 %s\n", 4894 (ifp->if_capenable & IFCAP_TSO6) ? "ON" : "OFF"); 4895 } 4896 4897 /* toggle VLAN_HWTSO capabilities enabled flag */ 4898 if (mask & IFCAP_VLAN_HWTSO) { 4899 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 4900 BLOGD(sc, DBG_IOCTL, "Turning VLAN_HWTSO %s\n", 4901 (ifp->if_capenable & IFCAP_VLAN_HWTSO) ? "ON" : "OFF"); 4902 } 4903 4904 /* toggle VLAN_HWCSUM capabilities enabled flag */ 4905 if (mask & IFCAP_VLAN_HWCSUM) { 4906 /* XXX investigate this... */ 4907 BLOGE(sc, "Changing VLAN_HWCSUM is not supported!\n"); 4908 error = EINVAL; 4909 } 4910 4911 /* toggle VLAN_MTU capabilities enable flag */ 4912 if (mask & IFCAP_VLAN_MTU) { 4913 /* XXX investigate this... */ 4914 BLOGE(sc, "Changing VLAN_MTU is not supported!\n"); 4915 error = EINVAL; 4916 } 4917 4918 /* toggle VLAN_HWTAGGING capabilities enabled flag */ 4919 if (mask & IFCAP_VLAN_HWTAGGING) { 4920 /* XXX investigate this... */ 4921 BLOGE(sc, "Changing VLAN_HWTAGGING is not supported!\n"); 4922 error = EINVAL; 4923 } 4924 4925 /* toggle VLAN_HWFILTER capabilities enabled flag */ 4926 if (mask & IFCAP_VLAN_HWFILTER) { 4927 /* XXX investigate this... */ 4928 BLOGE(sc, "Changing VLAN_HWFILTER is not supported!\n"); 4929 error = EINVAL; 4930 } 4931 4932 /* XXX not yet... 4933 * IFCAP_WOL_MAGIC 4934 */ 4935 4936 break; 4937 4938 case SIOCSIFMEDIA: 4939 case SIOCGIFMEDIA: 4940 /* set/get interface media */ 4941 BLOGD(sc, DBG_IOCTL, 4942 "Received SIOCSIFMEDIA/SIOCGIFMEDIA ioctl (cmd=%lu)\n", 4943 (command & 0xff)); 4944 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 4945 break; 4946 4947 case SIOCGPRIVATE_0: 4948 copyin(ifr->ifr_data, &priv_op, sizeof(priv_op)); 4949 4950 switch (priv_op) 4951 { 4952 case BXE_IOC_RD_NVRAM: 4953 case BXE_IOC_WR_NVRAM: 4954 nvdata = (struct bxe_nvram_data *)ifr->ifr_data; 4955 BLOGD(sc, DBG_IOCTL, 4956 "Received Private NVRAM ioctl addr=0x%x size=%u\n", 4957 nvdata->offset, nvdata->len); 4958 error = bxe_ioctl_nvram(sc, priv_op, ifr); 4959 break; 4960 4961 case BXE_IOC_STATS_SHOW_NUM: 4962 case BXE_IOC_STATS_SHOW_STR: 4963 case BXE_IOC_STATS_SHOW_CNT: 4964 BLOGD(sc, DBG_IOCTL, "Received Private Stats ioctl (%d)\n", 4965 priv_op); 4966 error = bxe_ioctl_stats_show(sc, priv_op, ifr); 4967 break; 4968 4969 default: 4970 BLOGW(sc, "Received Private Unknown ioctl (%d)\n", priv_op); 4971 error = EINVAL; 4972 break; 4973 } 4974 4975 break; 4976 4977 default: 4978 BLOGD(sc, DBG_IOCTL, "Received Unknown Ioctl (cmd=%lu)\n", 4979 (command & 0xff)); 4980 error = ether_ioctl(ifp, command, data); 4981 break; 4982 } 4983 4984 if (reinit && (sc->ifnet->if_drv_flags & IFF_DRV_RUNNING)) { 4985 BLOGD(sc, DBG_LOAD | DBG_IOCTL, 4986 "Re-initializing hardware from IOCTL change\n"); 4987 atomic_store_rel_long(&sc->chip_tq_flags, CHIP_TQ_REINIT); 4988 taskqueue_enqueue(sc->chip_tq, &sc->chip_tq_task); 4989 } 4990 4991 return (error); 4992 } 4993 4994 static __noinline void 4995 bxe_dump_mbuf(struct bxe_softc *sc, 4996 struct mbuf *m, 4997 uint8_t contents) 4998 { 4999 char * type; 5000 int i = 0; 5001 5002 if (!(sc->debug & DBG_MBUF)) { 5003 return; 5004 } 5005 5006 if (m == NULL) { 5007 BLOGD(sc, DBG_MBUF, "mbuf: null pointer\n"); 5008 return; 5009 } 5010 5011 while (m) { 5012 BLOGD(sc, DBG_MBUF, 5013 "%02d: mbuf=%p m_len=%d m_flags=0x%b m_data=%p\n", 5014 i, m, m->m_len, m->m_flags, M_FLAG_BITS, m->m_data); 5015 5016 if (m->m_flags & M_PKTHDR) { 5017 BLOGD(sc, DBG_MBUF, 5018 "%02d: - m_pkthdr: tot_len=%d flags=0x%b csum_flags=%b\n", 5019 i, m->m_pkthdr.len, m->m_flags, M_FLAG_BITS, 5020 (int)m->m_pkthdr.csum_flags, CSUM_BITS); 5021 } 5022 5023 if (m->m_flags & M_EXT) { 5024 switch (m->m_ext.ext_type) { 5025 case EXT_CLUSTER: type = "EXT_CLUSTER"; break; 5026 case EXT_SFBUF: type = "EXT_SFBUF"; break; 5027 case EXT_JUMBOP: type = "EXT_JUMBOP"; break; 5028 case EXT_JUMBO9: type = "EXT_JUMBO9"; break; 5029 case EXT_JUMBO16: type = "EXT_JUMBO16"; break; 5030 case EXT_PACKET: type = "EXT_PACKET"; break; 5031 case EXT_MBUF: type = "EXT_MBUF"; break; 5032 case EXT_NET_DRV: type = "EXT_NET_DRV"; break; 5033 case EXT_MOD_TYPE: type = "EXT_MOD_TYPE"; break; 5034 case EXT_DISPOSABLE: type = "EXT_DISPOSABLE"; break; 5035 case EXT_EXTREF: type = "EXT_EXTREF"; break; 5036 default: type = "UNKNOWN"; break; 5037 } 5038 5039 BLOGD(sc, DBG_MBUF, 5040 "%02d: - m_ext: %p ext_size=%d type=%s\n", 5041 i, m->m_ext.ext_buf, m->m_ext.ext_size, type); 5042 } 5043 5044 if (contents) { 5045 bxe_dump_mbuf_data(sc, "mbuf data", m, TRUE); 5046 } 5047 5048 m = m->m_next; 5049 i++; 5050 } 5051 } 5052 5053 /* 5054 * Checks to ensure the 13 bd sliding window is >= MSS for TSO. 5055 * Check that (13 total bds - 3 bds) = 10 bd window >= MSS. 5056 * The window: 3 bds are = 1 for headers BD + 2 for parse BD and last BD 5057 * The headers comes in a seperate bd in FreeBSD so 13-3=10. 5058 * Returns: 0 if OK to send, 1 if packet needs further defragmentation 5059 */ 5060 static int 5061 bxe_chktso_window(struct bxe_softc *sc, 5062 int nsegs, 5063 bus_dma_segment_t *segs, 5064 struct mbuf *m) 5065 { 5066 uint32_t num_wnds, wnd_size, wnd_sum; 5067 int32_t frag_idx, wnd_idx; 5068 unsigned short lso_mss; 5069 int defrag; 5070 5071 defrag = 0; 5072 wnd_sum = 0; 5073 wnd_size = 10; 5074 num_wnds = nsegs - wnd_size; 5075 lso_mss = htole16(m->m_pkthdr.tso_segsz); 5076 5077 /* 5078 * Total header lengths Eth+IP+TCP in first FreeBSD mbuf so calculate the 5079 * first window sum of data while skipping the first assuming it is the 5080 * header in FreeBSD. 5081 */ 5082 for (frag_idx = 1; (frag_idx <= wnd_size); frag_idx++) { 5083 wnd_sum += htole16(segs[frag_idx].ds_len); 5084 } 5085 5086 /* check the first 10 bd window size */ 5087 if (wnd_sum < lso_mss) { 5088 return (1); 5089 } 5090 5091 /* run through the windows */ 5092 for (wnd_idx = 0; wnd_idx < num_wnds; wnd_idx++, frag_idx++) { 5093 /* subtract the first mbuf->m_len of the last wndw(-header) */ 5094 wnd_sum -= htole16(segs[wnd_idx+1].ds_len); 5095 /* add the next mbuf len to the len of our new window */ 5096 wnd_sum += htole16(segs[frag_idx].ds_len); 5097 if (wnd_sum < lso_mss) { 5098 return (1); 5099 } 5100 } 5101 5102 return (0); 5103 } 5104 5105 static uint8_t 5106 bxe_set_pbd_csum_e2(struct bxe_fastpath *fp, 5107 struct mbuf *m, 5108 uint32_t *parsing_data) 5109 { 5110 struct ether_vlan_header *eh = NULL; 5111 struct ip *ip4 = NULL; 5112 struct ip6_hdr *ip6 = NULL; 5113 caddr_t ip = NULL; 5114 struct tcphdr *th = NULL; 5115 int e_hlen, ip_hlen, l4_off; 5116 uint16_t proto; 5117 5118 if (m->m_pkthdr.csum_flags == CSUM_IP) { 5119 /* no L4 checksum offload needed */ 5120 return (0); 5121 } 5122 5123 /* get the Ethernet header */ 5124 eh = mtod(m, struct ether_vlan_header *); 5125 5126 /* handle VLAN encapsulation if present */ 5127 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 5128 e_hlen = (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN); 5129 proto = ntohs(eh->evl_proto); 5130 } else { 5131 e_hlen = ETHER_HDR_LEN; 5132 proto = ntohs(eh->evl_encap_proto); 5133 } 5134 5135 switch (proto) { 5136 case ETHERTYPE_IP: 5137 /* get the IP header, if mbuf len < 20 then header in next mbuf */ 5138 ip4 = (m->m_len < sizeof(struct ip)) ? 5139 (struct ip *)m->m_next->m_data : 5140 (struct ip *)(m->m_data + e_hlen); 5141 /* ip_hl is number of 32-bit words */ 5142 ip_hlen = (ip4->ip_hl << 2); 5143 ip = (caddr_t)ip4; 5144 break; 5145 case ETHERTYPE_IPV6: 5146 /* get the IPv6 header, if mbuf len < 40 then header in next mbuf */ 5147 ip6 = (m->m_len < sizeof(struct ip6_hdr)) ? 5148 (struct ip6_hdr *)m->m_next->m_data : 5149 (struct ip6_hdr *)(m->m_data + e_hlen); 5150 /* XXX cannot support offload with IPv6 extensions */ 5151 ip_hlen = sizeof(struct ip6_hdr); 5152 ip = (caddr_t)ip6; 5153 break; 5154 default: 5155 /* We can't offload in this case... */ 5156 /* XXX error stat ??? */ 5157 return (0); 5158 } 5159 5160 /* XXX assuming L4 header is contiguous to IPv4/IPv6 in the same mbuf */ 5161 l4_off = (e_hlen + ip_hlen); 5162 5163 *parsing_data |= 5164 (((l4_off >> 1) << ETH_TX_PARSE_BD_E2_L4_HDR_START_OFFSET_W_SHIFT) & 5165 ETH_TX_PARSE_BD_E2_L4_HDR_START_OFFSET_W); 5166 5167 if (m->m_pkthdr.csum_flags & (CSUM_TCP | 5168 CSUM_TSO | 5169 CSUM_TCP_IPV6)) { 5170 fp->eth_q_stats.tx_ofld_frames_csum_tcp++; 5171 th = (struct tcphdr *)(ip + ip_hlen); 5172 /* th_off is number of 32-bit words */ 5173 *parsing_data |= ((th->th_off << 5174 ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW_SHIFT) & 5175 ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW); 5176 return (l4_off + (th->th_off << 2)); /* entire header length */ 5177 } else if (m->m_pkthdr.csum_flags & (CSUM_UDP | 5178 CSUM_UDP_IPV6)) { 5179 fp->eth_q_stats.tx_ofld_frames_csum_udp++; 5180 return (l4_off + sizeof(struct udphdr)); /* entire header length */ 5181 } else { 5182 /* XXX error stat ??? */ 5183 return (0); 5184 } 5185 } 5186 5187 static uint8_t 5188 bxe_set_pbd_csum(struct bxe_fastpath *fp, 5189 struct mbuf *m, 5190 struct eth_tx_parse_bd_e1x *pbd) 5191 { 5192 struct ether_vlan_header *eh = NULL; 5193 struct ip *ip4 = NULL; 5194 struct ip6_hdr *ip6 = NULL; 5195 caddr_t ip = NULL; 5196 struct tcphdr *th = NULL; 5197 struct udphdr *uh = NULL; 5198 int e_hlen, ip_hlen; 5199 uint16_t proto; 5200 uint8_t hlen; 5201 uint16_t tmp_csum; 5202 uint32_t *tmp_uh; 5203 5204 /* get the Ethernet header */ 5205 eh = mtod(m, struct ether_vlan_header *); 5206 5207 /* handle VLAN encapsulation if present */ 5208 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 5209 e_hlen = (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN); 5210 proto = ntohs(eh->evl_proto); 5211 } else { 5212 e_hlen = ETHER_HDR_LEN; 5213 proto = ntohs(eh->evl_encap_proto); 5214 } 5215 5216 switch (proto) { 5217 case ETHERTYPE_IP: 5218 /* get the IP header, if mbuf len < 20 then header in next mbuf */ 5219 ip4 = (m->m_len < sizeof(struct ip)) ? 5220 (struct ip *)m->m_next->m_data : 5221 (struct ip *)(m->m_data + e_hlen); 5222 /* ip_hl is number of 32-bit words */ 5223 ip_hlen = (ip4->ip_hl << 1); 5224 ip = (caddr_t)ip4; 5225 break; 5226 case ETHERTYPE_IPV6: 5227 /* get the IPv6 header, if mbuf len < 40 then header in next mbuf */ 5228 ip6 = (m->m_len < sizeof(struct ip6_hdr)) ? 5229 (struct ip6_hdr *)m->m_next->m_data : 5230 (struct ip6_hdr *)(m->m_data + e_hlen); 5231 /* XXX cannot support offload with IPv6 extensions */ 5232 ip_hlen = (sizeof(struct ip6_hdr) >> 1); 5233 ip = (caddr_t)ip6; 5234 break; 5235 default: 5236 /* We can't offload in this case... */ 5237 /* XXX error stat ??? */ 5238 return (0); 5239 } 5240 5241 hlen = (e_hlen >> 1); 5242 5243 /* note that rest of global_data is indirectly zeroed here */ 5244 if (m->m_flags & M_VLANTAG) { 5245 pbd->global_data = 5246 htole16(hlen | (1 << ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN_SHIFT)); 5247 } else { 5248 pbd->global_data = htole16(hlen); 5249 } 5250 5251 pbd->ip_hlen_w = ip_hlen; 5252 5253 hlen += pbd->ip_hlen_w; 5254 5255 /* XXX assuming L4 header is contiguous to IPv4/IPv6 in the same mbuf */ 5256 5257 if (m->m_pkthdr.csum_flags & (CSUM_TCP | 5258 CSUM_TSO | 5259 CSUM_TCP_IPV6)) { 5260 th = (struct tcphdr *)(ip + (ip_hlen << 1)); 5261 /* th_off is number of 32-bit words */ 5262 hlen += (uint16_t)(th->th_off << 1); 5263 } else if (m->m_pkthdr.csum_flags & (CSUM_UDP | 5264 CSUM_UDP_IPV6)) { 5265 uh = (struct udphdr *)(ip + (ip_hlen << 1)); 5266 hlen += (sizeof(struct udphdr) / 2); 5267 } else { 5268 /* valid case as only CSUM_IP was set */ 5269 return (0); 5270 } 5271 5272 pbd->total_hlen_w = htole16(hlen); 5273 5274 if (m->m_pkthdr.csum_flags & (CSUM_TCP | 5275 CSUM_TSO | 5276 CSUM_TCP_IPV6)) { 5277 fp->eth_q_stats.tx_ofld_frames_csum_tcp++; 5278 pbd->tcp_pseudo_csum = ntohs(th->th_sum); 5279 } else if (m->m_pkthdr.csum_flags & (CSUM_UDP | 5280 CSUM_UDP_IPV6)) { 5281 fp->eth_q_stats.tx_ofld_frames_csum_udp++; 5282 5283 /* 5284 * Everest1 (i.e. 57710, 57711, 57711E) does not natively support UDP 5285 * checksums and does not know anything about the UDP header and where 5286 * the checksum field is located. It only knows about TCP. Therefore 5287 * we "lie" to the hardware for outgoing UDP packets w/ checksum 5288 * offload. Since the checksum field offset for TCP is 16 bytes and 5289 * for UDP it is 6 bytes we pass a pointer to the hardware that is 10 5290 * bytes less than the start of the UDP header. This allows the 5291 * hardware to write the checksum in the correct spot. But the 5292 * hardware will compute a checksum which includes the last 10 bytes 5293 * of the IP header. To correct this we tweak the stack computed 5294 * pseudo checksum by folding in the calculation of the inverse 5295 * checksum for those final 10 bytes of the IP header. This allows 5296 * the correct checksum to be computed by the hardware. 5297 */ 5298 5299 /* set pointer 10 bytes before UDP header */ 5300 tmp_uh = (uint32_t *)((uint8_t *)uh - 10); 5301 5302 /* calculate a pseudo header checksum over the first 10 bytes */ 5303 tmp_csum = in_pseudo(*tmp_uh, 5304 *(tmp_uh + 1), 5305 *(uint16_t *)(tmp_uh + 2)); 5306 5307 pbd->tcp_pseudo_csum = ntohs(in_addword(uh->uh_sum, ~tmp_csum)); 5308 } 5309 5310 return (hlen * 2); /* entire header length, number of bytes */ 5311 } 5312 5313 static void 5314 bxe_set_pbd_lso_e2(struct mbuf *m, 5315 uint32_t *parsing_data) 5316 { 5317 *parsing_data |= ((m->m_pkthdr.tso_segsz << 5318 ETH_TX_PARSE_BD_E2_LSO_MSS_SHIFT) & 5319 ETH_TX_PARSE_BD_E2_LSO_MSS); 5320 5321 /* XXX test for IPv6 with extension header... */ 5322 #if 0 5323 struct ip6_hdr *ip6; 5324 if (ip6 && ip6->ip6_nxt == 'some ipv6 extension header') 5325 *parsing_data |= ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR; 5326 #endif 5327 } 5328 5329 static void 5330 bxe_set_pbd_lso(struct mbuf *m, 5331 struct eth_tx_parse_bd_e1x *pbd) 5332 { 5333 struct ether_vlan_header *eh = NULL; 5334 struct ip *ip = NULL; 5335 struct tcphdr *th = NULL; 5336 int e_hlen; 5337 5338 /* get the Ethernet header */ 5339 eh = mtod(m, struct ether_vlan_header *); 5340 5341 /* handle VLAN encapsulation if present */ 5342 e_hlen = (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) ? 5343 (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN) : ETHER_HDR_LEN; 5344 5345 /* get the IP and TCP header, with LSO entire header in first mbuf */ 5346 /* XXX assuming IPv4 */ 5347 ip = (struct ip *)(m->m_data + e_hlen); 5348 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 5349 5350 pbd->lso_mss = htole16(m->m_pkthdr.tso_segsz); 5351 pbd->tcp_send_seq = ntohl(th->th_seq); 5352 pbd->tcp_flags = ((ntohl(((uint32_t *)th)[3]) >> 16) & 0xff); 5353 5354 #if 1 5355 /* XXX IPv4 */ 5356 pbd->ip_id = ntohs(ip->ip_id); 5357 pbd->tcp_pseudo_csum = 5358 ntohs(in_pseudo(ip->ip_src.s_addr, 5359 ip->ip_dst.s_addr, 5360 htons(IPPROTO_TCP))); 5361 #else 5362 /* XXX IPv6 */ 5363 pbd->tcp_pseudo_csum = 5364 ntohs(in_pseudo(&ip6->ip6_src, 5365 &ip6->ip6_dst, 5366 htons(IPPROTO_TCP))); 5367 #endif 5368 5369 pbd->global_data |= 5370 htole16(ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN); 5371 } 5372 5373 /* 5374 * Encapsulte an mbuf cluster into the tx bd chain and makes the memory 5375 * visible to the controller. 5376 * 5377 * If an mbuf is submitted to this routine and cannot be given to the 5378 * controller (e.g. it has too many fragments) then the function may free 5379 * the mbuf and return to the caller. 5380 * 5381 * Returns: 5382 * 0 = Success, !0 = Failure 5383 * Note the side effect that an mbuf may be freed if it causes a problem. 5384 */ 5385 static int 5386 bxe_tx_encap(struct bxe_fastpath *fp, struct mbuf **m_head) 5387 { 5388 bus_dma_segment_t segs[32]; 5389 struct mbuf *m0; 5390 struct bxe_sw_tx_bd *tx_buf; 5391 struct eth_tx_parse_bd_e1x *pbd_e1x = NULL; 5392 struct eth_tx_parse_bd_e2 *pbd_e2 = NULL; 5393 /* struct eth_tx_parse_2nd_bd *pbd2 = NULL; */ 5394 struct eth_tx_bd *tx_data_bd; 5395 struct eth_tx_bd *tx_total_pkt_size_bd; 5396 struct eth_tx_start_bd *tx_start_bd; 5397 uint16_t bd_prod, pkt_prod, total_pkt_size; 5398 uint8_t mac_type; 5399 int defragged, error, nsegs, rc, nbds, vlan_off, ovlan; 5400 struct bxe_softc *sc; 5401 uint16_t tx_bd_avail; 5402 struct ether_vlan_header *eh; 5403 uint32_t pbd_e2_parsing_data = 0; 5404 uint8_t hlen = 0; 5405 int tmp_bd; 5406 int i; 5407 5408 sc = fp->sc; 5409 5410 M_ASSERTPKTHDR(*m_head); 5411 5412 m0 = *m_head; 5413 rc = defragged = nbds = ovlan = vlan_off = total_pkt_size = 0; 5414 tx_start_bd = NULL; 5415 tx_data_bd = NULL; 5416 tx_total_pkt_size_bd = NULL; 5417 5418 /* get the H/W pointer for packets and BDs */ 5419 pkt_prod = fp->tx_pkt_prod; 5420 bd_prod = fp->tx_bd_prod; 5421 5422 mac_type = UNICAST_ADDRESS; 5423 5424 /* map the mbuf into the next open DMAable memory */ 5425 tx_buf = &fp->tx_mbuf_chain[TX_BD(pkt_prod)]; 5426 error = bus_dmamap_load_mbuf_sg(fp->tx_mbuf_tag, 5427 tx_buf->m_map, m0, 5428 segs, &nsegs, BUS_DMA_NOWAIT); 5429 5430 /* mapping errors */ 5431 if(__predict_false(error != 0)) { 5432 fp->eth_q_stats.tx_dma_mapping_failure++; 5433 if (error == ENOMEM) { 5434 /* resource issue, try again later */ 5435 rc = ENOMEM; 5436 } else if (error == EFBIG) { 5437 /* possibly recoverable with defragmentation */ 5438 fp->eth_q_stats.mbuf_defrag_attempts++; 5439 m0 = m_defrag(*m_head, M_NOWAIT); 5440 if (m0 == NULL) { 5441 fp->eth_q_stats.mbuf_defrag_failures++; 5442 rc = ENOBUFS; 5443 } else { 5444 /* defrag successful, try mapping again */ 5445 *m_head = m0; 5446 error = bus_dmamap_load_mbuf_sg(fp->tx_mbuf_tag, 5447 tx_buf->m_map, m0, 5448 segs, &nsegs, BUS_DMA_NOWAIT); 5449 if (error) { 5450 fp->eth_q_stats.tx_dma_mapping_failure++; 5451 rc = error; 5452 } 5453 } 5454 } else { 5455 /* unknown, unrecoverable mapping error */ 5456 BLOGE(sc, "Unknown TX mapping error rc=%d\n", error); 5457 bxe_dump_mbuf(sc, m0, FALSE); 5458 rc = error; 5459 } 5460 5461 goto bxe_tx_encap_continue; 5462 } 5463 5464 tx_bd_avail = bxe_tx_avail(sc, fp); 5465 5466 /* make sure there is enough room in the send queue */ 5467 if (__predict_false(tx_bd_avail < (nsegs + 2))) { 5468 /* Recoverable, try again later. */ 5469 fp->eth_q_stats.tx_hw_queue_full++; 5470 bus_dmamap_unload(fp->tx_mbuf_tag, tx_buf->m_map); 5471 rc = ENOMEM; 5472 goto bxe_tx_encap_continue; 5473 } 5474 5475 /* capture the current H/W TX chain high watermark */ 5476 if (__predict_false(fp->eth_q_stats.tx_hw_max_queue_depth < 5477 (TX_BD_USABLE - tx_bd_avail))) { 5478 fp->eth_q_stats.tx_hw_max_queue_depth = (TX_BD_USABLE - tx_bd_avail); 5479 } 5480 5481 /* make sure it fits in the packet window */ 5482 if (__predict_false(nsegs > BXE_MAX_SEGMENTS)) { 5483 /* 5484 * The mbuf may be to big for the controller to handle. If the frame 5485 * is a TSO frame we'll need to do an additional check. 5486 */ 5487 if (m0->m_pkthdr.csum_flags & CSUM_TSO) { 5488 if (bxe_chktso_window(sc, nsegs, segs, m0) == 0) { 5489 goto bxe_tx_encap_continue; /* OK to send */ 5490 } else { 5491 fp->eth_q_stats.tx_window_violation_tso++; 5492 } 5493 } else { 5494 fp->eth_q_stats.tx_window_violation_std++; 5495 } 5496 5497 /* lets try to defragment this mbuf and remap it */ 5498 fp->eth_q_stats.mbuf_defrag_attempts++; 5499 bus_dmamap_unload(fp->tx_mbuf_tag, tx_buf->m_map); 5500 5501 m0 = m_defrag(*m_head, M_NOWAIT); 5502 if (m0 == NULL) { 5503 fp->eth_q_stats.mbuf_defrag_failures++; 5504 /* Ugh, just drop the frame... :( */ 5505 rc = ENOBUFS; 5506 } else { 5507 /* defrag successful, try mapping again */ 5508 *m_head = m0; 5509 error = bus_dmamap_load_mbuf_sg(fp->tx_mbuf_tag, 5510 tx_buf->m_map, m0, 5511 segs, &nsegs, BUS_DMA_NOWAIT); 5512 if (error) { 5513 fp->eth_q_stats.tx_dma_mapping_failure++; 5514 /* No sense in trying to defrag/copy chain, drop it. :( */ 5515 rc = error; 5516 } 5517 else { 5518 /* if the chain is still too long then drop it */ 5519 if (__predict_false(nsegs > BXE_MAX_SEGMENTS)) { 5520 bus_dmamap_unload(fp->tx_mbuf_tag, tx_buf->m_map); 5521 rc = ENODEV; 5522 } 5523 } 5524 } 5525 } 5526 5527 bxe_tx_encap_continue: 5528 5529 /* Check for errors */ 5530 if (rc) { 5531 if (rc == ENOMEM) { 5532 /* recoverable try again later */ 5533 } else { 5534 fp->eth_q_stats.tx_soft_errors++; 5535 fp->eth_q_stats.mbuf_alloc_tx--; 5536 m_freem(*m_head); 5537 *m_head = NULL; 5538 } 5539 5540 return (rc); 5541 } 5542 5543 /* set flag according to packet type (UNICAST_ADDRESS is default) */ 5544 if (m0->m_flags & M_BCAST) { 5545 mac_type = BROADCAST_ADDRESS; 5546 } else if (m0->m_flags & M_MCAST) { 5547 mac_type = MULTICAST_ADDRESS; 5548 } 5549 5550 /* store the mbuf into the mbuf ring */ 5551 tx_buf->m = m0; 5552 tx_buf->first_bd = fp->tx_bd_prod; 5553 tx_buf->flags = 0; 5554 5555 /* prepare the first transmit (start) BD for the mbuf */ 5556 tx_start_bd = &fp->tx_chain[TX_BD(bd_prod)].start_bd; 5557 5558 BLOGD(sc, DBG_TX, 5559 "sending pkt_prod=%u tx_buf=%p next_idx=%u bd=%u tx_start_bd=%p\n", 5560 pkt_prod, tx_buf, fp->tx_pkt_prod, bd_prod, tx_start_bd); 5561 5562 tx_start_bd->addr_lo = htole32(U64_LO(segs[0].ds_addr)); 5563 tx_start_bd->addr_hi = htole32(U64_HI(segs[0].ds_addr)); 5564 tx_start_bd->nbytes = htole16(segs[0].ds_len); 5565 total_pkt_size += tx_start_bd->nbytes; 5566 tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD; 5567 5568 tx_start_bd->general_data = (1 << ETH_TX_START_BD_HDR_NBDS_SHIFT); 5569 5570 /* all frames have at least Start BD + Parsing BD */ 5571 nbds = nsegs + 1; 5572 tx_start_bd->nbd = htole16(nbds); 5573 5574 if (m0->m_flags & M_VLANTAG) { 5575 tx_start_bd->vlan_or_ethertype = htole16(m0->m_pkthdr.ether_vtag); 5576 tx_start_bd->bd_flags.as_bitfield |= 5577 (X_ETH_OUTBAND_VLAN << ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT); 5578 } else { 5579 /* vf tx, start bd must hold the ethertype for fw to enforce it */ 5580 if (IS_VF(sc)) { 5581 /* map ethernet header to find type and header length */ 5582 eh = mtod(m0, struct ether_vlan_header *); 5583 tx_start_bd->vlan_or_ethertype = eh->evl_encap_proto; 5584 } else { 5585 /* used by FW for packet accounting */ 5586 tx_start_bd->vlan_or_ethertype = htole16(fp->tx_pkt_prod); 5587 #if 0 5588 /* 5589 * If NPAR-SD is active then FW should do the tagging regardless 5590 * of value of priority. Otherwise, if priority indicates this is 5591 * a control packet we need to indicate to FW to avoid tagging. 5592 */ 5593 if (!IS_MF_AFEX(sc) && (mbuf priority == PRIO_CONTROL)) { 5594 SET_FLAG(tx_start_bd->general_data, 5595 ETH_TX_START_BD_FORCE_VLAN_MODE, 1); 5596 } 5597 #endif 5598 } 5599 } 5600 5601 /* 5602 * add a parsing BD from the chain. The parsing BD is always added 5603 * though it is only used for TSO and chksum 5604 */ 5605 bd_prod = TX_BD_NEXT(bd_prod); 5606 5607 if (m0->m_pkthdr.csum_flags) { 5608 if (m0->m_pkthdr.csum_flags & CSUM_IP) { 5609 fp->eth_q_stats.tx_ofld_frames_csum_ip++; 5610 tx_start_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_IP_CSUM; 5611 } 5612 5613 if (m0->m_pkthdr.csum_flags & CSUM_TCP_IPV6) { 5614 tx_start_bd->bd_flags.as_bitfield |= (ETH_TX_BD_FLAGS_IPV6 | 5615 ETH_TX_BD_FLAGS_L4_CSUM); 5616 } else if (m0->m_pkthdr.csum_flags & CSUM_UDP_IPV6) { 5617 tx_start_bd->bd_flags.as_bitfield |= (ETH_TX_BD_FLAGS_IPV6 | 5618 ETH_TX_BD_FLAGS_IS_UDP | 5619 ETH_TX_BD_FLAGS_L4_CSUM); 5620 } else if ((m0->m_pkthdr.csum_flags & CSUM_TCP) || 5621 (m0->m_pkthdr.csum_flags & CSUM_TSO)) { 5622 tx_start_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_L4_CSUM; 5623 } else if (m0->m_pkthdr.csum_flags & CSUM_UDP) { 5624 tx_start_bd->bd_flags.as_bitfield |= (ETH_TX_BD_FLAGS_L4_CSUM | 5625 ETH_TX_BD_FLAGS_IS_UDP); 5626 } 5627 } 5628 5629 if (!CHIP_IS_E1x(sc)) { 5630 pbd_e2 = &fp->tx_chain[TX_BD(bd_prod)].parse_bd_e2; 5631 memset(pbd_e2, 0, sizeof(struct eth_tx_parse_bd_e2)); 5632 5633 if (m0->m_pkthdr.csum_flags) { 5634 hlen = bxe_set_pbd_csum_e2(fp, m0, &pbd_e2_parsing_data); 5635 } 5636 5637 #if 0 5638 /* 5639 * Add the MACs to the parsing BD if the module param was 5640 * explicitly set, if this is a vf, or in switch independent 5641 * mode. 5642 */ 5643 if (sc->flags & BXE_TX_SWITCHING || IS_VF(sc) || IS_MF_SI(sc)) { 5644 eh = mtod(m0, struct ether_vlan_header *); 5645 bxe_set_fw_mac_addr(&pbd_e2->data.mac_addr.src_hi, 5646 &pbd_e2->data.mac_addr.src_mid, 5647 &pbd_e2->data.mac_addr.src_lo, 5648 eh->evl_shost); 5649 bxe_set_fw_mac_addr(&pbd_e2->data.mac_addr.dst_hi, 5650 &pbd_e2->data.mac_addr.dst_mid, 5651 &pbd_e2->data.mac_addr.dst_lo, 5652 eh->evl_dhost); 5653 } 5654 #endif 5655 5656 SET_FLAG(pbd_e2_parsing_data, ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE, 5657 mac_type); 5658 } else { 5659 uint16_t global_data = 0; 5660 5661 pbd_e1x = &fp->tx_chain[TX_BD(bd_prod)].parse_bd_e1x; 5662 memset(pbd_e1x, 0, sizeof(struct eth_tx_parse_bd_e1x)); 5663 5664 if (m0->m_pkthdr.csum_flags) { 5665 hlen = bxe_set_pbd_csum(fp, m0, pbd_e1x); 5666 } 5667 5668 SET_FLAG(global_data, 5669 ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE, mac_type); 5670 pbd_e1x->global_data |= htole16(global_data); 5671 } 5672 5673 /* setup the parsing BD with TSO specific info */ 5674 if (m0->m_pkthdr.csum_flags & CSUM_TSO) { 5675 fp->eth_q_stats.tx_ofld_frames_lso++; 5676 tx_start_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_SW_LSO; 5677 5678 if (__predict_false(tx_start_bd->nbytes > hlen)) { 5679 fp->eth_q_stats.tx_ofld_frames_lso_hdr_splits++; 5680 5681 /* split the first BD into header/data making the fw job easy */ 5682 nbds++; 5683 tx_start_bd->nbd = htole16(nbds); 5684 tx_start_bd->nbytes = htole16(hlen); 5685 5686 bd_prod = TX_BD_NEXT(bd_prod); 5687 5688 /* new transmit BD after the tx_parse_bd */ 5689 tx_data_bd = &fp->tx_chain[TX_BD(bd_prod)].reg_bd; 5690 tx_data_bd->addr_hi = htole32(U64_HI(segs[0].ds_addr + hlen)); 5691 tx_data_bd->addr_lo = htole32(U64_LO(segs[0].ds_addr + hlen)); 5692 tx_data_bd->nbytes = htole16(segs[0].ds_len - hlen); 5693 if (tx_total_pkt_size_bd == NULL) { 5694 tx_total_pkt_size_bd = tx_data_bd; 5695 } 5696 5697 BLOGD(sc, DBG_TX, 5698 "TSO split header size is %d (%x:%x) nbds %d\n", 5699 le16toh(tx_start_bd->nbytes), 5700 le32toh(tx_start_bd->addr_hi), 5701 le32toh(tx_start_bd->addr_lo), 5702 nbds); 5703 } 5704 5705 if (!CHIP_IS_E1x(sc)) { 5706 bxe_set_pbd_lso_e2(m0, &pbd_e2_parsing_data); 5707 } else { 5708 bxe_set_pbd_lso(m0, pbd_e1x); 5709 } 5710 } 5711 5712 if (pbd_e2_parsing_data) { 5713 pbd_e2->parsing_data = htole32(pbd_e2_parsing_data); 5714 } 5715 5716 /* prepare remaining BDs, start tx bd contains first seg/frag */ 5717 for (i = 1; i < nsegs ; i++) { 5718 bd_prod = TX_BD_NEXT(bd_prod); 5719 tx_data_bd = &fp->tx_chain[TX_BD(bd_prod)].reg_bd; 5720 tx_data_bd->addr_lo = htole32(U64_LO(segs[i].ds_addr)); 5721 tx_data_bd->addr_hi = htole32(U64_HI(segs[i].ds_addr)); 5722 tx_data_bd->nbytes = htole16(segs[i].ds_len); 5723 if (tx_total_pkt_size_bd == NULL) { 5724 tx_total_pkt_size_bd = tx_data_bd; 5725 } 5726 total_pkt_size += tx_data_bd->nbytes; 5727 } 5728 5729 BLOGD(sc, DBG_TX, "last bd %p\n", tx_data_bd); 5730 5731 if (tx_total_pkt_size_bd != NULL) { 5732 tx_total_pkt_size_bd->total_pkt_bytes = total_pkt_size; 5733 } 5734 5735 if (__predict_false(sc->debug & DBG_TX)) { 5736 tmp_bd = tx_buf->first_bd; 5737 for (i = 0; i < nbds; i++) 5738 { 5739 if (i == 0) { 5740 BLOGD(sc, DBG_TX, 5741 "TX Strt: %p bd=%d nbd=%d vlan=0x%x " 5742 "bd_flags=0x%x hdr_nbds=%d\n", 5743 tx_start_bd, 5744 tmp_bd, 5745 le16toh(tx_start_bd->nbd), 5746 le16toh(tx_start_bd->vlan_or_ethertype), 5747 tx_start_bd->bd_flags.as_bitfield, 5748 (tx_start_bd->general_data & ETH_TX_START_BD_HDR_NBDS)); 5749 } else if (i == 1) { 5750 if (pbd_e1x) { 5751 BLOGD(sc, DBG_TX, 5752 "-> Prse: %p bd=%d global=0x%x ip_hlen_w=%u " 5753 "ip_id=%u lso_mss=%u tcp_flags=0x%x csum=0x%x " 5754 "tcp_seq=%u total_hlen_w=%u\n", 5755 pbd_e1x, 5756 tmp_bd, 5757 pbd_e1x->global_data, 5758 pbd_e1x->ip_hlen_w, 5759 pbd_e1x->ip_id, 5760 pbd_e1x->lso_mss, 5761 pbd_e1x->tcp_flags, 5762 pbd_e1x->tcp_pseudo_csum, 5763 pbd_e1x->tcp_send_seq, 5764 le16toh(pbd_e1x->total_hlen_w)); 5765 } else { /* if (pbd_e2) */ 5766 BLOGD(sc, DBG_TX, 5767 "-> Parse: %p bd=%d dst=%02x:%02x:%02x " 5768 "src=%02x:%02x:%02x parsing_data=0x%x\n", 5769 pbd_e2, 5770 tmp_bd, 5771 pbd_e2->data.mac_addr.dst_hi, 5772 pbd_e2->data.mac_addr.dst_mid, 5773 pbd_e2->data.mac_addr.dst_lo, 5774 pbd_e2->data.mac_addr.src_hi, 5775 pbd_e2->data.mac_addr.src_mid, 5776 pbd_e2->data.mac_addr.src_lo, 5777 pbd_e2->parsing_data); 5778 } 5779 } 5780 5781 if (i != 1) { /* skip parse db as it doesn't hold data */ 5782 tx_data_bd = &fp->tx_chain[TX_BD(tmp_bd)].reg_bd; 5783 BLOGD(sc, DBG_TX, 5784 "-> Frag: %p bd=%d nbytes=%d hi=0x%x lo: 0x%x\n", 5785 tx_data_bd, 5786 tmp_bd, 5787 le16toh(tx_data_bd->nbytes), 5788 le32toh(tx_data_bd->addr_hi), 5789 le32toh(tx_data_bd->addr_lo)); 5790 } 5791 5792 tmp_bd = TX_BD_NEXT(tmp_bd); 5793 } 5794 } 5795 5796 BLOGD(sc, DBG_TX, "doorbell: nbds=%d bd=%u\n", nbds, bd_prod); 5797 5798 /* update TX BD producer index value for next TX */ 5799 bd_prod = TX_BD_NEXT(bd_prod); 5800 5801 /* 5802 * If the chain of tx_bd's describing this frame is adjacent to or spans 5803 * an eth_tx_next_bd element then we need to increment the nbds value. 5804 */ 5805 if (TX_BD_IDX(bd_prod) < nbds) { 5806 nbds++; 5807 } 5808 5809 /* don't allow reordering of writes for nbd and packets */ 5810 mb(); 5811 5812 fp->tx_db.data.prod += nbds; 5813 5814 /* producer points to the next free tx_bd at this point */ 5815 fp->tx_pkt_prod++; 5816 fp->tx_bd_prod = bd_prod; 5817 5818 DOORBELL(sc, fp->index, fp->tx_db.raw); 5819 5820 fp->eth_q_stats.tx_pkts++; 5821 5822 /* Prevent speculative reads from getting ahead of the status block. */ 5823 bus_space_barrier(sc->bar[BAR0].tag, sc->bar[BAR0].handle, 5824 0, 0, BUS_SPACE_BARRIER_READ); 5825 5826 /* Prevent speculative reads from getting ahead of the doorbell. */ 5827 bus_space_barrier(sc->bar[BAR2].tag, sc->bar[BAR2].handle, 5828 0, 0, BUS_SPACE_BARRIER_READ); 5829 5830 return (0); 5831 } 5832 5833 static void 5834 bxe_tx_start_locked(struct bxe_softc *sc, 5835 struct ifnet *ifp, 5836 struct bxe_fastpath *fp) 5837 { 5838 struct mbuf *m = NULL; 5839 int tx_count = 0; 5840 uint16_t tx_bd_avail; 5841 5842 BXE_FP_TX_LOCK_ASSERT(fp); 5843 5844 /* keep adding entries while there are frames to send */ 5845 while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 5846 5847 /* 5848 * check for any frames to send 5849 * dequeue can still be NULL even if queue is not empty 5850 */ 5851 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 5852 if (__predict_false(m == NULL)) { 5853 break; 5854 } 5855 5856 /* the mbuf now belongs to us */ 5857 fp->eth_q_stats.mbuf_alloc_tx++; 5858 5859 /* 5860 * Put the frame into the transmit ring. If we don't have room, 5861 * place the mbuf back at the head of the TX queue, set the 5862 * OACTIVE flag, and wait for the NIC to drain the chain. 5863 */ 5864 if (__predict_false(bxe_tx_encap(fp, &m))) { 5865 fp->eth_q_stats.tx_encap_failures++; 5866 if (m != NULL) { 5867 /* mark the TX queue as full and return the frame */ 5868 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 5869 IFQ_DRV_PREPEND(&ifp->if_snd, m); 5870 fp->eth_q_stats.mbuf_alloc_tx--; 5871 fp->eth_q_stats.tx_queue_xoff++; 5872 } 5873 5874 /* stop looking for more work */ 5875 break; 5876 } 5877 5878 /* the frame was enqueued successfully */ 5879 tx_count++; 5880 5881 /* send a copy of the frame to any BPF listeners. */ 5882 BPF_MTAP(ifp, m); 5883 5884 tx_bd_avail = bxe_tx_avail(sc, fp); 5885 5886 /* handle any completions if we're running low */ 5887 if (tx_bd_avail < BXE_TX_CLEANUP_THRESHOLD) { 5888 /* bxe_txeof will set IFF_DRV_OACTIVE appropriately */ 5889 bxe_txeof(sc, fp); 5890 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) { 5891 break; 5892 } 5893 } 5894 } 5895 5896 /* all TX packets were dequeued and/or the tx ring is full */ 5897 if (tx_count > 0) { 5898 /* reset the TX watchdog timeout timer */ 5899 fp->watchdog_timer = BXE_TX_TIMEOUT; 5900 } 5901 } 5902 5903 /* Legacy (non-RSS) dispatch routine */ 5904 static void 5905 bxe_tx_start(struct ifnet *ifp) 5906 { 5907 struct bxe_softc *sc; 5908 struct bxe_fastpath *fp; 5909 5910 sc = ifp->if_softc; 5911 5912 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 5913 BLOGW(sc, "Interface not running, ignoring transmit request\n"); 5914 return; 5915 } 5916 5917 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) { 5918 BLOGW(sc, "Interface TX queue is full, ignoring transmit request\n"); 5919 return; 5920 } 5921 5922 if (!sc->link_vars.link_up) { 5923 BLOGW(sc, "Interface link is down, ignoring transmit request\n"); 5924 return; 5925 } 5926 5927 fp = &sc->fp[0]; 5928 5929 BXE_FP_TX_LOCK(fp); 5930 bxe_tx_start_locked(sc, ifp, fp); 5931 BXE_FP_TX_UNLOCK(fp); 5932 } 5933 5934 #if __FreeBSD_version >= 800000 5935 5936 static int 5937 bxe_tx_mq_start_locked(struct bxe_softc *sc, 5938 struct ifnet *ifp, 5939 struct bxe_fastpath *fp, 5940 struct mbuf *m) 5941 { 5942 struct buf_ring *tx_br = fp->tx_br; 5943 struct mbuf *next; 5944 int depth, rc, tx_count; 5945 uint16_t tx_bd_avail; 5946 5947 rc = tx_count = 0; 5948 5949 if (!tx_br) { 5950 BLOGE(sc, "Multiqueue TX and no buf_ring!\n"); 5951 return (EINVAL); 5952 } 5953 5954 /* fetch the depth of the driver queue */ 5955 depth = drbr_inuse(ifp, tx_br); 5956 if (depth > fp->eth_q_stats.tx_max_drbr_queue_depth) { 5957 fp->eth_q_stats.tx_max_drbr_queue_depth = depth; 5958 } 5959 5960 BXE_FP_TX_LOCK_ASSERT(fp); 5961 5962 if (m == NULL) { 5963 /* no new work, check for pending frames */ 5964 next = drbr_dequeue(ifp, tx_br); 5965 } else if (drbr_needs_enqueue(ifp, tx_br)) { 5966 /* have both new and pending work, maintain packet order */ 5967 rc = drbr_enqueue(ifp, tx_br, m); 5968 if (rc != 0) { 5969 fp->eth_q_stats.tx_soft_errors++; 5970 goto bxe_tx_mq_start_locked_exit; 5971 } 5972 next = drbr_dequeue(ifp, tx_br); 5973 } else { 5974 /* new work only and nothing pending */ 5975 next = m; 5976 } 5977 5978 /* keep adding entries while there are frames to send */ 5979 while (next != NULL) { 5980 5981 /* the mbuf now belongs to us */ 5982 fp->eth_q_stats.mbuf_alloc_tx++; 5983 5984 /* 5985 * Put the frame into the transmit ring. If we don't have room, 5986 * place the mbuf back at the head of the TX queue, set the 5987 * OACTIVE flag, and wait for the NIC to drain the chain. 5988 */ 5989 rc = bxe_tx_encap(fp, &next); 5990 if (__predict_false(rc != 0)) { 5991 fp->eth_q_stats.tx_encap_failures++; 5992 if (next != NULL) { 5993 /* mark the TX queue as full and save the frame */ 5994 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 5995 /* XXX this may reorder the frame */ 5996 rc = drbr_enqueue(ifp, tx_br, next); 5997 fp->eth_q_stats.mbuf_alloc_tx--; 5998 fp->eth_q_stats.tx_frames_deferred++; 5999 } 6000 6001 /* stop looking for more work */ 6002 break; 6003 } 6004 6005 /* the transmit frame was enqueued successfully */ 6006 tx_count++; 6007 6008 /* send a copy of the frame to any BPF listeners */ 6009 BPF_MTAP(ifp, next); 6010 6011 tx_bd_avail = bxe_tx_avail(sc, fp); 6012 6013 /* handle any completions if we're running low */ 6014 if (tx_bd_avail < BXE_TX_CLEANUP_THRESHOLD) { 6015 /* bxe_txeof will set IFF_DRV_OACTIVE appropriately */ 6016 bxe_txeof(sc, fp); 6017 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) { 6018 break; 6019 } 6020 } 6021 6022 next = drbr_dequeue(ifp, tx_br); 6023 } 6024 6025 /* all TX packets were dequeued and/or the tx ring is full */ 6026 if (tx_count > 0) { 6027 /* reset the TX watchdog timeout timer */ 6028 fp->watchdog_timer = BXE_TX_TIMEOUT; 6029 } 6030 6031 bxe_tx_mq_start_locked_exit: 6032 6033 return (rc); 6034 } 6035 6036 /* Multiqueue (TSS) dispatch routine. */ 6037 static int 6038 bxe_tx_mq_start(struct ifnet *ifp, 6039 struct mbuf *m) 6040 { 6041 struct bxe_softc *sc = ifp->if_softc; 6042 struct bxe_fastpath *fp; 6043 int fp_index, rc; 6044 6045 fp_index = 0; /* default is the first queue */ 6046 6047 /* change the queue if using flow ID */ 6048 if ((m->m_flags & M_FLOWID) != 0) { 6049 fp_index = (m->m_pkthdr.flowid % sc->num_queues); 6050 } 6051 6052 fp = &sc->fp[fp_index]; 6053 6054 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 6055 BLOGW(sc, "Interface not running, ignoring transmit request\n"); 6056 return (ENETDOWN); 6057 } 6058 6059 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) { 6060 BLOGW(sc, "Interface TX queue is full, ignoring transmit request\n"); 6061 return (EBUSY); 6062 } 6063 6064 if (!sc->link_vars.link_up) { 6065 BLOGW(sc, "Interface link is down, ignoring transmit request\n"); 6066 return (ENETDOWN); 6067 } 6068 6069 /* XXX change to TRYLOCK here and if failed then schedule taskqueue */ 6070 6071 BXE_FP_TX_LOCK(fp); 6072 rc = bxe_tx_mq_start_locked(sc, ifp, fp, m); 6073 BXE_FP_TX_UNLOCK(fp); 6074 6075 return (rc); 6076 } 6077 6078 static void 6079 bxe_mq_flush(struct ifnet *ifp) 6080 { 6081 struct bxe_softc *sc = ifp->if_softc; 6082 struct bxe_fastpath *fp; 6083 struct mbuf *m; 6084 int i; 6085 6086 for (i = 0; i < sc->num_queues; i++) { 6087 fp = &sc->fp[i]; 6088 6089 if (fp->state != BXE_FP_STATE_OPEN) { 6090 BLOGD(sc, DBG_LOAD, "Not clearing fp[%02d] buf_ring (state=%d)\n", 6091 fp->index, fp->state); 6092 continue; 6093 } 6094 6095 if (fp->tx_br != NULL) { 6096 BLOGD(sc, DBG_LOAD, "Clearing fp[%02d] buf_ring\n", fp->index); 6097 BXE_FP_TX_LOCK(fp); 6098 while ((m = buf_ring_dequeue_sc(fp->tx_br)) != NULL) { 6099 m_freem(m); 6100 } 6101 BXE_FP_TX_UNLOCK(fp); 6102 } 6103 } 6104 6105 if_qflush(ifp); 6106 } 6107 6108 #endif /* FreeBSD_version >= 800000 */ 6109 6110 static uint16_t 6111 bxe_cid_ilt_lines(struct bxe_softc *sc) 6112 { 6113 if (IS_SRIOV(sc)) { 6114 return ((BXE_FIRST_VF_CID + BXE_VF_CIDS) / ILT_PAGE_CIDS); 6115 } 6116 return (L2_ILT_LINES(sc)); 6117 } 6118 6119 static void 6120 bxe_ilt_set_info(struct bxe_softc *sc) 6121 { 6122 struct ilt_client_info *ilt_client; 6123 struct ecore_ilt *ilt = sc->ilt; 6124 uint16_t line = 0; 6125 6126 ilt->start_line = FUNC_ILT_BASE(SC_FUNC(sc)); 6127 BLOGD(sc, DBG_LOAD, "ilt starts at line %d\n", ilt->start_line); 6128 6129 /* CDU */ 6130 ilt_client = &ilt->clients[ILT_CLIENT_CDU]; 6131 ilt_client->client_num = ILT_CLIENT_CDU; 6132 ilt_client->page_size = CDU_ILT_PAGE_SZ; 6133 ilt_client->flags = ILT_CLIENT_SKIP_MEM; 6134 ilt_client->start = line; 6135 line += bxe_cid_ilt_lines(sc); 6136 6137 if (CNIC_SUPPORT(sc)) { 6138 line += CNIC_ILT_LINES; 6139 } 6140 6141 ilt_client->end = (line - 1); 6142 6143 BLOGD(sc, DBG_LOAD, 6144 "ilt client[CDU]: start %d, end %d, " 6145 "psz 0x%x, flags 0x%x, hw psz %d\n", 6146 ilt_client->start, ilt_client->end, 6147 ilt_client->page_size, 6148 ilt_client->flags, 6149 ilog2(ilt_client->page_size >> 12)); 6150 6151 /* QM */ 6152 if (QM_INIT(sc->qm_cid_count)) { 6153 ilt_client = &ilt->clients[ILT_CLIENT_QM]; 6154 ilt_client->client_num = ILT_CLIENT_QM; 6155 ilt_client->page_size = QM_ILT_PAGE_SZ; 6156 ilt_client->flags = 0; 6157 ilt_client->start = line; 6158 6159 /* 4 bytes for each cid */ 6160 line += DIV_ROUND_UP(sc->qm_cid_count * QM_QUEUES_PER_FUNC * 4, 6161 QM_ILT_PAGE_SZ); 6162 6163 ilt_client->end = (line - 1); 6164 6165 BLOGD(sc, DBG_LOAD, 6166 "ilt client[QM]: start %d, end %d, " 6167 "psz 0x%x, flags 0x%x, hw psz %d\n", 6168 ilt_client->start, ilt_client->end, 6169 ilt_client->page_size, ilt_client->flags, 6170 ilog2(ilt_client->page_size >> 12)); 6171 } 6172 6173 if (CNIC_SUPPORT(sc)) { 6174 /* SRC */ 6175 ilt_client = &ilt->clients[ILT_CLIENT_SRC]; 6176 ilt_client->client_num = ILT_CLIENT_SRC; 6177 ilt_client->page_size = SRC_ILT_PAGE_SZ; 6178 ilt_client->flags = 0; 6179 ilt_client->start = line; 6180 line += SRC_ILT_LINES; 6181 ilt_client->end = (line - 1); 6182 6183 BLOGD(sc, DBG_LOAD, 6184 "ilt client[SRC]: start %d, end %d, " 6185 "psz 0x%x, flags 0x%x, hw psz %d\n", 6186 ilt_client->start, ilt_client->end, 6187 ilt_client->page_size, ilt_client->flags, 6188 ilog2(ilt_client->page_size >> 12)); 6189 6190 /* TM */ 6191 ilt_client = &ilt->clients[ILT_CLIENT_TM]; 6192 ilt_client->client_num = ILT_CLIENT_TM; 6193 ilt_client->page_size = TM_ILT_PAGE_SZ; 6194 ilt_client->flags = 0; 6195 ilt_client->start = line; 6196 line += TM_ILT_LINES; 6197 ilt_client->end = (line - 1); 6198 6199 BLOGD(sc, DBG_LOAD, 6200 "ilt client[TM]: start %d, end %d, " 6201 "psz 0x%x, flags 0x%x, hw psz %d\n", 6202 ilt_client->start, ilt_client->end, 6203 ilt_client->page_size, ilt_client->flags, 6204 ilog2(ilt_client->page_size >> 12)); 6205 } 6206 6207 KASSERT((line <= ILT_MAX_LINES), ("Invalid number of ILT lines!")); 6208 } 6209 6210 static void 6211 bxe_set_fp_rx_buf_size(struct bxe_softc *sc) 6212 { 6213 int i; 6214 6215 BLOGD(sc, DBG_LOAD, "mtu = %d\n", sc->mtu); 6216 6217 for (i = 0; i < sc->num_queues; i++) { 6218 /* get the Rx buffer size for RX frames */ 6219 sc->fp[i].rx_buf_size = 6220 (IP_HEADER_ALIGNMENT_PADDING + 6221 ETH_OVERHEAD + 6222 sc->mtu); 6223 6224 BLOGD(sc, DBG_LOAD, "rx_buf_size for fp[%02d] = %d\n", 6225 i, sc->fp[i].rx_buf_size); 6226 6227 /* get the mbuf allocation size for RX frames */ 6228 if (sc->fp[i].rx_buf_size <= MCLBYTES) { 6229 sc->fp[i].mbuf_alloc_size = MCLBYTES; 6230 } else if (sc->fp[i].rx_buf_size <= BCM_PAGE_SIZE) { 6231 sc->fp[i].mbuf_alloc_size = PAGE_SIZE; 6232 } else { 6233 sc->fp[i].mbuf_alloc_size = MJUM9BYTES; 6234 } 6235 6236 BLOGD(sc, DBG_LOAD, "mbuf_alloc_size for fp[%02d] = %d\n", 6237 i, sc->fp[i].mbuf_alloc_size); 6238 } 6239 } 6240 6241 static int 6242 bxe_alloc_ilt_mem(struct bxe_softc *sc) 6243 { 6244 int rc = 0; 6245 6246 if ((sc->ilt = 6247 (struct ecore_ilt *)malloc(sizeof(struct ecore_ilt), 6248 M_BXE_ILT, 6249 (M_NOWAIT | M_ZERO))) == NULL) { 6250 rc = 1; 6251 } 6252 6253 return (rc); 6254 } 6255 6256 static int 6257 bxe_alloc_ilt_lines_mem(struct bxe_softc *sc) 6258 { 6259 int rc = 0; 6260 6261 if ((sc->ilt->lines = 6262 (struct ilt_line *)malloc((sizeof(struct ilt_line) * ILT_MAX_LINES), 6263 M_BXE_ILT, 6264 (M_NOWAIT | M_ZERO))) == NULL) { 6265 rc = 1; 6266 } 6267 6268 return (rc); 6269 } 6270 6271 static void 6272 bxe_free_ilt_mem(struct bxe_softc *sc) 6273 { 6274 if (sc->ilt != NULL) { 6275 free(sc->ilt, M_BXE_ILT); 6276 sc->ilt = NULL; 6277 } 6278 } 6279 6280 static void 6281 bxe_free_ilt_lines_mem(struct bxe_softc *sc) 6282 { 6283 if (sc->ilt->lines != NULL) { 6284 free(sc->ilt->lines, M_BXE_ILT); 6285 sc->ilt->lines = NULL; 6286 } 6287 } 6288 6289 static void 6290 bxe_free_mem(struct bxe_softc *sc) 6291 { 6292 int i; 6293 6294 #if 0 6295 if (!CONFIGURE_NIC_MODE(sc)) { 6296 /* free searcher T2 table */ 6297 bxe_dma_free(sc, &sc->t2); 6298 } 6299 #endif 6300 6301 for (i = 0; i < L2_ILT_LINES(sc); i++) { 6302 bxe_dma_free(sc, &sc->context[i].vcxt_dma); 6303 sc->context[i].vcxt = NULL; 6304 sc->context[i].size = 0; 6305 } 6306 6307 ecore_ilt_mem_op(sc, ILT_MEMOP_FREE); 6308 6309 bxe_free_ilt_lines_mem(sc); 6310 6311 #if 0 6312 bxe_iov_free_mem(sc); 6313 #endif 6314 } 6315 6316 static int 6317 bxe_alloc_mem(struct bxe_softc *sc) 6318 { 6319 int context_size; 6320 int allocated; 6321 int i; 6322 6323 #if 0 6324 if (!CONFIGURE_NIC_MODE(sc)) { 6325 /* allocate searcher T2 table */ 6326 if (bxe_dma_alloc(sc, SRC_T2_SZ, 6327 &sc->t2, "searcher t2 table") != 0) { 6328 return (-1); 6329 } 6330 } 6331 #endif 6332 6333 /* 6334 * Allocate memory for CDU context: 6335 * This memory is allocated separately and not in the generic ILT 6336 * functions because CDU differs in few aspects: 6337 * 1. There can be multiple entities allocating memory for context - 6338 * regular L2, CNIC, and SRIOV drivers. Each separately controls 6339 * its own ILT lines. 6340 * 2. Since CDU page-size is not a single 4KB page (which is the case 6341 * for the other ILT clients), to be efficient we want to support 6342 * allocation of sub-page-size in the last entry. 6343 * 3. Context pointers are used by the driver to pass to FW / update 6344 * the context (for the other ILT clients the pointers are used just to 6345 * free the memory during unload). 6346 */ 6347 context_size = (sizeof(union cdu_context) * BXE_L2_CID_COUNT(sc)); 6348 for (i = 0, allocated = 0; allocated < context_size; i++) { 6349 sc->context[i].size = min(CDU_ILT_PAGE_SZ, 6350 (context_size - allocated)); 6351 6352 if (bxe_dma_alloc(sc, sc->context[i].size, 6353 &sc->context[i].vcxt_dma, 6354 "cdu context") != 0) { 6355 bxe_free_mem(sc); 6356 return (-1); 6357 } 6358 6359 sc->context[i].vcxt = 6360 (union cdu_context *)sc->context[i].vcxt_dma.vaddr; 6361 6362 allocated += sc->context[i].size; 6363 } 6364 6365 bxe_alloc_ilt_lines_mem(sc); 6366 6367 BLOGD(sc, DBG_LOAD, "ilt=%p start_line=%u lines=%p\n", 6368 sc->ilt, sc->ilt->start_line, sc->ilt->lines); 6369 { 6370 for (i = 0; i < 4; i++) { 6371 BLOGD(sc, DBG_LOAD, 6372 "c%d page_size=%u start=%u end=%u num=%u flags=0x%x\n", 6373 i, 6374 sc->ilt->clients[i].page_size, 6375 sc->ilt->clients[i].start, 6376 sc->ilt->clients[i].end, 6377 sc->ilt->clients[i].client_num, 6378 sc->ilt->clients[i].flags); 6379 } 6380 } 6381 if (ecore_ilt_mem_op(sc, ILT_MEMOP_ALLOC)) { 6382 BLOGE(sc, "ecore_ilt_mem_op ILT_MEMOP_ALLOC failed\n"); 6383 bxe_free_mem(sc); 6384 return (-1); 6385 } 6386 6387 #if 0 6388 if (bxe_iov_alloc_mem(sc)) { 6389 BLOGE(sc, "Failed to allocate memory for SRIOV\n"); 6390 bxe_free_mem(sc); 6391 return (-1); 6392 } 6393 #endif 6394 6395 return (0); 6396 } 6397 6398 static void 6399 bxe_free_rx_bd_chain(struct bxe_fastpath *fp) 6400 { 6401 struct bxe_softc *sc; 6402 int i; 6403 6404 sc = fp->sc; 6405 6406 if (fp->rx_mbuf_tag == NULL) { 6407 return; 6408 } 6409 6410 /* free all mbufs and unload all maps */ 6411 for (i = 0; i < RX_BD_TOTAL; i++) { 6412 if (fp->rx_mbuf_chain[i].m_map != NULL) { 6413 bus_dmamap_sync(fp->rx_mbuf_tag, 6414 fp->rx_mbuf_chain[i].m_map, 6415 BUS_DMASYNC_POSTREAD); 6416 bus_dmamap_unload(fp->rx_mbuf_tag, 6417 fp->rx_mbuf_chain[i].m_map); 6418 } 6419 6420 if (fp->rx_mbuf_chain[i].m != NULL) { 6421 m_freem(fp->rx_mbuf_chain[i].m); 6422 fp->rx_mbuf_chain[i].m = NULL; 6423 fp->eth_q_stats.mbuf_alloc_rx--; 6424 } 6425 } 6426 } 6427 6428 static void 6429 bxe_free_tpa_pool(struct bxe_fastpath *fp) 6430 { 6431 struct bxe_softc *sc; 6432 int i, max_agg_queues; 6433 6434 sc = fp->sc; 6435 6436 if (fp->rx_mbuf_tag == NULL) { 6437 return; 6438 } 6439 6440 max_agg_queues = MAX_AGG_QS(sc); 6441 6442 /* release all mbufs and unload all DMA maps in the TPA pool */ 6443 for (i = 0; i < max_agg_queues; i++) { 6444 if (fp->rx_tpa_info[i].bd.m_map != NULL) { 6445 bus_dmamap_sync(fp->rx_mbuf_tag, 6446 fp->rx_tpa_info[i].bd.m_map, 6447 BUS_DMASYNC_POSTREAD); 6448 bus_dmamap_unload(fp->rx_mbuf_tag, 6449 fp->rx_tpa_info[i].bd.m_map); 6450 } 6451 6452 if (fp->rx_tpa_info[i].bd.m != NULL) { 6453 m_freem(fp->rx_tpa_info[i].bd.m); 6454 fp->rx_tpa_info[i].bd.m = NULL; 6455 fp->eth_q_stats.mbuf_alloc_tpa--; 6456 } 6457 } 6458 } 6459 6460 static void 6461 bxe_free_sge_chain(struct bxe_fastpath *fp) 6462 { 6463 struct bxe_softc *sc; 6464 int i; 6465 6466 sc = fp->sc; 6467 6468 if (fp->rx_sge_mbuf_tag == NULL) { 6469 return; 6470 } 6471 6472 /* rree all mbufs and unload all maps */ 6473 for (i = 0; i < RX_SGE_TOTAL; i++) { 6474 if (fp->rx_sge_mbuf_chain[i].m_map != NULL) { 6475 bus_dmamap_sync(fp->rx_sge_mbuf_tag, 6476 fp->rx_sge_mbuf_chain[i].m_map, 6477 BUS_DMASYNC_POSTREAD); 6478 bus_dmamap_unload(fp->rx_sge_mbuf_tag, 6479 fp->rx_sge_mbuf_chain[i].m_map); 6480 } 6481 6482 if (fp->rx_sge_mbuf_chain[i].m != NULL) { 6483 m_freem(fp->rx_sge_mbuf_chain[i].m); 6484 fp->rx_sge_mbuf_chain[i].m = NULL; 6485 fp->eth_q_stats.mbuf_alloc_sge--; 6486 } 6487 } 6488 } 6489 6490 static void 6491 bxe_free_fp_buffers(struct bxe_softc *sc) 6492 { 6493 struct bxe_fastpath *fp; 6494 int i; 6495 6496 for (i = 0; i < sc->num_queues; i++) { 6497 fp = &sc->fp[i]; 6498 6499 #if __FreeBSD_version >= 800000 6500 if (fp->tx_br != NULL) { 6501 struct mbuf *m; 6502 /* just in case bxe_mq_flush() wasn't called */ 6503 while ((m = buf_ring_dequeue_sc(fp->tx_br)) != NULL) { 6504 m_freem(m); 6505 } 6506 buf_ring_free(fp->tx_br, M_DEVBUF); 6507 fp->tx_br = NULL; 6508 } 6509 #endif 6510 6511 /* free all RX buffers */ 6512 bxe_free_rx_bd_chain(fp); 6513 bxe_free_tpa_pool(fp); 6514 bxe_free_sge_chain(fp); 6515 6516 if (fp->eth_q_stats.mbuf_alloc_rx != 0) { 6517 BLOGE(sc, "failed to claim all rx mbufs (%d left)\n", 6518 fp->eth_q_stats.mbuf_alloc_rx); 6519 } 6520 6521 if (fp->eth_q_stats.mbuf_alloc_sge != 0) { 6522 BLOGE(sc, "failed to claim all sge mbufs (%d left)\n", 6523 fp->eth_q_stats.mbuf_alloc_sge); 6524 } 6525 6526 if (fp->eth_q_stats.mbuf_alloc_tpa != 0) { 6527 BLOGE(sc, "failed to claim all sge mbufs (%d left)\n", 6528 fp->eth_q_stats.mbuf_alloc_tpa); 6529 } 6530 6531 if (fp->eth_q_stats.mbuf_alloc_tx != 0) { 6532 BLOGE(sc, "failed to release tx mbufs (%d left)\n", 6533 fp->eth_q_stats.mbuf_alloc_tx); 6534 } 6535 6536 /* XXX verify all mbufs were reclaimed */ 6537 6538 if (mtx_initialized(&fp->tx_mtx)) { 6539 mtx_destroy(&fp->tx_mtx); 6540 } 6541 6542 if (mtx_initialized(&fp->rx_mtx)) { 6543 mtx_destroy(&fp->rx_mtx); 6544 } 6545 } 6546 } 6547 6548 static int 6549 bxe_alloc_rx_bd_mbuf(struct bxe_fastpath *fp, 6550 uint16_t prev_index, 6551 uint16_t index) 6552 { 6553 struct bxe_sw_rx_bd *rx_buf; 6554 struct eth_rx_bd *rx_bd; 6555 bus_dma_segment_t segs[1]; 6556 bus_dmamap_t map; 6557 struct mbuf *m; 6558 int nsegs, rc; 6559 6560 rc = 0; 6561 6562 /* allocate the new RX BD mbuf */ 6563 m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, fp->mbuf_alloc_size); 6564 if (__predict_false(m == NULL)) { 6565 fp->eth_q_stats.mbuf_rx_bd_alloc_failed++; 6566 return (ENOBUFS); 6567 } 6568 6569 fp->eth_q_stats.mbuf_alloc_rx++; 6570 6571 /* initialize the mbuf buffer length */ 6572 m->m_pkthdr.len = m->m_len = fp->rx_buf_size; 6573 6574 /* map the mbuf into non-paged pool */ 6575 rc = bus_dmamap_load_mbuf_sg(fp->rx_mbuf_tag, 6576 fp->rx_mbuf_spare_map, 6577 m, segs, &nsegs, BUS_DMA_NOWAIT); 6578 if (__predict_false(rc != 0)) { 6579 fp->eth_q_stats.mbuf_rx_bd_mapping_failed++; 6580 m_freem(m); 6581 fp->eth_q_stats.mbuf_alloc_rx--; 6582 return (rc); 6583 } 6584 6585 /* all mbufs must map to a single segment */ 6586 KASSERT((nsegs == 1), ("Too many segments, %d returned!", nsegs)); 6587 6588 /* release any existing RX BD mbuf mappings */ 6589 6590 if (prev_index != index) { 6591 rx_buf = &fp->rx_mbuf_chain[prev_index]; 6592 6593 if (rx_buf->m_map != NULL) { 6594 bus_dmamap_sync(fp->rx_mbuf_tag, rx_buf->m_map, 6595 BUS_DMASYNC_POSTREAD); 6596 bus_dmamap_unload(fp->rx_mbuf_tag, rx_buf->m_map); 6597 } 6598 6599 /* 6600 * We only get here from bxe_rxeof() when the maximum number 6601 * of rx buffers is less than RX_BD_USABLE. bxe_rxeof() already 6602 * holds the mbuf in the prev_index so it's OK to NULL it out 6603 * here without concern of a memory leak. 6604 */ 6605 fp->rx_mbuf_chain[prev_index].m = NULL; 6606 } 6607 6608 rx_buf = &fp->rx_mbuf_chain[index]; 6609 6610 if (rx_buf->m_map != NULL) { 6611 bus_dmamap_sync(fp->rx_mbuf_tag, rx_buf->m_map, 6612 BUS_DMASYNC_POSTREAD); 6613 bus_dmamap_unload(fp->rx_mbuf_tag, rx_buf->m_map); 6614 } 6615 6616 /* save the mbuf and mapping info for a future packet */ 6617 map = (prev_index != index) ? 6618 fp->rx_mbuf_chain[prev_index].m_map : rx_buf->m_map; 6619 rx_buf->m_map = fp->rx_mbuf_spare_map; 6620 fp->rx_mbuf_spare_map = map; 6621 bus_dmamap_sync(fp->rx_mbuf_tag, rx_buf->m_map, 6622 BUS_DMASYNC_PREREAD); 6623 rx_buf->m = m; 6624 6625 rx_bd = &fp->rx_chain[index]; 6626 rx_bd->addr_hi = htole32(U64_HI(segs[0].ds_addr)); 6627 rx_bd->addr_lo = htole32(U64_LO(segs[0].ds_addr)); 6628 6629 return (rc); 6630 } 6631 6632 static int 6633 bxe_alloc_rx_tpa_mbuf(struct bxe_fastpath *fp, 6634 int queue) 6635 { 6636 struct bxe_sw_tpa_info *tpa_info = &fp->rx_tpa_info[queue]; 6637 bus_dma_segment_t segs[1]; 6638 bus_dmamap_t map; 6639 struct mbuf *m; 6640 int nsegs; 6641 int rc = 0; 6642 6643 /* allocate the new TPA mbuf */ 6644 m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, fp->mbuf_alloc_size); 6645 if (__predict_false(m == NULL)) { 6646 fp->eth_q_stats.mbuf_rx_tpa_alloc_failed++; 6647 return (ENOBUFS); 6648 } 6649 6650 fp->eth_q_stats.mbuf_alloc_tpa++; 6651 6652 /* initialize the mbuf buffer length */ 6653 m->m_pkthdr.len = m->m_len = fp->rx_buf_size; 6654 6655 /* map the mbuf into non-paged pool */ 6656 rc = bus_dmamap_load_mbuf_sg(fp->rx_mbuf_tag, 6657 fp->rx_tpa_info_mbuf_spare_map, 6658 m, segs, &nsegs, BUS_DMA_NOWAIT); 6659 if (__predict_false(rc != 0)) { 6660 fp->eth_q_stats.mbuf_rx_tpa_mapping_failed++; 6661 m_free(m); 6662 fp->eth_q_stats.mbuf_alloc_tpa--; 6663 return (rc); 6664 } 6665 6666 /* all mbufs must map to a single segment */ 6667 KASSERT((nsegs == 1), ("Too many segments, %d returned!", nsegs)); 6668 6669 /* release any existing TPA mbuf mapping */ 6670 if (tpa_info->bd.m_map != NULL) { 6671 bus_dmamap_sync(fp->rx_mbuf_tag, tpa_info->bd.m_map, 6672 BUS_DMASYNC_POSTREAD); 6673 bus_dmamap_unload(fp->rx_mbuf_tag, tpa_info->bd.m_map); 6674 } 6675 6676 /* save the mbuf and mapping info for the TPA mbuf */ 6677 map = tpa_info->bd.m_map; 6678 tpa_info->bd.m_map = fp->rx_tpa_info_mbuf_spare_map; 6679 fp->rx_tpa_info_mbuf_spare_map = map; 6680 bus_dmamap_sync(fp->rx_mbuf_tag, tpa_info->bd.m_map, 6681 BUS_DMASYNC_PREREAD); 6682 tpa_info->bd.m = m; 6683 tpa_info->seg = segs[0]; 6684 6685 return (rc); 6686 } 6687 6688 /* 6689 * Allocate an mbuf and assign it to the receive scatter gather chain. The 6690 * caller must take care to save a copy of the existing mbuf in the SG mbuf 6691 * chain. 6692 */ 6693 static int 6694 bxe_alloc_rx_sge_mbuf(struct bxe_fastpath *fp, 6695 uint16_t index) 6696 { 6697 struct bxe_sw_rx_bd *sge_buf; 6698 struct eth_rx_sge *sge; 6699 bus_dma_segment_t segs[1]; 6700 bus_dmamap_t map; 6701 struct mbuf *m; 6702 int nsegs; 6703 int rc = 0; 6704 6705 /* allocate a new SGE mbuf */ 6706 m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, SGE_PAGE_SIZE); 6707 if (__predict_false(m == NULL)) { 6708 fp->eth_q_stats.mbuf_rx_sge_alloc_failed++; 6709 return (ENOMEM); 6710 } 6711 6712 fp->eth_q_stats.mbuf_alloc_sge++; 6713 6714 /* initialize the mbuf buffer length */ 6715 m->m_pkthdr.len = m->m_len = SGE_PAGE_SIZE; 6716 6717 /* map the SGE mbuf into non-paged pool */ 6718 rc = bus_dmamap_load_mbuf_sg(fp->rx_sge_mbuf_tag, 6719 fp->rx_sge_mbuf_spare_map, 6720 m, segs, &nsegs, BUS_DMA_NOWAIT); 6721 if (__predict_false(rc != 0)) { 6722 fp->eth_q_stats.mbuf_rx_sge_mapping_failed++; 6723 m_freem(m); 6724 fp->eth_q_stats.mbuf_alloc_sge--; 6725 return (rc); 6726 } 6727 6728 /* all mbufs must map to a single segment */ 6729 KASSERT((nsegs == 1), ("Too many segments, %d returned!", nsegs)); 6730 6731 sge_buf = &fp->rx_sge_mbuf_chain[index]; 6732 6733 /* release any existing SGE mbuf mapping */ 6734 if (sge_buf->m_map != NULL) { 6735 bus_dmamap_sync(fp->rx_sge_mbuf_tag, sge_buf->m_map, 6736 BUS_DMASYNC_POSTREAD); 6737 bus_dmamap_unload(fp->rx_sge_mbuf_tag, sge_buf->m_map); 6738 } 6739 6740 /* save the mbuf and mapping info for a future packet */ 6741 map = sge_buf->m_map; 6742 sge_buf->m_map = fp->rx_sge_mbuf_spare_map; 6743 fp->rx_sge_mbuf_spare_map = map; 6744 bus_dmamap_sync(fp->rx_sge_mbuf_tag, sge_buf->m_map, 6745 BUS_DMASYNC_PREREAD); 6746 sge_buf->m = m; 6747 6748 sge = &fp->rx_sge_chain[index]; 6749 sge->addr_hi = htole32(U64_HI(segs[0].ds_addr)); 6750 sge->addr_lo = htole32(U64_LO(segs[0].ds_addr)); 6751 6752 return (rc); 6753 } 6754 6755 static __noinline int 6756 bxe_alloc_fp_buffers(struct bxe_softc *sc) 6757 { 6758 struct bxe_fastpath *fp; 6759 int i, j, rc = 0; 6760 int ring_prod, cqe_ring_prod; 6761 int max_agg_queues; 6762 6763 for (i = 0; i < sc->num_queues; i++) { 6764 fp = &sc->fp[i]; 6765 6766 #if __FreeBSD_version >= 800000 6767 fp->tx_br = buf_ring_alloc(BXE_BR_SIZE, M_DEVBUF, 6768 M_NOWAIT, &fp->tx_mtx); 6769 if (fp->tx_br == NULL) { 6770 BLOGE(sc, "buf_ring alloc fail for fp[%02d]\n", i); 6771 goto bxe_alloc_fp_buffers_error; 6772 } 6773 #endif 6774 6775 ring_prod = cqe_ring_prod = 0; 6776 fp->rx_bd_cons = 0; 6777 fp->rx_cq_cons = 0; 6778 6779 /* allocate buffers for the RX BDs in RX BD chain */ 6780 for (j = 0; j < sc->max_rx_bufs; j++) { 6781 rc = bxe_alloc_rx_bd_mbuf(fp, ring_prod, ring_prod); 6782 if (rc != 0) { 6783 BLOGE(sc, "mbuf alloc fail for fp[%02d] rx chain (%d)\n", 6784 i, rc); 6785 goto bxe_alloc_fp_buffers_error; 6786 } 6787 6788 ring_prod = RX_BD_NEXT(ring_prod); 6789 cqe_ring_prod = RCQ_NEXT(cqe_ring_prod); 6790 } 6791 6792 fp->rx_bd_prod = ring_prod; 6793 fp->rx_cq_prod = cqe_ring_prod; 6794 fp->eth_q_stats.rx_calls = fp->eth_q_stats.rx_pkts = 0; 6795 6796 if (sc->ifnet->if_capenable & IFCAP_LRO) { 6797 max_agg_queues = MAX_AGG_QS(sc); 6798 6799 fp->tpa_enable = TRUE; 6800 6801 /* fill the TPA pool */ 6802 for (j = 0; j < max_agg_queues; j++) { 6803 rc = bxe_alloc_rx_tpa_mbuf(fp, j); 6804 if (rc != 0) { 6805 BLOGE(sc, "mbuf alloc fail for fp[%02d] TPA queue %d\n", 6806 i, j); 6807 fp->tpa_enable = FALSE; 6808 goto bxe_alloc_fp_buffers_error; 6809 } 6810 6811 fp->rx_tpa_info[j].state = BXE_TPA_STATE_STOP; 6812 } 6813 6814 if (fp->tpa_enable) { 6815 /* fill the RX SGE chain */ 6816 ring_prod = 0; 6817 for (j = 0; j < RX_SGE_USABLE; j++) { 6818 rc = bxe_alloc_rx_sge_mbuf(fp, ring_prod); 6819 if (rc != 0) { 6820 BLOGE(sc, "mbuf alloc fail for fp[%02d] SGE %d\n", 6821 i, ring_prod); 6822 fp->tpa_enable = FALSE; 6823 ring_prod = 0; 6824 goto bxe_alloc_fp_buffers_error; 6825 } 6826 6827 ring_prod = RX_SGE_NEXT(ring_prod); 6828 } 6829 6830 fp->rx_sge_prod = ring_prod; 6831 } 6832 } 6833 } 6834 6835 return (0); 6836 6837 bxe_alloc_fp_buffers_error: 6838 6839 /* unwind what was already allocated */ 6840 bxe_free_rx_bd_chain(fp); 6841 bxe_free_tpa_pool(fp); 6842 bxe_free_sge_chain(fp); 6843 6844 return (ENOBUFS); 6845 } 6846 6847 static void 6848 bxe_free_fw_stats_mem(struct bxe_softc *sc) 6849 { 6850 bxe_dma_free(sc, &sc->fw_stats_dma); 6851 6852 sc->fw_stats_num = 0; 6853 6854 sc->fw_stats_req_size = 0; 6855 sc->fw_stats_req = NULL; 6856 sc->fw_stats_req_mapping = 0; 6857 6858 sc->fw_stats_data_size = 0; 6859 sc->fw_stats_data = NULL; 6860 sc->fw_stats_data_mapping = 0; 6861 } 6862 6863 static int 6864 bxe_alloc_fw_stats_mem(struct bxe_softc *sc) 6865 { 6866 uint8_t num_queue_stats; 6867 int num_groups; 6868 6869 /* number of queues for statistics is number of eth queues */ 6870 num_queue_stats = BXE_NUM_ETH_QUEUES(sc); 6871 6872 /* 6873 * Total number of FW statistics requests = 6874 * 1 for port stats + 1 for PF stats + num of queues 6875 */ 6876 sc->fw_stats_num = (2 + num_queue_stats); 6877 6878 /* 6879 * Request is built from stats_query_header and an array of 6880 * stats_query_cmd_group each of which contains STATS_QUERY_CMD_COUNT 6881 * rules. The real number or requests is configured in the 6882 * stats_query_header. 6883 */ 6884 num_groups = 6885 ((sc->fw_stats_num / STATS_QUERY_CMD_COUNT) + 6886 ((sc->fw_stats_num % STATS_QUERY_CMD_COUNT) ? 1 : 0)); 6887 6888 BLOGD(sc, DBG_LOAD, "stats fw_stats_num %d num_groups %d\n", 6889 sc->fw_stats_num, num_groups); 6890 6891 sc->fw_stats_req_size = 6892 (sizeof(struct stats_query_header) + 6893 (num_groups * sizeof(struct stats_query_cmd_group))); 6894 6895 /* 6896 * Data for statistics requests + stats_counter. 6897 * stats_counter holds per-STORM counters that are incremented when 6898 * STORM has finished with the current request. Memory for FCoE 6899 * offloaded statistics are counted anyway, even if they will not be sent. 6900 * VF stats are not accounted for here as the data of VF stats is stored 6901 * in memory allocated by the VF, not here. 6902 */ 6903 sc->fw_stats_data_size = 6904 (sizeof(struct stats_counter) + 6905 sizeof(struct per_port_stats) + 6906 sizeof(struct per_pf_stats) + 6907 /* sizeof(struct fcoe_statistics_params) + */ 6908 (sizeof(struct per_queue_stats) * num_queue_stats)); 6909 6910 if (bxe_dma_alloc(sc, (sc->fw_stats_req_size + sc->fw_stats_data_size), 6911 &sc->fw_stats_dma, "fw stats") != 0) { 6912 bxe_free_fw_stats_mem(sc); 6913 return (-1); 6914 } 6915 6916 /* set up the shortcuts */ 6917 6918 sc->fw_stats_req = 6919 (struct bxe_fw_stats_req *)sc->fw_stats_dma.vaddr; 6920 sc->fw_stats_req_mapping = sc->fw_stats_dma.paddr; 6921 6922 sc->fw_stats_data = 6923 (struct bxe_fw_stats_data *)((uint8_t *)sc->fw_stats_dma.vaddr + 6924 sc->fw_stats_req_size); 6925 sc->fw_stats_data_mapping = (sc->fw_stats_dma.paddr + 6926 sc->fw_stats_req_size); 6927 6928 BLOGD(sc, DBG_LOAD, "statistics request base address set to %#jx\n", 6929 (uintmax_t)sc->fw_stats_req_mapping); 6930 6931 BLOGD(sc, DBG_LOAD, "statistics data base address set to %#jx\n", 6932 (uintmax_t)sc->fw_stats_data_mapping); 6933 6934 return (0); 6935 } 6936 6937 /* 6938 * Bits map: 6939 * 0-7 - Engine0 load counter. 6940 * 8-15 - Engine1 load counter. 6941 * 16 - Engine0 RESET_IN_PROGRESS bit. 6942 * 17 - Engine1 RESET_IN_PROGRESS bit. 6943 * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active 6944 * function on the engine 6945 * 19 - Engine1 ONE_IS_LOADED. 6946 * 20 - Chip reset flow bit. When set none-leader must wait for both engines 6947 * leader to complete (check for both RESET_IN_PROGRESS bits and not 6948 * for just the one belonging to its engine). 6949 */ 6950 #define BXE_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1 6951 #define BXE_PATH0_LOAD_CNT_MASK 0x000000ff 6952 #define BXE_PATH0_LOAD_CNT_SHIFT 0 6953 #define BXE_PATH1_LOAD_CNT_MASK 0x0000ff00 6954 #define BXE_PATH1_LOAD_CNT_SHIFT 8 6955 #define BXE_PATH0_RST_IN_PROG_BIT 0x00010000 6956 #define BXE_PATH1_RST_IN_PROG_BIT 0x00020000 6957 #define BXE_GLOBAL_RESET_BIT 0x00040000 6958 6959 /* set the GLOBAL_RESET bit, should be run under rtnl lock */ 6960 static void 6961 bxe_set_reset_global(struct bxe_softc *sc) 6962 { 6963 uint32_t val; 6964 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG); 6965 val = REG_RD(sc, BXE_RECOVERY_GLOB_REG); 6966 REG_WR(sc, BXE_RECOVERY_GLOB_REG, val | BXE_GLOBAL_RESET_BIT); 6967 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG); 6968 } 6969 6970 /* clear the GLOBAL_RESET bit, should be run under rtnl lock */ 6971 static void 6972 bxe_clear_reset_global(struct bxe_softc *sc) 6973 { 6974 uint32_t val; 6975 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG); 6976 val = REG_RD(sc, BXE_RECOVERY_GLOB_REG); 6977 REG_WR(sc, BXE_RECOVERY_GLOB_REG, val & (~BXE_GLOBAL_RESET_BIT)); 6978 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG); 6979 } 6980 6981 /* checks the GLOBAL_RESET bit, should be run under rtnl lock */ 6982 static uint8_t 6983 bxe_reset_is_global(struct bxe_softc *sc) 6984 { 6985 uint32_t val = REG_RD(sc, BXE_RECOVERY_GLOB_REG); 6986 BLOGD(sc, DBG_LOAD, "GLOB_REG=0x%08x\n", val); 6987 return (val & BXE_GLOBAL_RESET_BIT) ? TRUE : FALSE; 6988 } 6989 6990 /* clear RESET_IN_PROGRESS bit for the engine, should be run under rtnl lock */ 6991 static void 6992 bxe_set_reset_done(struct bxe_softc *sc) 6993 { 6994 uint32_t val; 6995 uint32_t bit = SC_PATH(sc) ? BXE_PATH1_RST_IN_PROG_BIT : 6996 BXE_PATH0_RST_IN_PROG_BIT; 6997 6998 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG); 6999 7000 val = REG_RD(sc, BXE_RECOVERY_GLOB_REG); 7001 /* Clear the bit */ 7002 val &= ~bit; 7003 REG_WR(sc, BXE_RECOVERY_GLOB_REG, val); 7004 7005 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG); 7006 } 7007 7008 /* set RESET_IN_PROGRESS for the engine, should be run under rtnl lock */ 7009 static void 7010 bxe_set_reset_in_progress(struct bxe_softc *sc) 7011 { 7012 uint32_t val; 7013 uint32_t bit = SC_PATH(sc) ? BXE_PATH1_RST_IN_PROG_BIT : 7014 BXE_PATH0_RST_IN_PROG_BIT; 7015 7016 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG); 7017 7018 val = REG_RD(sc, BXE_RECOVERY_GLOB_REG); 7019 /* Set the bit */ 7020 val |= bit; 7021 REG_WR(sc, BXE_RECOVERY_GLOB_REG, val); 7022 7023 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG); 7024 } 7025 7026 /* check RESET_IN_PROGRESS bit for an engine, should be run under rtnl lock */ 7027 static uint8_t 7028 bxe_reset_is_done(struct bxe_softc *sc, 7029 int engine) 7030 { 7031 uint32_t val = REG_RD(sc, BXE_RECOVERY_GLOB_REG); 7032 uint32_t bit = engine ? BXE_PATH1_RST_IN_PROG_BIT : 7033 BXE_PATH0_RST_IN_PROG_BIT; 7034 7035 /* return false if bit is set */ 7036 return (val & bit) ? FALSE : TRUE; 7037 } 7038 7039 /* get the load status for an engine, should be run under rtnl lock */ 7040 static uint8_t 7041 bxe_get_load_status(struct bxe_softc *sc, 7042 int engine) 7043 { 7044 uint32_t mask = engine ? BXE_PATH1_LOAD_CNT_MASK : 7045 BXE_PATH0_LOAD_CNT_MASK; 7046 uint32_t shift = engine ? BXE_PATH1_LOAD_CNT_SHIFT : 7047 BXE_PATH0_LOAD_CNT_SHIFT; 7048 uint32_t val = REG_RD(sc, BXE_RECOVERY_GLOB_REG); 7049 7050 BLOGD(sc, DBG_LOAD, "Old value for GLOB_REG=0x%08x\n", val); 7051 7052 val = ((val & mask) >> shift); 7053 7054 BLOGD(sc, DBG_LOAD, "Load mask engine %d = 0x%08x\n", engine, val); 7055 7056 return (val != 0); 7057 } 7058 7059 /* set pf load mark */ 7060 /* XXX needs to be under rtnl lock */ 7061 static void 7062 bxe_set_pf_load(struct bxe_softc *sc) 7063 { 7064 uint32_t val; 7065 uint32_t val1; 7066 uint32_t mask = SC_PATH(sc) ? BXE_PATH1_LOAD_CNT_MASK : 7067 BXE_PATH0_LOAD_CNT_MASK; 7068 uint32_t shift = SC_PATH(sc) ? BXE_PATH1_LOAD_CNT_SHIFT : 7069 BXE_PATH0_LOAD_CNT_SHIFT; 7070 7071 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG); 7072 7073 val = REG_RD(sc, BXE_RECOVERY_GLOB_REG); 7074 BLOGD(sc, DBG_LOAD, "Old value for GLOB_REG=0x%08x\n", val); 7075 7076 /* get the current counter value */ 7077 val1 = ((val & mask) >> shift); 7078 7079 /* set bit of this PF */ 7080 val1 |= (1 << SC_ABS_FUNC(sc)); 7081 7082 /* clear the old value */ 7083 val &= ~mask; 7084 7085 /* set the new one */ 7086 val |= ((val1 << shift) & mask); 7087 7088 REG_WR(sc, BXE_RECOVERY_GLOB_REG, val); 7089 7090 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG); 7091 } 7092 7093 /* clear pf load mark */ 7094 /* XXX needs to be under rtnl lock */ 7095 static uint8_t 7096 bxe_clear_pf_load(struct bxe_softc *sc) 7097 { 7098 uint32_t val1, val; 7099 uint32_t mask = SC_PATH(sc) ? BXE_PATH1_LOAD_CNT_MASK : 7100 BXE_PATH0_LOAD_CNT_MASK; 7101 uint32_t shift = SC_PATH(sc) ? BXE_PATH1_LOAD_CNT_SHIFT : 7102 BXE_PATH0_LOAD_CNT_SHIFT; 7103 7104 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG); 7105 val = REG_RD(sc, BXE_RECOVERY_GLOB_REG); 7106 BLOGD(sc, DBG_LOAD, "Old GEN_REG_VAL=0x%08x\n", val); 7107 7108 /* get the current counter value */ 7109 val1 = (val & mask) >> shift; 7110 7111 /* clear bit of that PF */ 7112 val1 &= ~(1 << SC_ABS_FUNC(sc)); 7113 7114 /* clear the old value */ 7115 val &= ~mask; 7116 7117 /* set the new one */ 7118 val |= ((val1 << shift) & mask); 7119 7120 REG_WR(sc, BXE_RECOVERY_GLOB_REG, val); 7121 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG); 7122 return (val1 != 0); 7123 } 7124 7125 /* send load requrest to mcp and analyze response */ 7126 static int 7127 bxe_nic_load_request(struct bxe_softc *sc, 7128 uint32_t *load_code) 7129 { 7130 /* init fw_seq */ 7131 sc->fw_seq = 7132 (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_mb_header) & 7133 DRV_MSG_SEQ_NUMBER_MASK); 7134 7135 BLOGD(sc, DBG_LOAD, "initial fw_seq 0x%04x\n", sc->fw_seq); 7136 7137 /* get the current FW pulse sequence */ 7138 sc->fw_drv_pulse_wr_seq = 7139 (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_pulse_mb) & 7140 DRV_PULSE_SEQ_MASK); 7141 7142 BLOGD(sc, DBG_LOAD, "initial drv_pulse 0x%04x\n", 7143 sc->fw_drv_pulse_wr_seq); 7144 7145 /* load request */ 7146 (*load_code) = bxe_fw_command(sc, DRV_MSG_CODE_LOAD_REQ, 7147 DRV_MSG_CODE_LOAD_REQ_WITH_LFA); 7148 7149 /* if the MCP fails to respond we must abort */ 7150 if (!(*load_code)) { 7151 BLOGE(sc, "MCP response failure!\n"); 7152 return (-1); 7153 } 7154 7155 /* if MCP refused then must abort */ 7156 if ((*load_code) == FW_MSG_CODE_DRV_LOAD_REFUSED) { 7157 BLOGE(sc, "MCP refused load request\n"); 7158 return (-1); 7159 } 7160 7161 return (0); 7162 } 7163 7164 /* 7165 * Check whether another PF has already loaded FW to chip. In virtualized 7166 * environments a pf from anoth VM may have already initialized the device 7167 * including loading FW. 7168 */ 7169 static int 7170 bxe_nic_load_analyze_req(struct bxe_softc *sc, 7171 uint32_t load_code) 7172 { 7173 uint32_t my_fw, loaded_fw; 7174 7175 /* is another pf loaded on this engine? */ 7176 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) && 7177 (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) { 7178 /* build my FW version dword */ 7179 my_fw = (BCM_5710_FW_MAJOR_VERSION + 7180 (BCM_5710_FW_MINOR_VERSION << 8 ) + 7181 (BCM_5710_FW_REVISION_VERSION << 16) + 7182 (BCM_5710_FW_ENGINEERING_VERSION << 24)); 7183 7184 /* read loaded FW from chip */ 7185 loaded_fw = REG_RD(sc, XSEM_REG_PRAM); 7186 BLOGD(sc, DBG_LOAD, "loaded FW 0x%08x / my FW 0x%08x\n", 7187 loaded_fw, my_fw); 7188 7189 /* abort nic load if version mismatch */ 7190 if (my_fw != loaded_fw) { 7191 BLOGE(sc, "FW 0x%08x already loaded (mine is 0x%08x)", 7192 loaded_fw, my_fw); 7193 return (-1); 7194 } 7195 } 7196 7197 return (0); 7198 } 7199 7200 /* mark PMF if applicable */ 7201 static void 7202 bxe_nic_load_pmf(struct bxe_softc *sc, 7203 uint32_t load_code) 7204 { 7205 uint32_t ncsi_oem_data_addr; 7206 7207 if ((load_code == FW_MSG_CODE_DRV_LOAD_COMMON) || 7208 (load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) || 7209 (load_code == FW_MSG_CODE_DRV_LOAD_PORT)) { 7210 /* 7211 * Barrier here for ordering between the writing to sc->port.pmf here 7212 * and reading it from the periodic task. 7213 */ 7214 sc->port.pmf = 1; 7215 mb(); 7216 } else { 7217 sc->port.pmf = 0; 7218 } 7219 7220 BLOGD(sc, DBG_LOAD, "pmf %d\n", sc->port.pmf); 7221 7222 /* XXX needed? */ 7223 if (load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) { 7224 if (SHMEM2_HAS(sc, ncsi_oem_data_addr)) { 7225 ncsi_oem_data_addr = SHMEM2_RD(sc, ncsi_oem_data_addr); 7226 if (ncsi_oem_data_addr) { 7227 REG_WR(sc, 7228 (ncsi_oem_data_addr + 7229 offsetof(struct glob_ncsi_oem_data, driver_version)), 7230 0); 7231 } 7232 } 7233 } 7234 } 7235 7236 static void 7237 bxe_read_mf_cfg(struct bxe_softc *sc) 7238 { 7239 int n = (CHIP_IS_MODE_4_PORT(sc) ? 2 : 1); 7240 int abs_func; 7241 int vn; 7242 7243 if (BXE_NOMCP(sc)) { 7244 return; /* what should be the default bvalue in this case */ 7245 } 7246 7247 /* 7248 * The formula for computing the absolute function number is... 7249 * For 2 port configuration (4 functions per port): 7250 * abs_func = 2 * vn + SC_PORT + SC_PATH 7251 * For 4 port configuration (2 functions per port): 7252 * abs_func = 4 * vn + 2 * SC_PORT + SC_PATH 7253 */ 7254 for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) { 7255 abs_func = (n * (2 * vn + SC_PORT(sc)) + SC_PATH(sc)); 7256 if (abs_func >= E1H_FUNC_MAX) { 7257 break; 7258 } 7259 sc->devinfo.mf_info.mf_config[vn] = 7260 MFCFG_RD(sc, func_mf_config[abs_func].config); 7261 } 7262 7263 if (sc->devinfo.mf_info.mf_config[SC_VN(sc)] & 7264 FUNC_MF_CFG_FUNC_DISABLED) { 7265 BLOGD(sc, DBG_LOAD, "mf_cfg function disabled\n"); 7266 sc->flags |= BXE_MF_FUNC_DIS; 7267 } else { 7268 BLOGD(sc, DBG_LOAD, "mf_cfg function enabled\n"); 7269 sc->flags &= ~BXE_MF_FUNC_DIS; 7270 } 7271 } 7272 7273 /* acquire split MCP access lock register */ 7274 static int bxe_acquire_alr(struct bxe_softc *sc) 7275 { 7276 uint32_t j, val; 7277 7278 for (j = 0; j < 1000; j++) { 7279 val = (1UL << 31); 7280 REG_WR(sc, GRCBASE_MCP + 0x9c, val); 7281 val = REG_RD(sc, GRCBASE_MCP + 0x9c); 7282 if (val & (1L << 31)) 7283 break; 7284 7285 DELAY(5000); 7286 } 7287 7288 if (!(val & (1L << 31))) { 7289 BLOGE(sc, "Cannot acquire MCP access lock register\n"); 7290 return (-1); 7291 } 7292 7293 return (0); 7294 } 7295 7296 /* release split MCP access lock register */ 7297 static void bxe_release_alr(struct bxe_softc *sc) 7298 { 7299 REG_WR(sc, GRCBASE_MCP + 0x9c, 0); 7300 } 7301 7302 static void 7303 bxe_fan_failure(struct bxe_softc *sc) 7304 { 7305 int port = SC_PORT(sc); 7306 uint32_t ext_phy_config; 7307 7308 /* mark the failure */ 7309 ext_phy_config = 7310 SHMEM_RD(sc, dev_info.port_hw_config[port].external_phy_config); 7311 7312 ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK; 7313 ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE; 7314 SHMEM_WR(sc, dev_info.port_hw_config[port].external_phy_config, 7315 ext_phy_config); 7316 7317 /* log the failure */ 7318 BLOGW(sc, "Fan Failure has caused the driver to shutdown " 7319 "the card to prevent permanent damage. " 7320 "Please contact OEM Support for assistance\n"); 7321 7322 /* XXX */ 7323 #if 1 7324 bxe_panic(sc, ("Schedule task to handle fan failure\n")); 7325 #else 7326 /* 7327 * Schedule device reset (unload) 7328 * This is due to some boards consuming sufficient power when driver is 7329 * up to overheat if fan fails. 7330 */ 7331 bxe_set_bit(BXE_SP_RTNL_FAN_FAILURE, &sc->sp_rtnl_state); 7332 schedule_delayed_work(&sc->sp_rtnl_task, 0); 7333 #endif 7334 } 7335 7336 /* this function is called upon a link interrupt */ 7337 static void 7338 bxe_link_attn(struct bxe_softc *sc) 7339 { 7340 uint32_t pause_enabled = 0; 7341 struct host_port_stats *pstats; 7342 int cmng_fns; 7343 7344 /* Make sure that we are synced with the current statistics */ 7345 bxe_stats_handle(sc, STATS_EVENT_STOP); 7346 7347 elink_link_update(&sc->link_params, &sc->link_vars); 7348 7349 if (sc->link_vars.link_up) { 7350 7351 /* dropless flow control */ 7352 if (!CHIP_IS_E1(sc) && sc->dropless_fc) { 7353 pause_enabled = 0; 7354 7355 if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_TX) { 7356 pause_enabled = 1; 7357 } 7358 7359 REG_WR(sc, 7360 (BAR_USTRORM_INTMEM + 7361 USTORM_ETH_PAUSE_ENABLED_OFFSET(SC_PORT(sc))), 7362 pause_enabled); 7363 } 7364 7365 if (sc->link_vars.mac_type != ELINK_MAC_TYPE_EMAC) { 7366 pstats = BXE_SP(sc, port_stats); 7367 /* reset old mac stats */ 7368 memset(&(pstats->mac_stx[0]), 0, sizeof(struct mac_stx)); 7369 } 7370 7371 if (sc->state == BXE_STATE_OPEN) { 7372 bxe_stats_handle(sc, STATS_EVENT_LINK_UP); 7373 } 7374 } 7375 7376 if (sc->link_vars.link_up && sc->link_vars.line_speed) { 7377 cmng_fns = bxe_get_cmng_fns_mode(sc); 7378 7379 if (cmng_fns != CMNG_FNS_NONE) { 7380 bxe_cmng_fns_init(sc, FALSE, cmng_fns); 7381 storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc)); 7382 } else { 7383 /* rate shaping and fairness are disabled */ 7384 BLOGD(sc, DBG_LOAD, "single function mode without fairness\n"); 7385 } 7386 } 7387 7388 bxe_link_report_locked(sc); 7389 7390 if (IS_MF(sc)) { 7391 ; // XXX bxe_link_sync_notify(sc); 7392 } 7393 } 7394 7395 static void 7396 bxe_attn_int_asserted(struct bxe_softc *sc, 7397 uint32_t asserted) 7398 { 7399 int port = SC_PORT(sc); 7400 uint32_t aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : 7401 MISC_REG_AEU_MASK_ATTN_FUNC_0; 7402 uint32_t nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 : 7403 NIG_REG_MASK_INTERRUPT_PORT0; 7404 uint32_t aeu_mask; 7405 uint32_t nig_mask = 0; 7406 uint32_t reg_addr; 7407 uint32_t igu_acked; 7408 uint32_t cnt; 7409 7410 if (sc->attn_state & asserted) { 7411 BLOGE(sc, "IGU ERROR attn=0x%08x\n", asserted); 7412 } 7413 7414 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); 7415 7416 aeu_mask = REG_RD(sc, aeu_addr); 7417 7418 BLOGD(sc, DBG_INTR, "aeu_mask 0x%08x newly asserted 0x%08x\n", 7419 aeu_mask, asserted); 7420 7421 aeu_mask &= ~(asserted & 0x3ff); 7422 7423 BLOGD(sc, DBG_INTR, "new mask 0x%08x\n", aeu_mask); 7424 7425 REG_WR(sc, aeu_addr, aeu_mask); 7426 7427 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); 7428 7429 BLOGD(sc, DBG_INTR, "attn_state 0x%08x\n", sc->attn_state); 7430 sc->attn_state |= asserted; 7431 BLOGD(sc, DBG_INTR, "new state 0x%08x\n", sc->attn_state); 7432 7433 if (asserted & ATTN_HARD_WIRED_MASK) { 7434 if (asserted & ATTN_NIG_FOR_FUNC) { 7435 7436 BXE_PHY_LOCK(sc); 7437 7438 /* save nig interrupt mask */ 7439 nig_mask = REG_RD(sc, nig_int_mask_addr); 7440 7441 /* If nig_mask is not set, no need to call the update function */ 7442 if (nig_mask) { 7443 REG_WR(sc, nig_int_mask_addr, 0); 7444 7445 bxe_link_attn(sc); 7446 } 7447 7448 /* handle unicore attn? */ 7449 } 7450 7451 if (asserted & ATTN_SW_TIMER_4_FUNC) { 7452 BLOGD(sc, DBG_INTR, "ATTN_SW_TIMER_4_FUNC!\n"); 7453 } 7454 7455 if (asserted & GPIO_2_FUNC) { 7456 BLOGD(sc, DBG_INTR, "GPIO_2_FUNC!\n"); 7457 } 7458 7459 if (asserted & GPIO_3_FUNC) { 7460 BLOGD(sc, DBG_INTR, "GPIO_3_FUNC!\n"); 7461 } 7462 7463 if (asserted & GPIO_4_FUNC) { 7464 BLOGD(sc, DBG_INTR, "GPIO_4_FUNC!\n"); 7465 } 7466 7467 if (port == 0) { 7468 if (asserted & ATTN_GENERAL_ATTN_1) { 7469 BLOGD(sc, DBG_INTR, "ATTN_GENERAL_ATTN_1!\n"); 7470 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_1, 0x0); 7471 } 7472 if (asserted & ATTN_GENERAL_ATTN_2) { 7473 BLOGD(sc, DBG_INTR, "ATTN_GENERAL_ATTN_2!\n"); 7474 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_2, 0x0); 7475 } 7476 if (asserted & ATTN_GENERAL_ATTN_3) { 7477 BLOGD(sc, DBG_INTR, "ATTN_GENERAL_ATTN_3!\n"); 7478 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_3, 0x0); 7479 } 7480 } else { 7481 if (asserted & ATTN_GENERAL_ATTN_4) { 7482 BLOGD(sc, DBG_INTR, "ATTN_GENERAL_ATTN_4!\n"); 7483 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_4, 0x0); 7484 } 7485 if (asserted & ATTN_GENERAL_ATTN_5) { 7486 BLOGD(sc, DBG_INTR, "ATTN_GENERAL_ATTN_5!\n"); 7487 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_5, 0x0); 7488 } 7489 if (asserted & ATTN_GENERAL_ATTN_6) { 7490 BLOGD(sc, DBG_INTR, "ATTN_GENERAL_ATTN_6!\n"); 7491 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_6, 0x0); 7492 } 7493 } 7494 } /* hardwired */ 7495 7496 if (sc->devinfo.int_block == INT_BLOCK_HC) { 7497 reg_addr = (HC_REG_COMMAND_REG + port*32 + COMMAND_REG_ATTN_BITS_SET); 7498 } else { 7499 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8); 7500 } 7501 7502 BLOGD(sc, DBG_INTR, "about to mask 0x%08x at %s addr 0x%08x\n", 7503 asserted, 7504 (sc->devinfo.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr); 7505 REG_WR(sc, reg_addr, asserted); 7506 7507 /* now set back the mask */ 7508 if (asserted & ATTN_NIG_FOR_FUNC) { 7509 /* 7510 * Verify that IGU ack through BAR was written before restoring 7511 * NIG mask. This loop should exit after 2-3 iterations max. 7512 */ 7513 if (sc->devinfo.int_block != INT_BLOCK_HC) { 7514 cnt = 0; 7515 7516 do { 7517 igu_acked = REG_RD(sc, IGU_REG_ATTENTION_ACK_BITS); 7518 } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0) && 7519 (++cnt < MAX_IGU_ATTN_ACK_TO)); 7520 7521 if (!igu_acked) { 7522 BLOGE(sc, "Failed to verify IGU ack on time\n"); 7523 } 7524 7525 mb(); 7526 } 7527 7528 REG_WR(sc, nig_int_mask_addr, nig_mask); 7529 7530 BXE_PHY_UNLOCK(sc); 7531 } 7532 } 7533 7534 static void 7535 bxe_print_next_block(struct bxe_softc *sc, 7536 int idx, 7537 const char *blk) 7538 { 7539 BLOGI(sc, "%s%s", idx ? ", " : "", blk); 7540 } 7541 7542 static int 7543 bxe_check_blocks_with_parity0(struct bxe_softc *sc, 7544 uint32_t sig, 7545 int par_num, 7546 uint8_t print) 7547 { 7548 uint32_t cur_bit = 0; 7549 int i = 0; 7550 7551 for (i = 0; sig; i++) { 7552 cur_bit = ((uint32_t)0x1 << i); 7553 if (sig & cur_bit) { 7554 switch (cur_bit) { 7555 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR: 7556 if (print) 7557 bxe_print_next_block(sc, par_num++, "BRB"); 7558 break; 7559 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR: 7560 if (print) 7561 bxe_print_next_block(sc, par_num++, "PARSER"); 7562 break; 7563 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR: 7564 if (print) 7565 bxe_print_next_block(sc, par_num++, "TSDM"); 7566 break; 7567 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR: 7568 if (print) 7569 bxe_print_next_block(sc, par_num++, "SEARCHER"); 7570 break; 7571 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR: 7572 if (print) 7573 bxe_print_next_block(sc, par_num++, "TCM"); 7574 break; 7575 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR: 7576 if (print) 7577 bxe_print_next_block(sc, par_num++, "TSEMI"); 7578 break; 7579 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR: 7580 if (print) 7581 bxe_print_next_block(sc, par_num++, "XPB"); 7582 break; 7583 } 7584 7585 /* Clear the bit */ 7586 sig &= ~cur_bit; 7587 } 7588 } 7589 7590 return (par_num); 7591 } 7592 7593 static int 7594 bxe_check_blocks_with_parity1(struct bxe_softc *sc, 7595 uint32_t sig, 7596 int par_num, 7597 uint8_t *global, 7598 uint8_t print) 7599 { 7600 int i = 0; 7601 uint32_t cur_bit = 0; 7602 for (i = 0; sig; i++) { 7603 cur_bit = ((uint32_t)0x1 << i); 7604 if (sig & cur_bit) { 7605 switch (cur_bit) { 7606 case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR: 7607 if (print) 7608 bxe_print_next_block(sc, par_num++, "PBF"); 7609 break; 7610 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR: 7611 if (print) 7612 bxe_print_next_block(sc, par_num++, "QM"); 7613 break; 7614 case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR: 7615 if (print) 7616 bxe_print_next_block(sc, par_num++, "TM"); 7617 break; 7618 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR: 7619 if (print) 7620 bxe_print_next_block(sc, par_num++, "XSDM"); 7621 break; 7622 case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR: 7623 if (print) 7624 bxe_print_next_block(sc, par_num++, "XCM"); 7625 break; 7626 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR: 7627 if (print) 7628 bxe_print_next_block(sc, par_num++, "XSEMI"); 7629 break; 7630 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR: 7631 if (print) 7632 bxe_print_next_block(sc, par_num++, "DOORBELLQ"); 7633 break; 7634 case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR: 7635 if (print) 7636 bxe_print_next_block(sc, par_num++, "NIG"); 7637 break; 7638 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR: 7639 if (print) 7640 bxe_print_next_block(sc, par_num++, "VAUX PCI CORE"); 7641 *global = TRUE; 7642 break; 7643 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR: 7644 if (print) 7645 bxe_print_next_block(sc, par_num++, "DEBUG"); 7646 break; 7647 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR: 7648 if (print) 7649 bxe_print_next_block(sc, par_num++, "USDM"); 7650 break; 7651 case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR: 7652 if (print) 7653 bxe_print_next_block(sc, par_num++, "UCM"); 7654 break; 7655 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR: 7656 if (print) 7657 bxe_print_next_block(sc, par_num++, "USEMI"); 7658 break; 7659 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR: 7660 if (print) 7661 bxe_print_next_block(sc, par_num++, "UPB"); 7662 break; 7663 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR: 7664 if (print) 7665 bxe_print_next_block(sc, par_num++, "CSDM"); 7666 break; 7667 case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR: 7668 if (print) 7669 bxe_print_next_block(sc, par_num++, "CCM"); 7670 break; 7671 } 7672 7673 /* Clear the bit */ 7674 sig &= ~cur_bit; 7675 } 7676 } 7677 7678 return (par_num); 7679 } 7680 7681 static int 7682 bxe_check_blocks_with_parity2(struct bxe_softc *sc, 7683 uint32_t sig, 7684 int par_num, 7685 uint8_t print) 7686 { 7687 uint32_t cur_bit = 0; 7688 int i = 0; 7689 7690 for (i = 0; sig; i++) { 7691 cur_bit = ((uint32_t)0x1 << i); 7692 if (sig & cur_bit) { 7693 switch (cur_bit) { 7694 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR: 7695 if (print) 7696 bxe_print_next_block(sc, par_num++, "CSEMI"); 7697 break; 7698 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR: 7699 if (print) 7700 bxe_print_next_block(sc, par_num++, "PXP"); 7701 break; 7702 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR: 7703 if (print) 7704 bxe_print_next_block(sc, par_num++, "PXPPCICLOCKCLIENT"); 7705 break; 7706 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR: 7707 if (print) 7708 bxe_print_next_block(sc, par_num++, "CFC"); 7709 break; 7710 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR: 7711 if (print) 7712 bxe_print_next_block(sc, par_num++, "CDU"); 7713 break; 7714 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR: 7715 if (print) 7716 bxe_print_next_block(sc, par_num++, "DMAE"); 7717 break; 7718 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR: 7719 if (print) 7720 bxe_print_next_block(sc, par_num++, "IGU"); 7721 break; 7722 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR: 7723 if (print) 7724 bxe_print_next_block(sc, par_num++, "MISC"); 7725 break; 7726 } 7727 7728 /* Clear the bit */ 7729 sig &= ~cur_bit; 7730 } 7731 } 7732 7733 return (par_num); 7734 } 7735 7736 static int 7737 bxe_check_blocks_with_parity3(struct bxe_softc *sc, 7738 uint32_t sig, 7739 int par_num, 7740 uint8_t *global, 7741 uint8_t print) 7742 { 7743 uint32_t cur_bit = 0; 7744 int i = 0; 7745 7746 for (i = 0; sig; i++) { 7747 cur_bit = ((uint32_t)0x1 << i); 7748 if (sig & cur_bit) { 7749 switch (cur_bit) { 7750 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY: 7751 if (print) 7752 bxe_print_next_block(sc, par_num++, "MCP ROM"); 7753 *global = TRUE; 7754 break; 7755 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY: 7756 if (print) 7757 bxe_print_next_block(sc, par_num++, 7758 "MCP UMP RX"); 7759 *global = TRUE; 7760 break; 7761 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY: 7762 if (print) 7763 bxe_print_next_block(sc, par_num++, 7764 "MCP UMP TX"); 7765 *global = TRUE; 7766 break; 7767 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY: 7768 if (print) 7769 bxe_print_next_block(sc, par_num++, 7770 "MCP SCPAD"); 7771 *global = TRUE; 7772 break; 7773 } 7774 7775 /* Clear the bit */ 7776 sig &= ~cur_bit; 7777 } 7778 } 7779 7780 return (par_num); 7781 } 7782 7783 static int 7784 bxe_check_blocks_with_parity4(struct bxe_softc *sc, 7785 uint32_t sig, 7786 int par_num, 7787 uint8_t print) 7788 { 7789 uint32_t cur_bit = 0; 7790 int i = 0; 7791 7792 for (i = 0; sig; i++) { 7793 cur_bit = ((uint32_t)0x1 << i); 7794 if (sig & cur_bit) { 7795 switch (cur_bit) { 7796 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR: 7797 if (print) 7798 bxe_print_next_block(sc, par_num++, "PGLUE_B"); 7799 break; 7800 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR: 7801 if (print) 7802 bxe_print_next_block(sc, par_num++, "ATC"); 7803 break; 7804 } 7805 7806 /* Clear the bit */ 7807 sig &= ~cur_bit; 7808 } 7809 } 7810 7811 return (par_num); 7812 } 7813 7814 static uint8_t 7815 bxe_parity_attn(struct bxe_softc *sc, 7816 uint8_t *global, 7817 uint8_t print, 7818 uint32_t *sig) 7819 { 7820 int par_num = 0; 7821 7822 if ((sig[0] & HW_PRTY_ASSERT_SET_0) || 7823 (sig[1] & HW_PRTY_ASSERT_SET_1) || 7824 (sig[2] & HW_PRTY_ASSERT_SET_2) || 7825 (sig[3] & HW_PRTY_ASSERT_SET_3) || 7826 (sig[4] & HW_PRTY_ASSERT_SET_4)) { 7827 BLOGE(sc, "Parity error: HW block parity attention:\n" 7828 "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x\n", 7829 (uint32_t)(sig[0] & HW_PRTY_ASSERT_SET_0), 7830 (uint32_t)(sig[1] & HW_PRTY_ASSERT_SET_1), 7831 (uint32_t)(sig[2] & HW_PRTY_ASSERT_SET_2), 7832 (uint32_t)(sig[3] & HW_PRTY_ASSERT_SET_3), 7833 (uint32_t)(sig[4] & HW_PRTY_ASSERT_SET_4)); 7834 7835 if (print) 7836 BLOGI(sc, "Parity errors detected in blocks: "); 7837 7838 par_num = 7839 bxe_check_blocks_with_parity0(sc, sig[0] & 7840 HW_PRTY_ASSERT_SET_0, 7841 par_num, print); 7842 par_num = 7843 bxe_check_blocks_with_parity1(sc, sig[1] & 7844 HW_PRTY_ASSERT_SET_1, 7845 par_num, global, print); 7846 par_num = 7847 bxe_check_blocks_with_parity2(sc, sig[2] & 7848 HW_PRTY_ASSERT_SET_2, 7849 par_num, print); 7850 par_num = 7851 bxe_check_blocks_with_parity3(sc, sig[3] & 7852 HW_PRTY_ASSERT_SET_3, 7853 par_num, global, print); 7854 par_num = 7855 bxe_check_blocks_with_parity4(sc, sig[4] & 7856 HW_PRTY_ASSERT_SET_4, 7857 par_num, print); 7858 7859 if (print) 7860 BLOGI(sc, "\n"); 7861 7862 return (TRUE); 7863 } 7864 7865 return (FALSE); 7866 } 7867 7868 static uint8_t 7869 bxe_chk_parity_attn(struct bxe_softc *sc, 7870 uint8_t *global, 7871 uint8_t print) 7872 { 7873 struct attn_route attn = { {0} }; 7874 int port = SC_PORT(sc); 7875 7876 attn.sig[0] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4); 7877 attn.sig[1] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4); 7878 attn.sig[2] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4); 7879 attn.sig[3] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4); 7880 7881 if (!CHIP_IS_E1x(sc)) 7882 attn.sig[4] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4); 7883 7884 return (bxe_parity_attn(sc, global, print, attn.sig)); 7885 } 7886 7887 static void 7888 bxe_attn_int_deasserted4(struct bxe_softc *sc, 7889 uint32_t attn) 7890 { 7891 uint32_t val; 7892 7893 if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) { 7894 val = REG_RD(sc, PGLUE_B_REG_PGLUE_B_INT_STS_CLR); 7895 BLOGE(sc, "PGLUE hw attention 0x%08x\n", val); 7896 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR) 7897 BLOGE(sc, "PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR\n"); 7898 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR) 7899 BLOGE(sc, "PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR\n"); 7900 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) 7901 BLOGE(sc, "PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN\n"); 7902 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN) 7903 BLOGE(sc, "PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN\n"); 7904 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN) 7905 BLOGE(sc, "PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN\n"); 7906 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN) 7907 BLOGE(sc, "PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN\n"); 7908 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN) 7909 BLOGE(sc, "PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN\n"); 7910 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN) 7911 BLOGE(sc, "PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN\n"); 7912 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW) 7913 BLOGE(sc, "PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW\n"); 7914 } 7915 7916 if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) { 7917 val = REG_RD(sc, ATC_REG_ATC_INT_STS_CLR); 7918 BLOGE(sc, "ATC hw attention 0x%08x\n", val); 7919 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR) 7920 BLOGE(sc, "ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n"); 7921 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND) 7922 BLOGE(sc, "ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND\n"); 7923 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS) 7924 BLOGE(sc, "ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS\n"); 7925 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT) 7926 BLOGE(sc, "ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT\n"); 7927 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR) 7928 BLOGE(sc, "ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n"); 7929 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU) 7930 BLOGE(sc, "ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU\n"); 7931 } 7932 7933 if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | 7934 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) { 7935 BLOGE(sc, "FATAL parity attention set4 0x%08x\n", 7936 (uint32_t)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | 7937 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR))); 7938 } 7939 } 7940 7941 static void 7942 bxe_e1h_disable(struct bxe_softc *sc) 7943 { 7944 int port = SC_PORT(sc); 7945 7946 bxe_tx_disable(sc); 7947 7948 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port*8, 0); 7949 } 7950 7951 static void 7952 bxe_e1h_enable(struct bxe_softc *sc) 7953 { 7954 int port = SC_PORT(sc); 7955 7956 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port*8, 1); 7957 7958 // XXX bxe_tx_enable(sc); 7959 } 7960 7961 /* 7962 * called due to MCP event (on pmf): 7963 * reread new bandwidth configuration 7964 * configure FW 7965 * notify others function about the change 7966 */ 7967 static void 7968 bxe_config_mf_bw(struct bxe_softc *sc) 7969 { 7970 if (sc->link_vars.link_up) { 7971 bxe_cmng_fns_init(sc, TRUE, CMNG_FNS_MINMAX); 7972 // XXX bxe_link_sync_notify(sc); 7973 } 7974 7975 storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc)); 7976 } 7977 7978 static void 7979 bxe_set_mf_bw(struct bxe_softc *sc) 7980 { 7981 bxe_config_mf_bw(sc); 7982 bxe_fw_command(sc, DRV_MSG_CODE_SET_MF_BW_ACK, 0); 7983 } 7984 7985 static void 7986 bxe_handle_eee_event(struct bxe_softc *sc) 7987 { 7988 BLOGD(sc, DBG_INTR, "EEE - LLDP event\n"); 7989 bxe_fw_command(sc, DRV_MSG_CODE_EEE_RESULTS_ACK, 0); 7990 } 7991 7992 #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3 7993 7994 static void 7995 bxe_drv_info_ether_stat(struct bxe_softc *sc) 7996 { 7997 struct eth_stats_info *ether_stat = 7998 &sc->sp->drv_info_to_mcp.ether_stat; 7999 8000 strlcpy(ether_stat->version, BXE_DRIVER_VERSION, 8001 ETH_STAT_INFO_VERSION_LEN); 8002 8003 /* XXX (+ MAC_PAD) taken from other driver... verify this is right */ 8004 sc->sp_objs[0].mac_obj.get_n_elements(sc, &sc->sp_objs[0].mac_obj, 8005 DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED, 8006 ether_stat->mac_local + MAC_PAD, 8007 MAC_PAD, ETH_ALEN); 8008 8009 ether_stat->mtu_size = sc->mtu; 8010 8011 ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK; 8012 if (sc->ifnet->if_capenable & (IFCAP_TSO4 | IFCAP_TSO6)) { 8013 ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK; 8014 } 8015 8016 // XXX ether_stat->feature_flags |= ???; 8017 8018 ether_stat->promiscuous_mode = 0; // (flags & PROMISC) ? 1 : 0; 8019 8020 ether_stat->txq_size = sc->tx_ring_size; 8021 ether_stat->rxq_size = sc->rx_ring_size; 8022 } 8023 8024 static void 8025 bxe_handle_drv_info_req(struct bxe_softc *sc) 8026 { 8027 enum drv_info_opcode op_code; 8028 uint32_t drv_info_ctl = SHMEM2_RD(sc, drv_info_control); 8029 8030 /* if drv_info version supported by MFW doesn't match - send NACK */ 8031 if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) { 8032 bxe_fw_command(sc, DRV_MSG_CODE_DRV_INFO_NACK, 0); 8033 return; 8034 } 8035 8036 op_code = ((drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >> 8037 DRV_INFO_CONTROL_OP_CODE_SHIFT); 8038 8039 memset(&sc->sp->drv_info_to_mcp, 0, sizeof(union drv_info_to_mcp)); 8040 8041 switch (op_code) { 8042 case ETH_STATS_OPCODE: 8043 bxe_drv_info_ether_stat(sc); 8044 break; 8045 case FCOE_STATS_OPCODE: 8046 case ISCSI_STATS_OPCODE: 8047 default: 8048 /* if op code isn't supported - send NACK */ 8049 bxe_fw_command(sc, DRV_MSG_CODE_DRV_INFO_NACK, 0); 8050 return; 8051 } 8052 8053 /* 8054 * If we got drv_info attn from MFW then these fields are defined in 8055 * shmem2 for sure 8056 */ 8057 SHMEM2_WR(sc, drv_info_host_addr_lo, 8058 U64_LO(BXE_SP_MAPPING(sc, drv_info_to_mcp))); 8059 SHMEM2_WR(sc, drv_info_host_addr_hi, 8060 U64_HI(BXE_SP_MAPPING(sc, drv_info_to_mcp))); 8061 8062 bxe_fw_command(sc, DRV_MSG_CODE_DRV_INFO_ACK, 0); 8063 } 8064 8065 static void 8066 bxe_dcc_event(struct bxe_softc *sc, 8067 uint32_t dcc_event) 8068 { 8069 BLOGD(sc, DBG_INTR, "dcc_event 0x%08x\n", dcc_event); 8070 8071 if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) { 8072 /* 8073 * This is the only place besides the function initialization 8074 * where the sc->flags can change so it is done without any 8075 * locks 8076 */ 8077 if (sc->devinfo.mf_info.mf_config[SC_VN(sc)] & FUNC_MF_CFG_FUNC_DISABLED) { 8078 BLOGD(sc, DBG_INTR, "mf_cfg function disabled\n"); 8079 sc->flags |= BXE_MF_FUNC_DIS; 8080 bxe_e1h_disable(sc); 8081 } else { 8082 BLOGD(sc, DBG_INTR, "mf_cfg function enabled\n"); 8083 sc->flags &= ~BXE_MF_FUNC_DIS; 8084 bxe_e1h_enable(sc); 8085 } 8086 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF; 8087 } 8088 8089 if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) { 8090 bxe_config_mf_bw(sc); 8091 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION; 8092 } 8093 8094 /* Report results to MCP */ 8095 if (dcc_event) 8096 bxe_fw_command(sc, DRV_MSG_CODE_DCC_FAILURE, 0); 8097 else 8098 bxe_fw_command(sc, DRV_MSG_CODE_DCC_OK, 0); 8099 } 8100 8101 static void 8102 bxe_pmf_update(struct bxe_softc *sc) 8103 { 8104 int port = SC_PORT(sc); 8105 uint32_t val; 8106 8107 sc->port.pmf = 1; 8108 BLOGD(sc, DBG_INTR, "pmf %d\n", sc->port.pmf); 8109 8110 /* 8111 * We need the mb() to ensure the ordering between the writing to 8112 * sc->port.pmf here and reading it from the bxe_periodic_task(). 8113 */ 8114 mb(); 8115 8116 /* queue a periodic task */ 8117 // XXX schedule task... 8118 8119 // XXX bxe_dcbx_pmf_update(sc); 8120 8121 /* enable nig attention */ 8122 val = (0xff0f | (1 << (SC_VN(sc) + 4))); 8123 if (sc->devinfo.int_block == INT_BLOCK_HC) { 8124 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port*8, val); 8125 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port*8, val); 8126 } else if (!CHIP_IS_E1x(sc)) { 8127 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, val); 8128 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, val); 8129 } 8130 8131 bxe_stats_handle(sc, STATS_EVENT_PMF); 8132 } 8133 8134 static int 8135 bxe_mc_assert(struct bxe_softc *sc) 8136 { 8137 char last_idx; 8138 int i, rc = 0; 8139 uint32_t row0, row1, row2, row3; 8140 8141 /* XSTORM */ 8142 last_idx = REG_RD8(sc, BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_INDEX_OFFSET); 8143 if (last_idx) 8144 BLOGE(sc, "XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); 8145 8146 /* print the asserts */ 8147 for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) { 8148 8149 row0 = REG_RD(sc, BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i)); 8150 row1 = REG_RD(sc, BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) + 4); 8151 row2 = REG_RD(sc, BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) + 8); 8152 row3 = REG_RD(sc, BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) + 12); 8153 8154 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { 8155 BLOGE(sc, "XSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n", 8156 i, row3, row2, row1, row0); 8157 rc++; 8158 } else { 8159 break; 8160 } 8161 } 8162 8163 /* TSTORM */ 8164 last_idx = REG_RD8(sc, BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_INDEX_OFFSET); 8165 if (last_idx) { 8166 BLOGE(sc, "TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); 8167 } 8168 8169 /* print the asserts */ 8170 for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) { 8171 8172 row0 = REG_RD(sc, BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i)); 8173 row1 = REG_RD(sc, BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) + 4); 8174 row2 = REG_RD(sc, BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) + 8); 8175 row3 = REG_RD(sc, BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) + 12); 8176 8177 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { 8178 BLOGE(sc, "TSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n", 8179 i, row3, row2, row1, row0); 8180 rc++; 8181 } else { 8182 break; 8183 } 8184 } 8185 8186 /* CSTORM */ 8187 last_idx = REG_RD8(sc, BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_INDEX_OFFSET); 8188 if (last_idx) { 8189 BLOGE(sc, "CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); 8190 } 8191 8192 /* print the asserts */ 8193 for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) { 8194 8195 row0 = REG_RD(sc, BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i)); 8196 row1 = REG_RD(sc, BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) + 4); 8197 row2 = REG_RD(sc, BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) + 8); 8198 row3 = REG_RD(sc, BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) + 12); 8199 8200 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { 8201 BLOGE(sc, "CSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n", 8202 i, row3, row2, row1, row0); 8203 rc++; 8204 } else { 8205 break; 8206 } 8207 } 8208 8209 /* USTORM */ 8210 last_idx = REG_RD8(sc, BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_INDEX_OFFSET); 8211 if (last_idx) { 8212 BLOGE(sc, "USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); 8213 } 8214 8215 /* print the asserts */ 8216 for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) { 8217 8218 row0 = REG_RD(sc, BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i)); 8219 row1 = REG_RD(sc, BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) + 4); 8220 row2 = REG_RD(sc, BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) + 8); 8221 row3 = REG_RD(sc, BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) + 12); 8222 8223 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { 8224 BLOGE(sc, "USTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n", 8225 i, row3, row2, row1, row0); 8226 rc++; 8227 } else { 8228 break; 8229 } 8230 } 8231 8232 return (rc); 8233 } 8234 8235 static void 8236 bxe_attn_int_deasserted3(struct bxe_softc *sc, 8237 uint32_t attn) 8238 { 8239 int func = SC_FUNC(sc); 8240 uint32_t val; 8241 8242 if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) { 8243 8244 if (attn & BXE_PMF_LINK_ASSERT(sc)) { 8245 8246 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); 8247 bxe_read_mf_cfg(sc); 8248 sc->devinfo.mf_info.mf_config[SC_VN(sc)] = 8249 MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].config); 8250 val = SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_status); 8251 8252 if (val & DRV_STATUS_DCC_EVENT_MASK) 8253 bxe_dcc_event(sc, (val & DRV_STATUS_DCC_EVENT_MASK)); 8254 8255 if (val & DRV_STATUS_SET_MF_BW) 8256 bxe_set_mf_bw(sc); 8257 8258 if (val & DRV_STATUS_DRV_INFO_REQ) 8259 bxe_handle_drv_info_req(sc); 8260 8261 #if 0 8262 if (val & DRV_STATUS_VF_DISABLED) 8263 bxe_vf_handle_flr_event(sc); 8264 #endif 8265 8266 if ((sc->port.pmf == 0) && (val & DRV_STATUS_PMF)) 8267 bxe_pmf_update(sc); 8268 8269 #if 0 8270 if (sc->port.pmf && 8271 (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) && 8272 (sc->dcbx_enabled > 0)) 8273 /* start dcbx state machine */ 8274 bxe_dcbx_set_params(sc, BXE_DCBX_STATE_NEG_RECEIVED); 8275 #endif 8276 8277 #if 0 8278 if (val & DRV_STATUS_AFEX_EVENT_MASK) 8279 bxe_handle_afex_cmd(sc, val & DRV_STATUS_AFEX_EVENT_MASK); 8280 #endif 8281 8282 if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS) 8283 bxe_handle_eee_event(sc); 8284 8285 if (sc->link_vars.periodic_flags & 8286 ELINK_PERIODIC_FLAGS_LINK_EVENT) { 8287 /* sync with link */ 8288 BXE_PHY_LOCK(sc); 8289 sc->link_vars.periodic_flags &= 8290 ~ELINK_PERIODIC_FLAGS_LINK_EVENT; 8291 BXE_PHY_UNLOCK(sc); 8292 if (IS_MF(sc)) 8293 ; // XXX bxe_link_sync_notify(sc); 8294 bxe_link_report(sc); 8295 } 8296 8297 /* 8298 * Always call it here: bxe_link_report() will 8299 * prevent the link indication duplication. 8300 */ 8301 bxe_link_status_update(sc); 8302 8303 } else if (attn & BXE_MC_ASSERT_BITS) { 8304 8305 BLOGE(sc, "MC assert!\n"); 8306 bxe_mc_assert(sc); 8307 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_10, 0); 8308 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_9, 0); 8309 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_8, 0); 8310 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_7, 0); 8311 bxe_panic(sc, ("MC assert!\n")); 8312 8313 } else if (attn & BXE_MCP_ASSERT) { 8314 8315 BLOGE(sc, "MCP assert!\n"); 8316 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_11, 0); 8317 // XXX bxe_fw_dump(sc); 8318 8319 } else { 8320 BLOGE(sc, "Unknown HW assert! (attn 0x%08x)\n", attn); 8321 } 8322 } 8323 8324 if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) { 8325 BLOGE(sc, "LATCHED attention 0x%08x (masked)\n", attn); 8326 if (attn & BXE_GRC_TIMEOUT) { 8327 val = CHIP_IS_E1(sc) ? 0 : REG_RD(sc, MISC_REG_GRC_TIMEOUT_ATTN); 8328 BLOGE(sc, "GRC time-out 0x%08x\n", val); 8329 } 8330 if (attn & BXE_GRC_RSV) { 8331 val = CHIP_IS_E1(sc) ? 0 : REG_RD(sc, MISC_REG_GRC_RSV_ATTN); 8332 BLOGE(sc, "GRC reserved 0x%08x\n", val); 8333 } 8334 REG_WR(sc, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff); 8335 } 8336 } 8337 8338 static void 8339 bxe_attn_int_deasserted2(struct bxe_softc *sc, 8340 uint32_t attn) 8341 { 8342 int port = SC_PORT(sc); 8343 int reg_offset; 8344 uint32_t val0, mask0, val1, mask1; 8345 uint32_t val; 8346 8347 if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) { 8348 val = REG_RD(sc, CFC_REG_CFC_INT_STS_CLR); 8349 BLOGE(sc, "CFC hw attention 0x%08x\n", val); 8350 /* CFC error attention */ 8351 if (val & 0x2) { 8352 BLOGE(sc, "FATAL error from CFC\n"); 8353 } 8354 } 8355 8356 if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) { 8357 val = REG_RD(sc, PXP_REG_PXP_INT_STS_CLR_0); 8358 BLOGE(sc, "PXP hw attention-0 0x%08x\n", val); 8359 /* RQ_USDMDP_FIFO_OVERFLOW */ 8360 if (val & 0x18000) { 8361 BLOGE(sc, "FATAL error from PXP\n"); 8362 } 8363 8364 if (!CHIP_IS_E1x(sc)) { 8365 val = REG_RD(sc, PXP_REG_PXP_INT_STS_CLR_1); 8366 BLOGE(sc, "PXP hw attention-1 0x%08x\n", val); 8367 } 8368 } 8369 8370 #define PXP2_EOP_ERROR_BIT PXP2_PXP2_INT_STS_CLR_0_REG_WR_PGLUE_EOP_ERROR 8371 #define AEU_PXP2_HW_INT_BIT AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT 8372 8373 if (attn & AEU_PXP2_HW_INT_BIT) { 8374 /* CQ47854 workaround do not panic on 8375 * PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR 8376 */ 8377 if (!CHIP_IS_E1x(sc)) { 8378 mask0 = REG_RD(sc, PXP2_REG_PXP2_INT_MASK_0); 8379 val1 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_1); 8380 mask1 = REG_RD(sc, PXP2_REG_PXP2_INT_MASK_1); 8381 val0 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_0); 8382 /* 8383 * If the olny PXP2_EOP_ERROR_BIT is set in 8384 * STS0 and STS1 - clear it 8385 * 8386 * probably we lose additional attentions between 8387 * STS0 and STS_CLR0, in this case user will not 8388 * be notified about them 8389 */ 8390 if (val0 & mask0 & PXP2_EOP_ERROR_BIT && 8391 !(val1 & mask1)) 8392 val0 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_CLR_0); 8393 8394 /* print the register, since no one can restore it */ 8395 BLOGE(sc, "PXP2_REG_PXP2_INT_STS_CLR_0 0x%08x\n", val0); 8396 8397 /* 8398 * if PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR 8399 * then notify 8400 */ 8401 if (val0 & PXP2_EOP_ERROR_BIT) { 8402 BLOGE(sc, "PXP2_WR_PGLUE_EOP_ERROR\n"); 8403 8404 /* 8405 * if only PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR is 8406 * set then clear attention from PXP2 block without panic 8407 */ 8408 if (((val0 & mask0) == PXP2_EOP_ERROR_BIT) && 8409 ((val1 & mask1) == 0)) 8410 attn &= ~AEU_PXP2_HW_INT_BIT; 8411 } 8412 } 8413 } 8414 8415 if (attn & HW_INTERRUT_ASSERT_SET_2) { 8416 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 : 8417 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2); 8418 8419 val = REG_RD(sc, reg_offset); 8420 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2); 8421 REG_WR(sc, reg_offset, val); 8422 8423 BLOGE(sc, "FATAL HW block attention set2 0x%x\n", 8424 (uint32_t)(attn & HW_INTERRUT_ASSERT_SET_2)); 8425 bxe_panic(sc, ("HW block attention set2\n")); 8426 } 8427 } 8428 8429 static void 8430 bxe_attn_int_deasserted1(struct bxe_softc *sc, 8431 uint32_t attn) 8432 { 8433 int port = SC_PORT(sc); 8434 int reg_offset; 8435 uint32_t val; 8436 8437 if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) { 8438 val = REG_RD(sc, DORQ_REG_DORQ_INT_STS_CLR); 8439 BLOGE(sc, "DB hw attention 0x%08x\n", val); 8440 /* DORQ discard attention */ 8441 if (val & 0x2) { 8442 BLOGE(sc, "FATAL error from DORQ\n"); 8443 } 8444 } 8445 8446 if (attn & HW_INTERRUT_ASSERT_SET_1) { 8447 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 : 8448 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1); 8449 8450 val = REG_RD(sc, reg_offset); 8451 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1); 8452 REG_WR(sc, reg_offset, val); 8453 8454 BLOGE(sc, "FATAL HW block attention set1 0x%08x\n", 8455 (uint32_t)(attn & HW_INTERRUT_ASSERT_SET_1)); 8456 bxe_panic(sc, ("HW block attention set1\n")); 8457 } 8458 } 8459 8460 static void 8461 bxe_attn_int_deasserted0(struct bxe_softc *sc, 8462 uint32_t attn) 8463 { 8464 int port = SC_PORT(sc); 8465 int reg_offset; 8466 uint32_t val; 8467 8468 reg_offset = (port) ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : 8469 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0; 8470 8471 if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) { 8472 val = REG_RD(sc, reg_offset); 8473 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5; 8474 REG_WR(sc, reg_offset, val); 8475 8476 BLOGW(sc, "SPIO5 hw attention\n"); 8477 8478 /* Fan failure attention */ 8479 elink_hw_reset_phy(&sc->link_params); 8480 bxe_fan_failure(sc); 8481 } 8482 8483 if ((attn & sc->link_vars.aeu_int_mask) && sc->port.pmf) { 8484 BXE_PHY_LOCK(sc); 8485 elink_handle_module_detect_int(&sc->link_params); 8486 BXE_PHY_UNLOCK(sc); 8487 } 8488 8489 if (attn & HW_INTERRUT_ASSERT_SET_0) { 8490 val = REG_RD(sc, reg_offset); 8491 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0); 8492 REG_WR(sc, reg_offset, val); 8493 8494 bxe_panic(sc, ("FATAL HW block attention set0 0x%lx\n", 8495 (attn & HW_INTERRUT_ASSERT_SET_0))); 8496 } 8497 } 8498 8499 static void 8500 bxe_attn_int_deasserted(struct bxe_softc *sc, 8501 uint32_t deasserted) 8502 { 8503 struct attn_route attn; 8504 struct attn_route *group_mask; 8505 int port = SC_PORT(sc); 8506 int index; 8507 uint32_t reg_addr; 8508 uint32_t val; 8509 uint32_t aeu_mask; 8510 uint8_t global = FALSE; 8511 8512 /* 8513 * Need to take HW lock because MCP or other port might also 8514 * try to handle this event. 8515 */ 8516 bxe_acquire_alr(sc); 8517 8518 if (bxe_chk_parity_attn(sc, &global, TRUE)) { 8519 /* XXX 8520 * In case of parity errors don't handle attentions so that 8521 * other function would "see" parity errors. 8522 */ 8523 sc->recovery_state = BXE_RECOVERY_INIT; 8524 // XXX schedule a recovery task... 8525 /* disable HW interrupts */ 8526 bxe_int_disable(sc); 8527 bxe_release_alr(sc); 8528 return; 8529 } 8530 8531 attn.sig[0] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4); 8532 attn.sig[1] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4); 8533 attn.sig[2] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4); 8534 attn.sig[3] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4); 8535 if (!CHIP_IS_E1x(sc)) { 8536 attn.sig[4] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4); 8537 } else { 8538 attn.sig[4] = 0; 8539 } 8540 8541 BLOGD(sc, DBG_INTR, "attn: 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n", 8542 attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]); 8543 8544 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) { 8545 if (deasserted & (1 << index)) { 8546 group_mask = &sc->attn_group[index]; 8547 8548 BLOGD(sc, DBG_INTR, 8549 "group[%d]: 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n", index, 8550 group_mask->sig[0], group_mask->sig[1], 8551 group_mask->sig[2], group_mask->sig[3], 8552 group_mask->sig[4]); 8553 8554 bxe_attn_int_deasserted4(sc, attn.sig[4] & group_mask->sig[4]); 8555 bxe_attn_int_deasserted3(sc, attn.sig[3] & group_mask->sig[3]); 8556 bxe_attn_int_deasserted1(sc, attn.sig[1] & group_mask->sig[1]); 8557 bxe_attn_int_deasserted2(sc, attn.sig[2] & group_mask->sig[2]); 8558 bxe_attn_int_deasserted0(sc, attn.sig[0] & group_mask->sig[0]); 8559 } 8560 } 8561 8562 bxe_release_alr(sc); 8563 8564 if (sc->devinfo.int_block == INT_BLOCK_HC) { 8565 reg_addr = (HC_REG_COMMAND_REG + port*32 + 8566 COMMAND_REG_ATTN_BITS_CLR); 8567 } else { 8568 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8); 8569 } 8570 8571 val = ~deasserted; 8572 BLOGD(sc, DBG_INTR, 8573 "about to mask 0x%08x at %s addr 0x%08x\n", val, 8574 (sc->devinfo.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr); 8575 REG_WR(sc, reg_addr, val); 8576 8577 if (~sc->attn_state & deasserted) { 8578 BLOGE(sc, "IGU error\n"); 8579 } 8580 8581 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : 8582 MISC_REG_AEU_MASK_ATTN_FUNC_0; 8583 8584 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); 8585 8586 aeu_mask = REG_RD(sc, reg_addr); 8587 8588 BLOGD(sc, DBG_INTR, "aeu_mask 0x%08x newly deasserted 0x%08x\n", 8589 aeu_mask, deasserted); 8590 aeu_mask |= (deasserted & 0x3ff); 8591 BLOGD(sc, DBG_INTR, "new mask 0x%08x\n", aeu_mask); 8592 8593 REG_WR(sc, reg_addr, aeu_mask); 8594 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); 8595 8596 BLOGD(sc, DBG_INTR, "attn_state 0x%08x\n", sc->attn_state); 8597 sc->attn_state &= ~deasserted; 8598 BLOGD(sc, DBG_INTR, "new state 0x%08x\n", sc->attn_state); 8599 } 8600 8601 static void 8602 bxe_attn_int(struct bxe_softc *sc) 8603 { 8604 /* read local copy of bits */ 8605 uint32_t attn_bits = le32toh(sc->def_sb->atten_status_block.attn_bits); 8606 uint32_t attn_ack = le32toh(sc->def_sb->atten_status_block.attn_bits_ack); 8607 uint32_t attn_state = sc->attn_state; 8608 8609 /* look for changed bits */ 8610 uint32_t asserted = attn_bits & ~attn_ack & ~attn_state; 8611 uint32_t deasserted = ~attn_bits & attn_ack & attn_state; 8612 8613 BLOGD(sc, DBG_INTR, 8614 "attn_bits 0x%08x attn_ack 0x%08x asserted 0x%08x deasserted 0x%08x\n", 8615 attn_bits, attn_ack, asserted, deasserted); 8616 8617 if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state)) { 8618 BLOGE(sc, "BAD attention state\n"); 8619 } 8620 8621 /* handle bits that were raised */ 8622 if (asserted) { 8623 bxe_attn_int_asserted(sc, asserted); 8624 } 8625 8626 if (deasserted) { 8627 bxe_attn_int_deasserted(sc, deasserted); 8628 } 8629 } 8630 8631 static uint16_t 8632 bxe_update_dsb_idx(struct bxe_softc *sc) 8633 { 8634 struct host_sp_status_block *def_sb = sc->def_sb; 8635 uint16_t rc = 0; 8636 8637 mb(); /* status block is written to by the chip */ 8638 8639 if (sc->def_att_idx != def_sb->atten_status_block.attn_bits_index) { 8640 sc->def_att_idx = def_sb->atten_status_block.attn_bits_index; 8641 rc |= BXE_DEF_SB_ATT_IDX; 8642 } 8643 8644 if (sc->def_idx != def_sb->sp_sb.running_index) { 8645 sc->def_idx = def_sb->sp_sb.running_index; 8646 rc |= BXE_DEF_SB_IDX; 8647 } 8648 8649 mb(); 8650 8651 return (rc); 8652 } 8653 8654 static inline struct ecore_queue_sp_obj * 8655 bxe_cid_to_q_obj(struct bxe_softc *sc, 8656 uint32_t cid) 8657 { 8658 BLOGD(sc, DBG_SP, "retrieving fp from cid %d\n", cid); 8659 return (&sc->sp_objs[CID_TO_FP(cid, sc)].q_obj); 8660 } 8661 8662 static void 8663 bxe_handle_mcast_eqe(struct bxe_softc *sc) 8664 { 8665 struct ecore_mcast_ramrod_params rparam; 8666 int rc; 8667 8668 memset(&rparam, 0, sizeof(rparam)); 8669 8670 rparam.mcast_obj = &sc->mcast_obj; 8671 8672 BXE_MCAST_LOCK(sc); 8673 8674 /* clear pending state for the last command */ 8675 sc->mcast_obj.raw.clear_pending(&sc->mcast_obj.raw); 8676 8677 /* if there are pending mcast commands - send them */ 8678 if (sc->mcast_obj.check_pending(&sc->mcast_obj)) { 8679 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT); 8680 if (rc < 0) { 8681 BLOGD(sc, DBG_SP, 8682 "ERROR: Failed to send pending mcast commands (%d)\n", 8683 rc); 8684 } 8685 } 8686 8687 BXE_MCAST_UNLOCK(sc); 8688 } 8689 8690 static void 8691 bxe_handle_classification_eqe(struct bxe_softc *sc, 8692 union event_ring_elem *elem) 8693 { 8694 unsigned long ramrod_flags = 0; 8695 int rc = 0; 8696 uint32_t cid = elem->message.data.eth_event.echo & BXE_SWCID_MASK; 8697 struct ecore_vlan_mac_obj *vlan_mac_obj; 8698 8699 /* always push next commands out, don't wait here */ 8700 bit_set(&ramrod_flags, RAMROD_CONT); 8701 8702 switch (le32toh(elem->message.data.eth_event.echo) >> BXE_SWCID_SHIFT) { 8703 case ECORE_FILTER_MAC_PENDING: 8704 BLOGD(sc, DBG_SP, "Got SETUP_MAC completions\n"); 8705 vlan_mac_obj = &sc->sp_objs[cid].mac_obj; 8706 break; 8707 8708 case ECORE_FILTER_MCAST_PENDING: 8709 BLOGD(sc, DBG_SP, "Got SETUP_MCAST completions\n"); 8710 /* 8711 * This is only relevant for 57710 where multicast MACs are 8712 * configured as unicast MACs using the same ramrod. 8713 */ 8714 bxe_handle_mcast_eqe(sc); 8715 return; 8716 8717 default: 8718 BLOGE(sc, "Unsupported classification command: %d\n", 8719 elem->message.data.eth_event.echo); 8720 return; 8721 } 8722 8723 rc = vlan_mac_obj->complete(sc, vlan_mac_obj, elem, &ramrod_flags); 8724 8725 if (rc < 0) { 8726 BLOGE(sc, "Failed to schedule new commands (%d)\n", rc); 8727 } else if (rc > 0) { 8728 BLOGD(sc, DBG_SP, "Scheduled next pending commands...\n"); 8729 } 8730 } 8731 8732 static void 8733 bxe_handle_rx_mode_eqe(struct bxe_softc *sc, 8734 union event_ring_elem *elem) 8735 { 8736 bxe_clear_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state); 8737 8738 /* send rx_mode command again if was requested */ 8739 if (bxe_test_and_clear_bit(ECORE_FILTER_RX_MODE_SCHED, 8740 &sc->sp_state)) { 8741 bxe_set_storm_rx_mode(sc); 8742 } 8743 #if 0 8744 else if (bxe_test_and_clear_bit(ECORE_FILTER_ISCSI_ETH_START_SCHED, 8745 &sc->sp_state)) { 8746 bxe_set_iscsi_eth_rx_mode(sc, TRUE); 8747 } 8748 else if (bxe_test_and_clear_bit(ECORE_FILTER_ISCSI_ETH_STOP_SCHED, 8749 &sc->sp_state)) { 8750 bxe_set_iscsi_eth_rx_mode(sc, FALSE); 8751 } 8752 #endif 8753 } 8754 8755 static void 8756 bxe_update_eq_prod(struct bxe_softc *sc, 8757 uint16_t prod) 8758 { 8759 storm_memset_eq_prod(sc, prod, SC_FUNC(sc)); 8760 wmb(); /* keep prod updates ordered */ 8761 } 8762 8763 static void 8764 bxe_eq_int(struct bxe_softc *sc) 8765 { 8766 uint16_t hw_cons, sw_cons, sw_prod; 8767 union event_ring_elem *elem; 8768 uint8_t echo; 8769 uint32_t cid; 8770 uint8_t opcode; 8771 int spqe_cnt = 0; 8772 struct ecore_queue_sp_obj *q_obj; 8773 struct ecore_func_sp_obj *f_obj = &sc->func_obj; 8774 struct ecore_raw_obj *rss_raw = &sc->rss_conf_obj.raw; 8775 8776 hw_cons = le16toh(*sc->eq_cons_sb); 8777 8778 /* 8779 * The hw_cons range is 1-255, 257 - the sw_cons range is 0-254, 256. 8780 * when we get to the next-page we need to adjust so the loop 8781 * condition below will be met. The next element is the size of a 8782 * regular element and hence incrementing by 1 8783 */ 8784 if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE) { 8785 hw_cons++; 8786 } 8787 8788 /* 8789 * This function may never run in parallel with itself for a 8790 * specific sc and no need for a read memory barrier here. 8791 */ 8792 sw_cons = sc->eq_cons; 8793 sw_prod = sc->eq_prod; 8794 8795 BLOGD(sc, DBG_SP,"EQ: hw_cons=%u sw_cons=%u eq_spq_left=0x%lx\n", 8796 hw_cons, sw_cons, atomic_load_acq_long(&sc->eq_spq_left)); 8797 8798 for (; 8799 sw_cons != hw_cons; 8800 sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) { 8801 8802 elem = &sc->eq[EQ_DESC(sw_cons)]; 8803 8804 #if 0 8805 int rc; 8806 rc = bxe_iov_eq_sp_event(sc, elem); 8807 if (!rc) { 8808 BLOGE(sc, "bxe_iov_eq_sp_event returned %d\n", rc); 8809 goto next_spqe; 8810 } 8811 #endif 8812 8813 /* elem CID originates from FW, actually LE */ 8814 cid = SW_CID(elem->message.data.cfc_del_event.cid); 8815 opcode = elem->message.opcode; 8816 8817 /* handle eq element */ 8818 switch (opcode) { 8819 #if 0 8820 case EVENT_RING_OPCODE_VF_PF_CHANNEL: 8821 BLOGD(sc, DBG_SP, "vf/pf channel element on eq\n"); 8822 bxe_vf_mbx(sc, &elem->message.data.vf_pf_event); 8823 continue; 8824 #endif 8825 8826 case EVENT_RING_OPCODE_STAT_QUERY: 8827 BLOGD(sc, DBG_SP, "got statistics completion event %d\n", 8828 sc->stats_comp++); 8829 /* nothing to do with stats comp */ 8830 goto next_spqe; 8831 8832 case EVENT_RING_OPCODE_CFC_DEL: 8833 /* handle according to cid range */ 8834 /* we may want to verify here that the sc state is HALTING */ 8835 BLOGD(sc, DBG_SP, "got delete ramrod for MULTI[%d]\n", cid); 8836 q_obj = bxe_cid_to_q_obj(sc, cid); 8837 if (q_obj->complete_cmd(sc, q_obj, ECORE_Q_CMD_CFC_DEL)) { 8838 break; 8839 } 8840 goto next_spqe; 8841 8842 case EVENT_RING_OPCODE_STOP_TRAFFIC: 8843 BLOGD(sc, DBG_SP, "got STOP TRAFFIC\n"); 8844 if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_TX_STOP)) { 8845 break; 8846 } 8847 // XXX bxe_dcbx_set_params(sc, BXE_DCBX_STATE_TX_PAUSED); 8848 goto next_spqe; 8849 8850 case EVENT_RING_OPCODE_START_TRAFFIC: 8851 BLOGD(sc, DBG_SP, "got START TRAFFIC\n"); 8852 if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_TX_START)) { 8853 break; 8854 } 8855 // XXX bxe_dcbx_set_params(sc, BXE_DCBX_STATE_TX_RELEASED); 8856 goto next_spqe; 8857 8858 case EVENT_RING_OPCODE_FUNCTION_UPDATE: 8859 echo = elem->message.data.function_update_event.echo; 8860 if (echo == SWITCH_UPDATE) { 8861 BLOGD(sc, DBG_SP, "got FUNC_SWITCH_UPDATE ramrod\n"); 8862 if (f_obj->complete_cmd(sc, f_obj, 8863 ECORE_F_CMD_SWITCH_UPDATE)) { 8864 break; 8865 } 8866 } 8867 else { 8868 BLOGD(sc, DBG_SP, 8869 "AFEX: ramrod completed FUNCTION_UPDATE\n"); 8870 #if 0 8871 f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_AFEX_UPDATE); 8872 /* 8873 * We will perform the queues update from the sp_core_task as 8874 * all queue SP operations should run with CORE_LOCK. 8875 */ 8876 bxe_set_bit(BXE_SP_CORE_AFEX_F_UPDATE, &sc->sp_core_state); 8877 taskqueue_enqueue(sc->sp_tq, &sc->sp_tq_task); 8878 #endif 8879 } 8880 goto next_spqe; 8881 8882 #if 0 8883 case EVENT_RING_OPCODE_AFEX_VIF_LISTS: 8884 f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_AFEX_VIFLISTS); 8885 bxe_after_afex_vif_lists(sc, elem); 8886 goto next_spqe; 8887 #endif 8888 8889 case EVENT_RING_OPCODE_FORWARD_SETUP: 8890 q_obj = &bxe_fwd_sp_obj(sc, q_obj); 8891 if (q_obj->complete_cmd(sc, q_obj, 8892 ECORE_Q_CMD_SETUP_TX_ONLY)) { 8893 break; 8894 } 8895 goto next_spqe; 8896 8897 case EVENT_RING_OPCODE_FUNCTION_START: 8898 BLOGD(sc, DBG_SP, "got FUNC_START ramrod\n"); 8899 if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_START)) { 8900 break; 8901 } 8902 goto next_spqe; 8903 8904 case EVENT_RING_OPCODE_FUNCTION_STOP: 8905 BLOGD(sc, DBG_SP, "got FUNC_STOP ramrod\n"); 8906 if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_STOP)) { 8907 break; 8908 } 8909 goto next_spqe; 8910 } 8911 8912 switch (opcode | sc->state) { 8913 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | BXE_STATE_OPEN): 8914 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | BXE_STATE_OPENING_WAITING_PORT): 8915 cid = elem->message.data.eth_event.echo & BXE_SWCID_MASK; 8916 BLOGD(sc, DBG_SP, "got RSS_UPDATE ramrod. CID %d\n", cid); 8917 rss_raw->clear_pending(rss_raw); 8918 break; 8919 8920 case (EVENT_RING_OPCODE_SET_MAC | BXE_STATE_OPEN): 8921 case (EVENT_RING_OPCODE_SET_MAC | BXE_STATE_DIAG): 8922 case (EVENT_RING_OPCODE_SET_MAC | BXE_STATE_CLOSING_WAITING_HALT): 8923 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BXE_STATE_OPEN): 8924 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BXE_STATE_DIAG): 8925 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BXE_STATE_CLOSING_WAITING_HALT): 8926 BLOGD(sc, DBG_SP, "got (un)set mac ramrod\n"); 8927 bxe_handle_classification_eqe(sc, elem); 8928 break; 8929 8930 case (EVENT_RING_OPCODE_MULTICAST_RULES | BXE_STATE_OPEN): 8931 case (EVENT_RING_OPCODE_MULTICAST_RULES | BXE_STATE_DIAG): 8932 case (EVENT_RING_OPCODE_MULTICAST_RULES | BXE_STATE_CLOSING_WAITING_HALT): 8933 BLOGD(sc, DBG_SP, "got mcast ramrod\n"); 8934 bxe_handle_mcast_eqe(sc); 8935 break; 8936 8937 case (EVENT_RING_OPCODE_FILTERS_RULES | BXE_STATE_OPEN): 8938 case (EVENT_RING_OPCODE_FILTERS_RULES | BXE_STATE_DIAG): 8939 case (EVENT_RING_OPCODE_FILTERS_RULES | BXE_STATE_CLOSING_WAITING_HALT): 8940 BLOGD(sc, DBG_SP, "got rx_mode ramrod\n"); 8941 bxe_handle_rx_mode_eqe(sc, elem); 8942 break; 8943 8944 default: 8945 /* unknown event log error and continue */ 8946 BLOGE(sc, "Unknown EQ event %d, sc->state 0x%x\n", 8947 elem->message.opcode, sc->state); 8948 } 8949 8950 next_spqe: 8951 spqe_cnt++; 8952 } /* for */ 8953 8954 mb(); 8955 atomic_add_acq_long(&sc->eq_spq_left, spqe_cnt); 8956 8957 sc->eq_cons = sw_cons; 8958 sc->eq_prod = sw_prod; 8959 8960 /* make sure that above mem writes were issued towards the memory */ 8961 wmb(); 8962 8963 /* update producer */ 8964 bxe_update_eq_prod(sc, sc->eq_prod); 8965 } 8966 8967 static void 8968 bxe_handle_sp_tq(void *context, 8969 int pending) 8970 { 8971 struct bxe_softc *sc = (struct bxe_softc *)context; 8972 uint16_t status; 8973 8974 BLOGD(sc, DBG_SP, "---> SP TASK <---\n"); 8975 8976 /* what work needs to be performed? */ 8977 status = bxe_update_dsb_idx(sc); 8978 8979 BLOGD(sc, DBG_SP, "dsb status 0x%04x\n", status); 8980 8981 /* HW attentions */ 8982 if (status & BXE_DEF_SB_ATT_IDX) { 8983 BLOGD(sc, DBG_SP, "---> ATTN INTR <---\n"); 8984 bxe_attn_int(sc); 8985 status &= ~BXE_DEF_SB_ATT_IDX; 8986 } 8987 8988 /* SP events: STAT_QUERY and others */ 8989 if (status & BXE_DEF_SB_IDX) { 8990 /* handle EQ completions */ 8991 BLOGD(sc, DBG_SP, "---> EQ INTR <---\n"); 8992 bxe_eq_int(sc); 8993 bxe_ack_sb(sc, sc->igu_dsb_id, USTORM_ID, 8994 le16toh(sc->def_idx), IGU_INT_NOP, 1); 8995 status &= ~BXE_DEF_SB_IDX; 8996 } 8997 8998 /* if status is non zero then something went wrong */ 8999 if (__predict_false(status)) { 9000 BLOGE(sc, "Got an unknown SP interrupt! (0x%04x)\n", status); 9001 } 9002 9003 /* ack status block only if something was actually handled */ 9004 bxe_ack_sb(sc, sc->igu_dsb_id, ATTENTION_ID, 9005 le16toh(sc->def_att_idx), IGU_INT_ENABLE, 1); 9006 9007 /* 9008 * Must be called after the EQ processing (since eq leads to sriov 9009 * ramrod completion flows). 9010 * This flow may have been scheduled by the arrival of a ramrod 9011 * completion, or by the sriov code rescheduling itself. 9012 */ 9013 // XXX bxe_iov_sp_task(sc); 9014 9015 #if 0 9016 /* AFEX - poll to check if VIFSET_ACK should be sent to MFW */ 9017 if (bxe_test_and_clear_bit(ECORE_AFEX_PENDING_VIFSET_MCP_ACK, 9018 &sc->sp_state)) { 9019 bxe_link_report(sc); 9020 bxe_fw_command(sc, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0); 9021 } 9022 #endif 9023 } 9024 9025 static void 9026 bxe_handle_fp_tq(void *context, 9027 int pending) 9028 { 9029 struct bxe_fastpath *fp = (struct bxe_fastpath *)context; 9030 struct bxe_softc *sc = fp->sc; 9031 uint8_t more_tx = FALSE; 9032 uint8_t more_rx = FALSE; 9033 9034 BLOGD(sc, DBG_INTR, "---> FP TASK QUEUE (%d) <---\n", fp->index); 9035 9036 /* XXX 9037 * IFF_DRV_RUNNING state can't be checked here since we process 9038 * slowpath events on a client queue during setup. Instead 9039 * we need to add a "process/continue" flag here that the driver 9040 * can use to tell the task here not to do anything. 9041 */ 9042 #if 0 9043 if (!(sc->ifnet->if_drv_flags & IFF_DRV_RUNNING)) { 9044 return; 9045 } 9046 #endif 9047 9048 /* update the fastpath index */ 9049 bxe_update_fp_sb_idx(fp); 9050 9051 /* XXX add loop here if ever support multiple tx CoS */ 9052 /* fp->txdata[cos] */ 9053 if (bxe_has_tx_work(fp)) { 9054 BXE_FP_TX_LOCK(fp); 9055 more_tx = bxe_txeof(sc, fp); 9056 BXE_FP_TX_UNLOCK(fp); 9057 } 9058 9059 if (bxe_has_rx_work(fp)) { 9060 more_rx = bxe_rxeof(sc, fp); 9061 } 9062 9063 if (more_rx /*|| more_tx*/) { 9064 /* still more work to do */ 9065 taskqueue_enqueue_fast(fp->tq, &fp->tq_task); 9066 return; 9067 } 9068 9069 bxe_ack_sb(sc, fp->igu_sb_id, USTORM_ID, 9070 le16toh(fp->fp_hc_idx), IGU_INT_ENABLE, 1); 9071 } 9072 9073 static void 9074 bxe_task_fp(struct bxe_fastpath *fp) 9075 { 9076 struct bxe_softc *sc = fp->sc; 9077 uint8_t more_tx = FALSE; 9078 uint8_t more_rx = FALSE; 9079 9080 BLOGD(sc, DBG_INTR, "---> FP TASK ISR (%d) <---\n", fp->index); 9081 9082 /* update the fastpath index */ 9083 bxe_update_fp_sb_idx(fp); 9084 9085 /* XXX add loop here if ever support multiple tx CoS */ 9086 /* fp->txdata[cos] */ 9087 if (bxe_has_tx_work(fp)) { 9088 BXE_FP_TX_LOCK(fp); 9089 more_tx = bxe_txeof(sc, fp); 9090 BXE_FP_TX_UNLOCK(fp); 9091 } 9092 9093 if (bxe_has_rx_work(fp)) { 9094 more_rx = bxe_rxeof(sc, fp); 9095 } 9096 9097 if (more_rx /*|| more_tx*/) { 9098 /* still more work to do, bail out if this ISR and process later */ 9099 taskqueue_enqueue_fast(fp->tq, &fp->tq_task); 9100 return; 9101 } 9102 9103 /* 9104 * Here we write the fastpath index taken before doing any tx or rx work. 9105 * It is very well possible other hw events occurred up to this point and 9106 * they were actually processed accordingly above. Since we're going to 9107 * write an older fastpath index, an interrupt is coming which we might 9108 * not do any work in. 9109 */ 9110 bxe_ack_sb(sc, fp->igu_sb_id, USTORM_ID, 9111 le16toh(fp->fp_hc_idx), IGU_INT_ENABLE, 1); 9112 } 9113 9114 /* 9115 * Legacy interrupt entry point. 9116 * 9117 * Verifies that the controller generated the interrupt and 9118 * then calls a separate routine to handle the various 9119 * interrupt causes: link, RX, and TX. 9120 */ 9121 static void 9122 bxe_intr_legacy(void *xsc) 9123 { 9124 struct bxe_softc *sc = (struct bxe_softc *)xsc; 9125 struct bxe_fastpath *fp; 9126 uint16_t status, mask; 9127 int i; 9128 9129 BLOGD(sc, DBG_INTR, "---> BXE INTx <---\n"); 9130 9131 #if 0 9132 /* Don't handle any interrupts if we're not ready. */ 9133 if (__predict_false(sc->intr_sem != 0)) { 9134 return; 9135 } 9136 #endif 9137 9138 /* 9139 * 0 for ustorm, 1 for cstorm 9140 * the bits returned from ack_int() are 0-15 9141 * bit 0 = attention status block 9142 * bit 1 = fast path status block 9143 * a mask of 0x2 or more = tx/rx event 9144 * a mask of 1 = slow path event 9145 */ 9146 9147 status = bxe_ack_int(sc); 9148 9149 /* the interrupt is not for us */ 9150 if (__predict_false(status == 0)) { 9151 BLOGD(sc, DBG_INTR, "Not our interrupt!\n"); 9152 return; 9153 } 9154 9155 BLOGD(sc, DBG_INTR, "Interrupt status 0x%04x\n", status); 9156 9157 FOR_EACH_ETH_QUEUE(sc, i) { 9158 fp = &sc->fp[i]; 9159 mask = (0x2 << (fp->index + CNIC_SUPPORT(sc))); 9160 if (status & mask) { 9161 /* acknowledge and disable further fastpath interrupts */ 9162 bxe_ack_sb(sc, fp->igu_sb_id, USTORM_ID, 0, IGU_INT_DISABLE, 0); 9163 bxe_task_fp(fp); 9164 status &= ~mask; 9165 } 9166 } 9167 9168 #if 0 9169 if (CNIC_SUPPORT(sc)) { 9170 mask = 0x2; 9171 if (status & (mask | 0x1)) { 9172 ... 9173 status &= ~mask; 9174 } 9175 } 9176 #endif 9177 9178 if (__predict_false(status & 0x1)) { 9179 /* acknowledge and disable further slowpath interrupts */ 9180 bxe_ack_sb(sc, sc->igu_dsb_id, USTORM_ID, 0, IGU_INT_DISABLE, 0); 9181 9182 /* schedule slowpath handler */ 9183 taskqueue_enqueue_fast(sc->sp_tq, &sc->sp_tq_task); 9184 9185 status &= ~0x1; 9186 } 9187 9188 if (__predict_false(status)) { 9189 BLOGW(sc, "Unexpected fastpath status (0x%08x)!\n", status); 9190 } 9191 } 9192 9193 /* slowpath interrupt entry point */ 9194 static void 9195 bxe_intr_sp(void *xsc) 9196 { 9197 struct bxe_softc *sc = (struct bxe_softc *)xsc; 9198 9199 BLOGD(sc, (DBG_INTR | DBG_SP), "---> SP INTR <---\n"); 9200 9201 /* acknowledge and disable further slowpath interrupts */ 9202 bxe_ack_sb(sc, sc->igu_dsb_id, USTORM_ID, 0, IGU_INT_DISABLE, 0); 9203 9204 /* schedule slowpath handler */ 9205 taskqueue_enqueue_fast(sc->sp_tq, &sc->sp_tq_task); 9206 } 9207 9208 /* fastpath interrupt entry point */ 9209 static void 9210 bxe_intr_fp(void *xfp) 9211 { 9212 struct bxe_fastpath *fp = (struct bxe_fastpath *)xfp; 9213 struct bxe_softc *sc = fp->sc; 9214 9215 BLOGD(sc, DBG_INTR, "---> FP INTR %d <---\n", fp->index); 9216 9217 BLOGD(sc, DBG_INTR, 9218 "(cpu=%d) MSI-X fp=%d fw_sb=%d igu_sb=%d\n", 9219 curcpu, fp->index, fp->fw_sb_id, fp->igu_sb_id); 9220 9221 #if 0 9222 /* Don't handle any interrupts if we're not ready. */ 9223 if (__predict_false(sc->intr_sem != 0)) { 9224 return; 9225 } 9226 #endif 9227 9228 /* acknowledge and disable further fastpath interrupts */ 9229 bxe_ack_sb(sc, fp->igu_sb_id, USTORM_ID, 0, IGU_INT_DISABLE, 0); 9230 9231 bxe_task_fp(fp); 9232 } 9233 9234 /* Release all interrupts allocated by the driver. */ 9235 static void 9236 bxe_interrupt_free(struct bxe_softc *sc) 9237 { 9238 int i; 9239 9240 switch (sc->interrupt_mode) { 9241 case INTR_MODE_INTX: 9242 BLOGD(sc, DBG_LOAD, "Releasing legacy INTx vector\n"); 9243 if (sc->intr[0].resource != NULL) { 9244 bus_release_resource(sc->dev, 9245 SYS_RES_IRQ, 9246 sc->intr[0].rid, 9247 sc->intr[0].resource); 9248 } 9249 break; 9250 case INTR_MODE_MSI: 9251 for (i = 0; i < sc->intr_count; i++) { 9252 BLOGD(sc, DBG_LOAD, "Releasing MSI vector %d\n", i); 9253 if (sc->intr[i].resource && sc->intr[i].rid) { 9254 bus_release_resource(sc->dev, 9255 SYS_RES_IRQ, 9256 sc->intr[i].rid, 9257 sc->intr[i].resource); 9258 } 9259 } 9260 pci_release_msi(sc->dev); 9261 break; 9262 case INTR_MODE_MSIX: 9263 for (i = 0; i < sc->intr_count; i++) { 9264 BLOGD(sc, DBG_LOAD, "Releasing MSI-X vector %d\n", i); 9265 if (sc->intr[i].resource && sc->intr[i].rid) { 9266 bus_release_resource(sc->dev, 9267 SYS_RES_IRQ, 9268 sc->intr[i].rid, 9269 sc->intr[i].resource); 9270 } 9271 } 9272 pci_release_msi(sc->dev); 9273 break; 9274 default: 9275 /* nothing to do as initial allocation failed */ 9276 break; 9277 } 9278 } 9279 9280 /* 9281 * This function determines and allocates the appropriate 9282 * interrupt based on system capabilites and user request. 9283 * 9284 * The user may force a particular interrupt mode, specify 9285 * the number of receive queues, specify the method for 9286 * distribuitng received frames to receive queues, or use 9287 * the default settings which will automatically select the 9288 * best supported combination. In addition, the OS may or 9289 * may not support certain combinations of these settings. 9290 * This routine attempts to reconcile the settings requested 9291 * by the user with the capabilites available from the system 9292 * to select the optimal combination of features. 9293 * 9294 * Returns: 9295 * 0 = Success, !0 = Failure. 9296 */ 9297 static int 9298 bxe_interrupt_alloc(struct bxe_softc *sc) 9299 { 9300 int msix_count = 0; 9301 int msi_count = 0; 9302 int num_requested = 0; 9303 int num_allocated = 0; 9304 int rid, i, j; 9305 int rc; 9306 9307 /* get the number of available MSI/MSI-X interrupts from the OS */ 9308 if (sc->interrupt_mode > 0) { 9309 if (sc->devinfo.pcie_cap_flags & BXE_MSIX_CAPABLE_FLAG) { 9310 msix_count = pci_msix_count(sc->dev); 9311 } 9312 9313 if (sc->devinfo.pcie_cap_flags & BXE_MSI_CAPABLE_FLAG) { 9314 msi_count = pci_msi_count(sc->dev); 9315 } 9316 9317 BLOGD(sc, DBG_LOAD, "%d MSI and %d MSI-X vectors available\n", 9318 msi_count, msix_count); 9319 } 9320 9321 do { /* try allocating MSI-X interrupt resources (at least 2) */ 9322 if (sc->interrupt_mode != INTR_MODE_MSIX) { 9323 break; 9324 } 9325 9326 if (((sc->devinfo.pcie_cap_flags & BXE_MSIX_CAPABLE_FLAG) == 0) || 9327 (msix_count < 2)) { 9328 sc->interrupt_mode = INTR_MODE_MSI; /* try MSI next */ 9329 break; 9330 } 9331 9332 /* ask for the necessary number of MSI-X vectors */ 9333 num_requested = min((sc->num_queues + 1), msix_count); 9334 9335 BLOGD(sc, DBG_LOAD, "Requesting %d MSI-X vectors\n", num_requested); 9336 9337 num_allocated = num_requested; 9338 if ((rc = pci_alloc_msix(sc->dev, &num_allocated)) != 0) { 9339 BLOGE(sc, "MSI-X alloc failed! (%d)\n", rc); 9340 sc->interrupt_mode = INTR_MODE_MSI; /* try MSI next */ 9341 break; 9342 } 9343 9344 if (num_allocated < 2) { /* possible? */ 9345 BLOGE(sc, "MSI-X allocation less than 2!\n"); 9346 sc->interrupt_mode = INTR_MODE_MSI; /* try MSI next */ 9347 pci_release_msi(sc->dev); 9348 break; 9349 } 9350 9351 BLOGI(sc, "MSI-X vectors Requested %d and Allocated %d\n", 9352 num_requested, num_allocated); 9353 9354 /* best effort so use the number of vectors allocated to us */ 9355 sc->intr_count = num_allocated; 9356 sc->num_queues = num_allocated - 1; 9357 9358 rid = 1; /* initial resource identifier */ 9359 9360 /* allocate the MSI-X vectors */ 9361 for (i = 0; i < num_allocated; i++) { 9362 sc->intr[i].rid = (rid + i); 9363 9364 if ((sc->intr[i].resource = 9365 bus_alloc_resource_any(sc->dev, 9366 SYS_RES_IRQ, 9367 &sc->intr[i].rid, 9368 RF_ACTIVE)) == NULL) { 9369 BLOGE(sc, "Failed to map MSI-X[%d] (rid=%d)!\n", 9370 i, (rid + i)); 9371 9372 for (j = (i - 1); j >= 0; j--) { 9373 bus_release_resource(sc->dev, 9374 SYS_RES_IRQ, 9375 sc->intr[j].rid, 9376 sc->intr[j].resource); 9377 } 9378 9379 sc->intr_count = 0; 9380 sc->num_queues = 0; 9381 sc->interrupt_mode = INTR_MODE_MSI; /* try MSI next */ 9382 pci_release_msi(sc->dev); 9383 break; 9384 } 9385 9386 BLOGD(sc, DBG_LOAD, "Mapped MSI-X[%d] (rid=%d)\n", i, (rid + i)); 9387 } 9388 } while (0); 9389 9390 do { /* try allocating MSI vector resources (at least 2) */ 9391 if (sc->interrupt_mode != INTR_MODE_MSI) { 9392 break; 9393 } 9394 9395 if (((sc->devinfo.pcie_cap_flags & BXE_MSI_CAPABLE_FLAG) == 0) || 9396 (msi_count < 1)) { 9397 sc->interrupt_mode = INTR_MODE_INTX; /* try INTx next */ 9398 break; 9399 } 9400 9401 /* ask for a single MSI vector */ 9402 num_requested = 1; 9403 9404 BLOGD(sc, DBG_LOAD, "Requesting %d MSI vectors\n", num_requested); 9405 9406 num_allocated = num_requested; 9407 if ((rc = pci_alloc_msi(sc->dev, &num_allocated)) != 0) { 9408 BLOGE(sc, "MSI alloc failed (%d)!\n", rc); 9409 sc->interrupt_mode = INTR_MODE_INTX; /* try INTx next */ 9410 break; 9411 } 9412 9413 if (num_allocated != 1) { /* possible? */ 9414 BLOGE(sc, "MSI allocation is not 1!\n"); 9415 sc->interrupt_mode = INTR_MODE_INTX; /* try INTx next */ 9416 pci_release_msi(sc->dev); 9417 break; 9418 } 9419 9420 BLOGI(sc, "MSI vectors Requested %d and Allocated %d\n", 9421 num_requested, num_allocated); 9422 9423 /* best effort so use the number of vectors allocated to us */ 9424 sc->intr_count = num_allocated; 9425 sc->num_queues = num_allocated; 9426 9427 rid = 1; /* initial resource identifier */ 9428 9429 sc->intr[0].rid = rid; 9430 9431 if ((sc->intr[0].resource = 9432 bus_alloc_resource_any(sc->dev, 9433 SYS_RES_IRQ, 9434 &sc->intr[0].rid, 9435 RF_ACTIVE)) == NULL) { 9436 BLOGE(sc, "Failed to map MSI[0] (rid=%d)!\n", rid); 9437 sc->intr_count = 0; 9438 sc->num_queues = 0; 9439 sc->interrupt_mode = INTR_MODE_INTX; /* try INTx next */ 9440 pci_release_msi(sc->dev); 9441 break; 9442 } 9443 9444 BLOGD(sc, DBG_LOAD, "Mapped MSI[0] (rid=%d)\n", rid); 9445 } while (0); 9446 9447 do { /* try allocating INTx vector resources */ 9448 if (sc->interrupt_mode != INTR_MODE_INTX) { 9449 break; 9450 } 9451 9452 BLOGD(sc, DBG_LOAD, "Requesting legacy INTx interrupt\n"); 9453 9454 /* only one vector for INTx */ 9455 sc->intr_count = 1; 9456 sc->num_queues = 1; 9457 9458 rid = 0; /* initial resource identifier */ 9459 9460 sc->intr[0].rid = rid; 9461 9462 if ((sc->intr[0].resource = 9463 bus_alloc_resource_any(sc->dev, 9464 SYS_RES_IRQ, 9465 &sc->intr[0].rid, 9466 (RF_ACTIVE | RF_SHAREABLE))) == NULL) { 9467 BLOGE(sc, "Failed to map INTx (rid=%d)!\n", rid); 9468 sc->intr_count = 0; 9469 sc->num_queues = 0; 9470 sc->interrupt_mode = -1; /* Failed! */ 9471 break; 9472 } 9473 9474 BLOGD(sc, DBG_LOAD, "Mapped INTx (rid=%d)\n", rid); 9475 } while (0); 9476 9477 if (sc->interrupt_mode == -1) { 9478 BLOGE(sc, "Interrupt Allocation: FAILED!!!\n"); 9479 rc = 1; 9480 } else { 9481 BLOGD(sc, DBG_LOAD, 9482 "Interrupt Allocation: interrupt_mode=%d, num_queues=%d\n", 9483 sc->interrupt_mode, sc->num_queues); 9484 rc = 0; 9485 } 9486 9487 return (rc); 9488 } 9489 9490 static void 9491 bxe_interrupt_detach(struct bxe_softc *sc) 9492 { 9493 struct bxe_fastpath *fp; 9494 int i; 9495 9496 /* release interrupt resources */ 9497 for (i = 0; i < sc->intr_count; i++) { 9498 if (sc->intr[i].resource && sc->intr[i].tag) { 9499 BLOGD(sc, DBG_LOAD, "Disabling interrupt vector %d\n", i); 9500 bus_teardown_intr(sc->dev, sc->intr[i].resource, sc->intr[i].tag); 9501 } 9502 } 9503 9504 for (i = 0; i < sc->num_queues; i++) { 9505 fp = &sc->fp[i]; 9506 if (fp->tq) { 9507 taskqueue_drain(fp->tq, &fp->tq_task); 9508 taskqueue_free(fp->tq); 9509 fp->tq = NULL; 9510 } 9511 } 9512 9513 if (sc->rx_mode_tq) { 9514 taskqueue_drain(sc->rx_mode_tq, &sc->rx_mode_tq_task); 9515 taskqueue_free(sc->rx_mode_tq); 9516 sc->rx_mode_tq = NULL; 9517 } 9518 9519 if (sc->sp_tq) { 9520 taskqueue_drain(sc->sp_tq, &sc->sp_tq_task); 9521 taskqueue_free(sc->sp_tq); 9522 sc->sp_tq = NULL; 9523 } 9524 } 9525 9526 /* 9527 * Enables interrupts and attach to the ISR. 9528 * 9529 * When using multiple MSI/MSI-X vectors the first vector 9530 * is used for slowpath operations while all remaining 9531 * vectors are used for fastpath operations. If only a 9532 * single MSI/MSI-X vector is used (SINGLE_ISR) then the 9533 * ISR must look for both slowpath and fastpath completions. 9534 */ 9535 static int 9536 bxe_interrupt_attach(struct bxe_softc *sc) 9537 { 9538 struct bxe_fastpath *fp; 9539 int rc = 0; 9540 int i; 9541 9542 snprintf(sc->sp_tq_name, sizeof(sc->sp_tq_name), 9543 "bxe%d_sp_tq", sc->unit); 9544 TASK_INIT(&sc->sp_tq_task, 0, bxe_handle_sp_tq, sc); 9545 sc->sp_tq = taskqueue_create_fast(sc->sp_tq_name, M_NOWAIT, 9546 taskqueue_thread_enqueue, 9547 &sc->sp_tq); 9548 taskqueue_start_threads(&sc->sp_tq, 1, PWAIT, /* lower priority */ 9549 "%s", sc->sp_tq_name); 9550 9551 snprintf(sc->rx_mode_tq_name, sizeof(sc->rx_mode_tq_name), 9552 "bxe%d_rx_mode_tq", sc->unit); 9553 TASK_INIT(&sc->rx_mode_tq_task, 0, bxe_handle_rx_mode_tq, sc); 9554 sc->rx_mode_tq = taskqueue_create_fast(sc->rx_mode_tq_name, M_NOWAIT, 9555 taskqueue_thread_enqueue, 9556 &sc->rx_mode_tq); 9557 taskqueue_start_threads(&sc->rx_mode_tq, 1, PWAIT, /* lower priority */ 9558 "%s", sc->rx_mode_tq_name); 9559 9560 for (i = 0; i < sc->num_queues; i++) { 9561 fp = &sc->fp[i]; 9562 snprintf(fp->tq_name, sizeof(fp->tq_name), 9563 "bxe%d_fp%d_tq", sc->unit, i); 9564 TASK_INIT(&fp->tq_task, 0, bxe_handle_fp_tq, fp); 9565 fp->tq = taskqueue_create_fast(fp->tq_name, M_NOWAIT, 9566 taskqueue_thread_enqueue, 9567 &fp->tq); 9568 taskqueue_start_threads(&fp->tq, 1, PI_NET, /* higher priority */ 9569 "%s", fp->tq_name); 9570 } 9571 9572 /* setup interrupt handlers */ 9573 if (sc->interrupt_mode == INTR_MODE_MSIX) { 9574 BLOGD(sc, DBG_LOAD, "Enabling slowpath MSI-X[0] vector\n"); 9575 9576 /* 9577 * Setup the interrupt handler. Note that we pass the driver instance 9578 * to the interrupt handler for the slowpath. 9579 */ 9580 if ((rc = bus_setup_intr(sc->dev, sc->intr[0].resource, 9581 (INTR_TYPE_NET | INTR_MPSAFE), 9582 NULL, bxe_intr_sp, sc, 9583 &sc->intr[0].tag)) != 0) { 9584 BLOGE(sc, "Failed to allocate MSI-X[0] vector (%d)\n", rc); 9585 goto bxe_interrupt_attach_exit; 9586 } 9587 9588 bus_describe_intr(sc->dev, sc->intr[0].resource, 9589 sc->intr[0].tag, "sp"); 9590 9591 /* bus_bind_intr(sc->dev, sc->intr[0].resource, 0); */ 9592 9593 /* initialize the fastpath vectors (note the first was used for sp) */ 9594 for (i = 0; i < sc->num_queues; i++) { 9595 fp = &sc->fp[i]; 9596 BLOGD(sc, DBG_LOAD, "Enabling MSI-X[%d] vector\n", (i + 1)); 9597 9598 /* 9599 * Setup the interrupt handler. Note that we pass the 9600 * fastpath context to the interrupt handler in this 9601 * case. 9602 */ 9603 if ((rc = bus_setup_intr(sc->dev, sc->intr[i + 1].resource, 9604 (INTR_TYPE_NET | INTR_MPSAFE), 9605 NULL, bxe_intr_fp, fp, 9606 &sc->intr[i + 1].tag)) != 0) { 9607 BLOGE(sc, "Failed to allocate MSI-X[%d] vector (%d)\n", 9608 (i + 1), rc); 9609 goto bxe_interrupt_attach_exit; 9610 } 9611 9612 bus_describe_intr(sc->dev, sc->intr[i + 1].resource, 9613 sc->intr[i + 1].tag, "fp%02d", i); 9614 9615 /* bind the fastpath instance to a cpu */ 9616 if (sc->num_queues > 1) { 9617 bus_bind_intr(sc->dev, sc->intr[i + 1].resource, i); 9618 } 9619 9620 fp->state = BXE_FP_STATE_IRQ; 9621 } 9622 } else if (sc->interrupt_mode == INTR_MODE_MSI) { 9623 BLOGD(sc, DBG_LOAD, "Enabling MSI[0] vector\n"); 9624 9625 /* 9626 * Setup the interrupt handler. Note that we pass the 9627 * driver instance to the interrupt handler which 9628 * will handle both the slowpath and fastpath. 9629 */ 9630 if ((rc = bus_setup_intr(sc->dev, sc->intr[0].resource, 9631 (INTR_TYPE_NET | INTR_MPSAFE), 9632 NULL, bxe_intr_legacy, sc, 9633 &sc->intr[0].tag)) != 0) { 9634 BLOGE(sc, "Failed to allocate MSI[0] vector (%d)\n", rc); 9635 goto bxe_interrupt_attach_exit; 9636 } 9637 9638 } else { /* (sc->interrupt_mode == INTR_MODE_INTX) */ 9639 BLOGD(sc, DBG_LOAD, "Enabling INTx interrupts\n"); 9640 9641 /* 9642 * Setup the interrupt handler. Note that we pass the 9643 * driver instance to the interrupt handler which 9644 * will handle both the slowpath and fastpath. 9645 */ 9646 if ((rc = bus_setup_intr(sc->dev, sc->intr[0].resource, 9647 (INTR_TYPE_NET | INTR_MPSAFE), 9648 NULL, bxe_intr_legacy, sc, 9649 &sc->intr[0].tag)) != 0) { 9650 BLOGE(sc, "Failed to allocate INTx interrupt (%d)\n", rc); 9651 goto bxe_interrupt_attach_exit; 9652 } 9653 } 9654 9655 bxe_interrupt_attach_exit: 9656 9657 return (rc); 9658 } 9659 9660 static int bxe_init_hw_common_chip(struct bxe_softc *sc); 9661 static int bxe_init_hw_common(struct bxe_softc *sc); 9662 static int bxe_init_hw_port(struct bxe_softc *sc); 9663 static int bxe_init_hw_func(struct bxe_softc *sc); 9664 static void bxe_reset_common(struct bxe_softc *sc); 9665 static void bxe_reset_port(struct bxe_softc *sc); 9666 static void bxe_reset_func(struct bxe_softc *sc); 9667 static int bxe_gunzip_init(struct bxe_softc *sc); 9668 static void bxe_gunzip_end(struct bxe_softc *sc); 9669 static int bxe_init_firmware(struct bxe_softc *sc); 9670 static void bxe_release_firmware(struct bxe_softc *sc); 9671 9672 static struct 9673 ecore_func_sp_drv_ops bxe_func_sp_drv = { 9674 .init_hw_cmn_chip = bxe_init_hw_common_chip, 9675 .init_hw_cmn = bxe_init_hw_common, 9676 .init_hw_port = bxe_init_hw_port, 9677 .init_hw_func = bxe_init_hw_func, 9678 9679 .reset_hw_cmn = bxe_reset_common, 9680 .reset_hw_port = bxe_reset_port, 9681 .reset_hw_func = bxe_reset_func, 9682 9683 .gunzip_init = bxe_gunzip_init, 9684 .gunzip_end = bxe_gunzip_end, 9685 9686 .init_fw = bxe_init_firmware, 9687 .release_fw = bxe_release_firmware, 9688 }; 9689 9690 static void 9691 bxe_init_func_obj(struct bxe_softc *sc) 9692 { 9693 sc->dmae_ready = 0; 9694 9695 ecore_init_func_obj(sc, 9696 &sc->func_obj, 9697 BXE_SP(sc, func_rdata), 9698 BXE_SP_MAPPING(sc, func_rdata), 9699 BXE_SP(sc, func_afex_rdata), 9700 BXE_SP_MAPPING(sc, func_afex_rdata), 9701 &bxe_func_sp_drv); 9702 } 9703 9704 static int 9705 bxe_init_hw(struct bxe_softc *sc, 9706 uint32_t load_code) 9707 { 9708 struct ecore_func_state_params func_params = { NULL }; 9709 int rc; 9710 9711 /* prepare the parameters for function state transitions */ 9712 bit_set(&func_params.ramrod_flags, RAMROD_COMP_WAIT); 9713 9714 func_params.f_obj = &sc->func_obj; 9715 func_params.cmd = ECORE_F_CMD_HW_INIT; 9716 9717 func_params.params.hw_init.load_phase = load_code; 9718 9719 /* 9720 * Via a plethora of function pointers, we will eventually reach 9721 * bxe_init_hw_common(), bxe_init_hw_port(), or bxe_init_hw_func(). 9722 */ 9723 rc = ecore_func_state_change(sc, &func_params); 9724 9725 return (rc); 9726 } 9727 9728 static void 9729 bxe_fill(struct bxe_softc *sc, 9730 uint32_t addr, 9731 int fill, 9732 uint32_t len) 9733 { 9734 uint32_t i; 9735 9736 if (!(len % 4) && !(addr % 4)) { 9737 for (i = 0; i < len; i += 4) { 9738 REG_WR(sc, (addr + i), fill); 9739 } 9740 } else { 9741 for (i = 0; i < len; i++) { 9742 REG_WR8(sc, (addr + i), fill); 9743 } 9744 } 9745 } 9746 9747 /* writes FP SP data to FW - data_size in dwords */ 9748 static void 9749 bxe_wr_fp_sb_data(struct bxe_softc *sc, 9750 int fw_sb_id, 9751 uint32_t *sb_data_p, 9752 uint32_t data_size) 9753 { 9754 int index; 9755 9756 for (index = 0; index < data_size; index++) { 9757 REG_WR(sc, 9758 (BAR_CSTRORM_INTMEM + 9759 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) + 9760 (sizeof(uint32_t) * index)), 9761 *(sb_data_p + index)); 9762 } 9763 } 9764 9765 static void 9766 bxe_zero_fp_sb(struct bxe_softc *sc, 9767 int fw_sb_id) 9768 { 9769 struct hc_status_block_data_e2 sb_data_e2; 9770 struct hc_status_block_data_e1x sb_data_e1x; 9771 uint32_t *sb_data_p; 9772 uint32_t data_size = 0; 9773 9774 if (!CHIP_IS_E1x(sc)) { 9775 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2)); 9776 sb_data_e2.common.state = SB_DISABLED; 9777 sb_data_e2.common.p_func.vf_valid = FALSE; 9778 sb_data_p = (uint32_t *)&sb_data_e2; 9779 data_size = (sizeof(struct hc_status_block_data_e2) / 9780 sizeof(uint32_t)); 9781 } else { 9782 memset(&sb_data_e1x, 0, sizeof(struct hc_status_block_data_e1x)); 9783 sb_data_e1x.common.state = SB_DISABLED; 9784 sb_data_e1x.common.p_func.vf_valid = FALSE; 9785 sb_data_p = (uint32_t *)&sb_data_e1x; 9786 data_size = (sizeof(struct hc_status_block_data_e1x) / 9787 sizeof(uint32_t)); 9788 } 9789 9790 bxe_wr_fp_sb_data(sc, fw_sb_id, sb_data_p, data_size); 9791 9792 bxe_fill(sc, (BAR_CSTRORM_INTMEM + CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id)), 9793 0, CSTORM_STATUS_BLOCK_SIZE); 9794 bxe_fill(sc, (BAR_CSTRORM_INTMEM + CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id)), 9795 0, CSTORM_SYNC_BLOCK_SIZE); 9796 } 9797 9798 static void 9799 bxe_wr_sp_sb_data(struct bxe_softc *sc, 9800 struct hc_sp_status_block_data *sp_sb_data) 9801 { 9802 int i; 9803 9804 for (i = 0; 9805 i < (sizeof(struct hc_sp_status_block_data) / sizeof(uint32_t)); 9806 i++) { 9807 REG_WR(sc, 9808 (BAR_CSTRORM_INTMEM + 9809 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(SC_FUNC(sc)) + 9810 (i * sizeof(uint32_t))), 9811 *((uint32_t *)sp_sb_data + i)); 9812 } 9813 } 9814 9815 static void 9816 bxe_zero_sp_sb(struct bxe_softc *sc) 9817 { 9818 struct hc_sp_status_block_data sp_sb_data; 9819 9820 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data)); 9821 9822 sp_sb_data.state = SB_DISABLED; 9823 sp_sb_data.p_func.vf_valid = FALSE; 9824 9825 bxe_wr_sp_sb_data(sc, &sp_sb_data); 9826 9827 bxe_fill(sc, 9828 (BAR_CSTRORM_INTMEM + 9829 CSTORM_SP_STATUS_BLOCK_OFFSET(SC_FUNC(sc))), 9830 0, CSTORM_SP_STATUS_BLOCK_SIZE); 9831 bxe_fill(sc, 9832 (BAR_CSTRORM_INTMEM + 9833 CSTORM_SP_SYNC_BLOCK_OFFSET(SC_FUNC(sc))), 9834 0, CSTORM_SP_SYNC_BLOCK_SIZE); 9835 } 9836 9837 static void 9838 bxe_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm, 9839 int igu_sb_id, 9840 int igu_seg_id) 9841 { 9842 hc_sm->igu_sb_id = igu_sb_id; 9843 hc_sm->igu_seg_id = igu_seg_id; 9844 hc_sm->timer_value = 0xFF; 9845 hc_sm->time_to_expire = 0xFFFFFFFF; 9846 } 9847 9848 static void 9849 bxe_map_sb_state_machines(struct hc_index_data *index_data) 9850 { 9851 /* zero out state machine indices */ 9852 9853 /* rx indices */ 9854 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID; 9855 9856 /* tx indices */ 9857 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID; 9858 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID; 9859 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID; 9860 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID; 9861 9862 /* map indices */ 9863 9864 /* rx indices */ 9865 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |= 9866 (SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT); 9867 9868 /* tx indices */ 9869 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |= 9870 (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT); 9871 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |= 9872 (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT); 9873 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |= 9874 (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT); 9875 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |= 9876 (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT); 9877 } 9878 9879 static void 9880 bxe_init_sb(struct bxe_softc *sc, 9881 bus_addr_t busaddr, 9882 int vfid, 9883 uint8_t vf_valid, 9884 int fw_sb_id, 9885 int igu_sb_id) 9886 { 9887 struct hc_status_block_data_e2 sb_data_e2; 9888 struct hc_status_block_data_e1x sb_data_e1x; 9889 struct hc_status_block_sm *hc_sm_p; 9890 uint32_t *sb_data_p; 9891 int igu_seg_id; 9892 int data_size; 9893 9894 if (CHIP_INT_MODE_IS_BC(sc)) { 9895 igu_seg_id = HC_SEG_ACCESS_NORM; 9896 } else { 9897 igu_seg_id = IGU_SEG_ACCESS_NORM; 9898 } 9899 9900 bxe_zero_fp_sb(sc, fw_sb_id); 9901 9902 if (!CHIP_IS_E1x(sc)) { 9903 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2)); 9904 sb_data_e2.common.state = SB_ENABLED; 9905 sb_data_e2.common.p_func.pf_id = SC_FUNC(sc); 9906 sb_data_e2.common.p_func.vf_id = vfid; 9907 sb_data_e2.common.p_func.vf_valid = vf_valid; 9908 sb_data_e2.common.p_func.vnic_id = SC_VN(sc); 9909 sb_data_e2.common.same_igu_sb_1b = TRUE; 9910 sb_data_e2.common.host_sb_addr.hi = U64_HI(busaddr); 9911 sb_data_e2.common.host_sb_addr.lo = U64_LO(busaddr); 9912 hc_sm_p = sb_data_e2.common.state_machine; 9913 sb_data_p = (uint32_t *)&sb_data_e2; 9914 data_size = (sizeof(struct hc_status_block_data_e2) / 9915 sizeof(uint32_t)); 9916 bxe_map_sb_state_machines(sb_data_e2.index_data); 9917 } else { 9918 memset(&sb_data_e1x, 0, sizeof(struct hc_status_block_data_e1x)); 9919 sb_data_e1x.common.state = SB_ENABLED; 9920 sb_data_e1x.common.p_func.pf_id = SC_FUNC(sc); 9921 sb_data_e1x.common.p_func.vf_id = 0xff; 9922 sb_data_e1x.common.p_func.vf_valid = FALSE; 9923 sb_data_e1x.common.p_func.vnic_id = SC_VN(sc); 9924 sb_data_e1x.common.same_igu_sb_1b = TRUE; 9925 sb_data_e1x.common.host_sb_addr.hi = U64_HI(busaddr); 9926 sb_data_e1x.common.host_sb_addr.lo = U64_LO(busaddr); 9927 hc_sm_p = sb_data_e1x.common.state_machine; 9928 sb_data_p = (uint32_t *)&sb_data_e1x; 9929 data_size = (sizeof(struct hc_status_block_data_e1x) / 9930 sizeof(uint32_t)); 9931 bxe_map_sb_state_machines(sb_data_e1x.index_data); 9932 } 9933 9934 bxe_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID], igu_sb_id, igu_seg_id); 9935 bxe_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID], igu_sb_id, igu_seg_id); 9936 9937 BLOGD(sc, DBG_LOAD, "Init FW SB %d\n", fw_sb_id); 9938 9939 /* write indices to HW - PCI guarantees endianity of regpairs */ 9940 bxe_wr_fp_sb_data(sc, fw_sb_id, sb_data_p, data_size); 9941 } 9942 9943 static inline uint8_t 9944 bxe_fp_qzone_id(struct bxe_fastpath *fp) 9945 { 9946 if (CHIP_IS_E1x(fp->sc)) { 9947 return (fp->cl_id + SC_PORT(fp->sc) * ETH_MAX_RX_CLIENTS_E1H); 9948 } else { 9949 return (fp->cl_id); 9950 } 9951 } 9952 9953 static inline uint32_t 9954 bxe_rx_ustorm_prods_offset(struct bxe_softc *sc, 9955 struct bxe_fastpath *fp) 9956 { 9957 uint32_t offset = BAR_USTRORM_INTMEM; 9958 9959 #if 0 9960 if (IS_VF(sc)) { 9961 return (PXP_VF_ADDR_USDM_QUEUES_START + 9962 (sc->acquire_resp.resc.hw_qid[fp->index] * 9963 sizeof(struct ustorm_queue_zone_data))); 9964 } else 9965 #endif 9966 if (!CHIP_IS_E1x(sc)) { 9967 offset += USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id); 9968 } else { 9969 offset += USTORM_RX_PRODS_E1X_OFFSET(SC_PORT(sc), fp->cl_id); 9970 } 9971 9972 return (offset); 9973 } 9974 9975 static void 9976 bxe_init_eth_fp(struct bxe_softc *sc, 9977 int idx) 9978 { 9979 struct bxe_fastpath *fp = &sc->fp[idx]; 9980 uint32_t cids[ECORE_MULTI_TX_COS] = { 0 }; 9981 unsigned long q_type = 0; 9982 int cos; 9983 9984 fp->sc = sc; 9985 fp->index = idx; 9986 9987 snprintf(fp->tx_mtx_name, sizeof(fp->tx_mtx_name), 9988 "bxe%d_fp%d_tx_lock", sc->unit, idx); 9989 mtx_init(&fp->tx_mtx, fp->tx_mtx_name, NULL, MTX_DEF); 9990 9991 snprintf(fp->rx_mtx_name, sizeof(fp->rx_mtx_name), 9992 "bxe%d_fp%d_rx_lock", sc->unit, idx); 9993 mtx_init(&fp->rx_mtx, fp->rx_mtx_name, NULL, MTX_DEF); 9994 9995 fp->igu_sb_id = (sc->igu_base_sb + idx + CNIC_SUPPORT(sc)); 9996 fp->fw_sb_id = (sc->base_fw_ndsb + idx + CNIC_SUPPORT(sc)); 9997 9998 fp->cl_id = (CHIP_IS_E1x(sc)) ? 9999 (SC_L_ID(sc) + idx) : 10000 /* want client ID same as IGU SB ID for non-E1 */ 10001 fp->igu_sb_id; 10002 fp->cl_qzone_id = bxe_fp_qzone_id(fp); 10003 10004 /* setup sb indices */ 10005 if (!CHIP_IS_E1x(sc)) { 10006 fp->sb_index_values = fp->status_block.e2_sb->sb.index_values; 10007 fp->sb_running_index = fp->status_block.e2_sb->sb.running_index; 10008 } else { 10009 fp->sb_index_values = fp->status_block.e1x_sb->sb.index_values; 10010 fp->sb_running_index = fp->status_block.e1x_sb->sb.running_index; 10011 } 10012 10013 /* init shortcut */ 10014 fp->ustorm_rx_prods_offset = bxe_rx_ustorm_prods_offset(sc, fp); 10015 10016 fp->rx_cq_cons_sb = &fp->sb_index_values[HC_INDEX_ETH_RX_CQ_CONS]; 10017 10018 /* 10019 * XXX If multiple CoS is ever supported then each fastpath structure 10020 * will need to maintain tx producer/consumer/dma/etc values *per* CoS. 10021 */ 10022 for (cos = 0; cos < sc->max_cos; cos++) { 10023 cids[cos] = idx; 10024 } 10025 fp->tx_cons_sb = &fp->sb_index_values[HC_INDEX_ETH_TX_CQ_CONS_COS0]; 10026 10027 /* nothing more for a VF to do */ 10028 if (IS_VF(sc)) { 10029 return; 10030 } 10031 10032 bxe_init_sb(sc, fp->sb_dma.paddr, BXE_VF_ID_INVALID, FALSE, 10033 fp->fw_sb_id, fp->igu_sb_id); 10034 10035 bxe_update_fp_sb_idx(fp); 10036 10037 /* Configure Queue State object */ 10038 bit_set(&q_type, ECORE_Q_TYPE_HAS_RX); 10039 bit_set(&q_type, ECORE_Q_TYPE_HAS_TX); 10040 10041 ecore_init_queue_obj(sc, 10042 &sc->sp_objs[idx].q_obj, 10043 fp->cl_id, 10044 cids, 10045 sc->max_cos, 10046 SC_FUNC(sc), 10047 BXE_SP(sc, q_rdata), 10048 BXE_SP_MAPPING(sc, q_rdata), 10049 q_type); 10050 10051 /* configure classification DBs */ 10052 ecore_init_mac_obj(sc, 10053 &sc->sp_objs[idx].mac_obj, 10054 fp->cl_id, 10055 idx, 10056 SC_FUNC(sc), 10057 BXE_SP(sc, mac_rdata), 10058 BXE_SP_MAPPING(sc, mac_rdata), 10059 ECORE_FILTER_MAC_PENDING, 10060 &sc->sp_state, 10061 ECORE_OBJ_TYPE_RX_TX, 10062 &sc->macs_pool); 10063 10064 BLOGD(sc, DBG_LOAD, "fp[%d]: sb=%p cl_id=%d fw_sb=%d igu_sb=%d\n", 10065 idx, fp->status_block.e2_sb, fp->cl_id, fp->fw_sb_id, fp->igu_sb_id); 10066 } 10067 10068 static inline void 10069 bxe_update_rx_prod(struct bxe_softc *sc, 10070 struct bxe_fastpath *fp, 10071 uint16_t rx_bd_prod, 10072 uint16_t rx_cq_prod, 10073 uint16_t rx_sge_prod) 10074 { 10075 struct ustorm_eth_rx_producers rx_prods = { 0 }; 10076 uint32_t i; 10077 10078 /* update producers */ 10079 rx_prods.bd_prod = rx_bd_prod; 10080 rx_prods.cqe_prod = rx_cq_prod; 10081 rx_prods.sge_prod = rx_sge_prod; 10082 10083 /* 10084 * Make sure that the BD and SGE data is updated before updating the 10085 * producers since FW might read the BD/SGE right after the producer 10086 * is updated. 10087 * This is only applicable for weak-ordered memory model archs such 10088 * as IA-64. The following barrier is also mandatory since FW will 10089 * assumes BDs must have buffers. 10090 */ 10091 wmb(); 10092 10093 for (i = 0; i < (sizeof(rx_prods) / 4); i++) { 10094 REG_WR(sc, 10095 (fp->ustorm_rx_prods_offset + (i * 4)), 10096 ((uint32_t *)&rx_prods)[i]); 10097 } 10098 10099 wmb(); /* keep prod updates ordered */ 10100 10101 BLOGD(sc, DBG_RX, 10102 "RX fp[%d]: wrote prods bd_prod=%u cqe_prod=%u sge_prod=%u\n", 10103 fp->index, rx_bd_prod, rx_cq_prod, rx_sge_prod); 10104 } 10105 10106 static void 10107 bxe_init_rx_rings(struct bxe_softc *sc) 10108 { 10109 struct bxe_fastpath *fp; 10110 int i; 10111 10112 for (i = 0; i < sc->num_queues; i++) { 10113 fp = &sc->fp[i]; 10114 10115 fp->rx_bd_cons = 0; 10116 10117 /* 10118 * Activate the BD ring... 10119 * Warning, this will generate an interrupt (to the TSTORM) 10120 * so this can only be done after the chip is initialized 10121 */ 10122 bxe_update_rx_prod(sc, fp, 10123 fp->rx_bd_prod, 10124 fp->rx_cq_prod, 10125 fp->rx_sge_prod); 10126 10127 if (i != 0) { 10128 continue; 10129 } 10130 10131 if (CHIP_IS_E1(sc)) { 10132 REG_WR(sc, 10133 (BAR_USTRORM_INTMEM + 10134 USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(SC_FUNC(sc))), 10135 U64_LO(fp->rcq_dma.paddr)); 10136 REG_WR(sc, 10137 (BAR_USTRORM_INTMEM + 10138 USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(SC_FUNC(sc)) + 4), 10139 U64_HI(fp->rcq_dma.paddr)); 10140 } 10141 } 10142 } 10143 10144 static void 10145 bxe_init_tx_ring_one(struct bxe_fastpath *fp) 10146 { 10147 SET_FLAG(fp->tx_db.data.header.header, DOORBELL_HDR_DB_TYPE, 1); 10148 fp->tx_db.data.zero_fill1 = 0; 10149 fp->tx_db.data.prod = 0; 10150 10151 fp->tx_pkt_prod = 0; 10152 fp->tx_pkt_cons = 0; 10153 fp->tx_bd_prod = 0; 10154 fp->tx_bd_cons = 0; 10155 fp->eth_q_stats.tx_pkts = 0; 10156 } 10157 10158 static inline void 10159 bxe_init_tx_rings(struct bxe_softc *sc) 10160 { 10161 int i; 10162 10163 for (i = 0; i < sc->num_queues; i++) { 10164 #if 0 10165 uint8_t cos; 10166 for (cos = 0; cos < sc->max_cos; cos++) { 10167 bxe_init_tx_ring_one(&sc->fp[i].txdata[cos]); 10168 } 10169 #else 10170 bxe_init_tx_ring_one(&sc->fp[i]); 10171 #endif 10172 } 10173 } 10174 10175 static void 10176 bxe_init_def_sb(struct bxe_softc *sc) 10177 { 10178 struct host_sp_status_block *def_sb = sc->def_sb; 10179 bus_addr_t mapping = sc->def_sb_dma.paddr; 10180 int igu_sp_sb_index; 10181 int igu_seg_id; 10182 int port = SC_PORT(sc); 10183 int func = SC_FUNC(sc); 10184 int reg_offset, reg_offset_en5; 10185 uint64_t section; 10186 int index, sindex; 10187 struct hc_sp_status_block_data sp_sb_data; 10188 10189 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data)); 10190 10191 if (CHIP_INT_MODE_IS_BC(sc)) { 10192 igu_sp_sb_index = DEF_SB_IGU_ID; 10193 igu_seg_id = HC_SEG_ACCESS_DEF; 10194 } else { 10195 igu_sp_sb_index = sc->igu_dsb_id; 10196 igu_seg_id = IGU_SEG_ACCESS_DEF; 10197 } 10198 10199 /* attentions */ 10200 section = ((uint64_t)mapping + 10201 offsetof(struct host_sp_status_block, atten_status_block)); 10202 def_sb->atten_status_block.status_block_id = igu_sp_sb_index; 10203 sc->attn_state = 0; 10204 10205 reg_offset = (port) ? 10206 MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : 10207 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0; 10208 reg_offset_en5 = (port) ? 10209 MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 : 10210 MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0; 10211 10212 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) { 10213 /* take care of sig[0]..sig[4] */ 10214 for (sindex = 0; sindex < 4; sindex++) { 10215 sc->attn_group[index].sig[sindex] = 10216 REG_RD(sc, (reg_offset + (sindex * 0x4) + (0x10 * index))); 10217 } 10218 10219 if (!CHIP_IS_E1x(sc)) { 10220 /* 10221 * enable5 is separate from the rest of the registers, 10222 * and the address skip is 4 and not 16 between the 10223 * different groups 10224 */ 10225 sc->attn_group[index].sig[4] = 10226 REG_RD(sc, (reg_offset_en5 + (0x4 * index))); 10227 } else { 10228 sc->attn_group[index].sig[4] = 0; 10229 } 10230 } 10231 10232 if (sc->devinfo.int_block == INT_BLOCK_HC) { 10233 reg_offset = (port) ? 10234 HC_REG_ATTN_MSG1_ADDR_L : 10235 HC_REG_ATTN_MSG0_ADDR_L; 10236 REG_WR(sc, reg_offset, U64_LO(section)); 10237 REG_WR(sc, (reg_offset + 4), U64_HI(section)); 10238 } else if (!CHIP_IS_E1x(sc)) { 10239 REG_WR(sc, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section)); 10240 REG_WR(sc, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section)); 10241 } 10242 10243 section = ((uint64_t)mapping + 10244 offsetof(struct host_sp_status_block, sp_sb)); 10245 10246 bxe_zero_sp_sb(sc); 10247 10248 /* PCI guarantees endianity of regpair */ 10249 sp_sb_data.state = SB_ENABLED; 10250 sp_sb_data.host_sb_addr.lo = U64_LO(section); 10251 sp_sb_data.host_sb_addr.hi = U64_HI(section); 10252 sp_sb_data.igu_sb_id = igu_sp_sb_index; 10253 sp_sb_data.igu_seg_id = igu_seg_id; 10254 sp_sb_data.p_func.pf_id = func; 10255 sp_sb_data.p_func.vnic_id = SC_VN(sc); 10256 sp_sb_data.p_func.vf_id = 0xff; 10257 10258 bxe_wr_sp_sb_data(sc, &sp_sb_data); 10259 10260 bxe_ack_sb(sc, sc->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0); 10261 } 10262 10263 static void 10264 bxe_init_sp_ring(struct bxe_softc *sc) 10265 { 10266 atomic_store_rel_long(&sc->cq_spq_left, MAX_SPQ_PENDING); 10267 sc->spq_prod_idx = 0; 10268 sc->dsb_sp_prod = &sc->def_sb->sp_sb.index_values[HC_SP_INDEX_ETH_DEF_CONS]; 10269 sc->spq_prod_bd = sc->spq; 10270 sc->spq_last_bd = (sc->spq_prod_bd + MAX_SP_DESC_CNT); 10271 } 10272 10273 static void 10274 bxe_init_eq_ring(struct bxe_softc *sc) 10275 { 10276 union event_ring_elem *elem; 10277 int i; 10278 10279 for (i = 1; i <= NUM_EQ_PAGES; i++) { 10280 elem = &sc->eq[EQ_DESC_CNT_PAGE * i - 1]; 10281 10282 elem->next_page.addr.hi = htole32(U64_HI(sc->eq_dma.paddr + 10283 BCM_PAGE_SIZE * 10284 (i % NUM_EQ_PAGES))); 10285 elem->next_page.addr.lo = htole32(U64_LO(sc->eq_dma.paddr + 10286 BCM_PAGE_SIZE * 10287 (i % NUM_EQ_PAGES))); 10288 } 10289 10290 sc->eq_cons = 0; 10291 sc->eq_prod = NUM_EQ_DESC; 10292 sc->eq_cons_sb = &sc->def_sb->sp_sb.index_values[HC_SP_INDEX_EQ_CONS]; 10293 10294 atomic_store_rel_long(&sc->eq_spq_left, 10295 (min((MAX_SP_DESC_CNT - MAX_SPQ_PENDING), 10296 NUM_EQ_DESC) - 1)); 10297 } 10298 10299 static void 10300 bxe_init_internal_common(struct bxe_softc *sc) 10301 { 10302 int i; 10303 10304 if (IS_MF_SI(sc)) { 10305 /* 10306 * In switch independent mode, the TSTORM needs to accept 10307 * packets that failed classification, since approximate match 10308 * mac addresses aren't written to NIG LLH. 10309 */ 10310 REG_WR8(sc, 10311 (BAR_TSTRORM_INTMEM + TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET), 10312 2); 10313 } else if (!CHIP_IS_E1(sc)) { /* 57710 doesn't support MF */ 10314 REG_WR8(sc, 10315 (BAR_TSTRORM_INTMEM + TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET), 10316 0); 10317 } 10318 10319 /* 10320 * Zero this manually as its initialization is currently missing 10321 * in the initTool. 10322 */ 10323 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++) { 10324 REG_WR(sc, 10325 (BAR_USTRORM_INTMEM + USTORM_AGG_DATA_OFFSET + (i * 4)), 10326 0); 10327 } 10328 10329 if (!CHIP_IS_E1x(sc)) { 10330 REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET), 10331 CHIP_INT_MODE_IS_BC(sc) ? HC_IGU_BC_MODE : HC_IGU_NBC_MODE); 10332 } 10333 } 10334 10335 static void 10336 bxe_init_internal(struct bxe_softc *sc, 10337 uint32_t load_code) 10338 { 10339 switch (load_code) { 10340 case FW_MSG_CODE_DRV_LOAD_COMMON: 10341 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP: 10342 bxe_init_internal_common(sc); 10343 /* no break */ 10344 10345 case FW_MSG_CODE_DRV_LOAD_PORT: 10346 /* nothing to do */ 10347 /* no break */ 10348 10349 case FW_MSG_CODE_DRV_LOAD_FUNCTION: 10350 /* internal memory per function is initialized inside bxe_pf_init */ 10351 break; 10352 10353 default: 10354 BLOGE(sc, "Unknown load_code (0x%x) from MCP\n", load_code); 10355 break; 10356 } 10357 } 10358 10359 static void 10360 storm_memset_func_cfg(struct bxe_softc *sc, 10361 struct tstorm_eth_function_common_config *tcfg, 10362 uint16_t abs_fid) 10363 { 10364 uint32_t addr; 10365 size_t size; 10366 10367 addr = (BAR_TSTRORM_INTMEM + 10368 TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid)); 10369 size = sizeof(struct tstorm_eth_function_common_config); 10370 ecore_storm_memset_struct(sc, addr, size, (uint32_t *)tcfg); 10371 } 10372 10373 static void 10374 bxe_func_init(struct bxe_softc *sc, 10375 struct bxe_func_init_params *p) 10376 { 10377 struct tstorm_eth_function_common_config tcfg = { 0 }; 10378 10379 if (CHIP_IS_E1x(sc)) { 10380 storm_memset_func_cfg(sc, &tcfg, p->func_id); 10381 } 10382 10383 /* Enable the function in the FW */ 10384 storm_memset_vf_to_pf(sc, p->func_id, p->pf_id); 10385 storm_memset_func_en(sc, p->func_id, 1); 10386 10387 /* spq */ 10388 if (p->func_flgs & FUNC_FLG_SPQ) { 10389 storm_memset_spq_addr(sc, p->spq_map, p->func_id); 10390 REG_WR(sc, 10391 (XSEM_REG_FAST_MEMORY + XSTORM_SPQ_PROD_OFFSET(p->func_id)), 10392 p->spq_prod); 10393 } 10394 } 10395 10396 /* 10397 * Calculates the sum of vn_min_rates. 10398 * It's needed for further normalizing of the min_rates. 10399 * Returns: 10400 * sum of vn_min_rates. 10401 * or 10402 * 0 - if all the min_rates are 0. 10403 * In the later case fainess algorithm should be deactivated. 10404 * If all min rates are not zero then those that are zeroes will be set to 1. 10405 */ 10406 static void 10407 bxe_calc_vn_min(struct bxe_softc *sc, 10408 struct cmng_init_input *input) 10409 { 10410 uint32_t vn_cfg; 10411 uint32_t vn_min_rate; 10412 int all_zero = 1; 10413 int vn; 10414 10415 for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) { 10416 vn_cfg = sc->devinfo.mf_info.mf_config[vn]; 10417 vn_min_rate = (((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >> 10418 FUNC_MF_CFG_MIN_BW_SHIFT) * 100); 10419 10420 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) { 10421 /* skip hidden VNs */ 10422 vn_min_rate = 0; 10423 } else if (!vn_min_rate) { 10424 /* If min rate is zero - set it to 100 */ 10425 vn_min_rate = DEF_MIN_RATE; 10426 } else { 10427 all_zero = 0; 10428 } 10429 10430 input->vnic_min_rate[vn] = vn_min_rate; 10431 } 10432 10433 /* if ETS or all min rates are zeros - disable fairness */ 10434 if (BXE_IS_ETS_ENABLED(sc)) { 10435 input->flags.cmng_enables &= ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN; 10436 BLOGD(sc, DBG_LOAD, "Fairness disabled (ETS)\n"); 10437 } else if (all_zero) { 10438 input->flags.cmng_enables &= ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN; 10439 BLOGD(sc, DBG_LOAD, 10440 "Fariness disabled (all MIN values are zeroes)\n"); 10441 } else { 10442 input->flags.cmng_enables |= CMNG_FLAGS_PER_PORT_FAIRNESS_VN; 10443 } 10444 } 10445 10446 static inline uint16_t 10447 bxe_extract_max_cfg(struct bxe_softc *sc, 10448 uint32_t mf_cfg) 10449 { 10450 uint16_t max_cfg = ((mf_cfg & FUNC_MF_CFG_MAX_BW_MASK) >> 10451 FUNC_MF_CFG_MAX_BW_SHIFT); 10452 10453 if (!max_cfg) { 10454 BLOGD(sc, DBG_LOAD, "Max BW configured to 0 - using 100 instead\n"); 10455 max_cfg = 100; 10456 } 10457 10458 return (max_cfg); 10459 } 10460 10461 static void 10462 bxe_calc_vn_max(struct bxe_softc *sc, 10463 int vn, 10464 struct cmng_init_input *input) 10465 { 10466 uint16_t vn_max_rate; 10467 uint32_t vn_cfg = sc->devinfo.mf_info.mf_config[vn]; 10468 uint32_t max_cfg; 10469 10470 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) { 10471 vn_max_rate = 0; 10472 } else { 10473 max_cfg = bxe_extract_max_cfg(sc, vn_cfg); 10474 10475 if (IS_MF_SI(sc)) { 10476 /* max_cfg in percents of linkspeed */ 10477 vn_max_rate = ((sc->link_vars.line_speed * max_cfg) / 100); 10478 } else { /* SD modes */ 10479 /* max_cfg is absolute in 100Mb units */ 10480 vn_max_rate = (max_cfg * 100); 10481 } 10482 } 10483 10484 BLOGD(sc, DBG_LOAD, "vn %d: vn_max_rate %d\n", vn, vn_max_rate); 10485 10486 input->vnic_max_rate[vn] = vn_max_rate; 10487 } 10488 10489 static void 10490 bxe_cmng_fns_init(struct bxe_softc *sc, 10491 uint8_t read_cfg, 10492 uint8_t cmng_type) 10493 { 10494 struct cmng_init_input input; 10495 int vn; 10496 10497 memset(&input, 0, sizeof(struct cmng_init_input)); 10498 10499 input.port_rate = sc->link_vars.line_speed; 10500 10501 if (cmng_type == CMNG_FNS_MINMAX) { 10502 /* read mf conf from shmem */ 10503 if (read_cfg) { 10504 bxe_read_mf_cfg(sc); 10505 } 10506 10507 /* get VN min rate and enable fairness if not 0 */ 10508 bxe_calc_vn_min(sc, &input); 10509 10510 /* get VN max rate */ 10511 if (sc->port.pmf) { 10512 for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) { 10513 bxe_calc_vn_max(sc, vn, &input); 10514 } 10515 } 10516 10517 /* always enable rate shaping and fairness */ 10518 input.flags.cmng_enables |= CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN; 10519 10520 ecore_init_cmng(&input, &sc->cmng); 10521 return; 10522 } 10523 10524 /* rate shaping and fairness are disabled */ 10525 BLOGD(sc, DBG_LOAD, "rate shaping and fairness have been disabled\n"); 10526 } 10527 10528 static int 10529 bxe_get_cmng_fns_mode(struct bxe_softc *sc) 10530 { 10531 if (CHIP_REV_IS_SLOW(sc)) { 10532 return (CMNG_FNS_NONE); 10533 } 10534 10535 if (IS_MF(sc)) { 10536 return (CMNG_FNS_MINMAX); 10537 } 10538 10539 return (CMNG_FNS_NONE); 10540 } 10541 10542 static void 10543 storm_memset_cmng(struct bxe_softc *sc, 10544 struct cmng_init *cmng, 10545 uint8_t port) 10546 { 10547 int vn; 10548 int func; 10549 uint32_t addr; 10550 size_t size; 10551 10552 addr = (BAR_XSTRORM_INTMEM + 10553 XSTORM_CMNG_PER_PORT_VARS_OFFSET(port)); 10554 size = sizeof(struct cmng_struct_per_port); 10555 ecore_storm_memset_struct(sc, addr, size, (uint32_t *)&cmng->port); 10556 10557 for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) { 10558 func = func_by_vn(sc, vn); 10559 10560 addr = (BAR_XSTRORM_INTMEM + 10561 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func)); 10562 size = sizeof(struct rate_shaping_vars_per_vn); 10563 ecore_storm_memset_struct(sc, addr, size, 10564 (uint32_t *)&cmng->vnic.vnic_max_rate[vn]); 10565 10566 addr = (BAR_XSTRORM_INTMEM + 10567 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func)); 10568 size = sizeof(struct fairness_vars_per_vn); 10569 ecore_storm_memset_struct(sc, addr, size, 10570 (uint32_t *)&cmng->vnic.vnic_min_rate[vn]); 10571 } 10572 } 10573 10574 static void 10575 bxe_pf_init(struct bxe_softc *sc) 10576 { 10577 struct bxe_func_init_params func_init = { 0 }; 10578 struct event_ring_data eq_data = { { 0 } }; 10579 uint16_t flags; 10580 10581 if (!CHIP_IS_E1x(sc)) { 10582 /* reset IGU PF statistics: MSIX + ATTN */ 10583 /* PF */ 10584 REG_WR(sc, 10585 (IGU_REG_STATISTIC_NUM_MESSAGE_SENT + 10586 (BXE_IGU_STAS_MSG_VF_CNT * 4) + 10587 ((CHIP_IS_MODE_4_PORT(sc) ? SC_FUNC(sc) : SC_VN(sc)) * 4)), 10588 0); 10589 /* ATTN */ 10590 REG_WR(sc, 10591 (IGU_REG_STATISTIC_NUM_MESSAGE_SENT + 10592 (BXE_IGU_STAS_MSG_VF_CNT * 4) + 10593 (BXE_IGU_STAS_MSG_PF_CNT * 4) + 10594 ((CHIP_IS_MODE_4_PORT(sc) ? SC_FUNC(sc) : SC_VN(sc)) * 4)), 10595 0); 10596 } 10597 10598 /* function setup flags */ 10599 flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ); 10600 10601 /* 10602 * This flag is relevant for E1x only. 10603 * E2 doesn't have a TPA configuration in a function level. 10604 */ 10605 flags |= (sc->ifnet->if_capenable & IFCAP_LRO) ? FUNC_FLG_TPA : 0; 10606 10607 func_init.func_flgs = flags; 10608 func_init.pf_id = SC_FUNC(sc); 10609 func_init.func_id = SC_FUNC(sc); 10610 func_init.spq_map = sc->spq_dma.paddr; 10611 func_init.spq_prod = sc->spq_prod_idx; 10612 10613 bxe_func_init(sc, &func_init); 10614 10615 memset(&sc->cmng, 0, sizeof(struct cmng_struct_per_port)); 10616 10617 /* 10618 * Congestion management values depend on the link rate. 10619 * There is no active link so initial link rate is set to 10Gbps. 10620 * When the link comes up the congestion management values are 10621 * re-calculated according to the actual link rate. 10622 */ 10623 sc->link_vars.line_speed = SPEED_10000; 10624 bxe_cmng_fns_init(sc, TRUE, bxe_get_cmng_fns_mode(sc)); 10625 10626 /* Only the PMF sets the HW */ 10627 if (sc->port.pmf) { 10628 storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc)); 10629 } 10630 10631 /* init Event Queue - PCI bus guarantees correct endainity */ 10632 eq_data.base_addr.hi = U64_HI(sc->eq_dma.paddr); 10633 eq_data.base_addr.lo = U64_LO(sc->eq_dma.paddr); 10634 eq_data.producer = sc->eq_prod; 10635 eq_data.index_id = HC_SP_INDEX_EQ_CONS; 10636 eq_data.sb_id = DEF_SB_ID; 10637 storm_memset_eq_data(sc, &eq_data, SC_FUNC(sc)); 10638 } 10639 10640 static void 10641 bxe_hc_int_enable(struct bxe_softc *sc) 10642 { 10643 int port = SC_PORT(sc); 10644 uint32_t addr = (port) ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0; 10645 uint32_t val = REG_RD(sc, addr); 10646 uint8_t msix = (sc->interrupt_mode == INTR_MODE_MSIX) ? TRUE : FALSE; 10647 uint8_t single_msix = ((sc->interrupt_mode == INTR_MODE_MSIX) && 10648 (sc->intr_count == 1)) ? TRUE : FALSE; 10649 uint8_t msi = (sc->interrupt_mode == INTR_MODE_MSI) ? TRUE : FALSE; 10650 10651 if (msix) { 10652 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | 10653 HC_CONFIG_0_REG_INT_LINE_EN_0); 10654 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | 10655 HC_CONFIG_0_REG_ATTN_BIT_EN_0); 10656 if (single_msix) { 10657 val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0; 10658 } 10659 } else if (msi) { 10660 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0; 10661 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | 10662 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | 10663 HC_CONFIG_0_REG_ATTN_BIT_EN_0); 10664 } else { 10665 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | 10666 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | 10667 HC_CONFIG_0_REG_INT_LINE_EN_0 | 10668 HC_CONFIG_0_REG_ATTN_BIT_EN_0); 10669 10670 if (!CHIP_IS_E1(sc)) { 10671 BLOGD(sc, DBG_INTR, "write %x to HC %d (addr 0x%x)\n", 10672 val, port, addr); 10673 10674 REG_WR(sc, addr, val); 10675 10676 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0; 10677 } 10678 } 10679 10680 if (CHIP_IS_E1(sc)) { 10681 REG_WR(sc, (HC_REG_INT_MASK + port*4), 0x1FFFF); 10682 } 10683 10684 BLOGD(sc, DBG_INTR, "write %x to HC %d (addr 0x%x) mode %s\n", 10685 val, port, addr, ((msix) ? "MSI-X" : ((msi) ? "MSI" : "INTx"))); 10686 10687 REG_WR(sc, addr, val); 10688 10689 /* ensure that HC_CONFIG is written before leading/trailing edge config */ 10690 mb(); 10691 10692 if (!CHIP_IS_E1(sc)) { 10693 /* init leading/trailing edge */ 10694 if (IS_MF(sc)) { 10695 val = (0xee0f | (1 << (SC_VN(sc) + 4))); 10696 if (sc->port.pmf) { 10697 /* enable nig and gpio3 attention */ 10698 val |= 0x1100; 10699 } 10700 } else { 10701 val = 0xffff; 10702 } 10703 10704 REG_WR(sc, (HC_REG_TRAILING_EDGE_0 + port*8), val); 10705 REG_WR(sc, (HC_REG_LEADING_EDGE_0 + port*8), val); 10706 } 10707 10708 /* make sure that interrupts are indeed enabled from here on */ 10709 mb(); 10710 } 10711 10712 static void 10713 bxe_igu_int_enable(struct bxe_softc *sc) 10714 { 10715 uint32_t val; 10716 uint8_t msix = (sc->interrupt_mode == INTR_MODE_MSIX) ? TRUE : FALSE; 10717 uint8_t single_msix = ((sc->interrupt_mode == INTR_MODE_MSIX) && 10718 (sc->intr_count == 1)) ? TRUE : FALSE; 10719 uint8_t msi = (sc->interrupt_mode == INTR_MODE_MSI) ? TRUE : FALSE; 10720 10721 val = REG_RD(sc, IGU_REG_PF_CONFIGURATION); 10722 10723 if (msix) { 10724 val &= ~(IGU_PF_CONF_INT_LINE_EN | 10725 IGU_PF_CONF_SINGLE_ISR_EN); 10726 val |= (IGU_PF_CONF_MSI_MSIX_EN | 10727 IGU_PF_CONF_ATTN_BIT_EN); 10728 if (single_msix) { 10729 val |= IGU_PF_CONF_SINGLE_ISR_EN; 10730 } 10731 } else if (msi) { 10732 val &= ~IGU_PF_CONF_INT_LINE_EN; 10733 val |= (IGU_PF_CONF_MSI_MSIX_EN | 10734 IGU_PF_CONF_ATTN_BIT_EN | 10735 IGU_PF_CONF_SINGLE_ISR_EN); 10736 } else { 10737 val &= ~IGU_PF_CONF_MSI_MSIX_EN; 10738 val |= (IGU_PF_CONF_INT_LINE_EN | 10739 IGU_PF_CONF_ATTN_BIT_EN | 10740 IGU_PF_CONF_SINGLE_ISR_EN); 10741 } 10742 10743 /* clean previous status - need to configure igu prior to ack*/ 10744 if ((!msix) || single_msix) { 10745 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val); 10746 bxe_ack_int(sc); 10747 } 10748 10749 val |= IGU_PF_CONF_FUNC_EN; 10750 10751 BLOGD(sc, DBG_INTR, "write 0x%x to IGU mode %s\n", 10752 val, ((msix) ? "MSI-X" : ((msi) ? "MSI" : "INTx"))); 10753 10754 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val); 10755 10756 mb(); 10757 10758 /* init leading/trailing edge */ 10759 if (IS_MF(sc)) { 10760 val = (0xee0f | (1 << (SC_VN(sc) + 4))); 10761 if (sc->port.pmf) { 10762 /* enable nig and gpio3 attention */ 10763 val |= 0x1100; 10764 } 10765 } else { 10766 val = 0xffff; 10767 } 10768 10769 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, val); 10770 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, val); 10771 10772 /* make sure that interrupts are indeed enabled from here on */ 10773 mb(); 10774 } 10775 10776 static void 10777 bxe_int_enable(struct bxe_softc *sc) 10778 { 10779 if (sc->devinfo.int_block == INT_BLOCK_HC) { 10780 bxe_hc_int_enable(sc); 10781 } else { 10782 bxe_igu_int_enable(sc); 10783 } 10784 } 10785 10786 static void 10787 bxe_hc_int_disable(struct bxe_softc *sc) 10788 { 10789 int port = SC_PORT(sc); 10790 uint32_t addr = (port) ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0; 10791 uint32_t val = REG_RD(sc, addr); 10792 10793 /* 10794 * In E1 we must use only PCI configuration space to disable MSI/MSIX 10795 * capablility. It's forbidden to disable IGU_PF_CONF_MSI_MSIX_EN in HC 10796 * block 10797 */ 10798 if (CHIP_IS_E1(sc)) { 10799 /* 10800 * Since IGU_PF_CONF_MSI_MSIX_EN still always on use mask register 10801 * to prevent from HC sending interrupts after we exit the function 10802 */ 10803 REG_WR(sc, (HC_REG_INT_MASK + port*4), 0); 10804 10805 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | 10806 HC_CONFIG_0_REG_INT_LINE_EN_0 | 10807 HC_CONFIG_0_REG_ATTN_BIT_EN_0); 10808 } else { 10809 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | 10810 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | 10811 HC_CONFIG_0_REG_INT_LINE_EN_0 | 10812 HC_CONFIG_0_REG_ATTN_BIT_EN_0); 10813 } 10814 10815 BLOGD(sc, DBG_INTR, "write %x to HC %d (addr 0x%x)\n", val, port, addr); 10816 10817 /* flush all outstanding writes */ 10818 mb(); 10819 10820 REG_WR(sc, addr, val); 10821 if (REG_RD(sc, addr) != val) { 10822 BLOGE(sc, "proper val not read from HC IGU!\n"); 10823 } 10824 } 10825 10826 static void 10827 bxe_igu_int_disable(struct bxe_softc *sc) 10828 { 10829 uint32_t val = REG_RD(sc, IGU_REG_PF_CONFIGURATION); 10830 10831 val &= ~(IGU_PF_CONF_MSI_MSIX_EN | 10832 IGU_PF_CONF_INT_LINE_EN | 10833 IGU_PF_CONF_ATTN_BIT_EN); 10834 10835 BLOGD(sc, DBG_INTR, "write %x to IGU\n", val); 10836 10837 /* flush all outstanding writes */ 10838 mb(); 10839 10840 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val); 10841 if (REG_RD(sc, IGU_REG_PF_CONFIGURATION) != val) { 10842 BLOGE(sc, "proper val not read from IGU!\n"); 10843 } 10844 } 10845 10846 static void 10847 bxe_int_disable(struct bxe_softc *sc) 10848 { 10849 if (sc->devinfo.int_block == INT_BLOCK_HC) { 10850 bxe_hc_int_disable(sc); 10851 } else { 10852 bxe_igu_int_disable(sc); 10853 } 10854 } 10855 10856 static void 10857 bxe_nic_init(struct bxe_softc *sc, 10858 int load_code) 10859 { 10860 int i; 10861 10862 for (i = 0; i < sc->num_queues; i++) { 10863 bxe_init_eth_fp(sc, i); 10864 } 10865 10866 rmb(); /* ensure status block indices were read */ 10867 10868 bxe_init_rx_rings(sc); 10869 bxe_init_tx_rings(sc); 10870 10871 if (IS_VF(sc)) { 10872 return; 10873 } 10874 10875 /* initialize MOD_ABS interrupts */ 10876 elink_init_mod_abs_int(sc, &sc->link_vars, 10877 sc->devinfo.chip_id, 10878 sc->devinfo.shmem_base, 10879 sc->devinfo.shmem2_base, 10880 SC_PORT(sc)); 10881 10882 bxe_init_def_sb(sc); 10883 bxe_update_dsb_idx(sc); 10884 bxe_init_sp_ring(sc); 10885 bxe_init_eq_ring(sc); 10886 bxe_init_internal(sc, load_code); 10887 bxe_pf_init(sc); 10888 bxe_stats_init(sc); 10889 10890 /* flush all before enabling interrupts */ 10891 mb(); 10892 10893 bxe_int_enable(sc); 10894 10895 /* check for SPIO5 */ 10896 bxe_attn_int_deasserted0(sc, 10897 REG_RD(sc, 10898 (MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + 10899 SC_PORT(sc)*4)) & 10900 AEU_INPUTS_ATTN_BITS_SPIO5); 10901 } 10902 10903 static inline void 10904 bxe_init_objs(struct bxe_softc *sc) 10905 { 10906 /* mcast rules must be added to tx if tx switching is enabled */ 10907 ecore_obj_type o_type = 10908 (sc->flags & BXE_TX_SWITCHING) ? ECORE_OBJ_TYPE_RX_TX : 10909 ECORE_OBJ_TYPE_RX; 10910 10911 /* RX_MODE controlling object */ 10912 ecore_init_rx_mode_obj(sc, &sc->rx_mode_obj); 10913 10914 /* multicast configuration controlling object */ 10915 ecore_init_mcast_obj(sc, 10916 &sc->mcast_obj, 10917 sc->fp[0].cl_id, 10918 sc->fp[0].index, 10919 SC_FUNC(sc), 10920 SC_FUNC(sc), 10921 BXE_SP(sc, mcast_rdata), 10922 BXE_SP_MAPPING(sc, mcast_rdata), 10923 ECORE_FILTER_MCAST_PENDING, 10924 &sc->sp_state, 10925 o_type); 10926 10927 /* Setup CAM credit pools */ 10928 ecore_init_mac_credit_pool(sc, 10929 &sc->macs_pool, 10930 SC_FUNC(sc), 10931 CHIP_IS_E1x(sc) ? VNICS_PER_PORT(sc) : 10932 VNICS_PER_PATH(sc)); 10933 10934 ecore_init_vlan_credit_pool(sc, 10935 &sc->vlans_pool, 10936 SC_ABS_FUNC(sc) >> 1, 10937 CHIP_IS_E1x(sc) ? VNICS_PER_PORT(sc) : 10938 VNICS_PER_PATH(sc)); 10939 10940 /* RSS configuration object */ 10941 ecore_init_rss_config_obj(sc, 10942 &sc->rss_conf_obj, 10943 sc->fp[0].cl_id, 10944 sc->fp[0].index, 10945 SC_FUNC(sc), 10946 SC_FUNC(sc), 10947 BXE_SP(sc, rss_rdata), 10948 BXE_SP_MAPPING(sc, rss_rdata), 10949 ECORE_FILTER_RSS_CONF_PENDING, 10950 &sc->sp_state, ECORE_OBJ_TYPE_RX); 10951 } 10952 10953 /* 10954 * Initialize the function. This must be called before sending CLIENT_SETUP 10955 * for the first client. 10956 */ 10957 static inline int 10958 bxe_func_start(struct bxe_softc *sc) 10959 { 10960 struct ecore_func_state_params func_params = { NULL }; 10961 struct ecore_func_start_params *start_params = &func_params.params.start; 10962 10963 /* Prepare parameters for function state transitions */ 10964 bit_set(&func_params.ramrod_flags, RAMROD_COMP_WAIT); 10965 10966 func_params.f_obj = &sc->func_obj; 10967 func_params.cmd = ECORE_F_CMD_START; 10968 10969 /* Function parameters */ 10970 start_params->mf_mode = sc->devinfo.mf_info.mf_mode; 10971 start_params->sd_vlan_tag = OVLAN(sc); 10972 10973 if (CHIP_IS_E2(sc) || CHIP_IS_E3(sc)) { 10974 start_params->network_cos_mode = STATIC_COS; 10975 } else { /* CHIP_IS_E1X */ 10976 start_params->network_cos_mode = FW_WRR; 10977 } 10978 10979 start_params->gre_tunnel_mode = 0; 10980 start_params->gre_tunnel_rss = 0; 10981 10982 return (ecore_func_state_change(sc, &func_params)); 10983 } 10984 10985 static int 10986 bxe_set_power_state(struct bxe_softc *sc, 10987 uint8_t state) 10988 { 10989 uint16_t pmcsr; 10990 10991 /* If there is no power capability, silently succeed */ 10992 if (!(sc->devinfo.pcie_cap_flags & BXE_PM_CAPABLE_FLAG)) { 10993 BLOGW(sc, "No power capability\n"); 10994 return (0); 10995 } 10996 10997 pmcsr = pci_read_config(sc->dev, 10998 (sc->devinfo.pcie_pm_cap_reg + PCIR_POWER_STATUS), 10999 2); 11000 11001 switch (state) { 11002 case PCI_PM_D0: 11003 pci_write_config(sc->dev, 11004 (sc->devinfo.pcie_pm_cap_reg + PCIR_POWER_STATUS), 11005 ((pmcsr & ~PCIM_PSTAT_DMASK) | PCIM_PSTAT_PME), 2); 11006 11007 if (pmcsr & PCIM_PSTAT_DMASK) { 11008 /* delay required during transition out of D3hot */ 11009 DELAY(20000); 11010 } 11011 11012 break; 11013 11014 case PCI_PM_D3hot: 11015 /* XXX if there are other clients above don't shut down the power */ 11016 11017 /* don't shut down the power for emulation and FPGA */ 11018 if (CHIP_REV_IS_SLOW(sc)) { 11019 return (0); 11020 } 11021 11022 pmcsr &= ~PCIM_PSTAT_DMASK; 11023 pmcsr |= PCIM_PSTAT_D3; 11024 11025 if (sc->wol) { 11026 pmcsr |= PCIM_PSTAT_PMEENABLE; 11027 } 11028 11029 pci_write_config(sc->dev, 11030 (sc->devinfo.pcie_pm_cap_reg + PCIR_POWER_STATUS), 11031 pmcsr, 4); 11032 11033 /* 11034 * No more memory access after this point until device is brought back 11035 * to D0 state. 11036 */ 11037 break; 11038 11039 default: 11040 BLOGE(sc, "Can't support PCI power state = %d\n", state); 11041 return (-1); 11042 } 11043 11044 return (0); 11045 } 11046 11047 11048 /* return true if succeeded to acquire the lock */ 11049 static uint8_t 11050 bxe_trylock_hw_lock(struct bxe_softc *sc, 11051 uint32_t resource) 11052 { 11053 uint32_t lock_status; 11054 uint32_t resource_bit = (1 << resource); 11055 int func = SC_FUNC(sc); 11056 uint32_t hw_lock_control_reg; 11057 11058 BLOGD(sc, DBG_LOAD, "Trying to take a resource lock 0x%x\n", resource); 11059 11060 /* Validating that the resource is within range */ 11061 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { 11062 BLOGD(sc, DBG_LOAD, 11063 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n", 11064 resource, HW_LOCK_MAX_RESOURCE_VALUE); 11065 return (FALSE); 11066 } 11067 11068 if (func <= 5) { 11069 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8); 11070 } else { 11071 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8); 11072 } 11073 11074 /* try to acquire the lock */ 11075 REG_WR(sc, hw_lock_control_reg + 4, resource_bit); 11076 lock_status = REG_RD(sc, hw_lock_control_reg); 11077 if (lock_status & resource_bit) { 11078 return (TRUE); 11079 } 11080 11081 BLOGE(sc, "Failed to get a resource lock 0x%x\n", resource); 11082 11083 return (FALSE); 11084 } 11085 11086 /* 11087 * Get the recovery leader resource id according to the engine this function 11088 * belongs to. Currently only only 2 engines is supported. 11089 */ 11090 static int 11091 bxe_get_leader_lock_resource(struct bxe_softc *sc) 11092 { 11093 if (SC_PATH(sc)) { 11094 return (HW_LOCK_RESOURCE_RECOVERY_LEADER_1); 11095 } else { 11096 return (HW_LOCK_RESOURCE_RECOVERY_LEADER_0); 11097 } 11098 } 11099 11100 /* try to acquire a leader lock for current engine */ 11101 static uint8_t 11102 bxe_trylock_leader_lock(struct bxe_softc *sc) 11103 { 11104 return (bxe_trylock_hw_lock(sc, bxe_get_leader_lock_resource(sc))); 11105 } 11106 11107 static int 11108 bxe_release_leader_lock(struct bxe_softc *sc) 11109 { 11110 return (bxe_release_hw_lock(sc, bxe_get_leader_lock_resource(sc))); 11111 } 11112 11113 /* close gates #2, #3 and #4 */ 11114 static void 11115 bxe_set_234_gates(struct bxe_softc *sc, 11116 uint8_t close) 11117 { 11118 uint32_t val; 11119 11120 /* gates #2 and #4a are closed/opened for "not E1" only */ 11121 if (!CHIP_IS_E1(sc)) { 11122 /* #4 */ 11123 REG_WR(sc, PXP_REG_HST_DISCARD_DOORBELLS, !!close); 11124 /* #2 */ 11125 REG_WR(sc, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close); 11126 } 11127 11128 /* #3 */ 11129 if (CHIP_IS_E1x(sc)) { 11130 /* prevent interrupts from HC on both ports */ 11131 val = REG_RD(sc, HC_REG_CONFIG_1); 11132 REG_WR(sc, HC_REG_CONFIG_1, 11133 (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) : 11134 (val & ~(uint32_t)HC_CONFIG_1_REG_BLOCK_DISABLE_1)); 11135 11136 val = REG_RD(sc, HC_REG_CONFIG_0); 11137 REG_WR(sc, HC_REG_CONFIG_0, 11138 (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) : 11139 (val & ~(uint32_t)HC_CONFIG_0_REG_BLOCK_DISABLE_0)); 11140 } else { 11141 /* Prevent incomming interrupts in IGU */ 11142 val = REG_RD(sc, IGU_REG_BLOCK_CONFIGURATION); 11143 11144 REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION, 11145 (!close) ? 11146 (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) : 11147 (val & ~(uint32_t)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE)); 11148 } 11149 11150 BLOGD(sc, DBG_LOAD, "%s gates #2, #3 and #4\n", 11151 close ? "closing" : "opening"); 11152 11153 wmb(); 11154 } 11155 11156 /* poll for pending writes bit, it should get cleared in no more than 1s */ 11157 static int 11158 bxe_er_poll_igu_vq(struct bxe_softc *sc) 11159 { 11160 uint32_t cnt = 1000; 11161 uint32_t pend_bits = 0; 11162 11163 do { 11164 pend_bits = REG_RD(sc, IGU_REG_PENDING_BITS_STATUS); 11165 11166 if (pend_bits == 0) { 11167 break; 11168 } 11169 11170 DELAY(1000); 11171 } while (--cnt > 0); 11172 11173 if (cnt == 0) { 11174 BLOGE(sc, "Still pending IGU requests bits=0x%08x!\n", pend_bits); 11175 return (-1); 11176 } 11177 11178 return (0); 11179 } 11180 11181 #define SHARED_MF_CLP_MAGIC 0x80000000 /* 'magic' bit */ 11182 11183 static void 11184 bxe_clp_reset_prep(struct bxe_softc *sc, 11185 uint32_t *magic_val) 11186 { 11187 /* Do some magic... */ 11188 uint32_t val = MFCFG_RD(sc, shared_mf_config.clp_mb); 11189 *magic_val = val & SHARED_MF_CLP_MAGIC; 11190 MFCFG_WR(sc, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC); 11191 } 11192 11193 /* restore the value of the 'magic' bit */ 11194 static void 11195 bxe_clp_reset_done(struct bxe_softc *sc, 11196 uint32_t magic_val) 11197 { 11198 /* Restore the 'magic' bit value... */ 11199 uint32_t val = MFCFG_RD(sc, shared_mf_config.clp_mb); 11200 MFCFG_WR(sc, shared_mf_config.clp_mb, 11201 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val); 11202 } 11203 11204 /* prepare for MCP reset, takes care of CLP configurations */ 11205 static void 11206 bxe_reset_mcp_prep(struct bxe_softc *sc, 11207 uint32_t *magic_val) 11208 { 11209 uint32_t shmem; 11210 uint32_t validity_offset; 11211 11212 /* set `magic' bit in order to save MF config */ 11213 if (!CHIP_IS_E1(sc)) { 11214 bxe_clp_reset_prep(sc, magic_val); 11215 } 11216 11217 /* get shmem offset */ 11218 shmem = REG_RD(sc, MISC_REG_SHARED_MEM_ADDR); 11219 validity_offset = 11220 offsetof(struct shmem_region, validity_map[SC_PORT(sc)]); 11221 11222 /* Clear validity map flags */ 11223 if (shmem > 0) { 11224 REG_WR(sc, shmem + validity_offset, 0); 11225 } 11226 } 11227 11228 #define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */ 11229 #define MCP_ONE_TIMEOUT 100 /* 100 ms */ 11230 11231 static void 11232 bxe_mcp_wait_one(struct bxe_softc *sc) 11233 { 11234 /* special handling for emulation and FPGA (10 times longer) */ 11235 if (CHIP_REV_IS_SLOW(sc)) { 11236 DELAY((MCP_ONE_TIMEOUT*10) * 1000); 11237 } else { 11238 DELAY((MCP_ONE_TIMEOUT) * 1000); 11239 } 11240 } 11241 11242 /* initialize shmem_base and waits for validity signature to appear */ 11243 static int 11244 bxe_init_shmem(struct bxe_softc *sc) 11245 { 11246 int cnt = 0; 11247 uint32_t val = 0; 11248 11249 do { 11250 sc->devinfo.shmem_base = 11251 sc->link_params.shmem_base = 11252 REG_RD(sc, MISC_REG_SHARED_MEM_ADDR); 11253 11254 if (sc->devinfo.shmem_base) { 11255 val = SHMEM_RD(sc, validity_map[SC_PORT(sc)]); 11256 if (val & SHR_MEM_VALIDITY_MB) 11257 return (0); 11258 } 11259 11260 bxe_mcp_wait_one(sc); 11261 11262 } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT)); 11263 11264 BLOGE(sc, "BAD MCP validity signature\n"); 11265 11266 return (-1); 11267 } 11268 11269 static int 11270 bxe_reset_mcp_comp(struct bxe_softc *sc, 11271 uint32_t magic_val) 11272 { 11273 int rc = bxe_init_shmem(sc); 11274 11275 /* Restore the `magic' bit value */ 11276 if (!CHIP_IS_E1(sc)) { 11277 bxe_clp_reset_done(sc, magic_val); 11278 } 11279 11280 return (rc); 11281 } 11282 11283 static void 11284 bxe_pxp_prep(struct bxe_softc *sc) 11285 { 11286 if (!CHIP_IS_E1(sc)) { 11287 REG_WR(sc, PXP2_REG_RD_START_INIT, 0); 11288 REG_WR(sc, PXP2_REG_RQ_RBC_DONE, 0); 11289 wmb(); 11290 } 11291 } 11292 11293 /* 11294 * Reset the whole chip except for: 11295 * - PCIE core 11296 * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by one reset bit) 11297 * - IGU 11298 * - MISC (including AEU) 11299 * - GRC 11300 * - RBCN, RBCP 11301 */ 11302 static void 11303 bxe_process_kill_chip_reset(struct bxe_softc *sc, 11304 uint8_t global) 11305 { 11306 uint32_t not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2; 11307 uint32_t global_bits2, stay_reset2; 11308 11309 /* 11310 * Bits that have to be set in reset_mask2 if we want to reset 'global' 11311 * (per chip) blocks. 11312 */ 11313 global_bits2 = 11314 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU | 11315 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE; 11316 11317 /* 11318 * Don't reset the following blocks. 11319 * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be 11320 * reset, as in 4 port device they might still be owned 11321 * by the MCP (there is only one leader per path). 11322 */ 11323 not_reset_mask1 = 11324 MISC_REGISTERS_RESET_REG_1_RST_HC | 11325 MISC_REGISTERS_RESET_REG_1_RST_PXPV | 11326 MISC_REGISTERS_RESET_REG_1_RST_PXP; 11327 11328 not_reset_mask2 = 11329 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO | 11330 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE | 11331 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE | 11332 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE | 11333 MISC_REGISTERS_RESET_REG_2_RST_RBCN | 11334 MISC_REGISTERS_RESET_REG_2_RST_GRC | 11335 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE | 11336 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B | 11337 MISC_REGISTERS_RESET_REG_2_RST_ATC | 11338 MISC_REGISTERS_RESET_REG_2_PGLC | 11339 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 | 11340 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 | 11341 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 | 11342 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 | 11343 MISC_REGISTERS_RESET_REG_2_UMAC0 | 11344 MISC_REGISTERS_RESET_REG_2_UMAC1; 11345 11346 /* 11347 * Keep the following blocks in reset: 11348 * - all xxMACs are handled by the elink code. 11349 */ 11350 stay_reset2 = 11351 MISC_REGISTERS_RESET_REG_2_XMAC | 11352 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT; 11353 11354 /* Full reset masks according to the chip */ 11355 reset_mask1 = 0xffffffff; 11356 11357 if (CHIP_IS_E1(sc)) 11358 reset_mask2 = 0xffff; 11359 else if (CHIP_IS_E1H(sc)) 11360 reset_mask2 = 0x1ffff; 11361 else if (CHIP_IS_E2(sc)) 11362 reset_mask2 = 0xfffff; 11363 else /* CHIP_IS_E3 */ 11364 reset_mask2 = 0x3ffffff; 11365 11366 /* Don't reset global blocks unless we need to */ 11367 if (!global) 11368 reset_mask2 &= ~global_bits2; 11369 11370 /* 11371 * In case of attention in the QM, we need to reset PXP 11372 * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM 11373 * because otherwise QM reset would release 'close the gates' shortly 11374 * before resetting the PXP, then the PSWRQ would send a write 11375 * request to PGLUE. Then when PXP is reset, PGLUE would try to 11376 * read the payload data from PSWWR, but PSWWR would not 11377 * respond. The write queue in PGLUE would stuck, dmae commands 11378 * would not return. Therefore it's important to reset the second 11379 * reset register (containing the 11380 * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the 11381 * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM 11382 * bit). 11383 */ 11384 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 11385 reset_mask2 & (~not_reset_mask2)); 11386 11387 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 11388 reset_mask1 & (~not_reset_mask1)); 11389 11390 mb(); 11391 wmb(); 11392 11393 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 11394 reset_mask2 & (~stay_reset2)); 11395 11396 mb(); 11397 wmb(); 11398 11399 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1); 11400 wmb(); 11401 } 11402 11403 static int 11404 bxe_process_kill(struct bxe_softc *sc, 11405 uint8_t global) 11406 { 11407 int cnt = 1000; 11408 uint32_t val = 0; 11409 uint32_t sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2; 11410 uint32_t tags_63_32 = 0; 11411 11412 /* Empty the Tetris buffer, wait for 1s */ 11413 do { 11414 sr_cnt = REG_RD(sc, PXP2_REG_RD_SR_CNT); 11415 blk_cnt = REG_RD(sc, PXP2_REG_RD_BLK_CNT); 11416 port_is_idle_0 = REG_RD(sc, PXP2_REG_RD_PORT_IS_IDLE_0); 11417 port_is_idle_1 = REG_RD(sc, PXP2_REG_RD_PORT_IS_IDLE_1); 11418 pgl_exp_rom2 = REG_RD(sc, PXP2_REG_PGL_EXP_ROM2); 11419 if (CHIP_IS_E3(sc)) { 11420 tags_63_32 = REG_RD(sc, PGLUE_B_REG_TAGS_63_32); 11421 } 11422 11423 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) && 11424 ((port_is_idle_0 & 0x1) == 0x1) && 11425 ((port_is_idle_1 & 0x1) == 0x1) && 11426 (pgl_exp_rom2 == 0xffffffff) && 11427 (!CHIP_IS_E3(sc) || (tags_63_32 == 0xffffffff))) 11428 break; 11429 DELAY(1000); 11430 } while (cnt-- > 0); 11431 11432 if (cnt <= 0) { 11433 BLOGE(sc, "ERROR: Tetris buffer didn't get empty or there " 11434 "are still outstanding read requests after 1s! " 11435 "sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, " 11436 "port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n", 11437 sr_cnt, blk_cnt, port_is_idle_0, 11438 port_is_idle_1, pgl_exp_rom2); 11439 return (-1); 11440 } 11441 11442 mb(); 11443 11444 /* Close gates #2, #3 and #4 */ 11445 bxe_set_234_gates(sc, TRUE); 11446 11447 /* Poll for IGU VQs for 57712 and newer chips */ 11448 if (!CHIP_IS_E1x(sc) && bxe_er_poll_igu_vq(sc)) { 11449 return (-1); 11450 } 11451 11452 /* XXX indicate that "process kill" is in progress to MCP */ 11453 11454 /* clear "unprepared" bit */ 11455 REG_WR(sc, MISC_REG_UNPREPARED, 0); 11456 mb(); 11457 11458 /* Make sure all is written to the chip before the reset */ 11459 wmb(); 11460 11461 /* 11462 * Wait for 1ms to empty GLUE and PCI-E core queues, 11463 * PSWHST, GRC and PSWRD Tetris buffer. 11464 */ 11465 DELAY(1000); 11466 11467 /* Prepare to chip reset: */ 11468 /* MCP */ 11469 if (global) { 11470 bxe_reset_mcp_prep(sc, &val); 11471 } 11472 11473 /* PXP */ 11474 bxe_pxp_prep(sc); 11475 mb(); 11476 11477 /* reset the chip */ 11478 bxe_process_kill_chip_reset(sc, global); 11479 mb(); 11480 11481 /* Recover after reset: */ 11482 /* MCP */ 11483 if (global && bxe_reset_mcp_comp(sc, val)) { 11484 return (-1); 11485 } 11486 11487 /* XXX add resetting the NO_MCP mode DB here */ 11488 11489 /* Open the gates #2, #3 and #4 */ 11490 bxe_set_234_gates(sc, FALSE); 11491 11492 /* XXX 11493 * IGU/AEU preparation bring back the AEU/IGU to a reset state 11494 * re-enable attentions 11495 */ 11496 11497 return (0); 11498 } 11499 11500 static int 11501 bxe_leader_reset(struct bxe_softc *sc) 11502 { 11503 int rc = 0; 11504 uint8_t global = bxe_reset_is_global(sc); 11505 uint32_t load_code; 11506 11507 /* 11508 * If not going to reset MCP, load "fake" driver to reset HW while 11509 * driver is owner of the HW. 11510 */ 11511 if (!global && !BXE_NOMCP(sc)) { 11512 load_code = bxe_fw_command(sc, DRV_MSG_CODE_LOAD_REQ, 11513 DRV_MSG_CODE_LOAD_REQ_WITH_LFA); 11514 if (!load_code) { 11515 BLOGE(sc, "MCP response failure, aborting\n"); 11516 rc = -1; 11517 goto exit_leader_reset; 11518 } 11519 11520 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) && 11521 (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) { 11522 BLOGE(sc, "MCP unexpected response, aborting\n"); 11523 rc = -1; 11524 goto exit_leader_reset2; 11525 } 11526 11527 load_code = bxe_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0); 11528 if (!load_code) { 11529 BLOGE(sc, "MCP response failure, aborting\n"); 11530 rc = -1; 11531 goto exit_leader_reset2; 11532 } 11533 } 11534 11535 /* try to recover after the failure */ 11536 if (bxe_process_kill(sc, global)) { 11537 BLOGE(sc, "Something bad occurred on engine %d!\n", SC_PATH(sc)); 11538 rc = -1; 11539 goto exit_leader_reset2; 11540 } 11541 11542 /* 11543 * Clear the RESET_IN_PROGRESS and RESET_GLOBAL bits and update the driver 11544 * state. 11545 */ 11546 bxe_set_reset_done(sc); 11547 if (global) { 11548 bxe_clear_reset_global(sc); 11549 } 11550 11551 exit_leader_reset2: 11552 11553 /* unload "fake driver" if it was loaded */ 11554 if (!global && !BXE_NOMCP(sc)) { 11555 bxe_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0); 11556 bxe_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, 0); 11557 } 11558 11559 exit_leader_reset: 11560 11561 sc->is_leader = 0; 11562 bxe_release_leader_lock(sc); 11563 11564 mb(); 11565 return (rc); 11566 } 11567 11568 /* 11569 * prepare INIT transition, parameters configured: 11570 * - HC configuration 11571 * - Queue's CDU context 11572 */ 11573 static void 11574 bxe_pf_q_prep_init(struct bxe_softc *sc, 11575 struct bxe_fastpath *fp, 11576 struct ecore_queue_init_params *init_params) 11577 { 11578 uint8_t cos; 11579 int cxt_index, cxt_offset; 11580 11581 bxe_set_bit(ECORE_Q_FLG_HC, &init_params->rx.flags); 11582 bxe_set_bit(ECORE_Q_FLG_HC, &init_params->tx.flags); 11583 11584 bxe_set_bit(ECORE_Q_FLG_HC_EN, &init_params->rx.flags); 11585 bxe_set_bit(ECORE_Q_FLG_HC_EN, &init_params->tx.flags); 11586 11587 /* HC rate */ 11588 init_params->rx.hc_rate = 11589 sc->hc_rx_ticks ? (1000000 / sc->hc_rx_ticks) : 0; 11590 init_params->tx.hc_rate = 11591 sc->hc_tx_ticks ? (1000000 / sc->hc_tx_ticks) : 0; 11592 11593 /* FW SB ID */ 11594 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id = fp->fw_sb_id; 11595 11596 /* CQ index among the SB indices */ 11597 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS; 11598 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS; 11599 11600 /* set maximum number of COSs supported by this queue */ 11601 init_params->max_cos = sc->max_cos; 11602 11603 BLOGD(sc, DBG_LOAD, "fp %d setting queue params max cos to %d\n", 11604 fp->index, init_params->max_cos); 11605 11606 /* set the context pointers queue object */ 11607 for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) { 11608 /* XXX change index/cid here if ever support multiple tx CoS */ 11609 /* fp->txdata[cos]->cid */ 11610 cxt_index = fp->index / ILT_PAGE_CIDS; 11611 cxt_offset = fp->index - (cxt_index * ILT_PAGE_CIDS); 11612 init_params->cxts[cos] = &sc->context[cxt_index].vcxt[cxt_offset].eth; 11613 } 11614 } 11615 11616 /* set flags that are common for the Tx-only and not normal connections */ 11617 static unsigned long 11618 bxe_get_common_flags(struct bxe_softc *sc, 11619 struct bxe_fastpath *fp, 11620 uint8_t zero_stats) 11621 { 11622 unsigned long flags = 0; 11623 11624 /* PF driver will always initialize the Queue to an ACTIVE state */ 11625 bxe_set_bit(ECORE_Q_FLG_ACTIVE, &flags); 11626 11627 /* 11628 * tx only connections collect statistics (on the same index as the 11629 * parent connection). The statistics are zeroed when the parent 11630 * connection is initialized. 11631 */ 11632 11633 bxe_set_bit(ECORE_Q_FLG_STATS, &flags); 11634 if (zero_stats) { 11635 bxe_set_bit(ECORE_Q_FLG_ZERO_STATS, &flags); 11636 } 11637 11638 /* 11639 * tx only connections can support tx-switching, though their 11640 * CoS-ness doesn't survive the loopback 11641 */ 11642 if (sc->flags & BXE_TX_SWITCHING) { 11643 bxe_set_bit(ECORE_Q_FLG_TX_SWITCH, &flags); 11644 } 11645 11646 bxe_set_bit(ECORE_Q_FLG_PCSUM_ON_PKT, &flags); 11647 11648 return (flags); 11649 } 11650 11651 static unsigned long 11652 bxe_get_q_flags(struct bxe_softc *sc, 11653 struct bxe_fastpath *fp, 11654 uint8_t leading) 11655 { 11656 unsigned long flags = 0; 11657 11658 if (IS_MF_SD(sc)) { 11659 bxe_set_bit(ECORE_Q_FLG_OV, &flags); 11660 } 11661 11662 if (sc->ifnet->if_capenable & IFCAP_LRO) { 11663 bxe_set_bit(ECORE_Q_FLG_TPA, &flags); 11664 bxe_set_bit(ECORE_Q_FLG_TPA_IPV6, &flags); 11665 #if 0 11666 if (fp->mode == TPA_MODE_GRO) 11667 __set_bit(ECORE_Q_FLG_TPA_GRO, &flags); 11668 #endif 11669 } 11670 11671 if (leading) { 11672 bxe_set_bit(ECORE_Q_FLG_LEADING_RSS, &flags); 11673 bxe_set_bit(ECORE_Q_FLG_MCAST, &flags); 11674 } 11675 11676 bxe_set_bit(ECORE_Q_FLG_VLAN, &flags); 11677 11678 #if 0 11679 /* configure silent vlan removal */ 11680 if (IS_MF_AFEX(sc)) { 11681 bxe_set_bit(ECORE_Q_FLG_SILENT_VLAN_REM, &flags); 11682 } 11683 #endif 11684 11685 /* merge with common flags */ 11686 return (flags | bxe_get_common_flags(sc, fp, TRUE)); 11687 } 11688 11689 static void 11690 bxe_pf_q_prep_general(struct bxe_softc *sc, 11691 struct bxe_fastpath *fp, 11692 struct ecore_general_setup_params *gen_init, 11693 uint8_t cos) 11694 { 11695 gen_init->stat_id = bxe_stats_id(fp); 11696 gen_init->spcl_id = fp->cl_id; 11697 gen_init->mtu = sc->mtu; 11698 gen_init->cos = cos; 11699 } 11700 11701 static void 11702 bxe_pf_rx_q_prep(struct bxe_softc *sc, 11703 struct bxe_fastpath *fp, 11704 struct rxq_pause_params *pause, 11705 struct ecore_rxq_setup_params *rxq_init) 11706 { 11707 uint8_t max_sge = 0; 11708 uint16_t sge_sz = 0; 11709 uint16_t tpa_agg_size = 0; 11710 11711 if (sc->ifnet->if_capenable & IFCAP_LRO) { 11712 pause->sge_th_lo = SGE_TH_LO(sc); 11713 pause->sge_th_hi = SGE_TH_HI(sc); 11714 11715 /* validate SGE ring has enough to cross high threshold */ 11716 if (sc->dropless_fc && 11717 (pause->sge_th_hi + FW_PREFETCH_CNT) > 11718 (RX_SGE_USABLE_PER_PAGE * RX_SGE_NUM_PAGES)) { 11719 BLOGW(sc, "sge ring threshold limit\n"); 11720 } 11721 11722 /* minimum max_aggregation_size is 2*MTU (two full buffers) */ 11723 tpa_agg_size = (2 * sc->mtu); 11724 if (tpa_agg_size < sc->max_aggregation_size) { 11725 tpa_agg_size = sc->max_aggregation_size; 11726 } 11727 11728 max_sge = SGE_PAGE_ALIGN(sc->mtu) >> SGE_PAGE_SHIFT; 11729 max_sge = ((max_sge + PAGES_PER_SGE - 1) & 11730 (~(PAGES_PER_SGE - 1))) >> PAGES_PER_SGE_SHIFT; 11731 sge_sz = (uint16_t)min(SGE_PAGES, 0xffff); 11732 } 11733 11734 /* pause - not for e1 */ 11735 if (!CHIP_IS_E1(sc)) { 11736 pause->bd_th_lo = BD_TH_LO(sc); 11737 pause->bd_th_hi = BD_TH_HI(sc); 11738 11739 pause->rcq_th_lo = RCQ_TH_LO(sc); 11740 pause->rcq_th_hi = RCQ_TH_HI(sc); 11741 11742 /* validate rings have enough entries to cross high thresholds */ 11743 if (sc->dropless_fc && 11744 pause->bd_th_hi + FW_PREFETCH_CNT > 11745 sc->rx_ring_size) { 11746 BLOGW(sc, "rx bd ring threshold limit\n"); 11747 } 11748 11749 if (sc->dropless_fc && 11750 pause->rcq_th_hi + FW_PREFETCH_CNT > 11751 RCQ_NUM_PAGES * RCQ_USABLE_PER_PAGE) { 11752 BLOGW(sc, "rcq ring threshold limit\n"); 11753 } 11754 11755 pause->pri_map = 1; 11756 } 11757 11758 /* rxq setup */ 11759 rxq_init->dscr_map = fp->rx_dma.paddr; 11760 rxq_init->sge_map = fp->rx_sge_dma.paddr; 11761 rxq_init->rcq_map = fp->rcq_dma.paddr; 11762 rxq_init->rcq_np_map = (fp->rcq_dma.paddr + BCM_PAGE_SIZE); 11763 11764 /* 11765 * This should be a maximum number of data bytes that may be 11766 * placed on the BD (not including paddings). 11767 */ 11768 rxq_init->buf_sz = (fp->rx_buf_size - 11769 IP_HEADER_ALIGNMENT_PADDING); 11770 11771 rxq_init->cl_qzone_id = fp->cl_qzone_id; 11772 rxq_init->tpa_agg_sz = tpa_agg_size; 11773 rxq_init->sge_buf_sz = sge_sz; 11774 rxq_init->max_sges_pkt = max_sge; 11775 rxq_init->rss_engine_id = SC_FUNC(sc); 11776 rxq_init->mcast_engine_id = SC_FUNC(sc); 11777 11778 /* 11779 * Maximum number or simultaneous TPA aggregation for this Queue. 11780 * For PF Clients it should be the maximum available number. 11781 * VF driver(s) may want to define it to a smaller value. 11782 */ 11783 rxq_init->max_tpa_queues = MAX_AGG_QS(sc); 11784 11785 rxq_init->cache_line_log = BXE_RX_ALIGN_SHIFT; 11786 rxq_init->fw_sb_id = fp->fw_sb_id; 11787 11788 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS; 11789 11790 /* 11791 * configure silent vlan removal 11792 * if multi function mode is afex, then mask default vlan 11793 */ 11794 if (IS_MF_AFEX(sc)) { 11795 rxq_init->silent_removal_value = 11796 sc->devinfo.mf_info.afex_def_vlan_tag; 11797 rxq_init->silent_removal_mask = EVL_VLID_MASK; 11798 } 11799 } 11800 11801 static void 11802 bxe_pf_tx_q_prep(struct bxe_softc *sc, 11803 struct bxe_fastpath *fp, 11804 struct ecore_txq_setup_params *txq_init, 11805 uint8_t cos) 11806 { 11807 /* 11808 * XXX If multiple CoS is ever supported then each fastpath structure 11809 * will need to maintain tx producer/consumer/dma/etc values *per* CoS. 11810 * fp->txdata[cos]->tx_dma.paddr; 11811 */ 11812 txq_init->dscr_map = fp->tx_dma.paddr; 11813 txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos; 11814 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW; 11815 txq_init->fw_sb_id = fp->fw_sb_id; 11816 11817 /* 11818 * set the TSS leading client id for TX classfication to the 11819 * leading RSS client id 11820 */ 11821 txq_init->tss_leading_cl_id = BXE_FP(sc, 0, cl_id); 11822 } 11823 11824 /* 11825 * This function performs 2 steps in a queue state machine: 11826 * 1) RESET->INIT 11827 * 2) INIT->SETUP 11828 */ 11829 static int 11830 bxe_setup_queue(struct bxe_softc *sc, 11831 struct bxe_fastpath *fp, 11832 uint8_t leading) 11833 { 11834 struct ecore_queue_state_params q_params = { NULL }; 11835 struct ecore_queue_setup_params *setup_params = 11836 &q_params.params.setup; 11837 #if 0 11838 struct ecore_queue_setup_tx_only_params *tx_only_params = 11839 &q_params.params.tx_only; 11840 uint8_t tx_index; 11841 #endif 11842 int rc; 11843 11844 BLOGD(sc, DBG_LOAD, "setting up queue %d\n", fp->index); 11845 11846 bxe_ack_sb(sc, fp->igu_sb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0); 11847 11848 q_params.q_obj = &BXE_SP_OBJ(sc, fp).q_obj; 11849 11850 /* we want to wait for completion in this context */ 11851 bxe_set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags); 11852 11853 /* prepare the INIT parameters */ 11854 bxe_pf_q_prep_init(sc, fp, &q_params.params.init); 11855 11856 /* Set the command */ 11857 q_params.cmd = ECORE_Q_CMD_INIT; 11858 11859 /* Change the state to INIT */ 11860 rc = ecore_queue_state_change(sc, &q_params); 11861 if (rc) { 11862 BLOGE(sc, "Queue(%d) INIT failed\n", fp->index); 11863 return (rc); 11864 } 11865 11866 BLOGD(sc, DBG_LOAD, "init complete\n"); 11867 11868 /* now move the Queue to the SETUP state */ 11869 memset(setup_params, 0, sizeof(*setup_params)); 11870 11871 /* set Queue flags */ 11872 setup_params->flags = bxe_get_q_flags(sc, fp, leading); 11873 11874 /* set general SETUP parameters */ 11875 bxe_pf_q_prep_general(sc, fp, &setup_params->gen_params, 11876 FIRST_TX_COS_INDEX); 11877 11878 bxe_pf_rx_q_prep(sc, fp, 11879 &setup_params->pause_params, 11880 &setup_params->rxq_params); 11881 11882 bxe_pf_tx_q_prep(sc, fp, 11883 &setup_params->txq_params, 11884 FIRST_TX_COS_INDEX); 11885 11886 /* Set the command */ 11887 q_params.cmd = ECORE_Q_CMD_SETUP; 11888 11889 /* change the state to SETUP */ 11890 rc = ecore_queue_state_change(sc, &q_params); 11891 if (rc) { 11892 BLOGE(sc, "Queue(%d) SETUP failed\n", fp->index); 11893 return (rc); 11894 } 11895 11896 #if 0 11897 /* loop through the relevant tx-only indices */ 11898 for (tx_index = FIRST_TX_ONLY_COS_INDEX; 11899 tx_index < sc->max_cos; 11900 tx_index++) { 11901 /* prepare and send tx-only ramrod*/ 11902 rc = bxe_setup_tx_only(sc, fp, &q_params, 11903 tx_only_params, tx_index, leading); 11904 if (rc) { 11905 BLOGE(sc, "Queue(%d.%d) TX_ONLY_SETUP failed\n", 11906 fp->index, tx_index); 11907 return (rc); 11908 } 11909 } 11910 #endif 11911 11912 return (rc); 11913 } 11914 11915 static int 11916 bxe_setup_leading(struct bxe_softc *sc) 11917 { 11918 return (bxe_setup_queue(sc, &sc->fp[0], TRUE)); 11919 } 11920 11921 static int 11922 bxe_config_rss_pf(struct bxe_softc *sc, 11923 struct ecore_rss_config_obj *rss_obj, 11924 uint8_t config_hash) 11925 { 11926 struct ecore_config_rss_params params = { NULL }; 11927 int i; 11928 11929 /* 11930 * Although RSS is meaningless when there is a single HW queue we 11931 * still need it enabled in order to have HW Rx hash generated. 11932 */ 11933 11934 params.rss_obj = rss_obj; 11935 11936 bxe_set_bit(RAMROD_COMP_WAIT, ¶ms.ramrod_flags); 11937 11938 bxe_set_bit(ECORE_RSS_MODE_REGULAR, ¶ms.rss_flags); 11939 11940 /* RSS configuration */ 11941 bxe_set_bit(ECORE_RSS_IPV4, ¶ms.rss_flags); 11942 bxe_set_bit(ECORE_RSS_IPV4_TCP, ¶ms.rss_flags); 11943 bxe_set_bit(ECORE_RSS_IPV6, ¶ms.rss_flags); 11944 bxe_set_bit(ECORE_RSS_IPV6_TCP, ¶ms.rss_flags); 11945 if (rss_obj->udp_rss_v4) { 11946 bxe_set_bit(ECORE_RSS_IPV4_UDP, ¶ms.rss_flags); 11947 } 11948 if (rss_obj->udp_rss_v6) { 11949 bxe_set_bit(ECORE_RSS_IPV6_UDP, ¶ms.rss_flags); 11950 } 11951 11952 /* Hash bits */ 11953 params.rss_result_mask = MULTI_MASK; 11954 11955 memcpy(params.ind_table, rss_obj->ind_table, sizeof(params.ind_table)); 11956 11957 if (config_hash) { 11958 /* RSS keys */ 11959 for (i = 0; i < sizeof(params.rss_key) / 4; i++) { 11960 params.rss_key[i] = arc4random(); 11961 } 11962 11963 bxe_set_bit(ECORE_RSS_SET_SRCH, ¶ms.rss_flags); 11964 } 11965 11966 return (ecore_config_rss(sc, ¶ms)); 11967 } 11968 11969 static int 11970 bxe_config_rss_eth(struct bxe_softc *sc, 11971 uint8_t config_hash) 11972 { 11973 return (bxe_config_rss_pf(sc, &sc->rss_conf_obj, config_hash)); 11974 } 11975 11976 static int 11977 bxe_init_rss_pf(struct bxe_softc *sc) 11978 { 11979 uint8_t num_eth_queues = BXE_NUM_ETH_QUEUES(sc); 11980 int i; 11981 11982 /* 11983 * Prepare the initial contents of the indirection table if 11984 * RSS is enabled 11985 */ 11986 for (i = 0; i < sizeof(sc->rss_conf_obj.ind_table); i++) { 11987 sc->rss_conf_obj.ind_table[i] = 11988 (sc->fp->cl_id + (i % num_eth_queues)); 11989 } 11990 11991 if (sc->udp_rss) { 11992 sc->rss_conf_obj.udp_rss_v4 = sc->rss_conf_obj.udp_rss_v6 = 1; 11993 } 11994 11995 /* 11996 * For 57710 and 57711 SEARCHER configuration (rss_keys) is 11997 * per-port, so if explicit configuration is needed, do it only 11998 * for a PMF. 11999 * 12000 * For 57712 and newer it's a per-function configuration. 12001 */ 12002 return (bxe_config_rss_eth(sc, sc->port.pmf || !CHIP_IS_E1x(sc))); 12003 } 12004 12005 static int 12006 bxe_set_mac_one(struct bxe_softc *sc, 12007 uint8_t *mac, 12008 struct ecore_vlan_mac_obj *obj, 12009 uint8_t set, 12010 int mac_type, 12011 unsigned long *ramrod_flags) 12012 { 12013 struct ecore_vlan_mac_ramrod_params ramrod_param; 12014 int rc; 12015 12016 memset(&ramrod_param, 0, sizeof(ramrod_param)); 12017 12018 /* fill in general parameters */ 12019 ramrod_param.vlan_mac_obj = obj; 12020 ramrod_param.ramrod_flags = *ramrod_flags; 12021 12022 /* fill a user request section if needed */ 12023 if (!bxe_test_bit(RAMROD_CONT, ramrod_flags)) { 12024 memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN); 12025 12026 bxe_set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags); 12027 12028 /* Set the command: ADD or DEL */ 12029 ramrod_param.user_req.cmd = (set) ? ECORE_VLAN_MAC_ADD : 12030 ECORE_VLAN_MAC_DEL; 12031 } 12032 12033 rc = ecore_config_vlan_mac(sc, &ramrod_param); 12034 12035 if (rc == ECORE_EXISTS) { 12036 BLOGD(sc, DBG_SP, "Failed to schedule ADD operations (EEXIST)\n"); 12037 /* do not treat adding same MAC as error */ 12038 rc = 0; 12039 } else if (rc < 0) { 12040 BLOGE(sc, "%s MAC failed (%d)\n", (set ? "Set" : "Delete"), rc); 12041 } 12042 12043 return (rc); 12044 } 12045 12046 static int 12047 bxe_set_eth_mac(struct bxe_softc *sc, 12048 uint8_t set) 12049 { 12050 unsigned long ramrod_flags = 0; 12051 12052 BLOGD(sc, DBG_LOAD, "Adding Ethernet MAC\n"); 12053 12054 bxe_set_bit(RAMROD_COMP_WAIT, &ramrod_flags); 12055 12056 /* Eth MAC is set on RSS leading client (fp[0]) */ 12057 return (bxe_set_mac_one(sc, sc->link_params.mac_addr, 12058 &sc->sp_objs->mac_obj, 12059 set, ECORE_ETH_MAC, &ramrod_flags)); 12060 } 12061 12062 #if 0 12063 static void 12064 bxe_update_max_mf_config(struct bxe_softc *sc, 12065 uint32_t value) 12066 { 12067 /* load old values */ 12068 uint32_t mf_cfg = sc->devinfo.mf_info.mf_config[SC_VN(sc)]; 12069 12070 if (value != bxe_extract_max_cfg(sc, mf_cfg)) { 12071 /* leave all but MAX value */ 12072 mf_cfg &= ~FUNC_MF_CFG_MAX_BW_MASK; 12073 12074 /* set new MAX value */ 12075 mf_cfg |= ((value << FUNC_MF_CFG_MAX_BW_SHIFT) & 12076 FUNC_MF_CFG_MAX_BW_MASK); 12077 12078 bxe_fw_command(sc, DRV_MSG_CODE_SET_MF_BW, mf_cfg); 12079 } 12080 } 12081 #endif 12082 12083 static int 12084 bxe_get_cur_phy_idx(struct bxe_softc *sc) 12085 { 12086 uint32_t sel_phy_idx = 0; 12087 12088 if (sc->link_params.num_phys <= 1) { 12089 return (ELINK_INT_PHY); 12090 } 12091 12092 if (sc->link_vars.link_up) { 12093 sel_phy_idx = ELINK_EXT_PHY1; 12094 /* In case link is SERDES, check if the ELINK_EXT_PHY2 is the one */ 12095 if ((sc->link_vars.link_status & LINK_STATUS_SERDES_LINK) && 12096 (sc->link_params.phy[ELINK_EXT_PHY2].supported & 12097 ELINK_SUPPORTED_FIBRE)) 12098 sel_phy_idx = ELINK_EXT_PHY2; 12099 } else { 12100 switch (elink_phy_selection(&sc->link_params)) { 12101 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT: 12102 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY: 12103 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY: 12104 sel_phy_idx = ELINK_EXT_PHY1; 12105 break; 12106 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY: 12107 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY: 12108 sel_phy_idx = ELINK_EXT_PHY2; 12109 break; 12110 } 12111 } 12112 12113 return (sel_phy_idx); 12114 } 12115 12116 static int 12117 bxe_get_link_cfg_idx(struct bxe_softc *sc) 12118 { 12119 uint32_t sel_phy_idx = bxe_get_cur_phy_idx(sc); 12120 12121 /* 12122 * The selected activated PHY is always after swapping (in case PHY 12123 * swapping is enabled). So when swapping is enabled, we need to reverse 12124 * the configuration 12125 */ 12126 12127 if (sc->link_params.multi_phy_config & PORT_HW_CFG_PHY_SWAPPED_ENABLED) { 12128 if (sel_phy_idx == ELINK_EXT_PHY1) 12129 sel_phy_idx = ELINK_EXT_PHY2; 12130 else if (sel_phy_idx == ELINK_EXT_PHY2) 12131 sel_phy_idx = ELINK_EXT_PHY1; 12132 } 12133 12134 return (ELINK_LINK_CONFIG_IDX(sel_phy_idx)); 12135 } 12136 12137 static void 12138 bxe_set_requested_fc(struct bxe_softc *sc) 12139 { 12140 /* 12141 * Initialize link parameters structure variables 12142 * It is recommended to turn off RX FC for jumbo frames 12143 * for better performance 12144 */ 12145 if (CHIP_IS_E1x(sc) && (sc->mtu > 5000)) { 12146 sc->link_params.req_fc_auto_adv = ELINK_FLOW_CTRL_TX; 12147 } else { 12148 sc->link_params.req_fc_auto_adv = ELINK_FLOW_CTRL_BOTH; 12149 } 12150 } 12151 12152 static void 12153 bxe_calc_fc_adv(struct bxe_softc *sc) 12154 { 12155 uint8_t cfg_idx = bxe_get_link_cfg_idx(sc); 12156 switch (sc->link_vars.ieee_fc & 12157 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) { 12158 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE: 12159 default: 12160 sc->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause | 12161 ADVERTISED_Pause); 12162 break; 12163 12164 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH: 12165 sc->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause | 12166 ADVERTISED_Pause); 12167 break; 12168 12169 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC: 12170 sc->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause; 12171 break; 12172 } 12173 } 12174 12175 static uint16_t 12176 bxe_get_mf_speed(struct bxe_softc *sc) 12177 { 12178 uint16_t line_speed = sc->link_vars.line_speed; 12179 if (IS_MF(sc)) { 12180 uint16_t maxCfg = 12181 bxe_extract_max_cfg(sc, sc->devinfo.mf_info.mf_config[SC_VN(sc)]); 12182 12183 /* calculate the current MAX line speed limit for the MF devices */ 12184 if (IS_MF_SI(sc)) { 12185 line_speed = (line_speed * maxCfg) / 100; 12186 } else { /* SD mode */ 12187 uint16_t vn_max_rate = maxCfg * 100; 12188 12189 if (vn_max_rate < line_speed) { 12190 line_speed = vn_max_rate; 12191 } 12192 } 12193 } 12194 12195 return (line_speed); 12196 } 12197 12198 static void 12199 bxe_fill_report_data(struct bxe_softc *sc, 12200 struct bxe_link_report_data *data) 12201 { 12202 uint16_t line_speed = bxe_get_mf_speed(sc); 12203 12204 memset(data, 0, sizeof(*data)); 12205 12206 /* fill the report data with the effective line speed */ 12207 data->line_speed = line_speed; 12208 12209 /* Link is down */ 12210 if (!sc->link_vars.link_up || (sc->flags & BXE_MF_FUNC_DIS)) { 12211 bxe_set_bit(BXE_LINK_REPORT_LINK_DOWN, &data->link_report_flags); 12212 } 12213 12214 /* Full DUPLEX */ 12215 if (sc->link_vars.duplex == DUPLEX_FULL) { 12216 bxe_set_bit(BXE_LINK_REPORT_FULL_DUPLEX, &data->link_report_flags); 12217 } 12218 12219 /* Rx Flow Control is ON */ 12220 if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_RX) { 12221 bxe_set_bit(BXE_LINK_REPORT_RX_FC_ON, &data->link_report_flags); 12222 } 12223 12224 /* Tx Flow Control is ON */ 12225 if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_TX) { 12226 bxe_set_bit(BXE_LINK_REPORT_TX_FC_ON, &data->link_report_flags); 12227 } 12228 } 12229 12230 /* report link status to OS, should be called under phy_lock */ 12231 static void 12232 bxe_link_report_locked(struct bxe_softc *sc) 12233 { 12234 struct bxe_link_report_data cur_data; 12235 12236 /* reread mf_cfg */ 12237 if (IS_PF(sc) && !CHIP_IS_E1(sc)) { 12238 bxe_read_mf_cfg(sc); 12239 } 12240 12241 /* Read the current link report info */ 12242 bxe_fill_report_data(sc, &cur_data); 12243 12244 /* Don't report link down or exactly the same link status twice */ 12245 if (!memcmp(&cur_data, &sc->last_reported_link, sizeof(cur_data)) || 12246 (bxe_test_bit(BXE_LINK_REPORT_LINK_DOWN, 12247 &sc->last_reported_link.link_report_flags) && 12248 bxe_test_bit(BXE_LINK_REPORT_LINK_DOWN, 12249 &cur_data.link_report_flags))) { 12250 return; 12251 } 12252 12253 sc->link_cnt++; 12254 12255 /* report new link params and remember the state for the next time */ 12256 memcpy(&sc->last_reported_link, &cur_data, sizeof(cur_data)); 12257 12258 if (bxe_test_bit(BXE_LINK_REPORT_LINK_DOWN, 12259 &cur_data.link_report_flags)) { 12260 if_link_state_change(sc->ifnet, LINK_STATE_DOWN); 12261 BLOGI(sc, "NIC Link is Down\n"); 12262 } else { 12263 const char *duplex; 12264 const char *flow; 12265 12266 if (bxe_test_and_clear_bit(BXE_LINK_REPORT_FULL_DUPLEX, 12267 &cur_data.link_report_flags)) { 12268 duplex = "full"; 12269 } else { 12270 duplex = "half"; 12271 } 12272 12273 /* 12274 * Handle the FC at the end so that only these flags would be 12275 * possibly set. This way we may easily check if there is no FC 12276 * enabled. 12277 */ 12278 if (cur_data.link_report_flags) { 12279 if (bxe_test_bit(BXE_LINK_REPORT_RX_FC_ON, 12280 &cur_data.link_report_flags) && 12281 bxe_test_bit(BXE_LINK_REPORT_TX_FC_ON, 12282 &cur_data.link_report_flags)) { 12283 flow = "ON - receive & transmit"; 12284 } else if (bxe_test_bit(BXE_LINK_REPORT_RX_FC_ON, 12285 &cur_data.link_report_flags) && 12286 !bxe_test_bit(BXE_LINK_REPORT_TX_FC_ON, 12287 &cur_data.link_report_flags)) { 12288 flow = "ON - receive"; 12289 } else if (!bxe_test_bit(BXE_LINK_REPORT_RX_FC_ON, 12290 &cur_data.link_report_flags) && 12291 bxe_test_bit(BXE_LINK_REPORT_TX_FC_ON, 12292 &cur_data.link_report_flags)) { 12293 flow = "ON - transmit"; 12294 } else { 12295 flow = "none"; /* possible? */ 12296 } 12297 } else { 12298 flow = "none"; 12299 } 12300 12301 if_link_state_change(sc->ifnet, LINK_STATE_UP); 12302 BLOGI(sc, "NIC Link is Up, %d Mbps %s duplex, Flow control: %s\n", 12303 cur_data.line_speed, duplex, flow); 12304 } 12305 } 12306 12307 static void 12308 bxe_link_report(struct bxe_softc *sc) 12309 { 12310 BXE_PHY_LOCK(sc); 12311 bxe_link_report_locked(sc); 12312 BXE_PHY_UNLOCK(sc); 12313 } 12314 12315 static void 12316 bxe_link_status_update(struct bxe_softc *sc) 12317 { 12318 if (sc->state != BXE_STATE_OPEN) { 12319 return; 12320 } 12321 12322 #if 0 12323 /* read updated dcb configuration */ 12324 if (IS_PF(sc)) 12325 bxe_dcbx_pmf_update(sc); 12326 #endif 12327 12328 if (IS_PF(sc) && !CHIP_REV_IS_SLOW(sc)) { 12329 elink_link_status_update(&sc->link_params, &sc->link_vars); 12330 } else { 12331 sc->port.supported[0] |= (ELINK_SUPPORTED_10baseT_Half | 12332 ELINK_SUPPORTED_10baseT_Full | 12333 ELINK_SUPPORTED_100baseT_Half | 12334 ELINK_SUPPORTED_100baseT_Full | 12335 ELINK_SUPPORTED_1000baseT_Full | 12336 ELINK_SUPPORTED_2500baseX_Full | 12337 ELINK_SUPPORTED_10000baseT_Full | 12338 ELINK_SUPPORTED_TP | 12339 ELINK_SUPPORTED_FIBRE | 12340 ELINK_SUPPORTED_Autoneg | 12341 ELINK_SUPPORTED_Pause | 12342 ELINK_SUPPORTED_Asym_Pause); 12343 sc->port.advertising[0] = sc->port.supported[0]; 12344 12345 sc->link_params.sc = sc; 12346 sc->link_params.port = SC_PORT(sc); 12347 sc->link_params.req_duplex[0] = DUPLEX_FULL; 12348 sc->link_params.req_flow_ctrl[0] = ELINK_FLOW_CTRL_NONE; 12349 sc->link_params.req_line_speed[0] = SPEED_10000; 12350 sc->link_params.speed_cap_mask[0] = 0x7f0000; 12351 sc->link_params.switch_cfg = ELINK_SWITCH_CFG_10G; 12352 12353 if (CHIP_REV_IS_FPGA(sc)) { 12354 sc->link_vars.mac_type = ELINK_MAC_TYPE_EMAC; 12355 sc->link_vars.line_speed = ELINK_SPEED_1000; 12356 sc->link_vars.link_status = (LINK_STATUS_LINK_UP | 12357 LINK_STATUS_SPEED_AND_DUPLEX_1000TFD); 12358 } else { 12359 sc->link_vars.mac_type = ELINK_MAC_TYPE_BMAC; 12360 sc->link_vars.line_speed = ELINK_SPEED_10000; 12361 sc->link_vars.link_status = (LINK_STATUS_LINK_UP | 12362 LINK_STATUS_SPEED_AND_DUPLEX_10GTFD); 12363 } 12364 12365 sc->link_vars.link_up = 1; 12366 12367 sc->link_vars.duplex = DUPLEX_FULL; 12368 sc->link_vars.flow_ctrl = ELINK_FLOW_CTRL_NONE; 12369 12370 if (IS_PF(sc)) { 12371 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + sc->link_params.port*4, 0); 12372 bxe_stats_handle(sc, STATS_EVENT_LINK_UP); 12373 bxe_link_report(sc); 12374 } 12375 } 12376 12377 if (IS_PF(sc)) { 12378 if (sc->link_vars.link_up) { 12379 bxe_stats_handle(sc, STATS_EVENT_LINK_UP); 12380 } else { 12381 bxe_stats_handle(sc, STATS_EVENT_STOP); 12382 } 12383 bxe_link_report(sc); 12384 } else { 12385 bxe_link_report(sc); 12386 bxe_stats_handle(sc, STATS_EVENT_LINK_UP); 12387 } 12388 } 12389 12390 static int 12391 bxe_initial_phy_init(struct bxe_softc *sc, 12392 int load_mode) 12393 { 12394 int rc, cfg_idx = bxe_get_link_cfg_idx(sc); 12395 uint16_t req_line_speed = sc->link_params.req_line_speed[cfg_idx]; 12396 struct elink_params *lp = &sc->link_params; 12397 12398 bxe_set_requested_fc(sc); 12399 12400 if (CHIP_REV_IS_SLOW(sc)) { 12401 uint32_t bond = CHIP_BOND_ID(sc); 12402 uint32_t feat = 0; 12403 12404 if (CHIP_IS_E2(sc) && CHIP_IS_MODE_4_PORT(sc)) { 12405 feat |= ELINK_FEATURE_CONFIG_EMUL_DISABLE_BMAC; 12406 } else if (bond & 0x4) { 12407 if (CHIP_IS_E3(sc)) { 12408 feat |= ELINK_FEATURE_CONFIG_EMUL_DISABLE_XMAC; 12409 } else { 12410 feat |= ELINK_FEATURE_CONFIG_EMUL_DISABLE_BMAC; 12411 } 12412 } else if (bond & 0x8) { 12413 if (CHIP_IS_E3(sc)) { 12414 feat |= ELINK_FEATURE_CONFIG_EMUL_DISABLE_UMAC; 12415 } else { 12416 feat |= ELINK_FEATURE_CONFIG_EMUL_DISABLE_EMAC; 12417 } 12418 } 12419 12420 /* disable EMAC for E3 and above */ 12421 if (bond & 0x2) { 12422 feat |= ELINK_FEATURE_CONFIG_EMUL_DISABLE_EMAC; 12423 } 12424 12425 sc->link_params.feature_config_flags |= feat; 12426 } 12427 12428 BXE_PHY_LOCK(sc); 12429 12430 if (load_mode == LOAD_DIAG) { 12431 lp->loopback_mode = ELINK_LOOPBACK_XGXS; 12432 /* Prefer doing PHY loopback at 10G speed, if possible */ 12433 if (lp->req_line_speed[cfg_idx] < ELINK_SPEED_10000) { 12434 if (lp->speed_cap_mask[cfg_idx] & 12435 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) { 12436 lp->req_line_speed[cfg_idx] = ELINK_SPEED_10000; 12437 } else { 12438 lp->req_line_speed[cfg_idx] = ELINK_SPEED_1000; 12439 } 12440 } 12441 } 12442 12443 if (load_mode == LOAD_LOOPBACK_EXT) { 12444 lp->loopback_mode = ELINK_LOOPBACK_EXT; 12445 } 12446 12447 rc = elink_phy_init(&sc->link_params, &sc->link_vars); 12448 12449 BXE_PHY_UNLOCK(sc); 12450 12451 bxe_calc_fc_adv(sc); 12452 12453 if (sc->link_vars.link_up) { 12454 bxe_stats_handle(sc, STATS_EVENT_LINK_UP); 12455 bxe_link_report(sc); 12456 } 12457 12458 if (!CHIP_REV_IS_SLOW(sc)) { 12459 bxe_periodic_start(sc); 12460 } 12461 12462 sc->link_params.req_line_speed[cfg_idx] = req_line_speed; 12463 return (rc); 12464 } 12465 12466 /* must be called under IF_ADDR_LOCK */ 12467 static int 12468 bxe_init_mcast_macs_list(struct bxe_softc *sc, 12469 struct ecore_mcast_ramrod_params *p) 12470 { 12471 struct ifnet *ifp = sc->ifnet; 12472 int mc_count = 0; 12473 struct ifmultiaddr *ifma; 12474 struct ecore_mcast_list_elem *mc_mac; 12475 12476 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 12477 if (ifma->ifma_addr->sa_family != AF_LINK) { 12478 continue; 12479 } 12480 12481 mc_count++; 12482 } 12483 12484 ECORE_LIST_INIT(&p->mcast_list); 12485 p->mcast_list_len = 0; 12486 12487 if (!mc_count) { 12488 return (0); 12489 } 12490 12491 mc_mac = malloc(sizeof(*mc_mac) * mc_count, M_DEVBUF, 12492 (M_NOWAIT | M_ZERO)); 12493 if (!mc_mac) { 12494 BLOGE(sc, "Failed to allocate temp mcast list\n"); 12495 return (-1); 12496 } 12497 12498 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 12499 if (ifma->ifma_addr->sa_family != AF_LINK) { 12500 continue; 12501 } 12502 12503 mc_mac->mac = (uint8_t *)LLADDR((struct sockaddr_dl *)ifma->ifma_addr); 12504 ECORE_LIST_PUSH_TAIL(&mc_mac->link, &p->mcast_list); 12505 12506 BLOGD(sc, DBG_LOAD, 12507 "Setting MCAST %02X:%02X:%02X:%02X:%02X:%02X\n", 12508 mc_mac->mac[0], mc_mac->mac[1], mc_mac->mac[2], 12509 mc_mac->mac[3], mc_mac->mac[4], mc_mac->mac[5]); 12510 12511 mc_mac++; 12512 } 12513 12514 p->mcast_list_len = mc_count; 12515 12516 return (0); 12517 } 12518 12519 static void 12520 bxe_free_mcast_macs_list(struct ecore_mcast_ramrod_params *p) 12521 { 12522 struct ecore_mcast_list_elem *mc_mac = 12523 ECORE_LIST_FIRST_ENTRY(&p->mcast_list, 12524 struct ecore_mcast_list_elem, 12525 link); 12526 12527 if (mc_mac) { 12528 /* only a single free as all mc_macs are in the same heap array */ 12529 free(mc_mac, M_DEVBUF); 12530 } 12531 } 12532 12533 static int 12534 bxe_set_mc_list(struct bxe_softc *sc) 12535 { 12536 struct ecore_mcast_ramrod_params rparam = { NULL }; 12537 int rc = 0; 12538 12539 rparam.mcast_obj = &sc->mcast_obj; 12540 12541 BXE_MCAST_LOCK(sc); 12542 12543 /* first, clear all configured multicast MACs */ 12544 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_DEL); 12545 if (rc < 0) { 12546 BLOGE(sc, "Failed to clear multicast configuration: %d\n", rc); 12547 return (rc); 12548 } 12549 12550 /* configure a new MACs list */ 12551 rc = bxe_init_mcast_macs_list(sc, &rparam); 12552 if (rc) { 12553 BLOGE(sc, "Failed to create mcast MACs list (%d)\n", rc); 12554 BXE_MCAST_UNLOCK(sc); 12555 return (rc); 12556 } 12557 12558 /* Now add the new MACs */ 12559 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_ADD); 12560 if (rc < 0) { 12561 BLOGE(sc, "Failed to set new mcast config (%d)\n", rc); 12562 } 12563 12564 bxe_free_mcast_macs_list(&rparam); 12565 12566 BXE_MCAST_UNLOCK(sc); 12567 12568 return (rc); 12569 } 12570 12571 static int 12572 bxe_set_uc_list(struct bxe_softc *sc) 12573 { 12574 struct ifnet *ifp = sc->ifnet; 12575 struct ecore_vlan_mac_obj *mac_obj = &sc->sp_objs->mac_obj; 12576 struct ifaddr *ifa; 12577 unsigned long ramrod_flags = 0; 12578 int rc; 12579 12580 #if __FreeBSD_version < 800000 12581 IF_ADDR_LOCK(ifp); 12582 #else 12583 if_addr_rlock(ifp); 12584 #endif 12585 12586 /* first schedule a cleanup up of old configuration */ 12587 rc = bxe_del_all_macs(sc, mac_obj, ECORE_UC_LIST_MAC, FALSE); 12588 if (rc < 0) { 12589 BLOGE(sc, "Failed to schedule delete of all ETH MACs (%d)\n", rc); 12590 #if __FreeBSD_version < 800000 12591 IF_ADDR_UNLOCK(ifp); 12592 #else 12593 if_addr_runlock(ifp); 12594 #endif 12595 return (rc); 12596 } 12597 12598 ifa = ifp->if_addr; 12599 while (ifa) { 12600 if (ifa->ifa_addr->sa_family != AF_LINK) { 12601 ifa = TAILQ_NEXT(ifa, ifa_link); 12602 continue; 12603 } 12604 12605 rc = bxe_set_mac_one(sc, (uint8_t *)LLADDR((struct sockaddr_dl *)ifa->ifa_addr), 12606 mac_obj, TRUE, ECORE_UC_LIST_MAC, &ramrod_flags); 12607 if (rc == -EEXIST) { 12608 BLOGD(sc, DBG_SP, "Failed to schedule ADD operations (EEXIST)\n"); 12609 /* do not treat adding same MAC as an error */ 12610 rc = 0; 12611 } else if (rc < 0) { 12612 BLOGE(sc, "Failed to schedule ADD operations (%d)\n", rc); 12613 #if __FreeBSD_version < 800000 12614 IF_ADDR_UNLOCK(ifp); 12615 #else 12616 if_addr_runlock(ifp); 12617 #endif 12618 return (rc); 12619 } 12620 12621 ifa = TAILQ_NEXT(ifa, ifa_link); 12622 } 12623 12624 #if __FreeBSD_version < 800000 12625 IF_ADDR_UNLOCK(ifp); 12626 #else 12627 if_addr_runlock(ifp); 12628 #endif 12629 12630 /* Execute the pending commands */ 12631 bit_set(&ramrod_flags, RAMROD_CONT); 12632 return (bxe_set_mac_one(sc, NULL, mac_obj, FALSE /* don't care */, 12633 ECORE_UC_LIST_MAC, &ramrod_flags)); 12634 } 12635 12636 static void 12637 bxe_handle_rx_mode_tq(void *context, 12638 int pending) 12639 { 12640 struct bxe_softc *sc = (struct bxe_softc *)context; 12641 struct ifnet *ifp = sc->ifnet; 12642 uint32_t rx_mode = BXE_RX_MODE_NORMAL; 12643 12644 BXE_CORE_LOCK(sc); 12645 12646 if (sc->state != BXE_STATE_OPEN) { 12647 BLOGD(sc, DBG_SP, "state is %x, returning\n", sc->state); 12648 BXE_CORE_UNLOCK(sc); 12649 return; 12650 } 12651 12652 BLOGD(sc, DBG_SP, "ifp->if_flags=0x%x\n", ifp->if_flags); 12653 12654 if (ifp->if_flags & IFF_PROMISC) { 12655 rx_mode = BXE_RX_MODE_PROMISC; 12656 } else if ((ifp->if_flags & IFF_ALLMULTI) || 12657 ((ifp->if_amcount > BXE_MAX_MULTICAST) && 12658 CHIP_IS_E1(sc))) { 12659 rx_mode = BXE_RX_MODE_ALLMULTI; 12660 } else { 12661 if (IS_PF(sc)) { 12662 /* some multicasts */ 12663 if (bxe_set_mc_list(sc) < 0) { 12664 rx_mode = BXE_RX_MODE_ALLMULTI; 12665 } 12666 if (bxe_set_uc_list(sc) < 0) { 12667 rx_mode = BXE_RX_MODE_PROMISC; 12668 } 12669 } 12670 #if 0 12671 else { 12672 /* 12673 * Configuring mcast to a VF involves sleeping (when we 12674 * wait for the PF's response). Since this function is 12675 * called from a non sleepable context we must schedule 12676 * a work item for this purpose 12677 */ 12678 bxe_set_bit(BXE_SP_RTNL_VFPF_MCAST, &sc->sp_rtnl_state); 12679 schedule_delayed_work(&sc->sp_rtnl_task, 0); 12680 } 12681 #endif 12682 } 12683 12684 sc->rx_mode = rx_mode; 12685 12686 /* schedule the rx_mode command */ 12687 if (bxe_test_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state)) { 12688 BLOGD(sc, DBG_LOAD, "Scheduled setting rx_mode with ECORE...\n"); 12689 bxe_set_bit(ECORE_FILTER_RX_MODE_SCHED, &sc->sp_state); 12690 BXE_CORE_UNLOCK(sc); 12691 return; 12692 } 12693 12694 if (IS_PF(sc)) { 12695 bxe_set_storm_rx_mode(sc); 12696 } 12697 #if 0 12698 else { 12699 /* 12700 * Configuring mcast to a VF involves sleeping (when we 12701 * wait for the PF's response). Since this function is 12702 * called from a non sleepable context we must schedule 12703 * a work item for this purpose 12704 */ 12705 bxe_set_bit(BXE_SP_RTNL_VFPF_STORM_RX_MODE, &sc->sp_rtnl_state); 12706 schedule_delayed_work(&sc->sp_rtnl_task, 0); 12707 } 12708 #endif 12709 12710 BXE_CORE_UNLOCK(sc); 12711 } 12712 12713 static void 12714 bxe_set_rx_mode(struct bxe_softc *sc) 12715 { 12716 taskqueue_enqueue(sc->rx_mode_tq, &sc->rx_mode_tq_task); 12717 } 12718 12719 /* update flags in shmem */ 12720 static void 12721 bxe_update_drv_flags(struct bxe_softc *sc, 12722 uint32_t flags, 12723 uint32_t set) 12724 { 12725 uint32_t drv_flags; 12726 12727 if (SHMEM2_HAS(sc, drv_flags)) { 12728 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_DRV_FLAGS); 12729 drv_flags = SHMEM2_RD(sc, drv_flags); 12730 12731 if (set) { 12732 SET_FLAGS(drv_flags, flags); 12733 } else { 12734 RESET_FLAGS(drv_flags, flags); 12735 } 12736 12737 SHMEM2_WR(sc, drv_flags, drv_flags); 12738 BLOGD(sc, DBG_LOAD, "drv_flags 0x%08x\n", drv_flags); 12739 12740 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_DRV_FLAGS); 12741 } 12742 } 12743 12744 /* periodic timer callout routine, only runs when the interface is up */ 12745 12746 static void 12747 bxe_periodic_callout_func(void *xsc) 12748 { 12749 struct bxe_softc *sc = (struct bxe_softc *)xsc; 12750 int i; 12751 12752 if (!BXE_CORE_TRYLOCK(sc)) { 12753 /* just bail and try again next time */ 12754 12755 if ((sc->state == BXE_STATE_OPEN) && 12756 (atomic_load_acq_long(&sc->periodic_flags) == PERIODIC_GO)) { 12757 /* schedule the next periodic callout */ 12758 callout_reset(&sc->periodic_callout, hz, 12759 bxe_periodic_callout_func, sc); 12760 } 12761 12762 return; 12763 } 12764 12765 if ((sc->state != BXE_STATE_OPEN) || 12766 (atomic_load_acq_long(&sc->periodic_flags) == PERIODIC_STOP)) { 12767 BLOGW(sc, "periodic callout exit (state=0x%x)\n", sc->state); 12768 BXE_CORE_UNLOCK(sc); 12769 return; 12770 } 12771 12772 /* Check for TX timeouts on any fastpath. */ 12773 FOR_EACH_QUEUE(sc, i) { 12774 if (bxe_watchdog(sc, &sc->fp[i]) != 0) { 12775 /* Ruh-Roh, chip was reset! */ 12776 break; 12777 } 12778 } 12779 12780 if (!CHIP_REV_IS_SLOW(sc)) { 12781 /* 12782 * This barrier is needed to ensure the ordering between the writing 12783 * to the sc->port.pmf in the bxe_nic_load() or bxe_pmf_update() and 12784 * the reading here. 12785 */ 12786 mb(); 12787 if (sc->port.pmf) { 12788 BXE_PHY_LOCK(sc); 12789 elink_period_func(&sc->link_params, &sc->link_vars); 12790 BXE_PHY_UNLOCK(sc); 12791 } 12792 } 12793 12794 if (IS_PF(sc) && !BXE_NOMCP(sc)) { 12795 int mb_idx = SC_FW_MB_IDX(sc); 12796 uint32_t drv_pulse; 12797 uint32_t mcp_pulse; 12798 12799 ++sc->fw_drv_pulse_wr_seq; 12800 sc->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK; 12801 12802 drv_pulse = sc->fw_drv_pulse_wr_seq; 12803 bxe_drv_pulse(sc); 12804 12805 mcp_pulse = (SHMEM_RD(sc, func_mb[mb_idx].mcp_pulse_mb) & 12806 MCP_PULSE_SEQ_MASK); 12807 12808 /* 12809 * The delta between driver pulse and mcp response should 12810 * be 1 (before mcp response) or 0 (after mcp response). 12811 */ 12812 if ((drv_pulse != mcp_pulse) && 12813 (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) { 12814 /* someone lost a heartbeat... */ 12815 BLOGE(sc, "drv_pulse (0x%x) != mcp_pulse (0x%x)\n", 12816 drv_pulse, mcp_pulse); 12817 } 12818 } 12819 12820 /* state is BXE_STATE_OPEN */ 12821 bxe_stats_handle(sc, STATS_EVENT_UPDATE); 12822 12823 #if 0 12824 /* sample VF bulletin board for new posts from PF */ 12825 if (IS_VF(sc)) { 12826 bxe_sample_bulletin(sc); 12827 } 12828 #endif 12829 12830 BXE_CORE_UNLOCK(sc); 12831 12832 if ((sc->state == BXE_STATE_OPEN) && 12833 (atomic_load_acq_long(&sc->periodic_flags) == PERIODIC_GO)) { 12834 /* schedule the next periodic callout */ 12835 callout_reset(&sc->periodic_callout, hz, 12836 bxe_periodic_callout_func, sc); 12837 } 12838 } 12839 12840 static void 12841 bxe_periodic_start(struct bxe_softc *sc) 12842 { 12843 atomic_store_rel_long(&sc->periodic_flags, PERIODIC_GO); 12844 callout_reset(&sc->periodic_callout, hz, bxe_periodic_callout_func, sc); 12845 } 12846 12847 static void 12848 bxe_periodic_stop(struct bxe_softc *sc) 12849 { 12850 atomic_store_rel_long(&sc->periodic_flags, PERIODIC_STOP); 12851 callout_drain(&sc->periodic_callout); 12852 } 12853 12854 /* start the controller */ 12855 static __noinline int 12856 bxe_nic_load(struct bxe_softc *sc, 12857 int load_mode) 12858 { 12859 uint32_t val; 12860 int load_code = 0; 12861 int i, rc = 0; 12862 12863 BXE_CORE_LOCK_ASSERT(sc); 12864 12865 BLOGD(sc, DBG_LOAD, "Starting NIC load...\n"); 12866 12867 sc->state = BXE_STATE_OPENING_WAITING_LOAD; 12868 12869 if (IS_PF(sc)) { 12870 /* must be called before memory allocation and HW init */ 12871 bxe_ilt_set_info(sc); 12872 } 12873 12874 sc->last_reported_link_state = LINK_STATE_UNKNOWN; 12875 12876 bxe_set_fp_rx_buf_size(sc); 12877 12878 if (bxe_alloc_fp_buffers(sc) != 0) { 12879 BLOGE(sc, "Failed to allocate fastpath memory\n"); 12880 sc->state = BXE_STATE_CLOSED; 12881 rc = ENOMEM; 12882 goto bxe_nic_load_error0; 12883 } 12884 12885 if (bxe_alloc_mem(sc) != 0) { 12886 sc->state = BXE_STATE_CLOSED; 12887 rc = ENOMEM; 12888 goto bxe_nic_load_error0; 12889 } 12890 12891 if (bxe_alloc_fw_stats_mem(sc) != 0) { 12892 sc->state = BXE_STATE_CLOSED; 12893 rc = ENOMEM; 12894 goto bxe_nic_load_error0; 12895 } 12896 12897 if (IS_PF(sc)) { 12898 /* set pf load just before approaching the MCP */ 12899 bxe_set_pf_load(sc); 12900 12901 /* if MCP exists send load request and analyze response */ 12902 if (!BXE_NOMCP(sc)) { 12903 /* attempt to load pf */ 12904 if (bxe_nic_load_request(sc, &load_code) != 0) { 12905 sc->state = BXE_STATE_CLOSED; 12906 rc = ENXIO; 12907 goto bxe_nic_load_error1; 12908 } 12909 12910 /* what did the MCP say? */ 12911 if (bxe_nic_load_analyze_req(sc, load_code) != 0) { 12912 bxe_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0); 12913 sc->state = BXE_STATE_CLOSED; 12914 rc = ENXIO; 12915 goto bxe_nic_load_error2; 12916 } 12917 } else { 12918 BLOGI(sc, "Device has no MCP!\n"); 12919 load_code = bxe_nic_load_no_mcp(sc); 12920 } 12921 12922 /* mark PMF if applicable */ 12923 bxe_nic_load_pmf(sc, load_code); 12924 12925 /* Init Function state controlling object */ 12926 bxe_init_func_obj(sc); 12927 12928 /* Initialize HW */ 12929 if (bxe_init_hw(sc, load_code) != 0) { 12930 BLOGE(sc, "HW init failed\n"); 12931 bxe_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0); 12932 sc->state = BXE_STATE_CLOSED; 12933 rc = ENXIO; 12934 goto bxe_nic_load_error2; 12935 } 12936 } 12937 12938 /* attach interrupts */ 12939 if (bxe_interrupt_attach(sc) != 0) { 12940 sc->state = BXE_STATE_CLOSED; 12941 rc = ENXIO; 12942 goto bxe_nic_load_error2; 12943 } 12944 12945 bxe_nic_init(sc, load_code); 12946 12947 /* Init per-function objects */ 12948 if (IS_PF(sc)) { 12949 bxe_init_objs(sc); 12950 // XXX bxe_iov_nic_init(sc); 12951 12952 /* set AFEX default VLAN tag to an invalid value */ 12953 sc->devinfo.mf_info.afex_def_vlan_tag = -1; 12954 // XXX bxe_nic_load_afex_dcc(sc, load_code); 12955 12956 sc->state = BXE_STATE_OPENING_WAITING_PORT; 12957 rc = bxe_func_start(sc); 12958 if (rc) { 12959 BLOGE(sc, "Function start failed!\n"); 12960 bxe_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0); 12961 sc->state = BXE_STATE_ERROR; 12962 goto bxe_nic_load_error3; 12963 } 12964 12965 /* send LOAD_DONE command to MCP */ 12966 if (!BXE_NOMCP(sc)) { 12967 load_code = bxe_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0); 12968 if (!load_code) { 12969 BLOGE(sc, "MCP response failure, aborting\n"); 12970 sc->state = BXE_STATE_ERROR; 12971 rc = ENXIO; 12972 goto bxe_nic_load_error3; 12973 } 12974 } 12975 12976 rc = bxe_setup_leading(sc); 12977 if (rc) { 12978 BLOGE(sc, "Setup leading failed!\n"); 12979 sc->state = BXE_STATE_ERROR; 12980 goto bxe_nic_load_error3; 12981 } 12982 12983 FOR_EACH_NONDEFAULT_ETH_QUEUE(sc, i) { 12984 rc = bxe_setup_queue(sc, &sc->fp[i], FALSE); 12985 if (rc) { 12986 BLOGE(sc, "Queue(%d) setup failed\n", i); 12987 sc->state = BXE_STATE_ERROR; 12988 goto bxe_nic_load_error3; 12989 } 12990 } 12991 12992 rc = bxe_init_rss_pf(sc); 12993 if (rc) { 12994 BLOGE(sc, "PF RSS init failed\n"); 12995 sc->state = BXE_STATE_ERROR; 12996 goto bxe_nic_load_error3; 12997 } 12998 } 12999 /* XXX VF */ 13000 #if 0 13001 else { /* VF */ 13002 FOR_EACH_ETH_QUEUE(sc, i) { 13003 rc = bxe_vfpf_setup_q(sc, i); 13004 if (rc) { 13005 BLOGE(sc, "Queue(%d) setup failed\n", i); 13006 sc->state = BXE_STATE_ERROR; 13007 goto bxe_nic_load_error3; 13008 } 13009 } 13010 } 13011 #endif 13012 13013 /* now when Clients are configured we are ready to work */ 13014 sc->state = BXE_STATE_OPEN; 13015 13016 /* Configure a ucast MAC */ 13017 if (IS_PF(sc)) { 13018 rc = bxe_set_eth_mac(sc, TRUE); 13019 } 13020 #if 0 13021 else { /* IS_VF(sc) */ 13022 rc = bxe_vfpf_set_mac(sc); 13023 } 13024 #endif 13025 if (rc) { 13026 BLOGE(sc, "Setting Ethernet MAC failed\n"); 13027 sc->state = BXE_STATE_ERROR; 13028 goto bxe_nic_load_error3; 13029 } 13030 13031 #if 0 13032 if (IS_PF(sc) && sc->pending_max) { 13033 /* for AFEX */ 13034 bxe_update_max_mf_config(sc, sc->pending_max); 13035 sc->pending_max = 0; 13036 } 13037 #endif 13038 13039 if (sc->port.pmf) { 13040 rc = bxe_initial_phy_init(sc, /* XXX load_mode */LOAD_OPEN); 13041 if (rc) { 13042 sc->state = BXE_STATE_ERROR; 13043 goto bxe_nic_load_error3; 13044 } 13045 } 13046 13047 sc->link_params.feature_config_flags &= 13048 ~ELINK_FEATURE_CONFIG_BOOT_FROM_SAN; 13049 13050 /* start fast path */ 13051 13052 /* Initialize Rx filter */ 13053 bxe_set_rx_mode(sc); 13054 13055 /* start the Tx */ 13056 switch (/* XXX load_mode */LOAD_OPEN) { 13057 case LOAD_NORMAL: 13058 case LOAD_OPEN: 13059 break; 13060 13061 case LOAD_DIAG: 13062 case LOAD_LOOPBACK_EXT: 13063 sc->state = BXE_STATE_DIAG; 13064 break; 13065 13066 default: 13067 break; 13068 } 13069 13070 if (sc->port.pmf) { 13071 bxe_update_drv_flags(sc, 1 << DRV_FLAGS_PORT_MASK, 0); 13072 } else { 13073 bxe_link_status_update(sc); 13074 } 13075 13076 /* start the periodic timer callout */ 13077 bxe_periodic_start(sc); 13078 13079 if (IS_PF(sc) && SHMEM2_HAS(sc, drv_capabilities_flag)) { 13080 /* mark driver is loaded in shmem2 */ 13081 val = SHMEM2_RD(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)]); 13082 SHMEM2_WR(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)], 13083 (val | 13084 DRV_FLAGS_CAPABILITIES_LOADED_SUPPORTED | 13085 DRV_FLAGS_CAPABILITIES_LOADED_L2)); 13086 } 13087 13088 /* wait for all pending SP commands to complete */ 13089 if (IS_PF(sc) && !bxe_wait_sp_comp(sc, ~0x0UL)) { 13090 BLOGE(sc, "Timeout waiting for all SPs to complete!\n"); 13091 bxe_periodic_stop(sc); 13092 bxe_nic_unload(sc, UNLOAD_CLOSE, FALSE); 13093 return (ENXIO); 13094 } 13095 13096 #if 0 13097 /* If PMF - send ADMIN DCBX msg to MFW to initiate DCBX FSM */ 13098 if (sc->port.pmf && (sc->state != BXE_STATE_DIAG)) { 13099 bxe_dcbx_init(sc, FALSE); 13100 } 13101 #endif 13102 13103 /* Tell the stack the driver is running! */ 13104 sc->ifnet->if_drv_flags = IFF_DRV_RUNNING; 13105 13106 BLOGD(sc, DBG_LOAD, "NIC successfully loaded\n"); 13107 13108 return (0); 13109 13110 bxe_nic_load_error3: 13111 13112 if (IS_PF(sc)) { 13113 bxe_int_disable_sync(sc, 1); 13114 13115 /* clean out queued objects */ 13116 bxe_squeeze_objects(sc); 13117 } 13118 13119 bxe_interrupt_detach(sc); 13120 13121 bxe_nic_load_error2: 13122 13123 if (IS_PF(sc) && !BXE_NOMCP(sc)) { 13124 bxe_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0); 13125 bxe_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, 0); 13126 } 13127 13128 sc->port.pmf = 0; 13129 13130 bxe_nic_load_error1: 13131 13132 /* clear pf_load status, as it was already set */ 13133 if (IS_PF(sc)) { 13134 bxe_clear_pf_load(sc); 13135 } 13136 13137 bxe_nic_load_error0: 13138 13139 bxe_free_fw_stats_mem(sc); 13140 bxe_free_fp_buffers(sc); 13141 bxe_free_mem(sc); 13142 13143 return (rc); 13144 } 13145 13146 static int 13147 bxe_init_locked(struct bxe_softc *sc) 13148 { 13149 int other_engine = SC_PATH(sc) ? 0 : 1; 13150 uint8_t other_load_status, load_status; 13151 uint8_t global = FALSE; 13152 int rc; 13153 13154 BXE_CORE_LOCK_ASSERT(sc); 13155 13156 /* check if the driver is already running */ 13157 if (sc->ifnet->if_drv_flags & IFF_DRV_RUNNING) { 13158 BLOGD(sc, DBG_LOAD, "Init called while driver is running!\n"); 13159 return (0); 13160 } 13161 13162 bxe_set_power_state(sc, PCI_PM_D0); 13163 13164 /* 13165 * If parity occurred during the unload, then attentions and/or 13166 * RECOVERY_IN_PROGRES may still be set. If so we want the first function 13167 * loaded on the current engine to complete the recovery. Parity recovery 13168 * is only relevant for PF driver. 13169 */ 13170 if (IS_PF(sc)) { 13171 other_load_status = bxe_get_load_status(sc, other_engine); 13172 load_status = bxe_get_load_status(sc, SC_PATH(sc)); 13173 13174 if (!bxe_reset_is_done(sc, SC_PATH(sc)) || 13175 bxe_chk_parity_attn(sc, &global, TRUE)) { 13176 do { 13177 /* 13178 * If there are attentions and they are in global blocks, set 13179 * the GLOBAL_RESET bit regardless whether it will be this 13180 * function that will complete the recovery or not. 13181 */ 13182 if (global) { 13183 bxe_set_reset_global(sc); 13184 } 13185 13186 /* 13187 * Only the first function on the current engine should try 13188 * to recover in open. In case of attentions in global blocks 13189 * only the first in the chip should try to recover. 13190 */ 13191 if ((!load_status && (!global || !other_load_status)) && 13192 bxe_trylock_leader_lock(sc) && !bxe_leader_reset(sc)) { 13193 BLOGI(sc, "Recovered during init\n"); 13194 break; 13195 } 13196 13197 /* recovery has failed... */ 13198 bxe_set_power_state(sc, PCI_PM_D3hot); 13199 sc->recovery_state = BXE_RECOVERY_FAILED; 13200 13201 BLOGE(sc, "Recovery flow hasn't properly " 13202 "completed yet, try again later. " 13203 "If you still see this message after a " 13204 "few retries then power cycle is required.\n"); 13205 13206 rc = ENXIO; 13207 goto bxe_init_locked_done; 13208 } while (0); 13209 } 13210 } 13211 13212 sc->recovery_state = BXE_RECOVERY_DONE; 13213 13214 rc = bxe_nic_load(sc, LOAD_OPEN); 13215 13216 bxe_init_locked_done: 13217 13218 if (rc) { 13219 /* Tell the stack the driver is NOT running! */ 13220 BLOGE(sc, "Initialization failed, " 13221 "stack notified driver is NOT running!\n"); 13222 sc->ifnet->if_drv_flags &= ~IFF_DRV_RUNNING; 13223 } 13224 13225 return (rc); 13226 } 13227 13228 static int 13229 bxe_stop_locked(struct bxe_softc *sc) 13230 { 13231 BXE_CORE_LOCK_ASSERT(sc); 13232 return (bxe_nic_unload(sc, UNLOAD_NORMAL, TRUE)); 13233 } 13234 13235 /* 13236 * Handles controller initialization when called from an unlocked routine. 13237 * ifconfig calls this function. 13238 * 13239 * Returns: 13240 * void 13241 */ 13242 static void 13243 bxe_init(void *xsc) 13244 { 13245 struct bxe_softc *sc = (struct bxe_softc *)xsc; 13246 13247 BXE_CORE_LOCK(sc); 13248 bxe_init_locked(sc); 13249 BXE_CORE_UNLOCK(sc); 13250 } 13251 13252 static int 13253 bxe_init_ifnet(struct bxe_softc *sc) 13254 { 13255 struct ifnet *ifp; 13256 13257 /* ifconfig entrypoint for media type/status reporting */ 13258 ifmedia_init(&sc->ifmedia, IFM_IMASK, 13259 bxe_ifmedia_update, 13260 bxe_ifmedia_status); 13261 13262 /* set the default interface values */ 13263 ifmedia_add(&sc->ifmedia, (IFM_ETHER | IFM_FDX | sc->media), 0, NULL); 13264 ifmedia_add(&sc->ifmedia, (IFM_ETHER | IFM_AUTO), 0, NULL); 13265 ifmedia_set(&sc->ifmedia, (IFM_ETHER | IFM_AUTO)); 13266 13267 sc->ifmedia.ifm_media = sc->ifmedia.ifm_cur->ifm_media; /* XXX ? */ 13268 13269 /* allocate the ifnet structure */ 13270 if ((ifp = if_alloc(IFT_ETHER)) == NULL) { 13271 BLOGE(sc, "Interface allocation failed!\n"); 13272 return (ENXIO); 13273 } 13274 13275 ifp->if_softc = sc; 13276 if_initname(ifp, device_get_name(sc->dev), device_get_unit(sc->dev)); 13277 ifp->if_flags = (IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 13278 ifp->if_ioctl = bxe_ioctl; 13279 ifp->if_start = bxe_tx_start; 13280 #if __FreeBSD_version >= 800000 13281 ifp->if_transmit = bxe_tx_mq_start; 13282 ifp->if_qflush = bxe_mq_flush; 13283 #endif 13284 #ifdef FreeBSD8_0 13285 ifp->if_timer = 0; 13286 #endif 13287 ifp->if_init = bxe_init; 13288 ifp->if_mtu = sc->mtu; 13289 ifp->if_hwassist = (CSUM_IP | 13290 CSUM_TCP | 13291 CSUM_UDP | 13292 CSUM_TSO | 13293 CSUM_TCP_IPV6 | 13294 CSUM_UDP_IPV6); 13295 ifp->if_capabilities = 13296 #if __FreeBSD_version < 700000 13297 (IFCAP_VLAN_MTU | 13298 IFCAP_VLAN_HWTAGGING | 13299 IFCAP_HWCSUM | 13300 IFCAP_JUMBO_MTU | 13301 IFCAP_LRO); 13302 #else 13303 (IFCAP_VLAN_MTU | 13304 IFCAP_VLAN_HWTAGGING | 13305 IFCAP_VLAN_HWTSO | 13306 IFCAP_VLAN_HWFILTER | 13307 IFCAP_VLAN_HWCSUM | 13308 IFCAP_HWCSUM | 13309 IFCAP_JUMBO_MTU | 13310 IFCAP_LRO | 13311 IFCAP_TSO4 | 13312 IFCAP_TSO6 | 13313 IFCAP_WOL_MAGIC); 13314 #endif 13315 ifp->if_capenable = ifp->if_capabilities; 13316 ifp->if_capenable &= ~IFCAP_WOL_MAGIC; /* XXX not yet... */ 13317 ifp->if_baudrate = IF_Gbps(10); 13318 ifp->if_snd.ifq_drv_maxlen = sc->tx_ring_size; 13319 13320 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 13321 IFQ_SET_READY(&ifp->if_snd); 13322 13323 sc->ifnet = ifp; 13324 13325 /* attach to the Ethernet interface list */ 13326 ether_ifattach(ifp, sc->link_params.mac_addr); 13327 13328 return (0); 13329 } 13330 13331 static void 13332 bxe_deallocate_bars(struct bxe_softc *sc) 13333 { 13334 int i; 13335 13336 for (i = 0; i < MAX_BARS; i++) { 13337 if (sc->bar[i].resource != NULL) { 13338 bus_release_resource(sc->dev, 13339 SYS_RES_MEMORY, 13340 sc->bar[i].rid, 13341 sc->bar[i].resource); 13342 BLOGD(sc, DBG_LOAD, "Released PCI BAR%d [%02x] memory\n", 13343 i, PCIR_BAR(i)); 13344 } 13345 } 13346 } 13347 13348 static int 13349 bxe_allocate_bars(struct bxe_softc *sc) 13350 { 13351 u_int flags; 13352 int i; 13353 13354 memset(sc->bar, 0, sizeof(sc->bar)); 13355 13356 for (i = 0; i < MAX_BARS; i++) { 13357 13358 /* memory resources reside at BARs 0, 2, 4 */ 13359 /* Run `pciconf -lb` to see mappings */ 13360 if ((i != 0) && (i != 2) && (i != 4)) { 13361 continue; 13362 } 13363 13364 sc->bar[i].rid = PCIR_BAR(i); 13365 13366 flags = RF_ACTIVE; 13367 if (i == 0) { 13368 flags |= RF_SHAREABLE; 13369 } 13370 13371 if ((sc->bar[i].resource = 13372 bus_alloc_resource_any(sc->dev, 13373 SYS_RES_MEMORY, 13374 &sc->bar[i].rid, 13375 flags)) == NULL) { 13376 #if 0 13377 /* BAR4 doesn't exist for E1 */ 13378 BLOGE(sc, "PCI BAR%d [%02x] memory allocation failed\n", 13379 i, PCIR_BAR(i)); 13380 #endif 13381 return (0); 13382 } 13383 13384 sc->bar[i].tag = rman_get_bustag(sc->bar[i].resource); 13385 sc->bar[i].handle = rman_get_bushandle(sc->bar[i].resource); 13386 sc->bar[i].kva = (vm_offset_t)rman_get_virtual(sc->bar[i].resource); 13387 13388 BLOGI(sc, "PCI BAR%d [%02x] memory allocated: %p-%p (%ld) -> %p\n", 13389 i, PCIR_BAR(i), 13390 (void *)rman_get_start(sc->bar[i].resource), 13391 (void *)rman_get_end(sc->bar[i].resource), 13392 rman_get_size(sc->bar[i].resource), 13393 (void *)sc->bar[i].kva); 13394 } 13395 13396 return (0); 13397 } 13398 13399 static void 13400 bxe_get_function_num(struct bxe_softc *sc) 13401 { 13402 uint32_t val = 0; 13403 13404 /* 13405 * Read the ME register to get the function number. The ME register 13406 * holds the relative-function number and absolute-function number. The 13407 * absolute-function number appears only in E2 and above. Before that 13408 * these bits always contained zero, therefore we cannot blindly use them. 13409 */ 13410 13411 val = REG_RD(sc, BAR_ME_REGISTER); 13412 13413 sc->pfunc_rel = 13414 (uint8_t)((val & ME_REG_PF_NUM) >> ME_REG_PF_NUM_SHIFT); 13415 sc->path_id = 13416 (uint8_t)((val & ME_REG_ABS_PF_NUM) >> ME_REG_ABS_PF_NUM_SHIFT) & 1; 13417 13418 if (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) { 13419 sc->pfunc_abs = ((sc->pfunc_rel << 1) | sc->path_id); 13420 } else { 13421 sc->pfunc_abs = (sc->pfunc_rel | sc->path_id); 13422 } 13423 13424 BLOGD(sc, DBG_LOAD, 13425 "Relative function %d, Absolute function %d, Path %d\n", 13426 sc->pfunc_rel, sc->pfunc_abs, sc->path_id); 13427 } 13428 13429 static uint32_t 13430 bxe_get_shmem_mf_cfg_base(struct bxe_softc *sc) 13431 { 13432 uint32_t shmem2_size; 13433 uint32_t offset; 13434 uint32_t mf_cfg_offset_value; 13435 13436 /* Non 57712 */ 13437 offset = (SHMEM_RD(sc, func_mb) + 13438 (MAX_FUNC_NUM * sizeof(struct drv_func_mb))); 13439 13440 /* 57712 plus */ 13441 if (sc->devinfo.shmem2_base != 0) { 13442 shmem2_size = SHMEM2_RD(sc, size); 13443 if (shmem2_size > offsetof(struct shmem2_region, mf_cfg_addr)) { 13444 mf_cfg_offset_value = SHMEM2_RD(sc, mf_cfg_addr); 13445 if (SHMEM_MF_CFG_ADDR_NONE != mf_cfg_offset_value) { 13446 offset = mf_cfg_offset_value; 13447 } 13448 } 13449 } 13450 13451 return (offset); 13452 } 13453 13454 static uint32_t 13455 bxe_pcie_capability_read(struct bxe_softc *sc, 13456 int reg, 13457 int width) 13458 { 13459 int pcie_reg; 13460 13461 /* ensure PCIe capability is enabled */ 13462 if (pci_find_cap(sc->dev, PCIY_EXPRESS, &pcie_reg) == 0) { 13463 if (pcie_reg != 0) { 13464 BLOGD(sc, DBG_LOAD, "PCIe capability at 0x%04x\n", pcie_reg); 13465 return (pci_read_config(sc->dev, (pcie_reg + reg), width)); 13466 } 13467 } 13468 13469 BLOGE(sc, "PCIe capability NOT FOUND!!!\n"); 13470 13471 return (0); 13472 } 13473 13474 static uint8_t 13475 bxe_is_pcie_pending(struct bxe_softc *sc) 13476 { 13477 return (bxe_pcie_capability_read(sc, PCIR_EXPRESS_DEVICE_STA, 2) & 13478 PCIM_EXP_STA_TRANSACTION_PND); 13479 } 13480 13481 /* 13482 * Walk the PCI capabiites list for the device to find what features are 13483 * supported. These capabilites may be enabled/disabled by firmware so it's 13484 * best to walk the list rather than make assumptions. 13485 */ 13486 static void 13487 bxe_probe_pci_caps(struct bxe_softc *sc) 13488 { 13489 uint16_t link_status; 13490 int reg; 13491 13492 /* check if PCI Power Management is enabled */ 13493 if (pci_find_cap(sc->dev, PCIY_PMG, ®) == 0) { 13494 if (reg != 0) { 13495 BLOGD(sc, DBG_LOAD, "Found PM capability at 0x%04x\n", reg); 13496 13497 sc->devinfo.pcie_cap_flags |= BXE_PM_CAPABLE_FLAG; 13498 sc->devinfo.pcie_pm_cap_reg = (uint16_t)reg; 13499 } 13500 } 13501 13502 link_status = bxe_pcie_capability_read(sc, PCIR_EXPRESS_LINK_STA, 2); 13503 13504 /* handle PCIe 2.0 workarounds for 57710 */ 13505 if (CHIP_IS_E1(sc)) { 13506 /* workaround for 57710 errata E4_57710_27462 */ 13507 sc->devinfo.pcie_link_speed = 13508 (REG_RD(sc, 0x3d04) & (1 << 24)) ? 2 : 1; 13509 13510 /* workaround for 57710 errata E4_57710_27488 */ 13511 sc->devinfo.pcie_link_width = 13512 ((link_status & PCIM_LINK_STA_WIDTH) >> 4); 13513 if (sc->devinfo.pcie_link_speed > 1) { 13514 sc->devinfo.pcie_link_width = 13515 ((link_status & PCIM_LINK_STA_WIDTH) >> 4) >> 1; 13516 } 13517 } else { 13518 sc->devinfo.pcie_link_speed = 13519 (link_status & PCIM_LINK_STA_SPEED); 13520 sc->devinfo.pcie_link_width = 13521 ((link_status & PCIM_LINK_STA_WIDTH) >> 4); 13522 } 13523 13524 BLOGD(sc, DBG_LOAD, "PCIe link speed=%d width=%d\n", 13525 sc->devinfo.pcie_link_speed, sc->devinfo.pcie_link_width); 13526 13527 sc->devinfo.pcie_cap_flags |= BXE_PCIE_CAPABLE_FLAG; 13528 sc->devinfo.pcie_pcie_cap_reg = (uint16_t)reg; 13529 13530 /* check if MSI capability is enabled */ 13531 if (pci_find_cap(sc->dev, PCIY_MSI, ®) == 0) { 13532 if (reg != 0) { 13533 BLOGD(sc, DBG_LOAD, "Found MSI capability at 0x%04x\n", reg); 13534 13535 sc->devinfo.pcie_cap_flags |= BXE_MSI_CAPABLE_FLAG; 13536 sc->devinfo.pcie_msi_cap_reg = (uint16_t)reg; 13537 } 13538 } 13539 13540 /* check if MSI-X capability is enabled */ 13541 if (pci_find_cap(sc->dev, PCIY_MSIX, ®) == 0) { 13542 if (reg != 0) { 13543 BLOGD(sc, DBG_LOAD, "Found MSI-X capability at 0x%04x\n", reg); 13544 13545 sc->devinfo.pcie_cap_flags |= BXE_MSIX_CAPABLE_FLAG; 13546 sc->devinfo.pcie_msix_cap_reg = (uint16_t)reg; 13547 } 13548 } 13549 } 13550 13551 static int 13552 bxe_get_shmem_mf_cfg_info_sd(struct bxe_softc *sc) 13553 { 13554 struct bxe_mf_info *mf_info = &sc->devinfo.mf_info; 13555 uint32_t val; 13556 13557 /* get the outer vlan if we're in switch-dependent mode */ 13558 13559 val = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag); 13560 mf_info->ext_id = (uint16_t)val; 13561 13562 mf_info->multi_vnics_mode = 1; 13563 13564 if (!VALID_OVLAN(mf_info->ext_id)) { 13565 BLOGE(sc, "Invalid VLAN (%d)\n", mf_info->ext_id); 13566 return (1); 13567 } 13568 13569 /* get the capabilities */ 13570 if ((mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_PROTOCOL_MASK) == 13571 FUNC_MF_CFG_PROTOCOL_ISCSI) { 13572 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_ISCSI; 13573 } else if ((mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_PROTOCOL_MASK) == 13574 FUNC_MF_CFG_PROTOCOL_FCOE) { 13575 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_FCOE; 13576 } else { 13577 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_ETHERNET; 13578 } 13579 13580 mf_info->vnics_per_port = 13581 (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4; 13582 13583 return (0); 13584 } 13585 13586 static uint32_t 13587 bxe_get_shmem_ext_proto_support_flags(struct bxe_softc *sc) 13588 { 13589 uint32_t retval = 0; 13590 uint32_t val; 13591 13592 val = MFCFG_RD(sc, func_ext_config[SC_ABS_FUNC(sc)].func_cfg); 13593 13594 if (val & MACP_FUNC_CFG_FLAGS_ENABLED) { 13595 if (val & MACP_FUNC_CFG_FLAGS_ETHERNET) { 13596 retval |= MF_PROTO_SUPPORT_ETHERNET; 13597 } 13598 if (val & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) { 13599 retval |= MF_PROTO_SUPPORT_ISCSI; 13600 } 13601 if (val & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) { 13602 retval |= MF_PROTO_SUPPORT_FCOE; 13603 } 13604 } 13605 13606 return (retval); 13607 } 13608 13609 static int 13610 bxe_get_shmem_mf_cfg_info_si(struct bxe_softc *sc) 13611 { 13612 struct bxe_mf_info *mf_info = &sc->devinfo.mf_info; 13613 uint32_t val; 13614 13615 /* 13616 * There is no outer vlan if we're in switch-independent mode. 13617 * If the mac is valid then assume multi-function. 13618 */ 13619 13620 val = MFCFG_RD(sc, func_ext_config[SC_ABS_FUNC(sc)].func_cfg); 13621 13622 mf_info->multi_vnics_mode = ((val & MACP_FUNC_CFG_FLAGS_MASK) != 0); 13623 13624 mf_info->mf_protos_supported = bxe_get_shmem_ext_proto_support_flags(sc); 13625 13626 mf_info->vnics_per_port = 13627 (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4; 13628 13629 return (0); 13630 } 13631 13632 static int 13633 bxe_get_shmem_mf_cfg_info_niv(struct bxe_softc *sc) 13634 { 13635 struct bxe_mf_info *mf_info = &sc->devinfo.mf_info; 13636 uint32_t e1hov_tag; 13637 uint32_t func_config; 13638 uint32_t niv_config; 13639 13640 mf_info->multi_vnics_mode = 1; 13641 13642 e1hov_tag = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag); 13643 func_config = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].config); 13644 niv_config = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].afex_config); 13645 13646 mf_info->ext_id = 13647 (uint16_t)((e1hov_tag & FUNC_MF_CFG_E1HOV_TAG_MASK) >> 13648 FUNC_MF_CFG_E1HOV_TAG_SHIFT); 13649 13650 mf_info->default_vlan = 13651 (uint16_t)((e1hov_tag & FUNC_MF_CFG_AFEX_VLAN_MASK) >> 13652 FUNC_MF_CFG_AFEX_VLAN_SHIFT); 13653 13654 mf_info->niv_allowed_priorities = 13655 (uint8_t)((niv_config & FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >> 13656 FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT); 13657 13658 mf_info->niv_default_cos = 13659 (uint8_t)((func_config & FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >> 13660 FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT); 13661 13662 mf_info->afex_vlan_mode = 13663 ((niv_config & FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >> 13664 FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT); 13665 13666 mf_info->niv_mba_enabled = 13667 ((niv_config & FUNC_MF_CFG_AFEX_MBA_ENABLED_MASK) >> 13668 FUNC_MF_CFG_AFEX_MBA_ENABLED_SHIFT); 13669 13670 mf_info->mf_protos_supported = bxe_get_shmem_ext_proto_support_flags(sc); 13671 13672 mf_info->vnics_per_port = 13673 (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4; 13674 13675 return (0); 13676 } 13677 13678 static int 13679 bxe_check_valid_mf_cfg(struct bxe_softc *sc) 13680 { 13681 struct bxe_mf_info *mf_info = &sc->devinfo.mf_info; 13682 uint32_t mf_cfg1; 13683 uint32_t mf_cfg2; 13684 uint32_t ovlan1; 13685 uint32_t ovlan2; 13686 uint8_t i, j; 13687 13688 BLOGD(sc, DBG_LOAD, "MF config parameters for function %d\n", 13689 SC_PORT(sc)); 13690 BLOGD(sc, DBG_LOAD, "\tmf_config=0x%x\n", 13691 mf_info->mf_config[SC_VN(sc)]); 13692 BLOGD(sc, DBG_LOAD, "\tmulti_vnics_mode=%d\n", 13693 mf_info->multi_vnics_mode); 13694 BLOGD(sc, DBG_LOAD, "\tvnics_per_port=%d\n", 13695 mf_info->vnics_per_port); 13696 BLOGD(sc, DBG_LOAD, "\tovlan/vifid=%d\n", 13697 mf_info->ext_id); 13698 BLOGD(sc, DBG_LOAD, "\tmin_bw=%d/%d/%d/%d\n", 13699 mf_info->min_bw[0], mf_info->min_bw[1], 13700 mf_info->min_bw[2], mf_info->min_bw[3]); 13701 BLOGD(sc, DBG_LOAD, "\tmax_bw=%d/%d/%d/%d\n", 13702 mf_info->max_bw[0], mf_info->max_bw[1], 13703 mf_info->max_bw[2], mf_info->max_bw[3]); 13704 BLOGD(sc, DBG_LOAD, "\tmac_addr: %s\n", 13705 sc->mac_addr_str); 13706 13707 /* various MF mode sanity checks... */ 13708 13709 if (mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_FUNC_HIDE) { 13710 BLOGE(sc, "Enumerated function %d is marked as hidden\n", 13711 SC_PORT(sc)); 13712 return (1); 13713 } 13714 13715 if ((mf_info->vnics_per_port > 1) && !mf_info->multi_vnics_mode) { 13716 BLOGE(sc, "vnics_per_port=%d multi_vnics_mode=%d\n", 13717 mf_info->vnics_per_port, mf_info->multi_vnics_mode); 13718 return (1); 13719 } 13720 13721 if (mf_info->mf_mode == MULTI_FUNCTION_SD) { 13722 /* vnic id > 0 must have valid ovlan in switch-dependent mode */ 13723 if ((SC_VN(sc) > 0) && !VALID_OVLAN(OVLAN(sc))) { 13724 BLOGE(sc, "mf_mode=SD vnic_id=%d ovlan=%d\n", 13725 SC_VN(sc), OVLAN(sc)); 13726 return (1); 13727 } 13728 13729 if (!VALID_OVLAN(OVLAN(sc)) && mf_info->multi_vnics_mode) { 13730 BLOGE(sc, "mf_mode=SD multi_vnics_mode=%d ovlan=%d\n", 13731 mf_info->multi_vnics_mode, OVLAN(sc)); 13732 return (1); 13733 } 13734 13735 /* 13736 * Verify all functions are either MF or SF mode. If MF, make sure 13737 * sure that all non-hidden functions have a valid ovlan. If SF, 13738 * make sure that all non-hidden functions have an invalid ovlan. 13739 */ 13740 FOREACH_ABS_FUNC_IN_PORT(sc, i) { 13741 mf_cfg1 = MFCFG_RD(sc, func_mf_config[i].config); 13742 ovlan1 = MFCFG_RD(sc, func_mf_config[i].e1hov_tag); 13743 if (!(mf_cfg1 & FUNC_MF_CFG_FUNC_HIDE) && 13744 (((mf_info->multi_vnics_mode) && !VALID_OVLAN(ovlan1)) || 13745 ((!mf_info->multi_vnics_mode) && VALID_OVLAN(ovlan1)))) { 13746 BLOGE(sc, "mf_mode=SD function %d MF config " 13747 "mismatch, multi_vnics_mode=%d ovlan=%d\n", 13748 i, mf_info->multi_vnics_mode, ovlan1); 13749 return (1); 13750 } 13751 } 13752 13753 /* Verify all funcs on the same port each have a different ovlan. */ 13754 FOREACH_ABS_FUNC_IN_PORT(sc, i) { 13755 mf_cfg1 = MFCFG_RD(sc, func_mf_config[i].config); 13756 ovlan1 = MFCFG_RD(sc, func_mf_config[i].e1hov_tag); 13757 /* iterate from the next function on the port to the max func */ 13758 for (j = i + 2; j < MAX_FUNC_NUM; j += 2) { 13759 mf_cfg2 = MFCFG_RD(sc, func_mf_config[j].config); 13760 ovlan2 = MFCFG_RD(sc, func_mf_config[j].e1hov_tag); 13761 if (!(mf_cfg1 & FUNC_MF_CFG_FUNC_HIDE) && 13762 VALID_OVLAN(ovlan1) && 13763 !(mf_cfg2 & FUNC_MF_CFG_FUNC_HIDE) && 13764 VALID_OVLAN(ovlan2) && 13765 (ovlan1 == ovlan2)) { 13766 BLOGE(sc, "mf_mode=SD functions %d and %d " 13767 "have the same ovlan (%d)\n", 13768 i, j, ovlan1); 13769 return (1); 13770 } 13771 } 13772 } 13773 } /* MULTI_FUNCTION_SD */ 13774 13775 return (0); 13776 } 13777 13778 static int 13779 bxe_get_mf_cfg_info(struct bxe_softc *sc) 13780 { 13781 struct bxe_mf_info *mf_info = &sc->devinfo.mf_info; 13782 uint32_t val, mac_upper; 13783 uint8_t i, vnic; 13784 13785 /* initialize mf_info defaults */ 13786 mf_info->vnics_per_port = 1; 13787 mf_info->multi_vnics_mode = FALSE; 13788 mf_info->path_has_ovlan = FALSE; 13789 mf_info->mf_mode = SINGLE_FUNCTION; 13790 13791 if (!CHIP_IS_MF_CAP(sc)) { 13792 return (0); 13793 } 13794 13795 if (sc->devinfo.mf_cfg_base == SHMEM_MF_CFG_ADDR_NONE) { 13796 BLOGE(sc, "Invalid mf_cfg_base!\n"); 13797 return (1); 13798 } 13799 13800 /* get the MF mode (switch dependent / independent / single-function) */ 13801 13802 val = SHMEM_RD(sc, dev_info.shared_feature_config.config); 13803 13804 switch (val & SHARED_FEAT_CFG_FORCE_SF_MODE_MASK) 13805 { 13806 case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT: 13807 13808 mac_upper = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper); 13809 13810 /* check for legal upper mac bytes */ 13811 if (mac_upper != FUNC_MF_CFG_UPPERMAC_DEFAULT) { 13812 mf_info->mf_mode = MULTI_FUNCTION_SI; 13813 } else { 13814 BLOGE(sc, "Invalid config for Switch Independent mode\n"); 13815 } 13816 13817 break; 13818 13819 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED: 13820 case SHARED_FEAT_CFG_FORCE_SF_MODE_SPIO4: 13821 13822 /* get outer vlan configuration */ 13823 val = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag); 13824 13825 if ((val & FUNC_MF_CFG_E1HOV_TAG_MASK) != 13826 FUNC_MF_CFG_E1HOV_TAG_DEFAULT) { 13827 mf_info->mf_mode = MULTI_FUNCTION_SD; 13828 } else { 13829 BLOGE(sc, "Invalid config for Switch Dependent mode\n"); 13830 } 13831 13832 break; 13833 13834 case SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF: 13835 13836 /* not in MF mode, vnics_per_port=1 and multi_vnics_mode=FALSE */ 13837 return (0); 13838 13839 case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE: 13840 13841 /* 13842 * Mark MF mode as NIV if MCP version includes NPAR-SD support 13843 * and the MAC address is valid. 13844 */ 13845 mac_upper = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper); 13846 13847 if ((SHMEM2_HAS(sc, afex_driver_support)) && 13848 (mac_upper != FUNC_MF_CFG_UPPERMAC_DEFAULT)) { 13849 mf_info->mf_mode = MULTI_FUNCTION_AFEX; 13850 } else { 13851 BLOGE(sc, "Invalid config for AFEX mode\n"); 13852 } 13853 13854 break; 13855 13856 default: 13857 13858 BLOGE(sc, "Unknown MF mode (0x%08x)\n", 13859 (val & SHARED_FEAT_CFG_FORCE_SF_MODE_MASK)); 13860 13861 return (1); 13862 } 13863 13864 /* set path mf_mode (which could be different than function mf_mode) */ 13865 if (mf_info->mf_mode == MULTI_FUNCTION_SD) { 13866 mf_info->path_has_ovlan = TRUE; 13867 } else if (mf_info->mf_mode == SINGLE_FUNCTION) { 13868 /* 13869 * Decide on path multi vnics mode. If we're not in MF mode and in 13870 * 4-port mode, this is good enough to check vnic-0 of the other port 13871 * on the same path 13872 */ 13873 if (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) { 13874 uint8_t other_port = !(PORT_ID(sc) & 1); 13875 uint8_t abs_func_other_port = (SC_PATH(sc) + (2 * other_port)); 13876 13877 val = MFCFG_RD(sc, func_mf_config[abs_func_other_port].e1hov_tag); 13878 13879 mf_info->path_has_ovlan = VALID_OVLAN((uint16_t)val) ? 1 : 0; 13880 } 13881 } 13882 13883 if (mf_info->mf_mode == SINGLE_FUNCTION) { 13884 /* invalid MF config */ 13885 if (SC_VN(sc) >= 1) { 13886 BLOGE(sc, "VNIC ID >= 1 in SF mode\n"); 13887 return (1); 13888 } 13889 13890 return (0); 13891 } 13892 13893 /* get the MF configuration */ 13894 mf_info->mf_config[SC_VN(sc)] = 13895 MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].config); 13896 13897 switch(mf_info->mf_mode) 13898 { 13899 case MULTI_FUNCTION_SD: 13900 13901 bxe_get_shmem_mf_cfg_info_sd(sc); 13902 break; 13903 13904 case MULTI_FUNCTION_SI: 13905 13906 bxe_get_shmem_mf_cfg_info_si(sc); 13907 break; 13908 13909 case MULTI_FUNCTION_AFEX: 13910 13911 bxe_get_shmem_mf_cfg_info_niv(sc); 13912 break; 13913 13914 default: 13915 13916 BLOGE(sc, "Get MF config failed (mf_mode=0x%08x)\n", 13917 mf_info->mf_mode); 13918 return (1); 13919 } 13920 13921 /* get the congestion management parameters */ 13922 13923 vnic = 0; 13924 FOREACH_ABS_FUNC_IN_PORT(sc, i) { 13925 /* get min/max bw */ 13926 val = MFCFG_RD(sc, func_mf_config[i].config); 13927 mf_info->min_bw[vnic] = 13928 ((val & FUNC_MF_CFG_MIN_BW_MASK) >> FUNC_MF_CFG_MIN_BW_SHIFT); 13929 mf_info->max_bw[vnic] = 13930 ((val & FUNC_MF_CFG_MAX_BW_MASK) >> FUNC_MF_CFG_MAX_BW_SHIFT); 13931 vnic++; 13932 } 13933 13934 return (bxe_check_valid_mf_cfg(sc)); 13935 } 13936 13937 static int 13938 bxe_get_shmem_info(struct bxe_softc *sc) 13939 { 13940 int port; 13941 uint32_t mac_hi, mac_lo, val; 13942 13943 port = SC_PORT(sc); 13944 mac_hi = mac_lo = 0; 13945 13946 sc->link_params.sc = sc; 13947 sc->link_params.port = port; 13948 13949 /* get the hardware config info */ 13950 sc->devinfo.hw_config = 13951 SHMEM_RD(sc, dev_info.shared_hw_config.config); 13952 sc->devinfo.hw_config2 = 13953 SHMEM_RD(sc, dev_info.shared_hw_config.config2); 13954 13955 sc->link_params.hw_led_mode = 13956 ((sc->devinfo.hw_config & SHARED_HW_CFG_LED_MODE_MASK) >> 13957 SHARED_HW_CFG_LED_MODE_SHIFT); 13958 13959 /* get the port feature config */ 13960 sc->port.config = 13961 SHMEM_RD(sc, dev_info.port_feature_config[port].config), 13962 13963 /* get the link params */ 13964 sc->link_params.speed_cap_mask[0] = 13965 SHMEM_RD(sc, dev_info.port_hw_config[port].speed_capability_mask); 13966 sc->link_params.speed_cap_mask[1] = 13967 SHMEM_RD(sc, dev_info.port_hw_config[port].speed_capability_mask2); 13968 13969 /* get the lane config */ 13970 sc->link_params.lane_config = 13971 SHMEM_RD(sc, dev_info.port_hw_config[port].lane_config); 13972 13973 /* get the link config */ 13974 val = SHMEM_RD(sc, dev_info.port_feature_config[port].link_config); 13975 sc->port.link_config[ELINK_INT_PHY] = val; 13976 sc->link_params.switch_cfg = (val & PORT_FEATURE_CONNECTED_SWITCH_MASK); 13977 sc->port.link_config[ELINK_EXT_PHY1] = 13978 SHMEM_RD(sc, dev_info.port_feature_config[port].link_config2); 13979 13980 /* get the override preemphasis flag and enable it or turn it off */ 13981 val = SHMEM_RD(sc, dev_info.shared_feature_config.config); 13982 if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED) { 13983 sc->link_params.feature_config_flags |= 13984 ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED; 13985 } else { 13986 sc->link_params.feature_config_flags &= 13987 ~ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED; 13988 } 13989 13990 /* get the initial value of the link params */ 13991 sc->link_params.multi_phy_config = 13992 SHMEM_RD(sc, dev_info.port_hw_config[port].multi_phy_config); 13993 13994 /* get external phy info */ 13995 sc->port.ext_phy_config = 13996 SHMEM_RD(sc, dev_info.port_hw_config[port].external_phy_config); 13997 13998 /* get the multifunction configuration */ 13999 bxe_get_mf_cfg_info(sc); 14000 14001 /* get the mac address */ 14002 if (IS_MF(sc)) { 14003 mac_hi = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper); 14004 mac_lo = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_lower); 14005 } else { 14006 mac_hi = SHMEM_RD(sc, dev_info.port_hw_config[port].mac_upper); 14007 mac_lo = SHMEM_RD(sc, dev_info.port_hw_config[port].mac_lower); 14008 } 14009 14010 if ((mac_lo == 0) && (mac_hi == 0)) { 14011 *sc->mac_addr_str = 0; 14012 BLOGE(sc, "No Ethernet address programmed!\n"); 14013 } else { 14014 sc->link_params.mac_addr[0] = (uint8_t)(mac_hi >> 8); 14015 sc->link_params.mac_addr[1] = (uint8_t)(mac_hi); 14016 sc->link_params.mac_addr[2] = (uint8_t)(mac_lo >> 24); 14017 sc->link_params.mac_addr[3] = (uint8_t)(mac_lo >> 16); 14018 sc->link_params.mac_addr[4] = (uint8_t)(mac_lo >> 8); 14019 sc->link_params.mac_addr[5] = (uint8_t)(mac_lo); 14020 snprintf(sc->mac_addr_str, sizeof(sc->mac_addr_str), 14021 "%02x:%02x:%02x:%02x:%02x:%02x", 14022 sc->link_params.mac_addr[0], sc->link_params.mac_addr[1], 14023 sc->link_params.mac_addr[2], sc->link_params.mac_addr[3], 14024 sc->link_params.mac_addr[4], sc->link_params.mac_addr[5]); 14025 BLOGD(sc, DBG_LOAD, "Ethernet address: %s\n", sc->mac_addr_str); 14026 } 14027 14028 #if 0 14029 if (!IS_MF(sc) && 14030 ((sc->port.config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) == 14031 PORT_FEAT_CFG_STORAGE_PERSONALITY_FCOE)) { 14032 sc->flags |= BXE_NO_ISCSI; 14033 } 14034 if (!IS_MF(sc) && 14035 ((sc->port.config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) == 14036 PORT_FEAT_CFG_STORAGE_PERSONALITY_ISCSI)) { 14037 sc->flags |= BXE_NO_FCOE_FLAG; 14038 } 14039 #endif 14040 14041 return (0); 14042 } 14043 14044 static void 14045 bxe_get_tunable_params(struct bxe_softc *sc) 14046 { 14047 /* sanity checks */ 14048 14049 if ((bxe_interrupt_mode != INTR_MODE_INTX) && 14050 (bxe_interrupt_mode != INTR_MODE_MSI) && 14051 (bxe_interrupt_mode != INTR_MODE_MSIX)) { 14052 BLOGW(sc, "invalid interrupt_mode value (%d)\n", bxe_interrupt_mode); 14053 bxe_interrupt_mode = INTR_MODE_MSIX; 14054 } 14055 14056 if ((bxe_queue_count < 0) || (bxe_queue_count > MAX_RSS_CHAINS)) { 14057 BLOGW(sc, "invalid queue_count value (%d)\n", bxe_queue_count); 14058 bxe_queue_count = 0; 14059 } 14060 14061 if ((bxe_max_rx_bufs < 1) || (bxe_max_rx_bufs > RX_BD_USABLE)) { 14062 if (bxe_max_rx_bufs == 0) { 14063 bxe_max_rx_bufs = RX_BD_USABLE; 14064 } else { 14065 BLOGW(sc, "invalid max_rx_bufs (%d)\n", bxe_max_rx_bufs); 14066 bxe_max_rx_bufs = 2048; 14067 } 14068 } 14069 14070 if ((bxe_hc_rx_ticks < 1) || (bxe_hc_rx_ticks > 100)) { 14071 BLOGW(sc, "invalid hc_rx_ticks (%d)\n", bxe_hc_rx_ticks); 14072 bxe_hc_rx_ticks = 25; 14073 } 14074 14075 if ((bxe_hc_tx_ticks < 1) || (bxe_hc_tx_ticks > 100)) { 14076 BLOGW(sc, "invalid hc_tx_ticks (%d)\n", bxe_hc_tx_ticks); 14077 bxe_hc_tx_ticks = 50; 14078 } 14079 14080 if (bxe_max_aggregation_size == 0) { 14081 bxe_max_aggregation_size = TPA_AGG_SIZE; 14082 } 14083 14084 if (bxe_max_aggregation_size > 0xffff) { 14085 BLOGW(sc, "invalid max_aggregation_size (%d)\n", 14086 bxe_max_aggregation_size); 14087 bxe_max_aggregation_size = TPA_AGG_SIZE; 14088 } 14089 14090 if ((bxe_mrrs < -1) || (bxe_mrrs > 3)) { 14091 BLOGW(sc, "invalid mrrs (%d)\n", bxe_mrrs); 14092 bxe_mrrs = -1; 14093 } 14094 14095 if ((bxe_autogreeen < 0) || (bxe_autogreeen > 2)) { 14096 BLOGW(sc, "invalid autogreeen (%d)\n", bxe_autogreeen); 14097 bxe_autogreeen = 0; 14098 } 14099 14100 if ((bxe_udp_rss < 0) || (bxe_udp_rss > 1)) { 14101 BLOGW(sc, "invalid udp_rss (%d)\n", bxe_udp_rss); 14102 bxe_udp_rss = 0; 14103 } 14104 14105 /* pull in user settings */ 14106 14107 sc->interrupt_mode = bxe_interrupt_mode; 14108 sc->max_rx_bufs = bxe_max_rx_bufs; 14109 sc->hc_rx_ticks = bxe_hc_rx_ticks; 14110 sc->hc_tx_ticks = bxe_hc_tx_ticks; 14111 sc->max_aggregation_size = bxe_max_aggregation_size; 14112 sc->mrrs = bxe_mrrs; 14113 sc->autogreeen = bxe_autogreeen; 14114 sc->udp_rss = bxe_udp_rss; 14115 14116 if (bxe_interrupt_mode == INTR_MODE_INTX) { 14117 sc->num_queues = 1; 14118 } else { /* INTR_MODE_MSI or INTR_MODE_MSIX */ 14119 sc->num_queues = 14120 min((bxe_queue_count ? bxe_queue_count : mp_ncpus), 14121 MAX_RSS_CHAINS); 14122 if (sc->num_queues > mp_ncpus) { 14123 sc->num_queues = mp_ncpus; 14124 } 14125 } 14126 14127 BLOGD(sc, DBG_LOAD, 14128 "User Config: " 14129 "debug=0x%lx " 14130 "interrupt_mode=%d " 14131 "queue_count=%d " 14132 "hc_rx_ticks=%d " 14133 "hc_tx_ticks=%d " 14134 "rx_budget=%d " 14135 "max_aggregation_size=%d " 14136 "mrrs=%d " 14137 "autogreeen=%d " 14138 "udp_rss=%d\n", 14139 bxe_debug, 14140 sc->interrupt_mode, 14141 sc->num_queues, 14142 sc->hc_rx_ticks, 14143 sc->hc_tx_ticks, 14144 bxe_rx_budget, 14145 sc->max_aggregation_size, 14146 sc->mrrs, 14147 sc->autogreeen, 14148 sc->udp_rss); 14149 } 14150 14151 static void 14152 bxe_media_detect(struct bxe_softc *sc) 14153 { 14154 uint32_t phy_idx = bxe_get_cur_phy_idx(sc); 14155 switch (sc->link_params.phy[phy_idx].media_type) { 14156 case ELINK_ETH_PHY_SFPP_10G_FIBER: 14157 case ELINK_ETH_PHY_XFP_FIBER: 14158 BLOGI(sc, "Found 10Gb Fiber media.\n"); 14159 sc->media = IFM_10G_SR; 14160 break; 14161 case ELINK_ETH_PHY_SFP_1G_FIBER: 14162 BLOGI(sc, "Found 1Gb Fiber media.\n"); 14163 sc->media = IFM_1000_SX; 14164 break; 14165 case ELINK_ETH_PHY_KR: 14166 case ELINK_ETH_PHY_CX4: 14167 BLOGI(sc, "Found 10GBase-CX4 media.\n"); 14168 sc->media = IFM_10G_CX4; 14169 break; 14170 case ELINK_ETH_PHY_DA_TWINAX: 14171 BLOGI(sc, "Found 10Gb Twinax media.\n"); 14172 sc->media = IFM_10G_TWINAX; 14173 break; 14174 case ELINK_ETH_PHY_BASE_T: 14175 if (sc->link_params.speed_cap_mask[0] & 14176 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) { 14177 BLOGI(sc, "Found 10GBase-T media.\n"); 14178 sc->media = IFM_10G_T; 14179 } else { 14180 BLOGI(sc, "Found 1000Base-T media.\n"); 14181 sc->media = IFM_1000_T; 14182 } 14183 break; 14184 case ELINK_ETH_PHY_NOT_PRESENT: 14185 BLOGI(sc, "Media not present.\n"); 14186 sc->media = 0; 14187 break; 14188 case ELINK_ETH_PHY_UNSPECIFIED: 14189 default: 14190 BLOGI(sc, "Unknown media!\n"); 14191 sc->media = 0; 14192 break; 14193 } 14194 } 14195 14196 #define GET_FIELD(value, fname) \ 14197 (((value) & (fname##_MASK)) >> (fname##_SHIFT)) 14198 #define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID) 14199 #define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR) 14200 14201 static int 14202 bxe_get_igu_cam_info(struct bxe_softc *sc) 14203 { 14204 int pfid = SC_FUNC(sc); 14205 int igu_sb_id; 14206 uint32_t val; 14207 uint8_t fid, igu_sb_cnt = 0; 14208 14209 sc->igu_base_sb = 0xff; 14210 14211 if (CHIP_INT_MODE_IS_BC(sc)) { 14212 int vn = SC_VN(sc); 14213 igu_sb_cnt = sc->igu_sb_cnt; 14214 sc->igu_base_sb = ((CHIP_IS_MODE_4_PORT(sc) ? pfid : vn) * 14215 FP_SB_MAX_E1x); 14216 sc->igu_dsb_id = (E1HVN_MAX * FP_SB_MAX_E1x + 14217 (CHIP_IS_MODE_4_PORT(sc) ? pfid : vn)); 14218 return (0); 14219 } 14220 14221 /* IGU in normal mode - read CAM */ 14222 for (igu_sb_id = 0; 14223 igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE; 14224 igu_sb_id++) { 14225 val = REG_RD(sc, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4); 14226 if (!(val & IGU_REG_MAPPING_MEMORY_VALID)) { 14227 continue; 14228 } 14229 fid = IGU_FID(val); 14230 if ((fid & IGU_FID_ENCODE_IS_PF)) { 14231 if ((fid & IGU_FID_PF_NUM_MASK) != pfid) { 14232 continue; 14233 } 14234 if (IGU_VEC(val) == 0) { 14235 /* default status block */ 14236 sc->igu_dsb_id = igu_sb_id; 14237 } else { 14238 if (sc->igu_base_sb == 0xff) { 14239 sc->igu_base_sb = igu_sb_id; 14240 } 14241 igu_sb_cnt++; 14242 } 14243 } 14244 } 14245 14246 /* 14247 * Due to new PF resource allocation by MFW T7.4 and above, it's optional 14248 * that number of CAM entries will not be equal to the value advertised in 14249 * PCI. Driver should use the minimal value of both as the actual status 14250 * block count 14251 */ 14252 sc->igu_sb_cnt = min(sc->igu_sb_cnt, igu_sb_cnt); 14253 14254 if (igu_sb_cnt == 0) { 14255 BLOGE(sc, "CAM configuration error\n"); 14256 return (-1); 14257 } 14258 14259 return (0); 14260 } 14261 14262 /* 14263 * Gather various information from the device config space, the device itself, 14264 * shmem, and the user input. 14265 */ 14266 static int 14267 bxe_get_device_info(struct bxe_softc *sc) 14268 { 14269 uint32_t val; 14270 int rc; 14271 14272 /* Get the data for the device */ 14273 sc->devinfo.vendor_id = pci_get_vendor(sc->dev); 14274 sc->devinfo.device_id = pci_get_device(sc->dev); 14275 sc->devinfo.subvendor_id = pci_get_subvendor(sc->dev); 14276 sc->devinfo.subdevice_id = pci_get_subdevice(sc->dev); 14277 14278 /* get the chip revision (chip metal comes from pci config space) */ 14279 sc->devinfo.chip_id = 14280 sc->link_params.chip_id = 14281 (((REG_RD(sc, MISC_REG_CHIP_NUM) & 0xffff) << 16) | 14282 ((REG_RD(sc, MISC_REG_CHIP_REV) & 0xf) << 12) | 14283 (((REG_RD(sc, PCICFG_OFFSET + PCI_ID_VAL3) >> 24) & 0xf) << 4) | 14284 ((REG_RD(sc, MISC_REG_BOND_ID) & 0xf) << 0)); 14285 14286 /* force 57811 according to MISC register */ 14287 if (REG_RD(sc, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) { 14288 if (CHIP_IS_57810(sc)) { 14289 sc->devinfo.chip_id = ((CHIP_NUM_57811 << 16) | 14290 (sc->devinfo.chip_id & 0x0000ffff)); 14291 } else if (CHIP_IS_57810_MF(sc)) { 14292 sc->devinfo.chip_id = ((CHIP_NUM_57811_MF << 16) | 14293 (sc->devinfo.chip_id & 0x0000ffff)); 14294 } 14295 sc->devinfo.chip_id |= 0x1; 14296 } 14297 14298 BLOGD(sc, DBG_LOAD, 14299 "chip_id=0x%08x (num=0x%04x rev=0x%01x metal=0x%02x bond=0x%01x)\n", 14300 sc->devinfo.chip_id, 14301 ((sc->devinfo.chip_id >> 16) & 0xffff), 14302 ((sc->devinfo.chip_id >> 12) & 0xf), 14303 ((sc->devinfo.chip_id >> 4) & 0xff), 14304 ((sc->devinfo.chip_id >> 0) & 0xf)); 14305 14306 val = (REG_RD(sc, 0x2874) & 0x55); 14307 if ((sc->devinfo.chip_id & 0x1) || 14308 (CHIP_IS_E1(sc) && val) || 14309 (CHIP_IS_E1H(sc) && (val == 0x55))) { 14310 sc->flags |= BXE_ONE_PORT_FLAG; 14311 BLOGD(sc, DBG_LOAD, "single port device\n"); 14312 } 14313 14314 /* set the doorbell size */ 14315 sc->doorbell_size = (1 << BXE_DB_SHIFT); 14316 14317 /* determine whether the device is in 2 port or 4 port mode */ 14318 sc->devinfo.chip_port_mode = CHIP_PORT_MODE_NONE; /* E1 & E1h*/ 14319 if (CHIP_IS_E2E3(sc)) { 14320 /* 14321 * Read port4mode_en_ovwr[0]: 14322 * If 1, four port mode is in port4mode_en_ovwr[1]. 14323 * If 0, four port mode is in port4mode_en[0]. 14324 */ 14325 val = REG_RD(sc, MISC_REG_PORT4MODE_EN_OVWR); 14326 if (val & 1) { 14327 val = ((val >> 1) & 1); 14328 } else { 14329 val = REG_RD(sc, MISC_REG_PORT4MODE_EN); 14330 } 14331 14332 sc->devinfo.chip_port_mode = 14333 (val) ? CHIP_4_PORT_MODE : CHIP_2_PORT_MODE; 14334 14335 BLOGD(sc, DBG_LOAD, "Port mode = %s\n", (val) ? "4" : "2"); 14336 } 14337 14338 /* get the function and path info for the device */ 14339 bxe_get_function_num(sc); 14340 14341 /* get the shared memory base address */ 14342 sc->devinfo.shmem_base = 14343 sc->link_params.shmem_base = 14344 REG_RD(sc, MISC_REG_SHARED_MEM_ADDR); 14345 sc->devinfo.shmem2_base = 14346 REG_RD(sc, (SC_PATH(sc) ? MISC_REG_GENERIC_CR_1 : 14347 MISC_REG_GENERIC_CR_0)); 14348 14349 BLOGD(sc, DBG_LOAD, "shmem_base=0x%08x, shmem2_base=0x%08x\n", 14350 sc->devinfo.shmem_base, sc->devinfo.shmem2_base); 14351 14352 if (!sc->devinfo.shmem_base) { 14353 /* this should ONLY prevent upcoming shmem reads */ 14354 BLOGI(sc, "MCP not active\n"); 14355 sc->flags |= BXE_NO_MCP_FLAG; 14356 return (0); 14357 } 14358 14359 /* make sure the shared memory contents are valid */ 14360 val = SHMEM_RD(sc, validity_map[SC_PORT(sc)]); 14361 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) != 14362 (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) { 14363 BLOGE(sc, "Invalid SHMEM validity signature: 0x%08x\n", val); 14364 return (0); 14365 } 14366 BLOGD(sc, DBG_LOAD, "Valid SHMEM validity signature: 0x%08x\n", val); 14367 14368 /* get the bootcode version */ 14369 sc->devinfo.bc_ver = SHMEM_RD(sc, dev_info.bc_rev); 14370 snprintf(sc->devinfo.bc_ver_str, 14371 sizeof(sc->devinfo.bc_ver_str), 14372 "%d.%d.%d", 14373 ((sc->devinfo.bc_ver >> 24) & 0xff), 14374 ((sc->devinfo.bc_ver >> 16) & 0xff), 14375 ((sc->devinfo.bc_ver >> 8) & 0xff)); 14376 BLOGD(sc, DBG_LOAD, "Bootcode version: %s\n", sc->devinfo.bc_ver_str); 14377 14378 /* get the bootcode shmem address */ 14379 sc->devinfo.mf_cfg_base = bxe_get_shmem_mf_cfg_base(sc); 14380 BLOGD(sc, DBG_LOAD, "mf_cfg_base=0x08%x \n", sc->devinfo.mf_cfg_base); 14381 14382 /* clean indirect addresses as they're not used */ 14383 pci_write_config(sc->dev, PCICFG_GRC_ADDRESS, 0, 4); 14384 if (IS_PF(sc)) { 14385 REG_WR(sc, PXP2_REG_PGL_ADDR_88_F0, 0); 14386 REG_WR(sc, PXP2_REG_PGL_ADDR_8C_F0, 0); 14387 REG_WR(sc, PXP2_REG_PGL_ADDR_90_F0, 0); 14388 REG_WR(sc, PXP2_REG_PGL_ADDR_94_F0, 0); 14389 if (CHIP_IS_E1x(sc)) { 14390 REG_WR(sc, PXP2_REG_PGL_ADDR_88_F1, 0); 14391 REG_WR(sc, PXP2_REG_PGL_ADDR_8C_F1, 0); 14392 REG_WR(sc, PXP2_REG_PGL_ADDR_90_F1, 0); 14393 REG_WR(sc, PXP2_REG_PGL_ADDR_94_F1, 0); 14394 } 14395 14396 /* 14397 * Enable internal target-read (in case we are probed after PF 14398 * FLR). Must be done prior to any BAR read access. Only for 14399 * 57712 and up 14400 */ 14401 if (!CHIP_IS_E1x(sc)) { 14402 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1); 14403 } 14404 } 14405 14406 /* get the nvram size */ 14407 val = REG_RD(sc, MCP_REG_MCPR_NVM_CFG4); 14408 sc->devinfo.flash_size = 14409 (NVRAM_1MB_SIZE << (val & MCPR_NVM_CFG4_FLASH_SIZE)); 14410 BLOGD(sc, DBG_LOAD, "nvram flash size: %d\n", sc->devinfo.flash_size); 14411 14412 /* get PCI capabilites */ 14413 bxe_probe_pci_caps(sc); 14414 14415 bxe_set_power_state(sc, PCI_PM_D0); 14416 14417 /* get various configuration parameters from shmem */ 14418 bxe_get_shmem_info(sc); 14419 14420 if (sc->devinfo.pcie_msix_cap_reg != 0) { 14421 val = pci_read_config(sc->dev, 14422 (sc->devinfo.pcie_msix_cap_reg + 14423 PCIR_MSIX_CTRL), 14424 2); 14425 sc->igu_sb_cnt = (val & PCIM_MSIXCTRL_TABLE_SIZE); 14426 } else { 14427 sc->igu_sb_cnt = 1; 14428 } 14429 14430 sc->igu_base_addr = BAR_IGU_INTMEM; 14431 14432 /* initialize IGU parameters */ 14433 if (CHIP_IS_E1x(sc)) { 14434 sc->devinfo.int_block = INT_BLOCK_HC; 14435 sc->igu_dsb_id = DEF_SB_IGU_ID; 14436 sc->igu_base_sb = 0; 14437 } else { 14438 sc->devinfo.int_block = INT_BLOCK_IGU; 14439 14440 /* do not allow device reset during IGU info preocessing */ 14441 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RESET); 14442 14443 val = REG_RD(sc, IGU_REG_BLOCK_CONFIGURATION); 14444 14445 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) { 14446 int tout = 5000; 14447 14448 BLOGD(sc, DBG_LOAD, "FORCING IGU Normal Mode\n"); 14449 14450 val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN); 14451 REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION, val); 14452 REG_WR(sc, IGU_REG_RESET_MEMORIES, 0x7f); 14453 14454 while (tout && REG_RD(sc, IGU_REG_RESET_MEMORIES)) { 14455 tout--; 14456 DELAY(1000); 14457 } 14458 14459 if (REG_RD(sc, IGU_REG_RESET_MEMORIES)) { 14460 BLOGD(sc, DBG_LOAD, "FORCING IGU Normal Mode failed!!!\n"); 14461 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET); 14462 return (-1); 14463 } 14464 } 14465 14466 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) { 14467 BLOGD(sc, DBG_LOAD, "IGU Backward Compatible Mode\n"); 14468 sc->devinfo.int_block |= INT_BLOCK_MODE_BW_COMP; 14469 } else { 14470 BLOGD(sc, DBG_LOAD, "IGU Normal Mode\n"); 14471 } 14472 14473 rc = bxe_get_igu_cam_info(sc); 14474 14475 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET); 14476 14477 if (rc) { 14478 return (rc); 14479 } 14480 } 14481 14482 /* 14483 * Get base FW non-default (fast path) status block ID. This value is 14484 * used to initialize the fw_sb_id saved on the fp/queue structure to 14485 * determine the id used by the FW. 14486 */ 14487 if (CHIP_IS_E1x(sc)) { 14488 sc->base_fw_ndsb = ((SC_PORT(sc) * FP_SB_MAX_E1x) + SC_L_ID(sc)); 14489 } else { 14490 /* 14491 * 57712+ - We currently use one FW SB per IGU SB (Rx and Tx of 14492 * the same queue are indicated on the same IGU SB). So we prefer 14493 * FW and IGU SBs to be the same value. 14494 */ 14495 sc->base_fw_ndsb = sc->igu_base_sb; 14496 } 14497 14498 BLOGD(sc, DBG_LOAD, 14499 "igu_dsb_id=%d igu_base_sb=%d igu_sb_cnt=%d base_fw_ndsb=%d\n", 14500 sc->igu_dsb_id, sc->igu_base_sb, 14501 sc->igu_sb_cnt, sc->base_fw_ndsb); 14502 14503 elink_phy_probe(&sc->link_params); 14504 14505 return (0); 14506 } 14507 14508 static void 14509 bxe_link_settings_supported(struct bxe_softc *sc, 14510 uint32_t switch_cfg) 14511 { 14512 uint32_t cfg_size = 0; 14513 uint32_t idx; 14514 uint8_t port = SC_PORT(sc); 14515 14516 /* aggregation of supported attributes of all external phys */ 14517 sc->port.supported[0] = 0; 14518 sc->port.supported[1] = 0; 14519 14520 switch (sc->link_params.num_phys) { 14521 case 1: 14522 sc->port.supported[0] = sc->link_params.phy[ELINK_INT_PHY].supported; 14523 cfg_size = 1; 14524 break; 14525 case 2: 14526 sc->port.supported[0] = sc->link_params.phy[ELINK_EXT_PHY1].supported; 14527 cfg_size = 1; 14528 break; 14529 case 3: 14530 if (sc->link_params.multi_phy_config & 14531 PORT_HW_CFG_PHY_SWAPPED_ENABLED) { 14532 sc->port.supported[1] = 14533 sc->link_params.phy[ELINK_EXT_PHY1].supported; 14534 sc->port.supported[0] = 14535 sc->link_params.phy[ELINK_EXT_PHY2].supported; 14536 } else { 14537 sc->port.supported[0] = 14538 sc->link_params.phy[ELINK_EXT_PHY1].supported; 14539 sc->port.supported[1] = 14540 sc->link_params.phy[ELINK_EXT_PHY2].supported; 14541 } 14542 cfg_size = 2; 14543 break; 14544 } 14545 14546 if (!(sc->port.supported[0] || sc->port.supported[1])) { 14547 BLOGE(sc, "Invalid phy config in NVRAM (PHY1=0x%08x PHY2=0x%08x)\n", 14548 SHMEM_RD(sc, 14549 dev_info.port_hw_config[port].external_phy_config), 14550 SHMEM_RD(sc, 14551 dev_info.port_hw_config[port].external_phy_config2)); 14552 return; 14553 } 14554 14555 if (CHIP_IS_E3(sc)) 14556 sc->port.phy_addr = REG_RD(sc, MISC_REG_WC0_CTRL_PHY_ADDR); 14557 else { 14558 switch (switch_cfg) { 14559 case ELINK_SWITCH_CFG_1G: 14560 sc->port.phy_addr = 14561 REG_RD(sc, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10); 14562 break; 14563 case ELINK_SWITCH_CFG_10G: 14564 sc->port.phy_addr = 14565 REG_RD(sc, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18); 14566 break; 14567 default: 14568 BLOGE(sc, "Invalid switch config in link_config=0x%08x\n", 14569 sc->port.link_config[0]); 14570 return; 14571 } 14572 } 14573 14574 BLOGD(sc, DBG_LOAD, "PHY addr 0x%08x\n", sc->port.phy_addr); 14575 14576 /* mask what we support according to speed_cap_mask per configuration */ 14577 for (idx = 0; idx < cfg_size; idx++) { 14578 if (!(sc->link_params.speed_cap_mask[idx] & 14579 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) { 14580 sc->port.supported[idx] &= ~ELINK_SUPPORTED_10baseT_Half; 14581 } 14582 14583 if (!(sc->link_params.speed_cap_mask[idx] & 14584 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL)) { 14585 sc->port.supported[idx] &= ~ELINK_SUPPORTED_10baseT_Full; 14586 } 14587 14588 if (!(sc->link_params.speed_cap_mask[idx] & 14589 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)) { 14590 sc->port.supported[idx] &= ~ELINK_SUPPORTED_100baseT_Half; 14591 } 14592 14593 if (!(sc->link_params.speed_cap_mask[idx] & 14594 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL)) { 14595 sc->port.supported[idx] &= ~ELINK_SUPPORTED_100baseT_Full; 14596 } 14597 14598 if (!(sc->link_params.speed_cap_mask[idx] & 14599 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) { 14600 sc->port.supported[idx] &= ~ELINK_SUPPORTED_1000baseT_Full; 14601 } 14602 14603 if (!(sc->link_params.speed_cap_mask[idx] & 14604 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)) { 14605 sc->port.supported[idx] &= ~ELINK_SUPPORTED_2500baseX_Full; 14606 } 14607 14608 if (!(sc->link_params.speed_cap_mask[idx] & 14609 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) { 14610 sc->port.supported[idx] &= ~ELINK_SUPPORTED_10000baseT_Full; 14611 } 14612 14613 if (!(sc->link_params.speed_cap_mask[idx] & 14614 PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) { 14615 sc->port.supported[idx] &= ~ELINK_SUPPORTED_20000baseKR2_Full; 14616 } 14617 } 14618 14619 BLOGD(sc, DBG_LOAD, "PHY supported 0=0x%08x 1=0x%08x\n", 14620 sc->port.supported[0], sc->port.supported[1]); 14621 } 14622 14623 static void 14624 bxe_link_settings_requested(struct bxe_softc *sc) 14625 { 14626 uint32_t link_config; 14627 uint32_t idx; 14628 uint32_t cfg_size = 0; 14629 14630 sc->port.advertising[0] = 0; 14631 sc->port.advertising[1] = 0; 14632 14633 switch (sc->link_params.num_phys) { 14634 case 1: 14635 case 2: 14636 cfg_size = 1; 14637 break; 14638 case 3: 14639 cfg_size = 2; 14640 break; 14641 } 14642 14643 for (idx = 0; idx < cfg_size; idx++) { 14644 sc->link_params.req_duplex[idx] = DUPLEX_FULL; 14645 link_config = sc->port.link_config[idx]; 14646 14647 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) { 14648 case PORT_FEATURE_LINK_SPEED_AUTO: 14649 if (sc->port.supported[idx] & ELINK_SUPPORTED_Autoneg) { 14650 sc->link_params.req_line_speed[idx] = ELINK_SPEED_AUTO_NEG; 14651 sc->port.advertising[idx] |= sc->port.supported[idx]; 14652 if (sc->link_params.phy[ELINK_EXT_PHY1].type == 14653 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) 14654 sc->port.advertising[idx] |= 14655 (ELINK_SUPPORTED_100baseT_Half | 14656 ELINK_SUPPORTED_100baseT_Full); 14657 } else { 14658 /* force 10G, no AN */ 14659 sc->link_params.req_line_speed[idx] = ELINK_SPEED_10000; 14660 sc->port.advertising[idx] |= 14661 (ADVERTISED_10000baseT_Full | ADVERTISED_FIBRE); 14662 continue; 14663 } 14664 break; 14665 14666 case PORT_FEATURE_LINK_SPEED_10M_FULL: 14667 if (sc->port.supported[idx] & ELINK_SUPPORTED_10baseT_Full) { 14668 sc->link_params.req_line_speed[idx] = ELINK_SPEED_10; 14669 sc->port.advertising[idx] |= (ADVERTISED_10baseT_Full | 14670 ADVERTISED_TP); 14671 } else { 14672 BLOGE(sc, "Invalid NVRAM config link_config=0x%08x " 14673 "speed_cap_mask=0x%08x\n", 14674 link_config, sc->link_params.speed_cap_mask[idx]); 14675 return; 14676 } 14677 break; 14678 14679 case PORT_FEATURE_LINK_SPEED_10M_HALF: 14680 if (sc->port.supported[idx] & ELINK_SUPPORTED_10baseT_Half) { 14681 sc->link_params.req_line_speed[idx] = ELINK_SPEED_10; 14682 sc->link_params.req_duplex[idx] = DUPLEX_HALF; 14683 sc->port.advertising[idx] |= (ADVERTISED_10baseT_Half | 14684 ADVERTISED_TP); 14685 } else { 14686 BLOGE(sc, "Invalid NVRAM config link_config=0x%08x " 14687 "speed_cap_mask=0x%08x\n", 14688 link_config, sc->link_params.speed_cap_mask[idx]); 14689 return; 14690 } 14691 break; 14692 14693 case PORT_FEATURE_LINK_SPEED_100M_FULL: 14694 if (sc->port.supported[idx] & ELINK_SUPPORTED_100baseT_Full) { 14695 sc->link_params.req_line_speed[idx] = ELINK_SPEED_100; 14696 sc->port.advertising[idx] |= (ADVERTISED_100baseT_Full | 14697 ADVERTISED_TP); 14698 } else { 14699 BLOGE(sc, "Invalid NVRAM config link_config=0x%08x " 14700 "speed_cap_mask=0x%08x\n", 14701 link_config, sc->link_params.speed_cap_mask[idx]); 14702 return; 14703 } 14704 break; 14705 14706 case PORT_FEATURE_LINK_SPEED_100M_HALF: 14707 if (sc->port.supported[idx] & ELINK_SUPPORTED_100baseT_Half) { 14708 sc->link_params.req_line_speed[idx] = ELINK_SPEED_100; 14709 sc->link_params.req_duplex[idx] = DUPLEX_HALF; 14710 sc->port.advertising[idx] |= (ADVERTISED_100baseT_Half | 14711 ADVERTISED_TP); 14712 } else { 14713 BLOGE(sc, "Invalid NVRAM config link_config=0x%08x " 14714 "speed_cap_mask=0x%08x\n", 14715 link_config, sc->link_params.speed_cap_mask[idx]); 14716 return; 14717 } 14718 break; 14719 14720 case PORT_FEATURE_LINK_SPEED_1G: 14721 if (sc->port.supported[idx] & ELINK_SUPPORTED_1000baseT_Full) { 14722 sc->link_params.req_line_speed[idx] = ELINK_SPEED_1000; 14723 sc->port.advertising[idx] |= (ADVERTISED_1000baseT_Full | 14724 ADVERTISED_TP); 14725 } else { 14726 BLOGE(sc, "Invalid NVRAM config link_config=0x%08x " 14727 "speed_cap_mask=0x%08x\n", 14728 link_config, sc->link_params.speed_cap_mask[idx]); 14729 return; 14730 } 14731 break; 14732 14733 case PORT_FEATURE_LINK_SPEED_2_5G: 14734 if (sc->port.supported[idx] & ELINK_SUPPORTED_2500baseX_Full) { 14735 sc->link_params.req_line_speed[idx] = ELINK_SPEED_2500; 14736 sc->port.advertising[idx] |= (ADVERTISED_2500baseX_Full | 14737 ADVERTISED_TP); 14738 } else { 14739 BLOGE(sc, "Invalid NVRAM config link_config=0x%08x " 14740 "speed_cap_mask=0x%08x\n", 14741 link_config, sc->link_params.speed_cap_mask[idx]); 14742 return; 14743 } 14744 break; 14745 14746 case PORT_FEATURE_LINK_SPEED_10G_CX4: 14747 if (sc->port.supported[idx] & ELINK_SUPPORTED_10000baseT_Full) { 14748 sc->link_params.req_line_speed[idx] = ELINK_SPEED_10000; 14749 sc->port.advertising[idx] |= (ADVERTISED_10000baseT_Full | 14750 ADVERTISED_FIBRE); 14751 } else { 14752 BLOGE(sc, "Invalid NVRAM config link_config=0x%08x " 14753 "speed_cap_mask=0x%08x\n", 14754 link_config, sc->link_params.speed_cap_mask[idx]); 14755 return; 14756 } 14757 break; 14758 14759 case PORT_FEATURE_LINK_SPEED_20G: 14760 sc->link_params.req_line_speed[idx] = ELINK_SPEED_20000; 14761 break; 14762 14763 default: 14764 BLOGE(sc, "Invalid NVRAM config link_config=0x%08x " 14765 "speed_cap_mask=0x%08x\n", 14766 link_config, sc->link_params.speed_cap_mask[idx]); 14767 sc->link_params.req_line_speed[idx] = ELINK_SPEED_AUTO_NEG; 14768 sc->port.advertising[idx] = sc->port.supported[idx]; 14769 break; 14770 } 14771 14772 sc->link_params.req_flow_ctrl[idx] = 14773 (link_config & PORT_FEATURE_FLOW_CONTROL_MASK); 14774 14775 if (sc->link_params.req_flow_ctrl[idx] == ELINK_FLOW_CTRL_AUTO) { 14776 if (!(sc->port.supported[idx] & ELINK_SUPPORTED_Autoneg)) { 14777 sc->link_params.req_flow_ctrl[idx] = ELINK_FLOW_CTRL_NONE; 14778 } else { 14779 bxe_set_requested_fc(sc); 14780 } 14781 } 14782 14783 BLOGD(sc, DBG_LOAD, "req_line_speed=%d req_duplex=%d " 14784 "req_flow_ctrl=0x%x advertising=0x%x\n", 14785 sc->link_params.req_line_speed[idx], 14786 sc->link_params.req_duplex[idx], 14787 sc->link_params.req_flow_ctrl[idx], 14788 sc->port.advertising[idx]); 14789 } 14790 } 14791 14792 static void 14793 bxe_get_phy_info(struct bxe_softc *sc) 14794 { 14795 uint8_t port = SC_PORT(sc); 14796 uint32_t config = sc->port.config; 14797 uint32_t eee_mode; 14798 14799 /* shmem data already read in bxe_get_shmem_info() */ 14800 14801 BLOGD(sc, DBG_LOAD, "lane_config=0x%08x speed_cap_mask0=0x%08x " 14802 "link_config0=0x%08x\n", 14803 sc->link_params.lane_config, 14804 sc->link_params.speed_cap_mask[0], 14805 sc->port.link_config[0]); 14806 14807 bxe_link_settings_supported(sc, sc->link_params.switch_cfg); 14808 bxe_link_settings_requested(sc); 14809 14810 if (sc->autogreeen == AUTO_GREEN_FORCE_ON) { 14811 sc->link_params.feature_config_flags |= 14812 ELINK_FEATURE_CONFIG_AUTOGREEEN_ENABLED; 14813 } else if (sc->autogreeen == AUTO_GREEN_FORCE_OFF) { 14814 sc->link_params.feature_config_flags &= 14815 ~ELINK_FEATURE_CONFIG_AUTOGREEEN_ENABLED; 14816 } else if (config & PORT_FEAT_CFG_AUTOGREEEN_ENABLED) { 14817 sc->link_params.feature_config_flags |= 14818 ELINK_FEATURE_CONFIG_AUTOGREEEN_ENABLED; 14819 } 14820 14821 /* configure link feature according to nvram value */ 14822 eee_mode = 14823 (((SHMEM_RD(sc, dev_info.port_feature_config[port].eee_power_mode)) & 14824 PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >> 14825 PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT); 14826 if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) { 14827 sc->link_params.eee_mode = (ELINK_EEE_MODE_ADV_LPI | 14828 ELINK_EEE_MODE_ENABLE_LPI | 14829 ELINK_EEE_MODE_OUTPUT_TIME); 14830 } else { 14831 sc->link_params.eee_mode = 0; 14832 } 14833 14834 /* get the media type */ 14835 bxe_media_detect(sc); 14836 } 14837 14838 static void 14839 bxe_get_params(struct bxe_softc *sc) 14840 { 14841 /* get user tunable params */ 14842 bxe_get_tunable_params(sc); 14843 14844 /* select the RX and TX ring sizes */ 14845 sc->tx_ring_size = TX_BD_USABLE; 14846 sc->rx_ring_size = RX_BD_USABLE; 14847 14848 /* XXX disable WoL */ 14849 sc->wol = 0; 14850 } 14851 14852 static void 14853 bxe_set_modes_bitmap(struct bxe_softc *sc) 14854 { 14855 uint32_t flags = 0; 14856 14857 if (CHIP_REV_IS_FPGA(sc)) { 14858 SET_FLAGS(flags, MODE_FPGA); 14859 } else if (CHIP_REV_IS_EMUL(sc)) { 14860 SET_FLAGS(flags, MODE_EMUL); 14861 } else { 14862 SET_FLAGS(flags, MODE_ASIC); 14863 } 14864 14865 if (CHIP_IS_MODE_4_PORT(sc)) { 14866 SET_FLAGS(flags, MODE_PORT4); 14867 } else { 14868 SET_FLAGS(flags, MODE_PORT2); 14869 } 14870 14871 if (CHIP_IS_E2(sc)) { 14872 SET_FLAGS(flags, MODE_E2); 14873 } else if (CHIP_IS_E3(sc)) { 14874 SET_FLAGS(flags, MODE_E3); 14875 if (CHIP_REV(sc) == CHIP_REV_Ax) { 14876 SET_FLAGS(flags, MODE_E3_A0); 14877 } else /*if (CHIP_REV(sc) == CHIP_REV_Bx)*/ { 14878 SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3); 14879 } 14880 } 14881 14882 if (IS_MF(sc)) { 14883 SET_FLAGS(flags, MODE_MF); 14884 switch (sc->devinfo.mf_info.mf_mode) { 14885 case MULTI_FUNCTION_SD: 14886 SET_FLAGS(flags, MODE_MF_SD); 14887 break; 14888 case MULTI_FUNCTION_SI: 14889 SET_FLAGS(flags, MODE_MF_SI); 14890 break; 14891 case MULTI_FUNCTION_AFEX: 14892 SET_FLAGS(flags, MODE_MF_AFEX); 14893 break; 14894 } 14895 } else { 14896 SET_FLAGS(flags, MODE_SF); 14897 } 14898 14899 #if defined(__LITTLE_ENDIAN) 14900 SET_FLAGS(flags, MODE_LITTLE_ENDIAN); 14901 #else /* __BIG_ENDIAN */ 14902 SET_FLAGS(flags, MODE_BIG_ENDIAN); 14903 #endif 14904 14905 INIT_MODE_FLAGS(sc) = flags; 14906 } 14907 14908 static int 14909 bxe_alloc_hsi_mem(struct bxe_softc *sc) 14910 { 14911 struct bxe_fastpath *fp; 14912 bus_addr_t busaddr; 14913 int max_agg_queues; 14914 int max_segments; 14915 bus_size_t max_size; 14916 bus_size_t max_seg_size; 14917 char buf[32]; 14918 int rc; 14919 int i, j; 14920 14921 /* XXX zero out all vars here and call bxe_alloc_hsi_mem on error */ 14922 14923 /* allocate the parent bus DMA tag */ 14924 rc = bus_dma_tag_create(bus_get_dma_tag(sc->dev), /* parent tag */ 14925 1, /* alignment */ 14926 0, /* boundary limit */ 14927 BUS_SPACE_MAXADDR, /* restricted low */ 14928 BUS_SPACE_MAXADDR, /* restricted hi */ 14929 NULL, /* addr filter() */ 14930 NULL, /* addr filter() arg */ 14931 BUS_SPACE_MAXSIZE_32BIT, /* max map size */ 14932 BUS_SPACE_UNRESTRICTED, /* num discontinuous */ 14933 BUS_SPACE_MAXSIZE_32BIT, /* max seg size */ 14934 0, /* flags */ 14935 NULL, /* lock() */ 14936 NULL, /* lock() arg */ 14937 &sc->parent_dma_tag); /* returned dma tag */ 14938 if (rc != 0) { 14939 BLOGE(sc, "Failed to alloc parent DMA tag (%d)!\n", rc); 14940 return (1); 14941 } 14942 14943 /************************/ 14944 /* DEFAULT STATUS BLOCK */ 14945 /************************/ 14946 14947 if (bxe_dma_alloc(sc, sizeof(struct host_sp_status_block), 14948 &sc->def_sb_dma, "default status block") != 0) { 14949 /* XXX */ 14950 bus_dma_tag_destroy(sc->parent_dma_tag); 14951 return (1); 14952 } 14953 14954 sc->def_sb = (struct host_sp_status_block *)sc->def_sb_dma.vaddr; 14955 14956 /***************/ 14957 /* EVENT QUEUE */ 14958 /***************/ 14959 14960 if (bxe_dma_alloc(sc, BCM_PAGE_SIZE, 14961 &sc->eq_dma, "event queue") != 0) { 14962 /* XXX */ 14963 bxe_dma_free(sc, &sc->def_sb_dma); 14964 sc->def_sb = NULL; 14965 bus_dma_tag_destroy(sc->parent_dma_tag); 14966 return (1); 14967 } 14968 14969 sc->eq = (union event_ring_elem * )sc->eq_dma.vaddr; 14970 14971 /*************/ 14972 /* SLOW PATH */ 14973 /*************/ 14974 14975 if (bxe_dma_alloc(sc, sizeof(struct bxe_slowpath), 14976 &sc->sp_dma, "slow path") != 0) { 14977 /* XXX */ 14978 bxe_dma_free(sc, &sc->eq_dma); 14979 sc->eq = NULL; 14980 bxe_dma_free(sc, &sc->def_sb_dma); 14981 sc->def_sb = NULL; 14982 bus_dma_tag_destroy(sc->parent_dma_tag); 14983 return (1); 14984 } 14985 14986 sc->sp = (struct bxe_slowpath *)sc->sp_dma.vaddr; 14987 14988 /*******************/ 14989 /* SLOW PATH QUEUE */ 14990 /*******************/ 14991 14992 if (bxe_dma_alloc(sc, BCM_PAGE_SIZE, 14993 &sc->spq_dma, "slow path queue") != 0) { 14994 /* XXX */ 14995 bxe_dma_free(sc, &sc->sp_dma); 14996 sc->sp = NULL; 14997 bxe_dma_free(sc, &sc->eq_dma); 14998 sc->eq = NULL; 14999 bxe_dma_free(sc, &sc->def_sb_dma); 15000 sc->def_sb = NULL; 15001 bus_dma_tag_destroy(sc->parent_dma_tag); 15002 return (1); 15003 } 15004 15005 sc->spq = (struct eth_spe *)sc->spq_dma.vaddr; 15006 15007 /***************************/ 15008 /* FW DECOMPRESSION BUFFER */ 15009 /***************************/ 15010 15011 if (bxe_dma_alloc(sc, FW_BUF_SIZE, &sc->gz_buf_dma, 15012 "fw decompression buffer") != 0) { 15013 /* XXX */ 15014 bxe_dma_free(sc, &sc->spq_dma); 15015 sc->spq = NULL; 15016 bxe_dma_free(sc, &sc->sp_dma); 15017 sc->sp = NULL; 15018 bxe_dma_free(sc, &sc->eq_dma); 15019 sc->eq = NULL; 15020 bxe_dma_free(sc, &sc->def_sb_dma); 15021 sc->def_sb = NULL; 15022 bus_dma_tag_destroy(sc->parent_dma_tag); 15023 return (1); 15024 } 15025 15026 sc->gz_buf = (void *)sc->gz_buf_dma.vaddr; 15027 15028 if ((sc->gz_strm = 15029 malloc(sizeof(*sc->gz_strm), M_DEVBUF, M_NOWAIT)) == NULL) { 15030 /* XXX */ 15031 bxe_dma_free(sc, &sc->gz_buf_dma); 15032 sc->gz_buf = NULL; 15033 bxe_dma_free(sc, &sc->spq_dma); 15034 sc->spq = NULL; 15035 bxe_dma_free(sc, &sc->sp_dma); 15036 sc->sp = NULL; 15037 bxe_dma_free(sc, &sc->eq_dma); 15038 sc->eq = NULL; 15039 bxe_dma_free(sc, &sc->def_sb_dma); 15040 sc->def_sb = NULL; 15041 bus_dma_tag_destroy(sc->parent_dma_tag); 15042 return (1); 15043 } 15044 15045 /*************/ 15046 /* FASTPATHS */ 15047 /*************/ 15048 15049 /* allocate DMA memory for each fastpath structure */ 15050 for (i = 0; i < sc->num_queues; i++) { 15051 fp = &sc->fp[i]; 15052 fp->sc = sc; 15053 fp->index = i; 15054 15055 /*******************/ 15056 /* FP STATUS BLOCK */ 15057 /*******************/ 15058 15059 snprintf(buf, sizeof(buf), "fp %d status block", i); 15060 if (bxe_dma_alloc(sc, sizeof(union bxe_host_hc_status_block), 15061 &fp->sb_dma, buf) != 0) { 15062 /* XXX unwind and free previous fastpath allocations */ 15063 BLOGE(sc, "Failed to alloc %s\n", buf); 15064 return (1); 15065 } else { 15066 if (CHIP_IS_E2E3(sc)) { 15067 fp->status_block.e2_sb = 15068 (struct host_hc_status_block_e2 *)fp->sb_dma.vaddr; 15069 } else { 15070 fp->status_block.e1x_sb = 15071 (struct host_hc_status_block_e1x *)fp->sb_dma.vaddr; 15072 } 15073 } 15074 15075 /******************/ 15076 /* FP TX BD CHAIN */ 15077 /******************/ 15078 15079 snprintf(buf, sizeof(buf), "fp %d tx bd chain", i); 15080 if (bxe_dma_alloc(sc, (BCM_PAGE_SIZE * TX_BD_NUM_PAGES), 15081 &fp->tx_dma, buf) != 0) { 15082 /* XXX unwind and free previous fastpath allocations */ 15083 BLOGE(sc, "Failed to alloc %s\n", buf); 15084 return (1); 15085 } else { 15086 fp->tx_chain = (union eth_tx_bd_types *)fp->tx_dma.vaddr; 15087 } 15088 15089 /* link together the tx bd chain pages */ 15090 for (j = 1; j <= TX_BD_NUM_PAGES; j++) { 15091 /* index into the tx bd chain array to last entry per page */ 15092 struct eth_tx_next_bd *tx_next_bd = 15093 &fp->tx_chain[TX_BD_TOTAL_PER_PAGE * j - 1].next_bd; 15094 /* point to the next page and wrap from last page */ 15095 busaddr = (fp->tx_dma.paddr + 15096 (BCM_PAGE_SIZE * (j % TX_BD_NUM_PAGES))); 15097 tx_next_bd->addr_hi = htole32(U64_HI(busaddr)); 15098 tx_next_bd->addr_lo = htole32(U64_LO(busaddr)); 15099 } 15100 15101 /******************/ 15102 /* FP RX BD CHAIN */ 15103 /******************/ 15104 15105 snprintf(buf, sizeof(buf), "fp %d rx bd chain", i); 15106 if (bxe_dma_alloc(sc, (BCM_PAGE_SIZE * RX_BD_NUM_PAGES), 15107 &fp->rx_dma, buf) != 0) { 15108 /* XXX unwind and free previous fastpath allocations */ 15109 BLOGE(sc, "Failed to alloc %s\n", buf); 15110 return (1); 15111 } else { 15112 fp->rx_chain = (struct eth_rx_bd *)fp->rx_dma.vaddr; 15113 } 15114 15115 /* link together the rx bd chain pages */ 15116 for (j = 1; j <= RX_BD_NUM_PAGES; j++) { 15117 /* index into the rx bd chain array to last entry per page */ 15118 struct eth_rx_bd *rx_bd = 15119 &fp->rx_chain[RX_BD_TOTAL_PER_PAGE * j - 2]; 15120 /* point to the next page and wrap from last page */ 15121 busaddr = (fp->rx_dma.paddr + 15122 (BCM_PAGE_SIZE * (j % RX_BD_NUM_PAGES))); 15123 rx_bd->addr_hi = htole32(U64_HI(busaddr)); 15124 rx_bd->addr_lo = htole32(U64_LO(busaddr)); 15125 } 15126 15127 /*******************/ 15128 /* FP RX RCQ CHAIN */ 15129 /*******************/ 15130 15131 snprintf(buf, sizeof(buf), "fp %d rcq chain", i); 15132 if (bxe_dma_alloc(sc, (BCM_PAGE_SIZE * RCQ_NUM_PAGES), 15133 &fp->rcq_dma, buf) != 0) { 15134 /* XXX unwind and free previous fastpath allocations */ 15135 BLOGE(sc, "Failed to alloc %s\n", buf); 15136 return (1); 15137 } else { 15138 fp->rcq_chain = (union eth_rx_cqe *)fp->rcq_dma.vaddr; 15139 } 15140 15141 /* link together the rcq chain pages */ 15142 for (j = 1; j <= RCQ_NUM_PAGES; j++) { 15143 /* index into the rcq chain array to last entry per page */ 15144 struct eth_rx_cqe_next_page *rx_cqe_next = 15145 (struct eth_rx_cqe_next_page *) 15146 &fp->rcq_chain[RCQ_TOTAL_PER_PAGE * j - 1]; 15147 /* point to the next page and wrap from last page */ 15148 busaddr = (fp->rcq_dma.paddr + 15149 (BCM_PAGE_SIZE * (j % RCQ_NUM_PAGES))); 15150 rx_cqe_next->addr_hi = htole32(U64_HI(busaddr)); 15151 rx_cqe_next->addr_lo = htole32(U64_LO(busaddr)); 15152 } 15153 15154 /*******************/ 15155 /* FP RX SGE CHAIN */ 15156 /*******************/ 15157 15158 snprintf(buf, sizeof(buf), "fp %d sge chain", i); 15159 if (bxe_dma_alloc(sc, (BCM_PAGE_SIZE * RX_SGE_NUM_PAGES), 15160 &fp->rx_sge_dma, buf) != 0) { 15161 /* XXX unwind and free previous fastpath allocations */ 15162 BLOGE(sc, "Failed to alloc %s\n", buf); 15163 return (1); 15164 } else { 15165 fp->rx_sge_chain = (struct eth_rx_sge *)fp->rx_sge_dma.vaddr; 15166 } 15167 15168 /* link together the sge chain pages */ 15169 for (j = 1; j <= RX_SGE_NUM_PAGES; j++) { 15170 /* index into the rcq chain array to last entry per page */ 15171 struct eth_rx_sge *rx_sge = 15172 &fp->rx_sge_chain[RX_SGE_TOTAL_PER_PAGE * j - 2]; 15173 /* point to the next page and wrap from last page */ 15174 busaddr = (fp->rx_sge_dma.paddr + 15175 (BCM_PAGE_SIZE * (j % RX_SGE_NUM_PAGES))); 15176 rx_sge->addr_hi = htole32(U64_HI(busaddr)); 15177 rx_sge->addr_lo = htole32(U64_LO(busaddr)); 15178 } 15179 15180 /***********************/ 15181 /* FP TX MBUF DMA MAPS */ 15182 /***********************/ 15183 15184 /* set required sizes before mapping to conserve resources */ 15185 if (sc->ifnet->if_capenable & (IFCAP_TSO4 | IFCAP_TSO6)) { 15186 max_size = BXE_TSO_MAX_SIZE; 15187 max_segments = BXE_TSO_MAX_SEGMENTS; 15188 max_seg_size = BXE_TSO_MAX_SEG_SIZE; 15189 } else { 15190 max_size = (MCLBYTES * BXE_MAX_SEGMENTS); 15191 max_segments = BXE_MAX_SEGMENTS; 15192 max_seg_size = MCLBYTES; 15193 } 15194 15195 /* create a dma tag for the tx mbufs */ 15196 rc = bus_dma_tag_create(sc->parent_dma_tag, /* parent tag */ 15197 1, /* alignment */ 15198 0, /* boundary limit */ 15199 BUS_SPACE_MAXADDR, /* restricted low */ 15200 BUS_SPACE_MAXADDR, /* restricted hi */ 15201 NULL, /* addr filter() */ 15202 NULL, /* addr filter() arg */ 15203 max_size, /* max map size */ 15204 max_segments, /* num discontinuous */ 15205 max_seg_size, /* max seg size */ 15206 0, /* flags */ 15207 NULL, /* lock() */ 15208 NULL, /* lock() arg */ 15209 &fp->tx_mbuf_tag); /* returned dma tag */ 15210 if (rc != 0) { 15211 /* XXX unwind and free previous fastpath allocations */ 15212 BLOGE(sc, "Failed to create dma tag for " 15213 "'fp %d tx mbufs' (%d)\n", 15214 i, rc); 15215 return (1); 15216 } 15217 15218 /* create dma maps for each of the tx mbuf clusters */ 15219 for (j = 0; j < TX_BD_TOTAL; j++) { 15220 if (bus_dmamap_create(fp->tx_mbuf_tag, 15221 BUS_DMA_NOWAIT, 15222 &fp->tx_mbuf_chain[j].m_map)) { 15223 /* XXX unwind and free previous fastpath allocations */ 15224 BLOGE(sc, "Failed to create dma map for " 15225 "'fp %d tx mbuf %d' (%d)\n", 15226 i, j, rc); 15227 return (1); 15228 } 15229 } 15230 15231 /***********************/ 15232 /* FP RX MBUF DMA MAPS */ 15233 /***********************/ 15234 15235 /* create a dma tag for the rx mbufs */ 15236 rc = bus_dma_tag_create(sc->parent_dma_tag, /* parent tag */ 15237 1, /* alignment */ 15238 0, /* boundary limit */ 15239 BUS_SPACE_MAXADDR, /* restricted low */ 15240 BUS_SPACE_MAXADDR, /* restricted hi */ 15241 NULL, /* addr filter() */ 15242 NULL, /* addr filter() arg */ 15243 MJUM9BYTES, /* max map size */ 15244 1, /* num discontinuous */ 15245 MJUM9BYTES, /* max seg size */ 15246 0, /* flags */ 15247 NULL, /* lock() */ 15248 NULL, /* lock() arg */ 15249 &fp->rx_mbuf_tag); /* returned dma tag */ 15250 if (rc != 0) { 15251 /* XXX unwind and free previous fastpath allocations */ 15252 BLOGE(sc, "Failed to create dma tag for " 15253 "'fp %d rx mbufs' (%d)\n", 15254 i, rc); 15255 return (1); 15256 } 15257 15258 /* create dma maps for each of the rx mbuf clusters */ 15259 for (j = 0; j < RX_BD_TOTAL; j++) { 15260 if (bus_dmamap_create(fp->rx_mbuf_tag, 15261 BUS_DMA_NOWAIT, 15262 &fp->rx_mbuf_chain[j].m_map)) { 15263 /* XXX unwind and free previous fastpath allocations */ 15264 BLOGE(sc, "Failed to create dma map for " 15265 "'fp %d rx mbuf %d' (%d)\n", 15266 i, j, rc); 15267 return (1); 15268 } 15269 } 15270 15271 /* create dma map for the spare rx mbuf cluster */ 15272 if (bus_dmamap_create(fp->rx_mbuf_tag, 15273 BUS_DMA_NOWAIT, 15274 &fp->rx_mbuf_spare_map)) { 15275 /* XXX unwind and free previous fastpath allocations */ 15276 BLOGE(sc, "Failed to create dma map for " 15277 "'fp %d spare rx mbuf' (%d)\n", 15278 i, rc); 15279 return (1); 15280 } 15281 15282 /***************************/ 15283 /* FP RX SGE MBUF DMA MAPS */ 15284 /***************************/ 15285 15286 /* create a dma tag for the rx sge mbufs */ 15287 rc = bus_dma_tag_create(sc->parent_dma_tag, /* parent tag */ 15288 1, /* alignment */ 15289 0, /* boundary limit */ 15290 BUS_SPACE_MAXADDR, /* restricted low */ 15291 BUS_SPACE_MAXADDR, /* restricted hi */ 15292 NULL, /* addr filter() */ 15293 NULL, /* addr filter() arg */ 15294 BCM_PAGE_SIZE, /* max map size */ 15295 1, /* num discontinuous */ 15296 BCM_PAGE_SIZE, /* max seg size */ 15297 0, /* flags */ 15298 NULL, /* lock() */ 15299 NULL, /* lock() arg */ 15300 &fp->rx_sge_mbuf_tag); /* returned dma tag */ 15301 if (rc != 0) { 15302 /* XXX unwind and free previous fastpath allocations */ 15303 BLOGE(sc, "Failed to create dma tag for " 15304 "'fp %d rx sge mbufs' (%d)\n", 15305 i, rc); 15306 return (1); 15307 } 15308 15309 /* create dma maps for the rx sge mbuf clusters */ 15310 for (j = 0; j < RX_SGE_TOTAL; j++) { 15311 if (bus_dmamap_create(fp->rx_sge_mbuf_tag, 15312 BUS_DMA_NOWAIT, 15313 &fp->rx_sge_mbuf_chain[j].m_map)) { 15314 /* XXX unwind and free previous fastpath allocations */ 15315 BLOGE(sc, "Failed to create dma map for " 15316 "'fp %d rx sge mbuf %d' (%d)\n", 15317 i, j, rc); 15318 return (1); 15319 } 15320 } 15321 15322 /* create dma map for the spare rx sge mbuf cluster */ 15323 if (bus_dmamap_create(fp->rx_sge_mbuf_tag, 15324 BUS_DMA_NOWAIT, 15325 &fp->rx_sge_mbuf_spare_map)) { 15326 /* XXX unwind and free previous fastpath allocations */ 15327 BLOGE(sc, "Failed to create dma map for " 15328 "'fp %d spare rx sge mbuf' (%d)\n", 15329 i, rc); 15330 return (1); 15331 } 15332 15333 /***************************/ 15334 /* FP RX TPA MBUF DMA MAPS */ 15335 /***************************/ 15336 15337 /* create dma maps for the rx tpa mbuf clusters */ 15338 max_agg_queues = MAX_AGG_QS(sc); 15339 15340 for (j = 0; j < max_agg_queues; j++) { 15341 if (bus_dmamap_create(fp->rx_mbuf_tag, 15342 BUS_DMA_NOWAIT, 15343 &fp->rx_tpa_info[j].bd.m_map)) { 15344 /* XXX unwind and free previous fastpath allocations */ 15345 BLOGE(sc, "Failed to create dma map for " 15346 "'fp %d rx tpa mbuf %d' (%d)\n", 15347 i, j, rc); 15348 return (1); 15349 } 15350 } 15351 15352 /* create dma map for the spare rx tpa mbuf cluster */ 15353 if (bus_dmamap_create(fp->rx_mbuf_tag, 15354 BUS_DMA_NOWAIT, 15355 &fp->rx_tpa_info_mbuf_spare_map)) { 15356 /* XXX unwind and free previous fastpath allocations */ 15357 BLOGE(sc, "Failed to create dma map for " 15358 "'fp %d spare rx tpa mbuf' (%d)\n", 15359 i, rc); 15360 return (1); 15361 } 15362 15363 bxe_init_sge_ring_bit_mask(fp); 15364 } 15365 15366 return (0); 15367 } 15368 15369 static void 15370 bxe_free_hsi_mem(struct bxe_softc *sc) 15371 { 15372 struct bxe_fastpath *fp; 15373 int max_agg_queues; 15374 int i, j; 15375 15376 if (sc->parent_dma_tag == NULL) { 15377 return; /* assume nothing was allocated */ 15378 } 15379 15380 for (i = 0; i < sc->num_queues; i++) { 15381 fp = &sc->fp[i]; 15382 15383 /*******************/ 15384 /* FP STATUS BLOCK */ 15385 /*******************/ 15386 15387 bxe_dma_free(sc, &fp->sb_dma); 15388 memset(&fp->status_block, 0, sizeof(fp->status_block)); 15389 15390 /******************/ 15391 /* FP TX BD CHAIN */ 15392 /******************/ 15393 15394 bxe_dma_free(sc, &fp->tx_dma); 15395 fp->tx_chain = NULL; 15396 15397 /******************/ 15398 /* FP RX BD CHAIN */ 15399 /******************/ 15400 15401 bxe_dma_free(sc, &fp->rx_dma); 15402 fp->rx_chain = NULL; 15403 15404 /*******************/ 15405 /* FP RX RCQ CHAIN */ 15406 /*******************/ 15407 15408 bxe_dma_free(sc, &fp->rcq_dma); 15409 fp->rcq_chain = NULL; 15410 15411 /*******************/ 15412 /* FP RX SGE CHAIN */ 15413 /*******************/ 15414 15415 bxe_dma_free(sc, &fp->rx_sge_dma); 15416 fp->rx_sge_chain = NULL; 15417 15418 /***********************/ 15419 /* FP TX MBUF DMA MAPS */ 15420 /***********************/ 15421 15422 if (fp->tx_mbuf_tag != NULL) { 15423 for (j = 0; j < TX_BD_TOTAL; j++) { 15424 if (fp->tx_mbuf_chain[j].m_map != NULL) { 15425 bus_dmamap_unload(fp->tx_mbuf_tag, 15426 fp->tx_mbuf_chain[j].m_map); 15427 bus_dmamap_destroy(fp->tx_mbuf_tag, 15428 fp->tx_mbuf_chain[j].m_map); 15429 } 15430 } 15431 15432 bus_dma_tag_destroy(fp->tx_mbuf_tag); 15433 fp->tx_mbuf_tag = NULL; 15434 } 15435 15436 /***********************/ 15437 /* FP RX MBUF DMA MAPS */ 15438 /***********************/ 15439 15440 if (fp->rx_mbuf_tag != NULL) { 15441 for (j = 0; j < RX_BD_TOTAL; j++) { 15442 if (fp->rx_mbuf_chain[j].m_map != NULL) { 15443 bus_dmamap_unload(fp->rx_mbuf_tag, 15444 fp->rx_mbuf_chain[j].m_map); 15445 bus_dmamap_destroy(fp->rx_mbuf_tag, 15446 fp->rx_mbuf_chain[j].m_map); 15447 } 15448 } 15449 15450 if (fp->rx_mbuf_spare_map != NULL) { 15451 bus_dmamap_unload(fp->rx_mbuf_tag, fp->rx_mbuf_spare_map); 15452 bus_dmamap_destroy(fp->rx_mbuf_tag, fp->rx_mbuf_spare_map); 15453 } 15454 15455 /***************************/ 15456 /* FP RX TPA MBUF DMA MAPS */ 15457 /***************************/ 15458 15459 max_agg_queues = MAX_AGG_QS(sc); 15460 15461 for (j = 0; j < max_agg_queues; j++) { 15462 if (fp->rx_tpa_info[j].bd.m_map != NULL) { 15463 bus_dmamap_unload(fp->rx_mbuf_tag, 15464 fp->rx_tpa_info[j].bd.m_map); 15465 bus_dmamap_destroy(fp->rx_mbuf_tag, 15466 fp->rx_tpa_info[j].bd.m_map); 15467 } 15468 } 15469 15470 if (fp->rx_tpa_info_mbuf_spare_map != NULL) { 15471 bus_dmamap_unload(fp->rx_mbuf_tag, 15472 fp->rx_tpa_info_mbuf_spare_map); 15473 bus_dmamap_destroy(fp->rx_mbuf_tag, 15474 fp->rx_tpa_info_mbuf_spare_map); 15475 } 15476 15477 bus_dma_tag_destroy(fp->rx_mbuf_tag); 15478 fp->rx_mbuf_tag = NULL; 15479 } 15480 15481 /***************************/ 15482 /* FP RX SGE MBUF DMA MAPS */ 15483 /***************************/ 15484 15485 if (fp->rx_sge_mbuf_tag != NULL) { 15486 for (j = 0; j < RX_SGE_TOTAL; j++) { 15487 if (fp->rx_sge_mbuf_chain[j].m_map != NULL) { 15488 bus_dmamap_unload(fp->rx_sge_mbuf_tag, 15489 fp->rx_sge_mbuf_chain[j].m_map); 15490 bus_dmamap_destroy(fp->rx_sge_mbuf_tag, 15491 fp->rx_sge_mbuf_chain[j].m_map); 15492 } 15493 } 15494 15495 if (fp->rx_sge_mbuf_spare_map != NULL) { 15496 bus_dmamap_unload(fp->rx_sge_mbuf_tag, 15497 fp->rx_sge_mbuf_spare_map); 15498 bus_dmamap_destroy(fp->rx_sge_mbuf_tag, 15499 fp->rx_sge_mbuf_spare_map); 15500 } 15501 15502 bus_dma_tag_destroy(fp->rx_sge_mbuf_tag); 15503 fp->rx_sge_mbuf_tag = NULL; 15504 } 15505 } 15506 15507 /***************************/ 15508 /* FW DECOMPRESSION BUFFER */ 15509 /***************************/ 15510 15511 bxe_dma_free(sc, &sc->gz_buf_dma); 15512 sc->gz_buf = NULL; 15513 free(sc->gz_strm, M_DEVBUF); 15514 sc->gz_strm = NULL; 15515 15516 /*******************/ 15517 /* SLOW PATH QUEUE */ 15518 /*******************/ 15519 15520 bxe_dma_free(sc, &sc->spq_dma); 15521 sc->spq = NULL; 15522 15523 /*************/ 15524 /* SLOW PATH */ 15525 /*************/ 15526 15527 bxe_dma_free(sc, &sc->sp_dma); 15528 sc->sp = NULL; 15529 15530 /***************/ 15531 /* EVENT QUEUE */ 15532 /***************/ 15533 15534 bxe_dma_free(sc, &sc->eq_dma); 15535 sc->eq = NULL; 15536 15537 /************************/ 15538 /* DEFAULT STATUS BLOCK */ 15539 /************************/ 15540 15541 bxe_dma_free(sc, &sc->def_sb_dma); 15542 sc->def_sb = NULL; 15543 15544 bus_dma_tag_destroy(sc->parent_dma_tag); 15545 sc->parent_dma_tag = NULL; 15546 } 15547 15548 /* 15549 * Previous driver DMAE transaction may have occurred when pre-boot stage 15550 * ended and boot began. This would invalidate the addresses of the 15551 * transaction, resulting in was-error bit set in the PCI causing all 15552 * hw-to-host PCIe transactions to timeout. If this happened we want to clear 15553 * the interrupt which detected this from the pglueb and the was-done bit 15554 */ 15555 static void 15556 bxe_prev_interrupted_dmae(struct bxe_softc *sc) 15557 { 15558 uint32_t val; 15559 15560 if (!CHIP_IS_E1x(sc)) { 15561 val = REG_RD(sc, PGLUE_B_REG_PGLUE_B_INT_STS); 15562 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) { 15563 BLOGD(sc, DBG_LOAD, 15564 "Clearing 'was-error' bit that was set in pglueb"); 15565 REG_WR(sc, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, 1 << SC_FUNC(sc)); 15566 } 15567 } 15568 } 15569 15570 static int 15571 bxe_prev_mcp_done(struct bxe_softc *sc) 15572 { 15573 uint32_t rc = bxe_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, 15574 DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET); 15575 if (!rc) { 15576 BLOGE(sc, "MCP response failure, aborting\n"); 15577 return (-1); 15578 } 15579 15580 return (0); 15581 } 15582 15583 static struct bxe_prev_list_node * 15584 bxe_prev_path_get_entry(struct bxe_softc *sc) 15585 { 15586 struct bxe_prev_list_node *tmp; 15587 15588 LIST_FOREACH(tmp, &bxe_prev_list, node) { 15589 if ((sc->pcie_bus == tmp->bus) && 15590 (sc->pcie_device == tmp->slot) && 15591 (SC_PATH(sc) == tmp->path)) { 15592 return (tmp); 15593 } 15594 } 15595 15596 return (NULL); 15597 } 15598 15599 static uint8_t 15600 bxe_prev_is_path_marked(struct bxe_softc *sc) 15601 { 15602 struct bxe_prev_list_node *tmp; 15603 int rc = FALSE; 15604 15605 mtx_lock(&bxe_prev_mtx); 15606 15607 tmp = bxe_prev_path_get_entry(sc); 15608 if (tmp) { 15609 if (tmp->aer) { 15610 BLOGD(sc, DBG_LOAD, 15611 "Path %d/%d/%d was marked by AER\n", 15612 sc->pcie_bus, sc->pcie_device, SC_PATH(sc)); 15613 } else { 15614 rc = TRUE; 15615 BLOGD(sc, DBG_LOAD, 15616 "Path %d/%d/%d was already cleaned from previous drivers\n", 15617 sc->pcie_bus, sc->pcie_device, SC_PATH(sc)); 15618 } 15619 } 15620 15621 mtx_unlock(&bxe_prev_mtx); 15622 15623 return (rc); 15624 } 15625 15626 static int 15627 bxe_prev_mark_path(struct bxe_softc *sc, 15628 uint8_t after_undi) 15629 { 15630 struct bxe_prev_list_node *tmp; 15631 15632 mtx_lock(&bxe_prev_mtx); 15633 15634 /* Check whether the entry for this path already exists */ 15635 tmp = bxe_prev_path_get_entry(sc); 15636 if (tmp) { 15637 if (!tmp->aer) { 15638 BLOGD(sc, DBG_LOAD, 15639 "Re-marking AER in path %d/%d/%d\n", 15640 sc->pcie_bus, sc->pcie_device, SC_PATH(sc)); 15641 } else { 15642 BLOGD(sc, DBG_LOAD, 15643 "Removing AER indication from path %d/%d/%d\n", 15644 sc->pcie_bus, sc->pcie_device, SC_PATH(sc)); 15645 tmp->aer = 0; 15646 } 15647 15648 mtx_unlock(&bxe_prev_mtx); 15649 return (0); 15650 } 15651 15652 mtx_unlock(&bxe_prev_mtx); 15653 15654 /* Create an entry for this path and add it */ 15655 tmp = malloc(sizeof(struct bxe_prev_list_node), M_DEVBUF, 15656 (M_NOWAIT | M_ZERO)); 15657 if (!tmp) { 15658 BLOGE(sc, "Failed to allocate 'bxe_prev_list_node'\n"); 15659 return (-1); 15660 } 15661 15662 tmp->bus = sc->pcie_bus; 15663 tmp->slot = sc->pcie_device; 15664 tmp->path = SC_PATH(sc); 15665 tmp->aer = 0; 15666 tmp->undi = after_undi ? (1 << SC_PORT(sc)) : 0; 15667 15668 mtx_lock(&bxe_prev_mtx); 15669 15670 BLOGD(sc, DBG_LOAD, 15671 "Marked path %d/%d/%d - finished previous unload\n", 15672 sc->pcie_bus, sc->pcie_device, SC_PATH(sc)); 15673 LIST_INSERT_HEAD(&bxe_prev_list, tmp, node); 15674 15675 mtx_unlock(&bxe_prev_mtx); 15676 15677 return (0); 15678 } 15679 15680 static int 15681 bxe_do_flr(struct bxe_softc *sc) 15682 { 15683 int i; 15684 15685 /* only E2 and onwards support FLR */ 15686 if (CHIP_IS_E1x(sc)) { 15687 BLOGD(sc, DBG_LOAD, "FLR not supported in E1/E1H\n"); 15688 return (-1); 15689 } 15690 15691 /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */ 15692 if (sc->devinfo.bc_ver < REQ_BC_VER_4_INITIATE_FLR) { 15693 BLOGD(sc, DBG_LOAD, "FLR not supported by BC_VER: 0x%08x\n", 15694 sc->devinfo.bc_ver); 15695 return (-1); 15696 } 15697 15698 /* Wait for Transaction Pending bit clean */ 15699 for (i = 0; i < 4; i++) { 15700 if (i) { 15701 DELAY(((1 << (i - 1)) * 100) * 1000); 15702 } 15703 15704 if (!bxe_is_pcie_pending(sc)) { 15705 goto clear; 15706 } 15707 } 15708 15709 BLOGE(sc, "PCIE transaction is not cleared, " 15710 "proceeding with reset anyway\n"); 15711 15712 clear: 15713 15714 BLOGD(sc, DBG_LOAD, "Initiating FLR\n"); 15715 bxe_fw_command(sc, DRV_MSG_CODE_INITIATE_FLR, 0); 15716 15717 return (0); 15718 } 15719 15720 struct bxe_mac_vals { 15721 uint32_t xmac_addr; 15722 uint32_t xmac_val; 15723 uint32_t emac_addr; 15724 uint32_t emac_val; 15725 uint32_t umac_addr; 15726 uint32_t umac_val; 15727 uint32_t bmac_addr; 15728 uint32_t bmac_val[2]; 15729 }; 15730 15731 static void 15732 bxe_prev_unload_close_mac(struct bxe_softc *sc, 15733 struct bxe_mac_vals *vals) 15734 { 15735 uint32_t val, base_addr, offset, mask, reset_reg; 15736 uint8_t mac_stopped = FALSE; 15737 uint8_t port = SC_PORT(sc); 15738 uint32_t wb_data[2]; 15739 15740 /* reset addresses as they also mark which values were changed */ 15741 vals->bmac_addr = 0; 15742 vals->umac_addr = 0; 15743 vals->xmac_addr = 0; 15744 vals->emac_addr = 0; 15745 15746 reset_reg = REG_RD(sc, MISC_REG_RESET_REG_2); 15747 15748 if (!CHIP_IS_E3(sc)) { 15749 val = REG_RD(sc, NIG_REG_BMAC0_REGS_OUT_EN + port * 4); 15750 mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port; 15751 if ((mask & reset_reg) && val) { 15752 BLOGD(sc, DBG_LOAD, "Disable BMAC Rx\n"); 15753 base_addr = SC_PORT(sc) ? NIG_REG_INGRESS_BMAC1_MEM 15754 : NIG_REG_INGRESS_BMAC0_MEM; 15755 offset = CHIP_IS_E2(sc) ? BIGMAC2_REGISTER_BMAC_CONTROL 15756 : BIGMAC_REGISTER_BMAC_CONTROL; 15757 15758 /* 15759 * use rd/wr since we cannot use dmae. This is safe 15760 * since MCP won't access the bus due to the request 15761 * to unload, and no function on the path can be 15762 * loaded at this time. 15763 */ 15764 wb_data[0] = REG_RD(sc, base_addr + offset); 15765 wb_data[1] = REG_RD(sc, base_addr + offset + 0x4); 15766 vals->bmac_addr = base_addr + offset; 15767 vals->bmac_val[0] = wb_data[0]; 15768 vals->bmac_val[1] = wb_data[1]; 15769 wb_data[0] &= ~ELINK_BMAC_CONTROL_RX_ENABLE; 15770 REG_WR(sc, vals->bmac_addr, wb_data[0]); 15771 REG_WR(sc, vals->bmac_addr + 0x4, wb_data[1]); 15772 } 15773 15774 BLOGD(sc, DBG_LOAD, "Disable EMAC Rx\n"); 15775 vals->emac_addr = NIG_REG_NIG_EMAC0_EN + SC_PORT(sc)*4; 15776 vals->emac_val = REG_RD(sc, vals->emac_addr); 15777 REG_WR(sc, vals->emac_addr, 0); 15778 mac_stopped = TRUE; 15779 } else { 15780 if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) { 15781 BLOGD(sc, DBG_LOAD, "Disable XMAC Rx\n"); 15782 base_addr = SC_PORT(sc) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; 15783 val = REG_RD(sc, base_addr + XMAC_REG_PFC_CTRL_HI); 15784 REG_WR(sc, base_addr + XMAC_REG_PFC_CTRL_HI, val & ~(1 << 1)); 15785 REG_WR(sc, base_addr + XMAC_REG_PFC_CTRL_HI, val | (1 << 1)); 15786 vals->xmac_addr = base_addr + XMAC_REG_CTRL; 15787 vals->xmac_val = REG_RD(sc, vals->xmac_addr); 15788 REG_WR(sc, vals->xmac_addr, 0); 15789 mac_stopped = TRUE; 15790 } 15791 15792 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port; 15793 if (mask & reset_reg) { 15794 BLOGD(sc, DBG_LOAD, "Disable UMAC Rx\n"); 15795 base_addr = SC_PORT(sc) ? GRCBASE_UMAC1 : GRCBASE_UMAC0; 15796 vals->umac_addr = base_addr + UMAC_REG_COMMAND_CONFIG; 15797 vals->umac_val = REG_RD(sc, vals->umac_addr); 15798 REG_WR(sc, vals->umac_addr, 0); 15799 mac_stopped = TRUE; 15800 } 15801 } 15802 15803 if (mac_stopped) { 15804 DELAY(20000); 15805 } 15806 } 15807 15808 #define BXE_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4)) 15809 #define BXE_PREV_UNDI_RCQ(val) ((val) & 0xffff) 15810 #define BXE_PREV_UNDI_BD(val) ((val) >> 16 & 0xffff) 15811 #define BXE_PREV_UNDI_PROD(rcq, bd) ((bd) << 16 | (rcq)) 15812 15813 static void 15814 bxe_prev_unload_undi_inc(struct bxe_softc *sc, 15815 uint8_t port, 15816 uint8_t inc) 15817 { 15818 uint16_t rcq, bd; 15819 uint32_t tmp_reg = REG_RD(sc, BXE_PREV_UNDI_PROD_ADDR(port)); 15820 15821 rcq = BXE_PREV_UNDI_RCQ(tmp_reg) + inc; 15822 bd = BXE_PREV_UNDI_BD(tmp_reg) + inc; 15823 15824 tmp_reg = BXE_PREV_UNDI_PROD(rcq, bd); 15825 REG_WR(sc, BXE_PREV_UNDI_PROD_ADDR(port), tmp_reg); 15826 15827 BLOGD(sc, DBG_LOAD, 15828 "UNDI producer [%d] rings bd -> 0x%04x, rcq -> 0x%04x\n", 15829 port, bd, rcq); 15830 } 15831 15832 static int 15833 bxe_prev_unload_common(struct bxe_softc *sc) 15834 { 15835 uint32_t reset_reg, tmp_reg = 0, rc; 15836 uint8_t prev_undi = FALSE; 15837 struct bxe_mac_vals mac_vals; 15838 uint32_t timer_count = 1000; 15839 uint32_t prev_brb; 15840 15841 /* 15842 * It is possible a previous function received 'common' answer, 15843 * but hasn't loaded yet, therefore creating a scenario of 15844 * multiple functions receiving 'common' on the same path. 15845 */ 15846 BLOGD(sc, DBG_LOAD, "Common unload Flow\n"); 15847 15848 memset(&mac_vals, 0, sizeof(mac_vals)); 15849 15850 if (bxe_prev_is_path_marked(sc)) { 15851 return (bxe_prev_mcp_done(sc)); 15852 } 15853 15854 reset_reg = REG_RD(sc, MISC_REG_RESET_REG_1); 15855 15856 /* Reset should be performed after BRB is emptied */ 15857 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) { 15858 /* Close the MAC Rx to prevent BRB from filling up */ 15859 bxe_prev_unload_close_mac(sc, &mac_vals); 15860 15861 /* close LLH filters towards the BRB */ 15862 elink_set_rx_filter(&sc->link_params, 0); 15863 15864 /* 15865 * Check if the UNDI driver was previously loaded. 15866 * UNDI driver initializes CID offset for normal bell to 0x7 15867 */ 15868 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_DORQ) { 15869 tmp_reg = REG_RD(sc, DORQ_REG_NORM_CID_OFST); 15870 if (tmp_reg == 0x7) { 15871 BLOGD(sc, DBG_LOAD, "UNDI previously loaded\n"); 15872 prev_undi = TRUE; 15873 /* clear the UNDI indication */ 15874 REG_WR(sc, DORQ_REG_NORM_CID_OFST, 0); 15875 /* clear possible idle check errors */ 15876 REG_RD(sc, NIG_REG_NIG_INT_STS_CLR_0); 15877 } 15878 } 15879 15880 /* wait until BRB is empty */ 15881 tmp_reg = REG_RD(sc, BRB1_REG_NUM_OF_FULL_BLOCKS); 15882 while (timer_count) { 15883 prev_brb = tmp_reg; 15884 15885 tmp_reg = REG_RD(sc, BRB1_REG_NUM_OF_FULL_BLOCKS); 15886 if (!tmp_reg) { 15887 break; 15888 } 15889 15890 BLOGD(sc, DBG_LOAD, "BRB still has 0x%08x\n", tmp_reg); 15891 15892 /* reset timer as long as BRB actually gets emptied */ 15893 if (prev_brb > tmp_reg) { 15894 timer_count = 1000; 15895 } else { 15896 timer_count--; 15897 } 15898 15899 /* If UNDI resides in memory, manually increment it */ 15900 if (prev_undi) { 15901 bxe_prev_unload_undi_inc(sc, SC_PORT(sc), 1); 15902 } 15903 15904 DELAY(10); 15905 } 15906 15907 if (!timer_count) { 15908 BLOGE(sc, "Failed to empty BRB\n"); 15909 } 15910 } 15911 15912 /* No packets are in the pipeline, path is ready for reset */ 15913 bxe_reset_common(sc); 15914 15915 if (mac_vals.xmac_addr) { 15916 REG_WR(sc, mac_vals.xmac_addr, mac_vals.xmac_val); 15917 } 15918 if (mac_vals.umac_addr) { 15919 REG_WR(sc, mac_vals.umac_addr, mac_vals.umac_val); 15920 } 15921 if (mac_vals.emac_addr) { 15922 REG_WR(sc, mac_vals.emac_addr, mac_vals.emac_val); 15923 } 15924 if (mac_vals.bmac_addr) { 15925 REG_WR(sc, mac_vals.bmac_addr, mac_vals.bmac_val[0]); 15926 REG_WR(sc, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]); 15927 } 15928 15929 rc = bxe_prev_mark_path(sc, prev_undi); 15930 if (rc) { 15931 bxe_prev_mcp_done(sc); 15932 return (rc); 15933 } 15934 15935 return (bxe_prev_mcp_done(sc)); 15936 } 15937 15938 static int 15939 bxe_prev_unload_uncommon(struct bxe_softc *sc) 15940 { 15941 int rc; 15942 15943 BLOGD(sc, DBG_LOAD, "Uncommon unload Flow\n"); 15944 15945 /* Test if previous unload process was already finished for this path */ 15946 if (bxe_prev_is_path_marked(sc)) { 15947 return (bxe_prev_mcp_done(sc)); 15948 } 15949 15950 BLOGD(sc, DBG_LOAD, "Path is unmarked\n"); 15951 15952 /* 15953 * If function has FLR capabilities, and existing FW version matches 15954 * the one required, then FLR will be sufficient to clean any residue 15955 * left by previous driver 15956 */ 15957 rc = bxe_nic_load_analyze_req(sc, FW_MSG_CODE_DRV_LOAD_FUNCTION); 15958 if (!rc) { 15959 /* fw version is good */ 15960 BLOGD(sc, DBG_LOAD, "FW version matches our own, attempting FLR\n"); 15961 rc = bxe_do_flr(sc); 15962 } 15963 15964 if (!rc) { 15965 /* FLR was performed */ 15966 BLOGD(sc, DBG_LOAD, "FLR successful\n"); 15967 return (0); 15968 } 15969 15970 BLOGD(sc, DBG_LOAD, "Could not FLR\n"); 15971 15972 /* Close the MCP request, return failure*/ 15973 rc = bxe_prev_mcp_done(sc); 15974 if (!rc) { 15975 rc = BXE_PREV_WAIT_NEEDED; 15976 } 15977 15978 return (rc); 15979 } 15980 15981 static int 15982 bxe_prev_unload(struct bxe_softc *sc) 15983 { 15984 int time_counter = 10; 15985 uint32_t fw, hw_lock_reg, hw_lock_val; 15986 uint32_t rc = 0; 15987 15988 /* 15989 * Clear HW from errors which may have resulted from an interrupted 15990 * DMAE transaction. 15991 */ 15992 bxe_prev_interrupted_dmae(sc); 15993 15994 /* Release previously held locks */ 15995 hw_lock_reg = 15996 (SC_FUNC(sc) <= 5) ? 15997 (MISC_REG_DRIVER_CONTROL_1 + SC_FUNC(sc) * 8) : 15998 (MISC_REG_DRIVER_CONTROL_7 + (SC_FUNC(sc) - 6) * 8); 15999 16000 hw_lock_val = (REG_RD(sc, hw_lock_reg)); 16001 if (hw_lock_val) { 16002 if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) { 16003 BLOGD(sc, DBG_LOAD, "Releasing previously held NVRAM lock\n"); 16004 REG_WR(sc, MCP_REG_MCPR_NVM_SW_ARB, 16005 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << SC_PORT(sc))); 16006 } 16007 BLOGD(sc, DBG_LOAD, "Releasing previously held HW lock\n"); 16008 REG_WR(sc, hw_lock_reg, 0xffffffff); 16009 } else { 16010 BLOGD(sc, DBG_LOAD, "No need to release HW/NVRAM locks\n"); 16011 } 16012 16013 if (MCPR_ACCESS_LOCK_LOCK & REG_RD(sc, MCP_REG_MCPR_ACCESS_LOCK)) { 16014 BLOGD(sc, DBG_LOAD, "Releasing previously held ALR\n"); 16015 REG_WR(sc, MCP_REG_MCPR_ACCESS_LOCK, 0); 16016 } 16017 16018 do { 16019 /* Lock MCP using an unload request */ 16020 fw = bxe_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0); 16021 if (!fw) { 16022 BLOGE(sc, "MCP response failure, aborting\n"); 16023 rc = -1; 16024 break; 16025 } 16026 16027 if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON) { 16028 rc = bxe_prev_unload_common(sc); 16029 break; 16030 } 16031 16032 /* non-common reply from MCP night require looping */ 16033 rc = bxe_prev_unload_uncommon(sc); 16034 if (rc != BXE_PREV_WAIT_NEEDED) { 16035 break; 16036 } 16037 16038 DELAY(20000); 16039 } while (--time_counter); 16040 16041 if (!time_counter || rc) { 16042 BLOGE(sc, "Failed to unload previous driver!\n"); 16043 rc = -1; 16044 } 16045 16046 return (rc); 16047 } 16048 16049 void 16050 bxe_dcbx_set_state(struct bxe_softc *sc, 16051 uint8_t dcb_on, 16052 uint32_t dcbx_enabled) 16053 { 16054 if (!CHIP_IS_E1x(sc)) { 16055 sc->dcb_state = dcb_on; 16056 sc->dcbx_enabled = dcbx_enabled; 16057 } else { 16058 sc->dcb_state = FALSE; 16059 sc->dcbx_enabled = BXE_DCBX_ENABLED_INVALID; 16060 } 16061 BLOGD(sc, DBG_LOAD, 16062 "DCB state [%s:%s]\n", 16063 dcb_on ? "ON" : "OFF", 16064 (dcbx_enabled == BXE_DCBX_ENABLED_OFF) ? "user-mode" : 16065 (dcbx_enabled == BXE_DCBX_ENABLED_ON_NEG_OFF) ? "on-chip static" : 16066 (dcbx_enabled == BXE_DCBX_ENABLED_ON_NEG_ON) ? 16067 "on-chip with negotiation" : "invalid"); 16068 } 16069 16070 /* must be called after sriov-enable */ 16071 static int 16072 bxe_set_qm_cid_count(struct bxe_softc *sc) 16073 { 16074 int cid_count = BXE_L2_MAX_CID(sc); 16075 16076 if (IS_SRIOV(sc)) { 16077 cid_count += BXE_VF_CIDS; 16078 } 16079 16080 if (CNIC_SUPPORT(sc)) { 16081 cid_count += CNIC_CID_MAX; 16082 } 16083 16084 return (roundup(cid_count, QM_CID_ROUND)); 16085 } 16086 16087 static void 16088 bxe_init_multi_cos(struct bxe_softc *sc) 16089 { 16090 int pri, cos; 16091 16092 uint32_t pri_map = 0; /* XXX change to user config */ 16093 16094 for (pri = 0; pri < BXE_MAX_PRIORITY; pri++) { 16095 cos = ((pri_map & (0xf << (pri * 4))) >> (pri * 4)); 16096 if (cos < sc->max_cos) { 16097 sc->prio_to_cos[pri] = cos; 16098 } else { 16099 BLOGW(sc, "Invalid COS %d for priority %d " 16100 "(max COS is %d), setting to 0\n", 16101 cos, pri, (sc->max_cos - 1)); 16102 sc->prio_to_cos[pri] = 0; 16103 } 16104 } 16105 } 16106 16107 static int 16108 bxe_sysctl_state(SYSCTL_HANDLER_ARGS) 16109 { 16110 struct bxe_softc *sc; 16111 int error, result; 16112 16113 result = 0; 16114 error = sysctl_handle_int(oidp, &result, 0, req); 16115 16116 if (error || !req->newptr) { 16117 return (error); 16118 } 16119 16120 if (result == 1) { 16121 sc = (struct bxe_softc *)arg1; 16122 BLOGI(sc, "... dumping driver state ...\n"); 16123 /* XXX */ 16124 } 16125 16126 return (error); 16127 } 16128 16129 static int 16130 bxe_sysctl_eth_stat(SYSCTL_HANDLER_ARGS) 16131 { 16132 struct bxe_softc *sc = (struct bxe_softc *)arg1; 16133 uint32_t *eth_stats = (uint32_t *)&sc->eth_stats; 16134 uint32_t *offset; 16135 uint64_t value = 0; 16136 int index = (int)arg2; 16137 16138 if (index >= BXE_NUM_ETH_STATS) { 16139 BLOGE(sc, "bxe_eth_stats index out of range (%d)\n", index); 16140 return (-1); 16141 } 16142 16143 offset = (eth_stats + bxe_eth_stats_arr[index].offset); 16144 16145 switch (bxe_eth_stats_arr[index].size) { 16146 case 4: 16147 value = (uint64_t)*offset; 16148 break; 16149 case 8: 16150 value = HILO_U64(*offset, *(offset + 1)); 16151 break; 16152 default: 16153 BLOGE(sc, "Invalid bxe_eth_stats size (index=%d size=%d)\n", 16154 index, bxe_eth_stats_arr[index].size); 16155 return (-1); 16156 } 16157 16158 return (sysctl_handle_64(oidp, &value, 0, req)); 16159 } 16160 16161 static int 16162 bxe_sysctl_eth_q_stat(SYSCTL_HANDLER_ARGS) 16163 { 16164 struct bxe_softc *sc = (struct bxe_softc *)arg1; 16165 uint32_t *eth_stats; 16166 uint32_t *offset; 16167 uint64_t value = 0; 16168 uint32_t q_stat = (uint32_t)arg2; 16169 uint32_t fp_index = ((q_stat >> 16) & 0xffff); 16170 uint32_t index = (q_stat & 0xffff); 16171 16172 eth_stats = (uint32_t *)&sc->fp[fp_index].eth_q_stats; 16173 16174 if (index >= BXE_NUM_ETH_Q_STATS) { 16175 BLOGE(sc, "bxe_eth_q_stats index out of range (%d)\n", index); 16176 return (-1); 16177 } 16178 16179 offset = (eth_stats + bxe_eth_q_stats_arr[index].offset); 16180 16181 switch (bxe_eth_q_stats_arr[index].size) { 16182 case 4: 16183 value = (uint64_t)*offset; 16184 break; 16185 case 8: 16186 value = HILO_U64(*offset, *(offset + 1)); 16187 break; 16188 default: 16189 BLOGE(sc, "Invalid bxe_eth_q_stats size (index=%d size=%d)\n", 16190 index, bxe_eth_q_stats_arr[index].size); 16191 return (-1); 16192 } 16193 16194 return (sysctl_handle_64(oidp, &value, 0, req)); 16195 } 16196 16197 static void 16198 bxe_add_sysctls(struct bxe_softc *sc) 16199 { 16200 struct sysctl_ctx_list *ctx; 16201 struct sysctl_oid_list *children; 16202 struct sysctl_oid *queue_top, *queue; 16203 struct sysctl_oid_list *queue_top_children, *queue_children; 16204 char queue_num_buf[32]; 16205 uint32_t q_stat; 16206 int i, j; 16207 16208 ctx = device_get_sysctl_ctx(sc->dev); 16209 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)); 16210 16211 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "version", 16212 CTLFLAG_RD, BXE_DRIVER_VERSION, 0, 16213 "version"); 16214 16215 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "bc_version", 16216 CTLFLAG_RD, &sc->devinfo.bc_ver_str, 0, 16217 "bootcode version"); 16218 16219 snprintf(sc->fw_ver_str, sizeof(sc->fw_ver_str), "%d.%d.%d.%d", 16220 BCM_5710_FW_MAJOR_VERSION, 16221 BCM_5710_FW_MINOR_VERSION, 16222 BCM_5710_FW_REVISION_VERSION, 16223 BCM_5710_FW_ENGINEERING_VERSION); 16224 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "fw_version", 16225 CTLFLAG_RD, &sc->fw_ver_str, 0, 16226 "firmware version"); 16227 16228 snprintf(sc->mf_mode_str, sizeof(sc->mf_mode_str), "%s", 16229 ((sc->devinfo.mf_info.mf_mode == SINGLE_FUNCTION) ? "Single" : 16230 (sc->devinfo.mf_info.mf_mode == MULTI_FUNCTION_SD) ? "MF-SD" : 16231 (sc->devinfo.mf_info.mf_mode == MULTI_FUNCTION_SI) ? "MF-SI" : 16232 (sc->devinfo.mf_info.mf_mode == MULTI_FUNCTION_AFEX) ? "MF-AFEX" : 16233 "Unknown")); 16234 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "mf_mode", 16235 CTLFLAG_RD, &sc->mf_mode_str, 0, 16236 "multifunction mode"); 16237 16238 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "mf_vnics", 16239 CTLFLAG_RD, &sc->devinfo.mf_info.vnics_per_port, 0, 16240 "multifunction vnics per port"); 16241 16242 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "mac_addr", 16243 CTLFLAG_RD, &sc->mac_addr_str, 0, 16244 "mac address"); 16245 16246 snprintf(sc->pci_link_str, sizeof(sc->pci_link_str), "%s x%d", 16247 ((sc->devinfo.pcie_link_speed == 1) ? "2.5GT/s" : 16248 (sc->devinfo.pcie_link_speed == 2) ? "5.0GT/s" : 16249 (sc->devinfo.pcie_link_speed == 4) ? "8.0GT/s" : 16250 "???GT/s"), 16251 sc->devinfo.pcie_link_width); 16252 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "pci_link", 16253 CTLFLAG_RD, &sc->pci_link_str, 0, 16254 "pci link status"); 16255 16256 sc->debug = bxe_debug; 16257 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "debug", 16258 CTLFLAG_RW, &sc->debug, 0, 16259 "debug logging mode"); 16260 16261 sc->rx_budget = bxe_rx_budget; 16262 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rx_budget", 16263 CTLFLAG_RW, &sc->rx_budget, 0, 16264 "rx processing budget"); 16265 16266 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "state", 16267 CTLTYPE_UINT | CTLFLAG_RW, sc, 0, 16268 bxe_sysctl_state, "IU", "dump driver state"); 16269 16270 for (i = 0; i < BXE_NUM_ETH_STATS; i++) { 16271 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 16272 bxe_eth_stats_arr[i].string, 16273 CTLTYPE_U64 | CTLFLAG_RD, sc, i, 16274 bxe_sysctl_eth_stat, "LU", 16275 bxe_eth_stats_arr[i].string); 16276 } 16277 16278 /* add a new parent node for all queues "dev.bxe.#.queue" */ 16279 queue_top = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "queue", 16280 CTLFLAG_RD, NULL, "queue"); 16281 queue_top_children = SYSCTL_CHILDREN(queue_top); 16282 16283 for (i = 0; i < sc->num_queues; i++) { 16284 /* add a new parent node for a single queue "dev.bxe.#.queue.#" */ 16285 snprintf(queue_num_buf, sizeof(queue_num_buf), "%d", i); 16286 queue = SYSCTL_ADD_NODE(ctx, queue_top_children, OID_AUTO, 16287 queue_num_buf, CTLFLAG_RD, NULL, 16288 "single queue"); 16289 queue_children = SYSCTL_CHILDREN(queue); 16290 16291 for (j = 0; j < BXE_NUM_ETH_Q_STATS; j++) { 16292 q_stat = ((i << 16) | j); 16293 SYSCTL_ADD_PROC(ctx, queue_children, OID_AUTO, 16294 bxe_eth_q_stats_arr[j].string, 16295 CTLTYPE_U64 | CTLFLAG_RD, sc, q_stat, 16296 bxe_sysctl_eth_q_stat, "LU", 16297 bxe_eth_q_stats_arr[j].string); 16298 } 16299 } 16300 } 16301 16302 /* 16303 * Device attach function. 16304 * 16305 * Allocates device resources, performs secondary chip identification, and 16306 * initializes driver instance variables. This function is called from driver 16307 * load after a successful probe. 16308 * 16309 * Returns: 16310 * 0 = Success, >0 = Failure 16311 */ 16312 static int 16313 bxe_attach(device_t dev) 16314 { 16315 struct bxe_softc *sc; 16316 16317 sc = device_get_softc(dev); 16318 16319 BLOGD(sc, DBG_LOAD, "Starting attach...\n"); 16320 16321 sc->state = BXE_STATE_CLOSED; 16322 16323 sc->dev = dev; 16324 sc->unit = device_get_unit(dev); 16325 16326 BLOGD(sc, DBG_LOAD, "softc = %p\n", sc); 16327 16328 sc->pcie_bus = pci_get_bus(dev); 16329 sc->pcie_device = pci_get_slot(dev); 16330 sc->pcie_func = pci_get_function(dev); 16331 16332 /* enable bus master capability */ 16333 pci_enable_busmaster(dev); 16334 16335 /* get the BARs */ 16336 if (bxe_allocate_bars(sc) != 0) { 16337 return (ENXIO); 16338 } 16339 16340 /* initialize the mutexes */ 16341 bxe_init_mutexes(sc); 16342 16343 /* prepare the periodic callout */ 16344 callout_init(&sc->periodic_callout, 0); 16345 16346 /* prepare the chip taskqueue */ 16347 sc->chip_tq_flags = CHIP_TQ_NONE; 16348 snprintf(sc->chip_tq_name, sizeof(sc->chip_tq_name), 16349 "bxe%d_chip_tq", sc->unit); 16350 TASK_INIT(&sc->chip_tq_task, 0, bxe_handle_chip_tq, sc); 16351 sc->chip_tq = taskqueue_create(sc->chip_tq_name, M_NOWAIT, 16352 taskqueue_thread_enqueue, 16353 &sc->chip_tq); 16354 taskqueue_start_threads(&sc->chip_tq, 1, PWAIT, /* lower priority */ 16355 "%s", sc->chip_tq_name); 16356 16357 /* get device info and set params */ 16358 if (bxe_get_device_info(sc) != 0) { 16359 BLOGE(sc, "getting device info\n"); 16360 bxe_deallocate_bars(sc); 16361 pci_disable_busmaster(dev); 16362 return (ENXIO); 16363 } 16364 16365 /* get final misc params */ 16366 bxe_get_params(sc); 16367 16368 /* set the default MTU (changed via ifconfig) */ 16369 sc->mtu = ETHERMTU; 16370 16371 bxe_set_modes_bitmap(sc); 16372 16373 /* XXX 16374 * If in AFEX mode and the function is configured for FCoE 16375 * then bail... no L2 allowed. 16376 */ 16377 16378 /* get phy settings from shmem and 'and' against admin settings */ 16379 bxe_get_phy_info(sc); 16380 16381 /* initialize the FreeBSD ifnet interface */ 16382 if (bxe_init_ifnet(sc) != 0) { 16383 bxe_release_mutexes(sc); 16384 bxe_deallocate_bars(sc); 16385 pci_disable_busmaster(dev); 16386 return (ENXIO); 16387 } 16388 16389 /* allocate device interrupts */ 16390 if (bxe_interrupt_alloc(sc) != 0) { 16391 if (sc->ifnet != NULL) { 16392 ether_ifdetach(sc->ifnet); 16393 } 16394 ifmedia_removeall(&sc->ifmedia); 16395 bxe_release_mutexes(sc); 16396 bxe_deallocate_bars(sc); 16397 pci_disable_busmaster(dev); 16398 return (ENXIO); 16399 } 16400 16401 /* allocate ilt */ 16402 if (bxe_alloc_ilt_mem(sc) != 0) { 16403 bxe_interrupt_free(sc); 16404 if (sc->ifnet != NULL) { 16405 ether_ifdetach(sc->ifnet); 16406 } 16407 ifmedia_removeall(&sc->ifmedia); 16408 bxe_release_mutexes(sc); 16409 bxe_deallocate_bars(sc); 16410 pci_disable_busmaster(dev); 16411 return (ENXIO); 16412 } 16413 16414 /* allocate the host hardware/software hsi structures */ 16415 if (bxe_alloc_hsi_mem(sc) != 0) { 16416 bxe_free_ilt_mem(sc); 16417 bxe_interrupt_free(sc); 16418 if (sc->ifnet != NULL) { 16419 ether_ifdetach(sc->ifnet); 16420 } 16421 ifmedia_removeall(&sc->ifmedia); 16422 bxe_release_mutexes(sc); 16423 bxe_deallocate_bars(sc); 16424 pci_disable_busmaster(dev); 16425 return (ENXIO); 16426 } 16427 16428 /* need to reset chip if UNDI was active */ 16429 if (IS_PF(sc) && !BXE_NOMCP(sc)) { 16430 /* init fw_seq */ 16431 sc->fw_seq = 16432 (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_mb_header) & 16433 DRV_MSG_SEQ_NUMBER_MASK); 16434 BLOGD(sc, DBG_LOAD, "prev unload fw_seq 0x%04x\n", sc->fw_seq); 16435 bxe_prev_unload(sc); 16436 } 16437 16438 #if 1 16439 /* XXX */ 16440 bxe_dcbx_set_state(sc, FALSE, BXE_DCBX_ENABLED_OFF); 16441 #else 16442 if (SHMEM2_HAS(sc, dcbx_lldp_params_offset) && 16443 SHMEM2_HAS(sc, dcbx_lldp_dcbx_stat_offset) && 16444 SHMEM2_RD(sc, dcbx_lldp_params_offset) && 16445 SHMEM2_RD(sc, dcbx_lldp_dcbx_stat_offset)) { 16446 bxe_dcbx_set_state(sc, TRUE, BXE_DCBX_ENABLED_ON_NEG_ON); 16447 bxe_dcbx_init_params(sc); 16448 } else { 16449 bxe_dcbx_set_state(sc, FALSE, BXE_DCBX_ENABLED_OFF); 16450 } 16451 #endif 16452 16453 /* calculate qm_cid_count */ 16454 sc->qm_cid_count = bxe_set_qm_cid_count(sc); 16455 BLOGD(sc, DBG_LOAD, "qm_cid_count=%d\n", sc->qm_cid_count); 16456 16457 sc->max_cos = 1; 16458 bxe_init_multi_cos(sc); 16459 16460 bxe_add_sysctls(sc); 16461 16462 return (0); 16463 } 16464 16465 /* 16466 * Device detach function. 16467 * 16468 * Stops the controller, resets the controller, and releases resources. 16469 * 16470 * Returns: 16471 * 0 = Success, >0 = Failure 16472 */ 16473 static int 16474 bxe_detach(device_t dev) 16475 { 16476 struct bxe_softc *sc; 16477 struct ifnet *ifp; 16478 16479 sc = device_get_softc(dev); 16480 16481 BLOGD(sc, DBG_LOAD, "Starting detach...\n"); 16482 16483 ifp = sc->ifnet; 16484 if (ifp != NULL && ifp->if_vlantrunk != NULL) { 16485 BLOGE(sc, "Cannot detach while VLANs are in use.\n"); 16486 return(EBUSY); 16487 } 16488 16489 /* stop the periodic callout */ 16490 bxe_periodic_stop(sc); 16491 16492 /* stop the chip taskqueue */ 16493 atomic_store_rel_long(&sc->chip_tq_flags, CHIP_TQ_NONE); 16494 if (sc->chip_tq) { 16495 taskqueue_drain(sc->chip_tq, &sc->chip_tq_task); 16496 taskqueue_free(sc->chip_tq); 16497 sc->chip_tq = NULL; 16498 } 16499 16500 /* stop and reset the controller if it was open */ 16501 if (sc->state != BXE_STATE_CLOSED) { 16502 BXE_CORE_LOCK(sc); 16503 bxe_nic_unload(sc, UNLOAD_CLOSE, TRUE); 16504 BXE_CORE_UNLOCK(sc); 16505 } 16506 16507 /* release the network interface */ 16508 if (ifp != NULL) { 16509 ether_ifdetach(ifp); 16510 } 16511 ifmedia_removeall(&sc->ifmedia); 16512 16513 /* XXX do the following based on driver state... */ 16514 16515 /* free the host hardware/software hsi structures */ 16516 bxe_free_hsi_mem(sc); 16517 16518 /* free ilt */ 16519 bxe_free_ilt_mem(sc); 16520 16521 /* release the interrupts */ 16522 bxe_interrupt_free(sc); 16523 16524 /* Release the mutexes*/ 16525 bxe_release_mutexes(sc); 16526 16527 /* Release the PCIe BAR mapped memory */ 16528 bxe_deallocate_bars(sc); 16529 16530 /* Release the FreeBSD interface. */ 16531 if (sc->ifnet != NULL) { 16532 if_free(sc->ifnet); 16533 } 16534 16535 pci_disable_busmaster(dev); 16536 16537 return (0); 16538 } 16539 16540 /* 16541 * Device shutdown function. 16542 * 16543 * Stops and resets the controller. 16544 * 16545 * Returns: 16546 * Nothing 16547 */ 16548 static int 16549 bxe_shutdown(device_t dev) 16550 { 16551 struct bxe_softc *sc; 16552 16553 sc = device_get_softc(dev); 16554 16555 BLOGD(sc, DBG_LOAD, "Starting shutdown...\n"); 16556 16557 /* stop the periodic callout */ 16558 bxe_periodic_stop(sc); 16559 16560 BXE_CORE_LOCK(sc); 16561 bxe_nic_unload(sc, UNLOAD_NORMAL, FALSE); 16562 BXE_CORE_UNLOCK(sc); 16563 16564 return (0); 16565 } 16566 16567 void 16568 bxe_igu_ack_sb(struct bxe_softc *sc, 16569 uint8_t igu_sb_id, 16570 uint8_t segment, 16571 uint16_t index, 16572 uint8_t op, 16573 uint8_t update) 16574 { 16575 uint32_t igu_addr = sc->igu_base_addr; 16576 igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8; 16577 bxe_igu_ack_sb_gen(sc, igu_sb_id, segment, index, op, update, igu_addr); 16578 } 16579 16580 static void 16581 bxe_igu_clear_sb_gen(struct bxe_softc *sc, 16582 uint8_t func, 16583 uint8_t idu_sb_id, 16584 uint8_t is_pf) 16585 { 16586 uint32_t data, ctl, cnt = 100; 16587 uint32_t igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA; 16588 uint32_t igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL; 16589 uint32_t igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP + (idu_sb_id/32)*4; 16590 uint32_t sb_bit = 1 << (idu_sb_id%32); 16591 uint32_t func_encode = func | (is_pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT; 16592 uint32_t addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id; 16593 16594 /* Not supported in BC mode */ 16595 if (CHIP_INT_MODE_IS_BC(sc)) { 16596 return; 16597 } 16598 16599 data = ((IGU_USE_REGISTER_cstorm_type_0_sb_cleanup << 16600 IGU_REGULAR_CLEANUP_TYPE_SHIFT) | 16601 IGU_REGULAR_CLEANUP_SET | 16602 IGU_REGULAR_BCLEANUP); 16603 16604 ctl = ((addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT) | 16605 (func_encode << IGU_CTRL_REG_FID_SHIFT) | 16606 (IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT)); 16607 16608 BLOGD(sc, DBG_LOAD, "write 0x%08x to IGU(via GRC) addr 0x%x\n", 16609 data, igu_addr_data); 16610 REG_WR(sc, igu_addr_data, data); 16611 16612 bus_space_barrier(sc->bar[BAR0].tag, sc->bar[BAR0].handle, 0, 0, 16613 BUS_SPACE_BARRIER_WRITE); 16614 mb(); 16615 16616 BLOGD(sc, DBG_LOAD, "write 0x%08x to IGU(via GRC) addr 0x%x\n", 16617 ctl, igu_addr_ctl); 16618 REG_WR(sc, igu_addr_ctl, ctl); 16619 16620 bus_space_barrier(sc->bar[BAR0].tag, sc->bar[BAR0].handle, 0, 0, 16621 BUS_SPACE_BARRIER_WRITE); 16622 mb(); 16623 16624 /* wait for clean up to finish */ 16625 while (!(REG_RD(sc, igu_addr_ack) & sb_bit) && --cnt) { 16626 DELAY(20000); 16627 } 16628 16629 if (!(REG_RD(sc, igu_addr_ack) & sb_bit)) { 16630 BLOGD(sc, DBG_LOAD, 16631 "Unable to finish IGU cleanup: " 16632 "idu_sb_id %d offset %d bit %d (cnt %d)\n", 16633 idu_sb_id, idu_sb_id/32, idu_sb_id%32, cnt); 16634 } 16635 } 16636 16637 static void 16638 bxe_igu_clear_sb(struct bxe_softc *sc, 16639 uint8_t idu_sb_id) 16640 { 16641 bxe_igu_clear_sb_gen(sc, SC_FUNC(sc), idu_sb_id, TRUE /*PF*/); 16642 } 16643 16644 16645 16646 16647 16648 16649 16650 /*******************/ 16651 /* ECORE CALLBACKS */ 16652 /*******************/ 16653 16654 static void 16655 bxe_reset_common(struct bxe_softc *sc) 16656 { 16657 uint32_t val = 0x1400; 16658 16659 /* reset_common */ 16660 REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR), 0xd3ffff7f); 16661 16662 if (CHIP_IS_E3(sc)) { 16663 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0; 16664 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1; 16665 } 16666 16667 REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR), val); 16668 } 16669 16670 static void 16671 bxe_common_init_phy(struct bxe_softc *sc) 16672 { 16673 uint32_t shmem_base[2]; 16674 uint32_t shmem2_base[2]; 16675 16676 /* Avoid common init in case MFW supports LFA */ 16677 if (SHMEM2_RD(sc, size) > 16678 (uint32_t)offsetof(struct shmem2_region, 16679 lfa_host_addr[SC_PORT(sc)])) { 16680 return; 16681 } 16682 16683 shmem_base[0] = sc->devinfo.shmem_base; 16684 shmem2_base[0] = sc->devinfo.shmem2_base; 16685 16686 if (!CHIP_IS_E1x(sc)) { 16687 shmem_base[1] = SHMEM2_RD(sc, other_shmem_base_addr); 16688 shmem2_base[1] = SHMEM2_RD(sc, other_shmem2_base_addr); 16689 } 16690 16691 BXE_PHY_LOCK(sc); 16692 elink_common_init_phy(sc, shmem_base, shmem2_base, 16693 sc->devinfo.chip_id, 0); 16694 BXE_PHY_UNLOCK(sc); 16695 } 16696 16697 static void 16698 bxe_pf_disable(struct bxe_softc *sc) 16699 { 16700 uint32_t val = REG_RD(sc, IGU_REG_PF_CONFIGURATION); 16701 16702 val &= ~IGU_PF_CONF_FUNC_EN; 16703 16704 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val); 16705 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0); 16706 REG_WR(sc, CFC_REG_WEAK_ENABLE_PF, 0); 16707 } 16708 16709 static void 16710 bxe_init_pxp(struct bxe_softc *sc) 16711 { 16712 uint16_t devctl; 16713 int r_order, w_order; 16714 16715 devctl = bxe_pcie_capability_read(sc, PCIR_EXPRESS_DEVICE_CTL, 2); 16716 16717 BLOGD(sc, DBG_LOAD, "read 0x%08x from devctl\n", devctl); 16718 16719 w_order = ((devctl & PCIM_EXP_CTL_MAX_PAYLOAD) >> 5); 16720 16721 if (sc->mrrs == -1) { 16722 r_order = ((devctl & PCIM_EXP_CTL_MAX_READ_REQUEST) >> 12); 16723 } else { 16724 BLOGD(sc, DBG_LOAD, "forcing read order to %d\n", sc->mrrs); 16725 r_order = sc->mrrs; 16726 } 16727 16728 ecore_init_pxp_arb(sc, r_order, w_order); 16729 } 16730 16731 static uint32_t 16732 bxe_get_pretend_reg(struct bxe_softc *sc) 16733 { 16734 uint32_t base = PXP2_REG_PGL_PRETEND_FUNC_F0; 16735 uint32_t stride = (PXP2_REG_PGL_PRETEND_FUNC_F1 - base); 16736 return (base + (SC_ABS_FUNC(sc)) * stride); 16737 } 16738 16739 /* 16740 * Called only on E1H or E2. 16741 * When pretending to be PF, the pretend value is the function number 0..7. 16742 * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID 16743 * combination. 16744 */ 16745 static int 16746 bxe_pretend_func(struct bxe_softc *sc, 16747 uint16_t pretend_func_val) 16748 { 16749 uint32_t pretend_reg; 16750 16751 if (CHIP_IS_E1H(sc) && (pretend_func_val > E1H_FUNC_MAX)) { 16752 return (-1); 16753 } 16754 16755 /* get my own pretend register */ 16756 pretend_reg = bxe_get_pretend_reg(sc); 16757 REG_WR(sc, pretend_reg, pretend_func_val); 16758 REG_RD(sc, pretend_reg); 16759 return (0); 16760 } 16761 16762 static void 16763 bxe_iov_init_dmae(struct bxe_softc *sc) 16764 { 16765 return; 16766 #if 0 16767 BLOGD(sc, DBG_LOAD, "SRIOV is %s\n", IS_SRIOV(sc) ? "ON" : "OFF"); 16768 16769 if (!IS_SRIOV(sc)) { 16770 return; 16771 } 16772 16773 REG_WR(sc, DMAE_REG_BACKWARD_COMP_EN, 0); 16774 #endif 16775 } 16776 16777 #if 0 16778 static int 16779 bxe_iov_init_ilt(struct bxe_softc *sc, 16780 uint16_t line) 16781 { 16782 return (line); 16783 #if 0 16784 int i; 16785 struct ecore_ilt* ilt = sc->ilt; 16786 16787 if (!IS_SRIOV(sc)) { 16788 return (line); 16789 } 16790 16791 /* set vfs ilt lines */ 16792 for (i = 0; i < BXE_VF_CIDS/ILT_PAGE_CIDS ; i++) { 16793 struct hw_dma *hw_cxt = SC_VF_CXT_PAGE(sc,i); 16794 ilt->lines[line+i].page = hw_cxt->addr; 16795 ilt->lines[line+i].page_mapping = hw_cxt->mapping; 16796 ilt->lines[line+i].size = hw_cxt->size; /* doesn't matter */ 16797 } 16798 return (line+i); 16799 #endif 16800 } 16801 #endif 16802 16803 static void 16804 bxe_iov_init_dq(struct bxe_softc *sc) 16805 { 16806 return; 16807 #if 0 16808 if (!IS_SRIOV(sc)) { 16809 return; 16810 } 16811 16812 /* Set the DQ such that the CID reflect the abs_vfid */ 16813 REG_WR(sc, DORQ_REG_VF_NORM_VF_BASE, 0); 16814 REG_WR(sc, DORQ_REG_MAX_RVFID_SIZE, ilog2(BNX2X_MAX_NUM_OF_VFS)); 16815 16816 /* 16817 * Set VFs starting CID. If its > 0 the preceding CIDs are belong to 16818 * the PF L2 queues 16819 */ 16820 REG_WR(sc, DORQ_REG_VF_NORM_CID_BASE, BNX2X_FIRST_VF_CID); 16821 16822 /* The VF window size is the log2 of the max number of CIDs per VF */ 16823 REG_WR(sc, DORQ_REG_VF_NORM_CID_WND_SIZE, BNX2X_VF_CID_WND); 16824 16825 /* 16826 * The VF doorbell size 0 - *B, 4 - 128B. We set it here to match 16827 * the Pf doorbell size although the 2 are independent. 16828 */ 16829 REG_WR(sc, DORQ_REG_VF_NORM_CID_OFST, 16830 BNX2X_DB_SHIFT - BNX2X_DB_MIN_SHIFT); 16831 16832 /* 16833 * No security checks for now - 16834 * configure single rule (out of 16) mask = 0x1, value = 0x0, 16835 * CID range 0 - 0x1ffff 16836 */ 16837 REG_WR(sc, DORQ_REG_VF_TYPE_MASK_0, 1); 16838 REG_WR(sc, DORQ_REG_VF_TYPE_VALUE_0, 0); 16839 REG_WR(sc, DORQ_REG_VF_TYPE_MIN_MCID_0, 0); 16840 REG_WR(sc, DORQ_REG_VF_TYPE_MAX_MCID_0, 0x1ffff); 16841 16842 /* set the number of VF alllowed doorbells to the full DQ range */ 16843 REG_WR(sc, DORQ_REG_VF_NORM_MAX_CID_COUNT, 0x20000); 16844 16845 /* set the VF doorbell threshold */ 16846 REG_WR(sc, DORQ_REG_VF_USAGE_CT_LIMIT, 4); 16847 #endif 16848 } 16849 16850 /* send a NIG loopback debug packet */ 16851 static void 16852 bxe_lb_pckt(struct bxe_softc *sc) 16853 { 16854 uint32_t wb_write[3]; 16855 16856 /* Ethernet source and destination addresses */ 16857 wb_write[0] = 0x55555555; 16858 wb_write[1] = 0x55555555; 16859 wb_write[2] = 0x20; /* SOP */ 16860 REG_WR_DMAE(sc, NIG_REG_DEBUG_PACKET_LB, wb_write, 3); 16861 16862 /* NON-IP protocol */ 16863 wb_write[0] = 0x09000000; 16864 wb_write[1] = 0x55555555; 16865 wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */ 16866 REG_WR_DMAE(sc, NIG_REG_DEBUG_PACKET_LB, wb_write, 3); 16867 } 16868 16869 /* 16870 * Some of the internal memories are not directly readable from the driver. 16871 * To test them we send debug packets. 16872 */ 16873 static int 16874 bxe_int_mem_test(struct bxe_softc *sc) 16875 { 16876 int factor; 16877 int count, i; 16878 uint32_t val = 0; 16879 16880 if (CHIP_REV_IS_FPGA(sc)) { 16881 factor = 120; 16882 } else if (CHIP_REV_IS_EMUL(sc)) { 16883 factor = 200; 16884 } else { 16885 factor = 1; 16886 } 16887 16888 /* disable inputs of parser neighbor blocks */ 16889 REG_WR(sc, TSDM_REG_ENABLE_IN1, 0x0); 16890 REG_WR(sc, TCM_REG_PRS_IFEN, 0x0); 16891 REG_WR(sc, CFC_REG_DEBUG0, 0x1); 16892 REG_WR(sc, NIG_REG_PRS_REQ_IN_EN, 0x0); 16893 16894 /* write 0 to parser credits for CFC search request */ 16895 REG_WR(sc, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0); 16896 16897 /* send Ethernet packet */ 16898 bxe_lb_pckt(sc); 16899 16900 /* TODO do i reset NIG statistic? */ 16901 /* Wait until NIG register shows 1 packet of size 0x10 */ 16902 count = 1000 * factor; 16903 while (count) { 16904 bxe_read_dmae(sc, NIG_REG_STAT2_BRB_OCTET, 2); 16905 val = *BXE_SP(sc, wb_data[0]); 16906 if (val == 0x10) { 16907 break; 16908 } 16909 16910 DELAY(10000); 16911 count--; 16912 } 16913 16914 if (val != 0x10) { 16915 BLOGE(sc, "NIG timeout val=0x%x\n", val); 16916 return (-1); 16917 } 16918 16919 /* wait until PRS register shows 1 packet */ 16920 count = (1000 * factor); 16921 while (count) { 16922 val = REG_RD(sc, PRS_REG_NUM_OF_PACKETS); 16923 if (val == 1) { 16924 break; 16925 } 16926 16927 DELAY(10000); 16928 count--; 16929 } 16930 16931 if (val != 0x1) { 16932 BLOGE(sc, "PRS timeout val=0x%x\n", val); 16933 return (-2); 16934 } 16935 16936 /* Reset and init BRB, PRS */ 16937 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03); 16938 DELAY(50000); 16939 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03); 16940 DELAY(50000); 16941 ecore_init_block(sc, BLOCK_BRB1, PHASE_COMMON); 16942 ecore_init_block(sc, BLOCK_PRS, PHASE_COMMON); 16943 16944 /* Disable inputs of parser neighbor blocks */ 16945 REG_WR(sc, TSDM_REG_ENABLE_IN1, 0x0); 16946 REG_WR(sc, TCM_REG_PRS_IFEN, 0x0); 16947 REG_WR(sc, CFC_REG_DEBUG0, 0x1); 16948 REG_WR(sc, NIG_REG_PRS_REQ_IN_EN, 0x0); 16949 16950 /* Write 0 to parser credits for CFC search request */ 16951 REG_WR(sc, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0); 16952 16953 /* send 10 Ethernet packets */ 16954 for (i = 0; i < 10; i++) { 16955 bxe_lb_pckt(sc); 16956 } 16957 16958 /* Wait until NIG register shows 10+1 packets of size 11*0x10 = 0xb0 */ 16959 count = (1000 * factor); 16960 while (count) { 16961 bxe_read_dmae(sc, NIG_REG_STAT2_BRB_OCTET, 2); 16962 val = *BXE_SP(sc, wb_data[0]); 16963 if (val == 0xb0) { 16964 break; 16965 } 16966 16967 DELAY(10000); 16968 count--; 16969 } 16970 16971 if (val != 0xb0) { 16972 BLOGE(sc, "NIG timeout val=0x%x\n", val); 16973 return (-3); 16974 } 16975 16976 /* Wait until PRS register shows 2 packets */ 16977 val = REG_RD(sc, PRS_REG_NUM_OF_PACKETS); 16978 if (val != 2) { 16979 BLOGE(sc, "PRS timeout val=0x%x\n", val); 16980 } 16981 16982 /* Write 1 to parser credits for CFC search request */ 16983 REG_WR(sc, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1); 16984 16985 /* Wait until PRS register shows 3 packets */ 16986 DELAY(10000 * factor); 16987 16988 /* Wait until NIG register shows 1 packet of size 0x10 */ 16989 val = REG_RD(sc, PRS_REG_NUM_OF_PACKETS); 16990 if (val != 3) { 16991 BLOGE(sc, "PRS timeout val=0x%x\n", val); 16992 } 16993 16994 /* clear NIG EOP FIFO */ 16995 for (i = 0; i < 11; i++) { 16996 REG_RD(sc, NIG_REG_INGRESS_EOP_LB_FIFO); 16997 } 16998 16999 val = REG_RD(sc, NIG_REG_INGRESS_EOP_LB_EMPTY); 17000 if (val != 1) { 17001 BLOGE(sc, "clear of NIG failed\n"); 17002 return (-4); 17003 } 17004 17005 /* Reset and init BRB, PRS, NIG */ 17006 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03); 17007 DELAY(50000); 17008 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03); 17009 DELAY(50000); 17010 ecore_init_block(sc, BLOCK_BRB1, PHASE_COMMON); 17011 ecore_init_block(sc, BLOCK_PRS, PHASE_COMMON); 17012 if (!CNIC_SUPPORT(sc)) { 17013 /* set NIC mode */ 17014 REG_WR(sc, PRS_REG_NIC_MODE, 1); 17015 } 17016 17017 /* Enable inputs of parser neighbor blocks */ 17018 REG_WR(sc, TSDM_REG_ENABLE_IN1, 0x7fffffff); 17019 REG_WR(sc, TCM_REG_PRS_IFEN, 0x1); 17020 REG_WR(sc, CFC_REG_DEBUG0, 0x0); 17021 REG_WR(sc, NIG_REG_PRS_REQ_IN_EN, 0x1); 17022 17023 return (0); 17024 } 17025 17026 static void 17027 bxe_setup_fan_failure_detection(struct bxe_softc *sc) 17028 { 17029 int is_required; 17030 uint32_t val; 17031 int port; 17032 17033 is_required = 0; 17034 val = (SHMEM_RD(sc, dev_info.shared_hw_config.config2) & 17035 SHARED_HW_CFG_FAN_FAILURE_MASK); 17036 17037 if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED) { 17038 is_required = 1; 17039 } 17040 /* 17041 * The fan failure mechanism is usually related to the PHY type since 17042 * the power consumption of the board is affected by the PHY. Currently, 17043 * fan is required for most designs with SFX7101, BCM8727 and BCM8481. 17044 */ 17045 else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE) { 17046 for (port = PORT_0; port < PORT_MAX; port++) { 17047 is_required |= elink_fan_failure_det_req(sc, 17048 sc->devinfo.shmem_base, 17049 sc->devinfo.shmem2_base, 17050 port); 17051 } 17052 } 17053 17054 BLOGD(sc, DBG_LOAD, "fan detection setting: %d\n", is_required); 17055 17056 if (is_required == 0) { 17057 return; 17058 } 17059 17060 /* Fan failure is indicated by SPIO 5 */ 17061 bxe_set_spio(sc, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z); 17062 17063 /* set to active low mode */ 17064 val = REG_RD(sc, MISC_REG_SPIO_INT); 17065 val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS); 17066 REG_WR(sc, MISC_REG_SPIO_INT, val); 17067 17068 /* enable interrupt to signal the IGU */ 17069 val = REG_RD(sc, MISC_REG_SPIO_EVENT_EN); 17070 val |= MISC_SPIO_SPIO5; 17071 REG_WR(sc, MISC_REG_SPIO_EVENT_EN, val); 17072 } 17073 17074 static void 17075 bxe_enable_blocks_attention(struct bxe_softc *sc) 17076 { 17077 uint32_t val; 17078 17079 REG_WR(sc, PXP_REG_PXP_INT_MASK_0, 0); 17080 if (!CHIP_IS_E1x(sc)) { 17081 REG_WR(sc, PXP_REG_PXP_INT_MASK_1, 0x40); 17082 } else { 17083 REG_WR(sc, PXP_REG_PXP_INT_MASK_1, 0); 17084 } 17085 REG_WR(sc, DORQ_REG_DORQ_INT_MASK, 0); 17086 REG_WR(sc, CFC_REG_CFC_INT_MASK, 0); 17087 /* 17088 * mask read length error interrupts in brb for parser 17089 * (parsing unit and 'checksum and crc' unit) 17090 * these errors are legal (PU reads fixed length and CAC can cause 17091 * read length error on truncated packets) 17092 */ 17093 REG_WR(sc, BRB1_REG_BRB1_INT_MASK, 0xFC00); 17094 REG_WR(sc, QM_REG_QM_INT_MASK, 0); 17095 REG_WR(sc, TM_REG_TM_INT_MASK, 0); 17096 REG_WR(sc, XSDM_REG_XSDM_INT_MASK_0, 0); 17097 REG_WR(sc, XSDM_REG_XSDM_INT_MASK_1, 0); 17098 REG_WR(sc, XCM_REG_XCM_INT_MASK, 0); 17099 /* REG_WR(sc, XSEM_REG_XSEM_INT_MASK_0, 0); */ 17100 /* REG_WR(sc, XSEM_REG_XSEM_INT_MASK_1, 0); */ 17101 REG_WR(sc, USDM_REG_USDM_INT_MASK_0, 0); 17102 REG_WR(sc, USDM_REG_USDM_INT_MASK_1, 0); 17103 REG_WR(sc, UCM_REG_UCM_INT_MASK, 0); 17104 /* REG_WR(sc, USEM_REG_USEM_INT_MASK_0, 0); */ 17105 /* REG_WR(sc, USEM_REG_USEM_INT_MASK_1, 0); */ 17106 REG_WR(sc, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0); 17107 REG_WR(sc, CSDM_REG_CSDM_INT_MASK_0, 0); 17108 REG_WR(sc, CSDM_REG_CSDM_INT_MASK_1, 0); 17109 REG_WR(sc, CCM_REG_CCM_INT_MASK, 0); 17110 /* REG_WR(sc, CSEM_REG_CSEM_INT_MASK_0, 0); */ 17111 /* REG_WR(sc, CSEM_REG_CSEM_INT_MASK_1, 0); */ 17112 17113 val = (PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT | 17114 PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF | 17115 PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN); 17116 if (!CHIP_IS_E1x(sc)) { 17117 val |= (PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED | 17118 PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED); 17119 } 17120 REG_WR(sc, PXP2_REG_PXP2_INT_MASK_0, val); 17121 17122 REG_WR(sc, TSDM_REG_TSDM_INT_MASK_0, 0); 17123 REG_WR(sc, TSDM_REG_TSDM_INT_MASK_1, 0); 17124 REG_WR(sc, TCM_REG_TCM_INT_MASK, 0); 17125 /* REG_WR(sc, TSEM_REG_TSEM_INT_MASK_0, 0); */ 17126 17127 if (!CHIP_IS_E1x(sc)) { 17128 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */ 17129 REG_WR(sc, TSEM_REG_TSEM_INT_MASK_1, 0x07ff); 17130 } 17131 17132 REG_WR(sc, CDU_REG_CDU_INT_MASK, 0); 17133 REG_WR(sc, DMAE_REG_DMAE_INT_MASK, 0); 17134 /* REG_WR(sc, MISC_REG_MISC_INT_MASK, 0); */ 17135 REG_WR(sc, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */ 17136 } 17137 17138 /** 17139 * bxe_init_hw_common - initialize the HW at the COMMON phase. 17140 * 17141 * @sc: driver handle 17142 */ 17143 static int 17144 bxe_init_hw_common(struct bxe_softc *sc) 17145 { 17146 uint8_t abs_func_id; 17147 uint32_t val; 17148 17149 BLOGD(sc, DBG_LOAD, "starting common init for func %d\n", 17150 SC_ABS_FUNC(sc)); 17151 17152 /* 17153 * take the RESET lock to protect undi_unload flow from accessing 17154 * registers while we are resetting the chip 17155 */ 17156 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RESET); 17157 17158 bxe_reset_common(sc); 17159 17160 REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET), 0xffffffff); 17161 17162 val = 0xfffc; 17163 if (CHIP_IS_E3(sc)) { 17164 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0; 17165 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1; 17166 } 17167 17168 REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET), val); 17169 17170 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET); 17171 17172 ecore_init_block(sc, BLOCK_MISC, PHASE_COMMON); 17173 BLOGD(sc, DBG_LOAD, "after misc block init\n"); 17174 17175 if (!CHIP_IS_E1x(sc)) { 17176 /* 17177 * 4-port mode or 2-port mode we need to turn off master-enable for 17178 * everyone. After that we turn it back on for self. So, we disregard 17179 * multi-function, and always disable all functions on the given path, 17180 * this means 0,2,4,6 for path 0 and 1,3,5,7 for path 1 17181 */ 17182 for (abs_func_id = SC_PATH(sc); 17183 abs_func_id < (E2_FUNC_MAX * 2); 17184 abs_func_id += 2) { 17185 if (abs_func_id == SC_ABS_FUNC(sc)) { 17186 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); 17187 continue; 17188 } 17189 17190 bxe_pretend_func(sc, abs_func_id); 17191 17192 /* clear pf enable */ 17193 bxe_pf_disable(sc); 17194 17195 bxe_pretend_func(sc, SC_ABS_FUNC(sc)); 17196 } 17197 } 17198 17199 BLOGD(sc, DBG_LOAD, "after pf disable\n"); 17200 17201 ecore_init_block(sc, BLOCK_PXP, PHASE_COMMON); 17202 17203 if (CHIP_IS_E1(sc)) { 17204 /* 17205 * enable HW interrupt from PXP on USDM overflow 17206 * bit 16 on INT_MASK_0 17207 */ 17208 REG_WR(sc, PXP_REG_PXP_INT_MASK_0, 0); 17209 } 17210 17211 ecore_init_block(sc, BLOCK_PXP2, PHASE_COMMON); 17212 bxe_init_pxp(sc); 17213 17214 #ifdef __BIG_ENDIAN 17215 REG_WR(sc, PXP2_REG_RQ_QM_ENDIAN_M, 1); 17216 REG_WR(sc, PXP2_REG_RQ_TM_ENDIAN_M, 1); 17217 REG_WR(sc, PXP2_REG_RQ_SRC_ENDIAN_M, 1); 17218 REG_WR(sc, PXP2_REG_RQ_CDU_ENDIAN_M, 1); 17219 REG_WR(sc, PXP2_REG_RQ_DBG_ENDIAN_M, 1); 17220 /* make sure this value is 0 */ 17221 REG_WR(sc, PXP2_REG_RQ_HC_ENDIAN_M, 0); 17222 17223 //REG_WR(sc, PXP2_REG_RD_PBF_SWAP_MODE, 1); 17224 REG_WR(sc, PXP2_REG_RD_QM_SWAP_MODE, 1); 17225 REG_WR(sc, PXP2_REG_RD_TM_SWAP_MODE, 1); 17226 REG_WR(sc, PXP2_REG_RD_SRC_SWAP_MODE, 1); 17227 REG_WR(sc, PXP2_REG_RD_CDURD_SWAP_MODE, 1); 17228 #endif 17229 17230 ecore_ilt_init_page_size(sc, INITOP_SET); 17231 17232 if (CHIP_REV_IS_FPGA(sc) && CHIP_IS_E1H(sc)) { 17233 REG_WR(sc, PXP2_REG_PGL_TAGS_LIMIT, 0x1); 17234 } 17235 17236 /* let the HW do it's magic... */ 17237 DELAY(100000); 17238 17239 /* finish PXP init */ 17240 val = REG_RD(sc, PXP2_REG_RQ_CFG_DONE); 17241 if (val != 1) { 17242 BLOGE(sc, "PXP2 CFG failed\n"); 17243 return (-1); 17244 } 17245 val = REG_RD(sc, PXP2_REG_RD_INIT_DONE); 17246 if (val != 1) { 17247 BLOGE(sc, "PXP2 RD_INIT failed\n"); 17248 return (-1); 17249 } 17250 17251 BLOGD(sc, DBG_LOAD, "after pxp init\n"); 17252 17253 /* 17254 * Timer bug workaround for E2 only. We need to set the entire ILT to have 17255 * entries with value "0" and valid bit on. This needs to be done by the 17256 * first PF that is loaded in a path (i.e. common phase) 17257 */ 17258 if (!CHIP_IS_E1x(sc)) { 17259 /* 17260 * In E2 there is a bug in the timers block that can cause function 6 / 7 17261 * (i.e. vnic3) to start even if it is marked as "scan-off". 17262 * This occurs when a different function (func2,3) is being marked 17263 * as "scan-off". Real-life scenario for example: if a driver is being 17264 * load-unloaded while func6,7 are down. This will cause the timer to access 17265 * the ilt, translate to a logical address and send a request to read/write. 17266 * Since the ilt for the function that is down is not valid, this will cause 17267 * a translation error which is unrecoverable. 17268 * The Workaround is intended to make sure that when this happens nothing 17269 * fatal will occur. The workaround: 17270 * 1. First PF driver which loads on a path will: 17271 * a. After taking the chip out of reset, by using pretend, 17272 * it will write "0" to the following registers of 17273 * the other vnics. 17274 * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0); 17275 * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0); 17276 * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0); 17277 * And for itself it will write '1' to 17278 * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable 17279 * dmae-operations (writing to pram for example.) 17280 * note: can be done for only function 6,7 but cleaner this 17281 * way. 17282 * b. Write zero+valid to the entire ILT. 17283 * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of 17284 * VNIC3 (of that port). The range allocated will be the 17285 * entire ILT. This is needed to prevent ILT range error. 17286 * 2. Any PF driver load flow: 17287 * a. ILT update with the physical addresses of the allocated 17288 * logical pages. 17289 * b. Wait 20msec. - note that this timeout is needed to make 17290 * sure there are no requests in one of the PXP internal 17291 * queues with "old" ILT addresses. 17292 * c. PF enable in the PGLC. 17293 * d. Clear the was_error of the PF in the PGLC. (could have 17294 * occurred while driver was down) 17295 * e. PF enable in the CFC (WEAK + STRONG) 17296 * f. Timers scan enable 17297 * 3. PF driver unload flow: 17298 * a. Clear the Timers scan_en. 17299 * b. Polling for scan_on=0 for that PF. 17300 * c. Clear the PF enable bit in the PXP. 17301 * d. Clear the PF enable in the CFC (WEAK + STRONG) 17302 * e. Write zero+valid to all ILT entries (The valid bit must 17303 * stay set) 17304 * f. If this is VNIC 3 of a port then also init 17305 * first_timers_ilt_entry to zero and last_timers_ilt_entry 17306 * to the last enrty in the ILT. 17307 * 17308 * Notes: 17309 * Currently the PF error in the PGLC is non recoverable. 17310 * In the future the there will be a recovery routine for this error. 17311 * Currently attention is masked. 17312 * Having an MCP lock on the load/unload process does not guarantee that 17313 * there is no Timer disable during Func6/7 enable. This is because the 17314 * Timers scan is currently being cleared by the MCP on FLR. 17315 * Step 2.d can be done only for PF6/7 and the driver can also check if 17316 * there is error before clearing it. But the flow above is simpler and 17317 * more general. 17318 * All ILT entries are written by zero+valid and not just PF6/7 17319 * ILT entries since in the future the ILT entries allocation for 17320 * PF-s might be dynamic. 17321 */ 17322 struct ilt_client_info ilt_cli; 17323 struct ecore_ilt ilt; 17324 17325 memset(&ilt_cli, 0, sizeof(struct ilt_client_info)); 17326 memset(&ilt, 0, sizeof(struct ecore_ilt)); 17327 17328 /* initialize dummy TM client */ 17329 ilt_cli.start = 0; 17330 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1; 17331 ilt_cli.client_num = ILT_CLIENT_TM; 17332 17333 /* 17334 * Step 1: set zeroes to all ilt page entries with valid bit on 17335 * Step 2: set the timers first/last ilt entry to point 17336 * to the entire range to prevent ILT range error for 3rd/4th 17337 * vnic (this code assumes existence of the vnic) 17338 * 17339 * both steps performed by call to ecore_ilt_client_init_op() 17340 * with dummy TM client 17341 * 17342 * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT 17343 * and his brother are split registers 17344 */ 17345 17346 bxe_pretend_func(sc, (SC_PATH(sc) + 6)); 17347 ecore_ilt_client_init_op_ilt(sc, &ilt, &ilt_cli, INITOP_CLEAR); 17348 bxe_pretend_func(sc, SC_ABS_FUNC(sc)); 17349 17350 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN, BXE_PXP_DRAM_ALIGN); 17351 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN_RD, BXE_PXP_DRAM_ALIGN); 17352 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1); 17353 } 17354 17355 REG_WR(sc, PXP2_REG_RQ_DISABLE_INPUTS, 0); 17356 REG_WR(sc, PXP2_REG_RD_DISABLE_INPUTS, 0); 17357 17358 if (!CHIP_IS_E1x(sc)) { 17359 int factor = CHIP_REV_IS_EMUL(sc) ? 1000 : 17360 (CHIP_REV_IS_FPGA(sc) ? 400 : 0); 17361 17362 ecore_init_block(sc, BLOCK_PGLUE_B, PHASE_COMMON); 17363 ecore_init_block(sc, BLOCK_ATC, PHASE_COMMON); 17364 17365 /* let the HW do it's magic... */ 17366 do { 17367 DELAY(200000); 17368 val = REG_RD(sc, ATC_REG_ATC_INIT_DONE); 17369 } while (factor-- && (val != 1)); 17370 17371 if (val != 1) { 17372 BLOGE(sc, "ATC_INIT failed\n"); 17373 return (-1); 17374 } 17375 } 17376 17377 BLOGD(sc, DBG_LOAD, "after pglue and atc init\n"); 17378 17379 ecore_init_block(sc, BLOCK_DMAE, PHASE_COMMON); 17380 17381 bxe_iov_init_dmae(sc); 17382 17383 /* clean the DMAE memory */ 17384 sc->dmae_ready = 1; 17385 ecore_init_fill(sc, TSEM_REG_PRAM, 0, 8, 1); 17386 17387 ecore_init_block(sc, BLOCK_TCM, PHASE_COMMON); 17388 17389 ecore_init_block(sc, BLOCK_UCM, PHASE_COMMON); 17390 17391 ecore_init_block(sc, BLOCK_CCM, PHASE_COMMON); 17392 17393 ecore_init_block(sc, BLOCK_XCM, PHASE_COMMON); 17394 17395 bxe_read_dmae(sc, XSEM_REG_PASSIVE_BUFFER, 3); 17396 bxe_read_dmae(sc, CSEM_REG_PASSIVE_BUFFER, 3); 17397 bxe_read_dmae(sc, TSEM_REG_PASSIVE_BUFFER, 3); 17398 bxe_read_dmae(sc, USEM_REG_PASSIVE_BUFFER, 3); 17399 17400 ecore_init_block(sc, BLOCK_QM, PHASE_COMMON); 17401 17402 /* QM queues pointers table */ 17403 ecore_qm_init_ptr_table(sc, sc->qm_cid_count, INITOP_SET); 17404 17405 /* soft reset pulse */ 17406 REG_WR(sc, QM_REG_SOFT_RESET, 1); 17407 REG_WR(sc, QM_REG_SOFT_RESET, 0); 17408 17409 if (CNIC_SUPPORT(sc)) 17410 ecore_init_block(sc, BLOCK_TM, PHASE_COMMON); 17411 17412 ecore_init_block(sc, BLOCK_DORQ, PHASE_COMMON); 17413 REG_WR(sc, DORQ_REG_DPM_CID_OFST, BXE_DB_SHIFT); 17414 if (!CHIP_REV_IS_SLOW(sc)) { 17415 /* enable hw interrupt from doorbell Q */ 17416 REG_WR(sc, DORQ_REG_DORQ_INT_MASK, 0); 17417 } 17418 17419 ecore_init_block(sc, BLOCK_BRB1, PHASE_COMMON); 17420 17421 ecore_init_block(sc, BLOCK_PRS, PHASE_COMMON); 17422 REG_WR(sc, PRS_REG_A_PRSU_20, 0xf); 17423 17424 if (!CHIP_IS_E1(sc)) { 17425 REG_WR(sc, PRS_REG_E1HOV_MODE, sc->devinfo.mf_info.path_has_ovlan); 17426 } 17427 17428 if (!CHIP_IS_E1x(sc) && !CHIP_IS_E3B0(sc)) { 17429 if (IS_MF_AFEX(sc)) { 17430 /* 17431 * configure that AFEX and VLAN headers must be 17432 * received in AFEX mode 17433 */ 17434 REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC, 0xE); 17435 REG_WR(sc, PRS_REG_MUST_HAVE_HDRS, 0xA); 17436 REG_WR(sc, PRS_REG_HDRS_AFTER_TAG_0, 0x6); 17437 REG_WR(sc, PRS_REG_TAG_ETHERTYPE_0, 0x8926); 17438 REG_WR(sc, PRS_REG_TAG_LEN_0, 0x4); 17439 } else { 17440 /* 17441 * Bit-map indicating which L2 hdrs may appear 17442 * after the basic Ethernet header 17443 */ 17444 REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC, 17445 sc->devinfo.mf_info.path_has_ovlan ? 7 : 6); 17446 } 17447 } 17448 17449 ecore_init_block(sc, BLOCK_TSDM, PHASE_COMMON); 17450 ecore_init_block(sc, BLOCK_CSDM, PHASE_COMMON); 17451 ecore_init_block(sc, BLOCK_USDM, PHASE_COMMON); 17452 ecore_init_block(sc, BLOCK_XSDM, PHASE_COMMON); 17453 17454 if (!CHIP_IS_E1x(sc)) { 17455 /* reset VFC memories */ 17456 REG_WR(sc, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST, 17457 VFC_MEMORIES_RST_REG_CAM_RST | 17458 VFC_MEMORIES_RST_REG_RAM_RST); 17459 REG_WR(sc, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST, 17460 VFC_MEMORIES_RST_REG_CAM_RST | 17461 VFC_MEMORIES_RST_REG_RAM_RST); 17462 17463 DELAY(20000); 17464 } 17465 17466 ecore_init_block(sc, BLOCK_TSEM, PHASE_COMMON); 17467 ecore_init_block(sc, BLOCK_USEM, PHASE_COMMON); 17468 ecore_init_block(sc, BLOCK_CSEM, PHASE_COMMON); 17469 ecore_init_block(sc, BLOCK_XSEM, PHASE_COMMON); 17470 17471 /* sync semi rtc */ 17472 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 17473 0x80000000); 17474 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 17475 0x80000000); 17476 17477 ecore_init_block(sc, BLOCK_UPB, PHASE_COMMON); 17478 ecore_init_block(sc, BLOCK_XPB, PHASE_COMMON); 17479 ecore_init_block(sc, BLOCK_PBF, PHASE_COMMON); 17480 17481 if (!CHIP_IS_E1x(sc)) { 17482 if (IS_MF_AFEX(sc)) { 17483 /* 17484 * configure that AFEX and VLAN headers must be 17485 * sent in AFEX mode 17486 */ 17487 REG_WR(sc, PBF_REG_HDRS_AFTER_BASIC, 0xE); 17488 REG_WR(sc, PBF_REG_MUST_HAVE_HDRS, 0xA); 17489 REG_WR(sc, PBF_REG_HDRS_AFTER_TAG_0, 0x6); 17490 REG_WR(sc, PBF_REG_TAG_ETHERTYPE_0, 0x8926); 17491 REG_WR(sc, PBF_REG_TAG_LEN_0, 0x4); 17492 } else { 17493 REG_WR(sc, PBF_REG_HDRS_AFTER_BASIC, 17494 sc->devinfo.mf_info.path_has_ovlan ? 7 : 6); 17495 } 17496 } 17497 17498 REG_WR(sc, SRC_REG_SOFT_RST, 1); 17499 17500 ecore_init_block(sc, BLOCK_SRC, PHASE_COMMON); 17501 17502 if (CNIC_SUPPORT(sc)) { 17503 REG_WR(sc, SRC_REG_KEYSEARCH_0, 0x63285672); 17504 REG_WR(sc, SRC_REG_KEYSEARCH_1, 0x24b8f2cc); 17505 REG_WR(sc, SRC_REG_KEYSEARCH_2, 0x223aef9b); 17506 REG_WR(sc, SRC_REG_KEYSEARCH_3, 0x26001e3a); 17507 REG_WR(sc, SRC_REG_KEYSEARCH_4, 0x7ae91116); 17508 REG_WR(sc, SRC_REG_KEYSEARCH_5, 0x5ce5230b); 17509 REG_WR(sc, SRC_REG_KEYSEARCH_6, 0x298d8adf); 17510 REG_WR(sc, SRC_REG_KEYSEARCH_7, 0x6eb0ff09); 17511 REG_WR(sc, SRC_REG_KEYSEARCH_8, 0x1830f82f); 17512 REG_WR(sc, SRC_REG_KEYSEARCH_9, 0x01e46be7); 17513 } 17514 REG_WR(sc, SRC_REG_SOFT_RST, 0); 17515 17516 if (sizeof(union cdu_context) != 1024) { 17517 /* we currently assume that a context is 1024 bytes */ 17518 BLOGE(sc, "please adjust the size of cdu_context(%ld)\n", 17519 (long)sizeof(union cdu_context)); 17520 } 17521 17522 ecore_init_block(sc, BLOCK_CDU, PHASE_COMMON); 17523 val = (4 << 24) + (0 << 12) + 1024; 17524 REG_WR(sc, CDU_REG_CDU_GLOBAL_PARAMS, val); 17525 17526 ecore_init_block(sc, BLOCK_CFC, PHASE_COMMON); 17527 17528 REG_WR(sc, CFC_REG_INIT_REG, 0x7FF); 17529 /* enable context validation interrupt from CFC */ 17530 REG_WR(sc, CFC_REG_CFC_INT_MASK, 0); 17531 17532 /* set the thresholds to prevent CFC/CDU race */ 17533 REG_WR(sc, CFC_REG_DEBUG0, 0x20020000); 17534 ecore_init_block(sc, BLOCK_HC, PHASE_COMMON); 17535 17536 if (!CHIP_IS_E1x(sc) && BXE_NOMCP(sc)) { 17537 REG_WR(sc, IGU_REG_RESET_MEMORIES, 0x36); 17538 } 17539 17540 ecore_init_block(sc, BLOCK_IGU, PHASE_COMMON); 17541 ecore_init_block(sc, BLOCK_MISC_AEU, PHASE_COMMON); 17542 17543 /* Reset PCIE errors for debug */ 17544 REG_WR(sc, 0x2814, 0xffffffff); 17545 REG_WR(sc, 0x3820, 0xffffffff); 17546 17547 if (!CHIP_IS_E1x(sc)) { 17548 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_CONTROL_5, 17549 (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 | 17550 PXPCS_TL_CONTROL_5_ERR_UNSPPORT)); 17551 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT, 17552 (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 | 17553 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 | 17554 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2)); 17555 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT, 17556 (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 | 17557 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 | 17558 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5)); 17559 } 17560 17561 ecore_init_block(sc, BLOCK_NIG, PHASE_COMMON); 17562 17563 if (!CHIP_IS_E1(sc)) { 17564 /* in E3 this done in per-port section */ 17565 if (!CHIP_IS_E3(sc)) 17566 REG_WR(sc, NIG_REG_LLH_MF_MODE, IS_MF(sc)); 17567 } 17568 17569 if (CHIP_IS_E1H(sc)) { 17570 /* not applicable for E2 (and above ...) */ 17571 REG_WR(sc, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(sc)); 17572 } 17573 17574 if (CHIP_REV_IS_SLOW(sc)) { 17575 DELAY(200000); 17576 } 17577 17578 /* finish CFC init */ 17579 val = reg_poll(sc, CFC_REG_LL_INIT_DONE, 1, 100, 10); 17580 if (val != 1) { 17581 BLOGE(sc, "CFC LL_INIT failed\n"); 17582 return (-1); 17583 } 17584 val = reg_poll(sc, CFC_REG_AC_INIT_DONE, 1, 100, 10); 17585 if (val != 1) { 17586 BLOGE(sc, "CFC AC_INIT failed\n"); 17587 return (-1); 17588 } 17589 val = reg_poll(sc, CFC_REG_CAM_INIT_DONE, 1, 100, 10); 17590 if (val != 1) { 17591 BLOGE(sc, "CFC CAM_INIT failed\n"); 17592 return (-1); 17593 } 17594 REG_WR(sc, CFC_REG_DEBUG0, 0); 17595 17596 if (CHIP_IS_E1(sc)) { 17597 /* read NIG statistic to see if this is our first up since powerup */ 17598 bxe_read_dmae(sc, NIG_REG_STAT2_BRB_OCTET, 2); 17599 val = *BXE_SP(sc, wb_data[0]); 17600 17601 /* do internal memory self test */ 17602 if ((val == 0) && bxe_int_mem_test(sc)) { 17603 BLOGE(sc, "internal mem self test failed\n"); 17604 return (-1); 17605 } 17606 } 17607 17608 bxe_setup_fan_failure_detection(sc); 17609 17610 /* clear PXP2 attentions */ 17611 REG_RD(sc, PXP2_REG_PXP2_INT_STS_CLR_0); 17612 17613 bxe_enable_blocks_attention(sc); 17614 17615 if (!CHIP_REV_IS_SLOW(sc)) { 17616 ecore_enable_blocks_parity(sc); 17617 } 17618 17619 if (!BXE_NOMCP(sc)) { 17620 if (CHIP_IS_E1x(sc)) { 17621 bxe_common_init_phy(sc); 17622 } 17623 } 17624 17625 return (0); 17626 } 17627 17628 /** 17629 * bxe_init_hw_common_chip - init HW at the COMMON_CHIP phase. 17630 * 17631 * @sc: driver handle 17632 */ 17633 static int 17634 bxe_init_hw_common_chip(struct bxe_softc *sc) 17635 { 17636 int rc = bxe_init_hw_common(sc); 17637 17638 if (rc) { 17639 return (rc); 17640 } 17641 17642 /* In E2 2-PORT mode, same ext phy is used for the two paths */ 17643 if (!BXE_NOMCP(sc)) { 17644 bxe_common_init_phy(sc); 17645 } 17646 17647 return (0); 17648 } 17649 17650 static int 17651 bxe_init_hw_port(struct bxe_softc *sc) 17652 { 17653 int port = SC_PORT(sc); 17654 int init_phase = port ? PHASE_PORT1 : PHASE_PORT0; 17655 uint32_t low, high; 17656 uint32_t val; 17657 17658 BLOGD(sc, DBG_LOAD, "starting port init for port %d\n", port); 17659 17660 REG_WR(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0); 17661 17662 ecore_init_block(sc, BLOCK_MISC, init_phase); 17663 ecore_init_block(sc, BLOCK_PXP, init_phase); 17664 ecore_init_block(sc, BLOCK_PXP2, init_phase); 17665 17666 /* 17667 * Timers bug workaround: disables the pf_master bit in pglue at 17668 * common phase, we need to enable it here before any dmae access are 17669 * attempted. Therefore we manually added the enable-master to the 17670 * port phase (it also happens in the function phase) 17671 */ 17672 if (!CHIP_IS_E1x(sc)) { 17673 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); 17674 } 17675 17676 ecore_init_block(sc, BLOCK_ATC, init_phase); 17677 ecore_init_block(sc, BLOCK_DMAE, init_phase); 17678 ecore_init_block(sc, BLOCK_PGLUE_B, init_phase); 17679 ecore_init_block(sc, BLOCK_QM, init_phase); 17680 17681 ecore_init_block(sc, BLOCK_TCM, init_phase); 17682 ecore_init_block(sc, BLOCK_UCM, init_phase); 17683 ecore_init_block(sc, BLOCK_CCM, init_phase); 17684 ecore_init_block(sc, BLOCK_XCM, init_phase); 17685 17686 /* QM cid (connection) count */ 17687 ecore_qm_init_cid_count(sc, sc->qm_cid_count, INITOP_SET); 17688 17689 if (CNIC_SUPPORT(sc)) { 17690 ecore_init_block(sc, BLOCK_TM, init_phase); 17691 REG_WR(sc, TM_REG_LIN0_SCAN_TIME + port*4, 20); 17692 REG_WR(sc, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31); 17693 } 17694 17695 ecore_init_block(sc, BLOCK_DORQ, init_phase); 17696 17697 ecore_init_block(sc, BLOCK_BRB1, init_phase); 17698 17699 if (CHIP_IS_E1(sc) || CHIP_IS_E1H(sc)) { 17700 if (IS_MF(sc)) { 17701 low = (BXE_ONE_PORT(sc) ? 160 : 246); 17702 } else if (sc->mtu > 4096) { 17703 if (BXE_ONE_PORT(sc)) { 17704 low = 160; 17705 } else { 17706 val = sc->mtu; 17707 /* (24*1024 + val*4)/256 */ 17708 low = (96 + (val / 64) + ((val % 64) ? 1 : 0)); 17709 } 17710 } else { 17711 low = (BXE_ONE_PORT(sc) ? 80 : 160); 17712 } 17713 high = (low + 56); /* 14*1024/256 */ 17714 REG_WR(sc, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low); 17715 REG_WR(sc, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high); 17716 } 17717 17718 if (CHIP_IS_MODE_4_PORT(sc)) { 17719 REG_WR(sc, SC_PORT(sc) ? 17720 BRB1_REG_MAC_GUARANTIED_1 : 17721 BRB1_REG_MAC_GUARANTIED_0, 40); 17722 } 17723 17724 ecore_init_block(sc, BLOCK_PRS, init_phase); 17725 if (CHIP_IS_E3B0(sc)) { 17726 if (IS_MF_AFEX(sc)) { 17727 /* configure headers for AFEX mode */ 17728 REG_WR(sc, SC_PORT(sc) ? 17729 PRS_REG_HDRS_AFTER_BASIC_PORT_1 : 17730 PRS_REG_HDRS_AFTER_BASIC_PORT_0, 0xE); 17731 REG_WR(sc, SC_PORT(sc) ? 17732 PRS_REG_HDRS_AFTER_TAG_0_PORT_1 : 17733 PRS_REG_HDRS_AFTER_TAG_0_PORT_0, 0x6); 17734 REG_WR(sc, SC_PORT(sc) ? 17735 PRS_REG_MUST_HAVE_HDRS_PORT_1 : 17736 PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA); 17737 } else { 17738 /* Ovlan exists only if we are in multi-function + 17739 * switch-dependent mode, in switch-independent there 17740 * is no ovlan headers 17741 */ 17742 REG_WR(sc, SC_PORT(sc) ? 17743 PRS_REG_HDRS_AFTER_BASIC_PORT_1 : 17744 PRS_REG_HDRS_AFTER_BASIC_PORT_0, 17745 (sc->devinfo.mf_info.path_has_ovlan ? 7 : 6)); 17746 } 17747 } 17748 17749 ecore_init_block(sc, BLOCK_TSDM, init_phase); 17750 ecore_init_block(sc, BLOCK_CSDM, init_phase); 17751 ecore_init_block(sc, BLOCK_USDM, init_phase); 17752 ecore_init_block(sc, BLOCK_XSDM, init_phase); 17753 17754 ecore_init_block(sc, BLOCK_TSEM, init_phase); 17755 ecore_init_block(sc, BLOCK_USEM, init_phase); 17756 ecore_init_block(sc, BLOCK_CSEM, init_phase); 17757 ecore_init_block(sc, BLOCK_XSEM, init_phase); 17758 17759 ecore_init_block(sc, BLOCK_UPB, init_phase); 17760 ecore_init_block(sc, BLOCK_XPB, init_phase); 17761 17762 ecore_init_block(sc, BLOCK_PBF, init_phase); 17763 17764 if (CHIP_IS_E1x(sc)) { 17765 /* configure PBF to work without PAUSE mtu 9000 */ 17766 REG_WR(sc, PBF_REG_P0_PAUSE_ENABLE + port*4, 0); 17767 17768 /* update threshold */ 17769 REG_WR(sc, PBF_REG_P0_ARB_THRSH + port*4, (9040/16)); 17770 /* update init credit */ 17771 REG_WR(sc, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22); 17772 17773 /* probe changes */ 17774 REG_WR(sc, PBF_REG_INIT_P0 + port*4, 1); 17775 DELAY(50); 17776 REG_WR(sc, PBF_REG_INIT_P0 + port*4, 0); 17777 } 17778 17779 if (CNIC_SUPPORT(sc)) { 17780 ecore_init_block(sc, BLOCK_SRC, init_phase); 17781 } 17782 17783 ecore_init_block(sc, BLOCK_CDU, init_phase); 17784 ecore_init_block(sc, BLOCK_CFC, init_phase); 17785 17786 if (CHIP_IS_E1(sc)) { 17787 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port*8, 0); 17788 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port*8, 0); 17789 } 17790 ecore_init_block(sc, BLOCK_HC, init_phase); 17791 17792 ecore_init_block(sc, BLOCK_IGU, init_phase); 17793 17794 ecore_init_block(sc, BLOCK_MISC_AEU, init_phase); 17795 /* init aeu_mask_attn_func_0/1: 17796 * - SF mode: bits 3-7 are masked. only bits 0-2 are in use 17797 * - MF mode: bit 3 is masked. bits 0-2 are in use as in SF 17798 * bits 4-7 are used for "per vn group attention" */ 17799 val = IS_MF(sc) ? 0xF7 : 0x7; 17800 /* Enable DCBX attention for all but E1 */ 17801 val |= CHIP_IS_E1(sc) ? 0 : 0x10; 17802 REG_WR(sc, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val); 17803 17804 ecore_init_block(sc, BLOCK_NIG, init_phase); 17805 17806 if (!CHIP_IS_E1x(sc)) { 17807 /* Bit-map indicating which L2 hdrs may appear after the 17808 * basic Ethernet header 17809 */ 17810 if (IS_MF_AFEX(sc)) { 17811 REG_WR(sc, SC_PORT(sc) ? 17812 NIG_REG_P1_HDRS_AFTER_BASIC : 17813 NIG_REG_P0_HDRS_AFTER_BASIC, 0xE); 17814 } else { 17815 REG_WR(sc, SC_PORT(sc) ? 17816 NIG_REG_P1_HDRS_AFTER_BASIC : 17817 NIG_REG_P0_HDRS_AFTER_BASIC, 17818 IS_MF_SD(sc) ? 7 : 6); 17819 } 17820 17821 if (CHIP_IS_E3(sc)) { 17822 REG_WR(sc, SC_PORT(sc) ? 17823 NIG_REG_LLH1_MF_MODE : 17824 NIG_REG_LLH_MF_MODE, IS_MF(sc)); 17825 } 17826 } 17827 if (!CHIP_IS_E3(sc)) { 17828 REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1); 17829 } 17830 17831 if (!CHIP_IS_E1(sc)) { 17832 /* 0x2 disable mf_ov, 0x1 enable */ 17833 REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4, 17834 (IS_MF_SD(sc) ? 0x1 : 0x2)); 17835 17836 if (!CHIP_IS_E1x(sc)) { 17837 val = 0; 17838 switch (sc->devinfo.mf_info.mf_mode) { 17839 case MULTI_FUNCTION_SD: 17840 val = 1; 17841 break; 17842 case MULTI_FUNCTION_SI: 17843 case MULTI_FUNCTION_AFEX: 17844 val = 2; 17845 break; 17846 } 17847 17848 REG_WR(sc, (SC_PORT(sc) ? NIG_REG_LLH1_CLS_TYPE : 17849 NIG_REG_LLH0_CLS_TYPE), val); 17850 } 17851 REG_WR(sc, NIG_REG_LLFC_ENABLE_0 + port*4, 0); 17852 REG_WR(sc, NIG_REG_LLFC_OUT_EN_0 + port*4, 0); 17853 REG_WR(sc, NIG_REG_PAUSE_ENABLE_0 + port*4, 1); 17854 } 17855 17856 /* If SPIO5 is set to generate interrupts, enable it for this port */ 17857 val = REG_RD(sc, MISC_REG_SPIO_EVENT_EN); 17858 if (val & MISC_SPIO_SPIO5) { 17859 uint32_t reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : 17860 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); 17861 val = REG_RD(sc, reg_addr); 17862 val |= AEU_INPUTS_ATTN_BITS_SPIO5; 17863 REG_WR(sc, reg_addr, val); 17864 } 17865 17866 return (0); 17867 } 17868 17869 static uint32_t 17870 bxe_flr_clnup_reg_poll(struct bxe_softc *sc, 17871 uint32_t reg, 17872 uint32_t expected, 17873 uint32_t poll_count) 17874 { 17875 uint32_t cur_cnt = poll_count; 17876 uint32_t val; 17877 17878 while ((val = REG_RD(sc, reg)) != expected && cur_cnt--) { 17879 DELAY(FLR_WAIT_INTERVAL); 17880 } 17881 17882 return (val); 17883 } 17884 17885 static int 17886 bxe_flr_clnup_poll_hw_counter(struct bxe_softc *sc, 17887 uint32_t reg, 17888 char *msg, 17889 uint32_t poll_cnt) 17890 { 17891 uint32_t val = bxe_flr_clnup_reg_poll(sc, reg, 0, poll_cnt); 17892 17893 if (val != 0) { 17894 BLOGE(sc, "%s usage count=%d\n", msg, val); 17895 return (1); 17896 } 17897 17898 return (0); 17899 } 17900 17901 /* Common routines with VF FLR cleanup */ 17902 static uint32_t 17903 bxe_flr_clnup_poll_count(struct bxe_softc *sc) 17904 { 17905 /* adjust polling timeout */ 17906 if (CHIP_REV_IS_EMUL(sc)) { 17907 return (FLR_POLL_CNT * 2000); 17908 } 17909 17910 if (CHIP_REV_IS_FPGA(sc)) { 17911 return (FLR_POLL_CNT * 120); 17912 } 17913 17914 return (FLR_POLL_CNT); 17915 } 17916 17917 static int 17918 bxe_poll_hw_usage_counters(struct bxe_softc *sc, 17919 uint32_t poll_cnt) 17920 { 17921 /* wait for CFC PF usage-counter to zero (includes all the VFs) */ 17922 if (bxe_flr_clnup_poll_hw_counter(sc, 17923 CFC_REG_NUM_LCIDS_INSIDE_PF, 17924 "CFC PF usage counter timed out", 17925 poll_cnt)) { 17926 return (1); 17927 } 17928 17929 /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */ 17930 if (bxe_flr_clnup_poll_hw_counter(sc, 17931 DORQ_REG_PF_USAGE_CNT, 17932 "DQ PF usage counter timed out", 17933 poll_cnt)) { 17934 return (1); 17935 } 17936 17937 /* Wait for QM PF usage-counter to zero (until DQ cleanup) */ 17938 if (bxe_flr_clnup_poll_hw_counter(sc, 17939 QM_REG_PF_USG_CNT_0 + 4*SC_FUNC(sc), 17940 "QM PF usage counter timed out", 17941 poll_cnt)) { 17942 return (1); 17943 } 17944 17945 /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */ 17946 if (bxe_flr_clnup_poll_hw_counter(sc, 17947 TM_REG_LIN0_VNIC_UC + 4*SC_PORT(sc), 17948 "Timers VNIC usage counter timed out", 17949 poll_cnt)) { 17950 return (1); 17951 } 17952 17953 if (bxe_flr_clnup_poll_hw_counter(sc, 17954 TM_REG_LIN0_NUM_SCANS + 4*SC_PORT(sc), 17955 "Timers NUM_SCANS usage counter timed out", 17956 poll_cnt)) { 17957 return (1); 17958 } 17959 17960 /* Wait DMAE PF usage counter to zero */ 17961 if (bxe_flr_clnup_poll_hw_counter(sc, 17962 dmae_reg_go_c[INIT_DMAE_C(sc)], 17963 "DMAE dommand register timed out", 17964 poll_cnt)) { 17965 return (1); 17966 } 17967 17968 return (0); 17969 } 17970 17971 #define OP_GEN_PARAM(param) \ 17972 (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM) 17973 #define OP_GEN_TYPE(type) \ 17974 (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE) 17975 #define OP_GEN_AGG_VECT(index) \ 17976 (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX) 17977 17978 static int 17979 bxe_send_final_clnup(struct bxe_softc *sc, 17980 uint8_t clnup_func, 17981 uint32_t poll_cnt) 17982 { 17983 uint32_t op_gen_command = 0; 17984 uint32_t comp_addr = (BAR_CSTRORM_INTMEM + 17985 CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func)); 17986 int ret = 0; 17987 17988 if (REG_RD(sc, comp_addr)) { 17989 BLOGE(sc, "Cleanup complete was not 0 before sending\n"); 17990 return (1); 17991 } 17992 17993 op_gen_command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX); 17994 op_gen_command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE); 17995 op_gen_command |= OP_GEN_AGG_VECT(clnup_func); 17996 op_gen_command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT; 17997 17998 BLOGD(sc, DBG_LOAD, "sending FW Final cleanup\n"); 17999 REG_WR(sc, XSDM_REG_OPERATION_GEN, op_gen_command); 18000 18001 if (bxe_flr_clnup_reg_poll(sc, comp_addr, 1, poll_cnt) != 1) { 18002 BLOGE(sc, "FW final cleanup did not succeed\n"); 18003 BLOGD(sc, DBG_LOAD, "At timeout completion address contained %x\n", 18004 (REG_RD(sc, comp_addr))); 18005 bxe_panic(sc, ("FLR cleanup failed\n")); 18006 return (1); 18007 } 18008 18009 /* Zero completion for nxt FLR */ 18010 REG_WR(sc, comp_addr, 0); 18011 18012 return (ret); 18013 } 18014 18015 static void 18016 bxe_pbf_pN_buf_flushed(struct bxe_softc *sc, 18017 struct pbf_pN_buf_regs *regs, 18018 uint32_t poll_count) 18019 { 18020 uint32_t init_crd, crd, crd_start, crd_freed, crd_freed_start; 18021 uint32_t cur_cnt = poll_count; 18022 18023 crd_freed = crd_freed_start = REG_RD(sc, regs->crd_freed); 18024 crd = crd_start = REG_RD(sc, regs->crd); 18025 init_crd = REG_RD(sc, regs->init_crd); 18026 18027 BLOGD(sc, DBG_LOAD, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd); 18028 BLOGD(sc, DBG_LOAD, "CREDIT[%d] : s:%x\n", regs->pN, crd); 18029 BLOGD(sc, DBG_LOAD, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed); 18030 18031 while ((crd != init_crd) && 18032 ((uint32_t)((int32_t)crd_freed - (int32_t)crd_freed_start) < 18033 (init_crd - crd_start))) { 18034 if (cur_cnt--) { 18035 DELAY(FLR_WAIT_INTERVAL); 18036 crd = REG_RD(sc, regs->crd); 18037 crd_freed = REG_RD(sc, regs->crd_freed); 18038 } else { 18039 BLOGD(sc, DBG_LOAD, "PBF tx buffer[%d] timed out\n", regs->pN); 18040 BLOGD(sc, DBG_LOAD, "CREDIT[%d] : c:%x\n", regs->pN, crd); 18041 BLOGD(sc, DBG_LOAD, "CREDIT_FREED[%d]: c:%x\n", regs->pN, crd_freed); 18042 break; 18043 } 18044 } 18045 18046 BLOGD(sc, DBG_LOAD, "Waited %d*%d usec for PBF tx buffer[%d]\n", 18047 poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN); 18048 } 18049 18050 static void 18051 bxe_pbf_pN_cmd_flushed(struct bxe_softc *sc, 18052 struct pbf_pN_cmd_regs *regs, 18053 uint32_t poll_count) 18054 { 18055 uint32_t occup, to_free, freed, freed_start; 18056 uint32_t cur_cnt = poll_count; 18057 18058 occup = to_free = REG_RD(sc, regs->lines_occup); 18059 freed = freed_start = REG_RD(sc, regs->lines_freed); 18060 18061 BLOGD(sc, DBG_LOAD, "OCCUPANCY[%d] : s:%x\n", regs->pN, occup); 18062 BLOGD(sc, DBG_LOAD, "LINES_FREED[%d] : s:%x\n", regs->pN, freed); 18063 18064 while (occup && 18065 ((uint32_t)((int32_t)freed - (int32_t)freed_start) < to_free)) { 18066 if (cur_cnt--) { 18067 DELAY(FLR_WAIT_INTERVAL); 18068 occup = REG_RD(sc, regs->lines_occup); 18069 freed = REG_RD(sc, regs->lines_freed); 18070 } else { 18071 BLOGD(sc, DBG_LOAD, "PBF cmd queue[%d] timed out\n", regs->pN); 18072 BLOGD(sc, DBG_LOAD, "OCCUPANCY[%d] : s:%x\n", regs->pN, occup); 18073 BLOGD(sc, DBG_LOAD, "LINES_FREED[%d] : s:%x\n", regs->pN, freed); 18074 break; 18075 } 18076 } 18077 18078 BLOGD(sc, DBG_LOAD, "Waited %d*%d usec for PBF cmd queue[%d]\n", 18079 poll_count - cur_cnt, FLR_WAIT_INTERVAL, regs->pN); 18080 } 18081 18082 static void 18083 bxe_tx_hw_flushed(struct bxe_softc *sc, uint32_t poll_count) 18084 { 18085 struct pbf_pN_cmd_regs cmd_regs[] = { 18086 {0, (CHIP_IS_E3B0(sc)) ? 18087 PBF_REG_TQ_OCCUPANCY_Q0 : 18088 PBF_REG_P0_TQ_OCCUPANCY, 18089 (CHIP_IS_E3B0(sc)) ? 18090 PBF_REG_TQ_LINES_FREED_CNT_Q0 : 18091 PBF_REG_P0_TQ_LINES_FREED_CNT}, 18092 {1, (CHIP_IS_E3B0(sc)) ? 18093 PBF_REG_TQ_OCCUPANCY_Q1 : 18094 PBF_REG_P1_TQ_OCCUPANCY, 18095 (CHIP_IS_E3B0(sc)) ? 18096 PBF_REG_TQ_LINES_FREED_CNT_Q1 : 18097 PBF_REG_P1_TQ_LINES_FREED_CNT}, 18098 {4, (CHIP_IS_E3B0(sc)) ? 18099 PBF_REG_TQ_OCCUPANCY_LB_Q : 18100 PBF_REG_P4_TQ_OCCUPANCY, 18101 (CHIP_IS_E3B0(sc)) ? 18102 PBF_REG_TQ_LINES_FREED_CNT_LB_Q : 18103 PBF_REG_P4_TQ_LINES_FREED_CNT} 18104 }; 18105 18106 struct pbf_pN_buf_regs buf_regs[] = { 18107 {0, (CHIP_IS_E3B0(sc)) ? 18108 PBF_REG_INIT_CRD_Q0 : 18109 PBF_REG_P0_INIT_CRD , 18110 (CHIP_IS_E3B0(sc)) ? 18111 PBF_REG_CREDIT_Q0 : 18112 PBF_REG_P0_CREDIT, 18113 (CHIP_IS_E3B0(sc)) ? 18114 PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 : 18115 PBF_REG_P0_INTERNAL_CRD_FREED_CNT}, 18116 {1, (CHIP_IS_E3B0(sc)) ? 18117 PBF_REG_INIT_CRD_Q1 : 18118 PBF_REG_P1_INIT_CRD, 18119 (CHIP_IS_E3B0(sc)) ? 18120 PBF_REG_CREDIT_Q1 : 18121 PBF_REG_P1_CREDIT, 18122 (CHIP_IS_E3B0(sc)) ? 18123 PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 : 18124 PBF_REG_P1_INTERNAL_CRD_FREED_CNT}, 18125 {4, (CHIP_IS_E3B0(sc)) ? 18126 PBF_REG_INIT_CRD_LB_Q : 18127 PBF_REG_P4_INIT_CRD, 18128 (CHIP_IS_E3B0(sc)) ? 18129 PBF_REG_CREDIT_LB_Q : 18130 PBF_REG_P4_CREDIT, 18131 (CHIP_IS_E3B0(sc)) ? 18132 PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q : 18133 PBF_REG_P4_INTERNAL_CRD_FREED_CNT}, 18134 }; 18135 18136 int i; 18137 18138 /* Verify the command queues are flushed P0, P1, P4 */ 18139 for (i = 0; i < ARRAY_SIZE(cmd_regs); i++) { 18140 bxe_pbf_pN_cmd_flushed(sc, &cmd_regs[i], poll_count); 18141 } 18142 18143 /* Verify the transmission buffers are flushed P0, P1, P4 */ 18144 for (i = 0; i < ARRAY_SIZE(buf_regs); i++) { 18145 bxe_pbf_pN_buf_flushed(sc, &buf_regs[i], poll_count); 18146 } 18147 } 18148 18149 static void 18150 bxe_hw_enable_status(struct bxe_softc *sc) 18151 { 18152 uint32_t val; 18153 18154 val = REG_RD(sc, CFC_REG_WEAK_ENABLE_PF); 18155 BLOGD(sc, DBG_LOAD, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val); 18156 18157 val = REG_RD(sc, PBF_REG_DISABLE_PF); 18158 BLOGD(sc, DBG_LOAD, "PBF_REG_DISABLE_PF is 0x%x\n", val); 18159 18160 val = REG_RD(sc, IGU_REG_PCI_PF_MSI_EN); 18161 BLOGD(sc, DBG_LOAD, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val); 18162 18163 val = REG_RD(sc, IGU_REG_PCI_PF_MSIX_EN); 18164 BLOGD(sc, DBG_LOAD, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val); 18165 18166 val = REG_RD(sc, IGU_REG_PCI_PF_MSIX_FUNC_MASK); 18167 BLOGD(sc, DBG_LOAD, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val); 18168 18169 val = REG_RD(sc, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR); 18170 BLOGD(sc, DBG_LOAD, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val); 18171 18172 val = REG_RD(sc, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR); 18173 BLOGD(sc, DBG_LOAD, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val); 18174 18175 val = REG_RD(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER); 18176 BLOGD(sc, DBG_LOAD, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n", val); 18177 } 18178 18179 static int 18180 bxe_pf_flr_clnup(struct bxe_softc *sc) 18181 { 18182 uint32_t poll_cnt = bxe_flr_clnup_poll_count(sc); 18183 18184 BLOGD(sc, DBG_LOAD, "Cleanup after FLR PF[%d]\n", SC_ABS_FUNC(sc)); 18185 18186 /* Re-enable PF target read access */ 18187 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1); 18188 18189 /* Poll HW usage counters */ 18190 BLOGD(sc, DBG_LOAD, "Polling usage counters\n"); 18191 if (bxe_poll_hw_usage_counters(sc, poll_cnt)) { 18192 return (-1); 18193 } 18194 18195 /* Zero the igu 'trailing edge' and 'leading edge' */ 18196 18197 /* Send the FW cleanup command */ 18198 if (bxe_send_final_clnup(sc, (uint8_t)SC_FUNC(sc), poll_cnt)) { 18199 return (-1); 18200 } 18201 18202 /* ATC cleanup */ 18203 18204 /* Verify TX hw is flushed */ 18205 bxe_tx_hw_flushed(sc, poll_cnt); 18206 18207 /* Wait 100ms (not adjusted according to platform) */ 18208 DELAY(100000); 18209 18210 /* Verify no pending pci transactions */ 18211 if (bxe_is_pcie_pending(sc)) { 18212 BLOGE(sc, "PCIE Transactions still pending\n"); 18213 } 18214 18215 /* Debug */ 18216 bxe_hw_enable_status(sc); 18217 18218 /* 18219 * Master enable - Due to WB DMAE writes performed before this 18220 * register is re-initialized as part of the regular function init 18221 */ 18222 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); 18223 18224 return (0); 18225 } 18226 18227 #if 0 18228 static void 18229 bxe_init_searcher(struct bxe_softc *sc) 18230 { 18231 int port = SC_PORT(sc); 18232 ecore_src_init_t2(sc, sc->t2, sc->t2_mapping, SRC_CONN_NUM); 18233 /* T1 hash bits value determines the T1 number of entries */ 18234 REG_WR(sc, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS); 18235 } 18236 #endif 18237 18238 static int 18239 bxe_init_hw_func(struct bxe_softc *sc) 18240 { 18241 int port = SC_PORT(sc); 18242 int func = SC_FUNC(sc); 18243 int init_phase = PHASE_PF0 + func; 18244 struct ecore_ilt *ilt = sc->ilt; 18245 uint16_t cdu_ilt_start; 18246 uint32_t addr, val; 18247 uint32_t main_mem_base, main_mem_size, main_mem_prty_clr; 18248 int i, main_mem_width, rc; 18249 18250 BLOGD(sc, DBG_LOAD, "starting func init for func %d\n", func); 18251 18252 /* FLR cleanup */ 18253 if (!CHIP_IS_E1x(sc)) { 18254 rc = bxe_pf_flr_clnup(sc); 18255 if (rc) { 18256 BLOGE(sc, "FLR cleanup failed!\n"); 18257 // XXX bxe_fw_dump(sc); 18258 // XXX bxe_idle_chk(sc); 18259 return (rc); 18260 } 18261 } 18262 18263 /* set MSI reconfigure capability */ 18264 if (sc->devinfo.int_block == INT_BLOCK_HC) { 18265 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0); 18266 val = REG_RD(sc, addr); 18267 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0; 18268 REG_WR(sc, addr, val); 18269 } 18270 18271 ecore_init_block(sc, BLOCK_PXP, init_phase); 18272 ecore_init_block(sc, BLOCK_PXP2, init_phase); 18273 18274 ilt = sc->ilt; 18275 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start; 18276 18277 #if 0 18278 if (IS_SRIOV(sc)) { 18279 cdu_ilt_start += BXE_FIRST_VF_CID/ILT_PAGE_CIDS; 18280 } 18281 cdu_ilt_start = bxe_iov_init_ilt(sc, cdu_ilt_start); 18282 18283 #if (BXE_FIRST_VF_CID > 0) 18284 /* 18285 * If BXE_FIRST_VF_CID > 0 then the PF L2 cids precedes 18286 * those of the VFs, so start line should be reset 18287 */ 18288 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start; 18289 #endif 18290 #endif 18291 18292 for (i = 0; i < L2_ILT_LINES(sc); i++) { 18293 ilt->lines[cdu_ilt_start + i].page = sc->context[i].vcxt; 18294 ilt->lines[cdu_ilt_start + i].page_mapping = 18295 sc->context[i].vcxt_dma.paddr; 18296 ilt->lines[cdu_ilt_start + i].size = sc->context[i].size; 18297 } 18298 ecore_ilt_init_op(sc, INITOP_SET); 18299 18300 #if 0 18301 if (!CONFIGURE_NIC_MODE(sc)) { 18302 bxe_init_searcher(sc); 18303 REG_WR(sc, PRS_REG_NIC_MODE, 0); 18304 BLOGD(sc, DBG_LOAD, "NIC MODE disabled\n"); 18305 } else 18306 #endif 18307 { 18308 /* Set NIC mode */ 18309 REG_WR(sc, PRS_REG_NIC_MODE, 1); 18310 BLOGD(sc, DBG_LOAD, "NIC MODE configured\n"); 18311 } 18312 18313 if (!CHIP_IS_E1x(sc)) { 18314 uint32_t pf_conf = IGU_PF_CONF_FUNC_EN; 18315 18316 /* Turn on a single ISR mode in IGU if driver is going to use 18317 * INT#x or MSI 18318 */ 18319 if (sc->interrupt_mode != INTR_MODE_MSIX) { 18320 pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN; 18321 } 18322 18323 /* 18324 * Timers workaround bug: function init part. 18325 * Need to wait 20msec after initializing ILT, 18326 * needed to make sure there are no requests in 18327 * one of the PXP internal queues with "old" ILT addresses 18328 */ 18329 DELAY(20000); 18330 18331 /* 18332 * Master enable - Due to WB DMAE writes performed before this 18333 * register is re-initialized as part of the regular function 18334 * init 18335 */ 18336 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); 18337 /* Enable the function in IGU */ 18338 REG_WR(sc, IGU_REG_PF_CONFIGURATION, pf_conf); 18339 } 18340 18341 sc->dmae_ready = 1; 18342 18343 ecore_init_block(sc, BLOCK_PGLUE_B, init_phase); 18344 18345 if (!CHIP_IS_E1x(sc)) 18346 REG_WR(sc, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func); 18347 18348 ecore_init_block(sc, BLOCK_ATC, init_phase); 18349 ecore_init_block(sc, BLOCK_DMAE, init_phase); 18350 ecore_init_block(sc, BLOCK_NIG, init_phase); 18351 ecore_init_block(sc, BLOCK_SRC, init_phase); 18352 ecore_init_block(sc, BLOCK_MISC, init_phase); 18353 ecore_init_block(sc, BLOCK_TCM, init_phase); 18354 ecore_init_block(sc, BLOCK_UCM, init_phase); 18355 ecore_init_block(sc, BLOCK_CCM, init_phase); 18356 ecore_init_block(sc, BLOCK_XCM, init_phase); 18357 ecore_init_block(sc, BLOCK_TSEM, init_phase); 18358 ecore_init_block(sc, BLOCK_USEM, init_phase); 18359 ecore_init_block(sc, BLOCK_CSEM, init_phase); 18360 ecore_init_block(sc, BLOCK_XSEM, init_phase); 18361 18362 if (!CHIP_IS_E1x(sc)) 18363 REG_WR(sc, QM_REG_PF_EN, 1); 18364 18365 if (!CHIP_IS_E1x(sc)) { 18366 REG_WR(sc, TSEM_REG_VFPF_ERR_NUM, BXE_MAX_NUM_OF_VFS + func); 18367 REG_WR(sc, USEM_REG_VFPF_ERR_NUM, BXE_MAX_NUM_OF_VFS + func); 18368 REG_WR(sc, CSEM_REG_VFPF_ERR_NUM, BXE_MAX_NUM_OF_VFS + func); 18369 REG_WR(sc, XSEM_REG_VFPF_ERR_NUM, BXE_MAX_NUM_OF_VFS + func); 18370 } 18371 ecore_init_block(sc, BLOCK_QM, init_phase); 18372 18373 ecore_init_block(sc, BLOCK_TM, init_phase); 18374 ecore_init_block(sc, BLOCK_DORQ, init_phase); 18375 18376 bxe_iov_init_dq(sc); 18377 18378 ecore_init_block(sc, BLOCK_BRB1, init_phase); 18379 ecore_init_block(sc, BLOCK_PRS, init_phase); 18380 ecore_init_block(sc, BLOCK_TSDM, init_phase); 18381 ecore_init_block(sc, BLOCK_CSDM, init_phase); 18382 ecore_init_block(sc, BLOCK_USDM, init_phase); 18383 ecore_init_block(sc, BLOCK_XSDM, init_phase); 18384 ecore_init_block(sc, BLOCK_UPB, init_phase); 18385 ecore_init_block(sc, BLOCK_XPB, init_phase); 18386 ecore_init_block(sc, BLOCK_PBF, init_phase); 18387 if (!CHIP_IS_E1x(sc)) 18388 REG_WR(sc, PBF_REG_DISABLE_PF, 0); 18389 18390 ecore_init_block(sc, BLOCK_CDU, init_phase); 18391 18392 ecore_init_block(sc, BLOCK_CFC, init_phase); 18393 18394 if (!CHIP_IS_E1x(sc)) 18395 REG_WR(sc, CFC_REG_WEAK_ENABLE_PF, 1); 18396 18397 if (IS_MF(sc)) { 18398 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port*8, 1); 18399 REG_WR(sc, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, OVLAN(sc)); 18400 } 18401 18402 ecore_init_block(sc, BLOCK_MISC_AEU, init_phase); 18403 18404 /* HC init per function */ 18405 if (sc->devinfo.int_block == INT_BLOCK_HC) { 18406 if (CHIP_IS_E1H(sc)) { 18407 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); 18408 18409 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port*8, 0); 18410 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port*8, 0); 18411 } 18412 ecore_init_block(sc, BLOCK_HC, init_phase); 18413 18414 } else { 18415 int num_segs, sb_idx, prod_offset; 18416 18417 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); 18418 18419 if (!CHIP_IS_E1x(sc)) { 18420 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, 0); 18421 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, 0); 18422 } 18423 18424 ecore_init_block(sc, BLOCK_IGU, init_phase); 18425 18426 if (!CHIP_IS_E1x(sc)) { 18427 int dsb_idx = 0; 18428 /** 18429 * Producer memory: 18430 * E2 mode: address 0-135 match to the mapping memory; 18431 * 136 - PF0 default prod; 137 - PF1 default prod; 18432 * 138 - PF2 default prod; 139 - PF3 default prod; 18433 * 140 - PF0 attn prod; 141 - PF1 attn prod; 18434 * 142 - PF2 attn prod; 143 - PF3 attn prod; 18435 * 144-147 reserved. 18436 * 18437 * E1.5 mode - In backward compatible mode; 18438 * for non default SB; each even line in the memory 18439 * holds the U producer and each odd line hold 18440 * the C producer. The first 128 producers are for 18441 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20 18442 * producers are for the DSB for each PF. 18443 * Each PF has five segments: (the order inside each 18444 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods; 18445 * 132-135 C prods; 136-139 X prods; 140-143 T prods; 18446 * 144-147 attn prods; 18447 */ 18448 /* non-default-status-blocks */ 18449 num_segs = CHIP_INT_MODE_IS_BC(sc) ? 18450 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS; 18451 for (sb_idx = 0; sb_idx < sc->igu_sb_cnt; sb_idx++) { 18452 prod_offset = (sc->igu_base_sb + sb_idx) * 18453 num_segs; 18454 18455 for (i = 0; i < num_segs; i++) { 18456 addr = IGU_REG_PROD_CONS_MEMORY + 18457 (prod_offset + i) * 4; 18458 REG_WR(sc, addr, 0); 18459 } 18460 /* send consumer update with value 0 */ 18461 bxe_ack_sb(sc, sc->igu_base_sb + sb_idx, 18462 USTORM_ID, 0, IGU_INT_NOP, 1); 18463 bxe_igu_clear_sb(sc, sc->igu_base_sb + sb_idx); 18464 } 18465 18466 /* default-status-blocks */ 18467 num_segs = CHIP_INT_MODE_IS_BC(sc) ? 18468 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS; 18469 18470 if (CHIP_IS_MODE_4_PORT(sc)) 18471 dsb_idx = SC_FUNC(sc); 18472 else 18473 dsb_idx = SC_VN(sc); 18474 18475 prod_offset = (CHIP_INT_MODE_IS_BC(sc) ? 18476 IGU_BC_BASE_DSB_PROD + dsb_idx : 18477 IGU_NORM_BASE_DSB_PROD + dsb_idx); 18478 18479 /* 18480 * igu prods come in chunks of E1HVN_MAX (4) - 18481 * does not matters what is the current chip mode 18482 */ 18483 for (i = 0; i < (num_segs * E1HVN_MAX); 18484 i += E1HVN_MAX) { 18485 addr = IGU_REG_PROD_CONS_MEMORY + 18486 (prod_offset + i)*4; 18487 REG_WR(sc, addr, 0); 18488 } 18489 /* send consumer update with 0 */ 18490 if (CHIP_INT_MODE_IS_BC(sc)) { 18491 bxe_ack_sb(sc, sc->igu_dsb_id, 18492 USTORM_ID, 0, IGU_INT_NOP, 1); 18493 bxe_ack_sb(sc, sc->igu_dsb_id, 18494 CSTORM_ID, 0, IGU_INT_NOP, 1); 18495 bxe_ack_sb(sc, sc->igu_dsb_id, 18496 XSTORM_ID, 0, IGU_INT_NOP, 1); 18497 bxe_ack_sb(sc, sc->igu_dsb_id, 18498 TSTORM_ID, 0, IGU_INT_NOP, 1); 18499 bxe_ack_sb(sc, sc->igu_dsb_id, 18500 ATTENTION_ID, 0, IGU_INT_NOP, 1); 18501 } else { 18502 bxe_ack_sb(sc, sc->igu_dsb_id, 18503 USTORM_ID, 0, IGU_INT_NOP, 1); 18504 bxe_ack_sb(sc, sc->igu_dsb_id, 18505 ATTENTION_ID, 0, IGU_INT_NOP, 1); 18506 } 18507 bxe_igu_clear_sb(sc, sc->igu_dsb_id); 18508 18509 /* !!! these should become driver const once 18510 rf-tool supports split-68 const */ 18511 REG_WR(sc, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0); 18512 REG_WR(sc, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0); 18513 REG_WR(sc, IGU_REG_SB_MASK_LSB, 0); 18514 REG_WR(sc, IGU_REG_SB_MASK_MSB, 0); 18515 REG_WR(sc, IGU_REG_PBA_STATUS_LSB, 0); 18516 REG_WR(sc, IGU_REG_PBA_STATUS_MSB, 0); 18517 } 18518 } 18519 18520 /* Reset PCIE errors for debug */ 18521 REG_WR(sc, 0x2114, 0xffffffff); 18522 REG_WR(sc, 0x2120, 0xffffffff); 18523 18524 if (CHIP_IS_E1x(sc)) { 18525 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/ 18526 main_mem_base = HC_REG_MAIN_MEMORY + 18527 SC_PORT(sc) * (main_mem_size * 4); 18528 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR; 18529 main_mem_width = 8; 18530 18531 val = REG_RD(sc, main_mem_prty_clr); 18532 if (val) { 18533 BLOGD(sc, DBG_LOAD, 18534 "Parity errors in HC block during function init (0x%x)!\n", 18535 val); 18536 } 18537 18538 /* Clear "false" parity errors in MSI-X table */ 18539 for (i = main_mem_base; 18540 i < main_mem_base + main_mem_size * 4; 18541 i += main_mem_width) { 18542 bxe_read_dmae(sc, i, main_mem_width / 4); 18543 bxe_write_dmae(sc, BXE_SP_MAPPING(sc, wb_data), 18544 i, main_mem_width / 4); 18545 } 18546 /* Clear HC parity attention */ 18547 REG_RD(sc, main_mem_prty_clr); 18548 } 18549 18550 #if 1 18551 /* Enable STORMs SP logging */ 18552 REG_WR8(sc, BAR_USTRORM_INTMEM + 18553 USTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1); 18554 REG_WR8(sc, BAR_TSTRORM_INTMEM + 18555 TSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1); 18556 REG_WR8(sc, BAR_CSTRORM_INTMEM + 18557 CSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1); 18558 REG_WR8(sc, BAR_XSTRORM_INTMEM + 18559 XSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1); 18560 #endif 18561 18562 elink_phy_probe(&sc->link_params); 18563 18564 return (0); 18565 } 18566 18567 static void 18568 bxe_link_reset(struct bxe_softc *sc) 18569 { 18570 if (!BXE_NOMCP(sc)) { 18571 BXE_PHY_LOCK(sc); 18572 elink_lfa_reset(&sc->link_params, &sc->link_vars); 18573 BXE_PHY_UNLOCK(sc); 18574 } else { 18575 if (!CHIP_REV_IS_SLOW(sc)) { 18576 BLOGW(sc, "Bootcode is missing - cannot reset link\n"); 18577 } 18578 } 18579 } 18580 18581 static void 18582 bxe_reset_port(struct bxe_softc *sc) 18583 { 18584 int port = SC_PORT(sc); 18585 uint32_t val; 18586 18587 /* reset physical Link */ 18588 bxe_link_reset(sc); 18589 18590 REG_WR(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0); 18591 18592 /* Do not rcv packets to BRB */ 18593 REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0); 18594 /* Do not direct rcv packets that are not for MCP to the BRB */ 18595 REG_WR(sc, (port ? NIG_REG_LLH1_BRB1_NOT_MCP : 18596 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0); 18597 18598 /* Configure AEU */ 18599 REG_WR(sc, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0); 18600 18601 DELAY(100000); 18602 18603 /* Check for BRB port occupancy */ 18604 val = REG_RD(sc, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4); 18605 if (val) { 18606 BLOGD(sc, DBG_LOAD, 18607 "BRB1 is not empty, %d blocks are occupied\n", val); 18608 } 18609 18610 /* TODO: Close Doorbell port? */ 18611 } 18612 18613 static void 18614 bxe_ilt_wr(struct bxe_softc *sc, 18615 uint32_t index, 18616 bus_addr_t addr) 18617 { 18618 int reg; 18619 uint32_t wb_write[2]; 18620 18621 if (CHIP_IS_E1(sc)) { 18622 reg = PXP2_REG_RQ_ONCHIP_AT + index*8; 18623 } else { 18624 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8; 18625 } 18626 18627 wb_write[0] = ONCHIP_ADDR1(addr); 18628 wb_write[1] = ONCHIP_ADDR2(addr); 18629 REG_WR_DMAE(sc, reg, wb_write, 2); 18630 } 18631 18632 static void 18633 bxe_clear_func_ilt(struct bxe_softc *sc, 18634 uint32_t func) 18635 { 18636 uint32_t i, base = FUNC_ILT_BASE(func); 18637 for (i = base; i < base + ILT_PER_FUNC; i++) { 18638 bxe_ilt_wr(sc, i, 0); 18639 } 18640 } 18641 18642 static void 18643 bxe_reset_func(struct bxe_softc *sc) 18644 { 18645 struct bxe_fastpath *fp; 18646 int port = SC_PORT(sc); 18647 int func = SC_FUNC(sc); 18648 int i; 18649 18650 /* Disable the function in the FW */ 18651 REG_WR8(sc, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0); 18652 REG_WR8(sc, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0); 18653 REG_WR8(sc, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0); 18654 REG_WR8(sc, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0); 18655 18656 /* FP SBs */ 18657 FOR_EACH_ETH_QUEUE(sc, i) { 18658 fp = &sc->fp[i]; 18659 REG_WR8(sc, BAR_CSTRORM_INTMEM + 18660 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id), 18661 SB_DISABLED); 18662 } 18663 18664 #if 0 18665 if (CNIC_LOADED(sc)) { 18666 /* CNIC SB */ 18667 REG_WR8(sc, BAR_CSTRORM_INTMEM + 18668 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET 18669 (bxe_cnic_fw_sb_id(sc)), SB_DISABLED); 18670 } 18671 #endif 18672 18673 /* SP SB */ 18674 REG_WR8(sc, BAR_CSTRORM_INTMEM + 18675 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func), 18676 SB_DISABLED); 18677 18678 for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++) { 18679 REG_WR(sc, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func), 0); 18680 } 18681 18682 /* Configure IGU */ 18683 if (sc->devinfo.int_block == INT_BLOCK_HC) { 18684 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port*8, 0); 18685 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port*8, 0); 18686 } else { 18687 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, 0); 18688 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, 0); 18689 } 18690 18691 if (CNIC_LOADED(sc)) { 18692 /* Disable Timer scan */ 18693 REG_WR(sc, TM_REG_EN_LINEAR0_TIMER + port*4, 0); 18694 /* 18695 * Wait for at least 10ms and up to 2 second for the timers 18696 * scan to complete 18697 */ 18698 for (i = 0; i < 200; i++) { 18699 DELAY(10000); 18700 if (!REG_RD(sc, TM_REG_LIN0_SCAN_ON + port*4)) 18701 break; 18702 } 18703 } 18704 18705 /* Clear ILT */ 18706 bxe_clear_func_ilt(sc, func); 18707 18708 /* 18709 * Timers workaround bug for E2: if this is vnic-3, 18710 * we need to set the entire ilt range for this timers. 18711 */ 18712 if (!CHIP_IS_E1x(sc) && SC_VN(sc) == 3) { 18713 struct ilt_client_info ilt_cli; 18714 /* use dummy TM client */ 18715 memset(&ilt_cli, 0, sizeof(struct ilt_client_info)); 18716 ilt_cli.start = 0; 18717 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1; 18718 ilt_cli.client_num = ILT_CLIENT_TM; 18719 18720 ecore_ilt_boundry_init_op(sc, &ilt_cli, 0, INITOP_CLEAR); 18721 } 18722 18723 /* this assumes that reset_port() called before reset_func()*/ 18724 if (!CHIP_IS_E1x(sc)) { 18725 bxe_pf_disable(sc); 18726 } 18727 18728 sc->dmae_ready = 0; 18729 } 18730 18731 static int 18732 bxe_gunzip_init(struct bxe_softc *sc) 18733 { 18734 return (0); 18735 } 18736 18737 static void 18738 bxe_gunzip_end(struct bxe_softc *sc) 18739 { 18740 return; 18741 } 18742 18743 static int 18744 bxe_init_firmware(struct bxe_softc *sc) 18745 { 18746 if (CHIP_IS_E1(sc)) { 18747 ecore_init_e1_firmware(sc); 18748 sc->iro_array = e1_iro_arr; 18749 } else if (CHIP_IS_E1H(sc)) { 18750 ecore_init_e1h_firmware(sc); 18751 sc->iro_array = e1h_iro_arr; 18752 } else if (!CHIP_IS_E1x(sc)) { 18753 ecore_init_e2_firmware(sc); 18754 sc->iro_array = e2_iro_arr; 18755 } else { 18756 BLOGE(sc, "Unsupported chip revision\n"); 18757 return (-1); 18758 } 18759 18760 return (0); 18761 } 18762 18763 static void 18764 bxe_release_firmware(struct bxe_softc *sc) 18765 { 18766 /* Do nothing */ 18767 return; 18768 } 18769 18770 static int 18771 ecore_gunzip(struct bxe_softc *sc, 18772 const uint8_t *zbuf, 18773 int len) 18774 { 18775 /* XXX : Implement... */ 18776 BLOGD(sc, DBG_LOAD, "ECORE_GUNZIP NOT IMPLEMENTED\n"); 18777 return (FALSE); 18778 } 18779 18780 static void 18781 ecore_reg_wr_ind(struct bxe_softc *sc, 18782 uint32_t addr, 18783 uint32_t val) 18784 { 18785 bxe_reg_wr_ind(sc, addr, val); 18786 } 18787 18788 static void 18789 ecore_write_dmae_phys_len(struct bxe_softc *sc, 18790 bus_addr_t phys_addr, 18791 uint32_t addr, 18792 uint32_t len) 18793 { 18794 bxe_write_dmae_phys_len(sc, phys_addr, addr, len); 18795 } 18796 18797 void 18798 ecore_storm_memset_struct(struct bxe_softc *sc, 18799 uint32_t addr, 18800 size_t size, 18801 uint32_t *data) 18802 { 18803 uint8_t i; 18804 for (i = 0; i < size/4; i++) { 18805 REG_WR(sc, addr + (i * 4), data[i]); 18806 } 18807 } 18808 18809