1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2007-2014 QLogic Corporation. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' 17 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS 20 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 26 * THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/cdefs.h> 30 __FBSDID("$FreeBSD$"); 31 32 #define BXE_DRIVER_VERSION "1.78.91" 33 34 #include "bxe.h" 35 #include "ecore_sp.h" 36 #include "ecore_init.h" 37 #include "ecore_init_ops.h" 38 39 #include "57710_int_offsets.h" 40 #include "57711_int_offsets.h" 41 #include "57712_int_offsets.h" 42 43 /* 44 * CTLTYPE_U64 and sysctl_handle_64 were added in r217616. Define these 45 * explicitly here for older kernels that don't include this changeset. 46 */ 47 #ifndef CTLTYPE_U64 48 #define CTLTYPE_U64 CTLTYPE_QUAD 49 #define sysctl_handle_64 sysctl_handle_quad 50 #endif 51 52 /* 53 * CSUM_TCP_IPV6 and CSUM_UDP_IPV6 were added in r236170. Define these 54 * here as zero(0) for older kernels that don't include this changeset 55 * thereby masking the functionality. 56 */ 57 #ifndef CSUM_TCP_IPV6 58 #define CSUM_TCP_IPV6 0 59 #define CSUM_UDP_IPV6 0 60 #endif 61 62 /* 63 * pci_find_cap was added in r219865. Re-define this at pci_find_extcap 64 * for older kernels that don't include this changeset. 65 */ 66 #if __FreeBSD_version < 900035 67 #define pci_find_cap pci_find_extcap 68 #endif 69 70 #define BXE_DEF_SB_ATT_IDX 0x0001 71 #define BXE_DEF_SB_IDX 0x0002 72 73 /* 74 * FLR Support - bxe_pf_flr_clnup() is called during nic_load in the per 75 * function HW initialization. 76 */ 77 #define FLR_WAIT_USEC 10000 /* 10 msecs */ 78 #define FLR_WAIT_INTERVAL 50 /* usecs */ 79 #define FLR_POLL_CNT (FLR_WAIT_USEC / FLR_WAIT_INTERVAL) /* 200 */ 80 81 struct pbf_pN_buf_regs { 82 int pN; 83 uint32_t init_crd; 84 uint32_t crd; 85 uint32_t crd_freed; 86 }; 87 88 struct pbf_pN_cmd_regs { 89 int pN; 90 uint32_t lines_occup; 91 uint32_t lines_freed; 92 }; 93 94 /* 95 * PCI Device ID Table used by bxe_probe(). 96 */ 97 #define BXE_DEVDESC_MAX 64 98 static struct bxe_device_type bxe_devs[] = { 99 { 100 BRCM_VENDORID, 101 CHIP_NUM_57710, 102 PCI_ANY_ID, PCI_ANY_ID, 103 "QLogic NetXtreme II BCM57710 10GbE" 104 }, 105 { 106 BRCM_VENDORID, 107 CHIP_NUM_57711, 108 PCI_ANY_ID, PCI_ANY_ID, 109 "QLogic NetXtreme II BCM57711 10GbE" 110 }, 111 { 112 BRCM_VENDORID, 113 CHIP_NUM_57711E, 114 PCI_ANY_ID, PCI_ANY_ID, 115 "QLogic NetXtreme II BCM57711E 10GbE" 116 }, 117 { 118 BRCM_VENDORID, 119 CHIP_NUM_57712, 120 PCI_ANY_ID, PCI_ANY_ID, 121 "QLogic NetXtreme II BCM57712 10GbE" 122 }, 123 { 124 BRCM_VENDORID, 125 CHIP_NUM_57712_MF, 126 PCI_ANY_ID, PCI_ANY_ID, 127 "QLogic NetXtreme II BCM57712 MF 10GbE" 128 }, 129 { 130 BRCM_VENDORID, 131 CHIP_NUM_57800, 132 PCI_ANY_ID, PCI_ANY_ID, 133 "QLogic NetXtreme II BCM57800 10GbE" 134 }, 135 { 136 BRCM_VENDORID, 137 CHIP_NUM_57800_MF, 138 PCI_ANY_ID, PCI_ANY_ID, 139 "QLogic NetXtreme II BCM57800 MF 10GbE" 140 }, 141 { 142 BRCM_VENDORID, 143 CHIP_NUM_57810, 144 PCI_ANY_ID, PCI_ANY_ID, 145 "QLogic NetXtreme II BCM57810 10GbE" 146 }, 147 { 148 BRCM_VENDORID, 149 CHIP_NUM_57810_MF, 150 PCI_ANY_ID, PCI_ANY_ID, 151 "QLogic NetXtreme II BCM57810 MF 10GbE" 152 }, 153 { 154 BRCM_VENDORID, 155 CHIP_NUM_57811, 156 PCI_ANY_ID, PCI_ANY_ID, 157 "QLogic NetXtreme II BCM57811 10GbE" 158 }, 159 { 160 BRCM_VENDORID, 161 CHIP_NUM_57811_MF, 162 PCI_ANY_ID, PCI_ANY_ID, 163 "QLogic NetXtreme II BCM57811 MF 10GbE" 164 }, 165 { 166 BRCM_VENDORID, 167 CHIP_NUM_57840_4_10, 168 PCI_ANY_ID, PCI_ANY_ID, 169 "QLogic NetXtreme II BCM57840 4x10GbE" 170 }, 171 { 172 QLOGIC_VENDORID, 173 CHIP_NUM_57840_4_10, 174 PCI_ANY_ID, PCI_ANY_ID, 175 "QLogic NetXtreme II BCM57840 4x10GbE" 176 }, 177 { 178 BRCM_VENDORID, 179 CHIP_NUM_57840_2_20, 180 PCI_ANY_ID, PCI_ANY_ID, 181 "QLogic NetXtreme II BCM57840 2x20GbE" 182 }, 183 { 184 BRCM_VENDORID, 185 CHIP_NUM_57840_MF, 186 PCI_ANY_ID, PCI_ANY_ID, 187 "QLogic NetXtreme II BCM57840 MF 10GbE" 188 }, 189 { 190 0, 0, 0, 0, NULL 191 } 192 }; 193 194 MALLOC_DECLARE(M_BXE_ILT); 195 MALLOC_DEFINE(M_BXE_ILT, "bxe_ilt", "bxe ILT pointer"); 196 197 /* 198 * FreeBSD device entry points. 199 */ 200 static int bxe_probe(device_t); 201 static int bxe_attach(device_t); 202 static int bxe_detach(device_t); 203 static int bxe_shutdown(device_t); 204 205 /* 206 * FreeBSD KLD module/device interface event handler method. 207 */ 208 static device_method_t bxe_methods[] = { 209 /* Device interface (device_if.h) */ 210 DEVMETHOD(device_probe, bxe_probe), 211 DEVMETHOD(device_attach, bxe_attach), 212 DEVMETHOD(device_detach, bxe_detach), 213 DEVMETHOD(device_shutdown, bxe_shutdown), 214 /* Bus interface (bus_if.h) */ 215 DEVMETHOD(bus_print_child, bus_generic_print_child), 216 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 217 KOBJMETHOD_END 218 }; 219 220 /* 221 * FreeBSD KLD Module data declaration 222 */ 223 static driver_t bxe_driver = { 224 "bxe", /* module name */ 225 bxe_methods, /* event handler */ 226 sizeof(struct bxe_softc) /* extra data */ 227 }; 228 229 /* 230 * FreeBSD dev class is needed to manage dev instances and 231 * to associate with a bus type 232 */ 233 static devclass_t bxe_devclass; 234 235 MODULE_DEPEND(bxe, pci, 1, 1, 1); 236 MODULE_DEPEND(bxe, ether, 1, 1, 1); 237 DRIVER_MODULE(bxe, pci, bxe_driver, bxe_devclass, 0, 0); 238 239 NETDUMP_DEFINE(bxe); 240 241 /* resources needed for unloading a previously loaded device */ 242 243 #define BXE_PREV_WAIT_NEEDED 1 244 struct mtx bxe_prev_mtx; 245 MTX_SYSINIT(bxe_prev_mtx, &bxe_prev_mtx, "bxe_prev_lock", MTX_DEF); 246 struct bxe_prev_list_node { 247 LIST_ENTRY(bxe_prev_list_node) node; 248 uint8_t bus; 249 uint8_t slot; 250 uint8_t path; 251 uint8_t aer; /* XXX automatic error recovery */ 252 uint8_t undi; 253 }; 254 static LIST_HEAD(, bxe_prev_list_node) bxe_prev_list = LIST_HEAD_INITIALIZER(bxe_prev_list); 255 256 static int load_count[2][3] = { {0} }; /* per-path: 0-common, 1-port0, 2-port1 */ 257 258 /* Tunable device values... */ 259 260 SYSCTL_NODE(_hw, OID_AUTO, bxe, CTLFLAG_RD, 0, "bxe driver parameters"); 261 262 /* Debug */ 263 unsigned long bxe_debug = 0; 264 SYSCTL_ULONG(_hw_bxe, OID_AUTO, debug, CTLFLAG_RDTUN, 265 &bxe_debug, 0, "Debug logging mode"); 266 267 /* Interrupt Mode: 0 (IRQ), 1 (MSI/IRQ), and 2 (MSI-X/MSI/IRQ) */ 268 static int bxe_interrupt_mode = INTR_MODE_MSIX; 269 SYSCTL_INT(_hw_bxe, OID_AUTO, interrupt_mode, CTLFLAG_RDTUN, 270 &bxe_interrupt_mode, 0, "Interrupt (MSI-X/MSI/INTx) mode"); 271 272 /* Number of Queues: 0 (Auto) or 1 to 16 (fixed queue number) */ 273 static int bxe_queue_count = 4; 274 SYSCTL_INT(_hw_bxe, OID_AUTO, queue_count, CTLFLAG_RDTUN, 275 &bxe_queue_count, 0, "Multi-Queue queue count"); 276 277 /* max number of buffers per queue (default RX_BD_USABLE) */ 278 static int bxe_max_rx_bufs = 0; 279 SYSCTL_INT(_hw_bxe, OID_AUTO, max_rx_bufs, CTLFLAG_RDTUN, 280 &bxe_max_rx_bufs, 0, "Maximum Number of Rx Buffers Per Queue"); 281 282 /* Host interrupt coalescing RX tick timer (usecs) */ 283 static int bxe_hc_rx_ticks = 25; 284 SYSCTL_INT(_hw_bxe, OID_AUTO, hc_rx_ticks, CTLFLAG_RDTUN, 285 &bxe_hc_rx_ticks, 0, "Host Coalescing Rx ticks"); 286 287 /* Host interrupt coalescing TX tick timer (usecs) */ 288 static int bxe_hc_tx_ticks = 50; 289 SYSCTL_INT(_hw_bxe, OID_AUTO, hc_tx_ticks, CTLFLAG_RDTUN, 290 &bxe_hc_tx_ticks, 0, "Host Coalescing Tx ticks"); 291 292 /* Maximum number of Rx packets to process at a time */ 293 static int bxe_rx_budget = 0xffffffff; 294 SYSCTL_INT(_hw_bxe, OID_AUTO, rx_budget, CTLFLAG_TUN, 295 &bxe_rx_budget, 0, "Rx processing budget"); 296 297 /* Maximum LRO aggregation size */ 298 static int bxe_max_aggregation_size = 0; 299 SYSCTL_INT(_hw_bxe, OID_AUTO, max_aggregation_size, CTLFLAG_TUN, 300 &bxe_max_aggregation_size, 0, "max aggregation size"); 301 302 /* PCI MRRS: -1 (Auto), 0 (128B), 1 (256B), 2 (512B), 3 (1KB) */ 303 static int bxe_mrrs = -1; 304 SYSCTL_INT(_hw_bxe, OID_AUTO, mrrs, CTLFLAG_RDTUN, 305 &bxe_mrrs, 0, "PCIe maximum read request size"); 306 307 /* AutoGrEEEn: 0 (hardware default), 1 (force on), 2 (force off) */ 308 static int bxe_autogreeen = 0; 309 SYSCTL_INT(_hw_bxe, OID_AUTO, autogreeen, CTLFLAG_RDTUN, 310 &bxe_autogreeen, 0, "AutoGrEEEn support"); 311 312 /* 4-tuple RSS support for UDP: 0 (disabled), 1 (enabled) */ 313 static int bxe_udp_rss = 0; 314 SYSCTL_INT(_hw_bxe, OID_AUTO, udp_rss, CTLFLAG_RDTUN, 315 &bxe_udp_rss, 0, "UDP RSS support"); 316 317 318 #define STAT_NAME_LEN 32 /* no stat names below can be longer than this */ 319 320 #define STATS_OFFSET32(stat_name) \ 321 (offsetof(struct bxe_eth_stats, stat_name) / 4) 322 323 #define Q_STATS_OFFSET32(stat_name) \ 324 (offsetof(struct bxe_eth_q_stats, stat_name) / 4) 325 326 static const struct { 327 uint32_t offset; 328 uint32_t size; 329 uint32_t flags; 330 #define STATS_FLAGS_PORT 1 331 #define STATS_FLAGS_FUNC 2 /* MF only cares about function stats */ 332 #define STATS_FLAGS_BOTH (STATS_FLAGS_FUNC | STATS_FLAGS_PORT) 333 char string[STAT_NAME_LEN]; 334 } bxe_eth_stats_arr[] = { 335 { STATS_OFFSET32(total_bytes_received_hi), 336 8, STATS_FLAGS_BOTH, "rx_bytes" }, 337 { STATS_OFFSET32(error_bytes_received_hi), 338 8, STATS_FLAGS_BOTH, "rx_error_bytes" }, 339 { STATS_OFFSET32(total_unicast_packets_received_hi), 340 8, STATS_FLAGS_BOTH, "rx_ucast_packets" }, 341 { STATS_OFFSET32(total_multicast_packets_received_hi), 342 8, STATS_FLAGS_BOTH, "rx_mcast_packets" }, 343 { STATS_OFFSET32(total_broadcast_packets_received_hi), 344 8, STATS_FLAGS_BOTH, "rx_bcast_packets" }, 345 { STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi), 346 8, STATS_FLAGS_PORT, "rx_crc_errors" }, 347 { STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi), 348 8, STATS_FLAGS_PORT, "rx_align_errors" }, 349 { STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi), 350 8, STATS_FLAGS_PORT, "rx_undersize_packets" }, 351 { STATS_OFFSET32(etherstatsoverrsizepkts_hi), 352 8, STATS_FLAGS_PORT, "rx_oversize_packets" }, 353 { STATS_OFFSET32(rx_stat_etherstatsfragments_hi), 354 8, STATS_FLAGS_PORT, "rx_fragments" }, 355 { STATS_OFFSET32(rx_stat_etherstatsjabbers_hi), 356 8, STATS_FLAGS_PORT, "rx_jabbers" }, 357 { STATS_OFFSET32(no_buff_discard_hi), 358 8, STATS_FLAGS_BOTH, "rx_discards" }, 359 { STATS_OFFSET32(mac_filter_discard), 360 4, STATS_FLAGS_PORT, "rx_filtered_packets" }, 361 { STATS_OFFSET32(mf_tag_discard), 362 4, STATS_FLAGS_PORT, "rx_mf_tag_discard" }, 363 { STATS_OFFSET32(pfc_frames_received_hi), 364 8, STATS_FLAGS_PORT, "pfc_frames_received" }, 365 { STATS_OFFSET32(pfc_frames_sent_hi), 366 8, STATS_FLAGS_PORT, "pfc_frames_sent" }, 367 { STATS_OFFSET32(brb_drop_hi), 368 8, STATS_FLAGS_PORT, "rx_brb_discard" }, 369 { STATS_OFFSET32(brb_truncate_hi), 370 8, STATS_FLAGS_PORT, "rx_brb_truncate" }, 371 { STATS_OFFSET32(pause_frames_received_hi), 372 8, STATS_FLAGS_PORT, "rx_pause_frames" }, 373 { STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi), 374 8, STATS_FLAGS_PORT, "rx_mac_ctrl_frames" }, 375 { STATS_OFFSET32(nig_timer_max), 376 4, STATS_FLAGS_PORT, "rx_constant_pause_events" }, 377 { STATS_OFFSET32(total_bytes_transmitted_hi), 378 8, STATS_FLAGS_BOTH, "tx_bytes" }, 379 { STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi), 380 8, STATS_FLAGS_PORT, "tx_error_bytes" }, 381 { STATS_OFFSET32(total_unicast_packets_transmitted_hi), 382 8, STATS_FLAGS_BOTH, "tx_ucast_packets" }, 383 { STATS_OFFSET32(total_multicast_packets_transmitted_hi), 384 8, STATS_FLAGS_BOTH, "tx_mcast_packets" }, 385 { STATS_OFFSET32(total_broadcast_packets_transmitted_hi), 386 8, STATS_FLAGS_BOTH, "tx_bcast_packets" }, 387 { STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi), 388 8, STATS_FLAGS_PORT, "tx_mac_errors" }, 389 { STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi), 390 8, STATS_FLAGS_PORT, "tx_carrier_errors" }, 391 { STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi), 392 8, STATS_FLAGS_PORT, "tx_single_collisions" }, 393 { STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi), 394 8, STATS_FLAGS_PORT, "tx_multi_collisions" }, 395 { STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi), 396 8, STATS_FLAGS_PORT, "tx_deferred" }, 397 { STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi), 398 8, STATS_FLAGS_PORT, "tx_excess_collisions" }, 399 { STATS_OFFSET32(tx_stat_dot3statslatecollisions_hi), 400 8, STATS_FLAGS_PORT, "tx_late_collisions" }, 401 { STATS_OFFSET32(tx_stat_etherstatscollisions_hi), 402 8, STATS_FLAGS_PORT, "tx_total_collisions" }, 403 { STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi), 404 8, STATS_FLAGS_PORT, "tx_64_byte_packets" }, 405 { STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi), 406 8, STATS_FLAGS_PORT, "tx_65_to_127_byte_packets" }, 407 { STATS_OFFSET32(tx_stat_etherstatspkts128octetsto255octets_hi), 408 8, STATS_FLAGS_PORT, "tx_128_to_255_byte_packets" }, 409 { STATS_OFFSET32(tx_stat_etherstatspkts256octetsto511octets_hi), 410 8, STATS_FLAGS_PORT, "tx_256_to_511_byte_packets" }, 411 { STATS_OFFSET32(tx_stat_etherstatspkts512octetsto1023octets_hi), 412 8, STATS_FLAGS_PORT, "tx_512_to_1023_byte_packets" }, 413 { STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi), 414 8, STATS_FLAGS_PORT, "tx_1024_to_1522_byte_packets" }, 415 { STATS_OFFSET32(etherstatspktsover1522octets_hi), 416 8, STATS_FLAGS_PORT, "tx_1523_to_9022_byte_packets" }, 417 { STATS_OFFSET32(pause_frames_sent_hi), 418 8, STATS_FLAGS_PORT, "tx_pause_frames" }, 419 { STATS_OFFSET32(total_tpa_aggregations_hi), 420 8, STATS_FLAGS_FUNC, "tpa_aggregations" }, 421 { STATS_OFFSET32(total_tpa_aggregated_frames_hi), 422 8, STATS_FLAGS_FUNC, "tpa_aggregated_frames"}, 423 { STATS_OFFSET32(total_tpa_bytes_hi), 424 8, STATS_FLAGS_FUNC, "tpa_bytes"}, 425 { STATS_OFFSET32(eee_tx_lpi), 426 4, STATS_FLAGS_PORT, "eee_tx_lpi"}, 427 { STATS_OFFSET32(rx_calls), 428 4, STATS_FLAGS_FUNC, "rx_calls"}, 429 { STATS_OFFSET32(rx_pkts), 430 4, STATS_FLAGS_FUNC, "rx_pkts"}, 431 { STATS_OFFSET32(rx_tpa_pkts), 432 4, STATS_FLAGS_FUNC, "rx_tpa_pkts"}, 433 { STATS_OFFSET32(rx_erroneous_jumbo_sge_pkts), 434 4, STATS_FLAGS_FUNC, "rx_erroneous_jumbo_sge_pkts"}, 435 { STATS_OFFSET32(rx_bxe_service_rxsgl), 436 4, STATS_FLAGS_FUNC, "rx_bxe_service_rxsgl"}, 437 { STATS_OFFSET32(rx_jumbo_sge_pkts), 438 4, STATS_FLAGS_FUNC, "rx_jumbo_sge_pkts"}, 439 { STATS_OFFSET32(rx_soft_errors), 440 4, STATS_FLAGS_FUNC, "rx_soft_errors"}, 441 { STATS_OFFSET32(rx_hw_csum_errors), 442 4, STATS_FLAGS_FUNC, "rx_hw_csum_errors"}, 443 { STATS_OFFSET32(rx_ofld_frames_csum_ip), 444 4, STATS_FLAGS_FUNC, "rx_ofld_frames_csum_ip"}, 445 { STATS_OFFSET32(rx_ofld_frames_csum_tcp_udp), 446 4, STATS_FLAGS_FUNC, "rx_ofld_frames_csum_tcp_udp"}, 447 { STATS_OFFSET32(rx_budget_reached), 448 4, STATS_FLAGS_FUNC, "rx_budget_reached"}, 449 { STATS_OFFSET32(tx_pkts), 450 4, STATS_FLAGS_FUNC, "tx_pkts"}, 451 { STATS_OFFSET32(tx_soft_errors), 452 4, STATS_FLAGS_FUNC, "tx_soft_errors"}, 453 { STATS_OFFSET32(tx_ofld_frames_csum_ip), 454 4, STATS_FLAGS_FUNC, "tx_ofld_frames_csum_ip"}, 455 { STATS_OFFSET32(tx_ofld_frames_csum_tcp), 456 4, STATS_FLAGS_FUNC, "tx_ofld_frames_csum_tcp"}, 457 { STATS_OFFSET32(tx_ofld_frames_csum_udp), 458 4, STATS_FLAGS_FUNC, "tx_ofld_frames_csum_udp"}, 459 { STATS_OFFSET32(tx_ofld_frames_lso), 460 4, STATS_FLAGS_FUNC, "tx_ofld_frames_lso"}, 461 { STATS_OFFSET32(tx_ofld_frames_lso_hdr_splits), 462 4, STATS_FLAGS_FUNC, "tx_ofld_frames_lso_hdr_splits"}, 463 { STATS_OFFSET32(tx_encap_failures), 464 4, STATS_FLAGS_FUNC, "tx_encap_failures"}, 465 { STATS_OFFSET32(tx_hw_queue_full), 466 4, STATS_FLAGS_FUNC, "tx_hw_queue_full"}, 467 { STATS_OFFSET32(tx_hw_max_queue_depth), 468 4, STATS_FLAGS_FUNC, "tx_hw_max_queue_depth"}, 469 { STATS_OFFSET32(tx_dma_mapping_failure), 470 4, STATS_FLAGS_FUNC, "tx_dma_mapping_failure"}, 471 { STATS_OFFSET32(tx_max_drbr_queue_depth), 472 4, STATS_FLAGS_FUNC, "tx_max_drbr_queue_depth"}, 473 { STATS_OFFSET32(tx_window_violation_std), 474 4, STATS_FLAGS_FUNC, "tx_window_violation_std"}, 475 { STATS_OFFSET32(tx_window_violation_tso), 476 4, STATS_FLAGS_FUNC, "tx_window_violation_tso"}, 477 { STATS_OFFSET32(tx_chain_lost_mbuf), 478 4, STATS_FLAGS_FUNC, "tx_chain_lost_mbuf"}, 479 { STATS_OFFSET32(tx_frames_deferred), 480 4, STATS_FLAGS_FUNC, "tx_frames_deferred"}, 481 { STATS_OFFSET32(tx_queue_xoff), 482 4, STATS_FLAGS_FUNC, "tx_queue_xoff"}, 483 { STATS_OFFSET32(mbuf_defrag_attempts), 484 4, STATS_FLAGS_FUNC, "mbuf_defrag_attempts"}, 485 { STATS_OFFSET32(mbuf_defrag_failures), 486 4, STATS_FLAGS_FUNC, "mbuf_defrag_failures"}, 487 { STATS_OFFSET32(mbuf_rx_bd_alloc_failed), 488 4, STATS_FLAGS_FUNC, "mbuf_rx_bd_alloc_failed"}, 489 { STATS_OFFSET32(mbuf_rx_bd_mapping_failed), 490 4, STATS_FLAGS_FUNC, "mbuf_rx_bd_mapping_failed"}, 491 { STATS_OFFSET32(mbuf_rx_tpa_alloc_failed), 492 4, STATS_FLAGS_FUNC, "mbuf_rx_tpa_alloc_failed"}, 493 { STATS_OFFSET32(mbuf_rx_tpa_mapping_failed), 494 4, STATS_FLAGS_FUNC, "mbuf_rx_tpa_mapping_failed"}, 495 { STATS_OFFSET32(mbuf_rx_sge_alloc_failed), 496 4, STATS_FLAGS_FUNC, "mbuf_rx_sge_alloc_failed"}, 497 { STATS_OFFSET32(mbuf_rx_sge_mapping_failed), 498 4, STATS_FLAGS_FUNC, "mbuf_rx_sge_mapping_failed"}, 499 { STATS_OFFSET32(mbuf_alloc_tx), 500 4, STATS_FLAGS_FUNC, "mbuf_alloc_tx"}, 501 { STATS_OFFSET32(mbuf_alloc_rx), 502 4, STATS_FLAGS_FUNC, "mbuf_alloc_rx"}, 503 { STATS_OFFSET32(mbuf_alloc_sge), 504 4, STATS_FLAGS_FUNC, "mbuf_alloc_sge"}, 505 { STATS_OFFSET32(mbuf_alloc_tpa), 506 4, STATS_FLAGS_FUNC, "mbuf_alloc_tpa"}, 507 { STATS_OFFSET32(tx_queue_full_return), 508 4, STATS_FLAGS_FUNC, "tx_queue_full_return"}, 509 { STATS_OFFSET32(bxe_tx_mq_sc_state_failures), 510 4, STATS_FLAGS_FUNC, "bxe_tx_mq_sc_state_failures"}, 511 { STATS_OFFSET32(tx_request_link_down_failures), 512 4, STATS_FLAGS_FUNC, "tx_request_link_down_failures"}, 513 { STATS_OFFSET32(bd_avail_too_less_failures), 514 4, STATS_FLAGS_FUNC, "bd_avail_too_less_failures"}, 515 { STATS_OFFSET32(tx_mq_not_empty), 516 4, STATS_FLAGS_FUNC, "tx_mq_not_empty"}, 517 { STATS_OFFSET32(nsegs_path1_errors), 518 4, STATS_FLAGS_FUNC, "nsegs_path1_errors"}, 519 { STATS_OFFSET32(nsegs_path2_errors), 520 4, STATS_FLAGS_FUNC, "nsegs_path2_errors"} 521 522 523 }; 524 525 static const struct { 526 uint32_t offset; 527 uint32_t size; 528 char string[STAT_NAME_LEN]; 529 } bxe_eth_q_stats_arr[] = { 530 { Q_STATS_OFFSET32(total_bytes_received_hi), 531 8, "rx_bytes" }, 532 { Q_STATS_OFFSET32(total_unicast_packets_received_hi), 533 8, "rx_ucast_packets" }, 534 { Q_STATS_OFFSET32(total_multicast_packets_received_hi), 535 8, "rx_mcast_packets" }, 536 { Q_STATS_OFFSET32(total_broadcast_packets_received_hi), 537 8, "rx_bcast_packets" }, 538 { Q_STATS_OFFSET32(no_buff_discard_hi), 539 8, "rx_discards" }, 540 { Q_STATS_OFFSET32(total_bytes_transmitted_hi), 541 8, "tx_bytes" }, 542 { Q_STATS_OFFSET32(total_unicast_packets_transmitted_hi), 543 8, "tx_ucast_packets" }, 544 { Q_STATS_OFFSET32(total_multicast_packets_transmitted_hi), 545 8, "tx_mcast_packets" }, 546 { Q_STATS_OFFSET32(total_broadcast_packets_transmitted_hi), 547 8, "tx_bcast_packets" }, 548 { Q_STATS_OFFSET32(total_tpa_aggregations_hi), 549 8, "tpa_aggregations" }, 550 { Q_STATS_OFFSET32(total_tpa_aggregated_frames_hi), 551 8, "tpa_aggregated_frames"}, 552 { Q_STATS_OFFSET32(total_tpa_bytes_hi), 553 8, "tpa_bytes"}, 554 { Q_STATS_OFFSET32(rx_calls), 555 4, "rx_calls"}, 556 { Q_STATS_OFFSET32(rx_pkts), 557 4, "rx_pkts"}, 558 { Q_STATS_OFFSET32(rx_tpa_pkts), 559 4, "rx_tpa_pkts"}, 560 { Q_STATS_OFFSET32(rx_erroneous_jumbo_sge_pkts), 561 4, "rx_erroneous_jumbo_sge_pkts"}, 562 { Q_STATS_OFFSET32(rx_bxe_service_rxsgl), 563 4, "rx_bxe_service_rxsgl"}, 564 { Q_STATS_OFFSET32(rx_jumbo_sge_pkts), 565 4, "rx_jumbo_sge_pkts"}, 566 { Q_STATS_OFFSET32(rx_soft_errors), 567 4, "rx_soft_errors"}, 568 { Q_STATS_OFFSET32(rx_hw_csum_errors), 569 4, "rx_hw_csum_errors"}, 570 { Q_STATS_OFFSET32(rx_ofld_frames_csum_ip), 571 4, "rx_ofld_frames_csum_ip"}, 572 { Q_STATS_OFFSET32(rx_ofld_frames_csum_tcp_udp), 573 4, "rx_ofld_frames_csum_tcp_udp"}, 574 { Q_STATS_OFFSET32(rx_budget_reached), 575 4, "rx_budget_reached"}, 576 { Q_STATS_OFFSET32(tx_pkts), 577 4, "tx_pkts"}, 578 { Q_STATS_OFFSET32(tx_soft_errors), 579 4, "tx_soft_errors"}, 580 { Q_STATS_OFFSET32(tx_ofld_frames_csum_ip), 581 4, "tx_ofld_frames_csum_ip"}, 582 { Q_STATS_OFFSET32(tx_ofld_frames_csum_tcp), 583 4, "tx_ofld_frames_csum_tcp"}, 584 { Q_STATS_OFFSET32(tx_ofld_frames_csum_udp), 585 4, "tx_ofld_frames_csum_udp"}, 586 { Q_STATS_OFFSET32(tx_ofld_frames_lso), 587 4, "tx_ofld_frames_lso"}, 588 { Q_STATS_OFFSET32(tx_ofld_frames_lso_hdr_splits), 589 4, "tx_ofld_frames_lso_hdr_splits"}, 590 { Q_STATS_OFFSET32(tx_encap_failures), 591 4, "tx_encap_failures"}, 592 { Q_STATS_OFFSET32(tx_hw_queue_full), 593 4, "tx_hw_queue_full"}, 594 { Q_STATS_OFFSET32(tx_hw_max_queue_depth), 595 4, "tx_hw_max_queue_depth"}, 596 { Q_STATS_OFFSET32(tx_dma_mapping_failure), 597 4, "tx_dma_mapping_failure"}, 598 { Q_STATS_OFFSET32(tx_max_drbr_queue_depth), 599 4, "tx_max_drbr_queue_depth"}, 600 { Q_STATS_OFFSET32(tx_window_violation_std), 601 4, "tx_window_violation_std"}, 602 { Q_STATS_OFFSET32(tx_window_violation_tso), 603 4, "tx_window_violation_tso"}, 604 { Q_STATS_OFFSET32(tx_chain_lost_mbuf), 605 4, "tx_chain_lost_mbuf"}, 606 { Q_STATS_OFFSET32(tx_frames_deferred), 607 4, "tx_frames_deferred"}, 608 { Q_STATS_OFFSET32(tx_queue_xoff), 609 4, "tx_queue_xoff"}, 610 { Q_STATS_OFFSET32(mbuf_defrag_attempts), 611 4, "mbuf_defrag_attempts"}, 612 { Q_STATS_OFFSET32(mbuf_defrag_failures), 613 4, "mbuf_defrag_failures"}, 614 { Q_STATS_OFFSET32(mbuf_rx_bd_alloc_failed), 615 4, "mbuf_rx_bd_alloc_failed"}, 616 { Q_STATS_OFFSET32(mbuf_rx_bd_mapping_failed), 617 4, "mbuf_rx_bd_mapping_failed"}, 618 { Q_STATS_OFFSET32(mbuf_rx_tpa_alloc_failed), 619 4, "mbuf_rx_tpa_alloc_failed"}, 620 { Q_STATS_OFFSET32(mbuf_rx_tpa_mapping_failed), 621 4, "mbuf_rx_tpa_mapping_failed"}, 622 { Q_STATS_OFFSET32(mbuf_rx_sge_alloc_failed), 623 4, "mbuf_rx_sge_alloc_failed"}, 624 { Q_STATS_OFFSET32(mbuf_rx_sge_mapping_failed), 625 4, "mbuf_rx_sge_mapping_failed"}, 626 { Q_STATS_OFFSET32(mbuf_alloc_tx), 627 4, "mbuf_alloc_tx"}, 628 { Q_STATS_OFFSET32(mbuf_alloc_rx), 629 4, "mbuf_alloc_rx"}, 630 { Q_STATS_OFFSET32(mbuf_alloc_sge), 631 4, "mbuf_alloc_sge"}, 632 { Q_STATS_OFFSET32(mbuf_alloc_tpa), 633 4, "mbuf_alloc_tpa"}, 634 { Q_STATS_OFFSET32(tx_queue_full_return), 635 4, "tx_queue_full_return"}, 636 { Q_STATS_OFFSET32(bxe_tx_mq_sc_state_failures), 637 4, "bxe_tx_mq_sc_state_failures"}, 638 { Q_STATS_OFFSET32(tx_request_link_down_failures), 639 4, "tx_request_link_down_failures"}, 640 { Q_STATS_OFFSET32(bd_avail_too_less_failures), 641 4, "bd_avail_too_less_failures"}, 642 { Q_STATS_OFFSET32(tx_mq_not_empty), 643 4, "tx_mq_not_empty"}, 644 { Q_STATS_OFFSET32(nsegs_path1_errors), 645 4, "nsegs_path1_errors"}, 646 { Q_STATS_OFFSET32(nsegs_path2_errors), 647 4, "nsegs_path2_errors"} 648 649 650 }; 651 652 #define BXE_NUM_ETH_STATS ARRAY_SIZE(bxe_eth_stats_arr) 653 #define BXE_NUM_ETH_Q_STATS ARRAY_SIZE(bxe_eth_q_stats_arr) 654 655 656 static void bxe_cmng_fns_init(struct bxe_softc *sc, 657 uint8_t read_cfg, 658 uint8_t cmng_type); 659 static int bxe_get_cmng_fns_mode(struct bxe_softc *sc); 660 static void storm_memset_cmng(struct bxe_softc *sc, 661 struct cmng_init *cmng, 662 uint8_t port); 663 static void bxe_set_reset_global(struct bxe_softc *sc); 664 static void bxe_set_reset_in_progress(struct bxe_softc *sc); 665 static uint8_t bxe_reset_is_done(struct bxe_softc *sc, 666 int engine); 667 static uint8_t bxe_clear_pf_load(struct bxe_softc *sc); 668 static uint8_t bxe_chk_parity_attn(struct bxe_softc *sc, 669 uint8_t *global, 670 uint8_t print); 671 static void bxe_int_disable(struct bxe_softc *sc); 672 static int bxe_release_leader_lock(struct bxe_softc *sc); 673 static void bxe_pf_disable(struct bxe_softc *sc); 674 static void bxe_free_fp_buffers(struct bxe_softc *sc); 675 static inline void bxe_update_rx_prod(struct bxe_softc *sc, 676 struct bxe_fastpath *fp, 677 uint16_t rx_bd_prod, 678 uint16_t rx_cq_prod, 679 uint16_t rx_sge_prod); 680 static void bxe_link_report_locked(struct bxe_softc *sc); 681 static void bxe_link_report(struct bxe_softc *sc); 682 static void bxe_link_status_update(struct bxe_softc *sc); 683 static void bxe_periodic_callout_func(void *xsc); 684 static void bxe_periodic_start(struct bxe_softc *sc); 685 static void bxe_periodic_stop(struct bxe_softc *sc); 686 static int bxe_alloc_rx_bd_mbuf(struct bxe_fastpath *fp, 687 uint16_t prev_index, 688 uint16_t index); 689 static int bxe_alloc_rx_tpa_mbuf(struct bxe_fastpath *fp, 690 int queue); 691 static int bxe_alloc_rx_sge_mbuf(struct bxe_fastpath *fp, 692 uint16_t index); 693 static uint8_t bxe_txeof(struct bxe_softc *sc, 694 struct bxe_fastpath *fp); 695 static void bxe_task_fp(struct bxe_fastpath *fp); 696 static __noinline void bxe_dump_mbuf(struct bxe_softc *sc, 697 struct mbuf *m, 698 uint8_t contents); 699 static int bxe_alloc_mem(struct bxe_softc *sc); 700 static void bxe_free_mem(struct bxe_softc *sc); 701 static int bxe_alloc_fw_stats_mem(struct bxe_softc *sc); 702 static void bxe_free_fw_stats_mem(struct bxe_softc *sc); 703 static int bxe_interrupt_attach(struct bxe_softc *sc); 704 static void bxe_interrupt_detach(struct bxe_softc *sc); 705 static void bxe_set_rx_mode(struct bxe_softc *sc); 706 static int bxe_init_locked(struct bxe_softc *sc); 707 static int bxe_stop_locked(struct bxe_softc *sc); 708 static __noinline int bxe_nic_load(struct bxe_softc *sc, 709 int load_mode); 710 static __noinline int bxe_nic_unload(struct bxe_softc *sc, 711 uint32_t unload_mode, 712 uint8_t keep_link); 713 714 static void bxe_handle_sp_tq(void *context, int pending); 715 static void bxe_handle_fp_tq(void *context, int pending); 716 717 static int bxe_add_cdev(struct bxe_softc *sc); 718 static void bxe_del_cdev(struct bxe_softc *sc); 719 int bxe_grc_dump(struct bxe_softc *sc); 720 static int bxe_alloc_buf_rings(struct bxe_softc *sc); 721 static void bxe_free_buf_rings(struct bxe_softc *sc); 722 723 /* calculate crc32 on a buffer (NOTE: crc32_length MUST be aligned to 8) */ 724 uint32_t 725 calc_crc32(uint8_t *crc32_packet, 726 uint32_t crc32_length, 727 uint32_t crc32_seed, 728 uint8_t complement) 729 { 730 uint32_t byte = 0; 731 uint32_t bit = 0; 732 uint8_t msb = 0; 733 uint32_t temp = 0; 734 uint32_t shft = 0; 735 uint8_t current_byte = 0; 736 uint32_t crc32_result = crc32_seed; 737 const uint32_t CRC32_POLY = 0x1edc6f41; 738 739 if ((crc32_packet == NULL) || 740 (crc32_length == 0) || 741 ((crc32_length % 8) != 0)) 742 { 743 return (crc32_result); 744 } 745 746 for (byte = 0; byte < crc32_length; byte = byte + 1) 747 { 748 current_byte = crc32_packet[byte]; 749 for (bit = 0; bit < 8; bit = bit + 1) 750 { 751 /* msb = crc32_result[31]; */ 752 msb = (uint8_t)(crc32_result >> 31); 753 754 crc32_result = crc32_result << 1; 755 756 /* it (msb != current_byte[bit]) */ 757 if (msb != (0x1 & (current_byte >> bit))) 758 { 759 crc32_result = crc32_result ^ CRC32_POLY; 760 /* crc32_result[0] = 1 */ 761 crc32_result |= 1; 762 } 763 } 764 } 765 766 /* Last step is to: 767 * 1. "mirror" every bit 768 * 2. swap the 4 bytes 769 * 3. complement each bit 770 */ 771 772 /* Mirror */ 773 temp = crc32_result; 774 shft = sizeof(crc32_result) * 8 - 1; 775 776 for (crc32_result >>= 1; crc32_result; crc32_result >>= 1) 777 { 778 temp <<= 1; 779 temp |= crc32_result & 1; 780 shft-- ; 781 } 782 783 /* temp[31-bit] = crc32_result[bit] */ 784 temp <<= shft; 785 786 /* Swap */ 787 /* crc32_result = {temp[7:0], temp[15:8], temp[23:16], temp[31:24]} */ 788 { 789 uint32_t t0, t1, t2, t3; 790 t0 = (0x000000ff & (temp >> 24)); 791 t1 = (0x0000ff00 & (temp >> 8)); 792 t2 = (0x00ff0000 & (temp << 8)); 793 t3 = (0xff000000 & (temp << 24)); 794 crc32_result = t0 | t1 | t2 | t3; 795 } 796 797 /* Complement */ 798 if (complement) 799 { 800 crc32_result = ~crc32_result; 801 } 802 803 return (crc32_result); 804 } 805 806 int 807 bxe_test_bit(int nr, 808 volatile unsigned long *addr) 809 { 810 return ((atomic_load_acq_long(addr) & (1 << nr)) != 0); 811 } 812 813 void 814 bxe_set_bit(unsigned int nr, 815 volatile unsigned long *addr) 816 { 817 atomic_set_acq_long(addr, (1 << nr)); 818 } 819 820 void 821 bxe_clear_bit(int nr, 822 volatile unsigned long *addr) 823 { 824 atomic_clear_acq_long(addr, (1 << nr)); 825 } 826 827 int 828 bxe_test_and_set_bit(int nr, 829 volatile unsigned long *addr) 830 { 831 unsigned long x; 832 nr = (1 << nr); 833 do { 834 x = *addr; 835 } while (atomic_cmpset_acq_long(addr, x, x | nr) == 0); 836 // if (x & nr) bit_was_set; else bit_was_not_set; 837 return (x & nr); 838 } 839 840 int 841 bxe_test_and_clear_bit(int nr, 842 volatile unsigned long *addr) 843 { 844 unsigned long x; 845 nr = (1 << nr); 846 do { 847 x = *addr; 848 } while (atomic_cmpset_acq_long(addr, x, x & ~nr) == 0); 849 // if (x & nr) bit_was_set; else bit_was_not_set; 850 return (x & nr); 851 } 852 853 int 854 bxe_cmpxchg(volatile int *addr, 855 int old, 856 int new) 857 { 858 int x; 859 do { 860 x = *addr; 861 } while (atomic_cmpset_acq_int(addr, old, new) == 0); 862 return (x); 863 } 864 865 /* 866 * Get DMA memory from the OS. 867 * 868 * Validates that the OS has provided DMA buffers in response to a 869 * bus_dmamap_load call and saves the physical address of those buffers. 870 * When the callback is used the OS will return 0 for the mapping function 871 * (bus_dmamap_load) so we use the value of map_arg->maxsegs to pass any 872 * failures back to the caller. 873 * 874 * Returns: 875 * Nothing. 876 */ 877 static void 878 bxe_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 879 { 880 struct bxe_dma *dma = arg; 881 882 if (error) { 883 dma->paddr = 0; 884 dma->nseg = 0; 885 BLOGE(dma->sc, "Failed DMA alloc '%s' (%d)!\n", dma->msg, error); 886 } else { 887 dma->paddr = segs->ds_addr; 888 dma->nseg = nseg; 889 } 890 } 891 892 /* 893 * Allocate a block of memory and map it for DMA. No partial completions 894 * allowed and release any resources acquired if we can't acquire all 895 * resources. 896 * 897 * Returns: 898 * 0 = Success, !0 = Failure 899 */ 900 int 901 bxe_dma_alloc(struct bxe_softc *sc, 902 bus_size_t size, 903 struct bxe_dma *dma, 904 const char *msg) 905 { 906 int rc; 907 908 if (dma->size > 0) { 909 BLOGE(sc, "dma block '%s' already has size %lu\n", msg, 910 (unsigned long)dma->size); 911 return (1); 912 } 913 914 memset(dma, 0, sizeof(*dma)); /* sanity */ 915 dma->sc = sc; 916 dma->size = size; 917 snprintf(dma->msg, sizeof(dma->msg), "%s", msg); 918 919 rc = bus_dma_tag_create(sc->parent_dma_tag, /* parent tag */ 920 BCM_PAGE_SIZE, /* alignment */ 921 0, /* boundary limit */ 922 BUS_SPACE_MAXADDR, /* restricted low */ 923 BUS_SPACE_MAXADDR, /* restricted hi */ 924 NULL, /* addr filter() */ 925 NULL, /* addr filter() arg */ 926 size, /* max map size */ 927 1, /* num discontinuous */ 928 size, /* max seg size */ 929 BUS_DMA_ALLOCNOW, /* flags */ 930 NULL, /* lock() */ 931 NULL, /* lock() arg */ 932 &dma->tag); /* returned dma tag */ 933 if (rc != 0) { 934 BLOGE(sc, "Failed to create dma tag for '%s' (%d)\n", msg, rc); 935 memset(dma, 0, sizeof(*dma)); 936 return (1); 937 } 938 939 rc = bus_dmamem_alloc(dma->tag, 940 (void **)&dma->vaddr, 941 (BUS_DMA_NOWAIT | BUS_DMA_ZERO), 942 &dma->map); 943 if (rc != 0) { 944 BLOGE(sc, "Failed to alloc dma mem for '%s' (%d)\n", msg, rc); 945 bus_dma_tag_destroy(dma->tag); 946 memset(dma, 0, sizeof(*dma)); 947 return (1); 948 } 949 950 rc = bus_dmamap_load(dma->tag, 951 dma->map, 952 dma->vaddr, 953 size, 954 bxe_dma_map_addr, /* BLOGD in here */ 955 dma, 956 BUS_DMA_NOWAIT); 957 if (rc != 0) { 958 BLOGE(sc, "Failed to load dma map for '%s' (%d)\n", msg, rc); 959 bus_dmamem_free(dma->tag, dma->vaddr, dma->map); 960 bus_dma_tag_destroy(dma->tag); 961 memset(dma, 0, sizeof(*dma)); 962 return (1); 963 } 964 965 return (0); 966 } 967 968 void 969 bxe_dma_free(struct bxe_softc *sc, 970 struct bxe_dma *dma) 971 { 972 if (dma->size > 0) { 973 DBASSERT(sc, (dma->tag != NULL), ("dma tag is NULL")); 974 975 bus_dmamap_sync(dma->tag, dma->map, 976 (BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE)); 977 bus_dmamap_unload(dma->tag, dma->map); 978 bus_dmamem_free(dma->tag, dma->vaddr, dma->map); 979 bus_dma_tag_destroy(dma->tag); 980 } 981 982 memset(dma, 0, sizeof(*dma)); 983 } 984 985 /* 986 * These indirect read and write routines are only during init. 987 * The locking is handled by the MCP. 988 */ 989 990 void 991 bxe_reg_wr_ind(struct bxe_softc *sc, 992 uint32_t addr, 993 uint32_t val) 994 { 995 pci_write_config(sc->dev, PCICFG_GRC_ADDRESS, addr, 4); 996 pci_write_config(sc->dev, PCICFG_GRC_DATA, val, 4); 997 pci_write_config(sc->dev, PCICFG_GRC_ADDRESS, 0, 4); 998 } 999 1000 uint32_t 1001 bxe_reg_rd_ind(struct bxe_softc *sc, 1002 uint32_t addr) 1003 { 1004 uint32_t val; 1005 1006 pci_write_config(sc->dev, PCICFG_GRC_ADDRESS, addr, 4); 1007 val = pci_read_config(sc->dev, PCICFG_GRC_DATA, 4); 1008 pci_write_config(sc->dev, PCICFG_GRC_ADDRESS, 0, 4); 1009 1010 return (val); 1011 } 1012 1013 static int 1014 bxe_acquire_hw_lock(struct bxe_softc *sc, 1015 uint32_t resource) 1016 { 1017 uint32_t lock_status; 1018 uint32_t resource_bit = (1 << resource); 1019 int func = SC_FUNC(sc); 1020 uint32_t hw_lock_control_reg; 1021 int cnt; 1022 1023 /* validate the resource is within range */ 1024 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { 1025 BLOGE(sc, "(resource 0x%x > HW_LOCK_MAX_RESOURCE_VALUE)" 1026 " resource_bit 0x%x\n", resource, resource_bit); 1027 return (-1); 1028 } 1029 1030 if (func <= 5) { 1031 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + (func * 8)); 1032 } else { 1033 hw_lock_control_reg = 1034 (MISC_REG_DRIVER_CONTROL_7 + ((func - 6) * 8)); 1035 } 1036 1037 /* validate the resource is not already taken */ 1038 lock_status = REG_RD(sc, hw_lock_control_reg); 1039 if (lock_status & resource_bit) { 1040 BLOGE(sc, "resource (0x%x) in use (status 0x%x bit 0x%x)\n", 1041 resource, lock_status, resource_bit); 1042 return (-1); 1043 } 1044 1045 /* try every 5ms for 5 seconds */ 1046 for (cnt = 0; cnt < 1000; cnt++) { 1047 REG_WR(sc, (hw_lock_control_reg + 4), resource_bit); 1048 lock_status = REG_RD(sc, hw_lock_control_reg); 1049 if (lock_status & resource_bit) { 1050 return (0); 1051 } 1052 DELAY(5000); 1053 } 1054 1055 BLOGE(sc, "Resource 0x%x resource_bit 0x%x lock timeout!\n", 1056 resource, resource_bit); 1057 return (-1); 1058 } 1059 1060 static int 1061 bxe_release_hw_lock(struct bxe_softc *sc, 1062 uint32_t resource) 1063 { 1064 uint32_t lock_status; 1065 uint32_t resource_bit = (1 << resource); 1066 int func = SC_FUNC(sc); 1067 uint32_t hw_lock_control_reg; 1068 1069 /* validate the resource is within range */ 1070 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { 1071 BLOGE(sc, "(resource 0x%x > HW_LOCK_MAX_RESOURCE_VALUE)" 1072 " resource_bit 0x%x\n", resource, resource_bit); 1073 return (-1); 1074 } 1075 1076 if (func <= 5) { 1077 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + (func * 8)); 1078 } else { 1079 hw_lock_control_reg = 1080 (MISC_REG_DRIVER_CONTROL_7 + ((func - 6) * 8)); 1081 } 1082 1083 /* validate the resource is currently taken */ 1084 lock_status = REG_RD(sc, hw_lock_control_reg); 1085 if (!(lock_status & resource_bit)) { 1086 BLOGE(sc, "resource (0x%x) not in use (status 0x%x bit 0x%x)\n", 1087 resource, lock_status, resource_bit); 1088 return (-1); 1089 } 1090 1091 REG_WR(sc, hw_lock_control_reg, resource_bit); 1092 return (0); 1093 } 1094 static void bxe_acquire_phy_lock(struct bxe_softc *sc) 1095 { 1096 BXE_PHY_LOCK(sc); 1097 bxe_acquire_hw_lock(sc,HW_LOCK_RESOURCE_MDIO); 1098 } 1099 1100 static void bxe_release_phy_lock(struct bxe_softc *sc) 1101 { 1102 bxe_release_hw_lock(sc,HW_LOCK_RESOURCE_MDIO); 1103 BXE_PHY_UNLOCK(sc); 1104 } 1105 /* 1106 * Per pf misc lock must be acquired before the per port mcp lock. Otherwise, 1107 * had we done things the other way around, if two pfs from the same port 1108 * would attempt to access nvram at the same time, we could run into a 1109 * scenario such as: 1110 * pf A takes the port lock. 1111 * pf B succeeds in taking the same lock since they are from the same port. 1112 * pf A takes the per pf misc lock. Performs eeprom access. 1113 * pf A finishes. Unlocks the per pf misc lock. 1114 * Pf B takes the lock and proceeds to perform it's own access. 1115 * pf A unlocks the per port lock, while pf B is still working (!). 1116 * mcp takes the per port lock and corrupts pf B's access (and/or has it's own 1117 * access corrupted by pf B).* 1118 */ 1119 static int 1120 bxe_acquire_nvram_lock(struct bxe_softc *sc) 1121 { 1122 int port = SC_PORT(sc); 1123 int count, i; 1124 uint32_t val = 0; 1125 1126 /* acquire HW lock: protect against other PFs in PF Direct Assignment */ 1127 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_NVRAM); 1128 1129 /* adjust timeout for emulation/FPGA */ 1130 count = NVRAM_TIMEOUT_COUNT; 1131 if (CHIP_REV_IS_SLOW(sc)) { 1132 count *= 100; 1133 } 1134 1135 /* request access to nvram interface */ 1136 REG_WR(sc, MCP_REG_MCPR_NVM_SW_ARB, 1137 (MCPR_NVM_SW_ARB_ARB_REQ_SET1 << port)); 1138 1139 for (i = 0; i < count*10; i++) { 1140 val = REG_RD(sc, MCP_REG_MCPR_NVM_SW_ARB); 1141 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) { 1142 break; 1143 } 1144 1145 DELAY(5); 1146 } 1147 1148 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) { 1149 BLOGE(sc, "Cannot get access to nvram interface " 1150 "port %d val 0x%x (MCPR_NVM_SW_ARB_ARB_ARB1 << port)\n", 1151 port, val); 1152 return (-1); 1153 } 1154 1155 return (0); 1156 } 1157 1158 static int 1159 bxe_release_nvram_lock(struct bxe_softc *sc) 1160 { 1161 int port = SC_PORT(sc); 1162 int count, i; 1163 uint32_t val = 0; 1164 1165 /* adjust timeout for emulation/FPGA */ 1166 count = NVRAM_TIMEOUT_COUNT; 1167 if (CHIP_REV_IS_SLOW(sc)) { 1168 count *= 100; 1169 } 1170 1171 /* relinquish nvram interface */ 1172 REG_WR(sc, MCP_REG_MCPR_NVM_SW_ARB, 1173 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << port)); 1174 1175 for (i = 0; i < count*10; i++) { 1176 val = REG_RD(sc, MCP_REG_MCPR_NVM_SW_ARB); 1177 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) { 1178 break; 1179 } 1180 1181 DELAY(5); 1182 } 1183 1184 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) { 1185 BLOGE(sc, "Cannot free access to nvram interface " 1186 "port %d val 0x%x (MCPR_NVM_SW_ARB_ARB_ARB1 << port)\n", 1187 port, val); 1188 return (-1); 1189 } 1190 1191 /* release HW lock: protect against other PFs in PF Direct Assignment */ 1192 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_NVRAM); 1193 1194 return (0); 1195 } 1196 1197 static void 1198 bxe_enable_nvram_access(struct bxe_softc *sc) 1199 { 1200 uint32_t val; 1201 1202 val = REG_RD(sc, MCP_REG_MCPR_NVM_ACCESS_ENABLE); 1203 1204 /* enable both bits, even on read */ 1205 REG_WR(sc, MCP_REG_MCPR_NVM_ACCESS_ENABLE, 1206 (val | MCPR_NVM_ACCESS_ENABLE_EN | MCPR_NVM_ACCESS_ENABLE_WR_EN)); 1207 } 1208 1209 static void 1210 bxe_disable_nvram_access(struct bxe_softc *sc) 1211 { 1212 uint32_t val; 1213 1214 val = REG_RD(sc, MCP_REG_MCPR_NVM_ACCESS_ENABLE); 1215 1216 /* disable both bits, even after read */ 1217 REG_WR(sc, MCP_REG_MCPR_NVM_ACCESS_ENABLE, 1218 (val & ~(MCPR_NVM_ACCESS_ENABLE_EN | 1219 MCPR_NVM_ACCESS_ENABLE_WR_EN))); 1220 } 1221 1222 static int 1223 bxe_nvram_read_dword(struct bxe_softc *sc, 1224 uint32_t offset, 1225 uint32_t *ret_val, 1226 uint32_t cmd_flags) 1227 { 1228 int count, i, rc; 1229 uint32_t val; 1230 1231 /* build the command word */ 1232 cmd_flags |= MCPR_NVM_COMMAND_DOIT; 1233 1234 /* need to clear DONE bit separately */ 1235 REG_WR(sc, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE); 1236 1237 /* address of the NVRAM to read from */ 1238 REG_WR(sc, MCP_REG_MCPR_NVM_ADDR, 1239 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE)); 1240 1241 /* issue a read command */ 1242 REG_WR(sc, MCP_REG_MCPR_NVM_COMMAND, cmd_flags); 1243 1244 /* adjust timeout for emulation/FPGA */ 1245 count = NVRAM_TIMEOUT_COUNT; 1246 if (CHIP_REV_IS_SLOW(sc)) { 1247 count *= 100; 1248 } 1249 1250 /* wait for completion */ 1251 *ret_val = 0; 1252 rc = -1; 1253 for (i = 0; i < count; i++) { 1254 DELAY(5); 1255 val = REG_RD(sc, MCP_REG_MCPR_NVM_COMMAND); 1256 1257 if (val & MCPR_NVM_COMMAND_DONE) { 1258 val = REG_RD(sc, MCP_REG_MCPR_NVM_READ); 1259 /* we read nvram data in cpu order 1260 * but ethtool sees it as an array of bytes 1261 * converting to big-endian will do the work 1262 */ 1263 *ret_val = htobe32(val); 1264 rc = 0; 1265 break; 1266 } 1267 } 1268 1269 if (rc == -1) { 1270 BLOGE(sc, "nvram read timeout expired " 1271 "(offset 0x%x cmd_flags 0x%x val 0x%x)\n", 1272 offset, cmd_flags, val); 1273 } 1274 1275 return (rc); 1276 } 1277 1278 static int 1279 bxe_nvram_read(struct bxe_softc *sc, 1280 uint32_t offset, 1281 uint8_t *ret_buf, 1282 int buf_size) 1283 { 1284 uint32_t cmd_flags; 1285 uint32_t val; 1286 int rc; 1287 1288 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) { 1289 BLOGE(sc, "Invalid parameter, offset 0x%x buf_size 0x%x\n", 1290 offset, buf_size); 1291 return (-1); 1292 } 1293 1294 if ((offset + buf_size) > sc->devinfo.flash_size) { 1295 BLOGE(sc, "Invalid parameter, " 1296 "offset 0x%x + buf_size 0x%x > flash_size 0x%x\n", 1297 offset, buf_size, sc->devinfo.flash_size); 1298 return (-1); 1299 } 1300 1301 /* request access to nvram interface */ 1302 rc = bxe_acquire_nvram_lock(sc); 1303 if (rc) { 1304 return (rc); 1305 } 1306 1307 /* enable access to nvram interface */ 1308 bxe_enable_nvram_access(sc); 1309 1310 /* read the first word(s) */ 1311 cmd_flags = MCPR_NVM_COMMAND_FIRST; 1312 while ((buf_size > sizeof(uint32_t)) && (rc == 0)) { 1313 rc = bxe_nvram_read_dword(sc, offset, &val, cmd_flags); 1314 memcpy(ret_buf, &val, 4); 1315 1316 /* advance to the next dword */ 1317 offset += sizeof(uint32_t); 1318 ret_buf += sizeof(uint32_t); 1319 buf_size -= sizeof(uint32_t); 1320 cmd_flags = 0; 1321 } 1322 1323 if (rc == 0) { 1324 cmd_flags |= MCPR_NVM_COMMAND_LAST; 1325 rc = bxe_nvram_read_dword(sc, offset, &val, cmd_flags); 1326 memcpy(ret_buf, &val, 4); 1327 } 1328 1329 /* disable access to nvram interface */ 1330 bxe_disable_nvram_access(sc); 1331 bxe_release_nvram_lock(sc); 1332 1333 return (rc); 1334 } 1335 1336 static int 1337 bxe_nvram_write_dword(struct bxe_softc *sc, 1338 uint32_t offset, 1339 uint32_t val, 1340 uint32_t cmd_flags) 1341 { 1342 int count, i, rc; 1343 1344 /* build the command word */ 1345 cmd_flags |= (MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WR); 1346 1347 /* need to clear DONE bit separately */ 1348 REG_WR(sc, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE); 1349 1350 /* write the data */ 1351 REG_WR(sc, MCP_REG_MCPR_NVM_WRITE, val); 1352 1353 /* address of the NVRAM to write to */ 1354 REG_WR(sc, MCP_REG_MCPR_NVM_ADDR, 1355 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE)); 1356 1357 /* issue the write command */ 1358 REG_WR(sc, MCP_REG_MCPR_NVM_COMMAND, cmd_flags); 1359 1360 /* adjust timeout for emulation/FPGA */ 1361 count = NVRAM_TIMEOUT_COUNT; 1362 if (CHIP_REV_IS_SLOW(sc)) { 1363 count *= 100; 1364 } 1365 1366 /* wait for completion */ 1367 rc = -1; 1368 for (i = 0; i < count; i++) { 1369 DELAY(5); 1370 val = REG_RD(sc, MCP_REG_MCPR_NVM_COMMAND); 1371 if (val & MCPR_NVM_COMMAND_DONE) { 1372 rc = 0; 1373 break; 1374 } 1375 } 1376 1377 if (rc == -1) { 1378 BLOGE(sc, "nvram write timeout expired " 1379 "(offset 0x%x cmd_flags 0x%x val 0x%x)\n", 1380 offset, cmd_flags, val); 1381 } 1382 1383 return (rc); 1384 } 1385 1386 #define BYTE_OFFSET(offset) (8 * (offset & 0x03)) 1387 1388 static int 1389 bxe_nvram_write1(struct bxe_softc *sc, 1390 uint32_t offset, 1391 uint8_t *data_buf, 1392 int buf_size) 1393 { 1394 uint32_t cmd_flags; 1395 uint32_t align_offset; 1396 uint32_t val; 1397 int rc; 1398 1399 if ((offset + buf_size) > sc->devinfo.flash_size) { 1400 BLOGE(sc, "Invalid parameter, " 1401 "offset 0x%x + buf_size 0x%x > flash_size 0x%x\n", 1402 offset, buf_size, sc->devinfo.flash_size); 1403 return (-1); 1404 } 1405 1406 /* request access to nvram interface */ 1407 rc = bxe_acquire_nvram_lock(sc); 1408 if (rc) { 1409 return (rc); 1410 } 1411 1412 /* enable access to nvram interface */ 1413 bxe_enable_nvram_access(sc); 1414 1415 cmd_flags = (MCPR_NVM_COMMAND_FIRST | MCPR_NVM_COMMAND_LAST); 1416 align_offset = (offset & ~0x03); 1417 rc = bxe_nvram_read_dword(sc, align_offset, &val, cmd_flags); 1418 1419 if (rc == 0) { 1420 val &= ~(0xff << BYTE_OFFSET(offset)); 1421 val |= (*data_buf << BYTE_OFFSET(offset)); 1422 1423 /* nvram data is returned as an array of bytes 1424 * convert it back to cpu order 1425 */ 1426 val = be32toh(val); 1427 1428 rc = bxe_nvram_write_dword(sc, align_offset, val, cmd_flags); 1429 } 1430 1431 /* disable access to nvram interface */ 1432 bxe_disable_nvram_access(sc); 1433 bxe_release_nvram_lock(sc); 1434 1435 return (rc); 1436 } 1437 1438 static int 1439 bxe_nvram_write(struct bxe_softc *sc, 1440 uint32_t offset, 1441 uint8_t *data_buf, 1442 int buf_size) 1443 { 1444 uint32_t cmd_flags; 1445 uint32_t val; 1446 uint32_t written_so_far; 1447 int rc; 1448 1449 if (buf_size == 1) { 1450 return (bxe_nvram_write1(sc, offset, data_buf, buf_size)); 1451 } 1452 1453 if ((offset & 0x03) || (buf_size & 0x03) /* || (buf_size == 0) */) { 1454 BLOGE(sc, "Invalid parameter, offset 0x%x buf_size 0x%x\n", 1455 offset, buf_size); 1456 return (-1); 1457 } 1458 1459 if (buf_size == 0) { 1460 return (0); /* nothing to do */ 1461 } 1462 1463 if ((offset + buf_size) > sc->devinfo.flash_size) { 1464 BLOGE(sc, "Invalid parameter, " 1465 "offset 0x%x + buf_size 0x%x > flash_size 0x%x\n", 1466 offset, buf_size, sc->devinfo.flash_size); 1467 return (-1); 1468 } 1469 1470 /* request access to nvram interface */ 1471 rc = bxe_acquire_nvram_lock(sc); 1472 if (rc) { 1473 return (rc); 1474 } 1475 1476 /* enable access to nvram interface */ 1477 bxe_enable_nvram_access(sc); 1478 1479 written_so_far = 0; 1480 cmd_flags = MCPR_NVM_COMMAND_FIRST; 1481 while ((written_so_far < buf_size) && (rc == 0)) { 1482 if (written_so_far == (buf_size - sizeof(uint32_t))) { 1483 cmd_flags |= MCPR_NVM_COMMAND_LAST; 1484 } else if (((offset + 4) % NVRAM_PAGE_SIZE) == 0) { 1485 cmd_flags |= MCPR_NVM_COMMAND_LAST; 1486 } else if ((offset % NVRAM_PAGE_SIZE) == 0) { 1487 cmd_flags |= MCPR_NVM_COMMAND_FIRST; 1488 } 1489 1490 memcpy(&val, data_buf, 4); 1491 1492 rc = bxe_nvram_write_dword(sc, offset, val, cmd_flags); 1493 1494 /* advance to the next dword */ 1495 offset += sizeof(uint32_t); 1496 data_buf += sizeof(uint32_t); 1497 written_so_far += sizeof(uint32_t); 1498 cmd_flags = 0; 1499 } 1500 1501 /* disable access to nvram interface */ 1502 bxe_disable_nvram_access(sc); 1503 bxe_release_nvram_lock(sc); 1504 1505 return (rc); 1506 } 1507 1508 /* copy command into DMAE command memory and set DMAE command Go */ 1509 void 1510 bxe_post_dmae(struct bxe_softc *sc, 1511 struct dmae_cmd *dmae, 1512 int idx) 1513 { 1514 uint32_t cmd_offset; 1515 int i; 1516 1517 cmd_offset = (DMAE_REG_CMD_MEM + (sizeof(struct dmae_cmd) * idx)); 1518 for (i = 0; i < ((sizeof(struct dmae_cmd) / 4)); i++) { 1519 REG_WR(sc, (cmd_offset + (i * 4)), *(((uint32_t *)dmae) + i)); 1520 } 1521 1522 REG_WR(sc, dmae_reg_go_c[idx], 1); 1523 } 1524 1525 uint32_t 1526 bxe_dmae_opcode_add_comp(uint32_t opcode, 1527 uint8_t comp_type) 1528 { 1529 return (opcode | ((comp_type << DMAE_CMD_C_DST_SHIFT) | 1530 DMAE_CMD_C_TYPE_ENABLE)); 1531 } 1532 1533 uint32_t 1534 bxe_dmae_opcode_clr_src_reset(uint32_t opcode) 1535 { 1536 return (opcode & ~DMAE_CMD_SRC_RESET); 1537 } 1538 1539 uint32_t 1540 bxe_dmae_opcode(struct bxe_softc *sc, 1541 uint8_t src_type, 1542 uint8_t dst_type, 1543 uint8_t with_comp, 1544 uint8_t comp_type) 1545 { 1546 uint32_t opcode = 0; 1547 1548 opcode |= ((src_type << DMAE_CMD_SRC_SHIFT) | 1549 (dst_type << DMAE_CMD_DST_SHIFT)); 1550 1551 opcode |= (DMAE_CMD_SRC_RESET | DMAE_CMD_DST_RESET); 1552 1553 opcode |= (SC_PORT(sc) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0); 1554 1555 opcode |= ((SC_VN(sc) << DMAE_CMD_E1HVN_SHIFT) | 1556 (SC_VN(sc) << DMAE_CMD_DST_VN_SHIFT)); 1557 1558 opcode |= (DMAE_COM_SET_ERR << DMAE_CMD_ERR_POLICY_SHIFT); 1559 1560 #ifdef __BIG_ENDIAN 1561 opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP; 1562 #else 1563 opcode |= DMAE_CMD_ENDIANITY_DW_SWAP; 1564 #endif 1565 1566 if (with_comp) { 1567 opcode = bxe_dmae_opcode_add_comp(opcode, comp_type); 1568 } 1569 1570 return (opcode); 1571 } 1572 1573 static void 1574 bxe_prep_dmae_with_comp(struct bxe_softc *sc, 1575 struct dmae_cmd *dmae, 1576 uint8_t src_type, 1577 uint8_t dst_type) 1578 { 1579 memset(dmae, 0, sizeof(struct dmae_cmd)); 1580 1581 /* set the opcode */ 1582 dmae->opcode = bxe_dmae_opcode(sc, src_type, dst_type, 1583 TRUE, DMAE_COMP_PCI); 1584 1585 /* fill in the completion parameters */ 1586 dmae->comp_addr_lo = U64_LO(BXE_SP_MAPPING(sc, wb_comp)); 1587 dmae->comp_addr_hi = U64_HI(BXE_SP_MAPPING(sc, wb_comp)); 1588 dmae->comp_val = DMAE_COMP_VAL; 1589 } 1590 1591 /* issue a DMAE command over the init channel and wait for completion */ 1592 static int 1593 bxe_issue_dmae_with_comp(struct bxe_softc *sc, 1594 struct dmae_cmd *dmae) 1595 { 1596 uint32_t *wb_comp = BXE_SP(sc, wb_comp); 1597 int timeout = CHIP_REV_IS_SLOW(sc) ? 400000 : 4000; 1598 1599 BXE_DMAE_LOCK(sc); 1600 1601 /* reset completion */ 1602 *wb_comp = 0; 1603 1604 /* post the command on the channel used for initializations */ 1605 bxe_post_dmae(sc, dmae, INIT_DMAE_C(sc)); 1606 1607 /* wait for completion */ 1608 DELAY(5); 1609 1610 while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) { 1611 if (!timeout || 1612 (sc->recovery_state != BXE_RECOVERY_DONE && 1613 sc->recovery_state != BXE_RECOVERY_NIC_LOADING)) { 1614 BLOGE(sc, "DMAE timeout! *wb_comp 0x%x recovery_state 0x%x\n", 1615 *wb_comp, sc->recovery_state); 1616 BXE_DMAE_UNLOCK(sc); 1617 return (DMAE_TIMEOUT); 1618 } 1619 1620 timeout--; 1621 DELAY(50); 1622 } 1623 1624 if (*wb_comp & DMAE_PCI_ERR_FLAG) { 1625 BLOGE(sc, "DMAE PCI error! *wb_comp 0x%x recovery_state 0x%x\n", 1626 *wb_comp, sc->recovery_state); 1627 BXE_DMAE_UNLOCK(sc); 1628 return (DMAE_PCI_ERROR); 1629 } 1630 1631 BXE_DMAE_UNLOCK(sc); 1632 return (0); 1633 } 1634 1635 void 1636 bxe_read_dmae(struct bxe_softc *sc, 1637 uint32_t src_addr, 1638 uint32_t len32) 1639 { 1640 struct dmae_cmd dmae; 1641 uint32_t *data; 1642 int i, rc; 1643 1644 DBASSERT(sc, (len32 <= 4), ("DMAE read length is %d", len32)); 1645 1646 if (!sc->dmae_ready) { 1647 data = BXE_SP(sc, wb_data[0]); 1648 1649 for (i = 0; i < len32; i++) { 1650 data[i] = (CHIP_IS_E1(sc)) ? 1651 bxe_reg_rd_ind(sc, (src_addr + (i * 4))) : 1652 REG_RD(sc, (src_addr + (i * 4))); 1653 } 1654 1655 return; 1656 } 1657 1658 /* set opcode and fixed command fields */ 1659 bxe_prep_dmae_with_comp(sc, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI); 1660 1661 /* fill in addresses and len */ 1662 dmae.src_addr_lo = (src_addr >> 2); /* GRC addr has dword resolution */ 1663 dmae.src_addr_hi = 0; 1664 dmae.dst_addr_lo = U64_LO(BXE_SP_MAPPING(sc, wb_data)); 1665 dmae.dst_addr_hi = U64_HI(BXE_SP_MAPPING(sc, wb_data)); 1666 dmae.len = len32; 1667 1668 /* issue the command and wait for completion */ 1669 if ((rc = bxe_issue_dmae_with_comp(sc, &dmae)) != 0) { 1670 bxe_panic(sc, ("DMAE failed (%d)\n", rc)); 1671 } 1672 } 1673 1674 void 1675 bxe_write_dmae(struct bxe_softc *sc, 1676 bus_addr_t dma_addr, 1677 uint32_t dst_addr, 1678 uint32_t len32) 1679 { 1680 struct dmae_cmd dmae; 1681 int rc; 1682 1683 if (!sc->dmae_ready) { 1684 DBASSERT(sc, (len32 <= 4), ("DMAE not ready and length is %d", len32)); 1685 1686 if (CHIP_IS_E1(sc)) { 1687 ecore_init_ind_wr(sc, dst_addr, BXE_SP(sc, wb_data[0]), len32); 1688 } else { 1689 ecore_init_str_wr(sc, dst_addr, BXE_SP(sc, wb_data[0]), len32); 1690 } 1691 1692 return; 1693 } 1694 1695 /* set opcode and fixed command fields */ 1696 bxe_prep_dmae_with_comp(sc, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC); 1697 1698 /* fill in addresses and len */ 1699 dmae.src_addr_lo = U64_LO(dma_addr); 1700 dmae.src_addr_hi = U64_HI(dma_addr); 1701 dmae.dst_addr_lo = (dst_addr >> 2); /* GRC addr has dword resolution */ 1702 dmae.dst_addr_hi = 0; 1703 dmae.len = len32; 1704 1705 /* issue the command and wait for completion */ 1706 if ((rc = bxe_issue_dmae_with_comp(sc, &dmae)) != 0) { 1707 bxe_panic(sc, ("DMAE failed (%d)\n", rc)); 1708 } 1709 } 1710 1711 void 1712 bxe_write_dmae_phys_len(struct bxe_softc *sc, 1713 bus_addr_t phys_addr, 1714 uint32_t addr, 1715 uint32_t len) 1716 { 1717 int dmae_wr_max = DMAE_LEN32_WR_MAX(sc); 1718 int offset = 0; 1719 1720 while (len > dmae_wr_max) { 1721 bxe_write_dmae(sc, 1722 (phys_addr + offset), /* src DMA address */ 1723 (addr + offset), /* dst GRC address */ 1724 dmae_wr_max); 1725 offset += (dmae_wr_max * 4); 1726 len -= dmae_wr_max; 1727 } 1728 1729 bxe_write_dmae(sc, 1730 (phys_addr + offset), /* src DMA address */ 1731 (addr + offset), /* dst GRC address */ 1732 len); 1733 } 1734 1735 void 1736 bxe_set_ctx_validation(struct bxe_softc *sc, 1737 struct eth_context *cxt, 1738 uint32_t cid) 1739 { 1740 /* ustorm cxt validation */ 1741 cxt->ustorm_ag_context.cdu_usage = 1742 CDU_RSRVD_VALUE_TYPE_A(HW_CID(sc, cid), 1743 CDU_REGION_NUMBER_UCM_AG, ETH_CONNECTION_TYPE); 1744 /* xcontext validation */ 1745 cxt->xstorm_ag_context.cdu_reserved = 1746 CDU_RSRVD_VALUE_TYPE_A(HW_CID(sc, cid), 1747 CDU_REGION_NUMBER_XCM_AG, ETH_CONNECTION_TYPE); 1748 } 1749 1750 static void 1751 bxe_storm_memset_hc_timeout(struct bxe_softc *sc, 1752 uint8_t port, 1753 uint8_t fw_sb_id, 1754 uint8_t sb_index, 1755 uint8_t ticks) 1756 { 1757 uint32_t addr = 1758 (BAR_CSTRORM_INTMEM + 1759 CSTORM_STATUS_BLOCK_DATA_TIMEOUT_OFFSET(fw_sb_id, sb_index)); 1760 1761 REG_WR8(sc, addr, ticks); 1762 1763 BLOGD(sc, DBG_LOAD, 1764 "port %d fw_sb_id %d sb_index %d ticks %d\n", 1765 port, fw_sb_id, sb_index, ticks); 1766 } 1767 1768 static void 1769 bxe_storm_memset_hc_disable(struct bxe_softc *sc, 1770 uint8_t port, 1771 uint16_t fw_sb_id, 1772 uint8_t sb_index, 1773 uint8_t disable) 1774 { 1775 uint32_t enable_flag = 1776 (disable) ? 0 : (1 << HC_INDEX_DATA_HC_ENABLED_SHIFT); 1777 uint32_t addr = 1778 (BAR_CSTRORM_INTMEM + 1779 CSTORM_STATUS_BLOCK_DATA_FLAGS_OFFSET(fw_sb_id, sb_index)); 1780 uint8_t flags; 1781 1782 /* clear and set */ 1783 flags = REG_RD8(sc, addr); 1784 flags &= ~HC_INDEX_DATA_HC_ENABLED; 1785 flags |= enable_flag; 1786 REG_WR8(sc, addr, flags); 1787 1788 BLOGD(sc, DBG_LOAD, 1789 "port %d fw_sb_id %d sb_index %d disable %d\n", 1790 port, fw_sb_id, sb_index, disable); 1791 } 1792 1793 void 1794 bxe_update_coalesce_sb_index(struct bxe_softc *sc, 1795 uint8_t fw_sb_id, 1796 uint8_t sb_index, 1797 uint8_t disable, 1798 uint16_t usec) 1799 { 1800 int port = SC_PORT(sc); 1801 uint8_t ticks = (usec / 4); /* XXX ??? */ 1802 1803 bxe_storm_memset_hc_timeout(sc, port, fw_sb_id, sb_index, ticks); 1804 1805 disable = (disable) ? 1 : ((usec) ? 0 : 1); 1806 bxe_storm_memset_hc_disable(sc, port, fw_sb_id, sb_index, disable); 1807 } 1808 1809 void 1810 elink_cb_udelay(struct bxe_softc *sc, 1811 uint32_t usecs) 1812 { 1813 DELAY(usecs); 1814 } 1815 1816 uint32_t 1817 elink_cb_reg_read(struct bxe_softc *sc, 1818 uint32_t reg_addr) 1819 { 1820 return (REG_RD(sc, reg_addr)); 1821 } 1822 1823 void 1824 elink_cb_reg_write(struct bxe_softc *sc, 1825 uint32_t reg_addr, 1826 uint32_t val) 1827 { 1828 REG_WR(sc, reg_addr, val); 1829 } 1830 1831 void 1832 elink_cb_reg_wb_write(struct bxe_softc *sc, 1833 uint32_t offset, 1834 uint32_t *wb_write, 1835 uint16_t len) 1836 { 1837 REG_WR_DMAE(sc, offset, wb_write, len); 1838 } 1839 1840 void 1841 elink_cb_reg_wb_read(struct bxe_softc *sc, 1842 uint32_t offset, 1843 uint32_t *wb_write, 1844 uint16_t len) 1845 { 1846 REG_RD_DMAE(sc, offset, wb_write, len); 1847 } 1848 1849 uint8_t 1850 elink_cb_path_id(struct bxe_softc *sc) 1851 { 1852 return (SC_PATH(sc)); 1853 } 1854 1855 void 1856 elink_cb_event_log(struct bxe_softc *sc, 1857 const elink_log_id_t elink_log_id, 1858 ...) 1859 { 1860 /* XXX */ 1861 BLOGI(sc, "ELINK EVENT LOG (%d)\n", elink_log_id); 1862 } 1863 1864 static int 1865 bxe_set_spio(struct bxe_softc *sc, 1866 int spio, 1867 uint32_t mode) 1868 { 1869 uint32_t spio_reg; 1870 1871 /* Only 2 SPIOs are configurable */ 1872 if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) { 1873 BLOGE(sc, "Invalid SPIO 0x%x mode 0x%x\n", spio, mode); 1874 return (-1); 1875 } 1876 1877 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_SPIO); 1878 1879 /* read SPIO and mask except the float bits */ 1880 spio_reg = (REG_RD(sc, MISC_REG_SPIO) & MISC_SPIO_FLOAT); 1881 1882 switch (mode) { 1883 case MISC_SPIO_OUTPUT_LOW: 1884 BLOGD(sc, DBG_LOAD, "Set SPIO 0x%x -> output low\n", spio); 1885 /* clear FLOAT and set CLR */ 1886 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS); 1887 spio_reg |= (spio << MISC_SPIO_CLR_POS); 1888 break; 1889 1890 case MISC_SPIO_OUTPUT_HIGH: 1891 BLOGD(sc, DBG_LOAD, "Set SPIO 0x%x -> output high\n", spio); 1892 /* clear FLOAT and set SET */ 1893 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS); 1894 spio_reg |= (spio << MISC_SPIO_SET_POS); 1895 break; 1896 1897 case MISC_SPIO_INPUT_HI_Z: 1898 BLOGD(sc, DBG_LOAD, "Set SPIO 0x%x -> input\n", spio); 1899 /* set FLOAT */ 1900 spio_reg |= (spio << MISC_SPIO_FLOAT_POS); 1901 break; 1902 1903 default: 1904 break; 1905 } 1906 1907 REG_WR(sc, MISC_REG_SPIO, spio_reg); 1908 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_SPIO); 1909 1910 return (0); 1911 } 1912 1913 static int 1914 bxe_gpio_read(struct bxe_softc *sc, 1915 int gpio_num, 1916 uint8_t port) 1917 { 1918 /* The GPIO should be swapped if swap register is set and active */ 1919 int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) && 1920 REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port); 1921 int gpio_shift = (gpio_num + 1922 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0)); 1923 uint32_t gpio_mask = (1 << gpio_shift); 1924 uint32_t gpio_reg; 1925 1926 if (gpio_num > MISC_REGISTERS_GPIO_3) { 1927 BLOGE(sc, "Invalid GPIO %d port 0x%x gpio_port %d gpio_shift %d" 1928 " gpio_mask 0x%x\n", gpio_num, port, gpio_port, gpio_shift, 1929 gpio_mask); 1930 return (-1); 1931 } 1932 1933 /* read GPIO value */ 1934 gpio_reg = REG_RD(sc, MISC_REG_GPIO); 1935 1936 /* get the requested pin value */ 1937 return ((gpio_reg & gpio_mask) == gpio_mask) ? 1 : 0; 1938 } 1939 1940 static int 1941 bxe_gpio_write(struct bxe_softc *sc, 1942 int gpio_num, 1943 uint32_t mode, 1944 uint8_t port) 1945 { 1946 /* The GPIO should be swapped if swap register is set and active */ 1947 int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) && 1948 REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port); 1949 int gpio_shift = (gpio_num + 1950 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0)); 1951 uint32_t gpio_mask = (1 << gpio_shift); 1952 uint32_t gpio_reg; 1953 1954 if (gpio_num > MISC_REGISTERS_GPIO_3) { 1955 BLOGE(sc, "Invalid GPIO %d mode 0x%x port 0x%x gpio_port %d" 1956 " gpio_shift %d gpio_mask 0x%x\n", 1957 gpio_num, mode, port, gpio_port, gpio_shift, gpio_mask); 1958 return (-1); 1959 } 1960 1961 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO); 1962 1963 /* read GPIO and mask except the float bits */ 1964 gpio_reg = (REG_RD(sc, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT); 1965 1966 switch (mode) { 1967 case MISC_REGISTERS_GPIO_OUTPUT_LOW: 1968 BLOGD(sc, DBG_PHY, 1969 "Set GPIO %d (shift %d) -> output low\n", 1970 gpio_num, gpio_shift); 1971 /* clear FLOAT and set CLR */ 1972 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); 1973 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS); 1974 break; 1975 1976 case MISC_REGISTERS_GPIO_OUTPUT_HIGH: 1977 BLOGD(sc, DBG_PHY, 1978 "Set GPIO %d (shift %d) -> output high\n", 1979 gpio_num, gpio_shift); 1980 /* clear FLOAT and set SET */ 1981 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); 1982 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS); 1983 break; 1984 1985 case MISC_REGISTERS_GPIO_INPUT_HI_Z: 1986 BLOGD(sc, DBG_PHY, 1987 "Set GPIO %d (shift %d) -> input\n", 1988 gpio_num, gpio_shift); 1989 /* set FLOAT */ 1990 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); 1991 break; 1992 1993 default: 1994 break; 1995 } 1996 1997 REG_WR(sc, MISC_REG_GPIO, gpio_reg); 1998 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO); 1999 2000 return (0); 2001 } 2002 2003 static int 2004 bxe_gpio_mult_write(struct bxe_softc *sc, 2005 uint8_t pins, 2006 uint32_t mode) 2007 { 2008 uint32_t gpio_reg; 2009 2010 /* any port swapping should be handled by caller */ 2011 2012 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO); 2013 2014 /* read GPIO and mask except the float bits */ 2015 gpio_reg = REG_RD(sc, MISC_REG_GPIO); 2016 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS); 2017 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS); 2018 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS); 2019 2020 switch (mode) { 2021 case MISC_REGISTERS_GPIO_OUTPUT_LOW: 2022 BLOGD(sc, DBG_PHY, "Set GPIO 0x%x -> output low\n", pins); 2023 /* set CLR */ 2024 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS); 2025 break; 2026 2027 case MISC_REGISTERS_GPIO_OUTPUT_HIGH: 2028 BLOGD(sc, DBG_PHY, "Set GPIO 0x%x -> output high\n", pins); 2029 /* set SET */ 2030 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS); 2031 break; 2032 2033 case MISC_REGISTERS_GPIO_INPUT_HI_Z: 2034 BLOGD(sc, DBG_PHY, "Set GPIO 0x%x -> input\n", pins); 2035 /* set FLOAT */ 2036 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS); 2037 break; 2038 2039 default: 2040 BLOGE(sc, "Invalid GPIO mode assignment pins 0x%x mode 0x%x" 2041 " gpio_reg 0x%x\n", pins, mode, gpio_reg); 2042 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO); 2043 return (-1); 2044 } 2045 2046 REG_WR(sc, MISC_REG_GPIO, gpio_reg); 2047 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO); 2048 2049 return (0); 2050 } 2051 2052 static int 2053 bxe_gpio_int_write(struct bxe_softc *sc, 2054 int gpio_num, 2055 uint32_t mode, 2056 uint8_t port) 2057 { 2058 /* The GPIO should be swapped if swap register is set and active */ 2059 int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) && 2060 REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port); 2061 int gpio_shift = (gpio_num + 2062 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0)); 2063 uint32_t gpio_mask = (1 << gpio_shift); 2064 uint32_t gpio_reg; 2065 2066 if (gpio_num > MISC_REGISTERS_GPIO_3) { 2067 BLOGE(sc, "Invalid GPIO %d mode 0x%x port 0x%x gpio_port %d" 2068 " gpio_shift %d gpio_mask 0x%x\n", 2069 gpio_num, mode, port, gpio_port, gpio_shift, gpio_mask); 2070 return (-1); 2071 } 2072 2073 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO); 2074 2075 /* read GPIO int */ 2076 gpio_reg = REG_RD(sc, MISC_REG_GPIO_INT); 2077 2078 switch (mode) { 2079 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR: 2080 BLOGD(sc, DBG_PHY, 2081 "Clear GPIO INT %d (shift %d) -> output low\n", 2082 gpio_num, gpio_shift); 2083 /* clear SET and set CLR */ 2084 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS); 2085 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS); 2086 break; 2087 2088 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET: 2089 BLOGD(sc, DBG_PHY, 2090 "Set GPIO INT %d (shift %d) -> output high\n", 2091 gpio_num, gpio_shift); 2092 /* clear CLR and set SET */ 2093 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS); 2094 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS); 2095 break; 2096 2097 default: 2098 break; 2099 } 2100 2101 REG_WR(sc, MISC_REG_GPIO_INT, gpio_reg); 2102 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO); 2103 2104 return (0); 2105 } 2106 2107 uint32_t 2108 elink_cb_gpio_read(struct bxe_softc *sc, 2109 uint16_t gpio_num, 2110 uint8_t port) 2111 { 2112 return (bxe_gpio_read(sc, gpio_num, port)); 2113 } 2114 2115 uint8_t 2116 elink_cb_gpio_write(struct bxe_softc *sc, 2117 uint16_t gpio_num, 2118 uint8_t mode, /* 0=low 1=high */ 2119 uint8_t port) 2120 { 2121 return (bxe_gpio_write(sc, gpio_num, mode, port)); 2122 } 2123 2124 uint8_t 2125 elink_cb_gpio_mult_write(struct bxe_softc *sc, 2126 uint8_t pins, 2127 uint8_t mode) /* 0=low 1=high */ 2128 { 2129 return (bxe_gpio_mult_write(sc, pins, mode)); 2130 } 2131 2132 uint8_t 2133 elink_cb_gpio_int_write(struct bxe_softc *sc, 2134 uint16_t gpio_num, 2135 uint8_t mode, /* 0=low 1=high */ 2136 uint8_t port) 2137 { 2138 return (bxe_gpio_int_write(sc, gpio_num, mode, port)); 2139 } 2140 2141 void 2142 elink_cb_notify_link_changed(struct bxe_softc *sc) 2143 { 2144 REG_WR(sc, (MISC_REG_AEU_GENERAL_ATTN_12 + 2145 (SC_FUNC(sc) * sizeof(uint32_t))), 1); 2146 } 2147 2148 /* send the MCP a request, block until there is a reply */ 2149 uint32_t 2150 elink_cb_fw_command(struct bxe_softc *sc, 2151 uint32_t command, 2152 uint32_t param) 2153 { 2154 int mb_idx = SC_FW_MB_IDX(sc); 2155 uint32_t seq; 2156 uint32_t rc = 0; 2157 uint32_t cnt = 1; 2158 uint8_t delay = CHIP_REV_IS_SLOW(sc) ? 100 : 10; 2159 2160 BXE_FWMB_LOCK(sc); 2161 2162 seq = ++sc->fw_seq; 2163 SHMEM_WR(sc, func_mb[mb_idx].drv_mb_param, param); 2164 SHMEM_WR(sc, func_mb[mb_idx].drv_mb_header, (command | seq)); 2165 2166 BLOGD(sc, DBG_PHY, 2167 "wrote command 0x%08x to FW MB param 0x%08x\n", 2168 (command | seq), param); 2169 2170 /* Let the FW do it's magic. GIve it up to 5 seconds... */ 2171 do { 2172 DELAY(delay * 1000); 2173 rc = SHMEM_RD(sc, func_mb[mb_idx].fw_mb_header); 2174 } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500)); 2175 2176 BLOGD(sc, DBG_PHY, 2177 "[after %d ms] read 0x%x seq 0x%x from FW MB\n", 2178 cnt*delay, rc, seq); 2179 2180 /* is this a reply to our command? */ 2181 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK)) { 2182 rc &= FW_MSG_CODE_MASK; 2183 } else { 2184 /* Ruh-roh! */ 2185 BLOGE(sc, "FW failed to respond!\n"); 2186 // XXX bxe_fw_dump(sc); 2187 rc = 0; 2188 } 2189 2190 BXE_FWMB_UNLOCK(sc); 2191 return (rc); 2192 } 2193 2194 static uint32_t 2195 bxe_fw_command(struct bxe_softc *sc, 2196 uint32_t command, 2197 uint32_t param) 2198 { 2199 return (elink_cb_fw_command(sc, command, param)); 2200 } 2201 2202 static void 2203 __storm_memset_dma_mapping(struct bxe_softc *sc, 2204 uint32_t addr, 2205 bus_addr_t mapping) 2206 { 2207 REG_WR(sc, addr, U64_LO(mapping)); 2208 REG_WR(sc, (addr + 4), U64_HI(mapping)); 2209 } 2210 2211 static void 2212 storm_memset_spq_addr(struct bxe_softc *sc, 2213 bus_addr_t mapping, 2214 uint16_t abs_fid) 2215 { 2216 uint32_t addr = (XSEM_REG_FAST_MEMORY + 2217 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid)); 2218 __storm_memset_dma_mapping(sc, addr, mapping); 2219 } 2220 2221 static void 2222 storm_memset_vf_to_pf(struct bxe_softc *sc, 2223 uint16_t abs_fid, 2224 uint16_t pf_id) 2225 { 2226 REG_WR8(sc, (BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid)), pf_id); 2227 REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid)), pf_id); 2228 REG_WR8(sc, (BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid)), pf_id); 2229 REG_WR8(sc, (BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid)), pf_id); 2230 } 2231 2232 static void 2233 storm_memset_func_en(struct bxe_softc *sc, 2234 uint16_t abs_fid, 2235 uint8_t enable) 2236 { 2237 REG_WR8(sc, (BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid)), enable); 2238 REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid)), enable); 2239 REG_WR8(sc, (BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid)), enable); 2240 REG_WR8(sc, (BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid)), enable); 2241 } 2242 2243 static void 2244 storm_memset_eq_data(struct bxe_softc *sc, 2245 struct event_ring_data *eq_data, 2246 uint16_t pfid) 2247 { 2248 uint32_t addr; 2249 size_t size; 2250 2251 addr = (BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid)); 2252 size = sizeof(struct event_ring_data); 2253 ecore_storm_memset_struct(sc, addr, size, (uint32_t *)eq_data); 2254 } 2255 2256 static void 2257 storm_memset_eq_prod(struct bxe_softc *sc, 2258 uint16_t eq_prod, 2259 uint16_t pfid) 2260 { 2261 uint32_t addr = (BAR_CSTRORM_INTMEM + 2262 CSTORM_EVENT_RING_PROD_OFFSET(pfid)); 2263 REG_WR16(sc, addr, eq_prod); 2264 } 2265 2266 /* 2267 * Post a slowpath command. 2268 * 2269 * A slowpath command is used to propagate a configuration change through 2270 * the controller in a controlled manner, allowing each STORM processor and 2271 * other H/W blocks to phase in the change. The commands sent on the 2272 * slowpath are referred to as ramrods. Depending on the ramrod used the 2273 * completion of the ramrod will occur in different ways. Here's a 2274 * breakdown of ramrods and how they complete: 2275 * 2276 * RAMROD_CMD_ID_ETH_PORT_SETUP 2277 * Used to setup the leading connection on a port. Completes on the 2278 * Receive Completion Queue (RCQ) of that port (typically fp[0]). 2279 * 2280 * RAMROD_CMD_ID_ETH_CLIENT_SETUP 2281 * Used to setup an additional connection on a port. Completes on the 2282 * RCQ of the multi-queue/RSS connection being initialized. 2283 * 2284 * RAMROD_CMD_ID_ETH_STAT_QUERY 2285 * Used to force the storm processors to update the statistics database 2286 * in host memory. This ramrod is send on the leading connection CID and 2287 * completes as an index increment of the CSTORM on the default status 2288 * block. 2289 * 2290 * RAMROD_CMD_ID_ETH_UPDATE 2291 * Used to update the state of the leading connection, usually to udpate 2292 * the RSS indirection table. Completes on the RCQ of the leading 2293 * connection. (Not currently used under FreeBSD until OS support becomes 2294 * available.) 2295 * 2296 * RAMROD_CMD_ID_ETH_HALT 2297 * Used when tearing down a connection prior to driver unload. Completes 2298 * on the RCQ of the multi-queue/RSS connection being torn down. Don't 2299 * use this on the leading connection. 2300 * 2301 * RAMROD_CMD_ID_ETH_SET_MAC 2302 * Sets the Unicast/Broadcast/Multicast used by the port. Completes on 2303 * the RCQ of the leading connection. 2304 * 2305 * RAMROD_CMD_ID_ETH_CFC_DEL 2306 * Used when tearing down a conneciton prior to driver unload. Completes 2307 * on the RCQ of the leading connection (since the current connection 2308 * has been completely removed from controller memory). 2309 * 2310 * RAMROD_CMD_ID_ETH_PORT_DEL 2311 * Used to tear down the leading connection prior to driver unload, 2312 * typically fp[0]. Completes as an index increment of the CSTORM on the 2313 * default status block. 2314 * 2315 * RAMROD_CMD_ID_ETH_FORWARD_SETUP 2316 * Used for connection offload. Completes on the RCQ of the multi-queue 2317 * RSS connection that is being offloaded. (Not currently used under 2318 * FreeBSD.) 2319 * 2320 * There can only be one command pending per function. 2321 * 2322 * Returns: 2323 * 0 = Success, !0 = Failure. 2324 */ 2325 2326 /* must be called under the spq lock */ 2327 static inline 2328 struct eth_spe *bxe_sp_get_next(struct bxe_softc *sc) 2329 { 2330 struct eth_spe *next_spe = sc->spq_prod_bd; 2331 2332 if (sc->spq_prod_bd == sc->spq_last_bd) { 2333 /* wrap back to the first eth_spq */ 2334 sc->spq_prod_bd = sc->spq; 2335 sc->spq_prod_idx = 0; 2336 } else { 2337 sc->spq_prod_bd++; 2338 sc->spq_prod_idx++; 2339 } 2340 2341 return (next_spe); 2342 } 2343 2344 /* must be called under the spq lock */ 2345 static inline 2346 void bxe_sp_prod_update(struct bxe_softc *sc) 2347 { 2348 int func = SC_FUNC(sc); 2349 2350 /* 2351 * Make sure that BD data is updated before writing the producer. 2352 * BD data is written to the memory, the producer is read from the 2353 * memory, thus we need a full memory barrier to ensure the ordering. 2354 */ 2355 mb(); 2356 2357 REG_WR16(sc, (BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func)), 2358 sc->spq_prod_idx); 2359 2360 bus_space_barrier(sc->bar[BAR0].tag, sc->bar[BAR0].handle, 0, 0, 2361 BUS_SPACE_BARRIER_WRITE); 2362 } 2363 2364 /** 2365 * bxe_is_contextless_ramrod - check if the current command ends on EQ 2366 * 2367 * @cmd: command to check 2368 * @cmd_type: command type 2369 */ 2370 static inline 2371 int bxe_is_contextless_ramrod(int cmd, 2372 int cmd_type) 2373 { 2374 if ((cmd_type == NONE_CONNECTION_TYPE) || 2375 (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) || 2376 (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) || 2377 (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) || 2378 (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) || 2379 (cmd == RAMROD_CMD_ID_ETH_SET_MAC) || 2380 (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE)) { 2381 return (TRUE); 2382 } else { 2383 return (FALSE); 2384 } 2385 } 2386 2387 /** 2388 * bxe_sp_post - place a single command on an SP ring 2389 * 2390 * @sc: driver handle 2391 * @command: command to place (e.g. SETUP, FILTER_RULES, etc.) 2392 * @cid: SW CID the command is related to 2393 * @data_hi: command private data address (high 32 bits) 2394 * @data_lo: command private data address (low 32 bits) 2395 * @cmd_type: command type (e.g. NONE, ETH) 2396 * 2397 * SP data is handled as if it's always an address pair, thus data fields are 2398 * not swapped to little endian in upper functions. Instead this function swaps 2399 * data as if it's two uint32 fields. 2400 */ 2401 int 2402 bxe_sp_post(struct bxe_softc *sc, 2403 int command, 2404 int cid, 2405 uint32_t data_hi, 2406 uint32_t data_lo, 2407 int cmd_type) 2408 { 2409 struct eth_spe *spe; 2410 uint16_t type; 2411 int common; 2412 2413 common = bxe_is_contextless_ramrod(command, cmd_type); 2414 2415 BXE_SP_LOCK(sc); 2416 2417 if (common) { 2418 if (!atomic_load_acq_long(&sc->eq_spq_left)) { 2419 BLOGE(sc, "EQ ring is full!\n"); 2420 BXE_SP_UNLOCK(sc); 2421 return (-1); 2422 } 2423 } else { 2424 if (!atomic_load_acq_long(&sc->cq_spq_left)) { 2425 BLOGE(sc, "SPQ ring is full!\n"); 2426 BXE_SP_UNLOCK(sc); 2427 return (-1); 2428 } 2429 } 2430 2431 spe = bxe_sp_get_next(sc); 2432 2433 /* CID needs port number to be encoded int it */ 2434 spe->hdr.conn_and_cmd_data = 2435 htole32((command << SPE_HDR_T_CMD_ID_SHIFT) | HW_CID(sc, cid)); 2436 2437 type = (cmd_type << SPE_HDR_T_CONN_TYPE_SHIFT) & SPE_HDR_T_CONN_TYPE; 2438 2439 /* TBD: Check if it works for VFs */ 2440 type |= ((SC_FUNC(sc) << SPE_HDR_T_FUNCTION_ID_SHIFT) & 2441 SPE_HDR_T_FUNCTION_ID); 2442 2443 spe->hdr.type = htole16(type); 2444 2445 spe->data.update_data_addr.hi = htole32(data_hi); 2446 spe->data.update_data_addr.lo = htole32(data_lo); 2447 2448 /* 2449 * It's ok if the actual decrement is issued towards the memory 2450 * somewhere between the lock and unlock. Thus no more explict 2451 * memory barrier is needed. 2452 */ 2453 if (common) { 2454 atomic_subtract_acq_long(&sc->eq_spq_left, 1); 2455 } else { 2456 atomic_subtract_acq_long(&sc->cq_spq_left, 1); 2457 } 2458 2459 BLOGD(sc, DBG_SP, "SPQE -> %#jx\n", (uintmax_t)sc->spq_dma.paddr); 2460 BLOGD(sc, DBG_SP, "FUNC_RDATA -> %p / %#jx\n", 2461 BXE_SP(sc, func_rdata), (uintmax_t)BXE_SP_MAPPING(sc, func_rdata)); 2462 BLOGD(sc, DBG_SP, 2463 "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x data (%x:%x) type(0x%x) left (CQ, EQ) (%lx,%lx)\n", 2464 sc->spq_prod_idx, 2465 (uint32_t)U64_HI(sc->spq_dma.paddr), 2466 (uint32_t)(U64_LO(sc->spq_dma.paddr) + (uint8_t *)sc->spq_prod_bd - (uint8_t *)sc->spq), 2467 command, 2468 common, 2469 HW_CID(sc, cid), 2470 data_hi, 2471 data_lo, 2472 type, 2473 atomic_load_acq_long(&sc->cq_spq_left), 2474 atomic_load_acq_long(&sc->eq_spq_left)); 2475 2476 bxe_sp_prod_update(sc); 2477 2478 BXE_SP_UNLOCK(sc); 2479 return (0); 2480 } 2481 2482 /** 2483 * bxe_debug_print_ind_table - prints the indirection table configuration. 2484 * 2485 * @sc: driver hanlde 2486 * @p: pointer to rss configuration 2487 */ 2488 2489 /* 2490 * FreeBSD Device probe function. 2491 * 2492 * Compares the device found to the driver's list of supported devices and 2493 * reports back to the bsd loader whether this is the right driver for the device. 2494 * This is the driver entry function called from the "kldload" command. 2495 * 2496 * Returns: 2497 * BUS_PROBE_DEFAULT on success, positive value on failure. 2498 */ 2499 static int 2500 bxe_probe(device_t dev) 2501 { 2502 struct bxe_device_type *t; 2503 char *descbuf; 2504 uint16_t did, sdid, svid, vid; 2505 2506 /* Find our device structure */ 2507 t = bxe_devs; 2508 2509 /* Get the data for the device to be probed. */ 2510 vid = pci_get_vendor(dev); 2511 did = pci_get_device(dev); 2512 svid = pci_get_subvendor(dev); 2513 sdid = pci_get_subdevice(dev); 2514 2515 /* Look through the list of known devices for a match. */ 2516 while (t->bxe_name != NULL) { 2517 if ((vid == t->bxe_vid) && (did == t->bxe_did) && 2518 ((svid == t->bxe_svid) || (t->bxe_svid == PCI_ANY_ID)) && 2519 ((sdid == t->bxe_sdid) || (t->bxe_sdid == PCI_ANY_ID))) { 2520 descbuf = malloc(BXE_DEVDESC_MAX, M_TEMP, M_NOWAIT); 2521 if (descbuf == NULL) 2522 return (ENOMEM); 2523 2524 /* Print out the device identity. */ 2525 snprintf(descbuf, BXE_DEVDESC_MAX, 2526 "%s (%c%d) BXE v:%s\n", t->bxe_name, 2527 (((pci_read_config(dev, PCIR_REVID, 4) & 2528 0xf0) >> 4) + 'A'), 2529 (pci_read_config(dev, PCIR_REVID, 4) & 0xf), 2530 BXE_DRIVER_VERSION); 2531 2532 device_set_desc_copy(dev, descbuf); 2533 free(descbuf, M_TEMP); 2534 return (BUS_PROBE_DEFAULT); 2535 } 2536 t++; 2537 } 2538 2539 return (ENXIO); 2540 } 2541 2542 static void 2543 bxe_init_mutexes(struct bxe_softc *sc) 2544 { 2545 #ifdef BXE_CORE_LOCK_SX 2546 snprintf(sc->core_sx_name, sizeof(sc->core_sx_name), 2547 "bxe%d_core_lock", sc->unit); 2548 sx_init(&sc->core_sx, sc->core_sx_name); 2549 #else 2550 snprintf(sc->core_mtx_name, sizeof(sc->core_mtx_name), 2551 "bxe%d_core_lock", sc->unit); 2552 mtx_init(&sc->core_mtx, sc->core_mtx_name, NULL, MTX_DEF); 2553 #endif 2554 2555 snprintf(sc->sp_mtx_name, sizeof(sc->sp_mtx_name), 2556 "bxe%d_sp_lock", sc->unit); 2557 mtx_init(&sc->sp_mtx, sc->sp_mtx_name, NULL, MTX_DEF); 2558 2559 snprintf(sc->dmae_mtx_name, sizeof(sc->dmae_mtx_name), 2560 "bxe%d_dmae_lock", sc->unit); 2561 mtx_init(&sc->dmae_mtx, sc->dmae_mtx_name, NULL, MTX_DEF); 2562 2563 snprintf(sc->port.phy_mtx_name, sizeof(sc->port.phy_mtx_name), 2564 "bxe%d_phy_lock", sc->unit); 2565 mtx_init(&sc->port.phy_mtx, sc->port.phy_mtx_name, NULL, MTX_DEF); 2566 2567 snprintf(sc->fwmb_mtx_name, sizeof(sc->fwmb_mtx_name), 2568 "bxe%d_fwmb_lock", sc->unit); 2569 mtx_init(&sc->fwmb_mtx, sc->fwmb_mtx_name, NULL, MTX_DEF); 2570 2571 snprintf(sc->print_mtx_name, sizeof(sc->print_mtx_name), 2572 "bxe%d_print_lock", sc->unit); 2573 mtx_init(&(sc->print_mtx), sc->print_mtx_name, NULL, MTX_DEF); 2574 2575 snprintf(sc->stats_mtx_name, sizeof(sc->stats_mtx_name), 2576 "bxe%d_stats_lock", sc->unit); 2577 mtx_init(&(sc->stats_mtx), sc->stats_mtx_name, NULL, MTX_DEF); 2578 2579 snprintf(sc->mcast_mtx_name, sizeof(sc->mcast_mtx_name), 2580 "bxe%d_mcast_lock", sc->unit); 2581 mtx_init(&(sc->mcast_mtx), sc->mcast_mtx_name, NULL, MTX_DEF); 2582 } 2583 2584 static void 2585 bxe_release_mutexes(struct bxe_softc *sc) 2586 { 2587 #ifdef BXE_CORE_LOCK_SX 2588 sx_destroy(&sc->core_sx); 2589 #else 2590 if (mtx_initialized(&sc->core_mtx)) { 2591 mtx_destroy(&sc->core_mtx); 2592 } 2593 #endif 2594 2595 if (mtx_initialized(&sc->sp_mtx)) { 2596 mtx_destroy(&sc->sp_mtx); 2597 } 2598 2599 if (mtx_initialized(&sc->dmae_mtx)) { 2600 mtx_destroy(&sc->dmae_mtx); 2601 } 2602 2603 if (mtx_initialized(&sc->port.phy_mtx)) { 2604 mtx_destroy(&sc->port.phy_mtx); 2605 } 2606 2607 if (mtx_initialized(&sc->fwmb_mtx)) { 2608 mtx_destroy(&sc->fwmb_mtx); 2609 } 2610 2611 if (mtx_initialized(&sc->print_mtx)) { 2612 mtx_destroy(&sc->print_mtx); 2613 } 2614 2615 if (mtx_initialized(&sc->stats_mtx)) { 2616 mtx_destroy(&sc->stats_mtx); 2617 } 2618 2619 if (mtx_initialized(&sc->mcast_mtx)) { 2620 mtx_destroy(&sc->mcast_mtx); 2621 } 2622 } 2623 2624 static void 2625 bxe_tx_disable(struct bxe_softc* sc) 2626 { 2627 if_t ifp = sc->ifp; 2628 2629 /* tell the stack the driver is stopped and TX queue is full */ 2630 if (ifp != NULL) { 2631 if_setdrvflags(ifp, 0); 2632 } 2633 } 2634 2635 static void 2636 bxe_drv_pulse(struct bxe_softc *sc) 2637 { 2638 SHMEM_WR(sc, func_mb[SC_FW_MB_IDX(sc)].drv_pulse_mb, 2639 sc->fw_drv_pulse_wr_seq); 2640 } 2641 2642 static inline uint16_t 2643 bxe_tx_avail(struct bxe_softc *sc, 2644 struct bxe_fastpath *fp) 2645 { 2646 int16_t used; 2647 uint16_t prod; 2648 uint16_t cons; 2649 2650 prod = fp->tx_bd_prod; 2651 cons = fp->tx_bd_cons; 2652 2653 used = SUB_S16(prod, cons); 2654 2655 return (int16_t)(sc->tx_ring_size) - used; 2656 } 2657 2658 static inline int 2659 bxe_tx_queue_has_work(struct bxe_fastpath *fp) 2660 { 2661 uint16_t hw_cons; 2662 2663 mb(); /* status block fields can change */ 2664 hw_cons = le16toh(*fp->tx_cons_sb); 2665 return (hw_cons != fp->tx_pkt_cons); 2666 } 2667 2668 static inline uint8_t 2669 bxe_has_tx_work(struct bxe_fastpath *fp) 2670 { 2671 /* expand this for multi-cos if ever supported */ 2672 return (bxe_tx_queue_has_work(fp)) ? TRUE : FALSE; 2673 } 2674 2675 static inline int 2676 bxe_has_rx_work(struct bxe_fastpath *fp) 2677 { 2678 uint16_t rx_cq_cons_sb; 2679 2680 mb(); /* status block fields can change */ 2681 rx_cq_cons_sb = le16toh(*fp->rx_cq_cons_sb); 2682 if ((rx_cq_cons_sb & RCQ_MAX) == RCQ_MAX) 2683 rx_cq_cons_sb++; 2684 return (fp->rx_cq_cons != rx_cq_cons_sb); 2685 } 2686 2687 static void 2688 bxe_sp_event(struct bxe_softc *sc, 2689 struct bxe_fastpath *fp, 2690 union eth_rx_cqe *rr_cqe) 2691 { 2692 int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data); 2693 int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data); 2694 enum ecore_queue_cmd drv_cmd = ECORE_Q_CMD_MAX; 2695 struct ecore_queue_sp_obj *q_obj = &BXE_SP_OBJ(sc, fp).q_obj; 2696 2697 BLOGD(sc, DBG_SP, "fp=%d cid=%d got ramrod #%d state is %x type is %d\n", 2698 fp->index, cid, command, sc->state, rr_cqe->ramrod_cqe.ramrod_type); 2699 2700 switch (command) { 2701 case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE): 2702 BLOGD(sc, DBG_SP, "got UPDATE ramrod. CID %d\n", cid); 2703 drv_cmd = ECORE_Q_CMD_UPDATE; 2704 break; 2705 2706 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP): 2707 BLOGD(sc, DBG_SP, "got MULTI[%d] setup ramrod\n", cid); 2708 drv_cmd = ECORE_Q_CMD_SETUP; 2709 break; 2710 2711 case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP): 2712 BLOGD(sc, DBG_SP, "got MULTI[%d] tx-only setup ramrod\n", cid); 2713 drv_cmd = ECORE_Q_CMD_SETUP_TX_ONLY; 2714 break; 2715 2716 case (RAMROD_CMD_ID_ETH_HALT): 2717 BLOGD(sc, DBG_SP, "got MULTI[%d] halt ramrod\n", cid); 2718 drv_cmd = ECORE_Q_CMD_HALT; 2719 break; 2720 2721 case (RAMROD_CMD_ID_ETH_TERMINATE): 2722 BLOGD(sc, DBG_SP, "got MULTI[%d] teminate ramrod\n", cid); 2723 drv_cmd = ECORE_Q_CMD_TERMINATE; 2724 break; 2725 2726 case (RAMROD_CMD_ID_ETH_EMPTY): 2727 BLOGD(sc, DBG_SP, "got MULTI[%d] empty ramrod\n", cid); 2728 drv_cmd = ECORE_Q_CMD_EMPTY; 2729 break; 2730 2731 default: 2732 BLOGD(sc, DBG_SP, "ERROR: unexpected MC reply (%d) on fp[%d]\n", 2733 command, fp->index); 2734 return; 2735 } 2736 2737 if ((drv_cmd != ECORE_Q_CMD_MAX) && 2738 q_obj->complete_cmd(sc, q_obj, drv_cmd)) { 2739 /* 2740 * q_obj->complete_cmd() failure means that this was 2741 * an unexpected completion. 2742 * 2743 * In this case we don't want to increase the sc->spq_left 2744 * because apparently we haven't sent this command the first 2745 * place. 2746 */ 2747 // bxe_panic(sc, ("Unexpected SP completion\n")); 2748 return; 2749 } 2750 2751 atomic_add_acq_long(&sc->cq_spq_left, 1); 2752 2753 BLOGD(sc, DBG_SP, "sc->cq_spq_left 0x%lx\n", 2754 atomic_load_acq_long(&sc->cq_spq_left)); 2755 } 2756 2757 /* 2758 * The current mbuf is part of an aggregation. Move the mbuf into the TPA 2759 * aggregation queue, put an empty mbuf back onto the receive chain, and mark 2760 * the current aggregation queue as in-progress. 2761 */ 2762 static void 2763 bxe_tpa_start(struct bxe_softc *sc, 2764 struct bxe_fastpath *fp, 2765 uint16_t queue, 2766 uint16_t cons, 2767 uint16_t prod, 2768 struct eth_fast_path_rx_cqe *cqe) 2769 { 2770 struct bxe_sw_rx_bd tmp_bd; 2771 struct bxe_sw_rx_bd *rx_buf; 2772 struct eth_rx_bd *rx_bd; 2773 int max_agg_queues; 2774 struct bxe_sw_tpa_info *tpa_info = &fp->rx_tpa_info[queue]; 2775 uint16_t index; 2776 2777 BLOGD(sc, DBG_LRO, "fp[%02d].tpa[%02d] TPA START " 2778 "cons=%d prod=%d\n", 2779 fp->index, queue, cons, prod); 2780 2781 max_agg_queues = MAX_AGG_QS(sc); 2782 2783 KASSERT((queue < max_agg_queues), 2784 ("fp[%02d] invalid aggr queue (%d >= %d)!", 2785 fp->index, queue, max_agg_queues)); 2786 2787 KASSERT((tpa_info->state == BXE_TPA_STATE_STOP), 2788 ("fp[%02d].tpa[%02d] starting aggr on queue not stopped!", 2789 fp->index, queue)); 2790 2791 /* copy the existing mbuf and mapping from the TPA pool */ 2792 tmp_bd = tpa_info->bd; 2793 2794 if (tmp_bd.m == NULL) { 2795 uint32_t *tmp; 2796 2797 tmp = (uint32_t *)cqe; 2798 2799 BLOGE(sc, "fp[%02d].tpa[%02d] cons[%d] prod[%d]mbuf not allocated!\n", 2800 fp->index, queue, cons, prod); 2801 BLOGE(sc, "cqe [0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x]\n", 2802 *tmp, *(tmp+1), *(tmp+2), *(tmp+3), *(tmp+4), *(tmp+5), *(tmp+6), *(tmp+7)); 2803 2804 /* XXX Error handling? */ 2805 return; 2806 } 2807 2808 /* change the TPA queue to the start state */ 2809 tpa_info->state = BXE_TPA_STATE_START; 2810 tpa_info->placement_offset = cqe->placement_offset; 2811 tpa_info->parsing_flags = le16toh(cqe->pars_flags.flags); 2812 tpa_info->vlan_tag = le16toh(cqe->vlan_tag); 2813 tpa_info->len_on_bd = le16toh(cqe->len_on_bd); 2814 2815 fp->rx_tpa_queue_used |= (1 << queue); 2816 2817 /* 2818 * If all the buffer descriptors are filled with mbufs then fill in 2819 * the current consumer index with a new BD. Else if a maximum Rx 2820 * buffer limit is imposed then fill in the next producer index. 2821 */ 2822 index = (sc->max_rx_bufs != RX_BD_USABLE) ? 2823 prod : cons; 2824 2825 /* move the received mbuf and mapping to TPA pool */ 2826 tpa_info->bd = fp->rx_mbuf_chain[cons]; 2827 2828 /* release any existing RX BD mbuf mappings */ 2829 if (cons != index) { 2830 rx_buf = &fp->rx_mbuf_chain[cons]; 2831 2832 if (rx_buf->m_map != NULL) { 2833 bus_dmamap_sync(fp->rx_mbuf_tag, rx_buf->m_map, 2834 BUS_DMASYNC_POSTREAD); 2835 bus_dmamap_unload(fp->rx_mbuf_tag, rx_buf->m_map); 2836 } 2837 2838 /* 2839 * We get here when the maximum number of rx buffers is less than 2840 * RX_BD_USABLE. The mbuf is already saved above so it's OK to NULL 2841 * it out here without concern of a memory leak. 2842 */ 2843 fp->rx_mbuf_chain[cons].m = NULL; 2844 } 2845 2846 /* update the Rx SW BD with the mbuf info from the TPA pool */ 2847 fp->rx_mbuf_chain[index] = tmp_bd; 2848 2849 /* update the Rx BD with the empty mbuf phys address from the TPA pool */ 2850 rx_bd = &fp->rx_chain[index]; 2851 rx_bd->addr_hi = htole32(U64_HI(tpa_info->seg.ds_addr)); 2852 rx_bd->addr_lo = htole32(U64_LO(tpa_info->seg.ds_addr)); 2853 } 2854 2855 /* 2856 * When a TPA aggregation is completed, loop through the individual mbufs 2857 * of the aggregation, combining them into a single mbuf which will be sent 2858 * up the stack. Refill all freed SGEs with mbufs as we go along. 2859 */ 2860 static int 2861 bxe_fill_frag_mbuf(struct bxe_softc *sc, 2862 struct bxe_fastpath *fp, 2863 struct bxe_sw_tpa_info *tpa_info, 2864 uint16_t queue, 2865 uint16_t pages, 2866 struct mbuf *m, 2867 struct eth_end_agg_rx_cqe *cqe, 2868 uint16_t cqe_idx) 2869 { 2870 struct mbuf *m_frag; 2871 uint32_t frag_len, frag_size, i; 2872 uint16_t sge_idx; 2873 int rc = 0; 2874 int j; 2875 2876 frag_size = le16toh(cqe->pkt_len) - tpa_info->len_on_bd; 2877 2878 BLOGD(sc, DBG_LRO, 2879 "fp[%02d].tpa[%02d] TPA fill len_on_bd=%d frag_size=%d pages=%d\n", 2880 fp->index, queue, tpa_info->len_on_bd, frag_size, pages); 2881 2882 /* make sure the aggregated frame is not too big to handle */ 2883 if (pages > 8 * PAGES_PER_SGE) { 2884 2885 uint32_t *tmp = (uint32_t *)cqe; 2886 2887 BLOGE(sc, "fp[%02d].sge[0x%04x] has too many pages (%d)! " 2888 "pkt_len=%d len_on_bd=%d frag_size=%d\n", 2889 fp->index, cqe_idx, pages, le16toh(cqe->pkt_len), 2890 tpa_info->len_on_bd, frag_size); 2891 2892 BLOGE(sc, "cqe [0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x]\n", 2893 *tmp, *(tmp+1), *(tmp+2), *(tmp+3), *(tmp+4), *(tmp+5), *(tmp+6), *(tmp+7)); 2894 2895 bxe_panic(sc, ("sge page count error\n")); 2896 return (EINVAL); 2897 } 2898 2899 /* 2900 * Scan through the scatter gather list pulling individual mbufs into a 2901 * single mbuf for the host stack. 2902 */ 2903 for (i = 0, j = 0; i < pages; i += PAGES_PER_SGE, j++) { 2904 sge_idx = RX_SGE(le16toh(cqe->sgl_or_raw_data.sgl[j])); 2905 2906 /* 2907 * Firmware gives the indices of the SGE as if the ring is an array 2908 * (meaning that the "next" element will consume 2 indices). 2909 */ 2910 frag_len = min(frag_size, (uint32_t)(SGE_PAGES)); 2911 2912 BLOGD(sc, DBG_LRO, "fp[%02d].tpa[%02d] TPA fill i=%d j=%d " 2913 "sge_idx=%d frag_size=%d frag_len=%d\n", 2914 fp->index, queue, i, j, sge_idx, frag_size, frag_len); 2915 2916 m_frag = fp->rx_sge_mbuf_chain[sge_idx].m; 2917 2918 /* allocate a new mbuf for the SGE */ 2919 rc = bxe_alloc_rx_sge_mbuf(fp, sge_idx); 2920 if (rc) { 2921 /* Leave all remaining SGEs in the ring! */ 2922 return (rc); 2923 } 2924 2925 /* update the fragment length */ 2926 m_frag->m_len = frag_len; 2927 2928 /* concatenate the fragment to the head mbuf */ 2929 m_cat(m, m_frag); 2930 fp->eth_q_stats.mbuf_alloc_sge--; 2931 2932 /* update the TPA mbuf size and remaining fragment size */ 2933 m->m_pkthdr.len += frag_len; 2934 frag_size -= frag_len; 2935 } 2936 2937 BLOGD(sc, DBG_LRO, 2938 "fp[%02d].tpa[%02d] TPA fill done frag_size=%d\n", 2939 fp->index, queue, frag_size); 2940 2941 return (rc); 2942 } 2943 2944 static inline void 2945 bxe_clear_sge_mask_next_elems(struct bxe_fastpath *fp) 2946 { 2947 int i, j; 2948 2949 for (i = 1; i <= RX_SGE_NUM_PAGES; i++) { 2950 int idx = RX_SGE_TOTAL_PER_PAGE * i - 1; 2951 2952 for (j = 0; j < 2; j++) { 2953 BIT_VEC64_CLEAR_BIT(fp->sge_mask, idx); 2954 idx--; 2955 } 2956 } 2957 } 2958 2959 static inline void 2960 bxe_init_sge_ring_bit_mask(struct bxe_fastpath *fp) 2961 { 2962 /* set the mask to all 1's, it's faster to compare to 0 than to 0xf's */ 2963 memset(fp->sge_mask, 0xff, sizeof(fp->sge_mask)); 2964 2965 /* 2966 * Clear the two last indices in the page to 1. These are the indices that 2967 * correspond to the "next" element, hence will never be indicated and 2968 * should be removed from the calculations. 2969 */ 2970 bxe_clear_sge_mask_next_elems(fp); 2971 } 2972 2973 static inline void 2974 bxe_update_last_max_sge(struct bxe_fastpath *fp, 2975 uint16_t idx) 2976 { 2977 uint16_t last_max = fp->last_max_sge; 2978 2979 if (SUB_S16(idx, last_max) > 0) { 2980 fp->last_max_sge = idx; 2981 } 2982 } 2983 2984 static inline void 2985 bxe_update_sge_prod(struct bxe_softc *sc, 2986 struct bxe_fastpath *fp, 2987 uint16_t sge_len, 2988 union eth_sgl_or_raw_data *cqe) 2989 { 2990 uint16_t last_max, last_elem, first_elem; 2991 uint16_t delta = 0; 2992 uint16_t i; 2993 2994 if (!sge_len) { 2995 return; 2996 } 2997 2998 /* first mark all used pages */ 2999 for (i = 0; i < sge_len; i++) { 3000 BIT_VEC64_CLEAR_BIT(fp->sge_mask, 3001 RX_SGE(le16toh(cqe->sgl[i]))); 3002 } 3003 3004 BLOGD(sc, DBG_LRO, 3005 "fp[%02d] fp_cqe->sgl[%d] = %d\n", 3006 fp->index, sge_len - 1, 3007 le16toh(cqe->sgl[sge_len - 1])); 3008 3009 /* assume that the last SGE index is the biggest */ 3010 bxe_update_last_max_sge(fp, 3011 le16toh(cqe->sgl[sge_len - 1])); 3012 3013 last_max = RX_SGE(fp->last_max_sge); 3014 last_elem = last_max >> BIT_VEC64_ELEM_SHIFT; 3015 first_elem = RX_SGE(fp->rx_sge_prod) >> BIT_VEC64_ELEM_SHIFT; 3016 3017 /* if ring is not full */ 3018 if (last_elem + 1 != first_elem) { 3019 last_elem++; 3020 } 3021 3022 /* now update the prod */ 3023 for (i = first_elem; i != last_elem; i = RX_SGE_NEXT_MASK_ELEM(i)) { 3024 if (__predict_true(fp->sge_mask[i])) { 3025 break; 3026 } 3027 3028 fp->sge_mask[i] = BIT_VEC64_ELEM_ONE_MASK; 3029 delta += BIT_VEC64_ELEM_SZ; 3030 } 3031 3032 if (delta > 0) { 3033 fp->rx_sge_prod += delta; 3034 /* clear page-end entries */ 3035 bxe_clear_sge_mask_next_elems(fp); 3036 } 3037 3038 BLOGD(sc, DBG_LRO, 3039 "fp[%02d] fp->last_max_sge=%d fp->rx_sge_prod=%d\n", 3040 fp->index, fp->last_max_sge, fp->rx_sge_prod); 3041 } 3042 3043 /* 3044 * The aggregation on the current TPA queue has completed. Pull the individual 3045 * mbuf fragments together into a single mbuf, perform all necessary checksum 3046 * calculations, and send the resuting mbuf to the stack. 3047 */ 3048 static void 3049 bxe_tpa_stop(struct bxe_softc *sc, 3050 struct bxe_fastpath *fp, 3051 struct bxe_sw_tpa_info *tpa_info, 3052 uint16_t queue, 3053 uint16_t pages, 3054 struct eth_end_agg_rx_cqe *cqe, 3055 uint16_t cqe_idx) 3056 { 3057 if_t ifp = sc->ifp; 3058 struct mbuf *m; 3059 int rc = 0; 3060 3061 BLOGD(sc, DBG_LRO, 3062 "fp[%02d].tpa[%02d] pad=%d pkt_len=%d pages=%d vlan=%d\n", 3063 fp->index, queue, tpa_info->placement_offset, 3064 le16toh(cqe->pkt_len), pages, tpa_info->vlan_tag); 3065 3066 m = tpa_info->bd.m; 3067 3068 /* allocate a replacement before modifying existing mbuf */ 3069 rc = bxe_alloc_rx_tpa_mbuf(fp, queue); 3070 if (rc) { 3071 /* drop the frame and log an error */ 3072 fp->eth_q_stats.rx_soft_errors++; 3073 goto bxe_tpa_stop_exit; 3074 } 3075 3076 /* we have a replacement, fixup the current mbuf */ 3077 m_adj(m, tpa_info->placement_offset); 3078 m->m_pkthdr.len = m->m_len = tpa_info->len_on_bd; 3079 3080 /* mark the checksums valid (taken care of by the firmware) */ 3081 fp->eth_q_stats.rx_ofld_frames_csum_ip++; 3082 fp->eth_q_stats.rx_ofld_frames_csum_tcp_udp++; 3083 m->m_pkthdr.csum_data = 0xffff; 3084 m->m_pkthdr.csum_flags |= (CSUM_IP_CHECKED | 3085 CSUM_IP_VALID | 3086 CSUM_DATA_VALID | 3087 CSUM_PSEUDO_HDR); 3088 3089 /* aggregate all of the SGEs into a single mbuf */ 3090 rc = bxe_fill_frag_mbuf(sc, fp, tpa_info, queue, pages, m, cqe, cqe_idx); 3091 if (rc) { 3092 /* drop the packet and log an error */ 3093 fp->eth_q_stats.rx_soft_errors++; 3094 m_freem(m); 3095 } else { 3096 if (tpa_info->parsing_flags & PARSING_FLAGS_INNER_VLAN_EXIST) { 3097 m->m_pkthdr.ether_vtag = tpa_info->vlan_tag; 3098 m->m_flags |= M_VLANTAG; 3099 } 3100 3101 /* assign packet to this interface interface */ 3102 if_setrcvif(m, ifp); 3103 3104 #if __FreeBSD_version >= 800000 3105 /* specify what RSS queue was used for this flow */ 3106 m->m_pkthdr.flowid = fp->index; 3107 BXE_SET_FLOWID(m); 3108 #endif 3109 3110 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 3111 fp->eth_q_stats.rx_tpa_pkts++; 3112 3113 /* pass the frame to the stack */ 3114 if_input(ifp, m); 3115 } 3116 3117 /* we passed an mbuf up the stack or dropped the frame */ 3118 fp->eth_q_stats.mbuf_alloc_tpa--; 3119 3120 bxe_tpa_stop_exit: 3121 3122 fp->rx_tpa_info[queue].state = BXE_TPA_STATE_STOP; 3123 fp->rx_tpa_queue_used &= ~(1 << queue); 3124 } 3125 3126 static uint8_t 3127 bxe_service_rxsgl( 3128 struct bxe_fastpath *fp, 3129 uint16_t len, 3130 uint16_t lenonbd, 3131 struct mbuf *m, 3132 struct eth_fast_path_rx_cqe *cqe_fp) 3133 { 3134 struct mbuf *m_frag; 3135 uint16_t frags, frag_len; 3136 uint16_t sge_idx = 0; 3137 uint16_t j; 3138 uint8_t i, rc = 0; 3139 uint32_t frag_size; 3140 3141 /* adjust the mbuf */ 3142 m->m_len = lenonbd; 3143 3144 frag_size = len - lenonbd; 3145 frags = SGE_PAGE_ALIGN(frag_size) >> SGE_PAGE_SHIFT; 3146 3147 for (i = 0, j = 0; i < frags; i += PAGES_PER_SGE, j++) { 3148 sge_idx = RX_SGE(le16toh(cqe_fp->sgl_or_raw_data.sgl[j])); 3149 3150 m_frag = fp->rx_sge_mbuf_chain[sge_idx].m; 3151 frag_len = min(frag_size, (uint32_t)(SGE_PAGE_SIZE)); 3152 m_frag->m_len = frag_len; 3153 3154 /* allocate a new mbuf for the SGE */ 3155 rc = bxe_alloc_rx_sge_mbuf(fp, sge_idx); 3156 if (rc) { 3157 /* Leave all remaining SGEs in the ring! */ 3158 return (rc); 3159 } 3160 fp->eth_q_stats.mbuf_alloc_sge--; 3161 3162 /* concatenate the fragment to the head mbuf */ 3163 m_cat(m, m_frag); 3164 3165 frag_size -= frag_len; 3166 } 3167 3168 bxe_update_sge_prod(fp->sc, fp, frags, &cqe_fp->sgl_or_raw_data); 3169 3170 return rc; 3171 } 3172 3173 static uint8_t 3174 bxe_rxeof(struct bxe_softc *sc, 3175 struct bxe_fastpath *fp) 3176 { 3177 if_t ifp = sc->ifp; 3178 uint16_t bd_cons, bd_prod, bd_prod_fw, comp_ring_cons; 3179 uint16_t hw_cq_cons, sw_cq_cons, sw_cq_prod; 3180 int rx_pkts = 0; 3181 int rc = 0; 3182 3183 BXE_FP_RX_LOCK(fp); 3184 3185 /* CQ "next element" is of the size of the regular element */ 3186 hw_cq_cons = le16toh(*fp->rx_cq_cons_sb); 3187 if ((hw_cq_cons & RCQ_USABLE_PER_PAGE) == RCQ_USABLE_PER_PAGE) { 3188 hw_cq_cons++; 3189 } 3190 3191 bd_cons = fp->rx_bd_cons; 3192 bd_prod = fp->rx_bd_prod; 3193 bd_prod_fw = bd_prod; 3194 sw_cq_cons = fp->rx_cq_cons; 3195 sw_cq_prod = fp->rx_cq_prod; 3196 3197 /* 3198 * Memory barrier necessary as speculative reads of the rx 3199 * buffer can be ahead of the index in the status block 3200 */ 3201 rmb(); 3202 3203 BLOGD(sc, DBG_RX, 3204 "fp[%02d] Rx START hw_cq_cons=%u sw_cq_cons=%u\n", 3205 fp->index, hw_cq_cons, sw_cq_cons); 3206 3207 while (sw_cq_cons != hw_cq_cons) { 3208 struct bxe_sw_rx_bd *rx_buf = NULL; 3209 union eth_rx_cqe *cqe; 3210 struct eth_fast_path_rx_cqe *cqe_fp; 3211 uint8_t cqe_fp_flags; 3212 enum eth_rx_cqe_type cqe_fp_type; 3213 uint16_t len, lenonbd, pad; 3214 struct mbuf *m = NULL; 3215 3216 comp_ring_cons = RCQ(sw_cq_cons); 3217 bd_prod = RX_BD(bd_prod); 3218 bd_cons = RX_BD(bd_cons); 3219 3220 cqe = &fp->rcq_chain[comp_ring_cons]; 3221 cqe_fp = &cqe->fast_path_cqe; 3222 cqe_fp_flags = cqe_fp->type_error_flags; 3223 cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE; 3224 3225 BLOGD(sc, DBG_RX, 3226 "fp[%02d] Rx hw_cq_cons=%d hw_sw_cons=%d " 3227 "BD prod=%d cons=%d CQE type=0x%x err=0x%x " 3228 "status=0x%x rss_hash=0x%x vlan=0x%x len=%u lenonbd=%u\n", 3229 fp->index, 3230 hw_cq_cons, 3231 sw_cq_cons, 3232 bd_prod, 3233 bd_cons, 3234 CQE_TYPE(cqe_fp_flags), 3235 cqe_fp_flags, 3236 cqe_fp->status_flags, 3237 le32toh(cqe_fp->rss_hash_result), 3238 le16toh(cqe_fp->vlan_tag), 3239 le16toh(cqe_fp->pkt_len_or_gro_seg_len), 3240 le16toh(cqe_fp->len_on_bd)); 3241 3242 /* is this a slowpath msg? */ 3243 if (__predict_false(CQE_TYPE_SLOW(cqe_fp_type))) { 3244 bxe_sp_event(sc, fp, cqe); 3245 goto next_cqe; 3246 } 3247 3248 rx_buf = &fp->rx_mbuf_chain[bd_cons]; 3249 3250 if (!CQE_TYPE_FAST(cqe_fp_type)) { 3251 struct bxe_sw_tpa_info *tpa_info; 3252 uint16_t frag_size, pages; 3253 uint8_t queue; 3254 3255 if (CQE_TYPE_START(cqe_fp_type)) { 3256 bxe_tpa_start(sc, fp, cqe_fp->queue_index, 3257 bd_cons, bd_prod, cqe_fp); 3258 m = NULL; /* packet not ready yet */ 3259 goto next_rx; 3260 } 3261 3262 KASSERT(CQE_TYPE_STOP(cqe_fp_type), 3263 ("CQE type is not STOP! (0x%x)\n", cqe_fp_type)); 3264 3265 queue = cqe->end_agg_cqe.queue_index; 3266 tpa_info = &fp->rx_tpa_info[queue]; 3267 3268 BLOGD(sc, DBG_LRO, "fp[%02d].tpa[%02d] TPA STOP\n", 3269 fp->index, queue); 3270 3271 frag_size = (le16toh(cqe->end_agg_cqe.pkt_len) - 3272 tpa_info->len_on_bd); 3273 pages = SGE_PAGE_ALIGN(frag_size) >> SGE_PAGE_SHIFT; 3274 3275 bxe_tpa_stop(sc, fp, tpa_info, queue, pages, 3276 &cqe->end_agg_cqe, comp_ring_cons); 3277 3278 bxe_update_sge_prod(sc, fp, pages, &cqe->end_agg_cqe.sgl_or_raw_data); 3279 3280 goto next_cqe; 3281 } 3282 3283 /* non TPA */ 3284 3285 /* is this an error packet? */ 3286 if (__predict_false(cqe_fp_flags & 3287 ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG)) { 3288 BLOGE(sc, "flags 0x%x rx packet %u\n", cqe_fp_flags, sw_cq_cons); 3289 fp->eth_q_stats.rx_soft_errors++; 3290 goto next_rx; 3291 } 3292 3293 len = le16toh(cqe_fp->pkt_len_or_gro_seg_len); 3294 lenonbd = le16toh(cqe_fp->len_on_bd); 3295 pad = cqe_fp->placement_offset; 3296 3297 m = rx_buf->m; 3298 3299 if (__predict_false(m == NULL)) { 3300 BLOGE(sc, "No mbuf in rx chain descriptor %d for fp[%02d]\n", 3301 bd_cons, fp->index); 3302 goto next_rx; 3303 } 3304 3305 /* XXX double copy if packet length under a threshold */ 3306 3307 /* 3308 * If all the buffer descriptors are filled with mbufs then fill in 3309 * the current consumer index with a new BD. Else if a maximum Rx 3310 * buffer limit is imposed then fill in the next producer index. 3311 */ 3312 rc = bxe_alloc_rx_bd_mbuf(fp, bd_cons, 3313 (sc->max_rx_bufs != RX_BD_USABLE) ? 3314 bd_prod : bd_cons); 3315 if (rc != 0) { 3316 3317 /* we simply reuse the received mbuf and don't post it to the stack */ 3318 m = NULL; 3319 3320 BLOGE(sc, "mbuf alloc fail for fp[%02d] rx chain (%d)\n", 3321 fp->index, rc); 3322 fp->eth_q_stats.rx_soft_errors++; 3323 3324 if (sc->max_rx_bufs != RX_BD_USABLE) { 3325 /* copy this consumer index to the producer index */ 3326 memcpy(&fp->rx_mbuf_chain[bd_prod], rx_buf, 3327 sizeof(struct bxe_sw_rx_bd)); 3328 memset(rx_buf, 0, sizeof(struct bxe_sw_rx_bd)); 3329 } 3330 3331 goto next_rx; 3332 } 3333 3334 /* current mbuf was detached from the bd */ 3335 fp->eth_q_stats.mbuf_alloc_rx--; 3336 3337 /* we allocated a replacement mbuf, fixup the current one */ 3338 m_adj(m, pad); 3339 m->m_pkthdr.len = m->m_len = len; 3340 3341 if ((len > 60) && (len > lenonbd)) { 3342 fp->eth_q_stats.rx_bxe_service_rxsgl++; 3343 rc = bxe_service_rxsgl(fp, len, lenonbd, m, cqe_fp); 3344 if (rc) 3345 break; 3346 fp->eth_q_stats.rx_jumbo_sge_pkts++; 3347 } else if (lenonbd < len) { 3348 fp->eth_q_stats.rx_erroneous_jumbo_sge_pkts++; 3349 } 3350 3351 /* assign packet to this interface interface */ 3352 if_setrcvif(m, ifp); 3353 3354 /* assume no hardware checksum has complated */ 3355 m->m_pkthdr.csum_flags = 0; 3356 3357 /* validate checksum if offload enabled */ 3358 if (if_getcapenable(ifp) & IFCAP_RXCSUM) { 3359 /* check for a valid IP frame */ 3360 if (!(cqe->fast_path_cqe.status_flags & 3361 ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG)) { 3362 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 3363 if (__predict_false(cqe_fp_flags & 3364 ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG)) { 3365 fp->eth_q_stats.rx_hw_csum_errors++; 3366 } else { 3367 fp->eth_q_stats.rx_ofld_frames_csum_ip++; 3368 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 3369 } 3370 } 3371 3372 /* check for a valid TCP/UDP frame */ 3373 if (!(cqe->fast_path_cqe.status_flags & 3374 ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG)) { 3375 if (__predict_false(cqe_fp_flags & 3376 ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG)) { 3377 fp->eth_q_stats.rx_hw_csum_errors++; 3378 } else { 3379 fp->eth_q_stats.rx_ofld_frames_csum_tcp_udp++; 3380 m->m_pkthdr.csum_data = 0xFFFF; 3381 m->m_pkthdr.csum_flags |= (CSUM_DATA_VALID | 3382 CSUM_PSEUDO_HDR); 3383 } 3384 } 3385 } 3386 3387 /* if there is a VLAN tag then flag that info */ 3388 if (cqe->fast_path_cqe.pars_flags.flags & PARSING_FLAGS_INNER_VLAN_EXIST) { 3389 m->m_pkthdr.ether_vtag = cqe->fast_path_cqe.vlan_tag; 3390 m->m_flags |= M_VLANTAG; 3391 } 3392 3393 #if __FreeBSD_version >= 800000 3394 /* specify what RSS queue was used for this flow */ 3395 m->m_pkthdr.flowid = fp->index; 3396 BXE_SET_FLOWID(m); 3397 #endif 3398 3399 next_rx: 3400 3401 bd_cons = RX_BD_NEXT(bd_cons); 3402 bd_prod = RX_BD_NEXT(bd_prod); 3403 bd_prod_fw = RX_BD_NEXT(bd_prod_fw); 3404 3405 /* pass the frame to the stack */ 3406 if (__predict_true(m != NULL)) { 3407 if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1); 3408 rx_pkts++; 3409 if_input(ifp, m); 3410 } 3411 3412 next_cqe: 3413 3414 sw_cq_prod = RCQ_NEXT(sw_cq_prod); 3415 sw_cq_cons = RCQ_NEXT(sw_cq_cons); 3416 3417 /* limit spinning on the queue */ 3418 if (rc != 0) 3419 break; 3420 3421 if (rx_pkts == sc->rx_budget) { 3422 fp->eth_q_stats.rx_budget_reached++; 3423 break; 3424 } 3425 } /* while work to do */ 3426 3427 fp->rx_bd_cons = bd_cons; 3428 fp->rx_bd_prod = bd_prod_fw; 3429 fp->rx_cq_cons = sw_cq_cons; 3430 fp->rx_cq_prod = sw_cq_prod; 3431 3432 /* Update producers */ 3433 bxe_update_rx_prod(sc, fp, bd_prod_fw, sw_cq_prod, fp->rx_sge_prod); 3434 3435 fp->eth_q_stats.rx_pkts += rx_pkts; 3436 fp->eth_q_stats.rx_calls++; 3437 3438 BXE_FP_RX_UNLOCK(fp); 3439 3440 return (sw_cq_cons != hw_cq_cons); 3441 } 3442 3443 static uint16_t 3444 bxe_free_tx_pkt(struct bxe_softc *sc, 3445 struct bxe_fastpath *fp, 3446 uint16_t idx) 3447 { 3448 struct bxe_sw_tx_bd *tx_buf = &fp->tx_mbuf_chain[idx]; 3449 struct eth_tx_start_bd *tx_start_bd; 3450 uint16_t bd_idx = TX_BD(tx_buf->first_bd); 3451 uint16_t new_cons; 3452 int nbd; 3453 3454 /* unmap the mbuf from non-paged memory */ 3455 bus_dmamap_unload(fp->tx_mbuf_tag, tx_buf->m_map); 3456 3457 tx_start_bd = &fp->tx_chain[bd_idx].start_bd; 3458 nbd = le16toh(tx_start_bd->nbd) - 1; 3459 3460 new_cons = (tx_buf->first_bd + nbd); 3461 3462 /* free the mbuf */ 3463 if (__predict_true(tx_buf->m != NULL)) { 3464 m_freem(tx_buf->m); 3465 fp->eth_q_stats.mbuf_alloc_tx--; 3466 } else { 3467 fp->eth_q_stats.tx_chain_lost_mbuf++; 3468 } 3469 3470 tx_buf->m = NULL; 3471 tx_buf->first_bd = 0; 3472 3473 return (new_cons); 3474 } 3475 3476 /* transmit timeout watchdog */ 3477 static int 3478 bxe_watchdog(struct bxe_softc *sc, 3479 struct bxe_fastpath *fp) 3480 { 3481 BXE_FP_TX_LOCK(fp); 3482 3483 if ((fp->watchdog_timer == 0) || (--fp->watchdog_timer)) { 3484 BXE_FP_TX_UNLOCK(fp); 3485 return (0); 3486 } 3487 3488 BLOGE(sc, "TX watchdog timeout on fp[%02d], resetting!\n", fp->index); 3489 if(sc->trigger_grcdump) { 3490 /* taking grcdump */ 3491 bxe_grc_dump(sc); 3492 } 3493 3494 BXE_FP_TX_UNLOCK(fp); 3495 3496 atomic_store_rel_long(&sc->chip_tq_flags, CHIP_TQ_REINIT); 3497 taskqueue_enqueue(sc->chip_tq, &sc->chip_tq_task); 3498 3499 return (-1); 3500 } 3501 3502 /* processes transmit completions */ 3503 static uint8_t 3504 bxe_txeof(struct bxe_softc *sc, 3505 struct bxe_fastpath *fp) 3506 { 3507 if_t ifp = sc->ifp; 3508 uint16_t bd_cons, hw_cons, sw_cons, pkt_cons; 3509 uint16_t tx_bd_avail; 3510 3511 BXE_FP_TX_LOCK_ASSERT(fp); 3512 3513 bd_cons = fp->tx_bd_cons; 3514 hw_cons = le16toh(*fp->tx_cons_sb); 3515 sw_cons = fp->tx_pkt_cons; 3516 3517 while (sw_cons != hw_cons) { 3518 pkt_cons = TX_BD(sw_cons); 3519 3520 BLOGD(sc, DBG_TX, 3521 "TX: fp[%d]: hw_cons=%u sw_cons=%u pkt_cons=%u\n", 3522 fp->index, hw_cons, sw_cons, pkt_cons); 3523 3524 bd_cons = bxe_free_tx_pkt(sc, fp, pkt_cons); 3525 3526 sw_cons++; 3527 } 3528 3529 fp->tx_pkt_cons = sw_cons; 3530 fp->tx_bd_cons = bd_cons; 3531 3532 BLOGD(sc, DBG_TX, 3533 "TX done: fp[%d]: hw_cons=%u sw_cons=%u sw_prod=%u\n", 3534 fp->index, hw_cons, fp->tx_pkt_cons, fp->tx_pkt_prod); 3535 3536 mb(); 3537 3538 tx_bd_avail = bxe_tx_avail(sc, fp); 3539 3540 if (tx_bd_avail < BXE_TX_CLEANUP_THRESHOLD) { 3541 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 3542 } else { 3543 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 3544 } 3545 3546 if (fp->tx_pkt_prod != fp->tx_pkt_cons) { 3547 /* reset the watchdog timer if there are pending transmits */ 3548 fp->watchdog_timer = BXE_TX_TIMEOUT; 3549 return (TRUE); 3550 } else { 3551 /* clear watchdog when there are no pending transmits */ 3552 fp->watchdog_timer = 0; 3553 return (FALSE); 3554 } 3555 } 3556 3557 static void 3558 bxe_drain_tx_queues(struct bxe_softc *sc) 3559 { 3560 struct bxe_fastpath *fp; 3561 int i, count; 3562 3563 /* wait until all TX fastpath tasks have completed */ 3564 for (i = 0; i < sc->num_queues; i++) { 3565 fp = &sc->fp[i]; 3566 3567 count = 1000; 3568 3569 while (bxe_has_tx_work(fp)) { 3570 3571 BXE_FP_TX_LOCK(fp); 3572 bxe_txeof(sc, fp); 3573 BXE_FP_TX_UNLOCK(fp); 3574 3575 if (count == 0) { 3576 BLOGE(sc, "Timeout waiting for fp[%d] " 3577 "transmits to complete!\n", i); 3578 bxe_panic(sc, ("tx drain failure\n")); 3579 return; 3580 } 3581 3582 count--; 3583 DELAY(1000); 3584 rmb(); 3585 } 3586 } 3587 3588 return; 3589 } 3590 3591 static int 3592 bxe_del_all_macs(struct bxe_softc *sc, 3593 struct ecore_vlan_mac_obj *mac_obj, 3594 int mac_type, 3595 uint8_t wait_for_comp) 3596 { 3597 unsigned long ramrod_flags = 0, vlan_mac_flags = 0; 3598 int rc; 3599 3600 /* wait for completion of requested */ 3601 if (wait_for_comp) { 3602 bxe_set_bit(RAMROD_COMP_WAIT, &ramrod_flags); 3603 } 3604 3605 /* Set the mac type of addresses we want to clear */ 3606 bxe_set_bit(mac_type, &vlan_mac_flags); 3607 3608 rc = mac_obj->delete_all(sc, mac_obj, &vlan_mac_flags, &ramrod_flags); 3609 if (rc < 0) { 3610 BLOGE(sc, "Failed to delete MACs (%d) mac_type %d wait_for_comp 0x%x\n", 3611 rc, mac_type, wait_for_comp); 3612 } 3613 3614 return (rc); 3615 } 3616 3617 static int 3618 bxe_fill_accept_flags(struct bxe_softc *sc, 3619 uint32_t rx_mode, 3620 unsigned long *rx_accept_flags, 3621 unsigned long *tx_accept_flags) 3622 { 3623 /* Clear the flags first */ 3624 *rx_accept_flags = 0; 3625 *tx_accept_flags = 0; 3626 3627 switch (rx_mode) { 3628 case BXE_RX_MODE_NONE: 3629 /* 3630 * 'drop all' supersedes any accept flags that may have been 3631 * passed to the function. 3632 */ 3633 break; 3634 3635 case BXE_RX_MODE_NORMAL: 3636 bxe_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags); 3637 bxe_set_bit(ECORE_ACCEPT_MULTICAST, rx_accept_flags); 3638 bxe_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags); 3639 3640 /* internal switching mode */ 3641 bxe_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags); 3642 bxe_set_bit(ECORE_ACCEPT_MULTICAST, tx_accept_flags); 3643 bxe_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags); 3644 3645 break; 3646 3647 case BXE_RX_MODE_ALLMULTI: 3648 bxe_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags); 3649 bxe_set_bit(ECORE_ACCEPT_ALL_MULTICAST, rx_accept_flags); 3650 bxe_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags); 3651 3652 /* internal switching mode */ 3653 bxe_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags); 3654 bxe_set_bit(ECORE_ACCEPT_ALL_MULTICAST, tx_accept_flags); 3655 bxe_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags); 3656 3657 break; 3658 3659 case BXE_RX_MODE_PROMISC: 3660 /* 3661 * According to deffinition of SI mode, iface in promisc mode 3662 * should receive matched and unmatched (in resolution of port) 3663 * unicast packets. 3664 */ 3665 bxe_set_bit(ECORE_ACCEPT_UNMATCHED, rx_accept_flags); 3666 bxe_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags); 3667 bxe_set_bit(ECORE_ACCEPT_ALL_MULTICAST, rx_accept_flags); 3668 bxe_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags); 3669 3670 /* internal switching mode */ 3671 bxe_set_bit(ECORE_ACCEPT_ALL_MULTICAST, tx_accept_flags); 3672 bxe_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags); 3673 3674 if (IS_MF_SI(sc)) { 3675 bxe_set_bit(ECORE_ACCEPT_ALL_UNICAST, tx_accept_flags); 3676 } else { 3677 bxe_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags); 3678 } 3679 3680 break; 3681 3682 default: 3683 BLOGE(sc, "Unknown rx_mode (0x%x)\n", rx_mode); 3684 return (-1); 3685 } 3686 3687 /* Set ACCEPT_ANY_VLAN as we do not enable filtering by VLAN */ 3688 if (rx_mode != BXE_RX_MODE_NONE) { 3689 bxe_set_bit(ECORE_ACCEPT_ANY_VLAN, rx_accept_flags); 3690 bxe_set_bit(ECORE_ACCEPT_ANY_VLAN, tx_accept_flags); 3691 } 3692 3693 return (0); 3694 } 3695 3696 static int 3697 bxe_set_q_rx_mode(struct bxe_softc *sc, 3698 uint8_t cl_id, 3699 unsigned long rx_mode_flags, 3700 unsigned long rx_accept_flags, 3701 unsigned long tx_accept_flags, 3702 unsigned long ramrod_flags) 3703 { 3704 struct ecore_rx_mode_ramrod_params ramrod_param; 3705 int rc; 3706 3707 memset(&ramrod_param, 0, sizeof(ramrod_param)); 3708 3709 /* Prepare ramrod parameters */ 3710 ramrod_param.cid = 0; 3711 ramrod_param.cl_id = cl_id; 3712 ramrod_param.rx_mode_obj = &sc->rx_mode_obj; 3713 ramrod_param.func_id = SC_FUNC(sc); 3714 3715 ramrod_param.pstate = &sc->sp_state; 3716 ramrod_param.state = ECORE_FILTER_RX_MODE_PENDING; 3717 3718 ramrod_param.rdata = BXE_SP(sc, rx_mode_rdata); 3719 ramrod_param.rdata_mapping = BXE_SP_MAPPING(sc, rx_mode_rdata); 3720 3721 bxe_set_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state); 3722 3723 ramrod_param.ramrod_flags = ramrod_flags; 3724 ramrod_param.rx_mode_flags = rx_mode_flags; 3725 3726 ramrod_param.rx_accept_flags = rx_accept_flags; 3727 ramrod_param.tx_accept_flags = tx_accept_flags; 3728 3729 rc = ecore_config_rx_mode(sc, &ramrod_param); 3730 if (rc < 0) { 3731 BLOGE(sc, "Set rx_mode %d cli_id 0x%x rx_mode_flags 0x%x " 3732 "rx_accept_flags 0x%x tx_accept_flags 0x%x " 3733 "ramrod_flags 0x%x rc %d failed\n", sc->rx_mode, cl_id, 3734 (uint32_t)rx_mode_flags, (uint32_t)rx_accept_flags, 3735 (uint32_t)tx_accept_flags, (uint32_t)ramrod_flags, rc); 3736 return (rc); 3737 } 3738 3739 return (0); 3740 } 3741 3742 static int 3743 bxe_set_storm_rx_mode(struct bxe_softc *sc) 3744 { 3745 unsigned long rx_mode_flags = 0, ramrod_flags = 0; 3746 unsigned long rx_accept_flags = 0, tx_accept_flags = 0; 3747 int rc; 3748 3749 rc = bxe_fill_accept_flags(sc, sc->rx_mode, &rx_accept_flags, 3750 &tx_accept_flags); 3751 if (rc) { 3752 return (rc); 3753 } 3754 3755 bxe_set_bit(RAMROD_RX, &ramrod_flags); 3756 bxe_set_bit(RAMROD_TX, &ramrod_flags); 3757 3758 /* XXX ensure all fastpath have same cl_id and/or move it to bxe_softc */ 3759 return (bxe_set_q_rx_mode(sc, sc->fp[0].cl_id, rx_mode_flags, 3760 rx_accept_flags, tx_accept_flags, 3761 ramrod_flags)); 3762 } 3763 3764 /* returns the "mcp load_code" according to global load_count array */ 3765 static int 3766 bxe_nic_load_no_mcp(struct bxe_softc *sc) 3767 { 3768 int path = SC_PATH(sc); 3769 int port = SC_PORT(sc); 3770 3771 BLOGI(sc, "NO MCP - load counts[%d] %d, %d, %d\n", 3772 path, load_count[path][0], load_count[path][1], 3773 load_count[path][2]); 3774 load_count[path][0]++; 3775 load_count[path][1 + port]++; 3776 BLOGI(sc, "NO MCP - new load counts[%d] %d, %d, %d\n", 3777 path, load_count[path][0], load_count[path][1], 3778 load_count[path][2]); 3779 if (load_count[path][0] == 1) { 3780 return (FW_MSG_CODE_DRV_LOAD_COMMON); 3781 } else if (load_count[path][1 + port] == 1) { 3782 return (FW_MSG_CODE_DRV_LOAD_PORT); 3783 } else { 3784 return (FW_MSG_CODE_DRV_LOAD_FUNCTION); 3785 } 3786 } 3787 3788 /* returns the "mcp load_code" according to global load_count array */ 3789 static int 3790 bxe_nic_unload_no_mcp(struct bxe_softc *sc) 3791 { 3792 int port = SC_PORT(sc); 3793 int path = SC_PATH(sc); 3794 3795 BLOGI(sc, "NO MCP - load counts[%d] %d, %d, %d\n", 3796 path, load_count[path][0], load_count[path][1], 3797 load_count[path][2]); 3798 load_count[path][0]--; 3799 load_count[path][1 + port]--; 3800 BLOGI(sc, "NO MCP - new load counts[%d] %d, %d, %d\n", 3801 path, load_count[path][0], load_count[path][1], 3802 load_count[path][2]); 3803 if (load_count[path][0] == 0) { 3804 return (FW_MSG_CODE_DRV_UNLOAD_COMMON); 3805 } else if (load_count[path][1 + port] == 0) { 3806 return (FW_MSG_CODE_DRV_UNLOAD_PORT); 3807 } else { 3808 return (FW_MSG_CODE_DRV_UNLOAD_FUNCTION); 3809 } 3810 } 3811 3812 /* request unload mode from the MCP: COMMON, PORT or FUNCTION */ 3813 static uint32_t 3814 bxe_send_unload_req(struct bxe_softc *sc, 3815 int unload_mode) 3816 { 3817 uint32_t reset_code = 0; 3818 3819 /* Select the UNLOAD request mode */ 3820 if (unload_mode == UNLOAD_NORMAL) { 3821 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; 3822 } else { 3823 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; 3824 } 3825 3826 /* Send the request to the MCP */ 3827 if (!BXE_NOMCP(sc)) { 3828 reset_code = bxe_fw_command(sc, reset_code, 0); 3829 } else { 3830 reset_code = bxe_nic_unload_no_mcp(sc); 3831 } 3832 3833 return (reset_code); 3834 } 3835 3836 /* send UNLOAD_DONE command to the MCP */ 3837 static void 3838 bxe_send_unload_done(struct bxe_softc *sc, 3839 uint8_t keep_link) 3840 { 3841 uint32_t reset_param = 3842 keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0; 3843 3844 /* Report UNLOAD_DONE to MCP */ 3845 if (!BXE_NOMCP(sc)) { 3846 bxe_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, reset_param); 3847 } 3848 } 3849 3850 static int 3851 bxe_func_wait_started(struct bxe_softc *sc) 3852 { 3853 int tout = 50; 3854 3855 if (!sc->port.pmf) { 3856 return (0); 3857 } 3858 3859 /* 3860 * (assumption: No Attention from MCP at this stage) 3861 * PMF probably in the middle of TX disable/enable transaction 3862 * 1. Sync IRS for default SB 3863 * 2. Sync SP queue - this guarantees us that attention handling started 3864 * 3. Wait, that TX disable/enable transaction completes 3865 * 3866 * 1+2 guarantee that if DCBX attention was scheduled it already changed 3867 * pending bit of transaction from STARTED-->TX_STOPPED, if we already 3868 * received completion for the transaction the state is TX_STOPPED. 3869 * State will return to STARTED after completion of TX_STOPPED-->STARTED 3870 * transaction. 3871 */ 3872 3873 /* XXX make sure default SB ISR is done */ 3874 /* need a way to synchronize an irq (intr_mtx?) */ 3875 3876 /* XXX flush any work queues */ 3877 3878 while (ecore_func_get_state(sc, &sc->func_obj) != 3879 ECORE_F_STATE_STARTED && tout--) { 3880 DELAY(20000); 3881 } 3882 3883 if (ecore_func_get_state(sc, &sc->func_obj) != ECORE_F_STATE_STARTED) { 3884 /* 3885 * Failed to complete the transaction in a "good way" 3886 * Force both transactions with CLR bit. 3887 */ 3888 struct ecore_func_state_params func_params = { NULL }; 3889 3890 BLOGE(sc, "Unexpected function state! " 3891 "Forcing STARTED-->TX_STOPPED-->STARTED\n"); 3892 3893 func_params.f_obj = &sc->func_obj; 3894 bxe_set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags); 3895 3896 /* STARTED-->TX_STOPPED */ 3897 func_params.cmd = ECORE_F_CMD_TX_STOP; 3898 ecore_func_state_change(sc, &func_params); 3899 3900 /* TX_STOPPED-->STARTED */ 3901 func_params.cmd = ECORE_F_CMD_TX_START; 3902 return (ecore_func_state_change(sc, &func_params)); 3903 } 3904 3905 return (0); 3906 } 3907 3908 static int 3909 bxe_stop_queue(struct bxe_softc *sc, 3910 int index) 3911 { 3912 struct bxe_fastpath *fp = &sc->fp[index]; 3913 struct ecore_queue_state_params q_params = { NULL }; 3914 int rc; 3915 3916 BLOGD(sc, DBG_LOAD, "stopping queue %d cid %d\n", index, fp->index); 3917 3918 q_params.q_obj = &sc->sp_objs[fp->index].q_obj; 3919 /* We want to wait for completion in this context */ 3920 bxe_set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags); 3921 3922 /* Stop the primary connection: */ 3923 3924 /* ...halt the connection */ 3925 q_params.cmd = ECORE_Q_CMD_HALT; 3926 rc = ecore_queue_state_change(sc, &q_params); 3927 if (rc) { 3928 return (rc); 3929 } 3930 3931 /* ...terminate the connection */ 3932 q_params.cmd = ECORE_Q_CMD_TERMINATE; 3933 memset(&q_params.params.terminate, 0, sizeof(q_params.params.terminate)); 3934 q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX; 3935 rc = ecore_queue_state_change(sc, &q_params); 3936 if (rc) { 3937 return (rc); 3938 } 3939 3940 /* ...delete cfc entry */ 3941 q_params.cmd = ECORE_Q_CMD_CFC_DEL; 3942 memset(&q_params.params.cfc_del, 0, sizeof(q_params.params.cfc_del)); 3943 q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX; 3944 return (ecore_queue_state_change(sc, &q_params)); 3945 } 3946 3947 /* wait for the outstanding SP commands */ 3948 static inline uint8_t 3949 bxe_wait_sp_comp(struct bxe_softc *sc, 3950 unsigned long mask) 3951 { 3952 unsigned long tmp; 3953 int tout = 5000; /* wait for 5 secs tops */ 3954 3955 while (tout--) { 3956 mb(); 3957 if (!(atomic_load_acq_long(&sc->sp_state) & mask)) { 3958 return (TRUE); 3959 } 3960 3961 DELAY(1000); 3962 } 3963 3964 mb(); 3965 3966 tmp = atomic_load_acq_long(&sc->sp_state); 3967 if (tmp & mask) { 3968 BLOGE(sc, "Filtering completion timed out: " 3969 "sp_state 0x%lx, mask 0x%lx\n", 3970 tmp, mask); 3971 return (FALSE); 3972 } 3973 3974 return (FALSE); 3975 } 3976 3977 static int 3978 bxe_func_stop(struct bxe_softc *sc) 3979 { 3980 struct ecore_func_state_params func_params = { NULL }; 3981 int rc; 3982 3983 /* prepare parameters for function state transitions */ 3984 bxe_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); 3985 func_params.f_obj = &sc->func_obj; 3986 func_params.cmd = ECORE_F_CMD_STOP; 3987 3988 /* 3989 * Try to stop the function the 'good way'. If it fails (in case 3990 * of a parity error during bxe_chip_cleanup()) and we are 3991 * not in a debug mode, perform a state transaction in order to 3992 * enable further HW_RESET transaction. 3993 */ 3994 rc = ecore_func_state_change(sc, &func_params); 3995 if (rc) { 3996 BLOGE(sc, "FUNC_STOP ramrod failed. " 3997 "Running a dry transaction (%d)\n", rc); 3998 bxe_set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags); 3999 return (ecore_func_state_change(sc, &func_params)); 4000 } 4001 4002 return (0); 4003 } 4004 4005 static int 4006 bxe_reset_hw(struct bxe_softc *sc, 4007 uint32_t load_code) 4008 { 4009 struct ecore_func_state_params func_params = { NULL }; 4010 4011 /* Prepare parameters for function state transitions */ 4012 bxe_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); 4013 4014 func_params.f_obj = &sc->func_obj; 4015 func_params.cmd = ECORE_F_CMD_HW_RESET; 4016 4017 func_params.params.hw_init.load_phase = load_code; 4018 4019 return (ecore_func_state_change(sc, &func_params)); 4020 } 4021 4022 static void 4023 bxe_int_disable_sync(struct bxe_softc *sc, 4024 int disable_hw) 4025 { 4026 if (disable_hw) { 4027 /* prevent the HW from sending interrupts */ 4028 bxe_int_disable(sc); 4029 } 4030 4031 /* XXX need a way to synchronize ALL irqs (intr_mtx?) */ 4032 /* make sure all ISRs are done */ 4033 4034 /* XXX make sure sp_task is not running */ 4035 /* cancel and flush work queues */ 4036 } 4037 4038 static void 4039 bxe_chip_cleanup(struct bxe_softc *sc, 4040 uint32_t unload_mode, 4041 uint8_t keep_link) 4042 { 4043 int port = SC_PORT(sc); 4044 struct ecore_mcast_ramrod_params rparam = { NULL }; 4045 uint32_t reset_code; 4046 int i, rc = 0; 4047 4048 bxe_drain_tx_queues(sc); 4049 4050 /* give HW time to discard old tx messages */ 4051 DELAY(1000); 4052 4053 /* Clean all ETH MACs */ 4054 rc = bxe_del_all_macs(sc, &sc->sp_objs[0].mac_obj, ECORE_ETH_MAC, FALSE); 4055 if (rc < 0) { 4056 BLOGE(sc, "Failed to delete all ETH MACs (%d)\n", rc); 4057 } 4058 4059 /* Clean up UC list */ 4060 rc = bxe_del_all_macs(sc, &sc->sp_objs[0].mac_obj, ECORE_UC_LIST_MAC, TRUE); 4061 if (rc < 0) { 4062 BLOGE(sc, "Failed to delete UC MACs list (%d)\n", rc); 4063 } 4064 4065 /* Disable LLH */ 4066 if (!CHIP_IS_E1(sc)) { 4067 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port*8, 0); 4068 } 4069 4070 /* Set "drop all" to stop Rx */ 4071 4072 /* 4073 * We need to take the BXE_MCAST_LOCK() here in order to prevent 4074 * a race between the completion code and this code. 4075 */ 4076 BXE_MCAST_LOCK(sc); 4077 4078 if (bxe_test_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state)) { 4079 bxe_set_bit(ECORE_FILTER_RX_MODE_SCHED, &sc->sp_state); 4080 } else { 4081 bxe_set_storm_rx_mode(sc); 4082 } 4083 4084 /* Clean up multicast configuration */ 4085 rparam.mcast_obj = &sc->mcast_obj; 4086 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_DEL); 4087 if (rc < 0) { 4088 BLOGE(sc, "Failed to send DEL MCAST command (%d)\n", rc); 4089 } 4090 4091 BXE_MCAST_UNLOCK(sc); 4092 4093 // XXX bxe_iov_chip_cleanup(sc); 4094 4095 /* 4096 * Send the UNLOAD_REQUEST to the MCP. This will return if 4097 * this function should perform FUNCTION, PORT, or COMMON HW 4098 * reset. 4099 */ 4100 reset_code = bxe_send_unload_req(sc, unload_mode); 4101 4102 /* 4103 * (assumption: No Attention from MCP at this stage) 4104 * PMF probably in the middle of TX disable/enable transaction 4105 */ 4106 rc = bxe_func_wait_started(sc); 4107 if (rc) { 4108 BLOGE(sc, "bxe_func_wait_started failed (%d)\n", rc); 4109 } 4110 4111 /* 4112 * Close multi and leading connections 4113 * Completions for ramrods are collected in a synchronous way 4114 */ 4115 for (i = 0; i < sc->num_queues; i++) { 4116 if (bxe_stop_queue(sc, i)) { 4117 goto unload_error; 4118 } 4119 } 4120 4121 /* 4122 * If SP settings didn't get completed so far - something 4123 * very wrong has happen. 4124 */ 4125 if (!bxe_wait_sp_comp(sc, ~0x0UL)) { 4126 BLOGE(sc, "Common slow path ramrods got stuck!(%d)\n", rc); 4127 } 4128 4129 unload_error: 4130 4131 rc = bxe_func_stop(sc); 4132 if (rc) { 4133 BLOGE(sc, "Function stop failed!(%d)\n", rc); 4134 } 4135 4136 /* disable HW interrupts */ 4137 bxe_int_disable_sync(sc, TRUE); 4138 4139 /* detach interrupts */ 4140 bxe_interrupt_detach(sc); 4141 4142 /* Reset the chip */ 4143 rc = bxe_reset_hw(sc, reset_code); 4144 if (rc) { 4145 BLOGE(sc, "Hardware reset failed(%d)\n", rc); 4146 } 4147 4148 /* Report UNLOAD_DONE to MCP */ 4149 bxe_send_unload_done(sc, keep_link); 4150 } 4151 4152 static void 4153 bxe_disable_close_the_gate(struct bxe_softc *sc) 4154 { 4155 uint32_t val; 4156 int port = SC_PORT(sc); 4157 4158 BLOGD(sc, DBG_LOAD, 4159 "Disabling 'close the gates'\n"); 4160 4161 if (CHIP_IS_E1(sc)) { 4162 uint32_t addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : 4163 MISC_REG_AEU_MASK_ATTN_FUNC_0; 4164 val = REG_RD(sc, addr); 4165 val &= ~(0x300); 4166 REG_WR(sc, addr, val); 4167 } else { 4168 val = REG_RD(sc, MISC_REG_AEU_GENERAL_MASK); 4169 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK | 4170 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK); 4171 REG_WR(sc, MISC_REG_AEU_GENERAL_MASK, val); 4172 } 4173 } 4174 4175 /* 4176 * Cleans the object that have internal lists without sending 4177 * ramrods. Should be run when interrutps are disabled. 4178 */ 4179 static void 4180 bxe_squeeze_objects(struct bxe_softc *sc) 4181 { 4182 unsigned long ramrod_flags = 0, vlan_mac_flags = 0; 4183 struct ecore_mcast_ramrod_params rparam = { NULL }; 4184 struct ecore_vlan_mac_obj *mac_obj = &sc->sp_objs->mac_obj; 4185 int rc; 4186 4187 /* Cleanup MACs' object first... */ 4188 4189 /* Wait for completion of requested */ 4190 bxe_set_bit(RAMROD_COMP_WAIT, &ramrod_flags); 4191 /* Perform a dry cleanup */ 4192 bxe_set_bit(RAMROD_DRV_CLR_ONLY, &ramrod_flags); 4193 4194 /* Clean ETH primary MAC */ 4195 bxe_set_bit(ECORE_ETH_MAC, &vlan_mac_flags); 4196 rc = mac_obj->delete_all(sc, &sc->sp_objs->mac_obj, &vlan_mac_flags, 4197 &ramrod_flags); 4198 if (rc != 0) { 4199 BLOGE(sc, "Failed to clean ETH MACs (%d)\n", rc); 4200 } 4201 4202 /* Cleanup UC list */ 4203 vlan_mac_flags = 0; 4204 bxe_set_bit(ECORE_UC_LIST_MAC, &vlan_mac_flags); 4205 rc = mac_obj->delete_all(sc, mac_obj, &vlan_mac_flags, 4206 &ramrod_flags); 4207 if (rc != 0) { 4208 BLOGE(sc, "Failed to clean UC list MACs (%d)\n", rc); 4209 } 4210 4211 /* Now clean mcast object... */ 4212 4213 rparam.mcast_obj = &sc->mcast_obj; 4214 bxe_set_bit(RAMROD_DRV_CLR_ONLY, &rparam.ramrod_flags); 4215 4216 /* Add a DEL command... */ 4217 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_DEL); 4218 if (rc < 0) { 4219 BLOGE(sc, "Failed to send DEL MCAST command (%d)\n", rc); 4220 } 4221 4222 /* now wait until all pending commands are cleared */ 4223 4224 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT); 4225 while (rc != 0) { 4226 if (rc < 0) { 4227 BLOGE(sc, "Failed to clean MCAST object (%d)\n", rc); 4228 return; 4229 } 4230 4231 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT); 4232 } 4233 } 4234 4235 /* stop the controller */ 4236 static __noinline int 4237 bxe_nic_unload(struct bxe_softc *sc, 4238 uint32_t unload_mode, 4239 uint8_t keep_link) 4240 { 4241 uint8_t global = FALSE; 4242 uint32_t val; 4243 int i; 4244 4245 BXE_CORE_LOCK_ASSERT(sc); 4246 4247 if_setdrvflagbits(sc->ifp, 0, IFF_DRV_RUNNING); 4248 4249 for (i = 0; i < sc->num_queues; i++) { 4250 struct bxe_fastpath *fp; 4251 4252 fp = &sc->fp[i]; 4253 BXE_FP_TX_LOCK(fp); 4254 BXE_FP_TX_UNLOCK(fp); 4255 } 4256 4257 BLOGD(sc, DBG_LOAD, "Starting NIC unload...\n"); 4258 4259 /* mark driver as unloaded in shmem2 */ 4260 if (IS_PF(sc) && SHMEM2_HAS(sc, drv_capabilities_flag)) { 4261 val = SHMEM2_RD(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)]); 4262 SHMEM2_WR(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)], 4263 val & ~DRV_FLAGS_CAPABILITIES_LOADED_L2); 4264 } 4265 4266 if (IS_PF(sc) && sc->recovery_state != BXE_RECOVERY_DONE && 4267 (sc->state == BXE_STATE_CLOSED || sc->state == BXE_STATE_ERROR)) { 4268 /* 4269 * We can get here if the driver has been unloaded 4270 * during parity error recovery and is either waiting for a 4271 * leader to complete or for other functions to unload and 4272 * then ifconfig down has been issued. In this case we want to 4273 * unload and let other functions to complete a recovery 4274 * process. 4275 */ 4276 sc->recovery_state = BXE_RECOVERY_DONE; 4277 sc->is_leader = 0; 4278 bxe_release_leader_lock(sc); 4279 mb(); 4280 4281 BLOGD(sc, DBG_LOAD, "Releasing a leadership...\n"); 4282 BLOGE(sc, "Can't unload in closed or error state recover_state 0x%x" 4283 " state = 0x%x\n", sc->recovery_state, sc->state); 4284 return (-1); 4285 } 4286 4287 /* 4288 * Nothing to do during unload if previous bxe_nic_load() 4289 * did not completed successfully - all resourses are released. 4290 */ 4291 if ((sc->state == BXE_STATE_CLOSED) || 4292 (sc->state == BXE_STATE_ERROR)) { 4293 return (0); 4294 } 4295 4296 sc->state = BXE_STATE_CLOSING_WAITING_HALT; 4297 mb(); 4298 4299 /* stop tx */ 4300 bxe_tx_disable(sc); 4301 4302 sc->rx_mode = BXE_RX_MODE_NONE; 4303 /* XXX set rx mode ??? */ 4304 4305 if (IS_PF(sc) && !sc->grcdump_done) { 4306 /* set ALWAYS_ALIVE bit in shmem */ 4307 sc->fw_drv_pulse_wr_seq |= DRV_PULSE_ALWAYS_ALIVE; 4308 4309 bxe_drv_pulse(sc); 4310 4311 bxe_stats_handle(sc, STATS_EVENT_STOP); 4312 bxe_save_statistics(sc); 4313 } 4314 4315 /* wait till consumers catch up with producers in all queues */ 4316 bxe_drain_tx_queues(sc); 4317 4318 /* if VF indicate to PF this function is going down (PF will delete sp 4319 * elements and clear initializations 4320 */ 4321 if (IS_VF(sc)) { 4322 ; /* bxe_vfpf_close_vf(sc); */ 4323 } else if (unload_mode != UNLOAD_RECOVERY) { 4324 /* if this is a normal/close unload need to clean up chip */ 4325 if (!sc->grcdump_done) 4326 bxe_chip_cleanup(sc, unload_mode, keep_link); 4327 } else { 4328 /* Send the UNLOAD_REQUEST to the MCP */ 4329 bxe_send_unload_req(sc, unload_mode); 4330 4331 /* 4332 * Prevent transactions to host from the functions on the 4333 * engine that doesn't reset global blocks in case of global 4334 * attention once gloabl blocks are reset and gates are opened 4335 * (the engine which leader will perform the recovery 4336 * last). 4337 */ 4338 if (!CHIP_IS_E1x(sc)) { 4339 bxe_pf_disable(sc); 4340 } 4341 4342 /* disable HW interrupts */ 4343 bxe_int_disable_sync(sc, TRUE); 4344 4345 /* detach interrupts */ 4346 bxe_interrupt_detach(sc); 4347 4348 /* Report UNLOAD_DONE to MCP */ 4349 bxe_send_unload_done(sc, FALSE); 4350 } 4351 4352 /* 4353 * At this stage no more interrupts will arrive so we may safely clean 4354 * the queue'able objects here in case they failed to get cleaned so far. 4355 */ 4356 if (IS_PF(sc)) { 4357 bxe_squeeze_objects(sc); 4358 } 4359 4360 /* There should be no more pending SP commands at this stage */ 4361 sc->sp_state = 0; 4362 4363 sc->port.pmf = 0; 4364 4365 bxe_free_fp_buffers(sc); 4366 4367 if (IS_PF(sc)) { 4368 bxe_free_mem(sc); 4369 } 4370 4371 bxe_free_fw_stats_mem(sc); 4372 4373 sc->state = BXE_STATE_CLOSED; 4374 4375 /* 4376 * Check if there are pending parity attentions. If there are - set 4377 * RECOVERY_IN_PROGRESS. 4378 */ 4379 if (IS_PF(sc) && bxe_chk_parity_attn(sc, &global, FALSE)) { 4380 bxe_set_reset_in_progress(sc); 4381 4382 /* Set RESET_IS_GLOBAL if needed */ 4383 if (global) { 4384 bxe_set_reset_global(sc); 4385 } 4386 } 4387 4388 /* 4389 * The last driver must disable a "close the gate" if there is no 4390 * parity attention or "process kill" pending. 4391 */ 4392 if (IS_PF(sc) && !bxe_clear_pf_load(sc) && 4393 bxe_reset_is_done(sc, SC_PATH(sc))) { 4394 bxe_disable_close_the_gate(sc); 4395 } 4396 4397 BLOGD(sc, DBG_LOAD, "Ended NIC unload\n"); 4398 4399 bxe_link_report(sc); 4400 4401 return (0); 4402 } 4403 4404 /* 4405 * Called by the OS to set various media options (i.e. link, speed, etc.) when 4406 * the user runs "ifconfig bxe media ..." or "ifconfig bxe mediaopt ...". 4407 */ 4408 static int 4409 bxe_ifmedia_update(struct ifnet *ifp) 4410 { 4411 struct bxe_softc *sc = (struct bxe_softc *)if_getsoftc(ifp); 4412 struct ifmedia *ifm; 4413 4414 ifm = &sc->ifmedia; 4415 4416 /* We only support Ethernet media type. */ 4417 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) { 4418 return (EINVAL); 4419 } 4420 4421 switch (IFM_SUBTYPE(ifm->ifm_media)) { 4422 case IFM_AUTO: 4423 break; 4424 case IFM_10G_CX4: 4425 case IFM_10G_SR: 4426 case IFM_10G_T: 4427 case IFM_10G_TWINAX: 4428 default: 4429 /* We don't support changing the media type. */ 4430 BLOGD(sc, DBG_LOAD, "Invalid media type (%d)\n", 4431 IFM_SUBTYPE(ifm->ifm_media)); 4432 return (EINVAL); 4433 } 4434 4435 return (0); 4436 } 4437 4438 /* 4439 * Called by the OS to get the current media status (i.e. link, speed, etc.). 4440 */ 4441 static void 4442 bxe_ifmedia_status(struct ifnet *ifp, struct ifmediareq *ifmr) 4443 { 4444 struct bxe_softc *sc = if_getsoftc(ifp); 4445 4446 /* Bug 165447: the 'ifconfig' tool skips printing of the "status: ..." 4447 line if the IFM_AVALID flag is *NOT* set. So we need to set this 4448 flag unconditionally (irrespective of the admininistrative 4449 'up/down' state of the interface) to ensure that that line is always 4450 displayed. 4451 */ 4452 ifmr->ifm_status = IFM_AVALID; 4453 4454 /* Setup the default interface info. */ 4455 ifmr->ifm_active = IFM_ETHER; 4456 4457 /* Report link down if the driver isn't running. */ 4458 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 4459 ifmr->ifm_active |= IFM_NONE; 4460 BLOGD(sc, DBG_PHY, "in %s : nic still not loaded fully\n", __func__); 4461 BLOGD(sc, DBG_PHY, "in %s : link_up (1) : %d\n", 4462 __func__, sc->link_vars.link_up); 4463 return; 4464 } 4465 4466 4467 if (sc->link_vars.link_up) { 4468 ifmr->ifm_status |= IFM_ACTIVE; 4469 ifmr->ifm_active |= IFM_FDX; 4470 } else { 4471 ifmr->ifm_active |= IFM_NONE; 4472 BLOGD(sc, DBG_PHY, "in %s : setting IFM_NONE\n", 4473 __func__); 4474 return; 4475 } 4476 4477 ifmr->ifm_active |= sc->media; 4478 return; 4479 } 4480 4481 static void 4482 bxe_handle_chip_tq(void *context, 4483 int pending) 4484 { 4485 struct bxe_softc *sc = (struct bxe_softc *)context; 4486 long work = atomic_load_acq_long(&sc->chip_tq_flags); 4487 4488 switch (work) 4489 { 4490 4491 case CHIP_TQ_REINIT: 4492 if (if_getdrvflags(sc->ifp) & IFF_DRV_RUNNING) { 4493 /* restart the interface */ 4494 BLOGD(sc, DBG_LOAD, "Restarting the interface...\n"); 4495 bxe_periodic_stop(sc); 4496 BXE_CORE_LOCK(sc); 4497 bxe_stop_locked(sc); 4498 bxe_init_locked(sc); 4499 BXE_CORE_UNLOCK(sc); 4500 } 4501 break; 4502 4503 default: 4504 break; 4505 } 4506 } 4507 4508 /* 4509 * Handles any IOCTL calls from the operating system. 4510 * 4511 * Returns: 4512 * 0 = Success, >0 Failure 4513 */ 4514 static int 4515 bxe_ioctl(if_t ifp, 4516 u_long command, 4517 caddr_t data) 4518 { 4519 struct bxe_softc *sc = if_getsoftc(ifp); 4520 struct ifreq *ifr = (struct ifreq *)data; 4521 int mask = 0; 4522 int reinit = 0; 4523 int error = 0; 4524 4525 int mtu_min = (ETH_MIN_PACKET_SIZE - ETH_HLEN); 4526 int mtu_max = (MJUM9BYTES - ETH_OVERHEAD - IP_HEADER_ALIGNMENT_PADDING); 4527 4528 switch (command) 4529 { 4530 case SIOCSIFMTU: 4531 BLOGD(sc, DBG_IOCTL, "Received SIOCSIFMTU ioctl (mtu=%d)\n", 4532 ifr->ifr_mtu); 4533 4534 if (sc->mtu == ifr->ifr_mtu) { 4535 /* nothing to change */ 4536 break; 4537 } 4538 4539 if ((ifr->ifr_mtu < mtu_min) || (ifr->ifr_mtu > mtu_max)) { 4540 BLOGE(sc, "Unsupported MTU size %d (range is %d-%d)\n", 4541 ifr->ifr_mtu, mtu_min, mtu_max); 4542 error = EINVAL; 4543 break; 4544 } 4545 4546 atomic_store_rel_int((volatile unsigned int *)&sc->mtu, 4547 (unsigned long)ifr->ifr_mtu); 4548 /* 4549 atomic_store_rel_long((volatile unsigned long *)&if_getmtu(ifp), 4550 (unsigned long)ifr->ifr_mtu); 4551 XXX - Not sure why it needs to be atomic 4552 */ 4553 if_setmtu(ifp, ifr->ifr_mtu); 4554 reinit = 1; 4555 break; 4556 4557 case SIOCSIFFLAGS: 4558 /* toggle the interface state up or down */ 4559 BLOGD(sc, DBG_IOCTL, "Received SIOCSIFFLAGS ioctl\n"); 4560 4561 BXE_CORE_LOCK(sc); 4562 /* check if the interface is up */ 4563 if (if_getflags(ifp) & IFF_UP) { 4564 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4565 /* set the receive mode flags */ 4566 bxe_set_rx_mode(sc); 4567 } else if(sc->state != BXE_STATE_DISABLED) { 4568 bxe_init_locked(sc); 4569 } 4570 } else { 4571 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4572 bxe_periodic_stop(sc); 4573 bxe_stop_locked(sc); 4574 } 4575 } 4576 BXE_CORE_UNLOCK(sc); 4577 4578 break; 4579 4580 case SIOCADDMULTI: 4581 case SIOCDELMULTI: 4582 /* add/delete multicast addresses */ 4583 BLOGD(sc, DBG_IOCTL, "Received SIOCADDMULTI/SIOCDELMULTI ioctl\n"); 4584 4585 /* check if the interface is up */ 4586 if (if_getdrvflags(ifp) & IFF_DRV_RUNNING) { 4587 /* set the receive mode flags */ 4588 BXE_CORE_LOCK(sc); 4589 bxe_set_rx_mode(sc); 4590 BXE_CORE_UNLOCK(sc); 4591 } 4592 4593 break; 4594 4595 case SIOCSIFCAP: 4596 /* find out which capabilities have changed */ 4597 mask = (ifr->ifr_reqcap ^ if_getcapenable(ifp)); 4598 4599 BLOGD(sc, DBG_IOCTL, "Received SIOCSIFCAP ioctl (mask=0x%08x)\n", 4600 mask); 4601 4602 /* toggle the LRO capabilites enable flag */ 4603 if (mask & IFCAP_LRO) { 4604 if_togglecapenable(ifp, IFCAP_LRO); 4605 BLOGD(sc, DBG_IOCTL, "Turning LRO %s\n", 4606 (if_getcapenable(ifp) & IFCAP_LRO) ? "ON" : "OFF"); 4607 reinit = 1; 4608 } 4609 4610 /* toggle the TXCSUM checksum capabilites enable flag */ 4611 if (mask & IFCAP_TXCSUM) { 4612 if_togglecapenable(ifp, IFCAP_TXCSUM); 4613 BLOGD(sc, DBG_IOCTL, "Turning TXCSUM %s\n", 4614 (if_getcapenable(ifp) & IFCAP_TXCSUM) ? "ON" : "OFF"); 4615 if (if_getcapenable(ifp) & IFCAP_TXCSUM) { 4616 if_sethwassistbits(ifp, (CSUM_IP | 4617 CSUM_TCP | 4618 CSUM_UDP | 4619 CSUM_TSO | 4620 CSUM_TCP_IPV6 | 4621 CSUM_UDP_IPV6), 0); 4622 } else { 4623 if_clearhwassist(ifp); /* XXX */ 4624 } 4625 } 4626 4627 /* toggle the RXCSUM checksum capabilities enable flag */ 4628 if (mask & IFCAP_RXCSUM) { 4629 if_togglecapenable(ifp, IFCAP_RXCSUM); 4630 BLOGD(sc, DBG_IOCTL, "Turning RXCSUM %s\n", 4631 (if_getcapenable(ifp) & IFCAP_RXCSUM) ? "ON" : "OFF"); 4632 if (if_getcapenable(ifp) & IFCAP_RXCSUM) { 4633 if_sethwassistbits(ifp, (CSUM_IP | 4634 CSUM_TCP | 4635 CSUM_UDP | 4636 CSUM_TSO | 4637 CSUM_TCP_IPV6 | 4638 CSUM_UDP_IPV6), 0); 4639 } else { 4640 if_clearhwassist(ifp); /* XXX */ 4641 } 4642 } 4643 4644 /* toggle TSO4 capabilities enabled flag */ 4645 if (mask & IFCAP_TSO4) { 4646 if_togglecapenable(ifp, IFCAP_TSO4); 4647 BLOGD(sc, DBG_IOCTL, "Turning TSO4 %s\n", 4648 (if_getcapenable(ifp) & IFCAP_TSO4) ? "ON" : "OFF"); 4649 } 4650 4651 /* toggle TSO6 capabilities enabled flag */ 4652 if (mask & IFCAP_TSO6) { 4653 if_togglecapenable(ifp, IFCAP_TSO6); 4654 BLOGD(sc, DBG_IOCTL, "Turning TSO6 %s\n", 4655 (if_getcapenable(ifp) & IFCAP_TSO6) ? "ON" : "OFF"); 4656 } 4657 4658 /* toggle VLAN_HWTSO capabilities enabled flag */ 4659 if (mask & IFCAP_VLAN_HWTSO) { 4660 4661 if_togglecapenable(ifp, IFCAP_VLAN_HWTSO); 4662 BLOGD(sc, DBG_IOCTL, "Turning VLAN_HWTSO %s\n", 4663 (if_getcapenable(ifp) & IFCAP_VLAN_HWTSO) ? "ON" : "OFF"); 4664 } 4665 4666 /* toggle VLAN_HWCSUM capabilities enabled flag */ 4667 if (mask & IFCAP_VLAN_HWCSUM) { 4668 /* XXX investigate this... */ 4669 BLOGE(sc, "Changing VLAN_HWCSUM is not supported!\n"); 4670 error = EINVAL; 4671 } 4672 4673 /* toggle VLAN_MTU capabilities enable flag */ 4674 if (mask & IFCAP_VLAN_MTU) { 4675 /* XXX investigate this... */ 4676 BLOGE(sc, "Changing VLAN_MTU is not supported!\n"); 4677 error = EINVAL; 4678 } 4679 4680 /* toggle VLAN_HWTAGGING capabilities enabled flag */ 4681 if (mask & IFCAP_VLAN_HWTAGGING) { 4682 /* XXX investigate this... */ 4683 BLOGE(sc, "Changing VLAN_HWTAGGING is not supported!\n"); 4684 error = EINVAL; 4685 } 4686 4687 /* toggle VLAN_HWFILTER capabilities enabled flag */ 4688 if (mask & IFCAP_VLAN_HWFILTER) { 4689 /* XXX investigate this... */ 4690 BLOGE(sc, "Changing VLAN_HWFILTER is not supported!\n"); 4691 error = EINVAL; 4692 } 4693 4694 /* XXX not yet... 4695 * IFCAP_WOL_MAGIC 4696 */ 4697 4698 break; 4699 4700 case SIOCSIFMEDIA: 4701 case SIOCGIFMEDIA: 4702 /* set/get interface media */ 4703 BLOGD(sc, DBG_IOCTL, 4704 "Received SIOCSIFMEDIA/SIOCGIFMEDIA ioctl (cmd=%lu)\n", 4705 (command & 0xff)); 4706 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 4707 break; 4708 4709 default: 4710 BLOGD(sc, DBG_IOCTL, "Received Unknown Ioctl (cmd=%lu)\n", 4711 (command & 0xff)); 4712 error = ether_ioctl(ifp, command, data); 4713 break; 4714 } 4715 4716 if (reinit && (if_getdrvflags(sc->ifp) & IFF_DRV_RUNNING)) { 4717 BLOGD(sc, DBG_LOAD | DBG_IOCTL, 4718 "Re-initializing hardware from IOCTL change\n"); 4719 bxe_periodic_stop(sc); 4720 BXE_CORE_LOCK(sc); 4721 bxe_stop_locked(sc); 4722 bxe_init_locked(sc); 4723 BXE_CORE_UNLOCK(sc); 4724 } 4725 4726 return (error); 4727 } 4728 4729 static __noinline void 4730 bxe_dump_mbuf(struct bxe_softc *sc, 4731 struct mbuf *m, 4732 uint8_t contents) 4733 { 4734 char * type; 4735 int i = 0; 4736 4737 if (!(sc->debug & DBG_MBUF)) { 4738 return; 4739 } 4740 4741 if (m == NULL) { 4742 BLOGD(sc, DBG_MBUF, "mbuf: null pointer\n"); 4743 return; 4744 } 4745 4746 while (m) { 4747 4748 #if __FreeBSD_version >= 1000000 4749 BLOGD(sc, DBG_MBUF, 4750 "%02d: mbuf=%p m_len=%d m_flags=0x%b m_data=%p\n", 4751 i, m, m->m_len, m->m_flags, M_FLAG_BITS, m->m_data); 4752 4753 if (m->m_flags & M_PKTHDR) { 4754 BLOGD(sc, DBG_MBUF, 4755 "%02d: - m_pkthdr: tot_len=%d flags=0x%b csum_flags=%b\n", 4756 i, m->m_pkthdr.len, m->m_flags, M_FLAG_BITS, 4757 (int)m->m_pkthdr.csum_flags, CSUM_BITS); 4758 } 4759 #else 4760 BLOGD(sc, DBG_MBUF, 4761 "%02d: mbuf=%p m_len=%d m_flags=0x%b m_data=%p\n", 4762 i, m, m->m_len, m->m_flags, 4763 "\20\1M_EXT\2M_PKTHDR\3M_EOR\4M_RDONLY", m->m_data); 4764 4765 if (m->m_flags & M_PKTHDR) { 4766 BLOGD(sc, DBG_MBUF, 4767 "%02d: - m_pkthdr: tot_len=%d flags=0x%b csum_flags=%b\n", 4768 i, m->m_pkthdr.len, m->m_flags, 4769 "\20\12M_BCAST\13M_MCAST\14M_FRAG" 4770 "\15M_FIRSTFRAG\16M_LASTFRAG\21M_VLANTAG" 4771 "\22M_PROMISC\23M_NOFREE", 4772 (int)m->m_pkthdr.csum_flags, 4773 "\20\1CSUM_IP\2CSUM_TCP\3CSUM_UDP\4CSUM_IP_FRAGS" 4774 "\5CSUM_FRAGMENT\6CSUM_TSO\11CSUM_IP_CHECKED" 4775 "\12CSUM_IP_VALID\13CSUM_DATA_VALID" 4776 "\14CSUM_PSEUDO_HDR"); 4777 } 4778 #endif /* #if __FreeBSD_version >= 1000000 */ 4779 4780 if (m->m_flags & M_EXT) { 4781 switch (m->m_ext.ext_type) { 4782 case EXT_CLUSTER: type = "EXT_CLUSTER"; break; 4783 case EXT_SFBUF: type = "EXT_SFBUF"; break; 4784 case EXT_JUMBOP: type = "EXT_JUMBOP"; break; 4785 case EXT_JUMBO9: type = "EXT_JUMBO9"; break; 4786 case EXT_JUMBO16: type = "EXT_JUMBO16"; break; 4787 case EXT_PACKET: type = "EXT_PACKET"; break; 4788 case EXT_MBUF: type = "EXT_MBUF"; break; 4789 case EXT_NET_DRV: type = "EXT_NET_DRV"; break; 4790 case EXT_MOD_TYPE: type = "EXT_MOD_TYPE"; break; 4791 case EXT_DISPOSABLE: type = "EXT_DISPOSABLE"; break; 4792 case EXT_EXTREF: type = "EXT_EXTREF"; break; 4793 default: type = "UNKNOWN"; break; 4794 } 4795 4796 BLOGD(sc, DBG_MBUF, 4797 "%02d: - m_ext: %p ext_size=%d type=%s\n", 4798 i, m->m_ext.ext_buf, m->m_ext.ext_size, type); 4799 } 4800 4801 if (contents) { 4802 bxe_dump_mbuf_data(sc, "mbuf data", m, TRUE); 4803 } 4804 4805 m = m->m_next; 4806 i++; 4807 } 4808 } 4809 4810 /* 4811 * Checks to ensure the 13 bd sliding window is >= MSS for TSO. 4812 * Check that (13 total bds - 3 bds) = 10 bd window >= MSS. 4813 * The window: 3 bds are = 1 for headers BD + 2 for parse BD and last BD 4814 * The headers comes in a separate bd in FreeBSD so 13-3=10. 4815 * Returns: 0 if OK to send, 1 if packet needs further defragmentation 4816 */ 4817 static int 4818 bxe_chktso_window(struct bxe_softc *sc, 4819 int nsegs, 4820 bus_dma_segment_t *segs, 4821 struct mbuf *m) 4822 { 4823 uint32_t num_wnds, wnd_size, wnd_sum; 4824 int32_t frag_idx, wnd_idx; 4825 unsigned short lso_mss; 4826 int defrag; 4827 4828 defrag = 0; 4829 wnd_sum = 0; 4830 wnd_size = 10; 4831 num_wnds = nsegs - wnd_size; 4832 lso_mss = htole16(m->m_pkthdr.tso_segsz); 4833 4834 /* 4835 * Total header lengths Eth+IP+TCP in first FreeBSD mbuf so calculate the 4836 * first window sum of data while skipping the first assuming it is the 4837 * header in FreeBSD. 4838 */ 4839 for (frag_idx = 1; (frag_idx <= wnd_size); frag_idx++) { 4840 wnd_sum += htole16(segs[frag_idx].ds_len); 4841 } 4842 4843 /* check the first 10 bd window size */ 4844 if (wnd_sum < lso_mss) { 4845 return (1); 4846 } 4847 4848 /* run through the windows */ 4849 for (wnd_idx = 0; wnd_idx < num_wnds; wnd_idx++, frag_idx++) { 4850 /* subtract the first mbuf->m_len of the last wndw(-header) */ 4851 wnd_sum -= htole16(segs[wnd_idx+1].ds_len); 4852 /* add the next mbuf len to the len of our new window */ 4853 wnd_sum += htole16(segs[frag_idx].ds_len); 4854 if (wnd_sum < lso_mss) { 4855 return (1); 4856 } 4857 } 4858 4859 return (0); 4860 } 4861 4862 static uint8_t 4863 bxe_set_pbd_csum_e2(struct bxe_fastpath *fp, 4864 struct mbuf *m, 4865 uint32_t *parsing_data) 4866 { 4867 struct ether_vlan_header *eh = NULL; 4868 struct ip *ip4 = NULL; 4869 struct ip6_hdr *ip6 = NULL; 4870 caddr_t ip = NULL; 4871 struct tcphdr *th = NULL; 4872 int e_hlen, ip_hlen, l4_off; 4873 uint16_t proto; 4874 4875 if (m->m_pkthdr.csum_flags == CSUM_IP) { 4876 /* no L4 checksum offload needed */ 4877 return (0); 4878 } 4879 4880 /* get the Ethernet header */ 4881 eh = mtod(m, struct ether_vlan_header *); 4882 4883 /* handle VLAN encapsulation if present */ 4884 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 4885 e_hlen = (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN); 4886 proto = ntohs(eh->evl_proto); 4887 } else { 4888 e_hlen = ETHER_HDR_LEN; 4889 proto = ntohs(eh->evl_encap_proto); 4890 } 4891 4892 switch (proto) { 4893 case ETHERTYPE_IP: 4894 /* get the IP header, if mbuf len < 20 then header in next mbuf */ 4895 ip4 = (m->m_len < sizeof(struct ip)) ? 4896 (struct ip *)m->m_next->m_data : 4897 (struct ip *)(m->m_data + e_hlen); 4898 /* ip_hl is number of 32-bit words */ 4899 ip_hlen = (ip4->ip_hl << 2); 4900 ip = (caddr_t)ip4; 4901 break; 4902 case ETHERTYPE_IPV6: 4903 /* get the IPv6 header, if mbuf len < 40 then header in next mbuf */ 4904 ip6 = (m->m_len < sizeof(struct ip6_hdr)) ? 4905 (struct ip6_hdr *)m->m_next->m_data : 4906 (struct ip6_hdr *)(m->m_data + e_hlen); 4907 /* XXX cannot support offload with IPv6 extensions */ 4908 ip_hlen = sizeof(struct ip6_hdr); 4909 ip = (caddr_t)ip6; 4910 break; 4911 default: 4912 /* We can't offload in this case... */ 4913 /* XXX error stat ??? */ 4914 return (0); 4915 } 4916 4917 /* XXX assuming L4 header is contiguous to IPv4/IPv6 in the same mbuf */ 4918 l4_off = (e_hlen + ip_hlen); 4919 4920 *parsing_data |= 4921 (((l4_off >> 1) << ETH_TX_PARSE_BD_E2_L4_HDR_START_OFFSET_W_SHIFT) & 4922 ETH_TX_PARSE_BD_E2_L4_HDR_START_OFFSET_W); 4923 4924 if (m->m_pkthdr.csum_flags & (CSUM_TCP | 4925 CSUM_TSO | 4926 CSUM_TCP_IPV6)) { 4927 fp->eth_q_stats.tx_ofld_frames_csum_tcp++; 4928 th = (struct tcphdr *)(ip + ip_hlen); 4929 /* th_off is number of 32-bit words */ 4930 *parsing_data |= ((th->th_off << 4931 ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW_SHIFT) & 4932 ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW); 4933 return (l4_off + (th->th_off << 2)); /* entire header length */ 4934 } else if (m->m_pkthdr.csum_flags & (CSUM_UDP | 4935 CSUM_UDP_IPV6)) { 4936 fp->eth_q_stats.tx_ofld_frames_csum_udp++; 4937 return (l4_off + sizeof(struct udphdr)); /* entire header length */ 4938 } else { 4939 /* XXX error stat ??? */ 4940 return (0); 4941 } 4942 } 4943 4944 static uint8_t 4945 bxe_set_pbd_csum(struct bxe_fastpath *fp, 4946 struct mbuf *m, 4947 struct eth_tx_parse_bd_e1x *pbd) 4948 { 4949 struct ether_vlan_header *eh = NULL; 4950 struct ip *ip4 = NULL; 4951 struct ip6_hdr *ip6 = NULL; 4952 caddr_t ip = NULL; 4953 struct tcphdr *th = NULL; 4954 struct udphdr *uh = NULL; 4955 int e_hlen, ip_hlen; 4956 uint16_t proto; 4957 uint8_t hlen; 4958 uint16_t tmp_csum; 4959 uint32_t *tmp_uh; 4960 4961 /* get the Ethernet header */ 4962 eh = mtod(m, struct ether_vlan_header *); 4963 4964 /* handle VLAN encapsulation if present */ 4965 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 4966 e_hlen = (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN); 4967 proto = ntohs(eh->evl_proto); 4968 } else { 4969 e_hlen = ETHER_HDR_LEN; 4970 proto = ntohs(eh->evl_encap_proto); 4971 } 4972 4973 switch (proto) { 4974 case ETHERTYPE_IP: 4975 /* get the IP header, if mbuf len < 20 then header in next mbuf */ 4976 ip4 = (m->m_len < sizeof(struct ip)) ? 4977 (struct ip *)m->m_next->m_data : 4978 (struct ip *)(m->m_data + e_hlen); 4979 /* ip_hl is number of 32-bit words */ 4980 ip_hlen = (ip4->ip_hl << 1); 4981 ip = (caddr_t)ip4; 4982 break; 4983 case ETHERTYPE_IPV6: 4984 /* get the IPv6 header, if mbuf len < 40 then header in next mbuf */ 4985 ip6 = (m->m_len < sizeof(struct ip6_hdr)) ? 4986 (struct ip6_hdr *)m->m_next->m_data : 4987 (struct ip6_hdr *)(m->m_data + e_hlen); 4988 /* XXX cannot support offload with IPv6 extensions */ 4989 ip_hlen = (sizeof(struct ip6_hdr) >> 1); 4990 ip = (caddr_t)ip6; 4991 break; 4992 default: 4993 /* We can't offload in this case... */ 4994 /* XXX error stat ??? */ 4995 return (0); 4996 } 4997 4998 hlen = (e_hlen >> 1); 4999 5000 /* note that rest of global_data is indirectly zeroed here */ 5001 if (m->m_flags & M_VLANTAG) { 5002 pbd->global_data = 5003 htole16(hlen | (1 << ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN_SHIFT)); 5004 } else { 5005 pbd->global_data = htole16(hlen); 5006 } 5007 5008 pbd->ip_hlen_w = ip_hlen; 5009 5010 hlen += pbd->ip_hlen_w; 5011 5012 /* XXX assuming L4 header is contiguous to IPv4/IPv6 in the same mbuf */ 5013 5014 if (m->m_pkthdr.csum_flags & (CSUM_TCP | 5015 CSUM_TSO | 5016 CSUM_TCP_IPV6)) { 5017 th = (struct tcphdr *)(ip + (ip_hlen << 1)); 5018 /* th_off is number of 32-bit words */ 5019 hlen += (uint16_t)(th->th_off << 1); 5020 } else if (m->m_pkthdr.csum_flags & (CSUM_UDP | 5021 CSUM_UDP_IPV6)) { 5022 uh = (struct udphdr *)(ip + (ip_hlen << 1)); 5023 hlen += (sizeof(struct udphdr) / 2); 5024 } else { 5025 /* valid case as only CSUM_IP was set */ 5026 return (0); 5027 } 5028 5029 pbd->total_hlen_w = htole16(hlen); 5030 5031 if (m->m_pkthdr.csum_flags & (CSUM_TCP | 5032 CSUM_TSO | 5033 CSUM_TCP_IPV6)) { 5034 fp->eth_q_stats.tx_ofld_frames_csum_tcp++; 5035 pbd->tcp_pseudo_csum = ntohs(th->th_sum); 5036 } else if (m->m_pkthdr.csum_flags & (CSUM_UDP | 5037 CSUM_UDP_IPV6)) { 5038 fp->eth_q_stats.tx_ofld_frames_csum_udp++; 5039 5040 /* 5041 * Everest1 (i.e. 57710, 57711, 57711E) does not natively support UDP 5042 * checksums and does not know anything about the UDP header and where 5043 * the checksum field is located. It only knows about TCP. Therefore 5044 * we "lie" to the hardware for outgoing UDP packets w/ checksum 5045 * offload. Since the checksum field offset for TCP is 16 bytes and 5046 * for UDP it is 6 bytes we pass a pointer to the hardware that is 10 5047 * bytes less than the start of the UDP header. This allows the 5048 * hardware to write the checksum in the correct spot. But the 5049 * hardware will compute a checksum which includes the last 10 bytes 5050 * of the IP header. To correct this we tweak the stack computed 5051 * pseudo checksum by folding in the calculation of the inverse 5052 * checksum for those final 10 bytes of the IP header. This allows 5053 * the correct checksum to be computed by the hardware. 5054 */ 5055 5056 /* set pointer 10 bytes before UDP header */ 5057 tmp_uh = (uint32_t *)((uint8_t *)uh - 10); 5058 5059 /* calculate a pseudo header checksum over the first 10 bytes */ 5060 tmp_csum = in_pseudo(*tmp_uh, 5061 *(tmp_uh + 1), 5062 *(uint16_t *)(tmp_uh + 2)); 5063 5064 pbd->tcp_pseudo_csum = ntohs(in_addword(uh->uh_sum, ~tmp_csum)); 5065 } 5066 5067 return (hlen * 2); /* entire header length, number of bytes */ 5068 } 5069 5070 static void 5071 bxe_set_pbd_lso_e2(struct mbuf *m, 5072 uint32_t *parsing_data) 5073 { 5074 *parsing_data |= ((m->m_pkthdr.tso_segsz << 5075 ETH_TX_PARSE_BD_E2_LSO_MSS_SHIFT) & 5076 ETH_TX_PARSE_BD_E2_LSO_MSS); 5077 5078 /* XXX test for IPv6 with extension header... */ 5079 } 5080 5081 static void 5082 bxe_set_pbd_lso(struct mbuf *m, 5083 struct eth_tx_parse_bd_e1x *pbd) 5084 { 5085 struct ether_vlan_header *eh = NULL; 5086 struct ip *ip = NULL; 5087 struct tcphdr *th = NULL; 5088 int e_hlen; 5089 5090 /* get the Ethernet header */ 5091 eh = mtod(m, struct ether_vlan_header *); 5092 5093 /* handle VLAN encapsulation if present */ 5094 e_hlen = (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) ? 5095 (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN) : ETHER_HDR_LEN; 5096 5097 /* get the IP and TCP header, with LSO entire header in first mbuf */ 5098 /* XXX assuming IPv4 */ 5099 ip = (struct ip *)(m->m_data + e_hlen); 5100 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 5101 5102 pbd->lso_mss = htole16(m->m_pkthdr.tso_segsz); 5103 pbd->tcp_send_seq = ntohl(th->th_seq); 5104 pbd->tcp_flags = ((ntohl(((uint32_t *)th)[3]) >> 16) & 0xff); 5105 5106 #if 1 5107 /* XXX IPv4 */ 5108 pbd->ip_id = ntohs(ip->ip_id); 5109 pbd->tcp_pseudo_csum = 5110 ntohs(in_pseudo(ip->ip_src.s_addr, 5111 ip->ip_dst.s_addr, 5112 htons(IPPROTO_TCP))); 5113 #else 5114 /* XXX IPv6 */ 5115 pbd->tcp_pseudo_csum = 5116 ntohs(in_pseudo(&ip6->ip6_src, 5117 &ip6->ip6_dst, 5118 htons(IPPROTO_TCP))); 5119 #endif 5120 5121 pbd->global_data |= 5122 htole16(ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN); 5123 } 5124 5125 /* 5126 * Encapsulte an mbuf cluster into the tx bd chain and makes the memory 5127 * visible to the controller. 5128 * 5129 * If an mbuf is submitted to this routine and cannot be given to the 5130 * controller (e.g. it has too many fragments) then the function may free 5131 * the mbuf and return to the caller. 5132 * 5133 * Returns: 5134 * 0 = Success, !0 = Failure 5135 * Note the side effect that an mbuf may be freed if it causes a problem. 5136 */ 5137 static int 5138 bxe_tx_encap(struct bxe_fastpath *fp, struct mbuf **m_head) 5139 { 5140 bus_dma_segment_t segs[32]; 5141 struct mbuf *m0; 5142 struct bxe_sw_tx_bd *tx_buf; 5143 struct eth_tx_parse_bd_e1x *pbd_e1x = NULL; 5144 struct eth_tx_parse_bd_e2 *pbd_e2 = NULL; 5145 /* struct eth_tx_parse_2nd_bd *pbd2 = NULL; */ 5146 struct eth_tx_bd *tx_data_bd; 5147 struct eth_tx_bd *tx_total_pkt_size_bd; 5148 struct eth_tx_start_bd *tx_start_bd; 5149 uint16_t bd_prod, pkt_prod, total_pkt_size; 5150 uint8_t mac_type; 5151 int defragged, error, nsegs, rc, nbds, vlan_off, ovlan; 5152 struct bxe_softc *sc; 5153 uint16_t tx_bd_avail; 5154 struct ether_vlan_header *eh; 5155 uint32_t pbd_e2_parsing_data = 0; 5156 uint8_t hlen = 0; 5157 int tmp_bd; 5158 int i; 5159 5160 sc = fp->sc; 5161 5162 #if __FreeBSD_version >= 800000 5163 M_ASSERTPKTHDR(*m_head); 5164 #endif /* #if __FreeBSD_version >= 800000 */ 5165 5166 m0 = *m_head; 5167 rc = defragged = nbds = ovlan = vlan_off = total_pkt_size = 0; 5168 tx_start_bd = NULL; 5169 tx_data_bd = NULL; 5170 tx_total_pkt_size_bd = NULL; 5171 5172 /* get the H/W pointer for packets and BDs */ 5173 pkt_prod = fp->tx_pkt_prod; 5174 bd_prod = fp->tx_bd_prod; 5175 5176 mac_type = UNICAST_ADDRESS; 5177 5178 /* map the mbuf into the next open DMAable memory */ 5179 tx_buf = &fp->tx_mbuf_chain[TX_BD(pkt_prod)]; 5180 error = bus_dmamap_load_mbuf_sg(fp->tx_mbuf_tag, 5181 tx_buf->m_map, m0, 5182 segs, &nsegs, BUS_DMA_NOWAIT); 5183 5184 /* mapping errors */ 5185 if(__predict_false(error != 0)) { 5186 fp->eth_q_stats.tx_dma_mapping_failure++; 5187 if (error == ENOMEM) { 5188 /* resource issue, try again later */ 5189 rc = ENOMEM; 5190 } else if (error == EFBIG) { 5191 /* possibly recoverable with defragmentation */ 5192 fp->eth_q_stats.mbuf_defrag_attempts++; 5193 m0 = m_defrag(*m_head, M_NOWAIT); 5194 if (m0 == NULL) { 5195 fp->eth_q_stats.mbuf_defrag_failures++; 5196 rc = ENOBUFS; 5197 } else { 5198 /* defrag successful, try mapping again */ 5199 *m_head = m0; 5200 error = bus_dmamap_load_mbuf_sg(fp->tx_mbuf_tag, 5201 tx_buf->m_map, m0, 5202 segs, &nsegs, BUS_DMA_NOWAIT); 5203 if (error) { 5204 fp->eth_q_stats.tx_dma_mapping_failure++; 5205 rc = error; 5206 } 5207 } 5208 } else { 5209 /* unknown, unrecoverable mapping error */ 5210 BLOGE(sc, "Unknown TX mapping error rc=%d\n", error); 5211 bxe_dump_mbuf(sc, m0, FALSE); 5212 rc = error; 5213 } 5214 5215 goto bxe_tx_encap_continue; 5216 } 5217 5218 tx_bd_avail = bxe_tx_avail(sc, fp); 5219 5220 /* make sure there is enough room in the send queue */ 5221 if (__predict_false(tx_bd_avail < (nsegs + 2))) { 5222 /* Recoverable, try again later. */ 5223 fp->eth_q_stats.tx_hw_queue_full++; 5224 bus_dmamap_unload(fp->tx_mbuf_tag, tx_buf->m_map); 5225 rc = ENOMEM; 5226 goto bxe_tx_encap_continue; 5227 } 5228 5229 /* capture the current H/W TX chain high watermark */ 5230 if (__predict_false(fp->eth_q_stats.tx_hw_max_queue_depth < 5231 (TX_BD_USABLE - tx_bd_avail))) { 5232 fp->eth_q_stats.tx_hw_max_queue_depth = (TX_BD_USABLE - tx_bd_avail); 5233 } 5234 5235 /* make sure it fits in the packet window */ 5236 if (__predict_false(nsegs > BXE_MAX_SEGMENTS)) { 5237 /* 5238 * The mbuf may be to big for the controller to handle. If the frame 5239 * is a TSO frame we'll need to do an additional check. 5240 */ 5241 if (m0->m_pkthdr.csum_flags & CSUM_TSO) { 5242 if (bxe_chktso_window(sc, nsegs, segs, m0) == 0) { 5243 goto bxe_tx_encap_continue; /* OK to send */ 5244 } else { 5245 fp->eth_q_stats.tx_window_violation_tso++; 5246 } 5247 } else { 5248 fp->eth_q_stats.tx_window_violation_std++; 5249 } 5250 5251 /* lets try to defragment this mbuf and remap it */ 5252 fp->eth_q_stats.mbuf_defrag_attempts++; 5253 bus_dmamap_unload(fp->tx_mbuf_tag, tx_buf->m_map); 5254 5255 m0 = m_defrag(*m_head, M_NOWAIT); 5256 if (m0 == NULL) { 5257 fp->eth_q_stats.mbuf_defrag_failures++; 5258 /* Ugh, just drop the frame... :( */ 5259 rc = ENOBUFS; 5260 } else { 5261 /* defrag successful, try mapping again */ 5262 *m_head = m0; 5263 error = bus_dmamap_load_mbuf_sg(fp->tx_mbuf_tag, 5264 tx_buf->m_map, m0, 5265 segs, &nsegs, BUS_DMA_NOWAIT); 5266 if (error) { 5267 fp->eth_q_stats.tx_dma_mapping_failure++; 5268 /* No sense in trying to defrag/copy chain, drop it. :( */ 5269 rc = error; 5270 } else { 5271 /* if the chain is still too long then drop it */ 5272 if(m0->m_pkthdr.csum_flags & CSUM_TSO) { 5273 /* 5274 * in case TSO is enabled nsegs should be checked against 5275 * BXE_TSO_MAX_SEGMENTS 5276 */ 5277 if (__predict_false(nsegs > BXE_TSO_MAX_SEGMENTS)) { 5278 bus_dmamap_unload(fp->tx_mbuf_tag, tx_buf->m_map); 5279 fp->eth_q_stats.nsegs_path1_errors++; 5280 rc = ENODEV; 5281 } 5282 } else { 5283 if (__predict_false(nsegs > BXE_MAX_SEGMENTS)) { 5284 bus_dmamap_unload(fp->tx_mbuf_tag, tx_buf->m_map); 5285 fp->eth_q_stats.nsegs_path2_errors++; 5286 rc = ENODEV; 5287 } 5288 } 5289 } 5290 } 5291 } 5292 5293 bxe_tx_encap_continue: 5294 5295 /* Check for errors */ 5296 if (rc) { 5297 if (rc == ENOMEM) { 5298 /* recoverable try again later */ 5299 } else { 5300 fp->eth_q_stats.tx_soft_errors++; 5301 fp->eth_q_stats.mbuf_alloc_tx--; 5302 m_freem(*m_head); 5303 *m_head = NULL; 5304 } 5305 5306 return (rc); 5307 } 5308 5309 /* set flag according to packet type (UNICAST_ADDRESS is default) */ 5310 if (m0->m_flags & M_BCAST) { 5311 mac_type = BROADCAST_ADDRESS; 5312 } else if (m0->m_flags & M_MCAST) { 5313 mac_type = MULTICAST_ADDRESS; 5314 } 5315 5316 /* store the mbuf into the mbuf ring */ 5317 tx_buf->m = m0; 5318 tx_buf->first_bd = fp->tx_bd_prod; 5319 tx_buf->flags = 0; 5320 5321 /* prepare the first transmit (start) BD for the mbuf */ 5322 tx_start_bd = &fp->tx_chain[TX_BD(bd_prod)].start_bd; 5323 5324 BLOGD(sc, DBG_TX, 5325 "sending pkt_prod=%u tx_buf=%p next_idx=%u bd=%u tx_start_bd=%p\n", 5326 pkt_prod, tx_buf, fp->tx_pkt_prod, bd_prod, tx_start_bd); 5327 5328 tx_start_bd->addr_lo = htole32(U64_LO(segs[0].ds_addr)); 5329 tx_start_bd->addr_hi = htole32(U64_HI(segs[0].ds_addr)); 5330 tx_start_bd->nbytes = htole16(segs[0].ds_len); 5331 total_pkt_size += tx_start_bd->nbytes; 5332 tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD; 5333 5334 tx_start_bd->general_data = (1 << ETH_TX_START_BD_HDR_NBDS_SHIFT); 5335 5336 /* all frames have at least Start BD + Parsing BD */ 5337 nbds = nsegs + 1; 5338 tx_start_bd->nbd = htole16(nbds); 5339 5340 if (m0->m_flags & M_VLANTAG) { 5341 tx_start_bd->vlan_or_ethertype = htole16(m0->m_pkthdr.ether_vtag); 5342 tx_start_bd->bd_flags.as_bitfield |= 5343 (X_ETH_OUTBAND_VLAN << ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT); 5344 } else { 5345 /* vf tx, start bd must hold the ethertype for fw to enforce it */ 5346 if (IS_VF(sc)) { 5347 /* map ethernet header to find type and header length */ 5348 eh = mtod(m0, struct ether_vlan_header *); 5349 tx_start_bd->vlan_or_ethertype = eh->evl_encap_proto; 5350 } else { 5351 /* used by FW for packet accounting */ 5352 tx_start_bd->vlan_or_ethertype = htole16(fp->tx_pkt_prod); 5353 } 5354 } 5355 5356 /* 5357 * add a parsing BD from the chain. The parsing BD is always added 5358 * though it is only used for TSO and chksum 5359 */ 5360 bd_prod = TX_BD_NEXT(bd_prod); 5361 5362 if (m0->m_pkthdr.csum_flags) { 5363 if (m0->m_pkthdr.csum_flags & CSUM_IP) { 5364 fp->eth_q_stats.tx_ofld_frames_csum_ip++; 5365 tx_start_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_IP_CSUM; 5366 } 5367 5368 if (m0->m_pkthdr.csum_flags & CSUM_TCP_IPV6) { 5369 tx_start_bd->bd_flags.as_bitfield |= (ETH_TX_BD_FLAGS_IPV6 | 5370 ETH_TX_BD_FLAGS_L4_CSUM); 5371 } else if (m0->m_pkthdr.csum_flags & CSUM_UDP_IPV6) { 5372 tx_start_bd->bd_flags.as_bitfield |= (ETH_TX_BD_FLAGS_IPV6 | 5373 ETH_TX_BD_FLAGS_IS_UDP | 5374 ETH_TX_BD_FLAGS_L4_CSUM); 5375 } else if ((m0->m_pkthdr.csum_flags & CSUM_TCP) || 5376 (m0->m_pkthdr.csum_flags & CSUM_TSO)) { 5377 tx_start_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_L4_CSUM; 5378 } else if (m0->m_pkthdr.csum_flags & CSUM_UDP) { 5379 tx_start_bd->bd_flags.as_bitfield |= (ETH_TX_BD_FLAGS_L4_CSUM | 5380 ETH_TX_BD_FLAGS_IS_UDP); 5381 } 5382 } 5383 5384 if (!CHIP_IS_E1x(sc)) { 5385 pbd_e2 = &fp->tx_chain[TX_BD(bd_prod)].parse_bd_e2; 5386 memset(pbd_e2, 0, sizeof(struct eth_tx_parse_bd_e2)); 5387 5388 if (m0->m_pkthdr.csum_flags) { 5389 hlen = bxe_set_pbd_csum_e2(fp, m0, &pbd_e2_parsing_data); 5390 } 5391 5392 SET_FLAG(pbd_e2_parsing_data, ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE, 5393 mac_type); 5394 } else { 5395 uint16_t global_data = 0; 5396 5397 pbd_e1x = &fp->tx_chain[TX_BD(bd_prod)].parse_bd_e1x; 5398 memset(pbd_e1x, 0, sizeof(struct eth_tx_parse_bd_e1x)); 5399 5400 if (m0->m_pkthdr.csum_flags) { 5401 hlen = bxe_set_pbd_csum(fp, m0, pbd_e1x); 5402 } 5403 5404 SET_FLAG(global_data, 5405 ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE, mac_type); 5406 pbd_e1x->global_data |= htole16(global_data); 5407 } 5408 5409 /* setup the parsing BD with TSO specific info */ 5410 if (m0->m_pkthdr.csum_flags & CSUM_TSO) { 5411 fp->eth_q_stats.tx_ofld_frames_lso++; 5412 tx_start_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_SW_LSO; 5413 5414 if (__predict_false(tx_start_bd->nbytes > hlen)) { 5415 fp->eth_q_stats.tx_ofld_frames_lso_hdr_splits++; 5416 5417 /* split the first BD into header/data making the fw job easy */ 5418 nbds++; 5419 tx_start_bd->nbd = htole16(nbds); 5420 tx_start_bd->nbytes = htole16(hlen); 5421 5422 bd_prod = TX_BD_NEXT(bd_prod); 5423 5424 /* new transmit BD after the tx_parse_bd */ 5425 tx_data_bd = &fp->tx_chain[TX_BD(bd_prod)].reg_bd; 5426 tx_data_bd->addr_hi = htole32(U64_HI(segs[0].ds_addr + hlen)); 5427 tx_data_bd->addr_lo = htole32(U64_LO(segs[0].ds_addr + hlen)); 5428 tx_data_bd->nbytes = htole16(segs[0].ds_len - hlen); 5429 if (tx_total_pkt_size_bd == NULL) { 5430 tx_total_pkt_size_bd = tx_data_bd; 5431 } 5432 5433 BLOGD(sc, DBG_TX, 5434 "TSO split header size is %d (%x:%x) nbds %d\n", 5435 le16toh(tx_start_bd->nbytes), 5436 le32toh(tx_start_bd->addr_hi), 5437 le32toh(tx_start_bd->addr_lo), 5438 nbds); 5439 } 5440 5441 if (!CHIP_IS_E1x(sc)) { 5442 bxe_set_pbd_lso_e2(m0, &pbd_e2_parsing_data); 5443 } else { 5444 bxe_set_pbd_lso(m0, pbd_e1x); 5445 } 5446 } 5447 5448 if (pbd_e2_parsing_data) { 5449 pbd_e2->parsing_data = htole32(pbd_e2_parsing_data); 5450 } 5451 5452 /* prepare remaining BDs, start tx bd contains first seg/frag */ 5453 for (i = 1; i < nsegs ; i++) { 5454 bd_prod = TX_BD_NEXT(bd_prod); 5455 tx_data_bd = &fp->tx_chain[TX_BD(bd_prod)].reg_bd; 5456 tx_data_bd->addr_lo = htole32(U64_LO(segs[i].ds_addr)); 5457 tx_data_bd->addr_hi = htole32(U64_HI(segs[i].ds_addr)); 5458 tx_data_bd->nbytes = htole16(segs[i].ds_len); 5459 if (tx_total_pkt_size_bd == NULL) { 5460 tx_total_pkt_size_bd = tx_data_bd; 5461 } 5462 total_pkt_size += tx_data_bd->nbytes; 5463 } 5464 5465 BLOGD(sc, DBG_TX, "last bd %p\n", tx_data_bd); 5466 5467 if (tx_total_pkt_size_bd != NULL) { 5468 tx_total_pkt_size_bd->total_pkt_bytes = total_pkt_size; 5469 } 5470 5471 if (__predict_false(sc->debug & DBG_TX)) { 5472 tmp_bd = tx_buf->first_bd; 5473 for (i = 0; i < nbds; i++) 5474 { 5475 if (i == 0) { 5476 BLOGD(sc, DBG_TX, 5477 "TX Strt: %p bd=%d nbd=%d vlan=0x%x " 5478 "bd_flags=0x%x hdr_nbds=%d\n", 5479 tx_start_bd, 5480 tmp_bd, 5481 le16toh(tx_start_bd->nbd), 5482 le16toh(tx_start_bd->vlan_or_ethertype), 5483 tx_start_bd->bd_flags.as_bitfield, 5484 (tx_start_bd->general_data & ETH_TX_START_BD_HDR_NBDS)); 5485 } else if (i == 1) { 5486 if (pbd_e1x) { 5487 BLOGD(sc, DBG_TX, 5488 "-> Prse: %p bd=%d global=0x%x ip_hlen_w=%u " 5489 "ip_id=%u lso_mss=%u tcp_flags=0x%x csum=0x%x " 5490 "tcp_seq=%u total_hlen_w=%u\n", 5491 pbd_e1x, 5492 tmp_bd, 5493 pbd_e1x->global_data, 5494 pbd_e1x->ip_hlen_w, 5495 pbd_e1x->ip_id, 5496 pbd_e1x->lso_mss, 5497 pbd_e1x->tcp_flags, 5498 pbd_e1x->tcp_pseudo_csum, 5499 pbd_e1x->tcp_send_seq, 5500 le16toh(pbd_e1x->total_hlen_w)); 5501 } else { /* if (pbd_e2) */ 5502 BLOGD(sc, DBG_TX, 5503 "-> Parse: %p bd=%d dst=%02x:%02x:%02x " 5504 "src=%02x:%02x:%02x parsing_data=0x%x\n", 5505 pbd_e2, 5506 tmp_bd, 5507 pbd_e2->data.mac_addr.dst_hi, 5508 pbd_e2->data.mac_addr.dst_mid, 5509 pbd_e2->data.mac_addr.dst_lo, 5510 pbd_e2->data.mac_addr.src_hi, 5511 pbd_e2->data.mac_addr.src_mid, 5512 pbd_e2->data.mac_addr.src_lo, 5513 pbd_e2->parsing_data); 5514 } 5515 } 5516 5517 if (i != 1) { /* skip parse db as it doesn't hold data */ 5518 tx_data_bd = &fp->tx_chain[TX_BD(tmp_bd)].reg_bd; 5519 BLOGD(sc, DBG_TX, 5520 "-> Frag: %p bd=%d nbytes=%d hi=0x%x lo: 0x%x\n", 5521 tx_data_bd, 5522 tmp_bd, 5523 le16toh(tx_data_bd->nbytes), 5524 le32toh(tx_data_bd->addr_hi), 5525 le32toh(tx_data_bd->addr_lo)); 5526 } 5527 5528 tmp_bd = TX_BD_NEXT(tmp_bd); 5529 } 5530 } 5531 5532 BLOGD(sc, DBG_TX, "doorbell: nbds=%d bd=%u\n", nbds, bd_prod); 5533 5534 /* update TX BD producer index value for next TX */ 5535 bd_prod = TX_BD_NEXT(bd_prod); 5536 5537 /* 5538 * If the chain of tx_bd's describing this frame is adjacent to or spans 5539 * an eth_tx_next_bd element then we need to increment the nbds value. 5540 */ 5541 if (TX_BD_IDX(bd_prod) < nbds) { 5542 nbds++; 5543 } 5544 5545 /* don't allow reordering of writes for nbd and packets */ 5546 mb(); 5547 5548 fp->tx_db.data.prod += nbds; 5549 5550 /* producer points to the next free tx_bd at this point */ 5551 fp->tx_pkt_prod++; 5552 fp->tx_bd_prod = bd_prod; 5553 5554 DOORBELL(sc, fp->index, fp->tx_db.raw); 5555 5556 fp->eth_q_stats.tx_pkts++; 5557 5558 /* Prevent speculative reads from getting ahead of the status block. */ 5559 bus_space_barrier(sc->bar[BAR0].tag, sc->bar[BAR0].handle, 5560 0, 0, BUS_SPACE_BARRIER_READ); 5561 5562 /* Prevent speculative reads from getting ahead of the doorbell. */ 5563 bus_space_barrier(sc->bar[BAR2].tag, sc->bar[BAR2].handle, 5564 0, 0, BUS_SPACE_BARRIER_READ); 5565 5566 return (0); 5567 } 5568 5569 static void 5570 bxe_tx_start_locked(struct bxe_softc *sc, 5571 if_t ifp, 5572 struct bxe_fastpath *fp) 5573 { 5574 struct mbuf *m = NULL; 5575 int tx_count = 0; 5576 uint16_t tx_bd_avail; 5577 5578 BXE_FP_TX_LOCK_ASSERT(fp); 5579 5580 /* keep adding entries while there are frames to send */ 5581 while (!if_sendq_empty(ifp)) { 5582 5583 /* 5584 * check for any frames to send 5585 * dequeue can still be NULL even if queue is not empty 5586 */ 5587 m = if_dequeue(ifp); 5588 if (__predict_false(m == NULL)) { 5589 break; 5590 } 5591 5592 /* the mbuf now belongs to us */ 5593 fp->eth_q_stats.mbuf_alloc_tx++; 5594 5595 /* 5596 * Put the frame into the transmit ring. If we don't have room, 5597 * place the mbuf back at the head of the TX queue, set the 5598 * OACTIVE flag, and wait for the NIC to drain the chain. 5599 */ 5600 if (__predict_false(bxe_tx_encap(fp, &m))) { 5601 fp->eth_q_stats.tx_encap_failures++; 5602 if (m != NULL) { 5603 /* mark the TX queue as full and return the frame */ 5604 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 5605 if_sendq_prepend(ifp, m); 5606 fp->eth_q_stats.mbuf_alloc_tx--; 5607 fp->eth_q_stats.tx_queue_xoff++; 5608 } 5609 5610 /* stop looking for more work */ 5611 break; 5612 } 5613 5614 /* the frame was enqueued successfully */ 5615 tx_count++; 5616 5617 /* send a copy of the frame to any BPF listeners. */ 5618 if_etherbpfmtap(ifp, m); 5619 5620 tx_bd_avail = bxe_tx_avail(sc, fp); 5621 5622 /* handle any completions if we're running low */ 5623 if (tx_bd_avail < BXE_TX_CLEANUP_THRESHOLD) { 5624 /* bxe_txeof will set IFF_DRV_OACTIVE appropriately */ 5625 bxe_txeof(sc, fp); 5626 if (if_getdrvflags(ifp) & IFF_DRV_OACTIVE) { 5627 break; 5628 } 5629 } 5630 } 5631 5632 /* all TX packets were dequeued and/or the tx ring is full */ 5633 if (tx_count > 0) { 5634 /* reset the TX watchdog timeout timer */ 5635 fp->watchdog_timer = BXE_TX_TIMEOUT; 5636 } 5637 } 5638 5639 /* Legacy (non-RSS) dispatch routine */ 5640 static void 5641 bxe_tx_start(if_t ifp) 5642 { 5643 struct bxe_softc *sc; 5644 struct bxe_fastpath *fp; 5645 5646 sc = if_getsoftc(ifp); 5647 5648 if (!(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) { 5649 BLOGW(sc, "Interface not running, ignoring transmit request\n"); 5650 return; 5651 } 5652 5653 if (!sc->link_vars.link_up) { 5654 BLOGW(sc, "Interface link is down, ignoring transmit request\n"); 5655 return; 5656 } 5657 5658 fp = &sc->fp[0]; 5659 5660 if (if_getdrvflags(ifp) & IFF_DRV_OACTIVE) { 5661 fp->eth_q_stats.tx_queue_full_return++; 5662 return; 5663 } 5664 5665 BXE_FP_TX_LOCK(fp); 5666 bxe_tx_start_locked(sc, ifp, fp); 5667 BXE_FP_TX_UNLOCK(fp); 5668 } 5669 5670 #if __FreeBSD_version >= 901504 5671 5672 static int 5673 bxe_tx_mq_start_locked(struct bxe_softc *sc, 5674 if_t ifp, 5675 struct bxe_fastpath *fp, 5676 struct mbuf *m) 5677 { 5678 struct buf_ring *tx_br = fp->tx_br; 5679 struct mbuf *next; 5680 int depth, rc, tx_count; 5681 uint16_t tx_bd_avail; 5682 5683 rc = tx_count = 0; 5684 5685 BXE_FP_TX_LOCK_ASSERT(fp); 5686 5687 if (sc->state != BXE_STATE_OPEN) { 5688 fp->eth_q_stats.bxe_tx_mq_sc_state_failures++; 5689 return ENETDOWN; 5690 } 5691 5692 if (!tx_br) { 5693 BLOGE(sc, "Multiqueue TX and no buf_ring!\n"); 5694 return (EINVAL); 5695 } 5696 5697 if (m != NULL) { 5698 rc = drbr_enqueue(ifp, tx_br, m); 5699 if (rc != 0) { 5700 fp->eth_q_stats.tx_soft_errors++; 5701 goto bxe_tx_mq_start_locked_exit; 5702 } 5703 } 5704 5705 if (!sc->link_vars.link_up || !(if_getdrvflags(ifp) & IFF_DRV_RUNNING)) { 5706 fp->eth_q_stats.tx_request_link_down_failures++; 5707 goto bxe_tx_mq_start_locked_exit; 5708 } 5709 5710 /* fetch the depth of the driver queue */ 5711 depth = drbr_inuse_drv(ifp, tx_br); 5712 if (depth > fp->eth_q_stats.tx_max_drbr_queue_depth) { 5713 fp->eth_q_stats.tx_max_drbr_queue_depth = depth; 5714 } 5715 5716 /* keep adding entries while there are frames to send */ 5717 while ((next = drbr_peek(ifp, tx_br)) != NULL) { 5718 /* handle any completions if we're running low */ 5719 tx_bd_avail = bxe_tx_avail(sc, fp); 5720 if (tx_bd_avail < BXE_TX_CLEANUP_THRESHOLD) { 5721 /* bxe_txeof will set IFF_DRV_OACTIVE appropriately */ 5722 bxe_txeof(sc, fp); 5723 tx_bd_avail = bxe_tx_avail(sc, fp); 5724 if (tx_bd_avail < (BXE_TSO_MAX_SEGMENTS + 1)) { 5725 fp->eth_q_stats.bd_avail_too_less_failures++; 5726 m_freem(next); 5727 drbr_advance(ifp, tx_br); 5728 rc = ENOBUFS; 5729 break; 5730 } 5731 } 5732 5733 /* the mbuf now belongs to us */ 5734 fp->eth_q_stats.mbuf_alloc_tx++; 5735 5736 /* 5737 * Put the frame into the transmit ring. If we don't have room, 5738 * place the mbuf back at the head of the TX queue, set the 5739 * OACTIVE flag, and wait for the NIC to drain the chain. 5740 */ 5741 rc = bxe_tx_encap(fp, &next); 5742 if (__predict_false(rc != 0)) { 5743 fp->eth_q_stats.tx_encap_failures++; 5744 if (next != NULL) { 5745 /* mark the TX queue as full and save the frame */ 5746 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 5747 drbr_putback(ifp, tx_br, next); 5748 fp->eth_q_stats.mbuf_alloc_tx--; 5749 fp->eth_q_stats.tx_frames_deferred++; 5750 } else 5751 drbr_advance(ifp, tx_br); 5752 5753 /* stop looking for more work */ 5754 break; 5755 } 5756 5757 /* the transmit frame was enqueued successfully */ 5758 tx_count++; 5759 5760 /* send a copy of the frame to any BPF listeners */ 5761 if_etherbpfmtap(ifp, next); 5762 5763 drbr_advance(ifp, tx_br); 5764 } 5765 5766 /* all TX packets were dequeued and/or the tx ring is full */ 5767 if (tx_count > 0) { 5768 /* reset the TX watchdog timeout timer */ 5769 fp->watchdog_timer = BXE_TX_TIMEOUT; 5770 } 5771 5772 bxe_tx_mq_start_locked_exit: 5773 /* If we didn't drain the drbr, enqueue a task in the future to do it. */ 5774 if (!drbr_empty(ifp, tx_br)) { 5775 fp->eth_q_stats.tx_mq_not_empty++; 5776 taskqueue_enqueue_timeout(fp->tq, &fp->tx_timeout_task, 1); 5777 } 5778 5779 return (rc); 5780 } 5781 5782 static void 5783 bxe_tx_mq_start_deferred(void *arg, 5784 int pending) 5785 { 5786 struct bxe_fastpath *fp = (struct bxe_fastpath *)arg; 5787 struct bxe_softc *sc = fp->sc; 5788 if_t ifp = sc->ifp; 5789 5790 BXE_FP_TX_LOCK(fp); 5791 bxe_tx_mq_start_locked(sc, ifp, fp, NULL); 5792 BXE_FP_TX_UNLOCK(fp); 5793 } 5794 5795 /* Multiqueue (TSS) dispatch routine. */ 5796 static int 5797 bxe_tx_mq_start(struct ifnet *ifp, 5798 struct mbuf *m) 5799 { 5800 struct bxe_softc *sc = if_getsoftc(ifp); 5801 struct bxe_fastpath *fp; 5802 int fp_index, rc; 5803 5804 fp_index = 0; /* default is the first queue */ 5805 5806 /* check if flowid is set */ 5807 5808 if (BXE_VALID_FLOWID(m)) 5809 fp_index = (m->m_pkthdr.flowid % sc->num_queues); 5810 5811 fp = &sc->fp[fp_index]; 5812 5813 if (sc->state != BXE_STATE_OPEN) { 5814 fp->eth_q_stats.bxe_tx_mq_sc_state_failures++; 5815 return ENETDOWN; 5816 } 5817 5818 if (BXE_FP_TX_TRYLOCK(fp)) { 5819 rc = bxe_tx_mq_start_locked(sc, ifp, fp, m); 5820 BXE_FP_TX_UNLOCK(fp); 5821 } else { 5822 rc = drbr_enqueue(ifp, fp->tx_br, m); 5823 taskqueue_enqueue(fp->tq, &fp->tx_task); 5824 } 5825 5826 return (rc); 5827 } 5828 5829 static void 5830 bxe_mq_flush(struct ifnet *ifp) 5831 { 5832 struct bxe_softc *sc = if_getsoftc(ifp); 5833 struct bxe_fastpath *fp; 5834 struct mbuf *m; 5835 int i; 5836 5837 for (i = 0; i < sc->num_queues; i++) { 5838 fp = &sc->fp[i]; 5839 5840 if (fp->state != BXE_FP_STATE_IRQ) { 5841 BLOGD(sc, DBG_LOAD, "Not clearing fp[%02d] buf_ring (state=%d)\n", 5842 fp->index, fp->state); 5843 continue; 5844 } 5845 5846 if (fp->tx_br != NULL) { 5847 BLOGD(sc, DBG_LOAD, "Clearing fp[%02d] buf_ring\n", fp->index); 5848 BXE_FP_TX_LOCK(fp); 5849 while ((m = buf_ring_dequeue_sc(fp->tx_br)) != NULL) { 5850 m_freem(m); 5851 } 5852 BXE_FP_TX_UNLOCK(fp); 5853 } 5854 } 5855 5856 if_qflush(ifp); 5857 } 5858 5859 #endif /* FreeBSD_version >= 901504 */ 5860 5861 static uint16_t 5862 bxe_cid_ilt_lines(struct bxe_softc *sc) 5863 { 5864 if (IS_SRIOV(sc)) { 5865 return ((BXE_FIRST_VF_CID + BXE_VF_CIDS) / ILT_PAGE_CIDS); 5866 } 5867 return (L2_ILT_LINES(sc)); 5868 } 5869 5870 static void 5871 bxe_ilt_set_info(struct bxe_softc *sc) 5872 { 5873 struct ilt_client_info *ilt_client; 5874 struct ecore_ilt *ilt = sc->ilt; 5875 uint16_t line = 0; 5876 5877 ilt->start_line = FUNC_ILT_BASE(SC_FUNC(sc)); 5878 BLOGD(sc, DBG_LOAD, "ilt starts at line %d\n", ilt->start_line); 5879 5880 /* CDU */ 5881 ilt_client = &ilt->clients[ILT_CLIENT_CDU]; 5882 ilt_client->client_num = ILT_CLIENT_CDU; 5883 ilt_client->page_size = CDU_ILT_PAGE_SZ; 5884 ilt_client->flags = ILT_CLIENT_SKIP_MEM; 5885 ilt_client->start = line; 5886 line += bxe_cid_ilt_lines(sc); 5887 5888 if (CNIC_SUPPORT(sc)) { 5889 line += CNIC_ILT_LINES; 5890 } 5891 5892 ilt_client->end = (line - 1); 5893 5894 BLOGD(sc, DBG_LOAD, 5895 "ilt client[CDU]: start %d, end %d, " 5896 "psz 0x%x, flags 0x%x, hw psz %d\n", 5897 ilt_client->start, ilt_client->end, 5898 ilt_client->page_size, 5899 ilt_client->flags, 5900 ilog2(ilt_client->page_size >> 12)); 5901 5902 /* QM */ 5903 if (QM_INIT(sc->qm_cid_count)) { 5904 ilt_client = &ilt->clients[ILT_CLIENT_QM]; 5905 ilt_client->client_num = ILT_CLIENT_QM; 5906 ilt_client->page_size = QM_ILT_PAGE_SZ; 5907 ilt_client->flags = 0; 5908 ilt_client->start = line; 5909 5910 /* 4 bytes for each cid */ 5911 line += DIV_ROUND_UP(sc->qm_cid_count * QM_QUEUES_PER_FUNC * 4, 5912 QM_ILT_PAGE_SZ); 5913 5914 ilt_client->end = (line - 1); 5915 5916 BLOGD(sc, DBG_LOAD, 5917 "ilt client[QM]: start %d, end %d, " 5918 "psz 0x%x, flags 0x%x, hw psz %d\n", 5919 ilt_client->start, ilt_client->end, 5920 ilt_client->page_size, ilt_client->flags, 5921 ilog2(ilt_client->page_size >> 12)); 5922 } 5923 5924 if (CNIC_SUPPORT(sc)) { 5925 /* SRC */ 5926 ilt_client = &ilt->clients[ILT_CLIENT_SRC]; 5927 ilt_client->client_num = ILT_CLIENT_SRC; 5928 ilt_client->page_size = SRC_ILT_PAGE_SZ; 5929 ilt_client->flags = 0; 5930 ilt_client->start = line; 5931 line += SRC_ILT_LINES; 5932 ilt_client->end = (line - 1); 5933 5934 BLOGD(sc, DBG_LOAD, 5935 "ilt client[SRC]: start %d, end %d, " 5936 "psz 0x%x, flags 0x%x, hw psz %d\n", 5937 ilt_client->start, ilt_client->end, 5938 ilt_client->page_size, ilt_client->flags, 5939 ilog2(ilt_client->page_size >> 12)); 5940 5941 /* TM */ 5942 ilt_client = &ilt->clients[ILT_CLIENT_TM]; 5943 ilt_client->client_num = ILT_CLIENT_TM; 5944 ilt_client->page_size = TM_ILT_PAGE_SZ; 5945 ilt_client->flags = 0; 5946 ilt_client->start = line; 5947 line += TM_ILT_LINES; 5948 ilt_client->end = (line - 1); 5949 5950 BLOGD(sc, DBG_LOAD, 5951 "ilt client[TM]: start %d, end %d, " 5952 "psz 0x%x, flags 0x%x, hw psz %d\n", 5953 ilt_client->start, ilt_client->end, 5954 ilt_client->page_size, ilt_client->flags, 5955 ilog2(ilt_client->page_size >> 12)); 5956 } 5957 5958 KASSERT((line <= ILT_MAX_LINES), ("Invalid number of ILT lines!")); 5959 } 5960 5961 static void 5962 bxe_set_fp_rx_buf_size(struct bxe_softc *sc) 5963 { 5964 int i; 5965 uint32_t rx_buf_size; 5966 5967 rx_buf_size = (IP_HEADER_ALIGNMENT_PADDING + ETH_OVERHEAD + sc->mtu); 5968 5969 for (i = 0; i < sc->num_queues; i++) { 5970 if(rx_buf_size <= MCLBYTES){ 5971 sc->fp[i].rx_buf_size = rx_buf_size; 5972 sc->fp[i].mbuf_alloc_size = MCLBYTES; 5973 }else if (rx_buf_size <= MJUMPAGESIZE){ 5974 sc->fp[i].rx_buf_size = rx_buf_size; 5975 sc->fp[i].mbuf_alloc_size = MJUMPAGESIZE; 5976 }else if (rx_buf_size <= (MJUMPAGESIZE + MCLBYTES)){ 5977 sc->fp[i].rx_buf_size = MCLBYTES; 5978 sc->fp[i].mbuf_alloc_size = MCLBYTES; 5979 }else if (rx_buf_size <= (2 * MJUMPAGESIZE)){ 5980 sc->fp[i].rx_buf_size = MJUMPAGESIZE; 5981 sc->fp[i].mbuf_alloc_size = MJUMPAGESIZE; 5982 }else { 5983 sc->fp[i].rx_buf_size = MCLBYTES; 5984 sc->fp[i].mbuf_alloc_size = MCLBYTES; 5985 } 5986 } 5987 } 5988 5989 static int 5990 bxe_alloc_ilt_mem(struct bxe_softc *sc) 5991 { 5992 int rc = 0; 5993 5994 if ((sc->ilt = 5995 (struct ecore_ilt *)malloc(sizeof(struct ecore_ilt), 5996 M_BXE_ILT, 5997 (M_NOWAIT | M_ZERO))) == NULL) { 5998 rc = 1; 5999 } 6000 6001 return (rc); 6002 } 6003 6004 static int 6005 bxe_alloc_ilt_lines_mem(struct bxe_softc *sc) 6006 { 6007 int rc = 0; 6008 6009 if ((sc->ilt->lines = 6010 (struct ilt_line *)malloc((sizeof(struct ilt_line) * ILT_MAX_LINES), 6011 M_BXE_ILT, 6012 (M_NOWAIT | M_ZERO))) == NULL) { 6013 rc = 1; 6014 } 6015 6016 return (rc); 6017 } 6018 6019 static void 6020 bxe_free_ilt_mem(struct bxe_softc *sc) 6021 { 6022 if (sc->ilt != NULL) { 6023 free(sc->ilt, M_BXE_ILT); 6024 sc->ilt = NULL; 6025 } 6026 } 6027 6028 static void 6029 bxe_free_ilt_lines_mem(struct bxe_softc *sc) 6030 { 6031 if (sc->ilt->lines != NULL) { 6032 free(sc->ilt->lines, M_BXE_ILT); 6033 sc->ilt->lines = NULL; 6034 } 6035 } 6036 6037 static void 6038 bxe_free_mem(struct bxe_softc *sc) 6039 { 6040 int i; 6041 6042 for (i = 0; i < L2_ILT_LINES(sc); i++) { 6043 bxe_dma_free(sc, &sc->context[i].vcxt_dma); 6044 sc->context[i].vcxt = NULL; 6045 sc->context[i].size = 0; 6046 } 6047 6048 ecore_ilt_mem_op(sc, ILT_MEMOP_FREE); 6049 6050 bxe_free_ilt_lines_mem(sc); 6051 6052 } 6053 6054 static int 6055 bxe_alloc_mem(struct bxe_softc *sc) 6056 { 6057 6058 int context_size; 6059 int allocated; 6060 int i; 6061 6062 /* 6063 * Allocate memory for CDU context: 6064 * This memory is allocated separately and not in the generic ILT 6065 * functions because CDU differs in few aspects: 6066 * 1. There can be multiple entities allocating memory for context - 6067 * regular L2, CNIC, and SRIOV drivers. Each separately controls 6068 * its own ILT lines. 6069 * 2. Since CDU page-size is not a single 4KB page (which is the case 6070 * for the other ILT clients), to be efficient we want to support 6071 * allocation of sub-page-size in the last entry. 6072 * 3. Context pointers are used by the driver to pass to FW / update 6073 * the context (for the other ILT clients the pointers are used just to 6074 * free the memory during unload). 6075 */ 6076 context_size = (sizeof(union cdu_context) * BXE_L2_CID_COUNT(sc)); 6077 for (i = 0, allocated = 0; allocated < context_size; i++) { 6078 sc->context[i].size = min(CDU_ILT_PAGE_SZ, 6079 (context_size - allocated)); 6080 6081 if (bxe_dma_alloc(sc, sc->context[i].size, 6082 &sc->context[i].vcxt_dma, 6083 "cdu context") != 0) { 6084 bxe_free_mem(sc); 6085 return (-1); 6086 } 6087 6088 sc->context[i].vcxt = 6089 (union cdu_context *)sc->context[i].vcxt_dma.vaddr; 6090 6091 allocated += sc->context[i].size; 6092 } 6093 6094 bxe_alloc_ilt_lines_mem(sc); 6095 6096 BLOGD(sc, DBG_LOAD, "ilt=%p start_line=%u lines=%p\n", 6097 sc->ilt, sc->ilt->start_line, sc->ilt->lines); 6098 { 6099 for (i = 0; i < 4; i++) { 6100 BLOGD(sc, DBG_LOAD, 6101 "c%d page_size=%u start=%u end=%u num=%u flags=0x%x\n", 6102 i, 6103 sc->ilt->clients[i].page_size, 6104 sc->ilt->clients[i].start, 6105 sc->ilt->clients[i].end, 6106 sc->ilt->clients[i].client_num, 6107 sc->ilt->clients[i].flags); 6108 } 6109 } 6110 if (ecore_ilt_mem_op(sc, ILT_MEMOP_ALLOC)) { 6111 BLOGE(sc, "ecore_ilt_mem_op ILT_MEMOP_ALLOC failed\n"); 6112 bxe_free_mem(sc); 6113 return (-1); 6114 } 6115 6116 return (0); 6117 } 6118 6119 static void 6120 bxe_free_rx_bd_chain(struct bxe_fastpath *fp) 6121 { 6122 struct bxe_softc *sc; 6123 int i; 6124 6125 sc = fp->sc; 6126 6127 if (fp->rx_mbuf_tag == NULL) { 6128 return; 6129 } 6130 6131 /* free all mbufs and unload all maps */ 6132 for (i = 0; i < RX_BD_TOTAL; i++) { 6133 if (fp->rx_mbuf_chain[i].m_map != NULL) { 6134 bus_dmamap_sync(fp->rx_mbuf_tag, 6135 fp->rx_mbuf_chain[i].m_map, 6136 BUS_DMASYNC_POSTREAD); 6137 bus_dmamap_unload(fp->rx_mbuf_tag, 6138 fp->rx_mbuf_chain[i].m_map); 6139 } 6140 6141 if (fp->rx_mbuf_chain[i].m != NULL) { 6142 m_freem(fp->rx_mbuf_chain[i].m); 6143 fp->rx_mbuf_chain[i].m = NULL; 6144 fp->eth_q_stats.mbuf_alloc_rx--; 6145 } 6146 } 6147 } 6148 6149 static void 6150 bxe_free_tpa_pool(struct bxe_fastpath *fp) 6151 { 6152 struct bxe_softc *sc; 6153 int i, max_agg_queues; 6154 6155 sc = fp->sc; 6156 6157 if (fp->rx_mbuf_tag == NULL) { 6158 return; 6159 } 6160 6161 max_agg_queues = MAX_AGG_QS(sc); 6162 6163 /* release all mbufs and unload all DMA maps in the TPA pool */ 6164 for (i = 0; i < max_agg_queues; i++) { 6165 if (fp->rx_tpa_info[i].bd.m_map != NULL) { 6166 bus_dmamap_sync(fp->rx_mbuf_tag, 6167 fp->rx_tpa_info[i].bd.m_map, 6168 BUS_DMASYNC_POSTREAD); 6169 bus_dmamap_unload(fp->rx_mbuf_tag, 6170 fp->rx_tpa_info[i].bd.m_map); 6171 } 6172 6173 if (fp->rx_tpa_info[i].bd.m != NULL) { 6174 m_freem(fp->rx_tpa_info[i].bd.m); 6175 fp->rx_tpa_info[i].bd.m = NULL; 6176 fp->eth_q_stats.mbuf_alloc_tpa--; 6177 } 6178 } 6179 } 6180 6181 static void 6182 bxe_free_sge_chain(struct bxe_fastpath *fp) 6183 { 6184 struct bxe_softc *sc; 6185 int i; 6186 6187 sc = fp->sc; 6188 6189 if (fp->rx_sge_mbuf_tag == NULL) { 6190 return; 6191 } 6192 6193 /* rree all mbufs and unload all maps */ 6194 for (i = 0; i < RX_SGE_TOTAL; i++) { 6195 if (fp->rx_sge_mbuf_chain[i].m_map != NULL) { 6196 bus_dmamap_sync(fp->rx_sge_mbuf_tag, 6197 fp->rx_sge_mbuf_chain[i].m_map, 6198 BUS_DMASYNC_POSTREAD); 6199 bus_dmamap_unload(fp->rx_sge_mbuf_tag, 6200 fp->rx_sge_mbuf_chain[i].m_map); 6201 } 6202 6203 if (fp->rx_sge_mbuf_chain[i].m != NULL) { 6204 m_freem(fp->rx_sge_mbuf_chain[i].m); 6205 fp->rx_sge_mbuf_chain[i].m = NULL; 6206 fp->eth_q_stats.mbuf_alloc_sge--; 6207 } 6208 } 6209 } 6210 6211 static void 6212 bxe_free_fp_buffers(struct bxe_softc *sc) 6213 { 6214 struct bxe_fastpath *fp; 6215 int i; 6216 6217 for (i = 0; i < sc->num_queues; i++) { 6218 fp = &sc->fp[i]; 6219 6220 #if __FreeBSD_version >= 901504 6221 if (fp->tx_br != NULL) { 6222 /* just in case bxe_mq_flush() wasn't called */ 6223 if (mtx_initialized(&fp->tx_mtx)) { 6224 struct mbuf *m; 6225 6226 BXE_FP_TX_LOCK(fp); 6227 while ((m = buf_ring_dequeue_sc(fp->tx_br)) != NULL) 6228 m_freem(m); 6229 BXE_FP_TX_UNLOCK(fp); 6230 } 6231 } 6232 #endif 6233 6234 /* free all RX buffers */ 6235 bxe_free_rx_bd_chain(fp); 6236 bxe_free_tpa_pool(fp); 6237 bxe_free_sge_chain(fp); 6238 6239 if (fp->eth_q_stats.mbuf_alloc_rx != 0) { 6240 BLOGE(sc, "failed to claim all rx mbufs (%d left)\n", 6241 fp->eth_q_stats.mbuf_alloc_rx); 6242 } 6243 6244 if (fp->eth_q_stats.mbuf_alloc_sge != 0) { 6245 BLOGE(sc, "failed to claim all sge mbufs (%d left)\n", 6246 fp->eth_q_stats.mbuf_alloc_sge); 6247 } 6248 6249 if (fp->eth_q_stats.mbuf_alloc_tpa != 0) { 6250 BLOGE(sc, "failed to claim all sge mbufs (%d left)\n", 6251 fp->eth_q_stats.mbuf_alloc_tpa); 6252 } 6253 6254 if (fp->eth_q_stats.mbuf_alloc_tx != 0) { 6255 BLOGE(sc, "failed to release tx mbufs (%d left)\n", 6256 fp->eth_q_stats.mbuf_alloc_tx); 6257 } 6258 6259 /* XXX verify all mbufs were reclaimed */ 6260 } 6261 } 6262 6263 static int 6264 bxe_alloc_rx_bd_mbuf(struct bxe_fastpath *fp, 6265 uint16_t prev_index, 6266 uint16_t index) 6267 { 6268 struct bxe_sw_rx_bd *rx_buf; 6269 struct eth_rx_bd *rx_bd; 6270 bus_dma_segment_t segs[1]; 6271 bus_dmamap_t map; 6272 struct mbuf *m; 6273 int nsegs, rc; 6274 6275 rc = 0; 6276 6277 /* allocate the new RX BD mbuf */ 6278 m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, fp->mbuf_alloc_size); 6279 if (__predict_false(m == NULL)) { 6280 fp->eth_q_stats.mbuf_rx_bd_alloc_failed++; 6281 return (ENOBUFS); 6282 } 6283 6284 fp->eth_q_stats.mbuf_alloc_rx++; 6285 6286 /* initialize the mbuf buffer length */ 6287 m->m_pkthdr.len = m->m_len = fp->rx_buf_size; 6288 6289 /* map the mbuf into non-paged pool */ 6290 rc = bus_dmamap_load_mbuf_sg(fp->rx_mbuf_tag, 6291 fp->rx_mbuf_spare_map, 6292 m, segs, &nsegs, BUS_DMA_NOWAIT); 6293 if (__predict_false(rc != 0)) { 6294 fp->eth_q_stats.mbuf_rx_bd_mapping_failed++; 6295 m_freem(m); 6296 fp->eth_q_stats.mbuf_alloc_rx--; 6297 return (rc); 6298 } 6299 6300 /* all mbufs must map to a single segment */ 6301 KASSERT((nsegs == 1), ("Too many segments, %d returned!", nsegs)); 6302 6303 /* release any existing RX BD mbuf mappings */ 6304 6305 if (prev_index != index) { 6306 rx_buf = &fp->rx_mbuf_chain[prev_index]; 6307 6308 if (rx_buf->m_map != NULL) { 6309 bus_dmamap_sync(fp->rx_mbuf_tag, rx_buf->m_map, 6310 BUS_DMASYNC_POSTREAD); 6311 bus_dmamap_unload(fp->rx_mbuf_tag, rx_buf->m_map); 6312 } 6313 6314 /* 6315 * We only get here from bxe_rxeof() when the maximum number 6316 * of rx buffers is less than RX_BD_USABLE. bxe_rxeof() already 6317 * holds the mbuf in the prev_index so it's OK to NULL it out 6318 * here without concern of a memory leak. 6319 */ 6320 fp->rx_mbuf_chain[prev_index].m = NULL; 6321 } 6322 6323 rx_buf = &fp->rx_mbuf_chain[index]; 6324 6325 if (rx_buf->m_map != NULL) { 6326 bus_dmamap_sync(fp->rx_mbuf_tag, rx_buf->m_map, 6327 BUS_DMASYNC_POSTREAD); 6328 bus_dmamap_unload(fp->rx_mbuf_tag, rx_buf->m_map); 6329 } 6330 6331 /* save the mbuf and mapping info for a future packet */ 6332 map = (prev_index != index) ? 6333 fp->rx_mbuf_chain[prev_index].m_map : rx_buf->m_map; 6334 rx_buf->m_map = fp->rx_mbuf_spare_map; 6335 fp->rx_mbuf_spare_map = map; 6336 bus_dmamap_sync(fp->rx_mbuf_tag, rx_buf->m_map, 6337 BUS_DMASYNC_PREREAD); 6338 rx_buf->m = m; 6339 6340 rx_bd = &fp->rx_chain[index]; 6341 rx_bd->addr_hi = htole32(U64_HI(segs[0].ds_addr)); 6342 rx_bd->addr_lo = htole32(U64_LO(segs[0].ds_addr)); 6343 6344 return (rc); 6345 } 6346 6347 static int 6348 bxe_alloc_rx_tpa_mbuf(struct bxe_fastpath *fp, 6349 int queue) 6350 { 6351 struct bxe_sw_tpa_info *tpa_info = &fp->rx_tpa_info[queue]; 6352 bus_dma_segment_t segs[1]; 6353 bus_dmamap_t map; 6354 struct mbuf *m; 6355 int nsegs; 6356 int rc = 0; 6357 6358 /* allocate the new TPA mbuf */ 6359 m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, fp->mbuf_alloc_size); 6360 if (__predict_false(m == NULL)) { 6361 fp->eth_q_stats.mbuf_rx_tpa_alloc_failed++; 6362 return (ENOBUFS); 6363 } 6364 6365 fp->eth_q_stats.mbuf_alloc_tpa++; 6366 6367 /* initialize the mbuf buffer length */ 6368 m->m_pkthdr.len = m->m_len = fp->rx_buf_size; 6369 6370 /* map the mbuf into non-paged pool */ 6371 rc = bus_dmamap_load_mbuf_sg(fp->rx_mbuf_tag, 6372 fp->rx_tpa_info_mbuf_spare_map, 6373 m, segs, &nsegs, BUS_DMA_NOWAIT); 6374 if (__predict_false(rc != 0)) { 6375 fp->eth_q_stats.mbuf_rx_tpa_mapping_failed++; 6376 m_free(m); 6377 fp->eth_q_stats.mbuf_alloc_tpa--; 6378 return (rc); 6379 } 6380 6381 /* all mbufs must map to a single segment */ 6382 KASSERT((nsegs == 1), ("Too many segments, %d returned!", nsegs)); 6383 6384 /* release any existing TPA mbuf mapping */ 6385 if (tpa_info->bd.m_map != NULL) { 6386 bus_dmamap_sync(fp->rx_mbuf_tag, tpa_info->bd.m_map, 6387 BUS_DMASYNC_POSTREAD); 6388 bus_dmamap_unload(fp->rx_mbuf_tag, tpa_info->bd.m_map); 6389 } 6390 6391 /* save the mbuf and mapping info for the TPA mbuf */ 6392 map = tpa_info->bd.m_map; 6393 tpa_info->bd.m_map = fp->rx_tpa_info_mbuf_spare_map; 6394 fp->rx_tpa_info_mbuf_spare_map = map; 6395 bus_dmamap_sync(fp->rx_mbuf_tag, tpa_info->bd.m_map, 6396 BUS_DMASYNC_PREREAD); 6397 tpa_info->bd.m = m; 6398 tpa_info->seg = segs[0]; 6399 6400 return (rc); 6401 } 6402 6403 /* 6404 * Allocate an mbuf and assign it to the receive scatter gather chain. The 6405 * caller must take care to save a copy of the existing mbuf in the SG mbuf 6406 * chain. 6407 */ 6408 static int 6409 bxe_alloc_rx_sge_mbuf(struct bxe_fastpath *fp, 6410 uint16_t index) 6411 { 6412 struct bxe_sw_rx_bd *sge_buf; 6413 struct eth_rx_sge *sge; 6414 bus_dma_segment_t segs[1]; 6415 bus_dmamap_t map; 6416 struct mbuf *m; 6417 int nsegs; 6418 int rc = 0; 6419 6420 /* allocate a new SGE mbuf */ 6421 m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, SGE_PAGE_SIZE); 6422 if (__predict_false(m == NULL)) { 6423 fp->eth_q_stats.mbuf_rx_sge_alloc_failed++; 6424 return (ENOMEM); 6425 } 6426 6427 fp->eth_q_stats.mbuf_alloc_sge++; 6428 6429 /* initialize the mbuf buffer length */ 6430 m->m_pkthdr.len = m->m_len = SGE_PAGE_SIZE; 6431 6432 /* map the SGE mbuf into non-paged pool */ 6433 rc = bus_dmamap_load_mbuf_sg(fp->rx_sge_mbuf_tag, 6434 fp->rx_sge_mbuf_spare_map, 6435 m, segs, &nsegs, BUS_DMA_NOWAIT); 6436 if (__predict_false(rc != 0)) { 6437 fp->eth_q_stats.mbuf_rx_sge_mapping_failed++; 6438 m_freem(m); 6439 fp->eth_q_stats.mbuf_alloc_sge--; 6440 return (rc); 6441 } 6442 6443 /* all mbufs must map to a single segment */ 6444 KASSERT((nsegs == 1), ("Too many segments, %d returned!", nsegs)); 6445 6446 sge_buf = &fp->rx_sge_mbuf_chain[index]; 6447 6448 /* release any existing SGE mbuf mapping */ 6449 if (sge_buf->m_map != NULL) { 6450 bus_dmamap_sync(fp->rx_sge_mbuf_tag, sge_buf->m_map, 6451 BUS_DMASYNC_POSTREAD); 6452 bus_dmamap_unload(fp->rx_sge_mbuf_tag, sge_buf->m_map); 6453 } 6454 6455 /* save the mbuf and mapping info for a future packet */ 6456 map = sge_buf->m_map; 6457 sge_buf->m_map = fp->rx_sge_mbuf_spare_map; 6458 fp->rx_sge_mbuf_spare_map = map; 6459 bus_dmamap_sync(fp->rx_sge_mbuf_tag, sge_buf->m_map, 6460 BUS_DMASYNC_PREREAD); 6461 sge_buf->m = m; 6462 6463 sge = &fp->rx_sge_chain[index]; 6464 sge->addr_hi = htole32(U64_HI(segs[0].ds_addr)); 6465 sge->addr_lo = htole32(U64_LO(segs[0].ds_addr)); 6466 6467 return (rc); 6468 } 6469 6470 static __noinline int 6471 bxe_alloc_fp_buffers(struct bxe_softc *sc) 6472 { 6473 struct bxe_fastpath *fp; 6474 int i, j, rc = 0; 6475 int ring_prod, cqe_ring_prod; 6476 int max_agg_queues; 6477 6478 for (i = 0; i < sc->num_queues; i++) { 6479 fp = &sc->fp[i]; 6480 6481 ring_prod = cqe_ring_prod = 0; 6482 fp->rx_bd_cons = 0; 6483 fp->rx_cq_cons = 0; 6484 6485 /* allocate buffers for the RX BDs in RX BD chain */ 6486 for (j = 0; j < sc->max_rx_bufs; j++) { 6487 rc = bxe_alloc_rx_bd_mbuf(fp, ring_prod, ring_prod); 6488 if (rc != 0) { 6489 BLOGE(sc, "mbuf alloc fail for fp[%02d] rx chain (%d)\n", 6490 i, rc); 6491 goto bxe_alloc_fp_buffers_error; 6492 } 6493 6494 ring_prod = RX_BD_NEXT(ring_prod); 6495 cqe_ring_prod = RCQ_NEXT(cqe_ring_prod); 6496 } 6497 6498 fp->rx_bd_prod = ring_prod; 6499 fp->rx_cq_prod = cqe_ring_prod; 6500 fp->eth_q_stats.rx_calls = fp->eth_q_stats.rx_pkts = 0; 6501 6502 max_agg_queues = MAX_AGG_QS(sc); 6503 6504 fp->tpa_enable = TRUE; 6505 6506 /* fill the TPA pool */ 6507 for (j = 0; j < max_agg_queues; j++) { 6508 rc = bxe_alloc_rx_tpa_mbuf(fp, j); 6509 if (rc != 0) { 6510 BLOGE(sc, "mbuf alloc fail for fp[%02d] TPA queue %d\n", 6511 i, j); 6512 fp->tpa_enable = FALSE; 6513 goto bxe_alloc_fp_buffers_error; 6514 } 6515 6516 fp->rx_tpa_info[j].state = BXE_TPA_STATE_STOP; 6517 } 6518 6519 if (fp->tpa_enable) { 6520 /* fill the RX SGE chain */ 6521 ring_prod = 0; 6522 for (j = 0; j < RX_SGE_USABLE; j++) { 6523 rc = bxe_alloc_rx_sge_mbuf(fp, ring_prod); 6524 if (rc != 0) { 6525 BLOGE(sc, "mbuf alloc fail for fp[%02d] SGE %d\n", 6526 i, ring_prod); 6527 fp->tpa_enable = FALSE; 6528 ring_prod = 0; 6529 goto bxe_alloc_fp_buffers_error; 6530 } 6531 6532 ring_prod = RX_SGE_NEXT(ring_prod); 6533 } 6534 6535 fp->rx_sge_prod = ring_prod; 6536 } 6537 } 6538 6539 return (0); 6540 6541 bxe_alloc_fp_buffers_error: 6542 6543 /* unwind what was already allocated */ 6544 bxe_free_rx_bd_chain(fp); 6545 bxe_free_tpa_pool(fp); 6546 bxe_free_sge_chain(fp); 6547 6548 return (ENOBUFS); 6549 } 6550 6551 static void 6552 bxe_free_fw_stats_mem(struct bxe_softc *sc) 6553 { 6554 bxe_dma_free(sc, &sc->fw_stats_dma); 6555 6556 sc->fw_stats_num = 0; 6557 6558 sc->fw_stats_req_size = 0; 6559 sc->fw_stats_req = NULL; 6560 sc->fw_stats_req_mapping = 0; 6561 6562 sc->fw_stats_data_size = 0; 6563 sc->fw_stats_data = NULL; 6564 sc->fw_stats_data_mapping = 0; 6565 } 6566 6567 static int 6568 bxe_alloc_fw_stats_mem(struct bxe_softc *sc) 6569 { 6570 uint8_t num_queue_stats; 6571 int num_groups; 6572 6573 /* number of queues for statistics is number of eth queues */ 6574 num_queue_stats = BXE_NUM_ETH_QUEUES(sc); 6575 6576 /* 6577 * Total number of FW statistics requests = 6578 * 1 for port stats + 1 for PF stats + num of queues 6579 */ 6580 sc->fw_stats_num = (2 + num_queue_stats); 6581 6582 /* 6583 * Request is built from stats_query_header and an array of 6584 * stats_query_cmd_group each of which contains STATS_QUERY_CMD_COUNT 6585 * rules. The real number or requests is configured in the 6586 * stats_query_header. 6587 */ 6588 num_groups = 6589 ((sc->fw_stats_num / STATS_QUERY_CMD_COUNT) + 6590 ((sc->fw_stats_num % STATS_QUERY_CMD_COUNT) ? 1 : 0)); 6591 6592 BLOGD(sc, DBG_LOAD, "stats fw_stats_num %d num_groups %d\n", 6593 sc->fw_stats_num, num_groups); 6594 6595 sc->fw_stats_req_size = 6596 (sizeof(struct stats_query_header) + 6597 (num_groups * sizeof(struct stats_query_cmd_group))); 6598 6599 /* 6600 * Data for statistics requests + stats_counter. 6601 * stats_counter holds per-STORM counters that are incremented when 6602 * STORM has finished with the current request. Memory for FCoE 6603 * offloaded statistics are counted anyway, even if they will not be sent. 6604 * VF stats are not accounted for here as the data of VF stats is stored 6605 * in memory allocated by the VF, not here. 6606 */ 6607 sc->fw_stats_data_size = 6608 (sizeof(struct stats_counter) + 6609 sizeof(struct per_port_stats) + 6610 sizeof(struct per_pf_stats) + 6611 /* sizeof(struct fcoe_statistics_params) + */ 6612 (sizeof(struct per_queue_stats) * num_queue_stats)); 6613 6614 if (bxe_dma_alloc(sc, (sc->fw_stats_req_size + sc->fw_stats_data_size), 6615 &sc->fw_stats_dma, "fw stats") != 0) { 6616 bxe_free_fw_stats_mem(sc); 6617 return (-1); 6618 } 6619 6620 /* set up the shortcuts */ 6621 6622 sc->fw_stats_req = 6623 (struct bxe_fw_stats_req *)sc->fw_stats_dma.vaddr; 6624 sc->fw_stats_req_mapping = sc->fw_stats_dma.paddr; 6625 6626 sc->fw_stats_data = 6627 (struct bxe_fw_stats_data *)((uint8_t *)sc->fw_stats_dma.vaddr + 6628 sc->fw_stats_req_size); 6629 sc->fw_stats_data_mapping = (sc->fw_stats_dma.paddr + 6630 sc->fw_stats_req_size); 6631 6632 BLOGD(sc, DBG_LOAD, "statistics request base address set to %#jx\n", 6633 (uintmax_t)sc->fw_stats_req_mapping); 6634 6635 BLOGD(sc, DBG_LOAD, "statistics data base address set to %#jx\n", 6636 (uintmax_t)sc->fw_stats_data_mapping); 6637 6638 return (0); 6639 } 6640 6641 /* 6642 * Bits map: 6643 * 0-7 - Engine0 load counter. 6644 * 8-15 - Engine1 load counter. 6645 * 16 - Engine0 RESET_IN_PROGRESS bit. 6646 * 17 - Engine1 RESET_IN_PROGRESS bit. 6647 * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active 6648 * function on the engine 6649 * 19 - Engine1 ONE_IS_LOADED. 6650 * 20 - Chip reset flow bit. When set none-leader must wait for both engines 6651 * leader to complete (check for both RESET_IN_PROGRESS bits and not 6652 * for just the one belonging to its engine). 6653 */ 6654 #define BXE_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1 6655 #define BXE_PATH0_LOAD_CNT_MASK 0x000000ff 6656 #define BXE_PATH0_LOAD_CNT_SHIFT 0 6657 #define BXE_PATH1_LOAD_CNT_MASK 0x0000ff00 6658 #define BXE_PATH1_LOAD_CNT_SHIFT 8 6659 #define BXE_PATH0_RST_IN_PROG_BIT 0x00010000 6660 #define BXE_PATH1_RST_IN_PROG_BIT 0x00020000 6661 #define BXE_GLOBAL_RESET_BIT 0x00040000 6662 6663 /* set the GLOBAL_RESET bit, should be run under rtnl lock */ 6664 static void 6665 bxe_set_reset_global(struct bxe_softc *sc) 6666 { 6667 uint32_t val; 6668 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG); 6669 val = REG_RD(sc, BXE_RECOVERY_GLOB_REG); 6670 REG_WR(sc, BXE_RECOVERY_GLOB_REG, val | BXE_GLOBAL_RESET_BIT); 6671 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG); 6672 } 6673 6674 /* clear the GLOBAL_RESET bit, should be run under rtnl lock */ 6675 static void 6676 bxe_clear_reset_global(struct bxe_softc *sc) 6677 { 6678 uint32_t val; 6679 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG); 6680 val = REG_RD(sc, BXE_RECOVERY_GLOB_REG); 6681 REG_WR(sc, BXE_RECOVERY_GLOB_REG, val & (~BXE_GLOBAL_RESET_BIT)); 6682 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG); 6683 } 6684 6685 /* checks the GLOBAL_RESET bit, should be run under rtnl lock */ 6686 static uint8_t 6687 bxe_reset_is_global(struct bxe_softc *sc) 6688 { 6689 uint32_t val = REG_RD(sc, BXE_RECOVERY_GLOB_REG); 6690 BLOGD(sc, DBG_LOAD, "GLOB_REG=0x%08x\n", val); 6691 return (val & BXE_GLOBAL_RESET_BIT) ? TRUE : FALSE; 6692 } 6693 6694 /* clear RESET_IN_PROGRESS bit for the engine, should be run under rtnl lock */ 6695 static void 6696 bxe_set_reset_done(struct bxe_softc *sc) 6697 { 6698 uint32_t val; 6699 uint32_t bit = SC_PATH(sc) ? BXE_PATH1_RST_IN_PROG_BIT : 6700 BXE_PATH0_RST_IN_PROG_BIT; 6701 6702 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG); 6703 6704 val = REG_RD(sc, BXE_RECOVERY_GLOB_REG); 6705 /* Clear the bit */ 6706 val &= ~bit; 6707 REG_WR(sc, BXE_RECOVERY_GLOB_REG, val); 6708 6709 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG); 6710 } 6711 6712 /* set RESET_IN_PROGRESS for the engine, should be run under rtnl lock */ 6713 static void 6714 bxe_set_reset_in_progress(struct bxe_softc *sc) 6715 { 6716 uint32_t val; 6717 uint32_t bit = SC_PATH(sc) ? BXE_PATH1_RST_IN_PROG_BIT : 6718 BXE_PATH0_RST_IN_PROG_BIT; 6719 6720 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG); 6721 6722 val = REG_RD(sc, BXE_RECOVERY_GLOB_REG); 6723 /* Set the bit */ 6724 val |= bit; 6725 REG_WR(sc, BXE_RECOVERY_GLOB_REG, val); 6726 6727 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG); 6728 } 6729 6730 /* check RESET_IN_PROGRESS bit for an engine, should be run under rtnl lock */ 6731 static uint8_t 6732 bxe_reset_is_done(struct bxe_softc *sc, 6733 int engine) 6734 { 6735 uint32_t val = REG_RD(sc, BXE_RECOVERY_GLOB_REG); 6736 uint32_t bit = engine ? BXE_PATH1_RST_IN_PROG_BIT : 6737 BXE_PATH0_RST_IN_PROG_BIT; 6738 6739 /* return false if bit is set */ 6740 return (val & bit) ? FALSE : TRUE; 6741 } 6742 6743 /* get the load status for an engine, should be run under rtnl lock */ 6744 static uint8_t 6745 bxe_get_load_status(struct bxe_softc *sc, 6746 int engine) 6747 { 6748 uint32_t mask = engine ? BXE_PATH1_LOAD_CNT_MASK : 6749 BXE_PATH0_LOAD_CNT_MASK; 6750 uint32_t shift = engine ? BXE_PATH1_LOAD_CNT_SHIFT : 6751 BXE_PATH0_LOAD_CNT_SHIFT; 6752 uint32_t val = REG_RD(sc, BXE_RECOVERY_GLOB_REG); 6753 6754 BLOGD(sc, DBG_LOAD, "Old value for GLOB_REG=0x%08x\n", val); 6755 6756 val = ((val & mask) >> shift); 6757 6758 BLOGD(sc, DBG_LOAD, "Load mask engine %d = 0x%08x\n", engine, val); 6759 6760 return (val != 0); 6761 } 6762 6763 /* set pf load mark */ 6764 /* XXX needs to be under rtnl lock */ 6765 static void 6766 bxe_set_pf_load(struct bxe_softc *sc) 6767 { 6768 uint32_t val; 6769 uint32_t val1; 6770 uint32_t mask = SC_PATH(sc) ? BXE_PATH1_LOAD_CNT_MASK : 6771 BXE_PATH0_LOAD_CNT_MASK; 6772 uint32_t shift = SC_PATH(sc) ? BXE_PATH1_LOAD_CNT_SHIFT : 6773 BXE_PATH0_LOAD_CNT_SHIFT; 6774 6775 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG); 6776 6777 val = REG_RD(sc, BXE_RECOVERY_GLOB_REG); 6778 BLOGD(sc, DBG_LOAD, "Old value for GLOB_REG=0x%08x\n", val); 6779 6780 /* get the current counter value */ 6781 val1 = ((val & mask) >> shift); 6782 6783 /* set bit of this PF */ 6784 val1 |= (1 << SC_ABS_FUNC(sc)); 6785 6786 /* clear the old value */ 6787 val &= ~mask; 6788 6789 /* set the new one */ 6790 val |= ((val1 << shift) & mask); 6791 6792 REG_WR(sc, BXE_RECOVERY_GLOB_REG, val); 6793 6794 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG); 6795 } 6796 6797 /* clear pf load mark */ 6798 /* XXX needs to be under rtnl lock */ 6799 static uint8_t 6800 bxe_clear_pf_load(struct bxe_softc *sc) 6801 { 6802 uint32_t val1, val; 6803 uint32_t mask = SC_PATH(sc) ? BXE_PATH1_LOAD_CNT_MASK : 6804 BXE_PATH0_LOAD_CNT_MASK; 6805 uint32_t shift = SC_PATH(sc) ? BXE_PATH1_LOAD_CNT_SHIFT : 6806 BXE_PATH0_LOAD_CNT_SHIFT; 6807 6808 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG); 6809 val = REG_RD(sc, BXE_RECOVERY_GLOB_REG); 6810 BLOGD(sc, DBG_LOAD, "Old GEN_REG_VAL=0x%08x\n", val); 6811 6812 /* get the current counter value */ 6813 val1 = (val & mask) >> shift; 6814 6815 /* clear bit of that PF */ 6816 val1 &= ~(1 << SC_ABS_FUNC(sc)); 6817 6818 /* clear the old value */ 6819 val &= ~mask; 6820 6821 /* set the new one */ 6822 val |= ((val1 << shift) & mask); 6823 6824 REG_WR(sc, BXE_RECOVERY_GLOB_REG, val); 6825 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG); 6826 return (val1 != 0); 6827 } 6828 6829 /* send load requrest to mcp and analyze response */ 6830 static int 6831 bxe_nic_load_request(struct bxe_softc *sc, 6832 uint32_t *load_code) 6833 { 6834 /* init fw_seq */ 6835 sc->fw_seq = 6836 (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_mb_header) & 6837 DRV_MSG_SEQ_NUMBER_MASK); 6838 6839 BLOGD(sc, DBG_LOAD, "initial fw_seq 0x%04x\n", sc->fw_seq); 6840 6841 /* get the current FW pulse sequence */ 6842 sc->fw_drv_pulse_wr_seq = 6843 (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_pulse_mb) & 6844 DRV_PULSE_SEQ_MASK); 6845 6846 BLOGD(sc, DBG_LOAD, "initial drv_pulse 0x%04x\n", 6847 sc->fw_drv_pulse_wr_seq); 6848 6849 /* load request */ 6850 (*load_code) = bxe_fw_command(sc, DRV_MSG_CODE_LOAD_REQ, 6851 DRV_MSG_CODE_LOAD_REQ_WITH_LFA); 6852 6853 /* if the MCP fails to respond we must abort */ 6854 if (!(*load_code)) { 6855 BLOGE(sc, "MCP response failure!\n"); 6856 return (-1); 6857 } 6858 6859 /* if MCP refused then must abort */ 6860 if ((*load_code) == FW_MSG_CODE_DRV_LOAD_REFUSED) { 6861 BLOGE(sc, "MCP refused load request\n"); 6862 return (-1); 6863 } 6864 6865 return (0); 6866 } 6867 6868 /* 6869 * Check whether another PF has already loaded FW to chip. In virtualized 6870 * environments a pf from anoth VM may have already initialized the device 6871 * including loading FW. 6872 */ 6873 static int 6874 bxe_nic_load_analyze_req(struct bxe_softc *sc, 6875 uint32_t load_code) 6876 { 6877 uint32_t my_fw, loaded_fw; 6878 6879 /* is another pf loaded on this engine? */ 6880 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) && 6881 (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) { 6882 /* build my FW version dword */ 6883 my_fw = (BCM_5710_FW_MAJOR_VERSION + 6884 (BCM_5710_FW_MINOR_VERSION << 8 ) + 6885 (BCM_5710_FW_REVISION_VERSION << 16) + 6886 (BCM_5710_FW_ENGINEERING_VERSION << 24)); 6887 6888 /* read loaded FW from chip */ 6889 loaded_fw = REG_RD(sc, XSEM_REG_PRAM); 6890 BLOGD(sc, DBG_LOAD, "loaded FW 0x%08x / my FW 0x%08x\n", 6891 loaded_fw, my_fw); 6892 6893 /* abort nic load if version mismatch */ 6894 if (my_fw != loaded_fw) { 6895 BLOGE(sc, "FW 0x%08x already loaded (mine is 0x%08x)", 6896 loaded_fw, my_fw); 6897 return (-1); 6898 } 6899 } 6900 6901 return (0); 6902 } 6903 6904 /* mark PMF if applicable */ 6905 static void 6906 bxe_nic_load_pmf(struct bxe_softc *sc, 6907 uint32_t load_code) 6908 { 6909 uint32_t ncsi_oem_data_addr; 6910 6911 if ((load_code == FW_MSG_CODE_DRV_LOAD_COMMON) || 6912 (load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) || 6913 (load_code == FW_MSG_CODE_DRV_LOAD_PORT)) { 6914 /* 6915 * Barrier here for ordering between the writing to sc->port.pmf here 6916 * and reading it from the periodic task. 6917 */ 6918 sc->port.pmf = 1; 6919 mb(); 6920 } else { 6921 sc->port.pmf = 0; 6922 } 6923 6924 BLOGD(sc, DBG_LOAD, "pmf %d\n", sc->port.pmf); 6925 6926 /* XXX needed? */ 6927 if (load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) { 6928 if (SHMEM2_HAS(sc, ncsi_oem_data_addr)) { 6929 ncsi_oem_data_addr = SHMEM2_RD(sc, ncsi_oem_data_addr); 6930 if (ncsi_oem_data_addr) { 6931 REG_WR(sc, 6932 (ncsi_oem_data_addr + 6933 offsetof(struct glob_ncsi_oem_data, driver_version)), 6934 0); 6935 } 6936 } 6937 } 6938 } 6939 6940 static void 6941 bxe_read_mf_cfg(struct bxe_softc *sc) 6942 { 6943 int n = (CHIP_IS_MODE_4_PORT(sc) ? 2 : 1); 6944 int abs_func; 6945 int vn; 6946 6947 if (BXE_NOMCP(sc)) { 6948 return; /* what should be the default bvalue in this case */ 6949 } 6950 6951 /* 6952 * The formula for computing the absolute function number is... 6953 * For 2 port configuration (4 functions per port): 6954 * abs_func = 2 * vn + SC_PORT + SC_PATH 6955 * For 4 port configuration (2 functions per port): 6956 * abs_func = 4 * vn + 2 * SC_PORT + SC_PATH 6957 */ 6958 for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) { 6959 abs_func = (n * (2 * vn + SC_PORT(sc)) + SC_PATH(sc)); 6960 if (abs_func >= E1H_FUNC_MAX) { 6961 break; 6962 } 6963 sc->devinfo.mf_info.mf_config[vn] = 6964 MFCFG_RD(sc, func_mf_config[abs_func].config); 6965 } 6966 6967 if (sc->devinfo.mf_info.mf_config[SC_VN(sc)] & 6968 FUNC_MF_CFG_FUNC_DISABLED) { 6969 BLOGD(sc, DBG_LOAD, "mf_cfg function disabled\n"); 6970 sc->flags |= BXE_MF_FUNC_DIS; 6971 } else { 6972 BLOGD(sc, DBG_LOAD, "mf_cfg function enabled\n"); 6973 sc->flags &= ~BXE_MF_FUNC_DIS; 6974 } 6975 } 6976 6977 /* acquire split MCP access lock register */ 6978 static int bxe_acquire_alr(struct bxe_softc *sc) 6979 { 6980 uint32_t j, val; 6981 6982 for (j = 0; j < 1000; j++) { 6983 val = (1UL << 31); 6984 REG_WR(sc, GRCBASE_MCP + 0x9c, val); 6985 val = REG_RD(sc, GRCBASE_MCP + 0x9c); 6986 if (val & (1L << 31)) 6987 break; 6988 6989 DELAY(5000); 6990 } 6991 6992 if (!(val & (1L << 31))) { 6993 BLOGE(sc, "Cannot acquire MCP access lock register\n"); 6994 return (-1); 6995 } 6996 6997 return (0); 6998 } 6999 7000 /* release split MCP access lock register */ 7001 static void bxe_release_alr(struct bxe_softc *sc) 7002 { 7003 REG_WR(sc, GRCBASE_MCP + 0x9c, 0); 7004 } 7005 7006 static void 7007 bxe_fan_failure(struct bxe_softc *sc) 7008 { 7009 int port = SC_PORT(sc); 7010 uint32_t ext_phy_config; 7011 7012 /* mark the failure */ 7013 ext_phy_config = 7014 SHMEM_RD(sc, dev_info.port_hw_config[port].external_phy_config); 7015 7016 ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK; 7017 ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE; 7018 SHMEM_WR(sc, dev_info.port_hw_config[port].external_phy_config, 7019 ext_phy_config); 7020 7021 /* log the failure */ 7022 BLOGW(sc, "Fan Failure has caused the driver to shutdown " 7023 "the card to prevent permanent damage. " 7024 "Please contact OEM Support for assistance\n"); 7025 7026 /* XXX */ 7027 #if 1 7028 bxe_panic(sc, ("Schedule task to handle fan failure\n")); 7029 #else 7030 /* 7031 * Schedule device reset (unload) 7032 * This is due to some boards consuming sufficient power when driver is 7033 * up to overheat if fan fails. 7034 */ 7035 bxe_set_bit(BXE_SP_RTNL_FAN_FAILURE, &sc->sp_rtnl_state); 7036 schedule_delayed_work(&sc->sp_rtnl_task, 0); 7037 #endif 7038 } 7039 7040 /* this function is called upon a link interrupt */ 7041 static void 7042 bxe_link_attn(struct bxe_softc *sc) 7043 { 7044 uint32_t pause_enabled = 0; 7045 struct host_port_stats *pstats; 7046 int cmng_fns; 7047 struct bxe_fastpath *fp; 7048 int i; 7049 7050 /* Make sure that we are synced with the current statistics */ 7051 bxe_stats_handle(sc, STATS_EVENT_STOP); 7052 BLOGD(sc, DBG_LOAD, "link_vars phy_flags : %x\n", sc->link_vars.phy_flags); 7053 elink_link_update(&sc->link_params, &sc->link_vars); 7054 7055 if (sc->link_vars.link_up) { 7056 7057 /* dropless flow control */ 7058 if (!CHIP_IS_E1(sc) && sc->dropless_fc) { 7059 pause_enabled = 0; 7060 7061 if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_TX) { 7062 pause_enabled = 1; 7063 } 7064 7065 REG_WR(sc, 7066 (BAR_USTRORM_INTMEM + 7067 USTORM_ETH_PAUSE_ENABLED_OFFSET(SC_PORT(sc))), 7068 pause_enabled); 7069 } 7070 7071 if (sc->link_vars.mac_type != ELINK_MAC_TYPE_EMAC) { 7072 pstats = BXE_SP(sc, port_stats); 7073 /* reset old mac stats */ 7074 memset(&(pstats->mac_stx[0]), 0, sizeof(struct mac_stx)); 7075 } 7076 7077 if (sc->state == BXE_STATE_OPEN) { 7078 bxe_stats_handle(sc, STATS_EVENT_LINK_UP); 7079 } 7080 7081 /* Restart tx when the link comes back. */ 7082 FOR_EACH_ETH_QUEUE(sc, i) { 7083 fp = &sc->fp[i]; 7084 taskqueue_enqueue(fp->tq, &fp->tx_task); 7085 } 7086 } 7087 7088 if (sc->link_vars.link_up && sc->link_vars.line_speed) { 7089 cmng_fns = bxe_get_cmng_fns_mode(sc); 7090 7091 if (cmng_fns != CMNG_FNS_NONE) { 7092 bxe_cmng_fns_init(sc, FALSE, cmng_fns); 7093 storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc)); 7094 } else { 7095 /* rate shaping and fairness are disabled */ 7096 BLOGD(sc, DBG_LOAD, "single function mode without fairness\n"); 7097 } 7098 } 7099 7100 bxe_link_report_locked(sc); 7101 7102 if (IS_MF(sc)) { 7103 ; // XXX bxe_link_sync_notify(sc); 7104 } 7105 } 7106 7107 static void 7108 bxe_attn_int_asserted(struct bxe_softc *sc, 7109 uint32_t asserted) 7110 { 7111 int port = SC_PORT(sc); 7112 uint32_t aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : 7113 MISC_REG_AEU_MASK_ATTN_FUNC_0; 7114 uint32_t nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 : 7115 NIG_REG_MASK_INTERRUPT_PORT0; 7116 uint32_t aeu_mask; 7117 uint32_t nig_mask = 0; 7118 uint32_t reg_addr; 7119 uint32_t igu_acked; 7120 uint32_t cnt; 7121 7122 if (sc->attn_state & asserted) { 7123 BLOGE(sc, "IGU ERROR attn=0x%08x\n", asserted); 7124 } 7125 7126 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); 7127 7128 aeu_mask = REG_RD(sc, aeu_addr); 7129 7130 BLOGD(sc, DBG_INTR, "aeu_mask 0x%08x newly asserted 0x%08x\n", 7131 aeu_mask, asserted); 7132 7133 aeu_mask &= ~(asserted & 0x3ff); 7134 7135 BLOGD(sc, DBG_INTR, "new mask 0x%08x\n", aeu_mask); 7136 7137 REG_WR(sc, aeu_addr, aeu_mask); 7138 7139 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); 7140 7141 BLOGD(sc, DBG_INTR, "attn_state 0x%08x\n", sc->attn_state); 7142 sc->attn_state |= asserted; 7143 BLOGD(sc, DBG_INTR, "new state 0x%08x\n", sc->attn_state); 7144 7145 if (asserted & ATTN_HARD_WIRED_MASK) { 7146 if (asserted & ATTN_NIG_FOR_FUNC) { 7147 7148 bxe_acquire_phy_lock(sc); 7149 /* save nig interrupt mask */ 7150 nig_mask = REG_RD(sc, nig_int_mask_addr); 7151 7152 /* If nig_mask is not set, no need to call the update function */ 7153 if (nig_mask) { 7154 REG_WR(sc, nig_int_mask_addr, 0); 7155 7156 bxe_link_attn(sc); 7157 } 7158 7159 /* handle unicore attn? */ 7160 } 7161 7162 if (asserted & ATTN_SW_TIMER_4_FUNC) { 7163 BLOGD(sc, DBG_INTR, "ATTN_SW_TIMER_4_FUNC!\n"); 7164 } 7165 7166 if (asserted & GPIO_2_FUNC) { 7167 BLOGD(sc, DBG_INTR, "GPIO_2_FUNC!\n"); 7168 } 7169 7170 if (asserted & GPIO_3_FUNC) { 7171 BLOGD(sc, DBG_INTR, "GPIO_3_FUNC!\n"); 7172 } 7173 7174 if (asserted & GPIO_4_FUNC) { 7175 BLOGD(sc, DBG_INTR, "GPIO_4_FUNC!\n"); 7176 } 7177 7178 if (port == 0) { 7179 if (asserted & ATTN_GENERAL_ATTN_1) { 7180 BLOGD(sc, DBG_INTR, "ATTN_GENERAL_ATTN_1!\n"); 7181 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_1, 0x0); 7182 } 7183 if (asserted & ATTN_GENERAL_ATTN_2) { 7184 BLOGD(sc, DBG_INTR, "ATTN_GENERAL_ATTN_2!\n"); 7185 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_2, 0x0); 7186 } 7187 if (asserted & ATTN_GENERAL_ATTN_3) { 7188 BLOGD(sc, DBG_INTR, "ATTN_GENERAL_ATTN_3!\n"); 7189 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_3, 0x0); 7190 } 7191 } else { 7192 if (asserted & ATTN_GENERAL_ATTN_4) { 7193 BLOGD(sc, DBG_INTR, "ATTN_GENERAL_ATTN_4!\n"); 7194 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_4, 0x0); 7195 } 7196 if (asserted & ATTN_GENERAL_ATTN_5) { 7197 BLOGD(sc, DBG_INTR, "ATTN_GENERAL_ATTN_5!\n"); 7198 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_5, 0x0); 7199 } 7200 if (asserted & ATTN_GENERAL_ATTN_6) { 7201 BLOGD(sc, DBG_INTR, "ATTN_GENERAL_ATTN_6!\n"); 7202 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_6, 0x0); 7203 } 7204 } 7205 } /* hardwired */ 7206 7207 if (sc->devinfo.int_block == INT_BLOCK_HC) { 7208 reg_addr = (HC_REG_COMMAND_REG + port*32 + COMMAND_REG_ATTN_BITS_SET); 7209 } else { 7210 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8); 7211 } 7212 7213 BLOGD(sc, DBG_INTR, "about to mask 0x%08x at %s addr 0x%08x\n", 7214 asserted, 7215 (sc->devinfo.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr); 7216 REG_WR(sc, reg_addr, asserted); 7217 7218 /* now set back the mask */ 7219 if (asserted & ATTN_NIG_FOR_FUNC) { 7220 /* 7221 * Verify that IGU ack through BAR was written before restoring 7222 * NIG mask. This loop should exit after 2-3 iterations max. 7223 */ 7224 if (sc->devinfo.int_block != INT_BLOCK_HC) { 7225 cnt = 0; 7226 7227 do { 7228 igu_acked = REG_RD(sc, IGU_REG_ATTENTION_ACK_BITS); 7229 } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0) && 7230 (++cnt < MAX_IGU_ATTN_ACK_TO)); 7231 7232 if (!igu_acked) { 7233 BLOGE(sc, "Failed to verify IGU ack on time\n"); 7234 } 7235 7236 mb(); 7237 } 7238 7239 REG_WR(sc, nig_int_mask_addr, nig_mask); 7240 7241 bxe_release_phy_lock(sc); 7242 } 7243 } 7244 7245 static void 7246 bxe_print_next_block(struct bxe_softc *sc, 7247 int idx, 7248 const char *blk) 7249 { 7250 BLOGI(sc, "%s%s", idx ? ", " : "", blk); 7251 } 7252 7253 static int 7254 bxe_check_blocks_with_parity0(struct bxe_softc *sc, 7255 uint32_t sig, 7256 int par_num, 7257 uint8_t print) 7258 { 7259 uint32_t cur_bit = 0; 7260 int i = 0; 7261 7262 for (i = 0; sig; i++) { 7263 cur_bit = ((uint32_t)0x1 << i); 7264 if (sig & cur_bit) { 7265 switch (cur_bit) { 7266 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR: 7267 if (print) 7268 bxe_print_next_block(sc, par_num++, "BRB"); 7269 break; 7270 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR: 7271 if (print) 7272 bxe_print_next_block(sc, par_num++, "PARSER"); 7273 break; 7274 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR: 7275 if (print) 7276 bxe_print_next_block(sc, par_num++, "TSDM"); 7277 break; 7278 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR: 7279 if (print) 7280 bxe_print_next_block(sc, par_num++, "SEARCHER"); 7281 break; 7282 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR: 7283 if (print) 7284 bxe_print_next_block(sc, par_num++, "TCM"); 7285 break; 7286 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR: 7287 if (print) 7288 bxe_print_next_block(sc, par_num++, "TSEMI"); 7289 break; 7290 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR: 7291 if (print) 7292 bxe_print_next_block(sc, par_num++, "XPB"); 7293 break; 7294 } 7295 7296 /* Clear the bit */ 7297 sig &= ~cur_bit; 7298 } 7299 } 7300 7301 return (par_num); 7302 } 7303 7304 static int 7305 bxe_check_blocks_with_parity1(struct bxe_softc *sc, 7306 uint32_t sig, 7307 int par_num, 7308 uint8_t *global, 7309 uint8_t print) 7310 { 7311 int i = 0; 7312 uint32_t cur_bit = 0; 7313 for (i = 0; sig; i++) { 7314 cur_bit = ((uint32_t)0x1 << i); 7315 if (sig & cur_bit) { 7316 switch (cur_bit) { 7317 case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR: 7318 if (print) 7319 bxe_print_next_block(sc, par_num++, "PBF"); 7320 break; 7321 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR: 7322 if (print) 7323 bxe_print_next_block(sc, par_num++, "QM"); 7324 break; 7325 case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR: 7326 if (print) 7327 bxe_print_next_block(sc, par_num++, "TM"); 7328 break; 7329 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR: 7330 if (print) 7331 bxe_print_next_block(sc, par_num++, "XSDM"); 7332 break; 7333 case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR: 7334 if (print) 7335 bxe_print_next_block(sc, par_num++, "XCM"); 7336 break; 7337 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR: 7338 if (print) 7339 bxe_print_next_block(sc, par_num++, "XSEMI"); 7340 break; 7341 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR: 7342 if (print) 7343 bxe_print_next_block(sc, par_num++, "DOORBELLQ"); 7344 break; 7345 case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR: 7346 if (print) 7347 bxe_print_next_block(sc, par_num++, "NIG"); 7348 break; 7349 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR: 7350 if (print) 7351 bxe_print_next_block(sc, par_num++, "VAUX PCI CORE"); 7352 *global = TRUE; 7353 break; 7354 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR: 7355 if (print) 7356 bxe_print_next_block(sc, par_num++, "DEBUG"); 7357 break; 7358 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR: 7359 if (print) 7360 bxe_print_next_block(sc, par_num++, "USDM"); 7361 break; 7362 case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR: 7363 if (print) 7364 bxe_print_next_block(sc, par_num++, "UCM"); 7365 break; 7366 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR: 7367 if (print) 7368 bxe_print_next_block(sc, par_num++, "USEMI"); 7369 break; 7370 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR: 7371 if (print) 7372 bxe_print_next_block(sc, par_num++, "UPB"); 7373 break; 7374 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR: 7375 if (print) 7376 bxe_print_next_block(sc, par_num++, "CSDM"); 7377 break; 7378 case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR: 7379 if (print) 7380 bxe_print_next_block(sc, par_num++, "CCM"); 7381 break; 7382 } 7383 7384 /* Clear the bit */ 7385 sig &= ~cur_bit; 7386 } 7387 } 7388 7389 return (par_num); 7390 } 7391 7392 static int 7393 bxe_check_blocks_with_parity2(struct bxe_softc *sc, 7394 uint32_t sig, 7395 int par_num, 7396 uint8_t print) 7397 { 7398 uint32_t cur_bit = 0; 7399 int i = 0; 7400 7401 for (i = 0; sig; i++) { 7402 cur_bit = ((uint32_t)0x1 << i); 7403 if (sig & cur_bit) { 7404 switch (cur_bit) { 7405 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR: 7406 if (print) 7407 bxe_print_next_block(sc, par_num++, "CSEMI"); 7408 break; 7409 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR: 7410 if (print) 7411 bxe_print_next_block(sc, par_num++, "PXP"); 7412 break; 7413 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR: 7414 if (print) 7415 bxe_print_next_block(sc, par_num++, "PXPPCICLOCKCLIENT"); 7416 break; 7417 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR: 7418 if (print) 7419 bxe_print_next_block(sc, par_num++, "CFC"); 7420 break; 7421 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR: 7422 if (print) 7423 bxe_print_next_block(sc, par_num++, "CDU"); 7424 break; 7425 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR: 7426 if (print) 7427 bxe_print_next_block(sc, par_num++, "DMAE"); 7428 break; 7429 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR: 7430 if (print) 7431 bxe_print_next_block(sc, par_num++, "IGU"); 7432 break; 7433 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR: 7434 if (print) 7435 bxe_print_next_block(sc, par_num++, "MISC"); 7436 break; 7437 } 7438 7439 /* Clear the bit */ 7440 sig &= ~cur_bit; 7441 } 7442 } 7443 7444 return (par_num); 7445 } 7446 7447 static int 7448 bxe_check_blocks_with_parity3(struct bxe_softc *sc, 7449 uint32_t sig, 7450 int par_num, 7451 uint8_t *global, 7452 uint8_t print) 7453 { 7454 uint32_t cur_bit = 0; 7455 int i = 0; 7456 7457 for (i = 0; sig; i++) { 7458 cur_bit = ((uint32_t)0x1 << i); 7459 if (sig & cur_bit) { 7460 switch (cur_bit) { 7461 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY: 7462 if (print) 7463 bxe_print_next_block(sc, par_num++, "MCP ROM"); 7464 *global = TRUE; 7465 break; 7466 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY: 7467 if (print) 7468 bxe_print_next_block(sc, par_num++, 7469 "MCP UMP RX"); 7470 *global = TRUE; 7471 break; 7472 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY: 7473 if (print) 7474 bxe_print_next_block(sc, par_num++, 7475 "MCP UMP TX"); 7476 *global = TRUE; 7477 break; 7478 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY: 7479 if (print) 7480 bxe_print_next_block(sc, par_num++, 7481 "MCP SCPAD"); 7482 *global = TRUE; 7483 break; 7484 } 7485 7486 /* Clear the bit */ 7487 sig &= ~cur_bit; 7488 } 7489 } 7490 7491 return (par_num); 7492 } 7493 7494 static int 7495 bxe_check_blocks_with_parity4(struct bxe_softc *sc, 7496 uint32_t sig, 7497 int par_num, 7498 uint8_t print) 7499 { 7500 uint32_t cur_bit = 0; 7501 int i = 0; 7502 7503 for (i = 0; sig; i++) { 7504 cur_bit = ((uint32_t)0x1 << i); 7505 if (sig & cur_bit) { 7506 switch (cur_bit) { 7507 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR: 7508 if (print) 7509 bxe_print_next_block(sc, par_num++, "PGLUE_B"); 7510 break; 7511 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR: 7512 if (print) 7513 bxe_print_next_block(sc, par_num++, "ATC"); 7514 break; 7515 } 7516 7517 /* Clear the bit */ 7518 sig &= ~cur_bit; 7519 } 7520 } 7521 7522 return (par_num); 7523 } 7524 7525 static uint8_t 7526 bxe_parity_attn(struct bxe_softc *sc, 7527 uint8_t *global, 7528 uint8_t print, 7529 uint32_t *sig) 7530 { 7531 int par_num = 0; 7532 7533 if ((sig[0] & HW_PRTY_ASSERT_SET_0) || 7534 (sig[1] & HW_PRTY_ASSERT_SET_1) || 7535 (sig[2] & HW_PRTY_ASSERT_SET_2) || 7536 (sig[3] & HW_PRTY_ASSERT_SET_3) || 7537 (sig[4] & HW_PRTY_ASSERT_SET_4)) { 7538 BLOGE(sc, "Parity error: HW block parity attention:\n" 7539 "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x\n", 7540 (uint32_t)(sig[0] & HW_PRTY_ASSERT_SET_0), 7541 (uint32_t)(sig[1] & HW_PRTY_ASSERT_SET_1), 7542 (uint32_t)(sig[2] & HW_PRTY_ASSERT_SET_2), 7543 (uint32_t)(sig[3] & HW_PRTY_ASSERT_SET_3), 7544 (uint32_t)(sig[4] & HW_PRTY_ASSERT_SET_4)); 7545 7546 if (print) 7547 BLOGI(sc, "Parity errors detected in blocks: "); 7548 7549 par_num = 7550 bxe_check_blocks_with_parity0(sc, sig[0] & 7551 HW_PRTY_ASSERT_SET_0, 7552 par_num, print); 7553 par_num = 7554 bxe_check_blocks_with_parity1(sc, sig[1] & 7555 HW_PRTY_ASSERT_SET_1, 7556 par_num, global, print); 7557 par_num = 7558 bxe_check_blocks_with_parity2(sc, sig[2] & 7559 HW_PRTY_ASSERT_SET_2, 7560 par_num, print); 7561 par_num = 7562 bxe_check_blocks_with_parity3(sc, sig[3] & 7563 HW_PRTY_ASSERT_SET_3, 7564 par_num, global, print); 7565 par_num = 7566 bxe_check_blocks_with_parity4(sc, sig[4] & 7567 HW_PRTY_ASSERT_SET_4, 7568 par_num, print); 7569 7570 if (print) 7571 BLOGI(sc, "\n"); 7572 7573 return (TRUE); 7574 } 7575 7576 return (FALSE); 7577 } 7578 7579 static uint8_t 7580 bxe_chk_parity_attn(struct bxe_softc *sc, 7581 uint8_t *global, 7582 uint8_t print) 7583 { 7584 struct attn_route attn = { {0} }; 7585 int port = SC_PORT(sc); 7586 7587 attn.sig[0] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4); 7588 attn.sig[1] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4); 7589 attn.sig[2] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4); 7590 attn.sig[3] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4); 7591 7592 /* 7593 * Since MCP attentions can't be disabled inside the block, we need to 7594 * read AEU registers to see whether they're currently disabled 7595 */ 7596 attn.sig[3] &= ((REG_RD(sc, (!port ? MISC_REG_AEU_ENABLE4_FUNC_0_OUT_0 7597 : MISC_REG_AEU_ENABLE4_FUNC_1_OUT_0)) & 7598 MISC_AEU_ENABLE_MCP_PRTY_BITS) | 7599 ~MISC_AEU_ENABLE_MCP_PRTY_BITS); 7600 7601 7602 if (!CHIP_IS_E1x(sc)) 7603 attn.sig[4] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4); 7604 7605 return (bxe_parity_attn(sc, global, print, attn.sig)); 7606 } 7607 7608 static void 7609 bxe_attn_int_deasserted4(struct bxe_softc *sc, 7610 uint32_t attn) 7611 { 7612 uint32_t val; 7613 7614 if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) { 7615 val = REG_RD(sc, PGLUE_B_REG_PGLUE_B_INT_STS_CLR); 7616 BLOGE(sc, "PGLUE hw attention 0x%08x\n", val); 7617 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR) 7618 BLOGE(sc, "PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR\n"); 7619 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR) 7620 BLOGE(sc, "PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR\n"); 7621 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) 7622 BLOGE(sc, "PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN\n"); 7623 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN) 7624 BLOGE(sc, "PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN\n"); 7625 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN) 7626 BLOGE(sc, "PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN\n"); 7627 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN) 7628 BLOGE(sc, "PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN\n"); 7629 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN) 7630 BLOGE(sc, "PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN\n"); 7631 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN) 7632 BLOGE(sc, "PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN\n"); 7633 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW) 7634 BLOGE(sc, "PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW\n"); 7635 } 7636 7637 if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) { 7638 val = REG_RD(sc, ATC_REG_ATC_INT_STS_CLR); 7639 BLOGE(sc, "ATC hw attention 0x%08x\n", val); 7640 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR) 7641 BLOGE(sc, "ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n"); 7642 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND) 7643 BLOGE(sc, "ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND\n"); 7644 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS) 7645 BLOGE(sc, "ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS\n"); 7646 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT) 7647 BLOGE(sc, "ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT\n"); 7648 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR) 7649 BLOGE(sc, "ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n"); 7650 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU) 7651 BLOGE(sc, "ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU\n"); 7652 } 7653 7654 if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | 7655 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) { 7656 BLOGE(sc, "FATAL parity attention set4 0x%08x\n", 7657 (uint32_t)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | 7658 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR))); 7659 } 7660 } 7661 7662 static void 7663 bxe_e1h_disable(struct bxe_softc *sc) 7664 { 7665 int port = SC_PORT(sc); 7666 7667 bxe_tx_disable(sc); 7668 7669 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port*8, 0); 7670 } 7671 7672 static void 7673 bxe_e1h_enable(struct bxe_softc *sc) 7674 { 7675 int port = SC_PORT(sc); 7676 7677 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port*8, 1); 7678 7679 // XXX bxe_tx_enable(sc); 7680 } 7681 7682 /* 7683 * called due to MCP event (on pmf): 7684 * reread new bandwidth configuration 7685 * configure FW 7686 * notify others function about the change 7687 */ 7688 static void 7689 bxe_config_mf_bw(struct bxe_softc *sc) 7690 { 7691 if (sc->link_vars.link_up) { 7692 bxe_cmng_fns_init(sc, TRUE, CMNG_FNS_MINMAX); 7693 // XXX bxe_link_sync_notify(sc); 7694 } 7695 7696 storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc)); 7697 } 7698 7699 static void 7700 bxe_set_mf_bw(struct bxe_softc *sc) 7701 { 7702 bxe_config_mf_bw(sc); 7703 bxe_fw_command(sc, DRV_MSG_CODE_SET_MF_BW_ACK, 0); 7704 } 7705 7706 static void 7707 bxe_handle_eee_event(struct bxe_softc *sc) 7708 { 7709 BLOGD(sc, DBG_INTR, "EEE - LLDP event\n"); 7710 bxe_fw_command(sc, DRV_MSG_CODE_EEE_RESULTS_ACK, 0); 7711 } 7712 7713 #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3 7714 7715 static void 7716 bxe_drv_info_ether_stat(struct bxe_softc *sc) 7717 { 7718 struct eth_stats_info *ether_stat = 7719 &sc->sp->drv_info_to_mcp.ether_stat; 7720 7721 strlcpy(ether_stat->version, BXE_DRIVER_VERSION, 7722 ETH_STAT_INFO_VERSION_LEN); 7723 7724 /* XXX (+ MAC_PAD) taken from other driver... verify this is right */ 7725 sc->sp_objs[0].mac_obj.get_n_elements(sc, &sc->sp_objs[0].mac_obj, 7726 DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED, 7727 ether_stat->mac_local + MAC_PAD, 7728 MAC_PAD, ETH_ALEN); 7729 7730 ether_stat->mtu_size = sc->mtu; 7731 7732 ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK; 7733 if (if_getcapenable(sc->ifp) & (IFCAP_TSO4 | IFCAP_TSO6)) { 7734 ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK; 7735 } 7736 7737 // XXX ether_stat->feature_flags |= ???; 7738 7739 ether_stat->promiscuous_mode = 0; // (flags & PROMISC) ? 1 : 0; 7740 7741 ether_stat->txq_size = sc->tx_ring_size; 7742 ether_stat->rxq_size = sc->rx_ring_size; 7743 } 7744 7745 static void 7746 bxe_handle_drv_info_req(struct bxe_softc *sc) 7747 { 7748 enum drv_info_opcode op_code; 7749 uint32_t drv_info_ctl = SHMEM2_RD(sc, drv_info_control); 7750 7751 /* if drv_info version supported by MFW doesn't match - send NACK */ 7752 if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) { 7753 bxe_fw_command(sc, DRV_MSG_CODE_DRV_INFO_NACK, 0); 7754 return; 7755 } 7756 7757 op_code = ((drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >> 7758 DRV_INFO_CONTROL_OP_CODE_SHIFT); 7759 7760 memset(&sc->sp->drv_info_to_mcp, 0, sizeof(union drv_info_to_mcp)); 7761 7762 switch (op_code) { 7763 case ETH_STATS_OPCODE: 7764 bxe_drv_info_ether_stat(sc); 7765 break; 7766 case FCOE_STATS_OPCODE: 7767 case ISCSI_STATS_OPCODE: 7768 default: 7769 /* if op code isn't supported - send NACK */ 7770 bxe_fw_command(sc, DRV_MSG_CODE_DRV_INFO_NACK, 0); 7771 return; 7772 } 7773 7774 /* 7775 * If we got drv_info attn from MFW then these fields are defined in 7776 * shmem2 for sure 7777 */ 7778 SHMEM2_WR(sc, drv_info_host_addr_lo, 7779 U64_LO(BXE_SP_MAPPING(sc, drv_info_to_mcp))); 7780 SHMEM2_WR(sc, drv_info_host_addr_hi, 7781 U64_HI(BXE_SP_MAPPING(sc, drv_info_to_mcp))); 7782 7783 bxe_fw_command(sc, DRV_MSG_CODE_DRV_INFO_ACK, 0); 7784 } 7785 7786 static void 7787 bxe_dcc_event(struct bxe_softc *sc, 7788 uint32_t dcc_event) 7789 { 7790 BLOGD(sc, DBG_INTR, "dcc_event 0x%08x\n", dcc_event); 7791 7792 if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) { 7793 /* 7794 * This is the only place besides the function initialization 7795 * where the sc->flags can change so it is done without any 7796 * locks 7797 */ 7798 if (sc->devinfo.mf_info.mf_config[SC_VN(sc)] & FUNC_MF_CFG_FUNC_DISABLED) { 7799 BLOGD(sc, DBG_INTR, "mf_cfg function disabled\n"); 7800 sc->flags |= BXE_MF_FUNC_DIS; 7801 bxe_e1h_disable(sc); 7802 } else { 7803 BLOGD(sc, DBG_INTR, "mf_cfg function enabled\n"); 7804 sc->flags &= ~BXE_MF_FUNC_DIS; 7805 bxe_e1h_enable(sc); 7806 } 7807 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF; 7808 } 7809 7810 if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) { 7811 bxe_config_mf_bw(sc); 7812 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION; 7813 } 7814 7815 /* Report results to MCP */ 7816 if (dcc_event) 7817 bxe_fw_command(sc, DRV_MSG_CODE_DCC_FAILURE, 0); 7818 else 7819 bxe_fw_command(sc, DRV_MSG_CODE_DCC_OK, 0); 7820 } 7821 7822 static void 7823 bxe_pmf_update(struct bxe_softc *sc) 7824 { 7825 int port = SC_PORT(sc); 7826 uint32_t val; 7827 7828 sc->port.pmf = 1; 7829 BLOGD(sc, DBG_INTR, "pmf %d\n", sc->port.pmf); 7830 7831 /* 7832 * We need the mb() to ensure the ordering between the writing to 7833 * sc->port.pmf here and reading it from the bxe_periodic_task(). 7834 */ 7835 mb(); 7836 7837 /* queue a periodic task */ 7838 // XXX schedule task... 7839 7840 // XXX bxe_dcbx_pmf_update(sc); 7841 7842 /* enable nig attention */ 7843 val = (0xff0f | (1 << (SC_VN(sc) + 4))); 7844 if (sc->devinfo.int_block == INT_BLOCK_HC) { 7845 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port*8, val); 7846 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port*8, val); 7847 } else if (!CHIP_IS_E1x(sc)) { 7848 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, val); 7849 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, val); 7850 } 7851 7852 bxe_stats_handle(sc, STATS_EVENT_PMF); 7853 } 7854 7855 static int 7856 bxe_mc_assert(struct bxe_softc *sc) 7857 { 7858 char last_idx; 7859 int i, rc = 0; 7860 uint32_t row0, row1, row2, row3; 7861 7862 /* XSTORM */ 7863 last_idx = REG_RD8(sc, BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_INDEX_OFFSET); 7864 if (last_idx) 7865 BLOGE(sc, "XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); 7866 7867 /* print the asserts */ 7868 for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) { 7869 7870 row0 = REG_RD(sc, BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i)); 7871 row1 = REG_RD(sc, BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) + 4); 7872 row2 = REG_RD(sc, BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) + 8); 7873 row3 = REG_RD(sc, BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) + 12); 7874 7875 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { 7876 BLOGE(sc, "XSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n", 7877 i, row3, row2, row1, row0); 7878 rc++; 7879 } else { 7880 break; 7881 } 7882 } 7883 7884 /* TSTORM */ 7885 last_idx = REG_RD8(sc, BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_INDEX_OFFSET); 7886 if (last_idx) { 7887 BLOGE(sc, "TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); 7888 } 7889 7890 /* print the asserts */ 7891 for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) { 7892 7893 row0 = REG_RD(sc, BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i)); 7894 row1 = REG_RD(sc, BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) + 4); 7895 row2 = REG_RD(sc, BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) + 8); 7896 row3 = REG_RD(sc, BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) + 12); 7897 7898 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { 7899 BLOGE(sc, "TSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n", 7900 i, row3, row2, row1, row0); 7901 rc++; 7902 } else { 7903 break; 7904 } 7905 } 7906 7907 /* CSTORM */ 7908 last_idx = REG_RD8(sc, BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_INDEX_OFFSET); 7909 if (last_idx) { 7910 BLOGE(sc, "CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); 7911 } 7912 7913 /* print the asserts */ 7914 for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) { 7915 7916 row0 = REG_RD(sc, BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i)); 7917 row1 = REG_RD(sc, BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) + 4); 7918 row2 = REG_RD(sc, BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) + 8); 7919 row3 = REG_RD(sc, BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) + 12); 7920 7921 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { 7922 BLOGE(sc, "CSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n", 7923 i, row3, row2, row1, row0); 7924 rc++; 7925 } else { 7926 break; 7927 } 7928 } 7929 7930 /* USTORM */ 7931 last_idx = REG_RD8(sc, BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_INDEX_OFFSET); 7932 if (last_idx) { 7933 BLOGE(sc, "USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); 7934 } 7935 7936 /* print the asserts */ 7937 for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) { 7938 7939 row0 = REG_RD(sc, BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i)); 7940 row1 = REG_RD(sc, BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) + 4); 7941 row2 = REG_RD(sc, BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) + 8); 7942 row3 = REG_RD(sc, BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) + 12); 7943 7944 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { 7945 BLOGE(sc, "USTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n", 7946 i, row3, row2, row1, row0); 7947 rc++; 7948 } else { 7949 break; 7950 } 7951 } 7952 7953 return (rc); 7954 } 7955 7956 static void 7957 bxe_attn_int_deasserted3(struct bxe_softc *sc, 7958 uint32_t attn) 7959 { 7960 int func = SC_FUNC(sc); 7961 uint32_t val; 7962 7963 if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) { 7964 7965 if (attn & BXE_PMF_LINK_ASSERT(sc)) { 7966 7967 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); 7968 bxe_read_mf_cfg(sc); 7969 sc->devinfo.mf_info.mf_config[SC_VN(sc)] = 7970 MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].config); 7971 val = SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_status); 7972 7973 if (val & DRV_STATUS_DCC_EVENT_MASK) 7974 bxe_dcc_event(sc, (val & DRV_STATUS_DCC_EVENT_MASK)); 7975 7976 if (val & DRV_STATUS_SET_MF_BW) 7977 bxe_set_mf_bw(sc); 7978 7979 if (val & DRV_STATUS_DRV_INFO_REQ) 7980 bxe_handle_drv_info_req(sc); 7981 7982 if ((sc->port.pmf == 0) && (val & DRV_STATUS_PMF)) 7983 bxe_pmf_update(sc); 7984 7985 if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS) 7986 bxe_handle_eee_event(sc); 7987 7988 if (sc->link_vars.periodic_flags & 7989 ELINK_PERIODIC_FLAGS_LINK_EVENT) { 7990 /* sync with link */ 7991 bxe_acquire_phy_lock(sc); 7992 sc->link_vars.periodic_flags &= 7993 ~ELINK_PERIODIC_FLAGS_LINK_EVENT; 7994 bxe_release_phy_lock(sc); 7995 if (IS_MF(sc)) 7996 ; // XXX bxe_link_sync_notify(sc); 7997 bxe_link_report(sc); 7998 } 7999 8000 /* 8001 * Always call it here: bxe_link_report() will 8002 * prevent the link indication duplication. 8003 */ 8004 bxe_link_status_update(sc); 8005 8006 } else if (attn & BXE_MC_ASSERT_BITS) { 8007 8008 BLOGE(sc, "MC assert!\n"); 8009 bxe_mc_assert(sc); 8010 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_10, 0); 8011 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_9, 0); 8012 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_8, 0); 8013 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_7, 0); 8014 bxe_panic(sc, ("MC assert!\n")); 8015 8016 } else if (attn & BXE_MCP_ASSERT) { 8017 8018 BLOGE(sc, "MCP assert!\n"); 8019 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_11, 0); 8020 // XXX bxe_fw_dump(sc); 8021 8022 } else { 8023 BLOGE(sc, "Unknown HW assert! (attn 0x%08x)\n", attn); 8024 } 8025 } 8026 8027 if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) { 8028 BLOGE(sc, "LATCHED attention 0x%08x (masked)\n", attn); 8029 if (attn & BXE_GRC_TIMEOUT) { 8030 val = CHIP_IS_E1(sc) ? 0 : REG_RD(sc, MISC_REG_GRC_TIMEOUT_ATTN); 8031 BLOGE(sc, "GRC time-out 0x%08x\n", val); 8032 } 8033 if (attn & BXE_GRC_RSV) { 8034 val = CHIP_IS_E1(sc) ? 0 : REG_RD(sc, MISC_REG_GRC_RSV_ATTN); 8035 BLOGE(sc, "GRC reserved 0x%08x\n", val); 8036 } 8037 REG_WR(sc, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff); 8038 } 8039 } 8040 8041 static void 8042 bxe_attn_int_deasserted2(struct bxe_softc *sc, 8043 uint32_t attn) 8044 { 8045 int port = SC_PORT(sc); 8046 int reg_offset; 8047 uint32_t val0, mask0, val1, mask1; 8048 uint32_t val; 8049 8050 if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) { 8051 val = REG_RD(sc, CFC_REG_CFC_INT_STS_CLR); 8052 BLOGE(sc, "CFC hw attention 0x%08x\n", val); 8053 /* CFC error attention */ 8054 if (val & 0x2) { 8055 BLOGE(sc, "FATAL error from CFC\n"); 8056 } 8057 } 8058 8059 if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) { 8060 val = REG_RD(sc, PXP_REG_PXP_INT_STS_CLR_0); 8061 BLOGE(sc, "PXP hw attention-0 0x%08x\n", val); 8062 /* RQ_USDMDP_FIFO_OVERFLOW */ 8063 if (val & 0x18000) { 8064 BLOGE(sc, "FATAL error from PXP\n"); 8065 } 8066 8067 if (!CHIP_IS_E1x(sc)) { 8068 val = REG_RD(sc, PXP_REG_PXP_INT_STS_CLR_1); 8069 BLOGE(sc, "PXP hw attention-1 0x%08x\n", val); 8070 } 8071 } 8072 8073 #define PXP2_EOP_ERROR_BIT PXP2_PXP2_INT_STS_CLR_0_REG_WR_PGLUE_EOP_ERROR 8074 #define AEU_PXP2_HW_INT_BIT AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT 8075 8076 if (attn & AEU_PXP2_HW_INT_BIT) { 8077 /* CQ47854 workaround do not panic on 8078 * PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR 8079 */ 8080 if (!CHIP_IS_E1x(sc)) { 8081 mask0 = REG_RD(sc, PXP2_REG_PXP2_INT_MASK_0); 8082 val1 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_1); 8083 mask1 = REG_RD(sc, PXP2_REG_PXP2_INT_MASK_1); 8084 val0 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_0); 8085 /* 8086 * If the only PXP2_EOP_ERROR_BIT is set in 8087 * STS0 and STS1 - clear it 8088 * 8089 * probably we lose additional attentions between 8090 * STS0 and STS_CLR0, in this case user will not 8091 * be notified about them 8092 */ 8093 if (val0 & mask0 & PXP2_EOP_ERROR_BIT && 8094 !(val1 & mask1)) 8095 val0 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_CLR_0); 8096 8097 /* print the register, since no one can restore it */ 8098 BLOGE(sc, "PXP2_REG_PXP2_INT_STS_CLR_0 0x%08x\n", val0); 8099 8100 /* 8101 * if PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR 8102 * then notify 8103 */ 8104 if (val0 & PXP2_EOP_ERROR_BIT) { 8105 BLOGE(sc, "PXP2_WR_PGLUE_EOP_ERROR\n"); 8106 8107 /* 8108 * if only PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR is 8109 * set then clear attention from PXP2 block without panic 8110 */ 8111 if (((val0 & mask0) == PXP2_EOP_ERROR_BIT) && 8112 ((val1 & mask1) == 0)) 8113 attn &= ~AEU_PXP2_HW_INT_BIT; 8114 } 8115 } 8116 } 8117 8118 if (attn & HW_INTERRUT_ASSERT_SET_2) { 8119 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 : 8120 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2); 8121 8122 val = REG_RD(sc, reg_offset); 8123 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2); 8124 REG_WR(sc, reg_offset, val); 8125 8126 BLOGE(sc, "FATAL HW block attention set2 0x%x\n", 8127 (uint32_t)(attn & HW_INTERRUT_ASSERT_SET_2)); 8128 bxe_panic(sc, ("HW block attention set2\n")); 8129 } 8130 } 8131 8132 static void 8133 bxe_attn_int_deasserted1(struct bxe_softc *sc, 8134 uint32_t attn) 8135 { 8136 int port = SC_PORT(sc); 8137 int reg_offset; 8138 uint32_t val; 8139 8140 if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) { 8141 val = REG_RD(sc, DORQ_REG_DORQ_INT_STS_CLR); 8142 BLOGE(sc, "DB hw attention 0x%08x\n", val); 8143 /* DORQ discard attention */ 8144 if (val & 0x2) { 8145 BLOGE(sc, "FATAL error from DORQ\n"); 8146 } 8147 } 8148 8149 if (attn & HW_INTERRUT_ASSERT_SET_1) { 8150 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 : 8151 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1); 8152 8153 val = REG_RD(sc, reg_offset); 8154 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1); 8155 REG_WR(sc, reg_offset, val); 8156 8157 BLOGE(sc, "FATAL HW block attention set1 0x%08x\n", 8158 (uint32_t)(attn & HW_INTERRUT_ASSERT_SET_1)); 8159 bxe_panic(sc, ("HW block attention set1\n")); 8160 } 8161 } 8162 8163 static void 8164 bxe_attn_int_deasserted0(struct bxe_softc *sc, 8165 uint32_t attn) 8166 { 8167 int port = SC_PORT(sc); 8168 int reg_offset; 8169 uint32_t val; 8170 8171 reg_offset = (port) ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : 8172 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0; 8173 8174 if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) { 8175 val = REG_RD(sc, reg_offset); 8176 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5; 8177 REG_WR(sc, reg_offset, val); 8178 8179 BLOGW(sc, "SPIO5 hw attention\n"); 8180 8181 /* Fan failure attention */ 8182 elink_hw_reset_phy(&sc->link_params); 8183 bxe_fan_failure(sc); 8184 } 8185 8186 if ((attn & sc->link_vars.aeu_int_mask) && sc->port.pmf) { 8187 bxe_acquire_phy_lock(sc); 8188 elink_handle_module_detect_int(&sc->link_params); 8189 bxe_release_phy_lock(sc); 8190 } 8191 8192 if (attn & HW_INTERRUT_ASSERT_SET_0) { 8193 val = REG_RD(sc, reg_offset); 8194 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0); 8195 REG_WR(sc, reg_offset, val); 8196 8197 bxe_panic(sc, ("FATAL HW block attention set0 0x%lx\n", 8198 (attn & HW_INTERRUT_ASSERT_SET_0))); 8199 } 8200 } 8201 8202 static void 8203 bxe_attn_int_deasserted(struct bxe_softc *sc, 8204 uint32_t deasserted) 8205 { 8206 struct attn_route attn; 8207 struct attn_route *group_mask; 8208 int port = SC_PORT(sc); 8209 int index; 8210 uint32_t reg_addr; 8211 uint32_t val; 8212 uint32_t aeu_mask; 8213 uint8_t global = FALSE; 8214 8215 /* 8216 * Need to take HW lock because MCP or other port might also 8217 * try to handle this event. 8218 */ 8219 bxe_acquire_alr(sc); 8220 8221 if (bxe_chk_parity_attn(sc, &global, TRUE)) { 8222 /* XXX 8223 * In case of parity errors don't handle attentions so that 8224 * other function would "see" parity errors. 8225 */ 8226 sc->recovery_state = BXE_RECOVERY_INIT; 8227 // XXX schedule a recovery task... 8228 /* disable HW interrupts */ 8229 bxe_int_disable(sc); 8230 bxe_release_alr(sc); 8231 return; 8232 } 8233 8234 attn.sig[0] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4); 8235 attn.sig[1] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4); 8236 attn.sig[2] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4); 8237 attn.sig[3] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4); 8238 if (!CHIP_IS_E1x(sc)) { 8239 attn.sig[4] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4); 8240 } else { 8241 attn.sig[4] = 0; 8242 } 8243 8244 BLOGD(sc, DBG_INTR, "attn: 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n", 8245 attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]); 8246 8247 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) { 8248 if (deasserted & (1 << index)) { 8249 group_mask = &sc->attn_group[index]; 8250 8251 BLOGD(sc, DBG_INTR, 8252 "group[%d]: 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n", index, 8253 group_mask->sig[0], group_mask->sig[1], 8254 group_mask->sig[2], group_mask->sig[3], 8255 group_mask->sig[4]); 8256 8257 bxe_attn_int_deasserted4(sc, attn.sig[4] & group_mask->sig[4]); 8258 bxe_attn_int_deasserted3(sc, attn.sig[3] & group_mask->sig[3]); 8259 bxe_attn_int_deasserted1(sc, attn.sig[1] & group_mask->sig[1]); 8260 bxe_attn_int_deasserted2(sc, attn.sig[2] & group_mask->sig[2]); 8261 bxe_attn_int_deasserted0(sc, attn.sig[0] & group_mask->sig[0]); 8262 } 8263 } 8264 8265 bxe_release_alr(sc); 8266 8267 if (sc->devinfo.int_block == INT_BLOCK_HC) { 8268 reg_addr = (HC_REG_COMMAND_REG + port*32 + 8269 COMMAND_REG_ATTN_BITS_CLR); 8270 } else { 8271 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8); 8272 } 8273 8274 val = ~deasserted; 8275 BLOGD(sc, DBG_INTR, 8276 "about to mask 0x%08x at %s addr 0x%08x\n", val, 8277 (sc->devinfo.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr); 8278 REG_WR(sc, reg_addr, val); 8279 8280 if (~sc->attn_state & deasserted) { 8281 BLOGE(sc, "IGU error\n"); 8282 } 8283 8284 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : 8285 MISC_REG_AEU_MASK_ATTN_FUNC_0; 8286 8287 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); 8288 8289 aeu_mask = REG_RD(sc, reg_addr); 8290 8291 BLOGD(sc, DBG_INTR, "aeu_mask 0x%08x newly deasserted 0x%08x\n", 8292 aeu_mask, deasserted); 8293 aeu_mask |= (deasserted & 0x3ff); 8294 BLOGD(sc, DBG_INTR, "new mask 0x%08x\n", aeu_mask); 8295 8296 REG_WR(sc, reg_addr, aeu_mask); 8297 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); 8298 8299 BLOGD(sc, DBG_INTR, "attn_state 0x%08x\n", sc->attn_state); 8300 sc->attn_state &= ~deasserted; 8301 BLOGD(sc, DBG_INTR, "new state 0x%08x\n", sc->attn_state); 8302 } 8303 8304 static void 8305 bxe_attn_int(struct bxe_softc *sc) 8306 { 8307 /* read local copy of bits */ 8308 uint32_t attn_bits = le32toh(sc->def_sb->atten_status_block.attn_bits); 8309 uint32_t attn_ack = le32toh(sc->def_sb->atten_status_block.attn_bits_ack); 8310 uint32_t attn_state = sc->attn_state; 8311 8312 /* look for changed bits */ 8313 uint32_t asserted = attn_bits & ~attn_ack & ~attn_state; 8314 uint32_t deasserted = ~attn_bits & attn_ack & attn_state; 8315 8316 BLOGD(sc, DBG_INTR, 8317 "attn_bits 0x%08x attn_ack 0x%08x asserted 0x%08x deasserted 0x%08x\n", 8318 attn_bits, attn_ack, asserted, deasserted); 8319 8320 if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state)) { 8321 BLOGE(sc, "BAD attention state\n"); 8322 } 8323 8324 /* handle bits that were raised */ 8325 if (asserted) { 8326 bxe_attn_int_asserted(sc, asserted); 8327 } 8328 8329 if (deasserted) { 8330 bxe_attn_int_deasserted(sc, deasserted); 8331 } 8332 } 8333 8334 static uint16_t 8335 bxe_update_dsb_idx(struct bxe_softc *sc) 8336 { 8337 struct host_sp_status_block *def_sb = sc->def_sb; 8338 uint16_t rc = 0; 8339 8340 mb(); /* status block is written to by the chip */ 8341 8342 if (sc->def_att_idx != def_sb->atten_status_block.attn_bits_index) { 8343 sc->def_att_idx = def_sb->atten_status_block.attn_bits_index; 8344 rc |= BXE_DEF_SB_ATT_IDX; 8345 } 8346 8347 if (sc->def_idx != def_sb->sp_sb.running_index) { 8348 sc->def_idx = def_sb->sp_sb.running_index; 8349 rc |= BXE_DEF_SB_IDX; 8350 } 8351 8352 mb(); 8353 8354 return (rc); 8355 } 8356 8357 static inline struct ecore_queue_sp_obj * 8358 bxe_cid_to_q_obj(struct bxe_softc *sc, 8359 uint32_t cid) 8360 { 8361 BLOGD(sc, DBG_SP, "retrieving fp from cid %d\n", cid); 8362 return (&sc->sp_objs[CID_TO_FP(cid, sc)].q_obj); 8363 } 8364 8365 static void 8366 bxe_handle_mcast_eqe(struct bxe_softc *sc) 8367 { 8368 struct ecore_mcast_ramrod_params rparam; 8369 int rc; 8370 8371 memset(&rparam, 0, sizeof(rparam)); 8372 8373 rparam.mcast_obj = &sc->mcast_obj; 8374 8375 BXE_MCAST_LOCK(sc); 8376 8377 /* clear pending state for the last command */ 8378 sc->mcast_obj.raw.clear_pending(&sc->mcast_obj.raw); 8379 8380 /* if there are pending mcast commands - send them */ 8381 if (sc->mcast_obj.check_pending(&sc->mcast_obj)) { 8382 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT); 8383 if (rc < 0) { 8384 BLOGD(sc, DBG_SP, 8385 "ERROR: Failed to send pending mcast commands (%d)\n", rc); 8386 } 8387 } 8388 8389 BXE_MCAST_UNLOCK(sc); 8390 } 8391 8392 static void 8393 bxe_handle_classification_eqe(struct bxe_softc *sc, 8394 union event_ring_elem *elem) 8395 { 8396 unsigned long ramrod_flags = 0; 8397 int rc = 0; 8398 uint32_t cid = elem->message.data.eth_event.echo & BXE_SWCID_MASK; 8399 struct ecore_vlan_mac_obj *vlan_mac_obj; 8400 8401 /* always push next commands out, don't wait here */ 8402 bit_set(&ramrod_flags, RAMROD_CONT); 8403 8404 switch (le32toh(elem->message.data.eth_event.echo) >> BXE_SWCID_SHIFT) { 8405 case ECORE_FILTER_MAC_PENDING: 8406 BLOGD(sc, DBG_SP, "Got SETUP_MAC completions\n"); 8407 vlan_mac_obj = &sc->sp_objs[cid].mac_obj; 8408 break; 8409 8410 case ECORE_FILTER_MCAST_PENDING: 8411 BLOGD(sc, DBG_SP, "Got SETUP_MCAST completions\n"); 8412 /* 8413 * This is only relevant for 57710 where multicast MACs are 8414 * configured as unicast MACs using the same ramrod. 8415 */ 8416 bxe_handle_mcast_eqe(sc); 8417 return; 8418 8419 default: 8420 BLOGE(sc, "Unsupported classification command: %d\n", 8421 elem->message.data.eth_event.echo); 8422 return; 8423 } 8424 8425 rc = vlan_mac_obj->complete(sc, vlan_mac_obj, elem, &ramrod_flags); 8426 8427 if (rc < 0) { 8428 BLOGE(sc, "Failed to schedule new commands (%d)\n", rc); 8429 } else if (rc > 0) { 8430 BLOGD(sc, DBG_SP, "Scheduled next pending commands...\n"); 8431 } 8432 } 8433 8434 static void 8435 bxe_handle_rx_mode_eqe(struct bxe_softc *sc, 8436 union event_ring_elem *elem) 8437 { 8438 bxe_clear_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state); 8439 8440 /* send rx_mode command again if was requested */ 8441 if (bxe_test_and_clear_bit(ECORE_FILTER_RX_MODE_SCHED, 8442 &sc->sp_state)) { 8443 bxe_set_storm_rx_mode(sc); 8444 } 8445 } 8446 8447 static void 8448 bxe_update_eq_prod(struct bxe_softc *sc, 8449 uint16_t prod) 8450 { 8451 storm_memset_eq_prod(sc, prod, SC_FUNC(sc)); 8452 wmb(); /* keep prod updates ordered */ 8453 } 8454 8455 static void 8456 bxe_eq_int(struct bxe_softc *sc) 8457 { 8458 uint16_t hw_cons, sw_cons, sw_prod; 8459 union event_ring_elem *elem; 8460 uint8_t echo; 8461 uint32_t cid; 8462 uint8_t opcode; 8463 int spqe_cnt = 0; 8464 struct ecore_queue_sp_obj *q_obj; 8465 struct ecore_func_sp_obj *f_obj = &sc->func_obj; 8466 struct ecore_raw_obj *rss_raw = &sc->rss_conf_obj.raw; 8467 8468 hw_cons = le16toh(*sc->eq_cons_sb); 8469 8470 /* 8471 * The hw_cons range is 1-255, 257 - the sw_cons range is 0-254, 256. 8472 * when we get to the next-page we need to adjust so the loop 8473 * condition below will be met. The next element is the size of a 8474 * regular element and hence incrementing by 1 8475 */ 8476 if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE) { 8477 hw_cons++; 8478 } 8479 8480 /* 8481 * This function may never run in parallel with itself for a 8482 * specific sc and no need for a read memory barrier here. 8483 */ 8484 sw_cons = sc->eq_cons; 8485 sw_prod = sc->eq_prod; 8486 8487 BLOGD(sc, DBG_SP,"EQ: hw_cons=%u sw_cons=%u eq_spq_left=0x%lx\n", 8488 hw_cons, sw_cons, atomic_load_acq_long(&sc->eq_spq_left)); 8489 8490 for (; 8491 sw_cons != hw_cons; 8492 sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) { 8493 8494 elem = &sc->eq[EQ_DESC(sw_cons)]; 8495 8496 /* elem CID originates from FW, actually LE */ 8497 cid = SW_CID(elem->message.data.cfc_del_event.cid); 8498 opcode = elem->message.opcode; 8499 8500 /* handle eq element */ 8501 switch (opcode) { 8502 8503 case EVENT_RING_OPCODE_STAT_QUERY: 8504 BLOGD(sc, DBG_SP, "got statistics completion event %d\n", 8505 sc->stats_comp++); 8506 /* nothing to do with stats comp */ 8507 goto next_spqe; 8508 8509 case EVENT_RING_OPCODE_CFC_DEL: 8510 /* handle according to cid range */ 8511 /* we may want to verify here that the sc state is HALTING */ 8512 BLOGD(sc, DBG_SP, "got delete ramrod for MULTI[%d]\n", cid); 8513 q_obj = bxe_cid_to_q_obj(sc, cid); 8514 if (q_obj->complete_cmd(sc, q_obj, ECORE_Q_CMD_CFC_DEL)) { 8515 break; 8516 } 8517 goto next_spqe; 8518 8519 case EVENT_RING_OPCODE_STOP_TRAFFIC: 8520 BLOGD(sc, DBG_SP, "got STOP TRAFFIC\n"); 8521 if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_TX_STOP)) { 8522 break; 8523 } 8524 // XXX bxe_dcbx_set_params(sc, BXE_DCBX_STATE_TX_PAUSED); 8525 goto next_spqe; 8526 8527 case EVENT_RING_OPCODE_START_TRAFFIC: 8528 BLOGD(sc, DBG_SP, "got START TRAFFIC\n"); 8529 if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_TX_START)) { 8530 break; 8531 } 8532 // XXX bxe_dcbx_set_params(sc, BXE_DCBX_STATE_TX_RELEASED); 8533 goto next_spqe; 8534 8535 case EVENT_RING_OPCODE_FUNCTION_UPDATE: 8536 echo = elem->message.data.function_update_event.echo; 8537 if (echo == SWITCH_UPDATE) { 8538 BLOGD(sc, DBG_SP, "got FUNC_SWITCH_UPDATE ramrod\n"); 8539 if (f_obj->complete_cmd(sc, f_obj, 8540 ECORE_F_CMD_SWITCH_UPDATE)) { 8541 break; 8542 } 8543 } 8544 else { 8545 BLOGD(sc, DBG_SP, 8546 "AFEX: ramrod completed FUNCTION_UPDATE\n"); 8547 } 8548 goto next_spqe; 8549 8550 case EVENT_RING_OPCODE_FORWARD_SETUP: 8551 q_obj = &bxe_fwd_sp_obj(sc, q_obj); 8552 if (q_obj->complete_cmd(sc, q_obj, 8553 ECORE_Q_CMD_SETUP_TX_ONLY)) { 8554 break; 8555 } 8556 goto next_spqe; 8557 8558 case EVENT_RING_OPCODE_FUNCTION_START: 8559 BLOGD(sc, DBG_SP, "got FUNC_START ramrod\n"); 8560 if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_START)) { 8561 break; 8562 } 8563 goto next_spqe; 8564 8565 case EVENT_RING_OPCODE_FUNCTION_STOP: 8566 BLOGD(sc, DBG_SP, "got FUNC_STOP ramrod\n"); 8567 if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_STOP)) { 8568 break; 8569 } 8570 goto next_spqe; 8571 } 8572 8573 switch (opcode | sc->state) { 8574 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | BXE_STATE_OPEN): 8575 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | BXE_STATE_OPENING_WAITING_PORT): 8576 cid = elem->message.data.eth_event.echo & BXE_SWCID_MASK; 8577 BLOGD(sc, DBG_SP, "got RSS_UPDATE ramrod. CID %d\n", cid); 8578 rss_raw->clear_pending(rss_raw); 8579 break; 8580 8581 case (EVENT_RING_OPCODE_SET_MAC | BXE_STATE_OPEN): 8582 case (EVENT_RING_OPCODE_SET_MAC | BXE_STATE_DIAG): 8583 case (EVENT_RING_OPCODE_SET_MAC | BXE_STATE_CLOSING_WAITING_HALT): 8584 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BXE_STATE_OPEN): 8585 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BXE_STATE_DIAG): 8586 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BXE_STATE_CLOSING_WAITING_HALT): 8587 BLOGD(sc, DBG_SP, "got (un)set mac ramrod\n"); 8588 bxe_handle_classification_eqe(sc, elem); 8589 break; 8590 8591 case (EVENT_RING_OPCODE_MULTICAST_RULES | BXE_STATE_OPEN): 8592 case (EVENT_RING_OPCODE_MULTICAST_RULES | BXE_STATE_DIAG): 8593 case (EVENT_RING_OPCODE_MULTICAST_RULES | BXE_STATE_CLOSING_WAITING_HALT): 8594 BLOGD(sc, DBG_SP, "got mcast ramrod\n"); 8595 bxe_handle_mcast_eqe(sc); 8596 break; 8597 8598 case (EVENT_RING_OPCODE_FILTERS_RULES | BXE_STATE_OPEN): 8599 case (EVENT_RING_OPCODE_FILTERS_RULES | BXE_STATE_DIAG): 8600 case (EVENT_RING_OPCODE_FILTERS_RULES | BXE_STATE_CLOSING_WAITING_HALT): 8601 BLOGD(sc, DBG_SP, "got rx_mode ramrod\n"); 8602 bxe_handle_rx_mode_eqe(sc, elem); 8603 break; 8604 8605 default: 8606 /* unknown event log error and continue */ 8607 BLOGE(sc, "Unknown EQ event %d, sc->state 0x%x\n", 8608 elem->message.opcode, sc->state); 8609 } 8610 8611 next_spqe: 8612 spqe_cnt++; 8613 } /* for */ 8614 8615 mb(); 8616 atomic_add_acq_long(&sc->eq_spq_left, spqe_cnt); 8617 8618 sc->eq_cons = sw_cons; 8619 sc->eq_prod = sw_prod; 8620 8621 /* make sure that above mem writes were issued towards the memory */ 8622 wmb(); 8623 8624 /* update producer */ 8625 bxe_update_eq_prod(sc, sc->eq_prod); 8626 } 8627 8628 static void 8629 bxe_handle_sp_tq(void *context, 8630 int pending) 8631 { 8632 struct bxe_softc *sc = (struct bxe_softc *)context; 8633 uint16_t status; 8634 8635 BLOGD(sc, DBG_SP, "---> SP TASK <---\n"); 8636 8637 /* what work needs to be performed? */ 8638 status = bxe_update_dsb_idx(sc); 8639 8640 BLOGD(sc, DBG_SP, "dsb status 0x%04x\n", status); 8641 8642 /* HW attentions */ 8643 if (status & BXE_DEF_SB_ATT_IDX) { 8644 BLOGD(sc, DBG_SP, "---> ATTN INTR <---\n"); 8645 bxe_attn_int(sc); 8646 status &= ~BXE_DEF_SB_ATT_IDX; 8647 } 8648 8649 /* SP events: STAT_QUERY and others */ 8650 if (status & BXE_DEF_SB_IDX) { 8651 /* handle EQ completions */ 8652 BLOGD(sc, DBG_SP, "---> EQ INTR <---\n"); 8653 bxe_eq_int(sc); 8654 bxe_ack_sb(sc, sc->igu_dsb_id, USTORM_ID, 8655 le16toh(sc->def_idx), IGU_INT_NOP, 1); 8656 status &= ~BXE_DEF_SB_IDX; 8657 } 8658 8659 /* if status is non zero then something went wrong */ 8660 if (__predict_false(status)) { 8661 BLOGE(sc, "Got an unknown SP interrupt! (0x%04x)\n", status); 8662 } 8663 8664 /* ack status block only if something was actually handled */ 8665 bxe_ack_sb(sc, sc->igu_dsb_id, ATTENTION_ID, 8666 le16toh(sc->def_att_idx), IGU_INT_ENABLE, 1); 8667 8668 /* 8669 * Must be called after the EQ processing (since eq leads to sriov 8670 * ramrod completion flows). 8671 * This flow may have been scheduled by the arrival of a ramrod 8672 * completion, or by the sriov code rescheduling itself. 8673 */ 8674 // XXX bxe_iov_sp_task(sc); 8675 8676 } 8677 8678 static void 8679 bxe_handle_fp_tq(void *context, 8680 int pending) 8681 { 8682 struct bxe_fastpath *fp = (struct bxe_fastpath *)context; 8683 struct bxe_softc *sc = fp->sc; 8684 uint8_t more_tx = FALSE; 8685 uint8_t more_rx = FALSE; 8686 8687 BLOGD(sc, DBG_INTR, "---> FP TASK QUEUE (%d) <---\n", fp->index); 8688 8689 /* XXX 8690 * IFF_DRV_RUNNING state can't be checked here since we process 8691 * slowpath events on a client queue during setup. Instead 8692 * we need to add a "process/continue" flag here that the driver 8693 * can use to tell the task here not to do anything. 8694 */ 8695 #if 0 8696 if (!(if_getdrvflags(sc->ifp) & IFF_DRV_RUNNING)) { 8697 return; 8698 } 8699 #endif 8700 8701 /* update the fastpath index */ 8702 bxe_update_fp_sb_idx(fp); 8703 8704 /* XXX add loop here if ever support multiple tx CoS */ 8705 /* fp->txdata[cos] */ 8706 if (bxe_has_tx_work(fp)) { 8707 BXE_FP_TX_LOCK(fp); 8708 more_tx = bxe_txeof(sc, fp); 8709 BXE_FP_TX_UNLOCK(fp); 8710 } 8711 8712 if (bxe_has_rx_work(fp)) { 8713 more_rx = bxe_rxeof(sc, fp); 8714 } 8715 8716 if (more_rx /*|| more_tx*/) { 8717 /* still more work to do */ 8718 taskqueue_enqueue(fp->tq, &fp->tq_task); 8719 return; 8720 } 8721 8722 bxe_ack_sb(sc, fp->igu_sb_id, USTORM_ID, 8723 le16toh(fp->fp_hc_idx), IGU_INT_ENABLE, 1); 8724 } 8725 8726 static void 8727 bxe_task_fp(struct bxe_fastpath *fp) 8728 { 8729 struct bxe_softc *sc = fp->sc; 8730 uint8_t more_tx = FALSE; 8731 uint8_t more_rx = FALSE; 8732 8733 BLOGD(sc, DBG_INTR, "---> FP TASK ISR (%d) <---\n", fp->index); 8734 8735 /* update the fastpath index */ 8736 bxe_update_fp_sb_idx(fp); 8737 8738 /* XXX add loop here if ever support multiple tx CoS */ 8739 /* fp->txdata[cos] */ 8740 if (bxe_has_tx_work(fp)) { 8741 BXE_FP_TX_LOCK(fp); 8742 more_tx = bxe_txeof(sc, fp); 8743 BXE_FP_TX_UNLOCK(fp); 8744 } 8745 8746 if (bxe_has_rx_work(fp)) { 8747 more_rx = bxe_rxeof(sc, fp); 8748 } 8749 8750 if (more_rx /*|| more_tx*/) { 8751 /* still more work to do, bail out if this ISR and process later */ 8752 taskqueue_enqueue(fp->tq, &fp->tq_task); 8753 return; 8754 } 8755 8756 /* 8757 * Here we write the fastpath index taken before doing any tx or rx work. 8758 * It is very well possible other hw events occurred up to this point and 8759 * they were actually processed accordingly above. Since we're going to 8760 * write an older fastpath index, an interrupt is coming which we might 8761 * not do any work in. 8762 */ 8763 bxe_ack_sb(sc, fp->igu_sb_id, USTORM_ID, 8764 le16toh(fp->fp_hc_idx), IGU_INT_ENABLE, 1); 8765 } 8766 8767 /* 8768 * Legacy interrupt entry point. 8769 * 8770 * Verifies that the controller generated the interrupt and 8771 * then calls a separate routine to handle the various 8772 * interrupt causes: link, RX, and TX. 8773 */ 8774 static void 8775 bxe_intr_legacy(void *xsc) 8776 { 8777 struct bxe_softc *sc = (struct bxe_softc *)xsc; 8778 struct bxe_fastpath *fp; 8779 uint16_t status, mask; 8780 int i; 8781 8782 BLOGD(sc, DBG_INTR, "---> BXE INTx <---\n"); 8783 8784 /* 8785 * 0 for ustorm, 1 for cstorm 8786 * the bits returned from ack_int() are 0-15 8787 * bit 0 = attention status block 8788 * bit 1 = fast path status block 8789 * a mask of 0x2 or more = tx/rx event 8790 * a mask of 1 = slow path event 8791 */ 8792 8793 status = bxe_ack_int(sc); 8794 8795 /* the interrupt is not for us */ 8796 if (__predict_false(status == 0)) { 8797 BLOGD(sc, DBG_INTR, "Not our interrupt!\n"); 8798 return; 8799 } 8800 8801 BLOGD(sc, DBG_INTR, "Interrupt status 0x%04x\n", status); 8802 8803 FOR_EACH_ETH_QUEUE(sc, i) { 8804 fp = &sc->fp[i]; 8805 mask = (0x2 << (fp->index + CNIC_SUPPORT(sc))); 8806 if (status & mask) { 8807 /* acknowledge and disable further fastpath interrupts */ 8808 bxe_ack_sb(sc, fp->igu_sb_id, USTORM_ID, 0, IGU_INT_DISABLE, 0); 8809 bxe_task_fp(fp); 8810 status &= ~mask; 8811 } 8812 } 8813 8814 if (__predict_false(status & 0x1)) { 8815 /* acknowledge and disable further slowpath interrupts */ 8816 bxe_ack_sb(sc, sc->igu_dsb_id, USTORM_ID, 0, IGU_INT_DISABLE, 0); 8817 8818 /* schedule slowpath handler */ 8819 taskqueue_enqueue(sc->sp_tq, &sc->sp_tq_task); 8820 8821 status &= ~0x1; 8822 } 8823 8824 if (__predict_false(status)) { 8825 BLOGW(sc, "Unexpected fastpath status (0x%08x)!\n", status); 8826 } 8827 } 8828 8829 /* slowpath interrupt entry point */ 8830 static void 8831 bxe_intr_sp(void *xsc) 8832 { 8833 struct bxe_softc *sc = (struct bxe_softc *)xsc; 8834 8835 BLOGD(sc, (DBG_INTR | DBG_SP), "---> SP INTR <---\n"); 8836 8837 /* acknowledge and disable further slowpath interrupts */ 8838 bxe_ack_sb(sc, sc->igu_dsb_id, USTORM_ID, 0, IGU_INT_DISABLE, 0); 8839 8840 /* schedule slowpath handler */ 8841 taskqueue_enqueue(sc->sp_tq, &sc->sp_tq_task); 8842 } 8843 8844 /* fastpath interrupt entry point */ 8845 static void 8846 bxe_intr_fp(void *xfp) 8847 { 8848 struct bxe_fastpath *fp = (struct bxe_fastpath *)xfp; 8849 struct bxe_softc *sc = fp->sc; 8850 8851 BLOGD(sc, DBG_INTR, "---> FP INTR %d <---\n", fp->index); 8852 8853 BLOGD(sc, DBG_INTR, 8854 "(cpu=%d) MSI-X fp=%d fw_sb=%d igu_sb=%d\n", 8855 curcpu, fp->index, fp->fw_sb_id, fp->igu_sb_id); 8856 8857 /* acknowledge and disable further fastpath interrupts */ 8858 bxe_ack_sb(sc, fp->igu_sb_id, USTORM_ID, 0, IGU_INT_DISABLE, 0); 8859 8860 bxe_task_fp(fp); 8861 } 8862 8863 /* Release all interrupts allocated by the driver. */ 8864 static void 8865 bxe_interrupt_free(struct bxe_softc *sc) 8866 { 8867 int i; 8868 8869 switch (sc->interrupt_mode) { 8870 case INTR_MODE_INTX: 8871 BLOGD(sc, DBG_LOAD, "Releasing legacy INTx vector\n"); 8872 if (sc->intr[0].resource != NULL) { 8873 bus_release_resource(sc->dev, 8874 SYS_RES_IRQ, 8875 sc->intr[0].rid, 8876 sc->intr[0].resource); 8877 } 8878 break; 8879 case INTR_MODE_MSI: 8880 for (i = 0; i < sc->intr_count; i++) { 8881 BLOGD(sc, DBG_LOAD, "Releasing MSI vector %d\n", i); 8882 if (sc->intr[i].resource && sc->intr[i].rid) { 8883 bus_release_resource(sc->dev, 8884 SYS_RES_IRQ, 8885 sc->intr[i].rid, 8886 sc->intr[i].resource); 8887 } 8888 } 8889 pci_release_msi(sc->dev); 8890 break; 8891 case INTR_MODE_MSIX: 8892 for (i = 0; i < sc->intr_count; i++) { 8893 BLOGD(sc, DBG_LOAD, "Releasing MSI-X vector %d\n", i); 8894 if (sc->intr[i].resource && sc->intr[i].rid) { 8895 bus_release_resource(sc->dev, 8896 SYS_RES_IRQ, 8897 sc->intr[i].rid, 8898 sc->intr[i].resource); 8899 } 8900 } 8901 pci_release_msi(sc->dev); 8902 break; 8903 default: 8904 /* nothing to do as initial allocation failed */ 8905 break; 8906 } 8907 } 8908 8909 /* 8910 * This function determines and allocates the appropriate 8911 * interrupt based on system capabilites and user request. 8912 * 8913 * The user may force a particular interrupt mode, specify 8914 * the number of receive queues, specify the method for 8915 * distribuitng received frames to receive queues, or use 8916 * the default settings which will automatically select the 8917 * best supported combination. In addition, the OS may or 8918 * may not support certain combinations of these settings. 8919 * This routine attempts to reconcile the settings requested 8920 * by the user with the capabilites available from the system 8921 * to select the optimal combination of features. 8922 * 8923 * Returns: 8924 * 0 = Success, !0 = Failure. 8925 */ 8926 static int 8927 bxe_interrupt_alloc(struct bxe_softc *sc) 8928 { 8929 int msix_count = 0; 8930 int msi_count = 0; 8931 int num_requested = 0; 8932 int num_allocated = 0; 8933 int rid, i, j; 8934 int rc; 8935 8936 /* get the number of available MSI/MSI-X interrupts from the OS */ 8937 if (sc->interrupt_mode > 0) { 8938 if (sc->devinfo.pcie_cap_flags & BXE_MSIX_CAPABLE_FLAG) { 8939 msix_count = pci_msix_count(sc->dev); 8940 } 8941 8942 if (sc->devinfo.pcie_cap_flags & BXE_MSI_CAPABLE_FLAG) { 8943 msi_count = pci_msi_count(sc->dev); 8944 } 8945 8946 BLOGD(sc, DBG_LOAD, "%d MSI and %d MSI-X vectors available\n", 8947 msi_count, msix_count); 8948 } 8949 8950 do { /* try allocating MSI-X interrupt resources (at least 2) */ 8951 if (sc->interrupt_mode != INTR_MODE_MSIX) { 8952 break; 8953 } 8954 8955 if (((sc->devinfo.pcie_cap_flags & BXE_MSIX_CAPABLE_FLAG) == 0) || 8956 (msix_count < 2)) { 8957 sc->interrupt_mode = INTR_MODE_MSI; /* try MSI next */ 8958 break; 8959 } 8960 8961 /* ask for the necessary number of MSI-X vectors */ 8962 num_requested = min((sc->num_queues + 1), msix_count); 8963 8964 BLOGD(sc, DBG_LOAD, "Requesting %d MSI-X vectors\n", num_requested); 8965 8966 num_allocated = num_requested; 8967 if ((rc = pci_alloc_msix(sc->dev, &num_allocated)) != 0) { 8968 BLOGE(sc, "MSI-X alloc failed! (%d)\n", rc); 8969 sc->interrupt_mode = INTR_MODE_MSI; /* try MSI next */ 8970 break; 8971 } 8972 8973 if (num_allocated < 2) { /* possible? */ 8974 BLOGE(sc, "MSI-X allocation less than 2!\n"); 8975 sc->interrupt_mode = INTR_MODE_MSI; /* try MSI next */ 8976 pci_release_msi(sc->dev); 8977 break; 8978 } 8979 8980 BLOGI(sc, "MSI-X vectors Requested %d and Allocated %d\n", 8981 num_requested, num_allocated); 8982 8983 /* best effort so use the number of vectors allocated to us */ 8984 sc->intr_count = num_allocated; 8985 sc->num_queues = num_allocated - 1; 8986 8987 rid = 1; /* initial resource identifier */ 8988 8989 /* allocate the MSI-X vectors */ 8990 for (i = 0; i < num_allocated; i++) { 8991 sc->intr[i].rid = (rid + i); 8992 8993 if ((sc->intr[i].resource = 8994 bus_alloc_resource_any(sc->dev, 8995 SYS_RES_IRQ, 8996 &sc->intr[i].rid, 8997 RF_ACTIVE)) == NULL) { 8998 BLOGE(sc, "Failed to map MSI-X[%d] (rid=%d)!\n", 8999 i, (rid + i)); 9000 9001 for (j = (i - 1); j >= 0; j--) { 9002 bus_release_resource(sc->dev, 9003 SYS_RES_IRQ, 9004 sc->intr[j].rid, 9005 sc->intr[j].resource); 9006 } 9007 9008 sc->intr_count = 0; 9009 sc->num_queues = 0; 9010 sc->interrupt_mode = INTR_MODE_MSI; /* try MSI next */ 9011 pci_release_msi(sc->dev); 9012 break; 9013 } 9014 9015 BLOGD(sc, DBG_LOAD, "Mapped MSI-X[%d] (rid=%d)\n", i, (rid + i)); 9016 } 9017 } while (0); 9018 9019 do { /* try allocating MSI vector resources (at least 2) */ 9020 if (sc->interrupt_mode != INTR_MODE_MSI) { 9021 break; 9022 } 9023 9024 if (((sc->devinfo.pcie_cap_flags & BXE_MSI_CAPABLE_FLAG) == 0) || 9025 (msi_count < 1)) { 9026 sc->interrupt_mode = INTR_MODE_INTX; /* try INTx next */ 9027 break; 9028 } 9029 9030 /* ask for a single MSI vector */ 9031 num_requested = 1; 9032 9033 BLOGD(sc, DBG_LOAD, "Requesting %d MSI vectors\n", num_requested); 9034 9035 num_allocated = num_requested; 9036 if ((rc = pci_alloc_msi(sc->dev, &num_allocated)) != 0) { 9037 BLOGE(sc, "MSI alloc failed (%d)!\n", rc); 9038 sc->interrupt_mode = INTR_MODE_INTX; /* try INTx next */ 9039 break; 9040 } 9041 9042 if (num_allocated != 1) { /* possible? */ 9043 BLOGE(sc, "MSI allocation is not 1!\n"); 9044 sc->interrupt_mode = INTR_MODE_INTX; /* try INTx next */ 9045 pci_release_msi(sc->dev); 9046 break; 9047 } 9048 9049 BLOGI(sc, "MSI vectors Requested %d and Allocated %d\n", 9050 num_requested, num_allocated); 9051 9052 /* best effort so use the number of vectors allocated to us */ 9053 sc->intr_count = num_allocated; 9054 sc->num_queues = num_allocated; 9055 9056 rid = 1; /* initial resource identifier */ 9057 9058 sc->intr[0].rid = rid; 9059 9060 if ((sc->intr[0].resource = 9061 bus_alloc_resource_any(sc->dev, 9062 SYS_RES_IRQ, 9063 &sc->intr[0].rid, 9064 RF_ACTIVE)) == NULL) { 9065 BLOGE(sc, "Failed to map MSI[0] (rid=%d)!\n", rid); 9066 sc->intr_count = 0; 9067 sc->num_queues = 0; 9068 sc->interrupt_mode = INTR_MODE_INTX; /* try INTx next */ 9069 pci_release_msi(sc->dev); 9070 break; 9071 } 9072 9073 BLOGD(sc, DBG_LOAD, "Mapped MSI[0] (rid=%d)\n", rid); 9074 } while (0); 9075 9076 do { /* try allocating INTx vector resources */ 9077 if (sc->interrupt_mode != INTR_MODE_INTX) { 9078 break; 9079 } 9080 9081 BLOGD(sc, DBG_LOAD, "Requesting legacy INTx interrupt\n"); 9082 9083 /* only one vector for INTx */ 9084 sc->intr_count = 1; 9085 sc->num_queues = 1; 9086 9087 rid = 0; /* initial resource identifier */ 9088 9089 sc->intr[0].rid = rid; 9090 9091 if ((sc->intr[0].resource = 9092 bus_alloc_resource_any(sc->dev, 9093 SYS_RES_IRQ, 9094 &sc->intr[0].rid, 9095 (RF_ACTIVE | RF_SHAREABLE))) == NULL) { 9096 BLOGE(sc, "Failed to map INTx (rid=%d)!\n", rid); 9097 sc->intr_count = 0; 9098 sc->num_queues = 0; 9099 sc->interrupt_mode = -1; /* Failed! */ 9100 break; 9101 } 9102 9103 BLOGD(sc, DBG_LOAD, "Mapped INTx (rid=%d)\n", rid); 9104 } while (0); 9105 9106 if (sc->interrupt_mode == -1) { 9107 BLOGE(sc, "Interrupt Allocation: FAILED!!!\n"); 9108 rc = 1; 9109 } else { 9110 BLOGD(sc, DBG_LOAD, 9111 "Interrupt Allocation: interrupt_mode=%d, num_queues=%d\n", 9112 sc->interrupt_mode, sc->num_queues); 9113 rc = 0; 9114 } 9115 9116 return (rc); 9117 } 9118 9119 static void 9120 bxe_interrupt_detach(struct bxe_softc *sc) 9121 { 9122 struct bxe_fastpath *fp; 9123 int i; 9124 9125 /* release interrupt resources */ 9126 for (i = 0; i < sc->intr_count; i++) { 9127 if (sc->intr[i].resource && sc->intr[i].tag) { 9128 BLOGD(sc, DBG_LOAD, "Disabling interrupt vector %d\n", i); 9129 bus_teardown_intr(sc->dev, sc->intr[i].resource, sc->intr[i].tag); 9130 } 9131 } 9132 9133 for (i = 0; i < sc->num_queues; i++) { 9134 fp = &sc->fp[i]; 9135 if (fp->tq) { 9136 taskqueue_drain(fp->tq, &fp->tq_task); 9137 taskqueue_drain(fp->tq, &fp->tx_task); 9138 while (taskqueue_cancel_timeout(fp->tq, &fp->tx_timeout_task, 9139 NULL)) 9140 taskqueue_drain_timeout(fp->tq, &fp->tx_timeout_task); 9141 } 9142 9143 for (i = 0; i < sc->num_queues; i++) { 9144 fp = &sc->fp[i]; 9145 if (fp->tq != NULL) { 9146 taskqueue_free(fp->tq); 9147 fp->tq = NULL; 9148 } 9149 } 9150 } 9151 9152 if (sc->sp_tq) { 9153 taskqueue_drain(sc->sp_tq, &sc->sp_tq_task); 9154 taskqueue_free(sc->sp_tq); 9155 sc->sp_tq = NULL; 9156 } 9157 } 9158 9159 /* 9160 * Enables interrupts and attach to the ISR. 9161 * 9162 * When using multiple MSI/MSI-X vectors the first vector 9163 * is used for slowpath operations while all remaining 9164 * vectors are used for fastpath operations. If only a 9165 * single MSI/MSI-X vector is used (SINGLE_ISR) then the 9166 * ISR must look for both slowpath and fastpath completions. 9167 */ 9168 static int 9169 bxe_interrupt_attach(struct bxe_softc *sc) 9170 { 9171 struct bxe_fastpath *fp; 9172 int rc = 0; 9173 int i; 9174 9175 snprintf(sc->sp_tq_name, sizeof(sc->sp_tq_name), 9176 "bxe%d_sp_tq", sc->unit); 9177 TASK_INIT(&sc->sp_tq_task, 0, bxe_handle_sp_tq, sc); 9178 sc->sp_tq = taskqueue_create(sc->sp_tq_name, M_NOWAIT, 9179 taskqueue_thread_enqueue, 9180 &sc->sp_tq); 9181 taskqueue_start_threads(&sc->sp_tq, 1, PWAIT, /* lower priority */ 9182 "%s", sc->sp_tq_name); 9183 9184 9185 for (i = 0; i < sc->num_queues; i++) { 9186 fp = &sc->fp[i]; 9187 snprintf(fp->tq_name, sizeof(fp->tq_name), 9188 "bxe%d_fp%d_tq", sc->unit, i); 9189 TASK_INIT(&fp->tq_task, 0, bxe_handle_fp_tq, fp); 9190 TASK_INIT(&fp->tx_task, 0, bxe_tx_mq_start_deferred, fp); 9191 fp->tq = taskqueue_create(fp->tq_name, M_NOWAIT, 9192 taskqueue_thread_enqueue, 9193 &fp->tq); 9194 TIMEOUT_TASK_INIT(fp->tq, &fp->tx_timeout_task, 0, 9195 bxe_tx_mq_start_deferred, fp); 9196 taskqueue_start_threads(&fp->tq, 1, PI_NET, /* higher priority */ 9197 "%s", fp->tq_name); 9198 } 9199 9200 /* setup interrupt handlers */ 9201 if (sc->interrupt_mode == INTR_MODE_MSIX) { 9202 BLOGD(sc, DBG_LOAD, "Enabling slowpath MSI-X[0] vector\n"); 9203 9204 /* 9205 * Setup the interrupt handler. Note that we pass the driver instance 9206 * to the interrupt handler for the slowpath. 9207 */ 9208 if ((rc = bus_setup_intr(sc->dev, sc->intr[0].resource, 9209 (INTR_TYPE_NET | INTR_MPSAFE), 9210 NULL, bxe_intr_sp, sc, 9211 &sc->intr[0].tag)) != 0) { 9212 BLOGE(sc, "Failed to allocate MSI-X[0] vector (%d)\n", rc); 9213 goto bxe_interrupt_attach_exit; 9214 } 9215 9216 bus_describe_intr(sc->dev, sc->intr[0].resource, 9217 sc->intr[0].tag, "sp"); 9218 9219 /* bus_bind_intr(sc->dev, sc->intr[0].resource, 0); */ 9220 9221 /* initialize the fastpath vectors (note the first was used for sp) */ 9222 for (i = 0; i < sc->num_queues; i++) { 9223 fp = &sc->fp[i]; 9224 BLOGD(sc, DBG_LOAD, "Enabling MSI-X[%d] vector\n", (i + 1)); 9225 9226 /* 9227 * Setup the interrupt handler. Note that we pass the 9228 * fastpath context to the interrupt handler in this 9229 * case. 9230 */ 9231 if ((rc = bus_setup_intr(sc->dev, sc->intr[i + 1].resource, 9232 (INTR_TYPE_NET | INTR_MPSAFE), 9233 NULL, bxe_intr_fp, fp, 9234 &sc->intr[i + 1].tag)) != 0) { 9235 BLOGE(sc, "Failed to allocate MSI-X[%d] vector (%d)\n", 9236 (i + 1), rc); 9237 goto bxe_interrupt_attach_exit; 9238 } 9239 9240 bus_describe_intr(sc->dev, sc->intr[i + 1].resource, 9241 sc->intr[i + 1].tag, "fp%02d", i); 9242 9243 /* bind the fastpath instance to a cpu */ 9244 if (sc->num_queues > 1) { 9245 bus_bind_intr(sc->dev, sc->intr[i + 1].resource, i); 9246 } 9247 9248 fp->state = BXE_FP_STATE_IRQ; 9249 } 9250 } else if (sc->interrupt_mode == INTR_MODE_MSI) { 9251 BLOGD(sc, DBG_LOAD, "Enabling MSI[0] vector\n"); 9252 9253 /* 9254 * Setup the interrupt handler. Note that we pass the 9255 * driver instance to the interrupt handler which 9256 * will handle both the slowpath and fastpath. 9257 */ 9258 if ((rc = bus_setup_intr(sc->dev, sc->intr[0].resource, 9259 (INTR_TYPE_NET | INTR_MPSAFE), 9260 NULL, bxe_intr_legacy, sc, 9261 &sc->intr[0].tag)) != 0) { 9262 BLOGE(sc, "Failed to allocate MSI[0] vector (%d)\n", rc); 9263 goto bxe_interrupt_attach_exit; 9264 } 9265 9266 } else { /* (sc->interrupt_mode == INTR_MODE_INTX) */ 9267 BLOGD(sc, DBG_LOAD, "Enabling INTx interrupts\n"); 9268 9269 /* 9270 * Setup the interrupt handler. Note that we pass the 9271 * driver instance to the interrupt handler which 9272 * will handle both the slowpath and fastpath. 9273 */ 9274 if ((rc = bus_setup_intr(sc->dev, sc->intr[0].resource, 9275 (INTR_TYPE_NET | INTR_MPSAFE), 9276 NULL, bxe_intr_legacy, sc, 9277 &sc->intr[0].tag)) != 0) { 9278 BLOGE(sc, "Failed to allocate INTx interrupt (%d)\n", rc); 9279 goto bxe_interrupt_attach_exit; 9280 } 9281 } 9282 9283 bxe_interrupt_attach_exit: 9284 9285 return (rc); 9286 } 9287 9288 static int bxe_init_hw_common_chip(struct bxe_softc *sc); 9289 static int bxe_init_hw_common(struct bxe_softc *sc); 9290 static int bxe_init_hw_port(struct bxe_softc *sc); 9291 static int bxe_init_hw_func(struct bxe_softc *sc); 9292 static void bxe_reset_common(struct bxe_softc *sc); 9293 static void bxe_reset_port(struct bxe_softc *sc); 9294 static void bxe_reset_func(struct bxe_softc *sc); 9295 static int bxe_gunzip_init(struct bxe_softc *sc); 9296 static void bxe_gunzip_end(struct bxe_softc *sc); 9297 static int bxe_init_firmware(struct bxe_softc *sc); 9298 static void bxe_release_firmware(struct bxe_softc *sc); 9299 9300 static struct 9301 ecore_func_sp_drv_ops bxe_func_sp_drv = { 9302 .init_hw_cmn_chip = bxe_init_hw_common_chip, 9303 .init_hw_cmn = bxe_init_hw_common, 9304 .init_hw_port = bxe_init_hw_port, 9305 .init_hw_func = bxe_init_hw_func, 9306 9307 .reset_hw_cmn = bxe_reset_common, 9308 .reset_hw_port = bxe_reset_port, 9309 .reset_hw_func = bxe_reset_func, 9310 9311 .gunzip_init = bxe_gunzip_init, 9312 .gunzip_end = bxe_gunzip_end, 9313 9314 .init_fw = bxe_init_firmware, 9315 .release_fw = bxe_release_firmware, 9316 }; 9317 9318 static void 9319 bxe_init_func_obj(struct bxe_softc *sc) 9320 { 9321 sc->dmae_ready = 0; 9322 9323 ecore_init_func_obj(sc, 9324 &sc->func_obj, 9325 BXE_SP(sc, func_rdata), 9326 BXE_SP_MAPPING(sc, func_rdata), 9327 BXE_SP(sc, func_afex_rdata), 9328 BXE_SP_MAPPING(sc, func_afex_rdata), 9329 &bxe_func_sp_drv); 9330 } 9331 9332 static int 9333 bxe_init_hw(struct bxe_softc *sc, 9334 uint32_t load_code) 9335 { 9336 struct ecore_func_state_params func_params = { NULL }; 9337 int rc; 9338 9339 /* prepare the parameters for function state transitions */ 9340 bit_set(&func_params.ramrod_flags, RAMROD_COMP_WAIT); 9341 9342 func_params.f_obj = &sc->func_obj; 9343 func_params.cmd = ECORE_F_CMD_HW_INIT; 9344 9345 func_params.params.hw_init.load_phase = load_code; 9346 9347 /* 9348 * Via a plethora of function pointers, we will eventually reach 9349 * bxe_init_hw_common(), bxe_init_hw_port(), or bxe_init_hw_func(). 9350 */ 9351 rc = ecore_func_state_change(sc, &func_params); 9352 9353 return (rc); 9354 } 9355 9356 static void 9357 bxe_fill(struct bxe_softc *sc, 9358 uint32_t addr, 9359 int fill, 9360 uint32_t len) 9361 { 9362 uint32_t i; 9363 9364 if (!(len % 4) && !(addr % 4)) { 9365 for (i = 0; i < len; i += 4) { 9366 REG_WR(sc, (addr + i), fill); 9367 } 9368 } else { 9369 for (i = 0; i < len; i++) { 9370 REG_WR8(sc, (addr + i), fill); 9371 } 9372 } 9373 } 9374 9375 /* writes FP SP data to FW - data_size in dwords */ 9376 static void 9377 bxe_wr_fp_sb_data(struct bxe_softc *sc, 9378 int fw_sb_id, 9379 uint32_t *sb_data_p, 9380 uint32_t data_size) 9381 { 9382 int index; 9383 9384 for (index = 0; index < data_size; index++) { 9385 REG_WR(sc, 9386 (BAR_CSTRORM_INTMEM + 9387 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) + 9388 (sizeof(uint32_t) * index)), 9389 *(sb_data_p + index)); 9390 } 9391 } 9392 9393 static void 9394 bxe_zero_fp_sb(struct bxe_softc *sc, 9395 int fw_sb_id) 9396 { 9397 struct hc_status_block_data_e2 sb_data_e2; 9398 struct hc_status_block_data_e1x sb_data_e1x; 9399 uint32_t *sb_data_p; 9400 uint32_t data_size = 0; 9401 9402 if (!CHIP_IS_E1x(sc)) { 9403 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2)); 9404 sb_data_e2.common.state = SB_DISABLED; 9405 sb_data_e2.common.p_func.vf_valid = FALSE; 9406 sb_data_p = (uint32_t *)&sb_data_e2; 9407 data_size = (sizeof(struct hc_status_block_data_e2) / 9408 sizeof(uint32_t)); 9409 } else { 9410 memset(&sb_data_e1x, 0, sizeof(struct hc_status_block_data_e1x)); 9411 sb_data_e1x.common.state = SB_DISABLED; 9412 sb_data_e1x.common.p_func.vf_valid = FALSE; 9413 sb_data_p = (uint32_t *)&sb_data_e1x; 9414 data_size = (sizeof(struct hc_status_block_data_e1x) / 9415 sizeof(uint32_t)); 9416 } 9417 9418 bxe_wr_fp_sb_data(sc, fw_sb_id, sb_data_p, data_size); 9419 9420 bxe_fill(sc, (BAR_CSTRORM_INTMEM + CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id)), 9421 0, CSTORM_STATUS_BLOCK_SIZE); 9422 bxe_fill(sc, (BAR_CSTRORM_INTMEM + CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id)), 9423 0, CSTORM_SYNC_BLOCK_SIZE); 9424 } 9425 9426 static void 9427 bxe_wr_sp_sb_data(struct bxe_softc *sc, 9428 struct hc_sp_status_block_data *sp_sb_data) 9429 { 9430 int i; 9431 9432 for (i = 0; 9433 i < (sizeof(struct hc_sp_status_block_data) / sizeof(uint32_t)); 9434 i++) { 9435 REG_WR(sc, 9436 (BAR_CSTRORM_INTMEM + 9437 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(SC_FUNC(sc)) + 9438 (i * sizeof(uint32_t))), 9439 *((uint32_t *)sp_sb_data + i)); 9440 } 9441 } 9442 9443 static void 9444 bxe_zero_sp_sb(struct bxe_softc *sc) 9445 { 9446 struct hc_sp_status_block_data sp_sb_data; 9447 9448 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data)); 9449 9450 sp_sb_data.state = SB_DISABLED; 9451 sp_sb_data.p_func.vf_valid = FALSE; 9452 9453 bxe_wr_sp_sb_data(sc, &sp_sb_data); 9454 9455 bxe_fill(sc, 9456 (BAR_CSTRORM_INTMEM + 9457 CSTORM_SP_STATUS_BLOCK_OFFSET(SC_FUNC(sc))), 9458 0, CSTORM_SP_STATUS_BLOCK_SIZE); 9459 bxe_fill(sc, 9460 (BAR_CSTRORM_INTMEM + 9461 CSTORM_SP_SYNC_BLOCK_OFFSET(SC_FUNC(sc))), 9462 0, CSTORM_SP_SYNC_BLOCK_SIZE); 9463 } 9464 9465 static void 9466 bxe_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm, 9467 int igu_sb_id, 9468 int igu_seg_id) 9469 { 9470 hc_sm->igu_sb_id = igu_sb_id; 9471 hc_sm->igu_seg_id = igu_seg_id; 9472 hc_sm->timer_value = 0xFF; 9473 hc_sm->time_to_expire = 0xFFFFFFFF; 9474 } 9475 9476 static void 9477 bxe_map_sb_state_machines(struct hc_index_data *index_data) 9478 { 9479 /* zero out state machine indices */ 9480 9481 /* rx indices */ 9482 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID; 9483 9484 /* tx indices */ 9485 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID; 9486 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID; 9487 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID; 9488 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID; 9489 9490 /* map indices */ 9491 9492 /* rx indices */ 9493 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |= 9494 (SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT); 9495 9496 /* tx indices */ 9497 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |= 9498 (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT); 9499 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |= 9500 (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT); 9501 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |= 9502 (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT); 9503 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |= 9504 (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT); 9505 } 9506 9507 static void 9508 bxe_init_sb(struct bxe_softc *sc, 9509 bus_addr_t busaddr, 9510 int vfid, 9511 uint8_t vf_valid, 9512 int fw_sb_id, 9513 int igu_sb_id) 9514 { 9515 struct hc_status_block_data_e2 sb_data_e2; 9516 struct hc_status_block_data_e1x sb_data_e1x; 9517 struct hc_status_block_sm *hc_sm_p; 9518 uint32_t *sb_data_p; 9519 int igu_seg_id; 9520 int data_size; 9521 9522 if (CHIP_INT_MODE_IS_BC(sc)) { 9523 igu_seg_id = HC_SEG_ACCESS_NORM; 9524 } else { 9525 igu_seg_id = IGU_SEG_ACCESS_NORM; 9526 } 9527 9528 bxe_zero_fp_sb(sc, fw_sb_id); 9529 9530 if (!CHIP_IS_E1x(sc)) { 9531 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2)); 9532 sb_data_e2.common.state = SB_ENABLED; 9533 sb_data_e2.common.p_func.pf_id = SC_FUNC(sc); 9534 sb_data_e2.common.p_func.vf_id = vfid; 9535 sb_data_e2.common.p_func.vf_valid = vf_valid; 9536 sb_data_e2.common.p_func.vnic_id = SC_VN(sc); 9537 sb_data_e2.common.same_igu_sb_1b = TRUE; 9538 sb_data_e2.common.host_sb_addr.hi = U64_HI(busaddr); 9539 sb_data_e2.common.host_sb_addr.lo = U64_LO(busaddr); 9540 hc_sm_p = sb_data_e2.common.state_machine; 9541 sb_data_p = (uint32_t *)&sb_data_e2; 9542 data_size = (sizeof(struct hc_status_block_data_e2) / 9543 sizeof(uint32_t)); 9544 bxe_map_sb_state_machines(sb_data_e2.index_data); 9545 } else { 9546 memset(&sb_data_e1x, 0, sizeof(struct hc_status_block_data_e1x)); 9547 sb_data_e1x.common.state = SB_ENABLED; 9548 sb_data_e1x.common.p_func.pf_id = SC_FUNC(sc); 9549 sb_data_e1x.common.p_func.vf_id = 0xff; 9550 sb_data_e1x.common.p_func.vf_valid = FALSE; 9551 sb_data_e1x.common.p_func.vnic_id = SC_VN(sc); 9552 sb_data_e1x.common.same_igu_sb_1b = TRUE; 9553 sb_data_e1x.common.host_sb_addr.hi = U64_HI(busaddr); 9554 sb_data_e1x.common.host_sb_addr.lo = U64_LO(busaddr); 9555 hc_sm_p = sb_data_e1x.common.state_machine; 9556 sb_data_p = (uint32_t *)&sb_data_e1x; 9557 data_size = (sizeof(struct hc_status_block_data_e1x) / 9558 sizeof(uint32_t)); 9559 bxe_map_sb_state_machines(sb_data_e1x.index_data); 9560 } 9561 9562 bxe_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID], igu_sb_id, igu_seg_id); 9563 bxe_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID], igu_sb_id, igu_seg_id); 9564 9565 BLOGD(sc, DBG_LOAD, "Init FW SB %d\n", fw_sb_id); 9566 9567 /* write indices to HW - PCI guarantees endianity of regpairs */ 9568 bxe_wr_fp_sb_data(sc, fw_sb_id, sb_data_p, data_size); 9569 } 9570 9571 static inline uint8_t 9572 bxe_fp_qzone_id(struct bxe_fastpath *fp) 9573 { 9574 if (CHIP_IS_E1x(fp->sc)) { 9575 return (fp->cl_id + SC_PORT(fp->sc) * ETH_MAX_RX_CLIENTS_E1H); 9576 } else { 9577 return (fp->cl_id); 9578 } 9579 } 9580 9581 static inline uint32_t 9582 bxe_rx_ustorm_prods_offset(struct bxe_softc *sc, 9583 struct bxe_fastpath *fp) 9584 { 9585 uint32_t offset = BAR_USTRORM_INTMEM; 9586 9587 if (!CHIP_IS_E1x(sc)) { 9588 offset += USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id); 9589 } else { 9590 offset += USTORM_RX_PRODS_E1X_OFFSET(SC_PORT(sc), fp->cl_id); 9591 } 9592 9593 return (offset); 9594 } 9595 9596 static void 9597 bxe_init_eth_fp(struct bxe_softc *sc, 9598 int idx) 9599 { 9600 struct bxe_fastpath *fp = &sc->fp[idx]; 9601 uint32_t cids[ECORE_MULTI_TX_COS] = { 0 }; 9602 unsigned long q_type = 0; 9603 int cos; 9604 9605 fp->sc = sc; 9606 fp->index = idx; 9607 9608 fp->igu_sb_id = (sc->igu_base_sb + idx + CNIC_SUPPORT(sc)); 9609 fp->fw_sb_id = (sc->base_fw_ndsb + idx + CNIC_SUPPORT(sc)); 9610 9611 fp->cl_id = (CHIP_IS_E1x(sc)) ? 9612 (SC_L_ID(sc) + idx) : 9613 /* want client ID same as IGU SB ID for non-E1 */ 9614 fp->igu_sb_id; 9615 fp->cl_qzone_id = bxe_fp_qzone_id(fp); 9616 9617 /* setup sb indices */ 9618 if (!CHIP_IS_E1x(sc)) { 9619 fp->sb_index_values = fp->status_block.e2_sb->sb.index_values; 9620 fp->sb_running_index = fp->status_block.e2_sb->sb.running_index; 9621 } else { 9622 fp->sb_index_values = fp->status_block.e1x_sb->sb.index_values; 9623 fp->sb_running_index = fp->status_block.e1x_sb->sb.running_index; 9624 } 9625 9626 /* init shortcut */ 9627 fp->ustorm_rx_prods_offset = bxe_rx_ustorm_prods_offset(sc, fp); 9628 9629 fp->rx_cq_cons_sb = &fp->sb_index_values[HC_INDEX_ETH_RX_CQ_CONS]; 9630 9631 /* 9632 * XXX If multiple CoS is ever supported then each fastpath structure 9633 * will need to maintain tx producer/consumer/dma/etc values *per* CoS. 9634 */ 9635 for (cos = 0; cos < sc->max_cos; cos++) { 9636 cids[cos] = idx; 9637 } 9638 fp->tx_cons_sb = &fp->sb_index_values[HC_INDEX_ETH_TX_CQ_CONS_COS0]; 9639 9640 /* nothing more for a VF to do */ 9641 if (IS_VF(sc)) { 9642 return; 9643 } 9644 9645 bxe_init_sb(sc, fp->sb_dma.paddr, BXE_VF_ID_INVALID, FALSE, 9646 fp->fw_sb_id, fp->igu_sb_id); 9647 9648 bxe_update_fp_sb_idx(fp); 9649 9650 /* Configure Queue State object */ 9651 bit_set(&q_type, ECORE_Q_TYPE_HAS_RX); 9652 bit_set(&q_type, ECORE_Q_TYPE_HAS_TX); 9653 9654 ecore_init_queue_obj(sc, 9655 &sc->sp_objs[idx].q_obj, 9656 fp->cl_id, 9657 cids, 9658 sc->max_cos, 9659 SC_FUNC(sc), 9660 BXE_SP(sc, q_rdata), 9661 BXE_SP_MAPPING(sc, q_rdata), 9662 q_type); 9663 9664 /* configure classification DBs */ 9665 ecore_init_mac_obj(sc, 9666 &sc->sp_objs[idx].mac_obj, 9667 fp->cl_id, 9668 idx, 9669 SC_FUNC(sc), 9670 BXE_SP(sc, mac_rdata), 9671 BXE_SP_MAPPING(sc, mac_rdata), 9672 ECORE_FILTER_MAC_PENDING, 9673 &sc->sp_state, 9674 ECORE_OBJ_TYPE_RX_TX, 9675 &sc->macs_pool); 9676 9677 BLOGD(sc, DBG_LOAD, "fp[%d]: sb=%p cl_id=%d fw_sb=%d igu_sb=%d\n", 9678 idx, fp->status_block.e2_sb, fp->cl_id, fp->fw_sb_id, fp->igu_sb_id); 9679 } 9680 9681 static inline void 9682 bxe_update_rx_prod(struct bxe_softc *sc, 9683 struct bxe_fastpath *fp, 9684 uint16_t rx_bd_prod, 9685 uint16_t rx_cq_prod, 9686 uint16_t rx_sge_prod) 9687 { 9688 struct ustorm_eth_rx_producers rx_prods = { 0 }; 9689 uint32_t i; 9690 9691 /* update producers */ 9692 rx_prods.bd_prod = rx_bd_prod; 9693 rx_prods.cqe_prod = rx_cq_prod; 9694 rx_prods.sge_prod = rx_sge_prod; 9695 9696 /* 9697 * Make sure that the BD and SGE data is updated before updating the 9698 * producers since FW might read the BD/SGE right after the producer 9699 * is updated. 9700 * This is only applicable for weak-ordered memory model archs such 9701 * as IA-64. The following barrier is also mandatory since FW will 9702 * assumes BDs must have buffers. 9703 */ 9704 wmb(); 9705 9706 for (i = 0; i < (sizeof(rx_prods) / 4); i++) { 9707 REG_WR(sc, 9708 (fp->ustorm_rx_prods_offset + (i * 4)), 9709 ((uint32_t *)&rx_prods)[i]); 9710 } 9711 9712 wmb(); /* keep prod updates ordered */ 9713 9714 BLOGD(sc, DBG_RX, 9715 "RX fp[%d]: wrote prods bd_prod=%u cqe_prod=%u sge_prod=%u\n", 9716 fp->index, rx_bd_prod, rx_cq_prod, rx_sge_prod); 9717 } 9718 9719 static void 9720 bxe_init_rx_rings(struct bxe_softc *sc) 9721 { 9722 struct bxe_fastpath *fp; 9723 int i; 9724 9725 for (i = 0; i < sc->num_queues; i++) { 9726 fp = &sc->fp[i]; 9727 9728 fp->rx_bd_cons = 0; 9729 9730 /* 9731 * Activate the BD ring... 9732 * Warning, this will generate an interrupt (to the TSTORM) 9733 * so this can only be done after the chip is initialized 9734 */ 9735 bxe_update_rx_prod(sc, fp, 9736 fp->rx_bd_prod, 9737 fp->rx_cq_prod, 9738 fp->rx_sge_prod); 9739 9740 if (i != 0) { 9741 continue; 9742 } 9743 9744 if (CHIP_IS_E1(sc)) { 9745 REG_WR(sc, 9746 (BAR_USTRORM_INTMEM + 9747 USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(SC_FUNC(sc))), 9748 U64_LO(fp->rcq_dma.paddr)); 9749 REG_WR(sc, 9750 (BAR_USTRORM_INTMEM + 9751 USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(SC_FUNC(sc)) + 4), 9752 U64_HI(fp->rcq_dma.paddr)); 9753 } 9754 } 9755 } 9756 9757 static void 9758 bxe_init_tx_ring_one(struct bxe_fastpath *fp) 9759 { 9760 SET_FLAG(fp->tx_db.data.header.data, DOORBELL_HDR_T_DB_TYPE, 1); 9761 fp->tx_db.data.zero_fill1 = 0; 9762 fp->tx_db.data.prod = 0; 9763 9764 fp->tx_pkt_prod = 0; 9765 fp->tx_pkt_cons = 0; 9766 fp->tx_bd_prod = 0; 9767 fp->tx_bd_cons = 0; 9768 fp->eth_q_stats.tx_pkts = 0; 9769 } 9770 9771 static inline void 9772 bxe_init_tx_rings(struct bxe_softc *sc) 9773 { 9774 int i; 9775 9776 for (i = 0; i < sc->num_queues; i++) { 9777 bxe_init_tx_ring_one(&sc->fp[i]); 9778 } 9779 } 9780 9781 static void 9782 bxe_init_def_sb(struct bxe_softc *sc) 9783 { 9784 struct host_sp_status_block *def_sb = sc->def_sb; 9785 bus_addr_t mapping = sc->def_sb_dma.paddr; 9786 int igu_sp_sb_index; 9787 int igu_seg_id; 9788 int port = SC_PORT(sc); 9789 int func = SC_FUNC(sc); 9790 int reg_offset, reg_offset_en5; 9791 uint64_t section; 9792 int index, sindex; 9793 struct hc_sp_status_block_data sp_sb_data; 9794 9795 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data)); 9796 9797 if (CHIP_INT_MODE_IS_BC(sc)) { 9798 igu_sp_sb_index = DEF_SB_IGU_ID; 9799 igu_seg_id = HC_SEG_ACCESS_DEF; 9800 } else { 9801 igu_sp_sb_index = sc->igu_dsb_id; 9802 igu_seg_id = IGU_SEG_ACCESS_DEF; 9803 } 9804 9805 /* attentions */ 9806 section = ((uint64_t)mapping + 9807 offsetof(struct host_sp_status_block, atten_status_block)); 9808 def_sb->atten_status_block.status_block_id = igu_sp_sb_index; 9809 sc->attn_state = 0; 9810 9811 reg_offset = (port) ? 9812 MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : 9813 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0; 9814 reg_offset_en5 = (port) ? 9815 MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 : 9816 MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0; 9817 9818 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) { 9819 /* take care of sig[0]..sig[4] */ 9820 for (sindex = 0; sindex < 4; sindex++) { 9821 sc->attn_group[index].sig[sindex] = 9822 REG_RD(sc, (reg_offset + (sindex * 0x4) + (0x10 * index))); 9823 } 9824 9825 if (!CHIP_IS_E1x(sc)) { 9826 /* 9827 * enable5 is separate from the rest of the registers, 9828 * and the address skip is 4 and not 16 between the 9829 * different groups 9830 */ 9831 sc->attn_group[index].sig[4] = 9832 REG_RD(sc, (reg_offset_en5 + (0x4 * index))); 9833 } else { 9834 sc->attn_group[index].sig[4] = 0; 9835 } 9836 } 9837 9838 if (sc->devinfo.int_block == INT_BLOCK_HC) { 9839 reg_offset = (port) ? 9840 HC_REG_ATTN_MSG1_ADDR_L : 9841 HC_REG_ATTN_MSG0_ADDR_L; 9842 REG_WR(sc, reg_offset, U64_LO(section)); 9843 REG_WR(sc, (reg_offset + 4), U64_HI(section)); 9844 } else if (!CHIP_IS_E1x(sc)) { 9845 REG_WR(sc, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section)); 9846 REG_WR(sc, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section)); 9847 } 9848 9849 section = ((uint64_t)mapping + 9850 offsetof(struct host_sp_status_block, sp_sb)); 9851 9852 bxe_zero_sp_sb(sc); 9853 9854 /* PCI guarantees endianity of regpair */ 9855 sp_sb_data.state = SB_ENABLED; 9856 sp_sb_data.host_sb_addr.lo = U64_LO(section); 9857 sp_sb_data.host_sb_addr.hi = U64_HI(section); 9858 sp_sb_data.igu_sb_id = igu_sp_sb_index; 9859 sp_sb_data.igu_seg_id = igu_seg_id; 9860 sp_sb_data.p_func.pf_id = func; 9861 sp_sb_data.p_func.vnic_id = SC_VN(sc); 9862 sp_sb_data.p_func.vf_id = 0xff; 9863 9864 bxe_wr_sp_sb_data(sc, &sp_sb_data); 9865 9866 bxe_ack_sb(sc, sc->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0); 9867 } 9868 9869 static void 9870 bxe_init_sp_ring(struct bxe_softc *sc) 9871 { 9872 atomic_store_rel_long(&sc->cq_spq_left, MAX_SPQ_PENDING); 9873 sc->spq_prod_idx = 0; 9874 sc->dsb_sp_prod = &sc->def_sb->sp_sb.index_values[HC_SP_INDEX_ETH_DEF_CONS]; 9875 sc->spq_prod_bd = sc->spq; 9876 sc->spq_last_bd = (sc->spq_prod_bd + MAX_SP_DESC_CNT); 9877 } 9878 9879 static void 9880 bxe_init_eq_ring(struct bxe_softc *sc) 9881 { 9882 union event_ring_elem *elem; 9883 int i; 9884 9885 for (i = 1; i <= NUM_EQ_PAGES; i++) { 9886 elem = &sc->eq[EQ_DESC_CNT_PAGE * i - 1]; 9887 9888 elem->next_page.addr.hi = htole32(U64_HI(sc->eq_dma.paddr + 9889 BCM_PAGE_SIZE * 9890 (i % NUM_EQ_PAGES))); 9891 elem->next_page.addr.lo = htole32(U64_LO(sc->eq_dma.paddr + 9892 BCM_PAGE_SIZE * 9893 (i % NUM_EQ_PAGES))); 9894 } 9895 9896 sc->eq_cons = 0; 9897 sc->eq_prod = NUM_EQ_DESC; 9898 sc->eq_cons_sb = &sc->def_sb->sp_sb.index_values[HC_SP_INDEX_EQ_CONS]; 9899 9900 atomic_store_rel_long(&sc->eq_spq_left, 9901 (min((MAX_SP_DESC_CNT - MAX_SPQ_PENDING), 9902 NUM_EQ_DESC) - 1)); 9903 } 9904 9905 static void 9906 bxe_init_internal_common(struct bxe_softc *sc) 9907 { 9908 int i; 9909 9910 /* 9911 * Zero this manually as its initialization is currently missing 9912 * in the initTool. 9913 */ 9914 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++) { 9915 REG_WR(sc, 9916 (BAR_USTRORM_INTMEM + USTORM_AGG_DATA_OFFSET + (i * 4)), 9917 0); 9918 } 9919 9920 if (!CHIP_IS_E1x(sc)) { 9921 REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET), 9922 CHIP_INT_MODE_IS_BC(sc) ? HC_IGU_BC_MODE : HC_IGU_NBC_MODE); 9923 } 9924 } 9925 9926 static void 9927 bxe_init_internal(struct bxe_softc *sc, 9928 uint32_t load_code) 9929 { 9930 switch (load_code) { 9931 case FW_MSG_CODE_DRV_LOAD_COMMON: 9932 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP: 9933 bxe_init_internal_common(sc); 9934 /* no break */ 9935 9936 case FW_MSG_CODE_DRV_LOAD_PORT: 9937 /* nothing to do */ 9938 /* no break */ 9939 9940 case FW_MSG_CODE_DRV_LOAD_FUNCTION: 9941 /* internal memory per function is initialized inside bxe_pf_init */ 9942 break; 9943 9944 default: 9945 BLOGE(sc, "Unknown load_code (0x%x) from MCP\n", load_code); 9946 break; 9947 } 9948 } 9949 9950 static void 9951 storm_memset_func_cfg(struct bxe_softc *sc, 9952 struct tstorm_eth_function_common_config *tcfg, 9953 uint16_t abs_fid) 9954 { 9955 uint32_t addr; 9956 size_t size; 9957 9958 addr = (BAR_TSTRORM_INTMEM + 9959 TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid)); 9960 size = sizeof(struct tstorm_eth_function_common_config); 9961 ecore_storm_memset_struct(sc, addr, size, (uint32_t *)tcfg); 9962 } 9963 9964 static void 9965 bxe_func_init(struct bxe_softc *sc, 9966 struct bxe_func_init_params *p) 9967 { 9968 struct tstorm_eth_function_common_config tcfg = { 0 }; 9969 9970 if (CHIP_IS_E1x(sc)) { 9971 storm_memset_func_cfg(sc, &tcfg, p->func_id); 9972 } 9973 9974 /* Enable the function in the FW */ 9975 storm_memset_vf_to_pf(sc, p->func_id, p->pf_id); 9976 storm_memset_func_en(sc, p->func_id, 1); 9977 9978 /* spq */ 9979 if (p->func_flgs & FUNC_FLG_SPQ) { 9980 storm_memset_spq_addr(sc, p->spq_map, p->func_id); 9981 REG_WR(sc, 9982 (XSEM_REG_FAST_MEMORY + XSTORM_SPQ_PROD_OFFSET(p->func_id)), 9983 p->spq_prod); 9984 } 9985 } 9986 9987 /* 9988 * Calculates the sum of vn_min_rates. 9989 * It's needed for further normalizing of the min_rates. 9990 * Returns: 9991 * sum of vn_min_rates. 9992 * or 9993 * 0 - if all the min_rates are 0. 9994 * In the later case fainess algorithm should be deactivated. 9995 * If all min rates are not zero then those that are zeroes will be set to 1. 9996 */ 9997 static void 9998 bxe_calc_vn_min(struct bxe_softc *sc, 9999 struct cmng_init_input *input) 10000 { 10001 uint32_t vn_cfg; 10002 uint32_t vn_min_rate; 10003 int all_zero = 1; 10004 int vn; 10005 10006 for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) { 10007 vn_cfg = sc->devinfo.mf_info.mf_config[vn]; 10008 vn_min_rate = (((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >> 10009 FUNC_MF_CFG_MIN_BW_SHIFT) * 100); 10010 10011 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) { 10012 /* skip hidden VNs */ 10013 vn_min_rate = 0; 10014 } else if (!vn_min_rate) { 10015 /* If min rate is zero - set it to 100 */ 10016 vn_min_rate = DEF_MIN_RATE; 10017 } else { 10018 all_zero = 0; 10019 } 10020 10021 input->vnic_min_rate[vn] = vn_min_rate; 10022 } 10023 10024 /* if ETS or all min rates are zeros - disable fairness */ 10025 if (BXE_IS_ETS_ENABLED(sc)) { 10026 input->flags.cmng_enables &= ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN; 10027 BLOGD(sc, DBG_LOAD, "Fairness disabled (ETS)\n"); 10028 } else if (all_zero) { 10029 input->flags.cmng_enables &= ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN; 10030 BLOGD(sc, DBG_LOAD, 10031 "Fariness disabled (all MIN values are zeroes)\n"); 10032 } else { 10033 input->flags.cmng_enables |= CMNG_FLAGS_PER_PORT_FAIRNESS_VN; 10034 } 10035 } 10036 10037 static inline uint16_t 10038 bxe_extract_max_cfg(struct bxe_softc *sc, 10039 uint32_t mf_cfg) 10040 { 10041 uint16_t max_cfg = ((mf_cfg & FUNC_MF_CFG_MAX_BW_MASK) >> 10042 FUNC_MF_CFG_MAX_BW_SHIFT); 10043 10044 if (!max_cfg) { 10045 BLOGD(sc, DBG_LOAD, "Max BW configured to 0 - using 100 instead\n"); 10046 max_cfg = 100; 10047 } 10048 10049 return (max_cfg); 10050 } 10051 10052 static void 10053 bxe_calc_vn_max(struct bxe_softc *sc, 10054 int vn, 10055 struct cmng_init_input *input) 10056 { 10057 uint16_t vn_max_rate; 10058 uint32_t vn_cfg = sc->devinfo.mf_info.mf_config[vn]; 10059 uint32_t max_cfg; 10060 10061 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) { 10062 vn_max_rate = 0; 10063 } else { 10064 max_cfg = bxe_extract_max_cfg(sc, vn_cfg); 10065 10066 if (IS_MF_SI(sc)) { 10067 /* max_cfg in percents of linkspeed */ 10068 vn_max_rate = ((sc->link_vars.line_speed * max_cfg) / 100); 10069 } else { /* SD modes */ 10070 /* max_cfg is absolute in 100Mb units */ 10071 vn_max_rate = (max_cfg * 100); 10072 } 10073 } 10074 10075 BLOGD(sc, DBG_LOAD, "vn %d: vn_max_rate %d\n", vn, vn_max_rate); 10076 10077 input->vnic_max_rate[vn] = vn_max_rate; 10078 } 10079 10080 static void 10081 bxe_cmng_fns_init(struct bxe_softc *sc, 10082 uint8_t read_cfg, 10083 uint8_t cmng_type) 10084 { 10085 struct cmng_init_input input; 10086 int vn; 10087 10088 memset(&input, 0, sizeof(struct cmng_init_input)); 10089 10090 input.port_rate = sc->link_vars.line_speed; 10091 10092 if (cmng_type == CMNG_FNS_MINMAX) { 10093 /* read mf conf from shmem */ 10094 if (read_cfg) { 10095 bxe_read_mf_cfg(sc); 10096 } 10097 10098 /* get VN min rate and enable fairness if not 0 */ 10099 bxe_calc_vn_min(sc, &input); 10100 10101 /* get VN max rate */ 10102 if (sc->port.pmf) { 10103 for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) { 10104 bxe_calc_vn_max(sc, vn, &input); 10105 } 10106 } 10107 10108 /* always enable rate shaping and fairness */ 10109 input.flags.cmng_enables |= CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN; 10110 10111 ecore_init_cmng(&input, &sc->cmng); 10112 return; 10113 } 10114 10115 /* rate shaping and fairness are disabled */ 10116 BLOGD(sc, DBG_LOAD, "rate shaping and fairness have been disabled\n"); 10117 } 10118 10119 static int 10120 bxe_get_cmng_fns_mode(struct bxe_softc *sc) 10121 { 10122 if (CHIP_REV_IS_SLOW(sc)) { 10123 return (CMNG_FNS_NONE); 10124 } 10125 10126 if (IS_MF(sc)) { 10127 return (CMNG_FNS_MINMAX); 10128 } 10129 10130 return (CMNG_FNS_NONE); 10131 } 10132 10133 static void 10134 storm_memset_cmng(struct bxe_softc *sc, 10135 struct cmng_init *cmng, 10136 uint8_t port) 10137 { 10138 int vn; 10139 int func; 10140 uint32_t addr; 10141 size_t size; 10142 10143 addr = (BAR_XSTRORM_INTMEM + 10144 XSTORM_CMNG_PER_PORT_VARS_OFFSET(port)); 10145 size = sizeof(struct cmng_struct_per_port); 10146 ecore_storm_memset_struct(sc, addr, size, (uint32_t *)&cmng->port); 10147 10148 for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) { 10149 func = func_by_vn(sc, vn); 10150 10151 addr = (BAR_XSTRORM_INTMEM + 10152 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func)); 10153 size = sizeof(struct rate_shaping_vars_per_vn); 10154 ecore_storm_memset_struct(sc, addr, size, 10155 (uint32_t *)&cmng->vnic.vnic_max_rate[vn]); 10156 10157 addr = (BAR_XSTRORM_INTMEM + 10158 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func)); 10159 size = sizeof(struct fairness_vars_per_vn); 10160 ecore_storm_memset_struct(sc, addr, size, 10161 (uint32_t *)&cmng->vnic.vnic_min_rate[vn]); 10162 } 10163 } 10164 10165 static void 10166 bxe_pf_init(struct bxe_softc *sc) 10167 { 10168 struct bxe_func_init_params func_init = { 0 }; 10169 struct event_ring_data eq_data = { { 0 } }; 10170 uint16_t flags; 10171 10172 if (!CHIP_IS_E1x(sc)) { 10173 /* reset IGU PF statistics: MSIX + ATTN */ 10174 /* PF */ 10175 REG_WR(sc, 10176 (IGU_REG_STATISTIC_NUM_MESSAGE_SENT + 10177 (BXE_IGU_STAS_MSG_VF_CNT * 4) + 10178 ((CHIP_IS_MODE_4_PORT(sc) ? SC_FUNC(sc) : SC_VN(sc)) * 4)), 10179 0); 10180 /* ATTN */ 10181 REG_WR(sc, 10182 (IGU_REG_STATISTIC_NUM_MESSAGE_SENT + 10183 (BXE_IGU_STAS_MSG_VF_CNT * 4) + 10184 (BXE_IGU_STAS_MSG_PF_CNT * 4) + 10185 ((CHIP_IS_MODE_4_PORT(sc) ? SC_FUNC(sc) : SC_VN(sc)) * 4)), 10186 0); 10187 } 10188 10189 /* function setup flags */ 10190 flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ); 10191 10192 /* 10193 * This flag is relevant for E1x only. 10194 * E2 doesn't have a TPA configuration in a function level. 10195 */ 10196 flags |= (if_getcapenable(sc->ifp) & IFCAP_LRO) ? FUNC_FLG_TPA : 0; 10197 10198 func_init.func_flgs = flags; 10199 func_init.pf_id = SC_FUNC(sc); 10200 func_init.func_id = SC_FUNC(sc); 10201 func_init.spq_map = sc->spq_dma.paddr; 10202 func_init.spq_prod = sc->spq_prod_idx; 10203 10204 bxe_func_init(sc, &func_init); 10205 10206 memset(&sc->cmng, 0, sizeof(struct cmng_struct_per_port)); 10207 10208 /* 10209 * Congestion management values depend on the link rate. 10210 * There is no active link so initial link rate is set to 10Gbps. 10211 * When the link comes up the congestion management values are 10212 * re-calculated according to the actual link rate. 10213 */ 10214 sc->link_vars.line_speed = SPEED_10000; 10215 bxe_cmng_fns_init(sc, TRUE, bxe_get_cmng_fns_mode(sc)); 10216 10217 /* Only the PMF sets the HW */ 10218 if (sc->port.pmf) { 10219 storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc)); 10220 } 10221 10222 /* init Event Queue - PCI bus guarantees correct endainity */ 10223 eq_data.base_addr.hi = U64_HI(sc->eq_dma.paddr); 10224 eq_data.base_addr.lo = U64_LO(sc->eq_dma.paddr); 10225 eq_data.producer = sc->eq_prod; 10226 eq_data.index_id = HC_SP_INDEX_EQ_CONS; 10227 eq_data.sb_id = DEF_SB_ID; 10228 storm_memset_eq_data(sc, &eq_data, SC_FUNC(sc)); 10229 } 10230 10231 static void 10232 bxe_hc_int_enable(struct bxe_softc *sc) 10233 { 10234 int port = SC_PORT(sc); 10235 uint32_t addr = (port) ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0; 10236 uint32_t val = REG_RD(sc, addr); 10237 uint8_t msix = (sc->interrupt_mode == INTR_MODE_MSIX) ? TRUE : FALSE; 10238 uint8_t single_msix = ((sc->interrupt_mode == INTR_MODE_MSIX) && 10239 (sc->intr_count == 1)) ? TRUE : FALSE; 10240 uint8_t msi = (sc->interrupt_mode == INTR_MODE_MSI) ? TRUE : FALSE; 10241 10242 if (msix) { 10243 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | 10244 HC_CONFIG_0_REG_INT_LINE_EN_0); 10245 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | 10246 HC_CONFIG_0_REG_ATTN_BIT_EN_0); 10247 if (single_msix) { 10248 val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0; 10249 } 10250 } else if (msi) { 10251 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0; 10252 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | 10253 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | 10254 HC_CONFIG_0_REG_ATTN_BIT_EN_0); 10255 } else { 10256 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | 10257 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | 10258 HC_CONFIG_0_REG_INT_LINE_EN_0 | 10259 HC_CONFIG_0_REG_ATTN_BIT_EN_0); 10260 10261 if (!CHIP_IS_E1(sc)) { 10262 BLOGD(sc, DBG_INTR, "write %x to HC %d (addr 0x%x)\n", 10263 val, port, addr); 10264 10265 REG_WR(sc, addr, val); 10266 10267 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0; 10268 } 10269 } 10270 10271 if (CHIP_IS_E1(sc)) { 10272 REG_WR(sc, (HC_REG_INT_MASK + port*4), 0x1FFFF); 10273 } 10274 10275 BLOGD(sc, DBG_INTR, "write %x to HC %d (addr 0x%x) mode %s\n", 10276 val, port, addr, ((msix) ? "MSI-X" : ((msi) ? "MSI" : "INTx"))); 10277 10278 REG_WR(sc, addr, val); 10279 10280 /* ensure that HC_CONFIG is written before leading/trailing edge config */ 10281 mb(); 10282 10283 if (!CHIP_IS_E1(sc)) { 10284 /* init leading/trailing edge */ 10285 if (IS_MF(sc)) { 10286 val = (0xee0f | (1 << (SC_VN(sc) + 4))); 10287 if (sc->port.pmf) { 10288 /* enable nig and gpio3 attention */ 10289 val |= 0x1100; 10290 } 10291 } else { 10292 val = 0xffff; 10293 } 10294 10295 REG_WR(sc, (HC_REG_TRAILING_EDGE_0 + port*8), val); 10296 REG_WR(sc, (HC_REG_LEADING_EDGE_0 + port*8), val); 10297 } 10298 10299 /* make sure that interrupts are indeed enabled from here on */ 10300 mb(); 10301 } 10302 10303 static void 10304 bxe_igu_int_enable(struct bxe_softc *sc) 10305 { 10306 uint32_t val; 10307 uint8_t msix = (sc->interrupt_mode == INTR_MODE_MSIX) ? TRUE : FALSE; 10308 uint8_t single_msix = ((sc->interrupt_mode == INTR_MODE_MSIX) && 10309 (sc->intr_count == 1)) ? TRUE : FALSE; 10310 uint8_t msi = (sc->interrupt_mode == INTR_MODE_MSI) ? TRUE : FALSE; 10311 10312 val = REG_RD(sc, IGU_REG_PF_CONFIGURATION); 10313 10314 if (msix) { 10315 val &= ~(IGU_PF_CONF_INT_LINE_EN | 10316 IGU_PF_CONF_SINGLE_ISR_EN); 10317 val |= (IGU_PF_CONF_MSI_MSIX_EN | 10318 IGU_PF_CONF_ATTN_BIT_EN); 10319 if (single_msix) { 10320 val |= IGU_PF_CONF_SINGLE_ISR_EN; 10321 } 10322 } else if (msi) { 10323 val &= ~IGU_PF_CONF_INT_LINE_EN; 10324 val |= (IGU_PF_CONF_MSI_MSIX_EN | 10325 IGU_PF_CONF_ATTN_BIT_EN | 10326 IGU_PF_CONF_SINGLE_ISR_EN); 10327 } else { 10328 val &= ~IGU_PF_CONF_MSI_MSIX_EN; 10329 val |= (IGU_PF_CONF_INT_LINE_EN | 10330 IGU_PF_CONF_ATTN_BIT_EN | 10331 IGU_PF_CONF_SINGLE_ISR_EN); 10332 } 10333 10334 /* clean previous status - need to configure igu prior to ack*/ 10335 if ((!msix) || single_msix) { 10336 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val); 10337 bxe_ack_int(sc); 10338 } 10339 10340 val |= IGU_PF_CONF_FUNC_EN; 10341 10342 BLOGD(sc, DBG_INTR, "write 0x%x to IGU mode %s\n", 10343 val, ((msix) ? "MSI-X" : ((msi) ? "MSI" : "INTx"))); 10344 10345 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val); 10346 10347 mb(); 10348 10349 /* init leading/trailing edge */ 10350 if (IS_MF(sc)) { 10351 val = (0xee0f | (1 << (SC_VN(sc) + 4))); 10352 if (sc->port.pmf) { 10353 /* enable nig and gpio3 attention */ 10354 val |= 0x1100; 10355 } 10356 } else { 10357 val = 0xffff; 10358 } 10359 10360 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, val); 10361 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, val); 10362 10363 /* make sure that interrupts are indeed enabled from here on */ 10364 mb(); 10365 } 10366 10367 static void 10368 bxe_int_enable(struct bxe_softc *sc) 10369 { 10370 if (sc->devinfo.int_block == INT_BLOCK_HC) { 10371 bxe_hc_int_enable(sc); 10372 } else { 10373 bxe_igu_int_enable(sc); 10374 } 10375 } 10376 10377 static void 10378 bxe_hc_int_disable(struct bxe_softc *sc) 10379 { 10380 int port = SC_PORT(sc); 10381 uint32_t addr = (port) ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0; 10382 uint32_t val = REG_RD(sc, addr); 10383 10384 /* 10385 * In E1 we must use only PCI configuration space to disable MSI/MSIX 10386 * capablility. It's forbidden to disable IGU_PF_CONF_MSI_MSIX_EN in HC 10387 * block 10388 */ 10389 if (CHIP_IS_E1(sc)) { 10390 /* 10391 * Since IGU_PF_CONF_MSI_MSIX_EN still always on use mask register 10392 * to prevent from HC sending interrupts after we exit the function 10393 */ 10394 REG_WR(sc, (HC_REG_INT_MASK + port*4), 0); 10395 10396 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | 10397 HC_CONFIG_0_REG_INT_LINE_EN_0 | 10398 HC_CONFIG_0_REG_ATTN_BIT_EN_0); 10399 } else { 10400 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | 10401 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | 10402 HC_CONFIG_0_REG_INT_LINE_EN_0 | 10403 HC_CONFIG_0_REG_ATTN_BIT_EN_0); 10404 } 10405 10406 BLOGD(sc, DBG_INTR, "write %x to HC %d (addr 0x%x)\n", val, port, addr); 10407 10408 /* flush all outstanding writes */ 10409 mb(); 10410 10411 REG_WR(sc, addr, val); 10412 if (REG_RD(sc, addr) != val) { 10413 BLOGE(sc, "proper val not read from HC IGU!\n"); 10414 } 10415 } 10416 10417 static void 10418 bxe_igu_int_disable(struct bxe_softc *sc) 10419 { 10420 uint32_t val = REG_RD(sc, IGU_REG_PF_CONFIGURATION); 10421 10422 val &= ~(IGU_PF_CONF_MSI_MSIX_EN | 10423 IGU_PF_CONF_INT_LINE_EN | 10424 IGU_PF_CONF_ATTN_BIT_EN); 10425 10426 BLOGD(sc, DBG_INTR, "write %x to IGU\n", val); 10427 10428 /* flush all outstanding writes */ 10429 mb(); 10430 10431 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val); 10432 if (REG_RD(sc, IGU_REG_PF_CONFIGURATION) != val) { 10433 BLOGE(sc, "proper val not read from IGU!\n"); 10434 } 10435 } 10436 10437 static void 10438 bxe_int_disable(struct bxe_softc *sc) 10439 { 10440 if (sc->devinfo.int_block == INT_BLOCK_HC) { 10441 bxe_hc_int_disable(sc); 10442 } else { 10443 bxe_igu_int_disable(sc); 10444 } 10445 } 10446 10447 static void 10448 bxe_nic_init(struct bxe_softc *sc, 10449 int load_code) 10450 { 10451 int i; 10452 10453 for (i = 0; i < sc->num_queues; i++) { 10454 bxe_init_eth_fp(sc, i); 10455 } 10456 10457 rmb(); /* ensure status block indices were read */ 10458 10459 bxe_init_rx_rings(sc); 10460 bxe_init_tx_rings(sc); 10461 10462 if (IS_VF(sc)) { 10463 return; 10464 } 10465 10466 /* initialize MOD_ABS interrupts */ 10467 elink_init_mod_abs_int(sc, &sc->link_vars, 10468 sc->devinfo.chip_id, 10469 sc->devinfo.shmem_base, 10470 sc->devinfo.shmem2_base, 10471 SC_PORT(sc)); 10472 10473 bxe_init_def_sb(sc); 10474 bxe_update_dsb_idx(sc); 10475 bxe_init_sp_ring(sc); 10476 bxe_init_eq_ring(sc); 10477 bxe_init_internal(sc, load_code); 10478 bxe_pf_init(sc); 10479 bxe_stats_init(sc); 10480 10481 /* flush all before enabling interrupts */ 10482 mb(); 10483 10484 bxe_int_enable(sc); 10485 10486 /* check for SPIO5 */ 10487 bxe_attn_int_deasserted0(sc, 10488 REG_RD(sc, 10489 (MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + 10490 SC_PORT(sc)*4)) & 10491 AEU_INPUTS_ATTN_BITS_SPIO5); 10492 } 10493 10494 static inline void 10495 bxe_init_objs(struct bxe_softc *sc) 10496 { 10497 /* mcast rules must be added to tx if tx switching is enabled */ 10498 ecore_obj_type o_type = 10499 (sc->flags & BXE_TX_SWITCHING) ? ECORE_OBJ_TYPE_RX_TX : 10500 ECORE_OBJ_TYPE_RX; 10501 10502 /* RX_MODE controlling object */ 10503 ecore_init_rx_mode_obj(sc, &sc->rx_mode_obj); 10504 10505 /* multicast configuration controlling object */ 10506 ecore_init_mcast_obj(sc, 10507 &sc->mcast_obj, 10508 sc->fp[0].cl_id, 10509 sc->fp[0].index, 10510 SC_FUNC(sc), 10511 SC_FUNC(sc), 10512 BXE_SP(sc, mcast_rdata), 10513 BXE_SP_MAPPING(sc, mcast_rdata), 10514 ECORE_FILTER_MCAST_PENDING, 10515 &sc->sp_state, 10516 o_type); 10517 10518 /* Setup CAM credit pools */ 10519 ecore_init_mac_credit_pool(sc, 10520 &sc->macs_pool, 10521 SC_FUNC(sc), 10522 CHIP_IS_E1x(sc) ? VNICS_PER_PORT(sc) : 10523 VNICS_PER_PATH(sc)); 10524 10525 ecore_init_vlan_credit_pool(sc, 10526 &sc->vlans_pool, 10527 SC_ABS_FUNC(sc) >> 1, 10528 CHIP_IS_E1x(sc) ? VNICS_PER_PORT(sc) : 10529 VNICS_PER_PATH(sc)); 10530 10531 /* RSS configuration object */ 10532 ecore_init_rss_config_obj(sc, 10533 &sc->rss_conf_obj, 10534 sc->fp[0].cl_id, 10535 sc->fp[0].index, 10536 SC_FUNC(sc), 10537 SC_FUNC(sc), 10538 BXE_SP(sc, rss_rdata), 10539 BXE_SP_MAPPING(sc, rss_rdata), 10540 ECORE_FILTER_RSS_CONF_PENDING, 10541 &sc->sp_state, ECORE_OBJ_TYPE_RX); 10542 } 10543 10544 /* 10545 * Initialize the function. This must be called before sending CLIENT_SETUP 10546 * for the first client. 10547 */ 10548 static inline int 10549 bxe_func_start(struct bxe_softc *sc) 10550 { 10551 struct ecore_func_state_params func_params = { NULL }; 10552 struct ecore_func_start_params *start_params = &func_params.params.start; 10553 10554 /* Prepare parameters for function state transitions */ 10555 bit_set(&func_params.ramrod_flags, RAMROD_COMP_WAIT); 10556 10557 func_params.f_obj = &sc->func_obj; 10558 func_params.cmd = ECORE_F_CMD_START; 10559 10560 /* Function parameters */ 10561 start_params->mf_mode = sc->devinfo.mf_info.mf_mode; 10562 start_params->sd_vlan_tag = OVLAN(sc); 10563 10564 if (CHIP_IS_E2(sc) || CHIP_IS_E3(sc)) { 10565 start_params->network_cos_mode = STATIC_COS; 10566 } else { /* CHIP_IS_E1X */ 10567 start_params->network_cos_mode = FW_WRR; 10568 } 10569 10570 //start_params->gre_tunnel_mode = 0; 10571 //start_params->gre_tunnel_rss = 0; 10572 10573 return (ecore_func_state_change(sc, &func_params)); 10574 } 10575 10576 static int 10577 bxe_set_power_state(struct bxe_softc *sc, 10578 uint8_t state) 10579 { 10580 uint16_t pmcsr; 10581 10582 /* If there is no power capability, silently succeed */ 10583 if (!(sc->devinfo.pcie_cap_flags & BXE_PM_CAPABLE_FLAG)) { 10584 BLOGW(sc, "No power capability\n"); 10585 return (0); 10586 } 10587 10588 pmcsr = pci_read_config(sc->dev, 10589 (sc->devinfo.pcie_pm_cap_reg + PCIR_POWER_STATUS), 10590 2); 10591 10592 switch (state) { 10593 case PCI_PM_D0: 10594 pci_write_config(sc->dev, 10595 (sc->devinfo.pcie_pm_cap_reg + PCIR_POWER_STATUS), 10596 ((pmcsr & ~PCIM_PSTAT_DMASK) | PCIM_PSTAT_PME), 2); 10597 10598 if (pmcsr & PCIM_PSTAT_DMASK) { 10599 /* delay required during transition out of D3hot */ 10600 DELAY(20000); 10601 } 10602 10603 break; 10604 10605 case PCI_PM_D3hot: 10606 /* XXX if there are other clients above don't shut down the power */ 10607 10608 /* don't shut down the power for emulation and FPGA */ 10609 if (CHIP_REV_IS_SLOW(sc)) { 10610 return (0); 10611 } 10612 10613 pmcsr &= ~PCIM_PSTAT_DMASK; 10614 pmcsr |= PCIM_PSTAT_D3; 10615 10616 if (sc->wol) { 10617 pmcsr |= PCIM_PSTAT_PMEENABLE; 10618 } 10619 10620 pci_write_config(sc->dev, 10621 (sc->devinfo.pcie_pm_cap_reg + PCIR_POWER_STATUS), 10622 pmcsr, 4); 10623 10624 /* 10625 * No more memory access after this point until device is brought back 10626 * to D0 state. 10627 */ 10628 break; 10629 10630 default: 10631 BLOGE(sc, "Can't support PCI power state = 0x%x pmcsr 0x%x\n", 10632 state, pmcsr); 10633 return (-1); 10634 } 10635 10636 return (0); 10637 } 10638 10639 10640 /* return true if succeeded to acquire the lock */ 10641 static uint8_t 10642 bxe_trylock_hw_lock(struct bxe_softc *sc, 10643 uint32_t resource) 10644 { 10645 uint32_t lock_status; 10646 uint32_t resource_bit = (1 << resource); 10647 int func = SC_FUNC(sc); 10648 uint32_t hw_lock_control_reg; 10649 10650 BLOGD(sc, DBG_LOAD, "Trying to take a resource lock 0x%x\n", resource); 10651 10652 /* Validating that the resource is within range */ 10653 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { 10654 BLOGD(sc, DBG_LOAD, 10655 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n", 10656 resource, HW_LOCK_MAX_RESOURCE_VALUE); 10657 return (FALSE); 10658 } 10659 10660 if (func <= 5) { 10661 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8); 10662 } else { 10663 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8); 10664 } 10665 10666 /* try to acquire the lock */ 10667 REG_WR(sc, hw_lock_control_reg + 4, resource_bit); 10668 lock_status = REG_RD(sc, hw_lock_control_reg); 10669 if (lock_status & resource_bit) { 10670 return (TRUE); 10671 } 10672 10673 BLOGE(sc, "Failed to get a resource lock 0x%x func %d " 10674 "lock_status 0x%x resource_bit 0x%x\n", resource, func, 10675 lock_status, resource_bit); 10676 10677 return (FALSE); 10678 } 10679 10680 /* 10681 * Get the recovery leader resource id according to the engine this function 10682 * belongs to. Currently only only 2 engines is supported. 10683 */ 10684 static int 10685 bxe_get_leader_lock_resource(struct bxe_softc *sc) 10686 { 10687 if (SC_PATH(sc)) { 10688 return (HW_LOCK_RESOURCE_RECOVERY_LEADER_1); 10689 } else { 10690 return (HW_LOCK_RESOURCE_RECOVERY_LEADER_0); 10691 } 10692 } 10693 10694 /* try to acquire a leader lock for current engine */ 10695 static uint8_t 10696 bxe_trylock_leader_lock(struct bxe_softc *sc) 10697 { 10698 return (bxe_trylock_hw_lock(sc, bxe_get_leader_lock_resource(sc))); 10699 } 10700 10701 static int 10702 bxe_release_leader_lock(struct bxe_softc *sc) 10703 { 10704 return (bxe_release_hw_lock(sc, bxe_get_leader_lock_resource(sc))); 10705 } 10706 10707 /* close gates #2, #3 and #4 */ 10708 static void 10709 bxe_set_234_gates(struct bxe_softc *sc, 10710 uint8_t close) 10711 { 10712 uint32_t val; 10713 10714 /* gates #2 and #4a are closed/opened for "not E1" only */ 10715 if (!CHIP_IS_E1(sc)) { 10716 /* #4 */ 10717 REG_WR(sc, PXP_REG_HST_DISCARD_DOORBELLS, !!close); 10718 /* #2 */ 10719 REG_WR(sc, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close); 10720 } 10721 10722 /* #3 */ 10723 if (CHIP_IS_E1x(sc)) { 10724 /* prevent interrupts from HC on both ports */ 10725 val = REG_RD(sc, HC_REG_CONFIG_1); 10726 REG_WR(sc, HC_REG_CONFIG_1, 10727 (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) : 10728 (val & ~(uint32_t)HC_CONFIG_1_REG_BLOCK_DISABLE_1)); 10729 10730 val = REG_RD(sc, HC_REG_CONFIG_0); 10731 REG_WR(sc, HC_REG_CONFIG_0, 10732 (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) : 10733 (val & ~(uint32_t)HC_CONFIG_0_REG_BLOCK_DISABLE_0)); 10734 } else { 10735 /* Prevent incoming interrupts in IGU */ 10736 val = REG_RD(sc, IGU_REG_BLOCK_CONFIGURATION); 10737 10738 REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION, 10739 (!close) ? 10740 (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) : 10741 (val & ~(uint32_t)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE)); 10742 } 10743 10744 BLOGD(sc, DBG_LOAD, "%s gates #2, #3 and #4\n", 10745 close ? "closing" : "opening"); 10746 10747 wmb(); 10748 } 10749 10750 /* poll for pending writes bit, it should get cleared in no more than 1s */ 10751 static int 10752 bxe_er_poll_igu_vq(struct bxe_softc *sc) 10753 { 10754 uint32_t cnt = 1000; 10755 uint32_t pend_bits = 0; 10756 10757 do { 10758 pend_bits = REG_RD(sc, IGU_REG_PENDING_BITS_STATUS); 10759 10760 if (pend_bits == 0) { 10761 break; 10762 } 10763 10764 DELAY(1000); 10765 } while (--cnt > 0); 10766 10767 if (cnt == 0) { 10768 BLOGE(sc, "Still pending IGU requests bits=0x%08x!\n", pend_bits); 10769 return (-1); 10770 } 10771 10772 return (0); 10773 } 10774 10775 #define SHARED_MF_CLP_MAGIC 0x80000000 /* 'magic' bit */ 10776 10777 static void 10778 bxe_clp_reset_prep(struct bxe_softc *sc, 10779 uint32_t *magic_val) 10780 { 10781 /* Do some magic... */ 10782 uint32_t val = MFCFG_RD(sc, shared_mf_config.clp_mb); 10783 *magic_val = val & SHARED_MF_CLP_MAGIC; 10784 MFCFG_WR(sc, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC); 10785 } 10786 10787 /* restore the value of the 'magic' bit */ 10788 static void 10789 bxe_clp_reset_done(struct bxe_softc *sc, 10790 uint32_t magic_val) 10791 { 10792 /* Restore the 'magic' bit value... */ 10793 uint32_t val = MFCFG_RD(sc, shared_mf_config.clp_mb); 10794 MFCFG_WR(sc, shared_mf_config.clp_mb, 10795 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val); 10796 } 10797 10798 /* prepare for MCP reset, takes care of CLP configurations */ 10799 static void 10800 bxe_reset_mcp_prep(struct bxe_softc *sc, 10801 uint32_t *magic_val) 10802 { 10803 uint32_t shmem; 10804 uint32_t validity_offset; 10805 10806 /* set `magic' bit in order to save MF config */ 10807 if (!CHIP_IS_E1(sc)) { 10808 bxe_clp_reset_prep(sc, magic_val); 10809 } 10810 10811 /* get shmem offset */ 10812 shmem = REG_RD(sc, MISC_REG_SHARED_MEM_ADDR); 10813 validity_offset = 10814 offsetof(struct shmem_region, validity_map[SC_PORT(sc)]); 10815 10816 /* Clear validity map flags */ 10817 if (shmem > 0) { 10818 REG_WR(sc, shmem + validity_offset, 0); 10819 } 10820 } 10821 10822 #define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */ 10823 #define MCP_ONE_TIMEOUT 100 /* 100 ms */ 10824 10825 static void 10826 bxe_mcp_wait_one(struct bxe_softc *sc) 10827 { 10828 /* special handling for emulation and FPGA (10 times longer) */ 10829 if (CHIP_REV_IS_SLOW(sc)) { 10830 DELAY((MCP_ONE_TIMEOUT*10) * 1000); 10831 } else { 10832 DELAY((MCP_ONE_TIMEOUT) * 1000); 10833 } 10834 } 10835 10836 /* initialize shmem_base and waits for validity signature to appear */ 10837 static int 10838 bxe_init_shmem(struct bxe_softc *sc) 10839 { 10840 int cnt = 0; 10841 uint32_t val = 0; 10842 10843 do { 10844 sc->devinfo.shmem_base = 10845 sc->link_params.shmem_base = 10846 REG_RD(sc, MISC_REG_SHARED_MEM_ADDR); 10847 10848 if (sc->devinfo.shmem_base) { 10849 val = SHMEM_RD(sc, validity_map[SC_PORT(sc)]); 10850 if (val & SHR_MEM_VALIDITY_MB) 10851 return (0); 10852 } 10853 10854 bxe_mcp_wait_one(sc); 10855 10856 } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT)); 10857 10858 BLOGE(sc, "BAD MCP validity signature\n"); 10859 10860 return (-1); 10861 } 10862 10863 static int 10864 bxe_reset_mcp_comp(struct bxe_softc *sc, 10865 uint32_t magic_val) 10866 { 10867 int rc = bxe_init_shmem(sc); 10868 10869 /* Restore the `magic' bit value */ 10870 if (!CHIP_IS_E1(sc)) { 10871 bxe_clp_reset_done(sc, magic_val); 10872 } 10873 10874 return (rc); 10875 } 10876 10877 static void 10878 bxe_pxp_prep(struct bxe_softc *sc) 10879 { 10880 if (!CHIP_IS_E1(sc)) { 10881 REG_WR(sc, PXP2_REG_RD_START_INIT, 0); 10882 REG_WR(sc, PXP2_REG_RQ_RBC_DONE, 0); 10883 wmb(); 10884 } 10885 } 10886 10887 /* 10888 * Reset the whole chip except for: 10889 * - PCIE core 10890 * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by one reset bit) 10891 * - IGU 10892 * - MISC (including AEU) 10893 * - GRC 10894 * - RBCN, RBCP 10895 */ 10896 static void 10897 bxe_process_kill_chip_reset(struct bxe_softc *sc, 10898 uint8_t global) 10899 { 10900 uint32_t not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2; 10901 uint32_t global_bits2, stay_reset2; 10902 10903 /* 10904 * Bits that have to be set in reset_mask2 if we want to reset 'global' 10905 * (per chip) blocks. 10906 */ 10907 global_bits2 = 10908 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU | 10909 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE; 10910 10911 /* 10912 * Don't reset the following blocks. 10913 * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be 10914 * reset, as in 4 port device they might still be owned 10915 * by the MCP (there is only one leader per path). 10916 */ 10917 not_reset_mask1 = 10918 MISC_REGISTERS_RESET_REG_1_RST_HC | 10919 MISC_REGISTERS_RESET_REG_1_RST_PXPV | 10920 MISC_REGISTERS_RESET_REG_1_RST_PXP; 10921 10922 not_reset_mask2 = 10923 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO | 10924 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE | 10925 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE | 10926 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE | 10927 MISC_REGISTERS_RESET_REG_2_RST_RBCN | 10928 MISC_REGISTERS_RESET_REG_2_RST_GRC | 10929 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE | 10930 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B | 10931 MISC_REGISTERS_RESET_REG_2_RST_ATC | 10932 MISC_REGISTERS_RESET_REG_2_PGLC | 10933 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 | 10934 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 | 10935 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 | 10936 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 | 10937 MISC_REGISTERS_RESET_REG_2_UMAC0 | 10938 MISC_REGISTERS_RESET_REG_2_UMAC1; 10939 10940 /* 10941 * Keep the following blocks in reset: 10942 * - all xxMACs are handled by the elink code. 10943 */ 10944 stay_reset2 = 10945 MISC_REGISTERS_RESET_REG_2_XMAC | 10946 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT; 10947 10948 /* Full reset masks according to the chip */ 10949 reset_mask1 = 0xffffffff; 10950 10951 if (CHIP_IS_E1(sc)) 10952 reset_mask2 = 0xffff; 10953 else if (CHIP_IS_E1H(sc)) 10954 reset_mask2 = 0x1ffff; 10955 else if (CHIP_IS_E2(sc)) 10956 reset_mask2 = 0xfffff; 10957 else /* CHIP_IS_E3 */ 10958 reset_mask2 = 0x3ffffff; 10959 10960 /* Don't reset global blocks unless we need to */ 10961 if (!global) 10962 reset_mask2 &= ~global_bits2; 10963 10964 /* 10965 * In case of attention in the QM, we need to reset PXP 10966 * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM 10967 * because otherwise QM reset would release 'close the gates' shortly 10968 * before resetting the PXP, then the PSWRQ would send a write 10969 * request to PGLUE. Then when PXP is reset, PGLUE would try to 10970 * read the payload data from PSWWR, but PSWWR would not 10971 * respond. The write queue in PGLUE would stuck, dmae commands 10972 * would not return. Therefore it's important to reset the second 10973 * reset register (containing the 10974 * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the 10975 * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM 10976 * bit). 10977 */ 10978 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 10979 reset_mask2 & (~not_reset_mask2)); 10980 10981 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 10982 reset_mask1 & (~not_reset_mask1)); 10983 10984 mb(); 10985 wmb(); 10986 10987 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 10988 reset_mask2 & (~stay_reset2)); 10989 10990 mb(); 10991 wmb(); 10992 10993 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1); 10994 wmb(); 10995 } 10996 10997 static int 10998 bxe_process_kill(struct bxe_softc *sc, 10999 uint8_t global) 11000 { 11001 int cnt = 1000; 11002 uint32_t val = 0; 11003 uint32_t sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2; 11004 uint32_t tags_63_32 = 0; 11005 11006 /* Empty the Tetris buffer, wait for 1s */ 11007 do { 11008 sr_cnt = REG_RD(sc, PXP2_REG_RD_SR_CNT); 11009 blk_cnt = REG_RD(sc, PXP2_REG_RD_BLK_CNT); 11010 port_is_idle_0 = REG_RD(sc, PXP2_REG_RD_PORT_IS_IDLE_0); 11011 port_is_idle_1 = REG_RD(sc, PXP2_REG_RD_PORT_IS_IDLE_1); 11012 pgl_exp_rom2 = REG_RD(sc, PXP2_REG_PGL_EXP_ROM2); 11013 if (CHIP_IS_E3(sc)) { 11014 tags_63_32 = REG_RD(sc, PGLUE_B_REG_TAGS_63_32); 11015 } 11016 11017 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) && 11018 ((port_is_idle_0 & 0x1) == 0x1) && 11019 ((port_is_idle_1 & 0x1) == 0x1) && 11020 (pgl_exp_rom2 == 0xffffffff) && 11021 (!CHIP_IS_E3(sc) || (tags_63_32 == 0xffffffff))) 11022 break; 11023 DELAY(1000); 11024 } while (cnt-- > 0); 11025 11026 if (cnt <= 0) { 11027 BLOGE(sc, "ERROR: Tetris buffer didn't get empty or there " 11028 "are still outstanding read requests after 1s! " 11029 "sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, " 11030 "port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n", 11031 sr_cnt, blk_cnt, port_is_idle_0, 11032 port_is_idle_1, pgl_exp_rom2); 11033 return (-1); 11034 } 11035 11036 mb(); 11037 11038 /* Close gates #2, #3 and #4 */ 11039 bxe_set_234_gates(sc, TRUE); 11040 11041 /* Poll for IGU VQs for 57712 and newer chips */ 11042 if (!CHIP_IS_E1x(sc) && bxe_er_poll_igu_vq(sc)) { 11043 return (-1); 11044 } 11045 11046 /* XXX indicate that "process kill" is in progress to MCP */ 11047 11048 /* clear "unprepared" bit */ 11049 REG_WR(sc, MISC_REG_UNPREPARED, 0); 11050 mb(); 11051 11052 /* Make sure all is written to the chip before the reset */ 11053 wmb(); 11054 11055 /* 11056 * Wait for 1ms to empty GLUE and PCI-E core queues, 11057 * PSWHST, GRC and PSWRD Tetris buffer. 11058 */ 11059 DELAY(1000); 11060 11061 /* Prepare to chip reset: */ 11062 /* MCP */ 11063 if (global) { 11064 bxe_reset_mcp_prep(sc, &val); 11065 } 11066 11067 /* PXP */ 11068 bxe_pxp_prep(sc); 11069 mb(); 11070 11071 /* reset the chip */ 11072 bxe_process_kill_chip_reset(sc, global); 11073 mb(); 11074 11075 /* clear errors in PGB */ 11076 if (!CHIP_IS_E1(sc)) 11077 REG_WR(sc, PGLUE_B_REG_LATCHED_ERRORS_CLR, 0x7f); 11078 11079 /* Recover after reset: */ 11080 /* MCP */ 11081 if (global && bxe_reset_mcp_comp(sc, val)) { 11082 return (-1); 11083 } 11084 11085 /* XXX add resetting the NO_MCP mode DB here */ 11086 11087 /* Open the gates #2, #3 and #4 */ 11088 bxe_set_234_gates(sc, FALSE); 11089 11090 /* XXX 11091 * IGU/AEU preparation bring back the AEU/IGU to a reset state 11092 * re-enable attentions 11093 */ 11094 11095 return (0); 11096 } 11097 11098 static int 11099 bxe_leader_reset(struct bxe_softc *sc) 11100 { 11101 int rc = 0; 11102 uint8_t global = bxe_reset_is_global(sc); 11103 uint32_t load_code; 11104 11105 /* 11106 * If not going to reset MCP, load "fake" driver to reset HW while 11107 * driver is owner of the HW. 11108 */ 11109 if (!global && !BXE_NOMCP(sc)) { 11110 load_code = bxe_fw_command(sc, DRV_MSG_CODE_LOAD_REQ, 11111 DRV_MSG_CODE_LOAD_REQ_WITH_LFA); 11112 if (!load_code) { 11113 BLOGE(sc, "MCP response failure, aborting\n"); 11114 rc = -1; 11115 goto exit_leader_reset; 11116 } 11117 11118 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) && 11119 (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) { 11120 BLOGE(sc, "MCP unexpected response, aborting\n"); 11121 rc = -1; 11122 goto exit_leader_reset2; 11123 } 11124 11125 load_code = bxe_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0); 11126 if (!load_code) { 11127 BLOGE(sc, "MCP response failure, aborting\n"); 11128 rc = -1; 11129 goto exit_leader_reset2; 11130 } 11131 } 11132 11133 /* try to recover after the failure */ 11134 if (bxe_process_kill(sc, global)) { 11135 BLOGE(sc, "Something bad occurred on engine %d!\n", SC_PATH(sc)); 11136 rc = -1; 11137 goto exit_leader_reset2; 11138 } 11139 11140 /* 11141 * Clear the RESET_IN_PROGRESS and RESET_GLOBAL bits and update the driver 11142 * state. 11143 */ 11144 bxe_set_reset_done(sc); 11145 if (global) { 11146 bxe_clear_reset_global(sc); 11147 } 11148 11149 exit_leader_reset2: 11150 11151 /* unload "fake driver" if it was loaded */ 11152 if (!global && !BXE_NOMCP(sc)) { 11153 bxe_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0); 11154 bxe_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, 0); 11155 } 11156 11157 exit_leader_reset: 11158 11159 sc->is_leader = 0; 11160 bxe_release_leader_lock(sc); 11161 11162 mb(); 11163 return (rc); 11164 } 11165 11166 /* 11167 * prepare INIT transition, parameters configured: 11168 * - HC configuration 11169 * - Queue's CDU context 11170 */ 11171 static void 11172 bxe_pf_q_prep_init(struct bxe_softc *sc, 11173 struct bxe_fastpath *fp, 11174 struct ecore_queue_init_params *init_params) 11175 { 11176 uint8_t cos; 11177 int cxt_index, cxt_offset; 11178 11179 bxe_set_bit(ECORE_Q_FLG_HC, &init_params->rx.flags); 11180 bxe_set_bit(ECORE_Q_FLG_HC, &init_params->tx.flags); 11181 11182 bxe_set_bit(ECORE_Q_FLG_HC_EN, &init_params->rx.flags); 11183 bxe_set_bit(ECORE_Q_FLG_HC_EN, &init_params->tx.flags); 11184 11185 /* HC rate */ 11186 init_params->rx.hc_rate = 11187 sc->hc_rx_ticks ? (1000000 / sc->hc_rx_ticks) : 0; 11188 init_params->tx.hc_rate = 11189 sc->hc_tx_ticks ? (1000000 / sc->hc_tx_ticks) : 0; 11190 11191 /* FW SB ID */ 11192 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id = fp->fw_sb_id; 11193 11194 /* CQ index among the SB indices */ 11195 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS; 11196 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS; 11197 11198 /* set maximum number of COSs supported by this queue */ 11199 init_params->max_cos = sc->max_cos; 11200 11201 BLOGD(sc, DBG_LOAD, "fp %d setting queue params max cos to %d\n", 11202 fp->index, init_params->max_cos); 11203 11204 /* set the context pointers queue object */ 11205 for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) { 11206 /* XXX change index/cid here if ever support multiple tx CoS */ 11207 /* fp->txdata[cos]->cid */ 11208 cxt_index = fp->index / ILT_PAGE_CIDS; 11209 cxt_offset = fp->index - (cxt_index * ILT_PAGE_CIDS); 11210 init_params->cxts[cos] = &sc->context[cxt_index].vcxt[cxt_offset].eth; 11211 } 11212 } 11213 11214 /* set flags that are common for the Tx-only and not normal connections */ 11215 static unsigned long 11216 bxe_get_common_flags(struct bxe_softc *sc, 11217 struct bxe_fastpath *fp, 11218 uint8_t zero_stats) 11219 { 11220 unsigned long flags = 0; 11221 11222 /* PF driver will always initialize the Queue to an ACTIVE state */ 11223 bxe_set_bit(ECORE_Q_FLG_ACTIVE, &flags); 11224 11225 /* 11226 * tx only connections collect statistics (on the same index as the 11227 * parent connection). The statistics are zeroed when the parent 11228 * connection is initialized. 11229 */ 11230 11231 bxe_set_bit(ECORE_Q_FLG_STATS, &flags); 11232 if (zero_stats) { 11233 bxe_set_bit(ECORE_Q_FLG_ZERO_STATS, &flags); 11234 } 11235 11236 /* 11237 * tx only connections can support tx-switching, though their 11238 * CoS-ness doesn't survive the loopback 11239 */ 11240 if (sc->flags & BXE_TX_SWITCHING) { 11241 bxe_set_bit(ECORE_Q_FLG_TX_SWITCH, &flags); 11242 } 11243 11244 bxe_set_bit(ECORE_Q_FLG_PCSUM_ON_PKT, &flags); 11245 11246 return (flags); 11247 } 11248 11249 static unsigned long 11250 bxe_get_q_flags(struct bxe_softc *sc, 11251 struct bxe_fastpath *fp, 11252 uint8_t leading) 11253 { 11254 unsigned long flags = 0; 11255 11256 if (IS_MF_SD(sc)) { 11257 bxe_set_bit(ECORE_Q_FLG_OV, &flags); 11258 } 11259 11260 if (if_getcapenable(sc->ifp) & IFCAP_LRO) { 11261 bxe_set_bit(ECORE_Q_FLG_TPA, &flags); 11262 #if __FreeBSD_version >= 800000 11263 bxe_set_bit(ECORE_Q_FLG_TPA_IPV6, &flags); 11264 #endif 11265 } 11266 11267 if (leading) { 11268 bxe_set_bit(ECORE_Q_FLG_LEADING_RSS, &flags); 11269 bxe_set_bit(ECORE_Q_FLG_MCAST, &flags); 11270 } 11271 11272 bxe_set_bit(ECORE_Q_FLG_VLAN, &flags); 11273 11274 /* merge with common flags */ 11275 return (flags | bxe_get_common_flags(sc, fp, TRUE)); 11276 } 11277 11278 static void 11279 bxe_pf_q_prep_general(struct bxe_softc *sc, 11280 struct bxe_fastpath *fp, 11281 struct ecore_general_setup_params *gen_init, 11282 uint8_t cos) 11283 { 11284 gen_init->stat_id = bxe_stats_id(fp); 11285 gen_init->spcl_id = fp->cl_id; 11286 gen_init->mtu = sc->mtu; 11287 gen_init->cos = cos; 11288 } 11289 11290 static void 11291 bxe_pf_rx_q_prep(struct bxe_softc *sc, 11292 struct bxe_fastpath *fp, 11293 struct rxq_pause_params *pause, 11294 struct ecore_rxq_setup_params *rxq_init) 11295 { 11296 uint8_t max_sge = 0; 11297 uint16_t sge_sz = 0; 11298 uint16_t tpa_agg_size = 0; 11299 11300 pause->sge_th_lo = SGE_TH_LO(sc); 11301 pause->sge_th_hi = SGE_TH_HI(sc); 11302 11303 /* validate SGE ring has enough to cross high threshold */ 11304 if (sc->dropless_fc && 11305 (pause->sge_th_hi + FW_PREFETCH_CNT) > 11306 (RX_SGE_USABLE_PER_PAGE * RX_SGE_NUM_PAGES)) { 11307 BLOGW(sc, "sge ring threshold limit\n"); 11308 } 11309 11310 /* minimum max_aggregation_size is 2*MTU (two full buffers) */ 11311 tpa_agg_size = (2 * sc->mtu); 11312 if (tpa_agg_size < sc->max_aggregation_size) { 11313 tpa_agg_size = sc->max_aggregation_size; 11314 } 11315 11316 max_sge = SGE_PAGE_ALIGN(sc->mtu) >> SGE_PAGE_SHIFT; 11317 max_sge = ((max_sge + PAGES_PER_SGE - 1) & 11318 (~(PAGES_PER_SGE - 1))) >> PAGES_PER_SGE_SHIFT; 11319 sge_sz = (uint16_t)min(SGE_PAGES, 0xffff); 11320 11321 /* pause - not for e1 */ 11322 if (!CHIP_IS_E1(sc)) { 11323 pause->bd_th_lo = BD_TH_LO(sc); 11324 pause->bd_th_hi = BD_TH_HI(sc); 11325 11326 pause->rcq_th_lo = RCQ_TH_LO(sc); 11327 pause->rcq_th_hi = RCQ_TH_HI(sc); 11328 11329 /* validate rings have enough entries to cross high thresholds */ 11330 if (sc->dropless_fc && 11331 pause->bd_th_hi + FW_PREFETCH_CNT > 11332 sc->rx_ring_size) { 11333 BLOGW(sc, "rx bd ring threshold limit\n"); 11334 } 11335 11336 if (sc->dropless_fc && 11337 pause->rcq_th_hi + FW_PREFETCH_CNT > 11338 RCQ_NUM_PAGES * RCQ_USABLE_PER_PAGE) { 11339 BLOGW(sc, "rcq ring threshold limit\n"); 11340 } 11341 11342 pause->pri_map = 1; 11343 } 11344 11345 /* rxq setup */ 11346 rxq_init->dscr_map = fp->rx_dma.paddr; 11347 rxq_init->sge_map = fp->rx_sge_dma.paddr; 11348 rxq_init->rcq_map = fp->rcq_dma.paddr; 11349 rxq_init->rcq_np_map = (fp->rcq_dma.paddr + BCM_PAGE_SIZE); 11350 11351 /* 11352 * This should be a maximum number of data bytes that may be 11353 * placed on the BD (not including paddings). 11354 */ 11355 rxq_init->buf_sz = (fp->rx_buf_size - 11356 IP_HEADER_ALIGNMENT_PADDING); 11357 11358 rxq_init->cl_qzone_id = fp->cl_qzone_id; 11359 rxq_init->tpa_agg_sz = tpa_agg_size; 11360 rxq_init->sge_buf_sz = sge_sz; 11361 rxq_init->max_sges_pkt = max_sge; 11362 rxq_init->rss_engine_id = SC_FUNC(sc); 11363 rxq_init->mcast_engine_id = SC_FUNC(sc); 11364 11365 /* 11366 * Maximum number or simultaneous TPA aggregation for this Queue. 11367 * For PF Clients it should be the maximum available number. 11368 * VF driver(s) may want to define it to a smaller value. 11369 */ 11370 rxq_init->max_tpa_queues = MAX_AGG_QS(sc); 11371 11372 rxq_init->cache_line_log = BXE_RX_ALIGN_SHIFT; 11373 rxq_init->fw_sb_id = fp->fw_sb_id; 11374 11375 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS; 11376 11377 /* 11378 * configure silent vlan removal 11379 * if multi function mode is afex, then mask default vlan 11380 */ 11381 if (IS_MF_AFEX(sc)) { 11382 rxq_init->silent_removal_value = 11383 sc->devinfo.mf_info.afex_def_vlan_tag; 11384 rxq_init->silent_removal_mask = EVL_VLID_MASK; 11385 } 11386 } 11387 11388 static void 11389 bxe_pf_tx_q_prep(struct bxe_softc *sc, 11390 struct bxe_fastpath *fp, 11391 struct ecore_txq_setup_params *txq_init, 11392 uint8_t cos) 11393 { 11394 /* 11395 * XXX If multiple CoS is ever supported then each fastpath structure 11396 * will need to maintain tx producer/consumer/dma/etc values *per* CoS. 11397 * fp->txdata[cos]->tx_dma.paddr; 11398 */ 11399 txq_init->dscr_map = fp->tx_dma.paddr; 11400 txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos; 11401 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW; 11402 txq_init->fw_sb_id = fp->fw_sb_id; 11403 11404 /* 11405 * set the TSS leading client id for TX classfication to the 11406 * leading RSS client id 11407 */ 11408 txq_init->tss_leading_cl_id = BXE_FP(sc, 0, cl_id); 11409 } 11410 11411 /* 11412 * This function performs 2 steps in a queue state machine: 11413 * 1) RESET->INIT 11414 * 2) INIT->SETUP 11415 */ 11416 static int 11417 bxe_setup_queue(struct bxe_softc *sc, 11418 struct bxe_fastpath *fp, 11419 uint8_t leading) 11420 { 11421 struct ecore_queue_state_params q_params = { NULL }; 11422 struct ecore_queue_setup_params *setup_params = 11423 &q_params.params.setup; 11424 int rc; 11425 11426 BLOGD(sc, DBG_LOAD, "setting up queue %d\n", fp->index); 11427 11428 bxe_ack_sb(sc, fp->igu_sb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0); 11429 11430 q_params.q_obj = &BXE_SP_OBJ(sc, fp).q_obj; 11431 11432 /* we want to wait for completion in this context */ 11433 bxe_set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags); 11434 11435 /* prepare the INIT parameters */ 11436 bxe_pf_q_prep_init(sc, fp, &q_params.params.init); 11437 11438 /* Set the command */ 11439 q_params.cmd = ECORE_Q_CMD_INIT; 11440 11441 /* Change the state to INIT */ 11442 rc = ecore_queue_state_change(sc, &q_params); 11443 if (rc) { 11444 BLOGE(sc, "Queue(%d) INIT failed rc = %d\n", fp->index, rc); 11445 return (rc); 11446 } 11447 11448 BLOGD(sc, DBG_LOAD, "init complete\n"); 11449 11450 /* now move the Queue to the SETUP state */ 11451 memset(setup_params, 0, sizeof(*setup_params)); 11452 11453 /* set Queue flags */ 11454 setup_params->flags = bxe_get_q_flags(sc, fp, leading); 11455 11456 /* set general SETUP parameters */ 11457 bxe_pf_q_prep_general(sc, fp, &setup_params->gen_params, 11458 FIRST_TX_COS_INDEX); 11459 11460 bxe_pf_rx_q_prep(sc, fp, 11461 &setup_params->pause_params, 11462 &setup_params->rxq_params); 11463 11464 bxe_pf_tx_q_prep(sc, fp, 11465 &setup_params->txq_params, 11466 FIRST_TX_COS_INDEX); 11467 11468 /* Set the command */ 11469 q_params.cmd = ECORE_Q_CMD_SETUP; 11470 11471 /* change the state to SETUP */ 11472 rc = ecore_queue_state_change(sc, &q_params); 11473 if (rc) { 11474 BLOGE(sc, "Queue(%d) SETUP failed (rc = %d)\n", fp->index, rc); 11475 return (rc); 11476 } 11477 11478 return (rc); 11479 } 11480 11481 static int 11482 bxe_setup_leading(struct bxe_softc *sc) 11483 { 11484 return (bxe_setup_queue(sc, &sc->fp[0], TRUE)); 11485 } 11486 11487 static int 11488 bxe_config_rss_pf(struct bxe_softc *sc, 11489 struct ecore_rss_config_obj *rss_obj, 11490 uint8_t config_hash) 11491 { 11492 struct ecore_config_rss_params params = { NULL }; 11493 int i; 11494 11495 /* 11496 * Although RSS is meaningless when there is a single HW queue we 11497 * still need it enabled in order to have HW Rx hash generated. 11498 */ 11499 11500 params.rss_obj = rss_obj; 11501 11502 bxe_set_bit(RAMROD_COMP_WAIT, ¶ms.ramrod_flags); 11503 11504 bxe_set_bit(ECORE_RSS_MODE_REGULAR, ¶ms.rss_flags); 11505 11506 /* RSS configuration */ 11507 bxe_set_bit(ECORE_RSS_IPV4, ¶ms.rss_flags); 11508 bxe_set_bit(ECORE_RSS_IPV4_TCP, ¶ms.rss_flags); 11509 bxe_set_bit(ECORE_RSS_IPV6, ¶ms.rss_flags); 11510 bxe_set_bit(ECORE_RSS_IPV6_TCP, ¶ms.rss_flags); 11511 if (rss_obj->udp_rss_v4) { 11512 bxe_set_bit(ECORE_RSS_IPV4_UDP, ¶ms.rss_flags); 11513 } 11514 if (rss_obj->udp_rss_v6) { 11515 bxe_set_bit(ECORE_RSS_IPV6_UDP, ¶ms.rss_flags); 11516 } 11517 11518 /* Hash bits */ 11519 params.rss_result_mask = MULTI_MASK; 11520 11521 memcpy(params.ind_table, rss_obj->ind_table, sizeof(params.ind_table)); 11522 11523 if (config_hash) { 11524 /* RSS keys */ 11525 for (i = 0; i < sizeof(params.rss_key) / 4; i++) { 11526 params.rss_key[i] = arc4random(); 11527 } 11528 11529 bxe_set_bit(ECORE_RSS_SET_SRCH, ¶ms.rss_flags); 11530 } 11531 11532 return (ecore_config_rss(sc, ¶ms)); 11533 } 11534 11535 static int 11536 bxe_config_rss_eth(struct bxe_softc *sc, 11537 uint8_t config_hash) 11538 { 11539 return (bxe_config_rss_pf(sc, &sc->rss_conf_obj, config_hash)); 11540 } 11541 11542 static int 11543 bxe_init_rss_pf(struct bxe_softc *sc) 11544 { 11545 uint8_t num_eth_queues = BXE_NUM_ETH_QUEUES(sc); 11546 int i; 11547 11548 /* 11549 * Prepare the initial contents of the indirection table if 11550 * RSS is enabled 11551 */ 11552 for (i = 0; i < sizeof(sc->rss_conf_obj.ind_table); i++) { 11553 sc->rss_conf_obj.ind_table[i] = 11554 (sc->fp->cl_id + (i % num_eth_queues)); 11555 } 11556 11557 if (sc->udp_rss) { 11558 sc->rss_conf_obj.udp_rss_v4 = sc->rss_conf_obj.udp_rss_v6 = 1; 11559 } 11560 11561 /* 11562 * For 57710 and 57711 SEARCHER configuration (rss_keys) is 11563 * per-port, so if explicit configuration is needed, do it only 11564 * for a PMF. 11565 * 11566 * For 57712 and newer it's a per-function configuration. 11567 */ 11568 return (bxe_config_rss_eth(sc, sc->port.pmf || !CHIP_IS_E1x(sc))); 11569 } 11570 11571 static int 11572 bxe_set_mac_one(struct bxe_softc *sc, 11573 uint8_t *mac, 11574 struct ecore_vlan_mac_obj *obj, 11575 uint8_t set, 11576 int mac_type, 11577 unsigned long *ramrod_flags) 11578 { 11579 struct ecore_vlan_mac_ramrod_params ramrod_param; 11580 int rc; 11581 11582 memset(&ramrod_param, 0, sizeof(ramrod_param)); 11583 11584 /* fill in general parameters */ 11585 ramrod_param.vlan_mac_obj = obj; 11586 ramrod_param.ramrod_flags = *ramrod_flags; 11587 11588 /* fill a user request section if needed */ 11589 if (!bxe_test_bit(RAMROD_CONT, ramrod_flags)) { 11590 memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN); 11591 11592 bxe_set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags); 11593 11594 /* Set the command: ADD or DEL */ 11595 ramrod_param.user_req.cmd = (set) ? ECORE_VLAN_MAC_ADD : 11596 ECORE_VLAN_MAC_DEL; 11597 } 11598 11599 rc = ecore_config_vlan_mac(sc, &ramrod_param); 11600 11601 if (rc == ECORE_EXISTS) { 11602 BLOGD(sc, DBG_SP, "Failed to schedule ADD operations (EEXIST)\n"); 11603 /* do not treat adding same MAC as error */ 11604 rc = 0; 11605 } else if (rc < 0) { 11606 BLOGE(sc, "%s MAC failed (%d)\n", (set ? "Set" : "Delete"), rc); 11607 } 11608 11609 return (rc); 11610 } 11611 11612 static int 11613 bxe_set_eth_mac(struct bxe_softc *sc, 11614 uint8_t set) 11615 { 11616 unsigned long ramrod_flags = 0; 11617 11618 BLOGD(sc, DBG_LOAD, "Adding Ethernet MAC\n"); 11619 11620 bxe_set_bit(RAMROD_COMP_WAIT, &ramrod_flags); 11621 11622 /* Eth MAC is set on RSS leading client (fp[0]) */ 11623 return (bxe_set_mac_one(sc, sc->link_params.mac_addr, 11624 &sc->sp_objs->mac_obj, 11625 set, ECORE_ETH_MAC, &ramrod_flags)); 11626 } 11627 11628 static int 11629 bxe_get_cur_phy_idx(struct bxe_softc *sc) 11630 { 11631 uint32_t sel_phy_idx = 0; 11632 11633 if (sc->link_params.num_phys <= 1) { 11634 return (ELINK_INT_PHY); 11635 } 11636 11637 if (sc->link_vars.link_up) { 11638 sel_phy_idx = ELINK_EXT_PHY1; 11639 /* In case link is SERDES, check if the ELINK_EXT_PHY2 is the one */ 11640 if ((sc->link_vars.link_status & LINK_STATUS_SERDES_LINK) && 11641 (sc->link_params.phy[ELINK_EXT_PHY2].supported & 11642 ELINK_SUPPORTED_FIBRE)) 11643 sel_phy_idx = ELINK_EXT_PHY2; 11644 } else { 11645 switch (elink_phy_selection(&sc->link_params)) { 11646 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT: 11647 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY: 11648 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY: 11649 sel_phy_idx = ELINK_EXT_PHY1; 11650 break; 11651 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY: 11652 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY: 11653 sel_phy_idx = ELINK_EXT_PHY2; 11654 break; 11655 } 11656 } 11657 11658 return (sel_phy_idx); 11659 } 11660 11661 static int 11662 bxe_get_link_cfg_idx(struct bxe_softc *sc) 11663 { 11664 uint32_t sel_phy_idx = bxe_get_cur_phy_idx(sc); 11665 11666 /* 11667 * The selected activated PHY is always after swapping (in case PHY 11668 * swapping is enabled). So when swapping is enabled, we need to reverse 11669 * the configuration 11670 */ 11671 11672 if (sc->link_params.multi_phy_config & PORT_HW_CFG_PHY_SWAPPED_ENABLED) { 11673 if (sel_phy_idx == ELINK_EXT_PHY1) 11674 sel_phy_idx = ELINK_EXT_PHY2; 11675 else if (sel_phy_idx == ELINK_EXT_PHY2) 11676 sel_phy_idx = ELINK_EXT_PHY1; 11677 } 11678 11679 return (ELINK_LINK_CONFIG_IDX(sel_phy_idx)); 11680 } 11681 11682 static void 11683 bxe_set_requested_fc(struct bxe_softc *sc) 11684 { 11685 /* 11686 * Initialize link parameters structure variables 11687 * It is recommended to turn off RX FC for jumbo frames 11688 * for better performance 11689 */ 11690 if (CHIP_IS_E1x(sc) && (sc->mtu > 5000)) { 11691 sc->link_params.req_fc_auto_adv = ELINK_FLOW_CTRL_TX; 11692 } else { 11693 sc->link_params.req_fc_auto_adv = ELINK_FLOW_CTRL_BOTH; 11694 } 11695 } 11696 11697 static void 11698 bxe_calc_fc_adv(struct bxe_softc *sc) 11699 { 11700 uint8_t cfg_idx = bxe_get_link_cfg_idx(sc); 11701 11702 11703 sc->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause | 11704 ADVERTISED_Pause); 11705 11706 switch (sc->link_vars.ieee_fc & 11707 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) { 11708 11709 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH: 11710 sc->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause | 11711 ADVERTISED_Pause); 11712 break; 11713 11714 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC: 11715 sc->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause; 11716 break; 11717 11718 default: 11719 break; 11720 11721 } 11722 } 11723 11724 static uint16_t 11725 bxe_get_mf_speed(struct bxe_softc *sc) 11726 { 11727 uint16_t line_speed = sc->link_vars.line_speed; 11728 if (IS_MF(sc)) { 11729 uint16_t maxCfg = 11730 bxe_extract_max_cfg(sc, sc->devinfo.mf_info.mf_config[SC_VN(sc)]); 11731 11732 /* calculate the current MAX line speed limit for the MF devices */ 11733 if (IS_MF_SI(sc)) { 11734 line_speed = (line_speed * maxCfg) / 100; 11735 } else { /* SD mode */ 11736 uint16_t vn_max_rate = maxCfg * 100; 11737 11738 if (vn_max_rate < line_speed) { 11739 line_speed = vn_max_rate; 11740 } 11741 } 11742 } 11743 11744 return (line_speed); 11745 } 11746 11747 static void 11748 bxe_fill_report_data(struct bxe_softc *sc, 11749 struct bxe_link_report_data *data) 11750 { 11751 uint16_t line_speed = bxe_get_mf_speed(sc); 11752 11753 memset(data, 0, sizeof(*data)); 11754 11755 /* fill the report data with the effective line speed */ 11756 data->line_speed = line_speed; 11757 11758 /* Link is down */ 11759 if (!sc->link_vars.link_up || (sc->flags & BXE_MF_FUNC_DIS)) { 11760 bxe_set_bit(BXE_LINK_REPORT_LINK_DOWN, &data->link_report_flags); 11761 } 11762 11763 /* Full DUPLEX */ 11764 if (sc->link_vars.duplex == DUPLEX_FULL) { 11765 bxe_set_bit(BXE_LINK_REPORT_FULL_DUPLEX, &data->link_report_flags); 11766 } 11767 11768 /* Rx Flow Control is ON */ 11769 if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_RX) { 11770 bxe_set_bit(BXE_LINK_REPORT_RX_FC_ON, &data->link_report_flags); 11771 } 11772 11773 /* Tx Flow Control is ON */ 11774 if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_TX) { 11775 bxe_set_bit(BXE_LINK_REPORT_TX_FC_ON, &data->link_report_flags); 11776 } 11777 } 11778 11779 /* report link status to OS, should be called under phy_lock */ 11780 static void 11781 bxe_link_report_locked(struct bxe_softc *sc) 11782 { 11783 struct bxe_link_report_data cur_data; 11784 11785 /* reread mf_cfg */ 11786 if (IS_PF(sc) && !CHIP_IS_E1(sc)) { 11787 bxe_read_mf_cfg(sc); 11788 } 11789 11790 /* Read the current link report info */ 11791 bxe_fill_report_data(sc, &cur_data); 11792 11793 /* Don't report link down or exactly the same link status twice */ 11794 if (!memcmp(&cur_data, &sc->last_reported_link, sizeof(cur_data)) || 11795 (bxe_test_bit(BXE_LINK_REPORT_LINK_DOWN, 11796 &sc->last_reported_link.link_report_flags) && 11797 bxe_test_bit(BXE_LINK_REPORT_LINK_DOWN, 11798 &cur_data.link_report_flags))) { 11799 return; 11800 } 11801 11802 ELINK_DEBUG_P2(sc, "Change in link status : cur_data = %x, last_reported_link = %x\n", 11803 cur_data.link_report_flags, sc->last_reported_link.link_report_flags); 11804 sc->link_cnt++; 11805 11806 ELINK_DEBUG_P1(sc, "link status change count = %x\n", sc->link_cnt); 11807 /* report new link params and remember the state for the next time */ 11808 memcpy(&sc->last_reported_link, &cur_data, sizeof(cur_data)); 11809 11810 if (bxe_test_bit(BXE_LINK_REPORT_LINK_DOWN, 11811 &cur_data.link_report_flags)) { 11812 if_link_state_change(sc->ifp, LINK_STATE_DOWN); 11813 } else { 11814 const char *duplex; 11815 const char *flow; 11816 11817 if (bxe_test_and_clear_bit(BXE_LINK_REPORT_FULL_DUPLEX, 11818 &cur_data.link_report_flags)) { 11819 duplex = "full"; 11820 ELINK_DEBUG_P0(sc, "link set to full duplex\n"); 11821 } else { 11822 duplex = "half"; 11823 ELINK_DEBUG_P0(sc, "link set to half duplex\n"); 11824 } 11825 11826 /* 11827 * Handle the FC at the end so that only these flags would be 11828 * possibly set. This way we may easily check if there is no FC 11829 * enabled. 11830 */ 11831 if (cur_data.link_report_flags) { 11832 if (bxe_test_bit(BXE_LINK_REPORT_RX_FC_ON, 11833 &cur_data.link_report_flags) && 11834 bxe_test_bit(BXE_LINK_REPORT_TX_FC_ON, 11835 &cur_data.link_report_flags)) { 11836 flow = "ON - receive & transmit"; 11837 } else if (bxe_test_bit(BXE_LINK_REPORT_RX_FC_ON, 11838 &cur_data.link_report_flags) && 11839 !bxe_test_bit(BXE_LINK_REPORT_TX_FC_ON, 11840 &cur_data.link_report_flags)) { 11841 flow = "ON - receive"; 11842 } else if (!bxe_test_bit(BXE_LINK_REPORT_RX_FC_ON, 11843 &cur_data.link_report_flags) && 11844 bxe_test_bit(BXE_LINK_REPORT_TX_FC_ON, 11845 &cur_data.link_report_flags)) { 11846 flow = "ON - transmit"; 11847 } else { 11848 flow = "none"; /* possible? */ 11849 } 11850 } else { 11851 flow = "none"; 11852 } 11853 11854 if_link_state_change(sc->ifp, LINK_STATE_UP); 11855 BLOGI(sc, "NIC Link is Up, %d Mbps %s duplex, Flow control: %s\n", 11856 cur_data.line_speed, duplex, flow); 11857 } 11858 } 11859 11860 static void 11861 bxe_link_report(struct bxe_softc *sc) 11862 { 11863 bxe_acquire_phy_lock(sc); 11864 bxe_link_report_locked(sc); 11865 bxe_release_phy_lock(sc); 11866 } 11867 11868 static void 11869 bxe_link_status_update(struct bxe_softc *sc) 11870 { 11871 if (sc->state != BXE_STATE_OPEN) { 11872 return; 11873 } 11874 11875 if (IS_PF(sc) && !CHIP_REV_IS_SLOW(sc)) { 11876 elink_link_status_update(&sc->link_params, &sc->link_vars); 11877 } else { 11878 sc->port.supported[0] |= (ELINK_SUPPORTED_10baseT_Half | 11879 ELINK_SUPPORTED_10baseT_Full | 11880 ELINK_SUPPORTED_100baseT_Half | 11881 ELINK_SUPPORTED_100baseT_Full | 11882 ELINK_SUPPORTED_1000baseT_Full | 11883 ELINK_SUPPORTED_2500baseX_Full | 11884 ELINK_SUPPORTED_10000baseT_Full | 11885 ELINK_SUPPORTED_TP | 11886 ELINK_SUPPORTED_FIBRE | 11887 ELINK_SUPPORTED_Autoneg | 11888 ELINK_SUPPORTED_Pause | 11889 ELINK_SUPPORTED_Asym_Pause); 11890 sc->port.advertising[0] = sc->port.supported[0]; 11891 11892 sc->link_params.sc = sc; 11893 sc->link_params.port = SC_PORT(sc); 11894 sc->link_params.req_duplex[0] = DUPLEX_FULL; 11895 sc->link_params.req_flow_ctrl[0] = ELINK_FLOW_CTRL_NONE; 11896 sc->link_params.req_line_speed[0] = SPEED_10000; 11897 sc->link_params.speed_cap_mask[0] = 0x7f0000; 11898 sc->link_params.switch_cfg = ELINK_SWITCH_CFG_10G; 11899 11900 if (CHIP_REV_IS_FPGA(sc)) { 11901 sc->link_vars.mac_type = ELINK_MAC_TYPE_EMAC; 11902 sc->link_vars.line_speed = ELINK_SPEED_1000; 11903 sc->link_vars.link_status = (LINK_STATUS_LINK_UP | 11904 LINK_STATUS_SPEED_AND_DUPLEX_1000TFD); 11905 } else { 11906 sc->link_vars.mac_type = ELINK_MAC_TYPE_BMAC; 11907 sc->link_vars.line_speed = ELINK_SPEED_10000; 11908 sc->link_vars.link_status = (LINK_STATUS_LINK_UP | 11909 LINK_STATUS_SPEED_AND_DUPLEX_10GTFD); 11910 } 11911 11912 sc->link_vars.link_up = 1; 11913 11914 sc->link_vars.duplex = DUPLEX_FULL; 11915 sc->link_vars.flow_ctrl = ELINK_FLOW_CTRL_NONE; 11916 11917 if (IS_PF(sc)) { 11918 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + sc->link_params.port*4, 0); 11919 bxe_stats_handle(sc, STATS_EVENT_LINK_UP); 11920 bxe_link_report(sc); 11921 } 11922 } 11923 11924 if (IS_PF(sc)) { 11925 if (sc->link_vars.link_up) { 11926 bxe_stats_handle(sc, STATS_EVENT_LINK_UP); 11927 } else { 11928 bxe_stats_handle(sc, STATS_EVENT_STOP); 11929 } 11930 bxe_link_report(sc); 11931 } else { 11932 bxe_link_report(sc); 11933 bxe_stats_handle(sc, STATS_EVENT_LINK_UP); 11934 } 11935 } 11936 11937 static int 11938 bxe_initial_phy_init(struct bxe_softc *sc, 11939 int load_mode) 11940 { 11941 int rc, cfg_idx = bxe_get_link_cfg_idx(sc); 11942 uint16_t req_line_speed = sc->link_params.req_line_speed[cfg_idx]; 11943 struct elink_params *lp = &sc->link_params; 11944 11945 bxe_set_requested_fc(sc); 11946 11947 if (CHIP_REV_IS_SLOW(sc)) { 11948 uint32_t bond = CHIP_BOND_ID(sc); 11949 uint32_t feat = 0; 11950 11951 if (CHIP_IS_E2(sc) && CHIP_IS_MODE_4_PORT(sc)) { 11952 feat |= ELINK_FEATURE_CONFIG_EMUL_DISABLE_BMAC; 11953 } else if (bond & 0x4) { 11954 if (CHIP_IS_E3(sc)) { 11955 feat |= ELINK_FEATURE_CONFIG_EMUL_DISABLE_XMAC; 11956 } else { 11957 feat |= ELINK_FEATURE_CONFIG_EMUL_DISABLE_BMAC; 11958 } 11959 } else if (bond & 0x8) { 11960 if (CHIP_IS_E3(sc)) { 11961 feat |= ELINK_FEATURE_CONFIG_EMUL_DISABLE_UMAC; 11962 } else { 11963 feat |= ELINK_FEATURE_CONFIG_EMUL_DISABLE_EMAC; 11964 } 11965 } 11966 11967 /* disable EMAC for E3 and above */ 11968 if (bond & 0x2) { 11969 feat |= ELINK_FEATURE_CONFIG_EMUL_DISABLE_EMAC; 11970 } 11971 11972 sc->link_params.feature_config_flags |= feat; 11973 } 11974 11975 bxe_acquire_phy_lock(sc); 11976 11977 if (load_mode == LOAD_DIAG) { 11978 lp->loopback_mode = ELINK_LOOPBACK_XGXS; 11979 /* Prefer doing PHY loopback at 10G speed, if possible */ 11980 if (lp->req_line_speed[cfg_idx] < ELINK_SPEED_10000) { 11981 if (lp->speed_cap_mask[cfg_idx] & 11982 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) { 11983 lp->req_line_speed[cfg_idx] = ELINK_SPEED_10000; 11984 } else { 11985 lp->req_line_speed[cfg_idx] = ELINK_SPEED_1000; 11986 } 11987 } 11988 } 11989 11990 if (load_mode == LOAD_LOOPBACK_EXT) { 11991 lp->loopback_mode = ELINK_LOOPBACK_EXT; 11992 } 11993 11994 rc = elink_phy_init(&sc->link_params, &sc->link_vars); 11995 11996 bxe_release_phy_lock(sc); 11997 11998 bxe_calc_fc_adv(sc); 11999 12000 if (sc->link_vars.link_up) { 12001 bxe_stats_handle(sc, STATS_EVENT_LINK_UP); 12002 bxe_link_report(sc); 12003 } 12004 12005 if (!CHIP_REV_IS_SLOW(sc)) { 12006 bxe_periodic_start(sc); 12007 } 12008 12009 sc->link_params.req_line_speed[cfg_idx] = req_line_speed; 12010 return (rc); 12011 } 12012 12013 /* must be called under IF_ADDR_LOCK */ 12014 static int 12015 bxe_init_mcast_macs_list(struct bxe_softc *sc, 12016 struct ecore_mcast_ramrod_params *p) 12017 { 12018 if_t ifp = sc->ifp; 12019 int mc_count = 0; 12020 struct ifmultiaddr *ifma; 12021 struct ecore_mcast_list_elem *mc_mac; 12022 12023 CK_STAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 12024 if (ifma->ifma_addr->sa_family != AF_LINK) { 12025 continue; 12026 } 12027 12028 mc_count++; 12029 } 12030 12031 ECORE_LIST_INIT(&p->mcast_list); 12032 p->mcast_list_len = 0; 12033 12034 if (!mc_count) { 12035 return (0); 12036 } 12037 12038 mc_mac = malloc(sizeof(*mc_mac) * mc_count, M_DEVBUF, 12039 (M_NOWAIT | M_ZERO)); 12040 if (!mc_mac) { 12041 BLOGE(sc, "Failed to allocate temp mcast list\n"); 12042 return (-1); 12043 } 12044 bzero(mc_mac, (sizeof(*mc_mac) * mc_count)); 12045 12046 CK_STAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 12047 if (ifma->ifma_addr->sa_family != AF_LINK) { 12048 continue; 12049 } 12050 12051 mc_mac->mac = (uint8_t *)LLADDR((struct sockaddr_dl *)ifma->ifma_addr); 12052 ECORE_LIST_PUSH_TAIL(&mc_mac->link, &p->mcast_list); 12053 12054 BLOGD(sc, DBG_LOAD, 12055 "Setting MCAST %02X:%02X:%02X:%02X:%02X:%02X and mc_count %d\n", 12056 mc_mac->mac[0], mc_mac->mac[1], mc_mac->mac[2], 12057 mc_mac->mac[3], mc_mac->mac[4], mc_mac->mac[5], mc_count); 12058 mc_mac++; 12059 } 12060 12061 p->mcast_list_len = mc_count; 12062 12063 return (0); 12064 } 12065 12066 static void 12067 bxe_free_mcast_macs_list(struct ecore_mcast_ramrod_params *p) 12068 { 12069 struct ecore_mcast_list_elem *mc_mac = 12070 ECORE_LIST_FIRST_ENTRY(&p->mcast_list, 12071 struct ecore_mcast_list_elem, 12072 link); 12073 12074 if (mc_mac) { 12075 /* only a single free as all mc_macs are in the same heap array */ 12076 free(mc_mac, M_DEVBUF); 12077 } 12078 } 12079 static int 12080 bxe_set_mc_list(struct bxe_softc *sc) 12081 { 12082 struct ecore_mcast_ramrod_params rparam = { NULL }; 12083 int rc = 0; 12084 12085 rparam.mcast_obj = &sc->mcast_obj; 12086 12087 BXE_MCAST_LOCK(sc); 12088 12089 /* first, clear all configured multicast MACs */ 12090 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_DEL); 12091 if (rc < 0) { 12092 BLOGE(sc, "Failed to clear multicast configuration: %d\n", rc); 12093 /* Manual backport parts of FreeBSD upstream r284470. */ 12094 BXE_MCAST_UNLOCK(sc); 12095 return (rc); 12096 } 12097 12098 /* configure a new MACs list */ 12099 rc = bxe_init_mcast_macs_list(sc, &rparam); 12100 if (rc) { 12101 BLOGE(sc, "Failed to create mcast MACs list (%d)\n", rc); 12102 BXE_MCAST_UNLOCK(sc); 12103 return (rc); 12104 } 12105 12106 /* Now add the new MACs */ 12107 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_ADD); 12108 if (rc < 0) { 12109 BLOGE(sc, "Failed to set new mcast config (%d)\n", rc); 12110 } 12111 12112 bxe_free_mcast_macs_list(&rparam); 12113 12114 BXE_MCAST_UNLOCK(sc); 12115 12116 return (rc); 12117 } 12118 12119 static int 12120 bxe_set_uc_list(struct bxe_softc *sc) 12121 { 12122 if_t ifp = sc->ifp; 12123 struct ecore_vlan_mac_obj *mac_obj = &sc->sp_objs->mac_obj; 12124 struct ifaddr *ifa; 12125 unsigned long ramrod_flags = 0; 12126 int rc; 12127 12128 #if __FreeBSD_version < 800000 12129 IF_ADDR_LOCK(ifp); 12130 #else 12131 if_addr_rlock(ifp); 12132 #endif 12133 12134 /* first schedule a cleanup up of old configuration */ 12135 rc = bxe_del_all_macs(sc, mac_obj, ECORE_UC_LIST_MAC, FALSE); 12136 if (rc < 0) { 12137 BLOGE(sc, "Failed to schedule delete of all ETH MACs (%d)\n", rc); 12138 #if __FreeBSD_version < 800000 12139 IF_ADDR_UNLOCK(ifp); 12140 #else 12141 if_addr_runlock(ifp); 12142 #endif 12143 return (rc); 12144 } 12145 12146 ifa = if_getifaddr(ifp); /* XXX Is this structure */ 12147 while (ifa) { 12148 if (ifa->ifa_addr->sa_family != AF_LINK) { 12149 ifa = CK_STAILQ_NEXT(ifa, ifa_link); 12150 continue; 12151 } 12152 12153 rc = bxe_set_mac_one(sc, (uint8_t *)LLADDR((struct sockaddr_dl *)ifa->ifa_addr), 12154 mac_obj, TRUE, ECORE_UC_LIST_MAC, &ramrod_flags); 12155 if (rc == -EEXIST) { 12156 BLOGD(sc, DBG_SP, "Failed to schedule ADD operations (EEXIST)\n"); 12157 /* do not treat adding same MAC as an error */ 12158 rc = 0; 12159 } else if (rc < 0) { 12160 BLOGE(sc, "Failed to schedule ADD operations (%d)\n", rc); 12161 #if __FreeBSD_version < 800000 12162 IF_ADDR_UNLOCK(ifp); 12163 #else 12164 if_addr_runlock(ifp); 12165 #endif 12166 return (rc); 12167 } 12168 12169 ifa = CK_STAILQ_NEXT(ifa, ifa_link); 12170 } 12171 12172 #if __FreeBSD_version < 800000 12173 IF_ADDR_UNLOCK(ifp); 12174 #else 12175 if_addr_runlock(ifp); 12176 #endif 12177 12178 /* Execute the pending commands */ 12179 bit_set(&ramrod_flags, RAMROD_CONT); 12180 return (bxe_set_mac_one(sc, NULL, mac_obj, FALSE /* don't care */, 12181 ECORE_UC_LIST_MAC, &ramrod_flags)); 12182 } 12183 12184 static void 12185 bxe_set_rx_mode(struct bxe_softc *sc) 12186 { 12187 if_t ifp = sc->ifp; 12188 uint32_t rx_mode = BXE_RX_MODE_NORMAL; 12189 12190 if (sc->state != BXE_STATE_OPEN) { 12191 BLOGD(sc, DBG_SP, "state is %x, returning\n", sc->state); 12192 return; 12193 } 12194 12195 BLOGD(sc, DBG_SP, "if_flags(ifp)=0x%x\n", if_getflags(sc->ifp)); 12196 12197 if (if_getflags(ifp) & IFF_PROMISC) { 12198 rx_mode = BXE_RX_MODE_PROMISC; 12199 } else if ((if_getflags(ifp) & IFF_ALLMULTI) || 12200 ((if_getamcount(ifp) > BXE_MAX_MULTICAST) && 12201 CHIP_IS_E1(sc))) { 12202 rx_mode = BXE_RX_MODE_ALLMULTI; 12203 } else { 12204 if (IS_PF(sc)) { 12205 /* some multicasts */ 12206 if (bxe_set_mc_list(sc) < 0) { 12207 rx_mode = BXE_RX_MODE_ALLMULTI; 12208 } 12209 if (bxe_set_uc_list(sc) < 0) { 12210 rx_mode = BXE_RX_MODE_PROMISC; 12211 } 12212 } 12213 } 12214 12215 sc->rx_mode = rx_mode; 12216 12217 /* schedule the rx_mode command */ 12218 if (bxe_test_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state)) { 12219 BLOGD(sc, DBG_LOAD, "Scheduled setting rx_mode with ECORE...\n"); 12220 bxe_set_bit(ECORE_FILTER_RX_MODE_SCHED, &sc->sp_state); 12221 return; 12222 } 12223 12224 if (IS_PF(sc)) { 12225 bxe_set_storm_rx_mode(sc); 12226 } 12227 } 12228 12229 12230 /* update flags in shmem */ 12231 static void 12232 bxe_update_drv_flags(struct bxe_softc *sc, 12233 uint32_t flags, 12234 uint32_t set) 12235 { 12236 uint32_t drv_flags; 12237 12238 if (SHMEM2_HAS(sc, drv_flags)) { 12239 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_DRV_FLAGS); 12240 drv_flags = SHMEM2_RD(sc, drv_flags); 12241 12242 if (set) { 12243 SET_FLAGS(drv_flags, flags); 12244 } else { 12245 RESET_FLAGS(drv_flags, flags); 12246 } 12247 12248 SHMEM2_WR(sc, drv_flags, drv_flags); 12249 BLOGD(sc, DBG_LOAD, "drv_flags 0x%08x\n", drv_flags); 12250 12251 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_DRV_FLAGS); 12252 } 12253 } 12254 12255 /* periodic timer callout routine, only runs when the interface is up */ 12256 12257 static void 12258 bxe_periodic_callout_func(void *xsc) 12259 { 12260 struct bxe_softc *sc = (struct bxe_softc *)xsc; 12261 int i; 12262 12263 if (!BXE_CORE_TRYLOCK(sc)) { 12264 /* just bail and try again next time */ 12265 12266 if ((sc->state == BXE_STATE_OPEN) && 12267 (atomic_load_acq_long(&sc->periodic_flags) == PERIODIC_GO)) { 12268 /* schedule the next periodic callout */ 12269 callout_reset(&sc->periodic_callout, hz, 12270 bxe_periodic_callout_func, sc); 12271 } 12272 12273 return; 12274 } 12275 12276 if ((sc->state != BXE_STATE_OPEN) || 12277 (atomic_load_acq_long(&sc->periodic_flags) == PERIODIC_STOP)) { 12278 BLOGW(sc, "periodic callout exit (state=0x%x)\n", sc->state); 12279 BXE_CORE_UNLOCK(sc); 12280 return; 12281 } 12282 12283 12284 /* Check for TX timeouts on any fastpath. */ 12285 FOR_EACH_QUEUE(sc, i) { 12286 if (bxe_watchdog(sc, &sc->fp[i]) != 0) { 12287 /* Ruh-Roh, chip was reset! */ 12288 break; 12289 } 12290 } 12291 12292 if (!CHIP_REV_IS_SLOW(sc)) { 12293 /* 12294 * This barrier is needed to ensure the ordering between the writing 12295 * to the sc->port.pmf in the bxe_nic_load() or bxe_pmf_update() and 12296 * the reading here. 12297 */ 12298 mb(); 12299 if (sc->port.pmf) { 12300 bxe_acquire_phy_lock(sc); 12301 elink_period_func(&sc->link_params, &sc->link_vars); 12302 bxe_release_phy_lock(sc); 12303 } 12304 } 12305 12306 if (IS_PF(sc) && !(sc->flags & BXE_NO_PULSE)) { 12307 int mb_idx = SC_FW_MB_IDX(sc); 12308 uint32_t drv_pulse; 12309 uint32_t mcp_pulse; 12310 12311 ++sc->fw_drv_pulse_wr_seq; 12312 sc->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK; 12313 12314 drv_pulse = sc->fw_drv_pulse_wr_seq; 12315 bxe_drv_pulse(sc); 12316 12317 mcp_pulse = (SHMEM_RD(sc, func_mb[mb_idx].mcp_pulse_mb) & 12318 MCP_PULSE_SEQ_MASK); 12319 12320 /* 12321 * The delta between driver pulse and mcp response should 12322 * be 1 (before mcp response) or 0 (after mcp response). 12323 */ 12324 if ((drv_pulse != mcp_pulse) && 12325 (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) { 12326 /* someone lost a heartbeat... */ 12327 BLOGE(sc, "drv_pulse (0x%x) != mcp_pulse (0x%x)\n", 12328 drv_pulse, mcp_pulse); 12329 } 12330 } 12331 12332 /* state is BXE_STATE_OPEN */ 12333 bxe_stats_handle(sc, STATS_EVENT_UPDATE); 12334 12335 BXE_CORE_UNLOCK(sc); 12336 12337 if ((sc->state == BXE_STATE_OPEN) && 12338 (atomic_load_acq_long(&sc->periodic_flags) == PERIODIC_GO)) { 12339 /* schedule the next periodic callout */ 12340 callout_reset(&sc->periodic_callout, hz, 12341 bxe_periodic_callout_func, sc); 12342 } 12343 } 12344 12345 static void 12346 bxe_periodic_start(struct bxe_softc *sc) 12347 { 12348 atomic_store_rel_long(&sc->periodic_flags, PERIODIC_GO); 12349 callout_reset(&sc->periodic_callout, hz, bxe_periodic_callout_func, sc); 12350 } 12351 12352 static void 12353 bxe_periodic_stop(struct bxe_softc *sc) 12354 { 12355 atomic_store_rel_long(&sc->periodic_flags, PERIODIC_STOP); 12356 callout_drain(&sc->periodic_callout); 12357 } 12358 12359 /* start the controller */ 12360 static __noinline int 12361 bxe_nic_load(struct bxe_softc *sc, 12362 int load_mode) 12363 { 12364 uint32_t val; 12365 int load_code = 0; 12366 int i, rc = 0; 12367 12368 BXE_CORE_LOCK_ASSERT(sc); 12369 12370 BLOGD(sc, DBG_LOAD, "Starting NIC load...\n"); 12371 12372 sc->state = BXE_STATE_OPENING_WAITING_LOAD; 12373 12374 if (IS_PF(sc)) { 12375 /* must be called before memory allocation and HW init */ 12376 bxe_ilt_set_info(sc); 12377 } 12378 12379 sc->last_reported_link_state = LINK_STATE_UNKNOWN; 12380 12381 bxe_set_fp_rx_buf_size(sc); 12382 12383 if (bxe_alloc_fp_buffers(sc) != 0) { 12384 BLOGE(sc, "Failed to allocate fastpath memory\n"); 12385 sc->state = BXE_STATE_CLOSED; 12386 rc = ENOMEM; 12387 goto bxe_nic_load_error0; 12388 } 12389 12390 if (bxe_alloc_mem(sc) != 0) { 12391 sc->state = BXE_STATE_CLOSED; 12392 rc = ENOMEM; 12393 goto bxe_nic_load_error0; 12394 } 12395 12396 if (bxe_alloc_fw_stats_mem(sc) != 0) { 12397 sc->state = BXE_STATE_CLOSED; 12398 rc = ENOMEM; 12399 goto bxe_nic_load_error0; 12400 } 12401 12402 if (IS_PF(sc)) { 12403 /* set pf load just before approaching the MCP */ 12404 bxe_set_pf_load(sc); 12405 12406 /* if MCP exists send load request and analyze response */ 12407 if (!BXE_NOMCP(sc)) { 12408 /* attempt to load pf */ 12409 if (bxe_nic_load_request(sc, &load_code) != 0) { 12410 sc->state = BXE_STATE_CLOSED; 12411 rc = ENXIO; 12412 goto bxe_nic_load_error1; 12413 } 12414 12415 /* what did the MCP say? */ 12416 if (bxe_nic_load_analyze_req(sc, load_code) != 0) { 12417 bxe_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0); 12418 sc->state = BXE_STATE_CLOSED; 12419 rc = ENXIO; 12420 goto bxe_nic_load_error2; 12421 } 12422 } else { 12423 BLOGI(sc, "Device has no MCP!\n"); 12424 load_code = bxe_nic_load_no_mcp(sc); 12425 } 12426 12427 /* mark PMF if applicable */ 12428 bxe_nic_load_pmf(sc, load_code); 12429 12430 /* Init Function state controlling object */ 12431 bxe_init_func_obj(sc); 12432 12433 /* Initialize HW */ 12434 if (bxe_init_hw(sc, load_code) != 0) { 12435 BLOGE(sc, "HW init failed\n"); 12436 bxe_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0); 12437 sc->state = BXE_STATE_CLOSED; 12438 rc = ENXIO; 12439 goto bxe_nic_load_error2; 12440 } 12441 } 12442 12443 /* set ALWAYS_ALIVE bit in shmem */ 12444 sc->fw_drv_pulse_wr_seq |= DRV_PULSE_ALWAYS_ALIVE; 12445 bxe_drv_pulse(sc); 12446 sc->flags |= BXE_NO_PULSE; 12447 12448 /* attach interrupts */ 12449 if (bxe_interrupt_attach(sc) != 0) { 12450 sc->state = BXE_STATE_CLOSED; 12451 rc = ENXIO; 12452 goto bxe_nic_load_error2; 12453 } 12454 12455 bxe_nic_init(sc, load_code); 12456 12457 /* Init per-function objects */ 12458 if (IS_PF(sc)) { 12459 bxe_init_objs(sc); 12460 // XXX bxe_iov_nic_init(sc); 12461 12462 /* set AFEX default VLAN tag to an invalid value */ 12463 sc->devinfo.mf_info.afex_def_vlan_tag = -1; 12464 // XXX bxe_nic_load_afex_dcc(sc, load_code); 12465 12466 sc->state = BXE_STATE_OPENING_WAITING_PORT; 12467 rc = bxe_func_start(sc); 12468 if (rc) { 12469 BLOGE(sc, "Function start failed! rc = %d\n", rc); 12470 bxe_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0); 12471 sc->state = BXE_STATE_ERROR; 12472 goto bxe_nic_load_error3; 12473 } 12474 12475 /* send LOAD_DONE command to MCP */ 12476 if (!BXE_NOMCP(sc)) { 12477 load_code = bxe_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0); 12478 if (!load_code) { 12479 BLOGE(sc, "MCP response failure, aborting\n"); 12480 sc->state = BXE_STATE_ERROR; 12481 rc = ENXIO; 12482 goto bxe_nic_load_error3; 12483 } 12484 } 12485 12486 rc = bxe_setup_leading(sc); 12487 if (rc) { 12488 BLOGE(sc, "Setup leading failed! rc = %d\n", rc); 12489 sc->state = BXE_STATE_ERROR; 12490 goto bxe_nic_load_error3; 12491 } 12492 12493 FOR_EACH_NONDEFAULT_ETH_QUEUE(sc, i) { 12494 rc = bxe_setup_queue(sc, &sc->fp[i], FALSE); 12495 if (rc) { 12496 BLOGE(sc, "Queue(%d) setup failed rc = %d\n", i, rc); 12497 sc->state = BXE_STATE_ERROR; 12498 goto bxe_nic_load_error3; 12499 } 12500 } 12501 12502 rc = bxe_init_rss_pf(sc); 12503 if (rc) { 12504 BLOGE(sc, "PF RSS init failed\n"); 12505 sc->state = BXE_STATE_ERROR; 12506 goto bxe_nic_load_error3; 12507 } 12508 } 12509 /* XXX VF */ 12510 12511 /* now when Clients are configured we are ready to work */ 12512 sc->state = BXE_STATE_OPEN; 12513 12514 /* Configure a ucast MAC */ 12515 if (IS_PF(sc)) { 12516 rc = bxe_set_eth_mac(sc, TRUE); 12517 } 12518 if (rc) { 12519 BLOGE(sc, "Setting Ethernet MAC failed rc = %d\n", rc); 12520 sc->state = BXE_STATE_ERROR; 12521 goto bxe_nic_load_error3; 12522 } 12523 12524 if (sc->port.pmf) { 12525 rc = bxe_initial_phy_init(sc, /* XXX load_mode */LOAD_OPEN); 12526 if (rc) { 12527 sc->state = BXE_STATE_ERROR; 12528 goto bxe_nic_load_error3; 12529 } 12530 } 12531 12532 sc->link_params.feature_config_flags &= 12533 ~ELINK_FEATURE_CONFIG_BOOT_FROM_SAN; 12534 12535 /* start fast path */ 12536 12537 /* Initialize Rx filter */ 12538 bxe_set_rx_mode(sc); 12539 12540 /* start the Tx */ 12541 switch (/* XXX load_mode */LOAD_OPEN) { 12542 case LOAD_NORMAL: 12543 case LOAD_OPEN: 12544 break; 12545 12546 case LOAD_DIAG: 12547 case LOAD_LOOPBACK_EXT: 12548 sc->state = BXE_STATE_DIAG; 12549 break; 12550 12551 default: 12552 break; 12553 } 12554 12555 if (sc->port.pmf) { 12556 bxe_update_drv_flags(sc, 1 << DRV_FLAGS_PORT_MASK, 0); 12557 } else { 12558 bxe_link_status_update(sc); 12559 } 12560 12561 /* start the periodic timer callout */ 12562 bxe_periodic_start(sc); 12563 12564 if (IS_PF(sc) && SHMEM2_HAS(sc, drv_capabilities_flag)) { 12565 /* mark driver is loaded in shmem2 */ 12566 val = SHMEM2_RD(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)]); 12567 SHMEM2_WR(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)], 12568 (val | 12569 DRV_FLAGS_CAPABILITIES_LOADED_SUPPORTED | 12570 DRV_FLAGS_CAPABILITIES_LOADED_L2)); 12571 } 12572 12573 /* wait for all pending SP commands to complete */ 12574 if (IS_PF(sc) && !bxe_wait_sp_comp(sc, ~0x0UL)) { 12575 BLOGE(sc, "Timeout waiting for all SPs to complete!\n"); 12576 bxe_periodic_stop(sc); 12577 bxe_nic_unload(sc, UNLOAD_CLOSE, FALSE); 12578 return (ENXIO); 12579 } 12580 12581 /* Tell the stack the driver is running! */ 12582 if_setdrvflags(sc->ifp, IFF_DRV_RUNNING); 12583 12584 BLOGD(sc, DBG_LOAD, "NIC successfully loaded\n"); 12585 12586 return (0); 12587 12588 bxe_nic_load_error3: 12589 12590 if (IS_PF(sc)) { 12591 bxe_int_disable_sync(sc, 1); 12592 12593 /* clean out queued objects */ 12594 bxe_squeeze_objects(sc); 12595 } 12596 12597 bxe_interrupt_detach(sc); 12598 12599 bxe_nic_load_error2: 12600 12601 if (IS_PF(sc) && !BXE_NOMCP(sc)) { 12602 bxe_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0); 12603 bxe_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, 0); 12604 } 12605 12606 sc->port.pmf = 0; 12607 12608 bxe_nic_load_error1: 12609 12610 /* clear pf_load status, as it was already set */ 12611 if (IS_PF(sc)) { 12612 bxe_clear_pf_load(sc); 12613 } 12614 12615 bxe_nic_load_error0: 12616 12617 bxe_free_fw_stats_mem(sc); 12618 bxe_free_fp_buffers(sc); 12619 bxe_free_mem(sc); 12620 12621 return (rc); 12622 } 12623 12624 static int 12625 bxe_init_locked(struct bxe_softc *sc) 12626 { 12627 int other_engine = SC_PATH(sc) ? 0 : 1; 12628 uint8_t other_load_status, load_status; 12629 uint8_t global = FALSE; 12630 int rc; 12631 12632 BXE_CORE_LOCK_ASSERT(sc); 12633 12634 /* check if the driver is already running */ 12635 if (if_getdrvflags(sc->ifp) & IFF_DRV_RUNNING) { 12636 BLOGD(sc, DBG_LOAD, "Init called while driver is running!\n"); 12637 return (0); 12638 } 12639 12640 bxe_set_power_state(sc, PCI_PM_D0); 12641 12642 /* 12643 * If parity occurred during the unload, then attentions and/or 12644 * RECOVERY_IN_PROGRES may still be set. If so we want the first function 12645 * loaded on the current engine to complete the recovery. Parity recovery 12646 * is only relevant for PF driver. 12647 */ 12648 if (IS_PF(sc)) { 12649 other_load_status = bxe_get_load_status(sc, other_engine); 12650 load_status = bxe_get_load_status(sc, SC_PATH(sc)); 12651 12652 if (!bxe_reset_is_done(sc, SC_PATH(sc)) || 12653 bxe_chk_parity_attn(sc, &global, TRUE)) { 12654 do { 12655 /* 12656 * If there are attentions and they are in global blocks, set 12657 * the GLOBAL_RESET bit regardless whether it will be this 12658 * function that will complete the recovery or not. 12659 */ 12660 if (global) { 12661 bxe_set_reset_global(sc); 12662 } 12663 12664 /* 12665 * Only the first function on the current engine should try 12666 * to recover in open. In case of attentions in global blocks 12667 * only the first in the chip should try to recover. 12668 */ 12669 if ((!load_status && (!global || !other_load_status)) && 12670 bxe_trylock_leader_lock(sc) && !bxe_leader_reset(sc)) { 12671 BLOGI(sc, "Recovered during init\n"); 12672 break; 12673 } 12674 12675 /* recovery has failed... */ 12676 bxe_set_power_state(sc, PCI_PM_D3hot); 12677 sc->recovery_state = BXE_RECOVERY_FAILED; 12678 12679 BLOGE(sc, "Recovery flow hasn't properly " 12680 "completed yet, try again later. " 12681 "If you still see this message after a " 12682 "few retries then power cycle is required.\n"); 12683 12684 rc = ENXIO; 12685 goto bxe_init_locked_done; 12686 } while (0); 12687 } 12688 } 12689 12690 sc->recovery_state = BXE_RECOVERY_DONE; 12691 12692 rc = bxe_nic_load(sc, LOAD_OPEN); 12693 12694 bxe_init_locked_done: 12695 12696 if (rc) { 12697 /* Tell the stack the driver is NOT running! */ 12698 BLOGE(sc, "Initialization failed, " 12699 "stack notified driver is NOT running!\n"); 12700 if_setdrvflagbits(sc->ifp, 0, IFF_DRV_RUNNING); 12701 } 12702 12703 return (rc); 12704 } 12705 12706 static int 12707 bxe_stop_locked(struct bxe_softc *sc) 12708 { 12709 BXE_CORE_LOCK_ASSERT(sc); 12710 return (bxe_nic_unload(sc, UNLOAD_NORMAL, TRUE)); 12711 } 12712 12713 /* 12714 * Handles controller initialization when called from an unlocked routine. 12715 * ifconfig calls this function. 12716 * 12717 * Returns: 12718 * void 12719 */ 12720 static void 12721 bxe_init(void *xsc) 12722 { 12723 struct bxe_softc *sc = (struct bxe_softc *)xsc; 12724 12725 BXE_CORE_LOCK(sc); 12726 bxe_init_locked(sc); 12727 BXE_CORE_UNLOCK(sc); 12728 } 12729 12730 static int 12731 bxe_init_ifnet(struct bxe_softc *sc) 12732 { 12733 if_t ifp; 12734 int capabilities; 12735 12736 /* ifconfig entrypoint for media type/status reporting */ 12737 ifmedia_init(&sc->ifmedia, IFM_IMASK, 12738 bxe_ifmedia_update, 12739 bxe_ifmedia_status); 12740 12741 /* set the default interface values */ 12742 ifmedia_add(&sc->ifmedia, (IFM_ETHER | IFM_FDX | sc->media), 0, NULL); 12743 ifmedia_add(&sc->ifmedia, (IFM_ETHER | IFM_AUTO), 0, NULL); 12744 ifmedia_set(&sc->ifmedia, (IFM_ETHER | IFM_AUTO)); 12745 12746 sc->ifmedia.ifm_media = sc->ifmedia.ifm_cur->ifm_media; /* XXX ? */ 12747 BLOGI(sc, "IFMEDIA flags : %x\n", sc->ifmedia.ifm_media); 12748 12749 /* allocate the ifnet structure */ 12750 if ((ifp = if_gethandle(IFT_ETHER)) == NULL) { 12751 BLOGE(sc, "Interface allocation failed!\n"); 12752 return (ENXIO); 12753 } 12754 12755 if_setsoftc(ifp, sc); 12756 if_initname(ifp, device_get_name(sc->dev), device_get_unit(sc->dev)); 12757 if_setflags(ifp, (IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST)); 12758 if_setioctlfn(ifp, bxe_ioctl); 12759 if_setstartfn(ifp, bxe_tx_start); 12760 if_setgetcounterfn(ifp, bxe_get_counter); 12761 #if __FreeBSD_version >= 901504 12762 if_settransmitfn(ifp, bxe_tx_mq_start); 12763 if_setqflushfn(ifp, bxe_mq_flush); 12764 #endif 12765 #ifdef FreeBSD8_0 12766 if_settimer(ifp, 0); 12767 #endif 12768 if_setinitfn(ifp, bxe_init); 12769 if_setmtu(ifp, sc->mtu); 12770 if_sethwassist(ifp, (CSUM_IP | 12771 CSUM_TCP | 12772 CSUM_UDP | 12773 CSUM_TSO | 12774 CSUM_TCP_IPV6 | 12775 CSUM_UDP_IPV6)); 12776 12777 capabilities = 12778 #if __FreeBSD_version < 700000 12779 (IFCAP_VLAN_MTU | 12780 IFCAP_VLAN_HWTAGGING | 12781 IFCAP_HWCSUM | 12782 IFCAP_JUMBO_MTU | 12783 IFCAP_LRO); 12784 #else 12785 (IFCAP_VLAN_MTU | 12786 IFCAP_VLAN_HWTAGGING | 12787 IFCAP_VLAN_HWTSO | 12788 IFCAP_VLAN_HWFILTER | 12789 IFCAP_VLAN_HWCSUM | 12790 IFCAP_HWCSUM | 12791 IFCAP_JUMBO_MTU | 12792 IFCAP_LRO | 12793 IFCAP_TSO4 | 12794 IFCAP_TSO6 | 12795 IFCAP_WOL_MAGIC); 12796 #endif 12797 if_setcapabilitiesbit(ifp, capabilities, 0); /* XXX */ 12798 if_setcapenable(ifp, if_getcapabilities(ifp)); 12799 if_setbaudrate(ifp, IF_Gbps(10)); 12800 /* XXX */ 12801 if_setsendqlen(ifp, sc->tx_ring_size); 12802 if_setsendqready(ifp); 12803 /* XXX */ 12804 12805 sc->ifp = ifp; 12806 12807 /* attach to the Ethernet interface list */ 12808 ether_ifattach(ifp, sc->link_params.mac_addr); 12809 12810 /* Attach driver netdump methods. */ 12811 NETDUMP_SET(ifp, bxe); 12812 12813 return (0); 12814 } 12815 12816 static void 12817 bxe_deallocate_bars(struct bxe_softc *sc) 12818 { 12819 int i; 12820 12821 for (i = 0; i < MAX_BARS; i++) { 12822 if (sc->bar[i].resource != NULL) { 12823 bus_release_resource(sc->dev, 12824 SYS_RES_MEMORY, 12825 sc->bar[i].rid, 12826 sc->bar[i].resource); 12827 BLOGD(sc, DBG_LOAD, "Released PCI BAR%d [%02x] memory\n", 12828 i, PCIR_BAR(i)); 12829 } 12830 } 12831 } 12832 12833 static int 12834 bxe_allocate_bars(struct bxe_softc *sc) 12835 { 12836 u_int flags; 12837 int i; 12838 12839 memset(sc->bar, 0, sizeof(sc->bar)); 12840 12841 for (i = 0; i < MAX_BARS; i++) { 12842 12843 /* memory resources reside at BARs 0, 2, 4 */ 12844 /* Run `pciconf -lb` to see mappings */ 12845 if ((i != 0) && (i != 2) && (i != 4)) { 12846 continue; 12847 } 12848 12849 sc->bar[i].rid = PCIR_BAR(i); 12850 12851 flags = RF_ACTIVE; 12852 if (i == 0) { 12853 flags |= RF_SHAREABLE; 12854 } 12855 12856 if ((sc->bar[i].resource = 12857 bus_alloc_resource_any(sc->dev, 12858 SYS_RES_MEMORY, 12859 &sc->bar[i].rid, 12860 flags)) == NULL) { 12861 return (0); 12862 } 12863 12864 sc->bar[i].tag = rman_get_bustag(sc->bar[i].resource); 12865 sc->bar[i].handle = rman_get_bushandle(sc->bar[i].resource); 12866 sc->bar[i].kva = (vm_offset_t)rman_get_virtual(sc->bar[i].resource); 12867 12868 BLOGI(sc, "PCI BAR%d [%02x] memory allocated: %#jx-%#jx (%jd) -> %#jx\n", 12869 i, PCIR_BAR(i), 12870 rman_get_start(sc->bar[i].resource), 12871 rman_get_end(sc->bar[i].resource), 12872 rman_get_size(sc->bar[i].resource), 12873 (uintmax_t)sc->bar[i].kva); 12874 } 12875 12876 return (0); 12877 } 12878 12879 static void 12880 bxe_get_function_num(struct bxe_softc *sc) 12881 { 12882 uint32_t val = 0; 12883 12884 /* 12885 * Read the ME register to get the function number. The ME register 12886 * holds the relative-function number and absolute-function number. The 12887 * absolute-function number appears only in E2 and above. Before that 12888 * these bits always contained zero, therefore we cannot blindly use them. 12889 */ 12890 12891 val = REG_RD(sc, BAR_ME_REGISTER); 12892 12893 sc->pfunc_rel = 12894 (uint8_t)((val & ME_REG_PF_NUM) >> ME_REG_PF_NUM_SHIFT); 12895 sc->path_id = 12896 (uint8_t)((val & ME_REG_ABS_PF_NUM) >> ME_REG_ABS_PF_NUM_SHIFT) & 1; 12897 12898 if (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) { 12899 sc->pfunc_abs = ((sc->pfunc_rel << 1) | sc->path_id); 12900 } else { 12901 sc->pfunc_abs = (sc->pfunc_rel | sc->path_id); 12902 } 12903 12904 BLOGD(sc, DBG_LOAD, 12905 "Relative function %d, Absolute function %d, Path %d\n", 12906 sc->pfunc_rel, sc->pfunc_abs, sc->path_id); 12907 } 12908 12909 static uint32_t 12910 bxe_get_shmem_mf_cfg_base(struct bxe_softc *sc) 12911 { 12912 uint32_t shmem2_size; 12913 uint32_t offset; 12914 uint32_t mf_cfg_offset_value; 12915 12916 /* Non 57712 */ 12917 offset = (SHMEM_RD(sc, func_mb) + 12918 (MAX_FUNC_NUM * sizeof(struct drv_func_mb))); 12919 12920 /* 57712 plus */ 12921 if (sc->devinfo.shmem2_base != 0) { 12922 shmem2_size = SHMEM2_RD(sc, size); 12923 if (shmem2_size > offsetof(struct shmem2_region, mf_cfg_addr)) { 12924 mf_cfg_offset_value = SHMEM2_RD(sc, mf_cfg_addr); 12925 if (SHMEM_MF_CFG_ADDR_NONE != mf_cfg_offset_value) { 12926 offset = mf_cfg_offset_value; 12927 } 12928 } 12929 } 12930 12931 return (offset); 12932 } 12933 12934 static uint32_t 12935 bxe_pcie_capability_read(struct bxe_softc *sc, 12936 int reg, 12937 int width) 12938 { 12939 int pcie_reg; 12940 12941 /* ensure PCIe capability is enabled */ 12942 if (pci_find_cap(sc->dev, PCIY_EXPRESS, &pcie_reg) == 0) { 12943 if (pcie_reg != 0) { 12944 BLOGD(sc, DBG_LOAD, "PCIe capability at 0x%04x\n", pcie_reg); 12945 return (pci_read_config(sc->dev, (pcie_reg + reg), width)); 12946 } 12947 } 12948 12949 BLOGE(sc, "PCIe capability NOT FOUND!!!\n"); 12950 12951 return (0); 12952 } 12953 12954 static uint8_t 12955 bxe_is_pcie_pending(struct bxe_softc *sc) 12956 { 12957 return (bxe_pcie_capability_read(sc, PCIR_EXPRESS_DEVICE_STA, 2) & 12958 PCIM_EXP_STA_TRANSACTION_PND); 12959 } 12960 12961 /* 12962 * Walk the PCI capabiites list for the device to find what features are 12963 * supported. These capabilites may be enabled/disabled by firmware so it's 12964 * best to walk the list rather than make assumptions. 12965 */ 12966 static void 12967 bxe_probe_pci_caps(struct bxe_softc *sc) 12968 { 12969 uint16_t link_status; 12970 int reg; 12971 12972 /* check if PCI Power Management is enabled */ 12973 if (pci_find_cap(sc->dev, PCIY_PMG, ®) == 0) { 12974 if (reg != 0) { 12975 BLOGD(sc, DBG_LOAD, "Found PM capability at 0x%04x\n", reg); 12976 12977 sc->devinfo.pcie_cap_flags |= BXE_PM_CAPABLE_FLAG; 12978 sc->devinfo.pcie_pm_cap_reg = (uint16_t)reg; 12979 } 12980 } 12981 12982 link_status = bxe_pcie_capability_read(sc, PCIR_EXPRESS_LINK_STA, 2); 12983 12984 /* handle PCIe 2.0 workarounds for 57710 */ 12985 if (CHIP_IS_E1(sc)) { 12986 /* workaround for 57710 errata E4_57710_27462 */ 12987 sc->devinfo.pcie_link_speed = 12988 (REG_RD(sc, 0x3d04) & (1 << 24)) ? 2 : 1; 12989 12990 /* workaround for 57710 errata E4_57710_27488 */ 12991 sc->devinfo.pcie_link_width = 12992 ((link_status & PCIM_LINK_STA_WIDTH) >> 4); 12993 if (sc->devinfo.pcie_link_speed > 1) { 12994 sc->devinfo.pcie_link_width = 12995 ((link_status & PCIM_LINK_STA_WIDTH) >> 4) >> 1; 12996 } 12997 } else { 12998 sc->devinfo.pcie_link_speed = 12999 (link_status & PCIM_LINK_STA_SPEED); 13000 sc->devinfo.pcie_link_width = 13001 ((link_status & PCIM_LINK_STA_WIDTH) >> 4); 13002 } 13003 13004 BLOGD(sc, DBG_LOAD, "PCIe link speed=%d width=%d\n", 13005 sc->devinfo.pcie_link_speed, sc->devinfo.pcie_link_width); 13006 13007 sc->devinfo.pcie_cap_flags |= BXE_PCIE_CAPABLE_FLAG; 13008 sc->devinfo.pcie_pcie_cap_reg = (uint16_t)reg; 13009 13010 /* check if MSI capability is enabled */ 13011 if (pci_find_cap(sc->dev, PCIY_MSI, ®) == 0) { 13012 if (reg != 0) { 13013 BLOGD(sc, DBG_LOAD, "Found MSI capability at 0x%04x\n", reg); 13014 13015 sc->devinfo.pcie_cap_flags |= BXE_MSI_CAPABLE_FLAG; 13016 sc->devinfo.pcie_msi_cap_reg = (uint16_t)reg; 13017 } 13018 } 13019 13020 /* check if MSI-X capability is enabled */ 13021 if (pci_find_cap(sc->dev, PCIY_MSIX, ®) == 0) { 13022 if (reg != 0) { 13023 BLOGD(sc, DBG_LOAD, "Found MSI-X capability at 0x%04x\n", reg); 13024 13025 sc->devinfo.pcie_cap_flags |= BXE_MSIX_CAPABLE_FLAG; 13026 sc->devinfo.pcie_msix_cap_reg = (uint16_t)reg; 13027 } 13028 } 13029 } 13030 13031 static int 13032 bxe_get_shmem_mf_cfg_info_sd(struct bxe_softc *sc) 13033 { 13034 struct bxe_mf_info *mf_info = &sc->devinfo.mf_info; 13035 uint32_t val; 13036 13037 /* get the outer vlan if we're in switch-dependent mode */ 13038 13039 val = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag); 13040 mf_info->ext_id = (uint16_t)val; 13041 13042 mf_info->multi_vnics_mode = 1; 13043 13044 if (!VALID_OVLAN(mf_info->ext_id)) { 13045 BLOGE(sc, "Invalid VLAN (%d)\n", mf_info->ext_id); 13046 return (1); 13047 } 13048 13049 /* get the capabilities */ 13050 if ((mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_PROTOCOL_MASK) == 13051 FUNC_MF_CFG_PROTOCOL_ISCSI) { 13052 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_ISCSI; 13053 } else if ((mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_PROTOCOL_MASK) == 13054 FUNC_MF_CFG_PROTOCOL_FCOE) { 13055 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_FCOE; 13056 } else { 13057 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_ETHERNET; 13058 } 13059 13060 mf_info->vnics_per_port = 13061 (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4; 13062 13063 return (0); 13064 } 13065 13066 static uint32_t 13067 bxe_get_shmem_ext_proto_support_flags(struct bxe_softc *sc) 13068 { 13069 uint32_t retval = 0; 13070 uint32_t val; 13071 13072 val = MFCFG_RD(sc, func_ext_config[SC_ABS_FUNC(sc)].func_cfg); 13073 13074 if (val & MACP_FUNC_CFG_FLAGS_ENABLED) { 13075 if (val & MACP_FUNC_CFG_FLAGS_ETHERNET) { 13076 retval |= MF_PROTO_SUPPORT_ETHERNET; 13077 } 13078 if (val & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) { 13079 retval |= MF_PROTO_SUPPORT_ISCSI; 13080 } 13081 if (val & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) { 13082 retval |= MF_PROTO_SUPPORT_FCOE; 13083 } 13084 } 13085 13086 return (retval); 13087 } 13088 13089 static int 13090 bxe_get_shmem_mf_cfg_info_si(struct bxe_softc *sc) 13091 { 13092 struct bxe_mf_info *mf_info = &sc->devinfo.mf_info; 13093 uint32_t val; 13094 13095 /* 13096 * There is no outer vlan if we're in switch-independent mode. 13097 * If the mac is valid then assume multi-function. 13098 */ 13099 13100 val = MFCFG_RD(sc, func_ext_config[SC_ABS_FUNC(sc)].func_cfg); 13101 13102 mf_info->multi_vnics_mode = ((val & MACP_FUNC_CFG_FLAGS_MASK) != 0); 13103 13104 mf_info->mf_protos_supported = bxe_get_shmem_ext_proto_support_flags(sc); 13105 13106 mf_info->vnics_per_port = 13107 (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4; 13108 13109 return (0); 13110 } 13111 13112 static int 13113 bxe_get_shmem_mf_cfg_info_niv(struct bxe_softc *sc) 13114 { 13115 struct bxe_mf_info *mf_info = &sc->devinfo.mf_info; 13116 uint32_t e1hov_tag; 13117 uint32_t func_config; 13118 uint32_t niv_config; 13119 13120 mf_info->multi_vnics_mode = 1; 13121 13122 e1hov_tag = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag); 13123 func_config = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].config); 13124 niv_config = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].afex_config); 13125 13126 mf_info->ext_id = 13127 (uint16_t)((e1hov_tag & FUNC_MF_CFG_E1HOV_TAG_MASK) >> 13128 FUNC_MF_CFG_E1HOV_TAG_SHIFT); 13129 13130 mf_info->default_vlan = 13131 (uint16_t)((e1hov_tag & FUNC_MF_CFG_AFEX_VLAN_MASK) >> 13132 FUNC_MF_CFG_AFEX_VLAN_SHIFT); 13133 13134 mf_info->niv_allowed_priorities = 13135 (uint8_t)((niv_config & FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >> 13136 FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT); 13137 13138 mf_info->niv_default_cos = 13139 (uint8_t)((func_config & FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >> 13140 FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT); 13141 13142 mf_info->afex_vlan_mode = 13143 ((niv_config & FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >> 13144 FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT); 13145 13146 mf_info->niv_mba_enabled = 13147 ((niv_config & FUNC_MF_CFG_AFEX_MBA_ENABLED_MASK) >> 13148 FUNC_MF_CFG_AFEX_MBA_ENABLED_SHIFT); 13149 13150 mf_info->mf_protos_supported = bxe_get_shmem_ext_proto_support_flags(sc); 13151 13152 mf_info->vnics_per_port = 13153 (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4; 13154 13155 return (0); 13156 } 13157 13158 static int 13159 bxe_check_valid_mf_cfg(struct bxe_softc *sc) 13160 { 13161 struct bxe_mf_info *mf_info = &sc->devinfo.mf_info; 13162 uint32_t mf_cfg1; 13163 uint32_t mf_cfg2; 13164 uint32_t ovlan1; 13165 uint32_t ovlan2; 13166 uint8_t i, j; 13167 13168 BLOGD(sc, DBG_LOAD, "MF config parameters for function %d\n", 13169 SC_PORT(sc)); 13170 BLOGD(sc, DBG_LOAD, "\tmf_config=0x%x\n", 13171 mf_info->mf_config[SC_VN(sc)]); 13172 BLOGD(sc, DBG_LOAD, "\tmulti_vnics_mode=%d\n", 13173 mf_info->multi_vnics_mode); 13174 BLOGD(sc, DBG_LOAD, "\tvnics_per_port=%d\n", 13175 mf_info->vnics_per_port); 13176 BLOGD(sc, DBG_LOAD, "\tovlan/vifid=%d\n", 13177 mf_info->ext_id); 13178 BLOGD(sc, DBG_LOAD, "\tmin_bw=%d/%d/%d/%d\n", 13179 mf_info->min_bw[0], mf_info->min_bw[1], 13180 mf_info->min_bw[2], mf_info->min_bw[3]); 13181 BLOGD(sc, DBG_LOAD, "\tmax_bw=%d/%d/%d/%d\n", 13182 mf_info->max_bw[0], mf_info->max_bw[1], 13183 mf_info->max_bw[2], mf_info->max_bw[3]); 13184 BLOGD(sc, DBG_LOAD, "\tmac_addr: %s\n", 13185 sc->mac_addr_str); 13186 13187 /* various MF mode sanity checks... */ 13188 13189 if (mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_FUNC_HIDE) { 13190 BLOGE(sc, "Enumerated function %d is marked as hidden\n", 13191 SC_PORT(sc)); 13192 return (1); 13193 } 13194 13195 if ((mf_info->vnics_per_port > 1) && !mf_info->multi_vnics_mode) { 13196 BLOGE(sc, "vnics_per_port=%d multi_vnics_mode=%d\n", 13197 mf_info->vnics_per_port, mf_info->multi_vnics_mode); 13198 return (1); 13199 } 13200 13201 if (mf_info->mf_mode == MULTI_FUNCTION_SD) { 13202 /* vnic id > 0 must have valid ovlan in switch-dependent mode */ 13203 if ((SC_VN(sc) > 0) && !VALID_OVLAN(OVLAN(sc))) { 13204 BLOGE(sc, "mf_mode=SD vnic_id=%d ovlan=%d\n", 13205 SC_VN(sc), OVLAN(sc)); 13206 return (1); 13207 } 13208 13209 if (!VALID_OVLAN(OVLAN(sc)) && mf_info->multi_vnics_mode) { 13210 BLOGE(sc, "mf_mode=SD multi_vnics_mode=%d ovlan=%d\n", 13211 mf_info->multi_vnics_mode, OVLAN(sc)); 13212 return (1); 13213 } 13214 13215 /* 13216 * Verify all functions are either MF or SF mode. If MF, make sure 13217 * sure that all non-hidden functions have a valid ovlan. If SF, 13218 * make sure that all non-hidden functions have an invalid ovlan. 13219 */ 13220 FOREACH_ABS_FUNC_IN_PORT(sc, i) { 13221 mf_cfg1 = MFCFG_RD(sc, func_mf_config[i].config); 13222 ovlan1 = MFCFG_RD(sc, func_mf_config[i].e1hov_tag); 13223 if (!(mf_cfg1 & FUNC_MF_CFG_FUNC_HIDE) && 13224 (((mf_info->multi_vnics_mode) && !VALID_OVLAN(ovlan1)) || 13225 ((!mf_info->multi_vnics_mode) && VALID_OVLAN(ovlan1)))) { 13226 BLOGE(sc, "mf_mode=SD function %d MF config " 13227 "mismatch, multi_vnics_mode=%d ovlan=%d\n", 13228 i, mf_info->multi_vnics_mode, ovlan1); 13229 return (1); 13230 } 13231 } 13232 13233 /* Verify all funcs on the same port each have a different ovlan. */ 13234 FOREACH_ABS_FUNC_IN_PORT(sc, i) { 13235 mf_cfg1 = MFCFG_RD(sc, func_mf_config[i].config); 13236 ovlan1 = MFCFG_RD(sc, func_mf_config[i].e1hov_tag); 13237 /* iterate from the next function on the port to the max func */ 13238 for (j = i + 2; j < MAX_FUNC_NUM; j += 2) { 13239 mf_cfg2 = MFCFG_RD(sc, func_mf_config[j].config); 13240 ovlan2 = MFCFG_RD(sc, func_mf_config[j].e1hov_tag); 13241 if (!(mf_cfg1 & FUNC_MF_CFG_FUNC_HIDE) && 13242 VALID_OVLAN(ovlan1) && 13243 !(mf_cfg2 & FUNC_MF_CFG_FUNC_HIDE) && 13244 VALID_OVLAN(ovlan2) && 13245 (ovlan1 == ovlan2)) { 13246 BLOGE(sc, "mf_mode=SD functions %d and %d " 13247 "have the same ovlan (%d)\n", 13248 i, j, ovlan1); 13249 return (1); 13250 } 13251 } 13252 } 13253 } /* MULTI_FUNCTION_SD */ 13254 13255 return (0); 13256 } 13257 13258 static int 13259 bxe_get_mf_cfg_info(struct bxe_softc *sc) 13260 { 13261 struct bxe_mf_info *mf_info = &sc->devinfo.mf_info; 13262 uint32_t val, mac_upper; 13263 uint8_t i, vnic; 13264 13265 /* initialize mf_info defaults */ 13266 mf_info->vnics_per_port = 1; 13267 mf_info->multi_vnics_mode = FALSE; 13268 mf_info->path_has_ovlan = FALSE; 13269 mf_info->mf_mode = SINGLE_FUNCTION; 13270 13271 if (!CHIP_IS_MF_CAP(sc)) { 13272 return (0); 13273 } 13274 13275 if (sc->devinfo.mf_cfg_base == SHMEM_MF_CFG_ADDR_NONE) { 13276 BLOGE(sc, "Invalid mf_cfg_base!\n"); 13277 return (1); 13278 } 13279 13280 /* get the MF mode (switch dependent / independent / single-function) */ 13281 13282 val = SHMEM_RD(sc, dev_info.shared_feature_config.config); 13283 13284 switch (val & SHARED_FEAT_CFG_FORCE_SF_MODE_MASK) 13285 { 13286 case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT: 13287 13288 mac_upper = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper); 13289 13290 /* check for legal upper mac bytes */ 13291 if (mac_upper != FUNC_MF_CFG_UPPERMAC_DEFAULT) { 13292 mf_info->mf_mode = MULTI_FUNCTION_SI; 13293 } else { 13294 BLOGE(sc, "Invalid config for Switch Independent mode\n"); 13295 } 13296 13297 break; 13298 13299 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED: 13300 case SHARED_FEAT_CFG_FORCE_SF_MODE_SPIO4: 13301 13302 /* get outer vlan configuration */ 13303 val = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag); 13304 13305 if ((val & FUNC_MF_CFG_E1HOV_TAG_MASK) != 13306 FUNC_MF_CFG_E1HOV_TAG_DEFAULT) { 13307 mf_info->mf_mode = MULTI_FUNCTION_SD; 13308 } else { 13309 BLOGE(sc, "Invalid config for Switch Dependent mode\n"); 13310 } 13311 13312 break; 13313 13314 case SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF: 13315 13316 /* not in MF mode, vnics_per_port=1 and multi_vnics_mode=FALSE */ 13317 return (0); 13318 13319 case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE: 13320 13321 /* 13322 * Mark MF mode as NIV if MCP version includes NPAR-SD support 13323 * and the MAC address is valid. 13324 */ 13325 mac_upper = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper); 13326 13327 if ((SHMEM2_HAS(sc, afex_driver_support)) && 13328 (mac_upper != FUNC_MF_CFG_UPPERMAC_DEFAULT)) { 13329 mf_info->mf_mode = MULTI_FUNCTION_AFEX; 13330 } else { 13331 BLOGE(sc, "Invalid config for AFEX mode\n"); 13332 } 13333 13334 break; 13335 13336 default: 13337 13338 BLOGE(sc, "Unknown MF mode (0x%08x)\n", 13339 (val & SHARED_FEAT_CFG_FORCE_SF_MODE_MASK)); 13340 13341 return (1); 13342 } 13343 13344 /* set path mf_mode (which could be different than function mf_mode) */ 13345 if (mf_info->mf_mode == MULTI_FUNCTION_SD) { 13346 mf_info->path_has_ovlan = TRUE; 13347 } else if (mf_info->mf_mode == SINGLE_FUNCTION) { 13348 /* 13349 * Decide on path multi vnics mode. If we're not in MF mode and in 13350 * 4-port mode, this is good enough to check vnic-0 of the other port 13351 * on the same path 13352 */ 13353 if (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) { 13354 uint8_t other_port = !(PORT_ID(sc) & 1); 13355 uint8_t abs_func_other_port = (SC_PATH(sc) + (2 * other_port)); 13356 13357 val = MFCFG_RD(sc, func_mf_config[abs_func_other_port].e1hov_tag); 13358 13359 mf_info->path_has_ovlan = VALID_OVLAN((uint16_t)val) ? 1 : 0; 13360 } 13361 } 13362 13363 if (mf_info->mf_mode == SINGLE_FUNCTION) { 13364 /* invalid MF config */ 13365 if (SC_VN(sc) >= 1) { 13366 BLOGE(sc, "VNIC ID >= 1 in SF mode\n"); 13367 return (1); 13368 } 13369 13370 return (0); 13371 } 13372 13373 /* get the MF configuration */ 13374 mf_info->mf_config[SC_VN(sc)] = 13375 MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].config); 13376 13377 switch(mf_info->mf_mode) 13378 { 13379 case MULTI_FUNCTION_SD: 13380 13381 bxe_get_shmem_mf_cfg_info_sd(sc); 13382 break; 13383 13384 case MULTI_FUNCTION_SI: 13385 13386 bxe_get_shmem_mf_cfg_info_si(sc); 13387 break; 13388 13389 case MULTI_FUNCTION_AFEX: 13390 13391 bxe_get_shmem_mf_cfg_info_niv(sc); 13392 break; 13393 13394 default: 13395 13396 BLOGE(sc, "Get MF config failed (mf_mode=0x%08x)\n", 13397 mf_info->mf_mode); 13398 return (1); 13399 } 13400 13401 /* get the congestion management parameters */ 13402 13403 vnic = 0; 13404 FOREACH_ABS_FUNC_IN_PORT(sc, i) { 13405 /* get min/max bw */ 13406 val = MFCFG_RD(sc, func_mf_config[i].config); 13407 mf_info->min_bw[vnic] = 13408 ((val & FUNC_MF_CFG_MIN_BW_MASK) >> FUNC_MF_CFG_MIN_BW_SHIFT); 13409 mf_info->max_bw[vnic] = 13410 ((val & FUNC_MF_CFG_MAX_BW_MASK) >> FUNC_MF_CFG_MAX_BW_SHIFT); 13411 vnic++; 13412 } 13413 13414 return (bxe_check_valid_mf_cfg(sc)); 13415 } 13416 13417 static int 13418 bxe_get_shmem_info(struct bxe_softc *sc) 13419 { 13420 int port; 13421 uint32_t mac_hi, mac_lo, val; 13422 13423 port = SC_PORT(sc); 13424 mac_hi = mac_lo = 0; 13425 13426 sc->link_params.sc = sc; 13427 sc->link_params.port = port; 13428 13429 /* get the hardware config info */ 13430 sc->devinfo.hw_config = 13431 SHMEM_RD(sc, dev_info.shared_hw_config.config); 13432 sc->devinfo.hw_config2 = 13433 SHMEM_RD(sc, dev_info.shared_hw_config.config2); 13434 13435 sc->link_params.hw_led_mode = 13436 ((sc->devinfo.hw_config & SHARED_HW_CFG_LED_MODE_MASK) >> 13437 SHARED_HW_CFG_LED_MODE_SHIFT); 13438 13439 /* get the port feature config */ 13440 sc->port.config = 13441 SHMEM_RD(sc, dev_info.port_feature_config[port].config); 13442 13443 /* get the link params */ 13444 sc->link_params.speed_cap_mask[0] = 13445 SHMEM_RD(sc, dev_info.port_hw_config[port].speed_capability_mask); 13446 sc->link_params.speed_cap_mask[1] = 13447 SHMEM_RD(sc, dev_info.port_hw_config[port].speed_capability_mask2); 13448 13449 /* get the lane config */ 13450 sc->link_params.lane_config = 13451 SHMEM_RD(sc, dev_info.port_hw_config[port].lane_config); 13452 13453 /* get the link config */ 13454 val = SHMEM_RD(sc, dev_info.port_feature_config[port].link_config); 13455 sc->port.link_config[ELINK_INT_PHY] = val; 13456 sc->link_params.switch_cfg = (val & PORT_FEATURE_CONNECTED_SWITCH_MASK); 13457 sc->port.link_config[ELINK_EXT_PHY1] = 13458 SHMEM_RD(sc, dev_info.port_feature_config[port].link_config2); 13459 13460 /* get the override preemphasis flag and enable it or turn it off */ 13461 val = SHMEM_RD(sc, dev_info.shared_feature_config.config); 13462 if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED) { 13463 sc->link_params.feature_config_flags |= 13464 ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED; 13465 } else { 13466 sc->link_params.feature_config_flags &= 13467 ~ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED; 13468 } 13469 13470 /* get the initial value of the link params */ 13471 sc->link_params.multi_phy_config = 13472 SHMEM_RD(sc, dev_info.port_hw_config[port].multi_phy_config); 13473 13474 /* get external phy info */ 13475 sc->port.ext_phy_config = 13476 SHMEM_RD(sc, dev_info.port_hw_config[port].external_phy_config); 13477 13478 /* get the multifunction configuration */ 13479 bxe_get_mf_cfg_info(sc); 13480 13481 /* get the mac address */ 13482 if (IS_MF(sc)) { 13483 mac_hi = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper); 13484 mac_lo = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_lower); 13485 } else { 13486 mac_hi = SHMEM_RD(sc, dev_info.port_hw_config[port].mac_upper); 13487 mac_lo = SHMEM_RD(sc, dev_info.port_hw_config[port].mac_lower); 13488 } 13489 13490 if ((mac_lo == 0) && (mac_hi == 0)) { 13491 *sc->mac_addr_str = 0; 13492 BLOGE(sc, "No Ethernet address programmed!\n"); 13493 } else { 13494 sc->link_params.mac_addr[0] = (uint8_t)(mac_hi >> 8); 13495 sc->link_params.mac_addr[1] = (uint8_t)(mac_hi); 13496 sc->link_params.mac_addr[2] = (uint8_t)(mac_lo >> 24); 13497 sc->link_params.mac_addr[3] = (uint8_t)(mac_lo >> 16); 13498 sc->link_params.mac_addr[4] = (uint8_t)(mac_lo >> 8); 13499 sc->link_params.mac_addr[5] = (uint8_t)(mac_lo); 13500 snprintf(sc->mac_addr_str, sizeof(sc->mac_addr_str), 13501 "%02x:%02x:%02x:%02x:%02x:%02x", 13502 sc->link_params.mac_addr[0], sc->link_params.mac_addr[1], 13503 sc->link_params.mac_addr[2], sc->link_params.mac_addr[3], 13504 sc->link_params.mac_addr[4], sc->link_params.mac_addr[5]); 13505 BLOGD(sc, DBG_LOAD, "Ethernet address: %s\n", sc->mac_addr_str); 13506 } 13507 13508 return (0); 13509 } 13510 13511 static void 13512 bxe_get_tunable_params(struct bxe_softc *sc) 13513 { 13514 /* sanity checks */ 13515 13516 if ((bxe_interrupt_mode != INTR_MODE_INTX) && 13517 (bxe_interrupt_mode != INTR_MODE_MSI) && 13518 (bxe_interrupt_mode != INTR_MODE_MSIX)) { 13519 BLOGW(sc, "invalid interrupt_mode value (%d)\n", bxe_interrupt_mode); 13520 bxe_interrupt_mode = INTR_MODE_MSIX; 13521 } 13522 13523 if ((bxe_queue_count < 0) || (bxe_queue_count > MAX_RSS_CHAINS)) { 13524 BLOGW(sc, "invalid queue_count value (%d)\n", bxe_queue_count); 13525 bxe_queue_count = 0; 13526 } 13527 13528 if ((bxe_max_rx_bufs < 1) || (bxe_max_rx_bufs > RX_BD_USABLE)) { 13529 if (bxe_max_rx_bufs == 0) { 13530 bxe_max_rx_bufs = RX_BD_USABLE; 13531 } else { 13532 BLOGW(sc, "invalid max_rx_bufs (%d)\n", bxe_max_rx_bufs); 13533 bxe_max_rx_bufs = 2048; 13534 } 13535 } 13536 13537 if ((bxe_hc_rx_ticks < 1) || (bxe_hc_rx_ticks > 100)) { 13538 BLOGW(sc, "invalid hc_rx_ticks (%d)\n", bxe_hc_rx_ticks); 13539 bxe_hc_rx_ticks = 25; 13540 } 13541 13542 if ((bxe_hc_tx_ticks < 1) || (bxe_hc_tx_ticks > 100)) { 13543 BLOGW(sc, "invalid hc_tx_ticks (%d)\n", bxe_hc_tx_ticks); 13544 bxe_hc_tx_ticks = 50; 13545 } 13546 13547 if (bxe_max_aggregation_size == 0) { 13548 bxe_max_aggregation_size = TPA_AGG_SIZE; 13549 } 13550 13551 if (bxe_max_aggregation_size > 0xffff) { 13552 BLOGW(sc, "invalid max_aggregation_size (%d)\n", 13553 bxe_max_aggregation_size); 13554 bxe_max_aggregation_size = TPA_AGG_SIZE; 13555 } 13556 13557 if ((bxe_mrrs < -1) || (bxe_mrrs > 3)) { 13558 BLOGW(sc, "invalid mrrs (%d)\n", bxe_mrrs); 13559 bxe_mrrs = -1; 13560 } 13561 13562 if ((bxe_autogreeen < 0) || (bxe_autogreeen > 2)) { 13563 BLOGW(sc, "invalid autogreeen (%d)\n", bxe_autogreeen); 13564 bxe_autogreeen = 0; 13565 } 13566 13567 if ((bxe_udp_rss < 0) || (bxe_udp_rss > 1)) { 13568 BLOGW(sc, "invalid udp_rss (%d)\n", bxe_udp_rss); 13569 bxe_udp_rss = 0; 13570 } 13571 13572 /* pull in user settings */ 13573 13574 sc->interrupt_mode = bxe_interrupt_mode; 13575 sc->max_rx_bufs = bxe_max_rx_bufs; 13576 sc->hc_rx_ticks = bxe_hc_rx_ticks; 13577 sc->hc_tx_ticks = bxe_hc_tx_ticks; 13578 sc->max_aggregation_size = bxe_max_aggregation_size; 13579 sc->mrrs = bxe_mrrs; 13580 sc->autogreeen = bxe_autogreeen; 13581 sc->udp_rss = bxe_udp_rss; 13582 13583 if (bxe_interrupt_mode == INTR_MODE_INTX) { 13584 sc->num_queues = 1; 13585 } else { /* INTR_MODE_MSI or INTR_MODE_MSIX */ 13586 sc->num_queues = 13587 min((bxe_queue_count ? bxe_queue_count : mp_ncpus), 13588 MAX_RSS_CHAINS); 13589 if (sc->num_queues > mp_ncpus) { 13590 sc->num_queues = mp_ncpus; 13591 } 13592 } 13593 13594 BLOGD(sc, DBG_LOAD, 13595 "User Config: " 13596 "debug=0x%lx " 13597 "interrupt_mode=%d " 13598 "queue_count=%d " 13599 "hc_rx_ticks=%d " 13600 "hc_tx_ticks=%d " 13601 "rx_budget=%d " 13602 "max_aggregation_size=%d " 13603 "mrrs=%d " 13604 "autogreeen=%d " 13605 "udp_rss=%d\n", 13606 bxe_debug, 13607 sc->interrupt_mode, 13608 sc->num_queues, 13609 sc->hc_rx_ticks, 13610 sc->hc_tx_ticks, 13611 bxe_rx_budget, 13612 sc->max_aggregation_size, 13613 sc->mrrs, 13614 sc->autogreeen, 13615 sc->udp_rss); 13616 } 13617 13618 static int 13619 bxe_media_detect(struct bxe_softc *sc) 13620 { 13621 int port_type; 13622 uint32_t phy_idx = bxe_get_cur_phy_idx(sc); 13623 13624 switch (sc->link_params.phy[phy_idx].media_type) { 13625 case ELINK_ETH_PHY_SFPP_10G_FIBER: 13626 case ELINK_ETH_PHY_XFP_FIBER: 13627 BLOGI(sc, "Found 10Gb Fiber media.\n"); 13628 sc->media = IFM_10G_SR; 13629 port_type = PORT_FIBRE; 13630 break; 13631 case ELINK_ETH_PHY_SFP_1G_FIBER: 13632 BLOGI(sc, "Found 1Gb Fiber media.\n"); 13633 sc->media = IFM_1000_SX; 13634 port_type = PORT_FIBRE; 13635 break; 13636 case ELINK_ETH_PHY_KR: 13637 case ELINK_ETH_PHY_CX4: 13638 BLOGI(sc, "Found 10GBase-CX4 media.\n"); 13639 sc->media = IFM_10G_CX4; 13640 port_type = PORT_FIBRE; 13641 break; 13642 case ELINK_ETH_PHY_DA_TWINAX: 13643 BLOGI(sc, "Found 10Gb Twinax media.\n"); 13644 sc->media = IFM_10G_TWINAX; 13645 port_type = PORT_DA; 13646 break; 13647 case ELINK_ETH_PHY_BASE_T: 13648 if (sc->link_params.speed_cap_mask[0] & 13649 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) { 13650 BLOGI(sc, "Found 10GBase-T media.\n"); 13651 sc->media = IFM_10G_T; 13652 port_type = PORT_TP; 13653 } else { 13654 BLOGI(sc, "Found 1000Base-T media.\n"); 13655 sc->media = IFM_1000_T; 13656 port_type = PORT_TP; 13657 } 13658 break; 13659 case ELINK_ETH_PHY_NOT_PRESENT: 13660 BLOGI(sc, "Media not present.\n"); 13661 sc->media = 0; 13662 port_type = PORT_OTHER; 13663 break; 13664 case ELINK_ETH_PHY_UNSPECIFIED: 13665 default: 13666 BLOGI(sc, "Unknown media!\n"); 13667 sc->media = 0; 13668 port_type = PORT_OTHER; 13669 break; 13670 } 13671 return port_type; 13672 } 13673 13674 #define GET_FIELD(value, fname) \ 13675 (((value) & (fname##_MASK)) >> (fname##_SHIFT)) 13676 #define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID) 13677 #define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR) 13678 13679 static int 13680 bxe_get_igu_cam_info(struct bxe_softc *sc) 13681 { 13682 int pfid = SC_FUNC(sc); 13683 int igu_sb_id; 13684 uint32_t val; 13685 uint8_t fid, igu_sb_cnt = 0; 13686 13687 sc->igu_base_sb = 0xff; 13688 13689 if (CHIP_INT_MODE_IS_BC(sc)) { 13690 int vn = SC_VN(sc); 13691 igu_sb_cnt = sc->igu_sb_cnt; 13692 sc->igu_base_sb = ((CHIP_IS_MODE_4_PORT(sc) ? pfid : vn) * 13693 FP_SB_MAX_E1x); 13694 sc->igu_dsb_id = (E1HVN_MAX * FP_SB_MAX_E1x + 13695 (CHIP_IS_MODE_4_PORT(sc) ? pfid : vn)); 13696 return (0); 13697 } 13698 13699 /* IGU in normal mode - read CAM */ 13700 for (igu_sb_id = 0; 13701 igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE; 13702 igu_sb_id++) { 13703 val = REG_RD(sc, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4); 13704 if (!(val & IGU_REG_MAPPING_MEMORY_VALID)) { 13705 continue; 13706 } 13707 fid = IGU_FID(val); 13708 if ((fid & IGU_FID_ENCODE_IS_PF)) { 13709 if ((fid & IGU_FID_PF_NUM_MASK) != pfid) { 13710 continue; 13711 } 13712 if (IGU_VEC(val) == 0) { 13713 /* default status block */ 13714 sc->igu_dsb_id = igu_sb_id; 13715 } else { 13716 if (sc->igu_base_sb == 0xff) { 13717 sc->igu_base_sb = igu_sb_id; 13718 } 13719 igu_sb_cnt++; 13720 } 13721 } 13722 } 13723 13724 /* 13725 * Due to new PF resource allocation by MFW T7.4 and above, it's optional 13726 * that number of CAM entries will not be equal to the value advertised in 13727 * PCI. Driver should use the minimal value of both as the actual status 13728 * block count 13729 */ 13730 sc->igu_sb_cnt = min(sc->igu_sb_cnt, igu_sb_cnt); 13731 13732 if (igu_sb_cnt == 0) { 13733 BLOGE(sc, "CAM configuration error\n"); 13734 return (-1); 13735 } 13736 13737 return (0); 13738 } 13739 13740 /* 13741 * Gather various information from the device config space, the device itself, 13742 * shmem, and the user input. 13743 */ 13744 static int 13745 bxe_get_device_info(struct bxe_softc *sc) 13746 { 13747 uint32_t val; 13748 int rc; 13749 13750 /* Get the data for the device */ 13751 sc->devinfo.vendor_id = pci_get_vendor(sc->dev); 13752 sc->devinfo.device_id = pci_get_device(sc->dev); 13753 sc->devinfo.subvendor_id = pci_get_subvendor(sc->dev); 13754 sc->devinfo.subdevice_id = pci_get_subdevice(sc->dev); 13755 13756 /* get the chip revision (chip metal comes from pci config space) */ 13757 sc->devinfo.chip_id = 13758 sc->link_params.chip_id = 13759 (((REG_RD(sc, MISC_REG_CHIP_NUM) & 0xffff) << 16) | 13760 ((REG_RD(sc, MISC_REG_CHIP_REV) & 0xf) << 12) | 13761 (((REG_RD(sc, PCICFG_OFFSET + PCI_ID_VAL3) >> 24) & 0xf) << 4) | 13762 ((REG_RD(sc, MISC_REG_BOND_ID) & 0xf) << 0)); 13763 13764 /* force 57811 according to MISC register */ 13765 if (REG_RD(sc, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) { 13766 if (CHIP_IS_57810(sc)) { 13767 sc->devinfo.chip_id = ((CHIP_NUM_57811 << 16) | 13768 (sc->devinfo.chip_id & 0x0000ffff)); 13769 } else if (CHIP_IS_57810_MF(sc)) { 13770 sc->devinfo.chip_id = ((CHIP_NUM_57811_MF << 16) | 13771 (sc->devinfo.chip_id & 0x0000ffff)); 13772 } 13773 sc->devinfo.chip_id |= 0x1; 13774 } 13775 13776 BLOGD(sc, DBG_LOAD, 13777 "chip_id=0x%08x (num=0x%04x rev=0x%01x metal=0x%02x bond=0x%01x)\n", 13778 sc->devinfo.chip_id, 13779 ((sc->devinfo.chip_id >> 16) & 0xffff), 13780 ((sc->devinfo.chip_id >> 12) & 0xf), 13781 ((sc->devinfo.chip_id >> 4) & 0xff), 13782 ((sc->devinfo.chip_id >> 0) & 0xf)); 13783 13784 val = (REG_RD(sc, 0x2874) & 0x55); 13785 if ((sc->devinfo.chip_id & 0x1) || 13786 (CHIP_IS_E1(sc) && val) || 13787 (CHIP_IS_E1H(sc) && (val == 0x55))) { 13788 sc->flags |= BXE_ONE_PORT_FLAG; 13789 BLOGD(sc, DBG_LOAD, "single port device\n"); 13790 } 13791 13792 /* set the doorbell size */ 13793 sc->doorbell_size = (1 << BXE_DB_SHIFT); 13794 13795 /* determine whether the device is in 2 port or 4 port mode */ 13796 sc->devinfo.chip_port_mode = CHIP_PORT_MODE_NONE; /* E1 & E1h*/ 13797 if (CHIP_IS_E2E3(sc)) { 13798 /* 13799 * Read port4mode_en_ovwr[0]: 13800 * If 1, four port mode is in port4mode_en_ovwr[1]. 13801 * If 0, four port mode is in port4mode_en[0]. 13802 */ 13803 val = REG_RD(sc, MISC_REG_PORT4MODE_EN_OVWR); 13804 if (val & 1) { 13805 val = ((val >> 1) & 1); 13806 } else { 13807 val = REG_RD(sc, MISC_REG_PORT4MODE_EN); 13808 } 13809 13810 sc->devinfo.chip_port_mode = 13811 (val) ? CHIP_4_PORT_MODE : CHIP_2_PORT_MODE; 13812 13813 BLOGD(sc, DBG_LOAD, "Port mode = %s\n", (val) ? "4" : "2"); 13814 } 13815 13816 /* get the function and path info for the device */ 13817 bxe_get_function_num(sc); 13818 13819 /* get the shared memory base address */ 13820 sc->devinfo.shmem_base = 13821 sc->link_params.shmem_base = 13822 REG_RD(sc, MISC_REG_SHARED_MEM_ADDR); 13823 sc->devinfo.shmem2_base = 13824 REG_RD(sc, (SC_PATH(sc) ? MISC_REG_GENERIC_CR_1 : 13825 MISC_REG_GENERIC_CR_0)); 13826 13827 BLOGD(sc, DBG_LOAD, "shmem_base=0x%08x, shmem2_base=0x%08x\n", 13828 sc->devinfo.shmem_base, sc->devinfo.shmem2_base); 13829 13830 if (!sc->devinfo.shmem_base) { 13831 /* this should ONLY prevent upcoming shmem reads */ 13832 BLOGI(sc, "MCP not active\n"); 13833 sc->flags |= BXE_NO_MCP_FLAG; 13834 return (0); 13835 } 13836 13837 /* make sure the shared memory contents are valid */ 13838 val = SHMEM_RD(sc, validity_map[SC_PORT(sc)]); 13839 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) != 13840 (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) { 13841 BLOGE(sc, "Invalid SHMEM validity signature: 0x%08x\n", val); 13842 return (0); 13843 } 13844 BLOGD(sc, DBG_LOAD, "Valid SHMEM validity signature: 0x%08x\n", val); 13845 13846 /* get the bootcode version */ 13847 sc->devinfo.bc_ver = SHMEM_RD(sc, dev_info.bc_rev); 13848 snprintf(sc->devinfo.bc_ver_str, 13849 sizeof(sc->devinfo.bc_ver_str), 13850 "%d.%d.%d", 13851 ((sc->devinfo.bc_ver >> 24) & 0xff), 13852 ((sc->devinfo.bc_ver >> 16) & 0xff), 13853 ((sc->devinfo.bc_ver >> 8) & 0xff)); 13854 BLOGD(sc, DBG_LOAD, "Bootcode version: %s\n", sc->devinfo.bc_ver_str); 13855 13856 /* get the bootcode shmem address */ 13857 sc->devinfo.mf_cfg_base = bxe_get_shmem_mf_cfg_base(sc); 13858 BLOGD(sc, DBG_LOAD, "mf_cfg_base=0x08%x \n", sc->devinfo.mf_cfg_base); 13859 13860 /* clean indirect addresses as they're not used */ 13861 pci_write_config(sc->dev, PCICFG_GRC_ADDRESS, 0, 4); 13862 if (IS_PF(sc)) { 13863 REG_WR(sc, PXP2_REG_PGL_ADDR_88_F0, 0); 13864 REG_WR(sc, PXP2_REG_PGL_ADDR_8C_F0, 0); 13865 REG_WR(sc, PXP2_REG_PGL_ADDR_90_F0, 0); 13866 REG_WR(sc, PXP2_REG_PGL_ADDR_94_F0, 0); 13867 if (CHIP_IS_E1x(sc)) { 13868 REG_WR(sc, PXP2_REG_PGL_ADDR_88_F1, 0); 13869 REG_WR(sc, PXP2_REG_PGL_ADDR_8C_F1, 0); 13870 REG_WR(sc, PXP2_REG_PGL_ADDR_90_F1, 0); 13871 REG_WR(sc, PXP2_REG_PGL_ADDR_94_F1, 0); 13872 } 13873 13874 /* 13875 * Enable internal target-read (in case we are probed after PF 13876 * FLR). Must be done prior to any BAR read access. Only for 13877 * 57712 and up 13878 */ 13879 if (!CHIP_IS_E1x(sc)) { 13880 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1); 13881 } 13882 } 13883 13884 /* get the nvram size */ 13885 val = REG_RD(sc, MCP_REG_MCPR_NVM_CFG4); 13886 sc->devinfo.flash_size = 13887 (NVRAM_1MB_SIZE << (val & MCPR_NVM_CFG4_FLASH_SIZE)); 13888 BLOGD(sc, DBG_LOAD, "nvram flash size: %d\n", sc->devinfo.flash_size); 13889 13890 /* get PCI capabilites */ 13891 bxe_probe_pci_caps(sc); 13892 13893 bxe_set_power_state(sc, PCI_PM_D0); 13894 13895 /* get various configuration parameters from shmem */ 13896 bxe_get_shmem_info(sc); 13897 13898 if (sc->devinfo.pcie_msix_cap_reg != 0) { 13899 val = pci_read_config(sc->dev, 13900 (sc->devinfo.pcie_msix_cap_reg + 13901 PCIR_MSIX_CTRL), 13902 2); 13903 sc->igu_sb_cnt = (val & PCIM_MSIXCTRL_TABLE_SIZE); 13904 } else { 13905 sc->igu_sb_cnt = 1; 13906 } 13907 13908 sc->igu_base_addr = BAR_IGU_INTMEM; 13909 13910 /* initialize IGU parameters */ 13911 if (CHIP_IS_E1x(sc)) { 13912 sc->devinfo.int_block = INT_BLOCK_HC; 13913 sc->igu_dsb_id = DEF_SB_IGU_ID; 13914 sc->igu_base_sb = 0; 13915 } else { 13916 sc->devinfo.int_block = INT_BLOCK_IGU; 13917 13918 /* do not allow device reset during IGU info preocessing */ 13919 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RESET); 13920 13921 val = REG_RD(sc, IGU_REG_BLOCK_CONFIGURATION); 13922 13923 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) { 13924 int tout = 5000; 13925 13926 BLOGD(sc, DBG_LOAD, "FORCING IGU Normal Mode\n"); 13927 13928 val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN); 13929 REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION, val); 13930 REG_WR(sc, IGU_REG_RESET_MEMORIES, 0x7f); 13931 13932 while (tout && REG_RD(sc, IGU_REG_RESET_MEMORIES)) { 13933 tout--; 13934 DELAY(1000); 13935 } 13936 13937 if (REG_RD(sc, IGU_REG_RESET_MEMORIES)) { 13938 BLOGD(sc, DBG_LOAD, "FORCING IGU Normal Mode failed!!!\n"); 13939 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET); 13940 return (-1); 13941 } 13942 } 13943 13944 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) { 13945 BLOGD(sc, DBG_LOAD, "IGU Backward Compatible Mode\n"); 13946 sc->devinfo.int_block |= INT_BLOCK_MODE_BW_COMP; 13947 } else { 13948 BLOGD(sc, DBG_LOAD, "IGU Normal Mode\n"); 13949 } 13950 13951 rc = bxe_get_igu_cam_info(sc); 13952 13953 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET); 13954 13955 if (rc) { 13956 return (rc); 13957 } 13958 } 13959 13960 /* 13961 * Get base FW non-default (fast path) status block ID. This value is 13962 * used to initialize the fw_sb_id saved on the fp/queue structure to 13963 * determine the id used by the FW. 13964 */ 13965 if (CHIP_IS_E1x(sc)) { 13966 sc->base_fw_ndsb = ((SC_PORT(sc) * FP_SB_MAX_E1x) + SC_L_ID(sc)); 13967 } else { 13968 /* 13969 * 57712+ - We currently use one FW SB per IGU SB (Rx and Tx of 13970 * the same queue are indicated on the same IGU SB). So we prefer 13971 * FW and IGU SBs to be the same value. 13972 */ 13973 sc->base_fw_ndsb = sc->igu_base_sb; 13974 } 13975 13976 BLOGD(sc, DBG_LOAD, 13977 "igu_dsb_id=%d igu_base_sb=%d igu_sb_cnt=%d base_fw_ndsb=%d\n", 13978 sc->igu_dsb_id, sc->igu_base_sb, 13979 sc->igu_sb_cnt, sc->base_fw_ndsb); 13980 13981 elink_phy_probe(&sc->link_params); 13982 13983 return (0); 13984 } 13985 13986 static void 13987 bxe_link_settings_supported(struct bxe_softc *sc, 13988 uint32_t switch_cfg) 13989 { 13990 uint32_t cfg_size = 0; 13991 uint32_t idx; 13992 uint8_t port = SC_PORT(sc); 13993 13994 /* aggregation of supported attributes of all external phys */ 13995 sc->port.supported[0] = 0; 13996 sc->port.supported[1] = 0; 13997 13998 switch (sc->link_params.num_phys) { 13999 case 1: 14000 sc->port.supported[0] = sc->link_params.phy[ELINK_INT_PHY].supported; 14001 cfg_size = 1; 14002 break; 14003 case 2: 14004 sc->port.supported[0] = sc->link_params.phy[ELINK_EXT_PHY1].supported; 14005 cfg_size = 1; 14006 break; 14007 case 3: 14008 if (sc->link_params.multi_phy_config & 14009 PORT_HW_CFG_PHY_SWAPPED_ENABLED) { 14010 sc->port.supported[1] = 14011 sc->link_params.phy[ELINK_EXT_PHY1].supported; 14012 sc->port.supported[0] = 14013 sc->link_params.phy[ELINK_EXT_PHY2].supported; 14014 } else { 14015 sc->port.supported[0] = 14016 sc->link_params.phy[ELINK_EXT_PHY1].supported; 14017 sc->port.supported[1] = 14018 sc->link_params.phy[ELINK_EXT_PHY2].supported; 14019 } 14020 cfg_size = 2; 14021 break; 14022 } 14023 14024 if (!(sc->port.supported[0] || sc->port.supported[1])) { 14025 BLOGE(sc, "Invalid phy config in NVRAM (PHY1=0x%08x PHY2=0x%08x)\n", 14026 SHMEM_RD(sc, 14027 dev_info.port_hw_config[port].external_phy_config), 14028 SHMEM_RD(sc, 14029 dev_info.port_hw_config[port].external_phy_config2)); 14030 return; 14031 } 14032 14033 if (CHIP_IS_E3(sc)) 14034 sc->port.phy_addr = REG_RD(sc, MISC_REG_WC0_CTRL_PHY_ADDR); 14035 else { 14036 switch (switch_cfg) { 14037 case ELINK_SWITCH_CFG_1G: 14038 sc->port.phy_addr = 14039 REG_RD(sc, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10); 14040 break; 14041 case ELINK_SWITCH_CFG_10G: 14042 sc->port.phy_addr = 14043 REG_RD(sc, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18); 14044 break; 14045 default: 14046 BLOGE(sc, "Invalid switch config in link_config=0x%08x\n", 14047 sc->port.link_config[0]); 14048 return; 14049 } 14050 } 14051 14052 BLOGD(sc, DBG_LOAD, "PHY addr 0x%08x\n", sc->port.phy_addr); 14053 14054 /* mask what we support according to speed_cap_mask per configuration */ 14055 for (idx = 0; idx < cfg_size; idx++) { 14056 if (!(sc->link_params.speed_cap_mask[idx] & 14057 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) { 14058 sc->port.supported[idx] &= ~ELINK_SUPPORTED_10baseT_Half; 14059 } 14060 14061 if (!(sc->link_params.speed_cap_mask[idx] & 14062 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL)) { 14063 sc->port.supported[idx] &= ~ELINK_SUPPORTED_10baseT_Full; 14064 } 14065 14066 if (!(sc->link_params.speed_cap_mask[idx] & 14067 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)) { 14068 sc->port.supported[idx] &= ~ELINK_SUPPORTED_100baseT_Half; 14069 } 14070 14071 if (!(sc->link_params.speed_cap_mask[idx] & 14072 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL)) { 14073 sc->port.supported[idx] &= ~ELINK_SUPPORTED_100baseT_Full; 14074 } 14075 14076 if (!(sc->link_params.speed_cap_mask[idx] & 14077 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) { 14078 sc->port.supported[idx] &= ~ELINK_SUPPORTED_1000baseT_Full; 14079 } 14080 14081 if (!(sc->link_params.speed_cap_mask[idx] & 14082 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)) { 14083 sc->port.supported[idx] &= ~ELINK_SUPPORTED_2500baseX_Full; 14084 } 14085 14086 if (!(sc->link_params.speed_cap_mask[idx] & 14087 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) { 14088 sc->port.supported[idx] &= ~ELINK_SUPPORTED_10000baseT_Full; 14089 } 14090 14091 if (!(sc->link_params.speed_cap_mask[idx] & 14092 PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) { 14093 sc->port.supported[idx] &= ~ELINK_SUPPORTED_20000baseKR2_Full; 14094 } 14095 } 14096 14097 BLOGD(sc, DBG_LOAD, "PHY supported 0=0x%08x 1=0x%08x\n", 14098 sc->port.supported[0], sc->port.supported[1]); 14099 ELINK_DEBUG_P2(sc, "PHY supported 0=0x%08x 1=0x%08x\n", 14100 sc->port.supported[0], sc->port.supported[1]); 14101 } 14102 14103 static void 14104 bxe_link_settings_requested(struct bxe_softc *sc) 14105 { 14106 uint32_t link_config; 14107 uint32_t idx; 14108 uint32_t cfg_size = 0; 14109 14110 sc->port.advertising[0] = 0; 14111 sc->port.advertising[1] = 0; 14112 14113 switch (sc->link_params.num_phys) { 14114 case 1: 14115 case 2: 14116 cfg_size = 1; 14117 break; 14118 case 3: 14119 cfg_size = 2; 14120 break; 14121 } 14122 14123 for (idx = 0; idx < cfg_size; idx++) { 14124 sc->link_params.req_duplex[idx] = DUPLEX_FULL; 14125 link_config = sc->port.link_config[idx]; 14126 14127 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) { 14128 case PORT_FEATURE_LINK_SPEED_AUTO: 14129 if (sc->port.supported[idx] & ELINK_SUPPORTED_Autoneg) { 14130 sc->link_params.req_line_speed[idx] = ELINK_SPEED_AUTO_NEG; 14131 sc->port.advertising[idx] |= sc->port.supported[idx]; 14132 if (sc->link_params.phy[ELINK_EXT_PHY1].type == 14133 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) 14134 sc->port.advertising[idx] |= 14135 (ELINK_SUPPORTED_100baseT_Half | 14136 ELINK_SUPPORTED_100baseT_Full); 14137 } else { 14138 /* force 10G, no AN */ 14139 sc->link_params.req_line_speed[idx] = ELINK_SPEED_10000; 14140 sc->port.advertising[idx] |= 14141 (ADVERTISED_10000baseT_Full | ADVERTISED_FIBRE); 14142 continue; 14143 } 14144 break; 14145 14146 case PORT_FEATURE_LINK_SPEED_10M_FULL: 14147 if (sc->port.supported[idx] & ELINK_SUPPORTED_10baseT_Full) { 14148 sc->link_params.req_line_speed[idx] = ELINK_SPEED_10; 14149 sc->port.advertising[idx] |= (ADVERTISED_10baseT_Full | 14150 ADVERTISED_TP); 14151 } else { 14152 BLOGE(sc, "Invalid NVRAM config link_config=0x%08x " 14153 "speed_cap_mask=0x%08x\n", 14154 link_config, sc->link_params.speed_cap_mask[idx]); 14155 return; 14156 } 14157 break; 14158 14159 case PORT_FEATURE_LINK_SPEED_10M_HALF: 14160 if (sc->port.supported[idx] & ELINK_SUPPORTED_10baseT_Half) { 14161 sc->link_params.req_line_speed[idx] = ELINK_SPEED_10; 14162 sc->link_params.req_duplex[idx] = DUPLEX_HALF; 14163 sc->port.advertising[idx] |= (ADVERTISED_10baseT_Half | 14164 ADVERTISED_TP); 14165 ELINK_DEBUG_P1(sc, "driver requesting DUPLEX_HALF req_duplex = %x!\n", 14166 sc->link_params.req_duplex[idx]); 14167 } else { 14168 BLOGE(sc, "Invalid NVRAM config link_config=0x%08x " 14169 "speed_cap_mask=0x%08x\n", 14170 link_config, sc->link_params.speed_cap_mask[idx]); 14171 return; 14172 } 14173 break; 14174 14175 case PORT_FEATURE_LINK_SPEED_100M_FULL: 14176 if (sc->port.supported[idx] & ELINK_SUPPORTED_100baseT_Full) { 14177 sc->link_params.req_line_speed[idx] = ELINK_SPEED_100; 14178 sc->port.advertising[idx] |= (ADVERTISED_100baseT_Full | 14179 ADVERTISED_TP); 14180 } else { 14181 BLOGE(sc, "Invalid NVRAM config link_config=0x%08x " 14182 "speed_cap_mask=0x%08x\n", 14183 link_config, sc->link_params.speed_cap_mask[idx]); 14184 return; 14185 } 14186 break; 14187 14188 case PORT_FEATURE_LINK_SPEED_100M_HALF: 14189 if (sc->port.supported[idx] & ELINK_SUPPORTED_100baseT_Half) { 14190 sc->link_params.req_line_speed[idx] = ELINK_SPEED_100; 14191 sc->link_params.req_duplex[idx] = DUPLEX_HALF; 14192 sc->port.advertising[idx] |= (ADVERTISED_100baseT_Half | 14193 ADVERTISED_TP); 14194 } else { 14195 BLOGE(sc, "Invalid NVRAM config link_config=0x%08x " 14196 "speed_cap_mask=0x%08x\n", 14197 link_config, sc->link_params.speed_cap_mask[idx]); 14198 return; 14199 } 14200 break; 14201 14202 case PORT_FEATURE_LINK_SPEED_1G: 14203 if (sc->port.supported[idx] & ELINK_SUPPORTED_1000baseT_Full) { 14204 sc->link_params.req_line_speed[idx] = ELINK_SPEED_1000; 14205 sc->port.advertising[idx] |= (ADVERTISED_1000baseT_Full | 14206 ADVERTISED_TP); 14207 } else { 14208 BLOGE(sc, "Invalid NVRAM config link_config=0x%08x " 14209 "speed_cap_mask=0x%08x\n", 14210 link_config, sc->link_params.speed_cap_mask[idx]); 14211 return; 14212 } 14213 break; 14214 14215 case PORT_FEATURE_LINK_SPEED_2_5G: 14216 if (sc->port.supported[idx] & ELINK_SUPPORTED_2500baseX_Full) { 14217 sc->link_params.req_line_speed[idx] = ELINK_SPEED_2500; 14218 sc->port.advertising[idx] |= (ADVERTISED_2500baseX_Full | 14219 ADVERTISED_TP); 14220 } else { 14221 BLOGE(sc, "Invalid NVRAM config link_config=0x%08x " 14222 "speed_cap_mask=0x%08x\n", 14223 link_config, sc->link_params.speed_cap_mask[idx]); 14224 return; 14225 } 14226 break; 14227 14228 case PORT_FEATURE_LINK_SPEED_10G_CX4: 14229 if (sc->port.supported[idx] & ELINK_SUPPORTED_10000baseT_Full) { 14230 sc->link_params.req_line_speed[idx] = ELINK_SPEED_10000; 14231 sc->port.advertising[idx] |= (ADVERTISED_10000baseT_Full | 14232 ADVERTISED_FIBRE); 14233 } else { 14234 BLOGE(sc, "Invalid NVRAM config link_config=0x%08x " 14235 "speed_cap_mask=0x%08x\n", 14236 link_config, sc->link_params.speed_cap_mask[idx]); 14237 return; 14238 } 14239 break; 14240 14241 case PORT_FEATURE_LINK_SPEED_20G: 14242 sc->link_params.req_line_speed[idx] = ELINK_SPEED_20000; 14243 break; 14244 14245 default: 14246 BLOGE(sc, "Invalid NVRAM config link_config=0x%08x " 14247 "speed_cap_mask=0x%08x\n", 14248 link_config, sc->link_params.speed_cap_mask[idx]); 14249 sc->link_params.req_line_speed[idx] = ELINK_SPEED_AUTO_NEG; 14250 sc->port.advertising[idx] = sc->port.supported[idx]; 14251 break; 14252 } 14253 14254 sc->link_params.req_flow_ctrl[idx] = 14255 (link_config & PORT_FEATURE_FLOW_CONTROL_MASK); 14256 14257 if (sc->link_params.req_flow_ctrl[idx] == ELINK_FLOW_CTRL_AUTO) { 14258 if (!(sc->port.supported[idx] & ELINK_SUPPORTED_Autoneg)) { 14259 sc->link_params.req_flow_ctrl[idx] = ELINK_FLOW_CTRL_NONE; 14260 } else { 14261 bxe_set_requested_fc(sc); 14262 } 14263 } 14264 14265 BLOGD(sc, DBG_LOAD, "req_line_speed=%d req_duplex=%d " 14266 "req_flow_ctrl=0x%x advertising=0x%x\n", 14267 sc->link_params.req_line_speed[idx], 14268 sc->link_params.req_duplex[idx], 14269 sc->link_params.req_flow_ctrl[idx], 14270 sc->port.advertising[idx]); 14271 ELINK_DEBUG_P3(sc, "req_line_speed=%d req_duplex=%d " 14272 "advertising=0x%x\n", 14273 sc->link_params.req_line_speed[idx], 14274 sc->link_params.req_duplex[idx], 14275 sc->port.advertising[idx]); 14276 } 14277 } 14278 14279 static void 14280 bxe_get_phy_info(struct bxe_softc *sc) 14281 { 14282 uint8_t port = SC_PORT(sc); 14283 uint32_t config = sc->port.config; 14284 uint32_t eee_mode; 14285 14286 /* shmem data already read in bxe_get_shmem_info() */ 14287 14288 ELINK_DEBUG_P3(sc, "lane_config=0x%08x speed_cap_mask0=0x%08x " 14289 "link_config0=0x%08x\n", 14290 sc->link_params.lane_config, 14291 sc->link_params.speed_cap_mask[0], 14292 sc->port.link_config[0]); 14293 14294 14295 bxe_link_settings_supported(sc, sc->link_params.switch_cfg); 14296 bxe_link_settings_requested(sc); 14297 14298 if (sc->autogreeen == AUTO_GREEN_FORCE_ON) { 14299 sc->link_params.feature_config_flags |= 14300 ELINK_FEATURE_CONFIG_AUTOGREEEN_ENABLED; 14301 } else if (sc->autogreeen == AUTO_GREEN_FORCE_OFF) { 14302 sc->link_params.feature_config_flags &= 14303 ~ELINK_FEATURE_CONFIG_AUTOGREEEN_ENABLED; 14304 } else if (config & PORT_FEAT_CFG_AUTOGREEEN_ENABLED) { 14305 sc->link_params.feature_config_flags |= 14306 ELINK_FEATURE_CONFIG_AUTOGREEEN_ENABLED; 14307 } 14308 14309 /* configure link feature according to nvram value */ 14310 eee_mode = 14311 (((SHMEM_RD(sc, dev_info.port_feature_config[port].eee_power_mode)) & 14312 PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >> 14313 PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT); 14314 if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) { 14315 sc->link_params.eee_mode = (ELINK_EEE_MODE_ADV_LPI | 14316 ELINK_EEE_MODE_ENABLE_LPI | 14317 ELINK_EEE_MODE_OUTPUT_TIME); 14318 } else { 14319 sc->link_params.eee_mode = 0; 14320 } 14321 14322 /* get the media type */ 14323 bxe_media_detect(sc); 14324 ELINK_DEBUG_P1(sc, "detected media type\n", sc->media); 14325 } 14326 14327 static void 14328 bxe_get_params(struct bxe_softc *sc) 14329 { 14330 /* get user tunable params */ 14331 bxe_get_tunable_params(sc); 14332 14333 /* select the RX and TX ring sizes */ 14334 sc->tx_ring_size = TX_BD_USABLE; 14335 sc->rx_ring_size = RX_BD_USABLE; 14336 14337 /* XXX disable WoL */ 14338 sc->wol = 0; 14339 } 14340 14341 static void 14342 bxe_set_modes_bitmap(struct bxe_softc *sc) 14343 { 14344 uint32_t flags = 0; 14345 14346 if (CHIP_REV_IS_FPGA(sc)) { 14347 SET_FLAGS(flags, MODE_FPGA); 14348 } else if (CHIP_REV_IS_EMUL(sc)) { 14349 SET_FLAGS(flags, MODE_EMUL); 14350 } else { 14351 SET_FLAGS(flags, MODE_ASIC); 14352 } 14353 14354 if (CHIP_IS_MODE_4_PORT(sc)) { 14355 SET_FLAGS(flags, MODE_PORT4); 14356 } else { 14357 SET_FLAGS(flags, MODE_PORT2); 14358 } 14359 14360 if (CHIP_IS_E2(sc)) { 14361 SET_FLAGS(flags, MODE_E2); 14362 } else if (CHIP_IS_E3(sc)) { 14363 SET_FLAGS(flags, MODE_E3); 14364 if (CHIP_REV(sc) == CHIP_REV_Ax) { 14365 SET_FLAGS(flags, MODE_E3_A0); 14366 } else /*if (CHIP_REV(sc) == CHIP_REV_Bx)*/ { 14367 SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3); 14368 } 14369 } 14370 14371 if (IS_MF(sc)) { 14372 SET_FLAGS(flags, MODE_MF); 14373 switch (sc->devinfo.mf_info.mf_mode) { 14374 case MULTI_FUNCTION_SD: 14375 SET_FLAGS(flags, MODE_MF_SD); 14376 break; 14377 case MULTI_FUNCTION_SI: 14378 SET_FLAGS(flags, MODE_MF_SI); 14379 break; 14380 case MULTI_FUNCTION_AFEX: 14381 SET_FLAGS(flags, MODE_MF_AFEX); 14382 break; 14383 } 14384 } else { 14385 SET_FLAGS(flags, MODE_SF); 14386 } 14387 14388 #if defined(__LITTLE_ENDIAN) 14389 SET_FLAGS(flags, MODE_LITTLE_ENDIAN); 14390 #else /* __BIG_ENDIAN */ 14391 SET_FLAGS(flags, MODE_BIG_ENDIAN); 14392 #endif 14393 14394 INIT_MODE_FLAGS(sc) = flags; 14395 } 14396 14397 static int 14398 bxe_alloc_hsi_mem(struct bxe_softc *sc) 14399 { 14400 struct bxe_fastpath *fp; 14401 bus_addr_t busaddr; 14402 int max_agg_queues; 14403 int max_segments; 14404 bus_size_t max_size; 14405 bus_size_t max_seg_size; 14406 char buf[32]; 14407 int rc; 14408 int i, j; 14409 14410 /* XXX zero out all vars here and call bxe_alloc_hsi_mem on error */ 14411 14412 /* allocate the parent bus DMA tag */ 14413 rc = bus_dma_tag_create(bus_get_dma_tag(sc->dev), /* parent tag */ 14414 1, /* alignment */ 14415 0, /* boundary limit */ 14416 BUS_SPACE_MAXADDR, /* restricted low */ 14417 BUS_SPACE_MAXADDR, /* restricted hi */ 14418 NULL, /* addr filter() */ 14419 NULL, /* addr filter() arg */ 14420 BUS_SPACE_MAXSIZE_32BIT, /* max map size */ 14421 BUS_SPACE_UNRESTRICTED, /* num discontinuous */ 14422 BUS_SPACE_MAXSIZE_32BIT, /* max seg size */ 14423 0, /* flags */ 14424 NULL, /* lock() */ 14425 NULL, /* lock() arg */ 14426 &sc->parent_dma_tag); /* returned dma tag */ 14427 if (rc != 0) { 14428 BLOGE(sc, "Failed to alloc parent DMA tag (%d)!\n", rc); 14429 return (1); 14430 } 14431 14432 /************************/ 14433 /* DEFAULT STATUS BLOCK */ 14434 /************************/ 14435 14436 if (bxe_dma_alloc(sc, sizeof(struct host_sp_status_block), 14437 &sc->def_sb_dma, "default status block") != 0) { 14438 /* XXX */ 14439 bus_dma_tag_destroy(sc->parent_dma_tag); 14440 return (1); 14441 } 14442 14443 sc->def_sb = (struct host_sp_status_block *)sc->def_sb_dma.vaddr; 14444 14445 /***************/ 14446 /* EVENT QUEUE */ 14447 /***************/ 14448 14449 if (bxe_dma_alloc(sc, BCM_PAGE_SIZE, 14450 &sc->eq_dma, "event queue") != 0) { 14451 /* XXX */ 14452 bxe_dma_free(sc, &sc->def_sb_dma); 14453 sc->def_sb = NULL; 14454 bus_dma_tag_destroy(sc->parent_dma_tag); 14455 return (1); 14456 } 14457 14458 sc->eq = (union event_ring_elem * )sc->eq_dma.vaddr; 14459 14460 /*************/ 14461 /* SLOW PATH */ 14462 /*************/ 14463 14464 if (bxe_dma_alloc(sc, sizeof(struct bxe_slowpath), 14465 &sc->sp_dma, "slow path") != 0) { 14466 /* XXX */ 14467 bxe_dma_free(sc, &sc->eq_dma); 14468 sc->eq = NULL; 14469 bxe_dma_free(sc, &sc->def_sb_dma); 14470 sc->def_sb = NULL; 14471 bus_dma_tag_destroy(sc->parent_dma_tag); 14472 return (1); 14473 } 14474 14475 sc->sp = (struct bxe_slowpath *)sc->sp_dma.vaddr; 14476 14477 /*******************/ 14478 /* SLOW PATH QUEUE */ 14479 /*******************/ 14480 14481 if (bxe_dma_alloc(sc, BCM_PAGE_SIZE, 14482 &sc->spq_dma, "slow path queue") != 0) { 14483 /* XXX */ 14484 bxe_dma_free(sc, &sc->sp_dma); 14485 sc->sp = NULL; 14486 bxe_dma_free(sc, &sc->eq_dma); 14487 sc->eq = NULL; 14488 bxe_dma_free(sc, &sc->def_sb_dma); 14489 sc->def_sb = NULL; 14490 bus_dma_tag_destroy(sc->parent_dma_tag); 14491 return (1); 14492 } 14493 14494 sc->spq = (struct eth_spe *)sc->spq_dma.vaddr; 14495 14496 /***************************/ 14497 /* FW DECOMPRESSION BUFFER */ 14498 /***************************/ 14499 14500 if (bxe_dma_alloc(sc, FW_BUF_SIZE, &sc->gz_buf_dma, 14501 "fw decompression buffer") != 0) { 14502 /* XXX */ 14503 bxe_dma_free(sc, &sc->spq_dma); 14504 sc->spq = NULL; 14505 bxe_dma_free(sc, &sc->sp_dma); 14506 sc->sp = NULL; 14507 bxe_dma_free(sc, &sc->eq_dma); 14508 sc->eq = NULL; 14509 bxe_dma_free(sc, &sc->def_sb_dma); 14510 sc->def_sb = NULL; 14511 bus_dma_tag_destroy(sc->parent_dma_tag); 14512 return (1); 14513 } 14514 14515 sc->gz_buf = (void *)sc->gz_buf_dma.vaddr; 14516 14517 if ((sc->gz_strm = 14518 malloc(sizeof(*sc->gz_strm), M_DEVBUF, M_NOWAIT)) == NULL) { 14519 /* XXX */ 14520 bxe_dma_free(sc, &sc->gz_buf_dma); 14521 sc->gz_buf = NULL; 14522 bxe_dma_free(sc, &sc->spq_dma); 14523 sc->spq = NULL; 14524 bxe_dma_free(sc, &sc->sp_dma); 14525 sc->sp = NULL; 14526 bxe_dma_free(sc, &sc->eq_dma); 14527 sc->eq = NULL; 14528 bxe_dma_free(sc, &sc->def_sb_dma); 14529 sc->def_sb = NULL; 14530 bus_dma_tag_destroy(sc->parent_dma_tag); 14531 return (1); 14532 } 14533 14534 /*************/ 14535 /* FASTPATHS */ 14536 /*************/ 14537 14538 /* allocate DMA memory for each fastpath structure */ 14539 for (i = 0; i < sc->num_queues; i++) { 14540 fp = &sc->fp[i]; 14541 fp->sc = sc; 14542 fp->index = i; 14543 14544 /*******************/ 14545 /* FP STATUS BLOCK */ 14546 /*******************/ 14547 14548 snprintf(buf, sizeof(buf), "fp %d status block", i); 14549 if (bxe_dma_alloc(sc, sizeof(union bxe_host_hc_status_block), 14550 &fp->sb_dma, buf) != 0) { 14551 /* XXX unwind and free previous fastpath allocations */ 14552 BLOGE(sc, "Failed to alloc %s\n", buf); 14553 return (1); 14554 } else { 14555 if (CHIP_IS_E2E3(sc)) { 14556 fp->status_block.e2_sb = 14557 (struct host_hc_status_block_e2 *)fp->sb_dma.vaddr; 14558 } else { 14559 fp->status_block.e1x_sb = 14560 (struct host_hc_status_block_e1x *)fp->sb_dma.vaddr; 14561 } 14562 } 14563 14564 /******************/ 14565 /* FP TX BD CHAIN */ 14566 /******************/ 14567 14568 snprintf(buf, sizeof(buf), "fp %d tx bd chain", i); 14569 if (bxe_dma_alloc(sc, (BCM_PAGE_SIZE * TX_BD_NUM_PAGES), 14570 &fp->tx_dma, buf) != 0) { 14571 /* XXX unwind and free previous fastpath allocations */ 14572 BLOGE(sc, "Failed to alloc %s\n", buf); 14573 return (1); 14574 } else { 14575 fp->tx_chain = (union eth_tx_bd_types *)fp->tx_dma.vaddr; 14576 } 14577 14578 /* link together the tx bd chain pages */ 14579 for (j = 1; j <= TX_BD_NUM_PAGES; j++) { 14580 /* index into the tx bd chain array to last entry per page */ 14581 struct eth_tx_next_bd *tx_next_bd = 14582 &fp->tx_chain[TX_BD_TOTAL_PER_PAGE * j - 1].next_bd; 14583 /* point to the next page and wrap from last page */ 14584 busaddr = (fp->tx_dma.paddr + 14585 (BCM_PAGE_SIZE * (j % TX_BD_NUM_PAGES))); 14586 tx_next_bd->addr_hi = htole32(U64_HI(busaddr)); 14587 tx_next_bd->addr_lo = htole32(U64_LO(busaddr)); 14588 } 14589 14590 /******************/ 14591 /* FP RX BD CHAIN */ 14592 /******************/ 14593 14594 snprintf(buf, sizeof(buf), "fp %d rx bd chain", i); 14595 if (bxe_dma_alloc(sc, (BCM_PAGE_SIZE * RX_BD_NUM_PAGES), 14596 &fp->rx_dma, buf) != 0) { 14597 /* XXX unwind and free previous fastpath allocations */ 14598 BLOGE(sc, "Failed to alloc %s\n", buf); 14599 return (1); 14600 } else { 14601 fp->rx_chain = (struct eth_rx_bd *)fp->rx_dma.vaddr; 14602 } 14603 14604 /* link together the rx bd chain pages */ 14605 for (j = 1; j <= RX_BD_NUM_PAGES; j++) { 14606 /* index into the rx bd chain array to last entry per page */ 14607 struct eth_rx_bd *rx_bd = 14608 &fp->rx_chain[RX_BD_TOTAL_PER_PAGE * j - 2]; 14609 /* point to the next page and wrap from last page */ 14610 busaddr = (fp->rx_dma.paddr + 14611 (BCM_PAGE_SIZE * (j % RX_BD_NUM_PAGES))); 14612 rx_bd->addr_hi = htole32(U64_HI(busaddr)); 14613 rx_bd->addr_lo = htole32(U64_LO(busaddr)); 14614 } 14615 14616 /*******************/ 14617 /* FP RX RCQ CHAIN */ 14618 /*******************/ 14619 14620 snprintf(buf, sizeof(buf), "fp %d rcq chain", i); 14621 if (bxe_dma_alloc(sc, (BCM_PAGE_SIZE * RCQ_NUM_PAGES), 14622 &fp->rcq_dma, buf) != 0) { 14623 /* XXX unwind and free previous fastpath allocations */ 14624 BLOGE(sc, "Failed to alloc %s\n", buf); 14625 return (1); 14626 } else { 14627 fp->rcq_chain = (union eth_rx_cqe *)fp->rcq_dma.vaddr; 14628 } 14629 14630 /* link together the rcq chain pages */ 14631 for (j = 1; j <= RCQ_NUM_PAGES; j++) { 14632 /* index into the rcq chain array to last entry per page */ 14633 struct eth_rx_cqe_next_page *rx_cqe_next = 14634 (struct eth_rx_cqe_next_page *) 14635 &fp->rcq_chain[RCQ_TOTAL_PER_PAGE * j - 1]; 14636 /* point to the next page and wrap from last page */ 14637 busaddr = (fp->rcq_dma.paddr + 14638 (BCM_PAGE_SIZE * (j % RCQ_NUM_PAGES))); 14639 rx_cqe_next->addr_hi = htole32(U64_HI(busaddr)); 14640 rx_cqe_next->addr_lo = htole32(U64_LO(busaddr)); 14641 } 14642 14643 /*******************/ 14644 /* FP RX SGE CHAIN */ 14645 /*******************/ 14646 14647 snprintf(buf, sizeof(buf), "fp %d sge chain", i); 14648 if (bxe_dma_alloc(sc, (BCM_PAGE_SIZE * RX_SGE_NUM_PAGES), 14649 &fp->rx_sge_dma, buf) != 0) { 14650 /* XXX unwind and free previous fastpath allocations */ 14651 BLOGE(sc, "Failed to alloc %s\n", buf); 14652 return (1); 14653 } else { 14654 fp->rx_sge_chain = (struct eth_rx_sge *)fp->rx_sge_dma.vaddr; 14655 } 14656 14657 /* link together the sge chain pages */ 14658 for (j = 1; j <= RX_SGE_NUM_PAGES; j++) { 14659 /* index into the rcq chain array to last entry per page */ 14660 struct eth_rx_sge *rx_sge = 14661 &fp->rx_sge_chain[RX_SGE_TOTAL_PER_PAGE * j - 2]; 14662 /* point to the next page and wrap from last page */ 14663 busaddr = (fp->rx_sge_dma.paddr + 14664 (BCM_PAGE_SIZE * (j % RX_SGE_NUM_PAGES))); 14665 rx_sge->addr_hi = htole32(U64_HI(busaddr)); 14666 rx_sge->addr_lo = htole32(U64_LO(busaddr)); 14667 } 14668 14669 /***********************/ 14670 /* FP TX MBUF DMA MAPS */ 14671 /***********************/ 14672 14673 /* set required sizes before mapping to conserve resources */ 14674 if (if_getcapenable(sc->ifp) & (IFCAP_TSO4 | IFCAP_TSO6)) { 14675 max_size = BXE_TSO_MAX_SIZE; 14676 max_segments = BXE_TSO_MAX_SEGMENTS; 14677 max_seg_size = BXE_TSO_MAX_SEG_SIZE; 14678 } else { 14679 max_size = (MCLBYTES * BXE_MAX_SEGMENTS); 14680 max_segments = BXE_MAX_SEGMENTS; 14681 max_seg_size = MCLBYTES; 14682 } 14683 14684 /* create a dma tag for the tx mbufs */ 14685 rc = bus_dma_tag_create(sc->parent_dma_tag, /* parent tag */ 14686 1, /* alignment */ 14687 0, /* boundary limit */ 14688 BUS_SPACE_MAXADDR, /* restricted low */ 14689 BUS_SPACE_MAXADDR, /* restricted hi */ 14690 NULL, /* addr filter() */ 14691 NULL, /* addr filter() arg */ 14692 max_size, /* max map size */ 14693 max_segments, /* num discontinuous */ 14694 max_seg_size, /* max seg size */ 14695 0, /* flags */ 14696 NULL, /* lock() */ 14697 NULL, /* lock() arg */ 14698 &fp->tx_mbuf_tag); /* returned dma tag */ 14699 if (rc != 0) { 14700 /* XXX unwind and free previous fastpath allocations */ 14701 BLOGE(sc, "Failed to create dma tag for " 14702 "'fp %d tx mbufs' (%d)\n", i, rc); 14703 return (1); 14704 } 14705 14706 /* create dma maps for each of the tx mbuf clusters */ 14707 for (j = 0; j < TX_BD_TOTAL; j++) { 14708 if (bus_dmamap_create(fp->tx_mbuf_tag, 14709 BUS_DMA_NOWAIT, 14710 &fp->tx_mbuf_chain[j].m_map)) { 14711 /* XXX unwind and free previous fastpath allocations */ 14712 BLOGE(sc, "Failed to create dma map for " 14713 "'fp %d tx mbuf %d' (%d)\n", i, j, rc); 14714 return (1); 14715 } 14716 } 14717 14718 /***********************/ 14719 /* FP RX MBUF DMA MAPS */ 14720 /***********************/ 14721 14722 /* create a dma tag for the rx mbufs */ 14723 rc = bus_dma_tag_create(sc->parent_dma_tag, /* parent tag */ 14724 1, /* alignment */ 14725 0, /* boundary limit */ 14726 BUS_SPACE_MAXADDR, /* restricted low */ 14727 BUS_SPACE_MAXADDR, /* restricted hi */ 14728 NULL, /* addr filter() */ 14729 NULL, /* addr filter() arg */ 14730 MJUM9BYTES, /* max map size */ 14731 1, /* num discontinuous */ 14732 MJUM9BYTES, /* max seg size */ 14733 0, /* flags */ 14734 NULL, /* lock() */ 14735 NULL, /* lock() arg */ 14736 &fp->rx_mbuf_tag); /* returned dma tag */ 14737 if (rc != 0) { 14738 /* XXX unwind and free previous fastpath allocations */ 14739 BLOGE(sc, "Failed to create dma tag for " 14740 "'fp %d rx mbufs' (%d)\n", i, rc); 14741 return (1); 14742 } 14743 14744 /* create dma maps for each of the rx mbuf clusters */ 14745 for (j = 0; j < RX_BD_TOTAL; j++) { 14746 if (bus_dmamap_create(fp->rx_mbuf_tag, 14747 BUS_DMA_NOWAIT, 14748 &fp->rx_mbuf_chain[j].m_map)) { 14749 /* XXX unwind and free previous fastpath allocations */ 14750 BLOGE(sc, "Failed to create dma map for " 14751 "'fp %d rx mbuf %d' (%d)\n", i, j, rc); 14752 return (1); 14753 } 14754 } 14755 14756 /* create dma map for the spare rx mbuf cluster */ 14757 if (bus_dmamap_create(fp->rx_mbuf_tag, 14758 BUS_DMA_NOWAIT, 14759 &fp->rx_mbuf_spare_map)) { 14760 /* XXX unwind and free previous fastpath allocations */ 14761 BLOGE(sc, "Failed to create dma map for " 14762 "'fp %d spare rx mbuf' (%d)\n", i, rc); 14763 return (1); 14764 } 14765 14766 /***************************/ 14767 /* FP RX SGE MBUF DMA MAPS */ 14768 /***************************/ 14769 14770 /* create a dma tag for the rx sge mbufs */ 14771 rc = bus_dma_tag_create(sc->parent_dma_tag, /* parent tag */ 14772 1, /* alignment */ 14773 0, /* boundary limit */ 14774 BUS_SPACE_MAXADDR, /* restricted low */ 14775 BUS_SPACE_MAXADDR, /* restricted hi */ 14776 NULL, /* addr filter() */ 14777 NULL, /* addr filter() arg */ 14778 BCM_PAGE_SIZE, /* max map size */ 14779 1, /* num discontinuous */ 14780 BCM_PAGE_SIZE, /* max seg size */ 14781 0, /* flags */ 14782 NULL, /* lock() */ 14783 NULL, /* lock() arg */ 14784 &fp->rx_sge_mbuf_tag); /* returned dma tag */ 14785 if (rc != 0) { 14786 /* XXX unwind and free previous fastpath allocations */ 14787 BLOGE(sc, "Failed to create dma tag for " 14788 "'fp %d rx sge mbufs' (%d)\n", i, rc); 14789 return (1); 14790 } 14791 14792 /* create dma maps for the rx sge mbuf clusters */ 14793 for (j = 0; j < RX_SGE_TOTAL; j++) { 14794 if (bus_dmamap_create(fp->rx_sge_mbuf_tag, 14795 BUS_DMA_NOWAIT, 14796 &fp->rx_sge_mbuf_chain[j].m_map)) { 14797 /* XXX unwind and free previous fastpath allocations */ 14798 BLOGE(sc, "Failed to create dma map for " 14799 "'fp %d rx sge mbuf %d' (%d)\n", i, j, rc); 14800 return (1); 14801 } 14802 } 14803 14804 /* create dma map for the spare rx sge mbuf cluster */ 14805 if (bus_dmamap_create(fp->rx_sge_mbuf_tag, 14806 BUS_DMA_NOWAIT, 14807 &fp->rx_sge_mbuf_spare_map)) { 14808 /* XXX unwind and free previous fastpath allocations */ 14809 BLOGE(sc, "Failed to create dma map for " 14810 "'fp %d spare rx sge mbuf' (%d)\n", i, rc); 14811 return (1); 14812 } 14813 14814 /***************************/ 14815 /* FP RX TPA MBUF DMA MAPS */ 14816 /***************************/ 14817 14818 /* create dma maps for the rx tpa mbuf clusters */ 14819 max_agg_queues = MAX_AGG_QS(sc); 14820 14821 for (j = 0; j < max_agg_queues; j++) { 14822 if (bus_dmamap_create(fp->rx_mbuf_tag, 14823 BUS_DMA_NOWAIT, 14824 &fp->rx_tpa_info[j].bd.m_map)) { 14825 /* XXX unwind and free previous fastpath allocations */ 14826 BLOGE(sc, "Failed to create dma map for " 14827 "'fp %d rx tpa mbuf %d' (%d)\n", i, j, rc); 14828 return (1); 14829 } 14830 } 14831 14832 /* create dma map for the spare rx tpa mbuf cluster */ 14833 if (bus_dmamap_create(fp->rx_mbuf_tag, 14834 BUS_DMA_NOWAIT, 14835 &fp->rx_tpa_info_mbuf_spare_map)) { 14836 /* XXX unwind and free previous fastpath allocations */ 14837 BLOGE(sc, "Failed to create dma map for " 14838 "'fp %d spare rx tpa mbuf' (%d)\n", i, rc); 14839 return (1); 14840 } 14841 14842 bxe_init_sge_ring_bit_mask(fp); 14843 } 14844 14845 return (0); 14846 } 14847 14848 static void 14849 bxe_free_hsi_mem(struct bxe_softc *sc) 14850 { 14851 struct bxe_fastpath *fp; 14852 int max_agg_queues; 14853 int i, j; 14854 14855 if (sc->parent_dma_tag == NULL) { 14856 return; /* assume nothing was allocated */ 14857 } 14858 14859 for (i = 0; i < sc->num_queues; i++) { 14860 fp = &sc->fp[i]; 14861 14862 /*******************/ 14863 /* FP STATUS BLOCK */ 14864 /*******************/ 14865 14866 bxe_dma_free(sc, &fp->sb_dma); 14867 memset(&fp->status_block, 0, sizeof(fp->status_block)); 14868 14869 /******************/ 14870 /* FP TX BD CHAIN */ 14871 /******************/ 14872 14873 bxe_dma_free(sc, &fp->tx_dma); 14874 fp->tx_chain = NULL; 14875 14876 /******************/ 14877 /* FP RX BD CHAIN */ 14878 /******************/ 14879 14880 bxe_dma_free(sc, &fp->rx_dma); 14881 fp->rx_chain = NULL; 14882 14883 /*******************/ 14884 /* FP RX RCQ CHAIN */ 14885 /*******************/ 14886 14887 bxe_dma_free(sc, &fp->rcq_dma); 14888 fp->rcq_chain = NULL; 14889 14890 /*******************/ 14891 /* FP RX SGE CHAIN */ 14892 /*******************/ 14893 14894 bxe_dma_free(sc, &fp->rx_sge_dma); 14895 fp->rx_sge_chain = NULL; 14896 14897 /***********************/ 14898 /* FP TX MBUF DMA MAPS */ 14899 /***********************/ 14900 14901 if (fp->tx_mbuf_tag != NULL) { 14902 for (j = 0; j < TX_BD_TOTAL; j++) { 14903 if (fp->tx_mbuf_chain[j].m_map != NULL) { 14904 bus_dmamap_unload(fp->tx_mbuf_tag, 14905 fp->tx_mbuf_chain[j].m_map); 14906 bus_dmamap_destroy(fp->tx_mbuf_tag, 14907 fp->tx_mbuf_chain[j].m_map); 14908 } 14909 } 14910 14911 bus_dma_tag_destroy(fp->tx_mbuf_tag); 14912 fp->tx_mbuf_tag = NULL; 14913 } 14914 14915 /***********************/ 14916 /* FP RX MBUF DMA MAPS */ 14917 /***********************/ 14918 14919 if (fp->rx_mbuf_tag != NULL) { 14920 for (j = 0; j < RX_BD_TOTAL; j++) { 14921 if (fp->rx_mbuf_chain[j].m_map != NULL) { 14922 bus_dmamap_unload(fp->rx_mbuf_tag, 14923 fp->rx_mbuf_chain[j].m_map); 14924 bus_dmamap_destroy(fp->rx_mbuf_tag, 14925 fp->rx_mbuf_chain[j].m_map); 14926 } 14927 } 14928 14929 if (fp->rx_mbuf_spare_map != NULL) { 14930 bus_dmamap_unload(fp->rx_mbuf_tag, fp->rx_mbuf_spare_map); 14931 bus_dmamap_destroy(fp->rx_mbuf_tag, fp->rx_mbuf_spare_map); 14932 } 14933 14934 /***************************/ 14935 /* FP RX TPA MBUF DMA MAPS */ 14936 /***************************/ 14937 14938 max_agg_queues = MAX_AGG_QS(sc); 14939 14940 for (j = 0; j < max_agg_queues; j++) { 14941 if (fp->rx_tpa_info[j].bd.m_map != NULL) { 14942 bus_dmamap_unload(fp->rx_mbuf_tag, 14943 fp->rx_tpa_info[j].bd.m_map); 14944 bus_dmamap_destroy(fp->rx_mbuf_tag, 14945 fp->rx_tpa_info[j].bd.m_map); 14946 } 14947 } 14948 14949 if (fp->rx_tpa_info_mbuf_spare_map != NULL) { 14950 bus_dmamap_unload(fp->rx_mbuf_tag, 14951 fp->rx_tpa_info_mbuf_spare_map); 14952 bus_dmamap_destroy(fp->rx_mbuf_tag, 14953 fp->rx_tpa_info_mbuf_spare_map); 14954 } 14955 14956 bus_dma_tag_destroy(fp->rx_mbuf_tag); 14957 fp->rx_mbuf_tag = NULL; 14958 } 14959 14960 /***************************/ 14961 /* FP RX SGE MBUF DMA MAPS */ 14962 /***************************/ 14963 14964 if (fp->rx_sge_mbuf_tag != NULL) { 14965 for (j = 0; j < RX_SGE_TOTAL; j++) { 14966 if (fp->rx_sge_mbuf_chain[j].m_map != NULL) { 14967 bus_dmamap_unload(fp->rx_sge_mbuf_tag, 14968 fp->rx_sge_mbuf_chain[j].m_map); 14969 bus_dmamap_destroy(fp->rx_sge_mbuf_tag, 14970 fp->rx_sge_mbuf_chain[j].m_map); 14971 } 14972 } 14973 14974 if (fp->rx_sge_mbuf_spare_map != NULL) { 14975 bus_dmamap_unload(fp->rx_sge_mbuf_tag, 14976 fp->rx_sge_mbuf_spare_map); 14977 bus_dmamap_destroy(fp->rx_sge_mbuf_tag, 14978 fp->rx_sge_mbuf_spare_map); 14979 } 14980 14981 bus_dma_tag_destroy(fp->rx_sge_mbuf_tag); 14982 fp->rx_sge_mbuf_tag = NULL; 14983 } 14984 } 14985 14986 /***************************/ 14987 /* FW DECOMPRESSION BUFFER */ 14988 /***************************/ 14989 14990 bxe_dma_free(sc, &sc->gz_buf_dma); 14991 sc->gz_buf = NULL; 14992 free(sc->gz_strm, M_DEVBUF); 14993 sc->gz_strm = NULL; 14994 14995 /*******************/ 14996 /* SLOW PATH QUEUE */ 14997 /*******************/ 14998 14999 bxe_dma_free(sc, &sc->spq_dma); 15000 sc->spq = NULL; 15001 15002 /*************/ 15003 /* SLOW PATH */ 15004 /*************/ 15005 15006 bxe_dma_free(sc, &sc->sp_dma); 15007 sc->sp = NULL; 15008 15009 /***************/ 15010 /* EVENT QUEUE */ 15011 /***************/ 15012 15013 bxe_dma_free(sc, &sc->eq_dma); 15014 sc->eq = NULL; 15015 15016 /************************/ 15017 /* DEFAULT STATUS BLOCK */ 15018 /************************/ 15019 15020 bxe_dma_free(sc, &sc->def_sb_dma); 15021 sc->def_sb = NULL; 15022 15023 bus_dma_tag_destroy(sc->parent_dma_tag); 15024 sc->parent_dma_tag = NULL; 15025 } 15026 15027 /* 15028 * Previous driver DMAE transaction may have occurred when pre-boot stage 15029 * ended and boot began. This would invalidate the addresses of the 15030 * transaction, resulting in was-error bit set in the PCI causing all 15031 * hw-to-host PCIe transactions to timeout. If this happened we want to clear 15032 * the interrupt which detected this from the pglueb and the was-done bit 15033 */ 15034 static void 15035 bxe_prev_interrupted_dmae(struct bxe_softc *sc) 15036 { 15037 uint32_t val; 15038 15039 if (!CHIP_IS_E1x(sc)) { 15040 val = REG_RD(sc, PGLUE_B_REG_PGLUE_B_INT_STS); 15041 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) { 15042 BLOGD(sc, DBG_LOAD, 15043 "Clearing 'was-error' bit that was set in pglueb"); 15044 REG_WR(sc, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, 1 << SC_FUNC(sc)); 15045 } 15046 } 15047 } 15048 15049 static int 15050 bxe_prev_mcp_done(struct bxe_softc *sc) 15051 { 15052 uint32_t rc = bxe_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, 15053 DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET); 15054 if (!rc) { 15055 BLOGE(sc, "MCP response failure, aborting\n"); 15056 return (-1); 15057 } 15058 15059 return (0); 15060 } 15061 15062 static struct bxe_prev_list_node * 15063 bxe_prev_path_get_entry(struct bxe_softc *sc) 15064 { 15065 struct bxe_prev_list_node *tmp; 15066 15067 LIST_FOREACH(tmp, &bxe_prev_list, node) { 15068 if ((sc->pcie_bus == tmp->bus) && 15069 (sc->pcie_device == tmp->slot) && 15070 (SC_PATH(sc) == tmp->path)) { 15071 return (tmp); 15072 } 15073 } 15074 15075 return (NULL); 15076 } 15077 15078 static uint8_t 15079 bxe_prev_is_path_marked(struct bxe_softc *sc) 15080 { 15081 struct bxe_prev_list_node *tmp; 15082 int rc = FALSE; 15083 15084 mtx_lock(&bxe_prev_mtx); 15085 15086 tmp = bxe_prev_path_get_entry(sc); 15087 if (tmp) { 15088 if (tmp->aer) { 15089 BLOGD(sc, DBG_LOAD, 15090 "Path %d/%d/%d was marked by AER\n", 15091 sc->pcie_bus, sc->pcie_device, SC_PATH(sc)); 15092 } else { 15093 rc = TRUE; 15094 BLOGD(sc, DBG_LOAD, 15095 "Path %d/%d/%d was already cleaned from previous drivers\n", 15096 sc->pcie_bus, sc->pcie_device, SC_PATH(sc)); 15097 } 15098 } 15099 15100 mtx_unlock(&bxe_prev_mtx); 15101 15102 return (rc); 15103 } 15104 15105 static int 15106 bxe_prev_mark_path(struct bxe_softc *sc, 15107 uint8_t after_undi) 15108 { 15109 struct bxe_prev_list_node *tmp; 15110 15111 mtx_lock(&bxe_prev_mtx); 15112 15113 /* Check whether the entry for this path already exists */ 15114 tmp = bxe_prev_path_get_entry(sc); 15115 if (tmp) { 15116 if (!tmp->aer) { 15117 BLOGD(sc, DBG_LOAD, 15118 "Re-marking AER in path %d/%d/%d\n", 15119 sc->pcie_bus, sc->pcie_device, SC_PATH(sc)); 15120 } else { 15121 BLOGD(sc, DBG_LOAD, 15122 "Removing AER indication from path %d/%d/%d\n", 15123 sc->pcie_bus, sc->pcie_device, SC_PATH(sc)); 15124 tmp->aer = 0; 15125 } 15126 15127 mtx_unlock(&bxe_prev_mtx); 15128 return (0); 15129 } 15130 15131 mtx_unlock(&bxe_prev_mtx); 15132 15133 /* Create an entry for this path and add it */ 15134 tmp = malloc(sizeof(struct bxe_prev_list_node), M_DEVBUF, 15135 (M_NOWAIT | M_ZERO)); 15136 if (!tmp) { 15137 BLOGE(sc, "Failed to allocate 'bxe_prev_list_node'\n"); 15138 return (-1); 15139 } 15140 15141 tmp->bus = sc->pcie_bus; 15142 tmp->slot = sc->pcie_device; 15143 tmp->path = SC_PATH(sc); 15144 tmp->aer = 0; 15145 tmp->undi = after_undi ? (1 << SC_PORT(sc)) : 0; 15146 15147 mtx_lock(&bxe_prev_mtx); 15148 15149 BLOGD(sc, DBG_LOAD, 15150 "Marked path %d/%d/%d - finished previous unload\n", 15151 sc->pcie_bus, sc->pcie_device, SC_PATH(sc)); 15152 LIST_INSERT_HEAD(&bxe_prev_list, tmp, node); 15153 15154 mtx_unlock(&bxe_prev_mtx); 15155 15156 return (0); 15157 } 15158 15159 static int 15160 bxe_do_flr(struct bxe_softc *sc) 15161 { 15162 int i; 15163 15164 /* only E2 and onwards support FLR */ 15165 if (CHIP_IS_E1x(sc)) { 15166 BLOGD(sc, DBG_LOAD, "FLR not supported in E1/E1H\n"); 15167 return (-1); 15168 } 15169 15170 /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */ 15171 if (sc->devinfo.bc_ver < REQ_BC_VER_4_INITIATE_FLR) { 15172 BLOGD(sc, DBG_LOAD, "FLR not supported by BC_VER: 0x%08x\n", 15173 sc->devinfo.bc_ver); 15174 return (-1); 15175 } 15176 15177 /* Wait for Transaction Pending bit clean */ 15178 for (i = 0; i < 4; i++) { 15179 if (i) { 15180 DELAY(((1 << (i - 1)) * 100) * 1000); 15181 } 15182 15183 if (!bxe_is_pcie_pending(sc)) { 15184 goto clear; 15185 } 15186 } 15187 15188 BLOGE(sc, "PCIE transaction is not cleared, " 15189 "proceeding with reset anyway\n"); 15190 15191 clear: 15192 15193 BLOGD(sc, DBG_LOAD, "Initiating FLR\n"); 15194 bxe_fw_command(sc, DRV_MSG_CODE_INITIATE_FLR, 0); 15195 15196 return (0); 15197 } 15198 15199 struct bxe_mac_vals { 15200 uint32_t xmac_addr; 15201 uint32_t xmac_val; 15202 uint32_t emac_addr; 15203 uint32_t emac_val; 15204 uint32_t umac_addr; 15205 uint32_t umac_val; 15206 uint32_t bmac_addr; 15207 uint32_t bmac_val[2]; 15208 }; 15209 15210 static void 15211 bxe_prev_unload_close_mac(struct bxe_softc *sc, 15212 struct bxe_mac_vals *vals) 15213 { 15214 uint32_t val, base_addr, offset, mask, reset_reg; 15215 uint8_t mac_stopped = FALSE; 15216 uint8_t port = SC_PORT(sc); 15217 uint32_t wb_data[2]; 15218 15219 /* reset addresses as they also mark which values were changed */ 15220 vals->bmac_addr = 0; 15221 vals->umac_addr = 0; 15222 vals->xmac_addr = 0; 15223 vals->emac_addr = 0; 15224 15225 reset_reg = REG_RD(sc, MISC_REG_RESET_REG_2); 15226 15227 if (!CHIP_IS_E3(sc)) { 15228 val = REG_RD(sc, NIG_REG_BMAC0_REGS_OUT_EN + port * 4); 15229 mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port; 15230 if ((mask & reset_reg) && val) { 15231 BLOGD(sc, DBG_LOAD, "Disable BMAC Rx\n"); 15232 base_addr = SC_PORT(sc) ? NIG_REG_INGRESS_BMAC1_MEM 15233 : NIG_REG_INGRESS_BMAC0_MEM; 15234 offset = CHIP_IS_E2(sc) ? BIGMAC2_REGISTER_BMAC_CONTROL 15235 : BIGMAC_REGISTER_BMAC_CONTROL; 15236 15237 /* 15238 * use rd/wr since we cannot use dmae. This is safe 15239 * since MCP won't access the bus due to the request 15240 * to unload, and no function on the path can be 15241 * loaded at this time. 15242 */ 15243 wb_data[0] = REG_RD(sc, base_addr + offset); 15244 wb_data[1] = REG_RD(sc, base_addr + offset + 0x4); 15245 vals->bmac_addr = base_addr + offset; 15246 vals->bmac_val[0] = wb_data[0]; 15247 vals->bmac_val[1] = wb_data[1]; 15248 wb_data[0] &= ~ELINK_BMAC_CONTROL_RX_ENABLE; 15249 REG_WR(sc, vals->bmac_addr, wb_data[0]); 15250 REG_WR(sc, vals->bmac_addr + 0x4, wb_data[1]); 15251 } 15252 15253 BLOGD(sc, DBG_LOAD, "Disable EMAC Rx\n"); 15254 vals->emac_addr = NIG_REG_NIG_EMAC0_EN + SC_PORT(sc)*4; 15255 vals->emac_val = REG_RD(sc, vals->emac_addr); 15256 REG_WR(sc, vals->emac_addr, 0); 15257 mac_stopped = TRUE; 15258 } else { 15259 if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) { 15260 BLOGD(sc, DBG_LOAD, "Disable XMAC Rx\n"); 15261 base_addr = SC_PORT(sc) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; 15262 val = REG_RD(sc, base_addr + XMAC_REG_PFC_CTRL_HI); 15263 REG_WR(sc, base_addr + XMAC_REG_PFC_CTRL_HI, val & ~(1 << 1)); 15264 REG_WR(sc, base_addr + XMAC_REG_PFC_CTRL_HI, val | (1 << 1)); 15265 vals->xmac_addr = base_addr + XMAC_REG_CTRL; 15266 vals->xmac_val = REG_RD(sc, vals->xmac_addr); 15267 REG_WR(sc, vals->xmac_addr, 0); 15268 mac_stopped = TRUE; 15269 } 15270 15271 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port; 15272 if (mask & reset_reg) { 15273 BLOGD(sc, DBG_LOAD, "Disable UMAC Rx\n"); 15274 base_addr = SC_PORT(sc) ? GRCBASE_UMAC1 : GRCBASE_UMAC0; 15275 vals->umac_addr = base_addr + UMAC_REG_COMMAND_CONFIG; 15276 vals->umac_val = REG_RD(sc, vals->umac_addr); 15277 REG_WR(sc, vals->umac_addr, 0); 15278 mac_stopped = TRUE; 15279 } 15280 } 15281 15282 if (mac_stopped) { 15283 DELAY(20000); 15284 } 15285 } 15286 15287 #define BXE_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4)) 15288 #define BXE_PREV_UNDI_RCQ(val) ((val) & 0xffff) 15289 #define BXE_PREV_UNDI_BD(val) ((val) >> 16 & 0xffff) 15290 #define BXE_PREV_UNDI_PROD(rcq, bd) ((bd) << 16 | (rcq)) 15291 15292 static void 15293 bxe_prev_unload_undi_inc(struct bxe_softc *sc, 15294 uint8_t port, 15295 uint8_t inc) 15296 { 15297 uint16_t rcq, bd; 15298 uint32_t tmp_reg = REG_RD(sc, BXE_PREV_UNDI_PROD_ADDR(port)); 15299 15300 rcq = BXE_PREV_UNDI_RCQ(tmp_reg) + inc; 15301 bd = BXE_PREV_UNDI_BD(tmp_reg) + inc; 15302 15303 tmp_reg = BXE_PREV_UNDI_PROD(rcq, bd); 15304 REG_WR(sc, BXE_PREV_UNDI_PROD_ADDR(port), tmp_reg); 15305 15306 BLOGD(sc, DBG_LOAD, 15307 "UNDI producer [%d] rings bd -> 0x%04x, rcq -> 0x%04x\n", 15308 port, bd, rcq); 15309 } 15310 15311 static int 15312 bxe_prev_unload_common(struct bxe_softc *sc) 15313 { 15314 uint32_t reset_reg, tmp_reg = 0, rc; 15315 uint8_t prev_undi = FALSE; 15316 struct bxe_mac_vals mac_vals; 15317 uint32_t timer_count = 1000; 15318 uint32_t prev_brb; 15319 15320 /* 15321 * It is possible a previous function received 'common' answer, 15322 * but hasn't loaded yet, therefore creating a scenario of 15323 * multiple functions receiving 'common' on the same path. 15324 */ 15325 BLOGD(sc, DBG_LOAD, "Common unload Flow\n"); 15326 15327 memset(&mac_vals, 0, sizeof(mac_vals)); 15328 15329 if (bxe_prev_is_path_marked(sc)) { 15330 return (bxe_prev_mcp_done(sc)); 15331 } 15332 15333 reset_reg = REG_RD(sc, MISC_REG_RESET_REG_1); 15334 15335 /* Reset should be performed after BRB is emptied */ 15336 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) { 15337 /* Close the MAC Rx to prevent BRB from filling up */ 15338 bxe_prev_unload_close_mac(sc, &mac_vals); 15339 15340 /* close LLH filters towards the BRB */ 15341 elink_set_rx_filter(&sc->link_params, 0); 15342 15343 /* 15344 * Check if the UNDI driver was previously loaded. 15345 * UNDI driver initializes CID offset for normal bell to 0x7 15346 */ 15347 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_DORQ) { 15348 tmp_reg = REG_RD(sc, DORQ_REG_NORM_CID_OFST); 15349 if (tmp_reg == 0x7) { 15350 BLOGD(sc, DBG_LOAD, "UNDI previously loaded\n"); 15351 prev_undi = TRUE; 15352 /* clear the UNDI indication */ 15353 REG_WR(sc, DORQ_REG_NORM_CID_OFST, 0); 15354 /* clear possible idle check errors */ 15355 REG_RD(sc, NIG_REG_NIG_INT_STS_CLR_0); 15356 } 15357 } 15358 15359 /* wait until BRB is empty */ 15360 tmp_reg = REG_RD(sc, BRB1_REG_NUM_OF_FULL_BLOCKS); 15361 while (timer_count) { 15362 prev_brb = tmp_reg; 15363 15364 tmp_reg = REG_RD(sc, BRB1_REG_NUM_OF_FULL_BLOCKS); 15365 if (!tmp_reg) { 15366 break; 15367 } 15368 15369 BLOGD(sc, DBG_LOAD, "BRB still has 0x%08x\n", tmp_reg); 15370 15371 /* reset timer as long as BRB actually gets emptied */ 15372 if (prev_brb > tmp_reg) { 15373 timer_count = 1000; 15374 } else { 15375 timer_count--; 15376 } 15377 15378 /* If UNDI resides in memory, manually increment it */ 15379 if (prev_undi) { 15380 bxe_prev_unload_undi_inc(sc, SC_PORT(sc), 1); 15381 } 15382 15383 DELAY(10); 15384 } 15385 15386 if (!timer_count) { 15387 BLOGE(sc, "Failed to empty BRB\n"); 15388 } 15389 } 15390 15391 /* No packets are in the pipeline, path is ready for reset */ 15392 bxe_reset_common(sc); 15393 15394 if (mac_vals.xmac_addr) { 15395 REG_WR(sc, mac_vals.xmac_addr, mac_vals.xmac_val); 15396 } 15397 if (mac_vals.umac_addr) { 15398 REG_WR(sc, mac_vals.umac_addr, mac_vals.umac_val); 15399 } 15400 if (mac_vals.emac_addr) { 15401 REG_WR(sc, mac_vals.emac_addr, mac_vals.emac_val); 15402 } 15403 if (mac_vals.bmac_addr) { 15404 REG_WR(sc, mac_vals.bmac_addr, mac_vals.bmac_val[0]); 15405 REG_WR(sc, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]); 15406 } 15407 15408 rc = bxe_prev_mark_path(sc, prev_undi); 15409 if (rc) { 15410 bxe_prev_mcp_done(sc); 15411 return (rc); 15412 } 15413 15414 return (bxe_prev_mcp_done(sc)); 15415 } 15416 15417 static int 15418 bxe_prev_unload_uncommon(struct bxe_softc *sc) 15419 { 15420 int rc; 15421 15422 BLOGD(sc, DBG_LOAD, "Uncommon unload Flow\n"); 15423 15424 /* Test if previous unload process was already finished for this path */ 15425 if (bxe_prev_is_path_marked(sc)) { 15426 return (bxe_prev_mcp_done(sc)); 15427 } 15428 15429 BLOGD(sc, DBG_LOAD, "Path is unmarked\n"); 15430 15431 /* 15432 * If function has FLR capabilities, and existing FW version matches 15433 * the one required, then FLR will be sufficient to clean any residue 15434 * left by previous driver 15435 */ 15436 rc = bxe_nic_load_analyze_req(sc, FW_MSG_CODE_DRV_LOAD_FUNCTION); 15437 if (!rc) { 15438 /* fw version is good */ 15439 BLOGD(sc, DBG_LOAD, "FW version matches our own, attempting FLR\n"); 15440 rc = bxe_do_flr(sc); 15441 } 15442 15443 if (!rc) { 15444 /* FLR was performed */ 15445 BLOGD(sc, DBG_LOAD, "FLR successful\n"); 15446 return (0); 15447 } 15448 15449 BLOGD(sc, DBG_LOAD, "Could not FLR\n"); 15450 15451 /* Close the MCP request, return failure*/ 15452 rc = bxe_prev_mcp_done(sc); 15453 if (!rc) { 15454 rc = BXE_PREV_WAIT_NEEDED; 15455 } 15456 15457 return (rc); 15458 } 15459 15460 static int 15461 bxe_prev_unload(struct bxe_softc *sc) 15462 { 15463 int time_counter = 10; 15464 uint32_t fw, hw_lock_reg, hw_lock_val; 15465 uint32_t rc = 0; 15466 15467 /* 15468 * Clear HW from errors which may have resulted from an interrupted 15469 * DMAE transaction. 15470 */ 15471 bxe_prev_interrupted_dmae(sc); 15472 15473 /* Release previously held locks */ 15474 hw_lock_reg = 15475 (SC_FUNC(sc) <= 5) ? 15476 (MISC_REG_DRIVER_CONTROL_1 + SC_FUNC(sc) * 8) : 15477 (MISC_REG_DRIVER_CONTROL_7 + (SC_FUNC(sc) - 6) * 8); 15478 15479 hw_lock_val = (REG_RD(sc, hw_lock_reg)); 15480 if (hw_lock_val) { 15481 if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) { 15482 BLOGD(sc, DBG_LOAD, "Releasing previously held NVRAM lock\n"); 15483 REG_WR(sc, MCP_REG_MCPR_NVM_SW_ARB, 15484 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << SC_PORT(sc))); 15485 } 15486 BLOGD(sc, DBG_LOAD, "Releasing previously held HW lock\n"); 15487 REG_WR(sc, hw_lock_reg, 0xffffffff); 15488 } else { 15489 BLOGD(sc, DBG_LOAD, "No need to release HW/NVRAM locks\n"); 15490 } 15491 15492 if (MCPR_ACCESS_LOCK_LOCK & REG_RD(sc, MCP_REG_MCPR_ACCESS_LOCK)) { 15493 BLOGD(sc, DBG_LOAD, "Releasing previously held ALR\n"); 15494 REG_WR(sc, MCP_REG_MCPR_ACCESS_LOCK, 0); 15495 } 15496 15497 do { 15498 /* Lock MCP using an unload request */ 15499 fw = bxe_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0); 15500 if (!fw) { 15501 BLOGE(sc, "MCP response failure, aborting\n"); 15502 rc = -1; 15503 break; 15504 } 15505 15506 if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON) { 15507 rc = bxe_prev_unload_common(sc); 15508 break; 15509 } 15510 15511 /* non-common reply from MCP night require looping */ 15512 rc = bxe_prev_unload_uncommon(sc); 15513 if (rc != BXE_PREV_WAIT_NEEDED) { 15514 break; 15515 } 15516 15517 DELAY(20000); 15518 } while (--time_counter); 15519 15520 if (!time_counter || rc) { 15521 BLOGE(sc, "Failed to unload previous driver!" 15522 " time_counter %d rc %d\n", time_counter, rc); 15523 rc = -1; 15524 } 15525 15526 return (rc); 15527 } 15528 15529 void 15530 bxe_dcbx_set_state(struct bxe_softc *sc, 15531 uint8_t dcb_on, 15532 uint32_t dcbx_enabled) 15533 { 15534 if (!CHIP_IS_E1x(sc)) { 15535 sc->dcb_state = dcb_on; 15536 sc->dcbx_enabled = dcbx_enabled; 15537 } else { 15538 sc->dcb_state = FALSE; 15539 sc->dcbx_enabled = BXE_DCBX_ENABLED_INVALID; 15540 } 15541 BLOGD(sc, DBG_LOAD, 15542 "DCB state [%s:%s]\n", 15543 dcb_on ? "ON" : "OFF", 15544 (dcbx_enabled == BXE_DCBX_ENABLED_OFF) ? "user-mode" : 15545 (dcbx_enabled == BXE_DCBX_ENABLED_ON_NEG_OFF) ? "on-chip static" : 15546 (dcbx_enabled == BXE_DCBX_ENABLED_ON_NEG_ON) ? 15547 "on-chip with negotiation" : "invalid"); 15548 } 15549 15550 /* must be called after sriov-enable */ 15551 static int 15552 bxe_set_qm_cid_count(struct bxe_softc *sc) 15553 { 15554 int cid_count = BXE_L2_MAX_CID(sc); 15555 15556 if (IS_SRIOV(sc)) { 15557 cid_count += BXE_VF_CIDS; 15558 } 15559 15560 if (CNIC_SUPPORT(sc)) { 15561 cid_count += CNIC_CID_MAX; 15562 } 15563 15564 return (roundup(cid_count, QM_CID_ROUND)); 15565 } 15566 15567 static void 15568 bxe_init_multi_cos(struct bxe_softc *sc) 15569 { 15570 int pri, cos; 15571 15572 uint32_t pri_map = 0; /* XXX change to user config */ 15573 15574 for (pri = 0; pri < BXE_MAX_PRIORITY; pri++) { 15575 cos = ((pri_map & (0xf << (pri * 4))) >> (pri * 4)); 15576 if (cos < sc->max_cos) { 15577 sc->prio_to_cos[pri] = cos; 15578 } else { 15579 BLOGW(sc, "Invalid COS %d for priority %d " 15580 "(max COS is %d), setting to 0\n", 15581 cos, pri, (sc->max_cos - 1)); 15582 sc->prio_to_cos[pri] = 0; 15583 } 15584 } 15585 } 15586 15587 static int 15588 bxe_sysctl_state(SYSCTL_HANDLER_ARGS) 15589 { 15590 struct bxe_softc *sc; 15591 int error, result; 15592 15593 result = 0; 15594 error = sysctl_handle_int(oidp, &result, 0, req); 15595 15596 if (error || !req->newptr) { 15597 return (error); 15598 } 15599 15600 if (result == 1) { 15601 uint32_t temp; 15602 sc = (struct bxe_softc *)arg1; 15603 15604 BLOGI(sc, "... dumping driver state ...\n"); 15605 temp = SHMEM2_RD(sc, temperature_in_half_celsius); 15606 BLOGI(sc, "\t Device Temperature = %d Celsius\n", (temp/2)); 15607 } 15608 15609 return (error); 15610 } 15611 15612 static int 15613 bxe_sysctl_eth_stat(SYSCTL_HANDLER_ARGS) 15614 { 15615 struct bxe_softc *sc = (struct bxe_softc *)arg1; 15616 uint32_t *eth_stats = (uint32_t *)&sc->eth_stats; 15617 uint32_t *offset; 15618 uint64_t value = 0; 15619 int index = (int)arg2; 15620 15621 if (index >= BXE_NUM_ETH_STATS) { 15622 BLOGE(sc, "bxe_eth_stats index out of range (%d)\n", index); 15623 return (-1); 15624 } 15625 15626 offset = (eth_stats + bxe_eth_stats_arr[index].offset); 15627 15628 switch (bxe_eth_stats_arr[index].size) { 15629 case 4: 15630 value = (uint64_t)*offset; 15631 break; 15632 case 8: 15633 value = HILO_U64(*offset, *(offset + 1)); 15634 break; 15635 default: 15636 BLOGE(sc, "Invalid bxe_eth_stats size (index=%d size=%d)\n", 15637 index, bxe_eth_stats_arr[index].size); 15638 return (-1); 15639 } 15640 15641 return (sysctl_handle_64(oidp, &value, 0, req)); 15642 } 15643 15644 static int 15645 bxe_sysctl_eth_q_stat(SYSCTL_HANDLER_ARGS) 15646 { 15647 struct bxe_softc *sc = (struct bxe_softc *)arg1; 15648 uint32_t *eth_stats; 15649 uint32_t *offset; 15650 uint64_t value = 0; 15651 uint32_t q_stat = (uint32_t)arg2; 15652 uint32_t fp_index = ((q_stat >> 16) & 0xffff); 15653 uint32_t index = (q_stat & 0xffff); 15654 15655 eth_stats = (uint32_t *)&sc->fp[fp_index].eth_q_stats; 15656 15657 if (index >= BXE_NUM_ETH_Q_STATS) { 15658 BLOGE(sc, "bxe_eth_q_stats index out of range (%d)\n", index); 15659 return (-1); 15660 } 15661 15662 offset = (eth_stats + bxe_eth_q_stats_arr[index].offset); 15663 15664 switch (bxe_eth_q_stats_arr[index].size) { 15665 case 4: 15666 value = (uint64_t)*offset; 15667 break; 15668 case 8: 15669 value = HILO_U64(*offset, *(offset + 1)); 15670 break; 15671 default: 15672 BLOGE(sc, "Invalid bxe_eth_q_stats size (index=%d size=%d)\n", 15673 index, bxe_eth_q_stats_arr[index].size); 15674 return (-1); 15675 } 15676 15677 return (sysctl_handle_64(oidp, &value, 0, req)); 15678 } 15679 15680 static void bxe_force_link_reset(struct bxe_softc *sc) 15681 { 15682 15683 bxe_acquire_phy_lock(sc); 15684 elink_link_reset(&sc->link_params, &sc->link_vars, 1); 15685 bxe_release_phy_lock(sc); 15686 } 15687 15688 static int 15689 bxe_sysctl_pauseparam(SYSCTL_HANDLER_ARGS) 15690 { 15691 struct bxe_softc *sc = (struct bxe_softc *)arg1;; 15692 uint32_t cfg_idx = bxe_get_link_cfg_idx(sc); 15693 int rc = 0; 15694 int error; 15695 int result; 15696 15697 15698 error = sysctl_handle_int(oidp, &sc->bxe_pause_param, 0, req); 15699 15700 if (error || !req->newptr) { 15701 return (error); 15702 } 15703 if ((sc->bxe_pause_param < 0) || (sc->bxe_pause_param > 8)) { 15704 BLOGW(sc, "invalid pause param (%d) - use intergers between 1 & 8\n",sc->bxe_pause_param); 15705 sc->bxe_pause_param = 8; 15706 } 15707 15708 result = (sc->bxe_pause_param << PORT_FEATURE_FLOW_CONTROL_SHIFT); 15709 15710 15711 if((result & 0x400) && !(sc->port.supported[cfg_idx] & ELINK_SUPPORTED_Autoneg)) { 15712 BLOGW(sc, "Does not support Autoneg pause_param %d\n", sc->bxe_pause_param); 15713 return -EINVAL; 15714 } 15715 15716 if(IS_MF(sc)) 15717 return 0; 15718 sc->link_params.req_flow_ctrl[cfg_idx] = ELINK_FLOW_CTRL_AUTO; 15719 if(result & ELINK_FLOW_CTRL_RX) 15720 sc->link_params.req_flow_ctrl[cfg_idx] |= ELINK_FLOW_CTRL_RX; 15721 15722 if(result & ELINK_FLOW_CTRL_TX) 15723 sc->link_params.req_flow_ctrl[cfg_idx] |= ELINK_FLOW_CTRL_TX; 15724 if(sc->link_params.req_flow_ctrl[cfg_idx] == ELINK_FLOW_CTRL_AUTO) 15725 sc->link_params.req_flow_ctrl[cfg_idx] = ELINK_FLOW_CTRL_NONE; 15726 15727 if(result & 0x400) { 15728 if (sc->link_params.req_line_speed[cfg_idx] == ELINK_SPEED_AUTO_NEG) { 15729 sc->link_params.req_flow_ctrl[cfg_idx] = 15730 ELINK_FLOW_CTRL_AUTO; 15731 } 15732 sc->link_params.req_fc_auto_adv = 0; 15733 if (result & ELINK_FLOW_CTRL_RX) 15734 sc->link_params.req_fc_auto_adv |= ELINK_FLOW_CTRL_RX; 15735 15736 if (result & ELINK_FLOW_CTRL_TX) 15737 sc->link_params.req_fc_auto_adv |= ELINK_FLOW_CTRL_TX; 15738 if (!sc->link_params.req_fc_auto_adv) 15739 sc->link_params.req_fc_auto_adv |= ELINK_FLOW_CTRL_NONE; 15740 } 15741 if (IS_PF(sc)) { 15742 if (sc->link_vars.link_up) { 15743 bxe_stats_handle(sc, STATS_EVENT_STOP); 15744 } 15745 if (if_getdrvflags(sc->ifp) & IFF_DRV_RUNNING) { 15746 bxe_force_link_reset(sc); 15747 bxe_acquire_phy_lock(sc); 15748 15749 rc = elink_phy_init(&sc->link_params, &sc->link_vars); 15750 15751 bxe_release_phy_lock(sc); 15752 15753 bxe_calc_fc_adv(sc); 15754 } 15755 } 15756 return rc; 15757 } 15758 15759 15760 static void 15761 bxe_add_sysctls(struct bxe_softc *sc) 15762 { 15763 struct sysctl_ctx_list *ctx; 15764 struct sysctl_oid_list *children; 15765 struct sysctl_oid *queue_top, *queue; 15766 struct sysctl_oid_list *queue_top_children, *queue_children; 15767 char queue_num_buf[32]; 15768 uint32_t q_stat; 15769 int i, j; 15770 15771 ctx = device_get_sysctl_ctx(sc->dev); 15772 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)); 15773 15774 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "version", 15775 CTLFLAG_RD, BXE_DRIVER_VERSION, 0, 15776 "version"); 15777 15778 snprintf(sc->fw_ver_str, sizeof(sc->fw_ver_str), "%d.%d.%d.%d", 15779 BCM_5710_FW_MAJOR_VERSION, 15780 BCM_5710_FW_MINOR_VERSION, 15781 BCM_5710_FW_REVISION_VERSION, 15782 BCM_5710_FW_ENGINEERING_VERSION); 15783 15784 snprintf(sc->mf_mode_str, sizeof(sc->mf_mode_str), "%s", 15785 ((sc->devinfo.mf_info.mf_mode == SINGLE_FUNCTION) ? "Single" : 15786 (sc->devinfo.mf_info.mf_mode == MULTI_FUNCTION_SD) ? "MF-SD" : 15787 (sc->devinfo.mf_info.mf_mode == MULTI_FUNCTION_SI) ? "MF-SI" : 15788 (sc->devinfo.mf_info.mf_mode == MULTI_FUNCTION_AFEX) ? "MF-AFEX" : 15789 "Unknown")); 15790 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "mf_vnics", 15791 CTLFLAG_RD, &sc->devinfo.mf_info.vnics_per_port, 0, 15792 "multifunction vnics per port"); 15793 15794 snprintf(sc->pci_link_str, sizeof(sc->pci_link_str), "%s x%d", 15795 ((sc->devinfo.pcie_link_speed == 1) ? "2.5GT/s" : 15796 (sc->devinfo.pcie_link_speed == 2) ? "5.0GT/s" : 15797 (sc->devinfo.pcie_link_speed == 4) ? "8.0GT/s" : 15798 "???GT/s"), 15799 sc->devinfo.pcie_link_width); 15800 15801 sc->debug = bxe_debug; 15802 15803 #if __FreeBSD_version >= 900000 15804 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "bc_version", 15805 CTLFLAG_RD, sc->devinfo.bc_ver_str, 0, 15806 "bootcode version"); 15807 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "fw_version", 15808 CTLFLAG_RD, sc->fw_ver_str, 0, 15809 "firmware version"); 15810 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "mf_mode", 15811 CTLFLAG_RD, sc->mf_mode_str, 0, 15812 "multifunction mode"); 15813 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "mac_addr", 15814 CTLFLAG_RD, sc->mac_addr_str, 0, 15815 "mac address"); 15816 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "pci_link", 15817 CTLFLAG_RD, sc->pci_link_str, 0, 15818 "pci link status"); 15819 SYSCTL_ADD_ULONG(ctx, children, OID_AUTO, "debug", 15820 CTLFLAG_RW, &sc->debug, 15821 "debug logging mode"); 15822 #else 15823 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "bc_version", 15824 CTLFLAG_RD, &sc->devinfo.bc_ver_str, 0, 15825 "bootcode version"); 15826 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "fw_version", 15827 CTLFLAG_RD, &sc->fw_ver_str, 0, 15828 "firmware version"); 15829 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "mf_mode", 15830 CTLFLAG_RD, &sc->mf_mode_str, 0, 15831 "multifunction mode"); 15832 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "mac_addr", 15833 CTLFLAG_RD, &sc->mac_addr_str, 0, 15834 "mac address"); 15835 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "pci_link", 15836 CTLFLAG_RD, &sc->pci_link_str, 0, 15837 "pci link status"); 15838 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "debug", 15839 CTLFLAG_RW, &sc->debug, 0, 15840 "debug logging mode"); 15841 #endif /* #if __FreeBSD_version >= 900000 */ 15842 15843 sc->trigger_grcdump = 0; 15844 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "trigger_grcdump", 15845 CTLFLAG_RW, &sc->trigger_grcdump, 0, 15846 "trigger grcdump should be invoked" 15847 " before collecting grcdump"); 15848 15849 sc->grcdump_started = 0; 15850 sc->grcdump_done = 0; 15851 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "grcdump_done", 15852 CTLFLAG_RD, &sc->grcdump_done, 0, 15853 "set by driver when grcdump is done"); 15854 15855 sc->rx_budget = bxe_rx_budget; 15856 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rx_budget", 15857 CTLFLAG_RW, &sc->rx_budget, 0, 15858 "rx processing budget"); 15859 15860 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pause_param", 15861 CTLTYPE_UINT | CTLFLAG_RW, sc, 0, 15862 bxe_sysctl_pauseparam, "IU", 15863 "need pause frames- DEF:0/TX:1/RX:2/BOTH:3/AUTO:4/AUTOTX:5/AUTORX:6/AUTORXTX:7/NONE:8"); 15864 15865 15866 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "state", 15867 CTLTYPE_UINT | CTLFLAG_RW, sc, 0, 15868 bxe_sysctl_state, "IU", "dump driver state"); 15869 15870 for (i = 0; i < BXE_NUM_ETH_STATS; i++) { 15871 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 15872 bxe_eth_stats_arr[i].string, 15873 CTLTYPE_U64 | CTLFLAG_RD, sc, i, 15874 bxe_sysctl_eth_stat, "LU", 15875 bxe_eth_stats_arr[i].string); 15876 } 15877 15878 /* add a new parent node for all queues "dev.bxe.#.queue" */ 15879 queue_top = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "queue", 15880 CTLFLAG_RD, NULL, "queue"); 15881 queue_top_children = SYSCTL_CHILDREN(queue_top); 15882 15883 for (i = 0; i < sc->num_queues; i++) { 15884 /* add a new parent node for a single queue "dev.bxe.#.queue.#" */ 15885 snprintf(queue_num_buf, sizeof(queue_num_buf), "%d", i); 15886 queue = SYSCTL_ADD_NODE(ctx, queue_top_children, OID_AUTO, 15887 queue_num_buf, CTLFLAG_RD, NULL, 15888 "single queue"); 15889 queue_children = SYSCTL_CHILDREN(queue); 15890 15891 for (j = 0; j < BXE_NUM_ETH_Q_STATS; j++) { 15892 q_stat = ((i << 16) | j); 15893 SYSCTL_ADD_PROC(ctx, queue_children, OID_AUTO, 15894 bxe_eth_q_stats_arr[j].string, 15895 CTLTYPE_U64 | CTLFLAG_RD, sc, q_stat, 15896 bxe_sysctl_eth_q_stat, "LU", 15897 bxe_eth_q_stats_arr[j].string); 15898 } 15899 } 15900 } 15901 15902 static int 15903 bxe_alloc_buf_rings(struct bxe_softc *sc) 15904 { 15905 #if __FreeBSD_version >= 901504 15906 15907 int i; 15908 struct bxe_fastpath *fp; 15909 15910 for (i = 0; i < sc->num_queues; i++) { 15911 15912 fp = &sc->fp[i]; 15913 15914 fp->tx_br = buf_ring_alloc(BXE_BR_SIZE, M_DEVBUF, 15915 M_NOWAIT, &fp->tx_mtx); 15916 if (fp->tx_br == NULL) 15917 return (-1); 15918 } 15919 #endif 15920 return (0); 15921 } 15922 15923 static void 15924 bxe_free_buf_rings(struct bxe_softc *sc) 15925 { 15926 #if __FreeBSD_version >= 901504 15927 15928 int i; 15929 struct bxe_fastpath *fp; 15930 15931 for (i = 0; i < sc->num_queues; i++) { 15932 15933 fp = &sc->fp[i]; 15934 15935 if (fp->tx_br) { 15936 buf_ring_free(fp->tx_br, M_DEVBUF); 15937 fp->tx_br = NULL; 15938 } 15939 } 15940 15941 #endif 15942 } 15943 15944 static void 15945 bxe_init_fp_mutexs(struct bxe_softc *sc) 15946 { 15947 int i; 15948 struct bxe_fastpath *fp; 15949 15950 for (i = 0; i < sc->num_queues; i++) { 15951 15952 fp = &sc->fp[i]; 15953 15954 snprintf(fp->tx_mtx_name, sizeof(fp->tx_mtx_name), 15955 "bxe%d_fp%d_tx_lock", sc->unit, i); 15956 mtx_init(&fp->tx_mtx, fp->tx_mtx_name, NULL, MTX_DEF); 15957 15958 snprintf(fp->rx_mtx_name, sizeof(fp->rx_mtx_name), 15959 "bxe%d_fp%d_rx_lock", sc->unit, i); 15960 mtx_init(&fp->rx_mtx, fp->rx_mtx_name, NULL, MTX_DEF); 15961 } 15962 } 15963 15964 static void 15965 bxe_destroy_fp_mutexs(struct bxe_softc *sc) 15966 { 15967 int i; 15968 struct bxe_fastpath *fp; 15969 15970 for (i = 0; i < sc->num_queues; i++) { 15971 15972 fp = &sc->fp[i]; 15973 15974 if (mtx_initialized(&fp->tx_mtx)) { 15975 mtx_destroy(&fp->tx_mtx); 15976 } 15977 15978 if (mtx_initialized(&fp->rx_mtx)) { 15979 mtx_destroy(&fp->rx_mtx); 15980 } 15981 } 15982 } 15983 15984 15985 /* 15986 * Device attach function. 15987 * 15988 * Allocates device resources, performs secondary chip identification, and 15989 * initializes driver instance variables. This function is called from driver 15990 * load after a successful probe. 15991 * 15992 * Returns: 15993 * 0 = Success, >0 = Failure 15994 */ 15995 static int 15996 bxe_attach(device_t dev) 15997 { 15998 struct bxe_softc *sc; 15999 16000 sc = device_get_softc(dev); 16001 16002 BLOGD(sc, DBG_LOAD, "Starting attach...\n"); 16003 16004 sc->state = BXE_STATE_CLOSED; 16005 16006 sc->dev = dev; 16007 sc->unit = device_get_unit(dev); 16008 16009 BLOGD(sc, DBG_LOAD, "softc = %p\n", sc); 16010 16011 sc->pcie_bus = pci_get_bus(dev); 16012 sc->pcie_device = pci_get_slot(dev); 16013 sc->pcie_func = pci_get_function(dev); 16014 16015 /* enable bus master capability */ 16016 pci_enable_busmaster(dev); 16017 16018 /* get the BARs */ 16019 if (bxe_allocate_bars(sc) != 0) { 16020 return (ENXIO); 16021 } 16022 16023 /* initialize the mutexes */ 16024 bxe_init_mutexes(sc); 16025 16026 /* prepare the periodic callout */ 16027 callout_init(&sc->periodic_callout, 0); 16028 16029 /* prepare the chip taskqueue */ 16030 sc->chip_tq_flags = CHIP_TQ_NONE; 16031 snprintf(sc->chip_tq_name, sizeof(sc->chip_tq_name), 16032 "bxe%d_chip_tq", sc->unit); 16033 TASK_INIT(&sc->chip_tq_task, 0, bxe_handle_chip_tq, sc); 16034 sc->chip_tq = taskqueue_create(sc->chip_tq_name, M_NOWAIT, 16035 taskqueue_thread_enqueue, 16036 &sc->chip_tq); 16037 taskqueue_start_threads(&sc->chip_tq, 1, PWAIT, /* lower priority */ 16038 "%s", sc->chip_tq_name); 16039 16040 /* get device info and set params */ 16041 if (bxe_get_device_info(sc) != 0) { 16042 BLOGE(sc, "getting device info\n"); 16043 bxe_deallocate_bars(sc); 16044 pci_disable_busmaster(dev); 16045 return (ENXIO); 16046 } 16047 16048 /* get final misc params */ 16049 bxe_get_params(sc); 16050 16051 /* set the default MTU (changed via ifconfig) */ 16052 sc->mtu = ETHERMTU; 16053 16054 bxe_set_modes_bitmap(sc); 16055 16056 /* XXX 16057 * If in AFEX mode and the function is configured for FCoE 16058 * then bail... no L2 allowed. 16059 */ 16060 16061 /* get phy settings from shmem and 'and' against admin settings */ 16062 bxe_get_phy_info(sc); 16063 16064 /* initialize the FreeBSD ifnet interface */ 16065 if (bxe_init_ifnet(sc) != 0) { 16066 bxe_release_mutexes(sc); 16067 bxe_deallocate_bars(sc); 16068 pci_disable_busmaster(dev); 16069 return (ENXIO); 16070 } 16071 16072 if (bxe_add_cdev(sc) != 0) { 16073 if (sc->ifp != NULL) { 16074 ether_ifdetach(sc->ifp); 16075 } 16076 ifmedia_removeall(&sc->ifmedia); 16077 bxe_release_mutexes(sc); 16078 bxe_deallocate_bars(sc); 16079 pci_disable_busmaster(dev); 16080 return (ENXIO); 16081 } 16082 16083 /* allocate device interrupts */ 16084 if (bxe_interrupt_alloc(sc) != 0) { 16085 bxe_del_cdev(sc); 16086 if (sc->ifp != NULL) { 16087 ether_ifdetach(sc->ifp); 16088 } 16089 ifmedia_removeall(&sc->ifmedia); 16090 bxe_release_mutexes(sc); 16091 bxe_deallocate_bars(sc); 16092 pci_disable_busmaster(dev); 16093 return (ENXIO); 16094 } 16095 16096 bxe_init_fp_mutexs(sc); 16097 16098 if (bxe_alloc_buf_rings(sc) != 0) { 16099 bxe_free_buf_rings(sc); 16100 bxe_interrupt_free(sc); 16101 bxe_del_cdev(sc); 16102 if (sc->ifp != NULL) { 16103 ether_ifdetach(sc->ifp); 16104 } 16105 ifmedia_removeall(&sc->ifmedia); 16106 bxe_release_mutexes(sc); 16107 bxe_deallocate_bars(sc); 16108 pci_disable_busmaster(dev); 16109 return (ENXIO); 16110 } 16111 16112 /* allocate ilt */ 16113 if (bxe_alloc_ilt_mem(sc) != 0) { 16114 bxe_free_buf_rings(sc); 16115 bxe_interrupt_free(sc); 16116 bxe_del_cdev(sc); 16117 if (sc->ifp != NULL) { 16118 ether_ifdetach(sc->ifp); 16119 } 16120 ifmedia_removeall(&sc->ifmedia); 16121 bxe_release_mutexes(sc); 16122 bxe_deallocate_bars(sc); 16123 pci_disable_busmaster(dev); 16124 return (ENXIO); 16125 } 16126 16127 /* allocate the host hardware/software hsi structures */ 16128 if (bxe_alloc_hsi_mem(sc) != 0) { 16129 bxe_free_ilt_mem(sc); 16130 bxe_free_buf_rings(sc); 16131 bxe_interrupt_free(sc); 16132 bxe_del_cdev(sc); 16133 if (sc->ifp != NULL) { 16134 ether_ifdetach(sc->ifp); 16135 } 16136 ifmedia_removeall(&sc->ifmedia); 16137 bxe_release_mutexes(sc); 16138 bxe_deallocate_bars(sc); 16139 pci_disable_busmaster(dev); 16140 return (ENXIO); 16141 } 16142 16143 /* need to reset chip if UNDI was active */ 16144 if (IS_PF(sc) && !BXE_NOMCP(sc)) { 16145 /* init fw_seq */ 16146 sc->fw_seq = 16147 (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_mb_header) & 16148 DRV_MSG_SEQ_NUMBER_MASK); 16149 BLOGD(sc, DBG_LOAD, "prev unload fw_seq 0x%04x\n", sc->fw_seq); 16150 bxe_prev_unload(sc); 16151 } 16152 16153 #if 1 16154 /* XXX */ 16155 bxe_dcbx_set_state(sc, FALSE, BXE_DCBX_ENABLED_OFF); 16156 #else 16157 if (SHMEM2_HAS(sc, dcbx_lldp_params_offset) && 16158 SHMEM2_HAS(sc, dcbx_lldp_dcbx_stat_offset) && 16159 SHMEM2_RD(sc, dcbx_lldp_params_offset) && 16160 SHMEM2_RD(sc, dcbx_lldp_dcbx_stat_offset)) { 16161 bxe_dcbx_set_state(sc, TRUE, BXE_DCBX_ENABLED_ON_NEG_ON); 16162 bxe_dcbx_init_params(sc); 16163 } else { 16164 bxe_dcbx_set_state(sc, FALSE, BXE_DCBX_ENABLED_OFF); 16165 } 16166 #endif 16167 16168 /* calculate qm_cid_count */ 16169 sc->qm_cid_count = bxe_set_qm_cid_count(sc); 16170 BLOGD(sc, DBG_LOAD, "qm_cid_count=%d\n", sc->qm_cid_count); 16171 16172 sc->max_cos = 1; 16173 bxe_init_multi_cos(sc); 16174 16175 bxe_add_sysctls(sc); 16176 16177 return (0); 16178 } 16179 16180 /* 16181 * Device detach function. 16182 * 16183 * Stops the controller, resets the controller, and releases resources. 16184 * 16185 * Returns: 16186 * 0 = Success, >0 = Failure 16187 */ 16188 static int 16189 bxe_detach(device_t dev) 16190 { 16191 struct bxe_softc *sc; 16192 if_t ifp; 16193 16194 sc = device_get_softc(dev); 16195 16196 BLOGD(sc, DBG_LOAD, "Starting detach...\n"); 16197 16198 ifp = sc->ifp; 16199 if (ifp != NULL && if_vlantrunkinuse(ifp)) { 16200 BLOGE(sc, "Cannot detach while VLANs are in use.\n"); 16201 return(EBUSY); 16202 } 16203 16204 bxe_del_cdev(sc); 16205 16206 /* stop the periodic callout */ 16207 bxe_periodic_stop(sc); 16208 16209 /* stop the chip taskqueue */ 16210 atomic_store_rel_long(&sc->chip_tq_flags, CHIP_TQ_NONE); 16211 if (sc->chip_tq) { 16212 taskqueue_drain(sc->chip_tq, &sc->chip_tq_task); 16213 taskqueue_free(sc->chip_tq); 16214 sc->chip_tq = NULL; 16215 } 16216 16217 /* stop and reset the controller if it was open */ 16218 if (sc->state != BXE_STATE_CLOSED) { 16219 BXE_CORE_LOCK(sc); 16220 bxe_nic_unload(sc, UNLOAD_CLOSE, TRUE); 16221 sc->state = BXE_STATE_DISABLED; 16222 BXE_CORE_UNLOCK(sc); 16223 } 16224 16225 /* release the network interface */ 16226 if (ifp != NULL) { 16227 ether_ifdetach(ifp); 16228 } 16229 ifmedia_removeall(&sc->ifmedia); 16230 16231 /* XXX do the following based on driver state... */ 16232 16233 /* free the host hardware/software hsi structures */ 16234 bxe_free_hsi_mem(sc); 16235 16236 /* free ilt */ 16237 bxe_free_ilt_mem(sc); 16238 16239 bxe_free_buf_rings(sc); 16240 16241 /* release the interrupts */ 16242 bxe_interrupt_free(sc); 16243 16244 /* Release the mutexes*/ 16245 bxe_destroy_fp_mutexs(sc); 16246 bxe_release_mutexes(sc); 16247 16248 16249 /* Release the PCIe BAR mapped memory */ 16250 bxe_deallocate_bars(sc); 16251 16252 /* Release the FreeBSD interface. */ 16253 if (sc->ifp != NULL) { 16254 if_free(sc->ifp); 16255 } 16256 16257 pci_disable_busmaster(dev); 16258 16259 return (0); 16260 } 16261 16262 /* 16263 * Device shutdown function. 16264 * 16265 * Stops and resets the controller. 16266 * 16267 * Returns: 16268 * Nothing 16269 */ 16270 static int 16271 bxe_shutdown(device_t dev) 16272 { 16273 struct bxe_softc *sc; 16274 16275 sc = device_get_softc(dev); 16276 16277 BLOGD(sc, DBG_LOAD, "Starting shutdown...\n"); 16278 16279 /* stop the periodic callout */ 16280 bxe_periodic_stop(sc); 16281 16282 BXE_CORE_LOCK(sc); 16283 bxe_nic_unload(sc, UNLOAD_NORMAL, FALSE); 16284 BXE_CORE_UNLOCK(sc); 16285 16286 return (0); 16287 } 16288 16289 void 16290 bxe_igu_ack_sb(struct bxe_softc *sc, 16291 uint8_t igu_sb_id, 16292 uint8_t segment, 16293 uint16_t index, 16294 uint8_t op, 16295 uint8_t update) 16296 { 16297 uint32_t igu_addr = sc->igu_base_addr; 16298 igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8; 16299 bxe_igu_ack_sb_gen(sc, igu_sb_id, segment, index, op, update, igu_addr); 16300 } 16301 16302 static void 16303 bxe_igu_clear_sb_gen(struct bxe_softc *sc, 16304 uint8_t func, 16305 uint8_t idu_sb_id, 16306 uint8_t is_pf) 16307 { 16308 uint32_t data, ctl, cnt = 100; 16309 uint32_t igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA; 16310 uint32_t igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL; 16311 uint32_t igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP + (idu_sb_id/32)*4; 16312 uint32_t sb_bit = 1 << (idu_sb_id%32); 16313 uint32_t func_encode = func | (is_pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT; 16314 uint32_t addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id; 16315 16316 /* Not supported in BC mode */ 16317 if (CHIP_INT_MODE_IS_BC(sc)) { 16318 return; 16319 } 16320 16321 data = ((IGU_USE_REGISTER_cstorm_type_0_sb_cleanup << 16322 IGU_REGULAR_CLEANUP_TYPE_SHIFT) | 16323 IGU_REGULAR_CLEANUP_SET | 16324 IGU_REGULAR_BCLEANUP); 16325 16326 ctl = ((addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT) | 16327 (func_encode << IGU_CTRL_REG_FID_SHIFT) | 16328 (IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT)); 16329 16330 BLOGD(sc, DBG_LOAD, "write 0x%08x to IGU(via GRC) addr 0x%x\n", 16331 data, igu_addr_data); 16332 REG_WR(sc, igu_addr_data, data); 16333 16334 bus_space_barrier(sc->bar[BAR0].tag, sc->bar[BAR0].handle, 0, 0, 16335 BUS_SPACE_BARRIER_WRITE); 16336 mb(); 16337 16338 BLOGD(sc, DBG_LOAD, "write 0x%08x to IGU(via GRC) addr 0x%x\n", 16339 ctl, igu_addr_ctl); 16340 REG_WR(sc, igu_addr_ctl, ctl); 16341 16342 bus_space_barrier(sc->bar[BAR0].tag, sc->bar[BAR0].handle, 0, 0, 16343 BUS_SPACE_BARRIER_WRITE); 16344 mb(); 16345 16346 /* wait for clean up to finish */ 16347 while (!(REG_RD(sc, igu_addr_ack) & sb_bit) && --cnt) { 16348 DELAY(20000); 16349 } 16350 16351 if (!(REG_RD(sc, igu_addr_ack) & sb_bit)) { 16352 BLOGD(sc, DBG_LOAD, 16353 "Unable to finish IGU cleanup: " 16354 "idu_sb_id %d offset %d bit %d (cnt %d)\n", 16355 idu_sb_id, idu_sb_id/32, idu_sb_id%32, cnt); 16356 } 16357 } 16358 16359 static void 16360 bxe_igu_clear_sb(struct bxe_softc *sc, 16361 uint8_t idu_sb_id) 16362 { 16363 bxe_igu_clear_sb_gen(sc, SC_FUNC(sc), idu_sb_id, TRUE /*PF*/); 16364 } 16365 16366 16367 16368 16369 16370 16371 16372 /*******************/ 16373 /* ECORE CALLBACKS */ 16374 /*******************/ 16375 16376 static void 16377 bxe_reset_common(struct bxe_softc *sc) 16378 { 16379 uint32_t val = 0x1400; 16380 16381 /* reset_common */ 16382 REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR), 0xd3ffff7f); 16383 16384 if (CHIP_IS_E3(sc)) { 16385 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0; 16386 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1; 16387 } 16388 16389 REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR), val); 16390 } 16391 16392 static void 16393 bxe_common_init_phy(struct bxe_softc *sc) 16394 { 16395 uint32_t shmem_base[2]; 16396 uint32_t shmem2_base[2]; 16397 16398 /* Avoid common init in case MFW supports LFA */ 16399 if (SHMEM2_RD(sc, size) > 16400 (uint32_t)offsetof(struct shmem2_region, 16401 lfa_host_addr[SC_PORT(sc)])) { 16402 return; 16403 } 16404 16405 shmem_base[0] = sc->devinfo.shmem_base; 16406 shmem2_base[0] = sc->devinfo.shmem2_base; 16407 16408 if (!CHIP_IS_E1x(sc)) { 16409 shmem_base[1] = SHMEM2_RD(sc, other_shmem_base_addr); 16410 shmem2_base[1] = SHMEM2_RD(sc, other_shmem2_base_addr); 16411 } 16412 16413 bxe_acquire_phy_lock(sc); 16414 elink_common_init_phy(sc, shmem_base, shmem2_base, 16415 sc->devinfo.chip_id, 0); 16416 bxe_release_phy_lock(sc); 16417 } 16418 16419 static void 16420 bxe_pf_disable(struct bxe_softc *sc) 16421 { 16422 uint32_t val = REG_RD(sc, IGU_REG_PF_CONFIGURATION); 16423 16424 val &= ~IGU_PF_CONF_FUNC_EN; 16425 16426 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val); 16427 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0); 16428 REG_WR(sc, CFC_REG_WEAK_ENABLE_PF, 0); 16429 } 16430 16431 static void 16432 bxe_init_pxp(struct bxe_softc *sc) 16433 { 16434 uint16_t devctl; 16435 int r_order, w_order; 16436 16437 devctl = bxe_pcie_capability_read(sc, PCIR_EXPRESS_DEVICE_CTL, 2); 16438 16439 BLOGD(sc, DBG_LOAD, "read 0x%08x from devctl\n", devctl); 16440 16441 w_order = ((devctl & PCIM_EXP_CTL_MAX_PAYLOAD) >> 5); 16442 16443 if (sc->mrrs == -1) { 16444 r_order = ((devctl & PCIM_EXP_CTL_MAX_READ_REQUEST) >> 12); 16445 } else { 16446 BLOGD(sc, DBG_LOAD, "forcing read order to %d\n", sc->mrrs); 16447 r_order = sc->mrrs; 16448 } 16449 16450 ecore_init_pxp_arb(sc, r_order, w_order); 16451 } 16452 16453 static uint32_t 16454 bxe_get_pretend_reg(struct bxe_softc *sc) 16455 { 16456 uint32_t base = PXP2_REG_PGL_PRETEND_FUNC_F0; 16457 uint32_t stride = (PXP2_REG_PGL_PRETEND_FUNC_F1 - base); 16458 return (base + (SC_ABS_FUNC(sc)) * stride); 16459 } 16460 16461 /* 16462 * Called only on E1H or E2. 16463 * When pretending to be PF, the pretend value is the function number 0..7. 16464 * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID 16465 * combination. 16466 */ 16467 static int 16468 bxe_pretend_func(struct bxe_softc *sc, 16469 uint16_t pretend_func_val) 16470 { 16471 uint32_t pretend_reg; 16472 16473 if (CHIP_IS_E1H(sc) && (pretend_func_val > E1H_FUNC_MAX)) { 16474 return (-1); 16475 } 16476 16477 /* get my own pretend register */ 16478 pretend_reg = bxe_get_pretend_reg(sc); 16479 REG_WR(sc, pretend_reg, pretend_func_val); 16480 REG_RD(sc, pretend_reg); 16481 return (0); 16482 } 16483 16484 static void 16485 bxe_iov_init_dmae(struct bxe_softc *sc) 16486 { 16487 return; 16488 } 16489 16490 static void 16491 bxe_iov_init_dq(struct bxe_softc *sc) 16492 { 16493 return; 16494 } 16495 16496 /* send a NIG loopback debug packet */ 16497 static void 16498 bxe_lb_pckt(struct bxe_softc *sc) 16499 { 16500 uint32_t wb_write[3]; 16501 16502 /* Ethernet source and destination addresses */ 16503 wb_write[0] = 0x55555555; 16504 wb_write[1] = 0x55555555; 16505 wb_write[2] = 0x20; /* SOP */ 16506 REG_WR_DMAE(sc, NIG_REG_DEBUG_PACKET_LB, wb_write, 3); 16507 16508 /* NON-IP protocol */ 16509 wb_write[0] = 0x09000000; 16510 wb_write[1] = 0x55555555; 16511 wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */ 16512 REG_WR_DMAE(sc, NIG_REG_DEBUG_PACKET_LB, wb_write, 3); 16513 } 16514 16515 /* 16516 * Some of the internal memories are not directly readable from the driver. 16517 * To test them we send debug packets. 16518 */ 16519 static int 16520 bxe_int_mem_test(struct bxe_softc *sc) 16521 { 16522 int factor; 16523 int count, i; 16524 uint32_t val = 0; 16525 16526 if (CHIP_REV_IS_FPGA(sc)) { 16527 factor = 120; 16528 } else if (CHIP_REV_IS_EMUL(sc)) { 16529 factor = 200; 16530 } else { 16531 factor = 1; 16532 } 16533 16534 /* disable inputs of parser neighbor blocks */ 16535 REG_WR(sc, TSDM_REG_ENABLE_IN1, 0x0); 16536 REG_WR(sc, TCM_REG_PRS_IFEN, 0x0); 16537 REG_WR(sc, CFC_REG_DEBUG0, 0x1); 16538 REG_WR(sc, NIG_REG_PRS_REQ_IN_EN, 0x0); 16539 16540 /* write 0 to parser credits for CFC search request */ 16541 REG_WR(sc, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0); 16542 16543 /* send Ethernet packet */ 16544 bxe_lb_pckt(sc); 16545 16546 /* TODO do i reset NIG statistic? */ 16547 /* Wait until NIG register shows 1 packet of size 0x10 */ 16548 count = 1000 * factor; 16549 while (count) { 16550 bxe_read_dmae(sc, NIG_REG_STAT2_BRB_OCTET, 2); 16551 val = *BXE_SP(sc, wb_data[0]); 16552 if (val == 0x10) { 16553 break; 16554 } 16555 16556 DELAY(10000); 16557 count--; 16558 } 16559 16560 if (val != 0x10) { 16561 BLOGE(sc, "NIG timeout val=0x%x\n", val); 16562 return (-1); 16563 } 16564 16565 /* wait until PRS register shows 1 packet */ 16566 count = (1000 * factor); 16567 while (count) { 16568 val = REG_RD(sc, PRS_REG_NUM_OF_PACKETS); 16569 if (val == 1) { 16570 break; 16571 } 16572 16573 DELAY(10000); 16574 count--; 16575 } 16576 16577 if (val != 0x1) { 16578 BLOGE(sc, "PRS timeout val=0x%x\n", val); 16579 return (-2); 16580 } 16581 16582 /* Reset and init BRB, PRS */ 16583 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03); 16584 DELAY(50000); 16585 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03); 16586 DELAY(50000); 16587 ecore_init_block(sc, BLOCK_BRB1, PHASE_COMMON); 16588 ecore_init_block(sc, BLOCK_PRS, PHASE_COMMON); 16589 16590 /* Disable inputs of parser neighbor blocks */ 16591 REG_WR(sc, TSDM_REG_ENABLE_IN1, 0x0); 16592 REG_WR(sc, TCM_REG_PRS_IFEN, 0x0); 16593 REG_WR(sc, CFC_REG_DEBUG0, 0x1); 16594 REG_WR(sc, NIG_REG_PRS_REQ_IN_EN, 0x0); 16595 16596 /* Write 0 to parser credits for CFC search request */ 16597 REG_WR(sc, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0); 16598 16599 /* send 10 Ethernet packets */ 16600 for (i = 0; i < 10; i++) { 16601 bxe_lb_pckt(sc); 16602 } 16603 16604 /* Wait until NIG register shows 10+1 packets of size 11*0x10 = 0xb0 */ 16605 count = (1000 * factor); 16606 while (count) { 16607 bxe_read_dmae(sc, NIG_REG_STAT2_BRB_OCTET, 2); 16608 val = *BXE_SP(sc, wb_data[0]); 16609 if (val == 0xb0) { 16610 break; 16611 } 16612 16613 DELAY(10000); 16614 count--; 16615 } 16616 16617 if (val != 0xb0) { 16618 BLOGE(sc, "NIG timeout val=0x%x\n", val); 16619 return (-3); 16620 } 16621 16622 /* Wait until PRS register shows 2 packets */ 16623 val = REG_RD(sc, PRS_REG_NUM_OF_PACKETS); 16624 if (val != 2) { 16625 BLOGE(sc, "PRS timeout val=0x%x\n", val); 16626 } 16627 16628 /* Write 1 to parser credits for CFC search request */ 16629 REG_WR(sc, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1); 16630 16631 /* Wait until PRS register shows 3 packets */ 16632 DELAY(10000 * factor); 16633 16634 /* Wait until NIG register shows 1 packet of size 0x10 */ 16635 val = REG_RD(sc, PRS_REG_NUM_OF_PACKETS); 16636 if (val != 3) { 16637 BLOGE(sc, "PRS timeout val=0x%x\n", val); 16638 } 16639 16640 /* clear NIG EOP FIFO */ 16641 for (i = 0; i < 11; i++) { 16642 REG_RD(sc, NIG_REG_INGRESS_EOP_LB_FIFO); 16643 } 16644 16645 val = REG_RD(sc, NIG_REG_INGRESS_EOP_LB_EMPTY); 16646 if (val != 1) { 16647 BLOGE(sc, "clear of NIG failed val=0x%x\n", val); 16648 return (-4); 16649 } 16650 16651 /* Reset and init BRB, PRS, NIG */ 16652 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03); 16653 DELAY(50000); 16654 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03); 16655 DELAY(50000); 16656 ecore_init_block(sc, BLOCK_BRB1, PHASE_COMMON); 16657 ecore_init_block(sc, BLOCK_PRS, PHASE_COMMON); 16658 if (!CNIC_SUPPORT(sc)) { 16659 /* set NIC mode */ 16660 REG_WR(sc, PRS_REG_NIC_MODE, 1); 16661 } 16662 16663 /* Enable inputs of parser neighbor blocks */ 16664 REG_WR(sc, TSDM_REG_ENABLE_IN1, 0x7fffffff); 16665 REG_WR(sc, TCM_REG_PRS_IFEN, 0x1); 16666 REG_WR(sc, CFC_REG_DEBUG0, 0x0); 16667 REG_WR(sc, NIG_REG_PRS_REQ_IN_EN, 0x1); 16668 16669 return (0); 16670 } 16671 16672 static void 16673 bxe_setup_fan_failure_detection(struct bxe_softc *sc) 16674 { 16675 int is_required; 16676 uint32_t val; 16677 int port; 16678 16679 is_required = 0; 16680 val = (SHMEM_RD(sc, dev_info.shared_hw_config.config2) & 16681 SHARED_HW_CFG_FAN_FAILURE_MASK); 16682 16683 if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED) { 16684 is_required = 1; 16685 } 16686 /* 16687 * The fan failure mechanism is usually related to the PHY type since 16688 * the power consumption of the board is affected by the PHY. Currently, 16689 * fan is required for most designs with SFX7101, BCM8727 and BCM8481. 16690 */ 16691 else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE) { 16692 for (port = PORT_0; port < PORT_MAX; port++) { 16693 is_required |= elink_fan_failure_det_req(sc, 16694 sc->devinfo.shmem_base, 16695 sc->devinfo.shmem2_base, 16696 port); 16697 } 16698 } 16699 16700 BLOGD(sc, DBG_LOAD, "fan detection setting: %d\n", is_required); 16701 16702 if (is_required == 0) { 16703 return; 16704 } 16705 16706 /* Fan failure is indicated by SPIO 5 */ 16707 bxe_set_spio(sc, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z); 16708 16709 /* set to active low mode */ 16710 val = REG_RD(sc, MISC_REG_SPIO_INT); 16711 val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS); 16712 REG_WR(sc, MISC_REG_SPIO_INT, val); 16713 16714 /* enable interrupt to signal the IGU */ 16715 val = REG_RD(sc, MISC_REG_SPIO_EVENT_EN); 16716 val |= MISC_SPIO_SPIO5; 16717 REG_WR(sc, MISC_REG_SPIO_EVENT_EN, val); 16718 } 16719 16720 static void 16721 bxe_enable_blocks_attention(struct bxe_softc *sc) 16722 { 16723 uint32_t val; 16724 16725 REG_WR(sc, PXP_REG_PXP_INT_MASK_0, 0); 16726 if (!CHIP_IS_E1x(sc)) { 16727 REG_WR(sc, PXP_REG_PXP_INT_MASK_1, 0x40); 16728 } else { 16729 REG_WR(sc, PXP_REG_PXP_INT_MASK_1, 0); 16730 } 16731 REG_WR(sc, DORQ_REG_DORQ_INT_MASK, 0); 16732 REG_WR(sc, CFC_REG_CFC_INT_MASK, 0); 16733 /* 16734 * mask read length error interrupts in brb for parser 16735 * (parsing unit and 'checksum and crc' unit) 16736 * these errors are legal (PU reads fixed length and CAC can cause 16737 * read length error on truncated packets) 16738 */ 16739 REG_WR(sc, BRB1_REG_BRB1_INT_MASK, 0xFC00); 16740 REG_WR(sc, QM_REG_QM_INT_MASK, 0); 16741 REG_WR(sc, TM_REG_TM_INT_MASK, 0); 16742 REG_WR(sc, XSDM_REG_XSDM_INT_MASK_0, 0); 16743 REG_WR(sc, XSDM_REG_XSDM_INT_MASK_1, 0); 16744 REG_WR(sc, XCM_REG_XCM_INT_MASK, 0); 16745 /* REG_WR(sc, XSEM_REG_XSEM_INT_MASK_0, 0); */ 16746 /* REG_WR(sc, XSEM_REG_XSEM_INT_MASK_1, 0); */ 16747 REG_WR(sc, USDM_REG_USDM_INT_MASK_0, 0); 16748 REG_WR(sc, USDM_REG_USDM_INT_MASK_1, 0); 16749 REG_WR(sc, UCM_REG_UCM_INT_MASK, 0); 16750 /* REG_WR(sc, USEM_REG_USEM_INT_MASK_0, 0); */ 16751 /* REG_WR(sc, USEM_REG_USEM_INT_MASK_1, 0); */ 16752 REG_WR(sc, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0); 16753 REG_WR(sc, CSDM_REG_CSDM_INT_MASK_0, 0); 16754 REG_WR(sc, CSDM_REG_CSDM_INT_MASK_1, 0); 16755 REG_WR(sc, CCM_REG_CCM_INT_MASK, 0); 16756 /* REG_WR(sc, CSEM_REG_CSEM_INT_MASK_0, 0); */ 16757 /* REG_WR(sc, CSEM_REG_CSEM_INT_MASK_1, 0); */ 16758 16759 val = (PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT | 16760 PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF | 16761 PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN); 16762 if (!CHIP_IS_E1x(sc)) { 16763 val |= (PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED | 16764 PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED); 16765 } 16766 REG_WR(sc, PXP2_REG_PXP2_INT_MASK_0, val); 16767 16768 REG_WR(sc, TSDM_REG_TSDM_INT_MASK_0, 0); 16769 REG_WR(sc, TSDM_REG_TSDM_INT_MASK_1, 0); 16770 REG_WR(sc, TCM_REG_TCM_INT_MASK, 0); 16771 /* REG_WR(sc, TSEM_REG_TSEM_INT_MASK_0, 0); */ 16772 16773 if (!CHIP_IS_E1x(sc)) { 16774 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */ 16775 REG_WR(sc, TSEM_REG_TSEM_INT_MASK_1, 0x07ff); 16776 } 16777 16778 REG_WR(sc, CDU_REG_CDU_INT_MASK, 0); 16779 REG_WR(sc, DMAE_REG_DMAE_INT_MASK, 0); 16780 /* REG_WR(sc, MISC_REG_MISC_INT_MASK, 0); */ 16781 REG_WR(sc, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */ 16782 } 16783 16784 /** 16785 * bxe_init_hw_common - initialize the HW at the COMMON phase. 16786 * 16787 * @sc: driver handle 16788 */ 16789 static int 16790 bxe_init_hw_common(struct bxe_softc *sc) 16791 { 16792 uint8_t abs_func_id; 16793 uint32_t val; 16794 16795 BLOGD(sc, DBG_LOAD, "starting common init for func %d\n", 16796 SC_ABS_FUNC(sc)); 16797 16798 /* 16799 * take the RESET lock to protect undi_unload flow from accessing 16800 * registers while we are resetting the chip 16801 */ 16802 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RESET); 16803 16804 bxe_reset_common(sc); 16805 16806 REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET), 0xffffffff); 16807 16808 val = 0xfffc; 16809 if (CHIP_IS_E3(sc)) { 16810 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0; 16811 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1; 16812 } 16813 16814 REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET), val); 16815 16816 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET); 16817 16818 ecore_init_block(sc, BLOCK_MISC, PHASE_COMMON); 16819 BLOGD(sc, DBG_LOAD, "after misc block init\n"); 16820 16821 if (!CHIP_IS_E1x(sc)) { 16822 /* 16823 * 4-port mode or 2-port mode we need to turn off master-enable for 16824 * everyone. After that we turn it back on for self. So, we disregard 16825 * multi-function, and always disable all functions on the given path, 16826 * this means 0,2,4,6 for path 0 and 1,3,5,7 for path 1 16827 */ 16828 for (abs_func_id = SC_PATH(sc); 16829 abs_func_id < (E2_FUNC_MAX * 2); 16830 abs_func_id += 2) { 16831 if (abs_func_id == SC_ABS_FUNC(sc)) { 16832 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); 16833 continue; 16834 } 16835 16836 bxe_pretend_func(sc, abs_func_id); 16837 16838 /* clear pf enable */ 16839 bxe_pf_disable(sc); 16840 16841 bxe_pretend_func(sc, SC_ABS_FUNC(sc)); 16842 } 16843 } 16844 16845 BLOGD(sc, DBG_LOAD, "after pf disable\n"); 16846 16847 ecore_init_block(sc, BLOCK_PXP, PHASE_COMMON); 16848 16849 if (CHIP_IS_E1(sc)) { 16850 /* 16851 * enable HW interrupt from PXP on USDM overflow 16852 * bit 16 on INT_MASK_0 16853 */ 16854 REG_WR(sc, PXP_REG_PXP_INT_MASK_0, 0); 16855 } 16856 16857 ecore_init_block(sc, BLOCK_PXP2, PHASE_COMMON); 16858 bxe_init_pxp(sc); 16859 16860 #ifdef __BIG_ENDIAN 16861 REG_WR(sc, PXP2_REG_RQ_QM_ENDIAN_M, 1); 16862 REG_WR(sc, PXP2_REG_RQ_TM_ENDIAN_M, 1); 16863 REG_WR(sc, PXP2_REG_RQ_SRC_ENDIAN_M, 1); 16864 REG_WR(sc, PXP2_REG_RQ_CDU_ENDIAN_M, 1); 16865 REG_WR(sc, PXP2_REG_RQ_DBG_ENDIAN_M, 1); 16866 /* make sure this value is 0 */ 16867 REG_WR(sc, PXP2_REG_RQ_HC_ENDIAN_M, 0); 16868 16869 //REG_WR(sc, PXP2_REG_RD_PBF_SWAP_MODE, 1); 16870 REG_WR(sc, PXP2_REG_RD_QM_SWAP_MODE, 1); 16871 REG_WR(sc, PXP2_REG_RD_TM_SWAP_MODE, 1); 16872 REG_WR(sc, PXP2_REG_RD_SRC_SWAP_MODE, 1); 16873 REG_WR(sc, PXP2_REG_RD_CDURD_SWAP_MODE, 1); 16874 #endif 16875 16876 ecore_ilt_init_page_size(sc, INITOP_SET); 16877 16878 if (CHIP_REV_IS_FPGA(sc) && CHIP_IS_E1H(sc)) { 16879 REG_WR(sc, PXP2_REG_PGL_TAGS_LIMIT, 0x1); 16880 } 16881 16882 /* let the HW do it's magic... */ 16883 DELAY(100000); 16884 16885 /* finish PXP init */ 16886 val = REG_RD(sc, PXP2_REG_RQ_CFG_DONE); 16887 if (val != 1) { 16888 BLOGE(sc, "PXP2 CFG failed PXP2_REG_RQ_CFG_DONE val = 0x%x\n", 16889 val); 16890 return (-1); 16891 } 16892 val = REG_RD(sc, PXP2_REG_RD_INIT_DONE); 16893 if (val != 1) { 16894 BLOGE(sc, "PXP2 RD_INIT failed val = 0x%x\n", val); 16895 return (-1); 16896 } 16897 16898 BLOGD(sc, DBG_LOAD, "after pxp init\n"); 16899 16900 /* 16901 * Timer bug workaround for E2 only. We need to set the entire ILT to have 16902 * entries with value "0" and valid bit on. This needs to be done by the 16903 * first PF that is loaded in a path (i.e. common phase) 16904 */ 16905 if (!CHIP_IS_E1x(sc)) { 16906 /* 16907 * In E2 there is a bug in the timers block that can cause function 6 / 7 16908 * (i.e. vnic3) to start even if it is marked as "scan-off". 16909 * This occurs when a different function (func2,3) is being marked 16910 * as "scan-off". Real-life scenario for example: if a driver is being 16911 * load-unloaded while func6,7 are down. This will cause the timer to access 16912 * the ilt, translate to a logical address and send a request to read/write. 16913 * Since the ilt for the function that is down is not valid, this will cause 16914 * a translation error which is unrecoverable. 16915 * The Workaround is intended to make sure that when this happens nothing 16916 * fatal will occur. The workaround: 16917 * 1. First PF driver which loads on a path will: 16918 * a. After taking the chip out of reset, by using pretend, 16919 * it will write "0" to the following registers of 16920 * the other vnics. 16921 * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0); 16922 * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0); 16923 * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0); 16924 * And for itself it will write '1' to 16925 * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable 16926 * dmae-operations (writing to pram for example.) 16927 * note: can be done for only function 6,7 but cleaner this 16928 * way. 16929 * b. Write zero+valid to the entire ILT. 16930 * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of 16931 * VNIC3 (of that port). The range allocated will be the 16932 * entire ILT. This is needed to prevent ILT range error. 16933 * 2. Any PF driver load flow: 16934 * a. ILT update with the physical addresses of the allocated 16935 * logical pages. 16936 * b. Wait 20msec. - note that this timeout is needed to make 16937 * sure there are no requests in one of the PXP internal 16938 * queues with "old" ILT addresses. 16939 * c. PF enable in the PGLC. 16940 * d. Clear the was_error of the PF in the PGLC. (could have 16941 * occurred while driver was down) 16942 * e. PF enable in the CFC (WEAK + STRONG) 16943 * f. Timers scan enable 16944 * 3. PF driver unload flow: 16945 * a. Clear the Timers scan_en. 16946 * b. Polling for scan_on=0 for that PF. 16947 * c. Clear the PF enable bit in the PXP. 16948 * d. Clear the PF enable in the CFC (WEAK + STRONG) 16949 * e. Write zero+valid to all ILT entries (The valid bit must 16950 * stay set) 16951 * f. If this is VNIC 3 of a port then also init 16952 * first_timers_ilt_entry to zero and last_timers_ilt_entry 16953 * to the last enrty in the ILT. 16954 * 16955 * Notes: 16956 * Currently the PF error in the PGLC is non recoverable. 16957 * In the future the there will be a recovery routine for this error. 16958 * Currently attention is masked. 16959 * Having an MCP lock on the load/unload process does not guarantee that 16960 * there is no Timer disable during Func6/7 enable. This is because the 16961 * Timers scan is currently being cleared by the MCP on FLR. 16962 * Step 2.d can be done only for PF6/7 and the driver can also check if 16963 * there is error before clearing it. But the flow above is simpler and 16964 * more general. 16965 * All ILT entries are written by zero+valid and not just PF6/7 16966 * ILT entries since in the future the ILT entries allocation for 16967 * PF-s might be dynamic. 16968 */ 16969 struct ilt_client_info ilt_cli; 16970 struct ecore_ilt ilt; 16971 16972 memset(&ilt_cli, 0, sizeof(struct ilt_client_info)); 16973 memset(&ilt, 0, sizeof(struct ecore_ilt)); 16974 16975 /* initialize dummy TM client */ 16976 ilt_cli.start = 0; 16977 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1; 16978 ilt_cli.client_num = ILT_CLIENT_TM; 16979 16980 /* 16981 * Step 1: set zeroes to all ilt page entries with valid bit on 16982 * Step 2: set the timers first/last ilt entry to point 16983 * to the entire range to prevent ILT range error for 3rd/4th 16984 * vnic (this code assumes existence of the vnic) 16985 * 16986 * both steps performed by call to ecore_ilt_client_init_op() 16987 * with dummy TM client 16988 * 16989 * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT 16990 * and his brother are split registers 16991 */ 16992 16993 bxe_pretend_func(sc, (SC_PATH(sc) + 6)); 16994 ecore_ilt_client_init_op_ilt(sc, &ilt, &ilt_cli, INITOP_CLEAR); 16995 bxe_pretend_func(sc, SC_ABS_FUNC(sc)); 16996 16997 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN, BXE_PXP_DRAM_ALIGN); 16998 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN_RD, BXE_PXP_DRAM_ALIGN); 16999 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1); 17000 } 17001 17002 REG_WR(sc, PXP2_REG_RQ_DISABLE_INPUTS, 0); 17003 REG_WR(sc, PXP2_REG_RD_DISABLE_INPUTS, 0); 17004 17005 if (!CHIP_IS_E1x(sc)) { 17006 int factor = CHIP_REV_IS_EMUL(sc) ? 1000 : 17007 (CHIP_REV_IS_FPGA(sc) ? 400 : 0); 17008 17009 ecore_init_block(sc, BLOCK_PGLUE_B, PHASE_COMMON); 17010 ecore_init_block(sc, BLOCK_ATC, PHASE_COMMON); 17011 17012 /* let the HW do it's magic... */ 17013 do { 17014 DELAY(200000); 17015 val = REG_RD(sc, ATC_REG_ATC_INIT_DONE); 17016 } while (factor-- && (val != 1)); 17017 17018 if (val != 1) { 17019 BLOGE(sc, "ATC_INIT failed val = 0x%x\n", val); 17020 return (-1); 17021 } 17022 } 17023 17024 BLOGD(sc, DBG_LOAD, "after pglue and atc init\n"); 17025 17026 ecore_init_block(sc, BLOCK_DMAE, PHASE_COMMON); 17027 17028 bxe_iov_init_dmae(sc); 17029 17030 /* clean the DMAE memory */ 17031 sc->dmae_ready = 1; 17032 ecore_init_fill(sc, TSEM_REG_PRAM, 0, 8, 1); 17033 17034 ecore_init_block(sc, BLOCK_TCM, PHASE_COMMON); 17035 17036 ecore_init_block(sc, BLOCK_UCM, PHASE_COMMON); 17037 17038 ecore_init_block(sc, BLOCK_CCM, PHASE_COMMON); 17039 17040 ecore_init_block(sc, BLOCK_XCM, PHASE_COMMON); 17041 17042 bxe_read_dmae(sc, XSEM_REG_PASSIVE_BUFFER, 3); 17043 bxe_read_dmae(sc, CSEM_REG_PASSIVE_BUFFER, 3); 17044 bxe_read_dmae(sc, TSEM_REG_PASSIVE_BUFFER, 3); 17045 bxe_read_dmae(sc, USEM_REG_PASSIVE_BUFFER, 3); 17046 17047 ecore_init_block(sc, BLOCK_QM, PHASE_COMMON); 17048 17049 /* QM queues pointers table */ 17050 ecore_qm_init_ptr_table(sc, sc->qm_cid_count, INITOP_SET); 17051 17052 /* soft reset pulse */ 17053 REG_WR(sc, QM_REG_SOFT_RESET, 1); 17054 REG_WR(sc, QM_REG_SOFT_RESET, 0); 17055 17056 if (CNIC_SUPPORT(sc)) 17057 ecore_init_block(sc, BLOCK_TM, PHASE_COMMON); 17058 17059 ecore_init_block(sc, BLOCK_DORQ, PHASE_COMMON); 17060 REG_WR(sc, DORQ_REG_DPM_CID_OFST, BXE_DB_SHIFT); 17061 if (!CHIP_REV_IS_SLOW(sc)) { 17062 /* enable hw interrupt from doorbell Q */ 17063 REG_WR(sc, DORQ_REG_DORQ_INT_MASK, 0); 17064 } 17065 17066 ecore_init_block(sc, BLOCK_BRB1, PHASE_COMMON); 17067 17068 ecore_init_block(sc, BLOCK_PRS, PHASE_COMMON); 17069 REG_WR(sc, PRS_REG_A_PRSU_20, 0xf); 17070 17071 if (!CHIP_IS_E1(sc)) { 17072 REG_WR(sc, PRS_REG_E1HOV_MODE, sc->devinfo.mf_info.path_has_ovlan); 17073 } 17074 17075 if (!CHIP_IS_E1x(sc) && !CHIP_IS_E3B0(sc)) { 17076 if (IS_MF_AFEX(sc)) { 17077 /* 17078 * configure that AFEX and VLAN headers must be 17079 * received in AFEX mode 17080 */ 17081 REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC, 0xE); 17082 REG_WR(sc, PRS_REG_MUST_HAVE_HDRS, 0xA); 17083 REG_WR(sc, PRS_REG_HDRS_AFTER_TAG_0, 0x6); 17084 REG_WR(sc, PRS_REG_TAG_ETHERTYPE_0, 0x8926); 17085 REG_WR(sc, PRS_REG_TAG_LEN_0, 0x4); 17086 } else { 17087 /* 17088 * Bit-map indicating which L2 hdrs may appear 17089 * after the basic Ethernet header 17090 */ 17091 REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC, 17092 sc->devinfo.mf_info.path_has_ovlan ? 7 : 6); 17093 } 17094 } 17095 17096 ecore_init_block(sc, BLOCK_TSDM, PHASE_COMMON); 17097 ecore_init_block(sc, BLOCK_CSDM, PHASE_COMMON); 17098 ecore_init_block(sc, BLOCK_USDM, PHASE_COMMON); 17099 ecore_init_block(sc, BLOCK_XSDM, PHASE_COMMON); 17100 17101 if (!CHIP_IS_E1x(sc)) { 17102 /* reset VFC memories */ 17103 REG_WR(sc, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST, 17104 VFC_MEMORIES_RST_REG_CAM_RST | 17105 VFC_MEMORIES_RST_REG_RAM_RST); 17106 REG_WR(sc, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST, 17107 VFC_MEMORIES_RST_REG_CAM_RST | 17108 VFC_MEMORIES_RST_REG_RAM_RST); 17109 17110 DELAY(20000); 17111 } 17112 17113 ecore_init_block(sc, BLOCK_TSEM, PHASE_COMMON); 17114 ecore_init_block(sc, BLOCK_USEM, PHASE_COMMON); 17115 ecore_init_block(sc, BLOCK_CSEM, PHASE_COMMON); 17116 ecore_init_block(sc, BLOCK_XSEM, PHASE_COMMON); 17117 17118 /* sync semi rtc */ 17119 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 17120 0x80000000); 17121 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 17122 0x80000000); 17123 17124 ecore_init_block(sc, BLOCK_UPB, PHASE_COMMON); 17125 ecore_init_block(sc, BLOCK_XPB, PHASE_COMMON); 17126 ecore_init_block(sc, BLOCK_PBF, PHASE_COMMON); 17127 17128 if (!CHIP_IS_E1x(sc)) { 17129 if (IS_MF_AFEX(sc)) { 17130 /* 17131 * configure that AFEX and VLAN headers must be 17132 * sent in AFEX mode 17133 */ 17134 REG_WR(sc, PBF_REG_HDRS_AFTER_BASIC, 0xE); 17135 REG_WR(sc, PBF_REG_MUST_HAVE_HDRS, 0xA); 17136 REG_WR(sc, PBF_REG_HDRS_AFTER_TAG_0, 0x6); 17137 REG_WR(sc, PBF_REG_TAG_ETHERTYPE_0, 0x8926); 17138 REG_WR(sc, PBF_REG_TAG_LEN_0, 0x4); 17139 } else { 17140 REG_WR(sc, PBF_REG_HDRS_AFTER_BASIC, 17141 sc->devinfo.mf_info.path_has_ovlan ? 7 : 6); 17142 } 17143 } 17144 17145 REG_WR(sc, SRC_REG_SOFT_RST, 1); 17146 17147 ecore_init_block(sc, BLOCK_SRC, PHASE_COMMON); 17148 17149 if (CNIC_SUPPORT(sc)) { 17150 REG_WR(sc, SRC_REG_KEYSEARCH_0, 0x63285672); 17151 REG_WR(sc, SRC_REG_KEYSEARCH_1, 0x24b8f2cc); 17152 REG_WR(sc, SRC_REG_KEYSEARCH_2, 0x223aef9b); 17153 REG_WR(sc, SRC_REG_KEYSEARCH_3, 0x26001e3a); 17154 REG_WR(sc, SRC_REG_KEYSEARCH_4, 0x7ae91116); 17155 REG_WR(sc, SRC_REG_KEYSEARCH_5, 0x5ce5230b); 17156 REG_WR(sc, SRC_REG_KEYSEARCH_6, 0x298d8adf); 17157 REG_WR(sc, SRC_REG_KEYSEARCH_7, 0x6eb0ff09); 17158 REG_WR(sc, SRC_REG_KEYSEARCH_8, 0x1830f82f); 17159 REG_WR(sc, SRC_REG_KEYSEARCH_9, 0x01e46be7); 17160 } 17161 REG_WR(sc, SRC_REG_SOFT_RST, 0); 17162 17163 if (sizeof(union cdu_context) != 1024) { 17164 /* we currently assume that a context is 1024 bytes */ 17165 BLOGE(sc, "please adjust the size of cdu_context(%ld)\n", 17166 (long)sizeof(union cdu_context)); 17167 } 17168 17169 ecore_init_block(sc, BLOCK_CDU, PHASE_COMMON); 17170 val = (4 << 24) + (0 << 12) + 1024; 17171 REG_WR(sc, CDU_REG_CDU_GLOBAL_PARAMS, val); 17172 17173 ecore_init_block(sc, BLOCK_CFC, PHASE_COMMON); 17174 17175 REG_WR(sc, CFC_REG_INIT_REG, 0x7FF); 17176 /* enable context validation interrupt from CFC */ 17177 REG_WR(sc, CFC_REG_CFC_INT_MASK, 0); 17178 17179 /* set the thresholds to prevent CFC/CDU race */ 17180 REG_WR(sc, CFC_REG_DEBUG0, 0x20020000); 17181 ecore_init_block(sc, BLOCK_HC, PHASE_COMMON); 17182 17183 if (!CHIP_IS_E1x(sc) && BXE_NOMCP(sc)) { 17184 REG_WR(sc, IGU_REG_RESET_MEMORIES, 0x36); 17185 } 17186 17187 ecore_init_block(sc, BLOCK_IGU, PHASE_COMMON); 17188 ecore_init_block(sc, BLOCK_MISC_AEU, PHASE_COMMON); 17189 17190 /* Reset PCIE errors for debug */ 17191 REG_WR(sc, 0x2814, 0xffffffff); 17192 REG_WR(sc, 0x3820, 0xffffffff); 17193 17194 if (!CHIP_IS_E1x(sc)) { 17195 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_CONTROL_5, 17196 (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 | 17197 PXPCS_TL_CONTROL_5_ERR_UNSPPORT)); 17198 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT, 17199 (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 | 17200 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 | 17201 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2)); 17202 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT, 17203 (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 | 17204 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 | 17205 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5)); 17206 } 17207 17208 ecore_init_block(sc, BLOCK_NIG, PHASE_COMMON); 17209 17210 if (!CHIP_IS_E1(sc)) { 17211 /* in E3 this done in per-port section */ 17212 if (!CHIP_IS_E3(sc)) 17213 REG_WR(sc, NIG_REG_LLH_MF_MODE, IS_MF(sc)); 17214 } 17215 17216 if (CHIP_IS_E1H(sc)) { 17217 /* not applicable for E2 (and above ...) */ 17218 REG_WR(sc, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(sc)); 17219 } 17220 17221 if (CHIP_REV_IS_SLOW(sc)) { 17222 DELAY(200000); 17223 } 17224 17225 /* finish CFC init */ 17226 val = reg_poll(sc, CFC_REG_LL_INIT_DONE, 1, 100, 10); 17227 if (val != 1) { 17228 BLOGE(sc, "CFC LL_INIT failed val=0x%x\n", val); 17229 return (-1); 17230 } 17231 val = reg_poll(sc, CFC_REG_AC_INIT_DONE, 1, 100, 10); 17232 if (val != 1) { 17233 BLOGE(sc, "CFC AC_INIT failed val=0x%x\n", val); 17234 return (-1); 17235 } 17236 val = reg_poll(sc, CFC_REG_CAM_INIT_DONE, 1, 100, 10); 17237 if (val != 1) { 17238 BLOGE(sc, "CFC CAM_INIT failed val=0x%x\n", val); 17239 return (-1); 17240 } 17241 REG_WR(sc, CFC_REG_DEBUG0, 0); 17242 17243 if (CHIP_IS_E1(sc)) { 17244 /* read NIG statistic to see if this is our first up since powerup */ 17245 bxe_read_dmae(sc, NIG_REG_STAT2_BRB_OCTET, 2); 17246 val = *BXE_SP(sc, wb_data[0]); 17247 17248 /* do internal memory self test */ 17249 if ((val == 0) && bxe_int_mem_test(sc)) { 17250 BLOGE(sc, "internal mem self test failed val=0x%x\n", val); 17251 return (-1); 17252 } 17253 } 17254 17255 bxe_setup_fan_failure_detection(sc); 17256 17257 /* clear PXP2 attentions */ 17258 REG_RD(sc, PXP2_REG_PXP2_INT_STS_CLR_0); 17259 17260 bxe_enable_blocks_attention(sc); 17261 17262 if (!CHIP_REV_IS_SLOW(sc)) { 17263 ecore_enable_blocks_parity(sc); 17264 } 17265 17266 if (!BXE_NOMCP(sc)) { 17267 if (CHIP_IS_E1x(sc)) { 17268 bxe_common_init_phy(sc); 17269 } 17270 } 17271 17272 return (0); 17273 } 17274 17275 /** 17276 * bxe_init_hw_common_chip - init HW at the COMMON_CHIP phase. 17277 * 17278 * @sc: driver handle 17279 */ 17280 static int 17281 bxe_init_hw_common_chip(struct bxe_softc *sc) 17282 { 17283 int rc = bxe_init_hw_common(sc); 17284 17285 if (rc) { 17286 BLOGE(sc, "bxe_init_hw_common failed rc=%d\n", rc); 17287 return (rc); 17288 } 17289 17290 /* In E2 2-PORT mode, same ext phy is used for the two paths */ 17291 if (!BXE_NOMCP(sc)) { 17292 bxe_common_init_phy(sc); 17293 } 17294 17295 return (0); 17296 } 17297 17298 static int 17299 bxe_init_hw_port(struct bxe_softc *sc) 17300 { 17301 int port = SC_PORT(sc); 17302 int init_phase = port ? PHASE_PORT1 : PHASE_PORT0; 17303 uint32_t low, high; 17304 uint32_t val; 17305 17306 BLOGD(sc, DBG_LOAD, "starting port init for port %d\n", port); 17307 17308 REG_WR(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0); 17309 17310 ecore_init_block(sc, BLOCK_MISC, init_phase); 17311 ecore_init_block(sc, BLOCK_PXP, init_phase); 17312 ecore_init_block(sc, BLOCK_PXP2, init_phase); 17313 17314 /* 17315 * Timers bug workaround: disables the pf_master bit in pglue at 17316 * common phase, we need to enable it here before any dmae access are 17317 * attempted. Therefore we manually added the enable-master to the 17318 * port phase (it also happens in the function phase) 17319 */ 17320 if (!CHIP_IS_E1x(sc)) { 17321 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); 17322 } 17323 17324 ecore_init_block(sc, BLOCK_ATC, init_phase); 17325 ecore_init_block(sc, BLOCK_DMAE, init_phase); 17326 ecore_init_block(sc, BLOCK_PGLUE_B, init_phase); 17327 ecore_init_block(sc, BLOCK_QM, init_phase); 17328 17329 ecore_init_block(sc, BLOCK_TCM, init_phase); 17330 ecore_init_block(sc, BLOCK_UCM, init_phase); 17331 ecore_init_block(sc, BLOCK_CCM, init_phase); 17332 ecore_init_block(sc, BLOCK_XCM, init_phase); 17333 17334 /* QM cid (connection) count */ 17335 ecore_qm_init_cid_count(sc, sc->qm_cid_count, INITOP_SET); 17336 17337 if (CNIC_SUPPORT(sc)) { 17338 ecore_init_block(sc, BLOCK_TM, init_phase); 17339 REG_WR(sc, TM_REG_LIN0_SCAN_TIME + port*4, 20); 17340 REG_WR(sc, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31); 17341 } 17342 17343 ecore_init_block(sc, BLOCK_DORQ, init_phase); 17344 17345 ecore_init_block(sc, BLOCK_BRB1, init_phase); 17346 17347 if (CHIP_IS_E1(sc) || CHIP_IS_E1H(sc)) { 17348 if (IS_MF(sc)) { 17349 low = (BXE_ONE_PORT(sc) ? 160 : 246); 17350 } else if (sc->mtu > 4096) { 17351 if (BXE_ONE_PORT(sc)) { 17352 low = 160; 17353 } else { 17354 val = sc->mtu; 17355 /* (24*1024 + val*4)/256 */ 17356 low = (96 + (val / 64) + ((val % 64) ? 1 : 0)); 17357 } 17358 } else { 17359 low = (BXE_ONE_PORT(sc) ? 80 : 160); 17360 } 17361 high = (low + 56); /* 14*1024/256 */ 17362 REG_WR(sc, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low); 17363 REG_WR(sc, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high); 17364 } 17365 17366 if (CHIP_IS_MODE_4_PORT(sc)) { 17367 REG_WR(sc, SC_PORT(sc) ? 17368 BRB1_REG_MAC_GUARANTIED_1 : 17369 BRB1_REG_MAC_GUARANTIED_0, 40); 17370 } 17371 17372 ecore_init_block(sc, BLOCK_PRS, init_phase); 17373 if (CHIP_IS_E3B0(sc)) { 17374 if (IS_MF_AFEX(sc)) { 17375 /* configure headers for AFEX mode */ 17376 REG_WR(sc, SC_PORT(sc) ? 17377 PRS_REG_HDRS_AFTER_BASIC_PORT_1 : 17378 PRS_REG_HDRS_AFTER_BASIC_PORT_0, 0xE); 17379 REG_WR(sc, SC_PORT(sc) ? 17380 PRS_REG_HDRS_AFTER_TAG_0_PORT_1 : 17381 PRS_REG_HDRS_AFTER_TAG_0_PORT_0, 0x6); 17382 REG_WR(sc, SC_PORT(sc) ? 17383 PRS_REG_MUST_HAVE_HDRS_PORT_1 : 17384 PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA); 17385 } else { 17386 /* Ovlan exists only if we are in multi-function + 17387 * switch-dependent mode, in switch-independent there 17388 * is no ovlan headers 17389 */ 17390 REG_WR(sc, SC_PORT(sc) ? 17391 PRS_REG_HDRS_AFTER_BASIC_PORT_1 : 17392 PRS_REG_HDRS_AFTER_BASIC_PORT_0, 17393 (sc->devinfo.mf_info.path_has_ovlan ? 7 : 6)); 17394 } 17395 } 17396 17397 ecore_init_block(sc, BLOCK_TSDM, init_phase); 17398 ecore_init_block(sc, BLOCK_CSDM, init_phase); 17399 ecore_init_block(sc, BLOCK_USDM, init_phase); 17400 ecore_init_block(sc, BLOCK_XSDM, init_phase); 17401 17402 ecore_init_block(sc, BLOCK_TSEM, init_phase); 17403 ecore_init_block(sc, BLOCK_USEM, init_phase); 17404 ecore_init_block(sc, BLOCK_CSEM, init_phase); 17405 ecore_init_block(sc, BLOCK_XSEM, init_phase); 17406 17407 ecore_init_block(sc, BLOCK_UPB, init_phase); 17408 ecore_init_block(sc, BLOCK_XPB, init_phase); 17409 17410 ecore_init_block(sc, BLOCK_PBF, init_phase); 17411 17412 if (CHIP_IS_E1x(sc)) { 17413 /* configure PBF to work without PAUSE mtu 9000 */ 17414 REG_WR(sc, PBF_REG_P0_PAUSE_ENABLE + port*4, 0); 17415 17416 /* update threshold */ 17417 REG_WR(sc, PBF_REG_P0_ARB_THRSH + port*4, (9040/16)); 17418 /* update init credit */ 17419 REG_WR(sc, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22); 17420 17421 /* probe changes */ 17422 REG_WR(sc, PBF_REG_INIT_P0 + port*4, 1); 17423 DELAY(50); 17424 REG_WR(sc, PBF_REG_INIT_P0 + port*4, 0); 17425 } 17426 17427 if (CNIC_SUPPORT(sc)) { 17428 ecore_init_block(sc, BLOCK_SRC, init_phase); 17429 } 17430 17431 ecore_init_block(sc, BLOCK_CDU, init_phase); 17432 ecore_init_block(sc, BLOCK_CFC, init_phase); 17433 17434 if (CHIP_IS_E1(sc)) { 17435 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port*8, 0); 17436 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port*8, 0); 17437 } 17438 ecore_init_block(sc, BLOCK_HC, init_phase); 17439 17440 ecore_init_block(sc, BLOCK_IGU, init_phase); 17441 17442 ecore_init_block(sc, BLOCK_MISC_AEU, init_phase); 17443 /* init aeu_mask_attn_func_0/1: 17444 * - SF mode: bits 3-7 are masked. only bits 0-2 are in use 17445 * - MF mode: bit 3 is masked. bits 0-2 are in use as in SF 17446 * bits 4-7 are used for "per vn group attention" */ 17447 val = IS_MF(sc) ? 0xF7 : 0x7; 17448 /* Enable DCBX attention for all but E1 */ 17449 val |= CHIP_IS_E1(sc) ? 0 : 0x10; 17450 REG_WR(sc, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val); 17451 17452 ecore_init_block(sc, BLOCK_NIG, init_phase); 17453 17454 if (!CHIP_IS_E1x(sc)) { 17455 /* Bit-map indicating which L2 hdrs may appear after the 17456 * basic Ethernet header 17457 */ 17458 if (IS_MF_AFEX(sc)) { 17459 REG_WR(sc, SC_PORT(sc) ? 17460 NIG_REG_P1_HDRS_AFTER_BASIC : 17461 NIG_REG_P0_HDRS_AFTER_BASIC, 0xE); 17462 } else { 17463 REG_WR(sc, SC_PORT(sc) ? 17464 NIG_REG_P1_HDRS_AFTER_BASIC : 17465 NIG_REG_P0_HDRS_AFTER_BASIC, 17466 IS_MF_SD(sc) ? 7 : 6); 17467 } 17468 17469 if (CHIP_IS_E3(sc)) { 17470 REG_WR(sc, SC_PORT(sc) ? 17471 NIG_REG_LLH1_MF_MODE : 17472 NIG_REG_LLH_MF_MODE, IS_MF(sc)); 17473 } 17474 } 17475 if (!CHIP_IS_E3(sc)) { 17476 REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1); 17477 } 17478 17479 if (!CHIP_IS_E1(sc)) { 17480 /* 0x2 disable mf_ov, 0x1 enable */ 17481 REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4, 17482 (IS_MF_SD(sc) ? 0x1 : 0x2)); 17483 17484 if (!CHIP_IS_E1x(sc)) { 17485 val = 0; 17486 switch (sc->devinfo.mf_info.mf_mode) { 17487 case MULTI_FUNCTION_SD: 17488 val = 1; 17489 break; 17490 case MULTI_FUNCTION_SI: 17491 case MULTI_FUNCTION_AFEX: 17492 val = 2; 17493 break; 17494 } 17495 17496 REG_WR(sc, (SC_PORT(sc) ? NIG_REG_LLH1_CLS_TYPE : 17497 NIG_REG_LLH0_CLS_TYPE), val); 17498 } 17499 REG_WR(sc, NIG_REG_LLFC_ENABLE_0 + port*4, 0); 17500 REG_WR(sc, NIG_REG_LLFC_OUT_EN_0 + port*4, 0); 17501 REG_WR(sc, NIG_REG_PAUSE_ENABLE_0 + port*4, 1); 17502 } 17503 17504 /* If SPIO5 is set to generate interrupts, enable it for this port */ 17505 val = REG_RD(sc, MISC_REG_SPIO_EVENT_EN); 17506 if (val & MISC_SPIO_SPIO5) { 17507 uint32_t reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : 17508 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); 17509 val = REG_RD(sc, reg_addr); 17510 val |= AEU_INPUTS_ATTN_BITS_SPIO5; 17511 REG_WR(sc, reg_addr, val); 17512 } 17513 17514 return (0); 17515 } 17516 17517 static uint32_t 17518 bxe_flr_clnup_reg_poll(struct bxe_softc *sc, 17519 uint32_t reg, 17520 uint32_t expected, 17521 uint32_t poll_count) 17522 { 17523 uint32_t cur_cnt = poll_count; 17524 uint32_t val; 17525 17526 while ((val = REG_RD(sc, reg)) != expected && cur_cnt--) { 17527 DELAY(FLR_WAIT_INTERVAL); 17528 } 17529 17530 return (val); 17531 } 17532 17533 static int 17534 bxe_flr_clnup_poll_hw_counter(struct bxe_softc *sc, 17535 uint32_t reg, 17536 char *msg, 17537 uint32_t poll_cnt) 17538 { 17539 uint32_t val = bxe_flr_clnup_reg_poll(sc, reg, 0, poll_cnt); 17540 17541 if (val != 0) { 17542 BLOGE(sc, "%s usage count=%d\n", msg, val); 17543 return (1); 17544 } 17545 17546 return (0); 17547 } 17548 17549 /* Common routines with VF FLR cleanup */ 17550 static uint32_t 17551 bxe_flr_clnup_poll_count(struct bxe_softc *sc) 17552 { 17553 /* adjust polling timeout */ 17554 if (CHIP_REV_IS_EMUL(sc)) { 17555 return (FLR_POLL_CNT * 2000); 17556 } 17557 17558 if (CHIP_REV_IS_FPGA(sc)) { 17559 return (FLR_POLL_CNT * 120); 17560 } 17561 17562 return (FLR_POLL_CNT); 17563 } 17564 17565 static int 17566 bxe_poll_hw_usage_counters(struct bxe_softc *sc, 17567 uint32_t poll_cnt) 17568 { 17569 /* wait for CFC PF usage-counter to zero (includes all the VFs) */ 17570 if (bxe_flr_clnup_poll_hw_counter(sc, 17571 CFC_REG_NUM_LCIDS_INSIDE_PF, 17572 "CFC PF usage counter timed out", 17573 poll_cnt)) { 17574 return (1); 17575 } 17576 17577 /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */ 17578 if (bxe_flr_clnup_poll_hw_counter(sc, 17579 DORQ_REG_PF_USAGE_CNT, 17580 "DQ PF usage counter timed out", 17581 poll_cnt)) { 17582 return (1); 17583 } 17584 17585 /* Wait for QM PF usage-counter to zero (until DQ cleanup) */ 17586 if (bxe_flr_clnup_poll_hw_counter(sc, 17587 QM_REG_PF_USG_CNT_0 + 4*SC_FUNC(sc), 17588 "QM PF usage counter timed out", 17589 poll_cnt)) { 17590 return (1); 17591 } 17592 17593 /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */ 17594 if (bxe_flr_clnup_poll_hw_counter(sc, 17595 TM_REG_LIN0_VNIC_UC + 4*SC_PORT(sc), 17596 "Timers VNIC usage counter timed out", 17597 poll_cnt)) { 17598 return (1); 17599 } 17600 17601 if (bxe_flr_clnup_poll_hw_counter(sc, 17602 TM_REG_LIN0_NUM_SCANS + 4*SC_PORT(sc), 17603 "Timers NUM_SCANS usage counter timed out", 17604 poll_cnt)) { 17605 return (1); 17606 } 17607 17608 /* Wait DMAE PF usage counter to zero */ 17609 if (bxe_flr_clnup_poll_hw_counter(sc, 17610 dmae_reg_go_c[INIT_DMAE_C(sc)], 17611 "DMAE dommand register timed out", 17612 poll_cnt)) { 17613 return (1); 17614 } 17615 17616 return (0); 17617 } 17618 17619 #define OP_GEN_PARAM(param) \ 17620 (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM) 17621 #define OP_GEN_TYPE(type) \ 17622 (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE) 17623 #define OP_GEN_AGG_VECT(index) \ 17624 (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX) 17625 17626 static int 17627 bxe_send_final_clnup(struct bxe_softc *sc, 17628 uint8_t clnup_func, 17629 uint32_t poll_cnt) 17630 { 17631 uint32_t op_gen_command = 0; 17632 uint32_t comp_addr = (BAR_CSTRORM_INTMEM + 17633 CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func)); 17634 int ret = 0; 17635 17636 if (REG_RD(sc, comp_addr)) { 17637 BLOGE(sc, "Cleanup complete was not 0 before sending\n"); 17638 return (1); 17639 } 17640 17641 op_gen_command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX); 17642 op_gen_command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE); 17643 op_gen_command |= OP_GEN_AGG_VECT(clnup_func); 17644 op_gen_command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT; 17645 17646 BLOGD(sc, DBG_LOAD, "sending FW Final cleanup\n"); 17647 REG_WR(sc, XSDM_REG_OPERATION_GEN, op_gen_command); 17648 17649 if (bxe_flr_clnup_reg_poll(sc, comp_addr, 1, poll_cnt) != 1) { 17650 BLOGE(sc, "FW final cleanup did not succeed\n"); 17651 BLOGD(sc, DBG_LOAD, "At timeout completion address contained %x\n", 17652 (REG_RD(sc, comp_addr))); 17653 bxe_panic(sc, ("FLR cleanup failed\n")); 17654 return (1); 17655 } 17656 17657 /* Zero completion for nxt FLR */ 17658 REG_WR(sc, comp_addr, 0); 17659 17660 return (ret); 17661 } 17662 17663 static void 17664 bxe_pbf_pN_buf_flushed(struct bxe_softc *sc, 17665 struct pbf_pN_buf_regs *regs, 17666 uint32_t poll_count) 17667 { 17668 uint32_t init_crd, crd, crd_start, crd_freed, crd_freed_start; 17669 uint32_t cur_cnt = poll_count; 17670 17671 crd_freed = crd_freed_start = REG_RD(sc, regs->crd_freed); 17672 crd = crd_start = REG_RD(sc, regs->crd); 17673 init_crd = REG_RD(sc, regs->init_crd); 17674 17675 BLOGD(sc, DBG_LOAD, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd); 17676 BLOGD(sc, DBG_LOAD, "CREDIT[%d] : s:%x\n", regs->pN, crd); 17677 BLOGD(sc, DBG_LOAD, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed); 17678 17679 while ((crd != init_crd) && 17680 ((uint32_t)((int32_t)crd_freed - (int32_t)crd_freed_start) < 17681 (init_crd - crd_start))) { 17682 if (cur_cnt--) { 17683 DELAY(FLR_WAIT_INTERVAL); 17684 crd = REG_RD(sc, regs->crd); 17685 crd_freed = REG_RD(sc, regs->crd_freed); 17686 } else { 17687 BLOGD(sc, DBG_LOAD, "PBF tx buffer[%d] timed out\n", regs->pN); 17688 BLOGD(sc, DBG_LOAD, "CREDIT[%d] : c:%x\n", regs->pN, crd); 17689 BLOGD(sc, DBG_LOAD, "CREDIT_FREED[%d]: c:%x\n", regs->pN, crd_freed); 17690 break; 17691 } 17692 } 17693 17694 BLOGD(sc, DBG_LOAD, "Waited %d*%d usec for PBF tx buffer[%d]\n", 17695 poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN); 17696 } 17697 17698 static void 17699 bxe_pbf_pN_cmd_flushed(struct bxe_softc *sc, 17700 struct pbf_pN_cmd_regs *regs, 17701 uint32_t poll_count) 17702 { 17703 uint32_t occup, to_free, freed, freed_start; 17704 uint32_t cur_cnt = poll_count; 17705 17706 occup = to_free = REG_RD(sc, regs->lines_occup); 17707 freed = freed_start = REG_RD(sc, regs->lines_freed); 17708 17709 BLOGD(sc, DBG_LOAD, "OCCUPANCY[%d] : s:%x\n", regs->pN, occup); 17710 BLOGD(sc, DBG_LOAD, "LINES_FREED[%d] : s:%x\n", regs->pN, freed); 17711 17712 while (occup && 17713 ((uint32_t)((int32_t)freed - (int32_t)freed_start) < to_free)) { 17714 if (cur_cnt--) { 17715 DELAY(FLR_WAIT_INTERVAL); 17716 occup = REG_RD(sc, regs->lines_occup); 17717 freed = REG_RD(sc, regs->lines_freed); 17718 } else { 17719 BLOGD(sc, DBG_LOAD, "PBF cmd queue[%d] timed out\n", regs->pN); 17720 BLOGD(sc, DBG_LOAD, "OCCUPANCY[%d] : s:%x\n", regs->pN, occup); 17721 BLOGD(sc, DBG_LOAD, "LINES_FREED[%d] : s:%x\n", regs->pN, freed); 17722 break; 17723 } 17724 } 17725 17726 BLOGD(sc, DBG_LOAD, "Waited %d*%d usec for PBF cmd queue[%d]\n", 17727 poll_count - cur_cnt, FLR_WAIT_INTERVAL, regs->pN); 17728 } 17729 17730 static void 17731 bxe_tx_hw_flushed(struct bxe_softc *sc, uint32_t poll_count) 17732 { 17733 struct pbf_pN_cmd_regs cmd_regs[] = { 17734 {0, (CHIP_IS_E3B0(sc)) ? 17735 PBF_REG_TQ_OCCUPANCY_Q0 : 17736 PBF_REG_P0_TQ_OCCUPANCY, 17737 (CHIP_IS_E3B0(sc)) ? 17738 PBF_REG_TQ_LINES_FREED_CNT_Q0 : 17739 PBF_REG_P0_TQ_LINES_FREED_CNT}, 17740 {1, (CHIP_IS_E3B0(sc)) ? 17741 PBF_REG_TQ_OCCUPANCY_Q1 : 17742 PBF_REG_P1_TQ_OCCUPANCY, 17743 (CHIP_IS_E3B0(sc)) ? 17744 PBF_REG_TQ_LINES_FREED_CNT_Q1 : 17745 PBF_REG_P1_TQ_LINES_FREED_CNT}, 17746 {4, (CHIP_IS_E3B0(sc)) ? 17747 PBF_REG_TQ_OCCUPANCY_LB_Q : 17748 PBF_REG_P4_TQ_OCCUPANCY, 17749 (CHIP_IS_E3B0(sc)) ? 17750 PBF_REG_TQ_LINES_FREED_CNT_LB_Q : 17751 PBF_REG_P4_TQ_LINES_FREED_CNT} 17752 }; 17753 17754 struct pbf_pN_buf_regs buf_regs[] = { 17755 {0, (CHIP_IS_E3B0(sc)) ? 17756 PBF_REG_INIT_CRD_Q0 : 17757 PBF_REG_P0_INIT_CRD , 17758 (CHIP_IS_E3B0(sc)) ? 17759 PBF_REG_CREDIT_Q0 : 17760 PBF_REG_P0_CREDIT, 17761 (CHIP_IS_E3B0(sc)) ? 17762 PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 : 17763 PBF_REG_P0_INTERNAL_CRD_FREED_CNT}, 17764 {1, (CHIP_IS_E3B0(sc)) ? 17765 PBF_REG_INIT_CRD_Q1 : 17766 PBF_REG_P1_INIT_CRD, 17767 (CHIP_IS_E3B0(sc)) ? 17768 PBF_REG_CREDIT_Q1 : 17769 PBF_REG_P1_CREDIT, 17770 (CHIP_IS_E3B0(sc)) ? 17771 PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 : 17772 PBF_REG_P1_INTERNAL_CRD_FREED_CNT}, 17773 {4, (CHIP_IS_E3B0(sc)) ? 17774 PBF_REG_INIT_CRD_LB_Q : 17775 PBF_REG_P4_INIT_CRD, 17776 (CHIP_IS_E3B0(sc)) ? 17777 PBF_REG_CREDIT_LB_Q : 17778 PBF_REG_P4_CREDIT, 17779 (CHIP_IS_E3B0(sc)) ? 17780 PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q : 17781 PBF_REG_P4_INTERNAL_CRD_FREED_CNT}, 17782 }; 17783 17784 int i; 17785 17786 /* Verify the command queues are flushed P0, P1, P4 */ 17787 for (i = 0; i < ARRAY_SIZE(cmd_regs); i++) { 17788 bxe_pbf_pN_cmd_flushed(sc, &cmd_regs[i], poll_count); 17789 } 17790 17791 /* Verify the transmission buffers are flushed P0, P1, P4 */ 17792 for (i = 0; i < ARRAY_SIZE(buf_regs); i++) { 17793 bxe_pbf_pN_buf_flushed(sc, &buf_regs[i], poll_count); 17794 } 17795 } 17796 17797 static void 17798 bxe_hw_enable_status(struct bxe_softc *sc) 17799 { 17800 uint32_t val; 17801 17802 val = REG_RD(sc, CFC_REG_WEAK_ENABLE_PF); 17803 BLOGD(sc, DBG_LOAD, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val); 17804 17805 val = REG_RD(sc, PBF_REG_DISABLE_PF); 17806 BLOGD(sc, DBG_LOAD, "PBF_REG_DISABLE_PF is 0x%x\n", val); 17807 17808 val = REG_RD(sc, IGU_REG_PCI_PF_MSI_EN); 17809 BLOGD(sc, DBG_LOAD, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val); 17810 17811 val = REG_RD(sc, IGU_REG_PCI_PF_MSIX_EN); 17812 BLOGD(sc, DBG_LOAD, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val); 17813 17814 val = REG_RD(sc, IGU_REG_PCI_PF_MSIX_FUNC_MASK); 17815 BLOGD(sc, DBG_LOAD, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val); 17816 17817 val = REG_RD(sc, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR); 17818 BLOGD(sc, DBG_LOAD, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val); 17819 17820 val = REG_RD(sc, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR); 17821 BLOGD(sc, DBG_LOAD, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val); 17822 17823 val = REG_RD(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER); 17824 BLOGD(sc, DBG_LOAD, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n", val); 17825 } 17826 17827 static int 17828 bxe_pf_flr_clnup(struct bxe_softc *sc) 17829 { 17830 uint32_t poll_cnt = bxe_flr_clnup_poll_count(sc); 17831 17832 BLOGD(sc, DBG_LOAD, "Cleanup after FLR PF[%d]\n", SC_ABS_FUNC(sc)); 17833 17834 /* Re-enable PF target read access */ 17835 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1); 17836 17837 /* Poll HW usage counters */ 17838 BLOGD(sc, DBG_LOAD, "Polling usage counters\n"); 17839 if (bxe_poll_hw_usage_counters(sc, poll_cnt)) { 17840 return (-1); 17841 } 17842 17843 /* Zero the igu 'trailing edge' and 'leading edge' */ 17844 17845 /* Send the FW cleanup command */ 17846 if (bxe_send_final_clnup(sc, (uint8_t)SC_FUNC(sc), poll_cnt)) { 17847 return (-1); 17848 } 17849 17850 /* ATC cleanup */ 17851 17852 /* Verify TX hw is flushed */ 17853 bxe_tx_hw_flushed(sc, poll_cnt); 17854 17855 /* Wait 100ms (not adjusted according to platform) */ 17856 DELAY(100000); 17857 17858 /* Verify no pending pci transactions */ 17859 if (bxe_is_pcie_pending(sc)) { 17860 BLOGE(sc, "PCIE Transactions still pending\n"); 17861 } 17862 17863 /* Debug */ 17864 bxe_hw_enable_status(sc); 17865 17866 /* 17867 * Master enable - Due to WB DMAE writes performed before this 17868 * register is re-initialized as part of the regular function init 17869 */ 17870 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); 17871 17872 return (0); 17873 } 17874 17875 static int 17876 bxe_init_hw_func(struct bxe_softc *sc) 17877 { 17878 int port = SC_PORT(sc); 17879 int func = SC_FUNC(sc); 17880 int init_phase = PHASE_PF0 + func; 17881 struct ecore_ilt *ilt = sc->ilt; 17882 uint16_t cdu_ilt_start; 17883 uint32_t addr, val; 17884 uint32_t main_mem_base, main_mem_size, main_mem_prty_clr; 17885 int i, main_mem_width, rc; 17886 17887 BLOGD(sc, DBG_LOAD, "starting func init for func %d\n", func); 17888 17889 /* FLR cleanup */ 17890 if (!CHIP_IS_E1x(sc)) { 17891 rc = bxe_pf_flr_clnup(sc); 17892 if (rc) { 17893 BLOGE(sc, "FLR cleanup failed!\n"); 17894 // XXX bxe_fw_dump(sc); 17895 // XXX bxe_idle_chk(sc); 17896 return (rc); 17897 } 17898 } 17899 17900 /* set MSI reconfigure capability */ 17901 if (sc->devinfo.int_block == INT_BLOCK_HC) { 17902 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0); 17903 val = REG_RD(sc, addr); 17904 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0; 17905 REG_WR(sc, addr, val); 17906 } 17907 17908 ecore_init_block(sc, BLOCK_PXP, init_phase); 17909 ecore_init_block(sc, BLOCK_PXP2, init_phase); 17910 17911 ilt = sc->ilt; 17912 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start; 17913 17914 for (i = 0; i < L2_ILT_LINES(sc); i++) { 17915 ilt->lines[cdu_ilt_start + i].page = sc->context[i].vcxt; 17916 ilt->lines[cdu_ilt_start + i].page_mapping = 17917 sc->context[i].vcxt_dma.paddr; 17918 ilt->lines[cdu_ilt_start + i].size = sc->context[i].size; 17919 } 17920 ecore_ilt_init_op(sc, INITOP_SET); 17921 17922 /* Set NIC mode */ 17923 REG_WR(sc, PRS_REG_NIC_MODE, 1); 17924 BLOGD(sc, DBG_LOAD, "NIC MODE configured\n"); 17925 17926 if (!CHIP_IS_E1x(sc)) { 17927 uint32_t pf_conf = IGU_PF_CONF_FUNC_EN; 17928 17929 /* Turn on a single ISR mode in IGU if driver is going to use 17930 * INT#x or MSI 17931 */ 17932 if (sc->interrupt_mode != INTR_MODE_MSIX) { 17933 pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN; 17934 } 17935 17936 /* 17937 * Timers workaround bug: function init part. 17938 * Need to wait 20msec after initializing ILT, 17939 * needed to make sure there are no requests in 17940 * one of the PXP internal queues with "old" ILT addresses 17941 */ 17942 DELAY(20000); 17943 17944 /* 17945 * Master enable - Due to WB DMAE writes performed before this 17946 * register is re-initialized as part of the regular function 17947 * init 17948 */ 17949 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); 17950 /* Enable the function in IGU */ 17951 REG_WR(sc, IGU_REG_PF_CONFIGURATION, pf_conf); 17952 } 17953 17954 sc->dmae_ready = 1; 17955 17956 ecore_init_block(sc, BLOCK_PGLUE_B, init_phase); 17957 17958 if (!CHIP_IS_E1x(sc)) 17959 REG_WR(sc, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func); 17960 17961 ecore_init_block(sc, BLOCK_ATC, init_phase); 17962 ecore_init_block(sc, BLOCK_DMAE, init_phase); 17963 ecore_init_block(sc, BLOCK_NIG, init_phase); 17964 ecore_init_block(sc, BLOCK_SRC, init_phase); 17965 ecore_init_block(sc, BLOCK_MISC, init_phase); 17966 ecore_init_block(sc, BLOCK_TCM, init_phase); 17967 ecore_init_block(sc, BLOCK_UCM, init_phase); 17968 ecore_init_block(sc, BLOCK_CCM, init_phase); 17969 ecore_init_block(sc, BLOCK_XCM, init_phase); 17970 ecore_init_block(sc, BLOCK_TSEM, init_phase); 17971 ecore_init_block(sc, BLOCK_USEM, init_phase); 17972 ecore_init_block(sc, BLOCK_CSEM, init_phase); 17973 ecore_init_block(sc, BLOCK_XSEM, init_phase); 17974 17975 if (!CHIP_IS_E1x(sc)) 17976 REG_WR(sc, QM_REG_PF_EN, 1); 17977 17978 if (!CHIP_IS_E1x(sc)) { 17979 REG_WR(sc, TSEM_REG_VFPF_ERR_NUM, BXE_MAX_NUM_OF_VFS + func); 17980 REG_WR(sc, USEM_REG_VFPF_ERR_NUM, BXE_MAX_NUM_OF_VFS + func); 17981 REG_WR(sc, CSEM_REG_VFPF_ERR_NUM, BXE_MAX_NUM_OF_VFS + func); 17982 REG_WR(sc, XSEM_REG_VFPF_ERR_NUM, BXE_MAX_NUM_OF_VFS + func); 17983 } 17984 ecore_init_block(sc, BLOCK_QM, init_phase); 17985 17986 ecore_init_block(sc, BLOCK_TM, init_phase); 17987 ecore_init_block(sc, BLOCK_DORQ, init_phase); 17988 17989 bxe_iov_init_dq(sc); 17990 17991 ecore_init_block(sc, BLOCK_BRB1, init_phase); 17992 ecore_init_block(sc, BLOCK_PRS, init_phase); 17993 ecore_init_block(sc, BLOCK_TSDM, init_phase); 17994 ecore_init_block(sc, BLOCK_CSDM, init_phase); 17995 ecore_init_block(sc, BLOCK_USDM, init_phase); 17996 ecore_init_block(sc, BLOCK_XSDM, init_phase); 17997 ecore_init_block(sc, BLOCK_UPB, init_phase); 17998 ecore_init_block(sc, BLOCK_XPB, init_phase); 17999 ecore_init_block(sc, BLOCK_PBF, init_phase); 18000 if (!CHIP_IS_E1x(sc)) 18001 REG_WR(sc, PBF_REG_DISABLE_PF, 0); 18002 18003 ecore_init_block(sc, BLOCK_CDU, init_phase); 18004 18005 ecore_init_block(sc, BLOCK_CFC, init_phase); 18006 18007 if (!CHIP_IS_E1x(sc)) 18008 REG_WR(sc, CFC_REG_WEAK_ENABLE_PF, 1); 18009 18010 if (IS_MF(sc)) { 18011 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port*8, 1); 18012 REG_WR(sc, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, OVLAN(sc)); 18013 } 18014 18015 ecore_init_block(sc, BLOCK_MISC_AEU, init_phase); 18016 18017 /* HC init per function */ 18018 if (sc->devinfo.int_block == INT_BLOCK_HC) { 18019 if (CHIP_IS_E1H(sc)) { 18020 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); 18021 18022 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port*8, 0); 18023 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port*8, 0); 18024 } 18025 ecore_init_block(sc, BLOCK_HC, init_phase); 18026 18027 } else { 18028 int num_segs, sb_idx, prod_offset; 18029 18030 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); 18031 18032 if (!CHIP_IS_E1x(sc)) { 18033 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, 0); 18034 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, 0); 18035 } 18036 18037 ecore_init_block(sc, BLOCK_IGU, init_phase); 18038 18039 if (!CHIP_IS_E1x(sc)) { 18040 int dsb_idx = 0; 18041 /** 18042 * Producer memory: 18043 * E2 mode: address 0-135 match to the mapping memory; 18044 * 136 - PF0 default prod; 137 - PF1 default prod; 18045 * 138 - PF2 default prod; 139 - PF3 default prod; 18046 * 140 - PF0 attn prod; 141 - PF1 attn prod; 18047 * 142 - PF2 attn prod; 143 - PF3 attn prod; 18048 * 144-147 reserved. 18049 * 18050 * E1.5 mode - In backward compatible mode; 18051 * for non default SB; each even line in the memory 18052 * holds the U producer and each odd line hold 18053 * the C producer. The first 128 producers are for 18054 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20 18055 * producers are for the DSB for each PF. 18056 * Each PF has five segments: (the order inside each 18057 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods; 18058 * 132-135 C prods; 136-139 X prods; 140-143 T prods; 18059 * 144-147 attn prods; 18060 */ 18061 /* non-default-status-blocks */ 18062 num_segs = CHIP_INT_MODE_IS_BC(sc) ? 18063 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS; 18064 for (sb_idx = 0; sb_idx < sc->igu_sb_cnt; sb_idx++) { 18065 prod_offset = (sc->igu_base_sb + sb_idx) * 18066 num_segs; 18067 18068 for (i = 0; i < num_segs; i++) { 18069 addr = IGU_REG_PROD_CONS_MEMORY + 18070 (prod_offset + i) * 4; 18071 REG_WR(sc, addr, 0); 18072 } 18073 /* send consumer update with value 0 */ 18074 bxe_ack_sb(sc, sc->igu_base_sb + sb_idx, 18075 USTORM_ID, 0, IGU_INT_NOP, 1); 18076 bxe_igu_clear_sb(sc, sc->igu_base_sb + sb_idx); 18077 } 18078 18079 /* default-status-blocks */ 18080 num_segs = CHIP_INT_MODE_IS_BC(sc) ? 18081 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS; 18082 18083 if (CHIP_IS_MODE_4_PORT(sc)) 18084 dsb_idx = SC_FUNC(sc); 18085 else 18086 dsb_idx = SC_VN(sc); 18087 18088 prod_offset = (CHIP_INT_MODE_IS_BC(sc) ? 18089 IGU_BC_BASE_DSB_PROD + dsb_idx : 18090 IGU_NORM_BASE_DSB_PROD + dsb_idx); 18091 18092 /* 18093 * igu prods come in chunks of E1HVN_MAX (4) - 18094 * does not matters what is the current chip mode 18095 */ 18096 for (i = 0; i < (num_segs * E1HVN_MAX); 18097 i += E1HVN_MAX) { 18098 addr = IGU_REG_PROD_CONS_MEMORY + 18099 (prod_offset + i)*4; 18100 REG_WR(sc, addr, 0); 18101 } 18102 /* send consumer update with 0 */ 18103 if (CHIP_INT_MODE_IS_BC(sc)) { 18104 bxe_ack_sb(sc, sc->igu_dsb_id, 18105 USTORM_ID, 0, IGU_INT_NOP, 1); 18106 bxe_ack_sb(sc, sc->igu_dsb_id, 18107 CSTORM_ID, 0, IGU_INT_NOP, 1); 18108 bxe_ack_sb(sc, sc->igu_dsb_id, 18109 XSTORM_ID, 0, IGU_INT_NOP, 1); 18110 bxe_ack_sb(sc, sc->igu_dsb_id, 18111 TSTORM_ID, 0, IGU_INT_NOP, 1); 18112 bxe_ack_sb(sc, sc->igu_dsb_id, 18113 ATTENTION_ID, 0, IGU_INT_NOP, 1); 18114 } else { 18115 bxe_ack_sb(sc, sc->igu_dsb_id, 18116 USTORM_ID, 0, IGU_INT_NOP, 1); 18117 bxe_ack_sb(sc, sc->igu_dsb_id, 18118 ATTENTION_ID, 0, IGU_INT_NOP, 1); 18119 } 18120 bxe_igu_clear_sb(sc, sc->igu_dsb_id); 18121 18122 /* !!! these should become driver const once 18123 rf-tool supports split-68 const */ 18124 REG_WR(sc, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0); 18125 REG_WR(sc, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0); 18126 REG_WR(sc, IGU_REG_SB_MASK_LSB, 0); 18127 REG_WR(sc, IGU_REG_SB_MASK_MSB, 0); 18128 REG_WR(sc, IGU_REG_PBA_STATUS_LSB, 0); 18129 REG_WR(sc, IGU_REG_PBA_STATUS_MSB, 0); 18130 } 18131 } 18132 18133 /* Reset PCIE errors for debug */ 18134 REG_WR(sc, 0x2114, 0xffffffff); 18135 REG_WR(sc, 0x2120, 0xffffffff); 18136 18137 if (CHIP_IS_E1x(sc)) { 18138 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/ 18139 main_mem_base = HC_REG_MAIN_MEMORY + 18140 SC_PORT(sc) * (main_mem_size * 4); 18141 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR; 18142 main_mem_width = 8; 18143 18144 val = REG_RD(sc, main_mem_prty_clr); 18145 if (val) { 18146 BLOGD(sc, DBG_LOAD, 18147 "Parity errors in HC block during function init (0x%x)!\n", 18148 val); 18149 } 18150 18151 /* Clear "false" parity errors in MSI-X table */ 18152 for (i = main_mem_base; 18153 i < main_mem_base + main_mem_size * 4; 18154 i += main_mem_width) { 18155 bxe_read_dmae(sc, i, main_mem_width / 4); 18156 bxe_write_dmae(sc, BXE_SP_MAPPING(sc, wb_data), 18157 i, main_mem_width / 4); 18158 } 18159 /* Clear HC parity attention */ 18160 REG_RD(sc, main_mem_prty_clr); 18161 } 18162 18163 #if 1 18164 /* Enable STORMs SP logging */ 18165 REG_WR8(sc, BAR_USTRORM_INTMEM + 18166 USTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1); 18167 REG_WR8(sc, BAR_TSTRORM_INTMEM + 18168 TSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1); 18169 REG_WR8(sc, BAR_CSTRORM_INTMEM + 18170 CSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1); 18171 REG_WR8(sc, BAR_XSTRORM_INTMEM + 18172 XSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1); 18173 #endif 18174 18175 elink_phy_probe(&sc->link_params); 18176 18177 return (0); 18178 } 18179 18180 static void 18181 bxe_link_reset(struct bxe_softc *sc) 18182 { 18183 if (!BXE_NOMCP(sc)) { 18184 bxe_acquire_phy_lock(sc); 18185 elink_lfa_reset(&sc->link_params, &sc->link_vars); 18186 bxe_release_phy_lock(sc); 18187 } else { 18188 if (!CHIP_REV_IS_SLOW(sc)) { 18189 BLOGW(sc, "Bootcode is missing - cannot reset link\n"); 18190 } 18191 } 18192 } 18193 18194 static void 18195 bxe_reset_port(struct bxe_softc *sc) 18196 { 18197 int port = SC_PORT(sc); 18198 uint32_t val; 18199 18200 ELINK_DEBUG_P0(sc, "bxe_reset_port called\n"); 18201 /* reset physical Link */ 18202 bxe_link_reset(sc); 18203 18204 REG_WR(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0); 18205 18206 /* Do not rcv packets to BRB */ 18207 REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0); 18208 /* Do not direct rcv packets that are not for MCP to the BRB */ 18209 REG_WR(sc, (port ? NIG_REG_LLH1_BRB1_NOT_MCP : 18210 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0); 18211 18212 /* Configure AEU */ 18213 REG_WR(sc, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0); 18214 18215 DELAY(100000); 18216 18217 /* Check for BRB port occupancy */ 18218 val = REG_RD(sc, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4); 18219 if (val) { 18220 BLOGD(sc, DBG_LOAD, 18221 "BRB1 is not empty, %d blocks are occupied\n", val); 18222 } 18223 18224 /* TODO: Close Doorbell port? */ 18225 } 18226 18227 static void 18228 bxe_ilt_wr(struct bxe_softc *sc, 18229 uint32_t index, 18230 bus_addr_t addr) 18231 { 18232 int reg; 18233 uint32_t wb_write[2]; 18234 18235 if (CHIP_IS_E1(sc)) { 18236 reg = PXP2_REG_RQ_ONCHIP_AT + index*8; 18237 } else { 18238 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8; 18239 } 18240 18241 wb_write[0] = ONCHIP_ADDR1(addr); 18242 wb_write[1] = ONCHIP_ADDR2(addr); 18243 REG_WR_DMAE(sc, reg, wb_write, 2); 18244 } 18245 18246 static void 18247 bxe_clear_func_ilt(struct bxe_softc *sc, 18248 uint32_t func) 18249 { 18250 uint32_t i, base = FUNC_ILT_BASE(func); 18251 for (i = base; i < base + ILT_PER_FUNC; i++) { 18252 bxe_ilt_wr(sc, i, 0); 18253 } 18254 } 18255 18256 static void 18257 bxe_reset_func(struct bxe_softc *sc) 18258 { 18259 struct bxe_fastpath *fp; 18260 int port = SC_PORT(sc); 18261 int func = SC_FUNC(sc); 18262 int i; 18263 18264 /* Disable the function in the FW */ 18265 REG_WR8(sc, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0); 18266 REG_WR8(sc, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0); 18267 REG_WR8(sc, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0); 18268 REG_WR8(sc, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0); 18269 18270 /* FP SBs */ 18271 FOR_EACH_ETH_QUEUE(sc, i) { 18272 fp = &sc->fp[i]; 18273 REG_WR8(sc, BAR_CSTRORM_INTMEM + 18274 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id), 18275 SB_DISABLED); 18276 } 18277 18278 /* SP SB */ 18279 REG_WR8(sc, BAR_CSTRORM_INTMEM + 18280 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func), 18281 SB_DISABLED); 18282 18283 for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++) { 18284 REG_WR(sc, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func), 0); 18285 } 18286 18287 /* Configure IGU */ 18288 if (sc->devinfo.int_block == INT_BLOCK_HC) { 18289 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port*8, 0); 18290 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port*8, 0); 18291 } else { 18292 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, 0); 18293 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, 0); 18294 } 18295 18296 if (CNIC_LOADED(sc)) { 18297 /* Disable Timer scan */ 18298 REG_WR(sc, TM_REG_EN_LINEAR0_TIMER + port*4, 0); 18299 /* 18300 * Wait for at least 10ms and up to 2 second for the timers 18301 * scan to complete 18302 */ 18303 for (i = 0; i < 200; i++) { 18304 DELAY(10000); 18305 if (!REG_RD(sc, TM_REG_LIN0_SCAN_ON + port*4)) 18306 break; 18307 } 18308 } 18309 18310 /* Clear ILT */ 18311 bxe_clear_func_ilt(sc, func); 18312 18313 /* 18314 * Timers workaround bug for E2: if this is vnic-3, 18315 * we need to set the entire ilt range for this timers. 18316 */ 18317 if (!CHIP_IS_E1x(sc) && SC_VN(sc) == 3) { 18318 struct ilt_client_info ilt_cli; 18319 /* use dummy TM client */ 18320 memset(&ilt_cli, 0, sizeof(struct ilt_client_info)); 18321 ilt_cli.start = 0; 18322 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1; 18323 ilt_cli.client_num = ILT_CLIENT_TM; 18324 18325 ecore_ilt_boundry_init_op(sc, &ilt_cli, 0, INITOP_CLEAR); 18326 } 18327 18328 /* this assumes that reset_port() called before reset_func()*/ 18329 if (!CHIP_IS_E1x(sc)) { 18330 bxe_pf_disable(sc); 18331 } 18332 18333 sc->dmae_ready = 0; 18334 } 18335 18336 static int 18337 bxe_gunzip_init(struct bxe_softc *sc) 18338 { 18339 return (0); 18340 } 18341 18342 static void 18343 bxe_gunzip_end(struct bxe_softc *sc) 18344 { 18345 return; 18346 } 18347 18348 static int 18349 bxe_init_firmware(struct bxe_softc *sc) 18350 { 18351 if (CHIP_IS_E1(sc)) { 18352 ecore_init_e1_firmware(sc); 18353 sc->iro_array = e1_iro_arr; 18354 } else if (CHIP_IS_E1H(sc)) { 18355 ecore_init_e1h_firmware(sc); 18356 sc->iro_array = e1h_iro_arr; 18357 } else if (!CHIP_IS_E1x(sc)) { 18358 ecore_init_e2_firmware(sc); 18359 sc->iro_array = e2_iro_arr; 18360 } else { 18361 BLOGE(sc, "Unsupported chip revision\n"); 18362 return (-1); 18363 } 18364 18365 return (0); 18366 } 18367 18368 static void 18369 bxe_release_firmware(struct bxe_softc *sc) 18370 { 18371 /* Do nothing */ 18372 return; 18373 } 18374 18375 static int 18376 ecore_gunzip(struct bxe_softc *sc, 18377 const uint8_t *zbuf, 18378 int len) 18379 { 18380 /* XXX : Implement... */ 18381 BLOGD(sc, DBG_LOAD, "ECORE_GUNZIP NOT IMPLEMENTED\n"); 18382 return (FALSE); 18383 } 18384 18385 static void 18386 ecore_reg_wr_ind(struct bxe_softc *sc, 18387 uint32_t addr, 18388 uint32_t val) 18389 { 18390 bxe_reg_wr_ind(sc, addr, val); 18391 } 18392 18393 static void 18394 ecore_write_dmae_phys_len(struct bxe_softc *sc, 18395 bus_addr_t phys_addr, 18396 uint32_t addr, 18397 uint32_t len) 18398 { 18399 bxe_write_dmae_phys_len(sc, phys_addr, addr, len); 18400 } 18401 18402 void 18403 ecore_storm_memset_struct(struct bxe_softc *sc, 18404 uint32_t addr, 18405 size_t size, 18406 uint32_t *data) 18407 { 18408 uint8_t i; 18409 for (i = 0; i < size/4; i++) { 18410 REG_WR(sc, addr + (i * 4), data[i]); 18411 } 18412 } 18413 18414 18415 /* 18416 * character device - ioctl interface definitions 18417 */ 18418 18419 18420 #include "bxe_dump.h" 18421 #include "bxe_ioctl.h" 18422 #include <sys/conf.h> 18423 18424 static int bxe_eioctl(struct cdev *dev, u_long cmd, caddr_t data, int fflag, 18425 struct thread *td); 18426 18427 static struct cdevsw bxe_cdevsw = { 18428 .d_version = D_VERSION, 18429 .d_ioctl = bxe_eioctl, 18430 .d_name = "bxecnic", 18431 }; 18432 18433 #define BXE_PATH(sc) (CHIP_IS_E1x(sc) ? 0 : (sc->pcie_func & 1)) 18434 18435 18436 #define DUMP_ALL_PRESETS 0x1FFF 18437 #define DUMP_MAX_PRESETS 13 18438 #define IS_E1_REG(chips) ((chips & DUMP_CHIP_E1) == DUMP_CHIP_E1) 18439 #define IS_E1H_REG(chips) ((chips & DUMP_CHIP_E1H) == DUMP_CHIP_E1H) 18440 #define IS_E2_REG(chips) ((chips & DUMP_CHIP_E2) == DUMP_CHIP_E2) 18441 #define IS_E3A0_REG(chips) ((chips & DUMP_CHIP_E3A0) == DUMP_CHIP_E3A0) 18442 #define IS_E3B0_REG(chips) ((chips & DUMP_CHIP_E3B0) == DUMP_CHIP_E3B0) 18443 18444 #define IS_REG_IN_PRESET(presets, idx) \ 18445 ((presets & (1 << (idx-1))) == (1 << (idx-1))) 18446 18447 18448 static int 18449 bxe_get_preset_regs_len(struct bxe_softc *sc, uint32_t preset) 18450 { 18451 if (CHIP_IS_E1(sc)) 18452 return dump_num_registers[0][preset-1]; 18453 else if (CHIP_IS_E1H(sc)) 18454 return dump_num_registers[1][preset-1]; 18455 else if (CHIP_IS_E2(sc)) 18456 return dump_num_registers[2][preset-1]; 18457 else if (CHIP_IS_E3A0(sc)) 18458 return dump_num_registers[3][preset-1]; 18459 else if (CHIP_IS_E3B0(sc)) 18460 return dump_num_registers[4][preset-1]; 18461 else 18462 return 0; 18463 } 18464 18465 static int 18466 bxe_get_total_regs_len32(struct bxe_softc *sc) 18467 { 18468 uint32_t preset_idx; 18469 int regdump_len32 = 0; 18470 18471 18472 /* Calculate the total preset regs length */ 18473 for (preset_idx = 1; preset_idx <= DUMP_MAX_PRESETS; preset_idx++) { 18474 regdump_len32 += bxe_get_preset_regs_len(sc, preset_idx); 18475 } 18476 18477 return regdump_len32; 18478 } 18479 18480 static const uint32_t * 18481 __bxe_get_page_addr_ar(struct bxe_softc *sc) 18482 { 18483 if (CHIP_IS_E2(sc)) 18484 return page_vals_e2; 18485 else if (CHIP_IS_E3(sc)) 18486 return page_vals_e3; 18487 else 18488 return NULL; 18489 } 18490 18491 static uint32_t 18492 __bxe_get_page_reg_num(struct bxe_softc *sc) 18493 { 18494 if (CHIP_IS_E2(sc)) 18495 return PAGE_MODE_VALUES_E2; 18496 else if (CHIP_IS_E3(sc)) 18497 return PAGE_MODE_VALUES_E3; 18498 else 18499 return 0; 18500 } 18501 18502 static const uint32_t * 18503 __bxe_get_page_write_ar(struct bxe_softc *sc) 18504 { 18505 if (CHIP_IS_E2(sc)) 18506 return page_write_regs_e2; 18507 else if (CHIP_IS_E3(sc)) 18508 return page_write_regs_e3; 18509 else 18510 return NULL; 18511 } 18512 18513 static uint32_t 18514 __bxe_get_page_write_num(struct bxe_softc *sc) 18515 { 18516 if (CHIP_IS_E2(sc)) 18517 return PAGE_WRITE_REGS_E2; 18518 else if (CHIP_IS_E3(sc)) 18519 return PAGE_WRITE_REGS_E3; 18520 else 18521 return 0; 18522 } 18523 18524 static const struct reg_addr * 18525 __bxe_get_page_read_ar(struct bxe_softc *sc) 18526 { 18527 if (CHIP_IS_E2(sc)) 18528 return page_read_regs_e2; 18529 else if (CHIP_IS_E3(sc)) 18530 return page_read_regs_e3; 18531 else 18532 return NULL; 18533 } 18534 18535 static uint32_t 18536 __bxe_get_page_read_num(struct bxe_softc *sc) 18537 { 18538 if (CHIP_IS_E2(sc)) 18539 return PAGE_READ_REGS_E2; 18540 else if (CHIP_IS_E3(sc)) 18541 return PAGE_READ_REGS_E3; 18542 else 18543 return 0; 18544 } 18545 18546 static bool 18547 bxe_is_reg_in_chip(struct bxe_softc *sc, const struct reg_addr *reg_info) 18548 { 18549 if (CHIP_IS_E1(sc)) 18550 return IS_E1_REG(reg_info->chips); 18551 else if (CHIP_IS_E1H(sc)) 18552 return IS_E1H_REG(reg_info->chips); 18553 else if (CHIP_IS_E2(sc)) 18554 return IS_E2_REG(reg_info->chips); 18555 else if (CHIP_IS_E3A0(sc)) 18556 return IS_E3A0_REG(reg_info->chips); 18557 else if (CHIP_IS_E3B0(sc)) 18558 return IS_E3B0_REG(reg_info->chips); 18559 else 18560 return 0; 18561 } 18562 18563 static bool 18564 bxe_is_wreg_in_chip(struct bxe_softc *sc, const struct wreg_addr *wreg_info) 18565 { 18566 if (CHIP_IS_E1(sc)) 18567 return IS_E1_REG(wreg_info->chips); 18568 else if (CHIP_IS_E1H(sc)) 18569 return IS_E1H_REG(wreg_info->chips); 18570 else if (CHIP_IS_E2(sc)) 18571 return IS_E2_REG(wreg_info->chips); 18572 else if (CHIP_IS_E3A0(sc)) 18573 return IS_E3A0_REG(wreg_info->chips); 18574 else if (CHIP_IS_E3B0(sc)) 18575 return IS_E3B0_REG(wreg_info->chips); 18576 else 18577 return 0; 18578 } 18579 18580 /** 18581 * bxe_read_pages_regs - read "paged" registers 18582 * 18583 * @bp device handle 18584 * @p output buffer 18585 * 18586 * Reads "paged" memories: memories that may only be read by first writing to a 18587 * specific address ("write address") and then reading from a specific address 18588 * ("read address"). There may be more than one write address per "page" and 18589 * more than one read address per write address. 18590 */ 18591 static void 18592 bxe_read_pages_regs(struct bxe_softc *sc, uint32_t *p, uint32_t preset) 18593 { 18594 uint32_t i, j, k, n; 18595 18596 /* addresses of the paged registers */ 18597 const uint32_t *page_addr = __bxe_get_page_addr_ar(sc); 18598 /* number of paged registers */ 18599 int num_pages = __bxe_get_page_reg_num(sc); 18600 /* write addresses */ 18601 const uint32_t *write_addr = __bxe_get_page_write_ar(sc); 18602 /* number of write addresses */ 18603 int write_num = __bxe_get_page_write_num(sc); 18604 /* read addresses info */ 18605 const struct reg_addr *read_addr = __bxe_get_page_read_ar(sc); 18606 /* number of read addresses */ 18607 int read_num = __bxe_get_page_read_num(sc); 18608 uint32_t addr, size; 18609 18610 for (i = 0; i < num_pages; i++) { 18611 for (j = 0; j < write_num; j++) { 18612 REG_WR(sc, write_addr[j], page_addr[i]); 18613 18614 for (k = 0; k < read_num; k++) { 18615 if (IS_REG_IN_PRESET(read_addr[k].presets, preset)) { 18616 size = read_addr[k].size; 18617 for (n = 0; n < size; n++) { 18618 addr = read_addr[k].addr + n*4; 18619 *p++ = REG_RD(sc, addr); 18620 } 18621 } 18622 } 18623 } 18624 } 18625 return; 18626 } 18627 18628 18629 static int 18630 bxe_get_preset_regs(struct bxe_softc *sc, uint32_t *p, uint32_t preset) 18631 { 18632 uint32_t i, j, addr; 18633 const struct wreg_addr *wreg_addr_p = NULL; 18634 18635 if (CHIP_IS_E1(sc)) 18636 wreg_addr_p = &wreg_addr_e1; 18637 else if (CHIP_IS_E1H(sc)) 18638 wreg_addr_p = &wreg_addr_e1h; 18639 else if (CHIP_IS_E2(sc)) 18640 wreg_addr_p = &wreg_addr_e2; 18641 else if (CHIP_IS_E3A0(sc)) 18642 wreg_addr_p = &wreg_addr_e3; 18643 else if (CHIP_IS_E3B0(sc)) 18644 wreg_addr_p = &wreg_addr_e3b0; 18645 else 18646 return (-1); 18647 18648 /* Read the idle_chk registers */ 18649 for (i = 0; i < IDLE_REGS_COUNT; i++) { 18650 if (bxe_is_reg_in_chip(sc, &idle_reg_addrs[i]) && 18651 IS_REG_IN_PRESET(idle_reg_addrs[i].presets, preset)) { 18652 for (j = 0; j < idle_reg_addrs[i].size; j++) 18653 *p++ = REG_RD(sc, idle_reg_addrs[i].addr + j*4); 18654 } 18655 } 18656 18657 /* Read the regular registers */ 18658 for (i = 0; i < REGS_COUNT; i++) { 18659 if (bxe_is_reg_in_chip(sc, ®_addrs[i]) && 18660 IS_REG_IN_PRESET(reg_addrs[i].presets, preset)) { 18661 for (j = 0; j < reg_addrs[i].size; j++) 18662 *p++ = REG_RD(sc, reg_addrs[i].addr + j*4); 18663 } 18664 } 18665 18666 /* Read the CAM registers */ 18667 if (bxe_is_wreg_in_chip(sc, wreg_addr_p) && 18668 IS_REG_IN_PRESET(wreg_addr_p->presets, preset)) { 18669 for (i = 0; i < wreg_addr_p->size; i++) { 18670 *p++ = REG_RD(sc, wreg_addr_p->addr + i*4); 18671 18672 /* In case of wreg_addr register, read additional 18673 registers from read_regs array 18674 */ 18675 for (j = 0; j < wreg_addr_p->read_regs_count; j++) { 18676 addr = *(wreg_addr_p->read_regs); 18677 *p++ = REG_RD(sc, addr + j*4); 18678 } 18679 } 18680 } 18681 18682 /* Paged registers are supported in E2 & E3 only */ 18683 if (CHIP_IS_E2(sc) || CHIP_IS_E3(sc)) { 18684 /* Read "paged" registers */ 18685 bxe_read_pages_regs(sc, p, preset); 18686 } 18687 18688 return 0; 18689 } 18690 18691 int 18692 bxe_grc_dump(struct bxe_softc *sc) 18693 { 18694 int rval = 0; 18695 uint32_t preset_idx; 18696 uint8_t *buf; 18697 uint32_t size; 18698 struct dump_header *d_hdr; 18699 uint32_t i; 18700 uint32_t reg_val; 18701 uint32_t reg_addr; 18702 uint32_t cmd_offset; 18703 struct ecore_ilt *ilt = SC_ILT(sc); 18704 struct bxe_fastpath *fp; 18705 struct ilt_client_info *ilt_cli; 18706 int grc_dump_size; 18707 18708 18709 if (sc->grcdump_done || sc->grcdump_started) 18710 return (rval); 18711 18712 sc->grcdump_started = 1; 18713 BLOGI(sc, "Started collecting grcdump\n"); 18714 18715 grc_dump_size = (bxe_get_total_regs_len32(sc) * sizeof(uint32_t)) + 18716 sizeof(struct dump_header); 18717 18718 sc->grc_dump = malloc(grc_dump_size, M_DEVBUF, M_NOWAIT); 18719 18720 if (sc->grc_dump == NULL) { 18721 BLOGW(sc, "Unable to allocate memory for grcdump collection\n"); 18722 return(ENOMEM); 18723 } 18724 18725 18726 18727 /* Disable parity attentions as long as following dump may 18728 * cause false alarms by reading never written registers. We 18729 * will re-enable parity attentions right after the dump. 18730 */ 18731 18732 /* Disable parity on path 0 */ 18733 bxe_pretend_func(sc, 0); 18734 18735 ecore_disable_blocks_parity(sc); 18736 18737 /* Disable parity on path 1 */ 18738 bxe_pretend_func(sc, 1); 18739 ecore_disable_blocks_parity(sc); 18740 18741 /* Return to current function */ 18742 bxe_pretend_func(sc, SC_ABS_FUNC(sc)); 18743 18744 buf = sc->grc_dump; 18745 d_hdr = sc->grc_dump; 18746 18747 d_hdr->header_size = (sizeof(struct dump_header) >> 2) - 1; 18748 d_hdr->version = BNX2X_DUMP_VERSION; 18749 d_hdr->preset = DUMP_ALL_PRESETS; 18750 18751 if (CHIP_IS_E1(sc)) { 18752 d_hdr->dump_meta_data = DUMP_CHIP_E1; 18753 } else if (CHIP_IS_E1H(sc)) { 18754 d_hdr->dump_meta_data = DUMP_CHIP_E1H; 18755 } else if (CHIP_IS_E2(sc)) { 18756 d_hdr->dump_meta_data = DUMP_CHIP_E2 | 18757 (BXE_PATH(sc) ? DUMP_PATH_1 : DUMP_PATH_0); 18758 } else if (CHIP_IS_E3A0(sc)) { 18759 d_hdr->dump_meta_data = DUMP_CHIP_E3A0 | 18760 (BXE_PATH(sc) ? DUMP_PATH_1 : DUMP_PATH_0); 18761 } else if (CHIP_IS_E3B0(sc)) { 18762 d_hdr->dump_meta_data = DUMP_CHIP_E3B0 | 18763 (BXE_PATH(sc) ? DUMP_PATH_1 : DUMP_PATH_0); 18764 } 18765 18766 buf += sizeof(struct dump_header); 18767 18768 for (preset_idx = 1; preset_idx <= DUMP_MAX_PRESETS; preset_idx++) { 18769 18770 /* Skip presets with IOR */ 18771 if ((preset_idx == 2) || (preset_idx == 5) || (preset_idx == 8) || 18772 (preset_idx == 11)) 18773 continue; 18774 18775 rval = bxe_get_preset_regs(sc, (uint32_t *)buf, preset_idx); 18776 18777 if (rval) 18778 break; 18779 18780 size = bxe_get_preset_regs_len(sc, preset_idx) * (sizeof (uint32_t)); 18781 18782 buf += size; 18783 } 18784 18785 bxe_pretend_func(sc, 0); 18786 ecore_clear_blocks_parity(sc); 18787 ecore_enable_blocks_parity(sc); 18788 18789 bxe_pretend_func(sc, 1); 18790 ecore_clear_blocks_parity(sc); 18791 ecore_enable_blocks_parity(sc); 18792 18793 /* Return to current function */ 18794 bxe_pretend_func(sc, SC_ABS_FUNC(sc)); 18795 18796 18797 18798 if(sc->state == BXE_STATE_OPEN) { 18799 if(sc->fw_stats_req != NULL) { 18800 BLOGI(sc, "fw stats start_paddr %#jx end_paddr %#jx vaddr %p size 0x%x\n", 18801 (uintmax_t)sc->fw_stats_req_mapping, 18802 (uintmax_t)sc->fw_stats_data_mapping, 18803 sc->fw_stats_req, (sc->fw_stats_req_size + sc->fw_stats_data_size)); 18804 } 18805 if(sc->def_sb != NULL) { 18806 BLOGI(sc, "def_status_block paddr %p vaddr %p size 0x%zx\n", 18807 (void *)sc->def_sb_dma.paddr, sc->def_sb, 18808 sizeof(struct host_sp_status_block)); 18809 } 18810 if(sc->eq_dma.vaddr != NULL) { 18811 BLOGI(sc, "event_queue paddr %#jx vaddr %p size 0x%x\n", 18812 (uintmax_t)sc->eq_dma.paddr, sc->eq_dma.vaddr, BCM_PAGE_SIZE); 18813 } 18814 if(sc->sp_dma.vaddr != NULL) { 18815 BLOGI(sc, "slow path paddr %#jx vaddr %p size 0x%zx\n", 18816 (uintmax_t)sc->sp_dma.paddr, sc->sp_dma.vaddr, 18817 sizeof(struct bxe_slowpath)); 18818 } 18819 if(sc->spq_dma.vaddr != NULL) { 18820 BLOGI(sc, "slow path queue paddr %#jx vaddr %p size 0x%x\n", 18821 (uintmax_t)sc->spq_dma.paddr, sc->spq_dma.vaddr, BCM_PAGE_SIZE); 18822 } 18823 if(sc->gz_buf_dma.vaddr != NULL) { 18824 BLOGI(sc, "fw_buf paddr %#jx vaddr %p size 0x%x\n", 18825 (uintmax_t)sc->gz_buf_dma.paddr, sc->gz_buf_dma.vaddr, 18826 FW_BUF_SIZE); 18827 } 18828 for (i = 0; i < sc->num_queues; i++) { 18829 fp = &sc->fp[i]; 18830 if(fp->sb_dma.vaddr != NULL && fp->tx_dma.vaddr != NULL && 18831 fp->rx_dma.vaddr != NULL && fp->rcq_dma.vaddr != NULL && 18832 fp->rx_sge_dma.vaddr != NULL) { 18833 18834 BLOGI(sc, "FP status block fp %d paddr %#jx vaddr %p size 0x%zx\n", i, 18835 (uintmax_t)fp->sb_dma.paddr, fp->sb_dma.vaddr, 18836 sizeof(union bxe_host_hc_status_block)); 18837 BLOGI(sc, "TX BD CHAIN fp %d paddr %#jx vaddr %p size 0x%x\n", i, 18838 (uintmax_t)fp->tx_dma.paddr, fp->tx_dma.vaddr, 18839 (BCM_PAGE_SIZE * TX_BD_NUM_PAGES)); 18840 BLOGI(sc, "RX BD CHAIN fp %d paddr %#jx vaddr %p size 0x%x\n", i, 18841 (uintmax_t)fp->rx_dma.paddr, fp->rx_dma.vaddr, 18842 (BCM_PAGE_SIZE * RX_BD_NUM_PAGES)); 18843 BLOGI(sc, "RX RCQ CHAIN fp %d paddr %#jx vaddr %p size 0x%zx\n", i, 18844 (uintmax_t)fp->rcq_dma.paddr, fp->rcq_dma.vaddr, 18845 (BCM_PAGE_SIZE * RCQ_NUM_PAGES)); 18846 BLOGI(sc, "RX SGE CHAIN fp %d paddr %#jx vaddr %p size 0x%x\n", i, 18847 (uintmax_t)fp->rx_sge_dma.paddr, fp->rx_sge_dma.vaddr, 18848 (BCM_PAGE_SIZE * RX_SGE_NUM_PAGES)); 18849 } 18850 } 18851 if(ilt != NULL ) { 18852 ilt_cli = &ilt->clients[1]; 18853 if(ilt->lines != NULL) { 18854 for (i = ilt_cli->start; i <= ilt_cli->end; i++) { 18855 BLOGI(sc, "ECORE_ILT paddr %#jx vaddr %p size 0x%x\n", 18856 (uintmax_t)(((struct bxe_dma *)((&ilt->lines[i])->page))->paddr), 18857 ((struct bxe_dma *)((&ilt->lines[i])->page))->vaddr, BCM_PAGE_SIZE); 18858 } 18859 } 18860 } 18861 18862 18863 cmd_offset = DMAE_REG_CMD_MEM; 18864 for (i = 0; i < 224; i++) { 18865 reg_addr = (cmd_offset +(i * 4)); 18866 reg_val = REG_RD(sc, reg_addr); 18867 BLOGI(sc, "DMAE_REG_CMD_MEM i=%d reg_addr 0x%x reg_val 0x%08x\n",i, 18868 reg_addr, reg_val); 18869 } 18870 } 18871 18872 BLOGI(sc, "Collection of grcdump done\n"); 18873 sc->grcdump_done = 1; 18874 return(rval); 18875 } 18876 18877 static int 18878 bxe_add_cdev(struct bxe_softc *sc) 18879 { 18880 sc->eeprom = malloc(BXE_EEPROM_MAX_DATA_LEN, M_DEVBUF, M_NOWAIT); 18881 18882 if (sc->eeprom == NULL) { 18883 BLOGW(sc, "Unable to alloc for eeprom size buffer\n"); 18884 return (-1); 18885 } 18886 18887 sc->ioctl_dev = make_dev(&bxe_cdevsw, 18888 sc->ifp->if_dunit, 18889 UID_ROOT, 18890 GID_WHEEL, 18891 0600, 18892 "%s", 18893 if_name(sc->ifp)); 18894 18895 if (sc->ioctl_dev == NULL) { 18896 free(sc->eeprom, M_DEVBUF); 18897 sc->eeprom = NULL; 18898 return (-1); 18899 } 18900 18901 sc->ioctl_dev->si_drv1 = sc; 18902 18903 return (0); 18904 } 18905 18906 static void 18907 bxe_del_cdev(struct bxe_softc *sc) 18908 { 18909 if (sc->ioctl_dev != NULL) 18910 destroy_dev(sc->ioctl_dev); 18911 18912 if (sc->eeprom != NULL) { 18913 free(sc->eeprom, M_DEVBUF); 18914 sc->eeprom = NULL; 18915 } 18916 sc->ioctl_dev = NULL; 18917 18918 return; 18919 } 18920 18921 static bool bxe_is_nvram_accessible(struct bxe_softc *sc) 18922 { 18923 18924 if ((if_getdrvflags(sc->ifp) & IFF_DRV_RUNNING) == 0) 18925 return FALSE; 18926 18927 return TRUE; 18928 } 18929 18930 18931 static int 18932 bxe_wr_eeprom(struct bxe_softc *sc, void *data, uint32_t offset, uint32_t len) 18933 { 18934 int rval = 0; 18935 18936 if(!bxe_is_nvram_accessible(sc)) { 18937 BLOGW(sc, "Cannot access eeprom when interface is down\n"); 18938 return (-EAGAIN); 18939 } 18940 rval = bxe_nvram_write(sc, offset, (uint8_t *)data, len); 18941 18942 18943 return (rval); 18944 } 18945 18946 static int 18947 bxe_rd_eeprom(struct bxe_softc *sc, void *data, uint32_t offset, uint32_t len) 18948 { 18949 int rval = 0; 18950 18951 if(!bxe_is_nvram_accessible(sc)) { 18952 BLOGW(sc, "Cannot access eeprom when interface is down\n"); 18953 return (-EAGAIN); 18954 } 18955 rval = bxe_nvram_read(sc, offset, (uint8_t *)data, len); 18956 18957 return (rval); 18958 } 18959 18960 static int 18961 bxe_eeprom_rd_wr(struct bxe_softc *sc, bxe_eeprom_t *eeprom) 18962 { 18963 int rval = 0; 18964 18965 switch (eeprom->eeprom_cmd) { 18966 18967 case BXE_EEPROM_CMD_SET_EEPROM: 18968 18969 rval = copyin(eeprom->eeprom_data, sc->eeprom, 18970 eeprom->eeprom_data_len); 18971 18972 if (rval) 18973 break; 18974 18975 rval = bxe_wr_eeprom(sc, sc->eeprom, eeprom->eeprom_offset, 18976 eeprom->eeprom_data_len); 18977 break; 18978 18979 case BXE_EEPROM_CMD_GET_EEPROM: 18980 18981 rval = bxe_rd_eeprom(sc, sc->eeprom, eeprom->eeprom_offset, 18982 eeprom->eeprom_data_len); 18983 18984 if (rval) { 18985 break; 18986 } 18987 18988 rval = copyout(sc->eeprom, eeprom->eeprom_data, 18989 eeprom->eeprom_data_len); 18990 break; 18991 18992 default: 18993 rval = EINVAL; 18994 break; 18995 } 18996 18997 if (rval) { 18998 BLOGW(sc, "ioctl cmd %d failed rval %d\n", eeprom->eeprom_cmd, rval); 18999 } 19000 19001 return (rval); 19002 } 19003 19004 static int 19005 bxe_get_settings(struct bxe_softc *sc, bxe_dev_setting_t *dev_p) 19006 { 19007 uint32_t ext_phy_config; 19008 int port = SC_PORT(sc); 19009 int cfg_idx = bxe_get_link_cfg_idx(sc); 19010 19011 dev_p->supported = sc->port.supported[cfg_idx] | 19012 (sc->port.supported[cfg_idx ^ 1] & 19013 (ELINK_SUPPORTED_TP | ELINK_SUPPORTED_FIBRE)); 19014 dev_p->advertising = sc->port.advertising[cfg_idx]; 19015 if(sc->link_params.phy[bxe_get_cur_phy_idx(sc)].media_type == 19016 ELINK_ETH_PHY_SFP_1G_FIBER) { 19017 dev_p->supported = ~(ELINK_SUPPORTED_10000baseT_Full); 19018 dev_p->advertising &= ~(ADVERTISED_10000baseT_Full); 19019 } 19020 if ((sc->state == BXE_STATE_OPEN) && sc->link_vars.link_up && 19021 !(sc->flags & BXE_MF_FUNC_DIS)) { 19022 dev_p->duplex = sc->link_vars.duplex; 19023 if (IS_MF(sc) && !BXE_NOMCP(sc)) 19024 dev_p->speed = bxe_get_mf_speed(sc); 19025 else 19026 dev_p->speed = sc->link_vars.line_speed; 19027 } else { 19028 dev_p->duplex = DUPLEX_UNKNOWN; 19029 dev_p->speed = SPEED_UNKNOWN; 19030 } 19031 19032 dev_p->port = bxe_media_detect(sc); 19033 19034 ext_phy_config = SHMEM_RD(sc, 19035 dev_info.port_hw_config[port].external_phy_config); 19036 if((ext_phy_config & PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK) == 19037 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) 19038 dev_p->phy_address = sc->port.phy_addr; 19039 else if(((ext_phy_config & PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK) != 19040 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) && 19041 ((ext_phy_config & PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK) != 19042 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)) 19043 dev_p->phy_address = ELINK_XGXS_EXT_PHY_ADDR(ext_phy_config); 19044 else 19045 dev_p->phy_address = 0; 19046 19047 if(sc->link_params.req_line_speed[cfg_idx] == ELINK_SPEED_AUTO_NEG) 19048 dev_p->autoneg = AUTONEG_ENABLE; 19049 else 19050 dev_p->autoneg = AUTONEG_DISABLE; 19051 19052 19053 return 0; 19054 } 19055 19056 static int 19057 bxe_eioctl(struct cdev *dev, u_long cmd, caddr_t data, int fflag, 19058 struct thread *td) 19059 { 19060 struct bxe_softc *sc; 19061 int rval = 0; 19062 device_t pci_dev; 19063 bxe_grcdump_t *dump = NULL; 19064 int grc_dump_size; 19065 bxe_drvinfo_t *drv_infop = NULL; 19066 bxe_dev_setting_t *dev_p; 19067 bxe_dev_setting_t dev_set; 19068 bxe_get_regs_t *reg_p; 19069 bxe_reg_rdw_t *reg_rdw_p; 19070 bxe_pcicfg_rdw_t *cfg_rdw_p; 19071 bxe_perm_mac_addr_t *mac_addr_p; 19072 19073 19074 if ((sc = (struct bxe_softc *)dev->si_drv1) == NULL) 19075 return ENXIO; 19076 19077 pci_dev= sc->dev; 19078 19079 dump = (bxe_grcdump_t *)data; 19080 19081 switch(cmd) { 19082 19083 case BXE_GRC_DUMP_SIZE: 19084 dump->pci_func = sc->pcie_func; 19085 dump->grcdump_size = 19086 (bxe_get_total_regs_len32(sc) * sizeof(uint32_t)) + 19087 sizeof(struct dump_header); 19088 break; 19089 19090 case BXE_GRC_DUMP: 19091 19092 grc_dump_size = (bxe_get_total_regs_len32(sc) * sizeof(uint32_t)) + 19093 sizeof(struct dump_header); 19094 if ((!sc->trigger_grcdump) || (dump->grcdump == NULL) || 19095 (dump->grcdump_size < grc_dump_size)) { 19096 rval = EINVAL; 19097 break; 19098 } 19099 19100 if((sc->trigger_grcdump) && (!sc->grcdump_done) && 19101 (!sc->grcdump_started)) { 19102 rval = bxe_grc_dump(sc); 19103 } 19104 19105 if((!rval) && (sc->grcdump_done) && (sc->grcdump_started) && 19106 (sc->grc_dump != NULL)) { 19107 dump->grcdump_dwords = grc_dump_size >> 2; 19108 rval = copyout(sc->grc_dump, dump->grcdump, grc_dump_size); 19109 free(sc->grc_dump, M_DEVBUF); 19110 sc->grc_dump = NULL; 19111 sc->grcdump_started = 0; 19112 sc->grcdump_done = 0; 19113 } 19114 19115 break; 19116 19117 case BXE_DRV_INFO: 19118 drv_infop = (bxe_drvinfo_t *)data; 19119 snprintf(drv_infop->drv_name, BXE_DRV_NAME_LENGTH, "%s", "bxe"); 19120 snprintf(drv_infop->drv_version, BXE_DRV_VERSION_LENGTH, "v:%s", 19121 BXE_DRIVER_VERSION); 19122 snprintf(drv_infop->mfw_version, BXE_MFW_VERSION_LENGTH, "%s", 19123 sc->devinfo.bc_ver_str); 19124 snprintf(drv_infop->stormfw_version, BXE_STORMFW_VERSION_LENGTH, 19125 "%s", sc->fw_ver_str); 19126 drv_infop->eeprom_dump_len = sc->devinfo.flash_size; 19127 drv_infop->reg_dump_len = 19128 (bxe_get_total_regs_len32(sc) * sizeof(uint32_t)) 19129 + sizeof(struct dump_header); 19130 snprintf(drv_infop->bus_info, BXE_BUS_INFO_LENGTH, "%d:%d:%d", 19131 sc->pcie_bus, sc->pcie_device, sc->pcie_func); 19132 break; 19133 19134 case BXE_DEV_SETTING: 19135 dev_p = (bxe_dev_setting_t *)data; 19136 bxe_get_settings(sc, &dev_set); 19137 dev_p->supported = dev_set.supported; 19138 dev_p->advertising = dev_set.advertising; 19139 dev_p->speed = dev_set.speed; 19140 dev_p->duplex = dev_set.duplex; 19141 dev_p->port = dev_set.port; 19142 dev_p->phy_address = dev_set.phy_address; 19143 dev_p->autoneg = dev_set.autoneg; 19144 19145 break; 19146 19147 case BXE_GET_REGS: 19148 19149 reg_p = (bxe_get_regs_t *)data; 19150 grc_dump_size = reg_p->reg_buf_len; 19151 19152 if((!sc->grcdump_done) && (!sc->grcdump_started)) { 19153 bxe_grc_dump(sc); 19154 } 19155 if((sc->grcdump_done) && (sc->grcdump_started) && 19156 (sc->grc_dump != NULL)) { 19157 rval = copyout(sc->grc_dump, reg_p->reg_buf, grc_dump_size); 19158 free(sc->grc_dump, M_DEVBUF); 19159 sc->grc_dump = NULL; 19160 sc->grcdump_started = 0; 19161 sc->grcdump_done = 0; 19162 } 19163 19164 break; 19165 19166 case BXE_RDW_REG: 19167 reg_rdw_p = (bxe_reg_rdw_t *)data; 19168 if((reg_rdw_p->reg_cmd == BXE_READ_REG_CMD) && 19169 (reg_rdw_p->reg_access_type == BXE_REG_ACCESS_DIRECT)) 19170 reg_rdw_p->reg_val = REG_RD(sc, reg_rdw_p->reg_id); 19171 19172 if((reg_rdw_p->reg_cmd == BXE_WRITE_REG_CMD) && 19173 (reg_rdw_p->reg_access_type == BXE_REG_ACCESS_DIRECT)) 19174 REG_WR(sc, reg_rdw_p->reg_id, reg_rdw_p->reg_val); 19175 19176 break; 19177 19178 case BXE_RDW_PCICFG: 19179 cfg_rdw_p = (bxe_pcicfg_rdw_t *)data; 19180 if(cfg_rdw_p->cfg_cmd == BXE_READ_PCICFG) { 19181 19182 cfg_rdw_p->cfg_val = pci_read_config(sc->dev, cfg_rdw_p->cfg_id, 19183 cfg_rdw_p->cfg_width); 19184 19185 } else if(cfg_rdw_p->cfg_cmd == BXE_WRITE_PCICFG) { 19186 pci_write_config(sc->dev, cfg_rdw_p->cfg_id, cfg_rdw_p->cfg_val, 19187 cfg_rdw_p->cfg_width); 19188 } else { 19189 BLOGW(sc, "BXE_RDW_PCICFG ioctl wrong cmd passed\n"); 19190 } 19191 break; 19192 19193 case BXE_MAC_ADDR: 19194 mac_addr_p = (bxe_perm_mac_addr_t *)data; 19195 snprintf(mac_addr_p->mac_addr_str, sizeof(sc->mac_addr_str), "%s", 19196 sc->mac_addr_str); 19197 break; 19198 19199 case BXE_EEPROM: 19200 rval = bxe_eeprom_rd_wr(sc, (bxe_eeprom_t *)data); 19201 break; 19202 19203 19204 default: 19205 break; 19206 } 19207 19208 return (rval); 19209 } 19210 19211 #ifdef NETDUMP 19212 static void 19213 bxe_netdump_init(struct ifnet *ifp, int *nrxr, int *ncl, int *clsize) 19214 { 19215 struct bxe_softc *sc; 19216 19217 sc = if_getsoftc(ifp); 19218 BXE_CORE_LOCK(sc); 19219 *nrxr = sc->num_queues; 19220 *ncl = NETDUMP_MAX_IN_FLIGHT; 19221 *clsize = sc->fp[0].mbuf_alloc_size; 19222 BXE_CORE_UNLOCK(sc); 19223 } 19224 19225 static void 19226 bxe_netdump_event(struct ifnet *ifp __unused, enum netdump_ev event __unused) 19227 { 19228 } 19229 19230 static int 19231 bxe_netdump_transmit(struct ifnet *ifp, struct mbuf *m) 19232 { 19233 struct bxe_softc *sc; 19234 int error; 19235 19236 sc = if_getsoftc(ifp); 19237 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 19238 IFF_DRV_RUNNING || !sc->link_vars.link_up) 19239 return (ENOENT); 19240 19241 error = bxe_tx_encap(&sc->fp[0], &m); 19242 if (error != 0 && m != NULL) 19243 m_freem(m); 19244 return (error); 19245 } 19246 19247 static int 19248 bxe_netdump_poll(struct ifnet *ifp, int count) 19249 { 19250 struct bxe_softc *sc; 19251 int i; 19252 19253 sc = if_getsoftc(ifp); 19254 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0 || 19255 !sc->link_vars.link_up) 19256 return (ENOENT); 19257 19258 for (i = 0; i < sc->num_queues; i++) 19259 (void)bxe_rxeof(sc, &sc->fp[i]); 19260 (void)bxe_txeof(sc, &sc->fp[0]); 19261 return (0); 19262 } 19263 #endif /* NETDUMP */ 19264