1 /*- 2 * Copyright (c) 2007-2013 Broadcom Corporation. All rights reserved. 3 * 4 * Eric Davis <edavis@broadcom.com> 5 * David Christensen <davidch@broadcom.com> 6 * Gary Zambrano <zambrano@broadcom.com> 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. Neither the name of Broadcom Corporation nor the name of its contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written consent. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS' 22 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/cdefs.h> 35 __FBSDID("$FreeBSD$"); 36 37 #define BXE_DRIVER_VERSION "1.78.77" 38 39 #include "bxe.h" 40 #include "ecore_sp.h" 41 #include "ecore_init.h" 42 #include "ecore_init_ops.h" 43 44 #include "57710_int_offsets.h" 45 #include "57711_int_offsets.h" 46 #include "57712_int_offsets.h" 47 48 /* 49 * CTLTYPE_U64 and sysctl_handle_64 were added in r217616. Define these 50 * explicitly here for older kernels that don't include this changeset. 51 */ 52 #ifndef CTLTYPE_U64 53 #define CTLTYPE_U64 CTLTYPE_QUAD 54 #define sysctl_handle_64 sysctl_handle_quad 55 #endif 56 57 /* 58 * CSUM_TCP_IPV6 and CSUM_UDP_IPV6 were added in r236170. Define these 59 * here as zero(0) for older kernels that don't include this changeset 60 * thereby masking the functionality. 61 */ 62 #ifndef CSUM_TCP_IPV6 63 #define CSUM_TCP_IPV6 0 64 #define CSUM_UDP_IPV6 0 65 #endif 66 67 /* 68 * pci_find_cap was added in r219865. Re-define this at pci_find_extcap 69 * for older kernels that don't include this changeset. 70 */ 71 #if __FreeBSD_version < 900035 72 #define pci_find_cap pci_find_extcap 73 #endif 74 75 #define BXE_DEF_SB_ATT_IDX 0x0001 76 #define BXE_DEF_SB_IDX 0x0002 77 78 /* 79 * FLR Support - bxe_pf_flr_clnup() is called during nic_load in the per 80 * function HW initialization. 81 */ 82 #define FLR_WAIT_USEC 10000 /* 10 msecs */ 83 #define FLR_WAIT_INTERVAL 50 /* usecs */ 84 #define FLR_POLL_CNT (FLR_WAIT_USEC / FLR_WAIT_INTERVAL) /* 200 */ 85 86 struct pbf_pN_buf_regs { 87 int pN; 88 uint32_t init_crd; 89 uint32_t crd; 90 uint32_t crd_freed; 91 }; 92 93 struct pbf_pN_cmd_regs { 94 int pN; 95 uint32_t lines_occup; 96 uint32_t lines_freed; 97 }; 98 99 /* 100 * PCI Device ID Table used by bxe_probe(). 101 */ 102 #define BXE_DEVDESC_MAX 64 103 static struct bxe_device_type bxe_devs[] = { 104 { 105 BRCM_VENDORID, 106 CHIP_NUM_57710, 107 PCI_ANY_ID, PCI_ANY_ID, 108 "Broadcom NetXtreme II BCM57710 10GbE" 109 }, 110 { 111 BRCM_VENDORID, 112 CHIP_NUM_57711, 113 PCI_ANY_ID, PCI_ANY_ID, 114 "Broadcom NetXtreme II BCM57711 10GbE" 115 }, 116 { 117 BRCM_VENDORID, 118 CHIP_NUM_57711E, 119 PCI_ANY_ID, PCI_ANY_ID, 120 "Broadcom NetXtreme II BCM57711E 10GbE" 121 }, 122 { 123 BRCM_VENDORID, 124 CHIP_NUM_57712, 125 PCI_ANY_ID, PCI_ANY_ID, 126 "Broadcom NetXtreme II BCM57712 10GbE" 127 }, 128 { 129 BRCM_VENDORID, 130 CHIP_NUM_57712_MF, 131 PCI_ANY_ID, PCI_ANY_ID, 132 "Broadcom NetXtreme II BCM57712 MF 10GbE" 133 }, 134 #if 0 135 { 136 BRCM_VENDORID, 137 CHIP_NUM_57712_VF, 138 PCI_ANY_ID, PCI_ANY_ID, 139 "Broadcom NetXtreme II BCM57712 VF 10GbE" 140 }, 141 #endif 142 { 143 BRCM_VENDORID, 144 CHIP_NUM_57800, 145 PCI_ANY_ID, PCI_ANY_ID, 146 "Broadcom NetXtreme II BCM57800 10GbE" 147 }, 148 { 149 BRCM_VENDORID, 150 CHIP_NUM_57800_MF, 151 PCI_ANY_ID, PCI_ANY_ID, 152 "Broadcom NetXtreme II BCM57800 MF 10GbE" 153 }, 154 #if 0 155 { 156 BRCM_VENDORID, 157 CHIP_NUM_57800_VF, 158 PCI_ANY_ID, PCI_ANY_ID, 159 "Broadcom NetXtreme II BCM57800 VF 10GbE" 160 }, 161 #endif 162 { 163 BRCM_VENDORID, 164 CHIP_NUM_57810, 165 PCI_ANY_ID, PCI_ANY_ID, 166 "Broadcom NetXtreme II BCM57810 10GbE" 167 }, 168 { 169 BRCM_VENDORID, 170 CHIP_NUM_57810_MF, 171 PCI_ANY_ID, PCI_ANY_ID, 172 "Broadcom NetXtreme II BCM57810 MF 10GbE" 173 }, 174 #if 0 175 { 176 BRCM_VENDORID, 177 CHIP_NUM_57810_VF, 178 PCI_ANY_ID, PCI_ANY_ID, 179 "Broadcom NetXtreme II BCM57810 VF 10GbE" 180 }, 181 #endif 182 { 183 BRCM_VENDORID, 184 CHIP_NUM_57811, 185 PCI_ANY_ID, PCI_ANY_ID, 186 "Broadcom NetXtreme II BCM57811 10GbE" 187 }, 188 { 189 BRCM_VENDORID, 190 CHIP_NUM_57811_MF, 191 PCI_ANY_ID, PCI_ANY_ID, 192 "Broadcom NetXtreme II BCM57811 MF 10GbE" 193 }, 194 #if 0 195 { 196 BRCM_VENDORID, 197 CHIP_NUM_57811_VF, 198 PCI_ANY_ID, PCI_ANY_ID, 199 "Broadcom NetXtreme II BCM57811 VF 10GbE" 200 }, 201 #endif 202 { 203 BRCM_VENDORID, 204 CHIP_NUM_57840_4_10, 205 PCI_ANY_ID, PCI_ANY_ID, 206 "Broadcom NetXtreme II BCM57840 4x10GbE" 207 }, 208 #if 0 209 { 210 BRCM_VENDORID, 211 CHIP_NUM_57840_2_20, 212 PCI_ANY_ID, PCI_ANY_ID, 213 "Broadcom NetXtreme II BCM57840 2x20GbE" 214 }, 215 #endif 216 { 217 BRCM_VENDORID, 218 CHIP_NUM_57840_MF, 219 PCI_ANY_ID, PCI_ANY_ID, 220 "Broadcom NetXtreme II BCM57840 MF 10GbE" 221 }, 222 #if 0 223 { 224 BRCM_VENDORID, 225 CHIP_NUM_57840_VF, 226 PCI_ANY_ID, PCI_ANY_ID, 227 "Broadcom NetXtreme II BCM57840 VF 10GbE" 228 }, 229 #endif 230 { 231 0, 0, 0, 0, NULL 232 } 233 }; 234 235 MALLOC_DECLARE(M_BXE_ILT); 236 MALLOC_DEFINE(M_BXE_ILT, "bxe_ilt", "bxe ILT pointer"); 237 238 /* 239 * FreeBSD device entry points. 240 */ 241 static int bxe_probe(device_t); 242 static int bxe_attach(device_t); 243 static int bxe_detach(device_t); 244 static int bxe_shutdown(device_t); 245 246 /* 247 * FreeBSD KLD module/device interface event handler method. 248 */ 249 static device_method_t bxe_methods[] = { 250 /* Device interface (device_if.h) */ 251 DEVMETHOD(device_probe, bxe_probe), 252 DEVMETHOD(device_attach, bxe_attach), 253 DEVMETHOD(device_detach, bxe_detach), 254 DEVMETHOD(device_shutdown, bxe_shutdown), 255 #if 0 256 DEVMETHOD(device_suspend, bxe_suspend), 257 DEVMETHOD(device_resume, bxe_resume), 258 #endif 259 /* Bus interface (bus_if.h) */ 260 DEVMETHOD(bus_print_child, bus_generic_print_child), 261 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 262 KOBJMETHOD_END 263 }; 264 265 /* 266 * FreeBSD KLD Module data declaration 267 */ 268 static driver_t bxe_driver = { 269 "bxe", /* module name */ 270 bxe_methods, /* event handler */ 271 sizeof(struct bxe_softc) /* extra data */ 272 }; 273 274 /* 275 * FreeBSD dev class is needed to manage dev instances and 276 * to associate with a bus type 277 */ 278 static devclass_t bxe_devclass; 279 280 MODULE_DEPEND(bxe, pci, 1, 1, 1); 281 MODULE_DEPEND(bxe, ether, 1, 1, 1); 282 DRIVER_MODULE(bxe, pci, bxe_driver, bxe_devclass, 0, 0); 283 284 /* resources needed for unloading a previously loaded device */ 285 286 #define BXE_PREV_WAIT_NEEDED 1 287 struct mtx bxe_prev_mtx; 288 MTX_SYSINIT(bxe_prev_mtx, &bxe_prev_mtx, "bxe_prev_lock", MTX_DEF); 289 struct bxe_prev_list_node { 290 LIST_ENTRY(bxe_prev_list_node) node; 291 uint8_t bus; 292 uint8_t slot; 293 uint8_t path; 294 uint8_t aer; /* XXX automatic error recovery */ 295 uint8_t undi; 296 }; 297 static LIST_HEAD(, bxe_prev_list_node) bxe_prev_list = LIST_HEAD_INITIALIZER(bxe_prev_list); 298 299 static int load_count[2][3] = { {0} }; /* per-path: 0-common, 1-port0, 2-port1 */ 300 301 /* Tunable device values... */ 302 303 SYSCTL_NODE(_hw, OID_AUTO, bxe, CTLFLAG_RD, 0, "bxe driver parameters"); 304 305 /* Debug */ 306 unsigned long bxe_debug = 0; 307 TUNABLE_ULONG("hw.bxe.debug", &bxe_debug); 308 SYSCTL_ULONG(_hw_bxe, OID_AUTO, debug, (CTLFLAG_RDTUN), 309 &bxe_debug, 0, "Debug logging mode"); 310 311 /* Interrupt Mode: 0 (IRQ), 1 (MSI/IRQ), and 2 (MSI-X/MSI/IRQ) */ 312 static int bxe_interrupt_mode = INTR_MODE_MSIX; 313 TUNABLE_INT("hw.bxe.interrupt_mode", &bxe_interrupt_mode); 314 SYSCTL_INT(_hw_bxe, OID_AUTO, interrupt_mode, CTLFLAG_RDTUN, 315 &bxe_interrupt_mode, 0, "Interrupt (MSI-X/MSI/INTx) mode"); 316 317 /* Number of Queues: 0 (Auto) or 1 to 16 (fixed queue number) */ 318 static int bxe_queue_count = 4; 319 TUNABLE_INT("hw.bxe.queue_count", &bxe_queue_count); 320 SYSCTL_INT(_hw_bxe, OID_AUTO, queue_count, CTLFLAG_RDTUN, 321 &bxe_queue_count, 0, "Multi-Queue queue count"); 322 323 /* max number of buffers per queue (default RX_BD_USABLE) */ 324 static int bxe_max_rx_bufs = 0; 325 TUNABLE_INT("hw.bxe.max_rx_bufs", &bxe_max_rx_bufs); 326 SYSCTL_INT(_hw_bxe, OID_AUTO, max_rx_bufs, CTLFLAG_RDTUN, 327 &bxe_max_rx_bufs, 0, "Maximum Number of Rx Buffers Per Queue"); 328 329 /* Host interrupt coalescing RX tick timer (usecs) */ 330 static int bxe_hc_rx_ticks = 25; 331 TUNABLE_INT("hw.bxe.hc_rx_ticks", &bxe_hc_rx_ticks); 332 SYSCTL_INT(_hw_bxe, OID_AUTO, hc_rx_ticks, CTLFLAG_RDTUN, 333 &bxe_hc_rx_ticks, 0, "Host Coalescing Rx ticks"); 334 335 /* Host interrupt coalescing TX tick timer (usecs) */ 336 static int bxe_hc_tx_ticks = 50; 337 TUNABLE_INT("hw.bxe.hc_tx_ticks", &bxe_hc_tx_ticks); 338 SYSCTL_INT(_hw_bxe, OID_AUTO, hc_tx_ticks, CTLFLAG_RDTUN, 339 &bxe_hc_tx_ticks, 0, "Host Coalescing Tx ticks"); 340 341 /* Maximum number of Rx packets to process at a time */ 342 static int bxe_rx_budget = 0xffffffff; 343 TUNABLE_INT("hw.bxe.rx_budget", &bxe_rx_budget); 344 SYSCTL_INT(_hw_bxe, OID_AUTO, rx_budget, CTLFLAG_TUN, 345 &bxe_rx_budget, 0, "Rx processing budget"); 346 347 /* Maximum LRO aggregation size */ 348 static int bxe_max_aggregation_size = 0; 349 TUNABLE_INT("hw.bxe.max_aggregation_size", &bxe_max_aggregation_size); 350 SYSCTL_INT(_hw_bxe, OID_AUTO, max_aggregation_size, CTLFLAG_TUN, 351 &bxe_max_aggregation_size, 0, "max aggregation size"); 352 353 /* PCI MRRS: -1 (Auto), 0 (128B), 1 (256B), 2 (512B), 3 (1KB) */ 354 static int bxe_mrrs = -1; 355 TUNABLE_INT("hw.bxe.mrrs", &bxe_mrrs); 356 SYSCTL_INT(_hw_bxe, OID_AUTO, mrrs, CTLFLAG_RDTUN, 357 &bxe_mrrs, 0, "PCIe maximum read request size"); 358 359 /* AutoGrEEEn: 0 (hardware default), 1 (force on), 2 (force off) */ 360 static int bxe_autogreeen = 0; 361 TUNABLE_INT("hw.bxe.autogreeen", &bxe_autogreeen); 362 SYSCTL_INT(_hw_bxe, OID_AUTO, autogreeen, CTLFLAG_RDTUN, 363 &bxe_autogreeen, 0, "AutoGrEEEn support"); 364 365 /* 4-tuple RSS support for UDP: 0 (disabled), 1 (enabled) */ 366 static int bxe_udp_rss = 0; 367 TUNABLE_INT("hw.bxe.udp_rss", &bxe_udp_rss); 368 SYSCTL_INT(_hw_bxe, OID_AUTO, udp_rss, CTLFLAG_RDTUN, 369 &bxe_udp_rss, 0, "UDP RSS support"); 370 371 372 #define STAT_NAME_LEN 32 /* no stat names below can be longer than this */ 373 374 #define STATS_OFFSET32(stat_name) \ 375 (offsetof(struct bxe_eth_stats, stat_name) / 4) 376 377 #define Q_STATS_OFFSET32(stat_name) \ 378 (offsetof(struct bxe_eth_q_stats, stat_name) / 4) 379 380 static const struct { 381 uint32_t offset; 382 uint32_t size; 383 uint32_t flags; 384 #define STATS_FLAGS_PORT 1 385 #define STATS_FLAGS_FUNC 2 /* MF only cares about function stats */ 386 #define STATS_FLAGS_BOTH (STATS_FLAGS_FUNC | STATS_FLAGS_PORT) 387 char string[STAT_NAME_LEN]; 388 } bxe_eth_stats_arr[] = { 389 { STATS_OFFSET32(total_bytes_received_hi), 390 8, STATS_FLAGS_BOTH, "rx_bytes" }, 391 { STATS_OFFSET32(error_bytes_received_hi), 392 8, STATS_FLAGS_BOTH, "rx_error_bytes" }, 393 { STATS_OFFSET32(total_unicast_packets_received_hi), 394 8, STATS_FLAGS_BOTH, "rx_ucast_packets" }, 395 { STATS_OFFSET32(total_multicast_packets_received_hi), 396 8, STATS_FLAGS_BOTH, "rx_mcast_packets" }, 397 { STATS_OFFSET32(total_broadcast_packets_received_hi), 398 8, STATS_FLAGS_BOTH, "rx_bcast_packets" }, 399 { STATS_OFFSET32(rx_stat_dot3statsfcserrors_hi), 400 8, STATS_FLAGS_PORT, "rx_crc_errors" }, 401 { STATS_OFFSET32(rx_stat_dot3statsalignmenterrors_hi), 402 8, STATS_FLAGS_PORT, "rx_align_errors" }, 403 { STATS_OFFSET32(rx_stat_etherstatsundersizepkts_hi), 404 8, STATS_FLAGS_PORT, "rx_undersize_packets" }, 405 { STATS_OFFSET32(etherstatsoverrsizepkts_hi), 406 8, STATS_FLAGS_PORT, "rx_oversize_packets" }, 407 { STATS_OFFSET32(rx_stat_etherstatsfragments_hi), 408 8, STATS_FLAGS_PORT, "rx_fragments" }, 409 { STATS_OFFSET32(rx_stat_etherstatsjabbers_hi), 410 8, STATS_FLAGS_PORT, "rx_jabbers" }, 411 { STATS_OFFSET32(no_buff_discard_hi), 412 8, STATS_FLAGS_BOTH, "rx_discards" }, 413 { STATS_OFFSET32(mac_filter_discard), 414 4, STATS_FLAGS_PORT, "rx_filtered_packets" }, 415 { STATS_OFFSET32(mf_tag_discard), 416 4, STATS_FLAGS_PORT, "rx_mf_tag_discard" }, 417 { STATS_OFFSET32(pfc_frames_received_hi), 418 8, STATS_FLAGS_PORT, "pfc_frames_received" }, 419 { STATS_OFFSET32(pfc_frames_sent_hi), 420 8, STATS_FLAGS_PORT, "pfc_frames_sent" }, 421 { STATS_OFFSET32(brb_drop_hi), 422 8, STATS_FLAGS_PORT, "rx_brb_discard" }, 423 { STATS_OFFSET32(brb_truncate_hi), 424 8, STATS_FLAGS_PORT, "rx_brb_truncate" }, 425 { STATS_OFFSET32(pause_frames_received_hi), 426 8, STATS_FLAGS_PORT, "rx_pause_frames" }, 427 { STATS_OFFSET32(rx_stat_maccontrolframesreceived_hi), 428 8, STATS_FLAGS_PORT, "rx_mac_ctrl_frames" }, 429 { STATS_OFFSET32(nig_timer_max), 430 4, STATS_FLAGS_PORT, "rx_constant_pause_events" }, 431 { STATS_OFFSET32(total_bytes_transmitted_hi), 432 8, STATS_FLAGS_BOTH, "tx_bytes" }, 433 { STATS_OFFSET32(tx_stat_ifhcoutbadoctets_hi), 434 8, STATS_FLAGS_PORT, "tx_error_bytes" }, 435 { STATS_OFFSET32(total_unicast_packets_transmitted_hi), 436 8, STATS_FLAGS_BOTH, "tx_ucast_packets" }, 437 { STATS_OFFSET32(total_multicast_packets_transmitted_hi), 438 8, STATS_FLAGS_BOTH, "tx_mcast_packets" }, 439 { STATS_OFFSET32(total_broadcast_packets_transmitted_hi), 440 8, STATS_FLAGS_BOTH, "tx_bcast_packets" }, 441 { STATS_OFFSET32(tx_stat_dot3statsinternalmactransmiterrors_hi), 442 8, STATS_FLAGS_PORT, "tx_mac_errors" }, 443 { STATS_OFFSET32(rx_stat_dot3statscarriersenseerrors_hi), 444 8, STATS_FLAGS_PORT, "tx_carrier_errors" }, 445 { STATS_OFFSET32(tx_stat_dot3statssinglecollisionframes_hi), 446 8, STATS_FLAGS_PORT, "tx_single_collisions" }, 447 { STATS_OFFSET32(tx_stat_dot3statsmultiplecollisionframes_hi), 448 8, STATS_FLAGS_PORT, "tx_multi_collisions" }, 449 { STATS_OFFSET32(tx_stat_dot3statsdeferredtransmissions_hi), 450 8, STATS_FLAGS_PORT, "tx_deferred" }, 451 { STATS_OFFSET32(tx_stat_dot3statsexcessivecollisions_hi), 452 8, STATS_FLAGS_PORT, "tx_excess_collisions" }, 453 { STATS_OFFSET32(tx_stat_dot3statslatecollisions_hi), 454 8, STATS_FLAGS_PORT, "tx_late_collisions" }, 455 { STATS_OFFSET32(tx_stat_etherstatscollisions_hi), 456 8, STATS_FLAGS_PORT, "tx_total_collisions" }, 457 { STATS_OFFSET32(tx_stat_etherstatspkts64octets_hi), 458 8, STATS_FLAGS_PORT, "tx_64_byte_packets" }, 459 { STATS_OFFSET32(tx_stat_etherstatspkts65octetsto127octets_hi), 460 8, STATS_FLAGS_PORT, "tx_65_to_127_byte_packets" }, 461 { STATS_OFFSET32(tx_stat_etherstatspkts128octetsto255octets_hi), 462 8, STATS_FLAGS_PORT, "tx_128_to_255_byte_packets" }, 463 { STATS_OFFSET32(tx_stat_etherstatspkts256octetsto511octets_hi), 464 8, STATS_FLAGS_PORT, "tx_256_to_511_byte_packets" }, 465 { STATS_OFFSET32(tx_stat_etherstatspkts512octetsto1023octets_hi), 466 8, STATS_FLAGS_PORT, "tx_512_to_1023_byte_packets" }, 467 { STATS_OFFSET32(etherstatspkts1024octetsto1522octets_hi), 468 8, STATS_FLAGS_PORT, "tx_1024_to_1522_byte_packets" }, 469 { STATS_OFFSET32(etherstatspktsover1522octets_hi), 470 8, STATS_FLAGS_PORT, "tx_1523_to_9022_byte_packets" }, 471 { STATS_OFFSET32(pause_frames_sent_hi), 472 8, STATS_FLAGS_PORT, "tx_pause_frames" }, 473 { STATS_OFFSET32(total_tpa_aggregations_hi), 474 8, STATS_FLAGS_FUNC, "tpa_aggregations" }, 475 { STATS_OFFSET32(total_tpa_aggregated_frames_hi), 476 8, STATS_FLAGS_FUNC, "tpa_aggregated_frames"}, 477 { STATS_OFFSET32(total_tpa_bytes_hi), 478 8, STATS_FLAGS_FUNC, "tpa_bytes"}, 479 #if 0 480 { STATS_OFFSET32(recoverable_error), 481 4, STATS_FLAGS_FUNC, "recoverable_errors" }, 482 { STATS_OFFSET32(unrecoverable_error), 483 4, STATS_FLAGS_FUNC, "unrecoverable_errors" }, 484 #endif 485 { STATS_OFFSET32(eee_tx_lpi), 486 4, STATS_FLAGS_PORT, "eee_tx_lpi"}, 487 { STATS_OFFSET32(rx_calls), 488 4, STATS_FLAGS_FUNC, "rx_calls"}, 489 { STATS_OFFSET32(rx_pkts), 490 4, STATS_FLAGS_FUNC, "rx_pkts"}, 491 { STATS_OFFSET32(rx_tpa_pkts), 492 4, STATS_FLAGS_FUNC, "rx_tpa_pkts"}, 493 { STATS_OFFSET32(rx_soft_errors), 494 4, STATS_FLAGS_FUNC, "rx_soft_errors"}, 495 { STATS_OFFSET32(rx_hw_csum_errors), 496 4, STATS_FLAGS_FUNC, "rx_hw_csum_errors"}, 497 { STATS_OFFSET32(rx_ofld_frames_csum_ip), 498 4, STATS_FLAGS_FUNC, "rx_ofld_frames_csum_ip"}, 499 { STATS_OFFSET32(rx_ofld_frames_csum_tcp_udp), 500 4, STATS_FLAGS_FUNC, "rx_ofld_frames_csum_tcp_udp"}, 501 { STATS_OFFSET32(rx_budget_reached), 502 4, STATS_FLAGS_FUNC, "rx_budget_reached"}, 503 { STATS_OFFSET32(tx_pkts), 504 4, STATS_FLAGS_FUNC, "tx_pkts"}, 505 { STATS_OFFSET32(tx_soft_errors), 506 4, STATS_FLAGS_FUNC, "tx_soft_errors"}, 507 { STATS_OFFSET32(tx_ofld_frames_csum_ip), 508 4, STATS_FLAGS_FUNC, "tx_ofld_frames_csum_ip"}, 509 { STATS_OFFSET32(tx_ofld_frames_csum_tcp), 510 4, STATS_FLAGS_FUNC, "tx_ofld_frames_csum_tcp"}, 511 { STATS_OFFSET32(tx_ofld_frames_csum_udp), 512 4, STATS_FLAGS_FUNC, "tx_ofld_frames_csum_udp"}, 513 { STATS_OFFSET32(tx_ofld_frames_lso), 514 4, STATS_FLAGS_FUNC, "tx_ofld_frames_lso"}, 515 { STATS_OFFSET32(tx_ofld_frames_lso_hdr_splits), 516 4, STATS_FLAGS_FUNC, "tx_ofld_frames_lso_hdr_splits"}, 517 { STATS_OFFSET32(tx_encap_failures), 518 4, STATS_FLAGS_FUNC, "tx_encap_failures"}, 519 { STATS_OFFSET32(tx_hw_queue_full), 520 4, STATS_FLAGS_FUNC, "tx_hw_queue_full"}, 521 { STATS_OFFSET32(tx_hw_max_queue_depth), 522 4, STATS_FLAGS_FUNC, "tx_hw_max_queue_depth"}, 523 { STATS_OFFSET32(tx_dma_mapping_failure), 524 4, STATS_FLAGS_FUNC, "tx_dma_mapping_failure"}, 525 { STATS_OFFSET32(tx_max_drbr_queue_depth), 526 4, STATS_FLAGS_FUNC, "tx_max_drbr_queue_depth"}, 527 { STATS_OFFSET32(tx_window_violation_std), 528 4, STATS_FLAGS_FUNC, "tx_window_violation_std"}, 529 { STATS_OFFSET32(tx_window_violation_tso), 530 4, STATS_FLAGS_FUNC, "tx_window_violation_tso"}, 531 #if 0 532 { STATS_OFFSET32(tx_unsupported_tso_request_ipv6), 533 4, STATS_FLAGS_FUNC, "tx_unsupported_tso_request_ipv6"}, 534 { STATS_OFFSET32(tx_unsupported_tso_request_not_tcp), 535 4, STATS_FLAGS_FUNC, "tx_unsupported_tso_request_not_tcp"}, 536 #endif 537 { STATS_OFFSET32(tx_chain_lost_mbuf), 538 4, STATS_FLAGS_FUNC, "tx_chain_lost_mbuf"}, 539 { STATS_OFFSET32(tx_frames_deferred), 540 4, STATS_FLAGS_FUNC, "tx_frames_deferred"}, 541 { STATS_OFFSET32(tx_queue_xoff), 542 4, STATS_FLAGS_FUNC, "tx_queue_xoff"}, 543 { STATS_OFFSET32(mbuf_defrag_attempts), 544 4, STATS_FLAGS_FUNC, "mbuf_defrag_attempts"}, 545 { STATS_OFFSET32(mbuf_defrag_failures), 546 4, STATS_FLAGS_FUNC, "mbuf_defrag_failures"}, 547 { STATS_OFFSET32(mbuf_rx_bd_alloc_failed), 548 4, STATS_FLAGS_FUNC, "mbuf_rx_bd_alloc_failed"}, 549 { STATS_OFFSET32(mbuf_rx_bd_mapping_failed), 550 4, STATS_FLAGS_FUNC, "mbuf_rx_bd_mapping_failed"}, 551 { STATS_OFFSET32(mbuf_rx_tpa_alloc_failed), 552 4, STATS_FLAGS_FUNC, "mbuf_rx_tpa_alloc_failed"}, 553 { STATS_OFFSET32(mbuf_rx_tpa_mapping_failed), 554 4, STATS_FLAGS_FUNC, "mbuf_rx_tpa_mapping_failed"}, 555 { STATS_OFFSET32(mbuf_rx_sge_alloc_failed), 556 4, STATS_FLAGS_FUNC, "mbuf_rx_sge_alloc_failed"}, 557 { STATS_OFFSET32(mbuf_rx_sge_mapping_failed), 558 4, STATS_FLAGS_FUNC, "mbuf_rx_sge_mapping_failed"}, 559 { STATS_OFFSET32(mbuf_alloc_tx), 560 4, STATS_FLAGS_FUNC, "mbuf_alloc_tx"}, 561 { STATS_OFFSET32(mbuf_alloc_rx), 562 4, STATS_FLAGS_FUNC, "mbuf_alloc_rx"}, 563 { STATS_OFFSET32(mbuf_alloc_sge), 564 4, STATS_FLAGS_FUNC, "mbuf_alloc_sge"}, 565 { STATS_OFFSET32(mbuf_alloc_tpa), 566 4, STATS_FLAGS_FUNC, "mbuf_alloc_tpa"} 567 }; 568 569 static const struct { 570 uint32_t offset; 571 uint32_t size; 572 char string[STAT_NAME_LEN]; 573 } bxe_eth_q_stats_arr[] = { 574 { Q_STATS_OFFSET32(total_bytes_received_hi), 575 8, "rx_bytes" }, 576 { Q_STATS_OFFSET32(total_unicast_packets_received_hi), 577 8, "rx_ucast_packets" }, 578 { Q_STATS_OFFSET32(total_multicast_packets_received_hi), 579 8, "rx_mcast_packets" }, 580 { Q_STATS_OFFSET32(total_broadcast_packets_received_hi), 581 8, "rx_bcast_packets" }, 582 { Q_STATS_OFFSET32(no_buff_discard_hi), 583 8, "rx_discards" }, 584 { Q_STATS_OFFSET32(total_bytes_transmitted_hi), 585 8, "tx_bytes" }, 586 { Q_STATS_OFFSET32(total_unicast_packets_transmitted_hi), 587 8, "tx_ucast_packets" }, 588 { Q_STATS_OFFSET32(total_multicast_packets_transmitted_hi), 589 8, "tx_mcast_packets" }, 590 { Q_STATS_OFFSET32(total_broadcast_packets_transmitted_hi), 591 8, "tx_bcast_packets" }, 592 { Q_STATS_OFFSET32(total_tpa_aggregations_hi), 593 8, "tpa_aggregations" }, 594 { Q_STATS_OFFSET32(total_tpa_aggregated_frames_hi), 595 8, "tpa_aggregated_frames"}, 596 { Q_STATS_OFFSET32(total_tpa_bytes_hi), 597 8, "tpa_bytes"}, 598 { Q_STATS_OFFSET32(rx_calls), 599 4, "rx_calls"}, 600 { Q_STATS_OFFSET32(rx_pkts), 601 4, "rx_pkts"}, 602 { Q_STATS_OFFSET32(rx_tpa_pkts), 603 4, "rx_tpa_pkts"}, 604 { Q_STATS_OFFSET32(rx_soft_errors), 605 4, "rx_soft_errors"}, 606 { Q_STATS_OFFSET32(rx_hw_csum_errors), 607 4, "rx_hw_csum_errors"}, 608 { Q_STATS_OFFSET32(rx_ofld_frames_csum_ip), 609 4, "rx_ofld_frames_csum_ip"}, 610 { Q_STATS_OFFSET32(rx_ofld_frames_csum_tcp_udp), 611 4, "rx_ofld_frames_csum_tcp_udp"}, 612 { Q_STATS_OFFSET32(rx_budget_reached), 613 4, "rx_budget_reached"}, 614 { Q_STATS_OFFSET32(tx_pkts), 615 4, "tx_pkts"}, 616 { Q_STATS_OFFSET32(tx_soft_errors), 617 4, "tx_soft_errors"}, 618 { Q_STATS_OFFSET32(tx_ofld_frames_csum_ip), 619 4, "tx_ofld_frames_csum_ip"}, 620 { Q_STATS_OFFSET32(tx_ofld_frames_csum_tcp), 621 4, "tx_ofld_frames_csum_tcp"}, 622 { Q_STATS_OFFSET32(tx_ofld_frames_csum_udp), 623 4, "tx_ofld_frames_csum_udp"}, 624 { Q_STATS_OFFSET32(tx_ofld_frames_lso), 625 4, "tx_ofld_frames_lso"}, 626 { Q_STATS_OFFSET32(tx_ofld_frames_lso_hdr_splits), 627 4, "tx_ofld_frames_lso_hdr_splits"}, 628 { Q_STATS_OFFSET32(tx_encap_failures), 629 4, "tx_encap_failures"}, 630 { Q_STATS_OFFSET32(tx_hw_queue_full), 631 4, "tx_hw_queue_full"}, 632 { Q_STATS_OFFSET32(tx_hw_max_queue_depth), 633 4, "tx_hw_max_queue_depth"}, 634 { Q_STATS_OFFSET32(tx_dma_mapping_failure), 635 4, "tx_dma_mapping_failure"}, 636 { Q_STATS_OFFSET32(tx_max_drbr_queue_depth), 637 4, "tx_max_drbr_queue_depth"}, 638 { Q_STATS_OFFSET32(tx_window_violation_std), 639 4, "tx_window_violation_std"}, 640 { Q_STATS_OFFSET32(tx_window_violation_tso), 641 4, "tx_window_violation_tso"}, 642 #if 0 643 { Q_STATS_OFFSET32(tx_unsupported_tso_request_ipv6), 644 4, "tx_unsupported_tso_request_ipv6"}, 645 { Q_STATS_OFFSET32(tx_unsupported_tso_request_not_tcp), 646 4, "tx_unsupported_tso_request_not_tcp"}, 647 #endif 648 { Q_STATS_OFFSET32(tx_chain_lost_mbuf), 649 4, "tx_chain_lost_mbuf"}, 650 { Q_STATS_OFFSET32(tx_frames_deferred), 651 4, "tx_frames_deferred"}, 652 { Q_STATS_OFFSET32(tx_queue_xoff), 653 4, "tx_queue_xoff"}, 654 { Q_STATS_OFFSET32(mbuf_defrag_attempts), 655 4, "mbuf_defrag_attempts"}, 656 { Q_STATS_OFFSET32(mbuf_defrag_failures), 657 4, "mbuf_defrag_failures"}, 658 { Q_STATS_OFFSET32(mbuf_rx_bd_alloc_failed), 659 4, "mbuf_rx_bd_alloc_failed"}, 660 { Q_STATS_OFFSET32(mbuf_rx_bd_mapping_failed), 661 4, "mbuf_rx_bd_mapping_failed"}, 662 { Q_STATS_OFFSET32(mbuf_rx_tpa_alloc_failed), 663 4, "mbuf_rx_tpa_alloc_failed"}, 664 { Q_STATS_OFFSET32(mbuf_rx_tpa_mapping_failed), 665 4, "mbuf_rx_tpa_mapping_failed"}, 666 { Q_STATS_OFFSET32(mbuf_rx_sge_alloc_failed), 667 4, "mbuf_rx_sge_alloc_failed"}, 668 { Q_STATS_OFFSET32(mbuf_rx_sge_mapping_failed), 669 4, "mbuf_rx_sge_mapping_failed"}, 670 { Q_STATS_OFFSET32(mbuf_alloc_tx), 671 4, "mbuf_alloc_tx"}, 672 { Q_STATS_OFFSET32(mbuf_alloc_rx), 673 4, "mbuf_alloc_rx"}, 674 { Q_STATS_OFFSET32(mbuf_alloc_sge), 675 4, "mbuf_alloc_sge"}, 676 { Q_STATS_OFFSET32(mbuf_alloc_tpa), 677 4, "mbuf_alloc_tpa"} 678 }; 679 680 #define BXE_NUM_ETH_STATS ARRAY_SIZE(bxe_eth_stats_arr) 681 #define BXE_NUM_ETH_Q_STATS ARRAY_SIZE(bxe_eth_q_stats_arr) 682 683 684 static void bxe_cmng_fns_init(struct bxe_softc *sc, 685 uint8_t read_cfg, 686 uint8_t cmng_type); 687 static int bxe_get_cmng_fns_mode(struct bxe_softc *sc); 688 static void storm_memset_cmng(struct bxe_softc *sc, 689 struct cmng_init *cmng, 690 uint8_t port); 691 static void bxe_set_reset_global(struct bxe_softc *sc); 692 static void bxe_set_reset_in_progress(struct bxe_softc *sc); 693 static uint8_t bxe_reset_is_done(struct bxe_softc *sc, 694 int engine); 695 static uint8_t bxe_clear_pf_load(struct bxe_softc *sc); 696 static uint8_t bxe_chk_parity_attn(struct bxe_softc *sc, 697 uint8_t *global, 698 uint8_t print); 699 static void bxe_int_disable(struct bxe_softc *sc); 700 static int bxe_release_leader_lock(struct bxe_softc *sc); 701 static void bxe_pf_disable(struct bxe_softc *sc); 702 static void bxe_free_fp_buffers(struct bxe_softc *sc); 703 static inline void bxe_update_rx_prod(struct bxe_softc *sc, 704 struct bxe_fastpath *fp, 705 uint16_t rx_bd_prod, 706 uint16_t rx_cq_prod, 707 uint16_t rx_sge_prod); 708 static void bxe_link_report_locked(struct bxe_softc *sc); 709 static void bxe_link_report(struct bxe_softc *sc); 710 static void bxe_link_status_update(struct bxe_softc *sc); 711 static void bxe_periodic_callout_func(void *xsc); 712 static void bxe_periodic_start(struct bxe_softc *sc); 713 static void bxe_periodic_stop(struct bxe_softc *sc); 714 static int bxe_alloc_rx_bd_mbuf(struct bxe_fastpath *fp, 715 uint16_t prev_index, 716 uint16_t index); 717 static int bxe_alloc_rx_tpa_mbuf(struct bxe_fastpath *fp, 718 int queue); 719 static int bxe_alloc_rx_sge_mbuf(struct bxe_fastpath *fp, 720 uint16_t index); 721 static uint8_t bxe_txeof(struct bxe_softc *sc, 722 struct bxe_fastpath *fp); 723 static void bxe_task_fp(struct bxe_fastpath *fp); 724 static __noinline void bxe_dump_mbuf(struct bxe_softc *sc, 725 struct mbuf *m, 726 uint8_t contents); 727 static int bxe_alloc_mem(struct bxe_softc *sc); 728 static void bxe_free_mem(struct bxe_softc *sc); 729 static int bxe_alloc_fw_stats_mem(struct bxe_softc *sc); 730 static void bxe_free_fw_stats_mem(struct bxe_softc *sc); 731 static int bxe_interrupt_attach(struct bxe_softc *sc); 732 static void bxe_interrupt_detach(struct bxe_softc *sc); 733 static void bxe_set_rx_mode(struct bxe_softc *sc); 734 static int bxe_init_locked(struct bxe_softc *sc); 735 static int bxe_stop_locked(struct bxe_softc *sc); 736 static __noinline int bxe_nic_load(struct bxe_softc *sc, 737 int load_mode); 738 static __noinline int bxe_nic_unload(struct bxe_softc *sc, 739 uint32_t unload_mode, 740 uint8_t keep_link); 741 742 static void bxe_handle_sp_tq(void *context, int pending); 743 static void bxe_handle_rx_mode_tq(void *context, int pending); 744 static void bxe_handle_fp_tq(void *context, int pending); 745 746 747 /* calculate crc32 on a buffer (NOTE: crc32_length MUST be aligned to 8) */ 748 uint32_t 749 calc_crc32(uint8_t *crc32_packet, 750 uint32_t crc32_length, 751 uint32_t crc32_seed, 752 uint8_t complement) 753 { 754 uint32_t byte = 0; 755 uint32_t bit = 0; 756 uint8_t msb = 0; 757 uint32_t temp = 0; 758 uint32_t shft = 0; 759 uint8_t current_byte = 0; 760 uint32_t crc32_result = crc32_seed; 761 const uint32_t CRC32_POLY = 0x1edc6f41; 762 763 if ((crc32_packet == NULL) || 764 (crc32_length == 0) || 765 ((crc32_length % 8) != 0)) 766 { 767 return (crc32_result); 768 } 769 770 for (byte = 0; byte < crc32_length; byte = byte + 1) 771 { 772 current_byte = crc32_packet[byte]; 773 for (bit = 0; bit < 8; bit = bit + 1) 774 { 775 /* msb = crc32_result[31]; */ 776 msb = (uint8_t)(crc32_result >> 31); 777 778 crc32_result = crc32_result << 1; 779 780 /* it (msb != current_byte[bit]) */ 781 if (msb != (0x1 & (current_byte >> bit))) 782 { 783 crc32_result = crc32_result ^ CRC32_POLY; 784 /* crc32_result[0] = 1 */ 785 crc32_result |= 1; 786 } 787 } 788 } 789 790 /* Last step is to: 791 * 1. "mirror" every bit 792 * 2. swap the 4 bytes 793 * 3. complement each bit 794 */ 795 796 /* Mirror */ 797 temp = crc32_result; 798 shft = sizeof(crc32_result) * 8 - 1; 799 800 for (crc32_result >>= 1; crc32_result; crc32_result >>= 1) 801 { 802 temp <<= 1; 803 temp |= crc32_result & 1; 804 shft-- ; 805 } 806 807 /* temp[31-bit] = crc32_result[bit] */ 808 temp <<= shft; 809 810 /* Swap */ 811 /* crc32_result = {temp[7:0], temp[15:8], temp[23:16], temp[31:24]} */ 812 { 813 uint32_t t0, t1, t2, t3; 814 t0 = (0x000000ff & (temp >> 24)); 815 t1 = (0x0000ff00 & (temp >> 8)); 816 t2 = (0x00ff0000 & (temp << 8)); 817 t3 = (0xff000000 & (temp << 24)); 818 crc32_result = t0 | t1 | t2 | t3; 819 } 820 821 /* Complement */ 822 if (complement) 823 { 824 crc32_result = ~crc32_result; 825 } 826 827 return (crc32_result); 828 } 829 830 int 831 bxe_test_bit(int nr, 832 volatile unsigned long *addr) 833 { 834 return ((atomic_load_acq_long(addr) & (1 << nr)) != 0); 835 } 836 837 void 838 bxe_set_bit(unsigned int nr, 839 volatile unsigned long *addr) 840 { 841 atomic_set_acq_long(addr, (1 << nr)); 842 } 843 844 void 845 bxe_clear_bit(int nr, 846 volatile unsigned long *addr) 847 { 848 atomic_clear_acq_long(addr, (1 << nr)); 849 } 850 851 int 852 bxe_test_and_set_bit(int nr, 853 volatile unsigned long *addr) 854 { 855 unsigned long x; 856 nr = (1 << nr); 857 do { 858 x = *addr; 859 } while (atomic_cmpset_acq_long(addr, x, x | nr) == 0); 860 // if (x & nr) bit_was_set; else bit_was_not_set; 861 return (x & nr); 862 } 863 864 int 865 bxe_test_and_clear_bit(int nr, 866 volatile unsigned long *addr) 867 { 868 unsigned long x; 869 nr = (1 << nr); 870 do { 871 x = *addr; 872 } while (atomic_cmpset_acq_long(addr, x, x & ~nr) == 0); 873 // if (x & nr) bit_was_set; else bit_was_not_set; 874 return (x & nr); 875 } 876 877 int 878 bxe_cmpxchg(volatile int *addr, 879 int old, 880 int new) 881 { 882 int x; 883 do { 884 x = *addr; 885 } while (atomic_cmpset_acq_int(addr, old, new) == 0); 886 return (x); 887 } 888 889 /* 890 * Get DMA memory from the OS. 891 * 892 * Validates that the OS has provided DMA buffers in response to a 893 * bus_dmamap_load call and saves the physical address of those buffers. 894 * When the callback is used the OS will return 0 for the mapping function 895 * (bus_dmamap_load) so we use the value of map_arg->maxsegs to pass any 896 * failures back to the caller. 897 * 898 * Returns: 899 * Nothing. 900 */ 901 static void 902 bxe_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 903 { 904 struct bxe_dma *dma = arg; 905 906 if (error) { 907 dma->paddr = 0; 908 dma->nseg = 0; 909 BLOGE(dma->sc, "Failed DMA alloc '%s' (%d)!\n", dma->msg, error); 910 } else { 911 dma->paddr = segs->ds_addr; 912 dma->nseg = nseg; 913 #if 0 914 BLOGD(dma->sc, DBG_LOAD,, 915 "DMA alloc '%s': vaddr=%p paddr=%p nseg=%d size=%lu\n", 916 dma->msg, dma->vaddr, (void *)dma->paddr, 917 dma->nseg, dma->size); 918 #endif 919 } 920 } 921 922 /* 923 * Allocate a block of memory and map it for DMA. No partial completions 924 * allowed and release any resources acquired if we can't acquire all 925 * resources. 926 * 927 * Returns: 928 * 0 = Success, !0 = Failure 929 */ 930 int 931 bxe_dma_alloc(struct bxe_softc *sc, 932 bus_size_t size, 933 struct bxe_dma *dma, 934 const char *msg) 935 { 936 int rc; 937 938 if (dma->size > 0) { 939 BLOGE(sc, "dma block '%s' already has size %lu\n", msg, 940 (unsigned long)dma->size); 941 return (1); 942 } 943 944 memset(dma, 0, sizeof(*dma)); /* sanity */ 945 dma->sc = sc; 946 dma->size = size; 947 snprintf(dma->msg, sizeof(dma->msg), "%s", msg); 948 949 rc = bus_dma_tag_create(sc->parent_dma_tag, /* parent tag */ 950 BCM_PAGE_SIZE, /* alignment */ 951 0, /* boundary limit */ 952 BUS_SPACE_MAXADDR, /* restricted low */ 953 BUS_SPACE_MAXADDR, /* restricted hi */ 954 NULL, /* addr filter() */ 955 NULL, /* addr filter() arg */ 956 size, /* max map size */ 957 1, /* num discontinuous */ 958 size, /* max seg size */ 959 BUS_DMA_ALLOCNOW, /* flags */ 960 NULL, /* lock() */ 961 NULL, /* lock() arg */ 962 &dma->tag); /* returned dma tag */ 963 if (rc != 0) { 964 BLOGE(sc, "Failed to create dma tag for '%s' (%d)\n", msg, rc); 965 memset(dma, 0, sizeof(*dma)); 966 return (1); 967 } 968 969 rc = bus_dmamem_alloc(dma->tag, 970 (void **)&dma->vaddr, 971 (BUS_DMA_NOWAIT | BUS_DMA_ZERO), 972 &dma->map); 973 if (rc != 0) { 974 BLOGE(sc, "Failed to alloc dma mem for '%s' (%d)\n", msg, rc); 975 bus_dma_tag_destroy(dma->tag); 976 memset(dma, 0, sizeof(*dma)); 977 return (1); 978 } 979 980 rc = bus_dmamap_load(dma->tag, 981 dma->map, 982 dma->vaddr, 983 size, 984 bxe_dma_map_addr, /* BLOGD in here */ 985 dma, 986 BUS_DMA_NOWAIT); 987 if (rc != 0) { 988 BLOGE(sc, "Failed to load dma map for '%s' (%d)\n", msg, rc); 989 bus_dmamem_free(dma->tag, dma->vaddr, dma->map); 990 bus_dma_tag_destroy(dma->tag); 991 memset(dma, 0, sizeof(*dma)); 992 return (1); 993 } 994 995 return (0); 996 } 997 998 void 999 bxe_dma_free(struct bxe_softc *sc, 1000 struct bxe_dma *dma) 1001 { 1002 if (dma->size > 0) { 1003 #if 0 1004 BLOGD(sc, DBG_LOAD, 1005 "DMA free '%s': vaddr=%p paddr=%p nseg=%d size=%lu\n", 1006 dma->msg, dma->vaddr, (void *)dma->paddr, 1007 dma->nseg, dma->size); 1008 #endif 1009 1010 DBASSERT(sc, (dma->tag != NULL), ("dma tag is NULL")); 1011 1012 bus_dmamap_sync(dma->tag, dma->map, 1013 (BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE)); 1014 bus_dmamap_unload(dma->tag, dma->map); 1015 bus_dmamem_free(dma->tag, dma->vaddr, dma->map); 1016 bus_dma_tag_destroy(dma->tag); 1017 } 1018 1019 memset(dma, 0, sizeof(*dma)); 1020 } 1021 1022 /* 1023 * These indirect read and write routines are only during init. 1024 * The locking is handled by the MCP. 1025 */ 1026 1027 void 1028 bxe_reg_wr_ind(struct bxe_softc *sc, 1029 uint32_t addr, 1030 uint32_t val) 1031 { 1032 pci_write_config(sc->dev, PCICFG_GRC_ADDRESS, addr, 4); 1033 pci_write_config(sc->dev, PCICFG_GRC_DATA, val, 4); 1034 pci_write_config(sc->dev, PCICFG_GRC_ADDRESS, 0, 4); 1035 } 1036 1037 uint32_t 1038 bxe_reg_rd_ind(struct bxe_softc *sc, 1039 uint32_t addr) 1040 { 1041 uint32_t val; 1042 1043 pci_write_config(sc->dev, PCICFG_GRC_ADDRESS, addr, 4); 1044 val = pci_read_config(sc->dev, PCICFG_GRC_DATA, 4); 1045 pci_write_config(sc->dev, PCICFG_GRC_ADDRESS, 0, 4); 1046 1047 return (val); 1048 } 1049 1050 #if 0 1051 void bxe_dp_dmae(struct bxe_softc *sc, struct dmae_command *dmae, int msglvl) 1052 { 1053 uint32_t src_type = dmae->opcode & DMAE_COMMAND_SRC; 1054 1055 switch (dmae->opcode & DMAE_COMMAND_DST) { 1056 case DMAE_CMD_DST_PCI: 1057 if (src_type == DMAE_CMD_SRC_PCI) 1058 DP(msglvl, "DMAE: opcode 0x%08x\n" 1059 "src [%x:%08x], len [%d*4], dst [%x:%08x]\n" 1060 "comp_addr [%x:%08x], comp_val 0x%08x\n", 1061 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo, 1062 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo, 1063 dmae->comp_addr_hi, dmae->comp_addr_lo, 1064 dmae->comp_val); 1065 else 1066 DP(msglvl, "DMAE: opcode 0x%08x\n" 1067 "src [%08x], len [%d*4], dst [%x:%08x]\n" 1068 "comp_addr [%x:%08x], comp_val 0x%08x\n", 1069 dmae->opcode, dmae->src_addr_lo >> 2, 1070 dmae->len, dmae->dst_addr_hi, dmae->dst_addr_lo, 1071 dmae->comp_addr_hi, dmae->comp_addr_lo, 1072 dmae->comp_val); 1073 break; 1074 case DMAE_CMD_DST_GRC: 1075 if (src_type == DMAE_CMD_SRC_PCI) 1076 DP(msglvl, "DMAE: opcode 0x%08x\n" 1077 "src [%x:%08x], len [%d*4], dst_addr [%08x]\n" 1078 "comp_addr [%x:%08x], comp_val 0x%08x\n", 1079 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo, 1080 dmae->len, dmae->dst_addr_lo >> 2, 1081 dmae->comp_addr_hi, dmae->comp_addr_lo, 1082 dmae->comp_val); 1083 else 1084 DP(msglvl, "DMAE: opcode 0x%08x\n" 1085 "src [%08x], len [%d*4], dst [%08x]\n" 1086 "comp_addr [%x:%08x], comp_val 0x%08x\n", 1087 dmae->opcode, dmae->src_addr_lo >> 2, 1088 dmae->len, dmae->dst_addr_lo >> 2, 1089 dmae->comp_addr_hi, dmae->comp_addr_lo, 1090 dmae->comp_val); 1091 break; 1092 default: 1093 if (src_type == DMAE_CMD_SRC_PCI) 1094 DP(msglvl, "DMAE: opcode 0x%08x\n" 1095 "src_addr [%x:%08x] len [%d * 4] dst_addr [none]\n" 1096 "comp_addr [%x:%08x] comp_val 0x%08x\n", 1097 dmae->opcode, dmae->src_addr_hi, dmae->src_addr_lo, 1098 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo, 1099 dmae->comp_val); 1100 else 1101 DP(msglvl, "DMAE: opcode 0x%08x\n" 1102 "src_addr [%08x] len [%d * 4] dst_addr [none]\n" 1103 "comp_addr [%x:%08x] comp_val 0x%08x\n", 1104 dmae->opcode, dmae->src_addr_lo >> 2, 1105 dmae->len, dmae->comp_addr_hi, dmae->comp_addr_lo, 1106 dmae->comp_val); 1107 break; 1108 } 1109 1110 } 1111 #endif 1112 1113 static int 1114 bxe_acquire_hw_lock(struct bxe_softc *sc, 1115 uint32_t resource) 1116 { 1117 uint32_t lock_status; 1118 uint32_t resource_bit = (1 << resource); 1119 int func = SC_FUNC(sc); 1120 uint32_t hw_lock_control_reg; 1121 int cnt; 1122 1123 /* validate the resource is within range */ 1124 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { 1125 BLOGE(sc, "resource 0x%x > HW_LOCK_MAX_RESOURCE_VALUE\n", resource); 1126 return (-1); 1127 } 1128 1129 if (func <= 5) { 1130 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + (func * 8)); 1131 } else { 1132 hw_lock_control_reg = 1133 (MISC_REG_DRIVER_CONTROL_7 + ((func - 6) * 8)); 1134 } 1135 1136 /* validate the resource is not already taken */ 1137 lock_status = REG_RD(sc, hw_lock_control_reg); 1138 if (lock_status & resource_bit) { 1139 BLOGE(sc, "resource in use (status 0x%x bit 0x%x)\n", 1140 lock_status, resource_bit); 1141 return (-1); 1142 } 1143 1144 /* try every 5ms for 5 seconds */ 1145 for (cnt = 0; cnt < 1000; cnt++) { 1146 REG_WR(sc, (hw_lock_control_reg + 4), resource_bit); 1147 lock_status = REG_RD(sc, hw_lock_control_reg); 1148 if (lock_status & resource_bit) { 1149 return (0); 1150 } 1151 DELAY(5000); 1152 } 1153 1154 BLOGE(sc, "Resource lock timeout!\n"); 1155 return (-1); 1156 } 1157 1158 static int 1159 bxe_release_hw_lock(struct bxe_softc *sc, 1160 uint32_t resource) 1161 { 1162 uint32_t lock_status; 1163 uint32_t resource_bit = (1 << resource); 1164 int func = SC_FUNC(sc); 1165 uint32_t hw_lock_control_reg; 1166 1167 /* validate the resource is within range */ 1168 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { 1169 BLOGE(sc, "resource 0x%x > HW_LOCK_MAX_RESOURCE_VALUE\n", resource); 1170 return (-1); 1171 } 1172 1173 if (func <= 5) { 1174 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + (func * 8)); 1175 } else { 1176 hw_lock_control_reg = 1177 (MISC_REG_DRIVER_CONTROL_7 + ((func - 6) * 8)); 1178 } 1179 1180 /* validate the resource is currently taken */ 1181 lock_status = REG_RD(sc, hw_lock_control_reg); 1182 if (!(lock_status & resource_bit)) { 1183 BLOGE(sc, "resource not in use (status 0x%x bit 0x%x)\n", 1184 lock_status, resource_bit); 1185 return (-1); 1186 } 1187 1188 REG_WR(sc, hw_lock_control_reg, resource_bit); 1189 return (0); 1190 } 1191 1192 /* 1193 * Per pf misc lock must be acquired before the per port mcp lock. Otherwise, 1194 * had we done things the other way around, if two pfs from the same port 1195 * would attempt to access nvram at the same time, we could run into a 1196 * scenario such as: 1197 * pf A takes the port lock. 1198 * pf B succeeds in taking the same lock since they are from the same port. 1199 * pf A takes the per pf misc lock. Performs eeprom access. 1200 * pf A finishes. Unlocks the per pf misc lock. 1201 * Pf B takes the lock and proceeds to perform it's own access. 1202 * pf A unlocks the per port lock, while pf B is still working (!). 1203 * mcp takes the per port lock and corrupts pf B's access (and/or has it's own 1204 * access corrupted by pf B).* 1205 */ 1206 static int 1207 bxe_acquire_nvram_lock(struct bxe_softc *sc) 1208 { 1209 int port = SC_PORT(sc); 1210 int count, i; 1211 uint32_t val = 0; 1212 1213 /* acquire HW lock: protect against other PFs in PF Direct Assignment */ 1214 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_NVRAM); 1215 1216 /* adjust timeout for emulation/FPGA */ 1217 count = NVRAM_TIMEOUT_COUNT; 1218 if (CHIP_REV_IS_SLOW(sc)) { 1219 count *= 100; 1220 } 1221 1222 /* request access to nvram interface */ 1223 REG_WR(sc, MCP_REG_MCPR_NVM_SW_ARB, 1224 (MCPR_NVM_SW_ARB_ARB_REQ_SET1 << port)); 1225 1226 for (i = 0; i < count*10; i++) { 1227 val = REG_RD(sc, MCP_REG_MCPR_NVM_SW_ARB); 1228 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) { 1229 break; 1230 } 1231 1232 DELAY(5); 1233 } 1234 1235 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) { 1236 BLOGE(sc, "Cannot get access to nvram interface\n"); 1237 return (-1); 1238 } 1239 1240 return (0); 1241 } 1242 1243 static int 1244 bxe_release_nvram_lock(struct bxe_softc *sc) 1245 { 1246 int port = SC_PORT(sc); 1247 int count, i; 1248 uint32_t val = 0; 1249 1250 /* adjust timeout for emulation/FPGA */ 1251 count = NVRAM_TIMEOUT_COUNT; 1252 if (CHIP_REV_IS_SLOW(sc)) { 1253 count *= 100; 1254 } 1255 1256 /* relinquish nvram interface */ 1257 REG_WR(sc, MCP_REG_MCPR_NVM_SW_ARB, 1258 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << port)); 1259 1260 for (i = 0; i < count*10; i++) { 1261 val = REG_RD(sc, MCP_REG_MCPR_NVM_SW_ARB); 1262 if (!(val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port))) { 1263 break; 1264 } 1265 1266 DELAY(5); 1267 } 1268 1269 if (val & (MCPR_NVM_SW_ARB_ARB_ARB1 << port)) { 1270 BLOGE(sc, "Cannot free access to nvram interface\n"); 1271 return (-1); 1272 } 1273 1274 /* release HW lock: protect against other PFs in PF Direct Assignment */ 1275 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_NVRAM); 1276 1277 return (0); 1278 } 1279 1280 static void 1281 bxe_enable_nvram_access(struct bxe_softc *sc) 1282 { 1283 uint32_t val; 1284 1285 val = REG_RD(sc, MCP_REG_MCPR_NVM_ACCESS_ENABLE); 1286 1287 /* enable both bits, even on read */ 1288 REG_WR(sc, MCP_REG_MCPR_NVM_ACCESS_ENABLE, 1289 (val | MCPR_NVM_ACCESS_ENABLE_EN | MCPR_NVM_ACCESS_ENABLE_WR_EN)); 1290 } 1291 1292 static void 1293 bxe_disable_nvram_access(struct bxe_softc *sc) 1294 { 1295 uint32_t val; 1296 1297 val = REG_RD(sc, MCP_REG_MCPR_NVM_ACCESS_ENABLE); 1298 1299 /* disable both bits, even after read */ 1300 REG_WR(sc, MCP_REG_MCPR_NVM_ACCESS_ENABLE, 1301 (val & ~(MCPR_NVM_ACCESS_ENABLE_EN | 1302 MCPR_NVM_ACCESS_ENABLE_WR_EN))); 1303 } 1304 1305 static int 1306 bxe_nvram_read_dword(struct bxe_softc *sc, 1307 uint32_t offset, 1308 uint32_t *ret_val, 1309 uint32_t cmd_flags) 1310 { 1311 int count, i, rc; 1312 uint32_t val; 1313 1314 /* build the command word */ 1315 cmd_flags |= MCPR_NVM_COMMAND_DOIT; 1316 1317 /* need to clear DONE bit separately */ 1318 REG_WR(sc, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE); 1319 1320 /* address of the NVRAM to read from */ 1321 REG_WR(sc, MCP_REG_MCPR_NVM_ADDR, 1322 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE)); 1323 1324 /* issue a read command */ 1325 REG_WR(sc, MCP_REG_MCPR_NVM_COMMAND, cmd_flags); 1326 1327 /* adjust timeout for emulation/FPGA */ 1328 count = NVRAM_TIMEOUT_COUNT; 1329 if (CHIP_REV_IS_SLOW(sc)) { 1330 count *= 100; 1331 } 1332 1333 /* wait for completion */ 1334 *ret_val = 0; 1335 rc = -1; 1336 for (i = 0; i < count; i++) { 1337 DELAY(5); 1338 val = REG_RD(sc, MCP_REG_MCPR_NVM_COMMAND); 1339 1340 if (val & MCPR_NVM_COMMAND_DONE) { 1341 val = REG_RD(sc, MCP_REG_MCPR_NVM_READ); 1342 /* we read nvram data in cpu order 1343 * but ethtool sees it as an array of bytes 1344 * converting to big-endian will do the work 1345 */ 1346 *ret_val = htobe32(val); 1347 rc = 0; 1348 break; 1349 } 1350 } 1351 1352 if (rc == -1) { 1353 BLOGE(sc, "nvram read timeout expired\n"); 1354 } 1355 1356 return (rc); 1357 } 1358 1359 static int 1360 bxe_nvram_read(struct bxe_softc *sc, 1361 uint32_t offset, 1362 uint8_t *ret_buf, 1363 int buf_size) 1364 { 1365 uint32_t cmd_flags; 1366 uint32_t val; 1367 int rc; 1368 1369 if ((offset & 0x03) || (buf_size & 0x03) || (buf_size == 0)) { 1370 BLOGE(sc, "Invalid parameter, offset 0x%x buf_size 0x%x\n", 1371 offset, buf_size); 1372 return (-1); 1373 } 1374 1375 if ((offset + buf_size) > sc->devinfo.flash_size) { 1376 BLOGE(sc, "Invalid parameter, " 1377 "offset 0x%x + buf_size 0x%x > flash_size 0x%x\n", 1378 offset, buf_size, sc->devinfo.flash_size); 1379 return (-1); 1380 } 1381 1382 /* request access to nvram interface */ 1383 rc = bxe_acquire_nvram_lock(sc); 1384 if (rc) { 1385 return (rc); 1386 } 1387 1388 /* enable access to nvram interface */ 1389 bxe_enable_nvram_access(sc); 1390 1391 /* read the first word(s) */ 1392 cmd_flags = MCPR_NVM_COMMAND_FIRST; 1393 while ((buf_size > sizeof(uint32_t)) && (rc == 0)) { 1394 rc = bxe_nvram_read_dword(sc, offset, &val, cmd_flags); 1395 memcpy(ret_buf, &val, 4); 1396 1397 /* advance to the next dword */ 1398 offset += sizeof(uint32_t); 1399 ret_buf += sizeof(uint32_t); 1400 buf_size -= sizeof(uint32_t); 1401 cmd_flags = 0; 1402 } 1403 1404 if (rc == 0) { 1405 cmd_flags |= MCPR_NVM_COMMAND_LAST; 1406 rc = bxe_nvram_read_dword(sc, offset, &val, cmd_flags); 1407 memcpy(ret_buf, &val, 4); 1408 } 1409 1410 /* disable access to nvram interface */ 1411 bxe_disable_nvram_access(sc); 1412 bxe_release_nvram_lock(sc); 1413 1414 return (rc); 1415 } 1416 1417 static int 1418 bxe_nvram_write_dword(struct bxe_softc *sc, 1419 uint32_t offset, 1420 uint32_t val, 1421 uint32_t cmd_flags) 1422 { 1423 int count, i, rc; 1424 1425 /* build the command word */ 1426 cmd_flags |= (MCPR_NVM_COMMAND_DOIT | MCPR_NVM_COMMAND_WR); 1427 1428 /* need to clear DONE bit separately */ 1429 REG_WR(sc, MCP_REG_MCPR_NVM_COMMAND, MCPR_NVM_COMMAND_DONE); 1430 1431 /* write the data */ 1432 REG_WR(sc, MCP_REG_MCPR_NVM_WRITE, val); 1433 1434 /* address of the NVRAM to write to */ 1435 REG_WR(sc, MCP_REG_MCPR_NVM_ADDR, 1436 (offset & MCPR_NVM_ADDR_NVM_ADDR_VALUE)); 1437 1438 /* issue the write command */ 1439 REG_WR(sc, MCP_REG_MCPR_NVM_COMMAND, cmd_flags); 1440 1441 /* adjust timeout for emulation/FPGA */ 1442 count = NVRAM_TIMEOUT_COUNT; 1443 if (CHIP_REV_IS_SLOW(sc)) { 1444 count *= 100; 1445 } 1446 1447 /* wait for completion */ 1448 rc = -1; 1449 for (i = 0; i < count; i++) { 1450 DELAY(5); 1451 val = REG_RD(sc, MCP_REG_MCPR_NVM_COMMAND); 1452 if (val & MCPR_NVM_COMMAND_DONE) { 1453 rc = 0; 1454 break; 1455 } 1456 } 1457 1458 if (rc == -1) { 1459 BLOGE(sc, "nvram write timeout expired\n"); 1460 } 1461 1462 return (rc); 1463 } 1464 1465 #define BYTE_OFFSET(offset) (8 * (offset & 0x03)) 1466 1467 static int 1468 bxe_nvram_write1(struct bxe_softc *sc, 1469 uint32_t offset, 1470 uint8_t *data_buf, 1471 int buf_size) 1472 { 1473 uint32_t cmd_flags; 1474 uint32_t align_offset; 1475 uint32_t val; 1476 int rc; 1477 1478 if ((offset + buf_size) > sc->devinfo.flash_size) { 1479 BLOGE(sc, "Invalid parameter, " 1480 "offset 0x%x + buf_size 0x%x > flash_size 0x%x\n", 1481 offset, buf_size, sc->devinfo.flash_size); 1482 return (-1); 1483 } 1484 1485 /* request access to nvram interface */ 1486 rc = bxe_acquire_nvram_lock(sc); 1487 if (rc) { 1488 return (rc); 1489 } 1490 1491 /* enable access to nvram interface */ 1492 bxe_enable_nvram_access(sc); 1493 1494 cmd_flags = (MCPR_NVM_COMMAND_FIRST | MCPR_NVM_COMMAND_LAST); 1495 align_offset = (offset & ~0x03); 1496 rc = bxe_nvram_read_dword(sc, align_offset, &val, cmd_flags); 1497 1498 if (rc == 0) { 1499 val &= ~(0xff << BYTE_OFFSET(offset)); 1500 val |= (*data_buf << BYTE_OFFSET(offset)); 1501 1502 /* nvram data is returned as an array of bytes 1503 * convert it back to cpu order 1504 */ 1505 val = be32toh(val); 1506 1507 rc = bxe_nvram_write_dword(sc, align_offset, val, cmd_flags); 1508 } 1509 1510 /* disable access to nvram interface */ 1511 bxe_disable_nvram_access(sc); 1512 bxe_release_nvram_lock(sc); 1513 1514 return (rc); 1515 } 1516 1517 static int 1518 bxe_nvram_write(struct bxe_softc *sc, 1519 uint32_t offset, 1520 uint8_t *data_buf, 1521 int buf_size) 1522 { 1523 uint32_t cmd_flags; 1524 uint32_t val; 1525 uint32_t written_so_far; 1526 int rc; 1527 1528 if (buf_size == 1) { 1529 return (bxe_nvram_write1(sc, offset, data_buf, buf_size)); 1530 } 1531 1532 if ((offset & 0x03) || (buf_size & 0x03) /* || (buf_size == 0) */) { 1533 BLOGE(sc, "Invalid parameter, offset 0x%x buf_size 0x%x\n", 1534 offset, buf_size); 1535 return (-1); 1536 } 1537 1538 if (buf_size == 0) { 1539 return (0); /* nothing to do */ 1540 } 1541 1542 if ((offset + buf_size) > sc->devinfo.flash_size) { 1543 BLOGE(sc, "Invalid parameter, " 1544 "offset 0x%x + buf_size 0x%x > flash_size 0x%x\n", 1545 offset, buf_size, sc->devinfo.flash_size); 1546 return (-1); 1547 } 1548 1549 /* request access to nvram interface */ 1550 rc = bxe_acquire_nvram_lock(sc); 1551 if (rc) { 1552 return (rc); 1553 } 1554 1555 /* enable access to nvram interface */ 1556 bxe_enable_nvram_access(sc); 1557 1558 written_so_far = 0; 1559 cmd_flags = MCPR_NVM_COMMAND_FIRST; 1560 while ((written_so_far < buf_size) && (rc == 0)) { 1561 if (written_so_far == (buf_size - sizeof(uint32_t))) { 1562 cmd_flags |= MCPR_NVM_COMMAND_LAST; 1563 } else if (((offset + 4) % NVRAM_PAGE_SIZE) == 0) { 1564 cmd_flags |= MCPR_NVM_COMMAND_LAST; 1565 } else if ((offset % NVRAM_PAGE_SIZE) == 0) { 1566 cmd_flags |= MCPR_NVM_COMMAND_FIRST; 1567 } 1568 1569 memcpy(&val, data_buf, 4); 1570 1571 rc = bxe_nvram_write_dword(sc, offset, val, cmd_flags); 1572 1573 /* advance to the next dword */ 1574 offset += sizeof(uint32_t); 1575 data_buf += sizeof(uint32_t); 1576 written_so_far += sizeof(uint32_t); 1577 cmd_flags = 0; 1578 } 1579 1580 /* disable access to nvram interface */ 1581 bxe_disable_nvram_access(sc); 1582 bxe_release_nvram_lock(sc); 1583 1584 return (rc); 1585 } 1586 1587 /* copy command into DMAE command memory and set DMAE command Go */ 1588 void 1589 bxe_post_dmae(struct bxe_softc *sc, 1590 struct dmae_command *dmae, 1591 int idx) 1592 { 1593 uint32_t cmd_offset; 1594 int i; 1595 1596 cmd_offset = (DMAE_REG_CMD_MEM + (sizeof(struct dmae_command) * idx)); 1597 for (i = 0; i < ((sizeof(struct dmae_command) / 4)); i++) { 1598 REG_WR(sc, (cmd_offset + (i * 4)), *(((uint32_t *)dmae) + i)); 1599 } 1600 1601 REG_WR(sc, dmae_reg_go_c[idx], 1); 1602 } 1603 1604 uint32_t 1605 bxe_dmae_opcode_add_comp(uint32_t opcode, 1606 uint8_t comp_type) 1607 { 1608 return (opcode | ((comp_type << DMAE_COMMAND_C_DST_SHIFT) | 1609 DMAE_COMMAND_C_TYPE_ENABLE)); 1610 } 1611 1612 uint32_t 1613 bxe_dmae_opcode_clr_src_reset(uint32_t opcode) 1614 { 1615 return (opcode & ~DMAE_COMMAND_SRC_RESET); 1616 } 1617 1618 uint32_t 1619 bxe_dmae_opcode(struct bxe_softc *sc, 1620 uint8_t src_type, 1621 uint8_t dst_type, 1622 uint8_t with_comp, 1623 uint8_t comp_type) 1624 { 1625 uint32_t opcode = 0; 1626 1627 opcode |= ((src_type << DMAE_COMMAND_SRC_SHIFT) | 1628 (dst_type << DMAE_COMMAND_DST_SHIFT)); 1629 1630 opcode |= (DMAE_COMMAND_SRC_RESET | DMAE_COMMAND_DST_RESET); 1631 1632 opcode |= (SC_PORT(sc) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0); 1633 1634 opcode |= ((SC_VN(sc) << DMAE_COMMAND_E1HVN_SHIFT) | 1635 (SC_VN(sc) << DMAE_COMMAND_DST_VN_SHIFT)); 1636 1637 opcode |= (DMAE_COM_SET_ERR << DMAE_COMMAND_ERR_POLICY_SHIFT); 1638 1639 #ifdef __BIG_ENDIAN 1640 opcode |= DMAE_CMD_ENDIANITY_B_DW_SWAP; 1641 #else 1642 opcode |= DMAE_CMD_ENDIANITY_DW_SWAP; 1643 #endif 1644 1645 if (with_comp) { 1646 opcode = bxe_dmae_opcode_add_comp(opcode, comp_type); 1647 } 1648 1649 return (opcode); 1650 } 1651 1652 static void 1653 bxe_prep_dmae_with_comp(struct bxe_softc *sc, 1654 struct dmae_command *dmae, 1655 uint8_t src_type, 1656 uint8_t dst_type) 1657 { 1658 memset(dmae, 0, sizeof(struct dmae_command)); 1659 1660 /* set the opcode */ 1661 dmae->opcode = bxe_dmae_opcode(sc, src_type, dst_type, 1662 TRUE, DMAE_COMP_PCI); 1663 1664 /* fill in the completion parameters */ 1665 dmae->comp_addr_lo = U64_LO(BXE_SP_MAPPING(sc, wb_comp)); 1666 dmae->comp_addr_hi = U64_HI(BXE_SP_MAPPING(sc, wb_comp)); 1667 dmae->comp_val = DMAE_COMP_VAL; 1668 } 1669 1670 /* issue a DMAE command over the init channel and wait for completion */ 1671 static int 1672 bxe_issue_dmae_with_comp(struct bxe_softc *sc, 1673 struct dmae_command *dmae) 1674 { 1675 uint32_t *wb_comp = BXE_SP(sc, wb_comp); 1676 int timeout = CHIP_REV_IS_SLOW(sc) ? 400000 : 4000; 1677 1678 BXE_DMAE_LOCK(sc); 1679 1680 /* reset completion */ 1681 *wb_comp = 0; 1682 1683 /* post the command on the channel used for initializations */ 1684 bxe_post_dmae(sc, dmae, INIT_DMAE_C(sc)); 1685 1686 /* wait for completion */ 1687 DELAY(5); 1688 1689 while ((*wb_comp & ~DMAE_PCI_ERR_FLAG) != DMAE_COMP_VAL) { 1690 if (!timeout || 1691 (sc->recovery_state != BXE_RECOVERY_DONE && 1692 sc->recovery_state != BXE_RECOVERY_NIC_LOADING)) { 1693 BLOGE(sc, "DMAE timeout!\n"); 1694 BXE_DMAE_UNLOCK(sc); 1695 return (DMAE_TIMEOUT); 1696 } 1697 1698 timeout--; 1699 DELAY(50); 1700 } 1701 1702 if (*wb_comp & DMAE_PCI_ERR_FLAG) { 1703 BLOGE(sc, "DMAE PCI error!\n"); 1704 BXE_DMAE_UNLOCK(sc); 1705 return (DMAE_PCI_ERROR); 1706 } 1707 1708 BXE_DMAE_UNLOCK(sc); 1709 return (0); 1710 } 1711 1712 void 1713 bxe_read_dmae(struct bxe_softc *sc, 1714 uint32_t src_addr, 1715 uint32_t len32) 1716 { 1717 struct dmae_command dmae; 1718 uint32_t *data; 1719 int i, rc; 1720 1721 DBASSERT(sc, (len32 <= 4), ("DMAE read length is %d", len32)); 1722 1723 if (!sc->dmae_ready) { 1724 data = BXE_SP(sc, wb_data[0]); 1725 1726 for (i = 0; i < len32; i++) { 1727 data[i] = (CHIP_IS_E1(sc)) ? 1728 bxe_reg_rd_ind(sc, (src_addr + (i * 4))) : 1729 REG_RD(sc, (src_addr + (i * 4))); 1730 } 1731 1732 return; 1733 } 1734 1735 /* set opcode and fixed command fields */ 1736 bxe_prep_dmae_with_comp(sc, &dmae, DMAE_SRC_GRC, DMAE_DST_PCI); 1737 1738 /* fill in addresses and len */ 1739 dmae.src_addr_lo = (src_addr >> 2); /* GRC addr has dword resolution */ 1740 dmae.src_addr_hi = 0; 1741 dmae.dst_addr_lo = U64_LO(BXE_SP_MAPPING(sc, wb_data)); 1742 dmae.dst_addr_hi = U64_HI(BXE_SP_MAPPING(sc, wb_data)); 1743 dmae.len = len32; 1744 1745 /* issue the command and wait for completion */ 1746 if ((rc = bxe_issue_dmae_with_comp(sc, &dmae)) != 0) { 1747 bxe_panic(sc, ("DMAE failed (%d)\n", rc)); 1748 }; 1749 } 1750 1751 void 1752 bxe_write_dmae(struct bxe_softc *sc, 1753 bus_addr_t dma_addr, 1754 uint32_t dst_addr, 1755 uint32_t len32) 1756 { 1757 struct dmae_command dmae; 1758 int rc; 1759 1760 if (!sc->dmae_ready) { 1761 DBASSERT(sc, (len32 <= 4), ("DMAE not ready and length is %d", len32)); 1762 1763 if (CHIP_IS_E1(sc)) { 1764 ecore_init_ind_wr(sc, dst_addr, BXE_SP(sc, wb_data[0]), len32); 1765 } else { 1766 ecore_init_str_wr(sc, dst_addr, BXE_SP(sc, wb_data[0]), len32); 1767 } 1768 1769 return; 1770 } 1771 1772 /* set opcode and fixed command fields */ 1773 bxe_prep_dmae_with_comp(sc, &dmae, DMAE_SRC_PCI, DMAE_DST_GRC); 1774 1775 /* fill in addresses and len */ 1776 dmae.src_addr_lo = U64_LO(dma_addr); 1777 dmae.src_addr_hi = U64_HI(dma_addr); 1778 dmae.dst_addr_lo = (dst_addr >> 2); /* GRC addr has dword resolution */ 1779 dmae.dst_addr_hi = 0; 1780 dmae.len = len32; 1781 1782 /* issue the command and wait for completion */ 1783 if ((rc = bxe_issue_dmae_with_comp(sc, &dmae)) != 0) { 1784 bxe_panic(sc, ("DMAE failed (%d)\n", rc)); 1785 } 1786 } 1787 1788 void 1789 bxe_write_dmae_phys_len(struct bxe_softc *sc, 1790 bus_addr_t phys_addr, 1791 uint32_t addr, 1792 uint32_t len) 1793 { 1794 int dmae_wr_max = DMAE_LEN32_WR_MAX(sc); 1795 int offset = 0; 1796 1797 while (len > dmae_wr_max) { 1798 bxe_write_dmae(sc, 1799 (phys_addr + offset), /* src DMA address */ 1800 (addr + offset), /* dst GRC address */ 1801 dmae_wr_max); 1802 offset += (dmae_wr_max * 4); 1803 len -= dmae_wr_max; 1804 } 1805 1806 bxe_write_dmae(sc, 1807 (phys_addr + offset), /* src DMA address */ 1808 (addr + offset), /* dst GRC address */ 1809 len); 1810 } 1811 1812 void 1813 bxe_set_ctx_validation(struct bxe_softc *sc, 1814 struct eth_context *cxt, 1815 uint32_t cid) 1816 { 1817 /* ustorm cxt validation */ 1818 cxt->ustorm_ag_context.cdu_usage = 1819 CDU_RSRVD_VALUE_TYPE_A(HW_CID(sc, cid), 1820 CDU_REGION_NUMBER_UCM_AG, ETH_CONNECTION_TYPE); 1821 /* xcontext validation */ 1822 cxt->xstorm_ag_context.cdu_reserved = 1823 CDU_RSRVD_VALUE_TYPE_A(HW_CID(sc, cid), 1824 CDU_REGION_NUMBER_XCM_AG, ETH_CONNECTION_TYPE); 1825 } 1826 1827 static void 1828 bxe_storm_memset_hc_timeout(struct bxe_softc *sc, 1829 uint8_t port, 1830 uint8_t fw_sb_id, 1831 uint8_t sb_index, 1832 uint8_t ticks) 1833 { 1834 uint32_t addr = 1835 (BAR_CSTRORM_INTMEM + 1836 CSTORM_STATUS_BLOCK_DATA_TIMEOUT_OFFSET(fw_sb_id, sb_index)); 1837 1838 REG_WR8(sc, addr, ticks); 1839 1840 BLOGD(sc, DBG_LOAD, 1841 "port %d fw_sb_id %d sb_index %d ticks %d\n", 1842 port, fw_sb_id, sb_index, ticks); 1843 } 1844 1845 static void 1846 bxe_storm_memset_hc_disable(struct bxe_softc *sc, 1847 uint8_t port, 1848 uint16_t fw_sb_id, 1849 uint8_t sb_index, 1850 uint8_t disable) 1851 { 1852 uint32_t enable_flag = 1853 (disable) ? 0 : (1 << HC_INDEX_DATA_HC_ENABLED_SHIFT); 1854 uint32_t addr = 1855 (BAR_CSTRORM_INTMEM + 1856 CSTORM_STATUS_BLOCK_DATA_FLAGS_OFFSET(fw_sb_id, sb_index)); 1857 uint8_t flags; 1858 1859 /* clear and set */ 1860 flags = REG_RD8(sc, addr); 1861 flags &= ~HC_INDEX_DATA_HC_ENABLED; 1862 flags |= enable_flag; 1863 REG_WR8(sc, addr, flags); 1864 1865 BLOGD(sc, DBG_LOAD, 1866 "port %d fw_sb_id %d sb_index %d disable %d\n", 1867 port, fw_sb_id, sb_index, disable); 1868 } 1869 1870 void 1871 bxe_update_coalesce_sb_index(struct bxe_softc *sc, 1872 uint8_t fw_sb_id, 1873 uint8_t sb_index, 1874 uint8_t disable, 1875 uint16_t usec) 1876 { 1877 int port = SC_PORT(sc); 1878 uint8_t ticks = (usec / 4); /* XXX ??? */ 1879 1880 bxe_storm_memset_hc_timeout(sc, port, fw_sb_id, sb_index, ticks); 1881 1882 disable = (disable) ? 1 : ((usec) ? 0 : 1); 1883 bxe_storm_memset_hc_disable(sc, port, fw_sb_id, sb_index, disable); 1884 } 1885 1886 void 1887 elink_cb_udelay(struct bxe_softc *sc, 1888 uint32_t usecs) 1889 { 1890 DELAY(usecs); 1891 } 1892 1893 uint32_t 1894 elink_cb_reg_read(struct bxe_softc *sc, 1895 uint32_t reg_addr) 1896 { 1897 return (REG_RD(sc, reg_addr)); 1898 } 1899 1900 void 1901 elink_cb_reg_write(struct bxe_softc *sc, 1902 uint32_t reg_addr, 1903 uint32_t val) 1904 { 1905 REG_WR(sc, reg_addr, val); 1906 } 1907 1908 void 1909 elink_cb_reg_wb_write(struct bxe_softc *sc, 1910 uint32_t offset, 1911 uint32_t *wb_write, 1912 uint16_t len) 1913 { 1914 REG_WR_DMAE(sc, offset, wb_write, len); 1915 } 1916 1917 void 1918 elink_cb_reg_wb_read(struct bxe_softc *sc, 1919 uint32_t offset, 1920 uint32_t *wb_write, 1921 uint16_t len) 1922 { 1923 REG_RD_DMAE(sc, offset, wb_write, len); 1924 } 1925 1926 uint8_t 1927 elink_cb_path_id(struct bxe_softc *sc) 1928 { 1929 return (SC_PATH(sc)); 1930 } 1931 1932 void 1933 elink_cb_event_log(struct bxe_softc *sc, 1934 const elink_log_id_t elink_log_id, 1935 ...) 1936 { 1937 /* XXX */ 1938 #if 0 1939 //va_list ap; 1940 va_start(ap, elink_log_id); 1941 _XXX_(sc, lm_log_id, ap); 1942 va_end(ap); 1943 #endif 1944 BLOGI(sc, "ELINK EVENT LOG (%d)\n", elink_log_id); 1945 } 1946 1947 static int 1948 bxe_set_spio(struct bxe_softc *sc, 1949 int spio, 1950 uint32_t mode) 1951 { 1952 uint32_t spio_reg; 1953 1954 /* Only 2 SPIOs are configurable */ 1955 if ((spio != MISC_SPIO_SPIO4) && (spio != MISC_SPIO_SPIO5)) { 1956 BLOGE(sc, "Invalid SPIO 0x%x\n", spio); 1957 return (-1); 1958 } 1959 1960 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_SPIO); 1961 1962 /* read SPIO and mask except the float bits */ 1963 spio_reg = (REG_RD(sc, MISC_REG_SPIO) & MISC_SPIO_FLOAT); 1964 1965 switch (mode) { 1966 case MISC_SPIO_OUTPUT_LOW: 1967 BLOGD(sc, DBG_LOAD, "Set SPIO 0x%x -> output low\n", spio); 1968 /* clear FLOAT and set CLR */ 1969 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS); 1970 spio_reg |= (spio << MISC_SPIO_CLR_POS); 1971 break; 1972 1973 case MISC_SPIO_OUTPUT_HIGH: 1974 BLOGD(sc, DBG_LOAD, "Set SPIO 0x%x -> output high\n", spio); 1975 /* clear FLOAT and set SET */ 1976 spio_reg &= ~(spio << MISC_SPIO_FLOAT_POS); 1977 spio_reg |= (spio << MISC_SPIO_SET_POS); 1978 break; 1979 1980 case MISC_SPIO_INPUT_HI_Z: 1981 BLOGD(sc, DBG_LOAD, "Set SPIO 0x%x -> input\n", spio); 1982 /* set FLOAT */ 1983 spio_reg |= (spio << MISC_SPIO_FLOAT_POS); 1984 break; 1985 1986 default: 1987 break; 1988 } 1989 1990 REG_WR(sc, MISC_REG_SPIO, spio_reg); 1991 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_SPIO); 1992 1993 return (0); 1994 } 1995 1996 static int 1997 bxe_gpio_read(struct bxe_softc *sc, 1998 int gpio_num, 1999 uint8_t port) 2000 { 2001 /* The GPIO should be swapped if swap register is set and active */ 2002 int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) && 2003 REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port); 2004 int gpio_shift = (gpio_num + 2005 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0)); 2006 uint32_t gpio_mask = (1 << gpio_shift); 2007 uint32_t gpio_reg; 2008 2009 if (gpio_num > MISC_REGISTERS_GPIO_3) { 2010 BLOGE(sc, "Invalid GPIO %d\n", gpio_num); 2011 return (-1); 2012 } 2013 2014 /* read GPIO value */ 2015 gpio_reg = REG_RD(sc, MISC_REG_GPIO); 2016 2017 /* get the requested pin value */ 2018 return ((gpio_reg & gpio_mask) == gpio_mask) ? 1 : 0; 2019 } 2020 2021 static int 2022 bxe_gpio_write(struct bxe_softc *sc, 2023 int gpio_num, 2024 uint32_t mode, 2025 uint8_t port) 2026 { 2027 /* The GPIO should be swapped if swap register is set and active */ 2028 int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) && 2029 REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port); 2030 int gpio_shift = (gpio_num + 2031 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0)); 2032 uint32_t gpio_mask = (1 << gpio_shift); 2033 uint32_t gpio_reg; 2034 2035 if (gpio_num > MISC_REGISTERS_GPIO_3) { 2036 BLOGE(sc, "Invalid GPIO %d\n", gpio_num); 2037 return (-1); 2038 } 2039 2040 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO); 2041 2042 /* read GPIO and mask except the float bits */ 2043 gpio_reg = (REG_RD(sc, MISC_REG_GPIO) & MISC_REGISTERS_GPIO_FLOAT); 2044 2045 switch (mode) { 2046 case MISC_REGISTERS_GPIO_OUTPUT_LOW: 2047 BLOGD(sc, DBG_PHY, 2048 "Set GPIO %d (shift %d) -> output low\n", 2049 gpio_num, gpio_shift); 2050 /* clear FLOAT and set CLR */ 2051 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); 2052 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_CLR_POS); 2053 break; 2054 2055 case MISC_REGISTERS_GPIO_OUTPUT_HIGH: 2056 BLOGD(sc, DBG_PHY, 2057 "Set GPIO %d (shift %d) -> output high\n", 2058 gpio_num, gpio_shift); 2059 /* clear FLOAT and set SET */ 2060 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); 2061 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_SET_POS); 2062 break; 2063 2064 case MISC_REGISTERS_GPIO_INPUT_HI_Z: 2065 BLOGD(sc, DBG_PHY, 2066 "Set GPIO %d (shift %d) -> input\n", 2067 gpio_num, gpio_shift); 2068 /* set FLOAT */ 2069 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_FLOAT_POS); 2070 break; 2071 2072 default: 2073 break; 2074 } 2075 2076 REG_WR(sc, MISC_REG_GPIO, gpio_reg); 2077 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO); 2078 2079 return (0); 2080 } 2081 2082 static int 2083 bxe_gpio_mult_write(struct bxe_softc *sc, 2084 uint8_t pins, 2085 uint32_t mode) 2086 { 2087 uint32_t gpio_reg; 2088 2089 /* any port swapping should be handled by caller */ 2090 2091 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO); 2092 2093 /* read GPIO and mask except the float bits */ 2094 gpio_reg = REG_RD(sc, MISC_REG_GPIO); 2095 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_FLOAT_POS); 2096 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_CLR_POS); 2097 gpio_reg &= ~(pins << MISC_REGISTERS_GPIO_SET_POS); 2098 2099 switch (mode) { 2100 case MISC_REGISTERS_GPIO_OUTPUT_LOW: 2101 BLOGD(sc, DBG_PHY, "Set GPIO 0x%x -> output low\n", pins); 2102 /* set CLR */ 2103 gpio_reg |= (pins << MISC_REGISTERS_GPIO_CLR_POS); 2104 break; 2105 2106 case MISC_REGISTERS_GPIO_OUTPUT_HIGH: 2107 BLOGD(sc, DBG_PHY, "Set GPIO 0x%x -> output high\n", pins); 2108 /* set SET */ 2109 gpio_reg |= (pins << MISC_REGISTERS_GPIO_SET_POS); 2110 break; 2111 2112 case MISC_REGISTERS_GPIO_INPUT_HI_Z: 2113 BLOGD(sc, DBG_PHY, "Set GPIO 0x%x -> input\n", pins); 2114 /* set FLOAT */ 2115 gpio_reg |= (pins << MISC_REGISTERS_GPIO_FLOAT_POS); 2116 break; 2117 2118 default: 2119 BLOGE(sc, "Invalid GPIO mode assignment %d\n", mode); 2120 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO); 2121 return (-1); 2122 } 2123 2124 REG_WR(sc, MISC_REG_GPIO, gpio_reg); 2125 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO); 2126 2127 return (0); 2128 } 2129 2130 static int 2131 bxe_gpio_int_write(struct bxe_softc *sc, 2132 int gpio_num, 2133 uint32_t mode, 2134 uint8_t port) 2135 { 2136 /* The GPIO should be swapped if swap register is set and active */ 2137 int gpio_port = ((REG_RD(sc, NIG_REG_PORT_SWAP) && 2138 REG_RD(sc, NIG_REG_STRAP_OVERRIDE)) ^ port); 2139 int gpio_shift = (gpio_num + 2140 (gpio_port ? MISC_REGISTERS_GPIO_PORT_SHIFT : 0)); 2141 uint32_t gpio_mask = (1 << gpio_shift); 2142 uint32_t gpio_reg; 2143 2144 if (gpio_num > MISC_REGISTERS_GPIO_3) { 2145 BLOGE(sc, "Invalid GPIO %d\n", gpio_num); 2146 return (-1); 2147 } 2148 2149 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_GPIO); 2150 2151 /* read GPIO int */ 2152 gpio_reg = REG_RD(sc, MISC_REG_GPIO_INT); 2153 2154 switch (mode) { 2155 case MISC_REGISTERS_GPIO_INT_OUTPUT_CLR: 2156 BLOGD(sc, DBG_PHY, 2157 "Clear GPIO INT %d (shift %d) -> output low\n", 2158 gpio_num, gpio_shift); 2159 /* clear SET and set CLR */ 2160 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS); 2161 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS); 2162 break; 2163 2164 case MISC_REGISTERS_GPIO_INT_OUTPUT_SET: 2165 BLOGD(sc, DBG_PHY, 2166 "Set GPIO INT %d (shift %d) -> output high\n", 2167 gpio_num, gpio_shift); 2168 /* clear CLR and set SET */ 2169 gpio_reg &= ~(gpio_mask << MISC_REGISTERS_GPIO_INT_CLR_POS); 2170 gpio_reg |= (gpio_mask << MISC_REGISTERS_GPIO_INT_SET_POS); 2171 break; 2172 2173 default: 2174 break; 2175 } 2176 2177 REG_WR(sc, MISC_REG_GPIO_INT, gpio_reg); 2178 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_GPIO); 2179 2180 return (0); 2181 } 2182 2183 uint32_t 2184 elink_cb_gpio_read(struct bxe_softc *sc, 2185 uint16_t gpio_num, 2186 uint8_t port) 2187 { 2188 return (bxe_gpio_read(sc, gpio_num, port)); 2189 } 2190 2191 uint8_t 2192 elink_cb_gpio_write(struct bxe_softc *sc, 2193 uint16_t gpio_num, 2194 uint8_t mode, /* 0=low 1=high */ 2195 uint8_t port) 2196 { 2197 return (bxe_gpio_write(sc, gpio_num, mode, port)); 2198 } 2199 2200 uint8_t 2201 elink_cb_gpio_mult_write(struct bxe_softc *sc, 2202 uint8_t pins, 2203 uint8_t mode) /* 0=low 1=high */ 2204 { 2205 return (bxe_gpio_mult_write(sc, pins, mode)); 2206 } 2207 2208 uint8_t 2209 elink_cb_gpio_int_write(struct bxe_softc *sc, 2210 uint16_t gpio_num, 2211 uint8_t mode, /* 0=low 1=high */ 2212 uint8_t port) 2213 { 2214 return (bxe_gpio_int_write(sc, gpio_num, mode, port)); 2215 } 2216 2217 void 2218 elink_cb_notify_link_changed(struct bxe_softc *sc) 2219 { 2220 REG_WR(sc, (MISC_REG_AEU_GENERAL_ATTN_12 + 2221 (SC_FUNC(sc) * sizeof(uint32_t))), 1); 2222 } 2223 2224 /* send the MCP a request, block until there is a reply */ 2225 uint32_t 2226 elink_cb_fw_command(struct bxe_softc *sc, 2227 uint32_t command, 2228 uint32_t param) 2229 { 2230 int mb_idx = SC_FW_MB_IDX(sc); 2231 uint32_t seq; 2232 uint32_t rc = 0; 2233 uint32_t cnt = 1; 2234 uint8_t delay = CHIP_REV_IS_SLOW(sc) ? 100 : 10; 2235 2236 BXE_FWMB_LOCK(sc); 2237 2238 seq = ++sc->fw_seq; 2239 SHMEM_WR(sc, func_mb[mb_idx].drv_mb_param, param); 2240 SHMEM_WR(sc, func_mb[mb_idx].drv_mb_header, (command | seq)); 2241 2242 BLOGD(sc, DBG_PHY, 2243 "wrote command 0x%08x to FW MB param 0x%08x\n", 2244 (command | seq), param); 2245 2246 /* Let the FW do it's magic. GIve it up to 5 seconds... */ 2247 do { 2248 DELAY(delay * 1000); 2249 rc = SHMEM_RD(sc, func_mb[mb_idx].fw_mb_header); 2250 } while ((seq != (rc & FW_MSG_SEQ_NUMBER_MASK)) && (cnt++ < 500)); 2251 2252 BLOGD(sc, DBG_PHY, 2253 "[after %d ms] read 0x%x seq 0x%x from FW MB\n", 2254 cnt*delay, rc, seq); 2255 2256 /* is this a reply to our command? */ 2257 if (seq == (rc & FW_MSG_SEQ_NUMBER_MASK)) { 2258 rc &= FW_MSG_CODE_MASK; 2259 } else { 2260 /* Ruh-roh! */ 2261 BLOGE(sc, "FW failed to respond!\n"); 2262 // XXX bxe_fw_dump(sc); 2263 rc = 0; 2264 } 2265 2266 BXE_FWMB_UNLOCK(sc); 2267 return (rc); 2268 } 2269 2270 static uint32_t 2271 bxe_fw_command(struct bxe_softc *sc, 2272 uint32_t command, 2273 uint32_t param) 2274 { 2275 return (elink_cb_fw_command(sc, command, param)); 2276 } 2277 2278 static void 2279 __storm_memset_dma_mapping(struct bxe_softc *sc, 2280 uint32_t addr, 2281 bus_addr_t mapping) 2282 { 2283 REG_WR(sc, addr, U64_LO(mapping)); 2284 REG_WR(sc, (addr + 4), U64_HI(mapping)); 2285 } 2286 2287 static void 2288 storm_memset_spq_addr(struct bxe_softc *sc, 2289 bus_addr_t mapping, 2290 uint16_t abs_fid) 2291 { 2292 uint32_t addr = (XSEM_REG_FAST_MEMORY + 2293 XSTORM_SPQ_PAGE_BASE_OFFSET(abs_fid)); 2294 __storm_memset_dma_mapping(sc, addr, mapping); 2295 } 2296 2297 static void 2298 storm_memset_vf_to_pf(struct bxe_softc *sc, 2299 uint16_t abs_fid, 2300 uint16_t pf_id) 2301 { 2302 REG_WR8(sc, (BAR_XSTRORM_INTMEM + XSTORM_VF_TO_PF_OFFSET(abs_fid)), pf_id); 2303 REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_VF_TO_PF_OFFSET(abs_fid)), pf_id); 2304 REG_WR8(sc, (BAR_TSTRORM_INTMEM + TSTORM_VF_TO_PF_OFFSET(abs_fid)), pf_id); 2305 REG_WR8(sc, (BAR_USTRORM_INTMEM + USTORM_VF_TO_PF_OFFSET(abs_fid)), pf_id); 2306 } 2307 2308 static void 2309 storm_memset_func_en(struct bxe_softc *sc, 2310 uint16_t abs_fid, 2311 uint8_t enable) 2312 { 2313 REG_WR8(sc, (BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(abs_fid)), enable); 2314 REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(abs_fid)), enable); 2315 REG_WR8(sc, (BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(abs_fid)), enable); 2316 REG_WR8(sc, (BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(abs_fid)), enable); 2317 } 2318 2319 static void 2320 storm_memset_eq_data(struct bxe_softc *sc, 2321 struct event_ring_data *eq_data, 2322 uint16_t pfid) 2323 { 2324 uint32_t addr; 2325 size_t size; 2326 2327 addr = (BAR_CSTRORM_INTMEM + CSTORM_EVENT_RING_DATA_OFFSET(pfid)); 2328 size = sizeof(struct event_ring_data); 2329 ecore_storm_memset_struct(sc, addr, size, (uint32_t *)eq_data); 2330 } 2331 2332 static void 2333 storm_memset_eq_prod(struct bxe_softc *sc, 2334 uint16_t eq_prod, 2335 uint16_t pfid) 2336 { 2337 uint32_t addr = (BAR_CSTRORM_INTMEM + 2338 CSTORM_EVENT_RING_PROD_OFFSET(pfid)); 2339 REG_WR16(sc, addr, eq_prod); 2340 } 2341 2342 /* 2343 * Post a slowpath command. 2344 * 2345 * A slowpath command is used to propogate a configuration change through 2346 * the controller in a controlled manner, allowing each STORM processor and 2347 * other H/W blocks to phase in the change. The commands sent on the 2348 * slowpath are referred to as ramrods. Depending on the ramrod used the 2349 * completion of the ramrod will occur in different ways. Here's a 2350 * breakdown of ramrods and how they complete: 2351 * 2352 * RAMROD_CMD_ID_ETH_PORT_SETUP 2353 * Used to setup the leading connection on a port. Completes on the 2354 * Receive Completion Queue (RCQ) of that port (typically fp[0]). 2355 * 2356 * RAMROD_CMD_ID_ETH_CLIENT_SETUP 2357 * Used to setup an additional connection on a port. Completes on the 2358 * RCQ of the multi-queue/RSS connection being initialized. 2359 * 2360 * RAMROD_CMD_ID_ETH_STAT_QUERY 2361 * Used to force the storm processors to update the statistics database 2362 * in host memory. This ramrod is send on the leading connection CID and 2363 * completes as an index increment of the CSTORM on the default status 2364 * block. 2365 * 2366 * RAMROD_CMD_ID_ETH_UPDATE 2367 * Used to update the state of the leading connection, usually to udpate 2368 * the RSS indirection table. Completes on the RCQ of the leading 2369 * connection. (Not currently used under FreeBSD until OS support becomes 2370 * available.) 2371 * 2372 * RAMROD_CMD_ID_ETH_HALT 2373 * Used when tearing down a connection prior to driver unload. Completes 2374 * on the RCQ of the multi-queue/RSS connection being torn down. Don't 2375 * use this on the leading connection. 2376 * 2377 * RAMROD_CMD_ID_ETH_SET_MAC 2378 * Sets the Unicast/Broadcast/Multicast used by the port. Completes on 2379 * the RCQ of the leading connection. 2380 * 2381 * RAMROD_CMD_ID_ETH_CFC_DEL 2382 * Used when tearing down a conneciton prior to driver unload. Completes 2383 * on the RCQ of the leading connection (since the current connection 2384 * has been completely removed from controller memory). 2385 * 2386 * RAMROD_CMD_ID_ETH_PORT_DEL 2387 * Used to tear down the leading connection prior to driver unload, 2388 * typically fp[0]. Completes as an index increment of the CSTORM on the 2389 * default status block. 2390 * 2391 * RAMROD_CMD_ID_ETH_FORWARD_SETUP 2392 * Used for connection offload. Completes on the RCQ of the multi-queue 2393 * RSS connection that is being offloaded. (Not currently used under 2394 * FreeBSD.) 2395 * 2396 * There can only be one command pending per function. 2397 * 2398 * Returns: 2399 * 0 = Success, !0 = Failure. 2400 */ 2401 2402 /* must be called under the spq lock */ 2403 static inline 2404 struct eth_spe *bxe_sp_get_next(struct bxe_softc *sc) 2405 { 2406 struct eth_spe *next_spe = sc->spq_prod_bd; 2407 2408 if (sc->spq_prod_bd == sc->spq_last_bd) { 2409 /* wrap back to the first eth_spq */ 2410 sc->spq_prod_bd = sc->spq; 2411 sc->spq_prod_idx = 0; 2412 } else { 2413 sc->spq_prod_bd++; 2414 sc->spq_prod_idx++; 2415 } 2416 2417 return (next_spe); 2418 } 2419 2420 /* must be called under the spq lock */ 2421 static inline 2422 void bxe_sp_prod_update(struct bxe_softc *sc) 2423 { 2424 int func = SC_FUNC(sc); 2425 2426 /* 2427 * Make sure that BD data is updated before writing the producer. 2428 * BD data is written to the memory, the producer is read from the 2429 * memory, thus we need a full memory barrier to ensure the ordering. 2430 */ 2431 mb(); 2432 2433 REG_WR16(sc, (BAR_XSTRORM_INTMEM + XSTORM_SPQ_PROD_OFFSET(func)), 2434 sc->spq_prod_idx); 2435 2436 bus_space_barrier(sc->bar[BAR0].tag, sc->bar[BAR0].handle, 0, 0, 2437 BUS_SPACE_BARRIER_WRITE); 2438 } 2439 2440 /** 2441 * bxe_is_contextless_ramrod - check if the current command ends on EQ 2442 * 2443 * @cmd: command to check 2444 * @cmd_type: command type 2445 */ 2446 static inline 2447 int bxe_is_contextless_ramrod(int cmd, 2448 int cmd_type) 2449 { 2450 if ((cmd_type == NONE_CONNECTION_TYPE) || 2451 (cmd == RAMROD_CMD_ID_ETH_FORWARD_SETUP) || 2452 (cmd == RAMROD_CMD_ID_ETH_CLASSIFICATION_RULES) || 2453 (cmd == RAMROD_CMD_ID_ETH_FILTER_RULES) || 2454 (cmd == RAMROD_CMD_ID_ETH_MULTICAST_RULES) || 2455 (cmd == RAMROD_CMD_ID_ETH_SET_MAC) || 2456 (cmd == RAMROD_CMD_ID_ETH_RSS_UPDATE)) { 2457 return (TRUE); 2458 } else { 2459 return (FALSE); 2460 } 2461 } 2462 2463 /** 2464 * bxe_sp_post - place a single command on an SP ring 2465 * 2466 * @sc: driver handle 2467 * @command: command to place (e.g. SETUP, FILTER_RULES, etc.) 2468 * @cid: SW CID the command is related to 2469 * @data_hi: command private data address (high 32 bits) 2470 * @data_lo: command private data address (low 32 bits) 2471 * @cmd_type: command type (e.g. NONE, ETH) 2472 * 2473 * SP data is handled as if it's always an address pair, thus data fields are 2474 * not swapped to little endian in upper functions. Instead this function swaps 2475 * data as if it's two uint32 fields. 2476 */ 2477 int 2478 bxe_sp_post(struct bxe_softc *sc, 2479 int command, 2480 int cid, 2481 uint32_t data_hi, 2482 uint32_t data_lo, 2483 int cmd_type) 2484 { 2485 struct eth_spe *spe; 2486 uint16_t type; 2487 int common; 2488 2489 common = bxe_is_contextless_ramrod(command, cmd_type); 2490 2491 BXE_SP_LOCK(sc); 2492 2493 if (common) { 2494 if (!atomic_load_acq_long(&sc->eq_spq_left)) { 2495 BLOGE(sc, "EQ ring is full!\n"); 2496 BXE_SP_UNLOCK(sc); 2497 return (-1); 2498 } 2499 } else { 2500 if (!atomic_load_acq_long(&sc->cq_spq_left)) { 2501 BLOGE(sc, "SPQ ring is full!\n"); 2502 BXE_SP_UNLOCK(sc); 2503 return (-1); 2504 } 2505 } 2506 2507 spe = bxe_sp_get_next(sc); 2508 2509 /* CID needs port number to be encoded int it */ 2510 spe->hdr.conn_and_cmd_data = 2511 htole32((command << SPE_HDR_CMD_ID_SHIFT) | HW_CID(sc, cid)); 2512 2513 type = (cmd_type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE; 2514 2515 /* TBD: Check if it works for VFs */ 2516 type |= ((SC_FUNC(sc) << SPE_HDR_FUNCTION_ID_SHIFT) & 2517 SPE_HDR_FUNCTION_ID); 2518 2519 spe->hdr.type = htole16(type); 2520 2521 spe->data.update_data_addr.hi = htole32(data_hi); 2522 spe->data.update_data_addr.lo = htole32(data_lo); 2523 2524 /* 2525 * It's ok if the actual decrement is issued towards the memory 2526 * somewhere between the lock and unlock. Thus no more explict 2527 * memory barrier is needed. 2528 */ 2529 if (common) { 2530 atomic_subtract_acq_long(&sc->eq_spq_left, 1); 2531 } else { 2532 atomic_subtract_acq_long(&sc->cq_spq_left, 1); 2533 } 2534 2535 BLOGD(sc, DBG_SP, "SPQE -> %#jx\n", (uintmax_t)sc->spq_dma.paddr); 2536 BLOGD(sc, DBG_SP, "FUNC_RDATA -> %p / %#jx\n", 2537 BXE_SP(sc, func_rdata), (uintmax_t)BXE_SP_MAPPING(sc, func_rdata)); 2538 BLOGD(sc, DBG_SP, 2539 "SPQE[%x] (%x:%x) (cmd, common?) (%d,%d) hw_cid %x data (%x:%x) type(0x%x) left (CQ, EQ) (%lx,%lx)\n", 2540 sc->spq_prod_idx, 2541 (uint32_t)U64_HI(sc->spq_dma.paddr), 2542 (uint32_t)(U64_LO(sc->spq_dma.paddr) + (uint8_t *)sc->spq_prod_bd - (uint8_t *)sc->spq), 2543 command, 2544 common, 2545 HW_CID(sc, cid), 2546 data_hi, 2547 data_lo, 2548 type, 2549 atomic_load_acq_long(&sc->cq_spq_left), 2550 atomic_load_acq_long(&sc->eq_spq_left)); 2551 2552 bxe_sp_prod_update(sc); 2553 2554 BXE_SP_UNLOCK(sc); 2555 return (0); 2556 } 2557 2558 /** 2559 * bxe_debug_print_ind_table - prints the indirection table configuration. 2560 * 2561 * @sc: driver hanlde 2562 * @p: pointer to rss configuration 2563 */ 2564 #if 0 2565 static void 2566 bxe_debug_print_ind_table(struct bxe_softc *sc, 2567 struct ecore_config_rss_params *p) 2568 { 2569 int i; 2570 2571 BLOGD(sc, DBG_LOAD, "Setting indirection table to:\n"); 2572 BLOGD(sc, DBG_LOAD, " 0x0000: "); 2573 for (i = 0; i < T_ETH_INDIRECTION_TABLE_SIZE; i++) { 2574 BLOGD(sc, DBG_LOAD, "0x%02x ", p->ind_table[i]); 2575 2576 /* Print 4 bytes in a line */ 2577 if ((i + 1 < T_ETH_INDIRECTION_TABLE_SIZE) && 2578 (((i + 1) & 0x3) == 0)) { 2579 BLOGD(sc, DBG_LOAD, "\n"); 2580 BLOGD(sc, DBG_LOAD, "0x%04x: ", i + 1); 2581 } 2582 } 2583 2584 BLOGD(sc, DBG_LOAD, "\n"); 2585 } 2586 #endif 2587 2588 /* 2589 * FreeBSD Device probe function. 2590 * 2591 * Compares the device found to the driver's list of supported devices and 2592 * reports back to the bsd loader whether this is the right driver for the device. 2593 * This is the driver entry function called from the "kldload" command. 2594 * 2595 * Returns: 2596 * BUS_PROBE_DEFAULT on success, positive value on failure. 2597 */ 2598 static int 2599 bxe_probe(device_t dev) 2600 { 2601 struct bxe_softc *sc; 2602 struct bxe_device_type *t; 2603 char *descbuf; 2604 uint16_t did, sdid, svid, vid; 2605 2606 /* Find our device structure */ 2607 sc = device_get_softc(dev); 2608 sc->dev = dev; 2609 t = bxe_devs; 2610 2611 /* Get the data for the device to be probed. */ 2612 vid = pci_get_vendor(dev); 2613 did = pci_get_device(dev); 2614 svid = pci_get_subvendor(dev); 2615 sdid = pci_get_subdevice(dev); 2616 2617 BLOGD(sc, DBG_LOAD, 2618 "%s(); VID = 0x%04X, DID = 0x%04X, SVID = 0x%04X, " 2619 "SDID = 0x%04X\n", __FUNCTION__, vid, did, svid, sdid); 2620 2621 /* Look through the list of known devices for a match. */ 2622 while (t->bxe_name != NULL) { 2623 if ((vid == t->bxe_vid) && (did == t->bxe_did) && 2624 ((svid == t->bxe_svid) || (t->bxe_svid == PCI_ANY_ID)) && 2625 ((sdid == t->bxe_sdid) || (t->bxe_sdid == PCI_ANY_ID))) { 2626 descbuf = malloc(BXE_DEVDESC_MAX, M_TEMP, M_NOWAIT); 2627 if (descbuf == NULL) 2628 return (ENOMEM); 2629 2630 /* Print out the device identity. */ 2631 snprintf(descbuf, BXE_DEVDESC_MAX, 2632 "%s (%c%d) BXE v:%s\n", t->bxe_name, 2633 (((pci_read_config(dev, PCIR_REVID, 4) & 2634 0xf0) >> 4) + 'A'), 2635 (pci_read_config(dev, PCIR_REVID, 4) & 0xf), 2636 BXE_DRIVER_VERSION); 2637 2638 device_set_desc_copy(dev, descbuf); 2639 free(descbuf, M_TEMP); 2640 return (BUS_PROBE_DEFAULT); 2641 } 2642 t++; 2643 } 2644 2645 return (ENXIO); 2646 } 2647 2648 static void 2649 bxe_init_mutexes(struct bxe_softc *sc) 2650 { 2651 #ifdef BXE_CORE_LOCK_SX 2652 snprintf(sc->core_sx_name, sizeof(sc->core_sx_name), 2653 "bxe%d_core_lock", sc->unit); 2654 sx_init(&sc->core_sx, sc->core_sx_name); 2655 #else 2656 snprintf(sc->core_mtx_name, sizeof(sc->core_mtx_name), 2657 "bxe%d_core_lock", sc->unit); 2658 mtx_init(&sc->core_mtx, sc->core_mtx_name, NULL, MTX_DEF); 2659 #endif 2660 2661 snprintf(sc->sp_mtx_name, sizeof(sc->sp_mtx_name), 2662 "bxe%d_sp_lock", sc->unit); 2663 mtx_init(&sc->sp_mtx, sc->sp_mtx_name, NULL, MTX_DEF); 2664 2665 snprintf(sc->dmae_mtx_name, sizeof(sc->dmae_mtx_name), 2666 "bxe%d_dmae_lock", sc->unit); 2667 mtx_init(&sc->dmae_mtx, sc->dmae_mtx_name, NULL, MTX_DEF); 2668 2669 snprintf(sc->port.phy_mtx_name, sizeof(sc->port.phy_mtx_name), 2670 "bxe%d_phy_lock", sc->unit); 2671 mtx_init(&sc->port.phy_mtx, sc->port.phy_mtx_name, NULL, MTX_DEF); 2672 2673 snprintf(sc->fwmb_mtx_name, sizeof(sc->fwmb_mtx_name), 2674 "bxe%d_fwmb_lock", sc->unit); 2675 mtx_init(&sc->fwmb_mtx, sc->fwmb_mtx_name, NULL, MTX_DEF); 2676 2677 snprintf(sc->print_mtx_name, sizeof(sc->print_mtx_name), 2678 "bxe%d_print_lock", sc->unit); 2679 mtx_init(&(sc->print_mtx), sc->print_mtx_name, NULL, MTX_DEF); 2680 2681 snprintf(sc->stats_mtx_name, sizeof(sc->stats_mtx_name), 2682 "bxe%d_stats_lock", sc->unit); 2683 mtx_init(&(sc->stats_mtx), sc->stats_mtx_name, NULL, MTX_DEF); 2684 2685 snprintf(sc->mcast_mtx_name, sizeof(sc->mcast_mtx_name), 2686 "bxe%d_mcast_lock", sc->unit); 2687 mtx_init(&(sc->mcast_mtx), sc->mcast_mtx_name, NULL, MTX_DEF); 2688 } 2689 2690 static void 2691 bxe_release_mutexes(struct bxe_softc *sc) 2692 { 2693 #ifdef BXE_CORE_LOCK_SX 2694 sx_destroy(&sc->core_sx); 2695 #else 2696 if (mtx_initialized(&sc->core_mtx)) { 2697 mtx_destroy(&sc->core_mtx); 2698 } 2699 #endif 2700 2701 if (mtx_initialized(&sc->sp_mtx)) { 2702 mtx_destroy(&sc->sp_mtx); 2703 } 2704 2705 if (mtx_initialized(&sc->dmae_mtx)) { 2706 mtx_destroy(&sc->dmae_mtx); 2707 } 2708 2709 if (mtx_initialized(&sc->port.phy_mtx)) { 2710 mtx_destroy(&sc->port.phy_mtx); 2711 } 2712 2713 if (mtx_initialized(&sc->fwmb_mtx)) { 2714 mtx_destroy(&sc->fwmb_mtx); 2715 } 2716 2717 if (mtx_initialized(&sc->print_mtx)) { 2718 mtx_destroy(&sc->print_mtx); 2719 } 2720 2721 if (mtx_initialized(&sc->stats_mtx)) { 2722 mtx_destroy(&sc->stats_mtx); 2723 } 2724 2725 if (mtx_initialized(&sc->mcast_mtx)) { 2726 mtx_destroy(&sc->mcast_mtx); 2727 } 2728 } 2729 2730 static void 2731 bxe_tx_disable(struct bxe_softc* sc) 2732 { 2733 struct ifnet *ifp = sc->ifnet; 2734 2735 /* tell the stack the driver is stopped and TX queue is full */ 2736 if (ifp != NULL) { 2737 ifp->if_drv_flags = 0; 2738 } 2739 } 2740 2741 static void 2742 bxe_drv_pulse(struct bxe_softc *sc) 2743 { 2744 SHMEM_WR(sc, func_mb[SC_FW_MB_IDX(sc)].drv_pulse_mb, 2745 sc->fw_drv_pulse_wr_seq); 2746 } 2747 2748 static inline uint16_t 2749 bxe_tx_avail(struct bxe_softc *sc, 2750 struct bxe_fastpath *fp) 2751 { 2752 int16_t used; 2753 uint16_t prod; 2754 uint16_t cons; 2755 2756 prod = fp->tx_bd_prod; 2757 cons = fp->tx_bd_cons; 2758 2759 used = SUB_S16(prod, cons); 2760 2761 #if 0 2762 KASSERT((used < 0), ("used tx bds < 0")); 2763 KASSERT((used > sc->tx_ring_size), ("used tx bds > tx_ring_size")); 2764 KASSERT(((sc->tx_ring_size - used) > MAX_TX_AVAIL), 2765 ("invalid number of tx bds used")); 2766 #endif 2767 2768 return (int16_t)(sc->tx_ring_size) - used; 2769 } 2770 2771 static inline int 2772 bxe_tx_queue_has_work(struct bxe_fastpath *fp) 2773 { 2774 uint16_t hw_cons; 2775 2776 mb(); /* status block fields can change */ 2777 hw_cons = le16toh(*fp->tx_cons_sb); 2778 return (hw_cons != fp->tx_pkt_cons); 2779 } 2780 2781 static inline uint8_t 2782 bxe_has_tx_work(struct bxe_fastpath *fp) 2783 { 2784 /* expand this for multi-cos if ever supported */ 2785 return (bxe_tx_queue_has_work(fp)) ? TRUE : FALSE; 2786 } 2787 2788 static inline int 2789 bxe_has_rx_work(struct bxe_fastpath *fp) 2790 { 2791 uint16_t rx_cq_cons_sb; 2792 2793 mb(); /* status block fields can change */ 2794 rx_cq_cons_sb = le16toh(*fp->rx_cq_cons_sb); 2795 if ((rx_cq_cons_sb & RCQ_MAX) == RCQ_MAX) 2796 rx_cq_cons_sb++; 2797 return (fp->rx_cq_cons != rx_cq_cons_sb); 2798 } 2799 2800 static void 2801 bxe_sp_event(struct bxe_softc *sc, 2802 struct bxe_fastpath *fp, 2803 union eth_rx_cqe *rr_cqe) 2804 { 2805 int cid = SW_CID(rr_cqe->ramrod_cqe.conn_and_cmd_data); 2806 int command = CQE_CMD(rr_cqe->ramrod_cqe.conn_and_cmd_data); 2807 enum ecore_queue_cmd drv_cmd = ECORE_Q_CMD_MAX; 2808 struct ecore_queue_sp_obj *q_obj = &BXE_SP_OBJ(sc, fp).q_obj; 2809 2810 BLOGD(sc, DBG_SP, "fp=%d cid=%d got ramrod #%d state is %x type is %d\n", 2811 fp->index, cid, command, sc->state, rr_cqe->ramrod_cqe.ramrod_type); 2812 2813 #if 0 2814 /* 2815 * If cid is within VF range, replace the slowpath object with the 2816 * one corresponding to this VF 2817 */ 2818 if ((cid >= BXE_FIRST_VF_CID) && (cid < BXE_FIRST_VF_CID + BXE_VF_CIDS)) { 2819 bxe_iov_set_queue_sp_obj(sc, cid, &q_obj); 2820 } 2821 #endif 2822 2823 switch (command) { 2824 case (RAMROD_CMD_ID_ETH_CLIENT_UPDATE): 2825 BLOGD(sc, DBG_SP, "got UPDATE ramrod. CID %d\n", cid); 2826 drv_cmd = ECORE_Q_CMD_UPDATE; 2827 break; 2828 2829 case (RAMROD_CMD_ID_ETH_CLIENT_SETUP): 2830 BLOGD(sc, DBG_SP, "got MULTI[%d] setup ramrod\n", cid); 2831 drv_cmd = ECORE_Q_CMD_SETUP; 2832 break; 2833 2834 case (RAMROD_CMD_ID_ETH_TX_QUEUE_SETUP): 2835 BLOGD(sc, DBG_SP, "got MULTI[%d] tx-only setup ramrod\n", cid); 2836 drv_cmd = ECORE_Q_CMD_SETUP_TX_ONLY; 2837 break; 2838 2839 case (RAMROD_CMD_ID_ETH_HALT): 2840 BLOGD(sc, DBG_SP, "got MULTI[%d] halt ramrod\n", cid); 2841 drv_cmd = ECORE_Q_CMD_HALT; 2842 break; 2843 2844 case (RAMROD_CMD_ID_ETH_TERMINATE): 2845 BLOGD(sc, DBG_SP, "got MULTI[%d] teminate ramrod\n", cid); 2846 drv_cmd = ECORE_Q_CMD_TERMINATE; 2847 break; 2848 2849 case (RAMROD_CMD_ID_ETH_EMPTY): 2850 BLOGD(sc, DBG_SP, "got MULTI[%d] empty ramrod\n", cid); 2851 drv_cmd = ECORE_Q_CMD_EMPTY; 2852 break; 2853 2854 default: 2855 BLOGD(sc, DBG_SP, "ERROR: unexpected MC reply (%d) on fp[%d]\n", 2856 command, fp->index); 2857 return; 2858 } 2859 2860 if ((drv_cmd != ECORE_Q_CMD_MAX) && 2861 q_obj->complete_cmd(sc, q_obj, drv_cmd)) { 2862 /* 2863 * q_obj->complete_cmd() failure means that this was 2864 * an unexpected completion. 2865 * 2866 * In this case we don't want to increase the sc->spq_left 2867 * because apparently we haven't sent this command the first 2868 * place. 2869 */ 2870 // bxe_panic(sc, ("Unexpected SP completion\n")); 2871 return; 2872 } 2873 2874 #if 0 2875 /* SRIOV: reschedule any 'in_progress' operations */ 2876 bxe_iov_sp_event(sc, cid, TRUE); 2877 #endif 2878 2879 atomic_add_acq_long(&sc->cq_spq_left, 1); 2880 2881 BLOGD(sc, DBG_SP, "sc->cq_spq_left 0x%lx\n", 2882 atomic_load_acq_long(&sc->cq_spq_left)); 2883 2884 #if 0 2885 if ((drv_cmd == ECORE_Q_CMD_UPDATE) && (IS_FCOE_FP(fp)) && 2886 (!!bxe_test_bit(ECORE_AFEX_FCOE_Q_UPDATE_PENDING, &sc->sp_state))) { 2887 /* 2888 * If Queue update ramrod is completed for last Queue in AFEX VIF set 2889 * flow, then ACK MCP at the end. Mark pending ACK to MCP bit to 2890 * prevent case that both bits are cleared. At the end of load/unload 2891 * driver checks that sp_state is cleared and this order prevents 2892 * races. 2893 */ 2894 bxe_set_bit(ECORE_AFEX_PENDING_VIFSET_MCP_ACK, &sc->sp_state); 2895 wmb(); 2896 bxe_clear_bit(ECORE_AFEX_FCOE_Q_UPDATE_PENDING, &sc->sp_state); 2897 2898 /* schedule the sp task as MCP ack is required */ 2899 bxe_schedule_sp_task(sc); 2900 } 2901 #endif 2902 } 2903 2904 /* 2905 * The current mbuf is part of an aggregation. Move the mbuf into the TPA 2906 * aggregation queue, put an empty mbuf back onto the receive chain, and mark 2907 * the current aggregation queue as in-progress. 2908 */ 2909 static void 2910 bxe_tpa_start(struct bxe_softc *sc, 2911 struct bxe_fastpath *fp, 2912 uint16_t queue, 2913 uint16_t cons, 2914 uint16_t prod, 2915 struct eth_fast_path_rx_cqe *cqe) 2916 { 2917 struct bxe_sw_rx_bd tmp_bd; 2918 struct bxe_sw_rx_bd *rx_buf; 2919 struct eth_rx_bd *rx_bd; 2920 int max_agg_queues; 2921 struct bxe_sw_tpa_info *tpa_info = &fp->rx_tpa_info[queue]; 2922 uint16_t index; 2923 2924 BLOGD(sc, DBG_LRO, "fp[%02d].tpa[%02d] TPA START " 2925 "cons=%d prod=%d\n", 2926 fp->index, queue, cons, prod); 2927 2928 max_agg_queues = MAX_AGG_QS(sc); 2929 2930 KASSERT((queue < max_agg_queues), 2931 ("fp[%02d] invalid aggr queue (%d >= %d)!", 2932 fp->index, queue, max_agg_queues)); 2933 2934 KASSERT((tpa_info->state == BXE_TPA_STATE_STOP), 2935 ("fp[%02d].tpa[%02d] starting aggr on queue not stopped!", 2936 fp->index, queue)); 2937 2938 /* copy the existing mbuf and mapping from the TPA pool */ 2939 tmp_bd = tpa_info->bd; 2940 2941 if (tmp_bd.m == NULL) { 2942 BLOGE(sc, "fp[%02d].tpa[%02d] mbuf not allocated!\n", 2943 fp->index, queue); 2944 /* XXX Error handling? */ 2945 return; 2946 } 2947 2948 /* change the TPA queue to the start state */ 2949 tpa_info->state = BXE_TPA_STATE_START; 2950 tpa_info->placement_offset = cqe->placement_offset; 2951 tpa_info->parsing_flags = le16toh(cqe->pars_flags.flags); 2952 tpa_info->vlan_tag = le16toh(cqe->vlan_tag); 2953 tpa_info->len_on_bd = le16toh(cqe->len_on_bd); 2954 2955 fp->rx_tpa_queue_used |= (1 << queue); 2956 2957 /* 2958 * If all the buffer descriptors are filled with mbufs then fill in 2959 * the current consumer index with a new BD. Else if a maximum Rx 2960 * buffer limit is imposed then fill in the next producer index. 2961 */ 2962 index = (sc->max_rx_bufs != RX_BD_USABLE) ? 2963 prod : cons; 2964 2965 /* move the received mbuf and mapping to TPA pool */ 2966 tpa_info->bd = fp->rx_mbuf_chain[cons]; 2967 2968 /* release any existing RX BD mbuf mappings */ 2969 if (cons != index) { 2970 rx_buf = &fp->rx_mbuf_chain[cons]; 2971 2972 if (rx_buf->m_map != NULL) { 2973 bus_dmamap_sync(fp->rx_mbuf_tag, rx_buf->m_map, 2974 BUS_DMASYNC_POSTREAD); 2975 bus_dmamap_unload(fp->rx_mbuf_tag, rx_buf->m_map); 2976 } 2977 2978 /* 2979 * We get here when the maximum number of rx buffers is less than 2980 * RX_BD_USABLE. The mbuf is already saved above so it's OK to NULL 2981 * it out here without concern of a memory leak. 2982 */ 2983 fp->rx_mbuf_chain[cons].m = NULL; 2984 } 2985 2986 /* update the Rx SW BD with the mbuf info from the TPA pool */ 2987 fp->rx_mbuf_chain[index] = tmp_bd; 2988 2989 /* update the Rx BD with the empty mbuf phys address from the TPA pool */ 2990 rx_bd = &fp->rx_chain[index]; 2991 rx_bd->addr_hi = htole32(U64_HI(tpa_info->seg.ds_addr)); 2992 rx_bd->addr_lo = htole32(U64_LO(tpa_info->seg.ds_addr)); 2993 } 2994 2995 /* 2996 * When a TPA aggregation is completed, loop through the individual mbufs 2997 * of the aggregation, combining them into a single mbuf which will be sent 2998 * up the stack. Refill all freed SGEs with mbufs as we go along. 2999 */ 3000 static int 3001 bxe_fill_frag_mbuf(struct bxe_softc *sc, 3002 struct bxe_fastpath *fp, 3003 struct bxe_sw_tpa_info *tpa_info, 3004 uint16_t queue, 3005 uint16_t pages, 3006 struct mbuf *m, 3007 struct eth_end_agg_rx_cqe *cqe, 3008 uint16_t cqe_idx) 3009 { 3010 struct mbuf *m_frag; 3011 uint32_t frag_len, frag_size, i; 3012 uint16_t sge_idx; 3013 int rc = 0; 3014 int j; 3015 3016 frag_size = le16toh(cqe->pkt_len) - tpa_info->len_on_bd; 3017 3018 BLOGD(sc, DBG_LRO, 3019 "fp[%02d].tpa[%02d] TPA fill len_on_bd=%d frag_size=%d pages=%d\n", 3020 fp->index, queue, tpa_info->len_on_bd, frag_size, pages); 3021 3022 /* make sure the aggregated frame is not too big to handle */ 3023 if (pages > 8 * PAGES_PER_SGE) { 3024 BLOGE(sc, "fp[%02d].sge[0x%04x] has too many pages (%d)! " 3025 "pkt_len=%d len_on_bd=%d frag_size=%d\n", 3026 fp->index, cqe_idx, pages, le16toh(cqe->pkt_len), 3027 tpa_info->len_on_bd, frag_size); 3028 bxe_panic(sc, ("sge page count error\n")); 3029 return (EINVAL); 3030 } 3031 3032 /* 3033 * Scan through the scatter gather list pulling individual mbufs into a 3034 * single mbuf for the host stack. 3035 */ 3036 for (i = 0, j = 0; i < pages; i += PAGES_PER_SGE, j++) { 3037 sge_idx = RX_SGE(le16toh(cqe->sgl_or_raw_data.sgl[j])); 3038 3039 /* 3040 * Firmware gives the indices of the SGE as if the ring is an array 3041 * (meaning that the "next" element will consume 2 indices). 3042 */ 3043 frag_len = min(frag_size, (uint32_t)(SGE_PAGES)); 3044 3045 BLOGD(sc, DBG_LRO, "fp[%02d].tpa[%02d] TPA fill i=%d j=%d " 3046 "sge_idx=%d frag_size=%d frag_len=%d\n", 3047 fp->index, queue, i, j, sge_idx, frag_size, frag_len); 3048 3049 m_frag = fp->rx_sge_mbuf_chain[sge_idx].m; 3050 3051 /* allocate a new mbuf for the SGE */ 3052 rc = bxe_alloc_rx_sge_mbuf(fp, sge_idx); 3053 if (rc) { 3054 /* Leave all remaining SGEs in the ring! */ 3055 return (rc); 3056 } 3057 3058 /* update the fragment length */ 3059 m_frag->m_len = frag_len; 3060 3061 /* concatenate the fragment to the head mbuf */ 3062 m_cat(m, m_frag); 3063 fp->eth_q_stats.mbuf_alloc_sge--; 3064 3065 /* update the TPA mbuf size and remaining fragment size */ 3066 m->m_pkthdr.len += frag_len; 3067 frag_size -= frag_len; 3068 } 3069 3070 BLOGD(sc, DBG_LRO, 3071 "fp[%02d].tpa[%02d] TPA fill done frag_size=%d\n", 3072 fp->index, queue, frag_size); 3073 3074 return (rc); 3075 } 3076 3077 static inline void 3078 bxe_clear_sge_mask_next_elems(struct bxe_fastpath *fp) 3079 { 3080 int i, j; 3081 3082 for (i = 1; i <= RX_SGE_NUM_PAGES; i++) { 3083 int idx = RX_SGE_TOTAL_PER_PAGE * i - 1; 3084 3085 for (j = 0; j < 2; j++) { 3086 BIT_VEC64_CLEAR_BIT(fp->sge_mask, idx); 3087 idx--; 3088 } 3089 } 3090 } 3091 3092 static inline void 3093 bxe_init_sge_ring_bit_mask(struct bxe_fastpath *fp) 3094 { 3095 /* set the mask to all 1's, it's faster to compare to 0 than to 0xf's */ 3096 memset(fp->sge_mask, 0xff, sizeof(fp->sge_mask)); 3097 3098 /* 3099 * Clear the two last indices in the page to 1. These are the indices that 3100 * correspond to the "next" element, hence will never be indicated and 3101 * should be removed from the calculations. 3102 */ 3103 bxe_clear_sge_mask_next_elems(fp); 3104 } 3105 3106 static inline void 3107 bxe_update_last_max_sge(struct bxe_fastpath *fp, 3108 uint16_t idx) 3109 { 3110 uint16_t last_max = fp->last_max_sge; 3111 3112 if (SUB_S16(idx, last_max) > 0) { 3113 fp->last_max_sge = idx; 3114 } 3115 } 3116 3117 static inline void 3118 bxe_update_sge_prod(struct bxe_softc *sc, 3119 struct bxe_fastpath *fp, 3120 uint16_t sge_len, 3121 struct eth_end_agg_rx_cqe *cqe) 3122 { 3123 uint16_t last_max, last_elem, first_elem; 3124 uint16_t delta = 0; 3125 uint16_t i; 3126 3127 if (!sge_len) { 3128 return; 3129 } 3130 3131 /* first mark all used pages */ 3132 for (i = 0; i < sge_len; i++) { 3133 BIT_VEC64_CLEAR_BIT(fp->sge_mask, 3134 RX_SGE(le16toh(cqe->sgl_or_raw_data.sgl[i]))); 3135 } 3136 3137 BLOGD(sc, DBG_LRO, 3138 "fp[%02d] fp_cqe->sgl[%d] = %d\n", 3139 fp->index, sge_len - 1, 3140 le16toh(cqe->sgl_or_raw_data.sgl[sge_len - 1])); 3141 3142 /* assume that the last SGE index is the biggest */ 3143 bxe_update_last_max_sge(fp, 3144 le16toh(cqe->sgl_or_raw_data.sgl[sge_len - 1])); 3145 3146 last_max = RX_SGE(fp->last_max_sge); 3147 last_elem = last_max >> BIT_VEC64_ELEM_SHIFT; 3148 first_elem = RX_SGE(fp->rx_sge_prod) >> BIT_VEC64_ELEM_SHIFT; 3149 3150 /* if ring is not full */ 3151 if (last_elem + 1 != first_elem) { 3152 last_elem++; 3153 } 3154 3155 /* now update the prod */ 3156 for (i = first_elem; i != last_elem; i = RX_SGE_NEXT_MASK_ELEM(i)) { 3157 if (__predict_true(fp->sge_mask[i])) { 3158 break; 3159 } 3160 3161 fp->sge_mask[i] = BIT_VEC64_ELEM_ONE_MASK; 3162 delta += BIT_VEC64_ELEM_SZ; 3163 } 3164 3165 if (delta > 0) { 3166 fp->rx_sge_prod += delta; 3167 /* clear page-end entries */ 3168 bxe_clear_sge_mask_next_elems(fp); 3169 } 3170 3171 BLOGD(sc, DBG_LRO, 3172 "fp[%02d] fp->last_max_sge=%d fp->rx_sge_prod=%d\n", 3173 fp->index, fp->last_max_sge, fp->rx_sge_prod); 3174 } 3175 3176 /* 3177 * The aggregation on the current TPA queue has completed. Pull the individual 3178 * mbuf fragments together into a single mbuf, perform all necessary checksum 3179 * calculations, and send the resuting mbuf to the stack. 3180 */ 3181 static void 3182 bxe_tpa_stop(struct bxe_softc *sc, 3183 struct bxe_fastpath *fp, 3184 struct bxe_sw_tpa_info *tpa_info, 3185 uint16_t queue, 3186 uint16_t pages, 3187 struct eth_end_agg_rx_cqe *cqe, 3188 uint16_t cqe_idx) 3189 { 3190 struct ifnet *ifp = sc->ifnet; 3191 struct mbuf *m; 3192 int rc = 0; 3193 3194 BLOGD(sc, DBG_LRO, 3195 "fp[%02d].tpa[%02d] pad=%d pkt_len=%d pages=%d vlan=%d\n", 3196 fp->index, queue, tpa_info->placement_offset, 3197 le16toh(cqe->pkt_len), pages, tpa_info->vlan_tag); 3198 3199 m = tpa_info->bd.m; 3200 3201 /* allocate a replacement before modifying existing mbuf */ 3202 rc = bxe_alloc_rx_tpa_mbuf(fp, queue); 3203 if (rc) { 3204 /* drop the frame and log an error */ 3205 fp->eth_q_stats.rx_soft_errors++; 3206 goto bxe_tpa_stop_exit; 3207 } 3208 3209 /* we have a replacement, fixup the current mbuf */ 3210 m_adj(m, tpa_info->placement_offset); 3211 m->m_pkthdr.len = m->m_len = tpa_info->len_on_bd; 3212 3213 /* mark the checksums valid (taken care of by the firmware) */ 3214 fp->eth_q_stats.rx_ofld_frames_csum_ip++; 3215 fp->eth_q_stats.rx_ofld_frames_csum_tcp_udp++; 3216 m->m_pkthdr.csum_data = 0xffff; 3217 m->m_pkthdr.csum_flags |= (CSUM_IP_CHECKED | 3218 CSUM_IP_VALID | 3219 CSUM_DATA_VALID | 3220 CSUM_PSEUDO_HDR); 3221 3222 /* aggregate all of the SGEs into a single mbuf */ 3223 rc = bxe_fill_frag_mbuf(sc, fp, tpa_info, queue, pages, m, cqe, cqe_idx); 3224 if (rc) { 3225 /* drop the packet and log an error */ 3226 fp->eth_q_stats.rx_soft_errors++; 3227 m_freem(m); 3228 } else { 3229 if (tpa_info->parsing_flags & PARSING_FLAGS_VLAN) { 3230 m->m_pkthdr.ether_vtag = tpa_info->vlan_tag; 3231 m->m_flags |= M_VLANTAG; 3232 } 3233 3234 /* assign packet to this interface interface */ 3235 m->m_pkthdr.rcvif = ifp; 3236 3237 #if __FreeBSD_version >= 800000 3238 /* specify what RSS queue was used for this flow */ 3239 m->m_pkthdr.flowid = fp->index; 3240 m->m_flags |= M_FLOWID; 3241 #endif 3242 3243 ifp->if_ipackets++; 3244 fp->eth_q_stats.rx_tpa_pkts++; 3245 3246 /* pass the frame to the stack */ 3247 (*ifp->if_input)(ifp, m); 3248 } 3249 3250 /* we passed an mbuf up the stack or dropped the frame */ 3251 fp->eth_q_stats.mbuf_alloc_tpa--; 3252 3253 bxe_tpa_stop_exit: 3254 3255 fp->rx_tpa_info[queue].state = BXE_TPA_STATE_STOP; 3256 fp->rx_tpa_queue_used &= ~(1 << queue); 3257 } 3258 3259 static uint8_t 3260 bxe_rxeof(struct bxe_softc *sc, 3261 struct bxe_fastpath *fp) 3262 { 3263 struct ifnet *ifp = sc->ifnet; 3264 uint16_t bd_cons, bd_prod, bd_prod_fw, comp_ring_cons; 3265 uint16_t hw_cq_cons, sw_cq_cons, sw_cq_prod; 3266 int rx_pkts = 0; 3267 int rc; 3268 3269 BXE_FP_RX_LOCK(fp); 3270 3271 /* CQ "next element" is of the size of the regular element */ 3272 hw_cq_cons = le16toh(*fp->rx_cq_cons_sb); 3273 if ((hw_cq_cons & RCQ_USABLE_PER_PAGE) == RCQ_USABLE_PER_PAGE) { 3274 hw_cq_cons++; 3275 } 3276 3277 bd_cons = fp->rx_bd_cons; 3278 bd_prod = fp->rx_bd_prod; 3279 bd_prod_fw = bd_prod; 3280 sw_cq_cons = fp->rx_cq_cons; 3281 sw_cq_prod = fp->rx_cq_prod; 3282 3283 /* 3284 * Memory barrier necessary as speculative reads of the rx 3285 * buffer can be ahead of the index in the status block 3286 */ 3287 rmb(); 3288 3289 BLOGD(sc, DBG_RX, 3290 "fp[%02d] Rx START hw_cq_cons=%u sw_cq_cons=%u\n", 3291 fp->index, hw_cq_cons, sw_cq_cons); 3292 3293 while (sw_cq_cons != hw_cq_cons) { 3294 struct bxe_sw_rx_bd *rx_buf = NULL; 3295 union eth_rx_cqe *cqe; 3296 struct eth_fast_path_rx_cqe *cqe_fp; 3297 uint8_t cqe_fp_flags; 3298 enum eth_rx_cqe_type cqe_fp_type; 3299 uint16_t len, pad; 3300 struct mbuf *m = NULL; 3301 3302 comp_ring_cons = RCQ(sw_cq_cons); 3303 bd_prod = RX_BD(bd_prod); 3304 bd_cons = RX_BD(bd_cons); 3305 3306 cqe = &fp->rcq_chain[comp_ring_cons]; 3307 cqe_fp = &cqe->fast_path_cqe; 3308 cqe_fp_flags = cqe_fp->type_error_flags; 3309 cqe_fp_type = cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE; 3310 3311 BLOGD(sc, DBG_RX, 3312 "fp[%02d] Rx hw_cq_cons=%d hw_sw_cons=%d " 3313 "BD prod=%d cons=%d CQE type=0x%x err=0x%x " 3314 "status=0x%x rss_hash=0x%x vlan=0x%x len=%u\n", 3315 fp->index, 3316 hw_cq_cons, 3317 sw_cq_cons, 3318 bd_prod, 3319 bd_cons, 3320 CQE_TYPE(cqe_fp_flags), 3321 cqe_fp_flags, 3322 cqe_fp->status_flags, 3323 le32toh(cqe_fp->rss_hash_result), 3324 le16toh(cqe_fp->vlan_tag), 3325 le16toh(cqe_fp->pkt_len_or_gro_seg_len)); 3326 3327 /* is this a slowpath msg? */ 3328 if (__predict_false(CQE_TYPE_SLOW(cqe_fp_type))) { 3329 bxe_sp_event(sc, fp, cqe); 3330 goto next_cqe; 3331 } 3332 3333 rx_buf = &fp->rx_mbuf_chain[bd_cons]; 3334 3335 if (!CQE_TYPE_FAST(cqe_fp_type)) { 3336 struct bxe_sw_tpa_info *tpa_info; 3337 uint16_t frag_size, pages; 3338 uint8_t queue; 3339 3340 #if 0 3341 /* sanity check */ 3342 if (!fp->tpa_enable && 3343 (CQE_TYPE_START(cqe_fp_type) || CQE_TYPE_STOP(cqe_fp_type))) { 3344 BLOGE(sc, "START/STOP packet while !tpa_enable type (0x%x)\n", 3345 CQE_TYPE(cqe_fp_type)); 3346 } 3347 #endif 3348 3349 if (CQE_TYPE_START(cqe_fp_type)) { 3350 bxe_tpa_start(sc, fp, cqe_fp->queue_index, 3351 bd_cons, bd_prod, cqe_fp); 3352 m = NULL; /* packet not ready yet */ 3353 goto next_rx; 3354 } 3355 3356 KASSERT(CQE_TYPE_STOP(cqe_fp_type), 3357 ("CQE type is not STOP! (0x%x)\n", cqe_fp_type)); 3358 3359 queue = cqe->end_agg_cqe.queue_index; 3360 tpa_info = &fp->rx_tpa_info[queue]; 3361 3362 BLOGD(sc, DBG_LRO, "fp[%02d].tpa[%02d] TPA STOP\n", 3363 fp->index, queue); 3364 3365 frag_size = (le16toh(cqe->end_agg_cqe.pkt_len) - 3366 tpa_info->len_on_bd); 3367 pages = SGE_PAGE_ALIGN(frag_size) >> SGE_PAGE_SHIFT; 3368 3369 bxe_tpa_stop(sc, fp, tpa_info, queue, pages, 3370 &cqe->end_agg_cqe, comp_ring_cons); 3371 3372 bxe_update_sge_prod(sc, fp, pages, &cqe->end_agg_cqe); 3373 3374 goto next_cqe; 3375 } 3376 3377 /* non TPA */ 3378 3379 /* is this an error packet? */ 3380 if (__predict_false(cqe_fp_flags & 3381 ETH_FAST_PATH_RX_CQE_PHY_DECODE_ERR_FLG)) { 3382 BLOGE(sc, "flags 0x%x rx packet %u\n", cqe_fp_flags, sw_cq_cons); 3383 fp->eth_q_stats.rx_soft_errors++; 3384 goto next_rx; 3385 } 3386 3387 len = le16toh(cqe_fp->pkt_len_or_gro_seg_len); 3388 pad = cqe_fp->placement_offset; 3389 3390 m = rx_buf->m; 3391 3392 if (__predict_false(m == NULL)) { 3393 BLOGE(sc, "No mbuf in rx chain descriptor %d for fp[%02d]\n", 3394 bd_cons, fp->index); 3395 goto next_rx; 3396 } 3397 3398 /* XXX double copy if packet length under a threshold */ 3399 3400 /* 3401 * If all the buffer descriptors are filled with mbufs then fill in 3402 * the current consumer index with a new BD. Else if a maximum Rx 3403 * buffer limit is imposed then fill in the next producer index. 3404 */ 3405 rc = bxe_alloc_rx_bd_mbuf(fp, bd_cons, 3406 (sc->max_rx_bufs != RX_BD_USABLE) ? 3407 bd_prod : bd_cons); 3408 if (rc != 0) { 3409 BLOGE(sc, "mbuf alloc fail for fp[%02d] rx chain (%d)\n", 3410 fp->index, rc); 3411 fp->eth_q_stats.rx_soft_errors++; 3412 3413 if (sc->max_rx_bufs != RX_BD_USABLE) { 3414 /* copy this consumer index to the producer index */ 3415 memcpy(&fp->rx_mbuf_chain[bd_prod], rx_buf, 3416 sizeof(struct bxe_sw_rx_bd)); 3417 memset(rx_buf, 0, sizeof(struct bxe_sw_rx_bd)); 3418 } 3419 3420 goto next_rx; 3421 } 3422 3423 /* current mbuf was detached from the bd */ 3424 fp->eth_q_stats.mbuf_alloc_rx--; 3425 3426 /* we allocated a replacement mbuf, fixup the current one */ 3427 m_adj(m, pad); 3428 m->m_pkthdr.len = m->m_len = len; 3429 3430 /* assign packet to this interface interface */ 3431 m->m_pkthdr.rcvif = ifp; 3432 3433 /* assume no hardware checksum has complated */ 3434 m->m_pkthdr.csum_flags = 0; 3435 3436 /* validate checksum if offload enabled */ 3437 if (ifp->if_capenable & IFCAP_RXCSUM) { 3438 /* check for a valid IP frame */ 3439 if (!(cqe->fast_path_cqe.status_flags & 3440 ETH_FAST_PATH_RX_CQE_IP_XSUM_NO_VALIDATION_FLG)) { 3441 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 3442 if (__predict_false(cqe_fp_flags & 3443 ETH_FAST_PATH_RX_CQE_IP_BAD_XSUM_FLG)) { 3444 fp->eth_q_stats.rx_hw_csum_errors++; 3445 } else { 3446 fp->eth_q_stats.rx_ofld_frames_csum_ip++; 3447 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 3448 } 3449 } 3450 3451 /* check for a valid TCP/UDP frame */ 3452 if (!(cqe->fast_path_cqe.status_flags & 3453 ETH_FAST_PATH_RX_CQE_L4_XSUM_NO_VALIDATION_FLG)) { 3454 if (__predict_false(cqe_fp_flags & 3455 ETH_FAST_PATH_RX_CQE_L4_BAD_XSUM_FLG)) { 3456 fp->eth_q_stats.rx_hw_csum_errors++; 3457 } else { 3458 fp->eth_q_stats.rx_ofld_frames_csum_tcp_udp++; 3459 m->m_pkthdr.csum_data = 0xFFFF; 3460 m->m_pkthdr.csum_flags |= (CSUM_DATA_VALID | 3461 CSUM_PSEUDO_HDR); 3462 } 3463 } 3464 } 3465 3466 /* if there is a VLAN tag then flag that info */ 3467 if (cqe->fast_path_cqe.pars_flags.flags & PARSING_FLAGS_VLAN) { 3468 m->m_pkthdr.ether_vtag = cqe->fast_path_cqe.vlan_tag; 3469 m->m_flags |= M_VLANTAG; 3470 } 3471 3472 #if __FreeBSD_version >= 800000 3473 /* specify what RSS queue was used for this flow */ 3474 m->m_pkthdr.flowid = fp->index; 3475 m->m_flags |= M_FLOWID; 3476 #endif 3477 3478 next_rx: 3479 3480 bd_cons = RX_BD_NEXT(bd_cons); 3481 bd_prod = RX_BD_NEXT(bd_prod); 3482 bd_prod_fw = RX_BD_NEXT(bd_prod_fw); 3483 3484 /* pass the frame to the stack */ 3485 if (__predict_true(m != NULL)) { 3486 ifp->if_ipackets++; 3487 rx_pkts++; 3488 (*ifp->if_input)(ifp, m); 3489 } 3490 3491 next_cqe: 3492 3493 sw_cq_prod = RCQ_NEXT(sw_cq_prod); 3494 sw_cq_cons = RCQ_NEXT(sw_cq_cons); 3495 3496 /* limit spinning on the queue */ 3497 if (rx_pkts == sc->rx_budget) { 3498 fp->eth_q_stats.rx_budget_reached++; 3499 break; 3500 } 3501 } /* while work to do */ 3502 3503 fp->rx_bd_cons = bd_cons; 3504 fp->rx_bd_prod = bd_prod_fw; 3505 fp->rx_cq_cons = sw_cq_cons; 3506 fp->rx_cq_prod = sw_cq_prod; 3507 3508 /* Update producers */ 3509 bxe_update_rx_prod(sc, fp, bd_prod_fw, sw_cq_prod, fp->rx_sge_prod); 3510 3511 fp->eth_q_stats.rx_pkts += rx_pkts; 3512 fp->eth_q_stats.rx_calls++; 3513 3514 BXE_FP_RX_UNLOCK(fp); 3515 3516 return (sw_cq_cons != hw_cq_cons); 3517 } 3518 3519 static uint16_t 3520 bxe_free_tx_pkt(struct bxe_softc *sc, 3521 struct bxe_fastpath *fp, 3522 uint16_t idx) 3523 { 3524 struct bxe_sw_tx_bd *tx_buf = &fp->tx_mbuf_chain[idx]; 3525 struct eth_tx_start_bd *tx_start_bd; 3526 uint16_t bd_idx = TX_BD(tx_buf->first_bd); 3527 uint16_t new_cons; 3528 int nbd; 3529 3530 /* unmap the mbuf from non-paged memory */ 3531 bus_dmamap_unload(fp->tx_mbuf_tag, tx_buf->m_map); 3532 3533 tx_start_bd = &fp->tx_chain[bd_idx].start_bd; 3534 nbd = le16toh(tx_start_bd->nbd) - 1; 3535 3536 #if 0 3537 if ((nbd - 1) > (MAX_MBUF_FRAGS + 2)) { 3538 bxe_panic(sc, ("BAD nbd!\n")); 3539 } 3540 #endif 3541 3542 new_cons = (tx_buf->first_bd + nbd); 3543 3544 #if 0 3545 struct eth_tx_bd *tx_data_bd; 3546 3547 /* 3548 * The following code doesn't do anything but is left here 3549 * for clarity on what the new value of new_cons skipped. 3550 */ 3551 3552 /* get the next bd */ 3553 bd_idx = TX_BD(TX_BD_NEXT(bd_idx)); 3554 3555 /* skip the parse bd */ 3556 --nbd; 3557 bd_idx = TX_BD(TX_BD_NEXT(bd_idx)); 3558 3559 /* skip the TSO split header bd since they have no mapping */ 3560 if (tx_buf->flags & BXE_TSO_SPLIT_BD) { 3561 --nbd; 3562 bd_idx = TX_BD(TX_BD_NEXT(bd_idx)); 3563 } 3564 3565 /* now free frags */ 3566 while (nbd > 0) { 3567 tx_data_bd = &fp->tx_chain[bd_idx].reg_bd; 3568 if (--nbd) { 3569 bd_idx = TX_BD(TX_BD_NEXT(bd_idx)); 3570 } 3571 } 3572 #endif 3573 3574 /* free the mbuf */ 3575 if (__predict_true(tx_buf->m != NULL)) { 3576 m_freem(tx_buf->m); 3577 fp->eth_q_stats.mbuf_alloc_tx--; 3578 } else { 3579 fp->eth_q_stats.tx_chain_lost_mbuf++; 3580 } 3581 3582 tx_buf->m = NULL; 3583 tx_buf->first_bd = 0; 3584 3585 return (new_cons); 3586 } 3587 3588 /* transmit timeout watchdog */ 3589 static int 3590 bxe_watchdog(struct bxe_softc *sc, 3591 struct bxe_fastpath *fp) 3592 { 3593 BXE_FP_TX_LOCK(fp); 3594 3595 if ((fp->watchdog_timer == 0) || (--fp->watchdog_timer)) { 3596 BXE_FP_TX_UNLOCK(fp); 3597 return (0); 3598 } 3599 3600 BLOGE(sc, "TX watchdog timeout on fp[%02d], resetting!\n", fp->index); 3601 3602 BXE_FP_TX_UNLOCK(fp); 3603 3604 atomic_store_rel_long(&sc->chip_tq_flags, CHIP_TQ_REINIT); 3605 taskqueue_enqueue(sc->chip_tq, &sc->chip_tq_task); 3606 3607 return (-1); 3608 } 3609 3610 /* processes transmit completions */ 3611 static uint8_t 3612 bxe_txeof(struct bxe_softc *sc, 3613 struct bxe_fastpath *fp) 3614 { 3615 struct ifnet *ifp = sc->ifnet; 3616 uint16_t bd_cons, hw_cons, sw_cons, pkt_cons; 3617 uint16_t tx_bd_avail; 3618 3619 BXE_FP_TX_LOCK_ASSERT(fp); 3620 3621 bd_cons = fp->tx_bd_cons; 3622 hw_cons = le16toh(*fp->tx_cons_sb); 3623 sw_cons = fp->tx_pkt_cons; 3624 3625 while (sw_cons != hw_cons) { 3626 pkt_cons = TX_BD(sw_cons); 3627 3628 BLOGD(sc, DBG_TX, 3629 "TX: fp[%d]: hw_cons=%u sw_cons=%u pkt_cons=%u\n", 3630 fp->index, hw_cons, sw_cons, pkt_cons); 3631 3632 bd_cons = bxe_free_tx_pkt(sc, fp, pkt_cons); 3633 3634 sw_cons++; 3635 } 3636 3637 fp->tx_pkt_cons = sw_cons; 3638 fp->tx_bd_cons = bd_cons; 3639 3640 BLOGD(sc, DBG_TX, 3641 "TX done: fp[%d]: hw_cons=%u sw_cons=%u sw_prod=%u\n", 3642 fp->index, hw_cons, fp->tx_pkt_cons, fp->tx_pkt_prod); 3643 3644 mb(); 3645 3646 tx_bd_avail = bxe_tx_avail(sc, fp); 3647 3648 if (tx_bd_avail < BXE_TX_CLEANUP_THRESHOLD) { 3649 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 3650 } else { 3651 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3652 } 3653 3654 if (fp->tx_pkt_prod != fp->tx_pkt_cons) { 3655 /* reset the watchdog timer if there are pending transmits */ 3656 fp->watchdog_timer = BXE_TX_TIMEOUT; 3657 return (TRUE); 3658 } else { 3659 /* clear watchdog when there are no pending transmits */ 3660 fp->watchdog_timer = 0; 3661 return (FALSE); 3662 } 3663 } 3664 3665 static void 3666 bxe_drain_tx_queues(struct bxe_softc *sc) 3667 { 3668 struct bxe_fastpath *fp; 3669 int i, count; 3670 3671 /* wait until all TX fastpath tasks have completed */ 3672 for (i = 0; i < sc->num_queues; i++) { 3673 fp = &sc->fp[i]; 3674 3675 count = 1000; 3676 3677 while (bxe_has_tx_work(fp)) { 3678 3679 BXE_FP_TX_LOCK(fp); 3680 bxe_txeof(sc, fp); 3681 BXE_FP_TX_UNLOCK(fp); 3682 3683 if (count == 0) { 3684 BLOGE(sc, "Timeout waiting for fp[%d] " 3685 "transmits to complete!\n", i); 3686 bxe_panic(sc, ("tx drain failure\n")); 3687 return; 3688 } 3689 3690 count--; 3691 DELAY(1000); 3692 rmb(); 3693 } 3694 } 3695 3696 return; 3697 } 3698 3699 static int 3700 bxe_del_all_macs(struct bxe_softc *sc, 3701 struct ecore_vlan_mac_obj *mac_obj, 3702 int mac_type, 3703 uint8_t wait_for_comp) 3704 { 3705 unsigned long ramrod_flags = 0, vlan_mac_flags = 0; 3706 int rc; 3707 3708 /* wait for completion of requested */ 3709 if (wait_for_comp) { 3710 bxe_set_bit(RAMROD_COMP_WAIT, &ramrod_flags); 3711 } 3712 3713 /* Set the mac type of addresses we want to clear */ 3714 bxe_set_bit(mac_type, &vlan_mac_flags); 3715 3716 rc = mac_obj->delete_all(sc, mac_obj, &vlan_mac_flags, &ramrod_flags); 3717 if (rc < 0) { 3718 BLOGE(sc, "Failed to delete MACs (%d)\n", rc); 3719 } 3720 3721 return (rc); 3722 } 3723 3724 static int 3725 bxe_fill_accept_flags(struct bxe_softc *sc, 3726 uint32_t rx_mode, 3727 unsigned long *rx_accept_flags, 3728 unsigned long *tx_accept_flags) 3729 { 3730 /* Clear the flags first */ 3731 *rx_accept_flags = 0; 3732 *tx_accept_flags = 0; 3733 3734 switch (rx_mode) { 3735 case BXE_RX_MODE_NONE: 3736 /* 3737 * 'drop all' supersedes any accept flags that may have been 3738 * passed to the function. 3739 */ 3740 break; 3741 3742 case BXE_RX_MODE_NORMAL: 3743 bxe_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags); 3744 bxe_set_bit(ECORE_ACCEPT_MULTICAST, rx_accept_flags); 3745 bxe_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags); 3746 3747 /* internal switching mode */ 3748 bxe_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags); 3749 bxe_set_bit(ECORE_ACCEPT_MULTICAST, tx_accept_flags); 3750 bxe_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags); 3751 3752 break; 3753 3754 case BXE_RX_MODE_ALLMULTI: 3755 bxe_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags); 3756 bxe_set_bit(ECORE_ACCEPT_ALL_MULTICAST, rx_accept_flags); 3757 bxe_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags); 3758 3759 /* internal switching mode */ 3760 bxe_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags); 3761 bxe_set_bit(ECORE_ACCEPT_ALL_MULTICAST, tx_accept_flags); 3762 bxe_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags); 3763 3764 break; 3765 3766 case BXE_RX_MODE_PROMISC: 3767 /* 3768 * According to deffinition of SI mode, iface in promisc mode 3769 * should receive matched and unmatched (in resolution of port) 3770 * unicast packets. 3771 */ 3772 bxe_set_bit(ECORE_ACCEPT_UNMATCHED, rx_accept_flags); 3773 bxe_set_bit(ECORE_ACCEPT_UNICAST, rx_accept_flags); 3774 bxe_set_bit(ECORE_ACCEPT_ALL_MULTICAST, rx_accept_flags); 3775 bxe_set_bit(ECORE_ACCEPT_BROADCAST, rx_accept_flags); 3776 3777 /* internal switching mode */ 3778 bxe_set_bit(ECORE_ACCEPT_ALL_MULTICAST, tx_accept_flags); 3779 bxe_set_bit(ECORE_ACCEPT_BROADCAST, tx_accept_flags); 3780 3781 if (IS_MF_SI(sc)) { 3782 bxe_set_bit(ECORE_ACCEPT_ALL_UNICAST, tx_accept_flags); 3783 } else { 3784 bxe_set_bit(ECORE_ACCEPT_UNICAST, tx_accept_flags); 3785 } 3786 3787 break; 3788 3789 default: 3790 BLOGE(sc, "Unknown rx_mode (%d)\n", rx_mode); 3791 return (-1); 3792 } 3793 3794 /* Set ACCEPT_ANY_VLAN as we do not enable filtering by VLAN */ 3795 if (rx_mode != BXE_RX_MODE_NONE) { 3796 bxe_set_bit(ECORE_ACCEPT_ANY_VLAN, rx_accept_flags); 3797 bxe_set_bit(ECORE_ACCEPT_ANY_VLAN, tx_accept_flags); 3798 } 3799 3800 return (0); 3801 } 3802 3803 static int 3804 bxe_set_q_rx_mode(struct bxe_softc *sc, 3805 uint8_t cl_id, 3806 unsigned long rx_mode_flags, 3807 unsigned long rx_accept_flags, 3808 unsigned long tx_accept_flags, 3809 unsigned long ramrod_flags) 3810 { 3811 struct ecore_rx_mode_ramrod_params ramrod_param; 3812 int rc; 3813 3814 memset(&ramrod_param, 0, sizeof(ramrod_param)); 3815 3816 /* Prepare ramrod parameters */ 3817 ramrod_param.cid = 0; 3818 ramrod_param.cl_id = cl_id; 3819 ramrod_param.rx_mode_obj = &sc->rx_mode_obj; 3820 ramrod_param.func_id = SC_FUNC(sc); 3821 3822 ramrod_param.pstate = &sc->sp_state; 3823 ramrod_param.state = ECORE_FILTER_RX_MODE_PENDING; 3824 3825 ramrod_param.rdata = BXE_SP(sc, rx_mode_rdata); 3826 ramrod_param.rdata_mapping = BXE_SP_MAPPING(sc, rx_mode_rdata); 3827 3828 bxe_set_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state); 3829 3830 ramrod_param.ramrod_flags = ramrod_flags; 3831 ramrod_param.rx_mode_flags = rx_mode_flags; 3832 3833 ramrod_param.rx_accept_flags = rx_accept_flags; 3834 ramrod_param.tx_accept_flags = tx_accept_flags; 3835 3836 rc = ecore_config_rx_mode(sc, &ramrod_param); 3837 if (rc < 0) { 3838 BLOGE(sc, "Set rx_mode %d failed\n", sc->rx_mode); 3839 return (rc); 3840 } 3841 3842 return (0); 3843 } 3844 3845 static int 3846 bxe_set_storm_rx_mode(struct bxe_softc *sc) 3847 { 3848 unsigned long rx_mode_flags = 0, ramrod_flags = 0; 3849 unsigned long rx_accept_flags = 0, tx_accept_flags = 0; 3850 int rc; 3851 3852 rc = bxe_fill_accept_flags(sc, sc->rx_mode, &rx_accept_flags, 3853 &tx_accept_flags); 3854 if (rc) { 3855 return (rc); 3856 } 3857 3858 bxe_set_bit(RAMROD_RX, &ramrod_flags); 3859 bxe_set_bit(RAMROD_TX, &ramrod_flags); 3860 3861 /* XXX ensure all fastpath have same cl_id and/or move it to bxe_softc */ 3862 return (bxe_set_q_rx_mode(sc, sc->fp[0].cl_id, rx_mode_flags, 3863 rx_accept_flags, tx_accept_flags, 3864 ramrod_flags)); 3865 } 3866 3867 /* returns the "mcp load_code" according to global load_count array */ 3868 static int 3869 bxe_nic_load_no_mcp(struct bxe_softc *sc) 3870 { 3871 int path = SC_PATH(sc); 3872 int port = SC_PORT(sc); 3873 3874 BLOGI(sc, "NO MCP - load counts[%d] %d, %d, %d\n", 3875 path, load_count[path][0], load_count[path][1], 3876 load_count[path][2]); 3877 load_count[path][0]++; 3878 load_count[path][1 + port]++; 3879 BLOGI(sc, "NO MCP - new load counts[%d] %d, %d, %d\n", 3880 path, load_count[path][0], load_count[path][1], 3881 load_count[path][2]); 3882 if (load_count[path][0] == 1) { 3883 return (FW_MSG_CODE_DRV_LOAD_COMMON); 3884 } else if (load_count[path][1 + port] == 1) { 3885 return (FW_MSG_CODE_DRV_LOAD_PORT); 3886 } else { 3887 return (FW_MSG_CODE_DRV_LOAD_FUNCTION); 3888 } 3889 } 3890 3891 /* returns the "mcp load_code" according to global load_count array */ 3892 static int 3893 bxe_nic_unload_no_mcp(struct bxe_softc *sc) 3894 { 3895 int port = SC_PORT(sc); 3896 int path = SC_PATH(sc); 3897 3898 BLOGI(sc, "NO MCP - load counts[%d] %d, %d, %d\n", 3899 path, load_count[path][0], load_count[path][1], 3900 load_count[path][2]); 3901 load_count[path][0]--; 3902 load_count[path][1 + port]--; 3903 BLOGI(sc, "NO MCP - new load counts[%d] %d, %d, %d\n", 3904 path, load_count[path][0], load_count[path][1], 3905 load_count[path][2]); 3906 if (load_count[path][0] == 0) { 3907 return (FW_MSG_CODE_DRV_UNLOAD_COMMON); 3908 } else if (load_count[path][1 + port] == 0) { 3909 return (FW_MSG_CODE_DRV_UNLOAD_PORT); 3910 } else { 3911 return (FW_MSG_CODE_DRV_UNLOAD_FUNCTION); 3912 } 3913 } 3914 3915 /* request unload mode from the MCP: COMMON, PORT or FUNCTION */ 3916 static uint32_t 3917 bxe_send_unload_req(struct bxe_softc *sc, 3918 int unload_mode) 3919 { 3920 uint32_t reset_code = 0; 3921 #if 0 3922 int port = SC_PORT(sc); 3923 int path = SC_PATH(sc); 3924 #endif 3925 3926 /* Select the UNLOAD request mode */ 3927 if (unload_mode == UNLOAD_NORMAL) { 3928 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; 3929 } 3930 #if 0 3931 else if (sc->flags & BXE_NO_WOL_FLAG) { 3932 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP; 3933 } else if (sc->wol) { 3934 uint32_t emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0; 3935 uint8_t *mac_addr = sc->dev->dev_addr; 3936 uint32_t val; 3937 uint16_t pmc; 3938 3939 /* 3940 * The mac address is written to entries 1-4 to 3941 * preserve entry 0 which is used by the PMF 3942 */ 3943 uint8_t entry = (SC_VN(sc) + 1)*8; 3944 3945 val = (mac_addr[0] << 8) | mac_addr[1]; 3946 EMAC_WR(sc, EMAC_REG_EMAC_MAC_MATCH + entry, val); 3947 3948 val = (mac_addr[2] << 24) | (mac_addr[3] << 16) | 3949 (mac_addr[4] << 8) | mac_addr[5]; 3950 EMAC_WR(sc, EMAC_REG_EMAC_MAC_MATCH + entry + 4, val); 3951 3952 /* Enable the PME and clear the status */ 3953 pmc = pci_read_config(sc->dev, 3954 (sc->devinfo.pcie_pm_cap_reg + 3955 PCIR_POWER_STATUS), 3956 2); 3957 pmc |= PCIM_PSTAT_PMEENABLE | PCIM_PSTAT_PME; 3958 pci_write_config(sc->dev, 3959 (sc->devinfo.pcie_pm_cap_reg + 3960 PCIR_POWER_STATUS), 3961 pmc, 4); 3962 3963 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_EN; 3964 } 3965 #endif 3966 else { 3967 reset_code = DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS; 3968 } 3969 3970 /* Send the request to the MCP */ 3971 if (!BXE_NOMCP(sc)) { 3972 reset_code = bxe_fw_command(sc, reset_code, 0); 3973 } else { 3974 reset_code = bxe_nic_unload_no_mcp(sc); 3975 } 3976 3977 return (reset_code); 3978 } 3979 3980 /* send UNLOAD_DONE command to the MCP */ 3981 static void 3982 bxe_send_unload_done(struct bxe_softc *sc, 3983 uint8_t keep_link) 3984 { 3985 uint32_t reset_param = 3986 keep_link ? DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET : 0; 3987 3988 /* Report UNLOAD_DONE to MCP */ 3989 if (!BXE_NOMCP(sc)) { 3990 bxe_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, reset_param); 3991 } 3992 } 3993 3994 static int 3995 bxe_func_wait_started(struct bxe_softc *sc) 3996 { 3997 int tout = 50; 3998 3999 if (!sc->port.pmf) { 4000 return (0); 4001 } 4002 4003 /* 4004 * (assumption: No Attention from MCP at this stage) 4005 * PMF probably in the middle of TX disable/enable transaction 4006 * 1. Sync IRS for default SB 4007 * 2. Sync SP queue - this guarantees us that attention handling started 4008 * 3. Wait, that TX disable/enable transaction completes 4009 * 4010 * 1+2 guarantee that if DCBX attention was scheduled it already changed 4011 * pending bit of transaction from STARTED-->TX_STOPPED, if we already 4012 * received completion for the transaction the state is TX_STOPPED. 4013 * State will return to STARTED after completion of TX_STOPPED-->STARTED 4014 * transaction. 4015 */ 4016 4017 /* XXX make sure default SB ISR is done */ 4018 /* need a way to synchronize an irq (intr_mtx?) */ 4019 4020 /* XXX flush any work queues */ 4021 4022 while (ecore_func_get_state(sc, &sc->func_obj) != 4023 ECORE_F_STATE_STARTED && tout--) { 4024 DELAY(20000); 4025 } 4026 4027 if (ecore_func_get_state(sc, &sc->func_obj) != ECORE_F_STATE_STARTED) { 4028 /* 4029 * Failed to complete the transaction in a "good way" 4030 * Force both transactions with CLR bit. 4031 */ 4032 struct ecore_func_state_params func_params = { NULL }; 4033 4034 BLOGE(sc, "Unexpected function state! " 4035 "Forcing STARTED-->TX_STOPPED-->STARTED\n"); 4036 4037 func_params.f_obj = &sc->func_obj; 4038 bxe_set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags); 4039 4040 /* STARTED-->TX_STOPPED */ 4041 func_params.cmd = ECORE_F_CMD_TX_STOP; 4042 ecore_func_state_change(sc, &func_params); 4043 4044 /* TX_STOPPED-->STARTED */ 4045 func_params.cmd = ECORE_F_CMD_TX_START; 4046 return (ecore_func_state_change(sc, &func_params)); 4047 } 4048 4049 return (0); 4050 } 4051 4052 static int 4053 bxe_stop_queue(struct bxe_softc *sc, 4054 int index) 4055 { 4056 struct bxe_fastpath *fp = &sc->fp[index]; 4057 struct ecore_queue_state_params q_params = { NULL }; 4058 int rc; 4059 4060 BLOGD(sc, DBG_LOAD, "stopping queue %d cid %d\n", index, fp->index); 4061 4062 q_params.q_obj = &sc->sp_objs[fp->index].q_obj; 4063 /* We want to wait for completion in this context */ 4064 bxe_set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags); 4065 4066 /* Stop the primary connection: */ 4067 4068 /* ...halt the connection */ 4069 q_params.cmd = ECORE_Q_CMD_HALT; 4070 rc = ecore_queue_state_change(sc, &q_params); 4071 if (rc) { 4072 return (rc); 4073 } 4074 4075 /* ...terminate the connection */ 4076 q_params.cmd = ECORE_Q_CMD_TERMINATE; 4077 memset(&q_params.params.terminate, 0, sizeof(q_params.params.terminate)); 4078 q_params.params.terminate.cid_index = FIRST_TX_COS_INDEX; 4079 rc = ecore_queue_state_change(sc, &q_params); 4080 if (rc) { 4081 return (rc); 4082 } 4083 4084 /* ...delete cfc entry */ 4085 q_params.cmd = ECORE_Q_CMD_CFC_DEL; 4086 memset(&q_params.params.cfc_del, 0, sizeof(q_params.params.cfc_del)); 4087 q_params.params.cfc_del.cid_index = FIRST_TX_COS_INDEX; 4088 return (ecore_queue_state_change(sc, &q_params)); 4089 } 4090 4091 /* wait for the outstanding SP commands */ 4092 static inline uint8_t 4093 bxe_wait_sp_comp(struct bxe_softc *sc, 4094 unsigned long mask) 4095 { 4096 unsigned long tmp; 4097 int tout = 5000; /* wait for 5 secs tops */ 4098 4099 while (tout--) { 4100 mb(); 4101 if (!(atomic_load_acq_long(&sc->sp_state) & mask)) { 4102 return (TRUE); 4103 } 4104 4105 DELAY(1000); 4106 } 4107 4108 mb(); 4109 4110 tmp = atomic_load_acq_long(&sc->sp_state); 4111 if (tmp & mask) { 4112 BLOGE(sc, "Filtering completion timed out: " 4113 "sp_state 0x%lx, mask 0x%lx\n", 4114 tmp, mask); 4115 return (FALSE); 4116 } 4117 4118 return (FALSE); 4119 } 4120 4121 static int 4122 bxe_func_stop(struct bxe_softc *sc) 4123 { 4124 struct ecore_func_state_params func_params = { NULL }; 4125 int rc; 4126 4127 /* prepare parameters for function state transitions */ 4128 bxe_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); 4129 func_params.f_obj = &sc->func_obj; 4130 func_params.cmd = ECORE_F_CMD_STOP; 4131 4132 /* 4133 * Try to stop the function the 'good way'. If it fails (in case 4134 * of a parity error during bxe_chip_cleanup()) and we are 4135 * not in a debug mode, perform a state transaction in order to 4136 * enable further HW_RESET transaction. 4137 */ 4138 rc = ecore_func_state_change(sc, &func_params); 4139 if (rc) { 4140 BLOGE(sc, "FUNC_STOP ramrod failed. " 4141 "Running a dry transaction\n"); 4142 bxe_set_bit(RAMROD_DRV_CLR_ONLY, &func_params.ramrod_flags); 4143 return (ecore_func_state_change(sc, &func_params)); 4144 } 4145 4146 return (0); 4147 } 4148 4149 static int 4150 bxe_reset_hw(struct bxe_softc *sc, 4151 uint32_t load_code) 4152 { 4153 struct ecore_func_state_params func_params = { NULL }; 4154 4155 /* Prepare parameters for function state transitions */ 4156 bxe_set_bit(RAMROD_COMP_WAIT, &func_params.ramrod_flags); 4157 4158 func_params.f_obj = &sc->func_obj; 4159 func_params.cmd = ECORE_F_CMD_HW_RESET; 4160 4161 func_params.params.hw_init.load_phase = load_code; 4162 4163 return (ecore_func_state_change(sc, &func_params)); 4164 } 4165 4166 static void 4167 bxe_int_disable_sync(struct bxe_softc *sc, 4168 int disable_hw) 4169 { 4170 if (disable_hw) { 4171 /* prevent the HW from sending interrupts */ 4172 bxe_int_disable(sc); 4173 } 4174 4175 /* XXX need a way to synchronize ALL irqs (intr_mtx?) */ 4176 /* make sure all ISRs are done */ 4177 4178 /* XXX make sure sp_task is not running */ 4179 /* cancel and flush work queues */ 4180 } 4181 4182 static void 4183 bxe_chip_cleanup(struct bxe_softc *sc, 4184 uint32_t unload_mode, 4185 uint8_t keep_link) 4186 { 4187 int port = SC_PORT(sc); 4188 struct ecore_mcast_ramrod_params rparam = { NULL }; 4189 uint32_t reset_code; 4190 int i, rc = 0; 4191 4192 bxe_drain_tx_queues(sc); 4193 4194 /* give HW time to discard old tx messages */ 4195 DELAY(1000); 4196 4197 /* Clean all ETH MACs */ 4198 rc = bxe_del_all_macs(sc, &sc->sp_objs[0].mac_obj, ECORE_ETH_MAC, FALSE); 4199 if (rc < 0) { 4200 BLOGE(sc, "Failed to delete all ETH MACs (%d)\n", rc); 4201 } 4202 4203 /* Clean up UC list */ 4204 rc = bxe_del_all_macs(sc, &sc->sp_objs[0].mac_obj, ECORE_UC_LIST_MAC, TRUE); 4205 if (rc < 0) { 4206 BLOGE(sc, "Failed to delete UC MACs list (%d)\n", rc); 4207 } 4208 4209 /* Disable LLH */ 4210 if (!CHIP_IS_E1(sc)) { 4211 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port*8, 0); 4212 } 4213 4214 /* Set "drop all" to stop Rx */ 4215 4216 /* 4217 * We need to take the BXE_MCAST_LOCK() here in order to prevent 4218 * a race between the completion code and this code. 4219 */ 4220 BXE_MCAST_LOCK(sc); 4221 4222 if (bxe_test_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state)) { 4223 bxe_set_bit(ECORE_FILTER_RX_MODE_SCHED, &sc->sp_state); 4224 } else { 4225 bxe_set_storm_rx_mode(sc); 4226 } 4227 4228 /* Clean up multicast configuration */ 4229 rparam.mcast_obj = &sc->mcast_obj; 4230 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_DEL); 4231 if (rc < 0) { 4232 BLOGE(sc, "Failed to send DEL MCAST command (%d)\n", rc); 4233 } 4234 4235 BXE_MCAST_UNLOCK(sc); 4236 4237 // XXX bxe_iov_chip_cleanup(sc); 4238 4239 /* 4240 * Send the UNLOAD_REQUEST to the MCP. This will return if 4241 * this function should perform FUNCTION, PORT, or COMMON HW 4242 * reset. 4243 */ 4244 reset_code = bxe_send_unload_req(sc, unload_mode); 4245 4246 /* 4247 * (assumption: No Attention from MCP at this stage) 4248 * PMF probably in the middle of TX disable/enable transaction 4249 */ 4250 rc = bxe_func_wait_started(sc); 4251 if (rc) { 4252 BLOGE(sc, "bxe_func_wait_started failed\n"); 4253 } 4254 4255 /* 4256 * Close multi and leading connections 4257 * Completions for ramrods are collected in a synchronous way 4258 */ 4259 for (i = 0; i < sc->num_queues; i++) { 4260 if (bxe_stop_queue(sc, i)) { 4261 goto unload_error; 4262 } 4263 } 4264 4265 /* 4266 * If SP settings didn't get completed so far - something 4267 * very wrong has happen. 4268 */ 4269 if (!bxe_wait_sp_comp(sc, ~0x0UL)) { 4270 BLOGE(sc, "Common slow path ramrods got stuck!\n"); 4271 } 4272 4273 unload_error: 4274 4275 rc = bxe_func_stop(sc); 4276 if (rc) { 4277 BLOGE(sc, "Function stop failed!\n"); 4278 } 4279 4280 /* disable HW interrupts */ 4281 bxe_int_disable_sync(sc, TRUE); 4282 4283 /* detach interrupts */ 4284 bxe_interrupt_detach(sc); 4285 4286 /* Reset the chip */ 4287 rc = bxe_reset_hw(sc, reset_code); 4288 if (rc) { 4289 BLOGE(sc, "Hardware reset failed\n"); 4290 } 4291 4292 /* Report UNLOAD_DONE to MCP */ 4293 bxe_send_unload_done(sc, keep_link); 4294 } 4295 4296 static void 4297 bxe_disable_close_the_gate(struct bxe_softc *sc) 4298 { 4299 uint32_t val; 4300 int port = SC_PORT(sc); 4301 4302 BLOGD(sc, DBG_LOAD, 4303 "Disabling 'close the gates'\n"); 4304 4305 if (CHIP_IS_E1(sc)) { 4306 uint32_t addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : 4307 MISC_REG_AEU_MASK_ATTN_FUNC_0; 4308 val = REG_RD(sc, addr); 4309 val &= ~(0x300); 4310 REG_WR(sc, addr, val); 4311 } else { 4312 val = REG_RD(sc, MISC_REG_AEU_GENERAL_MASK); 4313 val &= ~(MISC_AEU_GENERAL_MASK_REG_AEU_PXP_CLOSE_MASK | 4314 MISC_AEU_GENERAL_MASK_REG_AEU_NIG_CLOSE_MASK); 4315 REG_WR(sc, MISC_REG_AEU_GENERAL_MASK, val); 4316 } 4317 } 4318 4319 /* 4320 * Cleans the object that have internal lists without sending 4321 * ramrods. Should be run when interrutps are disabled. 4322 */ 4323 static void 4324 bxe_squeeze_objects(struct bxe_softc *sc) 4325 { 4326 unsigned long ramrod_flags = 0, vlan_mac_flags = 0; 4327 struct ecore_mcast_ramrod_params rparam = { NULL }; 4328 struct ecore_vlan_mac_obj *mac_obj = &sc->sp_objs->mac_obj; 4329 int rc; 4330 4331 /* Cleanup MACs' object first... */ 4332 4333 /* Wait for completion of requested */ 4334 bxe_set_bit(RAMROD_COMP_WAIT, &ramrod_flags); 4335 /* Perform a dry cleanup */ 4336 bxe_set_bit(RAMROD_DRV_CLR_ONLY, &ramrod_flags); 4337 4338 /* Clean ETH primary MAC */ 4339 bxe_set_bit(ECORE_ETH_MAC, &vlan_mac_flags); 4340 rc = mac_obj->delete_all(sc, &sc->sp_objs->mac_obj, &vlan_mac_flags, 4341 &ramrod_flags); 4342 if (rc != 0) { 4343 BLOGE(sc, "Failed to clean ETH MACs (%d)\n", rc); 4344 } 4345 4346 /* Cleanup UC list */ 4347 vlan_mac_flags = 0; 4348 bxe_set_bit(ECORE_UC_LIST_MAC, &vlan_mac_flags); 4349 rc = mac_obj->delete_all(sc, mac_obj, &vlan_mac_flags, 4350 &ramrod_flags); 4351 if (rc != 0) { 4352 BLOGE(sc, "Failed to clean UC list MACs (%d)\n", rc); 4353 } 4354 4355 /* Now clean mcast object... */ 4356 4357 rparam.mcast_obj = &sc->mcast_obj; 4358 bxe_set_bit(RAMROD_DRV_CLR_ONLY, &rparam.ramrod_flags); 4359 4360 /* Add a DEL command... */ 4361 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_DEL); 4362 if (rc < 0) { 4363 BLOGE(sc, "Failed to send DEL MCAST command (%d)\n", rc); 4364 } 4365 4366 /* now wait until all pending commands are cleared */ 4367 4368 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT); 4369 while (rc != 0) { 4370 if (rc < 0) { 4371 BLOGE(sc, "Failed to clean MCAST object (%d)\n", rc); 4372 return; 4373 } 4374 4375 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT); 4376 } 4377 } 4378 4379 /* stop the controller */ 4380 static __noinline int 4381 bxe_nic_unload(struct bxe_softc *sc, 4382 uint32_t unload_mode, 4383 uint8_t keep_link) 4384 { 4385 uint8_t global = FALSE; 4386 uint32_t val; 4387 4388 BXE_CORE_LOCK_ASSERT(sc); 4389 4390 BLOGD(sc, DBG_LOAD, "Starting NIC unload...\n"); 4391 4392 /* mark driver as unloaded in shmem2 */ 4393 if (IS_PF(sc) && SHMEM2_HAS(sc, drv_capabilities_flag)) { 4394 val = SHMEM2_RD(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)]); 4395 SHMEM2_WR(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)], 4396 val & ~DRV_FLAGS_CAPABILITIES_LOADED_L2); 4397 } 4398 4399 if (IS_PF(sc) && sc->recovery_state != BXE_RECOVERY_DONE && 4400 (sc->state == BXE_STATE_CLOSED || sc->state == BXE_STATE_ERROR)) { 4401 /* 4402 * We can get here if the driver has been unloaded 4403 * during parity error recovery and is either waiting for a 4404 * leader to complete or for other functions to unload and 4405 * then ifconfig down has been issued. In this case we want to 4406 * unload and let other functions to complete a recovery 4407 * process. 4408 */ 4409 sc->recovery_state = BXE_RECOVERY_DONE; 4410 sc->is_leader = 0; 4411 bxe_release_leader_lock(sc); 4412 mb(); 4413 4414 BLOGD(sc, DBG_LOAD, "Releasing a leadership...\n"); 4415 BLOGE(sc, "Can't unload in closed or error state\n"); 4416 return (-1); 4417 } 4418 4419 /* 4420 * Nothing to do during unload if previous bxe_nic_load() 4421 * did not completed succesfully - all resourses are released. 4422 */ 4423 if ((sc->state == BXE_STATE_CLOSED) || 4424 (sc->state == BXE_STATE_ERROR)) { 4425 return (0); 4426 } 4427 4428 sc->state = BXE_STATE_CLOSING_WAITING_HALT; 4429 mb(); 4430 4431 /* stop tx */ 4432 bxe_tx_disable(sc); 4433 4434 sc->rx_mode = BXE_RX_MODE_NONE; 4435 /* XXX set rx mode ??? */ 4436 4437 if (IS_PF(sc)) { 4438 /* set ALWAYS_ALIVE bit in shmem */ 4439 sc->fw_drv_pulse_wr_seq |= DRV_PULSE_ALWAYS_ALIVE; 4440 4441 bxe_drv_pulse(sc); 4442 4443 bxe_stats_handle(sc, STATS_EVENT_STOP); 4444 bxe_save_statistics(sc); 4445 } 4446 4447 /* wait till consumers catch up with producers in all queues */ 4448 bxe_drain_tx_queues(sc); 4449 4450 /* if VF indicate to PF this function is going down (PF will delete sp 4451 * elements and clear initializations 4452 */ 4453 if (IS_VF(sc)) { 4454 ; /* bxe_vfpf_close_vf(sc); */ 4455 } else if (unload_mode != UNLOAD_RECOVERY) { 4456 /* if this is a normal/close unload need to clean up chip */ 4457 bxe_chip_cleanup(sc, unload_mode, keep_link); 4458 } else { 4459 /* Send the UNLOAD_REQUEST to the MCP */ 4460 bxe_send_unload_req(sc, unload_mode); 4461 4462 /* 4463 * Prevent transactions to host from the functions on the 4464 * engine that doesn't reset global blocks in case of global 4465 * attention once gloabl blocks are reset and gates are opened 4466 * (the engine which leader will perform the recovery 4467 * last). 4468 */ 4469 if (!CHIP_IS_E1x(sc)) { 4470 bxe_pf_disable(sc); 4471 } 4472 4473 /* disable HW interrupts */ 4474 bxe_int_disable_sync(sc, TRUE); 4475 4476 /* detach interrupts */ 4477 bxe_interrupt_detach(sc); 4478 4479 /* Report UNLOAD_DONE to MCP */ 4480 bxe_send_unload_done(sc, FALSE); 4481 } 4482 4483 /* 4484 * At this stage no more interrupts will arrive so we may safely clean 4485 * the queue'able objects here in case they failed to get cleaned so far. 4486 */ 4487 if (IS_PF(sc)) { 4488 bxe_squeeze_objects(sc); 4489 } 4490 4491 /* There should be no more pending SP commands at this stage */ 4492 sc->sp_state = 0; 4493 4494 sc->port.pmf = 0; 4495 4496 bxe_free_fp_buffers(sc); 4497 4498 if (IS_PF(sc)) { 4499 bxe_free_mem(sc); 4500 } 4501 4502 bxe_free_fw_stats_mem(sc); 4503 4504 sc->state = BXE_STATE_CLOSED; 4505 4506 /* 4507 * Check if there are pending parity attentions. If there are - set 4508 * RECOVERY_IN_PROGRESS. 4509 */ 4510 if (IS_PF(sc) && bxe_chk_parity_attn(sc, &global, FALSE)) { 4511 bxe_set_reset_in_progress(sc); 4512 4513 /* Set RESET_IS_GLOBAL if needed */ 4514 if (global) { 4515 bxe_set_reset_global(sc); 4516 } 4517 } 4518 4519 /* 4520 * The last driver must disable a "close the gate" if there is no 4521 * parity attention or "process kill" pending. 4522 */ 4523 if (IS_PF(sc) && !bxe_clear_pf_load(sc) && 4524 bxe_reset_is_done(sc, SC_PATH(sc))) { 4525 bxe_disable_close_the_gate(sc); 4526 } 4527 4528 BLOGD(sc, DBG_LOAD, "Ended NIC unload\n"); 4529 4530 return (0); 4531 } 4532 4533 /* 4534 * Called by the OS to set various media options (i.e. link, speed, etc.) when 4535 * the user runs "ifconfig bxe media ..." or "ifconfig bxe mediaopt ...". 4536 */ 4537 static int 4538 bxe_ifmedia_update(struct ifnet *ifp) 4539 { 4540 struct bxe_softc *sc = (struct bxe_softc *)ifp->if_softc; 4541 struct ifmedia *ifm; 4542 4543 ifm = &sc->ifmedia; 4544 4545 /* We only support Ethernet media type. */ 4546 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) { 4547 return (EINVAL); 4548 } 4549 4550 switch (IFM_SUBTYPE(ifm->ifm_media)) { 4551 case IFM_AUTO: 4552 break; 4553 case IFM_10G_CX4: 4554 case IFM_10G_SR: 4555 case IFM_10G_T: 4556 case IFM_10G_TWINAX: 4557 default: 4558 /* We don't support changing the media type. */ 4559 BLOGD(sc, DBG_LOAD, "Invalid media type (%d)\n", 4560 IFM_SUBTYPE(ifm->ifm_media)); 4561 return (EINVAL); 4562 } 4563 4564 return (0); 4565 } 4566 4567 /* 4568 * Called by the OS to get the current media status (i.e. link, speed, etc.). 4569 */ 4570 static void 4571 bxe_ifmedia_status(struct ifnet *ifp, struct ifmediareq *ifmr) 4572 { 4573 struct bxe_softc *sc = ifp->if_softc; 4574 4575 /* Report link down if the driver isn't running. */ 4576 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 4577 ifmr->ifm_active |= IFM_NONE; 4578 return; 4579 } 4580 4581 /* Setup the default interface info. */ 4582 ifmr->ifm_status = IFM_AVALID; 4583 ifmr->ifm_active = IFM_ETHER; 4584 4585 if (sc->link_vars.link_up) { 4586 ifmr->ifm_status |= IFM_ACTIVE; 4587 } else { 4588 ifmr->ifm_active |= IFM_NONE; 4589 return; 4590 } 4591 4592 ifmr->ifm_active |= sc->media; 4593 4594 if (sc->link_vars.duplex == DUPLEX_FULL) { 4595 ifmr->ifm_active |= IFM_FDX; 4596 } else { 4597 ifmr->ifm_active |= IFM_HDX; 4598 } 4599 } 4600 4601 static int 4602 bxe_ioctl_nvram(struct bxe_softc *sc, 4603 uint32_t priv_op, 4604 struct ifreq *ifr) 4605 { 4606 struct bxe_nvram_data nvdata_base; 4607 struct bxe_nvram_data *nvdata; 4608 int len; 4609 int error = 0; 4610 4611 copyin(ifr->ifr_data, &nvdata_base, sizeof(nvdata_base)); 4612 4613 len = (sizeof(struct bxe_nvram_data) + 4614 nvdata_base.len - 4615 sizeof(uint32_t)); 4616 4617 if (len > sizeof(struct bxe_nvram_data)) { 4618 if ((nvdata = (struct bxe_nvram_data *) 4619 malloc(len, M_DEVBUF, 4620 (M_NOWAIT | M_ZERO))) == NULL) { 4621 BLOGE(sc, "BXE_IOC_RD_NVRAM malloc failed\n"); 4622 return (1); 4623 } 4624 memcpy(nvdata, &nvdata_base, sizeof(struct bxe_nvram_data)); 4625 } else { 4626 nvdata = &nvdata_base; 4627 } 4628 4629 if (priv_op == BXE_IOC_RD_NVRAM) { 4630 BLOGD(sc, DBG_IOCTL, "IOC_RD_NVRAM 0x%x %d\n", 4631 nvdata->offset, nvdata->len); 4632 error = bxe_nvram_read(sc, 4633 nvdata->offset, 4634 (uint8_t *)nvdata->value, 4635 nvdata->len); 4636 copyout(nvdata, ifr->ifr_data, len); 4637 } else { /* BXE_IOC_WR_NVRAM */ 4638 BLOGD(sc, DBG_IOCTL, "IOC_WR_NVRAM 0x%x %d\n", 4639 nvdata->offset, nvdata->len); 4640 copyin(ifr->ifr_data, nvdata, len); 4641 error = bxe_nvram_write(sc, 4642 nvdata->offset, 4643 (uint8_t *)nvdata->value, 4644 nvdata->len); 4645 } 4646 4647 if (len > sizeof(struct bxe_nvram_data)) { 4648 free(nvdata, M_DEVBUF); 4649 } 4650 4651 return (error); 4652 } 4653 4654 static int 4655 bxe_ioctl_stats_show(struct bxe_softc *sc, 4656 uint32_t priv_op, 4657 struct ifreq *ifr) 4658 { 4659 const size_t str_size = (BXE_NUM_ETH_STATS * STAT_NAME_LEN); 4660 const size_t stats_size = (BXE_NUM_ETH_STATS * sizeof(uint64_t)); 4661 caddr_t p_tmp; 4662 uint32_t *offset; 4663 int i; 4664 4665 switch (priv_op) 4666 { 4667 case BXE_IOC_STATS_SHOW_NUM: 4668 memset(ifr->ifr_data, 0, sizeof(union bxe_stats_show_data)); 4669 ((union bxe_stats_show_data *)ifr->ifr_data)->desc.num = 4670 BXE_NUM_ETH_STATS; 4671 ((union bxe_stats_show_data *)ifr->ifr_data)->desc.len = 4672 STAT_NAME_LEN; 4673 return (0); 4674 4675 case BXE_IOC_STATS_SHOW_STR: 4676 memset(ifr->ifr_data, 0, str_size); 4677 p_tmp = ifr->ifr_data; 4678 for (i = 0; i < BXE_NUM_ETH_STATS; i++) { 4679 strcpy(p_tmp, bxe_eth_stats_arr[i].string); 4680 p_tmp += STAT_NAME_LEN; 4681 } 4682 return (0); 4683 4684 case BXE_IOC_STATS_SHOW_CNT: 4685 memset(ifr->ifr_data, 0, stats_size); 4686 p_tmp = ifr->ifr_data; 4687 for (i = 0; i < BXE_NUM_ETH_STATS; i++) { 4688 offset = ((uint32_t *)&sc->eth_stats + 4689 bxe_eth_stats_arr[i].offset); 4690 switch (bxe_eth_stats_arr[i].size) { 4691 case 4: 4692 *((uint64_t *)p_tmp) = (uint64_t)*offset; 4693 break; 4694 case 8: 4695 *((uint64_t *)p_tmp) = HILO_U64(*offset, *(offset + 1)); 4696 break; 4697 default: 4698 *((uint64_t *)p_tmp) = 0; 4699 } 4700 p_tmp += sizeof(uint64_t); 4701 } 4702 return (0); 4703 4704 default: 4705 return (-1); 4706 } 4707 } 4708 4709 static void 4710 bxe_handle_chip_tq(void *context, 4711 int pending) 4712 { 4713 struct bxe_softc *sc = (struct bxe_softc *)context; 4714 long work = atomic_load_acq_long(&sc->chip_tq_flags); 4715 4716 switch (work) 4717 { 4718 case CHIP_TQ_START: 4719 if ((sc->ifnet->if_flags & IFF_UP) && 4720 !(sc->ifnet->if_drv_flags & IFF_DRV_RUNNING)) { 4721 /* start the interface */ 4722 BLOGD(sc, DBG_LOAD, "Starting the interface...\n"); 4723 BXE_CORE_LOCK(sc); 4724 bxe_init_locked(sc); 4725 BXE_CORE_UNLOCK(sc); 4726 } 4727 break; 4728 4729 case CHIP_TQ_STOP: 4730 if (!(sc->ifnet->if_flags & IFF_UP) && 4731 (sc->ifnet->if_drv_flags & IFF_DRV_RUNNING)) { 4732 /* bring down the interface */ 4733 BLOGD(sc, DBG_LOAD, "Stopping the interface...\n"); 4734 bxe_periodic_stop(sc); 4735 BXE_CORE_LOCK(sc); 4736 bxe_stop_locked(sc); 4737 BXE_CORE_UNLOCK(sc); 4738 } 4739 break; 4740 4741 case CHIP_TQ_REINIT: 4742 if (sc->ifnet->if_drv_flags & IFF_DRV_RUNNING) { 4743 /* restart the interface */ 4744 BLOGD(sc, DBG_LOAD, "Restarting the interface...\n"); 4745 bxe_periodic_stop(sc); 4746 BXE_CORE_LOCK(sc); 4747 bxe_stop_locked(sc); 4748 bxe_init_locked(sc); 4749 BXE_CORE_UNLOCK(sc); 4750 } 4751 break; 4752 4753 default: 4754 break; 4755 } 4756 } 4757 4758 /* 4759 * Handles any IOCTL calls from the operating system. 4760 * 4761 * Returns: 4762 * 0 = Success, >0 Failure 4763 */ 4764 static int 4765 bxe_ioctl(struct ifnet *ifp, 4766 u_long command, 4767 caddr_t data) 4768 { 4769 struct bxe_softc *sc = ifp->if_softc; 4770 struct ifreq *ifr = (struct ifreq *)data; 4771 struct bxe_nvram_data *nvdata; 4772 uint32_t priv_op; 4773 int mask = 0; 4774 int reinit = 0; 4775 int error = 0; 4776 4777 int mtu_min = (ETH_MIN_PACKET_SIZE - ETH_HLEN); 4778 int mtu_max = (MJUM9BYTES - ETH_OVERHEAD - IP_HEADER_ALIGNMENT_PADDING); 4779 4780 switch (command) 4781 { 4782 case SIOCSIFMTU: 4783 BLOGD(sc, DBG_IOCTL, "Received SIOCSIFMTU ioctl (mtu=%d)\n", 4784 ifr->ifr_mtu); 4785 4786 if (sc->mtu == ifr->ifr_mtu) { 4787 /* nothing to change */ 4788 break; 4789 } 4790 4791 if ((ifr->ifr_mtu < mtu_min) || (ifr->ifr_mtu > mtu_max)) { 4792 BLOGE(sc, "Unsupported MTU size %d (range is %d-%d)\n", 4793 ifr->ifr_mtu, mtu_min, mtu_max); 4794 error = EINVAL; 4795 break; 4796 } 4797 4798 atomic_store_rel_int((volatile unsigned int *)&sc->mtu, 4799 (unsigned long)ifr->ifr_mtu); 4800 atomic_store_rel_long((volatile unsigned long *)&ifp->if_mtu, 4801 (unsigned long)ifr->ifr_mtu); 4802 4803 reinit = 1; 4804 break; 4805 4806 case SIOCSIFFLAGS: 4807 /* toggle the interface state up or down */ 4808 BLOGD(sc, DBG_IOCTL, "Received SIOCSIFFLAGS ioctl\n"); 4809 4810 /* check if the interface is up */ 4811 if (ifp->if_flags & IFF_UP) { 4812 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 4813 /* set the receive mode flags */ 4814 bxe_set_rx_mode(sc); 4815 } else { 4816 atomic_store_rel_long(&sc->chip_tq_flags, CHIP_TQ_START); 4817 taskqueue_enqueue(sc->chip_tq, &sc->chip_tq_task); 4818 } 4819 } else { 4820 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 4821 atomic_store_rel_long(&sc->chip_tq_flags, CHIP_TQ_STOP); 4822 taskqueue_enqueue(sc->chip_tq, &sc->chip_tq_task); 4823 } 4824 } 4825 4826 break; 4827 4828 case SIOCADDMULTI: 4829 case SIOCDELMULTI: 4830 /* add/delete multicast addresses */ 4831 BLOGD(sc, DBG_IOCTL, "Received SIOCADDMULTI/SIOCDELMULTI ioctl\n"); 4832 4833 /* check if the interface is up */ 4834 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 4835 /* set the receive mode flags */ 4836 bxe_set_rx_mode(sc); 4837 } 4838 4839 break; 4840 4841 case SIOCSIFCAP: 4842 /* find out which capabilities have changed */ 4843 mask = (ifr->ifr_reqcap ^ ifp->if_capenable); 4844 4845 BLOGD(sc, DBG_IOCTL, "Received SIOCSIFCAP ioctl (mask=0x%08x)\n", 4846 mask); 4847 4848 /* toggle the LRO capabilites enable flag */ 4849 if (mask & IFCAP_LRO) { 4850 ifp->if_capenable ^= IFCAP_LRO; 4851 BLOGD(sc, DBG_IOCTL, "Turning LRO %s\n", 4852 (ifp->if_capenable & IFCAP_LRO) ? "ON" : "OFF"); 4853 reinit = 1; 4854 } 4855 4856 /* toggle the TXCSUM checksum capabilites enable flag */ 4857 if (mask & IFCAP_TXCSUM) { 4858 ifp->if_capenable ^= IFCAP_TXCSUM; 4859 BLOGD(sc, DBG_IOCTL, "Turning TXCSUM %s\n", 4860 (ifp->if_capenable & IFCAP_TXCSUM) ? "ON" : "OFF"); 4861 if (ifp->if_capenable & IFCAP_TXCSUM) { 4862 ifp->if_hwassist = (CSUM_IP | 4863 CSUM_TCP | 4864 CSUM_UDP | 4865 CSUM_TSO | 4866 CSUM_TCP_IPV6 | 4867 CSUM_UDP_IPV6); 4868 } else { 4869 ifp->if_hwassist = 0; 4870 } 4871 } 4872 4873 /* toggle the RXCSUM checksum capabilities enable flag */ 4874 if (mask & IFCAP_RXCSUM) { 4875 ifp->if_capenable ^= IFCAP_RXCSUM; 4876 BLOGD(sc, DBG_IOCTL, "Turning RXCSUM %s\n", 4877 (ifp->if_capenable & IFCAP_RXCSUM) ? "ON" : "OFF"); 4878 if (ifp->if_capenable & IFCAP_RXCSUM) { 4879 ifp->if_hwassist = (CSUM_IP | 4880 CSUM_TCP | 4881 CSUM_UDP | 4882 CSUM_TSO | 4883 CSUM_TCP_IPV6 | 4884 CSUM_UDP_IPV6); 4885 } else { 4886 ifp->if_hwassist = 0; 4887 } 4888 } 4889 4890 /* toggle TSO4 capabilities enabled flag */ 4891 if (mask & IFCAP_TSO4) { 4892 ifp->if_capenable ^= IFCAP_TSO4; 4893 BLOGD(sc, DBG_IOCTL, "Turning TSO4 %s\n", 4894 (ifp->if_capenable & IFCAP_TSO4) ? "ON" : "OFF"); 4895 } 4896 4897 /* toggle TSO6 capabilities enabled flag */ 4898 if (mask & IFCAP_TSO6) { 4899 ifp->if_capenable ^= IFCAP_TSO6; 4900 BLOGD(sc, DBG_IOCTL, "Turning TSO6 %s\n", 4901 (ifp->if_capenable & IFCAP_TSO6) ? "ON" : "OFF"); 4902 } 4903 4904 /* toggle VLAN_HWTSO capabilities enabled flag */ 4905 if (mask & IFCAP_VLAN_HWTSO) { 4906 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 4907 BLOGD(sc, DBG_IOCTL, "Turning VLAN_HWTSO %s\n", 4908 (ifp->if_capenable & IFCAP_VLAN_HWTSO) ? "ON" : "OFF"); 4909 } 4910 4911 /* toggle VLAN_HWCSUM capabilities enabled flag */ 4912 if (mask & IFCAP_VLAN_HWCSUM) { 4913 /* XXX investigate this... */ 4914 BLOGE(sc, "Changing VLAN_HWCSUM is not supported!\n"); 4915 error = EINVAL; 4916 } 4917 4918 /* toggle VLAN_MTU capabilities enable flag */ 4919 if (mask & IFCAP_VLAN_MTU) { 4920 /* XXX investigate this... */ 4921 BLOGE(sc, "Changing VLAN_MTU is not supported!\n"); 4922 error = EINVAL; 4923 } 4924 4925 /* toggle VLAN_HWTAGGING capabilities enabled flag */ 4926 if (mask & IFCAP_VLAN_HWTAGGING) { 4927 /* XXX investigate this... */ 4928 BLOGE(sc, "Changing VLAN_HWTAGGING is not supported!\n"); 4929 error = EINVAL; 4930 } 4931 4932 /* toggle VLAN_HWFILTER capabilities enabled flag */ 4933 if (mask & IFCAP_VLAN_HWFILTER) { 4934 /* XXX investigate this... */ 4935 BLOGE(sc, "Changing VLAN_HWFILTER is not supported!\n"); 4936 error = EINVAL; 4937 } 4938 4939 /* XXX not yet... 4940 * IFCAP_WOL_MAGIC 4941 */ 4942 4943 break; 4944 4945 case SIOCSIFMEDIA: 4946 case SIOCGIFMEDIA: 4947 /* set/get interface media */ 4948 BLOGD(sc, DBG_IOCTL, 4949 "Received SIOCSIFMEDIA/SIOCGIFMEDIA ioctl (cmd=%lu)\n", 4950 (command & 0xff)); 4951 error = ifmedia_ioctl(ifp, ifr, &sc->ifmedia, command); 4952 break; 4953 4954 case SIOCGPRIVATE_0: 4955 copyin(ifr->ifr_data, &priv_op, sizeof(priv_op)); 4956 4957 switch (priv_op) 4958 { 4959 case BXE_IOC_RD_NVRAM: 4960 case BXE_IOC_WR_NVRAM: 4961 nvdata = (struct bxe_nvram_data *)ifr->ifr_data; 4962 BLOGD(sc, DBG_IOCTL, 4963 "Received Private NVRAM ioctl addr=0x%x size=%u\n", 4964 nvdata->offset, nvdata->len); 4965 error = bxe_ioctl_nvram(sc, priv_op, ifr); 4966 break; 4967 4968 case BXE_IOC_STATS_SHOW_NUM: 4969 case BXE_IOC_STATS_SHOW_STR: 4970 case BXE_IOC_STATS_SHOW_CNT: 4971 BLOGD(sc, DBG_IOCTL, "Received Private Stats ioctl (%d)\n", 4972 priv_op); 4973 error = bxe_ioctl_stats_show(sc, priv_op, ifr); 4974 break; 4975 4976 default: 4977 BLOGW(sc, "Received Private Unknown ioctl (%d)\n", priv_op); 4978 error = EINVAL; 4979 break; 4980 } 4981 4982 break; 4983 4984 default: 4985 BLOGD(sc, DBG_IOCTL, "Received Unknown Ioctl (cmd=%lu)\n", 4986 (command & 0xff)); 4987 error = ether_ioctl(ifp, command, data); 4988 break; 4989 } 4990 4991 if (reinit && (sc->ifnet->if_drv_flags & IFF_DRV_RUNNING)) { 4992 BLOGD(sc, DBG_LOAD | DBG_IOCTL, 4993 "Re-initializing hardware from IOCTL change\n"); 4994 atomic_store_rel_long(&sc->chip_tq_flags, CHIP_TQ_REINIT); 4995 taskqueue_enqueue(sc->chip_tq, &sc->chip_tq_task); 4996 } 4997 4998 return (error); 4999 } 5000 5001 static __noinline void 5002 bxe_dump_mbuf(struct bxe_softc *sc, 5003 struct mbuf *m, 5004 uint8_t contents) 5005 { 5006 char * type; 5007 int i = 0; 5008 5009 if (!(sc->debug & DBG_MBUF)) { 5010 return; 5011 } 5012 5013 if (m == NULL) { 5014 BLOGD(sc, DBG_MBUF, "mbuf: null pointer\n"); 5015 return; 5016 } 5017 5018 while (m) { 5019 BLOGD(sc, DBG_MBUF, 5020 "%02d: mbuf=%p m_len=%d m_flags=0x%b m_data=%p\n", 5021 i, m, m->m_len, m->m_flags, M_FLAG_BITS, m->m_data); 5022 5023 if (m->m_flags & M_PKTHDR) { 5024 BLOGD(sc, DBG_MBUF, 5025 "%02d: - m_pkthdr: tot_len=%d flags=0x%b csum_flags=%b\n", 5026 i, m->m_pkthdr.len, m->m_flags, M_FLAG_BITS, 5027 (int)m->m_pkthdr.csum_flags, CSUM_BITS); 5028 } 5029 5030 if (m->m_flags & M_EXT) { 5031 switch (m->m_ext.ext_type) { 5032 case EXT_CLUSTER: type = "EXT_CLUSTER"; break; 5033 case EXT_SFBUF: type = "EXT_SFBUF"; break; 5034 case EXT_JUMBOP: type = "EXT_JUMBOP"; break; 5035 case EXT_JUMBO9: type = "EXT_JUMBO9"; break; 5036 case EXT_JUMBO16: type = "EXT_JUMBO16"; break; 5037 case EXT_PACKET: type = "EXT_PACKET"; break; 5038 case EXT_MBUF: type = "EXT_MBUF"; break; 5039 case EXT_NET_DRV: type = "EXT_NET_DRV"; break; 5040 case EXT_MOD_TYPE: type = "EXT_MOD_TYPE"; break; 5041 case EXT_DISPOSABLE: type = "EXT_DISPOSABLE"; break; 5042 case EXT_EXTREF: type = "EXT_EXTREF"; break; 5043 default: type = "UNKNOWN"; break; 5044 } 5045 5046 BLOGD(sc, DBG_MBUF, 5047 "%02d: - m_ext: %p ext_size=%d type=%s\n", 5048 i, m->m_ext.ext_buf, m->m_ext.ext_size, type); 5049 } 5050 5051 if (contents) { 5052 bxe_dump_mbuf_data(sc, "mbuf data", m, TRUE); 5053 } 5054 5055 m = m->m_next; 5056 i++; 5057 } 5058 } 5059 5060 /* 5061 * Checks to ensure the 13 bd sliding window is >= MSS for TSO. 5062 * Check that (13 total bds - 3 bds) = 10 bd window >= MSS. 5063 * The window: 3 bds are = 1 for headers BD + 2 for parse BD and last BD 5064 * The headers comes in a seperate bd in FreeBSD so 13-3=10. 5065 * Returns: 0 if OK to send, 1 if packet needs further defragmentation 5066 */ 5067 static int 5068 bxe_chktso_window(struct bxe_softc *sc, 5069 int nsegs, 5070 bus_dma_segment_t *segs, 5071 struct mbuf *m) 5072 { 5073 uint32_t num_wnds, wnd_size, wnd_sum; 5074 int32_t frag_idx, wnd_idx; 5075 unsigned short lso_mss; 5076 int defrag; 5077 5078 defrag = 0; 5079 wnd_sum = 0; 5080 wnd_size = 10; 5081 num_wnds = nsegs - wnd_size; 5082 lso_mss = htole16(m->m_pkthdr.tso_segsz); 5083 5084 /* 5085 * Total header lengths Eth+IP+TCP in first FreeBSD mbuf so calculate the 5086 * first window sum of data while skipping the first assuming it is the 5087 * header in FreeBSD. 5088 */ 5089 for (frag_idx = 1; (frag_idx <= wnd_size); frag_idx++) { 5090 wnd_sum += htole16(segs[frag_idx].ds_len); 5091 } 5092 5093 /* check the first 10 bd window size */ 5094 if (wnd_sum < lso_mss) { 5095 return (1); 5096 } 5097 5098 /* run through the windows */ 5099 for (wnd_idx = 0; wnd_idx < num_wnds; wnd_idx++, frag_idx++) { 5100 /* subtract the first mbuf->m_len of the last wndw(-header) */ 5101 wnd_sum -= htole16(segs[wnd_idx+1].ds_len); 5102 /* add the next mbuf len to the len of our new window */ 5103 wnd_sum += htole16(segs[frag_idx].ds_len); 5104 if (wnd_sum < lso_mss) { 5105 return (1); 5106 } 5107 } 5108 5109 return (0); 5110 } 5111 5112 static uint8_t 5113 bxe_set_pbd_csum_e2(struct bxe_fastpath *fp, 5114 struct mbuf *m, 5115 uint32_t *parsing_data) 5116 { 5117 struct ether_vlan_header *eh = NULL; 5118 struct ip *ip4 = NULL; 5119 struct ip6_hdr *ip6 = NULL; 5120 caddr_t ip = NULL; 5121 struct tcphdr *th = NULL; 5122 int e_hlen, ip_hlen, l4_off; 5123 uint16_t proto; 5124 5125 if (m->m_pkthdr.csum_flags == CSUM_IP) { 5126 /* no L4 checksum offload needed */ 5127 return (0); 5128 } 5129 5130 /* get the Ethernet header */ 5131 eh = mtod(m, struct ether_vlan_header *); 5132 5133 /* handle VLAN encapsulation if present */ 5134 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 5135 e_hlen = (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN); 5136 proto = ntohs(eh->evl_proto); 5137 } else { 5138 e_hlen = ETHER_HDR_LEN; 5139 proto = ntohs(eh->evl_encap_proto); 5140 } 5141 5142 switch (proto) { 5143 case ETHERTYPE_IP: 5144 /* get the IP header, if mbuf len < 20 then header in next mbuf */ 5145 ip4 = (m->m_len < sizeof(struct ip)) ? 5146 (struct ip *)m->m_next->m_data : 5147 (struct ip *)(m->m_data + e_hlen); 5148 /* ip_hl is number of 32-bit words */ 5149 ip_hlen = (ip4->ip_hl << 2); 5150 ip = (caddr_t)ip4; 5151 break; 5152 case ETHERTYPE_IPV6: 5153 /* get the IPv6 header, if mbuf len < 40 then header in next mbuf */ 5154 ip6 = (m->m_len < sizeof(struct ip6_hdr)) ? 5155 (struct ip6_hdr *)m->m_next->m_data : 5156 (struct ip6_hdr *)(m->m_data + e_hlen); 5157 /* XXX cannot support offload with IPv6 extensions */ 5158 ip_hlen = sizeof(struct ip6_hdr); 5159 ip = (caddr_t)ip6; 5160 break; 5161 default: 5162 /* We can't offload in this case... */ 5163 /* XXX error stat ??? */ 5164 return (0); 5165 } 5166 5167 /* XXX assuming L4 header is contiguous to IPv4/IPv6 in the same mbuf */ 5168 l4_off = (e_hlen + ip_hlen); 5169 5170 *parsing_data |= 5171 (((l4_off >> 1) << ETH_TX_PARSE_BD_E2_L4_HDR_START_OFFSET_W_SHIFT) & 5172 ETH_TX_PARSE_BD_E2_L4_HDR_START_OFFSET_W); 5173 5174 if (m->m_pkthdr.csum_flags & (CSUM_TCP | 5175 CSUM_TSO | 5176 CSUM_TCP_IPV6)) { 5177 fp->eth_q_stats.tx_ofld_frames_csum_tcp++; 5178 th = (struct tcphdr *)(ip + ip_hlen); 5179 /* th_off is number of 32-bit words */ 5180 *parsing_data |= ((th->th_off << 5181 ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW_SHIFT) & 5182 ETH_TX_PARSE_BD_E2_TCP_HDR_LENGTH_DW); 5183 return (l4_off + (th->th_off << 2)); /* entire header length */ 5184 } else if (m->m_pkthdr.csum_flags & (CSUM_UDP | 5185 CSUM_UDP_IPV6)) { 5186 fp->eth_q_stats.tx_ofld_frames_csum_udp++; 5187 return (l4_off + sizeof(struct udphdr)); /* entire header length */ 5188 } else { 5189 /* XXX error stat ??? */ 5190 return (0); 5191 } 5192 } 5193 5194 static uint8_t 5195 bxe_set_pbd_csum(struct bxe_fastpath *fp, 5196 struct mbuf *m, 5197 struct eth_tx_parse_bd_e1x *pbd) 5198 { 5199 struct ether_vlan_header *eh = NULL; 5200 struct ip *ip4 = NULL; 5201 struct ip6_hdr *ip6 = NULL; 5202 caddr_t ip = NULL; 5203 struct tcphdr *th = NULL; 5204 struct udphdr *uh = NULL; 5205 int e_hlen, ip_hlen; 5206 uint16_t proto; 5207 uint8_t hlen; 5208 uint16_t tmp_csum; 5209 uint32_t *tmp_uh; 5210 5211 /* get the Ethernet header */ 5212 eh = mtod(m, struct ether_vlan_header *); 5213 5214 /* handle VLAN encapsulation if present */ 5215 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) { 5216 e_hlen = (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN); 5217 proto = ntohs(eh->evl_proto); 5218 } else { 5219 e_hlen = ETHER_HDR_LEN; 5220 proto = ntohs(eh->evl_encap_proto); 5221 } 5222 5223 switch (proto) { 5224 case ETHERTYPE_IP: 5225 /* get the IP header, if mbuf len < 20 then header in next mbuf */ 5226 ip4 = (m->m_len < sizeof(struct ip)) ? 5227 (struct ip *)m->m_next->m_data : 5228 (struct ip *)(m->m_data + e_hlen); 5229 /* ip_hl is number of 32-bit words */ 5230 ip_hlen = (ip4->ip_hl << 1); 5231 ip = (caddr_t)ip4; 5232 break; 5233 case ETHERTYPE_IPV6: 5234 /* get the IPv6 header, if mbuf len < 40 then header in next mbuf */ 5235 ip6 = (m->m_len < sizeof(struct ip6_hdr)) ? 5236 (struct ip6_hdr *)m->m_next->m_data : 5237 (struct ip6_hdr *)(m->m_data + e_hlen); 5238 /* XXX cannot support offload with IPv6 extensions */ 5239 ip_hlen = (sizeof(struct ip6_hdr) >> 1); 5240 ip = (caddr_t)ip6; 5241 break; 5242 default: 5243 /* We can't offload in this case... */ 5244 /* XXX error stat ??? */ 5245 return (0); 5246 } 5247 5248 hlen = (e_hlen >> 1); 5249 5250 /* note that rest of global_data is indirectly zeroed here */ 5251 if (m->m_flags & M_VLANTAG) { 5252 pbd->global_data = 5253 htole16(hlen | (1 << ETH_TX_PARSE_BD_E1X_LLC_SNAP_EN_SHIFT)); 5254 } else { 5255 pbd->global_data = htole16(hlen); 5256 } 5257 5258 pbd->ip_hlen_w = ip_hlen; 5259 5260 hlen += pbd->ip_hlen_w; 5261 5262 /* XXX assuming L4 header is contiguous to IPv4/IPv6 in the same mbuf */ 5263 5264 if (m->m_pkthdr.csum_flags & (CSUM_TCP | 5265 CSUM_TSO | 5266 CSUM_TCP_IPV6)) { 5267 th = (struct tcphdr *)(ip + (ip_hlen << 1)); 5268 /* th_off is number of 32-bit words */ 5269 hlen += (uint16_t)(th->th_off << 1); 5270 } else if (m->m_pkthdr.csum_flags & (CSUM_UDP | 5271 CSUM_UDP_IPV6)) { 5272 uh = (struct udphdr *)(ip + (ip_hlen << 1)); 5273 hlen += (sizeof(struct udphdr) / 2); 5274 } else { 5275 /* valid case as only CSUM_IP was set */ 5276 return (0); 5277 } 5278 5279 pbd->total_hlen_w = htole16(hlen); 5280 5281 if (m->m_pkthdr.csum_flags & (CSUM_TCP | 5282 CSUM_TSO | 5283 CSUM_TCP_IPV6)) { 5284 fp->eth_q_stats.tx_ofld_frames_csum_tcp++; 5285 pbd->tcp_pseudo_csum = ntohs(th->th_sum); 5286 } else if (m->m_pkthdr.csum_flags & (CSUM_UDP | 5287 CSUM_UDP_IPV6)) { 5288 fp->eth_q_stats.tx_ofld_frames_csum_udp++; 5289 5290 /* 5291 * Everest1 (i.e. 57710, 57711, 57711E) does not natively support UDP 5292 * checksums and does not know anything about the UDP header and where 5293 * the checksum field is located. It only knows about TCP. Therefore 5294 * we "lie" to the hardware for outgoing UDP packets w/ checksum 5295 * offload. Since the checksum field offset for TCP is 16 bytes and 5296 * for UDP it is 6 bytes we pass a pointer to the hardware that is 10 5297 * bytes less than the start of the UDP header. This allows the 5298 * hardware to write the checksum in the correct spot. But the 5299 * hardware will compute a checksum which includes the last 10 bytes 5300 * of the IP header. To correct this we tweak the stack computed 5301 * pseudo checksum by folding in the calculation of the inverse 5302 * checksum for those final 10 bytes of the IP header. This allows 5303 * the correct checksum to be computed by the hardware. 5304 */ 5305 5306 /* set pointer 10 bytes before UDP header */ 5307 tmp_uh = (uint32_t *)((uint8_t *)uh - 10); 5308 5309 /* calculate a pseudo header checksum over the first 10 bytes */ 5310 tmp_csum = in_pseudo(*tmp_uh, 5311 *(tmp_uh + 1), 5312 *(uint16_t *)(tmp_uh + 2)); 5313 5314 pbd->tcp_pseudo_csum = ntohs(in_addword(uh->uh_sum, ~tmp_csum)); 5315 } 5316 5317 return (hlen * 2); /* entire header length, number of bytes */ 5318 } 5319 5320 static void 5321 bxe_set_pbd_lso_e2(struct mbuf *m, 5322 uint32_t *parsing_data) 5323 { 5324 *parsing_data |= ((m->m_pkthdr.tso_segsz << 5325 ETH_TX_PARSE_BD_E2_LSO_MSS_SHIFT) & 5326 ETH_TX_PARSE_BD_E2_LSO_MSS); 5327 5328 /* XXX test for IPv6 with extension header... */ 5329 #if 0 5330 struct ip6_hdr *ip6; 5331 if (ip6 && ip6->ip6_nxt == 'some ipv6 extension header') 5332 *parsing_data |= ETH_TX_PARSE_BD_E2_IPV6_WITH_EXT_HDR; 5333 #endif 5334 } 5335 5336 static void 5337 bxe_set_pbd_lso(struct mbuf *m, 5338 struct eth_tx_parse_bd_e1x *pbd) 5339 { 5340 struct ether_vlan_header *eh = NULL; 5341 struct ip *ip = NULL; 5342 struct tcphdr *th = NULL; 5343 int e_hlen; 5344 5345 /* get the Ethernet header */ 5346 eh = mtod(m, struct ether_vlan_header *); 5347 5348 /* handle VLAN encapsulation if present */ 5349 e_hlen = (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) ? 5350 (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN) : ETHER_HDR_LEN; 5351 5352 /* get the IP and TCP header, with LSO entire header in first mbuf */ 5353 /* XXX assuming IPv4 */ 5354 ip = (struct ip *)(m->m_data + e_hlen); 5355 th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2)); 5356 5357 pbd->lso_mss = htole16(m->m_pkthdr.tso_segsz); 5358 pbd->tcp_send_seq = ntohl(th->th_seq); 5359 pbd->tcp_flags = ((ntohl(((uint32_t *)th)[3]) >> 16) & 0xff); 5360 5361 #if 1 5362 /* XXX IPv4 */ 5363 pbd->ip_id = ntohs(ip->ip_id); 5364 pbd->tcp_pseudo_csum = 5365 ntohs(in_pseudo(ip->ip_src.s_addr, 5366 ip->ip_dst.s_addr, 5367 htons(IPPROTO_TCP))); 5368 #else 5369 /* XXX IPv6 */ 5370 pbd->tcp_pseudo_csum = 5371 ntohs(in_pseudo(&ip6->ip6_src, 5372 &ip6->ip6_dst, 5373 htons(IPPROTO_TCP))); 5374 #endif 5375 5376 pbd->global_data |= 5377 htole16(ETH_TX_PARSE_BD_E1X_PSEUDO_CS_WITHOUT_LEN); 5378 } 5379 5380 /* 5381 * Encapsulte an mbuf cluster into the tx bd chain and makes the memory 5382 * visible to the controller. 5383 * 5384 * If an mbuf is submitted to this routine and cannot be given to the 5385 * controller (e.g. it has too many fragments) then the function may free 5386 * the mbuf and return to the caller. 5387 * 5388 * Returns: 5389 * 0 = Success, !0 = Failure 5390 * Note the side effect that an mbuf may be freed if it causes a problem. 5391 */ 5392 static int 5393 bxe_tx_encap(struct bxe_fastpath *fp, struct mbuf **m_head) 5394 { 5395 bus_dma_segment_t segs[32]; 5396 struct mbuf *m0; 5397 struct bxe_sw_tx_bd *tx_buf; 5398 struct eth_tx_parse_bd_e1x *pbd_e1x = NULL; 5399 struct eth_tx_parse_bd_e2 *pbd_e2 = NULL; 5400 /* struct eth_tx_parse_2nd_bd *pbd2 = NULL; */ 5401 struct eth_tx_bd *tx_data_bd; 5402 struct eth_tx_bd *tx_total_pkt_size_bd; 5403 struct eth_tx_start_bd *tx_start_bd; 5404 uint16_t bd_prod, pkt_prod, total_pkt_size; 5405 uint8_t mac_type; 5406 int defragged, error, nsegs, rc, nbds, vlan_off, ovlan; 5407 struct bxe_softc *sc; 5408 uint16_t tx_bd_avail; 5409 struct ether_vlan_header *eh; 5410 uint32_t pbd_e2_parsing_data = 0; 5411 uint8_t hlen = 0; 5412 int tmp_bd; 5413 int i; 5414 5415 sc = fp->sc; 5416 5417 M_ASSERTPKTHDR(*m_head); 5418 5419 m0 = *m_head; 5420 rc = defragged = nbds = ovlan = vlan_off = total_pkt_size = 0; 5421 tx_start_bd = NULL; 5422 tx_data_bd = NULL; 5423 tx_total_pkt_size_bd = NULL; 5424 5425 /* get the H/W pointer for packets and BDs */ 5426 pkt_prod = fp->tx_pkt_prod; 5427 bd_prod = fp->tx_bd_prod; 5428 5429 mac_type = UNICAST_ADDRESS; 5430 5431 /* map the mbuf into the next open DMAable memory */ 5432 tx_buf = &fp->tx_mbuf_chain[TX_BD(pkt_prod)]; 5433 error = bus_dmamap_load_mbuf_sg(fp->tx_mbuf_tag, 5434 tx_buf->m_map, m0, 5435 segs, &nsegs, BUS_DMA_NOWAIT); 5436 5437 /* mapping errors */ 5438 if(__predict_false(error != 0)) { 5439 fp->eth_q_stats.tx_dma_mapping_failure++; 5440 if (error == ENOMEM) { 5441 /* resource issue, try again later */ 5442 rc = ENOMEM; 5443 } else if (error == EFBIG) { 5444 /* possibly recoverable with defragmentation */ 5445 fp->eth_q_stats.mbuf_defrag_attempts++; 5446 m0 = m_defrag(*m_head, M_DONTWAIT); 5447 if (m0 == NULL) { 5448 fp->eth_q_stats.mbuf_defrag_failures++; 5449 rc = ENOBUFS; 5450 } else { 5451 /* defrag successful, try mapping again */ 5452 *m_head = m0; 5453 error = bus_dmamap_load_mbuf_sg(fp->tx_mbuf_tag, 5454 tx_buf->m_map, m0, 5455 segs, &nsegs, BUS_DMA_NOWAIT); 5456 if (error) { 5457 fp->eth_q_stats.tx_dma_mapping_failure++; 5458 rc = error; 5459 } 5460 } 5461 } else { 5462 /* unknown, unrecoverable mapping error */ 5463 BLOGE(sc, "Unknown TX mapping error rc=%d\n", error); 5464 bxe_dump_mbuf(sc, m0, FALSE); 5465 rc = error; 5466 } 5467 5468 goto bxe_tx_encap_continue; 5469 } 5470 5471 tx_bd_avail = bxe_tx_avail(sc, fp); 5472 5473 /* make sure there is enough room in the send queue */ 5474 if (__predict_false(tx_bd_avail < (nsegs + 2))) { 5475 /* Recoverable, try again later. */ 5476 fp->eth_q_stats.tx_hw_queue_full++; 5477 bus_dmamap_unload(fp->tx_mbuf_tag, tx_buf->m_map); 5478 rc = ENOMEM; 5479 goto bxe_tx_encap_continue; 5480 } 5481 5482 /* capture the current H/W TX chain high watermark */ 5483 if (__predict_false(fp->eth_q_stats.tx_hw_max_queue_depth < 5484 (TX_BD_USABLE - tx_bd_avail))) { 5485 fp->eth_q_stats.tx_hw_max_queue_depth = (TX_BD_USABLE - tx_bd_avail); 5486 } 5487 5488 /* make sure it fits in the packet window */ 5489 if (__predict_false(nsegs > 12)) { 5490 /* 5491 * The mbuf may be to big for the controller to handle. If the frame 5492 * is a TSO frame we'll need to do an additional check. 5493 */ 5494 if (m0->m_pkthdr.csum_flags & CSUM_TSO) { 5495 if (bxe_chktso_window(sc, nsegs, segs, m0) == 0) { 5496 goto bxe_tx_encap_continue; /* OK to send */ 5497 } else { 5498 fp->eth_q_stats.tx_window_violation_tso++; 5499 } 5500 } else { 5501 fp->eth_q_stats.tx_window_violation_std++; 5502 } 5503 5504 /* lets try to defragment this mbuf */ 5505 fp->eth_q_stats.mbuf_defrag_attempts++; 5506 5507 m0 = m_defrag(*m_head, M_DONTWAIT); 5508 if (m0 == NULL) { 5509 fp->eth_q_stats.mbuf_defrag_failures++; 5510 /* Ugh, just drop the frame... :( */ 5511 rc = ENOBUFS; 5512 } else { 5513 /* defrag successful, try mapping again */ 5514 *m_head = m0; 5515 error = bus_dmamap_load_mbuf_sg(fp->tx_mbuf_tag, 5516 tx_buf->m_map, m0, 5517 segs, &nsegs, BUS_DMA_NOWAIT); 5518 if (error) { 5519 fp->eth_q_stats.tx_dma_mapping_failure++; 5520 /* No sense in trying to defrag/copy chain, drop it. :( */ 5521 rc = error; 5522 } 5523 5524 /* if the chain is still too long then drop it */ 5525 if (__predict_false(nsegs > 12)) { 5526 rc = ENODEV; 5527 } 5528 } 5529 } 5530 5531 bxe_tx_encap_continue: 5532 5533 /* Check for errors */ 5534 if (rc) { 5535 if (rc == ENOMEM) { 5536 /* recoverable try again later */ 5537 } else { 5538 fp->eth_q_stats.tx_soft_errors++; 5539 fp->eth_q_stats.mbuf_alloc_tx--; 5540 m_freem(*m_head); 5541 *m_head = NULL; 5542 } 5543 5544 return (rc); 5545 } 5546 5547 /* set flag according to packet type (UNICAST_ADDRESS is default) */ 5548 if (m0->m_flags & M_BCAST) { 5549 mac_type = BROADCAST_ADDRESS; 5550 } else if (m0->m_flags & M_MCAST) { 5551 mac_type = MULTICAST_ADDRESS; 5552 } 5553 5554 /* store the mbuf into the mbuf ring */ 5555 tx_buf->m = m0; 5556 tx_buf->first_bd = fp->tx_bd_prod; 5557 tx_buf->flags = 0; 5558 5559 /* prepare the first transmit (start) BD for the mbuf */ 5560 tx_start_bd = &fp->tx_chain[TX_BD(bd_prod)].start_bd; 5561 5562 BLOGD(sc, DBG_TX, 5563 "sending pkt_prod=%u tx_buf=%p next_idx=%u bd=%u tx_start_bd=%p\n", 5564 pkt_prod, tx_buf, fp->tx_pkt_prod, bd_prod, tx_start_bd); 5565 5566 tx_start_bd->addr_lo = htole32(U64_LO(segs[0].ds_addr)); 5567 tx_start_bd->addr_hi = htole32(U64_HI(segs[0].ds_addr)); 5568 tx_start_bd->nbytes = htole16(segs[0].ds_len); 5569 total_pkt_size += tx_start_bd->nbytes; 5570 tx_start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD; 5571 5572 tx_start_bd->general_data = (1 << ETH_TX_START_BD_HDR_NBDS_SHIFT); 5573 5574 /* all frames have at least Start BD + Parsing BD */ 5575 nbds = nsegs + 1; 5576 tx_start_bd->nbd = htole16(nbds); 5577 5578 if (m0->m_flags & M_VLANTAG) { 5579 tx_start_bd->vlan_or_ethertype = htole16(m0->m_pkthdr.ether_vtag); 5580 tx_start_bd->bd_flags.as_bitfield |= 5581 (X_ETH_OUTBAND_VLAN << ETH_TX_BD_FLAGS_VLAN_MODE_SHIFT); 5582 } else { 5583 /* vf tx, start bd must hold the ethertype for fw to enforce it */ 5584 if (IS_VF(sc)) { 5585 /* map ethernet header to find type and header length */ 5586 eh = mtod(m0, struct ether_vlan_header *); 5587 tx_start_bd->vlan_or_ethertype = eh->evl_encap_proto; 5588 } else { 5589 /* used by FW for packet accounting */ 5590 tx_start_bd->vlan_or_ethertype = htole16(fp->tx_pkt_prod); 5591 #if 0 5592 /* 5593 * If NPAR-SD is active then FW should do the tagging regardless 5594 * of value of priority. Otherwise, if priority indicates this is 5595 * a control packet we need to indicate to FW to avoid tagging. 5596 */ 5597 if (!IS_MF_AFEX(sc) && (mbuf priority == PRIO_CONTROL)) { 5598 SET_FLAG(tx_start_bd->general_data, 5599 ETH_TX_START_BD_FORCE_VLAN_MODE, 1); 5600 } 5601 #endif 5602 } 5603 } 5604 5605 /* 5606 * add a parsing BD from the chain. The parsing BD is always added 5607 * though it is only used for TSO and chksum 5608 */ 5609 bd_prod = TX_BD_NEXT(bd_prod); 5610 5611 if (m0->m_pkthdr.csum_flags) { 5612 if (m0->m_pkthdr.csum_flags & CSUM_IP) { 5613 fp->eth_q_stats.tx_ofld_frames_csum_ip++; 5614 tx_start_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_IP_CSUM; 5615 } 5616 5617 if (m0->m_pkthdr.csum_flags & CSUM_TCP_IPV6) { 5618 tx_start_bd->bd_flags.as_bitfield |= (ETH_TX_BD_FLAGS_IPV6 | 5619 ETH_TX_BD_FLAGS_L4_CSUM); 5620 } else if (m0->m_pkthdr.csum_flags & CSUM_UDP_IPV6) { 5621 tx_start_bd->bd_flags.as_bitfield |= (ETH_TX_BD_FLAGS_IPV6 | 5622 ETH_TX_BD_FLAGS_IS_UDP | 5623 ETH_TX_BD_FLAGS_L4_CSUM); 5624 } else if ((m0->m_pkthdr.csum_flags & CSUM_TCP) || 5625 (m0->m_pkthdr.csum_flags & CSUM_TSO)) { 5626 tx_start_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_L4_CSUM; 5627 } else if (m0->m_pkthdr.csum_flags & CSUM_UDP) { 5628 tx_start_bd->bd_flags.as_bitfield |= (ETH_TX_BD_FLAGS_L4_CSUM | 5629 ETH_TX_BD_FLAGS_IS_UDP); 5630 } 5631 } 5632 5633 if (!CHIP_IS_E1x(sc)) { 5634 pbd_e2 = &fp->tx_chain[TX_BD(bd_prod)].parse_bd_e2; 5635 memset(pbd_e2, 0, sizeof(struct eth_tx_parse_bd_e2)); 5636 5637 if (m0->m_pkthdr.csum_flags) { 5638 hlen = bxe_set_pbd_csum_e2(fp, m0, &pbd_e2_parsing_data); 5639 } 5640 5641 #if 0 5642 /* 5643 * Add the MACs to the parsing BD if the module param was 5644 * explicitly set, if this is a vf, or in switch independent 5645 * mode. 5646 */ 5647 if (sc->flags & BXE_TX_SWITCHING || IS_VF(sc) || IS_MF_SI(sc)) { 5648 eh = mtod(m0, struct ether_vlan_header *); 5649 bxe_set_fw_mac_addr(&pbd_e2->data.mac_addr.src_hi, 5650 &pbd_e2->data.mac_addr.src_mid, 5651 &pbd_e2->data.mac_addr.src_lo, 5652 eh->evl_shost); 5653 bxe_set_fw_mac_addr(&pbd_e2->data.mac_addr.dst_hi, 5654 &pbd_e2->data.mac_addr.dst_mid, 5655 &pbd_e2->data.mac_addr.dst_lo, 5656 eh->evl_dhost); 5657 } 5658 #endif 5659 5660 SET_FLAG(pbd_e2_parsing_data, ETH_TX_PARSE_BD_E2_ETH_ADDR_TYPE, 5661 mac_type); 5662 } else { 5663 uint16_t global_data = 0; 5664 5665 pbd_e1x = &fp->tx_chain[TX_BD(bd_prod)].parse_bd_e1x; 5666 memset(pbd_e1x, 0, sizeof(struct eth_tx_parse_bd_e1x)); 5667 5668 if (m0->m_pkthdr.csum_flags) { 5669 hlen = bxe_set_pbd_csum(fp, m0, pbd_e1x); 5670 } 5671 5672 SET_FLAG(global_data, 5673 ETH_TX_PARSE_BD_E1X_ETH_ADDR_TYPE, mac_type); 5674 pbd_e1x->global_data |= htole16(global_data); 5675 } 5676 5677 /* setup the parsing BD with TSO specific info */ 5678 if (m0->m_pkthdr.csum_flags & CSUM_TSO) { 5679 fp->eth_q_stats.tx_ofld_frames_lso++; 5680 tx_start_bd->bd_flags.as_bitfield |= ETH_TX_BD_FLAGS_SW_LSO; 5681 5682 if (__predict_false(tx_start_bd->nbytes > hlen)) { 5683 fp->eth_q_stats.tx_ofld_frames_lso_hdr_splits++; 5684 5685 /* split the first BD into header/data making the fw job easy */ 5686 nbds++; 5687 tx_start_bd->nbd = htole16(nbds); 5688 tx_start_bd->nbytes = htole16(hlen); 5689 5690 bd_prod = TX_BD_NEXT(bd_prod); 5691 5692 /* new transmit BD after the tx_parse_bd */ 5693 tx_data_bd = &fp->tx_chain[TX_BD(bd_prod)].reg_bd; 5694 tx_data_bd->addr_hi = htole32(U64_HI(segs[0].ds_addr + hlen)); 5695 tx_data_bd->addr_lo = htole32(U64_LO(segs[0].ds_addr + hlen)); 5696 tx_data_bd->nbytes = htole16(segs[0].ds_len - hlen); 5697 if (tx_total_pkt_size_bd == NULL) { 5698 tx_total_pkt_size_bd = tx_data_bd; 5699 } 5700 5701 BLOGD(sc, DBG_TX, 5702 "TSO split header size is %d (%x:%x) nbds %d\n", 5703 le16toh(tx_start_bd->nbytes), 5704 le32toh(tx_start_bd->addr_hi), 5705 le32toh(tx_start_bd->addr_lo), 5706 nbds); 5707 } 5708 5709 if (!CHIP_IS_E1x(sc)) { 5710 bxe_set_pbd_lso_e2(m0, &pbd_e2_parsing_data); 5711 } else { 5712 bxe_set_pbd_lso(m0, pbd_e1x); 5713 } 5714 } 5715 5716 if (pbd_e2_parsing_data) { 5717 pbd_e2->parsing_data = htole32(pbd_e2_parsing_data); 5718 } 5719 5720 /* prepare remaining BDs, start tx bd contains first seg/frag */ 5721 for (i = 1; i < nsegs ; i++) { 5722 bd_prod = TX_BD_NEXT(bd_prod); 5723 tx_data_bd = &fp->tx_chain[TX_BD(bd_prod)].reg_bd; 5724 tx_data_bd->addr_lo = htole32(U64_LO(segs[i].ds_addr)); 5725 tx_data_bd->addr_hi = htole32(U64_HI(segs[i].ds_addr)); 5726 tx_data_bd->nbytes = htole16(segs[i].ds_len); 5727 if (tx_total_pkt_size_bd == NULL) { 5728 tx_total_pkt_size_bd = tx_data_bd; 5729 } 5730 total_pkt_size += tx_data_bd->nbytes; 5731 } 5732 5733 BLOGD(sc, DBG_TX, "last bd %p\n", tx_data_bd); 5734 5735 if (tx_total_pkt_size_bd != NULL) { 5736 tx_total_pkt_size_bd->total_pkt_bytes = total_pkt_size; 5737 } 5738 5739 if (__predict_false(sc->debug & DBG_TX)) { 5740 tmp_bd = tx_buf->first_bd; 5741 for (i = 0; i < nbds; i++) 5742 { 5743 if (i == 0) { 5744 BLOGD(sc, DBG_TX, 5745 "TX Strt: %p bd=%d nbd=%d vlan=0x%x " 5746 "bd_flags=0x%x hdr_nbds=%d\n", 5747 tx_start_bd, 5748 tmp_bd, 5749 le16toh(tx_start_bd->nbd), 5750 le16toh(tx_start_bd->vlan_or_ethertype), 5751 tx_start_bd->bd_flags.as_bitfield, 5752 (tx_start_bd->general_data & ETH_TX_START_BD_HDR_NBDS)); 5753 } else if (i == 1) { 5754 if (pbd_e1x) { 5755 BLOGD(sc, DBG_TX, 5756 "-> Prse: %p bd=%d global=0x%x ip_hlen_w=%u " 5757 "ip_id=%u lso_mss=%u tcp_flags=0x%x csum=0x%x " 5758 "tcp_seq=%u total_hlen_w=%u\n", 5759 pbd_e1x, 5760 tmp_bd, 5761 pbd_e1x->global_data, 5762 pbd_e1x->ip_hlen_w, 5763 pbd_e1x->ip_id, 5764 pbd_e1x->lso_mss, 5765 pbd_e1x->tcp_flags, 5766 pbd_e1x->tcp_pseudo_csum, 5767 pbd_e1x->tcp_send_seq, 5768 le16toh(pbd_e1x->total_hlen_w)); 5769 } else { /* if (pbd_e2) */ 5770 BLOGD(sc, DBG_TX, 5771 "-> Parse: %p bd=%d dst=%02x:%02x:%02x " 5772 "src=%02x:%02x:%02x parsing_data=0x%x\n", 5773 pbd_e2, 5774 tmp_bd, 5775 pbd_e2->data.mac_addr.dst_hi, 5776 pbd_e2->data.mac_addr.dst_mid, 5777 pbd_e2->data.mac_addr.dst_lo, 5778 pbd_e2->data.mac_addr.src_hi, 5779 pbd_e2->data.mac_addr.src_mid, 5780 pbd_e2->data.mac_addr.src_lo, 5781 pbd_e2->parsing_data); 5782 } 5783 } 5784 5785 if (i != 1) { /* skip parse db as it doesn't hold data */ 5786 tx_data_bd = &fp->tx_chain[TX_BD(tmp_bd)].reg_bd; 5787 BLOGD(sc, DBG_TX, 5788 "-> Frag: %p bd=%d nbytes=%d hi=0x%x lo: 0x%x\n", 5789 tx_data_bd, 5790 tmp_bd, 5791 le16toh(tx_data_bd->nbytes), 5792 le32toh(tx_data_bd->addr_hi), 5793 le32toh(tx_data_bd->addr_lo)); 5794 } 5795 5796 tmp_bd = TX_BD_NEXT(tmp_bd); 5797 } 5798 } 5799 5800 BLOGD(sc, DBG_TX, "doorbell: nbds=%d bd=%u\n", nbds, bd_prod); 5801 5802 /* update TX BD producer index value for next TX */ 5803 bd_prod = TX_BD_NEXT(bd_prod); 5804 5805 /* 5806 * If the chain of tx_bd's describing this frame is adjacent to or spans 5807 * an eth_tx_next_bd element then we need to increment the nbds value. 5808 */ 5809 if (TX_BD_IDX(bd_prod) < nbds) { 5810 nbds++; 5811 } 5812 5813 /* don't allow reordering of writes for nbd and packets */ 5814 mb(); 5815 5816 fp->tx_db.data.prod += nbds; 5817 5818 /* producer points to the next free tx_bd at this point */ 5819 fp->tx_pkt_prod++; 5820 fp->tx_bd_prod = bd_prod; 5821 5822 DOORBELL(sc, fp->index, fp->tx_db.raw); 5823 5824 fp->eth_q_stats.tx_pkts++; 5825 5826 /* Prevent speculative reads from getting ahead of the status block. */ 5827 bus_space_barrier(sc->bar[BAR0].tag, sc->bar[BAR0].handle, 5828 0, 0, BUS_SPACE_BARRIER_READ); 5829 5830 /* Prevent speculative reads from getting ahead of the doorbell. */ 5831 bus_space_barrier(sc->bar[BAR2].tag, sc->bar[BAR2].handle, 5832 0, 0, BUS_SPACE_BARRIER_READ); 5833 5834 return (0); 5835 } 5836 5837 static void 5838 bxe_tx_start_locked(struct bxe_softc *sc, 5839 struct ifnet *ifp, 5840 struct bxe_fastpath *fp) 5841 { 5842 struct mbuf *m = NULL; 5843 int tx_count = 0; 5844 uint16_t tx_bd_avail; 5845 5846 BXE_FP_TX_LOCK_ASSERT(fp); 5847 5848 /* keep adding entries while there are frames to send */ 5849 while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 5850 5851 /* 5852 * check for any frames to send 5853 * dequeue can still be NULL even if queue is not empty 5854 */ 5855 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); 5856 if (__predict_false(m == NULL)) { 5857 break; 5858 } 5859 5860 /* the mbuf now belongs to us */ 5861 fp->eth_q_stats.mbuf_alloc_tx++; 5862 5863 /* 5864 * Put the frame into the transmit ring. If we don't have room, 5865 * place the mbuf back at the head of the TX queue, set the 5866 * OACTIVE flag, and wait for the NIC to drain the chain. 5867 */ 5868 if (__predict_false(bxe_tx_encap(fp, &m))) { 5869 fp->eth_q_stats.tx_encap_failures++; 5870 if (m != NULL) { 5871 /* mark the TX queue as full and return the frame */ 5872 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 5873 IFQ_DRV_PREPEND(&ifp->if_snd, m); 5874 fp->eth_q_stats.mbuf_alloc_tx--; 5875 fp->eth_q_stats.tx_queue_xoff++; 5876 } 5877 5878 /* stop looking for more work */ 5879 break; 5880 } 5881 5882 /* the frame was enqueued successfully */ 5883 tx_count++; 5884 5885 /* send a copy of the frame to any BPF listeners. */ 5886 BPF_MTAP(ifp, m); 5887 5888 tx_bd_avail = bxe_tx_avail(sc, fp); 5889 5890 /* handle any completions if we're running low */ 5891 if (tx_bd_avail < BXE_TX_CLEANUP_THRESHOLD) { 5892 /* bxe_txeof will set IFF_DRV_OACTIVE appropriately */ 5893 bxe_txeof(sc, fp); 5894 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) { 5895 break; 5896 } 5897 } 5898 } 5899 5900 /* all TX packets were dequeued and/or the tx ring is full */ 5901 if (tx_count > 0) { 5902 /* reset the TX watchdog timeout timer */ 5903 fp->watchdog_timer = BXE_TX_TIMEOUT; 5904 } 5905 } 5906 5907 /* Legacy (non-RSS) dispatch routine */ 5908 static void 5909 bxe_tx_start(struct ifnet *ifp) 5910 { 5911 struct bxe_softc *sc; 5912 struct bxe_fastpath *fp; 5913 5914 sc = ifp->if_softc; 5915 5916 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 5917 BLOGW(sc, "Interface not running, ignoring transmit request\n"); 5918 return; 5919 } 5920 5921 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) { 5922 BLOGW(sc, "Interface TX queue is full, ignoring transmit request\n"); 5923 return; 5924 } 5925 5926 if (!sc->link_vars.link_up) { 5927 BLOGW(sc, "Interface link is down, ignoring transmit request\n"); 5928 return; 5929 } 5930 5931 fp = &sc->fp[0]; 5932 5933 BXE_FP_TX_LOCK(fp); 5934 bxe_tx_start_locked(sc, ifp, fp); 5935 BXE_FP_TX_UNLOCK(fp); 5936 } 5937 5938 #if __FreeBSD_version >= 800000 5939 5940 static int 5941 bxe_tx_mq_start_locked(struct bxe_softc *sc, 5942 struct ifnet *ifp, 5943 struct bxe_fastpath *fp, 5944 struct mbuf *m) 5945 { 5946 struct buf_ring *tx_br = fp->tx_br; 5947 struct mbuf *next; 5948 int depth, rc, tx_count; 5949 uint16_t tx_bd_avail; 5950 5951 rc = tx_count = 0; 5952 5953 if (!tx_br) { 5954 BLOGE(sc, "Multiqueue TX and no buf_ring!\n"); 5955 return (EINVAL); 5956 } 5957 5958 /* fetch the depth of the driver queue */ 5959 depth = drbr_inuse(ifp, tx_br); 5960 if (depth > fp->eth_q_stats.tx_max_drbr_queue_depth) { 5961 fp->eth_q_stats.tx_max_drbr_queue_depth = depth; 5962 } 5963 5964 BXE_FP_TX_LOCK_ASSERT(fp); 5965 5966 if (m == NULL) { 5967 /* no new work, check for pending frames */ 5968 next = drbr_dequeue(ifp, tx_br); 5969 } else if (drbr_needs_enqueue(ifp, tx_br)) { 5970 /* have both new and pending work, maintain packet order */ 5971 rc = drbr_enqueue(ifp, tx_br, m); 5972 if (rc != 0) { 5973 fp->eth_q_stats.tx_soft_errors++; 5974 goto bxe_tx_mq_start_locked_exit; 5975 } 5976 next = drbr_dequeue(ifp, tx_br); 5977 } else { 5978 /* new work only and nothing pending */ 5979 next = m; 5980 } 5981 5982 /* keep adding entries while there are frames to send */ 5983 while (next != NULL) { 5984 5985 /* the mbuf now belongs to us */ 5986 fp->eth_q_stats.mbuf_alloc_tx++; 5987 5988 /* 5989 * Put the frame into the transmit ring. If we don't have room, 5990 * place the mbuf back at the head of the TX queue, set the 5991 * OACTIVE flag, and wait for the NIC to drain the chain. 5992 */ 5993 rc = bxe_tx_encap(fp, &next); 5994 if (__predict_false(rc != 0)) { 5995 fp->eth_q_stats.tx_encap_failures++; 5996 if (next != NULL) { 5997 /* mark the TX queue as full and save the frame */ 5998 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 5999 /* XXX this may reorder the frame */ 6000 rc = drbr_enqueue(ifp, tx_br, next); 6001 fp->eth_q_stats.mbuf_alloc_tx--; 6002 fp->eth_q_stats.tx_frames_deferred++; 6003 } 6004 6005 /* stop looking for more work */ 6006 break; 6007 } 6008 6009 /* the transmit frame was enqueued successfully */ 6010 tx_count++; 6011 6012 /* send a copy of the frame to any BPF listeners */ 6013 BPF_MTAP(ifp, next); 6014 6015 tx_bd_avail = bxe_tx_avail(sc, fp); 6016 6017 /* handle any completions if we're running low */ 6018 if (tx_bd_avail < BXE_TX_CLEANUP_THRESHOLD) { 6019 /* bxe_txeof will set IFF_DRV_OACTIVE appropriately */ 6020 bxe_txeof(sc, fp); 6021 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) { 6022 break; 6023 } 6024 } 6025 6026 next = drbr_dequeue(ifp, tx_br); 6027 } 6028 6029 /* all TX packets were dequeued and/or the tx ring is full */ 6030 if (tx_count > 0) { 6031 /* reset the TX watchdog timeout timer */ 6032 fp->watchdog_timer = BXE_TX_TIMEOUT; 6033 } 6034 6035 bxe_tx_mq_start_locked_exit: 6036 6037 return (rc); 6038 } 6039 6040 /* Multiqueue (TSS) dispatch routine. */ 6041 static int 6042 bxe_tx_mq_start(struct ifnet *ifp, 6043 struct mbuf *m) 6044 { 6045 struct bxe_softc *sc = ifp->if_softc; 6046 struct bxe_fastpath *fp; 6047 int fp_index, rc; 6048 6049 fp_index = 0; /* default is the first queue */ 6050 6051 /* change the queue if using flow ID */ 6052 if ((m->m_flags & M_FLOWID) != 0) { 6053 fp_index = (m->m_pkthdr.flowid % sc->num_queues); 6054 } 6055 6056 fp = &sc->fp[fp_index]; 6057 6058 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 6059 BLOGW(sc, "Interface not running, ignoring transmit request\n"); 6060 return (ENETDOWN); 6061 } 6062 6063 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) { 6064 BLOGW(sc, "Interface TX queue is full, ignoring transmit request\n"); 6065 return (EBUSY); 6066 } 6067 6068 if (!sc->link_vars.link_up) { 6069 BLOGW(sc, "Interface link is down, ignoring transmit request\n"); 6070 return (ENETDOWN); 6071 } 6072 6073 /* XXX change to TRYLOCK here and if failed then schedule taskqueue */ 6074 6075 BXE_FP_TX_LOCK(fp); 6076 rc = bxe_tx_mq_start_locked(sc, ifp, fp, m); 6077 BXE_FP_TX_UNLOCK(fp); 6078 6079 return (rc); 6080 } 6081 6082 static void 6083 bxe_mq_flush(struct ifnet *ifp) 6084 { 6085 struct bxe_softc *sc = ifp->if_softc; 6086 struct bxe_fastpath *fp; 6087 struct mbuf *m; 6088 int i; 6089 6090 for (i = 0; i < sc->num_queues; i++) { 6091 fp = &sc->fp[i]; 6092 6093 if (fp->state != BXE_FP_STATE_OPEN) { 6094 BLOGD(sc, DBG_LOAD, "Not clearing fp[%02d] buf_ring (state=%d)\n", 6095 fp->index, fp->state); 6096 continue; 6097 } 6098 6099 if (fp->tx_br != NULL) { 6100 BLOGD(sc, DBG_LOAD, "Clearing fp[%02d] buf_ring\n", fp->index); 6101 BXE_FP_TX_LOCK(fp); 6102 while ((m = buf_ring_dequeue_sc(fp->tx_br)) != NULL) { 6103 m_freem(m); 6104 } 6105 BXE_FP_TX_UNLOCK(fp); 6106 } 6107 } 6108 6109 if_qflush(ifp); 6110 } 6111 6112 #endif /* FreeBSD_version >= 800000 */ 6113 6114 static uint16_t 6115 bxe_cid_ilt_lines(struct bxe_softc *sc) 6116 { 6117 if (IS_SRIOV(sc)) { 6118 return ((BXE_FIRST_VF_CID + BXE_VF_CIDS) / ILT_PAGE_CIDS); 6119 } 6120 return (L2_ILT_LINES(sc)); 6121 } 6122 6123 static void 6124 bxe_ilt_set_info(struct bxe_softc *sc) 6125 { 6126 struct ilt_client_info *ilt_client; 6127 struct ecore_ilt *ilt = sc->ilt; 6128 uint16_t line = 0; 6129 6130 ilt->start_line = FUNC_ILT_BASE(SC_FUNC(sc)); 6131 BLOGD(sc, DBG_LOAD, "ilt starts at line %d\n", ilt->start_line); 6132 6133 /* CDU */ 6134 ilt_client = &ilt->clients[ILT_CLIENT_CDU]; 6135 ilt_client->client_num = ILT_CLIENT_CDU; 6136 ilt_client->page_size = CDU_ILT_PAGE_SZ; 6137 ilt_client->flags = ILT_CLIENT_SKIP_MEM; 6138 ilt_client->start = line; 6139 line += bxe_cid_ilt_lines(sc); 6140 6141 if (CNIC_SUPPORT(sc)) { 6142 line += CNIC_ILT_LINES; 6143 } 6144 6145 ilt_client->end = (line - 1); 6146 6147 BLOGD(sc, DBG_LOAD, 6148 "ilt client[CDU]: start %d, end %d, " 6149 "psz 0x%x, flags 0x%x, hw psz %d\n", 6150 ilt_client->start, ilt_client->end, 6151 ilt_client->page_size, 6152 ilt_client->flags, 6153 ilog2(ilt_client->page_size >> 12)); 6154 6155 /* QM */ 6156 if (QM_INIT(sc->qm_cid_count)) { 6157 ilt_client = &ilt->clients[ILT_CLIENT_QM]; 6158 ilt_client->client_num = ILT_CLIENT_QM; 6159 ilt_client->page_size = QM_ILT_PAGE_SZ; 6160 ilt_client->flags = 0; 6161 ilt_client->start = line; 6162 6163 /* 4 bytes for each cid */ 6164 line += DIV_ROUND_UP(sc->qm_cid_count * QM_QUEUES_PER_FUNC * 4, 6165 QM_ILT_PAGE_SZ); 6166 6167 ilt_client->end = (line - 1); 6168 6169 BLOGD(sc, DBG_LOAD, 6170 "ilt client[QM]: start %d, end %d, " 6171 "psz 0x%x, flags 0x%x, hw psz %d\n", 6172 ilt_client->start, ilt_client->end, 6173 ilt_client->page_size, ilt_client->flags, 6174 ilog2(ilt_client->page_size >> 12)); 6175 } 6176 6177 if (CNIC_SUPPORT(sc)) { 6178 /* SRC */ 6179 ilt_client = &ilt->clients[ILT_CLIENT_SRC]; 6180 ilt_client->client_num = ILT_CLIENT_SRC; 6181 ilt_client->page_size = SRC_ILT_PAGE_SZ; 6182 ilt_client->flags = 0; 6183 ilt_client->start = line; 6184 line += SRC_ILT_LINES; 6185 ilt_client->end = (line - 1); 6186 6187 BLOGD(sc, DBG_LOAD, 6188 "ilt client[SRC]: start %d, end %d, " 6189 "psz 0x%x, flags 0x%x, hw psz %d\n", 6190 ilt_client->start, ilt_client->end, 6191 ilt_client->page_size, ilt_client->flags, 6192 ilog2(ilt_client->page_size >> 12)); 6193 6194 /* TM */ 6195 ilt_client = &ilt->clients[ILT_CLIENT_TM]; 6196 ilt_client->client_num = ILT_CLIENT_TM; 6197 ilt_client->page_size = TM_ILT_PAGE_SZ; 6198 ilt_client->flags = 0; 6199 ilt_client->start = line; 6200 line += TM_ILT_LINES; 6201 ilt_client->end = (line - 1); 6202 6203 BLOGD(sc, DBG_LOAD, 6204 "ilt client[TM]: start %d, end %d, " 6205 "psz 0x%x, flags 0x%x, hw psz %d\n", 6206 ilt_client->start, ilt_client->end, 6207 ilt_client->page_size, ilt_client->flags, 6208 ilog2(ilt_client->page_size >> 12)); 6209 } 6210 6211 KASSERT((line <= ILT_MAX_LINES), ("Invalid number of ILT lines!")); 6212 } 6213 6214 static void 6215 bxe_set_fp_rx_buf_size(struct bxe_softc *sc) 6216 { 6217 int i; 6218 6219 BLOGD(sc, DBG_LOAD, "mtu = %d\n", sc->mtu); 6220 6221 for (i = 0; i < sc->num_queues; i++) { 6222 /* get the Rx buffer size for RX frames */ 6223 sc->fp[i].rx_buf_size = 6224 (IP_HEADER_ALIGNMENT_PADDING + 6225 ETH_OVERHEAD + 6226 sc->mtu); 6227 6228 BLOGD(sc, DBG_LOAD, "rx_buf_size for fp[%02d] = %d\n", 6229 i, sc->fp[i].rx_buf_size); 6230 6231 /* get the mbuf allocation size for RX frames */ 6232 if (sc->fp[i].rx_buf_size <= MCLBYTES) { 6233 sc->fp[i].mbuf_alloc_size = MCLBYTES; 6234 } else if (sc->fp[i].rx_buf_size <= BCM_PAGE_SIZE) { 6235 sc->fp[i].mbuf_alloc_size = PAGE_SIZE; 6236 } else { 6237 sc->fp[i].mbuf_alloc_size = MJUM9BYTES; 6238 } 6239 6240 BLOGD(sc, DBG_LOAD, "mbuf_alloc_size for fp[%02d] = %d\n", 6241 i, sc->fp[i].mbuf_alloc_size); 6242 } 6243 } 6244 6245 static int 6246 bxe_alloc_ilt_mem(struct bxe_softc *sc) 6247 { 6248 int rc = 0; 6249 6250 if ((sc->ilt = 6251 (struct ecore_ilt *)malloc(sizeof(struct ecore_ilt), 6252 M_BXE_ILT, 6253 (M_NOWAIT | M_ZERO))) == NULL) { 6254 rc = 1; 6255 } 6256 6257 return (rc); 6258 } 6259 6260 static int 6261 bxe_alloc_ilt_lines_mem(struct bxe_softc *sc) 6262 { 6263 int rc = 0; 6264 6265 if ((sc->ilt->lines = 6266 (struct ilt_line *)malloc((sizeof(struct ilt_line) * ILT_MAX_LINES), 6267 M_BXE_ILT, 6268 (M_NOWAIT | M_ZERO))) == NULL) { 6269 rc = 1; 6270 } 6271 6272 return (rc); 6273 } 6274 6275 static void 6276 bxe_free_ilt_mem(struct bxe_softc *sc) 6277 { 6278 if (sc->ilt != NULL) { 6279 free(sc->ilt, M_BXE_ILT); 6280 sc->ilt = NULL; 6281 } 6282 } 6283 6284 static void 6285 bxe_free_ilt_lines_mem(struct bxe_softc *sc) 6286 { 6287 if (sc->ilt->lines != NULL) { 6288 free(sc->ilt->lines, M_BXE_ILT); 6289 sc->ilt->lines = NULL; 6290 } 6291 } 6292 6293 static void 6294 bxe_free_mem(struct bxe_softc *sc) 6295 { 6296 int i; 6297 6298 #if 0 6299 if (!CONFIGURE_NIC_MODE(sc)) { 6300 /* free searcher T2 table */ 6301 bxe_dma_free(sc, &sc->t2); 6302 } 6303 #endif 6304 6305 for (i = 0; i < L2_ILT_LINES(sc); i++) { 6306 bxe_dma_free(sc, &sc->context[i].vcxt_dma); 6307 sc->context[i].vcxt = NULL; 6308 sc->context[i].size = 0; 6309 } 6310 6311 ecore_ilt_mem_op(sc, ILT_MEMOP_FREE); 6312 6313 bxe_free_ilt_lines_mem(sc); 6314 6315 #if 0 6316 bxe_iov_free_mem(sc); 6317 #endif 6318 } 6319 6320 static int 6321 bxe_alloc_mem(struct bxe_softc *sc) 6322 { 6323 int context_size; 6324 int allocated; 6325 int i; 6326 6327 #if 0 6328 if (!CONFIGURE_NIC_MODE(sc)) { 6329 /* allocate searcher T2 table */ 6330 if (bxe_dma_alloc(sc, SRC_T2_SZ, 6331 &sc->t2, "searcher t2 table") != 0) { 6332 return (-1); 6333 } 6334 } 6335 #endif 6336 6337 /* 6338 * Allocate memory for CDU context: 6339 * This memory is allocated separately and not in the generic ILT 6340 * functions because CDU differs in few aspects: 6341 * 1. There can be multiple entities allocating memory for context - 6342 * regular L2, CNIC, and SRIOV drivers. Each separately controls 6343 * its own ILT lines. 6344 * 2. Since CDU page-size is not a single 4KB page (which is the case 6345 * for the other ILT clients), to be efficient we want to support 6346 * allocation of sub-page-size in the last entry. 6347 * 3. Context pointers are used by the driver to pass to FW / update 6348 * the context (for the other ILT clients the pointers are used just to 6349 * free the memory during unload). 6350 */ 6351 context_size = (sizeof(union cdu_context) * BXE_L2_CID_COUNT(sc)); 6352 for (i = 0, allocated = 0; allocated < context_size; i++) { 6353 sc->context[i].size = min(CDU_ILT_PAGE_SZ, 6354 (context_size - allocated)); 6355 6356 if (bxe_dma_alloc(sc, sc->context[i].size, 6357 &sc->context[i].vcxt_dma, 6358 "cdu context") != 0) { 6359 bxe_free_mem(sc); 6360 return (-1); 6361 } 6362 6363 sc->context[i].vcxt = 6364 (union cdu_context *)sc->context[i].vcxt_dma.vaddr; 6365 6366 allocated += sc->context[i].size; 6367 } 6368 6369 bxe_alloc_ilt_lines_mem(sc); 6370 6371 BLOGD(sc, DBG_LOAD, "ilt=%p start_line=%u lines=%p\n", 6372 sc->ilt, sc->ilt->start_line, sc->ilt->lines); 6373 { 6374 for (i = 0; i < 4; i++) { 6375 BLOGD(sc, DBG_LOAD, 6376 "c%d page_size=%u start=%u end=%u num=%u flags=0x%x\n", 6377 i, 6378 sc->ilt->clients[i].page_size, 6379 sc->ilt->clients[i].start, 6380 sc->ilt->clients[i].end, 6381 sc->ilt->clients[i].client_num, 6382 sc->ilt->clients[i].flags); 6383 } 6384 } 6385 if (ecore_ilt_mem_op(sc, ILT_MEMOP_ALLOC)) { 6386 BLOGE(sc, "ecore_ilt_mem_op ILT_MEMOP_ALLOC failed\n"); 6387 bxe_free_mem(sc); 6388 return (-1); 6389 } 6390 6391 #if 0 6392 if (bxe_iov_alloc_mem(sc)) { 6393 BLOGE(sc, "Failed to allocate memory for SRIOV\n"); 6394 bxe_free_mem(sc); 6395 return (-1); 6396 } 6397 #endif 6398 6399 return (0); 6400 } 6401 6402 static void 6403 bxe_free_rx_bd_chain(struct bxe_fastpath *fp) 6404 { 6405 struct bxe_softc *sc; 6406 int i; 6407 6408 sc = fp->sc; 6409 6410 if (fp->rx_mbuf_tag == NULL) { 6411 return; 6412 } 6413 6414 /* free all mbufs and unload all maps */ 6415 for (i = 0; i < RX_BD_TOTAL; i++) { 6416 if (fp->rx_mbuf_chain[i].m_map != NULL) { 6417 bus_dmamap_sync(fp->rx_mbuf_tag, 6418 fp->rx_mbuf_chain[i].m_map, 6419 BUS_DMASYNC_POSTREAD); 6420 bus_dmamap_unload(fp->rx_mbuf_tag, 6421 fp->rx_mbuf_chain[i].m_map); 6422 } 6423 6424 if (fp->rx_mbuf_chain[i].m != NULL) { 6425 m_freem(fp->rx_mbuf_chain[i].m); 6426 fp->rx_mbuf_chain[i].m = NULL; 6427 fp->eth_q_stats.mbuf_alloc_rx--; 6428 } 6429 } 6430 } 6431 6432 static void 6433 bxe_free_tpa_pool(struct bxe_fastpath *fp) 6434 { 6435 struct bxe_softc *sc; 6436 int i, max_agg_queues; 6437 6438 sc = fp->sc; 6439 6440 if (fp->rx_mbuf_tag == NULL) { 6441 return; 6442 } 6443 6444 max_agg_queues = MAX_AGG_QS(sc); 6445 6446 /* release all mbufs and unload all DMA maps in the TPA pool */ 6447 for (i = 0; i < max_agg_queues; i++) { 6448 if (fp->rx_tpa_info[i].bd.m_map != NULL) { 6449 bus_dmamap_sync(fp->rx_mbuf_tag, 6450 fp->rx_tpa_info[i].bd.m_map, 6451 BUS_DMASYNC_POSTREAD); 6452 bus_dmamap_unload(fp->rx_mbuf_tag, 6453 fp->rx_tpa_info[i].bd.m_map); 6454 } 6455 6456 if (fp->rx_tpa_info[i].bd.m != NULL) { 6457 m_freem(fp->rx_tpa_info[i].bd.m); 6458 fp->rx_tpa_info[i].bd.m = NULL; 6459 fp->eth_q_stats.mbuf_alloc_tpa--; 6460 } 6461 } 6462 } 6463 6464 static void 6465 bxe_free_sge_chain(struct bxe_fastpath *fp) 6466 { 6467 struct bxe_softc *sc; 6468 int i; 6469 6470 sc = fp->sc; 6471 6472 if (fp->rx_sge_mbuf_tag == NULL) { 6473 return; 6474 } 6475 6476 /* rree all mbufs and unload all maps */ 6477 for (i = 0; i < RX_SGE_TOTAL; i++) { 6478 if (fp->rx_sge_mbuf_chain[i].m_map != NULL) { 6479 bus_dmamap_sync(fp->rx_sge_mbuf_tag, 6480 fp->rx_sge_mbuf_chain[i].m_map, 6481 BUS_DMASYNC_POSTREAD); 6482 bus_dmamap_unload(fp->rx_sge_mbuf_tag, 6483 fp->rx_sge_mbuf_chain[i].m_map); 6484 } 6485 6486 if (fp->rx_sge_mbuf_chain[i].m != NULL) { 6487 m_freem(fp->rx_sge_mbuf_chain[i].m); 6488 fp->rx_sge_mbuf_chain[i].m = NULL; 6489 fp->eth_q_stats.mbuf_alloc_sge--; 6490 } 6491 } 6492 } 6493 6494 static void 6495 bxe_free_fp_buffers(struct bxe_softc *sc) 6496 { 6497 struct bxe_fastpath *fp; 6498 int i; 6499 6500 for (i = 0; i < sc->num_queues; i++) { 6501 fp = &sc->fp[i]; 6502 6503 #if __FreeBSD_version >= 800000 6504 if (fp->tx_br != NULL) { 6505 struct mbuf *m; 6506 /* just in case bxe_mq_flush() wasn't called */ 6507 while ((m = buf_ring_dequeue_sc(fp->tx_br)) != NULL) { 6508 m_freem(m); 6509 } 6510 buf_ring_free(fp->tx_br, M_DEVBUF); 6511 fp->tx_br = NULL; 6512 } 6513 #endif 6514 6515 /* free all RX buffers */ 6516 bxe_free_rx_bd_chain(fp); 6517 bxe_free_tpa_pool(fp); 6518 bxe_free_sge_chain(fp); 6519 6520 if (fp->eth_q_stats.mbuf_alloc_rx != 0) { 6521 BLOGE(sc, "failed to claim all rx mbufs (%d left)\n", 6522 fp->eth_q_stats.mbuf_alloc_rx); 6523 } 6524 6525 if (fp->eth_q_stats.mbuf_alloc_sge != 0) { 6526 BLOGE(sc, "failed to claim all sge mbufs (%d left)\n", 6527 fp->eth_q_stats.mbuf_alloc_sge); 6528 } 6529 6530 if (fp->eth_q_stats.mbuf_alloc_tpa != 0) { 6531 BLOGE(sc, "failed to claim all sge mbufs (%d left)\n", 6532 fp->eth_q_stats.mbuf_alloc_tpa); 6533 } 6534 6535 if (fp->eth_q_stats.mbuf_alloc_tx != 0) { 6536 BLOGE(sc, "failed to release tx mbufs (%d left)\n", 6537 fp->eth_q_stats.mbuf_alloc_tx); 6538 } 6539 6540 /* XXX verify all mbufs were reclaimed */ 6541 6542 if (mtx_initialized(&fp->tx_mtx)) { 6543 mtx_destroy(&fp->tx_mtx); 6544 } 6545 6546 if (mtx_initialized(&fp->rx_mtx)) { 6547 mtx_destroy(&fp->rx_mtx); 6548 } 6549 } 6550 } 6551 6552 static int 6553 bxe_alloc_rx_bd_mbuf(struct bxe_fastpath *fp, 6554 uint16_t prev_index, 6555 uint16_t index) 6556 { 6557 struct bxe_sw_rx_bd *rx_buf; 6558 struct eth_rx_bd *rx_bd; 6559 bus_dma_segment_t segs[1]; 6560 bus_dmamap_t map; 6561 struct mbuf *m; 6562 int nsegs, rc; 6563 6564 rc = 0; 6565 6566 /* allocate the new RX BD mbuf */ 6567 m = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, fp->mbuf_alloc_size); 6568 if (__predict_false(m == NULL)) { 6569 fp->eth_q_stats.mbuf_rx_bd_alloc_failed++; 6570 return (ENOBUFS); 6571 } 6572 6573 fp->eth_q_stats.mbuf_alloc_rx++; 6574 6575 /* initialize the mbuf buffer length */ 6576 m->m_pkthdr.len = m->m_len = fp->rx_buf_size; 6577 6578 /* map the mbuf into non-paged pool */ 6579 rc = bus_dmamap_load_mbuf_sg(fp->rx_mbuf_tag, 6580 fp->rx_mbuf_spare_map, 6581 m, segs, &nsegs, BUS_DMA_NOWAIT); 6582 if (__predict_false(rc != 0)) { 6583 fp->eth_q_stats.mbuf_rx_bd_mapping_failed++; 6584 m_freem(m); 6585 fp->eth_q_stats.mbuf_alloc_rx--; 6586 return (rc); 6587 } 6588 6589 /* all mbufs must map to a single segment */ 6590 KASSERT((nsegs == 1), ("Too many segments, %d returned!", nsegs)); 6591 6592 /* release any existing RX BD mbuf mappings */ 6593 6594 if (prev_index != index) { 6595 rx_buf = &fp->rx_mbuf_chain[prev_index]; 6596 6597 if (rx_buf->m_map != NULL) { 6598 bus_dmamap_sync(fp->rx_mbuf_tag, rx_buf->m_map, 6599 BUS_DMASYNC_POSTREAD); 6600 bus_dmamap_unload(fp->rx_mbuf_tag, rx_buf->m_map); 6601 } 6602 6603 /* 6604 * We only get here from bxe_rxeof() when the maximum number 6605 * of rx buffers is less than RX_BD_USABLE. bxe_rxeof() already 6606 * holds the mbuf in the prev_index so it's OK to NULL it out 6607 * here without concern of a memory leak. 6608 */ 6609 fp->rx_mbuf_chain[prev_index].m = NULL; 6610 } 6611 6612 rx_buf = &fp->rx_mbuf_chain[index]; 6613 6614 if (rx_buf->m_map != NULL) { 6615 bus_dmamap_sync(fp->rx_mbuf_tag, rx_buf->m_map, 6616 BUS_DMASYNC_POSTREAD); 6617 bus_dmamap_unload(fp->rx_mbuf_tag, rx_buf->m_map); 6618 } 6619 6620 /* save the mbuf and mapping info for a future packet */ 6621 map = (prev_index != index) ? 6622 fp->rx_mbuf_chain[prev_index].m_map : rx_buf->m_map; 6623 rx_buf->m_map = fp->rx_mbuf_spare_map; 6624 fp->rx_mbuf_spare_map = map; 6625 bus_dmamap_sync(fp->rx_mbuf_tag, rx_buf->m_map, 6626 BUS_DMASYNC_PREREAD); 6627 rx_buf->m = m; 6628 6629 rx_bd = &fp->rx_chain[index]; 6630 rx_bd->addr_hi = htole32(U64_HI(segs[0].ds_addr)); 6631 rx_bd->addr_lo = htole32(U64_LO(segs[0].ds_addr)); 6632 6633 return (rc); 6634 } 6635 6636 static int 6637 bxe_alloc_rx_tpa_mbuf(struct bxe_fastpath *fp, 6638 int queue) 6639 { 6640 struct bxe_sw_tpa_info *tpa_info = &fp->rx_tpa_info[queue]; 6641 bus_dma_segment_t segs[1]; 6642 bus_dmamap_t map; 6643 struct mbuf *m; 6644 int nsegs; 6645 int rc = 0; 6646 6647 /* allocate the new TPA mbuf */ 6648 m = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, fp->mbuf_alloc_size); 6649 if (__predict_false(m == NULL)) { 6650 fp->eth_q_stats.mbuf_rx_tpa_alloc_failed++; 6651 return (ENOBUFS); 6652 } 6653 6654 fp->eth_q_stats.mbuf_alloc_tpa++; 6655 6656 /* initialize the mbuf buffer length */ 6657 m->m_pkthdr.len = m->m_len = fp->rx_buf_size; 6658 6659 /* map the mbuf into non-paged pool */ 6660 rc = bus_dmamap_load_mbuf_sg(fp->rx_mbuf_tag, 6661 fp->rx_tpa_info_mbuf_spare_map, 6662 m, segs, &nsegs, BUS_DMA_NOWAIT); 6663 if (__predict_false(rc != 0)) { 6664 fp->eth_q_stats.mbuf_rx_tpa_mapping_failed++; 6665 m_free(m); 6666 fp->eth_q_stats.mbuf_alloc_tpa--; 6667 return (rc); 6668 } 6669 6670 /* all mbufs must map to a single segment */ 6671 KASSERT((nsegs == 1), ("Too many segments, %d returned!", nsegs)); 6672 6673 /* release any existing TPA mbuf mapping */ 6674 if (tpa_info->bd.m_map != NULL) { 6675 bus_dmamap_sync(fp->rx_mbuf_tag, tpa_info->bd.m_map, 6676 BUS_DMASYNC_POSTREAD); 6677 bus_dmamap_unload(fp->rx_mbuf_tag, tpa_info->bd.m_map); 6678 } 6679 6680 /* save the mbuf and mapping info for the TPA mbuf */ 6681 map = tpa_info->bd.m_map; 6682 tpa_info->bd.m_map = fp->rx_tpa_info_mbuf_spare_map; 6683 fp->rx_tpa_info_mbuf_spare_map = map; 6684 bus_dmamap_sync(fp->rx_mbuf_tag, tpa_info->bd.m_map, 6685 BUS_DMASYNC_PREREAD); 6686 tpa_info->bd.m = m; 6687 tpa_info->seg = segs[0]; 6688 6689 return (rc); 6690 } 6691 6692 /* 6693 * Allocate an mbuf and assign it to the receive scatter gather chain. The 6694 * caller must take care to save a copy of the existing mbuf in the SG mbuf 6695 * chain. 6696 */ 6697 static int 6698 bxe_alloc_rx_sge_mbuf(struct bxe_fastpath *fp, 6699 uint16_t index) 6700 { 6701 struct bxe_sw_rx_bd *sge_buf; 6702 struct eth_rx_sge *sge; 6703 bus_dma_segment_t segs[1]; 6704 bus_dmamap_t map; 6705 struct mbuf *m; 6706 int nsegs; 6707 int rc = 0; 6708 6709 /* allocate a new SGE mbuf */ 6710 m = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR, SGE_PAGE_SIZE); 6711 if (__predict_false(m == NULL)) { 6712 fp->eth_q_stats.mbuf_rx_sge_alloc_failed++; 6713 return (ENOMEM); 6714 } 6715 6716 fp->eth_q_stats.mbuf_alloc_sge++; 6717 6718 /* initialize the mbuf buffer length */ 6719 m->m_pkthdr.len = m->m_len = SGE_PAGE_SIZE; 6720 6721 /* map the SGE mbuf into non-paged pool */ 6722 rc = bus_dmamap_load_mbuf_sg(fp->rx_sge_mbuf_tag, 6723 fp->rx_sge_mbuf_spare_map, 6724 m, segs, &nsegs, BUS_DMA_NOWAIT); 6725 if (__predict_false(rc != 0)) { 6726 fp->eth_q_stats.mbuf_rx_sge_mapping_failed++; 6727 m_freem(m); 6728 fp->eth_q_stats.mbuf_alloc_sge--; 6729 return (rc); 6730 } 6731 6732 /* all mbufs must map to a single segment */ 6733 KASSERT((nsegs == 1), ("Too many segments, %d returned!", nsegs)); 6734 6735 sge_buf = &fp->rx_sge_mbuf_chain[index]; 6736 6737 /* release any existing SGE mbuf mapping */ 6738 if (sge_buf->m_map != NULL) { 6739 bus_dmamap_sync(fp->rx_sge_mbuf_tag, sge_buf->m_map, 6740 BUS_DMASYNC_POSTREAD); 6741 bus_dmamap_unload(fp->rx_sge_mbuf_tag, sge_buf->m_map); 6742 } 6743 6744 /* save the mbuf and mapping info for a future packet */ 6745 map = sge_buf->m_map; 6746 sge_buf->m_map = fp->rx_sge_mbuf_spare_map; 6747 fp->rx_sge_mbuf_spare_map = map; 6748 bus_dmamap_sync(fp->rx_sge_mbuf_tag, sge_buf->m_map, 6749 BUS_DMASYNC_PREREAD); 6750 sge_buf->m = m; 6751 6752 sge = &fp->rx_sge_chain[index]; 6753 sge->addr_hi = htole32(U64_HI(segs[0].ds_addr)); 6754 sge->addr_lo = htole32(U64_LO(segs[0].ds_addr)); 6755 6756 return (rc); 6757 } 6758 6759 static __noinline int 6760 bxe_alloc_fp_buffers(struct bxe_softc *sc) 6761 { 6762 struct bxe_fastpath *fp; 6763 int i, j, rc = 0; 6764 int ring_prod, cqe_ring_prod; 6765 int max_agg_queues; 6766 6767 for (i = 0; i < sc->num_queues; i++) { 6768 fp = &sc->fp[i]; 6769 6770 #if __FreeBSD_version >= 800000 6771 fp->tx_br = buf_ring_alloc(BXE_BR_SIZE, M_DEVBUF, 6772 M_DONTWAIT, &fp->tx_mtx); 6773 if (fp->tx_br == NULL) { 6774 BLOGE(sc, "buf_ring alloc fail for fp[%02d]\n", i); 6775 goto bxe_alloc_fp_buffers_error; 6776 } 6777 #endif 6778 6779 ring_prod = cqe_ring_prod = 0; 6780 fp->rx_bd_cons = 0; 6781 fp->rx_cq_cons = 0; 6782 6783 /* allocate buffers for the RX BDs in RX BD chain */ 6784 for (j = 0; j < sc->max_rx_bufs; j++) { 6785 rc = bxe_alloc_rx_bd_mbuf(fp, ring_prod, ring_prod); 6786 if (rc != 0) { 6787 BLOGE(sc, "mbuf alloc fail for fp[%02d] rx chain (%d)\n", 6788 i, rc); 6789 goto bxe_alloc_fp_buffers_error; 6790 } 6791 6792 ring_prod = RX_BD_NEXT(ring_prod); 6793 cqe_ring_prod = RCQ_NEXT(cqe_ring_prod); 6794 } 6795 6796 fp->rx_bd_prod = ring_prod; 6797 fp->rx_cq_prod = cqe_ring_prod; 6798 fp->eth_q_stats.rx_calls = fp->eth_q_stats.rx_pkts = 0; 6799 6800 if (sc->ifnet->if_capenable & IFCAP_LRO) { 6801 max_agg_queues = MAX_AGG_QS(sc); 6802 6803 fp->tpa_enable = TRUE; 6804 6805 /* fill the TPA pool */ 6806 for (j = 0; j < max_agg_queues; j++) { 6807 rc = bxe_alloc_rx_tpa_mbuf(fp, j); 6808 if (rc != 0) { 6809 BLOGE(sc, "mbuf alloc fail for fp[%02d] TPA queue %d\n", 6810 i, j); 6811 fp->tpa_enable = FALSE; 6812 goto bxe_alloc_fp_buffers_error; 6813 } 6814 6815 fp->rx_tpa_info[j].state = BXE_TPA_STATE_STOP; 6816 } 6817 6818 if (fp->tpa_enable) { 6819 /* fill the RX SGE chain */ 6820 ring_prod = 0; 6821 for (j = 0; j < RX_SGE_USABLE; j++) { 6822 rc = bxe_alloc_rx_sge_mbuf(fp, ring_prod); 6823 if (rc != 0) { 6824 BLOGE(sc, "mbuf alloc fail for fp[%02d] SGE %d\n", 6825 i, ring_prod); 6826 fp->tpa_enable = FALSE; 6827 ring_prod = 0; 6828 goto bxe_alloc_fp_buffers_error; 6829 } 6830 6831 ring_prod = RX_SGE_NEXT(ring_prod); 6832 } 6833 6834 fp->rx_sge_prod = ring_prod; 6835 } 6836 } 6837 } 6838 6839 return (0); 6840 6841 bxe_alloc_fp_buffers_error: 6842 6843 /* unwind what was already allocated */ 6844 bxe_free_rx_bd_chain(fp); 6845 bxe_free_tpa_pool(fp); 6846 bxe_free_sge_chain(fp); 6847 6848 return (ENOBUFS); 6849 } 6850 6851 static void 6852 bxe_free_fw_stats_mem(struct bxe_softc *sc) 6853 { 6854 bxe_dma_free(sc, &sc->fw_stats_dma); 6855 6856 sc->fw_stats_num = 0; 6857 6858 sc->fw_stats_req_size = 0; 6859 sc->fw_stats_req = NULL; 6860 sc->fw_stats_req_mapping = 0; 6861 6862 sc->fw_stats_data_size = 0; 6863 sc->fw_stats_data = NULL; 6864 sc->fw_stats_data_mapping = 0; 6865 } 6866 6867 static int 6868 bxe_alloc_fw_stats_mem(struct bxe_softc *sc) 6869 { 6870 uint8_t num_queue_stats; 6871 int num_groups; 6872 6873 /* number of queues for statistics is number of eth queues */ 6874 num_queue_stats = BXE_NUM_ETH_QUEUES(sc); 6875 6876 /* 6877 * Total number of FW statistics requests = 6878 * 1 for port stats + 1 for PF stats + num of queues 6879 */ 6880 sc->fw_stats_num = (2 + num_queue_stats); 6881 6882 /* 6883 * Request is built from stats_query_header and an array of 6884 * stats_query_cmd_group each of which contains STATS_QUERY_CMD_COUNT 6885 * rules. The real number or requests is configured in the 6886 * stats_query_header. 6887 */ 6888 num_groups = 6889 ((sc->fw_stats_num / STATS_QUERY_CMD_COUNT) + 6890 ((sc->fw_stats_num % STATS_QUERY_CMD_COUNT) ? 1 : 0)); 6891 6892 BLOGD(sc, DBG_LOAD, "stats fw_stats_num %d num_groups %d\n", 6893 sc->fw_stats_num, num_groups); 6894 6895 sc->fw_stats_req_size = 6896 (sizeof(struct stats_query_header) + 6897 (num_groups * sizeof(struct stats_query_cmd_group))); 6898 6899 /* 6900 * Data for statistics requests + stats_counter. 6901 * stats_counter holds per-STORM counters that are incremented when 6902 * STORM has finished with the current request. Memory for FCoE 6903 * offloaded statistics are counted anyway, even if they will not be sent. 6904 * VF stats are not accounted for here as the data of VF stats is stored 6905 * in memory allocated by the VF, not here. 6906 */ 6907 sc->fw_stats_data_size = 6908 (sizeof(struct stats_counter) + 6909 sizeof(struct per_port_stats) + 6910 sizeof(struct per_pf_stats) + 6911 /* sizeof(struct fcoe_statistics_params) + */ 6912 (sizeof(struct per_queue_stats) * num_queue_stats)); 6913 6914 if (bxe_dma_alloc(sc, (sc->fw_stats_req_size + sc->fw_stats_data_size), 6915 &sc->fw_stats_dma, "fw stats") != 0) { 6916 bxe_free_fw_stats_mem(sc); 6917 return (-1); 6918 } 6919 6920 /* set up the shortcuts */ 6921 6922 sc->fw_stats_req = 6923 (struct bxe_fw_stats_req *)sc->fw_stats_dma.vaddr; 6924 sc->fw_stats_req_mapping = sc->fw_stats_dma.paddr; 6925 6926 sc->fw_stats_data = 6927 (struct bxe_fw_stats_data *)((uint8_t *)sc->fw_stats_dma.vaddr + 6928 sc->fw_stats_req_size); 6929 sc->fw_stats_data_mapping = (sc->fw_stats_dma.paddr + 6930 sc->fw_stats_req_size); 6931 6932 BLOGD(sc, DBG_LOAD, "statistics request base address set to %#jx\n", 6933 (uintmax_t)sc->fw_stats_req_mapping); 6934 6935 BLOGD(sc, DBG_LOAD, "statistics data base address set to %#jx\n", 6936 (uintmax_t)sc->fw_stats_data_mapping); 6937 6938 return (0); 6939 } 6940 6941 /* 6942 * Bits map: 6943 * 0-7 - Engine0 load counter. 6944 * 8-15 - Engine1 load counter. 6945 * 16 - Engine0 RESET_IN_PROGRESS bit. 6946 * 17 - Engine1 RESET_IN_PROGRESS bit. 6947 * 18 - Engine0 ONE_IS_LOADED. Set when there is at least one active 6948 * function on the engine 6949 * 19 - Engine1 ONE_IS_LOADED. 6950 * 20 - Chip reset flow bit. When set none-leader must wait for both engines 6951 * leader to complete (check for both RESET_IN_PROGRESS bits and not 6952 * for just the one belonging to its engine). 6953 */ 6954 #define BXE_RECOVERY_GLOB_REG MISC_REG_GENERIC_POR_1 6955 #define BXE_PATH0_LOAD_CNT_MASK 0x000000ff 6956 #define BXE_PATH0_LOAD_CNT_SHIFT 0 6957 #define BXE_PATH1_LOAD_CNT_MASK 0x0000ff00 6958 #define BXE_PATH1_LOAD_CNT_SHIFT 8 6959 #define BXE_PATH0_RST_IN_PROG_BIT 0x00010000 6960 #define BXE_PATH1_RST_IN_PROG_BIT 0x00020000 6961 #define BXE_GLOBAL_RESET_BIT 0x00040000 6962 6963 /* set the GLOBAL_RESET bit, should be run under rtnl lock */ 6964 static void 6965 bxe_set_reset_global(struct bxe_softc *sc) 6966 { 6967 uint32_t val; 6968 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG); 6969 val = REG_RD(sc, BXE_RECOVERY_GLOB_REG); 6970 REG_WR(sc, BXE_RECOVERY_GLOB_REG, val | BXE_GLOBAL_RESET_BIT); 6971 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG); 6972 } 6973 6974 /* clear the GLOBAL_RESET bit, should be run under rtnl lock */ 6975 static void 6976 bxe_clear_reset_global(struct bxe_softc *sc) 6977 { 6978 uint32_t val; 6979 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG); 6980 val = REG_RD(sc, BXE_RECOVERY_GLOB_REG); 6981 REG_WR(sc, BXE_RECOVERY_GLOB_REG, val & (~BXE_GLOBAL_RESET_BIT)); 6982 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG); 6983 } 6984 6985 /* checks the GLOBAL_RESET bit, should be run under rtnl lock */ 6986 static uint8_t 6987 bxe_reset_is_global(struct bxe_softc *sc) 6988 { 6989 uint32_t val = REG_RD(sc, BXE_RECOVERY_GLOB_REG); 6990 BLOGD(sc, DBG_LOAD, "GLOB_REG=0x%08x\n", val); 6991 return (val & BXE_GLOBAL_RESET_BIT) ? TRUE : FALSE; 6992 } 6993 6994 /* clear RESET_IN_PROGRESS bit for the engine, should be run under rtnl lock */ 6995 static void 6996 bxe_set_reset_done(struct bxe_softc *sc) 6997 { 6998 uint32_t val; 6999 uint32_t bit = SC_PATH(sc) ? BXE_PATH1_RST_IN_PROG_BIT : 7000 BXE_PATH0_RST_IN_PROG_BIT; 7001 7002 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG); 7003 7004 val = REG_RD(sc, BXE_RECOVERY_GLOB_REG); 7005 /* Clear the bit */ 7006 val &= ~bit; 7007 REG_WR(sc, BXE_RECOVERY_GLOB_REG, val); 7008 7009 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG); 7010 } 7011 7012 /* set RESET_IN_PROGRESS for the engine, should be run under rtnl lock */ 7013 static void 7014 bxe_set_reset_in_progress(struct bxe_softc *sc) 7015 { 7016 uint32_t val; 7017 uint32_t bit = SC_PATH(sc) ? BXE_PATH1_RST_IN_PROG_BIT : 7018 BXE_PATH0_RST_IN_PROG_BIT; 7019 7020 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG); 7021 7022 val = REG_RD(sc, BXE_RECOVERY_GLOB_REG); 7023 /* Set the bit */ 7024 val |= bit; 7025 REG_WR(sc, BXE_RECOVERY_GLOB_REG, val); 7026 7027 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG); 7028 } 7029 7030 /* check RESET_IN_PROGRESS bit for an engine, should be run under rtnl lock */ 7031 static uint8_t 7032 bxe_reset_is_done(struct bxe_softc *sc, 7033 int engine) 7034 { 7035 uint32_t val = REG_RD(sc, BXE_RECOVERY_GLOB_REG); 7036 uint32_t bit = engine ? BXE_PATH1_RST_IN_PROG_BIT : 7037 BXE_PATH0_RST_IN_PROG_BIT; 7038 7039 /* return false if bit is set */ 7040 return (val & bit) ? FALSE : TRUE; 7041 } 7042 7043 /* get the load status for an engine, should be run under rtnl lock */ 7044 static uint8_t 7045 bxe_get_load_status(struct bxe_softc *sc, 7046 int engine) 7047 { 7048 uint32_t mask = engine ? BXE_PATH1_LOAD_CNT_MASK : 7049 BXE_PATH0_LOAD_CNT_MASK; 7050 uint32_t shift = engine ? BXE_PATH1_LOAD_CNT_SHIFT : 7051 BXE_PATH0_LOAD_CNT_SHIFT; 7052 uint32_t val = REG_RD(sc, BXE_RECOVERY_GLOB_REG); 7053 7054 BLOGD(sc, DBG_LOAD, "Old value for GLOB_REG=0x%08x\n", val); 7055 7056 val = ((val & mask) >> shift); 7057 7058 BLOGD(sc, DBG_LOAD, "Load mask engine %d = 0x%08x\n", engine, val); 7059 7060 return (val != 0); 7061 } 7062 7063 /* set pf load mark */ 7064 /* XXX needs to be under rtnl lock */ 7065 static void 7066 bxe_set_pf_load(struct bxe_softc *sc) 7067 { 7068 uint32_t val; 7069 uint32_t val1; 7070 uint32_t mask = SC_PATH(sc) ? BXE_PATH1_LOAD_CNT_MASK : 7071 BXE_PATH0_LOAD_CNT_MASK; 7072 uint32_t shift = SC_PATH(sc) ? BXE_PATH1_LOAD_CNT_SHIFT : 7073 BXE_PATH0_LOAD_CNT_SHIFT; 7074 7075 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG); 7076 7077 val = REG_RD(sc, BXE_RECOVERY_GLOB_REG); 7078 BLOGD(sc, DBG_LOAD, "Old value for GLOB_REG=0x%08x\n", val); 7079 7080 /* get the current counter value */ 7081 val1 = ((val & mask) >> shift); 7082 7083 /* set bit of this PF */ 7084 val1 |= (1 << SC_ABS_FUNC(sc)); 7085 7086 /* clear the old value */ 7087 val &= ~mask; 7088 7089 /* set the new one */ 7090 val |= ((val1 << shift) & mask); 7091 7092 REG_WR(sc, BXE_RECOVERY_GLOB_REG, val); 7093 7094 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG); 7095 } 7096 7097 /* clear pf load mark */ 7098 /* XXX needs to be under rtnl lock */ 7099 static uint8_t 7100 bxe_clear_pf_load(struct bxe_softc *sc) 7101 { 7102 uint32_t val1, val; 7103 uint32_t mask = SC_PATH(sc) ? BXE_PATH1_LOAD_CNT_MASK : 7104 BXE_PATH0_LOAD_CNT_MASK; 7105 uint32_t shift = SC_PATH(sc) ? BXE_PATH1_LOAD_CNT_SHIFT : 7106 BXE_PATH0_LOAD_CNT_SHIFT; 7107 7108 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG); 7109 val = REG_RD(sc, BXE_RECOVERY_GLOB_REG); 7110 BLOGD(sc, DBG_LOAD, "Old GEN_REG_VAL=0x%08x\n", val); 7111 7112 /* get the current counter value */ 7113 val1 = (val & mask) >> shift; 7114 7115 /* clear bit of that PF */ 7116 val1 &= ~(1 << SC_ABS_FUNC(sc)); 7117 7118 /* clear the old value */ 7119 val &= ~mask; 7120 7121 /* set the new one */ 7122 val |= ((val1 << shift) & mask); 7123 7124 REG_WR(sc, BXE_RECOVERY_GLOB_REG, val); 7125 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_RECOVERY_REG); 7126 return (val1 != 0); 7127 } 7128 7129 /* send load requrest to mcp and analyze response */ 7130 static int 7131 bxe_nic_load_request(struct bxe_softc *sc, 7132 uint32_t *load_code) 7133 { 7134 /* init fw_seq */ 7135 sc->fw_seq = 7136 (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_mb_header) & 7137 DRV_MSG_SEQ_NUMBER_MASK); 7138 7139 BLOGD(sc, DBG_LOAD, "initial fw_seq 0x%04x\n", sc->fw_seq); 7140 7141 /* get the current FW pulse sequence */ 7142 sc->fw_drv_pulse_wr_seq = 7143 (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_pulse_mb) & 7144 DRV_PULSE_SEQ_MASK); 7145 7146 BLOGD(sc, DBG_LOAD, "initial drv_pulse 0x%04x\n", 7147 sc->fw_drv_pulse_wr_seq); 7148 7149 /* load request */ 7150 (*load_code) = bxe_fw_command(sc, DRV_MSG_CODE_LOAD_REQ, 7151 DRV_MSG_CODE_LOAD_REQ_WITH_LFA); 7152 7153 /* if the MCP fails to respond we must abort */ 7154 if (!(*load_code)) { 7155 BLOGE(sc, "MCP response failure!\n"); 7156 return (-1); 7157 } 7158 7159 /* if MCP refused then must abort */ 7160 if ((*load_code) == FW_MSG_CODE_DRV_LOAD_REFUSED) { 7161 BLOGE(sc, "MCP refused load request\n"); 7162 return (-1); 7163 } 7164 7165 return (0); 7166 } 7167 7168 /* 7169 * Check whether another PF has already loaded FW to chip. In virtualized 7170 * environments a pf from anoth VM may have already initialized the device 7171 * including loading FW. 7172 */ 7173 static int 7174 bxe_nic_load_analyze_req(struct bxe_softc *sc, 7175 uint32_t load_code) 7176 { 7177 uint32_t my_fw, loaded_fw; 7178 7179 /* is another pf loaded on this engine? */ 7180 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) && 7181 (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) { 7182 /* build my FW version dword */ 7183 my_fw = (BCM_5710_FW_MAJOR_VERSION + 7184 (BCM_5710_FW_MINOR_VERSION << 8 ) + 7185 (BCM_5710_FW_REVISION_VERSION << 16) + 7186 (BCM_5710_FW_ENGINEERING_VERSION << 24)); 7187 7188 /* read loaded FW from chip */ 7189 loaded_fw = REG_RD(sc, XSEM_REG_PRAM); 7190 BLOGD(sc, DBG_LOAD, "loaded FW 0x%08x / my FW 0x%08x\n", 7191 loaded_fw, my_fw); 7192 7193 /* abort nic load if version mismatch */ 7194 if (my_fw != loaded_fw) { 7195 BLOGE(sc, "FW 0x%08x already loaded (mine is 0x%08x)", 7196 loaded_fw, my_fw); 7197 return (-1); 7198 } 7199 } 7200 7201 return (0); 7202 } 7203 7204 /* mark PMF if applicable */ 7205 static void 7206 bxe_nic_load_pmf(struct bxe_softc *sc, 7207 uint32_t load_code) 7208 { 7209 uint32_t ncsi_oem_data_addr; 7210 7211 if ((load_code == FW_MSG_CODE_DRV_LOAD_COMMON) || 7212 (load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) || 7213 (load_code == FW_MSG_CODE_DRV_LOAD_PORT)) { 7214 /* 7215 * Barrier here for ordering between the writing to sc->port.pmf here 7216 * and reading it from the periodic task. 7217 */ 7218 sc->port.pmf = 1; 7219 mb(); 7220 } else { 7221 sc->port.pmf = 0; 7222 } 7223 7224 BLOGD(sc, DBG_LOAD, "pmf %d\n", sc->port.pmf); 7225 7226 /* XXX needed? */ 7227 if (load_code == FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) { 7228 if (SHMEM2_HAS(sc, ncsi_oem_data_addr)) { 7229 ncsi_oem_data_addr = SHMEM2_RD(sc, ncsi_oem_data_addr); 7230 if (ncsi_oem_data_addr) { 7231 REG_WR(sc, 7232 (ncsi_oem_data_addr + 7233 offsetof(struct glob_ncsi_oem_data, driver_version)), 7234 0); 7235 } 7236 } 7237 } 7238 } 7239 7240 static void 7241 bxe_read_mf_cfg(struct bxe_softc *sc) 7242 { 7243 int n = (CHIP_IS_MODE_4_PORT(sc) ? 2 : 1); 7244 int abs_func; 7245 int vn; 7246 7247 if (BXE_NOMCP(sc)) { 7248 return; /* what should be the default bvalue in this case */ 7249 } 7250 7251 /* 7252 * The formula for computing the absolute function number is... 7253 * For 2 port configuration (4 functions per port): 7254 * abs_func = 2 * vn + SC_PORT + SC_PATH 7255 * For 4 port configuration (2 functions per port): 7256 * abs_func = 4 * vn + 2 * SC_PORT + SC_PATH 7257 */ 7258 for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) { 7259 abs_func = (n * (2 * vn + SC_PORT(sc)) + SC_PATH(sc)); 7260 if (abs_func >= E1H_FUNC_MAX) { 7261 break; 7262 } 7263 sc->devinfo.mf_info.mf_config[vn] = 7264 MFCFG_RD(sc, func_mf_config[abs_func].config); 7265 } 7266 7267 if (sc->devinfo.mf_info.mf_config[SC_VN(sc)] & 7268 FUNC_MF_CFG_FUNC_DISABLED) { 7269 BLOGD(sc, DBG_LOAD, "mf_cfg function disabled\n"); 7270 sc->flags |= BXE_MF_FUNC_DIS; 7271 } else { 7272 BLOGD(sc, DBG_LOAD, "mf_cfg function enabled\n"); 7273 sc->flags &= ~BXE_MF_FUNC_DIS; 7274 } 7275 } 7276 7277 /* acquire split MCP access lock register */ 7278 static int bxe_acquire_alr(struct bxe_softc *sc) 7279 { 7280 uint32_t j, val; 7281 7282 for (j = 0; j < 1000; j++) { 7283 val = (1UL << 31); 7284 REG_WR(sc, GRCBASE_MCP + 0x9c, val); 7285 val = REG_RD(sc, GRCBASE_MCP + 0x9c); 7286 if (val & (1L << 31)) 7287 break; 7288 7289 DELAY(5000); 7290 } 7291 7292 if (!(val & (1L << 31))) { 7293 BLOGE(sc, "Cannot acquire MCP access lock register\n"); 7294 return (-1); 7295 } 7296 7297 return (0); 7298 } 7299 7300 /* release split MCP access lock register */ 7301 static void bxe_release_alr(struct bxe_softc *sc) 7302 { 7303 REG_WR(sc, GRCBASE_MCP + 0x9c, 0); 7304 } 7305 7306 static void 7307 bxe_fan_failure(struct bxe_softc *sc) 7308 { 7309 int port = SC_PORT(sc); 7310 uint32_t ext_phy_config; 7311 7312 /* mark the failure */ 7313 ext_phy_config = 7314 SHMEM_RD(sc, dev_info.port_hw_config[port].external_phy_config); 7315 7316 ext_phy_config &= ~PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK; 7317 ext_phy_config |= PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE; 7318 SHMEM_WR(sc, dev_info.port_hw_config[port].external_phy_config, 7319 ext_phy_config); 7320 7321 /* log the failure */ 7322 BLOGW(sc, "Fan Failure has caused the driver to shutdown " 7323 "the card to prevent permanent damage. " 7324 "Please contact OEM Support for assistance\n"); 7325 7326 /* XXX */ 7327 #if 1 7328 bxe_panic(sc, ("Schedule task to handle fan failure\n")); 7329 #else 7330 /* 7331 * Schedule device reset (unload) 7332 * This is due to some boards consuming sufficient power when driver is 7333 * up to overheat if fan fails. 7334 */ 7335 bxe_set_bit(BXE_SP_RTNL_FAN_FAILURE, &sc->sp_rtnl_state); 7336 schedule_delayed_work(&sc->sp_rtnl_task, 0); 7337 #endif 7338 } 7339 7340 /* this function is called upon a link interrupt */ 7341 static void 7342 bxe_link_attn(struct bxe_softc *sc) 7343 { 7344 uint32_t pause_enabled = 0; 7345 struct host_port_stats *pstats; 7346 int cmng_fns; 7347 7348 /* Make sure that we are synced with the current statistics */ 7349 bxe_stats_handle(sc, STATS_EVENT_STOP); 7350 7351 elink_link_update(&sc->link_params, &sc->link_vars); 7352 7353 if (sc->link_vars.link_up) { 7354 7355 /* dropless flow control */ 7356 if (!CHIP_IS_E1(sc) && sc->dropless_fc) { 7357 pause_enabled = 0; 7358 7359 if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_TX) { 7360 pause_enabled = 1; 7361 } 7362 7363 REG_WR(sc, 7364 (BAR_USTRORM_INTMEM + 7365 USTORM_ETH_PAUSE_ENABLED_OFFSET(SC_PORT(sc))), 7366 pause_enabled); 7367 } 7368 7369 if (sc->link_vars.mac_type != ELINK_MAC_TYPE_EMAC) { 7370 pstats = BXE_SP(sc, port_stats); 7371 /* reset old mac stats */ 7372 memset(&(pstats->mac_stx[0]), 0, sizeof(struct mac_stx)); 7373 } 7374 7375 if (sc->state == BXE_STATE_OPEN) { 7376 bxe_stats_handle(sc, STATS_EVENT_LINK_UP); 7377 } 7378 } 7379 7380 if (sc->link_vars.link_up && sc->link_vars.line_speed) { 7381 cmng_fns = bxe_get_cmng_fns_mode(sc); 7382 7383 if (cmng_fns != CMNG_FNS_NONE) { 7384 bxe_cmng_fns_init(sc, FALSE, cmng_fns); 7385 storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc)); 7386 } else { 7387 /* rate shaping and fairness are disabled */ 7388 BLOGD(sc, DBG_LOAD, "single function mode without fairness\n"); 7389 } 7390 } 7391 7392 bxe_link_report_locked(sc); 7393 7394 if (IS_MF(sc)) { 7395 ; // XXX bxe_link_sync_notify(sc); 7396 } 7397 } 7398 7399 static void 7400 bxe_attn_int_asserted(struct bxe_softc *sc, 7401 uint32_t asserted) 7402 { 7403 int port = SC_PORT(sc); 7404 uint32_t aeu_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : 7405 MISC_REG_AEU_MASK_ATTN_FUNC_0; 7406 uint32_t nig_int_mask_addr = port ? NIG_REG_MASK_INTERRUPT_PORT1 : 7407 NIG_REG_MASK_INTERRUPT_PORT0; 7408 uint32_t aeu_mask; 7409 uint32_t nig_mask = 0; 7410 uint32_t reg_addr; 7411 uint32_t igu_acked; 7412 uint32_t cnt; 7413 7414 if (sc->attn_state & asserted) { 7415 BLOGE(sc, "IGU ERROR attn=0x%08x\n", asserted); 7416 } 7417 7418 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); 7419 7420 aeu_mask = REG_RD(sc, aeu_addr); 7421 7422 BLOGD(sc, DBG_INTR, "aeu_mask 0x%08x newly asserted 0x%08x\n", 7423 aeu_mask, asserted); 7424 7425 aeu_mask &= ~(asserted & 0x3ff); 7426 7427 BLOGD(sc, DBG_INTR, "new mask 0x%08x\n", aeu_mask); 7428 7429 REG_WR(sc, aeu_addr, aeu_mask); 7430 7431 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); 7432 7433 BLOGD(sc, DBG_INTR, "attn_state 0x%08x\n", sc->attn_state); 7434 sc->attn_state |= asserted; 7435 BLOGD(sc, DBG_INTR, "new state 0x%08x\n", sc->attn_state); 7436 7437 if (asserted & ATTN_HARD_WIRED_MASK) { 7438 if (asserted & ATTN_NIG_FOR_FUNC) { 7439 7440 BXE_PHY_LOCK(sc); 7441 7442 /* save nig interrupt mask */ 7443 nig_mask = REG_RD(sc, nig_int_mask_addr); 7444 7445 /* If nig_mask is not set, no need to call the update function */ 7446 if (nig_mask) { 7447 REG_WR(sc, nig_int_mask_addr, 0); 7448 7449 bxe_link_attn(sc); 7450 } 7451 7452 /* handle unicore attn? */ 7453 } 7454 7455 if (asserted & ATTN_SW_TIMER_4_FUNC) { 7456 BLOGD(sc, DBG_INTR, "ATTN_SW_TIMER_4_FUNC!\n"); 7457 } 7458 7459 if (asserted & GPIO_2_FUNC) { 7460 BLOGD(sc, DBG_INTR, "GPIO_2_FUNC!\n"); 7461 } 7462 7463 if (asserted & GPIO_3_FUNC) { 7464 BLOGD(sc, DBG_INTR, "GPIO_3_FUNC!\n"); 7465 } 7466 7467 if (asserted & GPIO_4_FUNC) { 7468 BLOGD(sc, DBG_INTR, "GPIO_4_FUNC!\n"); 7469 } 7470 7471 if (port == 0) { 7472 if (asserted & ATTN_GENERAL_ATTN_1) { 7473 BLOGD(sc, DBG_INTR, "ATTN_GENERAL_ATTN_1!\n"); 7474 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_1, 0x0); 7475 } 7476 if (asserted & ATTN_GENERAL_ATTN_2) { 7477 BLOGD(sc, DBG_INTR, "ATTN_GENERAL_ATTN_2!\n"); 7478 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_2, 0x0); 7479 } 7480 if (asserted & ATTN_GENERAL_ATTN_3) { 7481 BLOGD(sc, DBG_INTR, "ATTN_GENERAL_ATTN_3!\n"); 7482 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_3, 0x0); 7483 } 7484 } else { 7485 if (asserted & ATTN_GENERAL_ATTN_4) { 7486 BLOGD(sc, DBG_INTR, "ATTN_GENERAL_ATTN_4!\n"); 7487 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_4, 0x0); 7488 } 7489 if (asserted & ATTN_GENERAL_ATTN_5) { 7490 BLOGD(sc, DBG_INTR, "ATTN_GENERAL_ATTN_5!\n"); 7491 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_5, 0x0); 7492 } 7493 if (asserted & ATTN_GENERAL_ATTN_6) { 7494 BLOGD(sc, DBG_INTR, "ATTN_GENERAL_ATTN_6!\n"); 7495 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_6, 0x0); 7496 } 7497 } 7498 } /* hardwired */ 7499 7500 if (sc->devinfo.int_block == INT_BLOCK_HC) { 7501 reg_addr = (HC_REG_COMMAND_REG + port*32 + COMMAND_REG_ATTN_BITS_SET); 7502 } else { 7503 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_SET_UPPER*8); 7504 } 7505 7506 BLOGD(sc, DBG_INTR, "about to mask 0x%08x at %s addr 0x%08x\n", 7507 asserted, 7508 (sc->devinfo.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr); 7509 REG_WR(sc, reg_addr, asserted); 7510 7511 /* now set back the mask */ 7512 if (asserted & ATTN_NIG_FOR_FUNC) { 7513 /* 7514 * Verify that IGU ack through BAR was written before restoring 7515 * NIG mask. This loop should exit after 2-3 iterations max. 7516 */ 7517 if (sc->devinfo.int_block != INT_BLOCK_HC) { 7518 cnt = 0; 7519 7520 do { 7521 igu_acked = REG_RD(sc, IGU_REG_ATTENTION_ACK_BITS); 7522 } while (((igu_acked & ATTN_NIG_FOR_FUNC) == 0) && 7523 (++cnt < MAX_IGU_ATTN_ACK_TO)); 7524 7525 if (!igu_acked) { 7526 BLOGE(sc, "Failed to verify IGU ack on time\n"); 7527 } 7528 7529 mb(); 7530 } 7531 7532 REG_WR(sc, nig_int_mask_addr, nig_mask); 7533 7534 BXE_PHY_UNLOCK(sc); 7535 } 7536 } 7537 7538 static void 7539 bxe_print_next_block(struct bxe_softc *sc, 7540 int idx, 7541 const char *blk) 7542 { 7543 BLOGI(sc, "%s%s", idx ? ", " : "", blk); 7544 } 7545 7546 static int 7547 bxe_check_blocks_with_parity0(struct bxe_softc *sc, 7548 uint32_t sig, 7549 int par_num, 7550 uint8_t print) 7551 { 7552 uint32_t cur_bit = 0; 7553 int i = 0; 7554 7555 for (i = 0; sig; i++) { 7556 cur_bit = ((uint32_t)0x1 << i); 7557 if (sig & cur_bit) { 7558 switch (cur_bit) { 7559 case AEU_INPUTS_ATTN_BITS_BRB_PARITY_ERROR: 7560 if (print) 7561 bxe_print_next_block(sc, par_num++, "BRB"); 7562 break; 7563 case AEU_INPUTS_ATTN_BITS_PARSER_PARITY_ERROR: 7564 if (print) 7565 bxe_print_next_block(sc, par_num++, "PARSER"); 7566 break; 7567 case AEU_INPUTS_ATTN_BITS_TSDM_PARITY_ERROR: 7568 if (print) 7569 bxe_print_next_block(sc, par_num++, "TSDM"); 7570 break; 7571 case AEU_INPUTS_ATTN_BITS_SEARCHER_PARITY_ERROR: 7572 if (print) 7573 bxe_print_next_block(sc, par_num++, "SEARCHER"); 7574 break; 7575 case AEU_INPUTS_ATTN_BITS_TCM_PARITY_ERROR: 7576 if (print) 7577 bxe_print_next_block(sc, par_num++, "TCM"); 7578 break; 7579 case AEU_INPUTS_ATTN_BITS_TSEMI_PARITY_ERROR: 7580 if (print) 7581 bxe_print_next_block(sc, par_num++, "TSEMI"); 7582 break; 7583 case AEU_INPUTS_ATTN_BITS_PBCLIENT_PARITY_ERROR: 7584 if (print) 7585 bxe_print_next_block(sc, par_num++, "XPB"); 7586 break; 7587 } 7588 7589 /* Clear the bit */ 7590 sig &= ~cur_bit; 7591 } 7592 } 7593 7594 return (par_num); 7595 } 7596 7597 static int 7598 bxe_check_blocks_with_parity1(struct bxe_softc *sc, 7599 uint32_t sig, 7600 int par_num, 7601 uint8_t *global, 7602 uint8_t print) 7603 { 7604 int i = 0; 7605 uint32_t cur_bit = 0; 7606 for (i = 0; sig; i++) { 7607 cur_bit = ((uint32_t)0x1 << i); 7608 if (sig & cur_bit) { 7609 switch (cur_bit) { 7610 case AEU_INPUTS_ATTN_BITS_PBF_PARITY_ERROR: 7611 if (print) 7612 bxe_print_next_block(sc, par_num++, "PBF"); 7613 break; 7614 case AEU_INPUTS_ATTN_BITS_QM_PARITY_ERROR: 7615 if (print) 7616 bxe_print_next_block(sc, par_num++, "QM"); 7617 break; 7618 case AEU_INPUTS_ATTN_BITS_TIMERS_PARITY_ERROR: 7619 if (print) 7620 bxe_print_next_block(sc, par_num++, "TM"); 7621 break; 7622 case AEU_INPUTS_ATTN_BITS_XSDM_PARITY_ERROR: 7623 if (print) 7624 bxe_print_next_block(sc, par_num++, "XSDM"); 7625 break; 7626 case AEU_INPUTS_ATTN_BITS_XCM_PARITY_ERROR: 7627 if (print) 7628 bxe_print_next_block(sc, par_num++, "XCM"); 7629 break; 7630 case AEU_INPUTS_ATTN_BITS_XSEMI_PARITY_ERROR: 7631 if (print) 7632 bxe_print_next_block(sc, par_num++, "XSEMI"); 7633 break; 7634 case AEU_INPUTS_ATTN_BITS_DOORBELLQ_PARITY_ERROR: 7635 if (print) 7636 bxe_print_next_block(sc, par_num++, "DOORBELLQ"); 7637 break; 7638 case AEU_INPUTS_ATTN_BITS_NIG_PARITY_ERROR: 7639 if (print) 7640 bxe_print_next_block(sc, par_num++, "NIG"); 7641 break; 7642 case AEU_INPUTS_ATTN_BITS_VAUX_PCI_CORE_PARITY_ERROR: 7643 if (print) 7644 bxe_print_next_block(sc, par_num++, "VAUX PCI CORE"); 7645 *global = TRUE; 7646 break; 7647 case AEU_INPUTS_ATTN_BITS_DEBUG_PARITY_ERROR: 7648 if (print) 7649 bxe_print_next_block(sc, par_num++, "DEBUG"); 7650 break; 7651 case AEU_INPUTS_ATTN_BITS_USDM_PARITY_ERROR: 7652 if (print) 7653 bxe_print_next_block(sc, par_num++, "USDM"); 7654 break; 7655 case AEU_INPUTS_ATTN_BITS_UCM_PARITY_ERROR: 7656 if (print) 7657 bxe_print_next_block(sc, par_num++, "UCM"); 7658 break; 7659 case AEU_INPUTS_ATTN_BITS_USEMI_PARITY_ERROR: 7660 if (print) 7661 bxe_print_next_block(sc, par_num++, "USEMI"); 7662 break; 7663 case AEU_INPUTS_ATTN_BITS_UPB_PARITY_ERROR: 7664 if (print) 7665 bxe_print_next_block(sc, par_num++, "UPB"); 7666 break; 7667 case AEU_INPUTS_ATTN_BITS_CSDM_PARITY_ERROR: 7668 if (print) 7669 bxe_print_next_block(sc, par_num++, "CSDM"); 7670 break; 7671 case AEU_INPUTS_ATTN_BITS_CCM_PARITY_ERROR: 7672 if (print) 7673 bxe_print_next_block(sc, par_num++, "CCM"); 7674 break; 7675 } 7676 7677 /* Clear the bit */ 7678 sig &= ~cur_bit; 7679 } 7680 } 7681 7682 return (par_num); 7683 } 7684 7685 static int 7686 bxe_check_blocks_with_parity2(struct bxe_softc *sc, 7687 uint32_t sig, 7688 int par_num, 7689 uint8_t print) 7690 { 7691 uint32_t cur_bit = 0; 7692 int i = 0; 7693 7694 for (i = 0; sig; i++) { 7695 cur_bit = ((uint32_t)0x1 << i); 7696 if (sig & cur_bit) { 7697 switch (cur_bit) { 7698 case AEU_INPUTS_ATTN_BITS_CSEMI_PARITY_ERROR: 7699 if (print) 7700 bxe_print_next_block(sc, par_num++, "CSEMI"); 7701 break; 7702 case AEU_INPUTS_ATTN_BITS_PXP_PARITY_ERROR: 7703 if (print) 7704 bxe_print_next_block(sc, par_num++, "PXP"); 7705 break; 7706 case AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR: 7707 if (print) 7708 bxe_print_next_block(sc, par_num++, "PXPPCICLOCKCLIENT"); 7709 break; 7710 case AEU_INPUTS_ATTN_BITS_CFC_PARITY_ERROR: 7711 if (print) 7712 bxe_print_next_block(sc, par_num++, "CFC"); 7713 break; 7714 case AEU_INPUTS_ATTN_BITS_CDU_PARITY_ERROR: 7715 if (print) 7716 bxe_print_next_block(sc, par_num++, "CDU"); 7717 break; 7718 case AEU_INPUTS_ATTN_BITS_DMAE_PARITY_ERROR: 7719 if (print) 7720 bxe_print_next_block(sc, par_num++, "DMAE"); 7721 break; 7722 case AEU_INPUTS_ATTN_BITS_IGU_PARITY_ERROR: 7723 if (print) 7724 bxe_print_next_block(sc, par_num++, "IGU"); 7725 break; 7726 case AEU_INPUTS_ATTN_BITS_MISC_PARITY_ERROR: 7727 if (print) 7728 bxe_print_next_block(sc, par_num++, "MISC"); 7729 break; 7730 } 7731 7732 /* Clear the bit */ 7733 sig &= ~cur_bit; 7734 } 7735 } 7736 7737 return (par_num); 7738 } 7739 7740 static int 7741 bxe_check_blocks_with_parity3(struct bxe_softc *sc, 7742 uint32_t sig, 7743 int par_num, 7744 uint8_t *global, 7745 uint8_t print) 7746 { 7747 uint32_t cur_bit = 0; 7748 int i = 0; 7749 7750 for (i = 0; sig; i++) { 7751 cur_bit = ((uint32_t)0x1 << i); 7752 if (sig & cur_bit) { 7753 switch (cur_bit) { 7754 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_ROM_PARITY: 7755 if (print) 7756 bxe_print_next_block(sc, par_num++, "MCP ROM"); 7757 *global = TRUE; 7758 break; 7759 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_RX_PARITY: 7760 if (print) 7761 bxe_print_next_block(sc, par_num++, 7762 "MCP UMP RX"); 7763 *global = TRUE; 7764 break; 7765 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_UMP_TX_PARITY: 7766 if (print) 7767 bxe_print_next_block(sc, par_num++, 7768 "MCP UMP TX"); 7769 *global = TRUE; 7770 break; 7771 case AEU_INPUTS_ATTN_BITS_MCP_LATCHED_SCPAD_PARITY: 7772 if (print) 7773 bxe_print_next_block(sc, par_num++, 7774 "MCP SCPAD"); 7775 *global = TRUE; 7776 break; 7777 } 7778 7779 /* Clear the bit */ 7780 sig &= ~cur_bit; 7781 } 7782 } 7783 7784 return (par_num); 7785 } 7786 7787 static int 7788 bxe_check_blocks_with_parity4(struct bxe_softc *sc, 7789 uint32_t sig, 7790 int par_num, 7791 uint8_t print) 7792 { 7793 uint32_t cur_bit = 0; 7794 int i = 0; 7795 7796 for (i = 0; sig; i++) { 7797 cur_bit = ((uint32_t)0x1 << i); 7798 if (sig & cur_bit) { 7799 switch (cur_bit) { 7800 case AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR: 7801 if (print) 7802 bxe_print_next_block(sc, par_num++, "PGLUE_B"); 7803 break; 7804 case AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR: 7805 if (print) 7806 bxe_print_next_block(sc, par_num++, "ATC"); 7807 break; 7808 } 7809 7810 /* Clear the bit */ 7811 sig &= ~cur_bit; 7812 } 7813 } 7814 7815 return (par_num); 7816 } 7817 7818 static uint8_t 7819 bxe_parity_attn(struct bxe_softc *sc, 7820 uint8_t *global, 7821 uint8_t print, 7822 uint32_t *sig) 7823 { 7824 int par_num = 0; 7825 7826 if ((sig[0] & HW_PRTY_ASSERT_SET_0) || 7827 (sig[1] & HW_PRTY_ASSERT_SET_1) || 7828 (sig[2] & HW_PRTY_ASSERT_SET_2) || 7829 (sig[3] & HW_PRTY_ASSERT_SET_3) || 7830 (sig[4] & HW_PRTY_ASSERT_SET_4)) { 7831 BLOGE(sc, "Parity error: HW block parity attention:\n" 7832 "[0]:0x%08x [1]:0x%08x [2]:0x%08x [3]:0x%08x [4]:0x%08x\n", 7833 (uint32_t)(sig[0] & HW_PRTY_ASSERT_SET_0), 7834 (uint32_t)(sig[1] & HW_PRTY_ASSERT_SET_1), 7835 (uint32_t)(sig[2] & HW_PRTY_ASSERT_SET_2), 7836 (uint32_t)(sig[3] & HW_PRTY_ASSERT_SET_3), 7837 (uint32_t)(sig[4] & HW_PRTY_ASSERT_SET_4)); 7838 7839 if (print) 7840 BLOGI(sc, "Parity errors detected in blocks: "); 7841 7842 par_num = 7843 bxe_check_blocks_with_parity0(sc, sig[0] & 7844 HW_PRTY_ASSERT_SET_0, 7845 par_num, print); 7846 par_num = 7847 bxe_check_blocks_with_parity1(sc, sig[1] & 7848 HW_PRTY_ASSERT_SET_1, 7849 par_num, global, print); 7850 par_num = 7851 bxe_check_blocks_with_parity2(sc, sig[2] & 7852 HW_PRTY_ASSERT_SET_2, 7853 par_num, print); 7854 par_num = 7855 bxe_check_blocks_with_parity3(sc, sig[3] & 7856 HW_PRTY_ASSERT_SET_3, 7857 par_num, global, print); 7858 par_num = 7859 bxe_check_blocks_with_parity4(sc, sig[4] & 7860 HW_PRTY_ASSERT_SET_4, 7861 par_num, print); 7862 7863 if (print) 7864 BLOGI(sc, "\n"); 7865 7866 return (TRUE); 7867 } 7868 7869 return (FALSE); 7870 } 7871 7872 static uint8_t 7873 bxe_chk_parity_attn(struct bxe_softc *sc, 7874 uint8_t *global, 7875 uint8_t print) 7876 { 7877 struct attn_route attn = { {0} }; 7878 int port = SC_PORT(sc); 7879 7880 attn.sig[0] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4); 7881 attn.sig[1] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4); 7882 attn.sig[2] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4); 7883 attn.sig[3] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4); 7884 7885 if (!CHIP_IS_E1x(sc)) 7886 attn.sig[4] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4); 7887 7888 return (bxe_parity_attn(sc, global, print, attn.sig)); 7889 } 7890 7891 static void 7892 bxe_attn_int_deasserted4(struct bxe_softc *sc, 7893 uint32_t attn) 7894 { 7895 uint32_t val; 7896 7897 if (attn & AEU_INPUTS_ATTN_BITS_PGLUE_HW_INTERRUPT) { 7898 val = REG_RD(sc, PGLUE_B_REG_PGLUE_B_INT_STS_CLR); 7899 BLOGE(sc, "PGLUE hw attention 0x%08x\n", val); 7900 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR) 7901 BLOGE(sc, "PGLUE_B_PGLUE_B_INT_STS_REG_ADDRESS_ERROR\n"); 7902 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR) 7903 BLOGE(sc, "PGLUE_B_PGLUE_B_INT_STS_REG_INCORRECT_RCV_BEHAVIOR\n"); 7904 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) 7905 BLOGE(sc, "PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN\n"); 7906 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN) 7907 BLOGE(sc, "PGLUE_B_PGLUE_B_INT_STS_REG_VF_LENGTH_VIOLATION_ATTN\n"); 7908 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN) 7909 BLOGE(sc, "PGLUE_B_PGLUE_B_INT_STS_REG_VF_GRC_SPACE_VIOLATION_ATTN\n"); 7910 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN) 7911 BLOGE(sc, "PGLUE_B_PGLUE_B_INT_STS_REG_VF_MSIX_BAR_VIOLATION_ATTN\n"); 7912 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN) 7913 BLOGE(sc, "PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_ERROR_ATTN\n"); 7914 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN) 7915 BLOGE(sc, "PGLUE_B_PGLUE_B_INT_STS_REG_TCPL_IN_TWO_RCBS_ATTN\n"); 7916 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW) 7917 BLOGE(sc, "PGLUE_B_PGLUE_B_INT_STS_REG_CSSNOOP_FIFO_OVERFLOW\n"); 7918 } 7919 7920 if (attn & AEU_INPUTS_ATTN_BITS_ATC_HW_INTERRUPT) { 7921 val = REG_RD(sc, ATC_REG_ATC_INT_STS_CLR); 7922 BLOGE(sc, "ATC hw attention 0x%08x\n", val); 7923 if (val & ATC_ATC_INT_STS_REG_ADDRESS_ERROR) 7924 BLOGE(sc, "ATC_ATC_INT_STS_REG_ADDRESS_ERROR\n"); 7925 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND) 7926 BLOGE(sc, "ATC_ATC_INT_STS_REG_ATC_TCPL_TO_NOT_PEND\n"); 7927 if (val & ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS) 7928 BLOGE(sc, "ATC_ATC_INT_STS_REG_ATC_GPA_MULTIPLE_HITS\n"); 7929 if (val & ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT) 7930 BLOGE(sc, "ATC_ATC_INT_STS_REG_ATC_RCPL_TO_EMPTY_CNT\n"); 7931 if (val & ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR) 7932 BLOGE(sc, "ATC_ATC_INT_STS_REG_ATC_TCPL_ERROR\n"); 7933 if (val & ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU) 7934 BLOGE(sc, "ATC_ATC_INT_STS_REG_ATC_IREQ_LESS_THAN_STU\n"); 7935 } 7936 7937 if (attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | 7938 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR)) { 7939 BLOGE(sc, "FATAL parity attention set4 0x%08x\n", 7940 (uint32_t)(attn & (AEU_INPUTS_ATTN_BITS_PGLUE_PARITY_ERROR | 7941 AEU_INPUTS_ATTN_BITS_ATC_PARITY_ERROR))); 7942 } 7943 } 7944 7945 static void 7946 bxe_e1h_disable(struct bxe_softc *sc) 7947 { 7948 int port = SC_PORT(sc); 7949 7950 bxe_tx_disable(sc); 7951 7952 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port*8, 0); 7953 } 7954 7955 static void 7956 bxe_e1h_enable(struct bxe_softc *sc) 7957 { 7958 int port = SC_PORT(sc); 7959 7960 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port*8, 1); 7961 7962 // XXX bxe_tx_enable(sc); 7963 } 7964 7965 /* 7966 * called due to MCP event (on pmf): 7967 * reread new bandwidth configuration 7968 * configure FW 7969 * notify others function about the change 7970 */ 7971 static void 7972 bxe_config_mf_bw(struct bxe_softc *sc) 7973 { 7974 if (sc->link_vars.link_up) { 7975 bxe_cmng_fns_init(sc, TRUE, CMNG_FNS_MINMAX); 7976 // XXX bxe_link_sync_notify(sc); 7977 } 7978 7979 storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc)); 7980 } 7981 7982 static void 7983 bxe_set_mf_bw(struct bxe_softc *sc) 7984 { 7985 bxe_config_mf_bw(sc); 7986 bxe_fw_command(sc, DRV_MSG_CODE_SET_MF_BW_ACK, 0); 7987 } 7988 7989 static void 7990 bxe_handle_eee_event(struct bxe_softc *sc) 7991 { 7992 BLOGD(sc, DBG_INTR, "EEE - LLDP event\n"); 7993 bxe_fw_command(sc, DRV_MSG_CODE_EEE_RESULTS_ACK, 0); 7994 } 7995 7996 #define DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED 3 7997 7998 static void 7999 bxe_drv_info_ether_stat(struct bxe_softc *sc) 8000 { 8001 struct eth_stats_info *ether_stat = 8002 &sc->sp->drv_info_to_mcp.ether_stat; 8003 8004 strlcpy(ether_stat->version, BXE_DRIVER_VERSION, 8005 ETH_STAT_INFO_VERSION_LEN); 8006 8007 /* XXX (+ MAC_PAD) taken from other driver... verify this is right */ 8008 sc->sp_objs[0].mac_obj.get_n_elements(sc, &sc->sp_objs[0].mac_obj, 8009 DRV_INFO_ETH_STAT_NUM_MACS_REQUIRED, 8010 ether_stat->mac_local + MAC_PAD, 8011 MAC_PAD, ETH_ALEN); 8012 8013 ether_stat->mtu_size = sc->mtu; 8014 8015 ether_stat->feature_flags |= FEATURE_ETH_CHKSUM_OFFLOAD_MASK; 8016 if (sc->ifnet->if_capenable & (IFCAP_TSO4 | IFCAP_TSO6)) { 8017 ether_stat->feature_flags |= FEATURE_ETH_LSO_MASK; 8018 } 8019 8020 // XXX ether_stat->feature_flags |= ???; 8021 8022 ether_stat->promiscuous_mode = 0; // (flags & PROMISC) ? 1 : 0; 8023 8024 ether_stat->txq_size = sc->tx_ring_size; 8025 ether_stat->rxq_size = sc->rx_ring_size; 8026 } 8027 8028 static void 8029 bxe_handle_drv_info_req(struct bxe_softc *sc) 8030 { 8031 enum drv_info_opcode op_code; 8032 uint32_t drv_info_ctl = SHMEM2_RD(sc, drv_info_control); 8033 8034 /* if drv_info version supported by MFW doesn't match - send NACK */ 8035 if ((drv_info_ctl & DRV_INFO_CONTROL_VER_MASK) != DRV_INFO_CUR_VER) { 8036 bxe_fw_command(sc, DRV_MSG_CODE_DRV_INFO_NACK, 0); 8037 return; 8038 } 8039 8040 op_code = ((drv_info_ctl & DRV_INFO_CONTROL_OP_CODE_MASK) >> 8041 DRV_INFO_CONTROL_OP_CODE_SHIFT); 8042 8043 memset(&sc->sp->drv_info_to_mcp, 0, sizeof(union drv_info_to_mcp)); 8044 8045 switch (op_code) { 8046 case ETH_STATS_OPCODE: 8047 bxe_drv_info_ether_stat(sc); 8048 break; 8049 case FCOE_STATS_OPCODE: 8050 case ISCSI_STATS_OPCODE: 8051 default: 8052 /* if op code isn't supported - send NACK */ 8053 bxe_fw_command(sc, DRV_MSG_CODE_DRV_INFO_NACK, 0); 8054 return; 8055 } 8056 8057 /* 8058 * If we got drv_info attn from MFW then these fields are defined in 8059 * shmem2 for sure 8060 */ 8061 SHMEM2_WR(sc, drv_info_host_addr_lo, 8062 U64_LO(BXE_SP_MAPPING(sc, drv_info_to_mcp))); 8063 SHMEM2_WR(sc, drv_info_host_addr_hi, 8064 U64_HI(BXE_SP_MAPPING(sc, drv_info_to_mcp))); 8065 8066 bxe_fw_command(sc, DRV_MSG_CODE_DRV_INFO_ACK, 0); 8067 } 8068 8069 static void 8070 bxe_dcc_event(struct bxe_softc *sc, 8071 uint32_t dcc_event) 8072 { 8073 BLOGD(sc, DBG_INTR, "dcc_event 0x%08x\n", dcc_event); 8074 8075 if (dcc_event & DRV_STATUS_DCC_DISABLE_ENABLE_PF) { 8076 /* 8077 * This is the only place besides the function initialization 8078 * where the sc->flags can change so it is done without any 8079 * locks 8080 */ 8081 if (sc->devinfo.mf_info.mf_config[SC_VN(sc)] & FUNC_MF_CFG_FUNC_DISABLED) { 8082 BLOGD(sc, DBG_INTR, "mf_cfg function disabled\n"); 8083 sc->flags |= BXE_MF_FUNC_DIS; 8084 bxe_e1h_disable(sc); 8085 } else { 8086 BLOGD(sc, DBG_INTR, "mf_cfg function enabled\n"); 8087 sc->flags &= ~BXE_MF_FUNC_DIS; 8088 bxe_e1h_enable(sc); 8089 } 8090 dcc_event &= ~DRV_STATUS_DCC_DISABLE_ENABLE_PF; 8091 } 8092 8093 if (dcc_event & DRV_STATUS_DCC_BANDWIDTH_ALLOCATION) { 8094 bxe_config_mf_bw(sc); 8095 dcc_event &= ~DRV_STATUS_DCC_BANDWIDTH_ALLOCATION; 8096 } 8097 8098 /* Report results to MCP */ 8099 if (dcc_event) 8100 bxe_fw_command(sc, DRV_MSG_CODE_DCC_FAILURE, 0); 8101 else 8102 bxe_fw_command(sc, DRV_MSG_CODE_DCC_OK, 0); 8103 } 8104 8105 static void 8106 bxe_pmf_update(struct bxe_softc *sc) 8107 { 8108 int port = SC_PORT(sc); 8109 uint32_t val; 8110 8111 sc->port.pmf = 1; 8112 BLOGD(sc, DBG_INTR, "pmf %d\n", sc->port.pmf); 8113 8114 /* 8115 * We need the mb() to ensure the ordering between the writing to 8116 * sc->port.pmf here and reading it from the bxe_periodic_task(). 8117 */ 8118 mb(); 8119 8120 /* queue a periodic task */ 8121 // XXX schedule task... 8122 8123 // XXX bxe_dcbx_pmf_update(sc); 8124 8125 /* enable nig attention */ 8126 val = (0xff0f | (1 << (SC_VN(sc) + 4))); 8127 if (sc->devinfo.int_block == INT_BLOCK_HC) { 8128 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port*8, val); 8129 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port*8, val); 8130 } else if (!CHIP_IS_E1x(sc)) { 8131 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, val); 8132 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, val); 8133 } 8134 8135 bxe_stats_handle(sc, STATS_EVENT_PMF); 8136 } 8137 8138 static int 8139 bxe_mc_assert(struct bxe_softc *sc) 8140 { 8141 char last_idx; 8142 int i, rc = 0; 8143 uint32_t row0, row1, row2, row3; 8144 8145 /* XSTORM */ 8146 last_idx = REG_RD8(sc, BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_INDEX_OFFSET); 8147 if (last_idx) 8148 BLOGE(sc, "XSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); 8149 8150 /* print the asserts */ 8151 for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) { 8152 8153 row0 = REG_RD(sc, BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i)); 8154 row1 = REG_RD(sc, BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) + 4); 8155 row2 = REG_RD(sc, BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) + 8); 8156 row3 = REG_RD(sc, BAR_XSTRORM_INTMEM + XSTORM_ASSERT_LIST_OFFSET(i) + 12); 8157 8158 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { 8159 BLOGE(sc, "XSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n", 8160 i, row3, row2, row1, row0); 8161 rc++; 8162 } else { 8163 break; 8164 } 8165 } 8166 8167 /* TSTORM */ 8168 last_idx = REG_RD8(sc, BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_INDEX_OFFSET); 8169 if (last_idx) { 8170 BLOGE(sc, "TSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); 8171 } 8172 8173 /* print the asserts */ 8174 for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) { 8175 8176 row0 = REG_RD(sc, BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i)); 8177 row1 = REG_RD(sc, BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) + 4); 8178 row2 = REG_RD(sc, BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) + 8); 8179 row3 = REG_RD(sc, BAR_TSTRORM_INTMEM + TSTORM_ASSERT_LIST_OFFSET(i) + 12); 8180 8181 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { 8182 BLOGE(sc, "TSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n", 8183 i, row3, row2, row1, row0); 8184 rc++; 8185 } else { 8186 break; 8187 } 8188 } 8189 8190 /* CSTORM */ 8191 last_idx = REG_RD8(sc, BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_INDEX_OFFSET); 8192 if (last_idx) { 8193 BLOGE(sc, "CSTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); 8194 } 8195 8196 /* print the asserts */ 8197 for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) { 8198 8199 row0 = REG_RD(sc, BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i)); 8200 row1 = REG_RD(sc, BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) + 4); 8201 row2 = REG_RD(sc, BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) + 8); 8202 row3 = REG_RD(sc, BAR_CSTRORM_INTMEM + CSTORM_ASSERT_LIST_OFFSET(i) + 12); 8203 8204 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { 8205 BLOGE(sc, "CSTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n", 8206 i, row3, row2, row1, row0); 8207 rc++; 8208 } else { 8209 break; 8210 } 8211 } 8212 8213 /* USTORM */ 8214 last_idx = REG_RD8(sc, BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_INDEX_OFFSET); 8215 if (last_idx) { 8216 BLOGE(sc, "USTORM_ASSERT_LIST_INDEX 0x%x\n", last_idx); 8217 } 8218 8219 /* print the asserts */ 8220 for (i = 0; i < STORM_ASSERT_ARRAY_SIZE; i++) { 8221 8222 row0 = REG_RD(sc, BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i)); 8223 row1 = REG_RD(sc, BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) + 4); 8224 row2 = REG_RD(sc, BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) + 8); 8225 row3 = REG_RD(sc, BAR_USTRORM_INTMEM + USTORM_ASSERT_LIST_OFFSET(i) + 12); 8226 8227 if (row0 != COMMON_ASM_INVALID_ASSERT_OPCODE) { 8228 BLOGE(sc, "USTORM_ASSERT_INDEX 0x%x = 0x%08x 0x%08x 0x%08x 0x%08x\n", 8229 i, row3, row2, row1, row0); 8230 rc++; 8231 } else { 8232 break; 8233 } 8234 } 8235 8236 return (rc); 8237 } 8238 8239 static void 8240 bxe_attn_int_deasserted3(struct bxe_softc *sc, 8241 uint32_t attn) 8242 { 8243 int func = SC_FUNC(sc); 8244 uint32_t val; 8245 8246 if (attn & EVEREST_GEN_ATTN_IN_USE_MASK) { 8247 8248 if (attn & BXE_PMF_LINK_ASSERT(sc)) { 8249 8250 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); 8251 bxe_read_mf_cfg(sc); 8252 sc->devinfo.mf_info.mf_config[SC_VN(sc)] = 8253 MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].config); 8254 val = SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_status); 8255 8256 if (val & DRV_STATUS_DCC_EVENT_MASK) 8257 bxe_dcc_event(sc, (val & DRV_STATUS_DCC_EVENT_MASK)); 8258 8259 if (val & DRV_STATUS_SET_MF_BW) 8260 bxe_set_mf_bw(sc); 8261 8262 if (val & DRV_STATUS_DRV_INFO_REQ) 8263 bxe_handle_drv_info_req(sc); 8264 8265 #if 0 8266 if (val & DRV_STATUS_VF_DISABLED) 8267 bxe_vf_handle_flr_event(sc); 8268 #endif 8269 8270 if ((sc->port.pmf == 0) && (val & DRV_STATUS_PMF)) 8271 bxe_pmf_update(sc); 8272 8273 #if 0 8274 if (sc->port.pmf && 8275 (val & DRV_STATUS_DCBX_NEGOTIATION_RESULTS) && 8276 (sc->dcbx_enabled > 0)) 8277 /* start dcbx state machine */ 8278 bxe_dcbx_set_params(sc, BXE_DCBX_STATE_NEG_RECEIVED); 8279 #endif 8280 8281 #if 0 8282 if (val & DRV_STATUS_AFEX_EVENT_MASK) 8283 bxe_handle_afex_cmd(sc, val & DRV_STATUS_AFEX_EVENT_MASK); 8284 #endif 8285 8286 if (val & DRV_STATUS_EEE_NEGOTIATION_RESULTS) 8287 bxe_handle_eee_event(sc); 8288 8289 if (sc->link_vars.periodic_flags & 8290 ELINK_PERIODIC_FLAGS_LINK_EVENT) { 8291 /* sync with link */ 8292 BXE_PHY_LOCK(sc); 8293 sc->link_vars.periodic_flags &= 8294 ~ELINK_PERIODIC_FLAGS_LINK_EVENT; 8295 BXE_PHY_UNLOCK(sc); 8296 if (IS_MF(sc)) 8297 ; // XXX bxe_link_sync_notify(sc); 8298 bxe_link_report(sc); 8299 } 8300 8301 /* 8302 * Always call it here: bxe_link_report() will 8303 * prevent the link indication duplication. 8304 */ 8305 bxe_link_status_update(sc); 8306 8307 } else if (attn & BXE_MC_ASSERT_BITS) { 8308 8309 BLOGE(sc, "MC assert!\n"); 8310 bxe_mc_assert(sc); 8311 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_10, 0); 8312 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_9, 0); 8313 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_8, 0); 8314 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_7, 0); 8315 bxe_panic(sc, ("MC assert!\n")); 8316 8317 } else if (attn & BXE_MCP_ASSERT) { 8318 8319 BLOGE(sc, "MCP assert!\n"); 8320 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_11, 0); 8321 // XXX bxe_fw_dump(sc); 8322 8323 } else { 8324 BLOGE(sc, "Unknown HW assert! (attn 0x%08x)\n", attn); 8325 } 8326 } 8327 8328 if (attn & EVEREST_LATCHED_ATTN_IN_USE_MASK) { 8329 BLOGE(sc, "LATCHED attention 0x%08x (masked)\n", attn); 8330 if (attn & BXE_GRC_TIMEOUT) { 8331 val = CHIP_IS_E1(sc) ? 0 : REG_RD(sc, MISC_REG_GRC_TIMEOUT_ATTN); 8332 BLOGE(sc, "GRC time-out 0x%08x\n", val); 8333 } 8334 if (attn & BXE_GRC_RSV) { 8335 val = CHIP_IS_E1(sc) ? 0 : REG_RD(sc, MISC_REG_GRC_RSV_ATTN); 8336 BLOGE(sc, "GRC reserved 0x%08x\n", val); 8337 } 8338 REG_WR(sc, MISC_REG_AEU_CLR_LATCH_SIGNAL, 0x7ff); 8339 } 8340 } 8341 8342 static void 8343 bxe_attn_int_deasserted2(struct bxe_softc *sc, 8344 uint32_t attn) 8345 { 8346 int port = SC_PORT(sc); 8347 int reg_offset; 8348 uint32_t val0, mask0, val1, mask1; 8349 uint32_t val; 8350 8351 if (attn & AEU_INPUTS_ATTN_BITS_CFC_HW_INTERRUPT) { 8352 val = REG_RD(sc, CFC_REG_CFC_INT_STS_CLR); 8353 BLOGE(sc, "CFC hw attention 0x%08x\n", val); 8354 /* CFC error attention */ 8355 if (val & 0x2) { 8356 BLOGE(sc, "FATAL error from CFC\n"); 8357 } 8358 } 8359 8360 if (attn & AEU_INPUTS_ATTN_BITS_PXP_HW_INTERRUPT) { 8361 val = REG_RD(sc, PXP_REG_PXP_INT_STS_CLR_0); 8362 BLOGE(sc, "PXP hw attention-0 0x%08x\n", val); 8363 /* RQ_USDMDP_FIFO_OVERFLOW */ 8364 if (val & 0x18000) { 8365 BLOGE(sc, "FATAL error from PXP\n"); 8366 } 8367 8368 if (!CHIP_IS_E1x(sc)) { 8369 val = REG_RD(sc, PXP_REG_PXP_INT_STS_CLR_1); 8370 BLOGE(sc, "PXP hw attention-1 0x%08x\n", val); 8371 } 8372 } 8373 8374 #define PXP2_EOP_ERROR_BIT PXP2_PXP2_INT_STS_CLR_0_REG_WR_PGLUE_EOP_ERROR 8375 #define AEU_PXP2_HW_INT_BIT AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_HW_INTERRUPT 8376 8377 if (attn & AEU_PXP2_HW_INT_BIT) { 8378 /* CQ47854 workaround do not panic on 8379 * PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR 8380 */ 8381 if (!CHIP_IS_E1x(sc)) { 8382 mask0 = REG_RD(sc, PXP2_REG_PXP2_INT_MASK_0); 8383 val1 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_1); 8384 mask1 = REG_RD(sc, PXP2_REG_PXP2_INT_MASK_1); 8385 val0 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_0); 8386 /* 8387 * If the olny PXP2_EOP_ERROR_BIT is set in 8388 * STS0 and STS1 - clear it 8389 * 8390 * probably we lose additional attentions between 8391 * STS0 and STS_CLR0, in this case user will not 8392 * be notified about them 8393 */ 8394 if (val0 & mask0 & PXP2_EOP_ERROR_BIT && 8395 !(val1 & mask1)) 8396 val0 = REG_RD(sc, PXP2_REG_PXP2_INT_STS_CLR_0); 8397 8398 /* print the register, since no one can restore it */ 8399 BLOGE(sc, "PXP2_REG_PXP2_INT_STS_CLR_0 0x%08x\n", val0); 8400 8401 /* 8402 * if PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR 8403 * then notify 8404 */ 8405 if (val0 & PXP2_EOP_ERROR_BIT) { 8406 BLOGE(sc, "PXP2_WR_PGLUE_EOP_ERROR\n"); 8407 8408 /* 8409 * if only PXP2_PXP2_INT_STS_0_REG_WR_PGLUE_EOP_ERROR is 8410 * set then clear attention from PXP2 block without panic 8411 */ 8412 if (((val0 & mask0) == PXP2_EOP_ERROR_BIT) && 8413 ((val1 & mask1) == 0)) 8414 attn &= ~AEU_PXP2_HW_INT_BIT; 8415 } 8416 } 8417 } 8418 8419 if (attn & HW_INTERRUT_ASSERT_SET_2) { 8420 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_2 : 8421 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_2); 8422 8423 val = REG_RD(sc, reg_offset); 8424 val &= ~(attn & HW_INTERRUT_ASSERT_SET_2); 8425 REG_WR(sc, reg_offset, val); 8426 8427 BLOGE(sc, "FATAL HW block attention set2 0x%x\n", 8428 (uint32_t)(attn & HW_INTERRUT_ASSERT_SET_2)); 8429 bxe_panic(sc, ("HW block attention set2\n")); 8430 } 8431 } 8432 8433 static void 8434 bxe_attn_int_deasserted1(struct bxe_softc *sc, 8435 uint32_t attn) 8436 { 8437 int port = SC_PORT(sc); 8438 int reg_offset; 8439 uint32_t val; 8440 8441 if (attn & AEU_INPUTS_ATTN_BITS_DOORBELLQ_HW_INTERRUPT) { 8442 val = REG_RD(sc, DORQ_REG_DORQ_INT_STS_CLR); 8443 BLOGE(sc, "DB hw attention 0x%08x\n", val); 8444 /* DORQ discard attention */ 8445 if (val & 0x2) { 8446 BLOGE(sc, "FATAL error from DORQ\n"); 8447 } 8448 } 8449 8450 if (attn & HW_INTERRUT_ASSERT_SET_1) { 8451 reg_offset = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_1 : 8452 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_1); 8453 8454 val = REG_RD(sc, reg_offset); 8455 val &= ~(attn & HW_INTERRUT_ASSERT_SET_1); 8456 REG_WR(sc, reg_offset, val); 8457 8458 BLOGE(sc, "FATAL HW block attention set1 0x%08x\n", 8459 (uint32_t)(attn & HW_INTERRUT_ASSERT_SET_1)); 8460 bxe_panic(sc, ("HW block attention set1\n")); 8461 } 8462 } 8463 8464 static void 8465 bxe_attn_int_deasserted0(struct bxe_softc *sc, 8466 uint32_t attn) 8467 { 8468 int port = SC_PORT(sc); 8469 int reg_offset; 8470 uint32_t val; 8471 8472 reg_offset = (port) ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : 8473 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0; 8474 8475 if (attn & AEU_INPUTS_ATTN_BITS_SPIO5) { 8476 val = REG_RD(sc, reg_offset); 8477 val &= ~AEU_INPUTS_ATTN_BITS_SPIO5; 8478 REG_WR(sc, reg_offset, val); 8479 8480 BLOGW(sc, "SPIO5 hw attention\n"); 8481 8482 /* Fan failure attention */ 8483 elink_hw_reset_phy(&sc->link_params); 8484 bxe_fan_failure(sc); 8485 } 8486 8487 if ((attn & sc->link_vars.aeu_int_mask) && sc->port.pmf) { 8488 BXE_PHY_LOCK(sc); 8489 elink_handle_module_detect_int(&sc->link_params); 8490 BXE_PHY_UNLOCK(sc); 8491 } 8492 8493 if (attn & HW_INTERRUT_ASSERT_SET_0) { 8494 val = REG_RD(sc, reg_offset); 8495 val &= ~(attn & HW_INTERRUT_ASSERT_SET_0); 8496 REG_WR(sc, reg_offset, val); 8497 8498 bxe_panic(sc, ("FATAL HW block attention set0 0x%lx\n", 8499 (attn & HW_INTERRUT_ASSERT_SET_0))); 8500 } 8501 } 8502 8503 static void 8504 bxe_attn_int_deasserted(struct bxe_softc *sc, 8505 uint32_t deasserted) 8506 { 8507 struct attn_route attn; 8508 struct attn_route *group_mask; 8509 int port = SC_PORT(sc); 8510 int index; 8511 uint32_t reg_addr; 8512 uint32_t val; 8513 uint32_t aeu_mask; 8514 uint8_t global = FALSE; 8515 8516 /* 8517 * Need to take HW lock because MCP or other port might also 8518 * try to handle this event. 8519 */ 8520 bxe_acquire_alr(sc); 8521 8522 if (bxe_chk_parity_attn(sc, &global, TRUE)) { 8523 /* XXX 8524 * In case of parity errors don't handle attentions so that 8525 * other function would "see" parity errors. 8526 */ 8527 sc->recovery_state = BXE_RECOVERY_INIT; 8528 // XXX schedule a recovery task... 8529 /* disable HW interrupts */ 8530 bxe_int_disable(sc); 8531 bxe_release_alr(sc); 8532 return; 8533 } 8534 8535 attn.sig[0] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + port*4); 8536 attn.sig[1] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_2_FUNC_0 + port*4); 8537 attn.sig[2] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_3_FUNC_0 + port*4); 8538 attn.sig[3] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_4_FUNC_0 + port*4); 8539 if (!CHIP_IS_E1x(sc)) { 8540 attn.sig[4] = REG_RD(sc, MISC_REG_AEU_AFTER_INVERT_5_FUNC_0 + port*4); 8541 } else { 8542 attn.sig[4] = 0; 8543 } 8544 8545 BLOGD(sc, DBG_INTR, "attn: 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n", 8546 attn.sig[0], attn.sig[1], attn.sig[2], attn.sig[3], attn.sig[4]); 8547 8548 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) { 8549 if (deasserted & (1 << index)) { 8550 group_mask = &sc->attn_group[index]; 8551 8552 BLOGD(sc, DBG_INTR, 8553 "group[%d]: 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n", index, 8554 group_mask->sig[0], group_mask->sig[1], 8555 group_mask->sig[2], group_mask->sig[3], 8556 group_mask->sig[4]); 8557 8558 bxe_attn_int_deasserted4(sc, attn.sig[4] & group_mask->sig[4]); 8559 bxe_attn_int_deasserted3(sc, attn.sig[3] & group_mask->sig[3]); 8560 bxe_attn_int_deasserted1(sc, attn.sig[1] & group_mask->sig[1]); 8561 bxe_attn_int_deasserted2(sc, attn.sig[2] & group_mask->sig[2]); 8562 bxe_attn_int_deasserted0(sc, attn.sig[0] & group_mask->sig[0]); 8563 } 8564 } 8565 8566 bxe_release_alr(sc); 8567 8568 if (sc->devinfo.int_block == INT_BLOCK_HC) { 8569 reg_addr = (HC_REG_COMMAND_REG + port*32 + 8570 COMMAND_REG_ATTN_BITS_CLR); 8571 } else { 8572 reg_addr = (BAR_IGU_INTMEM + IGU_CMD_ATTN_BIT_CLR_UPPER*8); 8573 } 8574 8575 val = ~deasserted; 8576 BLOGD(sc, DBG_INTR, 8577 "about to mask 0x%08x at %s addr 0x%08x\n", val, 8578 (sc->devinfo.int_block == INT_BLOCK_HC) ? "HC" : "IGU", reg_addr); 8579 REG_WR(sc, reg_addr, val); 8580 8581 if (~sc->attn_state & deasserted) { 8582 BLOGE(sc, "IGU error\n"); 8583 } 8584 8585 reg_addr = port ? MISC_REG_AEU_MASK_ATTN_FUNC_1 : 8586 MISC_REG_AEU_MASK_ATTN_FUNC_0; 8587 8588 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); 8589 8590 aeu_mask = REG_RD(sc, reg_addr); 8591 8592 BLOGD(sc, DBG_INTR, "aeu_mask 0x%08x newly deasserted 0x%08x\n", 8593 aeu_mask, deasserted); 8594 aeu_mask |= (deasserted & 0x3ff); 8595 BLOGD(sc, DBG_INTR, "new mask 0x%08x\n", aeu_mask); 8596 8597 REG_WR(sc, reg_addr, aeu_mask); 8598 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_PORT0_ATT_MASK + port); 8599 8600 BLOGD(sc, DBG_INTR, "attn_state 0x%08x\n", sc->attn_state); 8601 sc->attn_state &= ~deasserted; 8602 BLOGD(sc, DBG_INTR, "new state 0x%08x\n", sc->attn_state); 8603 } 8604 8605 static void 8606 bxe_attn_int(struct bxe_softc *sc) 8607 { 8608 /* read local copy of bits */ 8609 uint32_t attn_bits = le32toh(sc->def_sb->atten_status_block.attn_bits); 8610 uint32_t attn_ack = le32toh(sc->def_sb->atten_status_block.attn_bits_ack); 8611 uint32_t attn_state = sc->attn_state; 8612 8613 /* look for changed bits */ 8614 uint32_t asserted = attn_bits & ~attn_ack & ~attn_state; 8615 uint32_t deasserted = ~attn_bits & attn_ack & attn_state; 8616 8617 BLOGD(sc, DBG_INTR, 8618 "attn_bits 0x%08x attn_ack 0x%08x asserted 0x%08x deasserted 0x%08x\n", 8619 attn_bits, attn_ack, asserted, deasserted); 8620 8621 if (~(attn_bits ^ attn_ack) & (attn_bits ^ attn_state)) { 8622 BLOGE(sc, "BAD attention state\n"); 8623 } 8624 8625 /* handle bits that were raised */ 8626 if (asserted) { 8627 bxe_attn_int_asserted(sc, asserted); 8628 } 8629 8630 if (deasserted) { 8631 bxe_attn_int_deasserted(sc, deasserted); 8632 } 8633 } 8634 8635 static uint16_t 8636 bxe_update_dsb_idx(struct bxe_softc *sc) 8637 { 8638 struct host_sp_status_block *def_sb = sc->def_sb; 8639 uint16_t rc = 0; 8640 8641 mb(); /* status block is written to by the chip */ 8642 8643 if (sc->def_att_idx != def_sb->atten_status_block.attn_bits_index) { 8644 sc->def_att_idx = def_sb->atten_status_block.attn_bits_index; 8645 rc |= BXE_DEF_SB_ATT_IDX; 8646 } 8647 8648 if (sc->def_idx != def_sb->sp_sb.running_index) { 8649 sc->def_idx = def_sb->sp_sb.running_index; 8650 rc |= BXE_DEF_SB_IDX; 8651 } 8652 8653 mb(); 8654 8655 return (rc); 8656 } 8657 8658 static inline struct ecore_queue_sp_obj * 8659 bxe_cid_to_q_obj(struct bxe_softc *sc, 8660 uint32_t cid) 8661 { 8662 BLOGD(sc, DBG_SP, "retrieving fp from cid %d\n", cid); 8663 return (&sc->sp_objs[CID_TO_FP(cid, sc)].q_obj); 8664 } 8665 8666 static void 8667 bxe_handle_mcast_eqe(struct bxe_softc *sc) 8668 { 8669 struct ecore_mcast_ramrod_params rparam; 8670 int rc; 8671 8672 memset(&rparam, 0, sizeof(rparam)); 8673 8674 rparam.mcast_obj = &sc->mcast_obj; 8675 8676 BXE_MCAST_LOCK(sc); 8677 8678 /* clear pending state for the last command */ 8679 sc->mcast_obj.raw.clear_pending(&sc->mcast_obj.raw); 8680 8681 /* if there are pending mcast commands - send them */ 8682 if (sc->mcast_obj.check_pending(&sc->mcast_obj)) { 8683 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_CONT); 8684 if (rc < 0) { 8685 BLOGD(sc, DBG_SP, 8686 "ERROR: Failed to send pending mcast commands (%d)\n", 8687 rc); 8688 } 8689 } 8690 8691 BXE_MCAST_UNLOCK(sc); 8692 } 8693 8694 static void 8695 bxe_handle_classification_eqe(struct bxe_softc *sc, 8696 union event_ring_elem *elem) 8697 { 8698 unsigned long ramrod_flags = 0; 8699 int rc = 0; 8700 uint32_t cid = elem->message.data.eth_event.echo & BXE_SWCID_MASK; 8701 struct ecore_vlan_mac_obj *vlan_mac_obj; 8702 8703 /* always push next commands out, don't wait here */ 8704 bit_set(&ramrod_flags, RAMROD_CONT); 8705 8706 switch (le32toh(elem->message.data.eth_event.echo) >> BXE_SWCID_SHIFT) { 8707 case ECORE_FILTER_MAC_PENDING: 8708 BLOGD(sc, DBG_SP, "Got SETUP_MAC completions\n"); 8709 vlan_mac_obj = &sc->sp_objs[cid].mac_obj; 8710 break; 8711 8712 case ECORE_FILTER_MCAST_PENDING: 8713 BLOGD(sc, DBG_SP, "Got SETUP_MCAST completions\n"); 8714 /* 8715 * This is only relevant for 57710 where multicast MACs are 8716 * configured as unicast MACs using the same ramrod. 8717 */ 8718 bxe_handle_mcast_eqe(sc); 8719 return; 8720 8721 default: 8722 BLOGE(sc, "Unsupported classification command: %d\n", 8723 elem->message.data.eth_event.echo); 8724 return; 8725 } 8726 8727 rc = vlan_mac_obj->complete(sc, vlan_mac_obj, elem, &ramrod_flags); 8728 8729 if (rc < 0) { 8730 BLOGE(sc, "Failed to schedule new commands (%d)\n", rc); 8731 } else if (rc > 0) { 8732 BLOGD(sc, DBG_SP, "Scheduled next pending commands...\n"); 8733 } 8734 } 8735 8736 static void 8737 bxe_handle_rx_mode_eqe(struct bxe_softc *sc, 8738 union event_ring_elem *elem) 8739 { 8740 bxe_clear_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state); 8741 8742 /* send rx_mode command again if was requested */ 8743 if (bxe_test_and_clear_bit(ECORE_FILTER_RX_MODE_SCHED, 8744 &sc->sp_state)) { 8745 bxe_set_storm_rx_mode(sc); 8746 } 8747 #if 0 8748 else if (bxe_test_and_clear_bit(ECORE_FILTER_ISCSI_ETH_START_SCHED, 8749 &sc->sp_state)) { 8750 bxe_set_iscsi_eth_rx_mode(sc, TRUE); 8751 } 8752 else if (bxe_test_and_clear_bit(ECORE_FILTER_ISCSI_ETH_STOP_SCHED, 8753 &sc->sp_state)) { 8754 bxe_set_iscsi_eth_rx_mode(sc, FALSE); 8755 } 8756 #endif 8757 } 8758 8759 static void 8760 bxe_update_eq_prod(struct bxe_softc *sc, 8761 uint16_t prod) 8762 { 8763 storm_memset_eq_prod(sc, prod, SC_FUNC(sc)); 8764 wmb(); /* keep prod updates ordered */ 8765 } 8766 8767 static void 8768 bxe_eq_int(struct bxe_softc *sc) 8769 { 8770 uint16_t hw_cons, sw_cons, sw_prod; 8771 union event_ring_elem *elem; 8772 uint8_t echo; 8773 uint32_t cid; 8774 uint8_t opcode; 8775 int spqe_cnt = 0; 8776 struct ecore_queue_sp_obj *q_obj; 8777 struct ecore_func_sp_obj *f_obj = &sc->func_obj; 8778 struct ecore_raw_obj *rss_raw = &sc->rss_conf_obj.raw; 8779 8780 hw_cons = le16toh(*sc->eq_cons_sb); 8781 8782 /* 8783 * The hw_cons range is 1-255, 257 - the sw_cons range is 0-254, 256. 8784 * when we get to the next-page we need to adjust so the loop 8785 * condition below will be met. The next element is the size of a 8786 * regular element and hence incrementing by 1 8787 */ 8788 if ((hw_cons & EQ_DESC_MAX_PAGE) == EQ_DESC_MAX_PAGE) { 8789 hw_cons++; 8790 } 8791 8792 /* 8793 * This function may never run in parallel with itself for a 8794 * specific sc and no need for a read memory barrier here. 8795 */ 8796 sw_cons = sc->eq_cons; 8797 sw_prod = sc->eq_prod; 8798 8799 BLOGD(sc, DBG_SP,"EQ: hw_cons=%u sw_cons=%u eq_spq_left=0x%lx\n", 8800 hw_cons, sw_cons, atomic_load_acq_long(&sc->eq_spq_left)); 8801 8802 for (; 8803 sw_cons != hw_cons; 8804 sw_prod = NEXT_EQ_IDX(sw_prod), sw_cons = NEXT_EQ_IDX(sw_cons)) { 8805 8806 elem = &sc->eq[EQ_DESC(sw_cons)]; 8807 8808 #if 0 8809 int rc; 8810 rc = bxe_iov_eq_sp_event(sc, elem); 8811 if (!rc) { 8812 BLOGE(sc, "bxe_iov_eq_sp_event returned %d\n", rc); 8813 goto next_spqe; 8814 } 8815 #endif 8816 8817 /* elem CID originates from FW, actually LE */ 8818 cid = SW_CID(elem->message.data.cfc_del_event.cid); 8819 opcode = elem->message.opcode; 8820 8821 /* handle eq element */ 8822 switch (opcode) { 8823 #if 0 8824 case EVENT_RING_OPCODE_VF_PF_CHANNEL: 8825 BLOGD(sc, DBG_SP, "vf/pf channel element on eq\n"); 8826 bxe_vf_mbx(sc, &elem->message.data.vf_pf_event); 8827 continue; 8828 #endif 8829 8830 case EVENT_RING_OPCODE_STAT_QUERY: 8831 BLOGD(sc, DBG_SP, "got statistics completion event %d\n", 8832 sc->stats_comp++); 8833 /* nothing to do with stats comp */ 8834 goto next_spqe; 8835 8836 case EVENT_RING_OPCODE_CFC_DEL: 8837 /* handle according to cid range */ 8838 /* we may want to verify here that the sc state is HALTING */ 8839 BLOGD(sc, DBG_SP, "got delete ramrod for MULTI[%d]\n", cid); 8840 q_obj = bxe_cid_to_q_obj(sc, cid); 8841 if (q_obj->complete_cmd(sc, q_obj, ECORE_Q_CMD_CFC_DEL)) { 8842 break; 8843 } 8844 goto next_spqe; 8845 8846 case EVENT_RING_OPCODE_STOP_TRAFFIC: 8847 BLOGD(sc, DBG_SP, "got STOP TRAFFIC\n"); 8848 if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_TX_STOP)) { 8849 break; 8850 } 8851 // XXX bxe_dcbx_set_params(sc, BXE_DCBX_STATE_TX_PAUSED); 8852 goto next_spqe; 8853 8854 case EVENT_RING_OPCODE_START_TRAFFIC: 8855 BLOGD(sc, DBG_SP, "got START TRAFFIC\n"); 8856 if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_TX_START)) { 8857 break; 8858 } 8859 // XXX bxe_dcbx_set_params(sc, BXE_DCBX_STATE_TX_RELEASED); 8860 goto next_spqe; 8861 8862 case EVENT_RING_OPCODE_FUNCTION_UPDATE: 8863 echo = elem->message.data.function_update_event.echo; 8864 if (echo == SWITCH_UPDATE) { 8865 BLOGD(sc, DBG_SP, "got FUNC_SWITCH_UPDATE ramrod\n"); 8866 if (f_obj->complete_cmd(sc, f_obj, 8867 ECORE_F_CMD_SWITCH_UPDATE)) { 8868 break; 8869 } 8870 } 8871 else { 8872 BLOGD(sc, DBG_SP, 8873 "AFEX: ramrod completed FUNCTION_UPDATE\n"); 8874 #if 0 8875 f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_AFEX_UPDATE); 8876 /* 8877 * We will perform the queues update from the sp_core_task as 8878 * all queue SP operations should run with CORE_LOCK. 8879 */ 8880 bxe_set_bit(BXE_SP_CORE_AFEX_F_UPDATE, &sc->sp_core_state); 8881 taskqueue_enqueue(sc->sp_tq, &sc->sp_tq_task); 8882 #endif 8883 } 8884 goto next_spqe; 8885 8886 #if 0 8887 case EVENT_RING_OPCODE_AFEX_VIF_LISTS: 8888 f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_AFEX_VIFLISTS); 8889 bxe_after_afex_vif_lists(sc, elem); 8890 goto next_spqe; 8891 #endif 8892 8893 case EVENT_RING_OPCODE_FORWARD_SETUP: 8894 q_obj = &bxe_fwd_sp_obj(sc, q_obj); 8895 if (q_obj->complete_cmd(sc, q_obj, 8896 ECORE_Q_CMD_SETUP_TX_ONLY)) { 8897 break; 8898 } 8899 goto next_spqe; 8900 8901 case EVENT_RING_OPCODE_FUNCTION_START: 8902 BLOGD(sc, DBG_SP, "got FUNC_START ramrod\n"); 8903 if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_START)) { 8904 break; 8905 } 8906 goto next_spqe; 8907 8908 case EVENT_RING_OPCODE_FUNCTION_STOP: 8909 BLOGD(sc, DBG_SP, "got FUNC_STOP ramrod\n"); 8910 if (f_obj->complete_cmd(sc, f_obj, ECORE_F_CMD_STOP)) { 8911 break; 8912 } 8913 goto next_spqe; 8914 } 8915 8916 switch (opcode | sc->state) { 8917 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | BXE_STATE_OPEN): 8918 case (EVENT_RING_OPCODE_RSS_UPDATE_RULES | BXE_STATE_OPENING_WAITING_PORT): 8919 cid = elem->message.data.eth_event.echo & BXE_SWCID_MASK; 8920 BLOGD(sc, DBG_SP, "got RSS_UPDATE ramrod. CID %d\n", cid); 8921 rss_raw->clear_pending(rss_raw); 8922 break; 8923 8924 case (EVENT_RING_OPCODE_SET_MAC | BXE_STATE_OPEN): 8925 case (EVENT_RING_OPCODE_SET_MAC | BXE_STATE_DIAG): 8926 case (EVENT_RING_OPCODE_SET_MAC | BXE_STATE_CLOSING_WAITING_HALT): 8927 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BXE_STATE_OPEN): 8928 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BXE_STATE_DIAG): 8929 case (EVENT_RING_OPCODE_CLASSIFICATION_RULES | BXE_STATE_CLOSING_WAITING_HALT): 8930 BLOGD(sc, DBG_SP, "got (un)set mac ramrod\n"); 8931 bxe_handle_classification_eqe(sc, elem); 8932 break; 8933 8934 case (EVENT_RING_OPCODE_MULTICAST_RULES | BXE_STATE_OPEN): 8935 case (EVENT_RING_OPCODE_MULTICAST_RULES | BXE_STATE_DIAG): 8936 case (EVENT_RING_OPCODE_MULTICAST_RULES | BXE_STATE_CLOSING_WAITING_HALT): 8937 BLOGD(sc, DBG_SP, "got mcast ramrod\n"); 8938 bxe_handle_mcast_eqe(sc); 8939 break; 8940 8941 case (EVENT_RING_OPCODE_FILTERS_RULES | BXE_STATE_OPEN): 8942 case (EVENT_RING_OPCODE_FILTERS_RULES | BXE_STATE_DIAG): 8943 case (EVENT_RING_OPCODE_FILTERS_RULES | BXE_STATE_CLOSING_WAITING_HALT): 8944 BLOGD(sc, DBG_SP, "got rx_mode ramrod\n"); 8945 bxe_handle_rx_mode_eqe(sc, elem); 8946 break; 8947 8948 default: 8949 /* unknown event log error and continue */ 8950 BLOGE(sc, "Unknown EQ event %d, sc->state 0x%x\n", 8951 elem->message.opcode, sc->state); 8952 } 8953 8954 next_spqe: 8955 spqe_cnt++; 8956 } /* for */ 8957 8958 mb(); 8959 atomic_add_acq_long(&sc->eq_spq_left, spqe_cnt); 8960 8961 sc->eq_cons = sw_cons; 8962 sc->eq_prod = sw_prod; 8963 8964 /* make sure that above mem writes were issued towards the memory */ 8965 wmb(); 8966 8967 /* update producer */ 8968 bxe_update_eq_prod(sc, sc->eq_prod); 8969 } 8970 8971 static void 8972 bxe_handle_sp_tq(void *context, 8973 int pending) 8974 { 8975 struct bxe_softc *sc = (struct bxe_softc *)context; 8976 uint16_t status; 8977 8978 BLOGD(sc, DBG_SP, "---> SP TASK <---\n"); 8979 8980 /* what work needs to be performed? */ 8981 status = bxe_update_dsb_idx(sc); 8982 8983 BLOGD(sc, DBG_SP, "dsb status 0x%04x\n", status); 8984 8985 /* HW attentions */ 8986 if (status & BXE_DEF_SB_ATT_IDX) { 8987 BLOGD(sc, DBG_SP, "---> ATTN INTR <---\n"); 8988 bxe_attn_int(sc); 8989 status &= ~BXE_DEF_SB_ATT_IDX; 8990 } 8991 8992 /* SP events: STAT_QUERY and others */ 8993 if (status & BXE_DEF_SB_IDX) { 8994 /* handle EQ completions */ 8995 BLOGD(sc, DBG_SP, "---> EQ INTR <---\n"); 8996 bxe_eq_int(sc); 8997 bxe_ack_sb(sc, sc->igu_dsb_id, USTORM_ID, 8998 le16toh(sc->def_idx), IGU_INT_NOP, 1); 8999 status &= ~BXE_DEF_SB_IDX; 9000 } 9001 9002 /* if status is non zero then something went wrong */ 9003 if (__predict_false(status)) { 9004 BLOGE(sc, "Got an unknown SP interrupt! (0x%04x)\n", status); 9005 } 9006 9007 /* ack status block only if something was actually handled */ 9008 bxe_ack_sb(sc, sc->igu_dsb_id, ATTENTION_ID, 9009 le16toh(sc->def_att_idx), IGU_INT_ENABLE, 1); 9010 9011 /* 9012 * Must be called after the EQ processing (since eq leads to sriov 9013 * ramrod completion flows). 9014 * This flow may have been scheduled by the arrival of a ramrod 9015 * completion, or by the sriov code rescheduling itself. 9016 */ 9017 // XXX bxe_iov_sp_task(sc); 9018 9019 #if 0 9020 /* AFEX - poll to check if VIFSET_ACK should be sent to MFW */ 9021 if (bxe_test_and_clear_bit(ECORE_AFEX_PENDING_VIFSET_MCP_ACK, 9022 &sc->sp_state)) { 9023 bxe_link_report(sc); 9024 bxe_fw_command(sc, DRV_MSG_CODE_AFEX_VIFSET_ACK, 0); 9025 } 9026 #endif 9027 } 9028 9029 static void 9030 bxe_handle_fp_tq(void *context, 9031 int pending) 9032 { 9033 struct bxe_fastpath *fp = (struct bxe_fastpath *)context; 9034 struct bxe_softc *sc = fp->sc; 9035 uint8_t more_tx = FALSE; 9036 uint8_t more_rx = FALSE; 9037 9038 BLOGD(sc, DBG_INTR, "---> FP TASK QUEUE (%d) <---\n", fp->index); 9039 9040 /* XXX 9041 * IFF_DRV_RUNNING state can't be checked here since we process 9042 * slowpath events on a client queue during setup. Instead 9043 * we need to add a "process/continue" flag here that the driver 9044 * can use to tell the task here not to do anything. 9045 */ 9046 #if 0 9047 if (!(sc->ifnet->if_drv_flags & IFF_DRV_RUNNING)) { 9048 return; 9049 } 9050 #endif 9051 9052 /* update the fastpath index */ 9053 bxe_update_fp_sb_idx(fp); 9054 9055 /* XXX add loop here if ever support multiple tx CoS */ 9056 /* fp->txdata[cos] */ 9057 if (bxe_has_tx_work(fp)) { 9058 BXE_FP_TX_LOCK(fp); 9059 more_tx = bxe_txeof(sc, fp); 9060 BXE_FP_TX_UNLOCK(fp); 9061 } 9062 9063 if (bxe_has_rx_work(fp)) { 9064 more_rx = bxe_rxeof(sc, fp); 9065 } 9066 9067 if (more_rx /*|| more_tx*/) { 9068 /* still more work to do */ 9069 taskqueue_enqueue_fast(fp->tq, &fp->tq_task); 9070 return; 9071 } 9072 9073 bxe_ack_sb(sc, fp->igu_sb_id, USTORM_ID, 9074 le16toh(fp->fp_hc_idx), IGU_INT_ENABLE, 1); 9075 } 9076 9077 static void 9078 bxe_task_fp(struct bxe_fastpath *fp) 9079 { 9080 struct bxe_softc *sc = fp->sc; 9081 uint8_t more_tx = FALSE; 9082 uint8_t more_rx = FALSE; 9083 9084 BLOGD(sc, DBG_INTR, "---> FP TASK ISR (%d) <---\n", fp->index); 9085 9086 /* update the fastpath index */ 9087 bxe_update_fp_sb_idx(fp); 9088 9089 /* XXX add loop here if ever support multiple tx CoS */ 9090 /* fp->txdata[cos] */ 9091 if (bxe_has_tx_work(fp)) { 9092 BXE_FP_TX_LOCK(fp); 9093 more_tx = bxe_txeof(sc, fp); 9094 BXE_FP_TX_UNLOCK(fp); 9095 } 9096 9097 if (bxe_has_rx_work(fp)) { 9098 more_rx = bxe_rxeof(sc, fp); 9099 } 9100 9101 if (more_rx /*|| more_tx*/) { 9102 /* still more work to do, bail out if this ISR and process later */ 9103 taskqueue_enqueue_fast(fp->tq, &fp->tq_task); 9104 return; 9105 } 9106 9107 /* 9108 * Here we write the fastpath index taken before doing any tx or rx work. 9109 * It is very well possible other hw events occurred up to this point and 9110 * they were actually processed accordingly above. Since we're going to 9111 * write an older fastpath index, an interrupt is coming which we might 9112 * not do any work in. 9113 */ 9114 bxe_ack_sb(sc, fp->igu_sb_id, USTORM_ID, 9115 le16toh(fp->fp_hc_idx), IGU_INT_ENABLE, 1); 9116 } 9117 9118 /* 9119 * Legacy interrupt entry point. 9120 * 9121 * Verifies that the controller generated the interrupt and 9122 * then calls a separate routine to handle the various 9123 * interrupt causes: link, RX, and TX. 9124 */ 9125 static void 9126 bxe_intr_legacy(void *xsc) 9127 { 9128 struct bxe_softc *sc = (struct bxe_softc *)xsc; 9129 struct bxe_fastpath *fp; 9130 uint16_t status, mask; 9131 int i; 9132 9133 BLOGD(sc, DBG_INTR, "---> BXE INTx <---\n"); 9134 9135 #if 0 9136 /* Don't handle any interrupts if we're not ready. */ 9137 if (__predict_false(sc->intr_sem != 0)) { 9138 return; 9139 } 9140 #endif 9141 9142 /* 9143 * 0 for ustorm, 1 for cstorm 9144 * the bits returned from ack_int() are 0-15 9145 * bit 0 = attention status block 9146 * bit 1 = fast path status block 9147 * a mask of 0x2 or more = tx/rx event 9148 * a mask of 1 = slow path event 9149 */ 9150 9151 status = bxe_ack_int(sc); 9152 9153 /* the interrupt is not for us */ 9154 if (__predict_false(status == 0)) { 9155 BLOGD(sc, DBG_INTR, "Not our interrupt!\n"); 9156 return; 9157 } 9158 9159 BLOGD(sc, DBG_INTR, "Interrupt status 0x%04x\n", status); 9160 9161 FOR_EACH_ETH_QUEUE(sc, i) { 9162 fp = &sc->fp[i]; 9163 mask = (0x2 << (fp->index + CNIC_SUPPORT(sc))); 9164 if (status & mask) { 9165 /* acknowledge and disable further fastpath interrupts */ 9166 bxe_ack_sb(sc, fp->igu_sb_id, USTORM_ID, 0, IGU_INT_DISABLE, 0); 9167 bxe_task_fp(fp); 9168 status &= ~mask; 9169 } 9170 } 9171 9172 #if 0 9173 if (CNIC_SUPPORT(sc)) { 9174 mask = 0x2; 9175 if (status & (mask | 0x1)) { 9176 ... 9177 status &= ~mask; 9178 } 9179 } 9180 #endif 9181 9182 if (__predict_false(status & 0x1)) { 9183 /* acknowledge and disable further slowpath interrupts */ 9184 bxe_ack_sb(sc, sc->igu_dsb_id, USTORM_ID, 0, IGU_INT_DISABLE, 0); 9185 9186 /* schedule slowpath handler */ 9187 taskqueue_enqueue_fast(sc->sp_tq, &sc->sp_tq_task); 9188 9189 status &= ~0x1; 9190 } 9191 9192 if (__predict_false(status)) { 9193 BLOGW(sc, "Unexpected fastpath status (0x%08x)!\n", status); 9194 } 9195 } 9196 9197 /* slowpath interrupt entry point */ 9198 static void 9199 bxe_intr_sp(void *xsc) 9200 { 9201 struct bxe_softc *sc = (struct bxe_softc *)xsc; 9202 9203 BLOGD(sc, (DBG_INTR | DBG_SP), "---> SP INTR <---\n"); 9204 9205 /* acknowledge and disable further slowpath interrupts */ 9206 bxe_ack_sb(sc, sc->igu_dsb_id, USTORM_ID, 0, IGU_INT_DISABLE, 0); 9207 9208 /* schedule slowpath handler */ 9209 taskqueue_enqueue_fast(sc->sp_tq, &sc->sp_tq_task); 9210 } 9211 9212 /* fastpath interrupt entry point */ 9213 static void 9214 bxe_intr_fp(void *xfp) 9215 { 9216 struct bxe_fastpath *fp = (struct bxe_fastpath *)xfp; 9217 struct bxe_softc *sc = fp->sc; 9218 9219 BLOGD(sc, DBG_INTR, "---> FP INTR %d <---\n", fp->index); 9220 9221 BLOGD(sc, DBG_INTR, 9222 "(cpu=%d) MSI-X fp=%d fw_sb=%d igu_sb=%d\n", 9223 curcpu, fp->index, fp->fw_sb_id, fp->igu_sb_id); 9224 9225 #if 0 9226 /* Don't handle any interrupts if we're not ready. */ 9227 if (__predict_false(sc->intr_sem != 0)) { 9228 return; 9229 } 9230 #endif 9231 9232 /* acknowledge and disable further fastpath interrupts */ 9233 bxe_ack_sb(sc, fp->igu_sb_id, USTORM_ID, 0, IGU_INT_DISABLE, 0); 9234 9235 bxe_task_fp(fp); 9236 } 9237 9238 /* Release all interrupts allocated by the driver. */ 9239 static void 9240 bxe_interrupt_free(struct bxe_softc *sc) 9241 { 9242 int i; 9243 9244 switch (sc->interrupt_mode) { 9245 case INTR_MODE_INTX: 9246 BLOGD(sc, DBG_LOAD, "Releasing legacy INTx vector\n"); 9247 if (sc->intr[0].resource != NULL) { 9248 bus_release_resource(sc->dev, 9249 SYS_RES_IRQ, 9250 sc->intr[0].rid, 9251 sc->intr[0].resource); 9252 } 9253 break; 9254 case INTR_MODE_MSI: 9255 for (i = 0; i < sc->intr_count; i++) { 9256 BLOGD(sc, DBG_LOAD, "Releasing MSI vector %d\n", i); 9257 if (sc->intr[i].resource && sc->intr[i].rid) { 9258 bus_release_resource(sc->dev, 9259 SYS_RES_IRQ, 9260 sc->intr[i].rid, 9261 sc->intr[i].resource); 9262 } 9263 } 9264 pci_release_msi(sc->dev); 9265 break; 9266 case INTR_MODE_MSIX: 9267 for (i = 0; i < sc->intr_count; i++) { 9268 BLOGD(sc, DBG_LOAD, "Releasing MSI-X vector %d\n", i); 9269 if (sc->intr[i].resource && sc->intr[i].rid) { 9270 bus_release_resource(sc->dev, 9271 SYS_RES_IRQ, 9272 sc->intr[i].rid, 9273 sc->intr[i].resource); 9274 } 9275 } 9276 pci_release_msi(sc->dev); 9277 break; 9278 default: 9279 /* nothing to do as initial allocation failed */ 9280 break; 9281 } 9282 } 9283 9284 /* 9285 * This function determines and allocates the appropriate 9286 * interrupt based on system capabilites and user request. 9287 * 9288 * The user may force a particular interrupt mode, specify 9289 * the number of receive queues, specify the method for 9290 * distribuitng received frames to receive queues, or use 9291 * the default settings which will automatically select the 9292 * best supported combination. In addition, the OS may or 9293 * may not support certain combinations of these settings. 9294 * This routine attempts to reconcile the settings requested 9295 * by the user with the capabilites available from the system 9296 * to select the optimal combination of features. 9297 * 9298 * Returns: 9299 * 0 = Success, !0 = Failure. 9300 */ 9301 static int 9302 bxe_interrupt_alloc(struct bxe_softc *sc) 9303 { 9304 int msix_count = 0; 9305 int msi_count = 0; 9306 int num_requested = 0; 9307 int num_allocated = 0; 9308 int rid, i, j; 9309 int rc; 9310 9311 /* get the number of available MSI/MSI-X interrupts from the OS */ 9312 if (sc->interrupt_mode > 0) { 9313 if (sc->devinfo.pcie_cap_flags & BXE_MSIX_CAPABLE_FLAG) { 9314 msix_count = pci_msix_count(sc->dev); 9315 } 9316 9317 if (sc->devinfo.pcie_cap_flags & BXE_MSI_CAPABLE_FLAG) { 9318 msi_count = pci_msi_count(sc->dev); 9319 } 9320 9321 BLOGD(sc, DBG_LOAD, "%d MSI and %d MSI-X vectors available\n", 9322 msi_count, msix_count); 9323 } 9324 9325 do { /* try allocating MSI-X interrupt resources (at least 2) */ 9326 if (sc->interrupt_mode != INTR_MODE_MSIX) { 9327 break; 9328 } 9329 9330 if (((sc->devinfo.pcie_cap_flags & BXE_MSIX_CAPABLE_FLAG) == 0) || 9331 (msix_count < 2)) { 9332 sc->interrupt_mode = INTR_MODE_MSI; /* try MSI next */ 9333 break; 9334 } 9335 9336 /* ask for the necessary number of MSI-X vectors */ 9337 num_requested = min((sc->num_queues + 1), msix_count); 9338 9339 BLOGD(sc, DBG_LOAD, "Requesting %d MSI-X vectors\n", num_requested); 9340 9341 num_allocated = num_requested; 9342 if ((rc = pci_alloc_msix(sc->dev, &num_allocated)) != 0) { 9343 BLOGE(sc, "MSI-X alloc failed! (%d)\n", rc); 9344 sc->interrupt_mode = INTR_MODE_MSI; /* try MSI next */ 9345 break; 9346 } 9347 9348 if (num_allocated < 2) { /* possible? */ 9349 BLOGE(sc, "MSI-X allocation less than 2!\n"); 9350 sc->interrupt_mode = INTR_MODE_MSI; /* try MSI next */ 9351 pci_release_msi(sc->dev); 9352 break; 9353 } 9354 9355 BLOGI(sc, "MSI-X vectors Requested %d and Allocated %d\n", 9356 num_requested, num_allocated); 9357 9358 /* best effort so use the number of vectors allocated to us */ 9359 sc->intr_count = num_allocated; 9360 sc->num_queues = num_allocated - 1; 9361 9362 rid = 1; /* initial resource identifier */ 9363 9364 /* allocate the MSI-X vectors */ 9365 for (i = 0; i < num_allocated; i++) { 9366 sc->intr[i].rid = (rid + i); 9367 9368 if ((sc->intr[i].resource = 9369 bus_alloc_resource_any(sc->dev, 9370 SYS_RES_IRQ, 9371 &sc->intr[i].rid, 9372 RF_ACTIVE)) == NULL) { 9373 BLOGE(sc, "Failed to map MSI-X[%d] (rid=%d)!\n", 9374 i, (rid + i)); 9375 9376 for (j = (i - 1); j >= 0; j--) { 9377 bus_release_resource(sc->dev, 9378 SYS_RES_IRQ, 9379 sc->intr[j].rid, 9380 sc->intr[j].resource); 9381 } 9382 9383 sc->intr_count = 0; 9384 sc->num_queues = 0; 9385 sc->interrupt_mode = INTR_MODE_MSI; /* try MSI next */ 9386 pci_release_msi(sc->dev); 9387 break; 9388 } 9389 9390 BLOGD(sc, DBG_LOAD, "Mapped MSI-X[%d] (rid=%d)\n", i, (rid + i)); 9391 } 9392 } while (0); 9393 9394 do { /* try allocating MSI vector resources (at least 2) */ 9395 if (sc->interrupt_mode != INTR_MODE_MSI) { 9396 break; 9397 } 9398 9399 if (((sc->devinfo.pcie_cap_flags & BXE_MSI_CAPABLE_FLAG) == 0) || 9400 (msi_count < 2)) { 9401 sc->interrupt_mode = INTR_MODE_INTX; /* try INTx next */ 9402 break; 9403 } 9404 9405 /* ask for the necessary number of MSI vectors */ 9406 num_requested = min((sc->num_queues + 1), msi_count); 9407 9408 BLOGD(sc, DBG_LOAD, "Requesting %d MSI vectors\n", num_requested); 9409 9410 num_allocated = num_requested; 9411 if ((rc = pci_alloc_msi(sc->dev, &num_allocated)) != 0) { 9412 BLOGE(sc, "MSI alloc failed (%d)!\n", rc); 9413 sc->interrupt_mode = INTR_MODE_INTX; /* try INTx next */ 9414 break; 9415 } 9416 9417 if (num_allocated < 2) { /* possible? */ 9418 BLOGE(sc, "MSI allocation less than 2!\n"); 9419 sc->interrupt_mode = INTR_MODE_INTX; /* try INTx next */ 9420 pci_release_msi(sc->dev); 9421 break; 9422 } 9423 9424 BLOGI(sc, "MSI vectors Requested %d and Allocated %d\n", 9425 num_requested, num_allocated); 9426 9427 /* best effort so use the number of vectors allocated to us */ 9428 sc->intr_count = num_allocated; 9429 sc->num_queues = num_allocated - 1; 9430 9431 rid = 1; /* initial resource identifier */ 9432 9433 /* allocate the MSI vectors */ 9434 for (i = 0; i < num_allocated; i++) { 9435 sc->intr[i].rid = (rid + i); 9436 9437 if ((sc->intr[i].resource = 9438 bus_alloc_resource_any(sc->dev, 9439 SYS_RES_IRQ, 9440 &sc->intr[i].rid, 9441 RF_ACTIVE)) == NULL) { 9442 BLOGE(sc, "Failed to map MSI[%d] (rid=%d)!\n", 9443 i, (rid + i)); 9444 9445 for (j = (i - 1); j >= 0; j--) { 9446 bus_release_resource(sc->dev, 9447 SYS_RES_IRQ, 9448 sc->intr[j].rid, 9449 sc->intr[j].resource); 9450 } 9451 9452 sc->intr_count = 0; 9453 sc->num_queues = 0; 9454 sc->interrupt_mode = INTR_MODE_INTX; /* try INTx next */ 9455 pci_release_msi(sc->dev); 9456 break; 9457 } 9458 9459 BLOGD(sc, DBG_LOAD, "Mapped MSI[%d] (rid=%d)\n", i, (rid + i)); 9460 } 9461 } while (0); 9462 9463 do { /* try allocating INTx vector resources */ 9464 if (sc->interrupt_mode != INTR_MODE_INTX) { 9465 break; 9466 } 9467 9468 BLOGD(sc, DBG_LOAD, "Requesting legacy INTx interrupt\n"); 9469 9470 /* only one vector for INTx */ 9471 sc->intr_count = 1; 9472 sc->num_queues = 1; 9473 9474 rid = 0; /* initial resource identifier */ 9475 9476 sc->intr[0].rid = rid; 9477 9478 if ((sc->intr[0].resource = 9479 bus_alloc_resource_any(sc->dev, 9480 SYS_RES_IRQ, 9481 &sc->intr[0].rid, 9482 (RF_ACTIVE | RF_SHAREABLE))) == NULL) { 9483 BLOGE(sc, "Failed to map INTx (rid=%d)!\n", rid); 9484 sc->intr_count = 0; 9485 sc->num_queues = 0; 9486 sc->interrupt_mode = -1; /* Failed! */ 9487 break; 9488 } 9489 9490 BLOGD(sc, DBG_LOAD, "Mapped INTx (rid=%d)\n", rid); 9491 } while (0); 9492 9493 if (sc->interrupt_mode == -1) { 9494 BLOGE(sc, "Interrupt Allocation: FAILED!!!\n"); 9495 rc = 1; 9496 } else { 9497 BLOGD(sc, DBG_LOAD, 9498 "Interrupt Allocation: interrupt_mode=%d, num_queues=%d\n", 9499 sc->interrupt_mode, sc->num_queues); 9500 rc = 0; 9501 } 9502 9503 return (rc); 9504 } 9505 9506 static void 9507 bxe_interrupt_detach(struct bxe_softc *sc) 9508 { 9509 struct bxe_fastpath *fp; 9510 int i; 9511 9512 /* release interrupt resources */ 9513 for (i = 0; i < sc->intr_count; i++) { 9514 if (sc->intr[i].resource && sc->intr[i].tag) { 9515 BLOGD(sc, DBG_LOAD, "Disabling interrupt vector %d\n", i); 9516 bus_teardown_intr(sc->dev, sc->intr[i].resource, sc->intr[i].tag); 9517 } 9518 } 9519 9520 for (i = 0; i < sc->num_queues; i++) { 9521 fp = &sc->fp[i]; 9522 if (fp->tq) { 9523 taskqueue_drain(fp->tq, &fp->tq_task); 9524 taskqueue_free(fp->tq); 9525 fp->tq = NULL; 9526 } 9527 } 9528 9529 if (sc->rx_mode_tq) { 9530 taskqueue_drain(sc->rx_mode_tq, &sc->rx_mode_tq_task); 9531 taskqueue_free(sc->rx_mode_tq); 9532 sc->rx_mode_tq = NULL; 9533 } 9534 9535 if (sc->sp_tq) { 9536 taskqueue_drain(sc->sp_tq, &sc->sp_tq_task); 9537 taskqueue_free(sc->sp_tq); 9538 sc->sp_tq = NULL; 9539 } 9540 } 9541 9542 /* 9543 * Enables interrupts and attach to the ISR. 9544 * 9545 * When using multiple MSI/MSI-X vectors the first vector 9546 * is used for slowpath operations while all remaining 9547 * vectors are used for fastpath operations. If only a 9548 * single MSI/MSI-X vector is used (SINGLE_ISR) then the 9549 * ISR must look for both slowpath and fastpath completions. 9550 */ 9551 static int 9552 bxe_interrupt_attach(struct bxe_softc *sc) 9553 { 9554 struct bxe_fastpath *fp; 9555 int rc = 0; 9556 int i; 9557 9558 snprintf(sc->sp_tq_name, sizeof(sc->sp_tq_name), 9559 "bxe%d_sp_tq", sc->unit); 9560 TASK_INIT(&sc->sp_tq_task, 0, bxe_handle_sp_tq, sc); 9561 sc->sp_tq = taskqueue_create_fast(sc->sp_tq_name, M_NOWAIT, 9562 taskqueue_thread_enqueue, 9563 &sc->sp_tq); 9564 taskqueue_start_threads(&sc->sp_tq, 1, PWAIT, /* lower priority */ 9565 "%s", sc->sp_tq_name); 9566 9567 snprintf(sc->rx_mode_tq_name, sizeof(sc->rx_mode_tq_name), 9568 "bxe%d_rx_mode_tq", sc->unit); 9569 TASK_INIT(&sc->rx_mode_tq_task, 0, bxe_handle_rx_mode_tq, sc); 9570 sc->rx_mode_tq = taskqueue_create_fast(sc->rx_mode_tq_name, M_NOWAIT, 9571 taskqueue_thread_enqueue, 9572 &sc->rx_mode_tq); 9573 taskqueue_start_threads(&sc->rx_mode_tq, 1, PWAIT, /* lower priority */ 9574 "%s", sc->rx_mode_tq_name); 9575 9576 for (i = 0; i < sc->num_queues; i++) { 9577 fp = &sc->fp[i]; 9578 snprintf(fp->tq_name, sizeof(fp->tq_name), 9579 "bxe%d_fp%d_tq", sc->unit, i); 9580 TASK_INIT(&fp->tq_task, 0, bxe_handle_fp_tq, fp); 9581 fp->tq = taskqueue_create_fast(fp->tq_name, M_NOWAIT, 9582 taskqueue_thread_enqueue, 9583 &fp->tq); 9584 taskqueue_start_threads(&fp->tq, 1, PI_NET, /* higher priority */ 9585 "%s", fp->tq_name); 9586 } 9587 9588 /* setup interrupt handlers */ 9589 if (sc->interrupt_mode == INTR_MODE_MSIX) { 9590 BLOGD(sc, DBG_LOAD, "Enabling slowpath MSI-X[0] vector\n"); 9591 9592 /* 9593 * Setup the interrupt handler. Note that we pass the driver instance 9594 * to the interrupt handler for the slowpath. 9595 */ 9596 if ((rc = bus_setup_intr(sc->dev, sc->intr[0].resource, 9597 (INTR_TYPE_NET | INTR_MPSAFE), 9598 NULL, bxe_intr_sp, sc, 9599 &sc->intr[0].tag)) != 0) { 9600 BLOGE(sc, "Failed to allocate MSI-X[0] vector (%d)\n", rc); 9601 goto bxe_interrupt_attach_exit; 9602 } 9603 9604 bus_describe_intr(sc->dev, sc->intr[0].resource, 9605 sc->intr[0].tag, "sp"); 9606 9607 /* bus_bind_intr(sc->dev, sc->intr[0].resource, 0); */ 9608 9609 /* initialize the fastpath vectors (note the first was used for sp) */ 9610 for (i = 0; i < sc->num_queues; i++) { 9611 fp = &sc->fp[i]; 9612 BLOGD(sc, DBG_LOAD, "Enabling MSI-X[%d] vector\n", (i + 1)); 9613 9614 /* 9615 * Setup the interrupt handler. Note that we pass the 9616 * fastpath context to the interrupt handler in this 9617 * case. 9618 */ 9619 if ((rc = bus_setup_intr(sc->dev, sc->intr[i + 1].resource, 9620 (INTR_TYPE_NET | INTR_MPSAFE), 9621 NULL, bxe_intr_fp, fp, 9622 &sc->intr[i + 1].tag)) != 0) { 9623 BLOGE(sc, "Failed to allocate MSI-X[%d] vector (%d)\n", 9624 (i + 1), rc); 9625 goto bxe_interrupt_attach_exit; 9626 } 9627 9628 bus_describe_intr(sc->dev, sc->intr[i + 1].resource, 9629 sc->intr[i + 1].tag, "fp%02d", i); 9630 9631 /* bind the fastpath instance to a cpu */ 9632 if (sc->num_queues > 1) { 9633 bus_bind_intr(sc->dev, sc->intr[i + 1].resource, i); 9634 } 9635 9636 fp->state = BXE_FP_STATE_IRQ; 9637 } 9638 } else if (sc->interrupt_mode == INTR_MODE_MSI) { 9639 BLOGD(sc, DBG_LOAD, "Enabling slowpath MSI[0] vector.\n"); 9640 9641 /* 9642 * Setup the interrupt handler. Note that we pass the driver instance 9643 * to the interrupt handler for the slowpath. 9644 */ 9645 if ((rc = bus_setup_intr(sc->dev, sc->intr[0].resource, 9646 (INTR_TYPE_NET | INTR_MPSAFE), 9647 NULL, bxe_intr_sp, sc, 9648 &sc->intr[0].tag)) != 0) { 9649 BLOGE(sc, "Failed to allocate MSI[0] vector (%d)\n", rc); 9650 goto bxe_interrupt_attach_exit; 9651 } 9652 9653 bus_describe_intr(sc->dev, sc->intr[0].resource, 9654 sc->intr[0].tag, "sp"); 9655 9656 /* bus_bind_intr(sc->dev, sc->intr[0].resource, 0); */ 9657 9658 /* initialize the fastpath vectors (note the first was used for sp) */ 9659 for (i = 0; i < sc->num_queues; i++) { 9660 fp = &sc->fp[i]; 9661 BLOGD(sc, DBG_LOAD, "Enabling MSI[%d] vector\n", (i + 1)); 9662 9663 /* 9664 * Setup the interrupt handler. Note that we pass the 9665 * fastpath context to the interrupt handler in this 9666 * case. 9667 */ 9668 if ((rc = bus_setup_intr(sc->dev, sc->intr[i + 1].resource, 9669 (INTR_TYPE_NET | INTR_MPSAFE), 9670 NULL, bxe_intr_fp, fp, 9671 &sc->intr[i + 1].tag)) != 0) { 9672 BLOGE(sc, "Failed to allocate MSI[%d] vector (%d)\n", 9673 (i + 1), rc); 9674 goto bxe_interrupt_attach_exit; 9675 } 9676 9677 bus_describe_intr(sc->dev, sc->intr[i + 1].resource, 9678 sc->intr[i + 1].tag, "fp%02d", i); 9679 9680 /* bind the fastpath instance to a cpu */ 9681 if (sc->num_queues > 1) { 9682 bus_bind_intr(sc->dev, sc->intr[i + 1].resource, i); 9683 } 9684 9685 fp->state = BXE_FP_STATE_IRQ; 9686 } 9687 } else { /* (sc->interrupt_mode == INTR_MODE_INTX) */ 9688 BLOGD(sc, DBG_LOAD, "Enabling INTx interrupts\n"); 9689 9690 /* 9691 * Setup the interrupt handler. Note that we pass the 9692 * driver instance to the interrupt handler which 9693 * will handle both the slowpath and fastpath. 9694 */ 9695 if ((rc = bus_setup_intr(sc->dev, sc->intr[0].resource, 9696 (INTR_TYPE_NET | INTR_MPSAFE), 9697 NULL, bxe_intr_legacy, sc, 9698 &sc->intr[0].tag)) != 0) { 9699 BLOGE(sc, "Failed to allocate INTx interrupt (%d)\n", rc); 9700 goto bxe_interrupt_attach_exit; 9701 } 9702 } 9703 9704 bxe_interrupt_attach_exit: 9705 9706 return (rc); 9707 } 9708 9709 static int bxe_init_hw_common_chip(struct bxe_softc *sc); 9710 static int bxe_init_hw_common(struct bxe_softc *sc); 9711 static int bxe_init_hw_port(struct bxe_softc *sc); 9712 static int bxe_init_hw_func(struct bxe_softc *sc); 9713 static void bxe_reset_common(struct bxe_softc *sc); 9714 static void bxe_reset_port(struct bxe_softc *sc); 9715 static void bxe_reset_func(struct bxe_softc *sc); 9716 static int bxe_gunzip_init(struct bxe_softc *sc); 9717 static void bxe_gunzip_end(struct bxe_softc *sc); 9718 static int bxe_init_firmware(struct bxe_softc *sc); 9719 static void bxe_release_firmware(struct bxe_softc *sc); 9720 9721 static struct 9722 ecore_func_sp_drv_ops bxe_func_sp_drv = { 9723 .init_hw_cmn_chip = bxe_init_hw_common_chip, 9724 .init_hw_cmn = bxe_init_hw_common, 9725 .init_hw_port = bxe_init_hw_port, 9726 .init_hw_func = bxe_init_hw_func, 9727 9728 .reset_hw_cmn = bxe_reset_common, 9729 .reset_hw_port = bxe_reset_port, 9730 .reset_hw_func = bxe_reset_func, 9731 9732 .gunzip_init = bxe_gunzip_init, 9733 .gunzip_end = bxe_gunzip_end, 9734 9735 .init_fw = bxe_init_firmware, 9736 .release_fw = bxe_release_firmware, 9737 }; 9738 9739 static void 9740 bxe_init_func_obj(struct bxe_softc *sc) 9741 { 9742 sc->dmae_ready = 0; 9743 9744 ecore_init_func_obj(sc, 9745 &sc->func_obj, 9746 BXE_SP(sc, func_rdata), 9747 BXE_SP_MAPPING(sc, func_rdata), 9748 BXE_SP(sc, func_afex_rdata), 9749 BXE_SP_MAPPING(sc, func_afex_rdata), 9750 &bxe_func_sp_drv); 9751 } 9752 9753 static int 9754 bxe_init_hw(struct bxe_softc *sc, 9755 uint32_t load_code) 9756 { 9757 struct ecore_func_state_params func_params = { NULL }; 9758 int rc; 9759 9760 /* prepare the parameters for function state transitions */ 9761 bit_set(&func_params.ramrod_flags, RAMROD_COMP_WAIT); 9762 9763 func_params.f_obj = &sc->func_obj; 9764 func_params.cmd = ECORE_F_CMD_HW_INIT; 9765 9766 func_params.params.hw_init.load_phase = load_code; 9767 9768 /* 9769 * Via a plethora of function pointers, we will eventually reach 9770 * bxe_init_hw_common(), bxe_init_hw_port(), or bxe_init_hw_func(). 9771 */ 9772 rc = ecore_func_state_change(sc, &func_params); 9773 9774 return (rc); 9775 } 9776 9777 static void 9778 bxe_fill(struct bxe_softc *sc, 9779 uint32_t addr, 9780 int fill, 9781 uint32_t len) 9782 { 9783 uint32_t i; 9784 9785 if (!(len % 4) && !(addr % 4)) { 9786 for (i = 0; i < len; i += 4) { 9787 REG_WR(sc, (addr + i), fill); 9788 } 9789 } else { 9790 for (i = 0; i < len; i++) { 9791 REG_WR8(sc, (addr + i), fill); 9792 } 9793 } 9794 } 9795 9796 /* writes FP SP data to FW - data_size in dwords */ 9797 static void 9798 bxe_wr_fp_sb_data(struct bxe_softc *sc, 9799 int fw_sb_id, 9800 uint32_t *sb_data_p, 9801 uint32_t data_size) 9802 { 9803 int index; 9804 9805 for (index = 0; index < data_size; index++) { 9806 REG_WR(sc, 9807 (BAR_CSTRORM_INTMEM + 9808 CSTORM_STATUS_BLOCK_DATA_OFFSET(fw_sb_id) + 9809 (sizeof(uint32_t) * index)), 9810 *(sb_data_p + index)); 9811 } 9812 } 9813 9814 static void 9815 bxe_zero_fp_sb(struct bxe_softc *sc, 9816 int fw_sb_id) 9817 { 9818 struct hc_status_block_data_e2 sb_data_e2; 9819 struct hc_status_block_data_e1x sb_data_e1x; 9820 uint32_t *sb_data_p; 9821 uint32_t data_size = 0; 9822 9823 if (!CHIP_IS_E1x(sc)) { 9824 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2)); 9825 sb_data_e2.common.state = SB_DISABLED; 9826 sb_data_e2.common.p_func.vf_valid = FALSE; 9827 sb_data_p = (uint32_t *)&sb_data_e2; 9828 data_size = (sizeof(struct hc_status_block_data_e2) / 9829 sizeof(uint32_t)); 9830 } else { 9831 memset(&sb_data_e1x, 0, sizeof(struct hc_status_block_data_e1x)); 9832 sb_data_e1x.common.state = SB_DISABLED; 9833 sb_data_e1x.common.p_func.vf_valid = FALSE; 9834 sb_data_p = (uint32_t *)&sb_data_e1x; 9835 data_size = (sizeof(struct hc_status_block_data_e1x) / 9836 sizeof(uint32_t)); 9837 } 9838 9839 bxe_wr_fp_sb_data(sc, fw_sb_id, sb_data_p, data_size); 9840 9841 bxe_fill(sc, (BAR_CSTRORM_INTMEM + CSTORM_STATUS_BLOCK_OFFSET(fw_sb_id)), 9842 0, CSTORM_STATUS_BLOCK_SIZE); 9843 bxe_fill(sc, (BAR_CSTRORM_INTMEM + CSTORM_SYNC_BLOCK_OFFSET(fw_sb_id)), 9844 0, CSTORM_SYNC_BLOCK_SIZE); 9845 } 9846 9847 static void 9848 bxe_wr_sp_sb_data(struct bxe_softc *sc, 9849 struct hc_sp_status_block_data *sp_sb_data) 9850 { 9851 int i; 9852 9853 for (i = 0; 9854 i < (sizeof(struct hc_sp_status_block_data) / sizeof(uint32_t)); 9855 i++) { 9856 REG_WR(sc, 9857 (BAR_CSTRORM_INTMEM + 9858 CSTORM_SP_STATUS_BLOCK_DATA_OFFSET(SC_FUNC(sc)) + 9859 (i * sizeof(uint32_t))), 9860 *((uint32_t *)sp_sb_data + i)); 9861 } 9862 } 9863 9864 static void 9865 bxe_zero_sp_sb(struct bxe_softc *sc) 9866 { 9867 struct hc_sp_status_block_data sp_sb_data; 9868 9869 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data)); 9870 9871 sp_sb_data.state = SB_DISABLED; 9872 sp_sb_data.p_func.vf_valid = FALSE; 9873 9874 bxe_wr_sp_sb_data(sc, &sp_sb_data); 9875 9876 bxe_fill(sc, 9877 (BAR_CSTRORM_INTMEM + 9878 CSTORM_SP_STATUS_BLOCK_OFFSET(SC_FUNC(sc))), 9879 0, CSTORM_SP_STATUS_BLOCK_SIZE); 9880 bxe_fill(sc, 9881 (BAR_CSTRORM_INTMEM + 9882 CSTORM_SP_SYNC_BLOCK_OFFSET(SC_FUNC(sc))), 9883 0, CSTORM_SP_SYNC_BLOCK_SIZE); 9884 } 9885 9886 static void 9887 bxe_setup_ndsb_state_machine(struct hc_status_block_sm *hc_sm, 9888 int igu_sb_id, 9889 int igu_seg_id) 9890 { 9891 hc_sm->igu_sb_id = igu_sb_id; 9892 hc_sm->igu_seg_id = igu_seg_id; 9893 hc_sm->timer_value = 0xFF; 9894 hc_sm->time_to_expire = 0xFFFFFFFF; 9895 } 9896 9897 static void 9898 bxe_map_sb_state_machines(struct hc_index_data *index_data) 9899 { 9900 /* zero out state machine indices */ 9901 9902 /* rx indices */ 9903 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID; 9904 9905 /* tx indices */ 9906 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags &= ~HC_INDEX_DATA_SM_ID; 9907 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags &= ~HC_INDEX_DATA_SM_ID; 9908 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags &= ~HC_INDEX_DATA_SM_ID; 9909 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags &= ~HC_INDEX_DATA_SM_ID; 9910 9911 /* map indices */ 9912 9913 /* rx indices */ 9914 index_data[HC_INDEX_ETH_RX_CQ_CONS].flags |= 9915 (SM_RX_ID << HC_INDEX_DATA_SM_ID_SHIFT); 9916 9917 /* tx indices */ 9918 index_data[HC_INDEX_OOO_TX_CQ_CONS].flags |= 9919 (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT); 9920 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS0].flags |= 9921 (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT); 9922 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS1].flags |= 9923 (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT); 9924 index_data[HC_INDEX_ETH_TX_CQ_CONS_COS2].flags |= 9925 (SM_TX_ID << HC_INDEX_DATA_SM_ID_SHIFT); 9926 } 9927 9928 static void 9929 bxe_init_sb(struct bxe_softc *sc, 9930 bus_addr_t busaddr, 9931 int vfid, 9932 uint8_t vf_valid, 9933 int fw_sb_id, 9934 int igu_sb_id) 9935 { 9936 struct hc_status_block_data_e2 sb_data_e2; 9937 struct hc_status_block_data_e1x sb_data_e1x; 9938 struct hc_status_block_sm *hc_sm_p; 9939 uint32_t *sb_data_p; 9940 int igu_seg_id; 9941 int data_size; 9942 9943 if (CHIP_INT_MODE_IS_BC(sc)) { 9944 igu_seg_id = HC_SEG_ACCESS_NORM; 9945 } else { 9946 igu_seg_id = IGU_SEG_ACCESS_NORM; 9947 } 9948 9949 bxe_zero_fp_sb(sc, fw_sb_id); 9950 9951 if (!CHIP_IS_E1x(sc)) { 9952 memset(&sb_data_e2, 0, sizeof(struct hc_status_block_data_e2)); 9953 sb_data_e2.common.state = SB_ENABLED; 9954 sb_data_e2.common.p_func.pf_id = SC_FUNC(sc); 9955 sb_data_e2.common.p_func.vf_id = vfid; 9956 sb_data_e2.common.p_func.vf_valid = vf_valid; 9957 sb_data_e2.common.p_func.vnic_id = SC_VN(sc); 9958 sb_data_e2.common.same_igu_sb_1b = TRUE; 9959 sb_data_e2.common.host_sb_addr.hi = U64_HI(busaddr); 9960 sb_data_e2.common.host_sb_addr.lo = U64_LO(busaddr); 9961 hc_sm_p = sb_data_e2.common.state_machine; 9962 sb_data_p = (uint32_t *)&sb_data_e2; 9963 data_size = (sizeof(struct hc_status_block_data_e2) / 9964 sizeof(uint32_t)); 9965 bxe_map_sb_state_machines(sb_data_e2.index_data); 9966 } else { 9967 memset(&sb_data_e1x, 0, sizeof(struct hc_status_block_data_e1x)); 9968 sb_data_e1x.common.state = SB_ENABLED; 9969 sb_data_e1x.common.p_func.pf_id = SC_FUNC(sc); 9970 sb_data_e1x.common.p_func.vf_id = 0xff; 9971 sb_data_e1x.common.p_func.vf_valid = FALSE; 9972 sb_data_e1x.common.p_func.vnic_id = SC_VN(sc); 9973 sb_data_e1x.common.same_igu_sb_1b = TRUE; 9974 sb_data_e1x.common.host_sb_addr.hi = U64_HI(busaddr); 9975 sb_data_e1x.common.host_sb_addr.lo = U64_LO(busaddr); 9976 hc_sm_p = sb_data_e1x.common.state_machine; 9977 sb_data_p = (uint32_t *)&sb_data_e1x; 9978 data_size = (sizeof(struct hc_status_block_data_e1x) / 9979 sizeof(uint32_t)); 9980 bxe_map_sb_state_machines(sb_data_e1x.index_data); 9981 } 9982 9983 bxe_setup_ndsb_state_machine(&hc_sm_p[SM_RX_ID], igu_sb_id, igu_seg_id); 9984 bxe_setup_ndsb_state_machine(&hc_sm_p[SM_TX_ID], igu_sb_id, igu_seg_id); 9985 9986 BLOGD(sc, DBG_LOAD, "Init FW SB %d\n", fw_sb_id); 9987 9988 /* write indices to HW - PCI guarantees endianity of regpairs */ 9989 bxe_wr_fp_sb_data(sc, fw_sb_id, sb_data_p, data_size); 9990 } 9991 9992 static inline uint8_t 9993 bxe_fp_qzone_id(struct bxe_fastpath *fp) 9994 { 9995 if (CHIP_IS_E1x(fp->sc)) { 9996 return (fp->cl_id + SC_PORT(fp->sc) * ETH_MAX_RX_CLIENTS_E1H); 9997 } else { 9998 return (fp->cl_id); 9999 } 10000 } 10001 10002 static inline uint32_t 10003 bxe_rx_ustorm_prods_offset(struct bxe_softc *sc, 10004 struct bxe_fastpath *fp) 10005 { 10006 uint32_t offset = BAR_USTRORM_INTMEM; 10007 10008 #if 0 10009 if (IS_VF(sc)) { 10010 return (PXP_VF_ADDR_USDM_QUEUES_START + 10011 (sc->acquire_resp.resc.hw_qid[fp->index] * 10012 sizeof(struct ustorm_queue_zone_data))); 10013 } else 10014 #endif 10015 if (!CHIP_IS_E1x(sc)) { 10016 offset += USTORM_RX_PRODS_E2_OFFSET(fp->cl_qzone_id); 10017 } else { 10018 offset += USTORM_RX_PRODS_E1X_OFFSET(SC_PORT(sc), fp->cl_id); 10019 } 10020 10021 return (offset); 10022 } 10023 10024 static void 10025 bxe_init_eth_fp(struct bxe_softc *sc, 10026 int idx) 10027 { 10028 struct bxe_fastpath *fp = &sc->fp[idx]; 10029 uint32_t cids[ECORE_MULTI_TX_COS] = { 0 }; 10030 unsigned long q_type = 0; 10031 int cos; 10032 10033 fp->sc = sc; 10034 fp->index = idx; 10035 10036 snprintf(fp->tx_mtx_name, sizeof(fp->tx_mtx_name), 10037 "bxe%d_fp%d_tx_lock", sc->unit, idx); 10038 mtx_init(&fp->tx_mtx, fp->tx_mtx_name, NULL, MTX_DEF); 10039 10040 snprintf(fp->rx_mtx_name, sizeof(fp->rx_mtx_name), 10041 "bxe%d_fp%d_rx_lock", sc->unit, idx); 10042 mtx_init(&fp->rx_mtx, fp->rx_mtx_name, NULL, MTX_DEF); 10043 10044 fp->igu_sb_id = (sc->igu_base_sb + idx + CNIC_SUPPORT(sc)); 10045 fp->fw_sb_id = (sc->base_fw_ndsb + idx + CNIC_SUPPORT(sc)); 10046 10047 fp->cl_id = (CHIP_IS_E1x(sc)) ? 10048 (SC_L_ID(sc) + idx) : 10049 /* want client ID same as IGU SB ID for non-E1 */ 10050 fp->igu_sb_id; 10051 fp->cl_qzone_id = bxe_fp_qzone_id(fp); 10052 10053 /* setup sb indices */ 10054 if (!CHIP_IS_E1x(sc)) { 10055 fp->sb_index_values = fp->status_block.e2_sb->sb.index_values; 10056 fp->sb_running_index = fp->status_block.e2_sb->sb.running_index; 10057 } else { 10058 fp->sb_index_values = fp->status_block.e1x_sb->sb.index_values; 10059 fp->sb_running_index = fp->status_block.e1x_sb->sb.running_index; 10060 } 10061 10062 /* init shortcut */ 10063 fp->ustorm_rx_prods_offset = bxe_rx_ustorm_prods_offset(sc, fp); 10064 10065 fp->rx_cq_cons_sb = &fp->sb_index_values[HC_INDEX_ETH_RX_CQ_CONS]; 10066 10067 /* 10068 * XXX If multiple CoS is ever supported then each fastpath structure 10069 * will need to maintain tx producer/consumer/dma/etc values *per* CoS. 10070 */ 10071 for (cos = 0; cos < sc->max_cos; cos++) { 10072 cids[cos] = idx; 10073 } 10074 fp->tx_cons_sb = &fp->sb_index_values[HC_INDEX_ETH_TX_CQ_CONS_COS0]; 10075 10076 /* nothing more for a VF to do */ 10077 if (IS_VF(sc)) { 10078 return; 10079 } 10080 10081 bxe_init_sb(sc, fp->sb_dma.paddr, BXE_VF_ID_INVALID, FALSE, 10082 fp->fw_sb_id, fp->igu_sb_id); 10083 10084 bxe_update_fp_sb_idx(fp); 10085 10086 /* Configure Queue State object */ 10087 bit_set(&q_type, ECORE_Q_TYPE_HAS_RX); 10088 bit_set(&q_type, ECORE_Q_TYPE_HAS_TX); 10089 10090 ecore_init_queue_obj(sc, 10091 &sc->sp_objs[idx].q_obj, 10092 fp->cl_id, 10093 cids, 10094 sc->max_cos, 10095 SC_FUNC(sc), 10096 BXE_SP(sc, q_rdata), 10097 BXE_SP_MAPPING(sc, q_rdata), 10098 q_type); 10099 10100 /* configure classification DBs */ 10101 ecore_init_mac_obj(sc, 10102 &sc->sp_objs[idx].mac_obj, 10103 fp->cl_id, 10104 idx, 10105 SC_FUNC(sc), 10106 BXE_SP(sc, mac_rdata), 10107 BXE_SP_MAPPING(sc, mac_rdata), 10108 ECORE_FILTER_MAC_PENDING, 10109 &sc->sp_state, 10110 ECORE_OBJ_TYPE_RX_TX, 10111 &sc->macs_pool); 10112 10113 BLOGD(sc, DBG_LOAD, "fp[%d]: sb=%p cl_id=%d fw_sb=%d igu_sb=%d\n", 10114 idx, fp->status_block.e2_sb, fp->cl_id, fp->fw_sb_id, fp->igu_sb_id); 10115 } 10116 10117 static inline void 10118 bxe_update_rx_prod(struct bxe_softc *sc, 10119 struct bxe_fastpath *fp, 10120 uint16_t rx_bd_prod, 10121 uint16_t rx_cq_prod, 10122 uint16_t rx_sge_prod) 10123 { 10124 struct ustorm_eth_rx_producers rx_prods = { 0 }; 10125 uint32_t i; 10126 10127 /* update producers */ 10128 rx_prods.bd_prod = rx_bd_prod; 10129 rx_prods.cqe_prod = rx_cq_prod; 10130 rx_prods.sge_prod = rx_sge_prod; 10131 10132 /* 10133 * Make sure that the BD and SGE data is updated before updating the 10134 * producers since FW might read the BD/SGE right after the producer 10135 * is updated. 10136 * This is only applicable for weak-ordered memory model archs such 10137 * as IA-64. The following barrier is also mandatory since FW will 10138 * assumes BDs must have buffers. 10139 */ 10140 wmb(); 10141 10142 for (i = 0; i < (sizeof(rx_prods) / 4); i++) { 10143 REG_WR(sc, 10144 (fp->ustorm_rx_prods_offset + (i * 4)), 10145 ((uint32_t *)&rx_prods)[i]); 10146 } 10147 10148 wmb(); /* keep prod updates ordered */ 10149 10150 BLOGD(sc, DBG_RX, 10151 "RX fp[%d]: wrote prods bd_prod=%u cqe_prod=%u sge_prod=%u\n", 10152 fp->index, rx_bd_prod, rx_cq_prod, rx_sge_prod); 10153 } 10154 10155 static void 10156 bxe_init_rx_rings(struct bxe_softc *sc) 10157 { 10158 struct bxe_fastpath *fp; 10159 int i; 10160 10161 for (i = 0; i < sc->num_queues; i++) { 10162 fp = &sc->fp[i]; 10163 10164 fp->rx_bd_cons = 0; 10165 10166 /* 10167 * Activate the BD ring... 10168 * Warning, this will generate an interrupt (to the TSTORM) 10169 * so this can only be done after the chip is initialized 10170 */ 10171 bxe_update_rx_prod(sc, fp, 10172 fp->rx_bd_prod, 10173 fp->rx_cq_prod, 10174 fp->rx_sge_prod); 10175 10176 if (i != 0) { 10177 continue; 10178 } 10179 10180 if (CHIP_IS_E1(sc)) { 10181 REG_WR(sc, 10182 (BAR_USTRORM_INTMEM + 10183 USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(SC_FUNC(sc))), 10184 U64_LO(fp->rcq_dma.paddr)); 10185 REG_WR(sc, 10186 (BAR_USTRORM_INTMEM + 10187 USTORM_MEM_WORKAROUND_ADDRESS_OFFSET(SC_FUNC(sc)) + 4), 10188 U64_HI(fp->rcq_dma.paddr)); 10189 } 10190 } 10191 } 10192 10193 static void 10194 bxe_init_tx_ring_one(struct bxe_fastpath *fp) 10195 { 10196 SET_FLAG(fp->tx_db.data.header.header, DOORBELL_HDR_DB_TYPE, 1); 10197 fp->tx_db.data.zero_fill1 = 0; 10198 fp->tx_db.data.prod = 0; 10199 10200 fp->tx_pkt_prod = 0; 10201 fp->tx_pkt_cons = 0; 10202 fp->tx_bd_prod = 0; 10203 fp->tx_bd_cons = 0; 10204 fp->eth_q_stats.tx_pkts = 0; 10205 } 10206 10207 static inline void 10208 bxe_init_tx_rings(struct bxe_softc *sc) 10209 { 10210 int i; 10211 10212 for (i = 0; i < sc->num_queues; i++) { 10213 #if 0 10214 uint8_t cos; 10215 for (cos = 0; cos < sc->max_cos; cos++) { 10216 bxe_init_tx_ring_one(&sc->fp[i].txdata[cos]); 10217 } 10218 #else 10219 bxe_init_tx_ring_one(&sc->fp[i]); 10220 #endif 10221 } 10222 } 10223 10224 static void 10225 bxe_init_def_sb(struct bxe_softc *sc) 10226 { 10227 struct host_sp_status_block *def_sb = sc->def_sb; 10228 bus_addr_t mapping = sc->def_sb_dma.paddr; 10229 int igu_sp_sb_index; 10230 int igu_seg_id; 10231 int port = SC_PORT(sc); 10232 int func = SC_FUNC(sc); 10233 int reg_offset, reg_offset_en5; 10234 uint64_t section; 10235 int index, sindex; 10236 struct hc_sp_status_block_data sp_sb_data; 10237 10238 memset(&sp_sb_data, 0, sizeof(struct hc_sp_status_block_data)); 10239 10240 if (CHIP_INT_MODE_IS_BC(sc)) { 10241 igu_sp_sb_index = DEF_SB_IGU_ID; 10242 igu_seg_id = HC_SEG_ACCESS_DEF; 10243 } else { 10244 igu_sp_sb_index = sc->igu_dsb_id; 10245 igu_seg_id = IGU_SEG_ACCESS_DEF; 10246 } 10247 10248 /* attentions */ 10249 section = ((uint64_t)mapping + 10250 offsetof(struct host_sp_status_block, atten_status_block)); 10251 def_sb->atten_status_block.status_block_id = igu_sp_sb_index; 10252 sc->attn_state = 0; 10253 10254 reg_offset = (port) ? 10255 MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : 10256 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0; 10257 reg_offset_en5 = (port) ? 10258 MISC_REG_AEU_ENABLE5_FUNC_1_OUT_0 : 10259 MISC_REG_AEU_ENABLE5_FUNC_0_OUT_0; 10260 10261 for (index = 0; index < MAX_DYNAMIC_ATTN_GRPS; index++) { 10262 /* take care of sig[0]..sig[4] */ 10263 for (sindex = 0; sindex < 4; sindex++) { 10264 sc->attn_group[index].sig[sindex] = 10265 REG_RD(sc, (reg_offset + (sindex * 0x4) + (0x10 * index))); 10266 } 10267 10268 if (!CHIP_IS_E1x(sc)) { 10269 /* 10270 * enable5 is separate from the rest of the registers, 10271 * and the address skip is 4 and not 16 between the 10272 * different groups 10273 */ 10274 sc->attn_group[index].sig[4] = 10275 REG_RD(sc, (reg_offset_en5 + (0x4 * index))); 10276 } else { 10277 sc->attn_group[index].sig[4] = 0; 10278 } 10279 } 10280 10281 if (sc->devinfo.int_block == INT_BLOCK_HC) { 10282 reg_offset = (port) ? 10283 HC_REG_ATTN_MSG1_ADDR_L : 10284 HC_REG_ATTN_MSG0_ADDR_L; 10285 REG_WR(sc, reg_offset, U64_LO(section)); 10286 REG_WR(sc, (reg_offset + 4), U64_HI(section)); 10287 } else if (!CHIP_IS_E1x(sc)) { 10288 REG_WR(sc, IGU_REG_ATTN_MSG_ADDR_L, U64_LO(section)); 10289 REG_WR(sc, IGU_REG_ATTN_MSG_ADDR_H, U64_HI(section)); 10290 } 10291 10292 section = ((uint64_t)mapping + 10293 offsetof(struct host_sp_status_block, sp_sb)); 10294 10295 bxe_zero_sp_sb(sc); 10296 10297 /* PCI guarantees endianity of regpair */ 10298 sp_sb_data.state = SB_ENABLED; 10299 sp_sb_data.host_sb_addr.lo = U64_LO(section); 10300 sp_sb_data.host_sb_addr.hi = U64_HI(section); 10301 sp_sb_data.igu_sb_id = igu_sp_sb_index; 10302 sp_sb_data.igu_seg_id = igu_seg_id; 10303 sp_sb_data.p_func.pf_id = func; 10304 sp_sb_data.p_func.vnic_id = SC_VN(sc); 10305 sp_sb_data.p_func.vf_id = 0xff; 10306 10307 bxe_wr_sp_sb_data(sc, &sp_sb_data); 10308 10309 bxe_ack_sb(sc, sc->igu_dsb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0); 10310 } 10311 10312 static void 10313 bxe_init_sp_ring(struct bxe_softc *sc) 10314 { 10315 atomic_store_rel_long(&sc->cq_spq_left, MAX_SPQ_PENDING); 10316 sc->spq_prod_idx = 0; 10317 sc->dsb_sp_prod = &sc->def_sb->sp_sb.index_values[HC_SP_INDEX_ETH_DEF_CONS]; 10318 sc->spq_prod_bd = sc->spq; 10319 sc->spq_last_bd = (sc->spq_prod_bd + MAX_SP_DESC_CNT); 10320 } 10321 10322 static void 10323 bxe_init_eq_ring(struct bxe_softc *sc) 10324 { 10325 union event_ring_elem *elem; 10326 int i; 10327 10328 for (i = 1; i <= NUM_EQ_PAGES; i++) { 10329 elem = &sc->eq[EQ_DESC_CNT_PAGE * i - 1]; 10330 10331 elem->next_page.addr.hi = htole32(U64_HI(sc->eq_dma.paddr + 10332 BCM_PAGE_SIZE * 10333 (i % NUM_EQ_PAGES))); 10334 elem->next_page.addr.lo = htole32(U64_LO(sc->eq_dma.paddr + 10335 BCM_PAGE_SIZE * 10336 (i % NUM_EQ_PAGES))); 10337 } 10338 10339 sc->eq_cons = 0; 10340 sc->eq_prod = NUM_EQ_DESC; 10341 sc->eq_cons_sb = &sc->def_sb->sp_sb.index_values[HC_SP_INDEX_EQ_CONS]; 10342 10343 atomic_store_rel_long(&sc->eq_spq_left, 10344 (min((MAX_SP_DESC_CNT - MAX_SPQ_PENDING), 10345 NUM_EQ_DESC) - 1)); 10346 } 10347 10348 static void 10349 bxe_init_internal_common(struct bxe_softc *sc) 10350 { 10351 int i; 10352 10353 if (IS_MF_SI(sc)) { 10354 /* 10355 * In switch independent mode, the TSTORM needs to accept 10356 * packets that failed classification, since approximate match 10357 * mac addresses aren't written to NIG LLH. 10358 */ 10359 REG_WR8(sc, 10360 (BAR_TSTRORM_INTMEM + TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET), 10361 2); 10362 } else if (!CHIP_IS_E1(sc)) { /* 57710 doesn't support MF */ 10363 REG_WR8(sc, 10364 (BAR_TSTRORM_INTMEM + TSTORM_ACCEPT_CLASSIFY_FAILED_OFFSET), 10365 0); 10366 } 10367 10368 /* 10369 * Zero this manually as its initialization is currently missing 10370 * in the initTool. 10371 */ 10372 for (i = 0; i < (USTORM_AGG_DATA_SIZE >> 2); i++) { 10373 REG_WR(sc, 10374 (BAR_USTRORM_INTMEM + USTORM_AGG_DATA_OFFSET + (i * 4)), 10375 0); 10376 } 10377 10378 if (!CHIP_IS_E1x(sc)) { 10379 REG_WR8(sc, (BAR_CSTRORM_INTMEM + CSTORM_IGU_MODE_OFFSET), 10380 CHIP_INT_MODE_IS_BC(sc) ? HC_IGU_BC_MODE : HC_IGU_NBC_MODE); 10381 } 10382 } 10383 10384 static void 10385 bxe_init_internal(struct bxe_softc *sc, 10386 uint32_t load_code) 10387 { 10388 switch (load_code) { 10389 case FW_MSG_CODE_DRV_LOAD_COMMON: 10390 case FW_MSG_CODE_DRV_LOAD_COMMON_CHIP: 10391 bxe_init_internal_common(sc); 10392 /* no break */ 10393 10394 case FW_MSG_CODE_DRV_LOAD_PORT: 10395 /* nothing to do */ 10396 /* no break */ 10397 10398 case FW_MSG_CODE_DRV_LOAD_FUNCTION: 10399 /* internal memory per function is initialized inside bxe_pf_init */ 10400 break; 10401 10402 default: 10403 BLOGE(sc, "Unknown load_code (0x%x) from MCP\n", load_code); 10404 break; 10405 } 10406 } 10407 10408 static void 10409 storm_memset_func_cfg(struct bxe_softc *sc, 10410 struct tstorm_eth_function_common_config *tcfg, 10411 uint16_t abs_fid) 10412 { 10413 uint32_t addr; 10414 size_t size; 10415 10416 addr = (BAR_TSTRORM_INTMEM + 10417 TSTORM_FUNCTION_COMMON_CONFIG_OFFSET(abs_fid)); 10418 size = sizeof(struct tstorm_eth_function_common_config); 10419 ecore_storm_memset_struct(sc, addr, size, (uint32_t *)tcfg); 10420 } 10421 10422 static void 10423 bxe_func_init(struct bxe_softc *sc, 10424 struct bxe_func_init_params *p) 10425 { 10426 struct tstorm_eth_function_common_config tcfg = { 0 }; 10427 10428 if (CHIP_IS_E1x(sc)) { 10429 storm_memset_func_cfg(sc, &tcfg, p->func_id); 10430 } 10431 10432 /* Enable the function in the FW */ 10433 storm_memset_vf_to_pf(sc, p->func_id, p->pf_id); 10434 storm_memset_func_en(sc, p->func_id, 1); 10435 10436 /* spq */ 10437 if (p->func_flgs & FUNC_FLG_SPQ) { 10438 storm_memset_spq_addr(sc, p->spq_map, p->func_id); 10439 REG_WR(sc, 10440 (XSEM_REG_FAST_MEMORY + XSTORM_SPQ_PROD_OFFSET(p->func_id)), 10441 p->spq_prod); 10442 } 10443 } 10444 10445 /* 10446 * Calculates the sum of vn_min_rates. 10447 * It's needed for further normalizing of the min_rates. 10448 * Returns: 10449 * sum of vn_min_rates. 10450 * or 10451 * 0 - if all the min_rates are 0. 10452 * In the later case fainess algorithm should be deactivated. 10453 * If all min rates are not zero then those that are zeroes will be set to 1. 10454 */ 10455 static void 10456 bxe_calc_vn_min(struct bxe_softc *sc, 10457 struct cmng_init_input *input) 10458 { 10459 uint32_t vn_cfg; 10460 uint32_t vn_min_rate; 10461 int all_zero = 1; 10462 int vn; 10463 10464 for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) { 10465 vn_cfg = sc->devinfo.mf_info.mf_config[vn]; 10466 vn_min_rate = (((vn_cfg & FUNC_MF_CFG_MIN_BW_MASK) >> 10467 FUNC_MF_CFG_MIN_BW_SHIFT) * 100); 10468 10469 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) { 10470 /* skip hidden VNs */ 10471 vn_min_rate = 0; 10472 } else if (!vn_min_rate) { 10473 /* If min rate is zero - set it to 100 */ 10474 vn_min_rate = DEF_MIN_RATE; 10475 } else { 10476 all_zero = 0; 10477 } 10478 10479 input->vnic_min_rate[vn] = vn_min_rate; 10480 } 10481 10482 /* if ETS or all min rates are zeros - disable fairness */ 10483 if (BXE_IS_ETS_ENABLED(sc)) { 10484 input->flags.cmng_enables &= ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN; 10485 BLOGD(sc, DBG_LOAD, "Fairness disabled (ETS)\n"); 10486 } else if (all_zero) { 10487 input->flags.cmng_enables &= ~CMNG_FLAGS_PER_PORT_FAIRNESS_VN; 10488 BLOGD(sc, DBG_LOAD, 10489 "Fariness disabled (all MIN values are zeroes)\n"); 10490 } else { 10491 input->flags.cmng_enables |= CMNG_FLAGS_PER_PORT_FAIRNESS_VN; 10492 } 10493 } 10494 10495 static inline uint16_t 10496 bxe_extract_max_cfg(struct bxe_softc *sc, 10497 uint32_t mf_cfg) 10498 { 10499 uint16_t max_cfg = ((mf_cfg & FUNC_MF_CFG_MAX_BW_MASK) >> 10500 FUNC_MF_CFG_MAX_BW_SHIFT); 10501 10502 if (!max_cfg) { 10503 BLOGD(sc, DBG_LOAD, "Max BW configured to 0 - using 100 instead\n"); 10504 max_cfg = 100; 10505 } 10506 10507 return (max_cfg); 10508 } 10509 10510 static void 10511 bxe_calc_vn_max(struct bxe_softc *sc, 10512 int vn, 10513 struct cmng_init_input *input) 10514 { 10515 uint16_t vn_max_rate; 10516 uint32_t vn_cfg = sc->devinfo.mf_info.mf_config[vn]; 10517 uint32_t max_cfg; 10518 10519 if (vn_cfg & FUNC_MF_CFG_FUNC_HIDE) { 10520 vn_max_rate = 0; 10521 } else { 10522 max_cfg = bxe_extract_max_cfg(sc, vn_cfg); 10523 10524 if (IS_MF_SI(sc)) { 10525 /* max_cfg in percents of linkspeed */ 10526 vn_max_rate = ((sc->link_vars.line_speed * max_cfg) / 100); 10527 } else { /* SD modes */ 10528 /* max_cfg is absolute in 100Mb units */ 10529 vn_max_rate = (max_cfg * 100); 10530 } 10531 } 10532 10533 BLOGD(sc, DBG_LOAD, "vn %d: vn_max_rate %d\n", vn, vn_max_rate); 10534 10535 input->vnic_max_rate[vn] = vn_max_rate; 10536 } 10537 10538 static void 10539 bxe_cmng_fns_init(struct bxe_softc *sc, 10540 uint8_t read_cfg, 10541 uint8_t cmng_type) 10542 { 10543 struct cmng_init_input input; 10544 int vn; 10545 10546 memset(&input, 0, sizeof(struct cmng_init_input)); 10547 10548 input.port_rate = sc->link_vars.line_speed; 10549 10550 if (cmng_type == CMNG_FNS_MINMAX) { 10551 /* read mf conf from shmem */ 10552 if (read_cfg) { 10553 bxe_read_mf_cfg(sc); 10554 } 10555 10556 /* get VN min rate and enable fairness if not 0 */ 10557 bxe_calc_vn_min(sc, &input); 10558 10559 /* get VN max rate */ 10560 if (sc->port.pmf) { 10561 for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) { 10562 bxe_calc_vn_max(sc, vn, &input); 10563 } 10564 } 10565 10566 /* always enable rate shaping and fairness */ 10567 input.flags.cmng_enables |= CMNG_FLAGS_PER_PORT_RATE_SHAPING_VN; 10568 10569 ecore_init_cmng(&input, &sc->cmng); 10570 return; 10571 } 10572 10573 /* rate shaping and fairness are disabled */ 10574 BLOGD(sc, DBG_LOAD, "rate shaping and fairness have been disabled\n"); 10575 } 10576 10577 static int 10578 bxe_get_cmng_fns_mode(struct bxe_softc *sc) 10579 { 10580 if (CHIP_REV_IS_SLOW(sc)) { 10581 return (CMNG_FNS_NONE); 10582 } 10583 10584 if (IS_MF(sc)) { 10585 return (CMNG_FNS_MINMAX); 10586 } 10587 10588 return (CMNG_FNS_NONE); 10589 } 10590 10591 static void 10592 storm_memset_cmng(struct bxe_softc *sc, 10593 struct cmng_init *cmng, 10594 uint8_t port) 10595 { 10596 int vn; 10597 int func; 10598 uint32_t addr; 10599 size_t size; 10600 10601 addr = (BAR_XSTRORM_INTMEM + 10602 XSTORM_CMNG_PER_PORT_VARS_OFFSET(port)); 10603 size = sizeof(struct cmng_struct_per_port); 10604 ecore_storm_memset_struct(sc, addr, size, (uint32_t *)&cmng->port); 10605 10606 for (vn = VN_0; vn < SC_MAX_VN_NUM(sc); vn++) { 10607 func = func_by_vn(sc, vn); 10608 10609 addr = (BAR_XSTRORM_INTMEM + 10610 XSTORM_RATE_SHAPING_PER_VN_VARS_OFFSET(func)); 10611 size = sizeof(struct rate_shaping_vars_per_vn); 10612 ecore_storm_memset_struct(sc, addr, size, 10613 (uint32_t *)&cmng->vnic.vnic_max_rate[vn]); 10614 10615 addr = (BAR_XSTRORM_INTMEM + 10616 XSTORM_FAIRNESS_PER_VN_VARS_OFFSET(func)); 10617 size = sizeof(struct fairness_vars_per_vn); 10618 ecore_storm_memset_struct(sc, addr, size, 10619 (uint32_t *)&cmng->vnic.vnic_min_rate[vn]); 10620 } 10621 } 10622 10623 static void 10624 bxe_pf_init(struct bxe_softc *sc) 10625 { 10626 struct bxe_func_init_params func_init = { 0 }; 10627 struct event_ring_data eq_data = { { 0 } }; 10628 uint16_t flags; 10629 10630 if (!CHIP_IS_E1x(sc)) { 10631 /* reset IGU PF statistics: MSIX + ATTN */ 10632 /* PF */ 10633 REG_WR(sc, 10634 (IGU_REG_STATISTIC_NUM_MESSAGE_SENT + 10635 (BXE_IGU_STAS_MSG_VF_CNT * 4) + 10636 ((CHIP_IS_MODE_4_PORT(sc) ? SC_FUNC(sc) : SC_VN(sc)) * 4)), 10637 0); 10638 /* ATTN */ 10639 REG_WR(sc, 10640 (IGU_REG_STATISTIC_NUM_MESSAGE_SENT + 10641 (BXE_IGU_STAS_MSG_VF_CNT * 4) + 10642 (BXE_IGU_STAS_MSG_PF_CNT * 4) + 10643 ((CHIP_IS_MODE_4_PORT(sc) ? SC_FUNC(sc) : SC_VN(sc)) * 4)), 10644 0); 10645 } 10646 10647 /* function setup flags */ 10648 flags = (FUNC_FLG_STATS | FUNC_FLG_LEADING | FUNC_FLG_SPQ); 10649 10650 /* 10651 * This flag is relevant for E1x only. 10652 * E2 doesn't have a TPA configuration in a function level. 10653 */ 10654 flags |= (sc->ifnet->if_capenable & IFCAP_LRO) ? FUNC_FLG_TPA : 0; 10655 10656 func_init.func_flgs = flags; 10657 func_init.pf_id = SC_FUNC(sc); 10658 func_init.func_id = SC_FUNC(sc); 10659 func_init.spq_map = sc->spq_dma.paddr; 10660 func_init.spq_prod = sc->spq_prod_idx; 10661 10662 bxe_func_init(sc, &func_init); 10663 10664 memset(&sc->cmng, 0, sizeof(struct cmng_struct_per_port)); 10665 10666 /* 10667 * Congestion management values depend on the link rate. 10668 * There is no active link so initial link rate is set to 10Gbps. 10669 * When the link comes up the congestion management values are 10670 * re-calculated according to the actual link rate. 10671 */ 10672 sc->link_vars.line_speed = SPEED_10000; 10673 bxe_cmng_fns_init(sc, TRUE, bxe_get_cmng_fns_mode(sc)); 10674 10675 /* Only the PMF sets the HW */ 10676 if (sc->port.pmf) { 10677 storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc)); 10678 } 10679 10680 /* init Event Queue - PCI bus guarantees correct endainity */ 10681 eq_data.base_addr.hi = U64_HI(sc->eq_dma.paddr); 10682 eq_data.base_addr.lo = U64_LO(sc->eq_dma.paddr); 10683 eq_data.producer = sc->eq_prod; 10684 eq_data.index_id = HC_SP_INDEX_EQ_CONS; 10685 eq_data.sb_id = DEF_SB_ID; 10686 storm_memset_eq_data(sc, &eq_data, SC_FUNC(sc)); 10687 } 10688 10689 static void 10690 bxe_hc_int_enable(struct bxe_softc *sc) 10691 { 10692 int port = SC_PORT(sc); 10693 uint32_t addr = (port) ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0; 10694 uint32_t val = REG_RD(sc, addr); 10695 uint8_t msix = (sc->interrupt_mode == INTR_MODE_MSIX) ? TRUE : FALSE; 10696 uint8_t single_msix = ((sc->interrupt_mode == INTR_MODE_MSIX) && 10697 (sc->intr_count == 1)) ? TRUE : FALSE; 10698 uint8_t msi = (sc->interrupt_mode == INTR_MODE_MSI) ? TRUE : FALSE; 10699 10700 if (msix) { 10701 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | 10702 HC_CONFIG_0_REG_INT_LINE_EN_0); 10703 val |= (HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | 10704 HC_CONFIG_0_REG_ATTN_BIT_EN_0); 10705 if (single_msix) { 10706 val |= HC_CONFIG_0_REG_SINGLE_ISR_EN_0; 10707 } 10708 } else if (msi) { 10709 val &= ~HC_CONFIG_0_REG_INT_LINE_EN_0; 10710 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | 10711 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | 10712 HC_CONFIG_0_REG_ATTN_BIT_EN_0); 10713 } else { 10714 val |= (HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | 10715 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | 10716 HC_CONFIG_0_REG_INT_LINE_EN_0 | 10717 HC_CONFIG_0_REG_ATTN_BIT_EN_0); 10718 10719 if (!CHIP_IS_E1(sc)) { 10720 BLOGD(sc, DBG_INTR, "write %x to HC %d (addr 0x%x)\n", 10721 val, port, addr); 10722 10723 REG_WR(sc, addr, val); 10724 10725 val &= ~HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0; 10726 } 10727 } 10728 10729 if (CHIP_IS_E1(sc)) { 10730 REG_WR(sc, (HC_REG_INT_MASK + port*4), 0x1FFFF); 10731 } 10732 10733 BLOGD(sc, DBG_INTR, "write %x to HC %d (addr 0x%x) mode %s\n", 10734 val, port, addr, ((msix) ? "MSI-X" : ((msi) ? "MSI" : "INTx"))); 10735 10736 REG_WR(sc, addr, val); 10737 10738 /* ensure that HC_CONFIG is written before leading/trailing edge config */ 10739 mb(); 10740 10741 if (!CHIP_IS_E1(sc)) { 10742 /* init leading/trailing edge */ 10743 if (IS_MF(sc)) { 10744 val = (0xee0f | (1 << (SC_VN(sc) + 4))); 10745 if (sc->port.pmf) { 10746 /* enable nig and gpio3 attention */ 10747 val |= 0x1100; 10748 } 10749 } else { 10750 val = 0xffff; 10751 } 10752 10753 REG_WR(sc, (HC_REG_TRAILING_EDGE_0 + port*8), val); 10754 REG_WR(sc, (HC_REG_LEADING_EDGE_0 + port*8), val); 10755 } 10756 10757 /* make sure that interrupts are indeed enabled from here on */ 10758 mb(); 10759 } 10760 10761 static void 10762 bxe_igu_int_enable(struct bxe_softc *sc) 10763 { 10764 uint32_t val; 10765 uint8_t msix = (sc->interrupt_mode == INTR_MODE_MSIX) ? TRUE : FALSE; 10766 uint8_t single_msix = ((sc->interrupt_mode == INTR_MODE_MSIX) && 10767 (sc->intr_count == 1)) ? TRUE : FALSE; 10768 uint8_t msi = (sc->interrupt_mode == INTR_MODE_MSI) ? TRUE : FALSE; 10769 10770 val = REG_RD(sc, IGU_REG_PF_CONFIGURATION); 10771 10772 if (msix) { 10773 val &= ~(IGU_PF_CONF_INT_LINE_EN | 10774 IGU_PF_CONF_SINGLE_ISR_EN); 10775 val |= (IGU_PF_CONF_MSI_MSIX_EN | 10776 IGU_PF_CONF_ATTN_BIT_EN); 10777 if (single_msix) { 10778 val |= IGU_PF_CONF_SINGLE_ISR_EN; 10779 } 10780 } else if (msi) { 10781 val &= ~IGU_PF_CONF_INT_LINE_EN; 10782 val |= (IGU_PF_CONF_MSI_MSIX_EN | 10783 IGU_PF_CONF_ATTN_BIT_EN | 10784 IGU_PF_CONF_SINGLE_ISR_EN); 10785 } else { 10786 val &= ~IGU_PF_CONF_MSI_MSIX_EN; 10787 val |= (IGU_PF_CONF_INT_LINE_EN | 10788 IGU_PF_CONF_ATTN_BIT_EN | 10789 IGU_PF_CONF_SINGLE_ISR_EN); 10790 } 10791 10792 /* clean previous status - need to configure igu prior to ack*/ 10793 if ((!msix) || single_msix) { 10794 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val); 10795 bxe_ack_int(sc); 10796 } 10797 10798 val |= IGU_PF_CONF_FUNC_EN; 10799 10800 BLOGD(sc, DBG_INTR, "write 0x%x to IGU mode %s\n", 10801 val, ((msix) ? "MSI-X" : ((msi) ? "MSI" : "INTx"))); 10802 10803 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val); 10804 10805 mb(); 10806 10807 /* init leading/trailing edge */ 10808 if (IS_MF(sc)) { 10809 val = (0xee0f | (1 << (SC_VN(sc) + 4))); 10810 if (sc->port.pmf) { 10811 /* enable nig and gpio3 attention */ 10812 val |= 0x1100; 10813 } 10814 } else { 10815 val = 0xffff; 10816 } 10817 10818 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, val); 10819 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, val); 10820 10821 /* make sure that interrupts are indeed enabled from here on */ 10822 mb(); 10823 } 10824 10825 static void 10826 bxe_int_enable(struct bxe_softc *sc) 10827 { 10828 if (sc->devinfo.int_block == INT_BLOCK_HC) { 10829 bxe_hc_int_enable(sc); 10830 } else { 10831 bxe_igu_int_enable(sc); 10832 } 10833 } 10834 10835 static void 10836 bxe_hc_int_disable(struct bxe_softc *sc) 10837 { 10838 int port = SC_PORT(sc); 10839 uint32_t addr = (port) ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0; 10840 uint32_t val = REG_RD(sc, addr); 10841 10842 /* 10843 * In E1 we must use only PCI configuration space to disable MSI/MSIX 10844 * capablility. It's forbidden to disable IGU_PF_CONF_MSI_MSIX_EN in HC 10845 * block 10846 */ 10847 if (CHIP_IS_E1(sc)) { 10848 /* 10849 * Since IGU_PF_CONF_MSI_MSIX_EN still always on use mask register 10850 * to prevent from HC sending interrupts after we exit the function 10851 */ 10852 REG_WR(sc, (HC_REG_INT_MASK + port*4), 0); 10853 10854 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | 10855 HC_CONFIG_0_REG_INT_LINE_EN_0 | 10856 HC_CONFIG_0_REG_ATTN_BIT_EN_0); 10857 } else { 10858 val &= ~(HC_CONFIG_0_REG_SINGLE_ISR_EN_0 | 10859 HC_CONFIG_0_REG_MSI_MSIX_INT_EN_0 | 10860 HC_CONFIG_0_REG_INT_LINE_EN_0 | 10861 HC_CONFIG_0_REG_ATTN_BIT_EN_0); 10862 } 10863 10864 BLOGD(sc, DBG_INTR, "write %x to HC %d (addr 0x%x)\n", val, port, addr); 10865 10866 /* flush all outstanding writes */ 10867 mb(); 10868 10869 REG_WR(sc, addr, val); 10870 if (REG_RD(sc, addr) != val) { 10871 BLOGE(sc, "proper val not read from HC IGU!\n"); 10872 } 10873 } 10874 10875 static void 10876 bxe_igu_int_disable(struct bxe_softc *sc) 10877 { 10878 uint32_t val = REG_RD(sc, IGU_REG_PF_CONFIGURATION); 10879 10880 val &= ~(IGU_PF_CONF_MSI_MSIX_EN | 10881 IGU_PF_CONF_INT_LINE_EN | 10882 IGU_PF_CONF_ATTN_BIT_EN); 10883 10884 BLOGD(sc, DBG_INTR, "write %x to IGU\n", val); 10885 10886 /* flush all outstanding writes */ 10887 mb(); 10888 10889 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val); 10890 if (REG_RD(sc, IGU_REG_PF_CONFIGURATION) != val) { 10891 BLOGE(sc, "proper val not read from IGU!\n"); 10892 } 10893 } 10894 10895 static void 10896 bxe_int_disable(struct bxe_softc *sc) 10897 { 10898 if (sc->devinfo.int_block == INT_BLOCK_HC) { 10899 bxe_hc_int_disable(sc); 10900 } else { 10901 bxe_igu_int_disable(sc); 10902 } 10903 } 10904 10905 static void 10906 bxe_nic_init(struct bxe_softc *sc, 10907 int load_code) 10908 { 10909 int i; 10910 10911 for (i = 0; i < sc->num_queues; i++) { 10912 bxe_init_eth_fp(sc, i); 10913 } 10914 10915 rmb(); /* ensure status block indices were read */ 10916 10917 bxe_init_rx_rings(sc); 10918 bxe_init_tx_rings(sc); 10919 10920 if (IS_VF(sc)) { 10921 return; 10922 } 10923 10924 /* initialize MOD_ABS interrupts */ 10925 elink_init_mod_abs_int(sc, &sc->link_vars, 10926 sc->devinfo.chip_id, 10927 sc->devinfo.shmem_base, 10928 sc->devinfo.shmem2_base, 10929 SC_PORT(sc)); 10930 10931 bxe_init_def_sb(sc); 10932 bxe_update_dsb_idx(sc); 10933 bxe_init_sp_ring(sc); 10934 bxe_init_eq_ring(sc); 10935 bxe_init_internal(sc, load_code); 10936 bxe_pf_init(sc); 10937 bxe_stats_init(sc); 10938 10939 /* flush all before enabling interrupts */ 10940 mb(); 10941 10942 bxe_int_enable(sc); 10943 10944 /* check for SPIO5 */ 10945 bxe_attn_int_deasserted0(sc, 10946 REG_RD(sc, 10947 (MISC_REG_AEU_AFTER_INVERT_1_FUNC_0 + 10948 SC_PORT(sc)*4)) & 10949 AEU_INPUTS_ATTN_BITS_SPIO5); 10950 } 10951 10952 static inline void 10953 bxe_init_objs(struct bxe_softc *sc) 10954 { 10955 /* mcast rules must be added to tx if tx switching is enabled */ 10956 ecore_obj_type o_type = 10957 (sc->flags & BXE_TX_SWITCHING) ? ECORE_OBJ_TYPE_RX_TX : 10958 ECORE_OBJ_TYPE_RX; 10959 10960 /* RX_MODE controlling object */ 10961 ecore_init_rx_mode_obj(sc, &sc->rx_mode_obj); 10962 10963 /* multicast configuration controlling object */ 10964 ecore_init_mcast_obj(sc, 10965 &sc->mcast_obj, 10966 sc->fp[0].cl_id, 10967 sc->fp[0].index, 10968 SC_FUNC(sc), 10969 SC_FUNC(sc), 10970 BXE_SP(sc, mcast_rdata), 10971 BXE_SP_MAPPING(sc, mcast_rdata), 10972 ECORE_FILTER_MCAST_PENDING, 10973 &sc->sp_state, 10974 o_type); 10975 10976 /* Setup CAM credit pools */ 10977 ecore_init_mac_credit_pool(sc, 10978 &sc->macs_pool, 10979 SC_FUNC(sc), 10980 CHIP_IS_E1x(sc) ? VNICS_PER_PORT(sc) : 10981 VNICS_PER_PATH(sc)); 10982 10983 ecore_init_vlan_credit_pool(sc, 10984 &sc->vlans_pool, 10985 SC_ABS_FUNC(sc) >> 1, 10986 CHIP_IS_E1x(sc) ? VNICS_PER_PORT(sc) : 10987 VNICS_PER_PATH(sc)); 10988 10989 /* RSS configuration object */ 10990 ecore_init_rss_config_obj(sc, 10991 &sc->rss_conf_obj, 10992 sc->fp[0].cl_id, 10993 sc->fp[0].index, 10994 SC_FUNC(sc), 10995 SC_FUNC(sc), 10996 BXE_SP(sc, rss_rdata), 10997 BXE_SP_MAPPING(sc, rss_rdata), 10998 ECORE_FILTER_RSS_CONF_PENDING, 10999 &sc->sp_state, ECORE_OBJ_TYPE_RX); 11000 } 11001 11002 /* 11003 * Initialize the function. This must be called before sending CLIENT_SETUP 11004 * for the first client. 11005 */ 11006 static inline int 11007 bxe_func_start(struct bxe_softc *sc) 11008 { 11009 struct ecore_func_state_params func_params = { NULL }; 11010 struct ecore_func_start_params *start_params = &func_params.params.start; 11011 11012 /* Prepare parameters for function state transitions */ 11013 bit_set(&func_params.ramrod_flags, RAMROD_COMP_WAIT); 11014 11015 func_params.f_obj = &sc->func_obj; 11016 func_params.cmd = ECORE_F_CMD_START; 11017 11018 /* Function parameters */ 11019 start_params->mf_mode = sc->devinfo.mf_info.mf_mode; 11020 start_params->sd_vlan_tag = OVLAN(sc); 11021 11022 if (CHIP_IS_E2(sc) || CHIP_IS_E3(sc)) { 11023 start_params->network_cos_mode = STATIC_COS; 11024 } else { /* CHIP_IS_E1X */ 11025 start_params->network_cos_mode = FW_WRR; 11026 } 11027 11028 start_params->gre_tunnel_mode = 0; 11029 start_params->gre_tunnel_rss = 0; 11030 11031 return (ecore_func_state_change(sc, &func_params)); 11032 } 11033 11034 static int 11035 bxe_set_power_state(struct bxe_softc *sc, 11036 uint8_t state) 11037 { 11038 uint16_t pmcsr; 11039 11040 /* If there is no power capability, silently succeed */ 11041 if (!(sc->devinfo.pcie_cap_flags & BXE_PM_CAPABLE_FLAG)) { 11042 BLOGW(sc, "No power capability\n"); 11043 return (0); 11044 } 11045 11046 pmcsr = pci_read_config(sc->dev, 11047 (sc->devinfo.pcie_pm_cap_reg + PCIR_POWER_STATUS), 11048 2); 11049 11050 switch (state) { 11051 case PCI_PM_D0: 11052 pci_write_config(sc->dev, 11053 (sc->devinfo.pcie_pm_cap_reg + PCIR_POWER_STATUS), 11054 ((pmcsr & ~PCIM_PSTAT_DMASK) | PCIM_PSTAT_PME), 2); 11055 11056 if (pmcsr & PCIM_PSTAT_DMASK) { 11057 /* delay required during transition out of D3hot */ 11058 DELAY(20000); 11059 } 11060 11061 break; 11062 11063 case PCI_PM_D3hot: 11064 /* XXX if there are other clients above don't shut down the power */ 11065 11066 /* don't shut down the power for emulation and FPGA */ 11067 if (CHIP_REV_IS_SLOW(sc)) { 11068 return (0); 11069 } 11070 11071 pmcsr &= ~PCIM_PSTAT_DMASK; 11072 pmcsr |= PCIM_PSTAT_D3; 11073 11074 if (sc->wol) { 11075 pmcsr |= PCIM_PSTAT_PMEENABLE; 11076 } 11077 11078 pci_write_config(sc->dev, 11079 (sc->devinfo.pcie_pm_cap_reg + PCIR_POWER_STATUS), 11080 pmcsr, 4); 11081 11082 /* 11083 * No more memory access after this point until device is brought back 11084 * to D0 state. 11085 */ 11086 break; 11087 11088 default: 11089 BLOGE(sc, "Can't support PCI power state = %d\n", state); 11090 return (-1); 11091 } 11092 11093 return (0); 11094 } 11095 11096 11097 /* return true if succeeded to acquire the lock */ 11098 static uint8_t 11099 bxe_trylock_hw_lock(struct bxe_softc *sc, 11100 uint32_t resource) 11101 { 11102 uint32_t lock_status; 11103 uint32_t resource_bit = (1 << resource); 11104 int func = SC_FUNC(sc); 11105 uint32_t hw_lock_control_reg; 11106 11107 BLOGD(sc, DBG_LOAD, "Trying to take a resource lock 0x%x\n", resource); 11108 11109 /* Validating that the resource is within range */ 11110 if (resource > HW_LOCK_MAX_RESOURCE_VALUE) { 11111 BLOGD(sc, DBG_LOAD, 11112 "resource(0x%x) > HW_LOCK_MAX_RESOURCE_VALUE(0x%x)\n", 11113 resource, HW_LOCK_MAX_RESOURCE_VALUE); 11114 return (FALSE); 11115 } 11116 11117 if (func <= 5) { 11118 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_1 + func*8); 11119 } else { 11120 hw_lock_control_reg = (MISC_REG_DRIVER_CONTROL_7 + (func - 6)*8); 11121 } 11122 11123 /* try to acquire the lock */ 11124 REG_WR(sc, hw_lock_control_reg + 4, resource_bit); 11125 lock_status = REG_RD(sc, hw_lock_control_reg); 11126 if (lock_status & resource_bit) { 11127 return (TRUE); 11128 } 11129 11130 BLOGE(sc, "Failed to get a resource lock 0x%x\n", resource); 11131 11132 return (FALSE); 11133 } 11134 11135 /* 11136 * Get the recovery leader resource id according to the engine this function 11137 * belongs to. Currently only only 2 engines is supported. 11138 */ 11139 static int 11140 bxe_get_leader_lock_resource(struct bxe_softc *sc) 11141 { 11142 if (SC_PATH(sc)) { 11143 return (HW_LOCK_RESOURCE_RECOVERY_LEADER_1); 11144 } else { 11145 return (HW_LOCK_RESOURCE_RECOVERY_LEADER_0); 11146 } 11147 } 11148 11149 /* try to acquire a leader lock for current engine */ 11150 static uint8_t 11151 bxe_trylock_leader_lock(struct bxe_softc *sc) 11152 { 11153 return (bxe_trylock_hw_lock(sc, bxe_get_leader_lock_resource(sc))); 11154 } 11155 11156 static int 11157 bxe_release_leader_lock(struct bxe_softc *sc) 11158 { 11159 return (bxe_release_hw_lock(sc, bxe_get_leader_lock_resource(sc))); 11160 } 11161 11162 /* close gates #2, #3 and #4 */ 11163 static void 11164 bxe_set_234_gates(struct bxe_softc *sc, 11165 uint8_t close) 11166 { 11167 uint32_t val; 11168 11169 /* gates #2 and #4a are closed/opened for "not E1" only */ 11170 if (!CHIP_IS_E1(sc)) { 11171 /* #4 */ 11172 REG_WR(sc, PXP_REG_HST_DISCARD_DOORBELLS, !!close); 11173 /* #2 */ 11174 REG_WR(sc, PXP_REG_HST_DISCARD_INTERNAL_WRITES, !!close); 11175 } 11176 11177 /* #3 */ 11178 if (CHIP_IS_E1x(sc)) { 11179 /* prevent interrupts from HC on both ports */ 11180 val = REG_RD(sc, HC_REG_CONFIG_1); 11181 REG_WR(sc, HC_REG_CONFIG_1, 11182 (!close) ? (val | HC_CONFIG_1_REG_BLOCK_DISABLE_1) : 11183 (val & ~(uint32_t)HC_CONFIG_1_REG_BLOCK_DISABLE_1)); 11184 11185 val = REG_RD(sc, HC_REG_CONFIG_0); 11186 REG_WR(sc, HC_REG_CONFIG_0, 11187 (!close) ? (val | HC_CONFIG_0_REG_BLOCK_DISABLE_0) : 11188 (val & ~(uint32_t)HC_CONFIG_0_REG_BLOCK_DISABLE_0)); 11189 } else { 11190 /* Prevent incomming interrupts in IGU */ 11191 val = REG_RD(sc, IGU_REG_BLOCK_CONFIGURATION); 11192 11193 REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION, 11194 (!close) ? 11195 (val | IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE) : 11196 (val & ~(uint32_t)IGU_BLOCK_CONFIGURATION_REG_BLOCK_ENABLE)); 11197 } 11198 11199 BLOGD(sc, DBG_LOAD, "%s gates #2, #3 and #4\n", 11200 close ? "closing" : "opening"); 11201 11202 wmb(); 11203 } 11204 11205 /* poll for pending writes bit, it should get cleared in no more than 1s */ 11206 static int 11207 bxe_er_poll_igu_vq(struct bxe_softc *sc) 11208 { 11209 uint32_t cnt = 1000; 11210 uint32_t pend_bits = 0; 11211 11212 do { 11213 pend_bits = REG_RD(sc, IGU_REG_PENDING_BITS_STATUS); 11214 11215 if (pend_bits == 0) { 11216 break; 11217 } 11218 11219 DELAY(1000); 11220 } while (--cnt > 0); 11221 11222 if (cnt == 0) { 11223 BLOGE(sc, "Still pending IGU requests bits=0x%08x!\n", pend_bits); 11224 return (-1); 11225 } 11226 11227 return (0); 11228 } 11229 11230 #define SHARED_MF_CLP_MAGIC 0x80000000 /* 'magic' bit */ 11231 11232 static void 11233 bxe_clp_reset_prep(struct bxe_softc *sc, 11234 uint32_t *magic_val) 11235 { 11236 /* Do some magic... */ 11237 uint32_t val = MFCFG_RD(sc, shared_mf_config.clp_mb); 11238 *magic_val = val & SHARED_MF_CLP_MAGIC; 11239 MFCFG_WR(sc, shared_mf_config.clp_mb, val | SHARED_MF_CLP_MAGIC); 11240 } 11241 11242 /* restore the value of the 'magic' bit */ 11243 static void 11244 bxe_clp_reset_done(struct bxe_softc *sc, 11245 uint32_t magic_val) 11246 { 11247 /* Restore the 'magic' bit value... */ 11248 uint32_t val = MFCFG_RD(sc, shared_mf_config.clp_mb); 11249 MFCFG_WR(sc, shared_mf_config.clp_mb, 11250 (val & (~SHARED_MF_CLP_MAGIC)) | magic_val); 11251 } 11252 11253 /* prepare for MCP reset, takes care of CLP configurations */ 11254 static void 11255 bxe_reset_mcp_prep(struct bxe_softc *sc, 11256 uint32_t *magic_val) 11257 { 11258 uint32_t shmem; 11259 uint32_t validity_offset; 11260 11261 /* set `magic' bit in order to save MF config */ 11262 if (!CHIP_IS_E1(sc)) { 11263 bxe_clp_reset_prep(sc, magic_val); 11264 } 11265 11266 /* get shmem offset */ 11267 shmem = REG_RD(sc, MISC_REG_SHARED_MEM_ADDR); 11268 validity_offset = 11269 offsetof(struct shmem_region, validity_map[SC_PORT(sc)]); 11270 11271 /* Clear validity map flags */ 11272 if (shmem > 0) { 11273 REG_WR(sc, shmem + validity_offset, 0); 11274 } 11275 } 11276 11277 #define MCP_TIMEOUT 5000 /* 5 seconds (in ms) */ 11278 #define MCP_ONE_TIMEOUT 100 /* 100 ms */ 11279 11280 static void 11281 bxe_mcp_wait_one(struct bxe_softc *sc) 11282 { 11283 /* special handling for emulation and FPGA (10 times longer) */ 11284 if (CHIP_REV_IS_SLOW(sc)) { 11285 DELAY((MCP_ONE_TIMEOUT*10) * 1000); 11286 } else { 11287 DELAY((MCP_ONE_TIMEOUT) * 1000); 11288 } 11289 } 11290 11291 /* initialize shmem_base and waits for validity signature to appear */ 11292 static int 11293 bxe_init_shmem(struct bxe_softc *sc) 11294 { 11295 int cnt = 0; 11296 uint32_t val = 0; 11297 11298 do { 11299 sc->devinfo.shmem_base = 11300 sc->link_params.shmem_base = 11301 REG_RD(sc, MISC_REG_SHARED_MEM_ADDR); 11302 11303 if (sc->devinfo.shmem_base) { 11304 val = SHMEM_RD(sc, validity_map[SC_PORT(sc)]); 11305 if (val & SHR_MEM_VALIDITY_MB) 11306 return (0); 11307 } 11308 11309 bxe_mcp_wait_one(sc); 11310 11311 } while (cnt++ < (MCP_TIMEOUT / MCP_ONE_TIMEOUT)); 11312 11313 BLOGE(sc, "BAD MCP validity signature\n"); 11314 11315 return (-1); 11316 } 11317 11318 static int 11319 bxe_reset_mcp_comp(struct bxe_softc *sc, 11320 uint32_t magic_val) 11321 { 11322 int rc = bxe_init_shmem(sc); 11323 11324 /* Restore the `magic' bit value */ 11325 if (!CHIP_IS_E1(sc)) { 11326 bxe_clp_reset_done(sc, magic_val); 11327 } 11328 11329 return (rc); 11330 } 11331 11332 static void 11333 bxe_pxp_prep(struct bxe_softc *sc) 11334 { 11335 if (!CHIP_IS_E1(sc)) { 11336 REG_WR(sc, PXP2_REG_RD_START_INIT, 0); 11337 REG_WR(sc, PXP2_REG_RQ_RBC_DONE, 0); 11338 wmb(); 11339 } 11340 } 11341 11342 /* 11343 * Reset the whole chip except for: 11344 * - PCIE core 11345 * - PCI Glue, PSWHST, PXP/PXP2 RF (all controlled by one reset bit) 11346 * - IGU 11347 * - MISC (including AEU) 11348 * - GRC 11349 * - RBCN, RBCP 11350 */ 11351 static void 11352 bxe_process_kill_chip_reset(struct bxe_softc *sc, 11353 uint8_t global) 11354 { 11355 uint32_t not_reset_mask1, reset_mask1, not_reset_mask2, reset_mask2; 11356 uint32_t global_bits2, stay_reset2; 11357 11358 /* 11359 * Bits that have to be set in reset_mask2 if we want to reset 'global' 11360 * (per chip) blocks. 11361 */ 11362 global_bits2 = 11363 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CPU | 11364 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_CMN_CORE; 11365 11366 /* 11367 * Don't reset the following blocks. 11368 * Important: per port blocks (such as EMAC, BMAC, UMAC) can't be 11369 * reset, as in 4 port device they might still be owned 11370 * by the MCP (there is only one leader per path). 11371 */ 11372 not_reset_mask1 = 11373 MISC_REGISTERS_RESET_REG_1_RST_HC | 11374 MISC_REGISTERS_RESET_REG_1_RST_PXPV | 11375 MISC_REGISTERS_RESET_REG_1_RST_PXP; 11376 11377 not_reset_mask2 = 11378 MISC_REGISTERS_RESET_REG_2_RST_PCI_MDIO | 11379 MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE | 11380 MISC_REGISTERS_RESET_REG_2_RST_EMAC1_HARD_CORE | 11381 MISC_REGISTERS_RESET_REG_2_RST_MISC_CORE | 11382 MISC_REGISTERS_RESET_REG_2_RST_RBCN | 11383 MISC_REGISTERS_RESET_REG_2_RST_GRC | 11384 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_RESET_REG_HARD_CORE | 11385 MISC_REGISTERS_RESET_REG_2_RST_MCP_N_HARD_CORE_RST_B | 11386 MISC_REGISTERS_RESET_REG_2_RST_ATC | 11387 MISC_REGISTERS_RESET_REG_2_PGLC | 11388 MISC_REGISTERS_RESET_REG_2_RST_BMAC0 | 11389 MISC_REGISTERS_RESET_REG_2_RST_BMAC1 | 11390 MISC_REGISTERS_RESET_REG_2_RST_EMAC0 | 11391 MISC_REGISTERS_RESET_REG_2_RST_EMAC1 | 11392 MISC_REGISTERS_RESET_REG_2_UMAC0 | 11393 MISC_REGISTERS_RESET_REG_2_UMAC1; 11394 11395 /* 11396 * Keep the following blocks in reset: 11397 * - all xxMACs are handled by the elink code. 11398 */ 11399 stay_reset2 = 11400 MISC_REGISTERS_RESET_REG_2_XMAC | 11401 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT; 11402 11403 /* Full reset masks according to the chip */ 11404 reset_mask1 = 0xffffffff; 11405 11406 if (CHIP_IS_E1(sc)) 11407 reset_mask2 = 0xffff; 11408 else if (CHIP_IS_E1H(sc)) 11409 reset_mask2 = 0x1ffff; 11410 else if (CHIP_IS_E2(sc)) 11411 reset_mask2 = 0xfffff; 11412 else /* CHIP_IS_E3 */ 11413 reset_mask2 = 0x3ffffff; 11414 11415 /* Don't reset global blocks unless we need to */ 11416 if (!global) 11417 reset_mask2 &= ~global_bits2; 11418 11419 /* 11420 * In case of attention in the QM, we need to reset PXP 11421 * (MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR) before QM 11422 * because otherwise QM reset would release 'close the gates' shortly 11423 * before resetting the PXP, then the PSWRQ would send a write 11424 * request to PGLUE. Then when PXP is reset, PGLUE would try to 11425 * read the payload data from PSWWR, but PSWWR would not 11426 * respond. The write queue in PGLUE would stuck, dmae commands 11427 * would not return. Therefore it's important to reset the second 11428 * reset register (containing the 11429 * MISC_REGISTERS_RESET_REG_2_RST_PXP_RQ_RD_WR bit) before the 11430 * first one (containing the MISC_REGISTERS_RESET_REG_1_RST_QM 11431 * bit). 11432 */ 11433 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR, 11434 reset_mask2 & (~not_reset_mask2)); 11435 11436 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 11437 reset_mask1 & (~not_reset_mask1)); 11438 11439 mb(); 11440 wmb(); 11441 11442 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET, 11443 reset_mask2 & (~stay_reset2)); 11444 11445 mb(); 11446 wmb(); 11447 11448 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, reset_mask1); 11449 wmb(); 11450 } 11451 11452 static int 11453 bxe_process_kill(struct bxe_softc *sc, 11454 uint8_t global) 11455 { 11456 int cnt = 1000; 11457 uint32_t val = 0; 11458 uint32_t sr_cnt, blk_cnt, port_is_idle_0, port_is_idle_1, pgl_exp_rom2; 11459 uint32_t tags_63_32 = 0; 11460 11461 /* Empty the Tetris buffer, wait for 1s */ 11462 do { 11463 sr_cnt = REG_RD(sc, PXP2_REG_RD_SR_CNT); 11464 blk_cnt = REG_RD(sc, PXP2_REG_RD_BLK_CNT); 11465 port_is_idle_0 = REG_RD(sc, PXP2_REG_RD_PORT_IS_IDLE_0); 11466 port_is_idle_1 = REG_RD(sc, PXP2_REG_RD_PORT_IS_IDLE_1); 11467 pgl_exp_rom2 = REG_RD(sc, PXP2_REG_PGL_EXP_ROM2); 11468 if (CHIP_IS_E3(sc)) { 11469 tags_63_32 = REG_RD(sc, PGLUE_B_REG_TAGS_63_32); 11470 } 11471 11472 if ((sr_cnt == 0x7e) && (blk_cnt == 0xa0) && 11473 ((port_is_idle_0 & 0x1) == 0x1) && 11474 ((port_is_idle_1 & 0x1) == 0x1) && 11475 (pgl_exp_rom2 == 0xffffffff) && 11476 (!CHIP_IS_E3(sc) || (tags_63_32 == 0xffffffff))) 11477 break; 11478 DELAY(1000); 11479 } while (cnt-- > 0); 11480 11481 if (cnt <= 0) { 11482 BLOGE(sc, "ERROR: Tetris buffer didn't get empty or there " 11483 "are still outstanding read requests after 1s! " 11484 "sr_cnt=0x%08x, blk_cnt=0x%08x, port_is_idle_0=0x%08x, " 11485 "port_is_idle_1=0x%08x, pgl_exp_rom2=0x%08x\n", 11486 sr_cnt, blk_cnt, port_is_idle_0, 11487 port_is_idle_1, pgl_exp_rom2); 11488 return (-1); 11489 } 11490 11491 mb(); 11492 11493 /* Close gates #2, #3 and #4 */ 11494 bxe_set_234_gates(sc, TRUE); 11495 11496 /* Poll for IGU VQs for 57712 and newer chips */ 11497 if (!CHIP_IS_E1x(sc) && bxe_er_poll_igu_vq(sc)) { 11498 return (-1); 11499 } 11500 11501 /* XXX indicate that "process kill" is in progress to MCP */ 11502 11503 /* clear "unprepared" bit */ 11504 REG_WR(sc, MISC_REG_UNPREPARED, 0); 11505 mb(); 11506 11507 /* Make sure all is written to the chip before the reset */ 11508 wmb(); 11509 11510 /* 11511 * Wait for 1ms to empty GLUE and PCI-E core queues, 11512 * PSWHST, GRC and PSWRD Tetris buffer. 11513 */ 11514 DELAY(1000); 11515 11516 /* Prepare to chip reset: */ 11517 /* MCP */ 11518 if (global) { 11519 bxe_reset_mcp_prep(sc, &val); 11520 } 11521 11522 /* PXP */ 11523 bxe_pxp_prep(sc); 11524 mb(); 11525 11526 /* reset the chip */ 11527 bxe_process_kill_chip_reset(sc, global); 11528 mb(); 11529 11530 /* Recover after reset: */ 11531 /* MCP */ 11532 if (global && bxe_reset_mcp_comp(sc, val)) { 11533 return (-1); 11534 } 11535 11536 /* XXX add resetting the NO_MCP mode DB here */ 11537 11538 /* Open the gates #2, #3 and #4 */ 11539 bxe_set_234_gates(sc, FALSE); 11540 11541 /* XXX 11542 * IGU/AEU preparation bring back the AEU/IGU to a reset state 11543 * re-enable attentions 11544 */ 11545 11546 return (0); 11547 } 11548 11549 static int 11550 bxe_leader_reset(struct bxe_softc *sc) 11551 { 11552 int rc = 0; 11553 uint8_t global = bxe_reset_is_global(sc); 11554 uint32_t load_code; 11555 11556 /* 11557 * If not going to reset MCP, load "fake" driver to reset HW while 11558 * driver is owner of the HW. 11559 */ 11560 if (!global && !BXE_NOMCP(sc)) { 11561 load_code = bxe_fw_command(sc, DRV_MSG_CODE_LOAD_REQ, 11562 DRV_MSG_CODE_LOAD_REQ_WITH_LFA); 11563 if (!load_code) { 11564 BLOGE(sc, "MCP response failure, aborting\n"); 11565 rc = -1; 11566 goto exit_leader_reset; 11567 } 11568 11569 if ((load_code != FW_MSG_CODE_DRV_LOAD_COMMON_CHIP) && 11570 (load_code != FW_MSG_CODE_DRV_LOAD_COMMON)) { 11571 BLOGE(sc, "MCP unexpected response, aborting\n"); 11572 rc = -1; 11573 goto exit_leader_reset2; 11574 } 11575 11576 load_code = bxe_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0); 11577 if (!load_code) { 11578 BLOGE(sc, "MCP response failure, aborting\n"); 11579 rc = -1; 11580 goto exit_leader_reset2; 11581 } 11582 } 11583 11584 /* try to recover after the failure */ 11585 if (bxe_process_kill(sc, global)) { 11586 BLOGE(sc, "Something bad occurred on engine %d!\n", SC_PATH(sc)); 11587 rc = -1; 11588 goto exit_leader_reset2; 11589 } 11590 11591 /* 11592 * Clear the RESET_IN_PROGRESS and RESET_GLOBAL bits and update the driver 11593 * state. 11594 */ 11595 bxe_set_reset_done(sc); 11596 if (global) { 11597 bxe_clear_reset_global(sc); 11598 } 11599 11600 exit_leader_reset2: 11601 11602 /* unload "fake driver" if it was loaded */ 11603 if (!global && !BXE_NOMCP(sc)) { 11604 bxe_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0); 11605 bxe_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, 0); 11606 } 11607 11608 exit_leader_reset: 11609 11610 sc->is_leader = 0; 11611 bxe_release_leader_lock(sc); 11612 11613 mb(); 11614 return (rc); 11615 } 11616 11617 /* 11618 * prepare INIT transition, parameters configured: 11619 * - HC configuration 11620 * - Queue's CDU context 11621 */ 11622 static void 11623 bxe_pf_q_prep_init(struct bxe_softc *sc, 11624 struct bxe_fastpath *fp, 11625 struct ecore_queue_init_params *init_params) 11626 { 11627 uint8_t cos; 11628 int cxt_index, cxt_offset; 11629 11630 bxe_set_bit(ECORE_Q_FLG_HC, &init_params->rx.flags); 11631 bxe_set_bit(ECORE_Q_FLG_HC, &init_params->tx.flags); 11632 11633 bxe_set_bit(ECORE_Q_FLG_HC_EN, &init_params->rx.flags); 11634 bxe_set_bit(ECORE_Q_FLG_HC_EN, &init_params->tx.flags); 11635 11636 /* HC rate */ 11637 init_params->rx.hc_rate = 11638 sc->hc_rx_ticks ? (1000000 / sc->hc_rx_ticks) : 0; 11639 init_params->tx.hc_rate = 11640 sc->hc_tx_ticks ? (1000000 / sc->hc_tx_ticks) : 0; 11641 11642 /* FW SB ID */ 11643 init_params->rx.fw_sb_id = init_params->tx.fw_sb_id = fp->fw_sb_id; 11644 11645 /* CQ index among the SB indices */ 11646 init_params->rx.sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS; 11647 init_params->tx.sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS; 11648 11649 /* set maximum number of COSs supported by this queue */ 11650 init_params->max_cos = sc->max_cos; 11651 11652 BLOGD(sc, DBG_LOAD, "fp %d setting queue params max cos to %d\n", 11653 fp->index, init_params->max_cos); 11654 11655 /* set the context pointers queue object */ 11656 for (cos = FIRST_TX_COS_INDEX; cos < init_params->max_cos; cos++) { 11657 /* XXX change index/cid here if ever support multiple tx CoS */ 11658 /* fp->txdata[cos]->cid */ 11659 cxt_index = fp->index / ILT_PAGE_CIDS; 11660 cxt_offset = fp->index - (cxt_index * ILT_PAGE_CIDS); 11661 init_params->cxts[cos] = &sc->context[cxt_index].vcxt[cxt_offset].eth; 11662 } 11663 } 11664 11665 /* set flags that are common for the Tx-only and not normal connections */ 11666 static unsigned long 11667 bxe_get_common_flags(struct bxe_softc *sc, 11668 struct bxe_fastpath *fp, 11669 uint8_t zero_stats) 11670 { 11671 unsigned long flags = 0; 11672 11673 /* PF driver will always initialize the Queue to an ACTIVE state */ 11674 bxe_set_bit(ECORE_Q_FLG_ACTIVE, &flags); 11675 11676 /* 11677 * tx only connections collect statistics (on the same index as the 11678 * parent connection). The statistics are zeroed when the parent 11679 * connection is initialized. 11680 */ 11681 11682 bxe_set_bit(ECORE_Q_FLG_STATS, &flags); 11683 if (zero_stats) { 11684 bxe_set_bit(ECORE_Q_FLG_ZERO_STATS, &flags); 11685 } 11686 11687 /* 11688 * tx only connections can support tx-switching, though their 11689 * CoS-ness doesn't survive the loopback 11690 */ 11691 if (sc->flags & BXE_TX_SWITCHING) { 11692 bxe_set_bit(ECORE_Q_FLG_TX_SWITCH, &flags); 11693 } 11694 11695 bxe_set_bit(ECORE_Q_FLG_PCSUM_ON_PKT, &flags); 11696 11697 return (flags); 11698 } 11699 11700 static unsigned long 11701 bxe_get_q_flags(struct bxe_softc *sc, 11702 struct bxe_fastpath *fp, 11703 uint8_t leading) 11704 { 11705 unsigned long flags = 0; 11706 11707 if (IS_MF_SD(sc)) { 11708 bxe_set_bit(ECORE_Q_FLG_OV, &flags); 11709 } 11710 11711 if (sc->ifnet->if_capenable & IFCAP_LRO) { 11712 bxe_set_bit(ECORE_Q_FLG_TPA, &flags); 11713 bxe_set_bit(ECORE_Q_FLG_TPA_IPV6, &flags); 11714 #if 0 11715 if (fp->mode == TPA_MODE_GRO) 11716 __set_bit(ECORE_Q_FLG_TPA_GRO, &flags); 11717 #endif 11718 } 11719 11720 if (leading) { 11721 bxe_set_bit(ECORE_Q_FLG_LEADING_RSS, &flags); 11722 bxe_set_bit(ECORE_Q_FLG_MCAST, &flags); 11723 } 11724 11725 bxe_set_bit(ECORE_Q_FLG_VLAN, &flags); 11726 11727 #if 0 11728 /* configure silent vlan removal */ 11729 if (IS_MF_AFEX(sc)) { 11730 bxe_set_bit(ECORE_Q_FLG_SILENT_VLAN_REM, &flags); 11731 } 11732 #endif 11733 11734 /* merge with common flags */ 11735 return (flags | bxe_get_common_flags(sc, fp, TRUE)); 11736 } 11737 11738 static void 11739 bxe_pf_q_prep_general(struct bxe_softc *sc, 11740 struct bxe_fastpath *fp, 11741 struct ecore_general_setup_params *gen_init, 11742 uint8_t cos) 11743 { 11744 gen_init->stat_id = bxe_stats_id(fp); 11745 gen_init->spcl_id = fp->cl_id; 11746 gen_init->mtu = sc->mtu; 11747 gen_init->cos = cos; 11748 } 11749 11750 static void 11751 bxe_pf_rx_q_prep(struct bxe_softc *sc, 11752 struct bxe_fastpath *fp, 11753 struct rxq_pause_params *pause, 11754 struct ecore_rxq_setup_params *rxq_init) 11755 { 11756 uint8_t max_sge = 0; 11757 uint16_t sge_sz = 0; 11758 uint16_t tpa_agg_size = 0; 11759 11760 if (sc->ifnet->if_capenable & IFCAP_LRO) { 11761 pause->sge_th_lo = SGE_TH_LO(sc); 11762 pause->sge_th_hi = SGE_TH_HI(sc); 11763 11764 /* validate SGE ring has enough to cross high threshold */ 11765 if (sc->dropless_fc && 11766 (pause->sge_th_hi + FW_PREFETCH_CNT) > 11767 (RX_SGE_USABLE_PER_PAGE * RX_SGE_NUM_PAGES)) { 11768 BLOGW(sc, "sge ring threshold limit\n"); 11769 } 11770 11771 /* minimum max_aggregation_size is 2*MTU (two full buffers) */ 11772 tpa_agg_size = (2 * sc->mtu); 11773 if (tpa_agg_size < sc->max_aggregation_size) { 11774 tpa_agg_size = sc->max_aggregation_size; 11775 } 11776 11777 max_sge = SGE_PAGE_ALIGN(sc->mtu) >> SGE_PAGE_SHIFT; 11778 max_sge = ((max_sge + PAGES_PER_SGE - 1) & 11779 (~(PAGES_PER_SGE - 1))) >> PAGES_PER_SGE_SHIFT; 11780 sge_sz = (uint16_t)min(SGE_PAGES, 0xffff); 11781 } 11782 11783 /* pause - not for e1 */ 11784 if (!CHIP_IS_E1(sc)) { 11785 pause->bd_th_lo = BD_TH_LO(sc); 11786 pause->bd_th_hi = BD_TH_HI(sc); 11787 11788 pause->rcq_th_lo = RCQ_TH_LO(sc); 11789 pause->rcq_th_hi = RCQ_TH_HI(sc); 11790 11791 /* validate rings have enough entries to cross high thresholds */ 11792 if (sc->dropless_fc && 11793 pause->bd_th_hi + FW_PREFETCH_CNT > 11794 sc->rx_ring_size) { 11795 BLOGW(sc, "rx bd ring threshold limit\n"); 11796 } 11797 11798 if (sc->dropless_fc && 11799 pause->rcq_th_hi + FW_PREFETCH_CNT > 11800 RCQ_NUM_PAGES * RCQ_USABLE_PER_PAGE) { 11801 BLOGW(sc, "rcq ring threshold limit\n"); 11802 } 11803 11804 pause->pri_map = 1; 11805 } 11806 11807 /* rxq setup */ 11808 rxq_init->dscr_map = fp->rx_dma.paddr; 11809 rxq_init->sge_map = fp->rx_sge_dma.paddr; 11810 rxq_init->rcq_map = fp->rcq_dma.paddr; 11811 rxq_init->rcq_np_map = (fp->rcq_dma.paddr + BCM_PAGE_SIZE); 11812 11813 /* 11814 * This should be a maximum number of data bytes that may be 11815 * placed on the BD (not including paddings). 11816 */ 11817 rxq_init->buf_sz = (fp->rx_buf_size - 11818 IP_HEADER_ALIGNMENT_PADDING); 11819 11820 rxq_init->cl_qzone_id = fp->cl_qzone_id; 11821 rxq_init->tpa_agg_sz = tpa_agg_size; 11822 rxq_init->sge_buf_sz = sge_sz; 11823 rxq_init->max_sges_pkt = max_sge; 11824 rxq_init->rss_engine_id = SC_FUNC(sc); 11825 rxq_init->mcast_engine_id = SC_FUNC(sc); 11826 11827 /* 11828 * Maximum number or simultaneous TPA aggregation for this Queue. 11829 * For PF Clients it should be the maximum available number. 11830 * VF driver(s) may want to define it to a smaller value. 11831 */ 11832 rxq_init->max_tpa_queues = MAX_AGG_QS(sc); 11833 11834 rxq_init->cache_line_log = BXE_RX_ALIGN_SHIFT; 11835 rxq_init->fw_sb_id = fp->fw_sb_id; 11836 11837 rxq_init->sb_cq_index = HC_INDEX_ETH_RX_CQ_CONS; 11838 11839 /* 11840 * configure silent vlan removal 11841 * if multi function mode is afex, then mask default vlan 11842 */ 11843 if (IS_MF_AFEX(sc)) { 11844 rxq_init->silent_removal_value = 11845 sc->devinfo.mf_info.afex_def_vlan_tag; 11846 rxq_init->silent_removal_mask = EVL_VLID_MASK; 11847 } 11848 } 11849 11850 static void 11851 bxe_pf_tx_q_prep(struct bxe_softc *sc, 11852 struct bxe_fastpath *fp, 11853 struct ecore_txq_setup_params *txq_init, 11854 uint8_t cos) 11855 { 11856 /* 11857 * XXX If multiple CoS is ever supported then each fastpath structure 11858 * will need to maintain tx producer/consumer/dma/etc values *per* CoS. 11859 * fp->txdata[cos]->tx_dma.paddr; 11860 */ 11861 txq_init->dscr_map = fp->tx_dma.paddr; 11862 txq_init->sb_cq_index = HC_INDEX_ETH_FIRST_TX_CQ_CONS + cos; 11863 txq_init->traffic_type = LLFC_TRAFFIC_TYPE_NW; 11864 txq_init->fw_sb_id = fp->fw_sb_id; 11865 11866 /* 11867 * set the TSS leading client id for TX classfication to the 11868 * leading RSS client id 11869 */ 11870 txq_init->tss_leading_cl_id = BXE_FP(sc, 0, cl_id); 11871 } 11872 11873 /* 11874 * This function performs 2 steps in a queue state machine: 11875 * 1) RESET->INIT 11876 * 2) INIT->SETUP 11877 */ 11878 static int 11879 bxe_setup_queue(struct bxe_softc *sc, 11880 struct bxe_fastpath *fp, 11881 uint8_t leading) 11882 { 11883 struct ecore_queue_state_params q_params = { NULL }; 11884 struct ecore_queue_setup_params *setup_params = 11885 &q_params.params.setup; 11886 #if 0 11887 struct ecore_queue_setup_tx_only_params *tx_only_params = 11888 &q_params.params.tx_only; 11889 uint8_t tx_index; 11890 #endif 11891 int rc; 11892 11893 BLOGD(sc, DBG_LOAD, "setting up queue %d\n", fp->index); 11894 11895 bxe_ack_sb(sc, fp->igu_sb_id, USTORM_ID, 0, IGU_INT_ENABLE, 0); 11896 11897 q_params.q_obj = &BXE_SP_OBJ(sc, fp).q_obj; 11898 11899 /* we want to wait for completion in this context */ 11900 bxe_set_bit(RAMROD_COMP_WAIT, &q_params.ramrod_flags); 11901 11902 /* prepare the INIT parameters */ 11903 bxe_pf_q_prep_init(sc, fp, &q_params.params.init); 11904 11905 /* Set the command */ 11906 q_params.cmd = ECORE_Q_CMD_INIT; 11907 11908 /* Change the state to INIT */ 11909 rc = ecore_queue_state_change(sc, &q_params); 11910 if (rc) { 11911 BLOGE(sc, "Queue(%d) INIT failed\n", fp->index); 11912 return (rc); 11913 } 11914 11915 BLOGD(sc, DBG_LOAD, "init complete\n"); 11916 11917 /* now move the Queue to the SETUP state */ 11918 memset(setup_params, 0, sizeof(*setup_params)); 11919 11920 /* set Queue flags */ 11921 setup_params->flags = bxe_get_q_flags(sc, fp, leading); 11922 11923 /* set general SETUP parameters */ 11924 bxe_pf_q_prep_general(sc, fp, &setup_params->gen_params, 11925 FIRST_TX_COS_INDEX); 11926 11927 bxe_pf_rx_q_prep(sc, fp, 11928 &setup_params->pause_params, 11929 &setup_params->rxq_params); 11930 11931 bxe_pf_tx_q_prep(sc, fp, 11932 &setup_params->txq_params, 11933 FIRST_TX_COS_INDEX); 11934 11935 /* Set the command */ 11936 q_params.cmd = ECORE_Q_CMD_SETUP; 11937 11938 /* change the state to SETUP */ 11939 rc = ecore_queue_state_change(sc, &q_params); 11940 if (rc) { 11941 BLOGE(sc, "Queue(%d) SETUP failed\n", fp->index); 11942 return (rc); 11943 } 11944 11945 #if 0 11946 /* loop through the relevant tx-only indices */ 11947 for (tx_index = FIRST_TX_ONLY_COS_INDEX; 11948 tx_index < sc->max_cos; 11949 tx_index++) { 11950 /* prepare and send tx-only ramrod*/ 11951 rc = bxe_setup_tx_only(sc, fp, &q_params, 11952 tx_only_params, tx_index, leading); 11953 if (rc) { 11954 BLOGE(sc, "Queue(%d.%d) TX_ONLY_SETUP failed\n", 11955 fp->index, tx_index); 11956 return (rc); 11957 } 11958 } 11959 #endif 11960 11961 return (rc); 11962 } 11963 11964 static int 11965 bxe_setup_leading(struct bxe_softc *sc) 11966 { 11967 return (bxe_setup_queue(sc, &sc->fp[0], TRUE)); 11968 } 11969 11970 static int 11971 bxe_config_rss_pf(struct bxe_softc *sc, 11972 struct ecore_rss_config_obj *rss_obj, 11973 uint8_t config_hash) 11974 { 11975 struct ecore_config_rss_params params = { NULL }; 11976 int i; 11977 11978 /* 11979 * Although RSS is meaningless when there is a single HW queue we 11980 * still need it enabled in order to have HW Rx hash generated. 11981 */ 11982 11983 params.rss_obj = rss_obj; 11984 11985 bxe_set_bit(RAMROD_COMP_WAIT, ¶ms.ramrod_flags); 11986 11987 bxe_set_bit(ECORE_RSS_MODE_REGULAR, ¶ms.rss_flags); 11988 11989 /* RSS configuration */ 11990 bxe_set_bit(ECORE_RSS_IPV4, ¶ms.rss_flags); 11991 bxe_set_bit(ECORE_RSS_IPV4_TCP, ¶ms.rss_flags); 11992 bxe_set_bit(ECORE_RSS_IPV6, ¶ms.rss_flags); 11993 bxe_set_bit(ECORE_RSS_IPV6_TCP, ¶ms.rss_flags); 11994 if (rss_obj->udp_rss_v4) { 11995 bxe_set_bit(ECORE_RSS_IPV4_UDP, ¶ms.rss_flags); 11996 } 11997 if (rss_obj->udp_rss_v6) { 11998 bxe_set_bit(ECORE_RSS_IPV6_UDP, ¶ms.rss_flags); 11999 } 12000 12001 /* Hash bits */ 12002 params.rss_result_mask = MULTI_MASK; 12003 12004 memcpy(params.ind_table, rss_obj->ind_table, sizeof(params.ind_table)); 12005 12006 if (config_hash) { 12007 /* RSS keys */ 12008 for (i = 0; i < sizeof(params.rss_key) / 4; i++) { 12009 params.rss_key[i] = arc4random(); 12010 } 12011 12012 bxe_set_bit(ECORE_RSS_SET_SRCH, ¶ms.rss_flags); 12013 } 12014 12015 return (ecore_config_rss(sc, ¶ms)); 12016 } 12017 12018 static int 12019 bxe_config_rss_eth(struct bxe_softc *sc, 12020 uint8_t config_hash) 12021 { 12022 return (bxe_config_rss_pf(sc, &sc->rss_conf_obj, config_hash)); 12023 } 12024 12025 static int 12026 bxe_init_rss_pf(struct bxe_softc *sc) 12027 { 12028 uint8_t num_eth_queues = BXE_NUM_ETH_QUEUES(sc); 12029 int i; 12030 12031 /* 12032 * Prepare the initial contents of the indirection table if 12033 * RSS is enabled 12034 */ 12035 for (i = 0; i < sizeof(sc->rss_conf_obj.ind_table); i++) { 12036 sc->rss_conf_obj.ind_table[i] = 12037 (sc->fp->cl_id + (i % num_eth_queues)); 12038 } 12039 12040 if (sc->udp_rss) { 12041 sc->rss_conf_obj.udp_rss_v4 = sc->rss_conf_obj.udp_rss_v6 = 1; 12042 } 12043 12044 /* 12045 * For 57710 and 57711 SEARCHER configuration (rss_keys) is 12046 * per-port, so if explicit configuration is needed, do it only 12047 * for a PMF. 12048 * 12049 * For 57712 and newer it's a per-function configuration. 12050 */ 12051 return (bxe_config_rss_eth(sc, sc->port.pmf || !CHIP_IS_E1x(sc))); 12052 } 12053 12054 static int 12055 bxe_set_mac_one(struct bxe_softc *sc, 12056 uint8_t *mac, 12057 struct ecore_vlan_mac_obj *obj, 12058 uint8_t set, 12059 int mac_type, 12060 unsigned long *ramrod_flags) 12061 { 12062 struct ecore_vlan_mac_ramrod_params ramrod_param; 12063 int rc; 12064 12065 memset(&ramrod_param, 0, sizeof(ramrod_param)); 12066 12067 /* fill in general parameters */ 12068 ramrod_param.vlan_mac_obj = obj; 12069 ramrod_param.ramrod_flags = *ramrod_flags; 12070 12071 /* fill a user request section if needed */ 12072 if (!bxe_test_bit(RAMROD_CONT, ramrod_flags)) { 12073 memcpy(ramrod_param.user_req.u.mac.mac, mac, ETH_ALEN); 12074 12075 bxe_set_bit(mac_type, &ramrod_param.user_req.vlan_mac_flags); 12076 12077 /* Set the command: ADD or DEL */ 12078 ramrod_param.user_req.cmd = (set) ? ECORE_VLAN_MAC_ADD : 12079 ECORE_VLAN_MAC_DEL; 12080 } 12081 12082 rc = ecore_config_vlan_mac(sc, &ramrod_param); 12083 12084 if (rc == ECORE_EXISTS) { 12085 BLOGD(sc, DBG_SP, "Failed to schedule ADD operations (EEXIST)\n"); 12086 /* do not treat adding same MAC as error */ 12087 rc = 0; 12088 } else if (rc < 0) { 12089 BLOGE(sc, "%s MAC failed (%d)\n", (set ? "Set" : "Delete"), rc); 12090 } 12091 12092 return (rc); 12093 } 12094 12095 static int 12096 bxe_set_eth_mac(struct bxe_softc *sc, 12097 uint8_t set) 12098 { 12099 unsigned long ramrod_flags = 0; 12100 12101 BLOGD(sc, DBG_LOAD, "Adding Ethernet MAC\n"); 12102 12103 bxe_set_bit(RAMROD_COMP_WAIT, &ramrod_flags); 12104 12105 /* Eth MAC is set on RSS leading client (fp[0]) */ 12106 return (bxe_set_mac_one(sc, sc->link_params.mac_addr, 12107 &sc->sp_objs->mac_obj, 12108 set, ECORE_ETH_MAC, &ramrod_flags)); 12109 } 12110 12111 #if 0 12112 static void 12113 bxe_update_max_mf_config(struct bxe_softc *sc, 12114 uint32_t value) 12115 { 12116 /* load old values */ 12117 uint32_t mf_cfg = sc->devinfo.mf_info.mf_config[SC_VN(sc)]; 12118 12119 if (value != bxe_extract_max_cfg(sc, mf_cfg)) { 12120 /* leave all but MAX value */ 12121 mf_cfg &= ~FUNC_MF_CFG_MAX_BW_MASK; 12122 12123 /* set new MAX value */ 12124 mf_cfg |= ((value << FUNC_MF_CFG_MAX_BW_SHIFT) & 12125 FUNC_MF_CFG_MAX_BW_MASK); 12126 12127 bxe_fw_command(sc, DRV_MSG_CODE_SET_MF_BW, mf_cfg); 12128 } 12129 } 12130 #endif 12131 12132 static int 12133 bxe_get_cur_phy_idx(struct bxe_softc *sc) 12134 { 12135 uint32_t sel_phy_idx = 0; 12136 12137 if (sc->link_params.num_phys <= 1) { 12138 return (ELINK_INT_PHY); 12139 } 12140 12141 if (sc->link_vars.link_up) { 12142 sel_phy_idx = ELINK_EXT_PHY1; 12143 /* In case link is SERDES, check if the ELINK_EXT_PHY2 is the one */ 12144 if ((sc->link_vars.link_status & LINK_STATUS_SERDES_LINK) && 12145 (sc->link_params.phy[ELINK_EXT_PHY2].supported & 12146 ELINK_SUPPORTED_FIBRE)) 12147 sel_phy_idx = ELINK_EXT_PHY2; 12148 } else { 12149 switch (elink_phy_selection(&sc->link_params)) { 12150 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT: 12151 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY: 12152 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY: 12153 sel_phy_idx = ELINK_EXT_PHY1; 12154 break; 12155 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY: 12156 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY: 12157 sel_phy_idx = ELINK_EXT_PHY2; 12158 break; 12159 } 12160 } 12161 12162 return (sel_phy_idx); 12163 } 12164 12165 static int 12166 bxe_get_link_cfg_idx(struct bxe_softc *sc) 12167 { 12168 uint32_t sel_phy_idx = bxe_get_cur_phy_idx(sc); 12169 12170 /* 12171 * The selected activated PHY is always after swapping (in case PHY 12172 * swapping is enabled). So when swapping is enabled, we need to reverse 12173 * the configuration 12174 */ 12175 12176 if (sc->link_params.multi_phy_config & PORT_HW_CFG_PHY_SWAPPED_ENABLED) { 12177 if (sel_phy_idx == ELINK_EXT_PHY1) 12178 sel_phy_idx = ELINK_EXT_PHY2; 12179 else if (sel_phy_idx == ELINK_EXT_PHY2) 12180 sel_phy_idx = ELINK_EXT_PHY1; 12181 } 12182 12183 return (ELINK_LINK_CONFIG_IDX(sel_phy_idx)); 12184 } 12185 12186 static void 12187 bxe_set_requested_fc(struct bxe_softc *sc) 12188 { 12189 /* 12190 * Initialize link parameters structure variables 12191 * It is recommended to turn off RX FC for jumbo frames 12192 * for better performance 12193 */ 12194 if (CHIP_IS_E1x(sc) && (sc->mtu > 5000)) { 12195 sc->link_params.req_fc_auto_adv = ELINK_FLOW_CTRL_TX; 12196 } else { 12197 sc->link_params.req_fc_auto_adv = ELINK_FLOW_CTRL_BOTH; 12198 } 12199 } 12200 12201 static void 12202 bxe_calc_fc_adv(struct bxe_softc *sc) 12203 { 12204 uint8_t cfg_idx = bxe_get_link_cfg_idx(sc); 12205 switch (sc->link_vars.ieee_fc & 12206 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK) { 12207 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE: 12208 default: 12209 sc->port.advertising[cfg_idx] &= ~(ADVERTISED_Asym_Pause | 12210 ADVERTISED_Pause); 12211 break; 12212 12213 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH: 12214 sc->port.advertising[cfg_idx] |= (ADVERTISED_Asym_Pause | 12215 ADVERTISED_Pause); 12216 break; 12217 12218 case MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC: 12219 sc->port.advertising[cfg_idx] |= ADVERTISED_Asym_Pause; 12220 break; 12221 } 12222 } 12223 12224 static uint16_t 12225 bxe_get_mf_speed(struct bxe_softc *sc) 12226 { 12227 uint16_t line_speed = sc->link_vars.line_speed; 12228 if (IS_MF(sc)) { 12229 uint16_t maxCfg = 12230 bxe_extract_max_cfg(sc, sc->devinfo.mf_info.mf_config[SC_VN(sc)]); 12231 12232 /* calculate the current MAX line speed limit for the MF devices */ 12233 if (IS_MF_SI(sc)) { 12234 line_speed = (line_speed * maxCfg) / 100; 12235 } else { /* SD mode */ 12236 uint16_t vn_max_rate = maxCfg * 100; 12237 12238 if (vn_max_rate < line_speed) { 12239 line_speed = vn_max_rate; 12240 } 12241 } 12242 } 12243 12244 return (line_speed); 12245 } 12246 12247 static void 12248 bxe_fill_report_data(struct bxe_softc *sc, 12249 struct bxe_link_report_data *data) 12250 { 12251 uint16_t line_speed = bxe_get_mf_speed(sc); 12252 12253 memset(data, 0, sizeof(*data)); 12254 12255 /* fill the report data with the effective line speed */ 12256 data->line_speed = line_speed; 12257 12258 /* Link is down */ 12259 if (!sc->link_vars.link_up || (sc->flags & BXE_MF_FUNC_DIS)) { 12260 bxe_set_bit(BXE_LINK_REPORT_LINK_DOWN, &data->link_report_flags); 12261 } 12262 12263 /* Full DUPLEX */ 12264 if (sc->link_vars.duplex == DUPLEX_FULL) { 12265 bxe_set_bit(BXE_LINK_REPORT_FULL_DUPLEX, &data->link_report_flags); 12266 } 12267 12268 /* Rx Flow Control is ON */ 12269 if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_RX) { 12270 bxe_set_bit(BXE_LINK_REPORT_RX_FC_ON, &data->link_report_flags); 12271 } 12272 12273 /* Tx Flow Control is ON */ 12274 if (sc->link_vars.flow_ctrl & ELINK_FLOW_CTRL_TX) { 12275 bxe_set_bit(BXE_LINK_REPORT_TX_FC_ON, &data->link_report_flags); 12276 } 12277 } 12278 12279 /* report link status to OS, should be called under phy_lock */ 12280 static void 12281 bxe_link_report_locked(struct bxe_softc *sc) 12282 { 12283 struct bxe_link_report_data cur_data; 12284 12285 /* reread mf_cfg */ 12286 if (IS_PF(sc) && !CHIP_IS_E1(sc)) { 12287 bxe_read_mf_cfg(sc); 12288 } 12289 12290 /* Read the current link report info */ 12291 bxe_fill_report_data(sc, &cur_data); 12292 12293 /* Don't report link down or exactly the same link status twice */ 12294 if (!memcmp(&cur_data, &sc->last_reported_link, sizeof(cur_data)) || 12295 (bxe_test_bit(BXE_LINK_REPORT_LINK_DOWN, 12296 &sc->last_reported_link.link_report_flags) && 12297 bxe_test_bit(BXE_LINK_REPORT_LINK_DOWN, 12298 &cur_data.link_report_flags))) { 12299 return; 12300 } 12301 12302 sc->link_cnt++; 12303 12304 /* report new link params and remember the state for the next time */ 12305 memcpy(&sc->last_reported_link, &cur_data, sizeof(cur_data)); 12306 12307 if (bxe_test_bit(BXE_LINK_REPORT_LINK_DOWN, 12308 &cur_data.link_report_flags)) { 12309 if_link_state_change(sc->ifnet, LINK_STATE_DOWN); 12310 BLOGI(sc, "NIC Link is Down\n"); 12311 } else { 12312 const char *duplex; 12313 const char *flow; 12314 12315 if (bxe_test_and_clear_bit(BXE_LINK_REPORT_FULL_DUPLEX, 12316 &cur_data.link_report_flags)) { 12317 duplex = "full"; 12318 } else { 12319 duplex = "half"; 12320 } 12321 12322 /* 12323 * Handle the FC at the end so that only these flags would be 12324 * possibly set. This way we may easily check if there is no FC 12325 * enabled. 12326 */ 12327 if (cur_data.link_report_flags) { 12328 if (bxe_test_bit(BXE_LINK_REPORT_RX_FC_ON, 12329 &cur_data.link_report_flags) && 12330 bxe_test_bit(BXE_LINK_REPORT_TX_FC_ON, 12331 &cur_data.link_report_flags)) { 12332 flow = "ON - receive & transmit"; 12333 } else if (bxe_test_bit(BXE_LINK_REPORT_RX_FC_ON, 12334 &cur_data.link_report_flags) && 12335 !bxe_test_bit(BXE_LINK_REPORT_TX_FC_ON, 12336 &cur_data.link_report_flags)) { 12337 flow = "ON - receive"; 12338 } else if (!bxe_test_bit(BXE_LINK_REPORT_RX_FC_ON, 12339 &cur_data.link_report_flags) && 12340 bxe_test_bit(BXE_LINK_REPORT_TX_FC_ON, 12341 &cur_data.link_report_flags)) { 12342 flow = "ON - transmit"; 12343 } else { 12344 flow = "none"; /* possible? */ 12345 } 12346 } else { 12347 flow = "none"; 12348 } 12349 12350 if_link_state_change(sc->ifnet, LINK_STATE_UP); 12351 BLOGI(sc, "NIC Link is Up, %d Mbps %s duplex, Flow control: %s\n", 12352 cur_data.line_speed, duplex, flow); 12353 } 12354 } 12355 12356 static void 12357 bxe_link_report(struct bxe_softc *sc) 12358 { 12359 BXE_PHY_LOCK(sc); 12360 bxe_link_report_locked(sc); 12361 BXE_PHY_UNLOCK(sc); 12362 } 12363 12364 static void 12365 bxe_link_status_update(struct bxe_softc *sc) 12366 { 12367 if (sc->state != BXE_STATE_OPEN) { 12368 return; 12369 } 12370 12371 #if 0 12372 /* read updated dcb configuration */ 12373 if (IS_PF(sc)) 12374 bxe_dcbx_pmf_update(sc); 12375 #endif 12376 12377 if (IS_PF(sc) && !CHIP_REV_IS_SLOW(sc)) { 12378 elink_link_status_update(&sc->link_params, &sc->link_vars); 12379 } else { 12380 sc->port.supported[0] |= (ELINK_SUPPORTED_10baseT_Half | 12381 ELINK_SUPPORTED_10baseT_Full | 12382 ELINK_SUPPORTED_100baseT_Half | 12383 ELINK_SUPPORTED_100baseT_Full | 12384 ELINK_SUPPORTED_1000baseT_Full | 12385 ELINK_SUPPORTED_2500baseX_Full | 12386 ELINK_SUPPORTED_10000baseT_Full | 12387 ELINK_SUPPORTED_TP | 12388 ELINK_SUPPORTED_FIBRE | 12389 ELINK_SUPPORTED_Autoneg | 12390 ELINK_SUPPORTED_Pause | 12391 ELINK_SUPPORTED_Asym_Pause); 12392 sc->port.advertising[0] = sc->port.supported[0]; 12393 12394 sc->link_params.sc = sc; 12395 sc->link_params.port = SC_PORT(sc); 12396 sc->link_params.req_duplex[0] = DUPLEX_FULL; 12397 sc->link_params.req_flow_ctrl[0] = ELINK_FLOW_CTRL_NONE; 12398 sc->link_params.req_line_speed[0] = SPEED_10000; 12399 sc->link_params.speed_cap_mask[0] = 0x7f0000; 12400 sc->link_params.switch_cfg = ELINK_SWITCH_CFG_10G; 12401 12402 if (CHIP_REV_IS_FPGA(sc)) { 12403 sc->link_vars.mac_type = ELINK_MAC_TYPE_EMAC; 12404 sc->link_vars.line_speed = ELINK_SPEED_1000; 12405 sc->link_vars.link_status = (LINK_STATUS_LINK_UP | 12406 LINK_STATUS_SPEED_AND_DUPLEX_1000TFD); 12407 } else { 12408 sc->link_vars.mac_type = ELINK_MAC_TYPE_BMAC; 12409 sc->link_vars.line_speed = ELINK_SPEED_10000; 12410 sc->link_vars.link_status = (LINK_STATUS_LINK_UP | 12411 LINK_STATUS_SPEED_AND_DUPLEX_10GTFD); 12412 } 12413 12414 sc->link_vars.link_up = 1; 12415 12416 sc->link_vars.duplex = DUPLEX_FULL; 12417 sc->link_vars.flow_ctrl = ELINK_FLOW_CTRL_NONE; 12418 12419 if (IS_PF(sc)) { 12420 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + sc->link_params.port*4, 0); 12421 bxe_stats_handle(sc, STATS_EVENT_LINK_UP); 12422 bxe_link_report(sc); 12423 } 12424 } 12425 12426 if (IS_PF(sc)) { 12427 if (sc->link_vars.link_up) { 12428 bxe_stats_handle(sc, STATS_EVENT_LINK_UP); 12429 } else { 12430 bxe_stats_handle(sc, STATS_EVENT_STOP); 12431 } 12432 bxe_link_report(sc); 12433 } else { 12434 bxe_link_report(sc); 12435 bxe_stats_handle(sc, STATS_EVENT_LINK_UP); 12436 } 12437 } 12438 12439 static int 12440 bxe_initial_phy_init(struct bxe_softc *sc, 12441 int load_mode) 12442 { 12443 int rc, cfg_idx = bxe_get_link_cfg_idx(sc); 12444 uint16_t req_line_speed = sc->link_params.req_line_speed[cfg_idx]; 12445 struct elink_params *lp = &sc->link_params; 12446 12447 bxe_set_requested_fc(sc); 12448 12449 if (CHIP_REV_IS_SLOW(sc)) { 12450 uint32_t bond = CHIP_BOND_ID(sc); 12451 uint32_t feat = 0; 12452 12453 if (CHIP_IS_E2(sc) && CHIP_IS_MODE_4_PORT(sc)) { 12454 feat |= ELINK_FEATURE_CONFIG_EMUL_DISABLE_BMAC; 12455 } else if (bond & 0x4) { 12456 if (CHIP_IS_E3(sc)) { 12457 feat |= ELINK_FEATURE_CONFIG_EMUL_DISABLE_XMAC; 12458 } else { 12459 feat |= ELINK_FEATURE_CONFIG_EMUL_DISABLE_BMAC; 12460 } 12461 } else if (bond & 0x8) { 12462 if (CHIP_IS_E3(sc)) { 12463 feat |= ELINK_FEATURE_CONFIG_EMUL_DISABLE_UMAC; 12464 } else { 12465 feat |= ELINK_FEATURE_CONFIG_EMUL_DISABLE_EMAC; 12466 } 12467 } 12468 12469 /* disable EMAC for E3 and above */ 12470 if (bond & 0x2) { 12471 feat |= ELINK_FEATURE_CONFIG_EMUL_DISABLE_EMAC; 12472 } 12473 12474 sc->link_params.feature_config_flags |= feat; 12475 } 12476 12477 BXE_PHY_LOCK(sc); 12478 12479 if (load_mode == LOAD_DIAG) { 12480 lp->loopback_mode = ELINK_LOOPBACK_XGXS; 12481 /* Prefer doing PHY loopback at 10G speed, if possible */ 12482 if (lp->req_line_speed[cfg_idx] < ELINK_SPEED_10000) { 12483 if (lp->speed_cap_mask[cfg_idx] & 12484 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) { 12485 lp->req_line_speed[cfg_idx] = ELINK_SPEED_10000; 12486 } else { 12487 lp->req_line_speed[cfg_idx] = ELINK_SPEED_1000; 12488 } 12489 } 12490 } 12491 12492 if (load_mode == LOAD_LOOPBACK_EXT) { 12493 lp->loopback_mode = ELINK_LOOPBACK_EXT; 12494 } 12495 12496 rc = elink_phy_init(&sc->link_params, &sc->link_vars); 12497 12498 BXE_PHY_UNLOCK(sc); 12499 12500 bxe_calc_fc_adv(sc); 12501 12502 if (sc->link_vars.link_up) { 12503 bxe_stats_handle(sc, STATS_EVENT_LINK_UP); 12504 bxe_link_report(sc); 12505 } 12506 12507 if (!CHIP_REV_IS_SLOW(sc)) { 12508 bxe_periodic_start(sc); 12509 } 12510 12511 sc->link_params.req_line_speed[cfg_idx] = req_line_speed; 12512 return (rc); 12513 } 12514 12515 /* must be called under IF_ADDR_LOCK */ 12516 static int 12517 bxe_init_mcast_macs_list(struct bxe_softc *sc, 12518 struct ecore_mcast_ramrod_params *p) 12519 { 12520 struct ifnet *ifp = sc->ifnet; 12521 int mc_count = 0; 12522 struct ifmultiaddr *ifma; 12523 struct ecore_mcast_list_elem *mc_mac; 12524 12525 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 12526 if (ifma->ifma_addr->sa_family != AF_LINK) { 12527 continue; 12528 } 12529 12530 mc_count++; 12531 } 12532 12533 ECORE_LIST_INIT(&p->mcast_list); 12534 p->mcast_list_len = 0; 12535 12536 if (!mc_count) { 12537 return (0); 12538 } 12539 12540 mc_mac = malloc(sizeof(*mc_mac) * mc_count, M_DEVBUF, 12541 (M_NOWAIT | M_ZERO)); 12542 if (!mc_mac) { 12543 BLOGE(sc, "Failed to allocate temp mcast list\n"); 12544 return (-1); 12545 } 12546 12547 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 12548 if (ifma->ifma_addr->sa_family != AF_LINK) { 12549 continue; 12550 } 12551 12552 mc_mac->mac = (uint8_t *)LLADDR((struct sockaddr_dl *)ifma->ifma_addr); 12553 ECORE_LIST_PUSH_TAIL(&mc_mac->link, &p->mcast_list); 12554 12555 BLOGD(sc, DBG_LOAD, 12556 "Setting MCAST %02X:%02X:%02X:%02X:%02X:%02X\n", 12557 mc_mac->mac[0], mc_mac->mac[1], mc_mac->mac[2], 12558 mc_mac->mac[3], mc_mac->mac[4], mc_mac->mac[5]); 12559 12560 mc_mac++; 12561 } 12562 12563 p->mcast_list_len = mc_count; 12564 12565 return (0); 12566 } 12567 12568 static void 12569 bxe_free_mcast_macs_list(struct ecore_mcast_ramrod_params *p) 12570 { 12571 struct ecore_mcast_list_elem *mc_mac = 12572 ECORE_LIST_FIRST_ENTRY(&p->mcast_list, 12573 struct ecore_mcast_list_elem, 12574 link); 12575 12576 if (mc_mac) { 12577 /* only a single free as all mc_macs are in the same heap array */ 12578 free(mc_mac, M_DEVBUF); 12579 } 12580 } 12581 12582 static int 12583 bxe_set_mc_list(struct bxe_softc *sc) 12584 { 12585 struct ecore_mcast_ramrod_params rparam = { NULL }; 12586 int rc = 0; 12587 12588 rparam.mcast_obj = &sc->mcast_obj; 12589 12590 BXE_MCAST_LOCK(sc); 12591 12592 /* first, clear all configured multicast MACs */ 12593 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_DEL); 12594 if (rc < 0) { 12595 BLOGE(sc, "Failed to clear multicast configuration: %d\n", rc); 12596 return (rc); 12597 } 12598 12599 /* configure a new MACs list */ 12600 rc = bxe_init_mcast_macs_list(sc, &rparam); 12601 if (rc) { 12602 BLOGE(sc, "Failed to create mcast MACs list (%d)\n", rc); 12603 BXE_MCAST_UNLOCK(sc); 12604 return (rc); 12605 } 12606 12607 /* Now add the new MACs */ 12608 rc = ecore_config_mcast(sc, &rparam, ECORE_MCAST_CMD_ADD); 12609 if (rc < 0) { 12610 BLOGE(sc, "Failed to set new mcast config (%d)\n", rc); 12611 } 12612 12613 bxe_free_mcast_macs_list(&rparam); 12614 12615 BXE_MCAST_UNLOCK(sc); 12616 12617 return (rc); 12618 } 12619 12620 static int 12621 bxe_set_uc_list(struct bxe_softc *sc) 12622 { 12623 struct ifnet *ifp = sc->ifnet; 12624 struct ecore_vlan_mac_obj *mac_obj = &sc->sp_objs->mac_obj; 12625 struct ifaddr *ifa; 12626 unsigned long ramrod_flags = 0; 12627 int rc; 12628 12629 #if __FreeBSD_version < 800000 12630 IF_ADDR_LOCK(ifp); 12631 #else 12632 if_addr_rlock(ifp); 12633 #endif 12634 12635 /* first schedule a cleanup up of old configuration */ 12636 rc = bxe_del_all_macs(sc, mac_obj, ECORE_UC_LIST_MAC, FALSE); 12637 if (rc < 0) { 12638 BLOGE(sc, "Failed to schedule delete of all ETH MACs (%d)\n", rc); 12639 #if __FreeBSD_version < 800000 12640 IF_ADDR_UNLOCK(ifp); 12641 #else 12642 if_addr_runlock(ifp); 12643 #endif 12644 return (rc); 12645 } 12646 12647 ifa = ifp->if_addr; 12648 while (ifa) { 12649 if (ifa->ifa_addr->sa_family != AF_LINK) { 12650 ifa = TAILQ_NEXT(ifa, ifa_link); 12651 continue; 12652 } 12653 12654 rc = bxe_set_mac_one(sc, (uint8_t *)LLADDR((struct sockaddr_dl *)ifa->ifa_addr), 12655 mac_obj, TRUE, ECORE_UC_LIST_MAC, &ramrod_flags); 12656 if (rc == -EEXIST) { 12657 BLOGD(sc, DBG_SP, "Failed to schedule ADD operations (EEXIST)\n"); 12658 /* do not treat adding same MAC as an error */ 12659 rc = 0; 12660 } else if (rc < 0) { 12661 BLOGE(sc, "Failed to schedule ADD operations (%d)\n", rc); 12662 #if __FreeBSD_version < 800000 12663 IF_ADDR_UNLOCK(ifp); 12664 #else 12665 if_addr_runlock(ifp); 12666 #endif 12667 return (rc); 12668 } 12669 12670 ifa = TAILQ_NEXT(ifa, ifa_link); 12671 } 12672 12673 #if __FreeBSD_version < 800000 12674 IF_ADDR_UNLOCK(ifp); 12675 #else 12676 if_addr_runlock(ifp); 12677 #endif 12678 12679 /* Execute the pending commands */ 12680 bit_set(&ramrod_flags, RAMROD_CONT); 12681 return (bxe_set_mac_one(sc, NULL, mac_obj, FALSE /* don't care */, 12682 ECORE_UC_LIST_MAC, &ramrod_flags)); 12683 } 12684 12685 static void 12686 bxe_handle_rx_mode_tq(void *context, 12687 int pending) 12688 { 12689 struct bxe_softc *sc = (struct bxe_softc *)context; 12690 struct ifnet *ifp = sc->ifnet; 12691 uint32_t rx_mode = BXE_RX_MODE_NORMAL; 12692 12693 BXE_CORE_LOCK(sc); 12694 12695 if (sc->state != BXE_STATE_OPEN) { 12696 BLOGD(sc, DBG_SP, "state is %x, returning\n", sc->state); 12697 BXE_CORE_UNLOCK(sc); 12698 return; 12699 } 12700 12701 BLOGD(sc, DBG_SP, "ifp->if_flags=0x%x\n", ifp->if_flags); 12702 12703 if (ifp->if_flags & IFF_PROMISC) { 12704 rx_mode = BXE_RX_MODE_PROMISC; 12705 } else if ((ifp->if_flags & IFF_ALLMULTI) || 12706 ((ifp->if_amcount > BXE_MAX_MULTICAST) && 12707 CHIP_IS_E1(sc))) { 12708 rx_mode = BXE_RX_MODE_ALLMULTI; 12709 } else { 12710 if (IS_PF(sc)) { 12711 /* some multicasts */ 12712 if (bxe_set_mc_list(sc) < 0) { 12713 rx_mode = BXE_RX_MODE_ALLMULTI; 12714 } 12715 if (bxe_set_uc_list(sc) < 0) { 12716 rx_mode = BXE_RX_MODE_PROMISC; 12717 } 12718 } 12719 #if 0 12720 else { 12721 /* 12722 * Configuring mcast to a VF involves sleeping (when we 12723 * wait for the PF's response). Since this function is 12724 * called from a non sleepable context we must schedule 12725 * a work item for this purpose 12726 */ 12727 bxe_set_bit(BXE_SP_RTNL_VFPF_MCAST, &sc->sp_rtnl_state); 12728 schedule_delayed_work(&sc->sp_rtnl_task, 0); 12729 } 12730 #endif 12731 } 12732 12733 sc->rx_mode = rx_mode; 12734 12735 /* schedule the rx_mode command */ 12736 if (bxe_test_bit(ECORE_FILTER_RX_MODE_PENDING, &sc->sp_state)) { 12737 BLOGD(sc, DBG_LOAD, "Scheduled setting rx_mode with ECORE...\n"); 12738 bxe_set_bit(ECORE_FILTER_RX_MODE_SCHED, &sc->sp_state); 12739 BXE_CORE_UNLOCK(sc); 12740 return; 12741 } 12742 12743 if (IS_PF(sc)) { 12744 bxe_set_storm_rx_mode(sc); 12745 } 12746 #if 0 12747 else { 12748 /* 12749 * Configuring mcast to a VF involves sleeping (when we 12750 * wait for the PF's response). Since this function is 12751 * called from a non sleepable context we must schedule 12752 * a work item for this purpose 12753 */ 12754 bxe_set_bit(BXE_SP_RTNL_VFPF_STORM_RX_MODE, &sc->sp_rtnl_state); 12755 schedule_delayed_work(&sc->sp_rtnl_task, 0); 12756 } 12757 #endif 12758 12759 BXE_CORE_UNLOCK(sc); 12760 } 12761 12762 static void 12763 bxe_set_rx_mode(struct bxe_softc *sc) 12764 { 12765 taskqueue_enqueue(sc->rx_mode_tq, &sc->rx_mode_tq_task); 12766 } 12767 12768 /* update flags in shmem */ 12769 static void 12770 bxe_update_drv_flags(struct bxe_softc *sc, 12771 uint32_t flags, 12772 uint32_t set) 12773 { 12774 uint32_t drv_flags; 12775 12776 if (SHMEM2_HAS(sc, drv_flags)) { 12777 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_DRV_FLAGS); 12778 drv_flags = SHMEM2_RD(sc, drv_flags); 12779 12780 if (set) { 12781 SET_FLAGS(drv_flags, flags); 12782 } else { 12783 RESET_FLAGS(drv_flags, flags); 12784 } 12785 12786 SHMEM2_WR(sc, drv_flags, drv_flags); 12787 BLOGD(sc, DBG_LOAD, "drv_flags 0x%08x\n", drv_flags); 12788 12789 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_DRV_FLAGS); 12790 } 12791 } 12792 12793 /* periodic timer callout routine, only runs when the interface is up */ 12794 12795 static void 12796 bxe_periodic_callout_func(void *xsc) 12797 { 12798 struct bxe_softc *sc = (struct bxe_softc *)xsc; 12799 int i; 12800 12801 if (!BXE_CORE_TRYLOCK(sc)) { 12802 /* just bail and try again next time */ 12803 12804 if ((sc->state == BXE_STATE_OPEN) && 12805 (atomic_load_acq_long(&sc->periodic_flags) == PERIODIC_GO)) { 12806 /* schedule the next periodic callout */ 12807 callout_reset(&sc->periodic_callout, hz, 12808 bxe_periodic_callout_func, sc); 12809 } 12810 12811 return; 12812 } 12813 12814 if ((sc->state != BXE_STATE_OPEN) || 12815 (atomic_load_acq_long(&sc->periodic_flags) == PERIODIC_STOP)) { 12816 BLOGW(sc, "periodic callout exit (state=0x%x)\n", sc->state); 12817 BXE_CORE_UNLOCK(sc); 12818 return; 12819 } 12820 12821 /* Check for TX timeouts on any fastpath. */ 12822 FOR_EACH_QUEUE(sc, i) { 12823 if (bxe_watchdog(sc, &sc->fp[i]) != 0) { 12824 /* Ruh-Roh, chip was reset! */ 12825 break; 12826 } 12827 } 12828 12829 if (!CHIP_REV_IS_SLOW(sc)) { 12830 /* 12831 * This barrier is needed to ensure the ordering between the writing 12832 * to the sc->port.pmf in the bxe_nic_load() or bxe_pmf_update() and 12833 * the reading here. 12834 */ 12835 mb(); 12836 if (sc->port.pmf) { 12837 BXE_PHY_LOCK(sc); 12838 elink_period_func(&sc->link_params, &sc->link_vars); 12839 BXE_PHY_UNLOCK(sc); 12840 } 12841 } 12842 12843 if (IS_PF(sc) && !BXE_NOMCP(sc)) { 12844 int mb_idx = SC_FW_MB_IDX(sc); 12845 uint32_t drv_pulse; 12846 uint32_t mcp_pulse; 12847 12848 ++sc->fw_drv_pulse_wr_seq; 12849 sc->fw_drv_pulse_wr_seq &= DRV_PULSE_SEQ_MASK; 12850 12851 drv_pulse = sc->fw_drv_pulse_wr_seq; 12852 bxe_drv_pulse(sc); 12853 12854 mcp_pulse = (SHMEM_RD(sc, func_mb[mb_idx].mcp_pulse_mb) & 12855 MCP_PULSE_SEQ_MASK); 12856 12857 /* 12858 * The delta between driver pulse and mcp response should 12859 * be 1 (before mcp response) or 0 (after mcp response). 12860 */ 12861 if ((drv_pulse != mcp_pulse) && 12862 (drv_pulse != ((mcp_pulse + 1) & MCP_PULSE_SEQ_MASK))) { 12863 /* someone lost a heartbeat... */ 12864 BLOGE(sc, "drv_pulse (0x%x) != mcp_pulse (0x%x)\n", 12865 drv_pulse, mcp_pulse); 12866 } 12867 } 12868 12869 /* state is BXE_STATE_OPEN */ 12870 bxe_stats_handle(sc, STATS_EVENT_UPDATE); 12871 12872 #if 0 12873 /* sample VF bulletin board for new posts from PF */ 12874 if (IS_VF(sc)) { 12875 bxe_sample_bulletin(sc); 12876 } 12877 #endif 12878 12879 BXE_CORE_UNLOCK(sc); 12880 12881 if ((sc->state == BXE_STATE_OPEN) && 12882 (atomic_load_acq_long(&sc->periodic_flags) == PERIODIC_GO)) { 12883 /* schedule the next periodic callout */ 12884 callout_reset(&sc->periodic_callout, hz, 12885 bxe_periodic_callout_func, sc); 12886 } 12887 } 12888 12889 static void 12890 bxe_periodic_start(struct bxe_softc *sc) 12891 { 12892 atomic_store_rel_long(&sc->periodic_flags, PERIODIC_GO); 12893 callout_reset(&sc->periodic_callout, hz, bxe_periodic_callout_func, sc); 12894 } 12895 12896 static void 12897 bxe_periodic_stop(struct bxe_softc *sc) 12898 { 12899 atomic_store_rel_long(&sc->periodic_flags, PERIODIC_STOP); 12900 callout_drain(&sc->periodic_callout); 12901 } 12902 12903 /* start the controller */ 12904 static __noinline int 12905 bxe_nic_load(struct bxe_softc *sc, 12906 int load_mode) 12907 { 12908 uint32_t val; 12909 int load_code = 0; 12910 int i, rc = 0; 12911 12912 BXE_CORE_LOCK_ASSERT(sc); 12913 12914 BLOGD(sc, DBG_LOAD, "Starting NIC load...\n"); 12915 12916 sc->state = BXE_STATE_OPENING_WAITING_LOAD; 12917 12918 if (IS_PF(sc)) { 12919 /* must be called before memory allocation and HW init */ 12920 bxe_ilt_set_info(sc); 12921 } 12922 12923 sc->last_reported_link_state = LINK_STATE_UNKNOWN; 12924 12925 bxe_set_fp_rx_buf_size(sc); 12926 12927 if (bxe_alloc_fp_buffers(sc) != 0) { 12928 BLOGE(sc, "Failed to allocate fastpath memory\n"); 12929 sc->state = BXE_STATE_CLOSED; 12930 rc = ENOMEM; 12931 goto bxe_nic_load_error0; 12932 } 12933 12934 if (bxe_alloc_mem(sc) != 0) { 12935 sc->state = BXE_STATE_CLOSED; 12936 rc = ENOMEM; 12937 goto bxe_nic_load_error0; 12938 } 12939 12940 if (bxe_alloc_fw_stats_mem(sc) != 0) { 12941 sc->state = BXE_STATE_CLOSED; 12942 rc = ENOMEM; 12943 goto bxe_nic_load_error0; 12944 } 12945 12946 if (IS_PF(sc)) { 12947 /* set pf load just before approaching the MCP */ 12948 bxe_set_pf_load(sc); 12949 12950 /* if MCP exists send load request and analyze response */ 12951 if (!BXE_NOMCP(sc)) { 12952 /* attempt to load pf */ 12953 if (bxe_nic_load_request(sc, &load_code) != 0) { 12954 sc->state = BXE_STATE_CLOSED; 12955 rc = ENXIO; 12956 goto bxe_nic_load_error1; 12957 } 12958 12959 /* what did the MCP say? */ 12960 if (bxe_nic_load_analyze_req(sc, load_code) != 0) { 12961 bxe_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0); 12962 sc->state = BXE_STATE_CLOSED; 12963 rc = ENXIO; 12964 goto bxe_nic_load_error2; 12965 } 12966 } else { 12967 BLOGI(sc, "Device has no MCP!\n"); 12968 load_code = bxe_nic_load_no_mcp(sc); 12969 } 12970 12971 /* mark PMF if applicable */ 12972 bxe_nic_load_pmf(sc, load_code); 12973 12974 /* Init Function state controlling object */ 12975 bxe_init_func_obj(sc); 12976 12977 /* Initialize HW */ 12978 if (bxe_init_hw(sc, load_code) != 0) { 12979 BLOGE(sc, "HW init failed\n"); 12980 bxe_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0); 12981 sc->state = BXE_STATE_CLOSED; 12982 rc = ENXIO; 12983 goto bxe_nic_load_error2; 12984 } 12985 } 12986 12987 /* attach interrupts */ 12988 if (bxe_interrupt_attach(sc) != 0) { 12989 sc->state = BXE_STATE_CLOSED; 12990 rc = ENXIO; 12991 goto bxe_nic_load_error2; 12992 } 12993 12994 bxe_nic_init(sc, load_code); 12995 12996 /* Init per-function objects */ 12997 if (IS_PF(sc)) { 12998 bxe_init_objs(sc); 12999 // XXX bxe_iov_nic_init(sc); 13000 13001 /* set AFEX default VLAN tag to an invalid value */ 13002 sc->devinfo.mf_info.afex_def_vlan_tag = -1; 13003 // XXX bxe_nic_load_afex_dcc(sc, load_code); 13004 13005 sc->state = BXE_STATE_OPENING_WAITING_PORT; 13006 rc = bxe_func_start(sc); 13007 if (rc) { 13008 BLOGE(sc, "Function start failed!\n"); 13009 bxe_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0); 13010 sc->state = BXE_STATE_ERROR; 13011 goto bxe_nic_load_error3; 13012 } 13013 13014 /* send LOAD_DONE command to MCP */ 13015 if (!BXE_NOMCP(sc)) { 13016 load_code = bxe_fw_command(sc, DRV_MSG_CODE_LOAD_DONE, 0); 13017 if (!load_code) { 13018 BLOGE(sc, "MCP response failure, aborting\n"); 13019 sc->state = BXE_STATE_ERROR; 13020 rc = ENXIO; 13021 goto bxe_nic_load_error3; 13022 } 13023 } 13024 13025 rc = bxe_setup_leading(sc); 13026 if (rc) { 13027 BLOGE(sc, "Setup leading failed!\n"); 13028 sc->state = BXE_STATE_ERROR; 13029 goto bxe_nic_load_error3; 13030 } 13031 13032 FOR_EACH_NONDEFAULT_ETH_QUEUE(sc, i) { 13033 rc = bxe_setup_queue(sc, &sc->fp[i], FALSE); 13034 if (rc) { 13035 BLOGE(sc, "Queue(%d) setup failed\n", i); 13036 sc->state = BXE_STATE_ERROR; 13037 goto bxe_nic_load_error3; 13038 } 13039 } 13040 13041 rc = bxe_init_rss_pf(sc); 13042 if (rc) { 13043 BLOGE(sc, "PF RSS init failed\n"); 13044 sc->state = BXE_STATE_ERROR; 13045 goto bxe_nic_load_error3; 13046 } 13047 } 13048 /* XXX VF */ 13049 #if 0 13050 else { /* VF */ 13051 FOR_EACH_ETH_QUEUE(sc, i) { 13052 rc = bxe_vfpf_setup_q(sc, i); 13053 if (rc) { 13054 BLOGE(sc, "Queue(%d) setup failed\n", i); 13055 sc->state = BXE_STATE_ERROR; 13056 goto bxe_nic_load_error3; 13057 } 13058 } 13059 } 13060 #endif 13061 13062 /* now when Clients are configured we are ready to work */ 13063 sc->state = BXE_STATE_OPEN; 13064 13065 /* Configure a ucast MAC */ 13066 if (IS_PF(sc)) { 13067 rc = bxe_set_eth_mac(sc, TRUE); 13068 } 13069 #if 0 13070 else { /* IS_VF(sc) */ 13071 rc = bxe_vfpf_set_mac(sc); 13072 } 13073 #endif 13074 if (rc) { 13075 BLOGE(sc, "Setting Ethernet MAC failed\n"); 13076 sc->state = BXE_STATE_ERROR; 13077 goto bxe_nic_load_error3; 13078 } 13079 13080 #if 0 13081 if (IS_PF(sc) && sc->pending_max) { 13082 /* for AFEX */ 13083 bxe_update_max_mf_config(sc, sc->pending_max); 13084 sc->pending_max = 0; 13085 } 13086 #endif 13087 13088 if (sc->port.pmf) { 13089 rc = bxe_initial_phy_init(sc, /* XXX load_mode */LOAD_OPEN); 13090 if (rc) { 13091 sc->state = BXE_STATE_ERROR; 13092 goto bxe_nic_load_error3; 13093 } 13094 } 13095 13096 sc->link_params.feature_config_flags &= 13097 ~ELINK_FEATURE_CONFIG_BOOT_FROM_SAN; 13098 13099 /* start fast path */ 13100 13101 /* Initialize Rx filter */ 13102 bxe_set_rx_mode(sc); 13103 13104 /* start the Tx */ 13105 switch (/* XXX load_mode */LOAD_OPEN) { 13106 case LOAD_NORMAL: 13107 case LOAD_OPEN: 13108 break; 13109 13110 case LOAD_DIAG: 13111 case LOAD_LOOPBACK_EXT: 13112 sc->state = BXE_STATE_DIAG; 13113 break; 13114 13115 default: 13116 break; 13117 } 13118 13119 if (sc->port.pmf) { 13120 bxe_update_drv_flags(sc, 1 << DRV_FLAGS_PORT_MASK, 0); 13121 } else { 13122 bxe_link_status_update(sc); 13123 } 13124 13125 /* start the periodic timer callout */ 13126 bxe_periodic_start(sc); 13127 13128 if (IS_PF(sc) && SHMEM2_HAS(sc, drv_capabilities_flag)) { 13129 /* mark driver is loaded in shmem2 */ 13130 val = SHMEM2_RD(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)]); 13131 SHMEM2_WR(sc, drv_capabilities_flag[SC_FW_MB_IDX(sc)], 13132 (val | 13133 DRV_FLAGS_CAPABILITIES_LOADED_SUPPORTED | 13134 DRV_FLAGS_CAPABILITIES_LOADED_L2)); 13135 } 13136 13137 /* wait for all pending SP commands to complete */ 13138 if (IS_PF(sc) && !bxe_wait_sp_comp(sc, ~0x0UL)) { 13139 BLOGE(sc, "Timeout waiting for all SPs to complete!\n"); 13140 bxe_periodic_stop(sc); 13141 bxe_nic_unload(sc, UNLOAD_CLOSE, FALSE); 13142 return (ENXIO); 13143 } 13144 13145 #if 0 13146 /* If PMF - send ADMIN DCBX msg to MFW to initiate DCBX FSM */ 13147 if (sc->port.pmf && (sc->state != BXE_STATE_DIAG)) { 13148 bxe_dcbx_init(sc, FALSE); 13149 } 13150 #endif 13151 13152 /* Tell the stack the driver is running! */ 13153 sc->ifnet->if_drv_flags = IFF_DRV_RUNNING; 13154 13155 BLOGD(sc, DBG_LOAD, "NIC successfully loaded\n"); 13156 13157 return (0); 13158 13159 bxe_nic_load_error3: 13160 13161 if (IS_PF(sc)) { 13162 bxe_int_disable_sync(sc, 1); 13163 13164 /* clean out queued objects */ 13165 bxe_squeeze_objects(sc); 13166 } 13167 13168 bxe_interrupt_detach(sc); 13169 13170 bxe_nic_load_error2: 13171 13172 if (IS_PF(sc) && !BXE_NOMCP(sc)) { 13173 bxe_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_MCP, 0); 13174 bxe_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, 0); 13175 } 13176 13177 sc->port.pmf = 0; 13178 13179 bxe_nic_load_error1: 13180 13181 /* clear pf_load status, as it was already set */ 13182 if (IS_PF(sc)) { 13183 bxe_clear_pf_load(sc); 13184 } 13185 13186 bxe_nic_load_error0: 13187 13188 bxe_free_fw_stats_mem(sc); 13189 bxe_free_fp_buffers(sc); 13190 bxe_free_mem(sc); 13191 13192 return (rc); 13193 } 13194 13195 static int 13196 bxe_init_locked(struct bxe_softc *sc) 13197 { 13198 int other_engine = SC_PATH(sc) ? 0 : 1; 13199 uint8_t other_load_status, load_status; 13200 uint8_t global = FALSE; 13201 int rc; 13202 13203 BXE_CORE_LOCK_ASSERT(sc); 13204 13205 /* check if the driver is already running */ 13206 if (sc->ifnet->if_drv_flags & IFF_DRV_RUNNING) { 13207 BLOGD(sc, DBG_LOAD, "Init called while driver is running!\n"); 13208 return (0); 13209 } 13210 13211 bxe_set_power_state(sc, PCI_PM_D0); 13212 13213 /* 13214 * If parity occurred during the unload, then attentions and/or 13215 * RECOVERY_IN_PROGRES may still be set. If so we want the first function 13216 * loaded on the current engine to complete the recovery. Parity recovery 13217 * is only relevant for PF driver. 13218 */ 13219 if (IS_PF(sc)) { 13220 other_load_status = bxe_get_load_status(sc, other_engine); 13221 load_status = bxe_get_load_status(sc, SC_PATH(sc)); 13222 13223 if (!bxe_reset_is_done(sc, SC_PATH(sc)) || 13224 bxe_chk_parity_attn(sc, &global, TRUE)) { 13225 do { 13226 /* 13227 * If there are attentions and they are in global blocks, set 13228 * the GLOBAL_RESET bit regardless whether it will be this 13229 * function that will complete the recovery or not. 13230 */ 13231 if (global) { 13232 bxe_set_reset_global(sc); 13233 } 13234 13235 /* 13236 * Only the first function on the current engine should try 13237 * to recover in open. In case of attentions in global blocks 13238 * only the first in the chip should try to recover. 13239 */ 13240 if ((!load_status && (!global || !other_load_status)) && 13241 bxe_trylock_leader_lock(sc) && !bxe_leader_reset(sc)) { 13242 BLOGI(sc, "Recovered during init\n"); 13243 break; 13244 } 13245 13246 /* recovery has failed... */ 13247 bxe_set_power_state(sc, PCI_PM_D3hot); 13248 sc->recovery_state = BXE_RECOVERY_FAILED; 13249 13250 BLOGE(sc, "Recovery flow hasn't properly " 13251 "completed yet, try again later. " 13252 "If you still see this message after a " 13253 "few retries then power cycle is required.\n"); 13254 13255 rc = ENXIO; 13256 goto bxe_init_locked_done; 13257 } while (0); 13258 } 13259 } 13260 13261 sc->recovery_state = BXE_RECOVERY_DONE; 13262 13263 rc = bxe_nic_load(sc, LOAD_OPEN); 13264 13265 bxe_init_locked_done: 13266 13267 if (rc) { 13268 /* Tell the stack the driver is NOT running! */ 13269 BLOGE(sc, "Initialization failed, " 13270 "stack notified driver is NOT running!\n"); 13271 sc->ifnet->if_drv_flags &= ~IFF_DRV_RUNNING; 13272 } 13273 13274 return (rc); 13275 } 13276 13277 static int 13278 bxe_stop_locked(struct bxe_softc *sc) 13279 { 13280 BXE_CORE_LOCK_ASSERT(sc); 13281 return (bxe_nic_unload(sc, UNLOAD_NORMAL, TRUE)); 13282 } 13283 13284 /* 13285 * Handles controller initialization when called from an unlocked routine. 13286 * ifconfig calls this function. 13287 * 13288 * Returns: 13289 * void 13290 */ 13291 static void 13292 bxe_init(void *xsc) 13293 { 13294 struct bxe_softc *sc = (struct bxe_softc *)xsc; 13295 13296 BXE_CORE_LOCK(sc); 13297 bxe_init_locked(sc); 13298 BXE_CORE_UNLOCK(sc); 13299 } 13300 13301 static int 13302 bxe_init_ifnet(struct bxe_softc *sc) 13303 { 13304 struct ifnet *ifp; 13305 13306 /* ifconfig entrypoint for media type/status reporting */ 13307 ifmedia_init(&sc->ifmedia, IFM_IMASK, 13308 bxe_ifmedia_update, 13309 bxe_ifmedia_status); 13310 13311 /* set the default interface values */ 13312 ifmedia_add(&sc->ifmedia, (IFM_ETHER | IFM_FDX | sc->media), 0, NULL); 13313 ifmedia_add(&sc->ifmedia, (IFM_ETHER | IFM_AUTO), 0, NULL); 13314 ifmedia_set(&sc->ifmedia, (IFM_ETHER | IFM_AUTO)); 13315 13316 sc->ifmedia.ifm_media = sc->ifmedia.ifm_cur->ifm_media; /* XXX ? */ 13317 13318 /* allocate the ifnet structure */ 13319 if ((ifp = if_alloc(IFT_ETHER)) == NULL) { 13320 BLOGE(sc, "Interface allocation failed!\n"); 13321 return (ENXIO); 13322 } 13323 13324 ifp->if_softc = sc; 13325 if_initname(ifp, device_get_name(sc->dev), device_get_unit(sc->dev)); 13326 ifp->if_flags = (IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 13327 ifp->if_ioctl = bxe_ioctl; 13328 ifp->if_start = bxe_tx_start; 13329 #if __FreeBSD_version >= 800000 13330 ifp->if_transmit = bxe_tx_mq_start; 13331 ifp->if_qflush = bxe_mq_flush; 13332 #endif 13333 #ifdef FreeBSD8_0 13334 ifp->if_timer = 0; 13335 #endif 13336 ifp->if_init = bxe_init; 13337 ifp->if_mtu = sc->mtu; 13338 ifp->if_hwassist = (CSUM_IP | 13339 CSUM_TCP | 13340 CSUM_UDP | 13341 CSUM_TSO | 13342 CSUM_TCP_IPV6 | 13343 CSUM_UDP_IPV6); 13344 ifp->if_capabilities = 13345 #if __FreeBSD_version < 700000 13346 (IFCAP_VLAN_MTU | 13347 IFCAP_VLAN_HWTAGGING | 13348 IFCAP_HWCSUM | 13349 IFCAP_JUMBO_MTU | 13350 IFCAP_LRO); 13351 #else 13352 (IFCAP_VLAN_MTU | 13353 IFCAP_VLAN_HWTAGGING | 13354 IFCAP_VLAN_HWTSO | 13355 IFCAP_VLAN_HWFILTER | 13356 IFCAP_VLAN_HWCSUM | 13357 IFCAP_HWCSUM | 13358 IFCAP_JUMBO_MTU | 13359 IFCAP_LRO | 13360 IFCAP_TSO4 | 13361 IFCAP_TSO6 | 13362 IFCAP_WOL_MAGIC); 13363 #endif 13364 ifp->if_capenable = ifp->if_capabilities; 13365 ifp->if_capenable &= ~IFCAP_WOL_MAGIC; /* XXX not yet... */ 13366 #if __FreeBSD_version < 1000025 13367 ifp->if_baudrate = 1000000000; 13368 #else 13369 if_initbaudrate(ifp, IF_Gbps(10)); 13370 #endif 13371 ifp->if_snd.ifq_drv_maxlen = sc->tx_ring_size; 13372 13373 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 13374 IFQ_SET_READY(&ifp->if_snd); 13375 13376 sc->ifnet = ifp; 13377 13378 /* attach to the Ethernet interface list */ 13379 ether_ifattach(ifp, sc->link_params.mac_addr); 13380 13381 return (0); 13382 } 13383 13384 static void 13385 bxe_deallocate_bars(struct bxe_softc *sc) 13386 { 13387 int i; 13388 13389 for (i = 0; i < MAX_BARS; i++) { 13390 if (sc->bar[i].resource != NULL) { 13391 bus_release_resource(sc->dev, 13392 SYS_RES_MEMORY, 13393 sc->bar[i].rid, 13394 sc->bar[i].resource); 13395 BLOGD(sc, DBG_LOAD, "Released PCI BAR%d [%02x] memory\n", 13396 i, PCIR_BAR(i)); 13397 } 13398 } 13399 } 13400 13401 static int 13402 bxe_allocate_bars(struct bxe_softc *sc) 13403 { 13404 u_int flags; 13405 int i; 13406 13407 memset(sc->bar, 0, sizeof(sc->bar)); 13408 13409 for (i = 0; i < MAX_BARS; i++) { 13410 13411 /* memory resources reside at BARs 0, 2, 4 */ 13412 /* Run `pciconf -lb` to see mappings */ 13413 if ((i != 0) && (i != 2) && (i != 4)) { 13414 continue; 13415 } 13416 13417 sc->bar[i].rid = PCIR_BAR(i); 13418 13419 flags = RF_ACTIVE; 13420 if (i == 0) { 13421 flags |= RF_SHAREABLE; 13422 } 13423 13424 if ((sc->bar[i].resource = 13425 bus_alloc_resource_any(sc->dev, 13426 SYS_RES_MEMORY, 13427 &sc->bar[i].rid, 13428 flags)) == NULL) { 13429 #if 0 13430 /* BAR4 doesn't exist for E1 */ 13431 BLOGE(sc, "PCI BAR%d [%02x] memory allocation failed\n", 13432 i, PCIR_BAR(i)); 13433 #endif 13434 return (0); 13435 } 13436 13437 sc->bar[i].tag = rman_get_bustag(sc->bar[i].resource); 13438 sc->bar[i].handle = rman_get_bushandle(sc->bar[i].resource); 13439 sc->bar[i].kva = (vm_offset_t)rman_get_virtual(sc->bar[i].resource); 13440 13441 BLOGI(sc, "PCI BAR%d [%02x] memory allocated: %p-%p (%ld) -> %p\n", 13442 i, PCIR_BAR(i), 13443 (void *)rman_get_start(sc->bar[i].resource), 13444 (void *)rman_get_end(sc->bar[i].resource), 13445 rman_get_size(sc->bar[i].resource), 13446 (void *)sc->bar[i].kva); 13447 } 13448 13449 return (0); 13450 } 13451 13452 static void 13453 bxe_get_function_num(struct bxe_softc *sc) 13454 { 13455 uint32_t val = 0; 13456 13457 /* 13458 * Read the ME register to get the function number. The ME register 13459 * holds the relative-function number and absolute-function number. The 13460 * absolute-function number appears only in E2 and above. Before that 13461 * these bits always contained zero, therefore we cannot blindly use them. 13462 */ 13463 13464 val = REG_RD(sc, BAR_ME_REGISTER); 13465 13466 sc->pfunc_rel = 13467 (uint8_t)((val & ME_REG_PF_NUM) >> ME_REG_PF_NUM_SHIFT); 13468 sc->path_id = 13469 (uint8_t)((val & ME_REG_ABS_PF_NUM) >> ME_REG_ABS_PF_NUM_SHIFT) & 1; 13470 13471 if (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) { 13472 sc->pfunc_abs = ((sc->pfunc_rel << 1) | sc->path_id); 13473 } else { 13474 sc->pfunc_abs = (sc->pfunc_rel | sc->path_id); 13475 } 13476 13477 BLOGD(sc, DBG_LOAD, 13478 "Relative function %d, Absolute function %d, Path %d\n", 13479 sc->pfunc_rel, sc->pfunc_abs, sc->path_id); 13480 } 13481 13482 static uint32_t 13483 bxe_get_shmem_mf_cfg_base(struct bxe_softc *sc) 13484 { 13485 uint32_t shmem2_size; 13486 uint32_t offset; 13487 uint32_t mf_cfg_offset_value; 13488 13489 /* Non 57712 */ 13490 offset = (SHMEM_RD(sc, func_mb) + 13491 (MAX_FUNC_NUM * sizeof(struct drv_func_mb))); 13492 13493 /* 57712 plus */ 13494 if (sc->devinfo.shmem2_base != 0) { 13495 shmem2_size = SHMEM2_RD(sc, size); 13496 if (shmem2_size > offsetof(struct shmem2_region, mf_cfg_addr)) { 13497 mf_cfg_offset_value = SHMEM2_RD(sc, mf_cfg_addr); 13498 if (SHMEM_MF_CFG_ADDR_NONE != mf_cfg_offset_value) { 13499 offset = mf_cfg_offset_value; 13500 } 13501 } 13502 } 13503 13504 return (offset); 13505 } 13506 13507 static uint32_t 13508 bxe_pcie_capability_read(struct bxe_softc *sc, 13509 int reg, 13510 int width) 13511 { 13512 int pcie_reg; 13513 13514 /* ensure PCIe capability is enabled */ 13515 if (pci_find_cap(sc->dev, PCIY_EXPRESS, &pcie_reg) == 0) { 13516 if (pcie_reg != 0) { 13517 BLOGD(sc, DBG_LOAD, "PCIe capability at 0x%04x\n", pcie_reg); 13518 return (pci_read_config(sc->dev, (pcie_reg + reg), width)); 13519 } 13520 } 13521 13522 BLOGE(sc, "PCIe capability NOT FOUND!!!\n"); 13523 13524 return (0); 13525 } 13526 13527 static uint8_t 13528 bxe_is_pcie_pending(struct bxe_softc *sc) 13529 { 13530 return (bxe_pcie_capability_read(sc, PCIR_EXPRESS_DEVICE_STA, 2) & 13531 PCIM_EXP_STA_TRANSACTION_PND); 13532 } 13533 13534 /* 13535 * Walk the PCI capabiites list for the device to find what features are 13536 * supported. These capabilites may be enabled/disabled by firmware so it's 13537 * best to walk the list rather than make assumptions. 13538 */ 13539 static void 13540 bxe_probe_pci_caps(struct bxe_softc *sc) 13541 { 13542 uint16_t link_status; 13543 int reg; 13544 13545 /* check if PCI Power Management is enabled */ 13546 if (pci_find_cap(sc->dev, PCIY_PMG, ®) == 0) { 13547 if (reg != 0) { 13548 BLOGD(sc, DBG_LOAD, "Found PM capability at 0x%04x\n", reg); 13549 13550 sc->devinfo.pcie_cap_flags |= BXE_PM_CAPABLE_FLAG; 13551 sc->devinfo.pcie_pm_cap_reg = (uint16_t)reg; 13552 } 13553 } 13554 13555 link_status = bxe_pcie_capability_read(sc, PCIR_EXPRESS_LINK_STA, 2); 13556 13557 /* handle PCIe 2.0 workarounds for 57710 */ 13558 if (CHIP_IS_E1(sc)) { 13559 /* workaround for 57710 errata E4_57710_27462 */ 13560 sc->devinfo.pcie_link_speed = 13561 (REG_RD(sc, 0x3d04) & (1 << 24)) ? 2 : 1; 13562 13563 /* workaround for 57710 errata E4_57710_27488 */ 13564 sc->devinfo.pcie_link_width = 13565 ((link_status & PCIM_LINK_STA_WIDTH) >> 4); 13566 if (sc->devinfo.pcie_link_speed > 1) { 13567 sc->devinfo.pcie_link_width = 13568 ((link_status & PCIM_LINK_STA_WIDTH) >> 4) >> 1; 13569 } 13570 } else { 13571 sc->devinfo.pcie_link_speed = 13572 (link_status & PCIM_LINK_STA_SPEED); 13573 sc->devinfo.pcie_link_width = 13574 ((link_status & PCIM_LINK_STA_WIDTH) >> 4); 13575 } 13576 13577 BLOGD(sc, DBG_LOAD, "PCIe link speed=%d width=%d\n", 13578 sc->devinfo.pcie_link_speed, sc->devinfo.pcie_link_width); 13579 13580 sc->devinfo.pcie_cap_flags |= BXE_PCIE_CAPABLE_FLAG; 13581 sc->devinfo.pcie_pcie_cap_reg = (uint16_t)reg; 13582 13583 /* check if MSI capability is enabled */ 13584 if (pci_find_cap(sc->dev, PCIY_MSI, ®) == 0) { 13585 if (reg != 0) { 13586 BLOGD(sc, DBG_LOAD, "Found MSI capability at 0x%04x\n", reg); 13587 13588 sc->devinfo.pcie_cap_flags |= BXE_MSI_CAPABLE_FLAG; 13589 sc->devinfo.pcie_msi_cap_reg = (uint16_t)reg; 13590 } 13591 } 13592 13593 /* check if MSI-X capability is enabled */ 13594 if (pci_find_cap(sc->dev, PCIY_MSIX, ®) == 0) { 13595 if (reg != 0) { 13596 BLOGD(sc, DBG_LOAD, "Found MSI-X capability at 0x%04x\n", reg); 13597 13598 sc->devinfo.pcie_cap_flags |= BXE_MSIX_CAPABLE_FLAG; 13599 sc->devinfo.pcie_msix_cap_reg = (uint16_t)reg; 13600 } 13601 } 13602 } 13603 13604 static int 13605 bxe_get_shmem_mf_cfg_info_sd(struct bxe_softc *sc) 13606 { 13607 struct bxe_mf_info *mf_info = &sc->devinfo.mf_info; 13608 uint32_t val; 13609 13610 /* get the outer vlan if we're in switch-dependent mode */ 13611 13612 val = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag); 13613 mf_info->ext_id = (uint16_t)val; 13614 13615 mf_info->multi_vnics_mode = 1; 13616 13617 if (!VALID_OVLAN(mf_info->ext_id)) { 13618 BLOGE(sc, "Invalid VLAN (%d)\n", mf_info->ext_id); 13619 return (1); 13620 } 13621 13622 /* get the capabilities */ 13623 if ((mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_PROTOCOL_MASK) == 13624 FUNC_MF_CFG_PROTOCOL_ISCSI) { 13625 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_ISCSI; 13626 } else if ((mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_PROTOCOL_MASK) == 13627 FUNC_MF_CFG_PROTOCOL_FCOE) { 13628 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_FCOE; 13629 } else { 13630 mf_info->mf_protos_supported |= MF_PROTO_SUPPORT_ETHERNET; 13631 } 13632 13633 mf_info->vnics_per_port = 13634 (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4; 13635 13636 return (0); 13637 } 13638 13639 static uint32_t 13640 bxe_get_shmem_ext_proto_support_flags(struct bxe_softc *sc) 13641 { 13642 uint32_t retval = 0; 13643 uint32_t val; 13644 13645 val = MFCFG_RD(sc, func_ext_config[SC_ABS_FUNC(sc)].func_cfg); 13646 13647 if (val & MACP_FUNC_CFG_FLAGS_ENABLED) { 13648 if (val & MACP_FUNC_CFG_FLAGS_ETHERNET) { 13649 retval |= MF_PROTO_SUPPORT_ETHERNET; 13650 } 13651 if (val & MACP_FUNC_CFG_FLAGS_ISCSI_OFFLOAD) { 13652 retval |= MF_PROTO_SUPPORT_ISCSI; 13653 } 13654 if (val & MACP_FUNC_CFG_FLAGS_FCOE_OFFLOAD) { 13655 retval |= MF_PROTO_SUPPORT_FCOE; 13656 } 13657 } 13658 13659 return (retval); 13660 } 13661 13662 static int 13663 bxe_get_shmem_mf_cfg_info_si(struct bxe_softc *sc) 13664 { 13665 struct bxe_mf_info *mf_info = &sc->devinfo.mf_info; 13666 uint32_t val; 13667 13668 /* 13669 * There is no outer vlan if we're in switch-independent mode. 13670 * If the mac is valid then assume multi-function. 13671 */ 13672 13673 val = MFCFG_RD(sc, func_ext_config[SC_ABS_FUNC(sc)].func_cfg); 13674 13675 mf_info->multi_vnics_mode = ((val & MACP_FUNC_CFG_FLAGS_MASK) != 0); 13676 13677 mf_info->mf_protos_supported = bxe_get_shmem_ext_proto_support_flags(sc); 13678 13679 mf_info->vnics_per_port = 13680 (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4; 13681 13682 return (0); 13683 } 13684 13685 static int 13686 bxe_get_shmem_mf_cfg_info_niv(struct bxe_softc *sc) 13687 { 13688 struct bxe_mf_info *mf_info = &sc->devinfo.mf_info; 13689 uint32_t e1hov_tag; 13690 uint32_t func_config; 13691 uint32_t niv_config; 13692 13693 mf_info->multi_vnics_mode = 1; 13694 13695 e1hov_tag = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag); 13696 func_config = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].config); 13697 niv_config = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].afex_config); 13698 13699 mf_info->ext_id = 13700 (uint16_t)((e1hov_tag & FUNC_MF_CFG_E1HOV_TAG_MASK) >> 13701 FUNC_MF_CFG_E1HOV_TAG_SHIFT); 13702 13703 mf_info->default_vlan = 13704 (uint16_t)((e1hov_tag & FUNC_MF_CFG_AFEX_VLAN_MASK) >> 13705 FUNC_MF_CFG_AFEX_VLAN_SHIFT); 13706 13707 mf_info->niv_allowed_priorities = 13708 (uint8_t)((niv_config & FUNC_MF_CFG_AFEX_COS_FILTER_MASK) >> 13709 FUNC_MF_CFG_AFEX_COS_FILTER_SHIFT); 13710 13711 mf_info->niv_default_cos = 13712 (uint8_t)((func_config & FUNC_MF_CFG_TRANSMIT_PRIORITY_MASK) >> 13713 FUNC_MF_CFG_TRANSMIT_PRIORITY_SHIFT); 13714 13715 mf_info->afex_vlan_mode = 13716 ((niv_config & FUNC_MF_CFG_AFEX_VLAN_MODE_MASK) >> 13717 FUNC_MF_CFG_AFEX_VLAN_MODE_SHIFT); 13718 13719 mf_info->niv_mba_enabled = 13720 ((niv_config & FUNC_MF_CFG_AFEX_MBA_ENABLED_MASK) >> 13721 FUNC_MF_CFG_AFEX_MBA_ENABLED_SHIFT); 13722 13723 mf_info->mf_protos_supported = bxe_get_shmem_ext_proto_support_flags(sc); 13724 13725 mf_info->vnics_per_port = 13726 (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4; 13727 13728 return (0); 13729 } 13730 13731 static int 13732 bxe_check_valid_mf_cfg(struct bxe_softc *sc) 13733 { 13734 struct bxe_mf_info *mf_info = &sc->devinfo.mf_info; 13735 uint32_t mf_cfg1; 13736 uint32_t mf_cfg2; 13737 uint32_t ovlan1; 13738 uint32_t ovlan2; 13739 uint8_t i, j; 13740 13741 BLOGD(sc, DBG_LOAD, "MF config parameters for function %d\n", 13742 SC_PORT(sc)); 13743 BLOGD(sc, DBG_LOAD, "\tmf_config=0x%x\n", 13744 mf_info->mf_config[SC_VN(sc)]); 13745 BLOGD(sc, DBG_LOAD, "\tmulti_vnics_mode=%d\n", 13746 mf_info->multi_vnics_mode); 13747 BLOGD(sc, DBG_LOAD, "\tvnics_per_port=%d\n", 13748 mf_info->vnics_per_port); 13749 BLOGD(sc, DBG_LOAD, "\tovlan/vifid=%d\n", 13750 mf_info->ext_id); 13751 BLOGD(sc, DBG_LOAD, "\tmin_bw=%d/%d/%d/%d\n", 13752 mf_info->min_bw[0], mf_info->min_bw[1], 13753 mf_info->min_bw[2], mf_info->min_bw[3]); 13754 BLOGD(sc, DBG_LOAD, "\tmax_bw=%d/%d/%d/%d\n", 13755 mf_info->max_bw[0], mf_info->max_bw[1], 13756 mf_info->max_bw[2], mf_info->max_bw[3]); 13757 BLOGD(sc, DBG_LOAD, "\tmac_addr: %s\n", 13758 sc->mac_addr_str); 13759 13760 /* various MF mode sanity checks... */ 13761 13762 if (mf_info->mf_config[SC_VN(sc)] & FUNC_MF_CFG_FUNC_HIDE) { 13763 BLOGE(sc, "Enumerated function %d is marked as hidden\n", 13764 SC_PORT(sc)); 13765 return (1); 13766 } 13767 13768 if ((mf_info->vnics_per_port > 1) && !mf_info->multi_vnics_mode) { 13769 BLOGE(sc, "vnics_per_port=%d multi_vnics_mode=%d\n", 13770 mf_info->vnics_per_port, mf_info->multi_vnics_mode); 13771 return (1); 13772 } 13773 13774 if (mf_info->mf_mode == MULTI_FUNCTION_SD) { 13775 /* vnic id > 0 must have valid ovlan in switch-dependent mode */ 13776 if ((SC_VN(sc) > 0) && !VALID_OVLAN(OVLAN(sc))) { 13777 BLOGE(sc, "mf_mode=SD vnic_id=%d ovlan=%d\n", 13778 SC_VN(sc), OVLAN(sc)); 13779 return (1); 13780 } 13781 13782 if (!VALID_OVLAN(OVLAN(sc)) && mf_info->multi_vnics_mode) { 13783 BLOGE(sc, "mf_mode=SD multi_vnics_mode=%d ovlan=%d\n", 13784 mf_info->multi_vnics_mode, OVLAN(sc)); 13785 return (1); 13786 } 13787 13788 /* 13789 * Verify all functions are either MF or SF mode. If MF, make sure 13790 * sure that all non-hidden functions have a valid ovlan. If SF, 13791 * make sure that all non-hidden functions have an invalid ovlan. 13792 */ 13793 FOREACH_ABS_FUNC_IN_PORT(sc, i) { 13794 mf_cfg1 = MFCFG_RD(sc, func_mf_config[i].config); 13795 ovlan1 = MFCFG_RD(sc, func_mf_config[i].e1hov_tag); 13796 if (!(mf_cfg1 & FUNC_MF_CFG_FUNC_HIDE) && 13797 (((mf_info->multi_vnics_mode) && !VALID_OVLAN(ovlan1)) || 13798 ((!mf_info->multi_vnics_mode) && VALID_OVLAN(ovlan1)))) { 13799 BLOGE(sc, "mf_mode=SD function %d MF config " 13800 "mismatch, multi_vnics_mode=%d ovlan=%d\n", 13801 i, mf_info->multi_vnics_mode, ovlan1); 13802 return (1); 13803 } 13804 } 13805 13806 /* Verify all funcs on the same port each have a different ovlan. */ 13807 FOREACH_ABS_FUNC_IN_PORT(sc, i) { 13808 mf_cfg1 = MFCFG_RD(sc, func_mf_config[i].config); 13809 ovlan1 = MFCFG_RD(sc, func_mf_config[i].e1hov_tag); 13810 /* iterate from the next function on the port to the max func */ 13811 for (j = i + 2; j < MAX_FUNC_NUM; j += 2) { 13812 mf_cfg2 = MFCFG_RD(sc, func_mf_config[j].config); 13813 ovlan2 = MFCFG_RD(sc, func_mf_config[j].e1hov_tag); 13814 if (!(mf_cfg1 & FUNC_MF_CFG_FUNC_HIDE) && 13815 VALID_OVLAN(ovlan1) && 13816 !(mf_cfg2 & FUNC_MF_CFG_FUNC_HIDE) && 13817 VALID_OVLAN(ovlan2) && 13818 (ovlan1 == ovlan2)) { 13819 BLOGE(sc, "mf_mode=SD functions %d and %d " 13820 "have the same ovlan (%d)\n", 13821 i, j, ovlan1); 13822 return (1); 13823 } 13824 } 13825 } 13826 } /* MULTI_FUNCTION_SD */ 13827 13828 return (0); 13829 } 13830 13831 static int 13832 bxe_get_mf_cfg_info(struct bxe_softc *sc) 13833 { 13834 struct bxe_mf_info *mf_info = &sc->devinfo.mf_info; 13835 uint32_t val, mac_upper; 13836 uint8_t i, vnic; 13837 13838 /* initialize mf_info defaults */ 13839 mf_info->vnics_per_port = 1; 13840 mf_info->multi_vnics_mode = FALSE; 13841 mf_info->path_has_ovlan = FALSE; 13842 mf_info->mf_mode = SINGLE_FUNCTION; 13843 13844 if (!CHIP_IS_MF_CAP(sc)) { 13845 return (0); 13846 } 13847 13848 if (sc->devinfo.mf_cfg_base == SHMEM_MF_CFG_ADDR_NONE) { 13849 BLOGE(sc, "Invalid mf_cfg_base!\n"); 13850 return (1); 13851 } 13852 13853 /* get the MF mode (switch dependent / independent / single-function) */ 13854 13855 val = SHMEM_RD(sc, dev_info.shared_feature_config.config); 13856 13857 switch (val & SHARED_FEAT_CFG_FORCE_SF_MODE_MASK) 13858 { 13859 case SHARED_FEAT_CFG_FORCE_SF_MODE_SWITCH_INDEPT: 13860 13861 mac_upper = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper); 13862 13863 /* check for legal upper mac bytes */ 13864 if (mac_upper != FUNC_MF_CFG_UPPERMAC_DEFAULT) { 13865 mf_info->mf_mode = MULTI_FUNCTION_SI; 13866 } else { 13867 BLOGE(sc, "Invalid config for Switch Independent mode\n"); 13868 } 13869 13870 break; 13871 13872 case SHARED_FEAT_CFG_FORCE_SF_MODE_MF_ALLOWED: 13873 case SHARED_FEAT_CFG_FORCE_SF_MODE_SPIO4: 13874 13875 /* get outer vlan configuration */ 13876 val = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].e1hov_tag); 13877 13878 if ((val & FUNC_MF_CFG_E1HOV_TAG_MASK) != 13879 FUNC_MF_CFG_E1HOV_TAG_DEFAULT) { 13880 mf_info->mf_mode = MULTI_FUNCTION_SD; 13881 } else { 13882 BLOGE(sc, "Invalid config for Switch Dependent mode\n"); 13883 } 13884 13885 break; 13886 13887 case SHARED_FEAT_CFG_FORCE_SF_MODE_FORCED_SF: 13888 13889 /* not in MF mode, vnics_per_port=1 and multi_vnics_mode=FALSE */ 13890 return (0); 13891 13892 case SHARED_FEAT_CFG_FORCE_SF_MODE_AFEX_MODE: 13893 13894 /* 13895 * Mark MF mode as NIV if MCP version includes NPAR-SD support 13896 * and the MAC address is valid. 13897 */ 13898 mac_upper = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper); 13899 13900 if ((SHMEM2_HAS(sc, afex_driver_support)) && 13901 (mac_upper != FUNC_MF_CFG_UPPERMAC_DEFAULT)) { 13902 mf_info->mf_mode = MULTI_FUNCTION_AFEX; 13903 } else { 13904 BLOGE(sc, "Invalid config for AFEX mode\n"); 13905 } 13906 13907 break; 13908 13909 default: 13910 13911 BLOGE(sc, "Unknown MF mode (0x%08x)\n", 13912 (val & SHARED_FEAT_CFG_FORCE_SF_MODE_MASK)); 13913 13914 return (1); 13915 } 13916 13917 /* set path mf_mode (which could be different than function mf_mode) */ 13918 if (mf_info->mf_mode == MULTI_FUNCTION_SD) { 13919 mf_info->path_has_ovlan = TRUE; 13920 } else if (mf_info->mf_mode == SINGLE_FUNCTION) { 13921 /* 13922 * Decide on path multi vnics mode. If we're not in MF mode and in 13923 * 4-port mode, this is good enough to check vnic-0 of the other port 13924 * on the same path 13925 */ 13926 if (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) { 13927 uint8_t other_port = !(PORT_ID(sc) & 1); 13928 uint8_t abs_func_other_port = (SC_PATH(sc) + (2 * other_port)); 13929 13930 val = MFCFG_RD(sc, func_mf_config[abs_func_other_port].e1hov_tag); 13931 13932 mf_info->path_has_ovlan = VALID_OVLAN((uint16_t)val) ? 1 : 0; 13933 } 13934 } 13935 13936 if (mf_info->mf_mode == SINGLE_FUNCTION) { 13937 /* invalid MF config */ 13938 if (SC_VN(sc) >= 1) { 13939 BLOGE(sc, "VNIC ID >= 1 in SF mode\n"); 13940 return (1); 13941 } 13942 13943 return (0); 13944 } 13945 13946 /* get the MF configuration */ 13947 mf_info->mf_config[SC_VN(sc)] = 13948 MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].config); 13949 13950 switch(mf_info->mf_mode) 13951 { 13952 case MULTI_FUNCTION_SD: 13953 13954 bxe_get_shmem_mf_cfg_info_sd(sc); 13955 break; 13956 13957 case MULTI_FUNCTION_SI: 13958 13959 bxe_get_shmem_mf_cfg_info_si(sc); 13960 break; 13961 13962 case MULTI_FUNCTION_AFEX: 13963 13964 bxe_get_shmem_mf_cfg_info_niv(sc); 13965 break; 13966 13967 default: 13968 13969 BLOGE(sc, "Get MF config failed (mf_mode=0x%08x)\n", 13970 mf_info->mf_mode); 13971 return (1); 13972 } 13973 13974 /* get the congestion management parameters */ 13975 13976 vnic = 0; 13977 FOREACH_ABS_FUNC_IN_PORT(sc, i) { 13978 /* get min/max bw */ 13979 val = MFCFG_RD(sc, func_mf_config[i].config); 13980 mf_info->min_bw[vnic] = 13981 ((val & FUNC_MF_CFG_MIN_BW_MASK) >> FUNC_MF_CFG_MIN_BW_SHIFT); 13982 mf_info->max_bw[vnic] = 13983 ((val & FUNC_MF_CFG_MAX_BW_MASK) >> FUNC_MF_CFG_MAX_BW_SHIFT); 13984 vnic++; 13985 } 13986 13987 return (bxe_check_valid_mf_cfg(sc)); 13988 } 13989 13990 static int 13991 bxe_get_shmem_info(struct bxe_softc *sc) 13992 { 13993 int port; 13994 uint32_t mac_hi, mac_lo, val; 13995 13996 port = SC_PORT(sc); 13997 mac_hi = mac_lo = 0; 13998 13999 sc->link_params.sc = sc; 14000 sc->link_params.port = port; 14001 14002 /* get the hardware config info */ 14003 sc->devinfo.hw_config = 14004 SHMEM_RD(sc, dev_info.shared_hw_config.config); 14005 sc->devinfo.hw_config2 = 14006 SHMEM_RD(sc, dev_info.shared_hw_config.config2); 14007 14008 sc->link_params.hw_led_mode = 14009 ((sc->devinfo.hw_config & SHARED_HW_CFG_LED_MODE_MASK) >> 14010 SHARED_HW_CFG_LED_MODE_SHIFT); 14011 14012 /* get the port feature config */ 14013 sc->port.config = 14014 SHMEM_RD(sc, dev_info.port_feature_config[port].config), 14015 14016 /* get the link params */ 14017 sc->link_params.speed_cap_mask[0] = 14018 SHMEM_RD(sc, dev_info.port_hw_config[port].speed_capability_mask); 14019 sc->link_params.speed_cap_mask[1] = 14020 SHMEM_RD(sc, dev_info.port_hw_config[port].speed_capability_mask2); 14021 14022 /* get the lane config */ 14023 sc->link_params.lane_config = 14024 SHMEM_RD(sc, dev_info.port_hw_config[port].lane_config); 14025 14026 /* get the link config */ 14027 val = SHMEM_RD(sc, dev_info.port_feature_config[port].link_config); 14028 sc->port.link_config[ELINK_INT_PHY] = val; 14029 sc->link_params.switch_cfg = (val & PORT_FEATURE_CONNECTED_SWITCH_MASK); 14030 sc->port.link_config[ELINK_EXT_PHY1] = 14031 SHMEM_RD(sc, dev_info.port_feature_config[port].link_config2); 14032 14033 /* get the override preemphasis flag and enable it or turn it off */ 14034 val = SHMEM_RD(sc, dev_info.shared_feature_config.config); 14035 if (val & SHARED_FEAT_CFG_OVERRIDE_PREEMPHASIS_CFG_ENABLED) { 14036 sc->link_params.feature_config_flags |= 14037 ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED; 14038 } else { 14039 sc->link_params.feature_config_flags &= 14040 ~ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED; 14041 } 14042 14043 /* get the initial value of the link params */ 14044 sc->link_params.multi_phy_config = 14045 SHMEM_RD(sc, dev_info.port_hw_config[port].multi_phy_config); 14046 14047 /* get external phy info */ 14048 sc->port.ext_phy_config = 14049 SHMEM_RD(sc, dev_info.port_hw_config[port].external_phy_config); 14050 14051 /* get the multifunction configuration */ 14052 bxe_get_mf_cfg_info(sc); 14053 14054 /* get the mac address */ 14055 if (IS_MF(sc)) { 14056 mac_hi = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_upper); 14057 mac_lo = MFCFG_RD(sc, func_mf_config[SC_ABS_FUNC(sc)].mac_lower); 14058 } else { 14059 mac_hi = SHMEM_RD(sc, dev_info.port_hw_config[port].mac_upper); 14060 mac_lo = SHMEM_RD(sc, dev_info.port_hw_config[port].mac_lower); 14061 } 14062 14063 if ((mac_lo == 0) && (mac_hi == 0)) { 14064 *sc->mac_addr_str = 0; 14065 BLOGE(sc, "No Ethernet address programmed!\n"); 14066 } else { 14067 sc->link_params.mac_addr[0] = (uint8_t)(mac_hi >> 8); 14068 sc->link_params.mac_addr[1] = (uint8_t)(mac_hi); 14069 sc->link_params.mac_addr[2] = (uint8_t)(mac_lo >> 24); 14070 sc->link_params.mac_addr[3] = (uint8_t)(mac_lo >> 16); 14071 sc->link_params.mac_addr[4] = (uint8_t)(mac_lo >> 8); 14072 sc->link_params.mac_addr[5] = (uint8_t)(mac_lo); 14073 snprintf(sc->mac_addr_str, sizeof(sc->mac_addr_str), 14074 "%02x:%02x:%02x:%02x:%02x:%02x", 14075 sc->link_params.mac_addr[0], sc->link_params.mac_addr[1], 14076 sc->link_params.mac_addr[2], sc->link_params.mac_addr[3], 14077 sc->link_params.mac_addr[4], sc->link_params.mac_addr[5]); 14078 BLOGD(sc, DBG_LOAD, "Ethernet address: %s\n", sc->mac_addr_str); 14079 } 14080 14081 #if 0 14082 if (!IS_MF(sc) && 14083 ((sc->port.config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) == 14084 PORT_FEAT_CFG_STORAGE_PERSONALITY_FCOE)) { 14085 sc->flags |= BXE_NO_ISCSI; 14086 } 14087 if (!IS_MF(sc) && 14088 ((sc->port.config & PORT_FEAT_CFG_STORAGE_PERSONALITY_MASK) == 14089 PORT_FEAT_CFG_STORAGE_PERSONALITY_ISCSI)) { 14090 sc->flags |= BXE_NO_FCOE_FLAG; 14091 } 14092 #endif 14093 14094 return (0); 14095 } 14096 14097 static void 14098 bxe_get_tunable_params(struct bxe_softc *sc) 14099 { 14100 /* sanity checks */ 14101 14102 if ((bxe_interrupt_mode != INTR_MODE_INTX) && 14103 (bxe_interrupt_mode != INTR_MODE_MSI) && 14104 (bxe_interrupt_mode != INTR_MODE_MSIX)) { 14105 BLOGW(sc, "invalid interrupt_mode value (%d)\n", bxe_interrupt_mode); 14106 bxe_interrupt_mode = INTR_MODE_MSIX; 14107 } 14108 14109 if ((bxe_queue_count < 0) || (bxe_queue_count > MAX_RSS_CHAINS)) { 14110 BLOGW(sc, "invalid queue_count value (%d)\n", bxe_queue_count); 14111 bxe_queue_count = 0; 14112 } 14113 14114 if ((bxe_max_rx_bufs < 1) || (bxe_max_rx_bufs > RX_BD_USABLE)) { 14115 if (bxe_max_rx_bufs == 0) { 14116 bxe_max_rx_bufs = RX_BD_USABLE; 14117 } else { 14118 BLOGW(sc, "invalid max_rx_bufs (%d)\n", bxe_max_rx_bufs); 14119 bxe_max_rx_bufs = 2048; 14120 } 14121 } 14122 14123 if ((bxe_hc_rx_ticks < 1) || (bxe_hc_rx_ticks > 100)) { 14124 BLOGW(sc, "invalid hc_rx_ticks (%d)\n", bxe_hc_rx_ticks); 14125 bxe_hc_rx_ticks = 25; 14126 } 14127 14128 if ((bxe_hc_tx_ticks < 1) || (bxe_hc_tx_ticks > 100)) { 14129 BLOGW(sc, "invalid hc_tx_ticks (%d)\n", bxe_hc_tx_ticks); 14130 bxe_hc_tx_ticks = 50; 14131 } 14132 14133 if (bxe_max_aggregation_size == 0) { 14134 bxe_max_aggregation_size = TPA_AGG_SIZE; 14135 } 14136 14137 if (bxe_max_aggregation_size > 0xffff) { 14138 BLOGW(sc, "invalid max_aggregation_size (%d)\n", 14139 bxe_max_aggregation_size); 14140 bxe_max_aggregation_size = TPA_AGG_SIZE; 14141 } 14142 14143 if ((bxe_mrrs < -1) || (bxe_mrrs > 3)) { 14144 BLOGW(sc, "invalid mrrs (%d)\n", bxe_mrrs); 14145 bxe_mrrs = -1; 14146 } 14147 14148 if ((bxe_autogreeen < 0) || (bxe_autogreeen > 2)) { 14149 BLOGW(sc, "invalid autogreeen (%d)\n", bxe_autogreeen); 14150 bxe_autogreeen = 0; 14151 } 14152 14153 if ((bxe_udp_rss < 0) || (bxe_udp_rss > 1)) { 14154 BLOGW(sc, "invalid udp_rss (%d)\n", bxe_udp_rss); 14155 bxe_udp_rss = 0; 14156 } 14157 14158 /* pull in user settings */ 14159 14160 sc->interrupt_mode = bxe_interrupt_mode; 14161 sc->max_rx_bufs = bxe_max_rx_bufs; 14162 sc->hc_rx_ticks = bxe_hc_rx_ticks; 14163 sc->hc_tx_ticks = bxe_hc_tx_ticks; 14164 sc->max_aggregation_size = bxe_max_aggregation_size; 14165 sc->mrrs = bxe_mrrs; 14166 sc->autogreeen = bxe_autogreeen; 14167 sc->udp_rss = bxe_udp_rss; 14168 14169 if (bxe_interrupt_mode == INTR_MODE_INTX) { 14170 sc->num_queues = 1; 14171 } else { /* INTR_MODE_MSI or INTR_MODE_MSIX */ 14172 sc->num_queues = 14173 min((bxe_queue_count ? bxe_queue_count : mp_ncpus), 14174 MAX_RSS_CHAINS); 14175 if (sc->num_queues > mp_ncpus) { 14176 sc->num_queues = mp_ncpus; 14177 } 14178 } 14179 14180 BLOGD(sc, DBG_LOAD, 14181 "User Config: " 14182 "debug=0x%lx " 14183 "interrupt_mode=%d " 14184 "queue_count=%d " 14185 "hc_rx_ticks=%d " 14186 "hc_tx_ticks=%d " 14187 "rx_budget=%d " 14188 "max_aggregation_size=%d " 14189 "mrrs=%d " 14190 "autogreeen=%d " 14191 "udp_rss=%d\n", 14192 bxe_debug, 14193 sc->interrupt_mode, 14194 sc->num_queues, 14195 sc->hc_rx_ticks, 14196 sc->hc_tx_ticks, 14197 bxe_rx_budget, 14198 sc->max_aggregation_size, 14199 sc->mrrs, 14200 sc->autogreeen, 14201 sc->udp_rss); 14202 } 14203 14204 static void 14205 bxe_media_detect(struct bxe_softc *sc) 14206 { 14207 uint32_t phy_idx = bxe_get_cur_phy_idx(sc); 14208 switch (sc->link_params.phy[phy_idx].media_type) { 14209 case ELINK_ETH_PHY_SFPP_10G_FIBER: 14210 case ELINK_ETH_PHY_XFP_FIBER: 14211 BLOGI(sc, "Found 10Gb Fiber media.\n"); 14212 sc->media = IFM_10G_SR; 14213 break; 14214 case ELINK_ETH_PHY_SFP_1G_FIBER: 14215 BLOGI(sc, "Found 1Gb Fiber media.\n"); 14216 sc->media = IFM_1000_SX; 14217 break; 14218 case ELINK_ETH_PHY_KR: 14219 case ELINK_ETH_PHY_CX4: 14220 BLOGI(sc, "Found 10GBase-CX4 media.\n"); 14221 sc->media = IFM_10G_CX4; 14222 break; 14223 case ELINK_ETH_PHY_DA_TWINAX: 14224 BLOGI(sc, "Found 10Gb Twinax media.\n"); 14225 sc->media = IFM_10G_TWINAX; 14226 break; 14227 case ELINK_ETH_PHY_BASE_T: 14228 if (sc->link_params.speed_cap_mask[0] & 14229 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) { 14230 BLOGI(sc, "Found 10GBase-T media.\n"); 14231 sc->media = IFM_10G_T; 14232 } else { 14233 BLOGI(sc, "Found 1000Base-T media.\n"); 14234 sc->media = IFM_1000_T; 14235 } 14236 break; 14237 case ELINK_ETH_PHY_NOT_PRESENT: 14238 BLOGI(sc, "Media not present.\n"); 14239 sc->media = 0; 14240 break; 14241 case ELINK_ETH_PHY_UNSPECIFIED: 14242 default: 14243 BLOGI(sc, "Unknown media!\n"); 14244 sc->media = 0; 14245 break; 14246 } 14247 } 14248 14249 #define GET_FIELD(value, fname) \ 14250 (((value) & (fname##_MASK)) >> (fname##_SHIFT)) 14251 #define IGU_FID(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_FID) 14252 #define IGU_VEC(val) GET_FIELD((val), IGU_REG_MAPPING_MEMORY_VECTOR) 14253 14254 static int 14255 bxe_get_igu_cam_info(struct bxe_softc *sc) 14256 { 14257 int pfid = SC_FUNC(sc); 14258 int igu_sb_id; 14259 uint32_t val; 14260 uint8_t fid, igu_sb_cnt = 0; 14261 14262 sc->igu_base_sb = 0xff; 14263 14264 if (CHIP_INT_MODE_IS_BC(sc)) { 14265 int vn = SC_VN(sc); 14266 igu_sb_cnt = sc->igu_sb_cnt; 14267 sc->igu_base_sb = ((CHIP_IS_MODE_4_PORT(sc) ? pfid : vn) * 14268 FP_SB_MAX_E1x); 14269 sc->igu_dsb_id = (E1HVN_MAX * FP_SB_MAX_E1x + 14270 (CHIP_IS_MODE_4_PORT(sc) ? pfid : vn)); 14271 return (0); 14272 } 14273 14274 /* IGU in normal mode - read CAM */ 14275 for (igu_sb_id = 0; 14276 igu_sb_id < IGU_REG_MAPPING_MEMORY_SIZE; 14277 igu_sb_id++) { 14278 val = REG_RD(sc, IGU_REG_MAPPING_MEMORY + igu_sb_id * 4); 14279 if (!(val & IGU_REG_MAPPING_MEMORY_VALID)) { 14280 continue; 14281 } 14282 fid = IGU_FID(val); 14283 if ((fid & IGU_FID_ENCODE_IS_PF)) { 14284 if ((fid & IGU_FID_PF_NUM_MASK) != pfid) { 14285 continue; 14286 } 14287 if (IGU_VEC(val) == 0) { 14288 /* default status block */ 14289 sc->igu_dsb_id = igu_sb_id; 14290 } else { 14291 if (sc->igu_base_sb == 0xff) { 14292 sc->igu_base_sb = igu_sb_id; 14293 } 14294 igu_sb_cnt++; 14295 } 14296 } 14297 } 14298 14299 /* 14300 * Due to new PF resource allocation by MFW T7.4 and above, it's optional 14301 * that number of CAM entries will not be equal to the value advertised in 14302 * PCI. Driver should use the minimal value of both as the actual status 14303 * block count 14304 */ 14305 sc->igu_sb_cnt = min(sc->igu_sb_cnt, igu_sb_cnt); 14306 14307 if (igu_sb_cnt == 0) { 14308 BLOGE(sc, "CAM configuration error\n"); 14309 return (-1); 14310 } 14311 14312 return (0); 14313 } 14314 14315 /* 14316 * Gather various information from the device config space, the device itself, 14317 * shmem, and the user input. 14318 */ 14319 static int 14320 bxe_get_device_info(struct bxe_softc *sc) 14321 { 14322 uint32_t val; 14323 int rc; 14324 14325 /* Get the data for the device */ 14326 sc->devinfo.vendor_id = pci_get_vendor(sc->dev); 14327 sc->devinfo.device_id = pci_get_device(sc->dev); 14328 sc->devinfo.subvendor_id = pci_get_subvendor(sc->dev); 14329 sc->devinfo.subdevice_id = pci_get_subdevice(sc->dev); 14330 14331 /* get the chip revision (chip metal comes from pci config space) */ 14332 sc->devinfo.chip_id = 14333 sc->link_params.chip_id = 14334 (((REG_RD(sc, MISC_REG_CHIP_NUM) & 0xffff) << 16) | 14335 ((REG_RD(sc, MISC_REG_CHIP_REV) & 0xf) << 12) | 14336 (((REG_RD(sc, PCICFG_OFFSET + PCI_ID_VAL3) >> 24) & 0xf) << 4) | 14337 ((REG_RD(sc, MISC_REG_BOND_ID) & 0xf) << 0)); 14338 14339 /* force 57811 according to MISC register */ 14340 if (REG_RD(sc, MISC_REG_CHIP_TYPE) & MISC_REG_CHIP_TYPE_57811_MASK) { 14341 if (CHIP_IS_57810(sc)) { 14342 sc->devinfo.chip_id = ((CHIP_NUM_57811 << 16) | 14343 (sc->devinfo.chip_id & 0x0000ffff)); 14344 } else if (CHIP_IS_57810_MF(sc)) { 14345 sc->devinfo.chip_id = ((CHIP_NUM_57811_MF << 16) | 14346 (sc->devinfo.chip_id & 0x0000ffff)); 14347 } 14348 sc->devinfo.chip_id |= 0x1; 14349 } 14350 14351 BLOGD(sc, DBG_LOAD, 14352 "chip_id=0x%08x (num=0x%04x rev=0x%01x metal=0x%02x bond=0x%01x)\n", 14353 sc->devinfo.chip_id, 14354 ((sc->devinfo.chip_id >> 16) & 0xffff), 14355 ((sc->devinfo.chip_id >> 12) & 0xf), 14356 ((sc->devinfo.chip_id >> 4) & 0xff), 14357 ((sc->devinfo.chip_id >> 0) & 0xf)); 14358 14359 val = (REG_RD(sc, 0x2874) & 0x55); 14360 if ((sc->devinfo.chip_id & 0x1) || 14361 (CHIP_IS_E1(sc) && val) || 14362 (CHIP_IS_E1H(sc) && (val == 0x55))) { 14363 sc->flags |= BXE_ONE_PORT_FLAG; 14364 BLOGD(sc, DBG_LOAD, "single port device\n"); 14365 } 14366 14367 /* set the doorbell size */ 14368 sc->doorbell_size = (1 << BXE_DB_SHIFT); 14369 14370 /* determine whether the device is in 2 port or 4 port mode */ 14371 sc->devinfo.chip_port_mode = CHIP_PORT_MODE_NONE; /* E1 & E1h*/ 14372 if (CHIP_IS_E2E3(sc)) { 14373 /* 14374 * Read port4mode_en_ovwr[0]: 14375 * If 1, four port mode is in port4mode_en_ovwr[1]. 14376 * If 0, four port mode is in port4mode_en[0]. 14377 */ 14378 val = REG_RD(sc, MISC_REG_PORT4MODE_EN_OVWR); 14379 if (val & 1) { 14380 val = ((val >> 1) & 1); 14381 } else { 14382 val = REG_RD(sc, MISC_REG_PORT4MODE_EN); 14383 } 14384 14385 sc->devinfo.chip_port_mode = 14386 (val) ? CHIP_4_PORT_MODE : CHIP_2_PORT_MODE; 14387 14388 BLOGD(sc, DBG_LOAD, "Port mode = %s\n", (val) ? "4" : "2"); 14389 } 14390 14391 /* get the function and path info for the device */ 14392 bxe_get_function_num(sc); 14393 14394 /* get the shared memory base address */ 14395 sc->devinfo.shmem_base = 14396 sc->link_params.shmem_base = 14397 REG_RD(sc, MISC_REG_SHARED_MEM_ADDR); 14398 sc->devinfo.shmem2_base = 14399 REG_RD(sc, (SC_PATH(sc) ? MISC_REG_GENERIC_CR_1 : 14400 MISC_REG_GENERIC_CR_0)); 14401 14402 BLOGD(sc, DBG_LOAD, "shmem_base=0x%08x, shmem2_base=0x%08x\n", 14403 sc->devinfo.shmem_base, sc->devinfo.shmem2_base); 14404 14405 if (!sc->devinfo.shmem_base) { 14406 /* this should ONLY prevent upcoming shmem reads */ 14407 BLOGI(sc, "MCP not active\n"); 14408 sc->flags |= BXE_NO_MCP_FLAG; 14409 return (0); 14410 } 14411 14412 /* make sure the shared memory contents are valid */ 14413 val = SHMEM_RD(sc, validity_map[SC_PORT(sc)]); 14414 if ((val & (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) != 14415 (SHR_MEM_VALIDITY_DEV_INFO | SHR_MEM_VALIDITY_MB)) { 14416 BLOGE(sc, "Invalid SHMEM validity signature: 0x%08x\n", val); 14417 return (0); 14418 } 14419 BLOGD(sc, DBG_LOAD, "Valid SHMEM validity signature: 0x%08x\n", val); 14420 14421 /* get the bootcode version */ 14422 sc->devinfo.bc_ver = SHMEM_RD(sc, dev_info.bc_rev); 14423 snprintf(sc->devinfo.bc_ver_str, 14424 sizeof(sc->devinfo.bc_ver_str), 14425 "%d.%d.%d", 14426 ((sc->devinfo.bc_ver >> 24) & 0xff), 14427 ((sc->devinfo.bc_ver >> 16) & 0xff), 14428 ((sc->devinfo.bc_ver >> 8) & 0xff)); 14429 BLOGD(sc, DBG_LOAD, "Bootcode version: %s\n", sc->devinfo.bc_ver_str); 14430 14431 /* get the bootcode shmem address */ 14432 sc->devinfo.mf_cfg_base = bxe_get_shmem_mf_cfg_base(sc); 14433 BLOGD(sc, DBG_LOAD, "mf_cfg_base=0x08%x \n", sc->devinfo.mf_cfg_base); 14434 14435 /* clean indirect addresses as they're not used */ 14436 pci_write_config(sc->dev, PCICFG_GRC_ADDRESS, 0, 4); 14437 if (IS_PF(sc)) { 14438 REG_WR(sc, PXP2_REG_PGL_ADDR_88_F0, 0); 14439 REG_WR(sc, PXP2_REG_PGL_ADDR_8C_F0, 0); 14440 REG_WR(sc, PXP2_REG_PGL_ADDR_90_F0, 0); 14441 REG_WR(sc, PXP2_REG_PGL_ADDR_94_F0, 0); 14442 if (CHIP_IS_E1x(sc)) { 14443 REG_WR(sc, PXP2_REG_PGL_ADDR_88_F1, 0); 14444 REG_WR(sc, PXP2_REG_PGL_ADDR_8C_F1, 0); 14445 REG_WR(sc, PXP2_REG_PGL_ADDR_90_F1, 0); 14446 REG_WR(sc, PXP2_REG_PGL_ADDR_94_F1, 0); 14447 } 14448 14449 /* 14450 * Enable internal target-read (in case we are probed after PF 14451 * FLR). Must be done prior to any BAR read access. Only for 14452 * 57712 and up 14453 */ 14454 if (!CHIP_IS_E1x(sc)) { 14455 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1); 14456 } 14457 } 14458 14459 /* get the nvram size */ 14460 val = REG_RD(sc, MCP_REG_MCPR_NVM_CFG4); 14461 sc->devinfo.flash_size = 14462 (NVRAM_1MB_SIZE << (val & MCPR_NVM_CFG4_FLASH_SIZE)); 14463 BLOGD(sc, DBG_LOAD, "nvram flash size: %d\n", sc->devinfo.flash_size); 14464 14465 /* get PCI capabilites */ 14466 bxe_probe_pci_caps(sc); 14467 14468 bxe_set_power_state(sc, PCI_PM_D0); 14469 14470 /* get various configuration parameters from shmem */ 14471 bxe_get_shmem_info(sc); 14472 14473 if (sc->devinfo.pcie_msix_cap_reg != 0) { 14474 val = pci_read_config(sc->dev, 14475 (sc->devinfo.pcie_msix_cap_reg + 14476 PCIR_MSIX_CTRL), 14477 2); 14478 sc->igu_sb_cnt = (val & PCIM_MSIXCTRL_TABLE_SIZE); 14479 } else { 14480 sc->igu_sb_cnt = 1; 14481 } 14482 14483 sc->igu_base_addr = BAR_IGU_INTMEM; 14484 14485 /* initialize IGU parameters */ 14486 if (CHIP_IS_E1x(sc)) { 14487 sc->devinfo.int_block = INT_BLOCK_HC; 14488 sc->igu_dsb_id = DEF_SB_IGU_ID; 14489 sc->igu_base_sb = 0; 14490 } else { 14491 sc->devinfo.int_block = INT_BLOCK_IGU; 14492 14493 /* do not allow device reset during IGU info preocessing */ 14494 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RESET); 14495 14496 val = REG_RD(sc, IGU_REG_BLOCK_CONFIGURATION); 14497 14498 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) { 14499 int tout = 5000; 14500 14501 BLOGD(sc, DBG_LOAD, "FORCING IGU Normal Mode\n"); 14502 14503 val &= ~(IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN); 14504 REG_WR(sc, IGU_REG_BLOCK_CONFIGURATION, val); 14505 REG_WR(sc, IGU_REG_RESET_MEMORIES, 0x7f); 14506 14507 while (tout && REG_RD(sc, IGU_REG_RESET_MEMORIES)) { 14508 tout--; 14509 DELAY(1000); 14510 } 14511 14512 if (REG_RD(sc, IGU_REG_RESET_MEMORIES)) { 14513 BLOGD(sc, DBG_LOAD, "FORCING IGU Normal Mode failed!!!\n"); 14514 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET); 14515 return (-1); 14516 } 14517 } 14518 14519 if (val & IGU_BLOCK_CONFIGURATION_REG_BACKWARD_COMP_EN) { 14520 BLOGD(sc, DBG_LOAD, "IGU Backward Compatible Mode\n"); 14521 sc->devinfo.int_block |= INT_BLOCK_MODE_BW_COMP; 14522 } else { 14523 BLOGD(sc, DBG_LOAD, "IGU Normal Mode\n"); 14524 } 14525 14526 rc = bxe_get_igu_cam_info(sc); 14527 14528 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET); 14529 14530 if (rc) { 14531 return (rc); 14532 } 14533 } 14534 14535 /* 14536 * Get base FW non-default (fast path) status block ID. This value is 14537 * used to initialize the fw_sb_id saved on the fp/queue structure to 14538 * determine the id used by the FW. 14539 */ 14540 if (CHIP_IS_E1x(sc)) { 14541 sc->base_fw_ndsb = ((SC_PORT(sc) * FP_SB_MAX_E1x) + SC_L_ID(sc)); 14542 } else { 14543 /* 14544 * 57712+ - We currently use one FW SB per IGU SB (Rx and Tx of 14545 * the same queue are indicated on the same IGU SB). So we prefer 14546 * FW and IGU SBs to be the same value. 14547 */ 14548 sc->base_fw_ndsb = sc->igu_base_sb; 14549 } 14550 14551 BLOGD(sc, DBG_LOAD, 14552 "igu_dsb_id=%d igu_base_sb=%d igu_sb_cnt=%d base_fw_ndsb=%d\n", 14553 sc->igu_dsb_id, sc->igu_base_sb, 14554 sc->igu_sb_cnt, sc->base_fw_ndsb); 14555 14556 elink_phy_probe(&sc->link_params); 14557 14558 return (0); 14559 } 14560 14561 static void 14562 bxe_link_settings_supported(struct bxe_softc *sc, 14563 uint32_t switch_cfg) 14564 { 14565 uint32_t cfg_size = 0; 14566 uint32_t idx; 14567 uint8_t port = SC_PORT(sc); 14568 14569 /* aggregation of supported attributes of all external phys */ 14570 sc->port.supported[0] = 0; 14571 sc->port.supported[1] = 0; 14572 14573 switch (sc->link_params.num_phys) { 14574 case 1: 14575 sc->port.supported[0] = sc->link_params.phy[ELINK_INT_PHY].supported; 14576 cfg_size = 1; 14577 break; 14578 case 2: 14579 sc->port.supported[0] = sc->link_params.phy[ELINK_EXT_PHY1].supported; 14580 cfg_size = 1; 14581 break; 14582 case 3: 14583 if (sc->link_params.multi_phy_config & 14584 PORT_HW_CFG_PHY_SWAPPED_ENABLED) { 14585 sc->port.supported[1] = 14586 sc->link_params.phy[ELINK_EXT_PHY1].supported; 14587 sc->port.supported[0] = 14588 sc->link_params.phy[ELINK_EXT_PHY2].supported; 14589 } else { 14590 sc->port.supported[0] = 14591 sc->link_params.phy[ELINK_EXT_PHY1].supported; 14592 sc->port.supported[1] = 14593 sc->link_params.phy[ELINK_EXT_PHY2].supported; 14594 } 14595 cfg_size = 2; 14596 break; 14597 } 14598 14599 if (!(sc->port.supported[0] || sc->port.supported[1])) { 14600 BLOGE(sc, "Invalid phy config in NVRAM (PHY1=0x%08x PHY2=0x%08x)\n", 14601 SHMEM_RD(sc, 14602 dev_info.port_hw_config[port].external_phy_config), 14603 SHMEM_RD(sc, 14604 dev_info.port_hw_config[port].external_phy_config2)); 14605 return; 14606 } 14607 14608 if (CHIP_IS_E3(sc)) 14609 sc->port.phy_addr = REG_RD(sc, MISC_REG_WC0_CTRL_PHY_ADDR); 14610 else { 14611 switch (switch_cfg) { 14612 case ELINK_SWITCH_CFG_1G: 14613 sc->port.phy_addr = 14614 REG_RD(sc, NIG_REG_SERDES0_CTRL_PHY_ADDR + port*0x10); 14615 break; 14616 case ELINK_SWITCH_CFG_10G: 14617 sc->port.phy_addr = 14618 REG_RD(sc, NIG_REG_XGXS0_CTRL_PHY_ADDR + port*0x18); 14619 break; 14620 default: 14621 BLOGE(sc, "Invalid switch config in link_config=0x%08x\n", 14622 sc->port.link_config[0]); 14623 return; 14624 } 14625 } 14626 14627 BLOGD(sc, DBG_LOAD, "PHY addr 0x%08x\n", sc->port.phy_addr); 14628 14629 /* mask what we support according to speed_cap_mask per configuration */ 14630 for (idx = 0; idx < cfg_size; idx++) { 14631 if (!(sc->link_params.speed_cap_mask[idx] & 14632 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF)) { 14633 sc->port.supported[idx] &= ~ELINK_SUPPORTED_10baseT_Half; 14634 } 14635 14636 if (!(sc->link_params.speed_cap_mask[idx] & 14637 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL)) { 14638 sc->port.supported[idx] &= ~ELINK_SUPPORTED_10baseT_Full; 14639 } 14640 14641 if (!(sc->link_params.speed_cap_mask[idx] & 14642 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF)) { 14643 sc->port.supported[idx] &= ~ELINK_SUPPORTED_100baseT_Half; 14644 } 14645 14646 if (!(sc->link_params.speed_cap_mask[idx] & 14647 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL)) { 14648 sc->port.supported[idx] &= ~ELINK_SUPPORTED_100baseT_Full; 14649 } 14650 14651 if (!(sc->link_params.speed_cap_mask[idx] & 14652 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) { 14653 sc->port.supported[idx] &= ~ELINK_SUPPORTED_1000baseT_Full; 14654 } 14655 14656 if (!(sc->link_params.speed_cap_mask[idx] & 14657 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)) { 14658 sc->port.supported[idx] &= ~ELINK_SUPPORTED_2500baseX_Full; 14659 } 14660 14661 if (!(sc->link_params.speed_cap_mask[idx] & 14662 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) { 14663 sc->port.supported[idx] &= ~ELINK_SUPPORTED_10000baseT_Full; 14664 } 14665 14666 if (!(sc->link_params.speed_cap_mask[idx] & 14667 PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) { 14668 sc->port.supported[idx] &= ~ELINK_SUPPORTED_20000baseKR2_Full; 14669 } 14670 } 14671 14672 BLOGD(sc, DBG_LOAD, "PHY supported 0=0x%08x 1=0x%08x\n", 14673 sc->port.supported[0], sc->port.supported[1]); 14674 } 14675 14676 static void 14677 bxe_link_settings_requested(struct bxe_softc *sc) 14678 { 14679 uint32_t link_config; 14680 uint32_t idx; 14681 uint32_t cfg_size = 0; 14682 14683 sc->port.advertising[0] = 0; 14684 sc->port.advertising[1] = 0; 14685 14686 switch (sc->link_params.num_phys) { 14687 case 1: 14688 case 2: 14689 cfg_size = 1; 14690 break; 14691 case 3: 14692 cfg_size = 2; 14693 break; 14694 } 14695 14696 for (idx = 0; idx < cfg_size; idx++) { 14697 sc->link_params.req_duplex[idx] = DUPLEX_FULL; 14698 link_config = sc->port.link_config[idx]; 14699 14700 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) { 14701 case PORT_FEATURE_LINK_SPEED_AUTO: 14702 if (sc->port.supported[idx] & ELINK_SUPPORTED_Autoneg) { 14703 sc->link_params.req_line_speed[idx] = ELINK_SPEED_AUTO_NEG; 14704 sc->port.advertising[idx] |= sc->port.supported[idx]; 14705 if (sc->link_params.phy[ELINK_EXT_PHY1].type == 14706 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) 14707 sc->port.advertising[idx] |= 14708 (ELINK_SUPPORTED_100baseT_Half | 14709 ELINK_SUPPORTED_100baseT_Full); 14710 } else { 14711 /* force 10G, no AN */ 14712 sc->link_params.req_line_speed[idx] = ELINK_SPEED_10000; 14713 sc->port.advertising[idx] |= 14714 (ADVERTISED_10000baseT_Full | ADVERTISED_FIBRE); 14715 continue; 14716 } 14717 break; 14718 14719 case PORT_FEATURE_LINK_SPEED_10M_FULL: 14720 if (sc->port.supported[idx] & ELINK_SUPPORTED_10baseT_Full) { 14721 sc->link_params.req_line_speed[idx] = ELINK_SPEED_10; 14722 sc->port.advertising[idx] |= (ADVERTISED_10baseT_Full | 14723 ADVERTISED_TP); 14724 } else { 14725 BLOGE(sc, "Invalid NVRAM config link_config=0x%08x " 14726 "speed_cap_mask=0x%08x\n", 14727 link_config, sc->link_params.speed_cap_mask[idx]); 14728 return; 14729 } 14730 break; 14731 14732 case PORT_FEATURE_LINK_SPEED_10M_HALF: 14733 if (sc->port.supported[idx] & ELINK_SUPPORTED_10baseT_Half) { 14734 sc->link_params.req_line_speed[idx] = ELINK_SPEED_10; 14735 sc->link_params.req_duplex[idx] = DUPLEX_HALF; 14736 sc->port.advertising[idx] |= (ADVERTISED_10baseT_Half | 14737 ADVERTISED_TP); 14738 } else { 14739 BLOGE(sc, "Invalid NVRAM config link_config=0x%08x " 14740 "speed_cap_mask=0x%08x\n", 14741 link_config, sc->link_params.speed_cap_mask[idx]); 14742 return; 14743 } 14744 break; 14745 14746 case PORT_FEATURE_LINK_SPEED_100M_FULL: 14747 if (sc->port.supported[idx] & ELINK_SUPPORTED_100baseT_Full) { 14748 sc->link_params.req_line_speed[idx] = ELINK_SPEED_100; 14749 sc->port.advertising[idx] |= (ADVERTISED_100baseT_Full | 14750 ADVERTISED_TP); 14751 } else { 14752 BLOGE(sc, "Invalid NVRAM config link_config=0x%08x " 14753 "speed_cap_mask=0x%08x\n", 14754 link_config, sc->link_params.speed_cap_mask[idx]); 14755 return; 14756 } 14757 break; 14758 14759 case PORT_FEATURE_LINK_SPEED_100M_HALF: 14760 if (sc->port.supported[idx] & ELINK_SUPPORTED_100baseT_Half) { 14761 sc->link_params.req_line_speed[idx] = ELINK_SPEED_100; 14762 sc->link_params.req_duplex[idx] = DUPLEX_HALF; 14763 sc->port.advertising[idx] |= (ADVERTISED_100baseT_Half | 14764 ADVERTISED_TP); 14765 } else { 14766 BLOGE(sc, "Invalid NVRAM config link_config=0x%08x " 14767 "speed_cap_mask=0x%08x\n", 14768 link_config, sc->link_params.speed_cap_mask[idx]); 14769 return; 14770 } 14771 break; 14772 14773 case PORT_FEATURE_LINK_SPEED_1G: 14774 if (sc->port.supported[idx] & ELINK_SUPPORTED_1000baseT_Full) { 14775 sc->link_params.req_line_speed[idx] = ELINK_SPEED_1000; 14776 sc->port.advertising[idx] |= (ADVERTISED_1000baseT_Full | 14777 ADVERTISED_TP); 14778 } else { 14779 BLOGE(sc, "Invalid NVRAM config link_config=0x%08x " 14780 "speed_cap_mask=0x%08x\n", 14781 link_config, sc->link_params.speed_cap_mask[idx]); 14782 return; 14783 } 14784 break; 14785 14786 case PORT_FEATURE_LINK_SPEED_2_5G: 14787 if (sc->port.supported[idx] & ELINK_SUPPORTED_2500baseX_Full) { 14788 sc->link_params.req_line_speed[idx] = ELINK_SPEED_2500; 14789 sc->port.advertising[idx] |= (ADVERTISED_2500baseX_Full | 14790 ADVERTISED_TP); 14791 } else { 14792 BLOGE(sc, "Invalid NVRAM config link_config=0x%08x " 14793 "speed_cap_mask=0x%08x\n", 14794 link_config, sc->link_params.speed_cap_mask[idx]); 14795 return; 14796 } 14797 break; 14798 14799 case PORT_FEATURE_LINK_SPEED_10G_CX4: 14800 if (sc->port.supported[idx] & ELINK_SUPPORTED_10000baseT_Full) { 14801 sc->link_params.req_line_speed[idx] = ELINK_SPEED_10000; 14802 sc->port.advertising[idx] |= (ADVERTISED_10000baseT_Full | 14803 ADVERTISED_FIBRE); 14804 } else { 14805 BLOGE(sc, "Invalid NVRAM config link_config=0x%08x " 14806 "speed_cap_mask=0x%08x\n", 14807 link_config, sc->link_params.speed_cap_mask[idx]); 14808 return; 14809 } 14810 break; 14811 14812 case PORT_FEATURE_LINK_SPEED_20G: 14813 sc->link_params.req_line_speed[idx] = ELINK_SPEED_20000; 14814 break; 14815 14816 default: 14817 BLOGE(sc, "Invalid NVRAM config link_config=0x%08x " 14818 "speed_cap_mask=0x%08x\n", 14819 link_config, sc->link_params.speed_cap_mask[idx]); 14820 sc->link_params.req_line_speed[idx] = ELINK_SPEED_AUTO_NEG; 14821 sc->port.advertising[idx] = sc->port.supported[idx]; 14822 break; 14823 } 14824 14825 sc->link_params.req_flow_ctrl[idx] = 14826 (link_config & PORT_FEATURE_FLOW_CONTROL_MASK); 14827 14828 if (sc->link_params.req_flow_ctrl[idx] == ELINK_FLOW_CTRL_AUTO) { 14829 if (!(sc->port.supported[idx] & ELINK_SUPPORTED_Autoneg)) { 14830 sc->link_params.req_flow_ctrl[idx] = ELINK_FLOW_CTRL_NONE; 14831 } else { 14832 bxe_set_requested_fc(sc); 14833 } 14834 } 14835 14836 BLOGD(sc, DBG_LOAD, "req_line_speed=%d req_duplex=%d " 14837 "req_flow_ctrl=0x%x advertising=0x%x\n", 14838 sc->link_params.req_line_speed[idx], 14839 sc->link_params.req_duplex[idx], 14840 sc->link_params.req_flow_ctrl[idx], 14841 sc->port.advertising[idx]); 14842 } 14843 } 14844 14845 static void 14846 bxe_get_phy_info(struct bxe_softc *sc) 14847 { 14848 uint8_t port = SC_PORT(sc); 14849 uint32_t config = sc->port.config; 14850 uint32_t eee_mode; 14851 14852 /* shmem data already read in bxe_get_shmem_info() */ 14853 14854 BLOGD(sc, DBG_LOAD, "lane_config=0x%08x speed_cap_mask0=0x%08x " 14855 "link_config0=0x%08x\n", 14856 sc->link_params.lane_config, 14857 sc->link_params.speed_cap_mask[0], 14858 sc->port.link_config[0]); 14859 14860 bxe_link_settings_supported(sc, sc->link_params.switch_cfg); 14861 bxe_link_settings_requested(sc); 14862 14863 if (sc->autogreeen == AUTO_GREEN_FORCE_ON) { 14864 sc->link_params.feature_config_flags |= 14865 ELINK_FEATURE_CONFIG_AUTOGREEEN_ENABLED; 14866 } else if (sc->autogreeen == AUTO_GREEN_FORCE_OFF) { 14867 sc->link_params.feature_config_flags &= 14868 ~ELINK_FEATURE_CONFIG_AUTOGREEEN_ENABLED; 14869 } else if (config & PORT_FEAT_CFG_AUTOGREEEN_ENABLED) { 14870 sc->link_params.feature_config_flags |= 14871 ELINK_FEATURE_CONFIG_AUTOGREEEN_ENABLED; 14872 } 14873 14874 /* configure link feature according to nvram value */ 14875 eee_mode = 14876 (((SHMEM_RD(sc, dev_info.port_feature_config[port].eee_power_mode)) & 14877 PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >> 14878 PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT); 14879 if (eee_mode != PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED) { 14880 sc->link_params.eee_mode = (ELINK_EEE_MODE_ADV_LPI | 14881 ELINK_EEE_MODE_ENABLE_LPI | 14882 ELINK_EEE_MODE_OUTPUT_TIME); 14883 } else { 14884 sc->link_params.eee_mode = 0; 14885 } 14886 14887 /* get the media type */ 14888 bxe_media_detect(sc); 14889 } 14890 14891 static void 14892 bxe_get_params(struct bxe_softc *sc) 14893 { 14894 /* get user tunable params */ 14895 bxe_get_tunable_params(sc); 14896 14897 /* select the RX and TX ring sizes */ 14898 sc->tx_ring_size = TX_BD_USABLE; 14899 sc->rx_ring_size = RX_BD_USABLE; 14900 14901 /* XXX disable WoL */ 14902 sc->wol = 0; 14903 } 14904 14905 static void 14906 bxe_set_modes_bitmap(struct bxe_softc *sc) 14907 { 14908 uint32_t flags = 0; 14909 14910 if (CHIP_REV_IS_FPGA(sc)) { 14911 SET_FLAGS(flags, MODE_FPGA); 14912 } else if (CHIP_REV_IS_EMUL(sc)) { 14913 SET_FLAGS(flags, MODE_EMUL); 14914 } else { 14915 SET_FLAGS(flags, MODE_ASIC); 14916 } 14917 14918 if (CHIP_IS_MODE_4_PORT(sc)) { 14919 SET_FLAGS(flags, MODE_PORT4); 14920 } else { 14921 SET_FLAGS(flags, MODE_PORT2); 14922 } 14923 14924 if (CHIP_IS_E2(sc)) { 14925 SET_FLAGS(flags, MODE_E2); 14926 } else if (CHIP_IS_E3(sc)) { 14927 SET_FLAGS(flags, MODE_E3); 14928 if (CHIP_REV(sc) == CHIP_REV_Ax) { 14929 SET_FLAGS(flags, MODE_E3_A0); 14930 } else /*if (CHIP_REV(sc) == CHIP_REV_Bx)*/ { 14931 SET_FLAGS(flags, MODE_E3_B0 | MODE_COS3); 14932 } 14933 } 14934 14935 if (IS_MF(sc)) { 14936 SET_FLAGS(flags, MODE_MF); 14937 switch (sc->devinfo.mf_info.mf_mode) { 14938 case MULTI_FUNCTION_SD: 14939 SET_FLAGS(flags, MODE_MF_SD); 14940 break; 14941 case MULTI_FUNCTION_SI: 14942 SET_FLAGS(flags, MODE_MF_SI); 14943 break; 14944 case MULTI_FUNCTION_AFEX: 14945 SET_FLAGS(flags, MODE_MF_AFEX); 14946 break; 14947 } 14948 } else { 14949 SET_FLAGS(flags, MODE_SF); 14950 } 14951 14952 #if defined(__LITTLE_ENDIAN) 14953 SET_FLAGS(flags, MODE_LITTLE_ENDIAN); 14954 #else /* __BIG_ENDIAN */ 14955 SET_FLAGS(flags, MODE_BIG_ENDIAN); 14956 #endif 14957 14958 INIT_MODE_FLAGS(sc) = flags; 14959 } 14960 14961 static int 14962 bxe_alloc_hsi_mem(struct bxe_softc *sc) 14963 { 14964 struct bxe_fastpath *fp; 14965 bus_addr_t busaddr; 14966 int max_agg_queues; 14967 int max_segments; 14968 bus_size_t max_size; 14969 bus_size_t max_seg_size; 14970 char buf[32]; 14971 int rc; 14972 int i, j; 14973 14974 /* XXX zero out all vars here and call bxe_alloc_hsi_mem on error */ 14975 14976 /* allocate the parent bus DMA tag */ 14977 rc = bus_dma_tag_create(bus_get_dma_tag(sc->dev), /* parent tag */ 14978 1, /* alignment */ 14979 0, /* boundary limit */ 14980 BUS_SPACE_MAXADDR, /* restricted low */ 14981 BUS_SPACE_MAXADDR, /* restricted hi */ 14982 NULL, /* addr filter() */ 14983 NULL, /* addr filter() arg */ 14984 BUS_SPACE_MAXSIZE_32BIT, /* max map size */ 14985 BUS_SPACE_UNRESTRICTED, /* num discontinuous */ 14986 BUS_SPACE_MAXSIZE_32BIT, /* max seg size */ 14987 0, /* flags */ 14988 NULL, /* lock() */ 14989 NULL, /* lock() arg */ 14990 &sc->parent_dma_tag); /* returned dma tag */ 14991 if (rc != 0) { 14992 BLOGE(sc, "Failed to alloc parent DMA tag (%d)!\n", rc); 14993 return (1); 14994 } 14995 14996 /************************/ 14997 /* DEFAULT STATUS BLOCK */ 14998 /************************/ 14999 15000 if (bxe_dma_alloc(sc, sizeof(struct host_sp_status_block), 15001 &sc->def_sb_dma, "default status block") != 0) { 15002 /* XXX */ 15003 bus_dma_tag_destroy(sc->parent_dma_tag); 15004 return (1); 15005 } 15006 15007 sc->def_sb = (struct host_sp_status_block *)sc->def_sb_dma.vaddr; 15008 15009 /***************/ 15010 /* EVENT QUEUE */ 15011 /***************/ 15012 15013 if (bxe_dma_alloc(sc, BCM_PAGE_SIZE, 15014 &sc->eq_dma, "event queue") != 0) { 15015 /* XXX */ 15016 bxe_dma_free(sc, &sc->def_sb_dma); 15017 sc->def_sb = NULL; 15018 bus_dma_tag_destroy(sc->parent_dma_tag); 15019 return (1); 15020 } 15021 15022 sc->eq = (union event_ring_elem * )sc->eq_dma.vaddr; 15023 15024 /*************/ 15025 /* SLOW PATH */ 15026 /*************/ 15027 15028 if (bxe_dma_alloc(sc, sizeof(struct bxe_slowpath), 15029 &sc->sp_dma, "slow path") != 0) { 15030 /* XXX */ 15031 bxe_dma_free(sc, &sc->eq_dma); 15032 sc->eq = NULL; 15033 bxe_dma_free(sc, &sc->def_sb_dma); 15034 sc->def_sb = NULL; 15035 bus_dma_tag_destroy(sc->parent_dma_tag); 15036 return (1); 15037 } 15038 15039 sc->sp = (struct bxe_slowpath *)sc->sp_dma.vaddr; 15040 15041 /*******************/ 15042 /* SLOW PATH QUEUE */ 15043 /*******************/ 15044 15045 if (bxe_dma_alloc(sc, BCM_PAGE_SIZE, 15046 &sc->spq_dma, "slow path queue") != 0) { 15047 /* XXX */ 15048 bxe_dma_free(sc, &sc->sp_dma); 15049 sc->sp = NULL; 15050 bxe_dma_free(sc, &sc->eq_dma); 15051 sc->eq = NULL; 15052 bxe_dma_free(sc, &sc->def_sb_dma); 15053 sc->def_sb = NULL; 15054 bus_dma_tag_destroy(sc->parent_dma_tag); 15055 return (1); 15056 } 15057 15058 sc->spq = (struct eth_spe *)sc->spq_dma.vaddr; 15059 15060 /***************************/ 15061 /* FW DECOMPRESSION BUFFER */ 15062 /***************************/ 15063 15064 if (bxe_dma_alloc(sc, FW_BUF_SIZE, &sc->gz_buf_dma, 15065 "fw decompression buffer") != 0) { 15066 /* XXX */ 15067 bxe_dma_free(sc, &sc->spq_dma); 15068 sc->spq = NULL; 15069 bxe_dma_free(sc, &sc->sp_dma); 15070 sc->sp = NULL; 15071 bxe_dma_free(sc, &sc->eq_dma); 15072 sc->eq = NULL; 15073 bxe_dma_free(sc, &sc->def_sb_dma); 15074 sc->def_sb = NULL; 15075 bus_dma_tag_destroy(sc->parent_dma_tag); 15076 return (1); 15077 } 15078 15079 sc->gz_buf = (void *)sc->gz_buf_dma.vaddr; 15080 15081 if ((sc->gz_strm = 15082 malloc(sizeof(*sc->gz_strm), M_DEVBUF, M_NOWAIT)) == NULL) { 15083 /* XXX */ 15084 bxe_dma_free(sc, &sc->gz_buf_dma); 15085 sc->gz_buf = NULL; 15086 bxe_dma_free(sc, &sc->spq_dma); 15087 sc->spq = NULL; 15088 bxe_dma_free(sc, &sc->sp_dma); 15089 sc->sp = NULL; 15090 bxe_dma_free(sc, &sc->eq_dma); 15091 sc->eq = NULL; 15092 bxe_dma_free(sc, &sc->def_sb_dma); 15093 sc->def_sb = NULL; 15094 bus_dma_tag_destroy(sc->parent_dma_tag); 15095 return (1); 15096 } 15097 15098 /*************/ 15099 /* FASTPATHS */ 15100 /*************/ 15101 15102 /* allocate DMA memory for each fastpath structure */ 15103 for (i = 0; i < sc->num_queues; i++) { 15104 fp = &sc->fp[i]; 15105 fp->sc = sc; 15106 fp->index = i; 15107 15108 /*******************/ 15109 /* FP STATUS BLOCK */ 15110 /*******************/ 15111 15112 snprintf(buf, sizeof(buf), "fp %d status block", i); 15113 if (bxe_dma_alloc(sc, sizeof(union bxe_host_hc_status_block), 15114 &fp->sb_dma, buf) != 0) { 15115 /* XXX unwind and free previous fastpath allocations */ 15116 BLOGE(sc, "Failed to alloc %s\n", buf); 15117 return (1); 15118 } else { 15119 if (CHIP_IS_E2E3(sc)) { 15120 fp->status_block.e2_sb = 15121 (struct host_hc_status_block_e2 *)fp->sb_dma.vaddr; 15122 } else { 15123 fp->status_block.e1x_sb = 15124 (struct host_hc_status_block_e1x *)fp->sb_dma.vaddr; 15125 } 15126 } 15127 15128 /******************/ 15129 /* FP TX BD CHAIN */ 15130 /******************/ 15131 15132 snprintf(buf, sizeof(buf), "fp %d tx bd chain", i); 15133 if (bxe_dma_alloc(sc, (BCM_PAGE_SIZE * TX_BD_NUM_PAGES), 15134 &fp->tx_dma, buf) != 0) { 15135 /* XXX unwind and free previous fastpath allocations */ 15136 BLOGE(sc, "Failed to alloc %s\n", buf); 15137 return (1); 15138 } else { 15139 fp->tx_chain = (union eth_tx_bd_types *)fp->tx_dma.vaddr; 15140 } 15141 15142 /* link together the tx bd chain pages */ 15143 for (j = 1; j <= TX_BD_NUM_PAGES; j++) { 15144 /* index into the tx bd chain array to last entry per page */ 15145 struct eth_tx_next_bd *tx_next_bd = 15146 &fp->tx_chain[TX_BD_TOTAL_PER_PAGE * j - 1].next_bd; 15147 /* point to the next page and wrap from last page */ 15148 busaddr = (fp->tx_dma.paddr + 15149 (BCM_PAGE_SIZE * (j % TX_BD_NUM_PAGES))); 15150 tx_next_bd->addr_hi = htole32(U64_HI(busaddr)); 15151 tx_next_bd->addr_lo = htole32(U64_LO(busaddr)); 15152 } 15153 15154 /******************/ 15155 /* FP RX BD CHAIN */ 15156 /******************/ 15157 15158 snprintf(buf, sizeof(buf), "fp %d rx bd chain", i); 15159 if (bxe_dma_alloc(sc, (BCM_PAGE_SIZE * RX_BD_NUM_PAGES), 15160 &fp->rx_dma, buf) != 0) { 15161 /* XXX unwind and free previous fastpath allocations */ 15162 BLOGE(sc, "Failed to alloc %s\n", buf); 15163 return (1); 15164 } else { 15165 fp->rx_chain = (struct eth_rx_bd *)fp->rx_dma.vaddr; 15166 } 15167 15168 /* link together the rx bd chain pages */ 15169 for (j = 1; j <= RX_BD_NUM_PAGES; j++) { 15170 /* index into the rx bd chain array to last entry per page */ 15171 struct eth_rx_bd *rx_bd = 15172 &fp->rx_chain[RX_BD_TOTAL_PER_PAGE * j - 2]; 15173 /* point to the next page and wrap from last page */ 15174 busaddr = (fp->rx_dma.paddr + 15175 (BCM_PAGE_SIZE * (j % RX_BD_NUM_PAGES))); 15176 rx_bd->addr_hi = htole32(U64_HI(busaddr)); 15177 rx_bd->addr_lo = htole32(U64_LO(busaddr)); 15178 } 15179 15180 /*******************/ 15181 /* FP RX RCQ CHAIN */ 15182 /*******************/ 15183 15184 snprintf(buf, sizeof(buf), "fp %d rcq chain", i); 15185 if (bxe_dma_alloc(sc, (BCM_PAGE_SIZE * RCQ_NUM_PAGES), 15186 &fp->rcq_dma, buf) != 0) { 15187 /* XXX unwind and free previous fastpath allocations */ 15188 BLOGE(sc, "Failed to alloc %s\n", buf); 15189 return (1); 15190 } else { 15191 fp->rcq_chain = (union eth_rx_cqe *)fp->rcq_dma.vaddr; 15192 } 15193 15194 /* link together the rcq chain pages */ 15195 for (j = 1; j <= RCQ_NUM_PAGES; j++) { 15196 /* index into the rcq chain array to last entry per page */ 15197 struct eth_rx_cqe_next_page *rx_cqe_next = 15198 (struct eth_rx_cqe_next_page *) 15199 &fp->rcq_chain[RCQ_TOTAL_PER_PAGE * j - 1]; 15200 /* point to the next page and wrap from last page */ 15201 busaddr = (fp->rcq_dma.paddr + 15202 (BCM_PAGE_SIZE * (j % RCQ_NUM_PAGES))); 15203 rx_cqe_next->addr_hi = htole32(U64_HI(busaddr)); 15204 rx_cqe_next->addr_lo = htole32(U64_LO(busaddr)); 15205 } 15206 15207 /*******************/ 15208 /* FP RX SGE CHAIN */ 15209 /*******************/ 15210 15211 snprintf(buf, sizeof(buf), "fp %d sge chain", i); 15212 if (bxe_dma_alloc(sc, (BCM_PAGE_SIZE * RX_SGE_NUM_PAGES), 15213 &fp->rx_sge_dma, buf) != 0) { 15214 /* XXX unwind and free previous fastpath allocations */ 15215 BLOGE(sc, "Failed to alloc %s\n", buf); 15216 return (1); 15217 } else { 15218 fp->rx_sge_chain = (struct eth_rx_sge *)fp->rx_sge_dma.vaddr; 15219 } 15220 15221 /* link together the sge chain pages */ 15222 for (j = 1; j <= RX_SGE_NUM_PAGES; j++) { 15223 /* index into the rcq chain array to last entry per page */ 15224 struct eth_rx_sge *rx_sge = 15225 &fp->rx_sge_chain[RX_SGE_TOTAL_PER_PAGE * j - 2]; 15226 /* point to the next page and wrap from last page */ 15227 busaddr = (fp->rx_sge_dma.paddr + 15228 (BCM_PAGE_SIZE * (j % RX_SGE_NUM_PAGES))); 15229 rx_sge->addr_hi = htole32(U64_HI(busaddr)); 15230 rx_sge->addr_lo = htole32(U64_LO(busaddr)); 15231 } 15232 15233 /***********************/ 15234 /* FP TX MBUF DMA MAPS */ 15235 /***********************/ 15236 15237 /* set required sizes before mapping to conserve resources */ 15238 if (sc->ifnet->if_capenable & (IFCAP_TSO4 | IFCAP_TSO6)) { 15239 max_size = BXE_TSO_MAX_SIZE; 15240 max_segments = BXE_TSO_MAX_SEGMENTS; 15241 max_seg_size = BXE_TSO_MAX_SEG_SIZE; 15242 } else { 15243 max_size = (MCLBYTES * BXE_MAX_SEGMENTS); 15244 max_segments = BXE_MAX_SEGMENTS; 15245 max_seg_size = MCLBYTES; 15246 } 15247 15248 /* create a dma tag for the tx mbufs */ 15249 rc = bus_dma_tag_create(sc->parent_dma_tag, /* parent tag */ 15250 1, /* alignment */ 15251 0, /* boundary limit */ 15252 BUS_SPACE_MAXADDR, /* restricted low */ 15253 BUS_SPACE_MAXADDR, /* restricted hi */ 15254 NULL, /* addr filter() */ 15255 NULL, /* addr filter() arg */ 15256 max_size, /* max map size */ 15257 max_segments, /* num discontinuous */ 15258 max_seg_size, /* max seg size */ 15259 0, /* flags */ 15260 NULL, /* lock() */ 15261 NULL, /* lock() arg */ 15262 &fp->tx_mbuf_tag); /* returned dma tag */ 15263 if (rc != 0) { 15264 /* XXX unwind and free previous fastpath allocations */ 15265 BLOGE(sc, "Failed to create dma tag for " 15266 "'fp %d tx mbufs' (%d)\n", 15267 i, rc); 15268 return (1); 15269 } 15270 15271 /* create dma maps for each of the tx mbuf clusters */ 15272 for (j = 0; j < TX_BD_TOTAL; j++) { 15273 if (bus_dmamap_create(fp->tx_mbuf_tag, 15274 BUS_DMA_NOWAIT, 15275 &fp->tx_mbuf_chain[j].m_map)) { 15276 /* XXX unwind and free previous fastpath allocations */ 15277 BLOGE(sc, "Failed to create dma map for " 15278 "'fp %d tx mbuf %d' (%d)\n", 15279 i, j, rc); 15280 return (1); 15281 } 15282 } 15283 15284 /***********************/ 15285 /* FP RX MBUF DMA MAPS */ 15286 /***********************/ 15287 15288 /* create a dma tag for the rx mbufs */ 15289 rc = bus_dma_tag_create(sc->parent_dma_tag, /* parent tag */ 15290 1, /* alignment */ 15291 0, /* boundary limit */ 15292 BUS_SPACE_MAXADDR, /* restricted low */ 15293 BUS_SPACE_MAXADDR, /* restricted hi */ 15294 NULL, /* addr filter() */ 15295 NULL, /* addr filter() arg */ 15296 MJUM9BYTES, /* max map size */ 15297 1, /* num discontinuous */ 15298 MJUM9BYTES, /* max seg size */ 15299 0, /* flags */ 15300 NULL, /* lock() */ 15301 NULL, /* lock() arg */ 15302 &fp->rx_mbuf_tag); /* returned dma tag */ 15303 if (rc != 0) { 15304 /* XXX unwind and free previous fastpath allocations */ 15305 BLOGE(sc, "Failed to create dma tag for " 15306 "'fp %d rx mbufs' (%d)\n", 15307 i, rc); 15308 return (1); 15309 } 15310 15311 /* create dma maps for each of the rx mbuf clusters */ 15312 for (j = 0; j < RX_BD_TOTAL; j++) { 15313 if (bus_dmamap_create(fp->rx_mbuf_tag, 15314 BUS_DMA_NOWAIT, 15315 &fp->rx_mbuf_chain[j].m_map)) { 15316 /* XXX unwind and free previous fastpath allocations */ 15317 BLOGE(sc, "Failed to create dma map for " 15318 "'fp %d rx mbuf %d' (%d)\n", 15319 i, j, rc); 15320 return (1); 15321 } 15322 } 15323 15324 /* create dma map for the spare rx mbuf cluster */ 15325 if (bus_dmamap_create(fp->rx_mbuf_tag, 15326 BUS_DMA_NOWAIT, 15327 &fp->rx_mbuf_spare_map)) { 15328 /* XXX unwind and free previous fastpath allocations */ 15329 BLOGE(sc, "Failed to create dma map for " 15330 "'fp %d spare rx mbuf' (%d)\n", 15331 i, rc); 15332 return (1); 15333 } 15334 15335 /***************************/ 15336 /* FP RX SGE MBUF DMA MAPS */ 15337 /***************************/ 15338 15339 /* create a dma tag for the rx sge mbufs */ 15340 rc = bus_dma_tag_create(sc->parent_dma_tag, /* parent tag */ 15341 1, /* alignment */ 15342 0, /* boundary limit */ 15343 BUS_SPACE_MAXADDR, /* restricted low */ 15344 BUS_SPACE_MAXADDR, /* restricted hi */ 15345 NULL, /* addr filter() */ 15346 NULL, /* addr filter() arg */ 15347 BCM_PAGE_SIZE, /* max map size */ 15348 1, /* num discontinuous */ 15349 BCM_PAGE_SIZE, /* max seg size */ 15350 0, /* flags */ 15351 NULL, /* lock() */ 15352 NULL, /* lock() arg */ 15353 &fp->rx_sge_mbuf_tag); /* returned dma tag */ 15354 if (rc != 0) { 15355 /* XXX unwind and free previous fastpath allocations */ 15356 BLOGE(sc, "Failed to create dma tag for " 15357 "'fp %d rx sge mbufs' (%d)\n", 15358 i, rc); 15359 return (1); 15360 } 15361 15362 /* create dma maps for the rx sge mbuf clusters */ 15363 for (j = 0; j < RX_SGE_TOTAL; j++) { 15364 if (bus_dmamap_create(fp->rx_sge_mbuf_tag, 15365 BUS_DMA_NOWAIT, 15366 &fp->rx_sge_mbuf_chain[j].m_map)) { 15367 /* XXX unwind and free previous fastpath allocations */ 15368 BLOGE(sc, "Failed to create dma map for " 15369 "'fp %d rx sge mbuf %d' (%d)\n", 15370 i, j, rc); 15371 return (1); 15372 } 15373 } 15374 15375 /* create dma map for the spare rx sge mbuf cluster */ 15376 if (bus_dmamap_create(fp->rx_sge_mbuf_tag, 15377 BUS_DMA_NOWAIT, 15378 &fp->rx_sge_mbuf_spare_map)) { 15379 /* XXX unwind and free previous fastpath allocations */ 15380 BLOGE(sc, "Failed to create dma map for " 15381 "'fp %d spare rx sge mbuf' (%d)\n", 15382 i, rc); 15383 return (1); 15384 } 15385 15386 /***************************/ 15387 /* FP RX TPA MBUF DMA MAPS */ 15388 /***************************/ 15389 15390 /* create dma maps for the rx tpa mbuf clusters */ 15391 max_agg_queues = MAX_AGG_QS(sc); 15392 15393 for (j = 0; j < max_agg_queues; j++) { 15394 if (bus_dmamap_create(fp->rx_mbuf_tag, 15395 BUS_DMA_NOWAIT, 15396 &fp->rx_tpa_info[j].bd.m_map)) { 15397 /* XXX unwind and free previous fastpath allocations */ 15398 BLOGE(sc, "Failed to create dma map for " 15399 "'fp %d rx tpa mbuf %d' (%d)\n", 15400 i, j, rc); 15401 return (1); 15402 } 15403 } 15404 15405 /* create dma map for the spare rx tpa mbuf cluster */ 15406 if (bus_dmamap_create(fp->rx_mbuf_tag, 15407 BUS_DMA_NOWAIT, 15408 &fp->rx_tpa_info_mbuf_spare_map)) { 15409 /* XXX unwind and free previous fastpath allocations */ 15410 BLOGE(sc, "Failed to create dma map for " 15411 "'fp %d spare rx tpa mbuf' (%d)\n", 15412 i, rc); 15413 return (1); 15414 } 15415 15416 bxe_init_sge_ring_bit_mask(fp); 15417 } 15418 15419 return (0); 15420 } 15421 15422 static void 15423 bxe_free_hsi_mem(struct bxe_softc *sc) 15424 { 15425 struct bxe_fastpath *fp; 15426 int max_agg_queues; 15427 int i, j; 15428 15429 if (sc->parent_dma_tag == NULL) { 15430 return; /* assume nothing was allocated */ 15431 } 15432 15433 for (i = 0; i < sc->num_queues; i++) { 15434 fp = &sc->fp[i]; 15435 15436 /*******************/ 15437 /* FP STATUS BLOCK */ 15438 /*******************/ 15439 15440 bxe_dma_free(sc, &fp->sb_dma); 15441 memset(&fp->status_block, 0, sizeof(fp->status_block)); 15442 15443 /******************/ 15444 /* FP TX BD CHAIN */ 15445 /******************/ 15446 15447 bxe_dma_free(sc, &fp->tx_dma); 15448 fp->tx_chain = NULL; 15449 15450 /******************/ 15451 /* FP RX BD CHAIN */ 15452 /******************/ 15453 15454 bxe_dma_free(sc, &fp->rx_dma); 15455 fp->rx_chain = NULL; 15456 15457 /*******************/ 15458 /* FP RX RCQ CHAIN */ 15459 /*******************/ 15460 15461 bxe_dma_free(sc, &fp->rcq_dma); 15462 fp->rcq_chain = NULL; 15463 15464 /*******************/ 15465 /* FP RX SGE CHAIN */ 15466 /*******************/ 15467 15468 bxe_dma_free(sc, &fp->rx_sge_dma); 15469 fp->rx_sge_chain = NULL; 15470 15471 /***********************/ 15472 /* FP TX MBUF DMA MAPS */ 15473 /***********************/ 15474 15475 if (fp->tx_mbuf_tag != NULL) { 15476 for (j = 0; j < TX_BD_TOTAL; j++) { 15477 if (fp->tx_mbuf_chain[j].m_map != NULL) { 15478 bus_dmamap_unload(fp->tx_mbuf_tag, 15479 fp->tx_mbuf_chain[j].m_map); 15480 bus_dmamap_destroy(fp->tx_mbuf_tag, 15481 fp->tx_mbuf_chain[j].m_map); 15482 } 15483 } 15484 15485 bus_dma_tag_destroy(fp->tx_mbuf_tag); 15486 fp->tx_mbuf_tag = NULL; 15487 } 15488 15489 /***********************/ 15490 /* FP RX MBUF DMA MAPS */ 15491 /***********************/ 15492 15493 if (fp->rx_mbuf_tag != NULL) { 15494 for (j = 0; j < RX_BD_TOTAL; j++) { 15495 if (fp->rx_mbuf_chain[j].m_map != NULL) { 15496 bus_dmamap_unload(fp->rx_mbuf_tag, 15497 fp->rx_mbuf_chain[j].m_map); 15498 bus_dmamap_destroy(fp->rx_mbuf_tag, 15499 fp->rx_mbuf_chain[j].m_map); 15500 } 15501 } 15502 15503 if (fp->rx_mbuf_spare_map != NULL) { 15504 bus_dmamap_unload(fp->rx_mbuf_tag, fp->rx_mbuf_spare_map); 15505 bus_dmamap_destroy(fp->rx_mbuf_tag, fp->rx_mbuf_spare_map); 15506 } 15507 15508 /***************************/ 15509 /* FP RX TPA MBUF DMA MAPS */ 15510 /***************************/ 15511 15512 max_agg_queues = MAX_AGG_QS(sc); 15513 15514 for (j = 0; j < max_agg_queues; j++) { 15515 if (fp->rx_tpa_info[j].bd.m_map != NULL) { 15516 bus_dmamap_unload(fp->rx_mbuf_tag, 15517 fp->rx_tpa_info[j].bd.m_map); 15518 bus_dmamap_destroy(fp->rx_mbuf_tag, 15519 fp->rx_tpa_info[j].bd.m_map); 15520 } 15521 } 15522 15523 if (fp->rx_tpa_info_mbuf_spare_map != NULL) { 15524 bus_dmamap_unload(fp->rx_mbuf_tag, 15525 fp->rx_tpa_info_mbuf_spare_map); 15526 bus_dmamap_destroy(fp->rx_mbuf_tag, 15527 fp->rx_tpa_info_mbuf_spare_map); 15528 } 15529 15530 bus_dma_tag_destroy(fp->rx_mbuf_tag); 15531 fp->rx_mbuf_tag = NULL; 15532 } 15533 15534 /***************************/ 15535 /* FP RX SGE MBUF DMA MAPS */ 15536 /***************************/ 15537 15538 if (fp->rx_sge_mbuf_tag != NULL) { 15539 for (j = 0; j < RX_SGE_TOTAL; j++) { 15540 if (fp->rx_sge_mbuf_chain[j].m_map != NULL) { 15541 bus_dmamap_unload(fp->rx_sge_mbuf_tag, 15542 fp->rx_sge_mbuf_chain[j].m_map); 15543 bus_dmamap_destroy(fp->rx_sge_mbuf_tag, 15544 fp->rx_sge_mbuf_chain[j].m_map); 15545 } 15546 } 15547 15548 if (fp->rx_sge_mbuf_spare_map != NULL) { 15549 bus_dmamap_unload(fp->rx_sge_mbuf_tag, 15550 fp->rx_sge_mbuf_spare_map); 15551 bus_dmamap_destroy(fp->rx_sge_mbuf_tag, 15552 fp->rx_sge_mbuf_spare_map); 15553 } 15554 15555 bus_dma_tag_destroy(fp->rx_sge_mbuf_tag); 15556 fp->rx_sge_mbuf_tag = NULL; 15557 } 15558 } 15559 15560 /***************************/ 15561 /* FW DECOMPRESSION BUFFER */ 15562 /***************************/ 15563 15564 bxe_dma_free(sc, &sc->gz_buf_dma); 15565 sc->gz_buf = NULL; 15566 free(sc->gz_strm, M_DEVBUF); 15567 sc->gz_strm = NULL; 15568 15569 /*******************/ 15570 /* SLOW PATH QUEUE */ 15571 /*******************/ 15572 15573 bxe_dma_free(sc, &sc->spq_dma); 15574 sc->spq = NULL; 15575 15576 /*************/ 15577 /* SLOW PATH */ 15578 /*************/ 15579 15580 bxe_dma_free(sc, &sc->sp_dma); 15581 sc->sp = NULL; 15582 15583 /***************/ 15584 /* EVENT QUEUE */ 15585 /***************/ 15586 15587 bxe_dma_free(sc, &sc->eq_dma); 15588 sc->eq = NULL; 15589 15590 /************************/ 15591 /* DEFAULT STATUS BLOCK */ 15592 /************************/ 15593 15594 bxe_dma_free(sc, &sc->def_sb_dma); 15595 sc->def_sb = NULL; 15596 15597 bus_dma_tag_destroy(sc->parent_dma_tag); 15598 sc->parent_dma_tag = NULL; 15599 } 15600 15601 /* 15602 * Previous driver DMAE transaction may have occurred when pre-boot stage 15603 * ended and boot began. This would invalidate the addresses of the 15604 * transaction, resulting in was-error bit set in the PCI causing all 15605 * hw-to-host PCIe transactions to timeout. If this happened we want to clear 15606 * the interrupt which detected this from the pglueb and the was-done bit 15607 */ 15608 static void 15609 bxe_prev_interrupted_dmae(struct bxe_softc *sc) 15610 { 15611 uint32_t val; 15612 15613 if (!CHIP_IS_E1x(sc)) { 15614 val = REG_RD(sc, PGLUE_B_REG_PGLUE_B_INT_STS); 15615 if (val & PGLUE_B_PGLUE_B_INT_STS_REG_WAS_ERROR_ATTN) { 15616 BLOGD(sc, DBG_LOAD, 15617 "Clearing 'was-error' bit that was set in pglueb"); 15618 REG_WR(sc, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, 1 << SC_FUNC(sc)); 15619 } 15620 } 15621 } 15622 15623 static int 15624 bxe_prev_mcp_done(struct bxe_softc *sc) 15625 { 15626 uint32_t rc = bxe_fw_command(sc, DRV_MSG_CODE_UNLOAD_DONE, 15627 DRV_MSG_CODE_UNLOAD_SKIP_LINK_RESET); 15628 if (!rc) { 15629 BLOGE(sc, "MCP response failure, aborting\n"); 15630 return (-1); 15631 } 15632 15633 return (0); 15634 } 15635 15636 static struct bxe_prev_list_node * 15637 bxe_prev_path_get_entry(struct bxe_softc *sc) 15638 { 15639 struct bxe_prev_list_node *tmp; 15640 15641 LIST_FOREACH(tmp, &bxe_prev_list, node) { 15642 if ((sc->pcie_bus == tmp->bus) && 15643 (sc->pcie_device == tmp->slot) && 15644 (SC_PATH(sc) == tmp->path)) { 15645 return (tmp); 15646 } 15647 } 15648 15649 return (NULL); 15650 } 15651 15652 static uint8_t 15653 bxe_prev_is_path_marked(struct bxe_softc *sc) 15654 { 15655 struct bxe_prev_list_node *tmp; 15656 int rc = FALSE; 15657 15658 mtx_lock(&bxe_prev_mtx); 15659 15660 tmp = bxe_prev_path_get_entry(sc); 15661 if (tmp) { 15662 if (tmp->aer) { 15663 BLOGD(sc, DBG_LOAD, 15664 "Path %d/%d/%d was marked by AER\n", 15665 sc->pcie_bus, sc->pcie_device, SC_PATH(sc)); 15666 } else { 15667 rc = TRUE; 15668 BLOGD(sc, DBG_LOAD, 15669 "Path %d/%d/%d was already cleaned from previous drivers\n", 15670 sc->pcie_bus, sc->pcie_device, SC_PATH(sc)); 15671 } 15672 } 15673 15674 mtx_unlock(&bxe_prev_mtx); 15675 15676 return (rc); 15677 } 15678 15679 static int 15680 bxe_prev_mark_path(struct bxe_softc *sc, 15681 uint8_t after_undi) 15682 { 15683 struct bxe_prev_list_node *tmp; 15684 15685 mtx_lock(&bxe_prev_mtx); 15686 15687 /* Check whether the entry for this path already exists */ 15688 tmp = bxe_prev_path_get_entry(sc); 15689 if (tmp) { 15690 if (!tmp->aer) { 15691 BLOGD(sc, DBG_LOAD, 15692 "Re-marking AER in path %d/%d/%d\n", 15693 sc->pcie_bus, sc->pcie_device, SC_PATH(sc)); 15694 } else { 15695 BLOGD(sc, DBG_LOAD, 15696 "Removing AER indication from path %d/%d/%d\n", 15697 sc->pcie_bus, sc->pcie_device, SC_PATH(sc)); 15698 tmp->aer = 0; 15699 } 15700 15701 mtx_unlock(&bxe_prev_mtx); 15702 return (0); 15703 } 15704 15705 mtx_unlock(&bxe_prev_mtx); 15706 15707 /* Create an entry for this path and add it */ 15708 tmp = malloc(sizeof(struct bxe_prev_list_node), M_DEVBUF, 15709 (M_NOWAIT | M_ZERO)); 15710 if (!tmp) { 15711 BLOGE(sc, "Failed to allocate 'bxe_prev_list_node'\n"); 15712 return (-1); 15713 } 15714 15715 tmp->bus = sc->pcie_bus; 15716 tmp->slot = sc->pcie_device; 15717 tmp->path = SC_PATH(sc); 15718 tmp->aer = 0; 15719 tmp->undi = after_undi ? (1 << SC_PORT(sc)) : 0; 15720 15721 mtx_lock(&bxe_prev_mtx); 15722 15723 BLOGD(sc, DBG_LOAD, 15724 "Marked path %d/%d/%d - finished previous unload\n", 15725 sc->pcie_bus, sc->pcie_device, SC_PATH(sc)); 15726 LIST_INSERT_HEAD(&bxe_prev_list, tmp, node); 15727 15728 mtx_unlock(&bxe_prev_mtx); 15729 15730 return (0); 15731 } 15732 15733 static int 15734 bxe_do_flr(struct bxe_softc *sc) 15735 { 15736 int i; 15737 15738 /* only E2 and onwards support FLR */ 15739 if (CHIP_IS_E1x(sc)) { 15740 BLOGD(sc, DBG_LOAD, "FLR not supported in E1/E1H\n"); 15741 return (-1); 15742 } 15743 15744 /* only bootcode REQ_BC_VER_4_INITIATE_FLR and onwards support flr */ 15745 if (sc->devinfo.bc_ver < REQ_BC_VER_4_INITIATE_FLR) { 15746 BLOGD(sc, DBG_LOAD, "FLR not supported by BC_VER: 0x%08x\n", 15747 sc->devinfo.bc_ver); 15748 return (-1); 15749 } 15750 15751 /* Wait for Transaction Pending bit clean */ 15752 for (i = 0; i < 4; i++) { 15753 if (i) { 15754 DELAY(((1 << (i - 1)) * 100) * 1000); 15755 } 15756 15757 if (!bxe_is_pcie_pending(sc)) { 15758 goto clear; 15759 } 15760 } 15761 15762 BLOGE(sc, "PCIE transaction is not cleared, " 15763 "proceeding with reset anyway\n"); 15764 15765 clear: 15766 15767 BLOGD(sc, DBG_LOAD, "Initiating FLR\n"); 15768 bxe_fw_command(sc, DRV_MSG_CODE_INITIATE_FLR, 0); 15769 15770 return (0); 15771 } 15772 15773 struct bxe_mac_vals { 15774 uint32_t xmac_addr; 15775 uint32_t xmac_val; 15776 uint32_t emac_addr; 15777 uint32_t emac_val; 15778 uint32_t umac_addr; 15779 uint32_t umac_val; 15780 uint32_t bmac_addr; 15781 uint32_t bmac_val[2]; 15782 }; 15783 15784 static void 15785 bxe_prev_unload_close_mac(struct bxe_softc *sc, 15786 struct bxe_mac_vals *vals) 15787 { 15788 uint32_t val, base_addr, offset, mask, reset_reg; 15789 uint8_t mac_stopped = FALSE; 15790 uint8_t port = SC_PORT(sc); 15791 uint32_t wb_data[2]; 15792 15793 /* reset addresses as they also mark which values were changed */ 15794 vals->bmac_addr = 0; 15795 vals->umac_addr = 0; 15796 vals->xmac_addr = 0; 15797 vals->emac_addr = 0; 15798 15799 reset_reg = REG_RD(sc, MISC_REG_RESET_REG_2); 15800 15801 if (!CHIP_IS_E3(sc)) { 15802 val = REG_RD(sc, NIG_REG_BMAC0_REGS_OUT_EN + port * 4); 15803 mask = MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port; 15804 if ((mask & reset_reg) && val) { 15805 BLOGD(sc, DBG_LOAD, "Disable BMAC Rx\n"); 15806 base_addr = SC_PORT(sc) ? NIG_REG_INGRESS_BMAC1_MEM 15807 : NIG_REG_INGRESS_BMAC0_MEM; 15808 offset = CHIP_IS_E2(sc) ? BIGMAC2_REGISTER_BMAC_CONTROL 15809 : BIGMAC_REGISTER_BMAC_CONTROL; 15810 15811 /* 15812 * use rd/wr since we cannot use dmae. This is safe 15813 * since MCP won't access the bus due to the request 15814 * to unload, and no function on the path can be 15815 * loaded at this time. 15816 */ 15817 wb_data[0] = REG_RD(sc, base_addr + offset); 15818 wb_data[1] = REG_RD(sc, base_addr + offset + 0x4); 15819 vals->bmac_addr = base_addr + offset; 15820 vals->bmac_val[0] = wb_data[0]; 15821 vals->bmac_val[1] = wb_data[1]; 15822 wb_data[0] &= ~ELINK_BMAC_CONTROL_RX_ENABLE; 15823 REG_WR(sc, vals->bmac_addr, wb_data[0]); 15824 REG_WR(sc, vals->bmac_addr + 0x4, wb_data[1]); 15825 } 15826 15827 BLOGD(sc, DBG_LOAD, "Disable EMAC Rx\n"); 15828 vals->emac_addr = NIG_REG_NIG_EMAC0_EN + SC_PORT(sc)*4; 15829 vals->emac_val = REG_RD(sc, vals->emac_addr); 15830 REG_WR(sc, vals->emac_addr, 0); 15831 mac_stopped = TRUE; 15832 } else { 15833 if (reset_reg & MISC_REGISTERS_RESET_REG_2_XMAC) { 15834 BLOGD(sc, DBG_LOAD, "Disable XMAC Rx\n"); 15835 base_addr = SC_PORT(sc) ? GRCBASE_XMAC1 : GRCBASE_XMAC0; 15836 val = REG_RD(sc, base_addr + XMAC_REG_PFC_CTRL_HI); 15837 REG_WR(sc, base_addr + XMAC_REG_PFC_CTRL_HI, val & ~(1 << 1)); 15838 REG_WR(sc, base_addr + XMAC_REG_PFC_CTRL_HI, val | (1 << 1)); 15839 vals->xmac_addr = base_addr + XMAC_REG_CTRL; 15840 vals->xmac_val = REG_RD(sc, vals->xmac_addr); 15841 REG_WR(sc, vals->xmac_addr, 0); 15842 mac_stopped = TRUE; 15843 } 15844 15845 mask = MISC_REGISTERS_RESET_REG_2_UMAC0 << port; 15846 if (mask & reset_reg) { 15847 BLOGD(sc, DBG_LOAD, "Disable UMAC Rx\n"); 15848 base_addr = SC_PORT(sc) ? GRCBASE_UMAC1 : GRCBASE_UMAC0; 15849 vals->umac_addr = base_addr + UMAC_REG_COMMAND_CONFIG; 15850 vals->umac_val = REG_RD(sc, vals->umac_addr); 15851 REG_WR(sc, vals->umac_addr, 0); 15852 mac_stopped = TRUE; 15853 } 15854 } 15855 15856 if (mac_stopped) { 15857 DELAY(20000); 15858 } 15859 } 15860 15861 #define BXE_PREV_UNDI_PROD_ADDR(p) (BAR_TSTRORM_INTMEM + 0x1508 + ((p) << 4)) 15862 #define BXE_PREV_UNDI_RCQ(val) ((val) & 0xffff) 15863 #define BXE_PREV_UNDI_BD(val) ((val) >> 16 & 0xffff) 15864 #define BXE_PREV_UNDI_PROD(rcq, bd) ((bd) << 16 | (rcq)) 15865 15866 static void 15867 bxe_prev_unload_undi_inc(struct bxe_softc *sc, 15868 uint8_t port, 15869 uint8_t inc) 15870 { 15871 uint16_t rcq, bd; 15872 uint32_t tmp_reg = REG_RD(sc, BXE_PREV_UNDI_PROD_ADDR(port)); 15873 15874 rcq = BXE_PREV_UNDI_RCQ(tmp_reg) + inc; 15875 bd = BXE_PREV_UNDI_BD(tmp_reg) + inc; 15876 15877 tmp_reg = BXE_PREV_UNDI_PROD(rcq, bd); 15878 REG_WR(sc, BXE_PREV_UNDI_PROD_ADDR(port), tmp_reg); 15879 15880 BLOGD(sc, DBG_LOAD, 15881 "UNDI producer [%d] rings bd -> 0x%04x, rcq -> 0x%04x\n", 15882 port, bd, rcq); 15883 } 15884 15885 static int 15886 bxe_prev_unload_common(struct bxe_softc *sc) 15887 { 15888 uint32_t reset_reg, tmp_reg = 0, rc; 15889 uint8_t prev_undi = FALSE; 15890 struct bxe_mac_vals mac_vals; 15891 uint32_t timer_count = 1000; 15892 uint32_t prev_brb; 15893 15894 /* 15895 * It is possible a previous function received 'common' answer, 15896 * but hasn't loaded yet, therefore creating a scenario of 15897 * multiple functions receiving 'common' on the same path. 15898 */ 15899 BLOGD(sc, DBG_LOAD, "Common unload Flow\n"); 15900 15901 memset(&mac_vals, 0, sizeof(mac_vals)); 15902 15903 if (bxe_prev_is_path_marked(sc)) { 15904 return (bxe_prev_mcp_done(sc)); 15905 } 15906 15907 reset_reg = REG_RD(sc, MISC_REG_RESET_REG_1); 15908 15909 /* Reset should be performed after BRB is emptied */ 15910 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_BRB1) { 15911 /* Close the MAC Rx to prevent BRB from filling up */ 15912 bxe_prev_unload_close_mac(sc, &mac_vals); 15913 15914 /* close LLH filters towards the BRB */ 15915 elink_set_rx_filter(&sc->link_params, 0); 15916 15917 /* 15918 * Check if the UNDI driver was previously loaded. 15919 * UNDI driver initializes CID offset for normal bell to 0x7 15920 */ 15921 if (reset_reg & MISC_REGISTERS_RESET_REG_1_RST_DORQ) { 15922 tmp_reg = REG_RD(sc, DORQ_REG_NORM_CID_OFST); 15923 if (tmp_reg == 0x7) { 15924 BLOGD(sc, DBG_LOAD, "UNDI previously loaded\n"); 15925 prev_undi = TRUE; 15926 /* clear the UNDI indication */ 15927 REG_WR(sc, DORQ_REG_NORM_CID_OFST, 0); 15928 /* clear possible idle check errors */ 15929 REG_RD(sc, NIG_REG_NIG_INT_STS_CLR_0); 15930 } 15931 } 15932 15933 /* wait until BRB is empty */ 15934 tmp_reg = REG_RD(sc, BRB1_REG_NUM_OF_FULL_BLOCKS); 15935 while (timer_count) { 15936 prev_brb = tmp_reg; 15937 15938 tmp_reg = REG_RD(sc, BRB1_REG_NUM_OF_FULL_BLOCKS); 15939 if (!tmp_reg) { 15940 break; 15941 } 15942 15943 BLOGD(sc, DBG_LOAD, "BRB still has 0x%08x\n", tmp_reg); 15944 15945 /* reset timer as long as BRB actually gets emptied */ 15946 if (prev_brb > tmp_reg) { 15947 timer_count = 1000; 15948 } else { 15949 timer_count--; 15950 } 15951 15952 /* If UNDI resides in memory, manually increment it */ 15953 if (prev_undi) { 15954 bxe_prev_unload_undi_inc(sc, SC_PORT(sc), 1); 15955 } 15956 15957 DELAY(10); 15958 } 15959 15960 if (!timer_count) { 15961 BLOGE(sc, "Failed to empty BRB\n"); 15962 } 15963 } 15964 15965 /* No packets are in the pipeline, path is ready for reset */ 15966 bxe_reset_common(sc); 15967 15968 if (mac_vals.xmac_addr) { 15969 REG_WR(sc, mac_vals.xmac_addr, mac_vals.xmac_val); 15970 } 15971 if (mac_vals.umac_addr) { 15972 REG_WR(sc, mac_vals.umac_addr, mac_vals.umac_val); 15973 } 15974 if (mac_vals.emac_addr) { 15975 REG_WR(sc, mac_vals.emac_addr, mac_vals.emac_val); 15976 } 15977 if (mac_vals.bmac_addr) { 15978 REG_WR(sc, mac_vals.bmac_addr, mac_vals.bmac_val[0]); 15979 REG_WR(sc, mac_vals.bmac_addr + 4, mac_vals.bmac_val[1]); 15980 } 15981 15982 rc = bxe_prev_mark_path(sc, prev_undi); 15983 if (rc) { 15984 bxe_prev_mcp_done(sc); 15985 return (rc); 15986 } 15987 15988 return (bxe_prev_mcp_done(sc)); 15989 } 15990 15991 static int 15992 bxe_prev_unload_uncommon(struct bxe_softc *sc) 15993 { 15994 int rc; 15995 15996 BLOGD(sc, DBG_LOAD, "Uncommon unload Flow\n"); 15997 15998 /* Test if previous unload process was already finished for this path */ 15999 if (bxe_prev_is_path_marked(sc)) { 16000 return (bxe_prev_mcp_done(sc)); 16001 } 16002 16003 BLOGD(sc, DBG_LOAD, "Path is unmarked\n"); 16004 16005 /* 16006 * If function has FLR capabilities, and existing FW version matches 16007 * the one required, then FLR will be sufficient to clean any residue 16008 * left by previous driver 16009 */ 16010 rc = bxe_nic_load_analyze_req(sc, FW_MSG_CODE_DRV_LOAD_FUNCTION); 16011 if (!rc) { 16012 /* fw version is good */ 16013 BLOGD(sc, DBG_LOAD, "FW version matches our own, attempting FLR\n"); 16014 rc = bxe_do_flr(sc); 16015 } 16016 16017 if (!rc) { 16018 /* FLR was performed */ 16019 BLOGD(sc, DBG_LOAD, "FLR successful\n"); 16020 return (0); 16021 } 16022 16023 BLOGD(sc, DBG_LOAD, "Could not FLR\n"); 16024 16025 /* Close the MCP request, return failure*/ 16026 rc = bxe_prev_mcp_done(sc); 16027 if (!rc) { 16028 rc = BXE_PREV_WAIT_NEEDED; 16029 } 16030 16031 return (rc); 16032 } 16033 16034 static int 16035 bxe_prev_unload(struct bxe_softc *sc) 16036 { 16037 int time_counter = 10; 16038 uint32_t fw, hw_lock_reg, hw_lock_val; 16039 uint32_t rc = 0; 16040 16041 /* 16042 * Clear HW from errors which may have resulted from an interrupted 16043 * DMAE transaction. 16044 */ 16045 bxe_prev_interrupted_dmae(sc); 16046 16047 /* Release previously held locks */ 16048 hw_lock_reg = 16049 (SC_FUNC(sc) <= 5) ? 16050 (MISC_REG_DRIVER_CONTROL_1 + SC_FUNC(sc) * 8) : 16051 (MISC_REG_DRIVER_CONTROL_7 + (SC_FUNC(sc) - 6) * 8); 16052 16053 hw_lock_val = (REG_RD(sc, hw_lock_reg)); 16054 if (hw_lock_val) { 16055 if (hw_lock_val & HW_LOCK_RESOURCE_NVRAM) { 16056 BLOGD(sc, DBG_LOAD, "Releasing previously held NVRAM lock\n"); 16057 REG_WR(sc, MCP_REG_MCPR_NVM_SW_ARB, 16058 (MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << SC_PORT(sc))); 16059 } 16060 BLOGD(sc, DBG_LOAD, "Releasing previously held HW lock\n"); 16061 REG_WR(sc, hw_lock_reg, 0xffffffff); 16062 } else { 16063 BLOGD(sc, DBG_LOAD, "No need to release HW/NVRAM locks\n"); 16064 } 16065 16066 if (MCPR_ACCESS_LOCK_LOCK & REG_RD(sc, MCP_REG_MCPR_ACCESS_LOCK)) { 16067 BLOGD(sc, DBG_LOAD, "Releasing previously held ALR\n"); 16068 REG_WR(sc, MCP_REG_MCPR_ACCESS_LOCK, 0); 16069 } 16070 16071 do { 16072 /* Lock MCP using an unload request */ 16073 fw = bxe_fw_command(sc, DRV_MSG_CODE_UNLOAD_REQ_WOL_DIS, 0); 16074 if (!fw) { 16075 BLOGE(sc, "MCP response failure, aborting\n"); 16076 rc = -1; 16077 break; 16078 } 16079 16080 if (fw == FW_MSG_CODE_DRV_UNLOAD_COMMON) { 16081 rc = bxe_prev_unload_common(sc); 16082 break; 16083 } 16084 16085 /* non-common reply from MCP night require looping */ 16086 rc = bxe_prev_unload_uncommon(sc); 16087 if (rc != BXE_PREV_WAIT_NEEDED) { 16088 break; 16089 } 16090 16091 DELAY(20000); 16092 } while (--time_counter); 16093 16094 if (!time_counter || rc) { 16095 BLOGE(sc, "Failed to unload previous driver!\n"); 16096 rc = -1; 16097 } 16098 16099 return (rc); 16100 } 16101 16102 void 16103 bxe_dcbx_set_state(struct bxe_softc *sc, 16104 uint8_t dcb_on, 16105 uint32_t dcbx_enabled) 16106 { 16107 if (!CHIP_IS_E1x(sc)) { 16108 sc->dcb_state = dcb_on; 16109 sc->dcbx_enabled = dcbx_enabled; 16110 } else { 16111 sc->dcb_state = FALSE; 16112 sc->dcbx_enabled = BXE_DCBX_ENABLED_INVALID; 16113 } 16114 BLOGD(sc, DBG_LOAD, 16115 "DCB state [%s:%s]\n", 16116 dcb_on ? "ON" : "OFF", 16117 (dcbx_enabled == BXE_DCBX_ENABLED_OFF) ? "user-mode" : 16118 (dcbx_enabled == BXE_DCBX_ENABLED_ON_NEG_OFF) ? "on-chip static" : 16119 (dcbx_enabled == BXE_DCBX_ENABLED_ON_NEG_ON) ? 16120 "on-chip with negotiation" : "invalid"); 16121 } 16122 16123 /* must be called after sriov-enable */ 16124 static int 16125 bxe_set_qm_cid_count(struct bxe_softc *sc) 16126 { 16127 int cid_count = BXE_L2_MAX_CID(sc); 16128 16129 if (IS_SRIOV(sc)) { 16130 cid_count += BXE_VF_CIDS; 16131 } 16132 16133 if (CNIC_SUPPORT(sc)) { 16134 cid_count += CNIC_CID_MAX; 16135 } 16136 16137 return (roundup(cid_count, QM_CID_ROUND)); 16138 } 16139 16140 static void 16141 bxe_init_multi_cos(struct bxe_softc *sc) 16142 { 16143 int pri, cos; 16144 16145 uint32_t pri_map = 0; /* XXX change to user config */ 16146 16147 for (pri = 0; pri < BXE_MAX_PRIORITY; pri++) { 16148 cos = ((pri_map & (0xf << (pri * 4))) >> (pri * 4)); 16149 if (cos < sc->max_cos) { 16150 sc->prio_to_cos[pri] = cos; 16151 } else { 16152 BLOGW(sc, "Invalid COS %d for priority %d " 16153 "(max COS is %d), setting to 0\n", 16154 cos, pri, (sc->max_cos - 1)); 16155 sc->prio_to_cos[pri] = 0; 16156 } 16157 } 16158 } 16159 16160 static int 16161 bxe_sysctl_state(SYSCTL_HANDLER_ARGS) 16162 { 16163 struct bxe_softc *sc; 16164 int error, result; 16165 16166 result = 0; 16167 error = sysctl_handle_int(oidp, &result, 0, req); 16168 16169 if (error || !req->newptr) { 16170 return (error); 16171 } 16172 16173 if (result == 1) { 16174 sc = (struct bxe_softc *)arg1; 16175 BLOGI(sc, "... dumping driver state ...\n"); 16176 /* XXX */ 16177 } 16178 16179 return (error); 16180 } 16181 16182 static int 16183 bxe_sysctl_eth_stat(SYSCTL_HANDLER_ARGS) 16184 { 16185 struct bxe_softc *sc = (struct bxe_softc *)arg1; 16186 uint32_t *eth_stats = (uint32_t *)&sc->eth_stats; 16187 uint32_t *offset; 16188 uint64_t value = 0; 16189 int index = (int)arg2; 16190 16191 if (index >= BXE_NUM_ETH_STATS) { 16192 BLOGE(sc, "bxe_eth_stats index out of range (%d)\n", index); 16193 return (-1); 16194 } 16195 16196 offset = (eth_stats + bxe_eth_stats_arr[index].offset); 16197 16198 switch (bxe_eth_stats_arr[index].size) { 16199 case 4: 16200 value = (uint64_t)*offset; 16201 break; 16202 case 8: 16203 value = HILO_U64(*offset, *(offset + 1)); 16204 break; 16205 default: 16206 BLOGE(sc, "Invalid bxe_eth_stats size (index=%d size=%d)\n", 16207 index, bxe_eth_stats_arr[index].size); 16208 return (-1); 16209 } 16210 16211 return (sysctl_handle_64(oidp, &value, 0, req)); 16212 } 16213 16214 static int 16215 bxe_sysctl_eth_q_stat(SYSCTL_HANDLER_ARGS) 16216 { 16217 struct bxe_softc *sc = (struct bxe_softc *)arg1; 16218 uint32_t *eth_stats; 16219 uint32_t *offset; 16220 uint64_t value = 0; 16221 uint32_t q_stat = (uint32_t)arg2; 16222 uint32_t fp_index = ((q_stat >> 16) & 0xffff); 16223 uint32_t index = (q_stat & 0xffff); 16224 16225 eth_stats = (uint32_t *)&sc->fp[fp_index].eth_q_stats; 16226 16227 if (index >= BXE_NUM_ETH_Q_STATS) { 16228 BLOGE(sc, "bxe_eth_q_stats index out of range (%d)\n", index); 16229 return (-1); 16230 } 16231 16232 offset = (eth_stats + bxe_eth_q_stats_arr[index].offset); 16233 16234 switch (bxe_eth_q_stats_arr[index].size) { 16235 case 4: 16236 value = (uint64_t)*offset; 16237 break; 16238 case 8: 16239 value = HILO_U64(*offset, *(offset + 1)); 16240 break; 16241 default: 16242 BLOGE(sc, "Invalid bxe_eth_q_stats size (index=%d size=%d)\n", 16243 index, bxe_eth_q_stats_arr[index].size); 16244 return (-1); 16245 } 16246 16247 return (sysctl_handle_64(oidp, &value, 0, req)); 16248 } 16249 16250 static void 16251 bxe_add_sysctls(struct bxe_softc *sc) 16252 { 16253 struct sysctl_ctx_list *ctx; 16254 struct sysctl_oid_list *children; 16255 struct sysctl_oid *queue_top, *queue; 16256 struct sysctl_oid_list *queue_top_children, *queue_children; 16257 char queue_num_buf[32]; 16258 uint32_t q_stat; 16259 int i, j; 16260 16261 ctx = device_get_sysctl_ctx(sc->dev); 16262 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)); 16263 16264 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "version", 16265 CTLFLAG_RD, BXE_DRIVER_VERSION, 0, 16266 "version"); 16267 16268 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "bc_version", 16269 CTLFLAG_RD, &sc->devinfo.bc_ver_str, 0, 16270 "bootcode version"); 16271 16272 snprintf(sc->fw_ver_str, sizeof(sc->fw_ver_str), "%d.%d.%d.%d", 16273 BCM_5710_FW_MAJOR_VERSION, 16274 BCM_5710_FW_MINOR_VERSION, 16275 BCM_5710_FW_REVISION_VERSION, 16276 BCM_5710_FW_ENGINEERING_VERSION); 16277 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "fw_version", 16278 CTLFLAG_RD, &sc->fw_ver_str, 0, 16279 "firmware version"); 16280 16281 snprintf(sc->mf_mode_str, sizeof(sc->mf_mode_str), "%s", 16282 ((sc->devinfo.mf_info.mf_mode == SINGLE_FUNCTION) ? "Single" : 16283 (sc->devinfo.mf_info.mf_mode == MULTI_FUNCTION_SD) ? "MF-SD" : 16284 (sc->devinfo.mf_info.mf_mode == MULTI_FUNCTION_SI) ? "MF-SI" : 16285 (sc->devinfo.mf_info.mf_mode == MULTI_FUNCTION_AFEX) ? "MF-AFEX" : 16286 "Unknown")); 16287 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "mf_mode", 16288 CTLFLAG_RD, &sc->mf_mode_str, 0, 16289 "multifunction mode"); 16290 16291 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "mf_vnics", 16292 CTLFLAG_RD, &sc->devinfo.mf_info.vnics_per_port, 0, 16293 "multifunction vnics per port"); 16294 16295 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "mac_addr", 16296 CTLFLAG_RD, &sc->mac_addr_str, 0, 16297 "mac address"); 16298 16299 snprintf(sc->pci_link_str, sizeof(sc->pci_link_str), "%s x%d", 16300 ((sc->devinfo.pcie_link_speed == 1) ? "2.5GT/s" : 16301 (sc->devinfo.pcie_link_speed == 2) ? "5.0GT/s" : 16302 (sc->devinfo.pcie_link_speed == 4) ? "8.0GT/s" : 16303 "???GT/s"), 16304 sc->devinfo.pcie_link_width); 16305 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "pci_link", 16306 CTLFLAG_RD, &sc->pci_link_str, 0, 16307 "pci link status"); 16308 16309 sc->debug = bxe_debug; 16310 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "debug", 16311 CTLFLAG_RW, &sc->debug, 0, 16312 "debug logging mode"); 16313 16314 sc->rx_budget = bxe_rx_budget; 16315 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rx_budget", 16316 CTLFLAG_RW, &sc->rx_budget, 0, 16317 "rx processing budget"); 16318 16319 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "state", 16320 CTLTYPE_UINT | CTLFLAG_RW, sc, 0, 16321 bxe_sysctl_state, "IU", "dump driver state"); 16322 16323 for (i = 0; i < BXE_NUM_ETH_STATS; i++) { 16324 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, 16325 bxe_eth_stats_arr[i].string, 16326 CTLTYPE_U64 | CTLFLAG_RD, sc, i, 16327 bxe_sysctl_eth_stat, "LU", 16328 bxe_eth_stats_arr[i].string); 16329 } 16330 16331 /* add a new parent node for all queues "dev.bxe.#.queue" */ 16332 queue_top = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "queue", 16333 CTLFLAG_RD, NULL, "queue"); 16334 queue_top_children = SYSCTL_CHILDREN(queue_top); 16335 16336 for (i = 0; i < sc->num_queues; i++) { 16337 /* add a new parent node for a single queue "dev.bxe.#.queue.#" */ 16338 snprintf(queue_num_buf, sizeof(queue_num_buf), "%d", i); 16339 queue = SYSCTL_ADD_NODE(ctx, queue_top_children, OID_AUTO, 16340 queue_num_buf, CTLFLAG_RD, NULL, 16341 "single queue"); 16342 queue_children = SYSCTL_CHILDREN(queue); 16343 16344 for (j = 0; j < BXE_NUM_ETH_Q_STATS; j++) { 16345 q_stat = ((i << 16) | j); 16346 SYSCTL_ADD_PROC(ctx, queue_children, OID_AUTO, 16347 bxe_eth_q_stats_arr[j].string, 16348 CTLTYPE_U64 | CTLFLAG_RD, sc, q_stat, 16349 bxe_sysctl_eth_q_stat, "LU", 16350 bxe_eth_q_stats_arr[j].string); 16351 } 16352 } 16353 } 16354 16355 /* 16356 * Device attach function. 16357 * 16358 * Allocates device resources, performs secondary chip identification, and 16359 * initializes driver instance variables. This function is called from driver 16360 * load after a successful probe. 16361 * 16362 * Returns: 16363 * 0 = Success, >0 = Failure 16364 */ 16365 static int 16366 bxe_attach(device_t dev) 16367 { 16368 struct bxe_softc *sc; 16369 16370 sc = device_get_softc(dev); 16371 16372 BLOGD(sc, DBG_LOAD, "Starting attach...\n"); 16373 16374 sc->state = BXE_STATE_CLOSED; 16375 16376 sc->dev = dev; 16377 sc->unit = device_get_unit(dev); 16378 16379 BLOGD(sc, DBG_LOAD, "softc = %p\n", sc); 16380 16381 sc->pcie_bus = pci_get_bus(dev); 16382 sc->pcie_device = pci_get_slot(dev); 16383 sc->pcie_func = pci_get_function(dev); 16384 16385 /* enable bus master capability */ 16386 pci_enable_busmaster(dev); 16387 16388 /* get the BARs */ 16389 if (bxe_allocate_bars(sc) != 0) { 16390 return (ENXIO); 16391 } 16392 16393 /* initialize the mutexes */ 16394 bxe_init_mutexes(sc); 16395 16396 /* prepare the periodic callout */ 16397 callout_init(&sc->periodic_callout, 0); 16398 16399 /* prepare the chip taskqueue */ 16400 sc->chip_tq_flags = CHIP_TQ_NONE; 16401 snprintf(sc->chip_tq_name, sizeof(sc->chip_tq_name), 16402 "bxe%d_chip_tq", sc->unit); 16403 TASK_INIT(&sc->chip_tq_task, 0, bxe_handle_chip_tq, sc); 16404 sc->chip_tq = taskqueue_create(sc->chip_tq_name, M_NOWAIT, 16405 taskqueue_thread_enqueue, 16406 &sc->chip_tq); 16407 taskqueue_start_threads(&sc->chip_tq, 1, PWAIT, /* lower priority */ 16408 "%s", sc->chip_tq_name); 16409 16410 /* get device info and set params */ 16411 if (bxe_get_device_info(sc) != 0) { 16412 BLOGE(sc, "getting device info\n"); 16413 bxe_deallocate_bars(sc); 16414 pci_disable_busmaster(dev); 16415 return (ENXIO); 16416 } 16417 16418 /* get final misc params */ 16419 bxe_get_params(sc); 16420 16421 /* set the default MTU (changed via ifconfig) */ 16422 sc->mtu = ETHERMTU; 16423 16424 bxe_set_modes_bitmap(sc); 16425 16426 /* XXX 16427 * If in AFEX mode and the function is configured for FCoE 16428 * then bail... no L2 allowed. 16429 */ 16430 16431 /* get phy settings from shmem and 'and' against admin settings */ 16432 bxe_get_phy_info(sc); 16433 16434 /* initialize the FreeBSD ifnet interface */ 16435 if (bxe_init_ifnet(sc) != 0) { 16436 bxe_release_mutexes(sc); 16437 bxe_deallocate_bars(sc); 16438 pci_disable_busmaster(dev); 16439 return (ENXIO); 16440 } 16441 16442 /* allocate device interrupts */ 16443 if (bxe_interrupt_alloc(sc) != 0) { 16444 if (sc->ifnet != NULL) { 16445 ether_ifdetach(sc->ifnet); 16446 } 16447 ifmedia_removeall(&sc->ifmedia); 16448 bxe_release_mutexes(sc); 16449 bxe_deallocate_bars(sc); 16450 pci_disable_busmaster(dev); 16451 return (ENXIO); 16452 } 16453 16454 /* allocate ilt */ 16455 if (bxe_alloc_ilt_mem(sc) != 0) { 16456 bxe_interrupt_free(sc); 16457 if (sc->ifnet != NULL) { 16458 ether_ifdetach(sc->ifnet); 16459 } 16460 ifmedia_removeall(&sc->ifmedia); 16461 bxe_release_mutexes(sc); 16462 bxe_deallocate_bars(sc); 16463 pci_disable_busmaster(dev); 16464 return (ENXIO); 16465 } 16466 16467 /* allocate the host hardware/software hsi structures */ 16468 if (bxe_alloc_hsi_mem(sc) != 0) { 16469 bxe_free_ilt_mem(sc); 16470 bxe_interrupt_free(sc); 16471 if (sc->ifnet != NULL) { 16472 ether_ifdetach(sc->ifnet); 16473 } 16474 ifmedia_removeall(&sc->ifmedia); 16475 bxe_release_mutexes(sc); 16476 bxe_deallocate_bars(sc); 16477 pci_disable_busmaster(dev); 16478 return (ENXIO); 16479 } 16480 16481 /* need to reset chip if UNDI was active */ 16482 if (IS_PF(sc) && !BXE_NOMCP(sc)) { 16483 /* init fw_seq */ 16484 sc->fw_seq = 16485 (SHMEM_RD(sc, func_mb[SC_FW_MB_IDX(sc)].drv_mb_header) & 16486 DRV_MSG_SEQ_NUMBER_MASK); 16487 BLOGD(sc, DBG_LOAD, "prev unload fw_seq 0x%04x\n", sc->fw_seq); 16488 bxe_prev_unload(sc); 16489 } 16490 16491 #if 1 16492 /* XXX */ 16493 bxe_dcbx_set_state(sc, FALSE, BXE_DCBX_ENABLED_OFF); 16494 #else 16495 if (SHMEM2_HAS(sc, dcbx_lldp_params_offset) && 16496 SHMEM2_HAS(sc, dcbx_lldp_dcbx_stat_offset) && 16497 SHMEM2_RD(sc, dcbx_lldp_params_offset) && 16498 SHMEM2_RD(sc, dcbx_lldp_dcbx_stat_offset)) { 16499 bxe_dcbx_set_state(sc, TRUE, BXE_DCBX_ENABLED_ON_NEG_ON); 16500 bxe_dcbx_init_params(sc); 16501 } else { 16502 bxe_dcbx_set_state(sc, FALSE, BXE_DCBX_ENABLED_OFF); 16503 } 16504 #endif 16505 16506 /* calculate qm_cid_count */ 16507 sc->qm_cid_count = bxe_set_qm_cid_count(sc); 16508 BLOGD(sc, DBG_LOAD, "qm_cid_count=%d\n", sc->qm_cid_count); 16509 16510 sc->max_cos = 1; 16511 bxe_init_multi_cos(sc); 16512 16513 bxe_add_sysctls(sc); 16514 16515 return (0); 16516 } 16517 16518 /* 16519 * Device detach function. 16520 * 16521 * Stops the controller, resets the controller, and releases resources. 16522 * 16523 * Returns: 16524 * 0 = Success, >0 = Failure 16525 */ 16526 static int 16527 bxe_detach(device_t dev) 16528 { 16529 struct bxe_softc *sc; 16530 struct ifnet *ifp; 16531 16532 sc = device_get_softc(dev); 16533 16534 BLOGD(sc, DBG_LOAD, "Starting detach...\n"); 16535 16536 ifp = sc->ifnet; 16537 if (ifp != NULL && ifp->if_vlantrunk != NULL) { 16538 BLOGE(sc, "Cannot detach while VLANs are in use.\n"); 16539 return(EBUSY); 16540 } 16541 16542 /* stop the periodic callout */ 16543 bxe_periodic_stop(sc); 16544 16545 /* stop the chip taskqueue */ 16546 atomic_store_rel_long(&sc->chip_tq_flags, CHIP_TQ_NONE); 16547 if (sc->chip_tq) { 16548 taskqueue_drain(sc->chip_tq, &sc->chip_tq_task); 16549 taskqueue_free(sc->chip_tq); 16550 sc->chip_tq = NULL; 16551 } 16552 16553 /* stop and reset the controller if it was open */ 16554 if (sc->state != BXE_STATE_CLOSED) { 16555 BXE_CORE_LOCK(sc); 16556 bxe_nic_unload(sc, UNLOAD_CLOSE, TRUE); 16557 BXE_CORE_UNLOCK(sc); 16558 } 16559 16560 /* release the network interface */ 16561 if (ifp != NULL) { 16562 ether_ifdetach(ifp); 16563 } 16564 ifmedia_removeall(&sc->ifmedia); 16565 16566 /* XXX do the following based on driver state... */ 16567 16568 /* free the host hardware/software hsi structures */ 16569 bxe_free_hsi_mem(sc); 16570 16571 /* free ilt */ 16572 bxe_free_ilt_mem(sc); 16573 16574 /* release the interrupts */ 16575 bxe_interrupt_free(sc); 16576 16577 /* Release the mutexes*/ 16578 bxe_release_mutexes(sc); 16579 16580 /* Release the PCIe BAR mapped memory */ 16581 bxe_deallocate_bars(sc); 16582 16583 /* Release the FreeBSD interface. */ 16584 if (sc->ifnet != NULL) { 16585 if_free(sc->ifnet); 16586 } 16587 16588 pci_disable_busmaster(dev); 16589 16590 return (0); 16591 } 16592 16593 /* 16594 * Device shutdown function. 16595 * 16596 * Stops and resets the controller. 16597 * 16598 * Returns: 16599 * Nothing 16600 */ 16601 static int 16602 bxe_shutdown(device_t dev) 16603 { 16604 struct bxe_softc *sc; 16605 16606 sc = device_get_softc(dev); 16607 16608 BLOGD(sc, DBG_LOAD, "Starting shutdown...\n"); 16609 16610 /* stop the periodic callout */ 16611 bxe_periodic_stop(sc); 16612 16613 BXE_CORE_LOCK(sc); 16614 bxe_nic_unload(sc, UNLOAD_NORMAL, FALSE); 16615 BXE_CORE_UNLOCK(sc); 16616 16617 return (0); 16618 } 16619 16620 void 16621 bxe_igu_ack_sb(struct bxe_softc *sc, 16622 uint8_t igu_sb_id, 16623 uint8_t segment, 16624 uint16_t index, 16625 uint8_t op, 16626 uint8_t update) 16627 { 16628 uint32_t igu_addr = sc->igu_base_addr; 16629 igu_addr += (IGU_CMD_INT_ACK_BASE + igu_sb_id)*8; 16630 bxe_igu_ack_sb_gen(sc, igu_sb_id, segment, index, op, update, igu_addr); 16631 } 16632 16633 static void 16634 bxe_igu_clear_sb_gen(struct bxe_softc *sc, 16635 uint8_t func, 16636 uint8_t idu_sb_id, 16637 uint8_t is_pf) 16638 { 16639 uint32_t data, ctl, cnt = 100; 16640 uint32_t igu_addr_data = IGU_REG_COMMAND_REG_32LSB_DATA; 16641 uint32_t igu_addr_ctl = IGU_REG_COMMAND_REG_CTRL; 16642 uint32_t igu_addr_ack = IGU_REG_CSTORM_TYPE_0_SB_CLEANUP + (idu_sb_id/32)*4; 16643 uint32_t sb_bit = 1 << (idu_sb_id%32); 16644 uint32_t func_encode = func | (is_pf ? 1 : 0) << IGU_FID_ENCODE_IS_PF_SHIFT; 16645 uint32_t addr_encode = IGU_CMD_E2_PROD_UPD_BASE + idu_sb_id; 16646 16647 /* Not supported in BC mode */ 16648 if (CHIP_INT_MODE_IS_BC(sc)) { 16649 return; 16650 } 16651 16652 data = ((IGU_USE_REGISTER_cstorm_type_0_sb_cleanup << 16653 IGU_REGULAR_CLEANUP_TYPE_SHIFT) | 16654 IGU_REGULAR_CLEANUP_SET | 16655 IGU_REGULAR_BCLEANUP); 16656 16657 ctl = ((addr_encode << IGU_CTRL_REG_ADDRESS_SHIFT) | 16658 (func_encode << IGU_CTRL_REG_FID_SHIFT) | 16659 (IGU_CTRL_CMD_TYPE_WR << IGU_CTRL_REG_TYPE_SHIFT)); 16660 16661 BLOGD(sc, DBG_LOAD, "write 0x%08x to IGU(via GRC) addr 0x%x\n", 16662 data, igu_addr_data); 16663 REG_WR(sc, igu_addr_data, data); 16664 16665 bus_space_barrier(sc->bar[BAR0].tag, sc->bar[BAR0].handle, 0, 0, 16666 BUS_SPACE_BARRIER_WRITE); 16667 mb(); 16668 16669 BLOGD(sc, DBG_LOAD, "write 0x%08x to IGU(via GRC) addr 0x%x\n", 16670 ctl, igu_addr_ctl); 16671 REG_WR(sc, igu_addr_ctl, ctl); 16672 16673 bus_space_barrier(sc->bar[BAR0].tag, sc->bar[BAR0].handle, 0, 0, 16674 BUS_SPACE_BARRIER_WRITE); 16675 mb(); 16676 16677 /* wait for clean up to finish */ 16678 while (!(REG_RD(sc, igu_addr_ack) & sb_bit) && --cnt) { 16679 DELAY(20000); 16680 } 16681 16682 if (!(REG_RD(sc, igu_addr_ack) & sb_bit)) { 16683 BLOGD(sc, DBG_LOAD, 16684 "Unable to finish IGU cleanup: " 16685 "idu_sb_id %d offset %d bit %d (cnt %d)\n", 16686 idu_sb_id, idu_sb_id/32, idu_sb_id%32, cnt); 16687 } 16688 } 16689 16690 static void 16691 bxe_igu_clear_sb(struct bxe_softc *sc, 16692 uint8_t idu_sb_id) 16693 { 16694 bxe_igu_clear_sb_gen(sc, SC_FUNC(sc), idu_sb_id, TRUE /*PF*/); 16695 } 16696 16697 16698 16699 16700 16701 16702 16703 /*******************/ 16704 /* ECORE CALLBACKS */ 16705 /*******************/ 16706 16707 static void 16708 bxe_reset_common(struct bxe_softc *sc) 16709 { 16710 uint32_t val = 0x1400; 16711 16712 /* reset_common */ 16713 REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR), 0xd3ffff7f); 16714 16715 if (CHIP_IS_E3(sc)) { 16716 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0; 16717 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1; 16718 } 16719 16720 REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR), val); 16721 } 16722 16723 static void 16724 bxe_common_init_phy(struct bxe_softc *sc) 16725 { 16726 uint32_t shmem_base[2]; 16727 uint32_t shmem2_base[2]; 16728 16729 /* Avoid common init in case MFW supports LFA */ 16730 if (SHMEM2_RD(sc, size) > 16731 (uint32_t)offsetof(struct shmem2_region, 16732 lfa_host_addr[SC_PORT(sc)])) { 16733 return; 16734 } 16735 16736 shmem_base[0] = sc->devinfo.shmem_base; 16737 shmem2_base[0] = sc->devinfo.shmem2_base; 16738 16739 if (!CHIP_IS_E1x(sc)) { 16740 shmem_base[1] = SHMEM2_RD(sc, other_shmem_base_addr); 16741 shmem2_base[1] = SHMEM2_RD(sc, other_shmem2_base_addr); 16742 } 16743 16744 BXE_PHY_LOCK(sc); 16745 elink_common_init_phy(sc, shmem_base, shmem2_base, 16746 sc->devinfo.chip_id, 0); 16747 BXE_PHY_UNLOCK(sc); 16748 } 16749 16750 static void 16751 bxe_pf_disable(struct bxe_softc *sc) 16752 { 16753 uint32_t val = REG_RD(sc, IGU_REG_PF_CONFIGURATION); 16754 16755 val &= ~IGU_PF_CONF_FUNC_EN; 16756 16757 REG_WR(sc, IGU_REG_PF_CONFIGURATION, val); 16758 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0); 16759 REG_WR(sc, CFC_REG_WEAK_ENABLE_PF, 0); 16760 } 16761 16762 static void 16763 bxe_init_pxp(struct bxe_softc *sc) 16764 { 16765 uint16_t devctl; 16766 int r_order, w_order; 16767 16768 devctl = bxe_pcie_capability_read(sc, PCIR_EXPRESS_DEVICE_CTL, 2); 16769 16770 BLOGD(sc, DBG_LOAD, "read 0x%08x from devctl\n", devctl); 16771 16772 w_order = ((devctl & PCIM_EXP_CTL_MAX_PAYLOAD) >> 5); 16773 16774 if (sc->mrrs == -1) { 16775 r_order = ((devctl & PCIM_EXP_CTL_MAX_READ_REQUEST) >> 12); 16776 } else { 16777 BLOGD(sc, DBG_LOAD, "forcing read order to %d\n", sc->mrrs); 16778 r_order = sc->mrrs; 16779 } 16780 16781 ecore_init_pxp_arb(sc, r_order, w_order); 16782 } 16783 16784 static uint32_t 16785 bxe_get_pretend_reg(struct bxe_softc *sc) 16786 { 16787 uint32_t base = PXP2_REG_PGL_PRETEND_FUNC_F0; 16788 uint32_t stride = (PXP2_REG_PGL_PRETEND_FUNC_F1 - base); 16789 return (base + (SC_ABS_FUNC(sc)) * stride); 16790 } 16791 16792 /* 16793 * Called only on E1H or E2. 16794 * When pretending to be PF, the pretend value is the function number 0..7. 16795 * When pretending to be VF, the pretend val is the PF-num:VF-valid:ABS-VFID 16796 * combination. 16797 */ 16798 static int 16799 bxe_pretend_func(struct bxe_softc *sc, 16800 uint16_t pretend_func_val) 16801 { 16802 uint32_t pretend_reg; 16803 16804 if (CHIP_IS_E1H(sc) && (pretend_func_val > E1H_FUNC_MAX)) { 16805 return (-1); 16806 } 16807 16808 /* get my own pretend register */ 16809 pretend_reg = bxe_get_pretend_reg(sc); 16810 REG_WR(sc, pretend_reg, pretend_func_val); 16811 REG_RD(sc, pretend_reg); 16812 return (0); 16813 } 16814 16815 static void 16816 bxe_iov_init_dmae(struct bxe_softc *sc) 16817 { 16818 return; 16819 #if 0 16820 BLOGD(sc, DBG_LOAD, "SRIOV is %s\n", IS_SRIOV(sc) ? "ON" : "OFF"); 16821 16822 if (!IS_SRIOV(sc)) { 16823 return; 16824 } 16825 16826 REG_WR(sc, DMAE_REG_BACKWARD_COMP_EN, 0); 16827 #endif 16828 } 16829 16830 #if 0 16831 static int 16832 bxe_iov_init_ilt(struct bxe_softc *sc, 16833 uint16_t line) 16834 { 16835 return (line); 16836 #if 0 16837 int i; 16838 struct ecore_ilt* ilt = sc->ilt; 16839 16840 if (!IS_SRIOV(sc)) { 16841 return (line); 16842 } 16843 16844 /* set vfs ilt lines */ 16845 for (i = 0; i < BXE_VF_CIDS/ILT_PAGE_CIDS ; i++) { 16846 struct hw_dma *hw_cxt = SC_VF_CXT_PAGE(sc,i); 16847 ilt->lines[line+i].page = hw_cxt->addr; 16848 ilt->lines[line+i].page_mapping = hw_cxt->mapping; 16849 ilt->lines[line+i].size = hw_cxt->size; /* doesn't matter */ 16850 } 16851 return (line+i); 16852 #endif 16853 } 16854 #endif 16855 16856 static void 16857 bxe_iov_init_dq(struct bxe_softc *sc) 16858 { 16859 return; 16860 #if 0 16861 if (!IS_SRIOV(sc)) { 16862 return; 16863 } 16864 16865 /* Set the DQ such that the CID reflect the abs_vfid */ 16866 REG_WR(sc, DORQ_REG_VF_NORM_VF_BASE, 0); 16867 REG_WR(sc, DORQ_REG_MAX_RVFID_SIZE, ilog2(BNX2X_MAX_NUM_OF_VFS)); 16868 16869 /* 16870 * Set VFs starting CID. If its > 0 the preceding CIDs are belong to 16871 * the PF L2 queues 16872 */ 16873 REG_WR(sc, DORQ_REG_VF_NORM_CID_BASE, BNX2X_FIRST_VF_CID); 16874 16875 /* The VF window size is the log2 of the max number of CIDs per VF */ 16876 REG_WR(sc, DORQ_REG_VF_NORM_CID_WND_SIZE, BNX2X_VF_CID_WND); 16877 16878 /* 16879 * The VF doorbell size 0 - *B, 4 - 128B. We set it here to match 16880 * the Pf doorbell size although the 2 are independent. 16881 */ 16882 REG_WR(sc, DORQ_REG_VF_NORM_CID_OFST, 16883 BNX2X_DB_SHIFT - BNX2X_DB_MIN_SHIFT); 16884 16885 /* 16886 * No security checks for now - 16887 * configure single rule (out of 16) mask = 0x1, value = 0x0, 16888 * CID range 0 - 0x1ffff 16889 */ 16890 REG_WR(sc, DORQ_REG_VF_TYPE_MASK_0, 1); 16891 REG_WR(sc, DORQ_REG_VF_TYPE_VALUE_0, 0); 16892 REG_WR(sc, DORQ_REG_VF_TYPE_MIN_MCID_0, 0); 16893 REG_WR(sc, DORQ_REG_VF_TYPE_MAX_MCID_0, 0x1ffff); 16894 16895 /* set the number of VF alllowed doorbells to the full DQ range */ 16896 REG_WR(sc, DORQ_REG_VF_NORM_MAX_CID_COUNT, 0x20000); 16897 16898 /* set the VF doorbell threshold */ 16899 REG_WR(sc, DORQ_REG_VF_USAGE_CT_LIMIT, 4); 16900 #endif 16901 } 16902 16903 /* send a NIG loopback debug packet */ 16904 static void 16905 bxe_lb_pckt(struct bxe_softc *sc) 16906 { 16907 uint32_t wb_write[3]; 16908 16909 /* Ethernet source and destination addresses */ 16910 wb_write[0] = 0x55555555; 16911 wb_write[1] = 0x55555555; 16912 wb_write[2] = 0x20; /* SOP */ 16913 REG_WR_DMAE(sc, NIG_REG_DEBUG_PACKET_LB, wb_write, 3); 16914 16915 /* NON-IP protocol */ 16916 wb_write[0] = 0x09000000; 16917 wb_write[1] = 0x55555555; 16918 wb_write[2] = 0x10; /* EOP, eop_bvalid = 0 */ 16919 REG_WR_DMAE(sc, NIG_REG_DEBUG_PACKET_LB, wb_write, 3); 16920 } 16921 16922 /* 16923 * Some of the internal memories are not directly readable from the driver. 16924 * To test them we send debug packets. 16925 */ 16926 static int 16927 bxe_int_mem_test(struct bxe_softc *sc) 16928 { 16929 int factor; 16930 int count, i; 16931 uint32_t val = 0; 16932 16933 if (CHIP_REV_IS_FPGA(sc)) { 16934 factor = 120; 16935 } else if (CHIP_REV_IS_EMUL(sc)) { 16936 factor = 200; 16937 } else { 16938 factor = 1; 16939 } 16940 16941 /* disable inputs of parser neighbor blocks */ 16942 REG_WR(sc, TSDM_REG_ENABLE_IN1, 0x0); 16943 REG_WR(sc, TCM_REG_PRS_IFEN, 0x0); 16944 REG_WR(sc, CFC_REG_DEBUG0, 0x1); 16945 REG_WR(sc, NIG_REG_PRS_REQ_IN_EN, 0x0); 16946 16947 /* write 0 to parser credits for CFC search request */ 16948 REG_WR(sc, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0); 16949 16950 /* send Ethernet packet */ 16951 bxe_lb_pckt(sc); 16952 16953 /* TODO do i reset NIG statistic? */ 16954 /* Wait until NIG register shows 1 packet of size 0x10 */ 16955 count = 1000 * factor; 16956 while (count) { 16957 bxe_read_dmae(sc, NIG_REG_STAT2_BRB_OCTET, 2); 16958 val = *BXE_SP(sc, wb_data[0]); 16959 if (val == 0x10) { 16960 break; 16961 } 16962 16963 DELAY(10000); 16964 count--; 16965 } 16966 16967 if (val != 0x10) { 16968 BLOGE(sc, "NIG timeout val=0x%x\n", val); 16969 return (-1); 16970 } 16971 16972 /* wait until PRS register shows 1 packet */ 16973 count = (1000 * factor); 16974 while (count) { 16975 val = REG_RD(sc, PRS_REG_NUM_OF_PACKETS); 16976 if (val == 1) { 16977 break; 16978 } 16979 16980 DELAY(10000); 16981 count--; 16982 } 16983 16984 if (val != 0x1) { 16985 BLOGE(sc, "PRS timeout val=0x%x\n", val); 16986 return (-2); 16987 } 16988 16989 /* Reset and init BRB, PRS */ 16990 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03); 16991 DELAY(50000); 16992 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03); 16993 DELAY(50000); 16994 ecore_init_block(sc, BLOCK_BRB1, PHASE_COMMON); 16995 ecore_init_block(sc, BLOCK_PRS, PHASE_COMMON); 16996 16997 /* Disable inputs of parser neighbor blocks */ 16998 REG_WR(sc, TSDM_REG_ENABLE_IN1, 0x0); 16999 REG_WR(sc, TCM_REG_PRS_IFEN, 0x0); 17000 REG_WR(sc, CFC_REG_DEBUG0, 0x1); 17001 REG_WR(sc, NIG_REG_PRS_REQ_IN_EN, 0x0); 17002 17003 /* Write 0 to parser credits for CFC search request */ 17004 REG_WR(sc, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x0); 17005 17006 /* send 10 Ethernet packets */ 17007 for (i = 0; i < 10; i++) { 17008 bxe_lb_pckt(sc); 17009 } 17010 17011 /* Wait until NIG register shows 10+1 packets of size 11*0x10 = 0xb0 */ 17012 count = (1000 * factor); 17013 while (count) { 17014 bxe_read_dmae(sc, NIG_REG_STAT2_BRB_OCTET, 2); 17015 val = *BXE_SP(sc, wb_data[0]); 17016 if (val == 0xb0) { 17017 break; 17018 } 17019 17020 DELAY(10000); 17021 count--; 17022 } 17023 17024 if (val != 0xb0) { 17025 BLOGE(sc, "NIG timeout val=0x%x\n", val); 17026 return (-3); 17027 } 17028 17029 /* Wait until PRS register shows 2 packets */ 17030 val = REG_RD(sc, PRS_REG_NUM_OF_PACKETS); 17031 if (val != 2) { 17032 BLOGE(sc, "PRS timeout val=0x%x\n", val); 17033 } 17034 17035 /* Write 1 to parser credits for CFC search request */ 17036 REG_WR(sc, PRS_REG_CFC_SEARCH_INITIAL_CREDIT, 0x1); 17037 17038 /* Wait until PRS register shows 3 packets */ 17039 DELAY(10000 * factor); 17040 17041 /* Wait until NIG register shows 1 packet of size 0x10 */ 17042 val = REG_RD(sc, PRS_REG_NUM_OF_PACKETS); 17043 if (val != 3) { 17044 BLOGE(sc, "PRS timeout val=0x%x\n", val); 17045 } 17046 17047 /* clear NIG EOP FIFO */ 17048 for (i = 0; i < 11; i++) { 17049 REG_RD(sc, NIG_REG_INGRESS_EOP_LB_FIFO); 17050 } 17051 17052 val = REG_RD(sc, NIG_REG_INGRESS_EOP_LB_EMPTY); 17053 if (val != 1) { 17054 BLOGE(sc, "clear of NIG failed\n"); 17055 return (-4); 17056 } 17057 17058 /* Reset and init BRB, PRS, NIG */ 17059 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 0x03); 17060 DELAY(50000); 17061 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 0x03); 17062 DELAY(50000); 17063 ecore_init_block(sc, BLOCK_BRB1, PHASE_COMMON); 17064 ecore_init_block(sc, BLOCK_PRS, PHASE_COMMON); 17065 if (!CNIC_SUPPORT(sc)) { 17066 /* set NIC mode */ 17067 REG_WR(sc, PRS_REG_NIC_MODE, 1); 17068 } 17069 17070 /* Enable inputs of parser neighbor blocks */ 17071 REG_WR(sc, TSDM_REG_ENABLE_IN1, 0x7fffffff); 17072 REG_WR(sc, TCM_REG_PRS_IFEN, 0x1); 17073 REG_WR(sc, CFC_REG_DEBUG0, 0x0); 17074 REG_WR(sc, NIG_REG_PRS_REQ_IN_EN, 0x1); 17075 17076 return (0); 17077 } 17078 17079 static void 17080 bxe_setup_fan_failure_detection(struct bxe_softc *sc) 17081 { 17082 int is_required; 17083 uint32_t val; 17084 int port; 17085 17086 is_required = 0; 17087 val = (SHMEM_RD(sc, dev_info.shared_hw_config.config2) & 17088 SHARED_HW_CFG_FAN_FAILURE_MASK); 17089 17090 if (val == SHARED_HW_CFG_FAN_FAILURE_ENABLED) { 17091 is_required = 1; 17092 } 17093 /* 17094 * The fan failure mechanism is usually related to the PHY type since 17095 * the power consumption of the board is affected by the PHY. Currently, 17096 * fan is required for most designs with SFX7101, BCM8727 and BCM8481. 17097 */ 17098 else if (val == SHARED_HW_CFG_FAN_FAILURE_PHY_TYPE) { 17099 for (port = PORT_0; port < PORT_MAX; port++) { 17100 is_required |= elink_fan_failure_det_req(sc, 17101 sc->devinfo.shmem_base, 17102 sc->devinfo.shmem2_base, 17103 port); 17104 } 17105 } 17106 17107 BLOGD(sc, DBG_LOAD, "fan detection setting: %d\n", is_required); 17108 17109 if (is_required == 0) { 17110 return; 17111 } 17112 17113 /* Fan failure is indicated by SPIO 5 */ 17114 bxe_set_spio(sc, MISC_SPIO_SPIO5, MISC_SPIO_INPUT_HI_Z); 17115 17116 /* set to active low mode */ 17117 val = REG_RD(sc, MISC_REG_SPIO_INT); 17118 val |= (MISC_SPIO_SPIO5 << MISC_SPIO_INT_OLD_SET_POS); 17119 REG_WR(sc, MISC_REG_SPIO_INT, val); 17120 17121 /* enable interrupt to signal the IGU */ 17122 val = REG_RD(sc, MISC_REG_SPIO_EVENT_EN); 17123 val |= MISC_SPIO_SPIO5; 17124 REG_WR(sc, MISC_REG_SPIO_EVENT_EN, val); 17125 } 17126 17127 static void 17128 bxe_enable_blocks_attention(struct bxe_softc *sc) 17129 { 17130 uint32_t val; 17131 17132 REG_WR(sc, PXP_REG_PXP_INT_MASK_0, 0); 17133 if (!CHIP_IS_E1x(sc)) { 17134 REG_WR(sc, PXP_REG_PXP_INT_MASK_1, 0x40); 17135 } else { 17136 REG_WR(sc, PXP_REG_PXP_INT_MASK_1, 0); 17137 } 17138 REG_WR(sc, DORQ_REG_DORQ_INT_MASK, 0); 17139 REG_WR(sc, CFC_REG_CFC_INT_MASK, 0); 17140 /* 17141 * mask read length error interrupts in brb for parser 17142 * (parsing unit and 'checksum and crc' unit) 17143 * these errors are legal (PU reads fixed length and CAC can cause 17144 * read length error on truncated packets) 17145 */ 17146 REG_WR(sc, BRB1_REG_BRB1_INT_MASK, 0xFC00); 17147 REG_WR(sc, QM_REG_QM_INT_MASK, 0); 17148 REG_WR(sc, TM_REG_TM_INT_MASK, 0); 17149 REG_WR(sc, XSDM_REG_XSDM_INT_MASK_0, 0); 17150 REG_WR(sc, XSDM_REG_XSDM_INT_MASK_1, 0); 17151 REG_WR(sc, XCM_REG_XCM_INT_MASK, 0); 17152 /* REG_WR(sc, XSEM_REG_XSEM_INT_MASK_0, 0); */ 17153 /* REG_WR(sc, XSEM_REG_XSEM_INT_MASK_1, 0); */ 17154 REG_WR(sc, USDM_REG_USDM_INT_MASK_0, 0); 17155 REG_WR(sc, USDM_REG_USDM_INT_MASK_1, 0); 17156 REG_WR(sc, UCM_REG_UCM_INT_MASK, 0); 17157 /* REG_WR(sc, USEM_REG_USEM_INT_MASK_0, 0); */ 17158 /* REG_WR(sc, USEM_REG_USEM_INT_MASK_1, 0); */ 17159 REG_WR(sc, GRCBASE_UPB + PB_REG_PB_INT_MASK, 0); 17160 REG_WR(sc, CSDM_REG_CSDM_INT_MASK_0, 0); 17161 REG_WR(sc, CSDM_REG_CSDM_INT_MASK_1, 0); 17162 REG_WR(sc, CCM_REG_CCM_INT_MASK, 0); 17163 /* REG_WR(sc, CSEM_REG_CSEM_INT_MASK_0, 0); */ 17164 /* REG_WR(sc, CSEM_REG_CSEM_INT_MASK_1, 0); */ 17165 17166 val = (PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_AFT | 17167 PXP2_PXP2_INT_MASK_0_REG_PGL_CPL_OF | 17168 PXP2_PXP2_INT_MASK_0_REG_PGL_PCIE_ATTN); 17169 if (!CHIP_IS_E1x(sc)) { 17170 val |= (PXP2_PXP2_INT_MASK_0_REG_PGL_READ_BLOCKED | 17171 PXP2_PXP2_INT_MASK_0_REG_PGL_WRITE_BLOCKED); 17172 } 17173 REG_WR(sc, PXP2_REG_PXP2_INT_MASK_0, val); 17174 17175 REG_WR(sc, TSDM_REG_TSDM_INT_MASK_0, 0); 17176 REG_WR(sc, TSDM_REG_TSDM_INT_MASK_1, 0); 17177 REG_WR(sc, TCM_REG_TCM_INT_MASK, 0); 17178 /* REG_WR(sc, TSEM_REG_TSEM_INT_MASK_0, 0); */ 17179 17180 if (!CHIP_IS_E1x(sc)) { 17181 /* enable VFC attentions: bits 11 and 12, bits 31:13 reserved */ 17182 REG_WR(sc, TSEM_REG_TSEM_INT_MASK_1, 0x07ff); 17183 } 17184 17185 REG_WR(sc, CDU_REG_CDU_INT_MASK, 0); 17186 REG_WR(sc, DMAE_REG_DMAE_INT_MASK, 0); 17187 /* REG_WR(sc, MISC_REG_MISC_INT_MASK, 0); */ 17188 REG_WR(sc, PBF_REG_PBF_INT_MASK, 0x18); /* bit 3,4 masked */ 17189 } 17190 17191 /** 17192 * bxe_init_hw_common - initialize the HW at the COMMON phase. 17193 * 17194 * @sc: driver handle 17195 */ 17196 static int 17197 bxe_init_hw_common(struct bxe_softc *sc) 17198 { 17199 uint8_t abs_func_id; 17200 uint32_t val; 17201 17202 BLOGD(sc, DBG_LOAD, "starting common init for func %d\n", 17203 SC_ABS_FUNC(sc)); 17204 17205 /* 17206 * take the RESET lock to protect undi_unload flow from accessing 17207 * registers while we are resetting the chip 17208 */ 17209 bxe_acquire_hw_lock(sc, HW_LOCK_RESOURCE_RESET); 17210 17211 bxe_reset_common(sc); 17212 17213 REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET), 0xffffffff); 17214 17215 val = 0xfffc; 17216 if (CHIP_IS_E3(sc)) { 17217 val |= MISC_REGISTERS_RESET_REG_2_MSTAT0; 17218 val |= MISC_REGISTERS_RESET_REG_2_MSTAT1; 17219 } 17220 17221 REG_WR(sc, (GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET), val); 17222 17223 bxe_release_hw_lock(sc, HW_LOCK_RESOURCE_RESET); 17224 17225 ecore_init_block(sc, BLOCK_MISC, PHASE_COMMON); 17226 BLOGD(sc, DBG_LOAD, "after misc block init\n"); 17227 17228 if (!CHIP_IS_E1x(sc)) { 17229 /* 17230 * 4-port mode or 2-port mode we need to turn off master-enable for 17231 * everyone. After that we turn it back on for self. So, we disregard 17232 * multi-function, and always disable all functions on the given path, 17233 * this means 0,2,4,6 for path 0 and 1,3,5,7 for path 1 17234 */ 17235 for (abs_func_id = SC_PATH(sc); 17236 abs_func_id < (E2_FUNC_MAX * 2); 17237 abs_func_id += 2) { 17238 if (abs_func_id == SC_ABS_FUNC(sc)) { 17239 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); 17240 continue; 17241 } 17242 17243 bxe_pretend_func(sc, abs_func_id); 17244 17245 /* clear pf enable */ 17246 bxe_pf_disable(sc); 17247 17248 bxe_pretend_func(sc, SC_ABS_FUNC(sc)); 17249 } 17250 } 17251 17252 BLOGD(sc, DBG_LOAD, "after pf disable\n"); 17253 17254 ecore_init_block(sc, BLOCK_PXP, PHASE_COMMON); 17255 17256 if (CHIP_IS_E1(sc)) { 17257 /* 17258 * enable HW interrupt from PXP on USDM overflow 17259 * bit 16 on INT_MASK_0 17260 */ 17261 REG_WR(sc, PXP_REG_PXP_INT_MASK_0, 0); 17262 } 17263 17264 ecore_init_block(sc, BLOCK_PXP2, PHASE_COMMON); 17265 bxe_init_pxp(sc); 17266 17267 #ifdef __BIG_ENDIAN 17268 REG_WR(sc, PXP2_REG_RQ_QM_ENDIAN_M, 1); 17269 REG_WR(sc, PXP2_REG_RQ_TM_ENDIAN_M, 1); 17270 REG_WR(sc, PXP2_REG_RQ_SRC_ENDIAN_M, 1); 17271 REG_WR(sc, PXP2_REG_RQ_CDU_ENDIAN_M, 1); 17272 REG_WR(sc, PXP2_REG_RQ_DBG_ENDIAN_M, 1); 17273 /* make sure this value is 0 */ 17274 REG_WR(sc, PXP2_REG_RQ_HC_ENDIAN_M, 0); 17275 17276 //REG_WR(sc, PXP2_REG_RD_PBF_SWAP_MODE, 1); 17277 REG_WR(sc, PXP2_REG_RD_QM_SWAP_MODE, 1); 17278 REG_WR(sc, PXP2_REG_RD_TM_SWAP_MODE, 1); 17279 REG_WR(sc, PXP2_REG_RD_SRC_SWAP_MODE, 1); 17280 REG_WR(sc, PXP2_REG_RD_CDURD_SWAP_MODE, 1); 17281 #endif 17282 17283 ecore_ilt_init_page_size(sc, INITOP_SET); 17284 17285 if (CHIP_REV_IS_FPGA(sc) && CHIP_IS_E1H(sc)) { 17286 REG_WR(sc, PXP2_REG_PGL_TAGS_LIMIT, 0x1); 17287 } 17288 17289 /* let the HW do it's magic... */ 17290 DELAY(100000); 17291 17292 /* finish PXP init */ 17293 val = REG_RD(sc, PXP2_REG_RQ_CFG_DONE); 17294 if (val != 1) { 17295 BLOGE(sc, "PXP2 CFG failed\n"); 17296 return (-1); 17297 } 17298 val = REG_RD(sc, PXP2_REG_RD_INIT_DONE); 17299 if (val != 1) { 17300 BLOGE(sc, "PXP2 RD_INIT failed\n"); 17301 return (-1); 17302 } 17303 17304 BLOGD(sc, DBG_LOAD, "after pxp init\n"); 17305 17306 /* 17307 * Timer bug workaround for E2 only. We need to set the entire ILT to have 17308 * entries with value "0" and valid bit on. This needs to be done by the 17309 * first PF that is loaded in a path (i.e. common phase) 17310 */ 17311 if (!CHIP_IS_E1x(sc)) { 17312 /* 17313 * In E2 there is a bug in the timers block that can cause function 6 / 7 17314 * (i.e. vnic3) to start even if it is marked as "scan-off". 17315 * This occurs when a different function (func2,3) is being marked 17316 * as "scan-off". Real-life scenario for example: if a driver is being 17317 * load-unloaded while func6,7 are down. This will cause the timer to access 17318 * the ilt, translate to a logical address and send a request to read/write. 17319 * Since the ilt for the function that is down is not valid, this will cause 17320 * a translation error which is unrecoverable. 17321 * The Workaround is intended to make sure that when this happens nothing 17322 * fatal will occur. The workaround: 17323 * 1. First PF driver which loads on a path will: 17324 * a. After taking the chip out of reset, by using pretend, 17325 * it will write "0" to the following registers of 17326 * the other vnics. 17327 * REG_WR(pdev, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 0); 17328 * REG_WR(pdev, CFC_REG_WEAK_ENABLE_PF,0); 17329 * REG_WR(pdev, CFC_REG_STRONG_ENABLE_PF,0); 17330 * And for itself it will write '1' to 17331 * PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER to enable 17332 * dmae-operations (writing to pram for example.) 17333 * note: can be done for only function 6,7 but cleaner this 17334 * way. 17335 * b. Write zero+valid to the entire ILT. 17336 * c. Init the first_timers_ilt_entry, last_timers_ilt_entry of 17337 * VNIC3 (of that port). The range allocated will be the 17338 * entire ILT. This is needed to prevent ILT range error. 17339 * 2. Any PF driver load flow: 17340 * a. ILT update with the physical addresses of the allocated 17341 * logical pages. 17342 * b. Wait 20msec. - note that this timeout is needed to make 17343 * sure there are no requests in one of the PXP internal 17344 * queues with "old" ILT addresses. 17345 * c. PF enable in the PGLC. 17346 * d. Clear the was_error of the PF in the PGLC. (could have 17347 * occurred while driver was down) 17348 * e. PF enable in the CFC (WEAK + STRONG) 17349 * f. Timers scan enable 17350 * 3. PF driver unload flow: 17351 * a. Clear the Timers scan_en. 17352 * b. Polling for scan_on=0 for that PF. 17353 * c. Clear the PF enable bit in the PXP. 17354 * d. Clear the PF enable in the CFC (WEAK + STRONG) 17355 * e. Write zero+valid to all ILT entries (The valid bit must 17356 * stay set) 17357 * f. If this is VNIC 3 of a port then also init 17358 * first_timers_ilt_entry to zero and last_timers_ilt_entry 17359 * to the last enrty in the ILT. 17360 * 17361 * Notes: 17362 * Currently the PF error in the PGLC is non recoverable. 17363 * In the future the there will be a recovery routine for this error. 17364 * Currently attention is masked. 17365 * Having an MCP lock on the load/unload process does not guarantee that 17366 * there is no Timer disable during Func6/7 enable. This is because the 17367 * Timers scan is currently being cleared by the MCP on FLR. 17368 * Step 2.d can be done only for PF6/7 and the driver can also check if 17369 * there is error before clearing it. But the flow above is simpler and 17370 * more general. 17371 * All ILT entries are written by zero+valid and not just PF6/7 17372 * ILT entries since in the future the ILT entries allocation for 17373 * PF-s might be dynamic. 17374 */ 17375 struct ilt_client_info ilt_cli; 17376 struct ecore_ilt ilt; 17377 17378 memset(&ilt_cli, 0, sizeof(struct ilt_client_info)); 17379 memset(&ilt, 0, sizeof(struct ecore_ilt)); 17380 17381 /* initialize dummy TM client */ 17382 ilt_cli.start = 0; 17383 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1; 17384 ilt_cli.client_num = ILT_CLIENT_TM; 17385 17386 /* 17387 * Step 1: set zeroes to all ilt page entries with valid bit on 17388 * Step 2: set the timers first/last ilt entry to point 17389 * to the entire range to prevent ILT range error for 3rd/4th 17390 * vnic (this code assumes existence of the vnic) 17391 * 17392 * both steps performed by call to ecore_ilt_client_init_op() 17393 * with dummy TM client 17394 * 17395 * we must use pretend since PXP2_REG_RQ_##blk##_FIRST_ILT 17396 * and his brother are split registers 17397 */ 17398 17399 bxe_pretend_func(sc, (SC_PATH(sc) + 6)); 17400 ecore_ilt_client_init_op_ilt(sc, &ilt, &ilt_cli, INITOP_CLEAR); 17401 bxe_pretend_func(sc, SC_ABS_FUNC(sc)); 17402 17403 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN, BXE_PXP_DRAM_ALIGN); 17404 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN_RD, BXE_PXP_DRAM_ALIGN); 17405 REG_WR(sc, PXP2_REG_RQ_DRAM_ALIGN_SEL, 1); 17406 } 17407 17408 REG_WR(sc, PXP2_REG_RQ_DISABLE_INPUTS, 0); 17409 REG_WR(sc, PXP2_REG_RD_DISABLE_INPUTS, 0); 17410 17411 if (!CHIP_IS_E1x(sc)) { 17412 int factor = CHIP_REV_IS_EMUL(sc) ? 1000 : 17413 (CHIP_REV_IS_FPGA(sc) ? 400 : 0); 17414 17415 ecore_init_block(sc, BLOCK_PGLUE_B, PHASE_COMMON); 17416 ecore_init_block(sc, BLOCK_ATC, PHASE_COMMON); 17417 17418 /* let the HW do it's magic... */ 17419 do { 17420 DELAY(200000); 17421 val = REG_RD(sc, ATC_REG_ATC_INIT_DONE); 17422 } while (factor-- && (val != 1)); 17423 17424 if (val != 1) { 17425 BLOGE(sc, "ATC_INIT failed\n"); 17426 return (-1); 17427 } 17428 } 17429 17430 BLOGD(sc, DBG_LOAD, "after pglue and atc init\n"); 17431 17432 ecore_init_block(sc, BLOCK_DMAE, PHASE_COMMON); 17433 17434 bxe_iov_init_dmae(sc); 17435 17436 /* clean the DMAE memory */ 17437 sc->dmae_ready = 1; 17438 ecore_init_fill(sc, TSEM_REG_PRAM, 0, 8, 1); 17439 17440 ecore_init_block(sc, BLOCK_TCM, PHASE_COMMON); 17441 17442 ecore_init_block(sc, BLOCK_UCM, PHASE_COMMON); 17443 17444 ecore_init_block(sc, BLOCK_CCM, PHASE_COMMON); 17445 17446 ecore_init_block(sc, BLOCK_XCM, PHASE_COMMON); 17447 17448 bxe_read_dmae(sc, XSEM_REG_PASSIVE_BUFFER, 3); 17449 bxe_read_dmae(sc, CSEM_REG_PASSIVE_BUFFER, 3); 17450 bxe_read_dmae(sc, TSEM_REG_PASSIVE_BUFFER, 3); 17451 bxe_read_dmae(sc, USEM_REG_PASSIVE_BUFFER, 3); 17452 17453 ecore_init_block(sc, BLOCK_QM, PHASE_COMMON); 17454 17455 /* QM queues pointers table */ 17456 ecore_qm_init_ptr_table(sc, sc->qm_cid_count, INITOP_SET); 17457 17458 /* soft reset pulse */ 17459 REG_WR(sc, QM_REG_SOFT_RESET, 1); 17460 REG_WR(sc, QM_REG_SOFT_RESET, 0); 17461 17462 if (CNIC_SUPPORT(sc)) 17463 ecore_init_block(sc, BLOCK_TM, PHASE_COMMON); 17464 17465 ecore_init_block(sc, BLOCK_DORQ, PHASE_COMMON); 17466 REG_WR(sc, DORQ_REG_DPM_CID_OFST, BXE_DB_SHIFT); 17467 if (!CHIP_REV_IS_SLOW(sc)) { 17468 /* enable hw interrupt from doorbell Q */ 17469 REG_WR(sc, DORQ_REG_DORQ_INT_MASK, 0); 17470 } 17471 17472 ecore_init_block(sc, BLOCK_BRB1, PHASE_COMMON); 17473 17474 ecore_init_block(sc, BLOCK_PRS, PHASE_COMMON); 17475 REG_WR(sc, PRS_REG_A_PRSU_20, 0xf); 17476 17477 if (!CHIP_IS_E1(sc)) { 17478 REG_WR(sc, PRS_REG_E1HOV_MODE, sc->devinfo.mf_info.path_has_ovlan); 17479 } 17480 17481 if (!CHIP_IS_E1x(sc) && !CHIP_IS_E3B0(sc)) { 17482 if (IS_MF_AFEX(sc)) { 17483 /* 17484 * configure that AFEX and VLAN headers must be 17485 * received in AFEX mode 17486 */ 17487 REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC, 0xE); 17488 REG_WR(sc, PRS_REG_MUST_HAVE_HDRS, 0xA); 17489 REG_WR(sc, PRS_REG_HDRS_AFTER_TAG_0, 0x6); 17490 REG_WR(sc, PRS_REG_TAG_ETHERTYPE_0, 0x8926); 17491 REG_WR(sc, PRS_REG_TAG_LEN_0, 0x4); 17492 } else { 17493 /* 17494 * Bit-map indicating which L2 hdrs may appear 17495 * after the basic Ethernet header 17496 */ 17497 REG_WR(sc, PRS_REG_HDRS_AFTER_BASIC, 17498 sc->devinfo.mf_info.path_has_ovlan ? 7 : 6); 17499 } 17500 } 17501 17502 ecore_init_block(sc, BLOCK_TSDM, PHASE_COMMON); 17503 ecore_init_block(sc, BLOCK_CSDM, PHASE_COMMON); 17504 ecore_init_block(sc, BLOCK_USDM, PHASE_COMMON); 17505 ecore_init_block(sc, BLOCK_XSDM, PHASE_COMMON); 17506 17507 if (!CHIP_IS_E1x(sc)) { 17508 /* reset VFC memories */ 17509 REG_WR(sc, TSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST, 17510 VFC_MEMORIES_RST_REG_CAM_RST | 17511 VFC_MEMORIES_RST_REG_RAM_RST); 17512 REG_WR(sc, XSEM_REG_FAST_MEMORY + VFC_REG_MEMORIES_RST, 17513 VFC_MEMORIES_RST_REG_CAM_RST | 17514 VFC_MEMORIES_RST_REG_RAM_RST); 17515 17516 DELAY(20000); 17517 } 17518 17519 ecore_init_block(sc, BLOCK_TSEM, PHASE_COMMON); 17520 ecore_init_block(sc, BLOCK_USEM, PHASE_COMMON); 17521 ecore_init_block(sc, BLOCK_CSEM, PHASE_COMMON); 17522 ecore_init_block(sc, BLOCK_XSEM, PHASE_COMMON); 17523 17524 /* sync semi rtc */ 17525 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_CLEAR, 17526 0x80000000); 17527 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_1_SET, 17528 0x80000000); 17529 17530 ecore_init_block(sc, BLOCK_UPB, PHASE_COMMON); 17531 ecore_init_block(sc, BLOCK_XPB, PHASE_COMMON); 17532 ecore_init_block(sc, BLOCK_PBF, PHASE_COMMON); 17533 17534 if (!CHIP_IS_E1x(sc)) { 17535 if (IS_MF_AFEX(sc)) { 17536 /* 17537 * configure that AFEX and VLAN headers must be 17538 * sent in AFEX mode 17539 */ 17540 REG_WR(sc, PBF_REG_HDRS_AFTER_BASIC, 0xE); 17541 REG_WR(sc, PBF_REG_MUST_HAVE_HDRS, 0xA); 17542 REG_WR(sc, PBF_REG_HDRS_AFTER_TAG_0, 0x6); 17543 REG_WR(sc, PBF_REG_TAG_ETHERTYPE_0, 0x8926); 17544 REG_WR(sc, PBF_REG_TAG_LEN_0, 0x4); 17545 } else { 17546 REG_WR(sc, PBF_REG_HDRS_AFTER_BASIC, 17547 sc->devinfo.mf_info.path_has_ovlan ? 7 : 6); 17548 } 17549 } 17550 17551 REG_WR(sc, SRC_REG_SOFT_RST, 1); 17552 17553 ecore_init_block(sc, BLOCK_SRC, PHASE_COMMON); 17554 17555 if (CNIC_SUPPORT(sc)) { 17556 REG_WR(sc, SRC_REG_KEYSEARCH_0, 0x63285672); 17557 REG_WR(sc, SRC_REG_KEYSEARCH_1, 0x24b8f2cc); 17558 REG_WR(sc, SRC_REG_KEYSEARCH_2, 0x223aef9b); 17559 REG_WR(sc, SRC_REG_KEYSEARCH_3, 0x26001e3a); 17560 REG_WR(sc, SRC_REG_KEYSEARCH_4, 0x7ae91116); 17561 REG_WR(sc, SRC_REG_KEYSEARCH_5, 0x5ce5230b); 17562 REG_WR(sc, SRC_REG_KEYSEARCH_6, 0x298d8adf); 17563 REG_WR(sc, SRC_REG_KEYSEARCH_7, 0x6eb0ff09); 17564 REG_WR(sc, SRC_REG_KEYSEARCH_8, 0x1830f82f); 17565 REG_WR(sc, SRC_REG_KEYSEARCH_9, 0x01e46be7); 17566 } 17567 REG_WR(sc, SRC_REG_SOFT_RST, 0); 17568 17569 if (sizeof(union cdu_context) != 1024) { 17570 /* we currently assume that a context is 1024 bytes */ 17571 BLOGE(sc, "please adjust the size of cdu_context(%ld)\n", 17572 (long)sizeof(union cdu_context)); 17573 } 17574 17575 ecore_init_block(sc, BLOCK_CDU, PHASE_COMMON); 17576 val = (4 << 24) + (0 << 12) + 1024; 17577 REG_WR(sc, CDU_REG_CDU_GLOBAL_PARAMS, val); 17578 17579 ecore_init_block(sc, BLOCK_CFC, PHASE_COMMON); 17580 17581 REG_WR(sc, CFC_REG_INIT_REG, 0x7FF); 17582 /* enable context validation interrupt from CFC */ 17583 REG_WR(sc, CFC_REG_CFC_INT_MASK, 0); 17584 17585 /* set the thresholds to prevent CFC/CDU race */ 17586 REG_WR(sc, CFC_REG_DEBUG0, 0x20020000); 17587 ecore_init_block(sc, BLOCK_HC, PHASE_COMMON); 17588 17589 if (!CHIP_IS_E1x(sc) && BXE_NOMCP(sc)) { 17590 REG_WR(sc, IGU_REG_RESET_MEMORIES, 0x36); 17591 } 17592 17593 ecore_init_block(sc, BLOCK_IGU, PHASE_COMMON); 17594 ecore_init_block(sc, BLOCK_MISC_AEU, PHASE_COMMON); 17595 17596 /* Reset PCIE errors for debug */ 17597 REG_WR(sc, 0x2814, 0xffffffff); 17598 REG_WR(sc, 0x3820, 0xffffffff); 17599 17600 if (!CHIP_IS_E1x(sc)) { 17601 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_CONTROL_5, 17602 (PXPCS_TL_CONTROL_5_ERR_UNSPPORT1 | 17603 PXPCS_TL_CONTROL_5_ERR_UNSPPORT)); 17604 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_FUNC345_STAT, 17605 (PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT4 | 17606 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT3 | 17607 PXPCS_TL_FUNC345_STAT_ERR_UNSPPORT2)); 17608 REG_WR(sc, PCICFG_OFFSET + PXPCS_TL_FUNC678_STAT, 17609 (PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT7 | 17610 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT6 | 17611 PXPCS_TL_FUNC678_STAT_ERR_UNSPPORT5)); 17612 } 17613 17614 ecore_init_block(sc, BLOCK_NIG, PHASE_COMMON); 17615 17616 if (!CHIP_IS_E1(sc)) { 17617 /* in E3 this done in per-port section */ 17618 if (!CHIP_IS_E3(sc)) 17619 REG_WR(sc, NIG_REG_LLH_MF_MODE, IS_MF(sc)); 17620 } 17621 17622 if (CHIP_IS_E1H(sc)) { 17623 /* not applicable for E2 (and above ...) */ 17624 REG_WR(sc, NIG_REG_LLH_E1HOV_MODE, IS_MF_SD(sc)); 17625 } 17626 17627 if (CHIP_REV_IS_SLOW(sc)) { 17628 DELAY(200000); 17629 } 17630 17631 /* finish CFC init */ 17632 val = reg_poll(sc, CFC_REG_LL_INIT_DONE, 1, 100, 10); 17633 if (val != 1) { 17634 BLOGE(sc, "CFC LL_INIT failed\n"); 17635 return (-1); 17636 } 17637 val = reg_poll(sc, CFC_REG_AC_INIT_DONE, 1, 100, 10); 17638 if (val != 1) { 17639 BLOGE(sc, "CFC AC_INIT failed\n"); 17640 return (-1); 17641 } 17642 val = reg_poll(sc, CFC_REG_CAM_INIT_DONE, 1, 100, 10); 17643 if (val != 1) { 17644 BLOGE(sc, "CFC CAM_INIT failed\n"); 17645 return (-1); 17646 } 17647 REG_WR(sc, CFC_REG_DEBUG0, 0); 17648 17649 if (CHIP_IS_E1(sc)) { 17650 /* read NIG statistic to see if this is our first up since powerup */ 17651 bxe_read_dmae(sc, NIG_REG_STAT2_BRB_OCTET, 2); 17652 val = *BXE_SP(sc, wb_data[0]); 17653 17654 /* do internal memory self test */ 17655 if ((val == 0) && bxe_int_mem_test(sc)) { 17656 BLOGE(sc, "internal mem self test failed\n"); 17657 return (-1); 17658 } 17659 } 17660 17661 bxe_setup_fan_failure_detection(sc); 17662 17663 /* clear PXP2 attentions */ 17664 REG_RD(sc, PXP2_REG_PXP2_INT_STS_CLR_0); 17665 17666 bxe_enable_blocks_attention(sc); 17667 17668 if (!CHIP_REV_IS_SLOW(sc)) { 17669 ecore_enable_blocks_parity(sc); 17670 } 17671 17672 if (!BXE_NOMCP(sc)) { 17673 if (CHIP_IS_E1x(sc)) { 17674 bxe_common_init_phy(sc); 17675 } 17676 } 17677 17678 return (0); 17679 } 17680 17681 /** 17682 * bxe_init_hw_common_chip - init HW at the COMMON_CHIP phase. 17683 * 17684 * @sc: driver handle 17685 */ 17686 static int 17687 bxe_init_hw_common_chip(struct bxe_softc *sc) 17688 { 17689 int rc = bxe_init_hw_common(sc); 17690 17691 if (rc) { 17692 return (rc); 17693 } 17694 17695 /* In E2 2-PORT mode, same ext phy is used for the two paths */ 17696 if (!BXE_NOMCP(sc)) { 17697 bxe_common_init_phy(sc); 17698 } 17699 17700 return (0); 17701 } 17702 17703 static int 17704 bxe_init_hw_port(struct bxe_softc *sc) 17705 { 17706 int port = SC_PORT(sc); 17707 int init_phase = port ? PHASE_PORT1 : PHASE_PORT0; 17708 uint32_t low, high; 17709 uint32_t val; 17710 17711 BLOGD(sc, DBG_LOAD, "starting port init for port %d\n", port); 17712 17713 REG_WR(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0); 17714 17715 ecore_init_block(sc, BLOCK_MISC, init_phase); 17716 ecore_init_block(sc, BLOCK_PXP, init_phase); 17717 ecore_init_block(sc, BLOCK_PXP2, init_phase); 17718 17719 /* 17720 * Timers bug workaround: disables the pf_master bit in pglue at 17721 * common phase, we need to enable it here before any dmae access are 17722 * attempted. Therefore we manually added the enable-master to the 17723 * port phase (it also happens in the function phase) 17724 */ 17725 if (!CHIP_IS_E1x(sc)) { 17726 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); 17727 } 17728 17729 ecore_init_block(sc, BLOCK_ATC, init_phase); 17730 ecore_init_block(sc, BLOCK_DMAE, init_phase); 17731 ecore_init_block(sc, BLOCK_PGLUE_B, init_phase); 17732 ecore_init_block(sc, BLOCK_QM, init_phase); 17733 17734 ecore_init_block(sc, BLOCK_TCM, init_phase); 17735 ecore_init_block(sc, BLOCK_UCM, init_phase); 17736 ecore_init_block(sc, BLOCK_CCM, init_phase); 17737 ecore_init_block(sc, BLOCK_XCM, init_phase); 17738 17739 /* QM cid (connection) count */ 17740 ecore_qm_init_cid_count(sc, sc->qm_cid_count, INITOP_SET); 17741 17742 if (CNIC_SUPPORT(sc)) { 17743 ecore_init_block(sc, BLOCK_TM, init_phase); 17744 REG_WR(sc, TM_REG_LIN0_SCAN_TIME + port*4, 20); 17745 REG_WR(sc, TM_REG_LIN0_MAX_ACTIVE_CID + port*4, 31); 17746 } 17747 17748 ecore_init_block(sc, BLOCK_DORQ, init_phase); 17749 17750 ecore_init_block(sc, BLOCK_BRB1, init_phase); 17751 17752 if (CHIP_IS_E1(sc) || CHIP_IS_E1H(sc)) { 17753 if (IS_MF(sc)) { 17754 low = (BXE_ONE_PORT(sc) ? 160 : 246); 17755 } else if (sc->mtu > 4096) { 17756 if (BXE_ONE_PORT(sc)) { 17757 low = 160; 17758 } else { 17759 val = sc->mtu; 17760 /* (24*1024 + val*4)/256 */ 17761 low = (96 + (val / 64) + ((val % 64) ? 1 : 0)); 17762 } 17763 } else { 17764 low = (BXE_ONE_PORT(sc) ? 80 : 160); 17765 } 17766 high = (low + 56); /* 14*1024/256 */ 17767 REG_WR(sc, BRB1_REG_PAUSE_LOW_THRESHOLD_0 + port*4, low); 17768 REG_WR(sc, BRB1_REG_PAUSE_HIGH_THRESHOLD_0 + port*4, high); 17769 } 17770 17771 if (CHIP_IS_MODE_4_PORT(sc)) { 17772 REG_WR(sc, SC_PORT(sc) ? 17773 BRB1_REG_MAC_GUARANTIED_1 : 17774 BRB1_REG_MAC_GUARANTIED_0, 40); 17775 } 17776 17777 ecore_init_block(sc, BLOCK_PRS, init_phase); 17778 if (CHIP_IS_E3B0(sc)) { 17779 if (IS_MF_AFEX(sc)) { 17780 /* configure headers for AFEX mode */ 17781 REG_WR(sc, SC_PORT(sc) ? 17782 PRS_REG_HDRS_AFTER_BASIC_PORT_1 : 17783 PRS_REG_HDRS_AFTER_BASIC_PORT_0, 0xE); 17784 REG_WR(sc, SC_PORT(sc) ? 17785 PRS_REG_HDRS_AFTER_TAG_0_PORT_1 : 17786 PRS_REG_HDRS_AFTER_TAG_0_PORT_0, 0x6); 17787 REG_WR(sc, SC_PORT(sc) ? 17788 PRS_REG_MUST_HAVE_HDRS_PORT_1 : 17789 PRS_REG_MUST_HAVE_HDRS_PORT_0, 0xA); 17790 } else { 17791 /* Ovlan exists only if we are in multi-function + 17792 * switch-dependent mode, in switch-independent there 17793 * is no ovlan headers 17794 */ 17795 REG_WR(sc, SC_PORT(sc) ? 17796 PRS_REG_HDRS_AFTER_BASIC_PORT_1 : 17797 PRS_REG_HDRS_AFTER_BASIC_PORT_0, 17798 (sc->devinfo.mf_info.path_has_ovlan ? 7 : 6)); 17799 } 17800 } 17801 17802 ecore_init_block(sc, BLOCK_TSDM, init_phase); 17803 ecore_init_block(sc, BLOCK_CSDM, init_phase); 17804 ecore_init_block(sc, BLOCK_USDM, init_phase); 17805 ecore_init_block(sc, BLOCK_XSDM, init_phase); 17806 17807 ecore_init_block(sc, BLOCK_TSEM, init_phase); 17808 ecore_init_block(sc, BLOCK_USEM, init_phase); 17809 ecore_init_block(sc, BLOCK_CSEM, init_phase); 17810 ecore_init_block(sc, BLOCK_XSEM, init_phase); 17811 17812 ecore_init_block(sc, BLOCK_UPB, init_phase); 17813 ecore_init_block(sc, BLOCK_XPB, init_phase); 17814 17815 ecore_init_block(sc, BLOCK_PBF, init_phase); 17816 17817 if (CHIP_IS_E1x(sc)) { 17818 /* configure PBF to work without PAUSE mtu 9000 */ 17819 REG_WR(sc, PBF_REG_P0_PAUSE_ENABLE + port*4, 0); 17820 17821 /* update threshold */ 17822 REG_WR(sc, PBF_REG_P0_ARB_THRSH + port*4, (9040/16)); 17823 /* update init credit */ 17824 REG_WR(sc, PBF_REG_P0_INIT_CRD + port*4, (9040/16) + 553 - 22); 17825 17826 /* probe changes */ 17827 REG_WR(sc, PBF_REG_INIT_P0 + port*4, 1); 17828 DELAY(50); 17829 REG_WR(sc, PBF_REG_INIT_P0 + port*4, 0); 17830 } 17831 17832 if (CNIC_SUPPORT(sc)) { 17833 ecore_init_block(sc, BLOCK_SRC, init_phase); 17834 } 17835 17836 ecore_init_block(sc, BLOCK_CDU, init_phase); 17837 ecore_init_block(sc, BLOCK_CFC, init_phase); 17838 17839 if (CHIP_IS_E1(sc)) { 17840 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port*8, 0); 17841 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port*8, 0); 17842 } 17843 ecore_init_block(sc, BLOCK_HC, init_phase); 17844 17845 ecore_init_block(sc, BLOCK_IGU, init_phase); 17846 17847 ecore_init_block(sc, BLOCK_MISC_AEU, init_phase); 17848 /* init aeu_mask_attn_func_0/1: 17849 * - SF mode: bits 3-7 are masked. only bits 0-2 are in use 17850 * - MF mode: bit 3 is masked. bits 0-2 are in use as in SF 17851 * bits 4-7 are used for "per vn group attention" */ 17852 val = IS_MF(sc) ? 0xF7 : 0x7; 17853 /* Enable DCBX attention for all but E1 */ 17854 val |= CHIP_IS_E1(sc) ? 0 : 0x10; 17855 REG_WR(sc, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, val); 17856 17857 ecore_init_block(sc, BLOCK_NIG, init_phase); 17858 17859 if (!CHIP_IS_E1x(sc)) { 17860 /* Bit-map indicating which L2 hdrs may appear after the 17861 * basic Ethernet header 17862 */ 17863 if (IS_MF_AFEX(sc)) { 17864 REG_WR(sc, SC_PORT(sc) ? 17865 NIG_REG_P1_HDRS_AFTER_BASIC : 17866 NIG_REG_P0_HDRS_AFTER_BASIC, 0xE); 17867 } else { 17868 REG_WR(sc, SC_PORT(sc) ? 17869 NIG_REG_P1_HDRS_AFTER_BASIC : 17870 NIG_REG_P0_HDRS_AFTER_BASIC, 17871 IS_MF_SD(sc) ? 7 : 6); 17872 } 17873 17874 if (CHIP_IS_E3(sc)) { 17875 REG_WR(sc, SC_PORT(sc) ? 17876 NIG_REG_LLH1_MF_MODE : 17877 NIG_REG_LLH_MF_MODE, IS_MF(sc)); 17878 } 17879 } 17880 if (!CHIP_IS_E3(sc)) { 17881 REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1); 17882 } 17883 17884 if (!CHIP_IS_E1(sc)) { 17885 /* 0x2 disable mf_ov, 0x1 enable */ 17886 REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK_MF + port*4, 17887 (IS_MF_SD(sc) ? 0x1 : 0x2)); 17888 17889 if (!CHIP_IS_E1x(sc)) { 17890 val = 0; 17891 switch (sc->devinfo.mf_info.mf_mode) { 17892 case MULTI_FUNCTION_SD: 17893 val = 1; 17894 break; 17895 case MULTI_FUNCTION_SI: 17896 case MULTI_FUNCTION_AFEX: 17897 val = 2; 17898 break; 17899 } 17900 17901 REG_WR(sc, (SC_PORT(sc) ? NIG_REG_LLH1_CLS_TYPE : 17902 NIG_REG_LLH0_CLS_TYPE), val); 17903 } 17904 REG_WR(sc, NIG_REG_LLFC_ENABLE_0 + port*4, 0); 17905 REG_WR(sc, NIG_REG_LLFC_OUT_EN_0 + port*4, 0); 17906 REG_WR(sc, NIG_REG_PAUSE_ENABLE_0 + port*4, 1); 17907 } 17908 17909 /* If SPIO5 is set to generate interrupts, enable it for this port */ 17910 val = REG_RD(sc, MISC_REG_SPIO_EVENT_EN); 17911 if (val & MISC_SPIO_SPIO5) { 17912 uint32_t reg_addr = (port ? MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0 : 17913 MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0); 17914 val = REG_RD(sc, reg_addr); 17915 val |= AEU_INPUTS_ATTN_BITS_SPIO5; 17916 REG_WR(sc, reg_addr, val); 17917 } 17918 17919 return (0); 17920 } 17921 17922 static uint32_t 17923 bxe_flr_clnup_reg_poll(struct bxe_softc *sc, 17924 uint32_t reg, 17925 uint32_t expected, 17926 uint32_t poll_count) 17927 { 17928 uint32_t cur_cnt = poll_count; 17929 uint32_t val; 17930 17931 while ((val = REG_RD(sc, reg)) != expected && cur_cnt--) { 17932 DELAY(FLR_WAIT_INTERVAL); 17933 } 17934 17935 return (val); 17936 } 17937 17938 static int 17939 bxe_flr_clnup_poll_hw_counter(struct bxe_softc *sc, 17940 uint32_t reg, 17941 char *msg, 17942 uint32_t poll_cnt) 17943 { 17944 uint32_t val = bxe_flr_clnup_reg_poll(sc, reg, 0, poll_cnt); 17945 17946 if (val != 0) { 17947 BLOGE(sc, "%s usage count=%d\n", msg, val); 17948 return (1); 17949 } 17950 17951 return (0); 17952 } 17953 17954 /* Common routines with VF FLR cleanup */ 17955 static uint32_t 17956 bxe_flr_clnup_poll_count(struct bxe_softc *sc) 17957 { 17958 /* adjust polling timeout */ 17959 if (CHIP_REV_IS_EMUL(sc)) { 17960 return (FLR_POLL_CNT * 2000); 17961 } 17962 17963 if (CHIP_REV_IS_FPGA(sc)) { 17964 return (FLR_POLL_CNT * 120); 17965 } 17966 17967 return (FLR_POLL_CNT); 17968 } 17969 17970 static int 17971 bxe_poll_hw_usage_counters(struct bxe_softc *sc, 17972 uint32_t poll_cnt) 17973 { 17974 /* wait for CFC PF usage-counter to zero (includes all the VFs) */ 17975 if (bxe_flr_clnup_poll_hw_counter(sc, 17976 CFC_REG_NUM_LCIDS_INSIDE_PF, 17977 "CFC PF usage counter timed out", 17978 poll_cnt)) { 17979 return (1); 17980 } 17981 17982 /* Wait for DQ PF usage-counter to zero (until DQ cleanup) */ 17983 if (bxe_flr_clnup_poll_hw_counter(sc, 17984 DORQ_REG_PF_USAGE_CNT, 17985 "DQ PF usage counter timed out", 17986 poll_cnt)) { 17987 return (1); 17988 } 17989 17990 /* Wait for QM PF usage-counter to zero (until DQ cleanup) */ 17991 if (bxe_flr_clnup_poll_hw_counter(sc, 17992 QM_REG_PF_USG_CNT_0 + 4*SC_FUNC(sc), 17993 "QM PF usage counter timed out", 17994 poll_cnt)) { 17995 return (1); 17996 } 17997 17998 /* Wait for Timer PF usage-counters to zero (until DQ cleanup) */ 17999 if (bxe_flr_clnup_poll_hw_counter(sc, 18000 TM_REG_LIN0_VNIC_UC + 4*SC_PORT(sc), 18001 "Timers VNIC usage counter timed out", 18002 poll_cnt)) { 18003 return (1); 18004 } 18005 18006 if (bxe_flr_clnup_poll_hw_counter(sc, 18007 TM_REG_LIN0_NUM_SCANS + 4*SC_PORT(sc), 18008 "Timers NUM_SCANS usage counter timed out", 18009 poll_cnt)) { 18010 return (1); 18011 } 18012 18013 /* Wait DMAE PF usage counter to zero */ 18014 if (bxe_flr_clnup_poll_hw_counter(sc, 18015 dmae_reg_go_c[INIT_DMAE_C(sc)], 18016 "DMAE dommand register timed out", 18017 poll_cnt)) { 18018 return (1); 18019 } 18020 18021 return (0); 18022 } 18023 18024 #define OP_GEN_PARAM(param) \ 18025 (((param) << SDM_OP_GEN_COMP_PARAM_SHIFT) & SDM_OP_GEN_COMP_PARAM) 18026 #define OP_GEN_TYPE(type) \ 18027 (((type) << SDM_OP_GEN_COMP_TYPE_SHIFT) & SDM_OP_GEN_COMP_TYPE) 18028 #define OP_GEN_AGG_VECT(index) \ 18029 (((index) << SDM_OP_GEN_AGG_VECT_IDX_SHIFT) & SDM_OP_GEN_AGG_VECT_IDX) 18030 18031 static int 18032 bxe_send_final_clnup(struct bxe_softc *sc, 18033 uint8_t clnup_func, 18034 uint32_t poll_cnt) 18035 { 18036 uint32_t op_gen_command = 0; 18037 uint32_t comp_addr = (BAR_CSTRORM_INTMEM + 18038 CSTORM_FINAL_CLEANUP_COMPLETE_OFFSET(clnup_func)); 18039 int ret = 0; 18040 18041 if (REG_RD(sc, comp_addr)) { 18042 BLOGE(sc, "Cleanup complete was not 0 before sending\n"); 18043 return (1); 18044 } 18045 18046 op_gen_command |= OP_GEN_PARAM(XSTORM_AGG_INT_FINAL_CLEANUP_INDEX); 18047 op_gen_command |= OP_GEN_TYPE(XSTORM_AGG_INT_FINAL_CLEANUP_COMP_TYPE); 18048 op_gen_command |= OP_GEN_AGG_VECT(clnup_func); 18049 op_gen_command |= 1 << SDM_OP_GEN_AGG_VECT_IDX_VALID_SHIFT; 18050 18051 BLOGD(sc, DBG_LOAD, "sending FW Final cleanup\n"); 18052 REG_WR(sc, XSDM_REG_OPERATION_GEN, op_gen_command); 18053 18054 if (bxe_flr_clnup_reg_poll(sc, comp_addr, 1, poll_cnt) != 1) { 18055 BLOGE(sc, "FW final cleanup did not succeed\n"); 18056 BLOGD(sc, DBG_LOAD, "At timeout completion address contained %x\n", 18057 (REG_RD(sc, comp_addr))); 18058 bxe_panic(sc, ("FLR cleanup failed\n")); 18059 return (1); 18060 } 18061 18062 /* Zero completion for nxt FLR */ 18063 REG_WR(sc, comp_addr, 0); 18064 18065 return (ret); 18066 } 18067 18068 static void 18069 bxe_pbf_pN_buf_flushed(struct bxe_softc *sc, 18070 struct pbf_pN_buf_regs *regs, 18071 uint32_t poll_count) 18072 { 18073 uint32_t init_crd, crd, crd_start, crd_freed, crd_freed_start; 18074 uint32_t cur_cnt = poll_count; 18075 18076 crd_freed = crd_freed_start = REG_RD(sc, regs->crd_freed); 18077 crd = crd_start = REG_RD(sc, regs->crd); 18078 init_crd = REG_RD(sc, regs->init_crd); 18079 18080 BLOGD(sc, DBG_LOAD, "INIT CREDIT[%d] : %x\n", regs->pN, init_crd); 18081 BLOGD(sc, DBG_LOAD, "CREDIT[%d] : s:%x\n", regs->pN, crd); 18082 BLOGD(sc, DBG_LOAD, "CREDIT_FREED[%d]: s:%x\n", regs->pN, crd_freed); 18083 18084 while ((crd != init_crd) && 18085 ((uint32_t)((int32_t)crd_freed - (int32_t)crd_freed_start) < 18086 (init_crd - crd_start))) { 18087 if (cur_cnt--) { 18088 DELAY(FLR_WAIT_INTERVAL); 18089 crd = REG_RD(sc, regs->crd); 18090 crd_freed = REG_RD(sc, regs->crd_freed); 18091 } else { 18092 BLOGD(sc, DBG_LOAD, "PBF tx buffer[%d] timed out\n", regs->pN); 18093 BLOGD(sc, DBG_LOAD, "CREDIT[%d] : c:%x\n", regs->pN, crd); 18094 BLOGD(sc, DBG_LOAD, "CREDIT_FREED[%d]: c:%x\n", regs->pN, crd_freed); 18095 break; 18096 } 18097 } 18098 18099 BLOGD(sc, DBG_LOAD, "Waited %d*%d usec for PBF tx buffer[%d]\n", 18100 poll_count-cur_cnt, FLR_WAIT_INTERVAL, regs->pN); 18101 } 18102 18103 static void 18104 bxe_pbf_pN_cmd_flushed(struct bxe_softc *sc, 18105 struct pbf_pN_cmd_regs *regs, 18106 uint32_t poll_count) 18107 { 18108 uint32_t occup, to_free, freed, freed_start; 18109 uint32_t cur_cnt = poll_count; 18110 18111 occup = to_free = REG_RD(sc, regs->lines_occup); 18112 freed = freed_start = REG_RD(sc, regs->lines_freed); 18113 18114 BLOGD(sc, DBG_LOAD, "OCCUPANCY[%d] : s:%x\n", regs->pN, occup); 18115 BLOGD(sc, DBG_LOAD, "LINES_FREED[%d] : s:%x\n", regs->pN, freed); 18116 18117 while (occup && 18118 ((uint32_t)((int32_t)freed - (int32_t)freed_start) < to_free)) { 18119 if (cur_cnt--) { 18120 DELAY(FLR_WAIT_INTERVAL); 18121 occup = REG_RD(sc, regs->lines_occup); 18122 freed = REG_RD(sc, regs->lines_freed); 18123 } else { 18124 BLOGD(sc, DBG_LOAD, "PBF cmd queue[%d] timed out\n", regs->pN); 18125 BLOGD(sc, DBG_LOAD, "OCCUPANCY[%d] : s:%x\n", regs->pN, occup); 18126 BLOGD(sc, DBG_LOAD, "LINES_FREED[%d] : s:%x\n", regs->pN, freed); 18127 break; 18128 } 18129 } 18130 18131 BLOGD(sc, DBG_LOAD, "Waited %d*%d usec for PBF cmd queue[%d]\n", 18132 poll_count - cur_cnt, FLR_WAIT_INTERVAL, regs->pN); 18133 } 18134 18135 static void 18136 bxe_tx_hw_flushed(struct bxe_softc *sc, uint32_t poll_count) 18137 { 18138 struct pbf_pN_cmd_regs cmd_regs[] = { 18139 {0, (CHIP_IS_E3B0(sc)) ? 18140 PBF_REG_TQ_OCCUPANCY_Q0 : 18141 PBF_REG_P0_TQ_OCCUPANCY, 18142 (CHIP_IS_E3B0(sc)) ? 18143 PBF_REG_TQ_LINES_FREED_CNT_Q0 : 18144 PBF_REG_P0_TQ_LINES_FREED_CNT}, 18145 {1, (CHIP_IS_E3B0(sc)) ? 18146 PBF_REG_TQ_OCCUPANCY_Q1 : 18147 PBF_REG_P1_TQ_OCCUPANCY, 18148 (CHIP_IS_E3B0(sc)) ? 18149 PBF_REG_TQ_LINES_FREED_CNT_Q1 : 18150 PBF_REG_P1_TQ_LINES_FREED_CNT}, 18151 {4, (CHIP_IS_E3B0(sc)) ? 18152 PBF_REG_TQ_OCCUPANCY_LB_Q : 18153 PBF_REG_P4_TQ_OCCUPANCY, 18154 (CHIP_IS_E3B0(sc)) ? 18155 PBF_REG_TQ_LINES_FREED_CNT_LB_Q : 18156 PBF_REG_P4_TQ_LINES_FREED_CNT} 18157 }; 18158 18159 struct pbf_pN_buf_regs buf_regs[] = { 18160 {0, (CHIP_IS_E3B0(sc)) ? 18161 PBF_REG_INIT_CRD_Q0 : 18162 PBF_REG_P0_INIT_CRD , 18163 (CHIP_IS_E3B0(sc)) ? 18164 PBF_REG_CREDIT_Q0 : 18165 PBF_REG_P0_CREDIT, 18166 (CHIP_IS_E3B0(sc)) ? 18167 PBF_REG_INTERNAL_CRD_FREED_CNT_Q0 : 18168 PBF_REG_P0_INTERNAL_CRD_FREED_CNT}, 18169 {1, (CHIP_IS_E3B0(sc)) ? 18170 PBF_REG_INIT_CRD_Q1 : 18171 PBF_REG_P1_INIT_CRD, 18172 (CHIP_IS_E3B0(sc)) ? 18173 PBF_REG_CREDIT_Q1 : 18174 PBF_REG_P1_CREDIT, 18175 (CHIP_IS_E3B0(sc)) ? 18176 PBF_REG_INTERNAL_CRD_FREED_CNT_Q1 : 18177 PBF_REG_P1_INTERNAL_CRD_FREED_CNT}, 18178 {4, (CHIP_IS_E3B0(sc)) ? 18179 PBF_REG_INIT_CRD_LB_Q : 18180 PBF_REG_P4_INIT_CRD, 18181 (CHIP_IS_E3B0(sc)) ? 18182 PBF_REG_CREDIT_LB_Q : 18183 PBF_REG_P4_CREDIT, 18184 (CHIP_IS_E3B0(sc)) ? 18185 PBF_REG_INTERNAL_CRD_FREED_CNT_LB_Q : 18186 PBF_REG_P4_INTERNAL_CRD_FREED_CNT}, 18187 }; 18188 18189 int i; 18190 18191 /* Verify the command queues are flushed P0, P1, P4 */ 18192 for (i = 0; i < ARRAY_SIZE(cmd_regs); i++) { 18193 bxe_pbf_pN_cmd_flushed(sc, &cmd_regs[i], poll_count); 18194 } 18195 18196 /* Verify the transmission buffers are flushed P0, P1, P4 */ 18197 for (i = 0; i < ARRAY_SIZE(buf_regs); i++) { 18198 bxe_pbf_pN_buf_flushed(sc, &buf_regs[i], poll_count); 18199 } 18200 } 18201 18202 static void 18203 bxe_hw_enable_status(struct bxe_softc *sc) 18204 { 18205 uint32_t val; 18206 18207 val = REG_RD(sc, CFC_REG_WEAK_ENABLE_PF); 18208 BLOGD(sc, DBG_LOAD, "CFC_REG_WEAK_ENABLE_PF is 0x%x\n", val); 18209 18210 val = REG_RD(sc, PBF_REG_DISABLE_PF); 18211 BLOGD(sc, DBG_LOAD, "PBF_REG_DISABLE_PF is 0x%x\n", val); 18212 18213 val = REG_RD(sc, IGU_REG_PCI_PF_MSI_EN); 18214 BLOGD(sc, DBG_LOAD, "IGU_REG_PCI_PF_MSI_EN is 0x%x\n", val); 18215 18216 val = REG_RD(sc, IGU_REG_PCI_PF_MSIX_EN); 18217 BLOGD(sc, DBG_LOAD, "IGU_REG_PCI_PF_MSIX_EN is 0x%x\n", val); 18218 18219 val = REG_RD(sc, IGU_REG_PCI_PF_MSIX_FUNC_MASK); 18220 BLOGD(sc, DBG_LOAD, "IGU_REG_PCI_PF_MSIX_FUNC_MASK is 0x%x\n", val); 18221 18222 val = REG_RD(sc, PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR); 18223 BLOGD(sc, DBG_LOAD, "PGLUE_B_REG_SHADOW_BME_PF_7_0_CLR is 0x%x\n", val); 18224 18225 val = REG_RD(sc, PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR); 18226 BLOGD(sc, DBG_LOAD, "PGLUE_B_REG_FLR_REQUEST_PF_7_0_CLR is 0x%x\n", val); 18227 18228 val = REG_RD(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER); 18229 BLOGD(sc, DBG_LOAD, "PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER is 0x%x\n", val); 18230 } 18231 18232 static int 18233 bxe_pf_flr_clnup(struct bxe_softc *sc) 18234 { 18235 uint32_t poll_cnt = bxe_flr_clnup_poll_count(sc); 18236 18237 BLOGD(sc, DBG_LOAD, "Cleanup after FLR PF[%d]\n", SC_ABS_FUNC(sc)); 18238 18239 /* Re-enable PF target read access */ 18240 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_TARGET_READ, 1); 18241 18242 /* Poll HW usage counters */ 18243 BLOGD(sc, DBG_LOAD, "Polling usage counters\n"); 18244 if (bxe_poll_hw_usage_counters(sc, poll_cnt)) { 18245 return (-1); 18246 } 18247 18248 /* Zero the igu 'trailing edge' and 'leading edge' */ 18249 18250 /* Send the FW cleanup command */ 18251 if (bxe_send_final_clnup(sc, (uint8_t)SC_FUNC(sc), poll_cnt)) { 18252 return (-1); 18253 } 18254 18255 /* ATC cleanup */ 18256 18257 /* Verify TX hw is flushed */ 18258 bxe_tx_hw_flushed(sc, poll_cnt); 18259 18260 /* Wait 100ms (not adjusted according to platform) */ 18261 DELAY(100000); 18262 18263 /* Verify no pending pci transactions */ 18264 if (bxe_is_pcie_pending(sc)) { 18265 BLOGE(sc, "PCIE Transactions still pending\n"); 18266 } 18267 18268 /* Debug */ 18269 bxe_hw_enable_status(sc); 18270 18271 /* 18272 * Master enable - Due to WB DMAE writes performed before this 18273 * register is re-initialized as part of the regular function init 18274 */ 18275 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); 18276 18277 return (0); 18278 } 18279 18280 #if 0 18281 static void 18282 bxe_init_searcher(struct bxe_softc *sc) 18283 { 18284 int port = SC_PORT(sc); 18285 ecore_src_init_t2(sc, sc->t2, sc->t2_mapping, SRC_CONN_NUM); 18286 /* T1 hash bits value determines the T1 number of entries */ 18287 REG_WR(sc, SRC_REG_NUMBER_HASH_BITS0 + port*4, SRC_HASH_BITS); 18288 } 18289 #endif 18290 18291 static int 18292 bxe_init_hw_func(struct bxe_softc *sc) 18293 { 18294 int port = SC_PORT(sc); 18295 int func = SC_FUNC(sc); 18296 int init_phase = PHASE_PF0 + func; 18297 struct ecore_ilt *ilt = sc->ilt; 18298 uint16_t cdu_ilt_start; 18299 uint32_t addr, val; 18300 uint32_t main_mem_base, main_mem_size, main_mem_prty_clr; 18301 int i, main_mem_width, rc; 18302 18303 BLOGD(sc, DBG_LOAD, "starting func init for func %d\n", func); 18304 18305 /* FLR cleanup */ 18306 if (!CHIP_IS_E1x(sc)) { 18307 rc = bxe_pf_flr_clnup(sc); 18308 if (rc) { 18309 BLOGE(sc, "FLR cleanup failed!\n"); 18310 // XXX bxe_fw_dump(sc); 18311 // XXX bxe_idle_chk(sc); 18312 return (rc); 18313 } 18314 } 18315 18316 /* set MSI reconfigure capability */ 18317 if (sc->devinfo.int_block == INT_BLOCK_HC) { 18318 addr = (port ? HC_REG_CONFIG_1 : HC_REG_CONFIG_0); 18319 val = REG_RD(sc, addr); 18320 val |= HC_CONFIG_0_REG_MSI_ATTN_EN_0; 18321 REG_WR(sc, addr, val); 18322 } 18323 18324 ecore_init_block(sc, BLOCK_PXP, init_phase); 18325 ecore_init_block(sc, BLOCK_PXP2, init_phase); 18326 18327 ilt = sc->ilt; 18328 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start; 18329 18330 #if 0 18331 if (IS_SRIOV(sc)) { 18332 cdu_ilt_start += BXE_FIRST_VF_CID/ILT_PAGE_CIDS; 18333 } 18334 cdu_ilt_start = bxe_iov_init_ilt(sc, cdu_ilt_start); 18335 18336 #if (BXE_FIRST_VF_CID > 0) 18337 /* 18338 * If BXE_FIRST_VF_CID > 0 then the PF L2 cids precedes 18339 * those of the VFs, so start line should be reset 18340 */ 18341 cdu_ilt_start = ilt->clients[ILT_CLIENT_CDU].start; 18342 #endif 18343 #endif 18344 18345 for (i = 0; i < L2_ILT_LINES(sc); i++) { 18346 ilt->lines[cdu_ilt_start + i].page = sc->context[i].vcxt; 18347 ilt->lines[cdu_ilt_start + i].page_mapping = 18348 sc->context[i].vcxt_dma.paddr; 18349 ilt->lines[cdu_ilt_start + i].size = sc->context[i].size; 18350 } 18351 ecore_ilt_init_op(sc, INITOP_SET); 18352 18353 #if 0 18354 if (!CONFIGURE_NIC_MODE(sc)) { 18355 bxe_init_searcher(sc); 18356 REG_WR(sc, PRS_REG_NIC_MODE, 0); 18357 BLOGD(sc, DBG_LOAD, "NIC MODE disabled\n"); 18358 } else 18359 #endif 18360 { 18361 /* Set NIC mode */ 18362 REG_WR(sc, PRS_REG_NIC_MODE, 1); 18363 BLOGD(sc, DBG_LOAD, "NIC MODE configured\n"); 18364 } 18365 18366 if (!CHIP_IS_E1x(sc)) { 18367 uint32_t pf_conf = IGU_PF_CONF_FUNC_EN; 18368 18369 /* Turn on a single ISR mode in IGU if driver is going to use 18370 * INT#x or MSI 18371 */ 18372 if (sc->interrupt_mode != INTR_MODE_MSIX) { 18373 pf_conf |= IGU_PF_CONF_SINGLE_ISR_EN; 18374 } 18375 18376 /* 18377 * Timers workaround bug: function init part. 18378 * Need to wait 20msec after initializing ILT, 18379 * needed to make sure there are no requests in 18380 * one of the PXP internal queues with "old" ILT addresses 18381 */ 18382 DELAY(20000); 18383 18384 /* 18385 * Master enable - Due to WB DMAE writes performed before this 18386 * register is re-initialized as part of the regular function 18387 * init 18388 */ 18389 REG_WR(sc, PGLUE_B_REG_INTERNAL_PFID_ENABLE_MASTER, 1); 18390 /* Enable the function in IGU */ 18391 REG_WR(sc, IGU_REG_PF_CONFIGURATION, pf_conf); 18392 } 18393 18394 sc->dmae_ready = 1; 18395 18396 ecore_init_block(sc, BLOCK_PGLUE_B, init_phase); 18397 18398 if (!CHIP_IS_E1x(sc)) 18399 REG_WR(sc, PGLUE_B_REG_WAS_ERROR_PF_7_0_CLR, func); 18400 18401 ecore_init_block(sc, BLOCK_ATC, init_phase); 18402 ecore_init_block(sc, BLOCK_DMAE, init_phase); 18403 ecore_init_block(sc, BLOCK_NIG, init_phase); 18404 ecore_init_block(sc, BLOCK_SRC, init_phase); 18405 ecore_init_block(sc, BLOCK_MISC, init_phase); 18406 ecore_init_block(sc, BLOCK_TCM, init_phase); 18407 ecore_init_block(sc, BLOCK_UCM, init_phase); 18408 ecore_init_block(sc, BLOCK_CCM, init_phase); 18409 ecore_init_block(sc, BLOCK_XCM, init_phase); 18410 ecore_init_block(sc, BLOCK_TSEM, init_phase); 18411 ecore_init_block(sc, BLOCK_USEM, init_phase); 18412 ecore_init_block(sc, BLOCK_CSEM, init_phase); 18413 ecore_init_block(sc, BLOCK_XSEM, init_phase); 18414 18415 if (!CHIP_IS_E1x(sc)) 18416 REG_WR(sc, QM_REG_PF_EN, 1); 18417 18418 if (!CHIP_IS_E1x(sc)) { 18419 REG_WR(sc, TSEM_REG_VFPF_ERR_NUM, BXE_MAX_NUM_OF_VFS + func); 18420 REG_WR(sc, USEM_REG_VFPF_ERR_NUM, BXE_MAX_NUM_OF_VFS + func); 18421 REG_WR(sc, CSEM_REG_VFPF_ERR_NUM, BXE_MAX_NUM_OF_VFS + func); 18422 REG_WR(sc, XSEM_REG_VFPF_ERR_NUM, BXE_MAX_NUM_OF_VFS + func); 18423 } 18424 ecore_init_block(sc, BLOCK_QM, init_phase); 18425 18426 ecore_init_block(sc, BLOCK_TM, init_phase); 18427 ecore_init_block(sc, BLOCK_DORQ, init_phase); 18428 18429 bxe_iov_init_dq(sc); 18430 18431 ecore_init_block(sc, BLOCK_BRB1, init_phase); 18432 ecore_init_block(sc, BLOCK_PRS, init_phase); 18433 ecore_init_block(sc, BLOCK_TSDM, init_phase); 18434 ecore_init_block(sc, BLOCK_CSDM, init_phase); 18435 ecore_init_block(sc, BLOCK_USDM, init_phase); 18436 ecore_init_block(sc, BLOCK_XSDM, init_phase); 18437 ecore_init_block(sc, BLOCK_UPB, init_phase); 18438 ecore_init_block(sc, BLOCK_XPB, init_phase); 18439 ecore_init_block(sc, BLOCK_PBF, init_phase); 18440 if (!CHIP_IS_E1x(sc)) 18441 REG_WR(sc, PBF_REG_DISABLE_PF, 0); 18442 18443 ecore_init_block(sc, BLOCK_CDU, init_phase); 18444 18445 ecore_init_block(sc, BLOCK_CFC, init_phase); 18446 18447 if (!CHIP_IS_E1x(sc)) 18448 REG_WR(sc, CFC_REG_WEAK_ENABLE_PF, 1); 18449 18450 if (IS_MF(sc)) { 18451 REG_WR(sc, NIG_REG_LLH0_FUNC_EN + port*8, 1); 18452 REG_WR(sc, NIG_REG_LLH0_FUNC_VLAN_ID + port*8, OVLAN(sc)); 18453 } 18454 18455 ecore_init_block(sc, BLOCK_MISC_AEU, init_phase); 18456 18457 /* HC init per function */ 18458 if (sc->devinfo.int_block == INT_BLOCK_HC) { 18459 if (CHIP_IS_E1H(sc)) { 18460 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); 18461 18462 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port*8, 0); 18463 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port*8, 0); 18464 } 18465 ecore_init_block(sc, BLOCK_HC, init_phase); 18466 18467 } else { 18468 int num_segs, sb_idx, prod_offset; 18469 18470 REG_WR(sc, MISC_REG_AEU_GENERAL_ATTN_12 + func*4, 0); 18471 18472 if (!CHIP_IS_E1x(sc)) { 18473 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, 0); 18474 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, 0); 18475 } 18476 18477 ecore_init_block(sc, BLOCK_IGU, init_phase); 18478 18479 if (!CHIP_IS_E1x(sc)) { 18480 int dsb_idx = 0; 18481 /** 18482 * Producer memory: 18483 * E2 mode: address 0-135 match to the mapping memory; 18484 * 136 - PF0 default prod; 137 - PF1 default prod; 18485 * 138 - PF2 default prod; 139 - PF3 default prod; 18486 * 140 - PF0 attn prod; 141 - PF1 attn prod; 18487 * 142 - PF2 attn prod; 143 - PF3 attn prod; 18488 * 144-147 reserved. 18489 * 18490 * E1.5 mode - In backward compatible mode; 18491 * for non default SB; each even line in the memory 18492 * holds the U producer and each odd line hold 18493 * the C producer. The first 128 producers are for 18494 * NDSB (PF0 - 0-31; PF1 - 32-63 and so on). The last 20 18495 * producers are for the DSB for each PF. 18496 * Each PF has five segments: (the order inside each 18497 * segment is PF0; PF1; PF2; PF3) - 128-131 U prods; 18498 * 132-135 C prods; 136-139 X prods; 140-143 T prods; 18499 * 144-147 attn prods; 18500 */ 18501 /* non-default-status-blocks */ 18502 num_segs = CHIP_INT_MODE_IS_BC(sc) ? 18503 IGU_BC_NDSB_NUM_SEGS : IGU_NORM_NDSB_NUM_SEGS; 18504 for (sb_idx = 0; sb_idx < sc->igu_sb_cnt; sb_idx++) { 18505 prod_offset = (sc->igu_base_sb + sb_idx) * 18506 num_segs; 18507 18508 for (i = 0; i < num_segs; i++) { 18509 addr = IGU_REG_PROD_CONS_MEMORY + 18510 (prod_offset + i) * 4; 18511 REG_WR(sc, addr, 0); 18512 } 18513 /* send consumer update with value 0 */ 18514 bxe_ack_sb(sc, sc->igu_base_sb + sb_idx, 18515 USTORM_ID, 0, IGU_INT_NOP, 1); 18516 bxe_igu_clear_sb(sc, sc->igu_base_sb + sb_idx); 18517 } 18518 18519 /* default-status-blocks */ 18520 num_segs = CHIP_INT_MODE_IS_BC(sc) ? 18521 IGU_BC_DSB_NUM_SEGS : IGU_NORM_DSB_NUM_SEGS; 18522 18523 if (CHIP_IS_MODE_4_PORT(sc)) 18524 dsb_idx = SC_FUNC(sc); 18525 else 18526 dsb_idx = SC_VN(sc); 18527 18528 prod_offset = (CHIP_INT_MODE_IS_BC(sc) ? 18529 IGU_BC_BASE_DSB_PROD + dsb_idx : 18530 IGU_NORM_BASE_DSB_PROD + dsb_idx); 18531 18532 /* 18533 * igu prods come in chunks of E1HVN_MAX (4) - 18534 * does not matters what is the current chip mode 18535 */ 18536 for (i = 0; i < (num_segs * E1HVN_MAX); 18537 i += E1HVN_MAX) { 18538 addr = IGU_REG_PROD_CONS_MEMORY + 18539 (prod_offset + i)*4; 18540 REG_WR(sc, addr, 0); 18541 } 18542 /* send consumer update with 0 */ 18543 if (CHIP_INT_MODE_IS_BC(sc)) { 18544 bxe_ack_sb(sc, sc->igu_dsb_id, 18545 USTORM_ID, 0, IGU_INT_NOP, 1); 18546 bxe_ack_sb(sc, sc->igu_dsb_id, 18547 CSTORM_ID, 0, IGU_INT_NOP, 1); 18548 bxe_ack_sb(sc, sc->igu_dsb_id, 18549 XSTORM_ID, 0, IGU_INT_NOP, 1); 18550 bxe_ack_sb(sc, sc->igu_dsb_id, 18551 TSTORM_ID, 0, IGU_INT_NOP, 1); 18552 bxe_ack_sb(sc, sc->igu_dsb_id, 18553 ATTENTION_ID, 0, IGU_INT_NOP, 1); 18554 } else { 18555 bxe_ack_sb(sc, sc->igu_dsb_id, 18556 USTORM_ID, 0, IGU_INT_NOP, 1); 18557 bxe_ack_sb(sc, sc->igu_dsb_id, 18558 ATTENTION_ID, 0, IGU_INT_NOP, 1); 18559 } 18560 bxe_igu_clear_sb(sc, sc->igu_dsb_id); 18561 18562 /* !!! these should become driver const once 18563 rf-tool supports split-68 const */ 18564 REG_WR(sc, IGU_REG_SB_INT_BEFORE_MASK_LSB, 0); 18565 REG_WR(sc, IGU_REG_SB_INT_BEFORE_MASK_MSB, 0); 18566 REG_WR(sc, IGU_REG_SB_MASK_LSB, 0); 18567 REG_WR(sc, IGU_REG_SB_MASK_MSB, 0); 18568 REG_WR(sc, IGU_REG_PBA_STATUS_LSB, 0); 18569 REG_WR(sc, IGU_REG_PBA_STATUS_MSB, 0); 18570 } 18571 } 18572 18573 /* Reset PCIE errors for debug */ 18574 REG_WR(sc, 0x2114, 0xffffffff); 18575 REG_WR(sc, 0x2120, 0xffffffff); 18576 18577 if (CHIP_IS_E1x(sc)) { 18578 main_mem_size = HC_REG_MAIN_MEMORY_SIZE / 2; /*dwords*/ 18579 main_mem_base = HC_REG_MAIN_MEMORY + 18580 SC_PORT(sc) * (main_mem_size * 4); 18581 main_mem_prty_clr = HC_REG_HC_PRTY_STS_CLR; 18582 main_mem_width = 8; 18583 18584 val = REG_RD(sc, main_mem_prty_clr); 18585 if (val) { 18586 BLOGD(sc, DBG_LOAD, 18587 "Parity errors in HC block during function init (0x%x)!\n", 18588 val); 18589 } 18590 18591 /* Clear "false" parity errors in MSI-X table */ 18592 for (i = main_mem_base; 18593 i < main_mem_base + main_mem_size * 4; 18594 i += main_mem_width) { 18595 bxe_read_dmae(sc, i, main_mem_width / 4); 18596 bxe_write_dmae(sc, BXE_SP_MAPPING(sc, wb_data), 18597 i, main_mem_width / 4); 18598 } 18599 /* Clear HC parity attention */ 18600 REG_RD(sc, main_mem_prty_clr); 18601 } 18602 18603 #if 1 18604 /* Enable STORMs SP logging */ 18605 REG_WR8(sc, BAR_USTRORM_INTMEM + 18606 USTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1); 18607 REG_WR8(sc, BAR_TSTRORM_INTMEM + 18608 TSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1); 18609 REG_WR8(sc, BAR_CSTRORM_INTMEM + 18610 CSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1); 18611 REG_WR8(sc, BAR_XSTRORM_INTMEM + 18612 XSTORM_RECORD_SLOW_PATH_OFFSET(SC_FUNC(sc)), 1); 18613 #endif 18614 18615 elink_phy_probe(&sc->link_params); 18616 18617 return (0); 18618 } 18619 18620 static void 18621 bxe_link_reset(struct bxe_softc *sc) 18622 { 18623 if (!BXE_NOMCP(sc)) { 18624 BXE_PHY_LOCK(sc); 18625 elink_lfa_reset(&sc->link_params, &sc->link_vars); 18626 BXE_PHY_UNLOCK(sc); 18627 } else { 18628 if (!CHIP_REV_IS_SLOW(sc)) { 18629 BLOGW(sc, "Bootcode is missing - cannot reset link\n"); 18630 } 18631 } 18632 } 18633 18634 static void 18635 bxe_reset_port(struct bxe_softc *sc) 18636 { 18637 int port = SC_PORT(sc); 18638 uint32_t val; 18639 18640 /* reset physical Link */ 18641 bxe_link_reset(sc); 18642 18643 REG_WR(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port*4, 0); 18644 18645 /* Do not rcv packets to BRB */ 18646 REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK + port*4, 0x0); 18647 /* Do not direct rcv packets that are not for MCP to the BRB */ 18648 REG_WR(sc, (port ? NIG_REG_LLH1_BRB1_NOT_MCP : 18649 NIG_REG_LLH0_BRB1_NOT_MCP), 0x0); 18650 18651 /* Configure AEU */ 18652 REG_WR(sc, MISC_REG_AEU_MASK_ATTN_FUNC_0 + port*4, 0); 18653 18654 DELAY(100000); 18655 18656 /* Check for BRB port occupancy */ 18657 val = REG_RD(sc, BRB1_REG_PORT_NUM_OCC_BLOCKS_0 + port*4); 18658 if (val) { 18659 BLOGD(sc, DBG_LOAD, 18660 "BRB1 is not empty, %d blocks are occupied\n", val); 18661 } 18662 18663 /* TODO: Close Doorbell port? */ 18664 } 18665 18666 static void 18667 bxe_ilt_wr(struct bxe_softc *sc, 18668 uint32_t index, 18669 bus_addr_t addr) 18670 { 18671 int reg; 18672 uint32_t wb_write[2]; 18673 18674 if (CHIP_IS_E1(sc)) { 18675 reg = PXP2_REG_RQ_ONCHIP_AT + index*8; 18676 } else { 18677 reg = PXP2_REG_RQ_ONCHIP_AT_B0 + index*8; 18678 } 18679 18680 wb_write[0] = ONCHIP_ADDR1(addr); 18681 wb_write[1] = ONCHIP_ADDR2(addr); 18682 REG_WR_DMAE(sc, reg, wb_write, 2); 18683 } 18684 18685 static void 18686 bxe_clear_func_ilt(struct bxe_softc *sc, 18687 uint32_t func) 18688 { 18689 uint32_t i, base = FUNC_ILT_BASE(func); 18690 for (i = base; i < base + ILT_PER_FUNC; i++) { 18691 bxe_ilt_wr(sc, i, 0); 18692 } 18693 } 18694 18695 static void 18696 bxe_reset_func(struct bxe_softc *sc) 18697 { 18698 struct bxe_fastpath *fp; 18699 int port = SC_PORT(sc); 18700 int func = SC_FUNC(sc); 18701 int i; 18702 18703 /* Disable the function in the FW */ 18704 REG_WR8(sc, BAR_XSTRORM_INTMEM + XSTORM_FUNC_EN_OFFSET(func), 0); 18705 REG_WR8(sc, BAR_CSTRORM_INTMEM + CSTORM_FUNC_EN_OFFSET(func), 0); 18706 REG_WR8(sc, BAR_TSTRORM_INTMEM + TSTORM_FUNC_EN_OFFSET(func), 0); 18707 REG_WR8(sc, BAR_USTRORM_INTMEM + USTORM_FUNC_EN_OFFSET(func), 0); 18708 18709 /* FP SBs */ 18710 FOR_EACH_ETH_QUEUE(sc, i) { 18711 fp = &sc->fp[i]; 18712 REG_WR8(sc, BAR_CSTRORM_INTMEM + 18713 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET(fp->fw_sb_id), 18714 SB_DISABLED); 18715 } 18716 18717 #if 0 18718 if (CNIC_LOADED(sc)) { 18719 /* CNIC SB */ 18720 REG_WR8(sc, BAR_CSTRORM_INTMEM + 18721 CSTORM_STATUS_BLOCK_DATA_STATE_OFFSET 18722 (bxe_cnic_fw_sb_id(sc)), SB_DISABLED); 18723 } 18724 #endif 18725 18726 /* SP SB */ 18727 REG_WR8(sc, BAR_CSTRORM_INTMEM + 18728 CSTORM_SP_STATUS_BLOCK_DATA_STATE_OFFSET(func), 18729 SB_DISABLED); 18730 18731 for (i = 0; i < XSTORM_SPQ_DATA_SIZE / 4; i++) { 18732 REG_WR(sc, BAR_XSTRORM_INTMEM + XSTORM_SPQ_DATA_OFFSET(func), 0); 18733 } 18734 18735 /* Configure IGU */ 18736 if (sc->devinfo.int_block == INT_BLOCK_HC) { 18737 REG_WR(sc, HC_REG_LEADING_EDGE_0 + port*8, 0); 18738 REG_WR(sc, HC_REG_TRAILING_EDGE_0 + port*8, 0); 18739 } else { 18740 REG_WR(sc, IGU_REG_LEADING_EDGE_LATCH, 0); 18741 REG_WR(sc, IGU_REG_TRAILING_EDGE_LATCH, 0); 18742 } 18743 18744 if (CNIC_LOADED(sc)) { 18745 /* Disable Timer scan */ 18746 REG_WR(sc, TM_REG_EN_LINEAR0_TIMER + port*4, 0); 18747 /* 18748 * Wait for at least 10ms and up to 2 second for the timers 18749 * scan to complete 18750 */ 18751 for (i = 0; i < 200; i++) { 18752 DELAY(10000); 18753 if (!REG_RD(sc, TM_REG_LIN0_SCAN_ON + port*4)) 18754 break; 18755 } 18756 } 18757 18758 /* Clear ILT */ 18759 bxe_clear_func_ilt(sc, func); 18760 18761 /* 18762 * Timers workaround bug for E2: if this is vnic-3, 18763 * we need to set the entire ilt range for this timers. 18764 */ 18765 if (!CHIP_IS_E1x(sc) && SC_VN(sc) == 3) { 18766 struct ilt_client_info ilt_cli; 18767 /* use dummy TM client */ 18768 memset(&ilt_cli, 0, sizeof(struct ilt_client_info)); 18769 ilt_cli.start = 0; 18770 ilt_cli.end = ILT_NUM_PAGE_ENTRIES - 1; 18771 ilt_cli.client_num = ILT_CLIENT_TM; 18772 18773 ecore_ilt_boundry_init_op(sc, &ilt_cli, 0, INITOP_CLEAR); 18774 } 18775 18776 /* this assumes that reset_port() called before reset_func()*/ 18777 if (!CHIP_IS_E1x(sc)) { 18778 bxe_pf_disable(sc); 18779 } 18780 18781 sc->dmae_ready = 0; 18782 } 18783 18784 static int 18785 bxe_gunzip_init(struct bxe_softc *sc) 18786 { 18787 return (0); 18788 } 18789 18790 static void 18791 bxe_gunzip_end(struct bxe_softc *sc) 18792 { 18793 return; 18794 } 18795 18796 static int 18797 bxe_init_firmware(struct bxe_softc *sc) 18798 { 18799 if (CHIP_IS_E1(sc)) { 18800 ecore_init_e1_firmware(sc); 18801 sc->iro_array = e1_iro_arr; 18802 } else if (CHIP_IS_E1H(sc)) { 18803 ecore_init_e1h_firmware(sc); 18804 sc->iro_array = e1h_iro_arr; 18805 } else if (!CHIP_IS_E1x(sc)) { 18806 ecore_init_e2_firmware(sc); 18807 sc->iro_array = e2_iro_arr; 18808 } else { 18809 BLOGE(sc, "Unsupported chip revision\n"); 18810 return (-1); 18811 } 18812 18813 return (0); 18814 } 18815 18816 static void 18817 bxe_release_firmware(struct bxe_softc *sc) 18818 { 18819 /* Do nothing */ 18820 return; 18821 } 18822 18823 static int 18824 ecore_gunzip(struct bxe_softc *sc, 18825 const uint8_t *zbuf, 18826 int len) 18827 { 18828 /* XXX : Implement... */ 18829 BLOGD(sc, DBG_LOAD, "ECORE_GUNZIP NOT IMPLEMENTED\n"); 18830 return (FALSE); 18831 } 18832 18833 static void 18834 ecore_reg_wr_ind(struct bxe_softc *sc, 18835 uint32_t addr, 18836 uint32_t val) 18837 { 18838 bxe_reg_wr_ind(sc, addr, val); 18839 } 18840 18841 static void 18842 ecore_write_dmae_phys_len(struct bxe_softc *sc, 18843 bus_addr_t phys_addr, 18844 uint32_t addr, 18845 uint32_t len) 18846 { 18847 bxe_write_dmae_phys_len(sc, phys_addr, addr, len); 18848 } 18849 18850 void 18851 ecore_storm_memset_struct(struct bxe_softc *sc, 18852 uint32_t addr, 18853 size_t size, 18854 uint32_t *data) 18855 { 18856 uint8_t i; 18857 for (i = 0; i < size/4; i++) { 18858 REG_WR(sc, addr + (i * 4), data[i]); 18859 } 18860 } 18861 18862