1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2009-2010 Weongyo Jeong <weongyo@freebsd.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer, 12 * without modification. 13 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 14 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 15 * redistribution must be conditioned upon including a substantially 16 * similar Disclaimer requirement for further binary redistribution. 17 * 18 * NO WARRANTY 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 21 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 22 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 23 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 24 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 27 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 29 * THE POSSIBILITY OF SUCH DAMAGES. 30 * 31 * $FreeBSD$ 32 */ 33 34 #ifndef _IF_BWNVAR_H 35 #define _IF_BWNVAR_H 36 37 struct siba_dev_softc; 38 struct bwn_softc; 39 struct bwn_mac; 40 41 #define N(a) (sizeof(a) / sizeof(a[0])) 42 #define BWN_ALIGN 0x1000 43 #define BWN_BUS_SPACE_MAXADDR_30BIT 0x3fffffff 44 #define BWN_RETRY_SHORT 7 45 #define BWN_RETRY_LONG 4 46 #define BWN_STAID_MAX 64 47 #define BWN_TXPWR_IGNORE_TIME (1 << 0) 48 #define BWN_TXPWR_IGNORE_TSSI (1 << 1) 49 #define BWN_HAS_TXMAG(phy) \ 50 (((phy)->rev >= 2) && ((phy)->rf_ver == 0x2050) && \ 51 ((phy)->rf_rev == 8)) 52 #define BWN_HAS_LOOPBACK(phy) \ 53 (((phy)->rev > 1) || ((phy)->gmode)) 54 #define BWN_TXERROR_MAX 1000 55 #define BWN_GETTIME(v) do { \ 56 struct timespec ts; \ 57 nanouptime(&ts); \ 58 (v) = ts.tv_nsec / 1000000 + ts.tv_sec * 1000; \ 59 } while (0) 60 #define BWN_ISOLDFMT(mac) ((mac)->mac_fw.rev <= 351) 61 #define BWN_TSSI2DBM(num, den) \ 62 ((int32_t)((num < 0) ? num / den : (num + den / 2) / den)) 63 #define BWN_HDRSIZE(mac) bwn_tx_hdrsize(mac) 64 #define BWN_MAXTXHDRSIZE (112 + (sizeof(struct bwn_plcp6))) 65 66 #define BWN_PIO_COOKIE(tq, tp) \ 67 ((uint16_t)((((uint16_t)tq->tq_index + 1) << 12) | tp->tp_index)) 68 #define BWN_DMA_COOKIE(dr, slot) \ 69 ((uint16_t)(((uint16_t)dr->dr_index + 1) << 12) | (uint16_t)slot) 70 #define BWN_READ_2(mac, o) (siba_read_2(mac->mac_sc->sc_dev, o)) 71 #define BWN_READ_4(mac, o) (siba_read_4(mac->mac_sc->sc_dev, o)) 72 #define BWN_WRITE_2(mac, o, v) \ 73 (siba_write_2(mac->mac_sc->sc_dev, o, v)) 74 #define BWN_WRITE_2_F(mac, o, v) do { \ 75 (BWN_WRITE_2(mac, o, v)); \ 76 BWN_READ_2(mac, o); \ 77 } while(0) 78 #define BWN_WRITE_SETMASK2(mac, offset, mask, set) \ 79 BWN_WRITE_2(mac, offset, (BWN_READ_2(mac, offset) & mask) | set) 80 #define BWN_WRITE_4(mac, o, v) \ 81 (siba_write_4(mac->mac_sc->sc_dev, o, v)) 82 #define BWN_WRITE_SETMASK4(mac, offset, mask, set) \ 83 BWN_WRITE_4(mac, offset, (BWN_READ_4(mac, offset) & mask) | set) 84 #define BWN_PIO_TXQOFFSET(mac) \ 85 ((siba_get_revid(mac->mac_sc->sc_dev) >= 11) ? 0x18 : 0) 86 #define BWN_PIO_RXQOFFSET(mac) \ 87 ((siba_get_revid(mac->mac_sc->sc_dev) >= 11) ? 0x38 : 8) 88 #define BWN_SEC_NEWAPI(mac) (mac->mac_fw.rev >= 351) 89 #define BWN_SEC_KEY2FW(mac, idx) \ 90 (BWN_SEC_NEWAPI(mac) ? idx : ((idx >= 4) ? idx - 4 : idx)) 91 #define BWN_RF_READ(mac, r) (mac->mac_phy.rf_read(mac, r)) 92 #define BWN_RF_WRITE(mac, r, v) (mac->mac_phy.rf_write(mac, r, v)) 93 #define BWN_RF_MASK(mac, o, m) \ 94 BWN_RF_WRITE(mac, o, BWN_RF_READ(mac, o) & m) 95 #define BWN_RF_SETMASK(mac, offset, mask, set) \ 96 BWN_RF_WRITE(mac, offset, (BWN_RF_READ(mac, offset) & mask) | set) 97 #define BWN_RF_SET(mac, offset, set) \ 98 BWN_RF_WRITE(mac, offset, BWN_RF_READ(mac, offset) | set) 99 #define BWN_PHY_READ(mac, r) (mac->mac_phy.phy_read(mac, r)) 100 #define BWN_PHY_WRITE(mac, r, v) \ 101 (mac->mac_phy.phy_write(mac, r, v)) 102 #define BWN_PHY_SET(mac, offset, set) do { \ 103 if (mac->mac_phy.phy_maskset != NULL) { \ 104 KASSERT(mac->mac_status < BWN_MAC_STATUS_INITED || \ 105 mac->mac_suspended > 0, \ 106 ("dont access PHY or RF registers after turning on MAC")); \ 107 mac->mac_phy.phy_maskset(mac, offset, 0xffff, set); \ 108 } else \ 109 BWN_PHY_WRITE(mac, offset, \ 110 BWN_PHY_READ(mac, offset) | (set)); \ 111 } while (0) 112 #define BWN_PHY_SETMASK(mac, offset, mask, set) do { \ 113 if (mac->mac_phy.phy_maskset != NULL) { \ 114 KASSERT(mac->mac_status < BWN_MAC_STATUS_INITED || \ 115 mac->mac_suspended > 0, \ 116 ("dont access PHY or RF registers after turning on MAC")); \ 117 mac->mac_phy.phy_maskset(mac, offset, mask, set); \ 118 } else \ 119 BWN_PHY_WRITE(mac, offset, \ 120 (BWN_PHY_READ(mac, offset) & (mask)) | (set)); \ 121 } while (0) 122 #define BWN_PHY_MASK(mac, offset, mask) do { \ 123 if (mac->mac_phy.phy_maskset != NULL) { \ 124 KASSERT(mac->mac_status < BWN_MAC_STATUS_INITED || \ 125 mac->mac_suspended > 0, \ 126 ("dont access PHY or RF registers after turning on MAC")); \ 127 mac->mac_phy.phy_maskset(mac, offset, mask, 0); \ 128 } else \ 129 BWN_PHY_WRITE(mac, offset, \ 130 BWN_PHY_READ(mac, offset) & mask); \ 131 } while (0) 132 #define BWN_PHY_COPY(mac, dst, src) do { \ 133 KASSERT(mac->mac_status < BWN_MAC_STATUS_INITED || \ 134 mac->mac_suspended > 0, \ 135 ("dont access PHY or RF registers after turning on MAC")); \ 136 BWN_PHY_WRITE(mac, dst, BWN_PHY_READ(mac, src)); \ 137 } while (0) 138 #define BWN_LO_CALIB_EXPIRE (1000 * (30 - 2)) 139 #define BWN_LO_PWRVEC_EXPIRE (1000 * (30 - 2)) 140 #define BWN_LO_TXCTL_EXPIRE (1000 * (180 - 4)) 141 #define BWN_DMA_BIT_MASK(n) (((n) == 64) ? ~0ULL : ((1ULL<<(n))-1)) 142 #define BWN_LPD(L, P, D) (((L) << 2) | ((P) << 1) | ((D) << 0)) 143 #define BWN_BITREV4(tmp) (BWN_BITREV8(tmp) >> 4) 144 #define BWN_BITREV8(byte) (bwn_bitrev_table[byte]) 145 #define BWN_BBATTCMP(a, b) ((a)->att == (b)->att) 146 #define BWN_RFATTCMP(a, b) \ 147 (((a)->att == (b)->att) && ((a)->padmix == (b)->padmix)) 148 #define BWN_PIO_WRITE_2(mac, tq, offset, value) \ 149 BWN_WRITE_2(mac, (tq)->tq_base + offset, value) 150 #define BWN_PIO_READ_4(mac, tq, offset) \ 151 BWN_READ_4(mac, tq->tq_base + offset) 152 #define BWN_ISCCKRATE(rate) \ 153 (rate == BWN_CCK_RATE_1MB || rate == BWN_CCK_RATE_2MB || \ 154 rate == BWN_CCK_RATE_5MB || rate == BWN_CCK_RATE_11MB) 155 #define BWN_ISOFDMRATE(rate) (!BWN_ISCCKRATE(rate)) 156 #define BWN_BARRIER(mac, flags) siba_barrier(mac->mac_sc->sc_dev, flags) 157 #define BWN_DMA_READ(dr, offset) \ 158 (BWN_READ_4(dr->dr_mac, dr->dr_base + offset)) 159 #define BWN_DMA_WRITE(dr, offset, value) \ 160 (BWN_WRITE_4(dr->dr_mac, dr->dr_base + offset, value)) 161 162 163 typedef enum { 164 BWN_PHY_BAND_2G = 0, 165 BWN_PHY_BAND_5G_LO = 1, 166 BWN_PHY_BAND_5G_MI = 2, 167 BWN_PHY_BAND_5G_HI = 3 168 } bwn_phy_band_t; 169 170 typedef enum { 171 BWN_BAND_2G, 172 BWN_BAND_5G, 173 } bwn_band_t; 174 175 typedef enum { 176 BWN_CHAN_TYPE_20, 177 BWN_CHAN_TYPE_20_HT, 178 BWN_CHAN_TYPE_40_HT_U, 179 BWN_CHAN_TYPE_40_HT_D, 180 } bwn_chan_type_t; 181 182 struct bwn_rate { 183 uint16_t rateid; 184 uint32_t flags; 185 }; 186 187 #define BWN_ANT0 0 188 #define BWN_ANT1 1 189 #define BWN_ANTAUTO0 2 190 #define BWN_ANTAUTO1 3 191 #define BWN_ANT2 4 192 #define BWN_ANT3 8 193 #define BWN_ANTAUTO BWN_ANTAUTO0 194 #define BWN_ANT_DEFAULT BWN_ANTAUTO 195 #define BWN_TX_SLOTS_PER_FRAME 2 196 197 struct bwn_channel { 198 unsigned freq; 199 unsigned ieee; 200 unsigned maxTxPow; 201 }; 202 203 struct bwn_channelinfo { 204 struct bwn_channel channels[IEEE80211_CHAN_MAX]; 205 unsigned nchannels; 206 }; 207 208 struct bwn_bbatt { 209 uint8_t att; 210 }; 211 212 struct bwn_bbatt_list { 213 const struct bwn_bbatt *array; 214 uint8_t len; 215 uint8_t min; 216 uint8_t max; 217 }; 218 219 struct bwn_rfatt { 220 uint8_t att; 221 int padmix; 222 }; 223 224 struct bwn_rfatt_list { 225 const struct bwn_rfatt *array; 226 uint8_t len; 227 uint8_t min; 228 uint8_t max; 229 }; 230 231 #define BWN_DC_LT_SIZE 32 232 233 struct bwn_loctl { 234 int8_t i; 235 int8_t q; 236 }; 237 238 typedef enum { 239 BWN_TXPWR_RES_NEED_ADJUST, 240 BWN_TXPWR_RES_DONE, 241 } bwn_txpwr_result_t; 242 243 struct bwn_lo_calib { 244 struct bwn_bbatt bbatt; 245 struct bwn_rfatt rfatt; 246 struct bwn_loctl ctl; 247 unsigned long calib_time; 248 TAILQ_ENTRY(bwn_lo_calib) list; 249 }; 250 251 struct bwn_rxhdr4 { 252 uint16_t frame_len; 253 uint8_t pad1[2]; 254 uint16_t phy_status0; 255 union { 256 struct { 257 uint8_t rssi; 258 uint8_t sig_qual; 259 } __packed abg; 260 struct { 261 int8_t power0; 262 int8_t power1; 263 } __packed n; 264 } __packed phy; 265 union { 266 struct { 267 int8_t power2; 268 uint8_t pad; 269 } __packed n; 270 struct { 271 uint8_t pad; 272 int8_t ht_power0; 273 } __packed ht; 274 uint16_t phy_status2; 275 } __packed ps2; 276 union { 277 struct { 278 uint16_t phy_status3; 279 } __packed lp; 280 struct { 281 int8_t phy_ht_power1; 282 int8_t phy_ht_power2; 283 } __packed ht; 284 } __packed ps3; 285 union { 286 struct { 287 uint32_t mac_status; 288 uint16_t mac_time; 289 uint16_t channel; 290 } __packed r351; 291 struct { 292 uint16_t phy_status4; 293 uint16_t phy_status5; 294 uint32_t mac_status; 295 uint16_t mac_time; 296 uint16_t channel; 297 } __packed r598; 298 } __packed ps4; 299 } __packed; 300 301 struct bwn_txstatus { 302 uint16_t cookie; 303 uint16_t seq; 304 uint8_t phy_stat; 305 uint8_t framecnt; 306 uint8_t rtscnt; 307 uint8_t sreason; 308 uint8_t pm; 309 uint8_t im; 310 uint8_t ampdu; 311 uint8_t ack; 312 }; 313 314 #define BWN_TXCTL_PA3DB 0x40 315 #define BWN_TXCTL_PA2DB 0x20 316 #define BWN_TXCTL_TXMIX 0x10 317 318 struct bwn_txpwr_loctl { 319 struct bwn_rfatt_list rfatt; 320 struct bwn_bbatt_list bbatt; 321 uint16_t dc_lt[BWN_DC_LT_SIZE]; 322 TAILQ_HEAD(, bwn_lo_calib) calib_list; 323 unsigned long pwr_vec_read_time; 324 unsigned long txctl_measured_time; 325 uint8_t tx_bias; 326 uint8_t tx_magn; 327 uint64_t power_vector; 328 }; 329 330 #define BWN_OFDMTAB_DIR_UNKNOWN 0 331 #define BWN_OFDMTAB_DIR_READ 1 332 #define BWN_OFDMTAB_DIR_WRITE 2 333 334 struct bwn_phy_g { 335 unsigned pg_flags; 336 #define BWN_PHY_G_FLAG_TSSITABLE_ALLOC (1 << 0) 337 #define BWN_PHY_G_FLAG_RADIOCTX_VALID (1 << 1) 338 int pg_aci_enable; 339 int pg_aci_wlan_automatic; 340 int pg_aci_hw_rssi; 341 int pg_rf_on; 342 uint16_t pg_radioctx_over; 343 uint16_t pg_radioctx_overval; 344 uint16_t pg_minlowsig[2]; 345 uint16_t pg_minlowsigpos[2]; 346 int8_t *pg_tssi2dbm; 347 int pg_idletssi; 348 int pg_curtssi; 349 uint8_t pg_avgtssi; 350 struct bwn_bbatt pg_bbatt; 351 struct bwn_rfatt pg_rfatt; 352 uint8_t pg_txctl; 353 int pg_bbatt_delta; 354 int pg_rfatt_delta; 355 356 struct bwn_txpwr_loctl pg_loctl; 357 int16_t pg_max_lb_gain; 358 int16_t pg_trsw_rx_gain; 359 int16_t pg_lna_lod_gain; 360 int16_t pg_lna_gain; 361 int16_t pg_pga_gain; 362 int pg_immode; 363 #define BWN_INTERFSTACK_SIZE 26 364 uint32_t pg_interfstack[BWN_INTERFSTACK_SIZE]; 365 366 int16_t pg_nrssi[2]; 367 int32_t pg_nrssi_slope; 368 int8_t pg_nrssi_lt[64]; 369 370 uint16_t pg_lofcal; 371 372 uint16_t pg_initval; 373 uint16_t pg_ofdmtab_addr; 374 unsigned pg_ofdmtab_dir; 375 }; 376 377 #define BWN_IMMODE_NONE 0 378 #define BWN_IMMODE_NONWLAN 1 379 #define BWN_IMMODE_MANUAL 2 380 #define BWN_IMMODE_AUTO 3 381 382 #define BWN_PHYLP_TXPCTL_UNKNOWN 0 383 #define BWN_PHYLP_TXPCTL_OFF 1 384 #define BWN_PHYLP_TXPCTL_ON_SW 2 385 #define BWN_PHYLP_TXPCTL_ON_HW 3 386 387 struct bwn_phy_lp { 388 uint8_t plp_chan; 389 uint8_t plp_chanfullcal; 390 int32_t plp_antenna; 391 uint8_t plp_txpctlmode; 392 uint8_t plp_txisoband_h; 393 uint8_t plp_txisoband_m; 394 uint8_t plp_txisoband_l; 395 uint8_t plp_rxpwroffset; 396 int8_t plp_txpwridx; 397 uint16_t plp_tssiidx; 398 uint16_t plp_tssinpt; 399 uint8_t plp_rssivf; 400 uint8_t plp_rssivc; 401 uint8_t plp_rssigs; 402 uint8_t plp_rccap; 403 uint8_t plp_bxarch; 404 uint8_t plp_crsusr_off; 405 uint8_t plp_crssys_off; 406 uint32_t plp_div; 407 int32_t plp_tonefreq; 408 uint16_t plp_digfilt[9]; 409 }; 410 411 /* for LP */ 412 struct bwn_txgain { 413 uint16_t tg_gm; 414 uint16_t tg_pga; 415 uint16_t tg_pad; 416 uint16_t tg_dac; 417 }; 418 419 struct bwn_rxcompco { 420 uint8_t rc_chan; 421 int8_t rc_c1; 422 int8_t rc_c0; 423 }; 424 425 struct bwn_phy_lp_iq_est { 426 uint32_t ie_iqprod; 427 uint32_t ie_ipwr; 428 uint32_t ie_qpwr; 429 }; 430 431 struct bwn_txgain_entry { 432 uint8_t te_gm; 433 uint8_t te_pga; 434 uint8_t te_pad; 435 uint8_t te_dac; 436 uint8_t te_bbmult; 437 }; 438 439 /* only for LP PHY */ 440 struct bwn_stxtable { 441 uint16_t st_phyoffset; 442 uint16_t st_physhift; 443 uint16_t st_rfaddr; 444 uint16_t st_rfshift; 445 uint16_t st_mask; 446 }; 447 448 struct bwn_b206x_chan { 449 uint8_t bc_chan; 450 uint16_t bc_freq; 451 const uint8_t *bc_data; 452 }; 453 454 struct bwn_b206x_rfinit_entry { 455 uint16_t br_offset; 456 uint16_t br_valuea; 457 uint16_t br_valueg; 458 uint8_t br_flags; 459 }; 460 461 struct bwn_phy_n; 462 463 struct bwn_phy { 464 uint8_t type; 465 uint8_t rev; 466 uint8_t analog; 467 468 int supports_2ghz; 469 int supports_5ghz; 470 471 int gmode; 472 struct bwn_phy_g phy_g; 473 struct bwn_phy_lp phy_lp; 474 475 /* 476 * I'd like the newer PHY code to not hide in the top-level 477 * structs.. 478 */ 479 struct bwn_phy_n *phy_n; 480 481 uint16_t rf_manuf; 482 uint16_t rf_ver; 483 uint8_t rf_rev; 484 int rf_on; 485 int phy_do_full_init; 486 487 int txpower; 488 int hwpctl; 489 unsigned long nexttime; 490 unsigned int chan; 491 int txerrors; 492 493 int (*attach)(struct bwn_mac *); 494 void (*detach)(struct bwn_mac *); 495 int (*prepare_hw)(struct bwn_mac *); 496 void (*init_pre)(struct bwn_mac *); 497 int (*init)(struct bwn_mac *); 498 void (*exit)(struct bwn_mac *); 499 uint16_t (*phy_read)(struct bwn_mac *, uint16_t); 500 void (*phy_write)(struct bwn_mac *, uint16_t, 501 uint16_t); 502 void (*phy_maskset)(struct bwn_mac *, 503 uint16_t, uint16_t, uint16_t); 504 uint16_t (*rf_read)(struct bwn_mac *, uint16_t); 505 void (*rf_write)(struct bwn_mac *, uint16_t, 506 uint16_t); 507 int (*use_hwpctl)(struct bwn_mac *); 508 void (*rf_onoff)(struct bwn_mac *, int); 509 void (*switch_analog)(struct bwn_mac *, int); 510 int (*switch_channel)(struct bwn_mac *, 511 unsigned int); 512 uint32_t (*get_default_chan)(struct bwn_mac *); 513 void (*set_antenna)(struct bwn_mac *, int); 514 int (*set_im)(struct bwn_mac *, int); 515 bwn_txpwr_result_t (*recalc_txpwr)(struct bwn_mac *, int); 516 void (*set_txpwr)(struct bwn_mac *); 517 void (*task_15s)(struct bwn_mac *); 518 void (*task_60s)(struct bwn_mac *); 519 }; 520 521 struct bwn_chan_band { 522 uint32_t flags; 523 uint8_t nchan; 524 #define BWN_MAX_CHAN_PER_BAND 14 525 uint8_t chan[BWN_MAX_CHAN_PER_BAND]; 526 }; 527 528 #define BWN_NR_WMEPARAMS 16 529 enum { 530 BWN_WMEPARAM_TXOP = 0, 531 BWN_WMEPARAM_CWMIN, 532 BWN_WMEPARAM_CWMAX, 533 BWN_WMEPARAM_CWCUR, 534 BWN_WMEPARAM_AIFS, 535 BWN_WMEPARAM_BSLOTS, 536 BWN_WMEPARAM_REGGAP, 537 BWN_WMEPARAM_STATUS, 538 }; 539 540 #define BWN_WME_PARAMS(queue) \ 541 (BWN_SHARED_EDCFQ + (BWN_NR_WMEPARAMS * sizeof(uint16_t) * (queue))) 542 #define BWN_WME_BACKGROUND BWN_WME_PARAMS(0) 543 #define BWN_WME_BESTEFFORT BWN_WME_PARAMS(1) 544 #define BWN_WME_VIDEO BWN_WME_PARAMS(2) 545 #define BWN_WME_VOICE BWN_WME_PARAMS(3) 546 547 /* 548 * Radio capture format. 549 */ 550 #define BWN_RX_RADIOTAP_PRESENT ( \ 551 (1 << IEEE80211_RADIOTAP_TSFT) | \ 552 (1 << IEEE80211_RADIOTAP_FLAGS) | \ 553 (1 << IEEE80211_RADIOTAP_RATE) | \ 554 (1 << IEEE80211_RADIOTAP_CHANNEL) | \ 555 (1 << IEEE80211_RADIOTAP_ANTENNA) | \ 556 (1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) | \ 557 (1 << IEEE80211_RADIOTAP_DBM_ANTNOISE) | \ 558 0) 559 560 struct bwn_rx_radiotap_header { 561 struct ieee80211_radiotap_header wr_ihdr; 562 uint64_t wr_tsf; 563 u_int8_t wr_flags; 564 u_int8_t wr_rate; 565 u_int16_t wr_chan_freq; 566 u_int16_t wr_chan_flags; 567 int8_t wr_antsignal; 568 int8_t wr_antnoise; 569 u_int8_t wr_antenna; 570 }; 571 572 #define BWN_TX_RADIOTAP_PRESENT ( \ 573 (1 << IEEE80211_RADIOTAP_FLAGS) | \ 574 (1 << IEEE80211_RADIOTAP_RATE) | \ 575 (1 << IEEE80211_RADIOTAP_CHANNEL) | \ 576 (1 << IEEE80211_RADIOTAP_DBM_TX_POWER) | \ 577 (1 << IEEE80211_RADIOTAP_ANTENNA) | \ 578 0) 579 580 struct bwn_tx_radiotap_header { 581 struct ieee80211_radiotap_header wt_ihdr; 582 u_int8_t wt_flags; 583 u_int8_t wt_rate; 584 u_int16_t wt_chan_freq; 585 u_int16_t wt_chan_flags; 586 u_int8_t wt_txpower; 587 u_int8_t wt_antenna; 588 }; 589 590 struct bwn_stats { 591 int32_t rtsfail; 592 int32_t rts; 593 int32_t link_noise; 594 }; 595 596 /* Noise Calculation (Link Quality) */ 597 struct bwn_noise { 598 uint8_t noi_running; 599 uint8_t noi_nsamples; 600 int8_t noi_samples[8][4]; 601 }; 602 603 #define BWN_DMA_30BIT 30 604 #define BWN_DMA_32BIT 32 605 #define BWN_DMA_64BIT 64 606 607 struct bwn_dmadesc_meta { 608 bus_dmamap_t mt_dmap; 609 bus_addr_t mt_paddr; 610 struct mbuf *mt_m; 611 struct ieee80211_node *mt_ni; 612 uint8_t mt_txtype; 613 #define BWN_DMADESC_METATYPE_HEADER 0 614 #define BWN_DMADESC_METATYPE_BODY 1 615 uint8_t mt_islast; 616 }; 617 618 #define BWN_DMAINTR_FATALMASK \ 619 ((1 << 10) | (1 << 11) | (1 << 12) | (1 << 14) | (1 << 15)) 620 #define BWN_DMAINTR_NONFATALMASK (1 << 13) 621 #define BWN_DMAINTR_RX_DONE (1 << 16) 622 623 #define BWN_DMA32_DCTL_BYTECNT 0x00001fff 624 #define BWN_DMA32_DCTL_ADDREXT_MASK 0x00030000 625 #define BWN_DMA32_DCTL_ADDREXT_SHIFT 16 626 #define BWN_DMA32_DCTL_DTABLEEND 0x10000000 627 #define BWN_DMA32_DCTL_IRQ 0x20000000 628 #define BWN_DMA32_DCTL_FRAMEEND 0x40000000 629 #define BWN_DMA32_DCTL_FRAMESTART 0x80000000 630 struct bwn_dmadesc32 { 631 uint32_t control; 632 uint32_t address; 633 } __packed; 634 635 #define BWN_DMA64_DCTL0_DTABLEEND 0x10000000 636 #define BWN_DMA64_DCTL0_IRQ 0x20000000 637 #define BWN_DMA64_DCTL0_FRAMEEND 0x40000000 638 #define BWN_DMA64_DCTL0_FRAMESTART 0x80000000 639 #define BWN_DMA64_DCTL1_BYTECNT 0x00001fff 640 #define BWN_DMA64_DCTL1_ADDREXT_MASK 0x00030000 641 #define BWN_DMA64_DCTL1_ADDREXT_SHIFT 16 642 struct bwn_dmadesc64 { 643 uint32_t control0; 644 uint32_t control1; 645 uint32_t address_low; 646 uint32_t address_high; 647 } __packed; 648 649 struct bwn_dmadesc_generic { 650 union { 651 struct bwn_dmadesc32 dma32; 652 struct bwn_dmadesc64 dma64; 653 } __packed dma; 654 } __packed; 655 656 struct bwn_dma_ring; 657 658 struct bwn_dma_ring { 659 struct bwn_mac *dr_mac; 660 const struct bwn_dma_ops *dr_ops; 661 struct bwn_dmadesc_meta *dr_meta; 662 void *dr_txhdr_cache; 663 bus_dma_tag_t dr_ring_dtag; 664 bus_dma_tag_t dr_txring_dtag; 665 bus_dmamap_t dr_spare_dmap; /* only for RX */ 666 bus_dmamap_t dr_ring_dmap; 667 bus_addr_t dr_txring_paddr; 668 void *dr_ring_descbase; 669 bus_addr_t dr_ring_dmabase; 670 int dr_numslots; 671 int dr_usedslot; 672 int dr_curslot; 673 uint32_t dr_frameoffset; 674 uint16_t dr_rx_bufsize; 675 uint16_t dr_base; 676 int dr_index; 677 uint8_t dr_tx; 678 uint8_t dr_stop; 679 int dr_type; 680 681 void (*getdesc)(struct bwn_dma_ring *, 682 int, struct bwn_dmadesc_generic **, 683 struct bwn_dmadesc_meta **); 684 void (*setdesc)(struct bwn_dma_ring *, 685 struct bwn_dmadesc_generic *, 686 bus_addr_t, uint16_t, int, int, 687 int); 688 void (*start_transfer)(struct bwn_dma_ring *, 689 int); 690 void (*suspend)(struct bwn_dma_ring *); 691 void (*resume)(struct bwn_dma_ring *); 692 int (*get_curslot)(struct bwn_dma_ring *); 693 void (*set_curslot)(struct bwn_dma_ring *, 694 int); 695 }; 696 697 struct bwn_dma { 698 int dmatype; 699 bus_dma_tag_t parent_dtag; 700 bus_dma_tag_t rxbuf_dtag; 701 bus_dma_tag_t txbuf_dtag; 702 703 struct bwn_dma_ring *wme[5]; 704 struct bwn_dma_ring *mcast; 705 struct bwn_dma_ring *rx; 706 uint64_t lastseq; /* XXX FIXME */ 707 }; 708 709 struct bwn_pio_rxqueue { 710 struct bwn_mac *prq_mac; 711 uint16_t prq_base; 712 uint8_t prq_rev; 713 }; 714 715 struct bwn_pio_txqueue; 716 struct bwn_pio_txpkt { 717 struct bwn_pio_txqueue *tp_queue; 718 struct ieee80211_node *tp_ni; 719 struct mbuf *tp_m; 720 uint8_t tp_index; 721 TAILQ_ENTRY(bwn_pio_txpkt) tp_list; 722 }; 723 724 #define BWN_PIO_MAX_TXPACKETS 32 725 struct bwn_pio_txqueue { 726 uint16_t tq_base; 727 uint16_t tq_size; 728 uint16_t tq_used; 729 uint16_t tq_free; 730 uint8_t tq_index; 731 struct bwn_pio_txpkt tq_pkts[BWN_PIO_MAX_TXPACKETS]; 732 TAILQ_HEAD(, bwn_pio_txpkt) tq_pktlist; 733 }; 734 735 struct bwn_pio { 736 struct bwn_pio_txqueue wme[5]; 737 struct bwn_pio_txqueue mcast; 738 struct bwn_pio_rxqueue rx; 739 }; 740 741 struct bwn_plcp4 { 742 union { 743 uint32_t data; 744 uint8_t raw[4]; 745 } __packed o; 746 } __packed; 747 748 struct bwn_plcp6 { 749 union { 750 uint32_t data; 751 uint8_t raw[6]; 752 } __packed o; 753 } __packed; 754 755 struct bwn_txhdr { 756 uint32_t macctl; 757 uint8_t macfc[2]; 758 uint16_t tx_festime; 759 uint16_t phyctl; 760 uint16_t phyctl_1; 761 uint16_t phyctl_1fb; 762 uint16_t phyctl_1rts; 763 uint16_t phyctl_1rtsfb; 764 uint8_t phyrate; 765 uint8_t phyrate_rts; 766 uint8_t eftypes; /* extra frame types */ 767 uint8_t chan; 768 uint8_t iv[16]; 769 uint8_t addr1[IEEE80211_ADDR_LEN]; 770 uint16_t tx_festime_fb; 771 struct bwn_plcp6 rts_plcp_fb; 772 uint16_t rts_dur_fb; 773 struct bwn_plcp6 plcp_fb; 774 uint16_t dur_fb; 775 uint16_t mimo_modelen; 776 uint16_t mimo_ratelen_fb; 777 uint32_t timeout; 778 779 union { 780 /* format <= r351 */ 781 struct { 782 uint8_t pad0[2]; 783 uint16_t cookie; 784 uint16_t tx_status; 785 struct bwn_plcp6 rts_plcp; 786 uint8_t rts_frame[16]; 787 uint8_t pad1[2]; 788 struct bwn_plcp6 plcp; 789 } __packed r351; 790 /* format > r410 < r598 */ 791 struct { 792 uint16_t mimo_antenna; 793 uint16_t preload_size; 794 uint8_t pad0[2]; 795 uint16_t cookie; 796 uint16_t tx_status; 797 struct bwn_plcp6 rts_plcp; 798 uint8_t rts_frame[16]; 799 uint8_t pad1[2]; 800 struct bwn_plcp6 plcp; 801 } __packed r410; 802 struct { 803 uint16_t mimo_antenna; 804 uint16_t preload_size; 805 uint8_t pad0[2]; 806 uint16_t cookie; 807 uint16_t tx_status; 808 uint16_t max_n_mpdus; 809 uint16_t max_a_bytes_mrt; 810 uint16_t max_a_bytes_fbr; 811 uint16_t min_m_bytes; 812 struct bwn_plcp6 rts_plcp; 813 uint8_t rts_frame[16]; 814 uint8_t pad1[2]; 815 struct bwn_plcp6 plcp; 816 } __packed r598; 817 } __packed body; 818 } __packed; 819 820 #define BWN_FWTYPE_UCODE 'u' 821 #define BWN_FWTYPE_PCM 'p' 822 #define BWN_FWTYPE_IV 'i' 823 struct bwn_fwhdr { 824 uint8_t type; 825 uint8_t ver; 826 uint8_t pad[2]; 827 uint32_t size; 828 } __packed; 829 830 #define BWN_FWINITVALS_OFFSET_MASK 0x7fff 831 #define BWN_FWINITVALS_32BIT 0x8000 832 struct bwn_fwinitvals { 833 uint16_t offset_size; 834 union { 835 uint16_t d16; 836 uint32_t d32; 837 } __packed data; 838 } __packed; 839 840 enum bwn_fw_hdr_format { 841 BWN_FW_HDR_598, 842 BWN_FW_HDR_410, 843 BWN_FW_HDR_351, 844 }; 845 846 enum bwn_fwtype { 847 BWN_FWTYPE_DEFAULT, 848 BWN_FWTYPE_OPENSOURCE, 849 BWN_NR_FWTYPES, 850 }; 851 852 struct bwn_fwfile { 853 const char *filename; 854 const struct firmware *fw; 855 enum bwn_fwtype type; 856 }; 857 858 struct bwn_key { 859 void *keyconf; 860 uint8_t algorithm; 861 }; 862 863 struct bwn_fw { 864 struct bwn_fwfile ucode; 865 struct bwn_fwfile pcm; 866 struct bwn_fwfile initvals; 867 struct bwn_fwfile initvals_band; 868 enum bwn_fw_hdr_format fw_hdr_format; 869 870 uint16_t rev; 871 uint16_t patch; 872 uint8_t opensource; 873 uint8_t no_pcmfile; 874 }; 875 876 struct bwn_lo_g_sm { 877 int curstate; 878 int nmeasure; 879 int multipler; 880 uint16_t feedth; 881 struct bwn_loctl loctl; 882 }; 883 884 struct bwn_lo_g_value { 885 uint8_t old_channel; 886 uint16_t phy_lomask; 887 uint16_t phy_extg; 888 uint16_t phy_dacctl_hwpctl; 889 uint16_t phy_dacctl; 890 uint16_t phy_hpwr_tssictl; 891 uint16_t phy_analogover; 892 uint16_t phy_analogoverval; 893 uint16_t phy_rfover; 894 uint16_t phy_rfoverval; 895 uint16_t phy_classctl; 896 uint16_t phy_crs0; 897 uint16_t phy_pgactl; 898 uint16_t phy_syncctl; 899 uint16_t phy_cck0; 900 uint16_t phy_cck1; 901 uint16_t phy_cck2; 902 uint16_t phy_cck3; 903 uint16_t phy_cck4; 904 uint16_t reg0; 905 uint16_t reg1; 906 uint16_t rf0; 907 uint16_t rf1; 908 uint16_t rf2; 909 }; 910 911 #define BWN_LED_MAX 4 912 913 #define BWN_LED_EVENT_NONE -1 914 #define BWN_LED_EVENT_POLL 0 915 #define BWN_LED_EVENT_TX 1 916 #define BWN_LED_EVENT_RX 2 917 #define BWN_LED_SLOWDOWN(dur) (dur) = (((dur) * 3) / 2) 918 919 struct bwn_led { 920 uint8_t led_flags; /* BWN_LED_F_ */ 921 uint8_t led_act; /* BWN_LED_ACT_ */ 922 uint8_t led_mask; 923 }; 924 925 #define BWN_LED_F_ACTLOW 0x1 926 #define BWN_LED_F_BLINK 0x2 927 #define BWN_LED_F_POLLABLE 0x4 928 #define BWN_LED_F_SLOW 0x8 929 930 struct bwn_mac { 931 struct bwn_softc *mac_sc; 932 unsigned mac_status; 933 #define BWN_MAC_STATUS_UNINIT 0 934 #define BWN_MAC_STATUS_INITED 1 935 #define BWN_MAC_STATUS_STARTED 2 936 unsigned mac_flags; 937 /* use "Bad Frames Preemption" */ 938 #define BWN_MAC_FLAG_BADFRAME_PREEMP (1 << 0) 939 #define BWN_MAC_FLAG_DFQVALID (1 << 1) 940 #define BWN_MAC_FLAG_RADIO_ON (1 << 2) 941 #define BWN_MAC_FLAG_DMA (1 << 3) 942 #define BWN_MAC_FLAG_WME (1 << 4) 943 #define BWN_MAC_FLAG_HWCRYPTO (1 << 5) 944 945 struct resource_spec *mac_intr_spec; 946 #define BWN_MSI_MESSAGES 1 947 struct resource *mac_res_irq[BWN_MSI_MESSAGES]; 948 void *mac_intrhand[BWN_MSI_MESSAGES]; 949 int mac_msi; 950 951 struct bwn_noise mac_noise; 952 struct bwn_phy mac_phy; 953 struct bwn_stats mac_stats; 954 uint32_t mac_reason_intr; 955 uint32_t mac_reason[6]; 956 uint32_t mac_intr_mask; 957 int mac_suspended; 958 959 struct bwn_fw mac_fw; 960 961 union { 962 struct bwn_dma dma; 963 struct bwn_pio pio; 964 } mac_method; 965 966 uint16_t mac_ktp; /* Key table pointer */ 967 uint8_t mac_max_nr_keys; 968 struct bwn_key mac_key[58]; 969 970 unsigned int mac_task_state; 971 struct task mac_intrtask; 972 struct task mac_hwreset; 973 struct task mac_txpower; 974 975 TAILQ_ENTRY(bwn_mac) mac_list; 976 }; 977 978 static inline int 979 bwn_tx_hdrsize(struct bwn_mac *mac) 980 { 981 switch (mac->mac_fw.fw_hdr_format) { 982 case BWN_FW_HDR_598: 983 return (112 + (sizeof(struct bwn_plcp6))); 984 case BWN_FW_HDR_410: 985 return (104 + (sizeof(struct bwn_plcp6))); 986 case BWN_FW_HDR_351: 987 return (100 + (sizeof(struct bwn_plcp6))); 988 default: 989 printf("%s: unknown header format (%d)\n", __func__, 990 mac->mac_fw.fw_hdr_format); 991 return (112 + (sizeof(struct bwn_plcp6))); 992 } 993 } 994 995 /* 996 * Driver-specific vap state. 997 */ 998 struct bwn_vap { 999 struct ieee80211vap bv_vap; /* base class */ 1000 int (*bv_newstate)(struct ieee80211vap *, 1001 enum ieee80211_state, int); 1002 }; 1003 #define BWN_VAP(vap) ((struct bwn_vap *)(vap)) 1004 #define BWN_VAP_CONST(vap) ((const struct mwl_vap *)(vap)) 1005 1006 struct bwn_softc { 1007 device_t sc_dev; 1008 struct mtx sc_mtx; 1009 struct ieee80211com sc_ic; 1010 struct mbufq sc_snd; 1011 unsigned sc_flags; 1012 #define BWN_FLAG_ATTACHED (1 << 0) 1013 #define BWN_FLAG_INVALID (1 << 1) 1014 #define BWN_FLAG_NEED_BEACON_TP (1 << 2) 1015 #define BWN_FLAG_RUNNING (1 << 3) 1016 unsigned sc_debug; 1017 1018 struct bwn_mac *sc_curmac; 1019 TAILQ_HEAD(, bwn_mac) sc_maclist; 1020 1021 uint8_t sc_bssid[IEEE80211_ADDR_LEN]; 1022 unsigned int sc_filters; 1023 uint8_t sc_beacons[2]; 1024 uint8_t sc_rf_enabled; 1025 1026 struct wmeParams sc_wmeParams[4]; 1027 1028 struct callout sc_rfswitch_ch; /* for laptop */ 1029 struct callout sc_task_ch; 1030 struct callout sc_watchdog_ch; 1031 int sc_watchdog_timer; 1032 struct taskqueue *sc_tq; /* private task queue */ 1033 int (*sc_newstate)(struct ieee80211com *, 1034 enum ieee80211_state, int); 1035 void (*sc_node_cleanup)( 1036 struct ieee80211_node *); 1037 1038 int sc_rx_rate; 1039 int sc_tx_rate; 1040 1041 int sc_led_blinking; 1042 int sc_led_ticks; 1043 struct bwn_led *sc_blink_led; 1044 struct callout sc_led_blink_ch; 1045 int sc_led_blink_offdur; 1046 struct bwn_led sc_leds[BWN_LED_MAX]; 1047 int sc_led_idle; 1048 int sc_led_blink; 1049 1050 struct bwn_tx_radiotap_header sc_tx_th; 1051 struct bwn_rx_radiotap_header sc_rx_th; 1052 }; 1053 1054 #define BWN_LOCK_INIT(sc) \ 1055 mtx_init(&(sc)->sc_mtx, device_get_nameunit((sc)->sc_dev), \ 1056 MTX_NETWORK_LOCK, MTX_DEF) 1057 #define BWN_LOCK_DESTROY(sc) mtx_destroy(&(sc)->sc_mtx) 1058 #define BWN_LOCK(sc) mtx_lock(&(sc)->sc_mtx) 1059 #define BWN_UNLOCK(sc) mtx_unlock(&(sc)->sc_mtx) 1060 #define BWN_ASSERT_LOCKED(sc) mtx_assert(&(sc)->sc_mtx, MA_OWNED) 1061 1062 static inline bwn_band_t 1063 bwn_channel_band(struct bwn_mac *mac, struct ieee80211_channel *c) 1064 { 1065 if (IEEE80211_IS_CHAN_5GHZ(c)) 1066 return BWN_BAND_5G; 1067 /* XXX check 2g, log error if not 2g or 5g? */ 1068 return BWN_BAND_2G; 1069 } 1070 1071 static inline bwn_band_t 1072 bwn_current_band(struct bwn_mac *mac) 1073 { 1074 struct ieee80211com *ic = &mac->mac_sc->sc_ic; 1075 if (IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan)) 1076 return BWN_BAND_5G; 1077 /* XXX check 2g, log error if not 2g or 5g? */ 1078 return BWN_BAND_2G; 1079 } 1080 1081 static inline bool 1082 bwn_is_40mhz(struct bwn_mac *mac) 1083 { 1084 struct ieee80211com *ic = &mac->mac_sc->sc_ic; 1085 1086 return !! (IEEE80211_IS_CHAN_HT40(ic->ic_curchan)); 1087 } 1088 1089 static inline int 1090 bwn_get_centre_freq(struct bwn_mac *mac) 1091 { 1092 1093 struct ieee80211com *ic = &mac->mac_sc->sc_ic; 1094 /* XXX TODO: calculate correctly for HT40 mode */ 1095 return ic->ic_curchan->ic_freq; 1096 } 1097 1098 static inline int 1099 bwn_get_chan_centre_freq(struct bwn_mac *mac, struct ieee80211_channel *chan) 1100 { 1101 1102 /* XXX TODO: calculate correctly for HT40 mode */ 1103 return chan->ic_freq; 1104 } 1105 1106 static inline int 1107 bwn_get_chan(struct bwn_mac *mac) 1108 { 1109 1110 struct ieee80211com *ic = &mac->mac_sc->sc_ic; 1111 /* XXX TODO: calculate correctly for HT40 mode */ 1112 return ic->ic_curchan->ic_ieee; 1113 } 1114 1115 static inline struct ieee80211_channel * 1116 bwn_get_channel(struct bwn_mac *mac) 1117 { 1118 1119 struct ieee80211com *ic = &mac->mac_sc->sc_ic; 1120 return ic->ic_curchan; 1121 } 1122 1123 static inline bool 1124 bwn_is_chan_passive(struct bwn_mac *mac) 1125 { 1126 1127 struct ieee80211com *ic = &mac->mac_sc->sc_ic; 1128 return !! IEEE80211_IS_CHAN_PASSIVE(ic->ic_curchan); 1129 } 1130 1131 static inline bwn_chan_type_t 1132 bwn_get_chan_type(struct bwn_mac *mac, struct ieee80211_channel *c) 1133 { 1134 struct ieee80211com *ic = &mac->mac_sc->sc_ic; 1135 if (c == NULL) 1136 c = ic->ic_curchan; 1137 if (IEEE80211_IS_CHAN_HT40U(c)) 1138 return BWN_CHAN_TYPE_40_HT_U; 1139 else if (IEEE80211_IS_CHAN_HT40D(c)) 1140 return BWN_CHAN_TYPE_40_HT_D; 1141 else if (IEEE80211_IS_CHAN_HT20(c)) 1142 return BWN_CHAN_TYPE_20_HT; 1143 else 1144 return BWN_CHAN_TYPE_20; 1145 } 1146 1147 static inline int 1148 bwn_get_chan_power(struct bwn_mac *mac, struct ieee80211_channel *c) 1149 { 1150 1151 /* return in dbm */ 1152 return c->ic_maxpower / 2; 1153 } 1154 1155 /* 1156 * For now there's no bhnd bus support. Places where it matters 1157 * should call this routine so we can start logging things. 1158 */ 1159 static inline int 1160 bwn_is_bus_siba(struct bwn_mac *mac) 1161 { 1162 1163 return 1; 1164 } 1165 #endif /* !_IF_BWNVAR_H */ 1166