1 /*- 2 * Copyright (c) 2009-2010 Weongyo Jeong <weongyo@freebsd.org> 3 * Copyright (c) 2016 Adrian Chadd <adrian@freebsd.org> 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer, 11 * without modification. 12 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 13 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 14 * redistribution must be conditioned upon including a substantially 15 * similar Disclaimer requirement for further binary redistribution. 16 * 17 * NO WARRANTY 18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 19 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 20 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 21 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 22 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 23 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 26 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 28 * THE POSSIBILITY OF SUCH DAMAGES. 29 */ 30 31 #include <sys/cdefs.h> 32 __FBSDID("$FreeBSD$"); 33 34 #include "opt_bwn.h" 35 #include "opt_wlan.h" 36 37 /* 38 * The Broadcom Wireless LAN controller driver. 39 */ 40 41 #include <sys/param.h> 42 #include <sys/systm.h> 43 #include <sys/kernel.h> 44 #include <sys/malloc.h> 45 #include <sys/module.h> 46 #include <sys/endian.h> 47 #include <sys/errno.h> 48 #include <sys/firmware.h> 49 #include <sys/lock.h> 50 #include <sys/mutex.h> 51 #include <machine/bus.h> 52 #include <machine/resource.h> 53 #include <sys/bus.h> 54 #include <sys/rman.h> 55 #include <sys/socket.h> 56 #include <sys/sockio.h> 57 58 #include <net/ethernet.h> 59 #include <net/if.h> 60 #include <net/if_var.h> 61 #include <net/if_arp.h> 62 #include <net/if_dl.h> 63 #include <net/if_llc.h> 64 #include <net/if_media.h> 65 #include <net/if_types.h> 66 67 #include <dev/pci/pcivar.h> 68 #include <dev/pci/pcireg.h> 69 70 #include <net80211/ieee80211_var.h> 71 #include <net80211/ieee80211_radiotap.h> 72 #include <net80211/ieee80211_regdomain.h> 73 #include <net80211/ieee80211_phy.h> 74 #include <net80211/ieee80211_ratectl.h> 75 76 #include <dev/bwn/if_bwn_siba.h> 77 78 #include <dev/bwn/if_bwnreg.h> 79 #include <dev/bwn/if_bwnvar.h> 80 81 #include <dev/bwn/if_bwn_chipid.h> 82 #include <dev/bwn/if_bwn_debug.h> 83 #include <dev/bwn/if_bwn_misc.h> 84 #include <dev/bwn/if_bwn_phy_common.h> 85 86 void 87 bwn_mac_switch_freq(struct bwn_mac *mac, int spurmode) 88 { 89 struct bwn_softc *sc = mac->mac_sc; 90 uint16_t chip_id = siba_get_chipid(sc->sc_dev); 91 92 if (chip_id == BCMA_CHIP_ID_BCM4331) { 93 switch (spurmode) { 94 case 2: /* 168 Mhz: 2^26/168 = 0x61862 */ 95 BWN_WRITE_2(mac, BWN_TSF_CLK_FRAC_LOW, 0x1862); 96 BWN_WRITE_2(mac, BWN_TSF_CLK_FRAC_HIGH, 0x6); 97 break; 98 case 1: /* 164 Mhz: 2^26/164 = 0x63e70 */ 99 BWN_WRITE_2(mac, BWN_TSF_CLK_FRAC_LOW, 0x3e70); 100 BWN_WRITE_2(mac, BWN_TSF_CLK_FRAC_HIGH, 0x6); 101 break; 102 default: /* 160 Mhz: 2^26/160 = 0x66666 */ 103 BWN_WRITE_2(mac, BWN_TSF_CLK_FRAC_LOW, 0x6666); 104 BWN_WRITE_2(mac, BWN_TSF_CLK_FRAC_HIGH, 0x6); 105 break; 106 } 107 } else if (chip_id == BCMA_CHIP_ID_BCM43131 || 108 chip_id == BCMA_CHIP_ID_BCM43217 || 109 chip_id == BCMA_CHIP_ID_BCM43222 || 110 chip_id == BCMA_CHIP_ID_BCM43224 || 111 chip_id == BCMA_CHIP_ID_BCM43225 || 112 chip_id == BCMA_CHIP_ID_BCM43227 || 113 chip_id == BCMA_CHIP_ID_BCM43228) { 114 switch (spurmode) { 115 case 2: /* 126 Mhz */ 116 BWN_WRITE_2(mac, BWN_TSF_CLK_FRAC_LOW, 0x2082); 117 BWN_WRITE_2(mac, BWN_TSF_CLK_FRAC_HIGH, 0x8); 118 break; 119 case 1: /* 123 Mhz */ 120 BWN_WRITE_2(mac, BWN_TSF_CLK_FRAC_LOW, 0x5341); 121 BWN_WRITE_2(mac, BWN_TSF_CLK_FRAC_HIGH, 0x8); 122 break; 123 default: /* 120 Mhz */ 124 BWN_WRITE_2(mac, BWN_TSF_CLK_FRAC_LOW, 0x8889); 125 BWN_WRITE_2(mac, BWN_TSF_CLK_FRAC_HIGH, 0x8); 126 break; 127 } 128 } else if (mac->mac_phy.type == BWN_PHYTYPE_LCN) { 129 switch (spurmode) { 130 case 1: /* 82 Mhz */ 131 BWN_WRITE_2(mac, BWN_TSF_CLK_FRAC_LOW, 0x7CE0); 132 BWN_WRITE_2(mac, BWN_TSF_CLK_FRAC_HIGH, 0xC); 133 break; 134 default: /* 80 Mhz */ 135 BWN_WRITE_2(mac, BWN_TSF_CLK_FRAC_LOW, 0xCCCD); 136 BWN_WRITE_2(mac, BWN_TSF_CLK_FRAC_HIGH, 0xC); 137 break; 138 } 139 } 140 } 141 142 /* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BmacPhyClkFgc */ 143 void 144 bwn_phy_force_clock(struct bwn_mac *mac, int force) 145 { 146 struct bwn_softc *sc = mac->mac_sc; 147 uint32_t tmp; 148 149 /* XXX Only for N, HT and AC PHYs */ 150 151 tmp = siba_read_4(sc->sc_dev, SIBA_TGSLOW); 152 if (force) 153 tmp |= SIBA_TGSLOW_FGC; 154 else 155 tmp &= ~SIBA_TGSLOW_FGC; 156 siba_write_4(sc->sc_dev, SIBA_TGSLOW, tmp); 157 } 158 159 int 160 bwn_radio_wait_value(struct bwn_mac *mac, uint16_t offset, uint16_t mask, 161 uint16_t value, int delay, int timeout) 162 { 163 uint16_t val; 164 int i; 165 166 for (i = 0; i < timeout; i += delay) { 167 val = BWN_RF_READ(mac, offset); 168 if ((val & mask) == value) 169 return (1); 170 DELAY(delay); 171 } 172 return (0); 173 } 174 175 void 176 bwn_mac_phy_clock_set(struct bwn_mac *mac, int enabled) 177 { 178 struct bwn_softc *sc = mac->mac_sc; 179 uint32_t val; 180 181 val = siba_read_4(sc->sc_dev, SIBA_TGSLOW); 182 if (enabled) 183 val |= BWN_TGSLOW_MACPHYCLKEN; 184 else 185 val &= ~BWN_TGSLOW_MACPHYCLKEN; 186 siba_write_4(sc->sc_dev, SIBA_TGSLOW, val); 187 } 188 189 /* http://bcm-v4.sipsolutions.net/802.11/PHY/BmacCorePllReset */ 190 void 191 bwn_wireless_core_phy_pll_reset(struct bwn_mac *mac) 192 { 193 struct bwn_softc *sc = mac->mac_sc; 194 195 siba_cc_write32(sc->sc_dev, SIBA_CC_CHIPCTL_ADDR, 0); 196 siba_cc_mask32(sc->sc_dev, SIBA_CC_CHIPCTL_DATA, ~0x4); 197 siba_cc_set32(sc->sc_dev, SIBA_CC_CHIPCTL_DATA, 0x4); 198 siba_cc_mask32(sc->sc_dev, SIBA_CC_CHIPCTL_DATA, ~0x4); 199 } 200