1 /*- 2 * Copyright (c) 2009-2010 Weongyo Jeong <weongyo@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 16 * NO WARRANTY 17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 27 * THE POSSIBILITY OF SUCH DAMAGES. 28 */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 /* 34 * The Broadcom Wireless LAN controller driver. 35 */ 36 37 #include "opt_bwn.h" 38 #include "opt_wlan.h" 39 40 #include <sys/param.h> 41 #include <sys/systm.h> 42 #include <sys/kernel.h> 43 #include <sys/malloc.h> 44 #include <sys/module.h> 45 #include <sys/endian.h> 46 #include <sys/errno.h> 47 #include <sys/firmware.h> 48 #include <sys/lock.h> 49 #include <sys/mutex.h> 50 #include <machine/bus.h> 51 #include <machine/resource.h> 52 #include <sys/bus.h> 53 #include <sys/rman.h> 54 #include <sys/socket.h> 55 #include <sys/sockio.h> 56 57 #include <net/ethernet.h> 58 #include <net/if.h> 59 #include <net/if_var.h> 60 #include <net/if_arp.h> 61 #include <net/if_dl.h> 62 #include <net/if_llc.h> 63 #include <net/if_media.h> 64 #include <net/if_types.h> 65 66 #include <dev/pci/pcivar.h> 67 #include <dev/pci/pcireg.h> 68 #include <dev/siba/siba_ids.h> 69 #include <dev/siba/sibareg.h> 70 #include <dev/siba/sibavar.h> 71 72 #include <net80211/ieee80211_var.h> 73 #include <net80211/ieee80211_radiotap.h> 74 #include <net80211/ieee80211_regdomain.h> 75 #include <net80211/ieee80211_phy.h> 76 #include <net80211/ieee80211_ratectl.h> 77 78 #include <dev/bwn/if_bwnreg.h> 79 #include <dev/bwn/if_bwnvar.h> 80 81 #include <dev/bwn/if_bwn_debug.h> 82 #include <dev/bwn/if_bwn_misc.h> 83 #include <dev/bwn/if_bwn_util.h> 84 #include <dev/bwn/if_bwn_phy_common.h> 85 #include <dev/bwn/if_bwn_phy_g.h> 86 #include <dev/bwn/if_bwn_phy_lp.h> 87 #include <dev/bwn/if_bwn_phy_n.h> 88 89 static SYSCTL_NODE(_hw, OID_AUTO, bwn, CTLFLAG_RD, 0, 90 "Broadcom driver parameters"); 91 92 /* 93 * Tunable & sysctl variables. 94 */ 95 96 #ifdef BWN_DEBUG 97 static int bwn_debug = 0; 98 SYSCTL_INT(_hw_bwn, OID_AUTO, debug, CTLFLAG_RWTUN, &bwn_debug, 0, 99 "Broadcom debugging printfs"); 100 #endif 101 102 static int bwn_bfp = 0; /* use "Bad Frames Preemption" */ 103 SYSCTL_INT(_hw_bwn, OID_AUTO, bfp, CTLFLAG_RW, &bwn_bfp, 0, 104 "uses Bad Frames Preemption"); 105 static int bwn_bluetooth = 1; 106 SYSCTL_INT(_hw_bwn, OID_AUTO, bluetooth, CTLFLAG_RW, &bwn_bluetooth, 0, 107 "turns on Bluetooth Coexistence"); 108 static int bwn_hwpctl = 0; 109 SYSCTL_INT(_hw_bwn, OID_AUTO, hwpctl, CTLFLAG_RW, &bwn_hwpctl, 0, 110 "uses H/W power control"); 111 static int bwn_msi_disable = 0; /* MSI disabled */ 112 TUNABLE_INT("hw.bwn.msi_disable", &bwn_msi_disable); 113 static int bwn_usedma = 1; 114 SYSCTL_INT(_hw_bwn, OID_AUTO, usedma, CTLFLAG_RD, &bwn_usedma, 0, 115 "uses DMA"); 116 TUNABLE_INT("hw.bwn.usedma", &bwn_usedma); 117 static int bwn_wme = 1; 118 SYSCTL_INT(_hw_bwn, OID_AUTO, wme, CTLFLAG_RW, &bwn_wme, 0, 119 "uses WME support"); 120 121 static void bwn_attach_pre(struct bwn_softc *); 122 static int bwn_attach_post(struct bwn_softc *); 123 static void bwn_sprom_bugfixes(device_t); 124 static int bwn_init(struct bwn_softc *); 125 static void bwn_parent(struct ieee80211com *); 126 static void bwn_start(struct bwn_softc *); 127 static int bwn_transmit(struct ieee80211com *, struct mbuf *); 128 static int bwn_attach_core(struct bwn_mac *); 129 static int bwn_phy_getinfo(struct bwn_mac *, int); 130 static int bwn_chiptest(struct bwn_mac *); 131 static int bwn_setup_channels(struct bwn_mac *, int, int); 132 static void bwn_shm_ctlword(struct bwn_mac *, uint16_t, 133 uint16_t); 134 static void bwn_addchannels(struct ieee80211_channel [], int, int *, 135 const struct bwn_channelinfo *, const uint8_t []); 136 static int bwn_raw_xmit(struct ieee80211_node *, struct mbuf *, 137 const struct ieee80211_bpf_params *); 138 static void bwn_updateslot(struct ieee80211com *); 139 static void bwn_update_promisc(struct ieee80211com *); 140 static void bwn_wme_init(struct bwn_mac *); 141 static int bwn_wme_update(struct ieee80211com *); 142 static void bwn_wme_clear(struct bwn_softc *); 143 static void bwn_wme_load(struct bwn_mac *); 144 static void bwn_wme_loadparams(struct bwn_mac *, 145 const struct wmeParams *, uint16_t); 146 static void bwn_scan_start(struct ieee80211com *); 147 static void bwn_scan_end(struct ieee80211com *); 148 static void bwn_set_channel(struct ieee80211com *); 149 static struct ieee80211vap *bwn_vap_create(struct ieee80211com *, 150 const char [IFNAMSIZ], int, enum ieee80211_opmode, int, 151 const uint8_t [IEEE80211_ADDR_LEN], 152 const uint8_t [IEEE80211_ADDR_LEN]); 153 static void bwn_vap_delete(struct ieee80211vap *); 154 static void bwn_stop(struct bwn_softc *); 155 static int bwn_core_init(struct bwn_mac *); 156 static void bwn_core_start(struct bwn_mac *); 157 static void bwn_core_exit(struct bwn_mac *); 158 static void bwn_bt_disable(struct bwn_mac *); 159 static int bwn_chip_init(struct bwn_mac *); 160 static void bwn_set_txretry(struct bwn_mac *, int, int); 161 static void bwn_rate_init(struct bwn_mac *); 162 static void bwn_set_phytxctl(struct bwn_mac *); 163 static void bwn_spu_setdelay(struct bwn_mac *, int); 164 static void bwn_bt_enable(struct bwn_mac *); 165 static void bwn_set_macaddr(struct bwn_mac *); 166 static void bwn_crypt_init(struct bwn_mac *); 167 static void bwn_chip_exit(struct bwn_mac *); 168 static int bwn_fw_fillinfo(struct bwn_mac *); 169 static int bwn_fw_loaducode(struct bwn_mac *); 170 static int bwn_gpio_init(struct bwn_mac *); 171 static int bwn_fw_loadinitvals(struct bwn_mac *); 172 static int bwn_phy_init(struct bwn_mac *); 173 static void bwn_set_txantenna(struct bwn_mac *, int); 174 static void bwn_set_opmode(struct bwn_mac *); 175 static void bwn_rate_write(struct bwn_mac *, uint16_t, int); 176 static uint8_t bwn_plcp_getcck(const uint8_t); 177 static uint8_t bwn_plcp_getofdm(const uint8_t); 178 static void bwn_pio_init(struct bwn_mac *); 179 static uint16_t bwn_pio_idx2base(struct bwn_mac *, int); 180 static void bwn_pio_set_txqueue(struct bwn_mac *, struct bwn_pio_txqueue *, 181 int); 182 static void bwn_pio_setupqueue_rx(struct bwn_mac *, 183 struct bwn_pio_rxqueue *, int); 184 static void bwn_destroy_queue_tx(struct bwn_pio_txqueue *); 185 static uint16_t bwn_pio_read_2(struct bwn_mac *, struct bwn_pio_txqueue *, 186 uint16_t); 187 static void bwn_pio_cancel_tx_packets(struct bwn_pio_txqueue *); 188 static int bwn_pio_rx(struct bwn_pio_rxqueue *); 189 static uint8_t bwn_pio_rxeof(struct bwn_pio_rxqueue *); 190 static void bwn_pio_handle_txeof(struct bwn_mac *, 191 const struct bwn_txstatus *); 192 static uint16_t bwn_pio_rx_read_2(struct bwn_pio_rxqueue *, uint16_t); 193 static uint32_t bwn_pio_rx_read_4(struct bwn_pio_rxqueue *, uint16_t); 194 static void bwn_pio_rx_write_2(struct bwn_pio_rxqueue *, uint16_t, 195 uint16_t); 196 static void bwn_pio_rx_write_4(struct bwn_pio_rxqueue *, uint16_t, 197 uint32_t); 198 static int bwn_pio_tx_start(struct bwn_mac *, struct ieee80211_node *, 199 struct mbuf *); 200 static struct bwn_pio_txqueue *bwn_pio_select(struct bwn_mac *, uint8_t); 201 static uint32_t bwn_pio_write_multi_4(struct bwn_mac *, 202 struct bwn_pio_txqueue *, uint32_t, const void *, int); 203 static void bwn_pio_write_4(struct bwn_mac *, struct bwn_pio_txqueue *, 204 uint16_t, uint32_t); 205 static uint16_t bwn_pio_write_multi_2(struct bwn_mac *, 206 struct bwn_pio_txqueue *, uint16_t, const void *, int); 207 static uint16_t bwn_pio_write_mbuf_2(struct bwn_mac *, 208 struct bwn_pio_txqueue *, uint16_t, struct mbuf *); 209 static struct bwn_pio_txqueue *bwn_pio_parse_cookie(struct bwn_mac *, 210 uint16_t, struct bwn_pio_txpkt **); 211 static void bwn_dma_init(struct bwn_mac *); 212 static void bwn_dma_rxdirectfifo(struct bwn_mac *, int, uint8_t); 213 static int bwn_dma_mask2type(uint64_t); 214 static uint64_t bwn_dma_mask(struct bwn_mac *); 215 static uint16_t bwn_dma_base(int, int); 216 static void bwn_dma_ringfree(struct bwn_dma_ring **); 217 static void bwn_dma_32_getdesc(struct bwn_dma_ring *, 218 int, struct bwn_dmadesc_generic **, 219 struct bwn_dmadesc_meta **); 220 static void bwn_dma_32_setdesc(struct bwn_dma_ring *, 221 struct bwn_dmadesc_generic *, bus_addr_t, uint16_t, int, 222 int, int); 223 static void bwn_dma_32_start_transfer(struct bwn_dma_ring *, int); 224 static void bwn_dma_32_suspend(struct bwn_dma_ring *); 225 static void bwn_dma_32_resume(struct bwn_dma_ring *); 226 static int bwn_dma_32_get_curslot(struct bwn_dma_ring *); 227 static void bwn_dma_32_set_curslot(struct bwn_dma_ring *, int); 228 static void bwn_dma_64_getdesc(struct bwn_dma_ring *, 229 int, struct bwn_dmadesc_generic **, 230 struct bwn_dmadesc_meta **); 231 static void bwn_dma_64_setdesc(struct bwn_dma_ring *, 232 struct bwn_dmadesc_generic *, bus_addr_t, uint16_t, int, 233 int, int); 234 static void bwn_dma_64_start_transfer(struct bwn_dma_ring *, int); 235 static void bwn_dma_64_suspend(struct bwn_dma_ring *); 236 static void bwn_dma_64_resume(struct bwn_dma_ring *); 237 static int bwn_dma_64_get_curslot(struct bwn_dma_ring *); 238 static void bwn_dma_64_set_curslot(struct bwn_dma_ring *, int); 239 static int bwn_dma_allocringmemory(struct bwn_dma_ring *); 240 static void bwn_dma_setup(struct bwn_dma_ring *); 241 static void bwn_dma_free_ringmemory(struct bwn_dma_ring *); 242 static void bwn_dma_cleanup(struct bwn_dma_ring *); 243 static void bwn_dma_free_descbufs(struct bwn_dma_ring *); 244 static int bwn_dma_tx_reset(struct bwn_mac *, uint16_t, int); 245 static void bwn_dma_rx(struct bwn_dma_ring *); 246 static int bwn_dma_rx_reset(struct bwn_mac *, uint16_t, int); 247 static void bwn_dma_free_descbuf(struct bwn_dma_ring *, 248 struct bwn_dmadesc_meta *); 249 static void bwn_dma_set_redzone(struct bwn_dma_ring *, struct mbuf *); 250 static int bwn_dma_gettype(struct bwn_mac *); 251 static void bwn_dma_ring_addr(void *, bus_dma_segment_t *, int, int); 252 static int bwn_dma_freeslot(struct bwn_dma_ring *); 253 static int bwn_dma_nextslot(struct bwn_dma_ring *, int); 254 static void bwn_dma_rxeof(struct bwn_dma_ring *, int *); 255 static int bwn_dma_newbuf(struct bwn_dma_ring *, 256 struct bwn_dmadesc_generic *, struct bwn_dmadesc_meta *, 257 int); 258 static void bwn_dma_buf_addr(void *, bus_dma_segment_t *, int, 259 bus_size_t, int); 260 static uint8_t bwn_dma_check_redzone(struct bwn_dma_ring *, struct mbuf *); 261 static void bwn_dma_handle_txeof(struct bwn_mac *, 262 const struct bwn_txstatus *); 263 static int bwn_dma_tx_start(struct bwn_mac *, struct ieee80211_node *, 264 struct mbuf *); 265 static int bwn_dma_getslot(struct bwn_dma_ring *); 266 static struct bwn_dma_ring *bwn_dma_select(struct bwn_mac *, 267 uint8_t); 268 static int bwn_dma_attach(struct bwn_mac *); 269 static struct bwn_dma_ring *bwn_dma_ringsetup(struct bwn_mac *, 270 int, int, int); 271 static struct bwn_dma_ring *bwn_dma_parse_cookie(struct bwn_mac *, 272 const struct bwn_txstatus *, uint16_t, int *); 273 static void bwn_dma_free(struct bwn_mac *); 274 static int bwn_fw_gets(struct bwn_mac *, enum bwn_fwtype); 275 static int bwn_fw_get(struct bwn_mac *, enum bwn_fwtype, 276 const char *, struct bwn_fwfile *); 277 static void bwn_release_firmware(struct bwn_mac *); 278 static void bwn_do_release_fw(struct bwn_fwfile *); 279 static uint16_t bwn_fwcaps_read(struct bwn_mac *); 280 static int bwn_fwinitvals_write(struct bwn_mac *, 281 const struct bwn_fwinitvals *, size_t, size_t); 282 static uint16_t bwn_ant2phy(int); 283 static void bwn_mac_write_bssid(struct bwn_mac *); 284 static void bwn_mac_setfilter(struct bwn_mac *, uint16_t, 285 const uint8_t *); 286 static void bwn_key_dowrite(struct bwn_mac *, uint8_t, uint8_t, 287 const uint8_t *, size_t, const uint8_t *); 288 static void bwn_key_macwrite(struct bwn_mac *, uint8_t, 289 const uint8_t *); 290 static void bwn_key_write(struct bwn_mac *, uint8_t, uint8_t, 291 const uint8_t *); 292 static void bwn_phy_exit(struct bwn_mac *); 293 static void bwn_core_stop(struct bwn_mac *); 294 static int bwn_switch_band(struct bwn_softc *, 295 struct ieee80211_channel *); 296 static void bwn_phy_reset(struct bwn_mac *); 297 static int bwn_newstate(struct ieee80211vap *, enum ieee80211_state, int); 298 static void bwn_set_pretbtt(struct bwn_mac *); 299 static int bwn_intr(void *); 300 static void bwn_intrtask(void *, int); 301 static void bwn_restart(struct bwn_mac *, const char *); 302 static void bwn_intr_ucode_debug(struct bwn_mac *); 303 static void bwn_intr_tbtt_indication(struct bwn_mac *); 304 static void bwn_intr_atim_end(struct bwn_mac *); 305 static void bwn_intr_beacon(struct bwn_mac *); 306 static void bwn_intr_pmq(struct bwn_mac *); 307 static void bwn_intr_noise(struct bwn_mac *); 308 static void bwn_intr_txeof(struct bwn_mac *); 309 static void bwn_hwreset(void *, int); 310 static void bwn_handle_fwpanic(struct bwn_mac *); 311 static void bwn_load_beacon0(struct bwn_mac *); 312 static void bwn_load_beacon1(struct bwn_mac *); 313 static uint32_t bwn_jssi_read(struct bwn_mac *); 314 static void bwn_noise_gensample(struct bwn_mac *); 315 static void bwn_handle_txeof(struct bwn_mac *, 316 const struct bwn_txstatus *); 317 static void bwn_rxeof(struct bwn_mac *, struct mbuf *, const void *); 318 static void bwn_phy_txpower_check(struct bwn_mac *, uint32_t); 319 static int bwn_tx_start(struct bwn_softc *, struct ieee80211_node *, 320 struct mbuf *); 321 static int bwn_tx_isfull(struct bwn_softc *, struct mbuf *); 322 static int bwn_set_txhdr(struct bwn_mac *, 323 struct ieee80211_node *, struct mbuf *, struct bwn_txhdr *, 324 uint16_t); 325 static void bwn_plcp_genhdr(struct bwn_plcp4 *, const uint16_t, 326 const uint8_t); 327 static uint8_t bwn_antenna_sanitize(struct bwn_mac *, uint8_t); 328 static uint8_t bwn_get_fbrate(uint8_t); 329 static void bwn_txpwr(void *, int); 330 static void bwn_tasks(void *); 331 static void bwn_task_15s(struct bwn_mac *); 332 static void bwn_task_30s(struct bwn_mac *); 333 static void bwn_task_60s(struct bwn_mac *); 334 static int bwn_plcp_get_ofdmrate(struct bwn_mac *, struct bwn_plcp6 *, 335 uint8_t); 336 static int bwn_plcp_get_cckrate(struct bwn_mac *, struct bwn_plcp6 *); 337 static void bwn_rx_radiotap(struct bwn_mac *, struct mbuf *, 338 const struct bwn_rxhdr4 *, struct bwn_plcp6 *, int, 339 int, int); 340 static void bwn_tsf_read(struct bwn_mac *, uint64_t *); 341 static void bwn_set_slot_time(struct bwn_mac *, uint16_t); 342 static void bwn_watchdog(void *); 343 static void bwn_dma_stop(struct bwn_mac *); 344 static void bwn_pio_stop(struct bwn_mac *); 345 static void bwn_dma_ringstop(struct bwn_dma_ring **); 346 static void bwn_led_attach(struct bwn_mac *); 347 static void bwn_led_newstate(struct bwn_mac *, enum ieee80211_state); 348 static void bwn_led_event(struct bwn_mac *, int); 349 static void bwn_led_blink_start(struct bwn_mac *, int, int); 350 static void bwn_led_blink_next(void *); 351 static void bwn_led_blink_end(void *); 352 static void bwn_rfswitch(void *); 353 static void bwn_rf_turnon(struct bwn_mac *); 354 static void bwn_rf_turnoff(struct bwn_mac *); 355 static void bwn_sysctl_node(struct bwn_softc *); 356 357 static struct resource_spec bwn_res_spec_legacy[] = { 358 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 359 { -1, 0, 0 } 360 }; 361 362 static struct resource_spec bwn_res_spec_msi[] = { 363 { SYS_RES_IRQ, 1, RF_ACTIVE }, 364 { -1, 0, 0 } 365 }; 366 367 static const struct bwn_channelinfo bwn_chantable_bg = { 368 .channels = { 369 { 2412, 1, 30 }, { 2417, 2, 30 }, { 2422, 3, 30 }, 370 { 2427, 4, 30 }, { 2432, 5, 30 }, { 2437, 6, 30 }, 371 { 2442, 7, 30 }, { 2447, 8, 30 }, { 2452, 9, 30 }, 372 { 2457, 10, 30 }, { 2462, 11, 30 }, { 2467, 12, 30 }, 373 { 2472, 13, 30 }, { 2484, 14, 30 } }, 374 .nchannels = 14 375 }; 376 377 static const struct bwn_channelinfo bwn_chantable_a = { 378 .channels = { 379 { 5170, 34, 30 }, { 5180, 36, 30 }, { 5190, 38, 30 }, 380 { 5200, 40, 30 }, { 5210, 42, 30 }, { 5220, 44, 30 }, 381 { 5230, 46, 30 }, { 5240, 48, 30 }, { 5260, 52, 30 }, 382 { 5280, 56, 30 }, { 5300, 60, 30 }, { 5320, 64, 30 }, 383 { 5500, 100, 30 }, { 5520, 104, 30 }, { 5540, 108, 30 }, 384 { 5560, 112, 30 }, { 5580, 116, 30 }, { 5600, 120, 30 }, 385 { 5620, 124, 30 }, { 5640, 128, 30 }, { 5660, 132, 30 }, 386 { 5680, 136, 30 }, { 5700, 140, 30 }, { 5745, 149, 30 }, 387 { 5765, 153, 30 }, { 5785, 157, 30 }, { 5805, 161, 30 }, 388 { 5825, 165, 30 }, { 5920, 184, 30 }, { 5940, 188, 30 }, 389 { 5960, 192, 30 }, { 5980, 196, 30 }, { 6000, 200, 30 }, 390 { 6020, 204, 30 }, { 6040, 208, 30 }, { 6060, 212, 30 }, 391 { 6080, 216, 30 } }, 392 .nchannels = 37 393 }; 394 395 #if 0 396 static const struct bwn_channelinfo bwn_chantable_n = { 397 .channels = { 398 { 5160, 32, 30 }, { 5170, 34, 30 }, { 5180, 36, 30 }, 399 { 5190, 38, 30 }, { 5200, 40, 30 }, { 5210, 42, 30 }, 400 { 5220, 44, 30 }, { 5230, 46, 30 }, { 5240, 48, 30 }, 401 { 5250, 50, 30 }, { 5260, 52, 30 }, { 5270, 54, 30 }, 402 { 5280, 56, 30 }, { 5290, 58, 30 }, { 5300, 60, 30 }, 403 { 5310, 62, 30 }, { 5320, 64, 30 }, { 5330, 66, 30 }, 404 { 5340, 68, 30 }, { 5350, 70, 30 }, { 5360, 72, 30 }, 405 { 5370, 74, 30 }, { 5380, 76, 30 }, { 5390, 78, 30 }, 406 { 5400, 80, 30 }, { 5410, 82, 30 }, { 5420, 84, 30 }, 407 { 5430, 86, 30 }, { 5440, 88, 30 }, { 5450, 90, 30 }, 408 { 5460, 92, 30 }, { 5470, 94, 30 }, { 5480, 96, 30 }, 409 { 5490, 98, 30 }, { 5500, 100, 30 }, { 5510, 102, 30 }, 410 { 5520, 104, 30 }, { 5530, 106, 30 }, { 5540, 108, 30 }, 411 { 5550, 110, 30 }, { 5560, 112, 30 }, { 5570, 114, 30 }, 412 { 5580, 116, 30 }, { 5590, 118, 30 }, { 5600, 120, 30 }, 413 { 5610, 122, 30 }, { 5620, 124, 30 }, { 5630, 126, 30 }, 414 { 5640, 128, 30 }, { 5650, 130, 30 }, { 5660, 132, 30 }, 415 { 5670, 134, 30 }, { 5680, 136, 30 }, { 5690, 138, 30 }, 416 { 5700, 140, 30 }, { 5710, 142, 30 }, { 5720, 144, 30 }, 417 { 5725, 145, 30 }, { 5730, 146, 30 }, { 5735, 147, 30 }, 418 { 5740, 148, 30 }, { 5745, 149, 30 }, { 5750, 150, 30 }, 419 { 5755, 151, 30 }, { 5760, 152, 30 }, { 5765, 153, 30 }, 420 { 5770, 154, 30 }, { 5775, 155, 30 }, { 5780, 156, 30 }, 421 { 5785, 157, 30 }, { 5790, 158, 30 }, { 5795, 159, 30 }, 422 { 5800, 160, 30 }, { 5805, 161, 30 }, { 5810, 162, 30 }, 423 { 5815, 163, 30 }, { 5820, 164, 30 }, { 5825, 165, 30 }, 424 { 5830, 166, 30 }, { 5840, 168, 30 }, { 5850, 170, 30 }, 425 { 5860, 172, 30 }, { 5870, 174, 30 }, { 5880, 176, 30 }, 426 { 5890, 178, 30 }, { 5900, 180, 30 }, { 5910, 182, 30 }, 427 { 5920, 184, 30 }, { 5930, 186, 30 }, { 5940, 188, 30 }, 428 { 5950, 190, 30 }, { 5960, 192, 30 }, { 5970, 194, 30 }, 429 { 5980, 196, 30 }, { 5990, 198, 30 }, { 6000, 200, 30 }, 430 { 6010, 202, 30 }, { 6020, 204, 30 }, { 6030, 206, 30 }, 431 { 6040, 208, 30 }, { 6050, 210, 30 }, { 6060, 212, 30 }, 432 { 6070, 214, 30 }, { 6080, 216, 30 }, { 6090, 218, 30 }, 433 { 6100, 220, 30 }, { 6110, 222, 30 }, { 6120, 224, 30 }, 434 { 6130, 226, 30 }, { 6140, 228, 30 } }, 435 .nchannels = 110 436 }; 437 #endif 438 439 #define VENDOR_LED_ACT(vendor) \ 440 { \ 441 .vid = PCI_VENDOR_##vendor, \ 442 .led_act = { BWN_VENDOR_LED_ACT_##vendor } \ 443 } 444 445 static const struct { 446 uint16_t vid; 447 uint8_t led_act[BWN_LED_MAX]; 448 } bwn_vendor_led_act[] = { 449 VENDOR_LED_ACT(COMPAQ), 450 VENDOR_LED_ACT(ASUSTEK) 451 }; 452 453 static const uint8_t bwn_default_led_act[BWN_LED_MAX] = 454 { BWN_VENDOR_LED_ACT_DEFAULT }; 455 456 #undef VENDOR_LED_ACT 457 458 static const struct { 459 int on_dur; 460 int off_dur; 461 } bwn_led_duration[109] = { 462 [0] = { 400, 100 }, 463 [2] = { 150, 75 }, 464 [4] = { 90, 45 }, 465 [11] = { 66, 34 }, 466 [12] = { 53, 26 }, 467 [18] = { 42, 21 }, 468 [22] = { 35, 17 }, 469 [24] = { 32, 16 }, 470 [36] = { 21, 10 }, 471 [48] = { 16, 8 }, 472 [72] = { 11, 5 }, 473 [96] = { 9, 4 }, 474 [108] = { 7, 3 } 475 }; 476 477 static const uint16_t bwn_wme_shm_offsets[] = { 478 [0] = BWN_WME_BESTEFFORT, 479 [1] = BWN_WME_BACKGROUND, 480 [2] = BWN_WME_VOICE, 481 [3] = BWN_WME_VIDEO, 482 }; 483 484 static const struct siba_devid bwn_devs[] = { 485 SIBA_DEV(BROADCOM, 80211, 5, "Revision 5"), 486 SIBA_DEV(BROADCOM, 80211, 6, "Revision 6"), 487 SIBA_DEV(BROADCOM, 80211, 7, "Revision 7"), 488 SIBA_DEV(BROADCOM, 80211, 9, "Revision 9"), 489 SIBA_DEV(BROADCOM, 80211, 10, "Revision 10"), 490 SIBA_DEV(BROADCOM, 80211, 11, "Revision 11"), 491 SIBA_DEV(BROADCOM, 80211, 12, "Revision 12"), 492 SIBA_DEV(BROADCOM, 80211, 13, "Revision 13"), 493 SIBA_DEV(BROADCOM, 80211, 15, "Revision 15"), 494 SIBA_DEV(BROADCOM, 80211, 16, "Revision 16") 495 }; 496 497 static int 498 bwn_probe(device_t dev) 499 { 500 int i; 501 502 for (i = 0; i < nitems(bwn_devs); i++) { 503 if (siba_get_vendor(dev) == bwn_devs[i].sd_vendor && 504 siba_get_device(dev) == bwn_devs[i].sd_device && 505 siba_get_revid(dev) == bwn_devs[i].sd_rev) 506 return (BUS_PROBE_DEFAULT); 507 } 508 509 return (ENXIO); 510 } 511 512 static int 513 bwn_attach(device_t dev) 514 { 515 struct bwn_mac *mac; 516 struct bwn_softc *sc = device_get_softc(dev); 517 int error, i, msic, reg; 518 519 sc->sc_dev = dev; 520 #ifdef BWN_DEBUG 521 sc->sc_debug = bwn_debug; 522 #endif 523 524 if ((sc->sc_flags & BWN_FLAG_ATTACHED) == 0) { 525 bwn_attach_pre(sc); 526 bwn_sprom_bugfixes(dev); 527 sc->sc_flags |= BWN_FLAG_ATTACHED; 528 } 529 530 if (!TAILQ_EMPTY(&sc->sc_maclist)) { 531 if (siba_get_pci_device(dev) != 0x4313 && 532 siba_get_pci_device(dev) != 0x431a && 533 siba_get_pci_device(dev) != 0x4321) { 534 device_printf(sc->sc_dev, 535 "skip 802.11 cores\n"); 536 return (ENODEV); 537 } 538 } 539 540 mac = malloc(sizeof(*mac), M_DEVBUF, M_WAITOK | M_ZERO); 541 mac->mac_sc = sc; 542 mac->mac_status = BWN_MAC_STATUS_UNINIT; 543 if (bwn_bfp != 0) 544 mac->mac_flags |= BWN_MAC_FLAG_BADFRAME_PREEMP; 545 546 TASK_INIT(&mac->mac_hwreset, 0, bwn_hwreset, mac); 547 TASK_INIT(&mac->mac_intrtask, 0, bwn_intrtask, mac); 548 TASK_INIT(&mac->mac_txpower, 0, bwn_txpwr, mac); 549 550 error = bwn_attach_core(mac); 551 if (error) 552 goto fail0; 553 bwn_led_attach(mac); 554 555 device_printf(sc->sc_dev, "WLAN (chipid %#x rev %u) " 556 "PHY (analog %d type %d rev %d) RADIO (manuf %#x ver %#x rev %d)\n", 557 siba_get_chipid(sc->sc_dev), siba_get_revid(sc->sc_dev), 558 mac->mac_phy.analog, mac->mac_phy.type, mac->mac_phy.rev, 559 mac->mac_phy.rf_manuf, mac->mac_phy.rf_ver, 560 mac->mac_phy.rf_rev); 561 if (mac->mac_flags & BWN_MAC_FLAG_DMA) 562 device_printf(sc->sc_dev, "DMA (%d bits)\n", 563 mac->mac_method.dma.dmatype); 564 else 565 device_printf(sc->sc_dev, "PIO\n"); 566 567 #ifdef BWN_GPL_PHY 568 device_printf(sc->sc_dev, 569 "Note: compiled with BWN_GPL_PHY; includes GPLv2 code\n"); 570 #endif 571 572 /* 573 * setup PCI resources and interrupt. 574 */ 575 if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0) { 576 msic = pci_msi_count(dev); 577 if (bootverbose) 578 device_printf(sc->sc_dev, "MSI count : %d\n", msic); 579 } else 580 msic = 0; 581 582 mac->mac_intr_spec = bwn_res_spec_legacy; 583 if (msic == BWN_MSI_MESSAGES && bwn_msi_disable == 0) { 584 if (pci_alloc_msi(dev, &msic) == 0) { 585 device_printf(sc->sc_dev, 586 "Using %d MSI messages\n", msic); 587 mac->mac_intr_spec = bwn_res_spec_msi; 588 mac->mac_msi = 1; 589 } 590 } 591 592 error = bus_alloc_resources(dev, mac->mac_intr_spec, 593 mac->mac_res_irq); 594 if (error) { 595 device_printf(sc->sc_dev, 596 "couldn't allocate IRQ resources (%d)\n", error); 597 goto fail1; 598 } 599 600 if (mac->mac_msi == 0) 601 error = bus_setup_intr(dev, mac->mac_res_irq[0], 602 INTR_TYPE_NET | INTR_MPSAFE, bwn_intr, NULL, mac, 603 &mac->mac_intrhand[0]); 604 else { 605 for (i = 0; i < BWN_MSI_MESSAGES; i++) { 606 error = bus_setup_intr(dev, mac->mac_res_irq[i], 607 INTR_TYPE_NET | INTR_MPSAFE, bwn_intr, NULL, mac, 608 &mac->mac_intrhand[i]); 609 if (error != 0) { 610 device_printf(sc->sc_dev, 611 "couldn't setup interrupt (%d)\n", error); 612 break; 613 } 614 } 615 } 616 617 TAILQ_INSERT_TAIL(&sc->sc_maclist, mac, mac_list); 618 619 /* 620 * calls attach-post routine 621 */ 622 if ((sc->sc_flags & BWN_FLAG_ATTACHED) != 0) 623 bwn_attach_post(sc); 624 625 return (0); 626 fail1: 627 if (msic == BWN_MSI_MESSAGES && bwn_msi_disable == 0) 628 pci_release_msi(dev); 629 fail0: 630 free(mac, M_DEVBUF); 631 return (error); 632 } 633 634 static int 635 bwn_is_valid_ether_addr(uint8_t *addr) 636 { 637 char zero_addr[6] = { 0, 0, 0, 0, 0, 0 }; 638 639 if ((addr[0] & 1) || (!bcmp(addr, zero_addr, ETHER_ADDR_LEN))) 640 return (FALSE); 641 642 return (TRUE); 643 } 644 645 static int 646 bwn_attach_post(struct bwn_softc *sc) 647 { 648 struct ieee80211com *ic = &sc->sc_ic; 649 650 ic->ic_softc = sc; 651 ic->ic_name = device_get_nameunit(sc->sc_dev); 652 /* XXX not right but it's not used anywhere important */ 653 ic->ic_phytype = IEEE80211_T_OFDM; 654 ic->ic_opmode = IEEE80211_M_STA; 655 ic->ic_caps = 656 IEEE80211_C_STA /* station mode supported */ 657 | IEEE80211_C_MONITOR /* monitor mode */ 658 | IEEE80211_C_AHDEMO /* adhoc demo mode */ 659 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 660 | IEEE80211_C_SHSLOT /* short slot time supported */ 661 | IEEE80211_C_WME /* WME/WMM supported */ 662 | IEEE80211_C_WPA /* capable of WPA1+WPA2 */ 663 #if 0 664 | IEEE80211_C_BGSCAN /* capable of bg scanning */ 665 #endif 666 | IEEE80211_C_TXPMGT /* capable of txpow mgt */ 667 ; 668 669 ic->ic_flags_ext |= IEEE80211_FEXT_SWBMISS; /* s/w bmiss */ 670 671 IEEE80211_ADDR_COPY(ic->ic_macaddr, 672 bwn_is_valid_ether_addr(siba_sprom_get_mac_80211a(sc->sc_dev)) ? 673 siba_sprom_get_mac_80211a(sc->sc_dev) : 674 siba_sprom_get_mac_80211bg(sc->sc_dev)); 675 676 /* call MI attach routine. */ 677 ieee80211_ifattach(ic); 678 679 ic->ic_headroom = sizeof(struct bwn_txhdr); 680 681 /* override default methods */ 682 ic->ic_raw_xmit = bwn_raw_xmit; 683 ic->ic_updateslot = bwn_updateslot; 684 ic->ic_update_promisc = bwn_update_promisc; 685 ic->ic_wme.wme_update = bwn_wme_update; 686 ic->ic_scan_start = bwn_scan_start; 687 ic->ic_scan_end = bwn_scan_end; 688 ic->ic_set_channel = bwn_set_channel; 689 ic->ic_vap_create = bwn_vap_create; 690 ic->ic_vap_delete = bwn_vap_delete; 691 ic->ic_transmit = bwn_transmit; 692 ic->ic_parent = bwn_parent; 693 694 ieee80211_radiotap_attach(ic, 695 &sc->sc_tx_th.wt_ihdr, sizeof(sc->sc_tx_th), 696 BWN_TX_RADIOTAP_PRESENT, 697 &sc->sc_rx_th.wr_ihdr, sizeof(sc->sc_rx_th), 698 BWN_RX_RADIOTAP_PRESENT); 699 700 bwn_sysctl_node(sc); 701 702 if (bootverbose) 703 ieee80211_announce(ic); 704 return (0); 705 } 706 707 static void 708 bwn_phy_detach(struct bwn_mac *mac) 709 { 710 711 if (mac->mac_phy.detach != NULL) 712 mac->mac_phy.detach(mac); 713 } 714 715 static int 716 bwn_detach(device_t dev) 717 { 718 struct bwn_softc *sc = device_get_softc(dev); 719 struct bwn_mac *mac = sc->sc_curmac; 720 struct ieee80211com *ic = &sc->sc_ic; 721 int i; 722 723 sc->sc_flags |= BWN_FLAG_INVALID; 724 725 if (device_is_attached(sc->sc_dev)) { 726 BWN_LOCK(sc); 727 bwn_stop(sc); 728 BWN_UNLOCK(sc); 729 bwn_dma_free(mac); 730 callout_drain(&sc->sc_led_blink_ch); 731 callout_drain(&sc->sc_rfswitch_ch); 732 callout_drain(&sc->sc_task_ch); 733 callout_drain(&sc->sc_watchdog_ch); 734 bwn_phy_detach(mac); 735 ieee80211_draintask(ic, &mac->mac_hwreset); 736 ieee80211_draintask(ic, &mac->mac_txpower); 737 ieee80211_ifdetach(ic); 738 } 739 taskqueue_drain(sc->sc_tq, &mac->mac_intrtask); 740 taskqueue_free(sc->sc_tq); 741 742 for (i = 0; i < BWN_MSI_MESSAGES; i++) { 743 if (mac->mac_intrhand[i] != NULL) { 744 bus_teardown_intr(dev, mac->mac_res_irq[i], 745 mac->mac_intrhand[i]); 746 mac->mac_intrhand[i] = NULL; 747 } 748 } 749 bus_release_resources(dev, mac->mac_intr_spec, mac->mac_res_irq); 750 if (mac->mac_msi != 0) 751 pci_release_msi(dev); 752 mbufq_drain(&sc->sc_snd); 753 BWN_LOCK_DESTROY(sc); 754 return (0); 755 } 756 757 static void 758 bwn_attach_pre(struct bwn_softc *sc) 759 { 760 761 BWN_LOCK_INIT(sc); 762 TAILQ_INIT(&sc->sc_maclist); 763 callout_init_mtx(&sc->sc_rfswitch_ch, &sc->sc_mtx, 0); 764 callout_init_mtx(&sc->sc_task_ch, &sc->sc_mtx, 0); 765 callout_init_mtx(&sc->sc_watchdog_ch, &sc->sc_mtx, 0); 766 mbufq_init(&sc->sc_snd, ifqmaxlen); 767 sc->sc_tq = taskqueue_create_fast("bwn_taskq", M_NOWAIT, 768 taskqueue_thread_enqueue, &sc->sc_tq); 769 taskqueue_start_threads(&sc->sc_tq, 1, PI_NET, 770 "%s taskq", device_get_nameunit(sc->sc_dev)); 771 } 772 773 static void 774 bwn_sprom_bugfixes(device_t dev) 775 { 776 #define BWN_ISDEV(_vendor, _device, _subvendor, _subdevice) \ 777 ((siba_get_pci_vendor(dev) == PCI_VENDOR_##_vendor) && \ 778 (siba_get_pci_device(dev) == _device) && \ 779 (siba_get_pci_subvendor(dev) == PCI_VENDOR_##_subvendor) && \ 780 (siba_get_pci_subdevice(dev) == _subdevice)) 781 782 if (siba_get_pci_subvendor(dev) == PCI_VENDOR_APPLE && 783 siba_get_pci_subdevice(dev) == 0x4e && 784 siba_get_pci_revid(dev) > 0x40) 785 siba_sprom_set_bf_lo(dev, 786 siba_sprom_get_bf_lo(dev) | BWN_BFL_PACTRL); 787 if (siba_get_pci_subvendor(dev) == SIBA_BOARDVENDOR_DELL && 788 siba_get_chipid(dev) == 0x4301 && siba_get_pci_revid(dev) == 0x74) 789 siba_sprom_set_bf_lo(dev, 790 siba_sprom_get_bf_lo(dev) | BWN_BFL_BTCOEXIST); 791 if (siba_get_type(dev) == SIBA_TYPE_PCI) { 792 if (BWN_ISDEV(BROADCOM, 0x4318, ASUSTEK, 0x100f) || 793 BWN_ISDEV(BROADCOM, 0x4320, DELL, 0x0003) || 794 BWN_ISDEV(BROADCOM, 0x4320, HP, 0x12f8) || 795 BWN_ISDEV(BROADCOM, 0x4320, LINKSYS, 0x0013) || 796 BWN_ISDEV(BROADCOM, 0x4320, LINKSYS, 0x0014) || 797 BWN_ISDEV(BROADCOM, 0x4320, LINKSYS, 0x0015) || 798 BWN_ISDEV(BROADCOM, 0x4320, MOTOROLA, 0x7010)) 799 siba_sprom_set_bf_lo(dev, 800 siba_sprom_get_bf_lo(dev) & ~BWN_BFL_BTCOEXIST); 801 } 802 #undef BWN_ISDEV 803 } 804 805 static void 806 bwn_parent(struct ieee80211com *ic) 807 { 808 struct bwn_softc *sc = ic->ic_softc; 809 int startall = 0; 810 811 BWN_LOCK(sc); 812 if (ic->ic_nrunning > 0) { 813 if ((sc->sc_flags & BWN_FLAG_RUNNING) == 0) { 814 bwn_init(sc); 815 startall = 1; 816 } else 817 bwn_update_promisc(ic); 818 } else if (sc->sc_flags & BWN_FLAG_RUNNING) 819 bwn_stop(sc); 820 BWN_UNLOCK(sc); 821 822 if (startall) 823 ieee80211_start_all(ic); 824 } 825 826 static int 827 bwn_transmit(struct ieee80211com *ic, struct mbuf *m) 828 { 829 struct bwn_softc *sc = ic->ic_softc; 830 int error; 831 832 BWN_LOCK(sc); 833 if ((sc->sc_flags & BWN_FLAG_RUNNING) == 0) { 834 BWN_UNLOCK(sc); 835 return (ENXIO); 836 } 837 error = mbufq_enqueue(&sc->sc_snd, m); 838 if (error) { 839 BWN_UNLOCK(sc); 840 return (error); 841 } 842 bwn_start(sc); 843 BWN_UNLOCK(sc); 844 return (0); 845 } 846 847 static void 848 bwn_start(struct bwn_softc *sc) 849 { 850 struct bwn_mac *mac = sc->sc_curmac; 851 struct ieee80211_frame *wh; 852 struct ieee80211_node *ni; 853 struct ieee80211_key *k; 854 struct mbuf *m; 855 856 BWN_ASSERT_LOCKED(sc); 857 858 if ((sc->sc_flags & BWN_FLAG_RUNNING) == 0 || mac == NULL || 859 mac->mac_status < BWN_MAC_STATUS_STARTED) 860 return; 861 862 while ((m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 863 if (bwn_tx_isfull(sc, m)) 864 break; 865 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif; 866 if (ni == NULL) { 867 device_printf(sc->sc_dev, "unexpected NULL ni\n"); 868 m_freem(m); 869 counter_u64_add(sc->sc_ic.ic_oerrors, 1); 870 continue; 871 } 872 wh = mtod(m, struct ieee80211_frame *); 873 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 874 k = ieee80211_crypto_encap(ni, m); 875 if (k == NULL) { 876 if_inc_counter(ni->ni_vap->iv_ifp, 877 IFCOUNTER_OERRORS, 1); 878 ieee80211_free_node(ni); 879 m_freem(m); 880 continue; 881 } 882 } 883 wh = NULL; /* Catch any invalid use */ 884 if (bwn_tx_start(sc, ni, m) != 0) { 885 if (ni != NULL) { 886 if_inc_counter(ni->ni_vap->iv_ifp, 887 IFCOUNTER_OERRORS, 1); 888 ieee80211_free_node(ni); 889 } 890 continue; 891 } 892 sc->sc_watchdog_timer = 5; 893 } 894 } 895 896 static int 897 bwn_tx_isfull(struct bwn_softc *sc, struct mbuf *m) 898 { 899 struct bwn_dma_ring *dr; 900 struct bwn_mac *mac = sc->sc_curmac; 901 struct bwn_pio_txqueue *tq; 902 int pktlen = roundup(m->m_pkthdr.len + BWN_HDRSIZE(mac), 4); 903 904 BWN_ASSERT_LOCKED(sc); 905 906 if (mac->mac_flags & BWN_MAC_FLAG_DMA) { 907 dr = bwn_dma_select(mac, M_WME_GETAC(m)); 908 if (dr->dr_stop == 1 || 909 bwn_dma_freeslot(dr) < BWN_TX_SLOTS_PER_FRAME) { 910 dr->dr_stop = 1; 911 goto full; 912 } 913 } else { 914 tq = bwn_pio_select(mac, M_WME_GETAC(m)); 915 if (tq->tq_free == 0 || pktlen > tq->tq_size || 916 pktlen > (tq->tq_size - tq->tq_used)) 917 goto full; 918 } 919 return (0); 920 full: 921 mbufq_prepend(&sc->sc_snd, m); 922 return (1); 923 } 924 925 static int 926 bwn_tx_start(struct bwn_softc *sc, struct ieee80211_node *ni, struct mbuf *m) 927 { 928 struct bwn_mac *mac = sc->sc_curmac; 929 int error; 930 931 BWN_ASSERT_LOCKED(sc); 932 933 if (m->m_pkthdr.len < IEEE80211_MIN_LEN || mac == NULL) { 934 m_freem(m); 935 return (ENXIO); 936 } 937 938 error = (mac->mac_flags & BWN_MAC_FLAG_DMA) ? 939 bwn_dma_tx_start(mac, ni, m) : bwn_pio_tx_start(mac, ni, m); 940 if (error) { 941 m_freem(m); 942 return (error); 943 } 944 return (0); 945 } 946 947 static int 948 bwn_pio_tx_start(struct bwn_mac *mac, struct ieee80211_node *ni, struct mbuf *m) 949 { 950 struct bwn_pio_txpkt *tp; 951 struct bwn_pio_txqueue *tq = bwn_pio_select(mac, M_WME_GETAC(m)); 952 struct bwn_softc *sc = mac->mac_sc; 953 struct bwn_txhdr txhdr; 954 struct mbuf *m_new; 955 uint32_t ctl32; 956 int error; 957 uint16_t ctl16; 958 959 BWN_ASSERT_LOCKED(sc); 960 961 /* XXX TODO send packets after DTIM */ 962 963 KASSERT(!TAILQ_EMPTY(&tq->tq_pktlist), ("%s: fail", __func__)); 964 tp = TAILQ_FIRST(&tq->tq_pktlist); 965 tp->tp_ni = ni; 966 tp->tp_m = m; 967 968 error = bwn_set_txhdr(mac, ni, m, &txhdr, BWN_PIO_COOKIE(tq, tp)); 969 if (error) { 970 device_printf(sc->sc_dev, "tx fail\n"); 971 return (error); 972 } 973 974 TAILQ_REMOVE(&tq->tq_pktlist, tp, tp_list); 975 tq->tq_used += roundup(m->m_pkthdr.len + BWN_HDRSIZE(mac), 4); 976 tq->tq_free--; 977 978 if (siba_get_revid(sc->sc_dev) >= 8) { 979 /* 980 * XXX please removes m_defrag(9) 981 */ 982 m_new = m_defrag(m, M_NOWAIT); 983 if (m_new == NULL) { 984 device_printf(sc->sc_dev, 985 "%s: can't defrag TX buffer\n", 986 __func__); 987 return (ENOBUFS); 988 } 989 if (m_new->m_next != NULL) 990 device_printf(sc->sc_dev, 991 "TODO: fragmented packets for PIO\n"); 992 tp->tp_m = m_new; 993 994 /* send HEADER */ 995 ctl32 = bwn_pio_write_multi_4(mac, tq, 996 (BWN_PIO_READ_4(mac, tq, BWN_PIO8_TXCTL) | 997 BWN_PIO8_TXCTL_FRAMEREADY) & ~BWN_PIO8_TXCTL_EOF, 998 (const uint8_t *)&txhdr, BWN_HDRSIZE(mac)); 999 /* send BODY */ 1000 ctl32 = bwn_pio_write_multi_4(mac, tq, ctl32, 1001 mtod(m_new, const void *), m_new->m_pkthdr.len); 1002 bwn_pio_write_4(mac, tq, BWN_PIO_TXCTL, 1003 ctl32 | BWN_PIO8_TXCTL_EOF); 1004 } else { 1005 ctl16 = bwn_pio_write_multi_2(mac, tq, 1006 (bwn_pio_read_2(mac, tq, BWN_PIO_TXCTL) | 1007 BWN_PIO_TXCTL_FRAMEREADY) & ~BWN_PIO_TXCTL_EOF, 1008 (const uint8_t *)&txhdr, BWN_HDRSIZE(mac)); 1009 ctl16 = bwn_pio_write_mbuf_2(mac, tq, ctl16, m); 1010 BWN_PIO_WRITE_2(mac, tq, BWN_PIO_TXCTL, 1011 ctl16 | BWN_PIO_TXCTL_EOF); 1012 } 1013 1014 return (0); 1015 } 1016 1017 static struct bwn_pio_txqueue * 1018 bwn_pio_select(struct bwn_mac *mac, uint8_t prio) 1019 { 1020 1021 if ((mac->mac_flags & BWN_MAC_FLAG_WME) == 0) 1022 return (&mac->mac_method.pio.wme[WME_AC_BE]); 1023 1024 switch (prio) { 1025 case 0: 1026 return (&mac->mac_method.pio.wme[WME_AC_BE]); 1027 case 1: 1028 return (&mac->mac_method.pio.wme[WME_AC_BK]); 1029 case 2: 1030 return (&mac->mac_method.pio.wme[WME_AC_VI]); 1031 case 3: 1032 return (&mac->mac_method.pio.wme[WME_AC_VO]); 1033 } 1034 KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__)); 1035 return (NULL); 1036 } 1037 1038 static int 1039 bwn_dma_tx_start(struct bwn_mac *mac, struct ieee80211_node *ni, struct mbuf *m) 1040 { 1041 #define BWN_GET_TXHDRCACHE(slot) \ 1042 &(txhdr_cache[(slot / BWN_TX_SLOTS_PER_FRAME) * BWN_HDRSIZE(mac)]) 1043 struct bwn_dma *dma = &mac->mac_method.dma; 1044 struct bwn_dma_ring *dr = bwn_dma_select(mac, M_WME_GETAC(m)); 1045 struct bwn_dmadesc_generic *desc; 1046 struct bwn_dmadesc_meta *mt; 1047 struct bwn_softc *sc = mac->mac_sc; 1048 uint8_t *txhdr_cache = (uint8_t *)dr->dr_txhdr_cache; 1049 int error, slot, backup[2] = { dr->dr_curslot, dr->dr_usedslot }; 1050 1051 BWN_ASSERT_LOCKED(sc); 1052 KASSERT(!dr->dr_stop, ("%s:%d: fail", __func__, __LINE__)); 1053 1054 /* XXX send after DTIM */ 1055 1056 slot = bwn_dma_getslot(dr); 1057 dr->getdesc(dr, slot, &desc, &mt); 1058 KASSERT(mt->mt_txtype == BWN_DMADESC_METATYPE_HEADER, 1059 ("%s:%d: fail", __func__, __LINE__)); 1060 1061 error = bwn_set_txhdr(dr->dr_mac, ni, m, 1062 (struct bwn_txhdr *)BWN_GET_TXHDRCACHE(slot), 1063 BWN_DMA_COOKIE(dr, slot)); 1064 if (error) 1065 goto fail; 1066 error = bus_dmamap_load(dr->dr_txring_dtag, mt->mt_dmap, 1067 BWN_GET_TXHDRCACHE(slot), BWN_HDRSIZE(mac), bwn_dma_ring_addr, 1068 &mt->mt_paddr, BUS_DMA_NOWAIT); 1069 if (error) { 1070 device_printf(sc->sc_dev, "%s: can't load TX buffer (1) %d\n", 1071 __func__, error); 1072 goto fail; 1073 } 1074 bus_dmamap_sync(dr->dr_txring_dtag, mt->mt_dmap, 1075 BUS_DMASYNC_PREWRITE); 1076 dr->setdesc(dr, desc, mt->mt_paddr, BWN_HDRSIZE(mac), 1, 0, 0); 1077 bus_dmamap_sync(dr->dr_ring_dtag, dr->dr_ring_dmap, 1078 BUS_DMASYNC_PREWRITE); 1079 1080 slot = bwn_dma_getslot(dr); 1081 dr->getdesc(dr, slot, &desc, &mt); 1082 KASSERT(mt->mt_txtype == BWN_DMADESC_METATYPE_BODY && 1083 mt->mt_islast == 1, ("%s:%d: fail", __func__, __LINE__)); 1084 mt->mt_m = m; 1085 mt->mt_ni = ni; 1086 1087 error = bus_dmamap_load_mbuf(dma->txbuf_dtag, mt->mt_dmap, m, 1088 bwn_dma_buf_addr, &mt->mt_paddr, BUS_DMA_NOWAIT); 1089 if (error && error != EFBIG) { 1090 device_printf(sc->sc_dev, "%s: can't load TX buffer (1) %d\n", 1091 __func__, error); 1092 goto fail; 1093 } 1094 if (error) { /* error == EFBIG */ 1095 struct mbuf *m_new; 1096 1097 m_new = m_defrag(m, M_NOWAIT); 1098 if (m_new == NULL) { 1099 device_printf(sc->sc_dev, 1100 "%s: can't defrag TX buffer\n", 1101 __func__); 1102 error = ENOBUFS; 1103 goto fail; 1104 } else { 1105 m = m_new; 1106 } 1107 1108 mt->mt_m = m; 1109 error = bus_dmamap_load_mbuf(dma->txbuf_dtag, mt->mt_dmap, 1110 m, bwn_dma_buf_addr, &mt->mt_paddr, BUS_DMA_NOWAIT); 1111 if (error) { 1112 device_printf(sc->sc_dev, 1113 "%s: can't load TX buffer (2) %d\n", 1114 __func__, error); 1115 goto fail; 1116 } 1117 } 1118 bus_dmamap_sync(dma->txbuf_dtag, mt->mt_dmap, BUS_DMASYNC_PREWRITE); 1119 dr->setdesc(dr, desc, mt->mt_paddr, m->m_pkthdr.len, 0, 1, 1); 1120 bus_dmamap_sync(dr->dr_ring_dtag, dr->dr_ring_dmap, 1121 BUS_DMASYNC_PREWRITE); 1122 1123 /* XXX send after DTIM */ 1124 1125 dr->start_transfer(dr, bwn_dma_nextslot(dr, slot)); 1126 return (0); 1127 fail: 1128 dr->dr_curslot = backup[0]; 1129 dr->dr_usedslot = backup[1]; 1130 return (error); 1131 #undef BWN_GET_TXHDRCACHE 1132 } 1133 1134 static void 1135 bwn_watchdog(void *arg) 1136 { 1137 struct bwn_softc *sc = arg; 1138 1139 if (sc->sc_watchdog_timer != 0 && --sc->sc_watchdog_timer == 0) { 1140 device_printf(sc->sc_dev, "device timeout\n"); 1141 counter_u64_add(sc->sc_ic.ic_oerrors, 1); 1142 } 1143 callout_schedule(&sc->sc_watchdog_ch, hz); 1144 } 1145 1146 static int 1147 bwn_attach_core(struct bwn_mac *mac) 1148 { 1149 struct bwn_softc *sc = mac->mac_sc; 1150 int error, have_bg = 0, have_a = 0; 1151 uint32_t high; 1152 1153 KASSERT(siba_get_revid(sc->sc_dev) >= 5, 1154 ("unsupported revision %d", siba_get_revid(sc->sc_dev))); 1155 1156 siba_powerup(sc->sc_dev, 0); 1157 1158 high = siba_read_4(sc->sc_dev, SIBA_TGSHIGH); 1159 1160 /* 1161 * Guess at whether it has A-PHY or G-PHY. 1162 * This is just used for resetting the core to probe things; 1163 * we will re-guess once it's all up and working. 1164 * 1165 * XXX TODO: there's the TGSHIGH DUALPHY flag based on 1166 * the PHY revision. 1167 */ 1168 bwn_reset_core(mac, !!(high & BWN_TGSHIGH_HAVE_2GHZ)); 1169 1170 /* 1171 * Get the PHY version. 1172 */ 1173 error = bwn_phy_getinfo(mac, high); 1174 if (error) 1175 goto fail; 1176 1177 /* XXX TODO need bhnd */ 1178 if (bwn_is_bus_siba(mac)) { 1179 have_a = (high & BWN_TGSHIGH_HAVE_5GHZ) ? 1 : 0; 1180 have_bg = (high & BWN_TGSHIGH_HAVE_2GHZ) ? 1 : 0; 1181 if (high & BWN_TGSHIGH_DUALPHY) { 1182 have_bg = 1; 1183 have_a = 1; 1184 } 1185 } else { 1186 device_printf(sc->sc_dev, "%s: not siba; bailing\n", __func__); 1187 error = ENXIO; 1188 goto fail; 1189 } 1190 1191 #if 0 1192 device_printf(sc->sc_dev, "%s: high=0x%08x, have_a=%d, have_bg=%d," 1193 " deviceid=0x%04x, siba_deviceid=0x%04x\n", 1194 __func__, 1195 high, 1196 have_a, 1197 have_bg, 1198 siba_get_pci_device(sc->sc_dev), 1199 siba_get_chipid(sc->sc_dev)); 1200 #endif 1201 1202 if (siba_get_pci_device(sc->sc_dev) != 0x4312 && 1203 siba_get_pci_device(sc->sc_dev) != 0x4319 && 1204 siba_get_pci_device(sc->sc_dev) != 0x4324 && 1205 siba_get_pci_device(sc->sc_dev) != 0x4328 && 1206 siba_get_pci_device(sc->sc_dev) != 0x432b) { 1207 have_a = have_bg = 0; 1208 if (mac->mac_phy.type == BWN_PHYTYPE_A) 1209 have_a = 1; 1210 else if (mac->mac_phy.type == BWN_PHYTYPE_G || 1211 mac->mac_phy.type == BWN_PHYTYPE_N || 1212 mac->mac_phy.type == BWN_PHYTYPE_LP) 1213 have_bg = 1; 1214 else 1215 KASSERT(0 == 1, ("%s: unknown phy type (%d)", __func__, 1216 mac->mac_phy.type)); 1217 } 1218 1219 /* 1220 * XXX The PHY-G support doesn't do 5GHz operation. 1221 */ 1222 if (mac->mac_phy.type != BWN_PHYTYPE_LP && 1223 mac->mac_phy.type != BWN_PHYTYPE_N) { 1224 device_printf(sc->sc_dev, 1225 "%s: forcing 2GHz only; no dual-band support for PHY\n", 1226 __func__); 1227 have_a = 0; 1228 have_bg = 1; 1229 } 1230 1231 mac->mac_phy.phy_n = NULL; 1232 1233 if (mac->mac_phy.type == BWN_PHYTYPE_G) { 1234 mac->mac_phy.attach = bwn_phy_g_attach; 1235 mac->mac_phy.detach = bwn_phy_g_detach; 1236 mac->mac_phy.prepare_hw = bwn_phy_g_prepare_hw; 1237 mac->mac_phy.init_pre = bwn_phy_g_init_pre; 1238 mac->mac_phy.init = bwn_phy_g_init; 1239 mac->mac_phy.exit = bwn_phy_g_exit; 1240 mac->mac_phy.phy_read = bwn_phy_g_read; 1241 mac->mac_phy.phy_write = bwn_phy_g_write; 1242 mac->mac_phy.rf_read = bwn_phy_g_rf_read; 1243 mac->mac_phy.rf_write = bwn_phy_g_rf_write; 1244 mac->mac_phy.use_hwpctl = bwn_phy_g_hwpctl; 1245 mac->mac_phy.rf_onoff = bwn_phy_g_rf_onoff; 1246 mac->mac_phy.switch_analog = bwn_phy_switch_analog; 1247 mac->mac_phy.switch_channel = bwn_phy_g_switch_channel; 1248 mac->mac_phy.get_default_chan = bwn_phy_g_get_default_chan; 1249 mac->mac_phy.set_antenna = bwn_phy_g_set_antenna; 1250 mac->mac_phy.set_im = bwn_phy_g_im; 1251 mac->mac_phy.recalc_txpwr = bwn_phy_g_recalc_txpwr; 1252 mac->mac_phy.set_txpwr = bwn_phy_g_set_txpwr; 1253 mac->mac_phy.task_15s = bwn_phy_g_task_15s; 1254 mac->mac_phy.task_60s = bwn_phy_g_task_60s; 1255 } else if (mac->mac_phy.type == BWN_PHYTYPE_LP) { 1256 mac->mac_phy.init_pre = bwn_phy_lp_init_pre; 1257 mac->mac_phy.init = bwn_phy_lp_init; 1258 mac->mac_phy.phy_read = bwn_phy_lp_read; 1259 mac->mac_phy.phy_write = bwn_phy_lp_write; 1260 mac->mac_phy.phy_maskset = bwn_phy_lp_maskset; 1261 mac->mac_phy.rf_read = bwn_phy_lp_rf_read; 1262 mac->mac_phy.rf_write = bwn_phy_lp_rf_write; 1263 mac->mac_phy.rf_onoff = bwn_phy_lp_rf_onoff; 1264 mac->mac_phy.switch_analog = bwn_phy_lp_switch_analog; 1265 mac->mac_phy.switch_channel = bwn_phy_lp_switch_channel; 1266 mac->mac_phy.get_default_chan = bwn_phy_lp_get_default_chan; 1267 mac->mac_phy.set_antenna = bwn_phy_lp_set_antenna; 1268 mac->mac_phy.task_60s = bwn_phy_lp_task_60s; 1269 } else if (mac->mac_phy.type == BWN_PHYTYPE_N) { 1270 mac->mac_phy.attach = bwn_phy_n_attach; 1271 mac->mac_phy.detach = bwn_phy_n_detach; 1272 mac->mac_phy.prepare_hw = bwn_phy_n_prepare_hw; 1273 mac->mac_phy.init_pre = bwn_phy_n_init_pre; 1274 mac->mac_phy.init = bwn_phy_n_init; 1275 mac->mac_phy.exit = bwn_phy_n_exit; 1276 mac->mac_phy.phy_read = bwn_phy_n_read; 1277 mac->mac_phy.phy_write = bwn_phy_n_write; 1278 mac->mac_phy.rf_read = bwn_phy_n_rf_read; 1279 mac->mac_phy.rf_write = bwn_phy_n_rf_write; 1280 mac->mac_phy.use_hwpctl = bwn_phy_n_hwpctl; 1281 mac->mac_phy.rf_onoff = bwn_phy_n_rf_onoff; 1282 mac->mac_phy.switch_analog = bwn_phy_n_switch_analog; 1283 mac->mac_phy.switch_channel = bwn_phy_n_switch_channel; 1284 mac->mac_phy.get_default_chan = bwn_phy_n_get_default_chan; 1285 mac->mac_phy.set_antenna = bwn_phy_n_set_antenna; 1286 mac->mac_phy.set_im = bwn_phy_n_im; 1287 mac->mac_phy.recalc_txpwr = bwn_phy_n_recalc_txpwr; 1288 mac->mac_phy.set_txpwr = bwn_phy_n_set_txpwr; 1289 mac->mac_phy.task_15s = bwn_phy_n_task_15s; 1290 mac->mac_phy.task_60s = bwn_phy_n_task_60s; 1291 } else { 1292 device_printf(sc->sc_dev, "unsupported PHY type (%d)\n", 1293 mac->mac_phy.type); 1294 error = ENXIO; 1295 goto fail; 1296 } 1297 1298 mac->mac_phy.gmode = have_bg; 1299 if (mac->mac_phy.attach != NULL) { 1300 error = mac->mac_phy.attach(mac); 1301 if (error) { 1302 device_printf(sc->sc_dev, "failed\n"); 1303 goto fail; 1304 } 1305 } 1306 1307 bwn_reset_core(mac, have_bg); 1308 1309 error = bwn_chiptest(mac); 1310 if (error) 1311 goto fail; 1312 error = bwn_setup_channels(mac, have_bg, have_a); 1313 if (error) { 1314 device_printf(sc->sc_dev, "failed to setup channels\n"); 1315 goto fail; 1316 } 1317 1318 if (sc->sc_curmac == NULL) 1319 sc->sc_curmac = mac; 1320 1321 error = bwn_dma_attach(mac); 1322 if (error != 0) { 1323 device_printf(sc->sc_dev, "failed to initialize DMA\n"); 1324 goto fail; 1325 } 1326 1327 mac->mac_phy.switch_analog(mac, 0); 1328 1329 siba_dev_down(sc->sc_dev, 0); 1330 fail: 1331 siba_powerdown(sc->sc_dev); 1332 return (error); 1333 } 1334 1335 /* 1336 * Reset - SIBA. 1337 * 1338 * XXX TODO: implement BCMA version! 1339 */ 1340 void 1341 bwn_reset_core(struct bwn_mac *mac, int g_mode) 1342 { 1343 struct bwn_softc *sc = mac->mac_sc; 1344 uint32_t low, ctl; 1345 uint32_t flags = 0; 1346 1347 DPRINTF(sc, BWN_DEBUG_RESET, "%s: g_mode=%d\n", __func__, g_mode); 1348 1349 flags |= (BWN_TGSLOW_PHYCLOCK_ENABLE | BWN_TGSLOW_PHYRESET); 1350 if (g_mode) 1351 flags |= BWN_TGSLOW_SUPPORT_G; 1352 1353 /* XXX N-PHY only; and hard-code to 20MHz for now */ 1354 if (mac->mac_phy.type == BWN_PHYTYPE_N) 1355 flags |= BWN_TGSLOW_PHY_BANDWIDTH_20MHZ; 1356 1357 siba_dev_up(sc->sc_dev, flags); 1358 DELAY(2000); 1359 1360 /* Take PHY out of reset */ 1361 low = (siba_read_4(sc->sc_dev, SIBA_TGSLOW) | SIBA_TGSLOW_FGC) & 1362 ~(BWN_TGSLOW_PHYRESET | BWN_TGSLOW_PHYCLOCK_ENABLE); 1363 siba_write_4(sc->sc_dev, SIBA_TGSLOW, low); 1364 siba_read_4(sc->sc_dev, SIBA_TGSLOW); 1365 DELAY(2000); 1366 low &= ~SIBA_TGSLOW_FGC; 1367 low |= BWN_TGSLOW_PHYCLOCK_ENABLE; 1368 siba_write_4(sc->sc_dev, SIBA_TGSLOW, low); 1369 siba_read_4(sc->sc_dev, SIBA_TGSLOW); 1370 DELAY(2000); 1371 1372 if (mac->mac_phy.switch_analog != NULL) 1373 mac->mac_phy.switch_analog(mac, 1); 1374 1375 ctl = BWN_READ_4(mac, BWN_MACCTL) & ~BWN_MACCTL_GMODE; 1376 if (g_mode) 1377 ctl |= BWN_MACCTL_GMODE; 1378 BWN_WRITE_4(mac, BWN_MACCTL, ctl | BWN_MACCTL_IHR_ON); 1379 } 1380 1381 static int 1382 bwn_phy_getinfo(struct bwn_mac *mac, int tgshigh) 1383 { 1384 struct bwn_phy *phy = &mac->mac_phy; 1385 struct bwn_softc *sc = mac->mac_sc; 1386 uint32_t tmp; 1387 1388 /* PHY */ 1389 tmp = BWN_READ_2(mac, BWN_PHYVER); 1390 phy->gmode = !! (tgshigh & BWN_TGSHIGH_HAVE_2GHZ); 1391 phy->rf_on = 1; 1392 phy->analog = (tmp & BWN_PHYVER_ANALOG) >> 12; 1393 phy->type = (tmp & BWN_PHYVER_TYPE) >> 8; 1394 phy->rev = (tmp & BWN_PHYVER_VERSION); 1395 if ((phy->type == BWN_PHYTYPE_A && phy->rev >= 4) || 1396 (phy->type == BWN_PHYTYPE_B && phy->rev != 2 && 1397 phy->rev != 4 && phy->rev != 6 && phy->rev != 7) || 1398 (phy->type == BWN_PHYTYPE_G && phy->rev > 9) || 1399 (phy->type == BWN_PHYTYPE_N && phy->rev > 4) || 1400 (phy->type == BWN_PHYTYPE_LP && phy->rev > 2)) 1401 goto unsupphy; 1402 1403 /* RADIO */ 1404 if (siba_get_chipid(sc->sc_dev) == 0x4317) { 1405 if (siba_get_chiprev(sc->sc_dev) == 0) 1406 tmp = 0x3205017f; 1407 else if (siba_get_chiprev(sc->sc_dev) == 1) 1408 tmp = 0x4205017f; 1409 else 1410 tmp = 0x5205017f; 1411 } else { 1412 BWN_WRITE_2(mac, BWN_RFCTL, BWN_RFCTL_ID); 1413 tmp = BWN_READ_2(mac, BWN_RFDATALO); 1414 BWN_WRITE_2(mac, BWN_RFCTL, BWN_RFCTL_ID); 1415 tmp |= (uint32_t)BWN_READ_2(mac, BWN_RFDATAHI) << 16; 1416 } 1417 phy->rf_rev = (tmp & 0xf0000000) >> 28; 1418 phy->rf_ver = (tmp & 0x0ffff000) >> 12; 1419 phy->rf_manuf = (tmp & 0x00000fff); 1420 1421 /* 1422 * For now, just always do full init (ie, what bwn has traditionally 1423 * done) 1424 */ 1425 phy->phy_do_full_init = 1; 1426 1427 if (phy->rf_manuf != 0x17f) /* 0x17f is broadcom */ 1428 goto unsupradio; 1429 if ((phy->type == BWN_PHYTYPE_A && (phy->rf_ver != 0x2060 || 1430 phy->rf_rev != 1 || phy->rf_manuf != 0x17f)) || 1431 (phy->type == BWN_PHYTYPE_B && (phy->rf_ver & 0xfff0) != 0x2050) || 1432 (phy->type == BWN_PHYTYPE_G && phy->rf_ver != 0x2050) || 1433 (phy->type == BWN_PHYTYPE_N && 1434 phy->rf_ver != 0x2055 && phy->rf_ver != 0x2056) || 1435 (phy->type == BWN_PHYTYPE_LP && 1436 phy->rf_ver != 0x2062 && phy->rf_ver != 0x2063)) 1437 goto unsupradio; 1438 1439 return (0); 1440 unsupphy: 1441 device_printf(sc->sc_dev, "unsupported PHY (type %#x, rev %#x, " 1442 "analog %#x)\n", 1443 phy->type, phy->rev, phy->analog); 1444 return (ENXIO); 1445 unsupradio: 1446 device_printf(sc->sc_dev, "unsupported radio (manuf %#x, ver %#x, " 1447 "rev %#x)\n", 1448 phy->rf_manuf, phy->rf_ver, phy->rf_rev); 1449 return (ENXIO); 1450 } 1451 1452 static int 1453 bwn_chiptest(struct bwn_mac *mac) 1454 { 1455 #define TESTVAL0 0x55aaaa55 1456 #define TESTVAL1 0xaa5555aa 1457 struct bwn_softc *sc = mac->mac_sc; 1458 uint32_t v, backup; 1459 1460 BWN_LOCK(sc); 1461 1462 backup = bwn_shm_read_4(mac, BWN_SHARED, 0); 1463 1464 bwn_shm_write_4(mac, BWN_SHARED, 0, TESTVAL0); 1465 if (bwn_shm_read_4(mac, BWN_SHARED, 0) != TESTVAL0) 1466 goto error; 1467 bwn_shm_write_4(mac, BWN_SHARED, 0, TESTVAL1); 1468 if (bwn_shm_read_4(mac, BWN_SHARED, 0) != TESTVAL1) 1469 goto error; 1470 1471 bwn_shm_write_4(mac, BWN_SHARED, 0, backup); 1472 1473 if ((siba_get_revid(sc->sc_dev) >= 3) && 1474 (siba_get_revid(sc->sc_dev) <= 10)) { 1475 BWN_WRITE_2(mac, BWN_TSF_CFP_START, 0xaaaa); 1476 BWN_WRITE_4(mac, BWN_TSF_CFP_START, 0xccccbbbb); 1477 if (BWN_READ_2(mac, BWN_TSF_CFP_START_LOW) != 0xbbbb) 1478 goto error; 1479 if (BWN_READ_2(mac, BWN_TSF_CFP_START_HIGH) != 0xcccc) 1480 goto error; 1481 } 1482 BWN_WRITE_4(mac, BWN_TSF_CFP_START, 0); 1483 1484 v = BWN_READ_4(mac, BWN_MACCTL) | BWN_MACCTL_GMODE; 1485 if (v != (BWN_MACCTL_GMODE | BWN_MACCTL_IHR_ON)) 1486 goto error; 1487 1488 BWN_UNLOCK(sc); 1489 return (0); 1490 error: 1491 BWN_UNLOCK(sc); 1492 device_printf(sc->sc_dev, "failed to validate the chipaccess\n"); 1493 return (ENODEV); 1494 } 1495 1496 static int 1497 bwn_setup_channels(struct bwn_mac *mac, int have_bg, int have_a) 1498 { 1499 struct bwn_softc *sc = mac->mac_sc; 1500 struct ieee80211com *ic = &sc->sc_ic; 1501 uint8_t bands[IEEE80211_MODE_BYTES]; 1502 1503 memset(ic->ic_channels, 0, sizeof(ic->ic_channels)); 1504 ic->ic_nchans = 0; 1505 1506 DPRINTF(sc, BWN_DEBUG_EEPROM, "%s: called; bg=%d, a=%d\n", 1507 __func__, 1508 have_bg, 1509 have_a); 1510 1511 if (have_bg) { 1512 memset(bands, 0, sizeof(bands)); 1513 setbit(bands, IEEE80211_MODE_11B); 1514 setbit(bands, IEEE80211_MODE_11G); 1515 bwn_addchannels(ic->ic_channels, IEEE80211_CHAN_MAX, 1516 &ic->ic_nchans, &bwn_chantable_bg, bands); 1517 } 1518 1519 if (have_a) { 1520 memset(bands, 0, sizeof(bands)); 1521 setbit(bands, IEEE80211_MODE_11A); 1522 bwn_addchannels(ic->ic_channels, IEEE80211_CHAN_MAX, 1523 &ic->ic_nchans, &bwn_chantable_a, bands); 1524 } 1525 1526 mac->mac_phy.supports_2ghz = have_bg; 1527 mac->mac_phy.supports_5ghz = have_a; 1528 1529 return (ic->ic_nchans == 0 ? ENXIO : 0); 1530 } 1531 1532 uint32_t 1533 bwn_shm_read_4(struct bwn_mac *mac, uint16_t way, uint16_t offset) 1534 { 1535 uint32_t ret; 1536 1537 BWN_ASSERT_LOCKED(mac->mac_sc); 1538 1539 if (way == BWN_SHARED) { 1540 KASSERT((offset & 0x0001) == 0, 1541 ("%s:%d warn", __func__, __LINE__)); 1542 if (offset & 0x0003) { 1543 bwn_shm_ctlword(mac, way, offset >> 2); 1544 ret = BWN_READ_2(mac, BWN_SHM_DATA_UNALIGNED); 1545 ret <<= 16; 1546 bwn_shm_ctlword(mac, way, (offset >> 2) + 1); 1547 ret |= BWN_READ_2(mac, BWN_SHM_DATA); 1548 goto out; 1549 } 1550 offset >>= 2; 1551 } 1552 bwn_shm_ctlword(mac, way, offset); 1553 ret = BWN_READ_4(mac, BWN_SHM_DATA); 1554 out: 1555 return (ret); 1556 } 1557 1558 uint16_t 1559 bwn_shm_read_2(struct bwn_mac *mac, uint16_t way, uint16_t offset) 1560 { 1561 uint16_t ret; 1562 1563 BWN_ASSERT_LOCKED(mac->mac_sc); 1564 1565 if (way == BWN_SHARED) { 1566 KASSERT((offset & 0x0001) == 0, 1567 ("%s:%d warn", __func__, __LINE__)); 1568 if (offset & 0x0003) { 1569 bwn_shm_ctlword(mac, way, offset >> 2); 1570 ret = BWN_READ_2(mac, BWN_SHM_DATA_UNALIGNED); 1571 goto out; 1572 } 1573 offset >>= 2; 1574 } 1575 bwn_shm_ctlword(mac, way, offset); 1576 ret = BWN_READ_2(mac, BWN_SHM_DATA); 1577 out: 1578 1579 return (ret); 1580 } 1581 1582 static void 1583 bwn_shm_ctlword(struct bwn_mac *mac, uint16_t way, 1584 uint16_t offset) 1585 { 1586 uint32_t control; 1587 1588 control = way; 1589 control <<= 16; 1590 control |= offset; 1591 BWN_WRITE_4(mac, BWN_SHM_CONTROL, control); 1592 } 1593 1594 void 1595 bwn_shm_write_4(struct bwn_mac *mac, uint16_t way, uint16_t offset, 1596 uint32_t value) 1597 { 1598 BWN_ASSERT_LOCKED(mac->mac_sc); 1599 1600 if (way == BWN_SHARED) { 1601 KASSERT((offset & 0x0001) == 0, 1602 ("%s:%d warn", __func__, __LINE__)); 1603 if (offset & 0x0003) { 1604 bwn_shm_ctlword(mac, way, offset >> 2); 1605 BWN_WRITE_2(mac, BWN_SHM_DATA_UNALIGNED, 1606 (value >> 16) & 0xffff); 1607 bwn_shm_ctlword(mac, way, (offset >> 2) + 1); 1608 BWN_WRITE_2(mac, BWN_SHM_DATA, value & 0xffff); 1609 return; 1610 } 1611 offset >>= 2; 1612 } 1613 bwn_shm_ctlword(mac, way, offset); 1614 BWN_WRITE_4(mac, BWN_SHM_DATA, value); 1615 } 1616 1617 void 1618 bwn_shm_write_2(struct bwn_mac *mac, uint16_t way, uint16_t offset, 1619 uint16_t value) 1620 { 1621 BWN_ASSERT_LOCKED(mac->mac_sc); 1622 1623 if (way == BWN_SHARED) { 1624 KASSERT((offset & 0x0001) == 0, 1625 ("%s:%d warn", __func__, __LINE__)); 1626 if (offset & 0x0003) { 1627 bwn_shm_ctlword(mac, way, offset >> 2); 1628 BWN_WRITE_2(mac, BWN_SHM_DATA_UNALIGNED, value); 1629 return; 1630 } 1631 offset >>= 2; 1632 } 1633 bwn_shm_ctlword(mac, way, offset); 1634 BWN_WRITE_2(mac, BWN_SHM_DATA, value); 1635 } 1636 1637 static void 1638 bwn_addchannels(struct ieee80211_channel chans[], int maxchans, int *nchans, 1639 const struct bwn_channelinfo *ci, const uint8_t bands[]) 1640 { 1641 int i, error; 1642 1643 for (i = 0, error = 0; i < ci->nchannels && error == 0; i++) { 1644 const struct bwn_channel *hc = &ci->channels[i]; 1645 1646 error = ieee80211_add_channel(chans, maxchans, nchans, 1647 hc->ieee, hc->freq, hc->maxTxPow, 0, bands); 1648 } 1649 } 1650 1651 static int 1652 bwn_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 1653 const struct ieee80211_bpf_params *params) 1654 { 1655 struct ieee80211com *ic = ni->ni_ic; 1656 struct bwn_softc *sc = ic->ic_softc; 1657 struct bwn_mac *mac = sc->sc_curmac; 1658 int error; 1659 1660 if ((sc->sc_flags & BWN_FLAG_RUNNING) == 0 || 1661 mac->mac_status < BWN_MAC_STATUS_STARTED) { 1662 m_freem(m); 1663 return (ENETDOWN); 1664 } 1665 1666 BWN_LOCK(sc); 1667 if (bwn_tx_isfull(sc, m)) { 1668 m_freem(m); 1669 BWN_UNLOCK(sc); 1670 return (ENOBUFS); 1671 } 1672 1673 error = bwn_tx_start(sc, ni, m); 1674 if (error == 0) 1675 sc->sc_watchdog_timer = 5; 1676 BWN_UNLOCK(sc); 1677 return (error); 1678 } 1679 1680 /* 1681 * Callback from the 802.11 layer to update the slot time 1682 * based on the current setting. We use it to notify the 1683 * firmware of ERP changes and the f/w takes care of things 1684 * like slot time and preamble. 1685 */ 1686 static void 1687 bwn_updateslot(struct ieee80211com *ic) 1688 { 1689 struct bwn_softc *sc = ic->ic_softc; 1690 struct bwn_mac *mac; 1691 1692 BWN_LOCK(sc); 1693 if (sc->sc_flags & BWN_FLAG_RUNNING) { 1694 mac = (struct bwn_mac *)sc->sc_curmac; 1695 bwn_set_slot_time(mac, IEEE80211_GET_SLOTTIME(ic)); 1696 } 1697 BWN_UNLOCK(sc); 1698 } 1699 1700 /* 1701 * Callback from the 802.11 layer after a promiscuous mode change. 1702 * Note this interface does not check the operating mode as this 1703 * is an internal callback and we are expected to honor the current 1704 * state (e.g. this is used for setting the interface in promiscuous 1705 * mode when operating in hostap mode to do ACS). 1706 */ 1707 static void 1708 bwn_update_promisc(struct ieee80211com *ic) 1709 { 1710 struct bwn_softc *sc = ic->ic_softc; 1711 struct bwn_mac *mac = sc->sc_curmac; 1712 1713 BWN_LOCK(sc); 1714 mac = sc->sc_curmac; 1715 if (mac != NULL && mac->mac_status >= BWN_MAC_STATUS_INITED) { 1716 if (ic->ic_promisc > 0) 1717 sc->sc_filters |= BWN_MACCTL_PROMISC; 1718 else 1719 sc->sc_filters &= ~BWN_MACCTL_PROMISC; 1720 bwn_set_opmode(mac); 1721 } 1722 BWN_UNLOCK(sc); 1723 } 1724 1725 /* 1726 * Callback from the 802.11 layer to update WME parameters. 1727 */ 1728 static int 1729 bwn_wme_update(struct ieee80211com *ic) 1730 { 1731 struct bwn_softc *sc = ic->ic_softc; 1732 struct bwn_mac *mac = sc->sc_curmac; 1733 struct wmeParams *wmep; 1734 int i; 1735 1736 BWN_LOCK(sc); 1737 mac = sc->sc_curmac; 1738 if (mac != NULL && mac->mac_status >= BWN_MAC_STATUS_INITED) { 1739 bwn_mac_suspend(mac); 1740 for (i = 0; i < N(sc->sc_wmeParams); i++) { 1741 wmep = &ic->ic_wme.wme_chanParams.cap_wmeParams[i]; 1742 bwn_wme_loadparams(mac, wmep, bwn_wme_shm_offsets[i]); 1743 } 1744 bwn_mac_enable(mac); 1745 } 1746 BWN_UNLOCK(sc); 1747 return (0); 1748 } 1749 1750 static void 1751 bwn_scan_start(struct ieee80211com *ic) 1752 { 1753 struct bwn_softc *sc = ic->ic_softc; 1754 struct bwn_mac *mac; 1755 1756 BWN_LOCK(sc); 1757 mac = sc->sc_curmac; 1758 if (mac != NULL && mac->mac_status >= BWN_MAC_STATUS_INITED) { 1759 sc->sc_filters |= BWN_MACCTL_BEACON_PROMISC; 1760 bwn_set_opmode(mac); 1761 /* disable CFP update during scan */ 1762 bwn_hf_write(mac, bwn_hf_read(mac) | BWN_HF_SKIP_CFP_UPDATE); 1763 } 1764 BWN_UNLOCK(sc); 1765 } 1766 1767 static void 1768 bwn_scan_end(struct ieee80211com *ic) 1769 { 1770 struct bwn_softc *sc = ic->ic_softc; 1771 struct bwn_mac *mac; 1772 1773 BWN_LOCK(sc); 1774 mac = sc->sc_curmac; 1775 if (mac != NULL && mac->mac_status >= BWN_MAC_STATUS_INITED) { 1776 sc->sc_filters &= ~BWN_MACCTL_BEACON_PROMISC; 1777 bwn_set_opmode(mac); 1778 bwn_hf_write(mac, bwn_hf_read(mac) & ~BWN_HF_SKIP_CFP_UPDATE); 1779 } 1780 BWN_UNLOCK(sc); 1781 } 1782 1783 static void 1784 bwn_set_channel(struct ieee80211com *ic) 1785 { 1786 struct bwn_softc *sc = ic->ic_softc; 1787 struct bwn_mac *mac = sc->sc_curmac; 1788 struct bwn_phy *phy = &mac->mac_phy; 1789 int chan, error; 1790 1791 BWN_LOCK(sc); 1792 1793 error = bwn_switch_band(sc, ic->ic_curchan); 1794 if (error) 1795 goto fail; 1796 bwn_mac_suspend(mac); 1797 bwn_set_txretry(mac, BWN_RETRY_SHORT, BWN_RETRY_LONG); 1798 chan = ieee80211_chan2ieee(ic, ic->ic_curchan); 1799 if (chan != phy->chan) 1800 bwn_switch_channel(mac, chan); 1801 1802 /* TX power level */ 1803 if (ic->ic_curchan->ic_maxpower != 0 && 1804 ic->ic_curchan->ic_maxpower != phy->txpower) { 1805 phy->txpower = ic->ic_curchan->ic_maxpower / 2; 1806 bwn_phy_txpower_check(mac, BWN_TXPWR_IGNORE_TIME | 1807 BWN_TXPWR_IGNORE_TSSI); 1808 } 1809 1810 bwn_set_txantenna(mac, BWN_ANT_DEFAULT); 1811 if (phy->set_antenna) 1812 phy->set_antenna(mac, BWN_ANT_DEFAULT); 1813 1814 if (sc->sc_rf_enabled != phy->rf_on) { 1815 if (sc->sc_rf_enabled) { 1816 bwn_rf_turnon(mac); 1817 if (!(mac->mac_flags & BWN_MAC_FLAG_RADIO_ON)) 1818 device_printf(sc->sc_dev, 1819 "please turn on the RF switch\n"); 1820 } else 1821 bwn_rf_turnoff(mac); 1822 } 1823 1824 bwn_mac_enable(mac); 1825 1826 fail: 1827 /* 1828 * Setup radio tap channel freq and flags 1829 */ 1830 sc->sc_tx_th.wt_chan_freq = sc->sc_rx_th.wr_chan_freq = 1831 htole16(ic->ic_curchan->ic_freq); 1832 sc->sc_tx_th.wt_chan_flags = sc->sc_rx_th.wr_chan_flags = 1833 htole16(ic->ic_curchan->ic_flags & 0xffff); 1834 1835 BWN_UNLOCK(sc); 1836 } 1837 1838 static struct ieee80211vap * 1839 bwn_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 1840 enum ieee80211_opmode opmode, int flags, 1841 const uint8_t bssid[IEEE80211_ADDR_LEN], 1842 const uint8_t mac[IEEE80211_ADDR_LEN]) 1843 { 1844 struct ieee80211vap *vap; 1845 struct bwn_vap *bvp; 1846 1847 switch (opmode) { 1848 case IEEE80211_M_HOSTAP: 1849 case IEEE80211_M_MBSS: 1850 case IEEE80211_M_STA: 1851 case IEEE80211_M_WDS: 1852 case IEEE80211_M_MONITOR: 1853 case IEEE80211_M_IBSS: 1854 case IEEE80211_M_AHDEMO: 1855 break; 1856 default: 1857 return (NULL); 1858 } 1859 1860 bvp = malloc(sizeof(struct bwn_vap), M_80211_VAP, M_WAITOK | M_ZERO); 1861 vap = &bvp->bv_vap; 1862 ieee80211_vap_setup(ic, vap, name, unit, opmode, flags, bssid); 1863 /* override with driver methods */ 1864 bvp->bv_newstate = vap->iv_newstate; 1865 vap->iv_newstate = bwn_newstate; 1866 1867 /* override max aid so sta's cannot assoc when we're out of sta id's */ 1868 vap->iv_max_aid = BWN_STAID_MAX; 1869 1870 ieee80211_ratectl_init(vap); 1871 1872 /* complete setup */ 1873 ieee80211_vap_attach(vap, ieee80211_media_change, 1874 ieee80211_media_status, mac); 1875 return (vap); 1876 } 1877 1878 static void 1879 bwn_vap_delete(struct ieee80211vap *vap) 1880 { 1881 struct bwn_vap *bvp = BWN_VAP(vap); 1882 1883 ieee80211_ratectl_deinit(vap); 1884 ieee80211_vap_detach(vap); 1885 free(bvp, M_80211_VAP); 1886 } 1887 1888 static int 1889 bwn_init(struct bwn_softc *sc) 1890 { 1891 struct bwn_mac *mac; 1892 int error; 1893 1894 BWN_ASSERT_LOCKED(sc); 1895 1896 DPRINTF(sc, BWN_DEBUG_RESET, "%s: called\n", __func__); 1897 1898 bzero(sc->sc_bssid, IEEE80211_ADDR_LEN); 1899 sc->sc_flags |= BWN_FLAG_NEED_BEACON_TP; 1900 sc->sc_filters = 0; 1901 bwn_wme_clear(sc); 1902 sc->sc_beacons[0] = sc->sc_beacons[1] = 0; 1903 sc->sc_rf_enabled = 1; 1904 1905 mac = sc->sc_curmac; 1906 if (mac->mac_status == BWN_MAC_STATUS_UNINIT) { 1907 error = bwn_core_init(mac); 1908 if (error != 0) 1909 return (error); 1910 } 1911 if (mac->mac_status == BWN_MAC_STATUS_INITED) 1912 bwn_core_start(mac); 1913 1914 bwn_set_opmode(mac); 1915 bwn_set_pretbtt(mac); 1916 bwn_spu_setdelay(mac, 0); 1917 bwn_set_macaddr(mac); 1918 1919 sc->sc_flags |= BWN_FLAG_RUNNING; 1920 callout_reset(&sc->sc_rfswitch_ch, hz, bwn_rfswitch, sc); 1921 callout_reset(&sc->sc_watchdog_ch, hz, bwn_watchdog, sc); 1922 1923 return (0); 1924 } 1925 1926 static void 1927 bwn_stop(struct bwn_softc *sc) 1928 { 1929 struct bwn_mac *mac = sc->sc_curmac; 1930 1931 BWN_ASSERT_LOCKED(sc); 1932 1933 DPRINTF(sc, BWN_DEBUG_RESET, "%s: called\n", __func__); 1934 1935 if (mac->mac_status >= BWN_MAC_STATUS_INITED) { 1936 /* XXX FIXME opmode not based on VAP */ 1937 bwn_set_opmode(mac); 1938 bwn_set_macaddr(mac); 1939 } 1940 1941 if (mac->mac_status >= BWN_MAC_STATUS_STARTED) 1942 bwn_core_stop(mac); 1943 1944 callout_stop(&sc->sc_led_blink_ch); 1945 sc->sc_led_blinking = 0; 1946 1947 bwn_core_exit(mac); 1948 sc->sc_rf_enabled = 0; 1949 1950 sc->sc_flags &= ~BWN_FLAG_RUNNING; 1951 } 1952 1953 static void 1954 bwn_wme_clear(struct bwn_softc *sc) 1955 { 1956 #define MS(_v, _f) (((_v) & _f) >> _f##_S) 1957 struct wmeParams *p; 1958 unsigned int i; 1959 1960 KASSERT(N(bwn_wme_shm_offsets) == N(sc->sc_wmeParams), 1961 ("%s:%d: fail", __func__, __LINE__)); 1962 1963 for (i = 0; i < N(sc->sc_wmeParams); i++) { 1964 p = &(sc->sc_wmeParams[i]); 1965 1966 switch (bwn_wme_shm_offsets[i]) { 1967 case BWN_WME_VOICE: 1968 p->wmep_txopLimit = 0; 1969 p->wmep_aifsn = 2; 1970 /* XXX FIXME: log2(cwmin) */ 1971 p->wmep_logcwmin = MS(0x0001, WME_PARAM_LOGCWMIN); 1972 p->wmep_logcwmax = MS(0x0001, WME_PARAM_LOGCWMAX); 1973 break; 1974 case BWN_WME_VIDEO: 1975 p->wmep_txopLimit = 0; 1976 p->wmep_aifsn = 2; 1977 /* XXX FIXME: log2(cwmin) */ 1978 p->wmep_logcwmin = MS(0x0001, WME_PARAM_LOGCWMIN); 1979 p->wmep_logcwmax = MS(0x0001, WME_PARAM_LOGCWMAX); 1980 break; 1981 case BWN_WME_BESTEFFORT: 1982 p->wmep_txopLimit = 0; 1983 p->wmep_aifsn = 3; 1984 /* XXX FIXME: log2(cwmin) */ 1985 p->wmep_logcwmin = MS(0x0001, WME_PARAM_LOGCWMIN); 1986 p->wmep_logcwmax = MS(0x03ff, WME_PARAM_LOGCWMAX); 1987 break; 1988 case BWN_WME_BACKGROUND: 1989 p->wmep_txopLimit = 0; 1990 p->wmep_aifsn = 7; 1991 /* XXX FIXME: log2(cwmin) */ 1992 p->wmep_logcwmin = MS(0x0001, WME_PARAM_LOGCWMIN); 1993 p->wmep_logcwmax = MS(0x03ff, WME_PARAM_LOGCWMAX); 1994 break; 1995 default: 1996 KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__)); 1997 } 1998 } 1999 } 2000 2001 static int 2002 bwn_core_init(struct bwn_mac *mac) 2003 { 2004 struct bwn_softc *sc = mac->mac_sc; 2005 uint64_t hf; 2006 int error; 2007 2008 KASSERT(mac->mac_status == BWN_MAC_STATUS_UNINIT, 2009 ("%s:%d: fail", __func__, __LINE__)); 2010 2011 DPRINTF(mac->mac_sc, BWN_DEBUG_RESET, "%s: called\n", __func__); 2012 2013 siba_powerup(sc->sc_dev, 0); 2014 if (!siba_dev_isup(sc->sc_dev)) 2015 bwn_reset_core(mac, mac->mac_phy.gmode); 2016 2017 mac->mac_flags &= ~BWN_MAC_FLAG_DFQVALID; 2018 mac->mac_flags |= BWN_MAC_FLAG_RADIO_ON; 2019 mac->mac_phy.hwpctl = (bwn_hwpctl) ? 1 : 0; 2020 BWN_GETTIME(mac->mac_phy.nexttime); 2021 mac->mac_phy.txerrors = BWN_TXERROR_MAX; 2022 bzero(&mac->mac_stats, sizeof(mac->mac_stats)); 2023 mac->mac_stats.link_noise = -95; 2024 mac->mac_reason_intr = 0; 2025 bzero(mac->mac_reason, sizeof(mac->mac_reason)); 2026 mac->mac_intr_mask = BWN_INTR_MASKTEMPLATE; 2027 #ifdef BWN_DEBUG 2028 if (sc->sc_debug & BWN_DEBUG_XMIT) 2029 mac->mac_intr_mask &= ~BWN_INTR_PHY_TXERR; 2030 #endif 2031 mac->mac_suspended = 1; 2032 mac->mac_task_state = 0; 2033 memset(&mac->mac_noise, 0, sizeof(mac->mac_noise)); 2034 2035 mac->mac_phy.init_pre(mac); 2036 2037 siba_pcicore_intr(sc->sc_dev); 2038 2039 siba_fix_imcfglobug(sc->sc_dev); 2040 bwn_bt_disable(mac); 2041 if (mac->mac_phy.prepare_hw) { 2042 error = mac->mac_phy.prepare_hw(mac); 2043 if (error) 2044 goto fail0; 2045 } 2046 DPRINTF(mac->mac_sc, BWN_DEBUG_RESET, "%s: chip_init\n", __func__); 2047 error = bwn_chip_init(mac); 2048 if (error) 2049 goto fail0; 2050 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_COREREV, 2051 siba_get_revid(sc->sc_dev)); 2052 hf = bwn_hf_read(mac); 2053 if (mac->mac_phy.type == BWN_PHYTYPE_G) { 2054 hf |= BWN_HF_GPHY_SYM_WORKAROUND; 2055 if (siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_PACTRL) 2056 hf |= BWN_HF_PAGAINBOOST_OFDM_ON; 2057 if (mac->mac_phy.rev == 1) 2058 hf |= BWN_HF_GPHY_DC_CANCELFILTER; 2059 } 2060 if (mac->mac_phy.rf_ver == 0x2050) { 2061 if (mac->mac_phy.rf_rev < 6) 2062 hf |= BWN_HF_FORCE_VCO_RECALC; 2063 if (mac->mac_phy.rf_rev == 6) 2064 hf |= BWN_HF_4318_TSSI; 2065 } 2066 if (siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_CRYSTAL_NOSLOW) 2067 hf |= BWN_HF_SLOWCLOCK_REQ_OFF; 2068 if ((siba_get_type(sc->sc_dev) == SIBA_TYPE_PCI) && 2069 (siba_get_pcicore_revid(sc->sc_dev) <= 10)) 2070 hf |= BWN_HF_PCI_SLOWCLOCK_WORKAROUND; 2071 hf &= ~BWN_HF_SKIP_CFP_UPDATE; 2072 bwn_hf_write(mac, hf); 2073 2074 /* Tell the firmware about the MAC capabilities */ 2075 if (siba_get_revid(sc->sc_dev) >= 13) { 2076 uint32_t cap; 2077 cap = BWN_READ_4(mac, BWN_MAC_HW_CAP); 2078 DPRINTF(sc, BWN_DEBUG_RESET, 2079 "%s: hw capabilities: 0x%08x\n", 2080 __func__, cap); 2081 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_MACHW_L, 2082 cap & 0xffff); 2083 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_MACHW_H, 2084 (cap >> 16) & 0xffff); 2085 } 2086 2087 bwn_set_txretry(mac, BWN_RETRY_SHORT, BWN_RETRY_LONG); 2088 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_SHORT_RETRY_FALLBACK, 3); 2089 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_LONG_RETRY_FALLBACK, 2); 2090 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_PROBE_RESP_MAXTIME, 1); 2091 2092 bwn_rate_init(mac); 2093 bwn_set_phytxctl(mac); 2094 2095 bwn_shm_write_2(mac, BWN_SCRATCH, BWN_SCRATCH_CONT_MIN, 2096 (mac->mac_phy.type == BWN_PHYTYPE_B) ? 0x1f : 0xf); 2097 bwn_shm_write_2(mac, BWN_SCRATCH, BWN_SCRATCH_CONT_MAX, 0x3ff); 2098 2099 if (siba_get_type(sc->sc_dev) == SIBA_TYPE_PCMCIA || bwn_usedma == 0) 2100 bwn_pio_init(mac); 2101 else 2102 bwn_dma_init(mac); 2103 bwn_wme_init(mac); 2104 bwn_spu_setdelay(mac, 1); 2105 bwn_bt_enable(mac); 2106 2107 DPRINTF(mac->mac_sc, BWN_DEBUG_RESET, "%s: powerup\n", __func__); 2108 siba_powerup(sc->sc_dev, 2109 !(siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_CRYSTAL_NOSLOW)); 2110 bwn_set_macaddr(mac); 2111 bwn_crypt_init(mac); 2112 2113 /* XXX LED initializatin */ 2114 2115 mac->mac_status = BWN_MAC_STATUS_INITED; 2116 2117 DPRINTF(mac->mac_sc, BWN_DEBUG_RESET, "%s: done\n", __func__); 2118 return (error); 2119 2120 fail0: 2121 siba_powerdown(sc->sc_dev); 2122 KASSERT(mac->mac_status == BWN_MAC_STATUS_UNINIT, 2123 ("%s:%d: fail", __func__, __LINE__)); 2124 DPRINTF(mac->mac_sc, BWN_DEBUG_RESET, "%s: fail\n", __func__); 2125 return (error); 2126 } 2127 2128 static void 2129 bwn_core_start(struct bwn_mac *mac) 2130 { 2131 struct bwn_softc *sc = mac->mac_sc; 2132 uint32_t tmp; 2133 2134 KASSERT(mac->mac_status == BWN_MAC_STATUS_INITED, 2135 ("%s:%d: fail", __func__, __LINE__)); 2136 2137 if (siba_get_revid(sc->sc_dev) < 5) 2138 return; 2139 2140 while (1) { 2141 tmp = BWN_READ_4(mac, BWN_XMITSTAT_0); 2142 if (!(tmp & 0x00000001)) 2143 break; 2144 tmp = BWN_READ_4(mac, BWN_XMITSTAT_1); 2145 } 2146 2147 bwn_mac_enable(mac); 2148 BWN_WRITE_4(mac, BWN_INTR_MASK, mac->mac_intr_mask); 2149 callout_reset(&sc->sc_task_ch, hz * 15, bwn_tasks, mac); 2150 2151 mac->mac_status = BWN_MAC_STATUS_STARTED; 2152 } 2153 2154 static void 2155 bwn_core_exit(struct bwn_mac *mac) 2156 { 2157 struct bwn_softc *sc = mac->mac_sc; 2158 uint32_t macctl; 2159 2160 BWN_ASSERT_LOCKED(mac->mac_sc); 2161 2162 KASSERT(mac->mac_status <= BWN_MAC_STATUS_INITED, 2163 ("%s:%d: fail", __func__, __LINE__)); 2164 2165 if (mac->mac_status != BWN_MAC_STATUS_INITED) 2166 return; 2167 mac->mac_status = BWN_MAC_STATUS_UNINIT; 2168 2169 macctl = BWN_READ_4(mac, BWN_MACCTL); 2170 macctl &= ~BWN_MACCTL_MCODE_RUN; 2171 macctl |= BWN_MACCTL_MCODE_JMP0; 2172 BWN_WRITE_4(mac, BWN_MACCTL, macctl); 2173 2174 bwn_dma_stop(mac); 2175 bwn_pio_stop(mac); 2176 bwn_chip_exit(mac); 2177 mac->mac_phy.switch_analog(mac, 0); 2178 siba_dev_down(sc->sc_dev, 0); 2179 siba_powerdown(sc->sc_dev); 2180 } 2181 2182 static void 2183 bwn_bt_disable(struct bwn_mac *mac) 2184 { 2185 struct bwn_softc *sc = mac->mac_sc; 2186 2187 (void)sc; 2188 /* XXX do nothing yet */ 2189 } 2190 2191 static int 2192 bwn_chip_init(struct bwn_mac *mac) 2193 { 2194 struct bwn_softc *sc = mac->mac_sc; 2195 struct bwn_phy *phy = &mac->mac_phy; 2196 uint32_t macctl; 2197 int error; 2198 2199 macctl = BWN_MACCTL_IHR_ON | BWN_MACCTL_SHM_ON | BWN_MACCTL_STA; 2200 if (phy->gmode) 2201 macctl |= BWN_MACCTL_GMODE; 2202 BWN_WRITE_4(mac, BWN_MACCTL, macctl); 2203 2204 error = bwn_fw_fillinfo(mac); 2205 if (error) 2206 return (error); 2207 error = bwn_fw_loaducode(mac); 2208 if (error) 2209 return (error); 2210 2211 error = bwn_gpio_init(mac); 2212 if (error) 2213 return (error); 2214 2215 error = bwn_fw_loadinitvals(mac); 2216 if (error) { 2217 siba_gpio_set(sc->sc_dev, 0); 2218 return (error); 2219 } 2220 phy->switch_analog(mac, 1); 2221 error = bwn_phy_init(mac); 2222 if (error) { 2223 siba_gpio_set(sc->sc_dev, 0); 2224 return (error); 2225 } 2226 if (phy->set_im) 2227 phy->set_im(mac, BWN_IMMODE_NONE); 2228 if (phy->set_antenna) 2229 phy->set_antenna(mac, BWN_ANT_DEFAULT); 2230 bwn_set_txantenna(mac, BWN_ANT_DEFAULT); 2231 2232 if (phy->type == BWN_PHYTYPE_B) 2233 BWN_WRITE_2(mac, 0x005e, BWN_READ_2(mac, 0x005e) | 0x0004); 2234 BWN_WRITE_4(mac, 0x0100, 0x01000000); 2235 if (siba_get_revid(sc->sc_dev) < 5) 2236 BWN_WRITE_4(mac, 0x010c, 0x01000000); 2237 2238 BWN_WRITE_4(mac, BWN_MACCTL, 2239 BWN_READ_4(mac, BWN_MACCTL) & ~BWN_MACCTL_STA); 2240 BWN_WRITE_4(mac, BWN_MACCTL, 2241 BWN_READ_4(mac, BWN_MACCTL) | BWN_MACCTL_STA); 2242 bwn_shm_write_2(mac, BWN_SHARED, 0x0074, 0x0000); 2243 2244 bwn_set_opmode(mac); 2245 if (siba_get_revid(sc->sc_dev) < 3) { 2246 BWN_WRITE_2(mac, 0x060e, 0x0000); 2247 BWN_WRITE_2(mac, 0x0610, 0x8000); 2248 BWN_WRITE_2(mac, 0x0604, 0x0000); 2249 BWN_WRITE_2(mac, 0x0606, 0x0200); 2250 } else { 2251 BWN_WRITE_4(mac, 0x0188, 0x80000000); 2252 BWN_WRITE_4(mac, 0x018c, 0x02000000); 2253 } 2254 BWN_WRITE_4(mac, BWN_INTR_REASON, 0x00004000); 2255 BWN_WRITE_4(mac, BWN_DMA0_INTR_MASK, 0x0001dc00); 2256 BWN_WRITE_4(mac, BWN_DMA1_INTR_MASK, 0x0000dc00); 2257 BWN_WRITE_4(mac, BWN_DMA2_INTR_MASK, 0x0000dc00); 2258 BWN_WRITE_4(mac, BWN_DMA3_INTR_MASK, 0x0001dc00); 2259 BWN_WRITE_4(mac, BWN_DMA4_INTR_MASK, 0x0000dc00); 2260 BWN_WRITE_4(mac, BWN_DMA5_INTR_MASK, 0x0000dc00); 2261 2262 bwn_mac_phy_clock_set(mac, true); 2263 2264 /* SIBA powerup */ 2265 /* XXX TODO: BCMA powerup */ 2266 BWN_WRITE_2(mac, BWN_POWERUP_DELAY, siba_get_cc_powerdelay(sc->sc_dev)); 2267 return (error); 2268 } 2269 2270 /* read hostflags */ 2271 uint64_t 2272 bwn_hf_read(struct bwn_mac *mac) 2273 { 2274 uint64_t ret; 2275 2276 ret = bwn_shm_read_2(mac, BWN_SHARED, BWN_SHARED_HFHI); 2277 ret <<= 16; 2278 ret |= bwn_shm_read_2(mac, BWN_SHARED, BWN_SHARED_HFMI); 2279 ret <<= 16; 2280 ret |= bwn_shm_read_2(mac, BWN_SHARED, BWN_SHARED_HFLO); 2281 return (ret); 2282 } 2283 2284 void 2285 bwn_hf_write(struct bwn_mac *mac, uint64_t value) 2286 { 2287 2288 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_HFLO, 2289 (value & 0x00000000ffffull)); 2290 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_HFMI, 2291 (value & 0x0000ffff0000ull) >> 16); 2292 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_HFHI, 2293 (value & 0xffff00000000ULL) >> 32); 2294 } 2295 2296 static void 2297 bwn_set_txretry(struct bwn_mac *mac, int s, int l) 2298 { 2299 2300 bwn_shm_write_2(mac, BWN_SCRATCH, BWN_SCRATCH_SHORT_RETRY, MIN(s, 0xf)); 2301 bwn_shm_write_2(mac, BWN_SCRATCH, BWN_SCRATCH_LONG_RETRY, MIN(l, 0xf)); 2302 } 2303 2304 static void 2305 bwn_rate_init(struct bwn_mac *mac) 2306 { 2307 2308 switch (mac->mac_phy.type) { 2309 case BWN_PHYTYPE_A: 2310 case BWN_PHYTYPE_G: 2311 case BWN_PHYTYPE_LP: 2312 case BWN_PHYTYPE_N: 2313 bwn_rate_write(mac, BWN_OFDM_RATE_6MB, 1); 2314 bwn_rate_write(mac, BWN_OFDM_RATE_12MB, 1); 2315 bwn_rate_write(mac, BWN_OFDM_RATE_18MB, 1); 2316 bwn_rate_write(mac, BWN_OFDM_RATE_24MB, 1); 2317 bwn_rate_write(mac, BWN_OFDM_RATE_36MB, 1); 2318 bwn_rate_write(mac, BWN_OFDM_RATE_48MB, 1); 2319 bwn_rate_write(mac, BWN_OFDM_RATE_54MB, 1); 2320 if (mac->mac_phy.type == BWN_PHYTYPE_A) 2321 break; 2322 /* FALLTHROUGH */ 2323 case BWN_PHYTYPE_B: 2324 bwn_rate_write(mac, BWN_CCK_RATE_1MB, 0); 2325 bwn_rate_write(mac, BWN_CCK_RATE_2MB, 0); 2326 bwn_rate_write(mac, BWN_CCK_RATE_5MB, 0); 2327 bwn_rate_write(mac, BWN_CCK_RATE_11MB, 0); 2328 break; 2329 default: 2330 KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__)); 2331 } 2332 } 2333 2334 static void 2335 bwn_rate_write(struct bwn_mac *mac, uint16_t rate, int ofdm) 2336 { 2337 uint16_t offset; 2338 2339 if (ofdm) { 2340 offset = 0x480; 2341 offset += (bwn_plcp_getofdm(rate) & 0x000f) * 2; 2342 } else { 2343 offset = 0x4c0; 2344 offset += (bwn_plcp_getcck(rate) & 0x000f) * 2; 2345 } 2346 bwn_shm_write_2(mac, BWN_SHARED, offset + 0x20, 2347 bwn_shm_read_2(mac, BWN_SHARED, offset)); 2348 } 2349 2350 static uint8_t 2351 bwn_plcp_getcck(const uint8_t bitrate) 2352 { 2353 2354 switch (bitrate) { 2355 case BWN_CCK_RATE_1MB: 2356 return (0x0a); 2357 case BWN_CCK_RATE_2MB: 2358 return (0x14); 2359 case BWN_CCK_RATE_5MB: 2360 return (0x37); 2361 case BWN_CCK_RATE_11MB: 2362 return (0x6e); 2363 } 2364 KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__)); 2365 return (0); 2366 } 2367 2368 static uint8_t 2369 bwn_plcp_getofdm(const uint8_t bitrate) 2370 { 2371 2372 switch (bitrate) { 2373 case BWN_OFDM_RATE_6MB: 2374 return (0xb); 2375 case BWN_OFDM_RATE_9MB: 2376 return (0xf); 2377 case BWN_OFDM_RATE_12MB: 2378 return (0xa); 2379 case BWN_OFDM_RATE_18MB: 2380 return (0xe); 2381 case BWN_OFDM_RATE_24MB: 2382 return (0x9); 2383 case BWN_OFDM_RATE_36MB: 2384 return (0xd); 2385 case BWN_OFDM_RATE_48MB: 2386 return (0x8); 2387 case BWN_OFDM_RATE_54MB: 2388 return (0xc); 2389 } 2390 KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__)); 2391 return (0); 2392 } 2393 2394 static void 2395 bwn_set_phytxctl(struct bwn_mac *mac) 2396 { 2397 uint16_t ctl; 2398 2399 ctl = (BWN_TX_PHY_ENC_CCK | BWN_TX_PHY_ANT01AUTO | 2400 BWN_TX_PHY_TXPWR); 2401 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_BEACON_PHYCTL, ctl); 2402 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_ACKCTS_PHYCTL, ctl); 2403 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_PROBE_RESP_PHYCTL, ctl); 2404 } 2405 2406 static void 2407 bwn_pio_init(struct bwn_mac *mac) 2408 { 2409 struct bwn_pio *pio = &mac->mac_method.pio; 2410 2411 BWN_WRITE_4(mac, BWN_MACCTL, BWN_READ_4(mac, BWN_MACCTL) 2412 & ~BWN_MACCTL_BIGENDIAN); 2413 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_RX_PADOFFSET, 0); 2414 2415 bwn_pio_set_txqueue(mac, &pio->wme[WME_AC_BK], 0); 2416 bwn_pio_set_txqueue(mac, &pio->wme[WME_AC_BE], 1); 2417 bwn_pio_set_txqueue(mac, &pio->wme[WME_AC_VI], 2); 2418 bwn_pio_set_txqueue(mac, &pio->wme[WME_AC_VO], 3); 2419 bwn_pio_set_txqueue(mac, &pio->mcast, 4); 2420 bwn_pio_setupqueue_rx(mac, &pio->rx, 0); 2421 } 2422 2423 static void 2424 bwn_pio_set_txqueue(struct bwn_mac *mac, struct bwn_pio_txqueue *tq, 2425 int index) 2426 { 2427 struct bwn_pio_txpkt *tp; 2428 struct bwn_softc *sc = mac->mac_sc; 2429 unsigned int i; 2430 2431 tq->tq_base = bwn_pio_idx2base(mac, index) + BWN_PIO_TXQOFFSET(mac); 2432 tq->tq_index = index; 2433 2434 tq->tq_free = BWN_PIO_MAX_TXPACKETS; 2435 if (siba_get_revid(sc->sc_dev) >= 8) 2436 tq->tq_size = 1920; 2437 else { 2438 tq->tq_size = bwn_pio_read_2(mac, tq, BWN_PIO_TXQBUFSIZE); 2439 tq->tq_size -= 80; 2440 } 2441 2442 TAILQ_INIT(&tq->tq_pktlist); 2443 for (i = 0; i < N(tq->tq_pkts); i++) { 2444 tp = &(tq->tq_pkts[i]); 2445 tp->tp_index = i; 2446 tp->tp_queue = tq; 2447 TAILQ_INSERT_TAIL(&tq->tq_pktlist, tp, tp_list); 2448 } 2449 } 2450 2451 static uint16_t 2452 bwn_pio_idx2base(struct bwn_mac *mac, int index) 2453 { 2454 struct bwn_softc *sc = mac->mac_sc; 2455 static const uint16_t bases[] = { 2456 BWN_PIO_BASE0, 2457 BWN_PIO_BASE1, 2458 BWN_PIO_BASE2, 2459 BWN_PIO_BASE3, 2460 BWN_PIO_BASE4, 2461 BWN_PIO_BASE5, 2462 BWN_PIO_BASE6, 2463 BWN_PIO_BASE7, 2464 }; 2465 static const uint16_t bases_rev11[] = { 2466 BWN_PIO11_BASE0, 2467 BWN_PIO11_BASE1, 2468 BWN_PIO11_BASE2, 2469 BWN_PIO11_BASE3, 2470 BWN_PIO11_BASE4, 2471 BWN_PIO11_BASE5, 2472 }; 2473 2474 if (siba_get_revid(sc->sc_dev) >= 11) { 2475 if (index >= N(bases_rev11)) 2476 device_printf(sc->sc_dev, "%s: warning\n", __func__); 2477 return (bases_rev11[index]); 2478 } 2479 if (index >= N(bases)) 2480 device_printf(sc->sc_dev, "%s: warning\n", __func__); 2481 return (bases[index]); 2482 } 2483 2484 static void 2485 bwn_pio_setupqueue_rx(struct bwn_mac *mac, struct bwn_pio_rxqueue *prq, 2486 int index) 2487 { 2488 struct bwn_softc *sc = mac->mac_sc; 2489 2490 prq->prq_mac = mac; 2491 prq->prq_rev = siba_get_revid(sc->sc_dev); 2492 prq->prq_base = bwn_pio_idx2base(mac, index) + BWN_PIO_RXQOFFSET(mac); 2493 bwn_dma_rxdirectfifo(mac, index, 1); 2494 } 2495 2496 static void 2497 bwn_destroy_pioqueue_tx(struct bwn_pio_txqueue *tq) 2498 { 2499 if (tq == NULL) 2500 return; 2501 bwn_pio_cancel_tx_packets(tq); 2502 } 2503 2504 static void 2505 bwn_destroy_queue_tx(struct bwn_pio_txqueue *pio) 2506 { 2507 2508 bwn_destroy_pioqueue_tx(pio); 2509 } 2510 2511 static uint16_t 2512 bwn_pio_read_2(struct bwn_mac *mac, struct bwn_pio_txqueue *tq, 2513 uint16_t offset) 2514 { 2515 2516 return (BWN_READ_2(mac, tq->tq_base + offset)); 2517 } 2518 2519 static void 2520 bwn_dma_rxdirectfifo(struct bwn_mac *mac, int idx, uint8_t enable) 2521 { 2522 uint32_t ctl; 2523 int type; 2524 uint16_t base; 2525 2526 type = bwn_dma_mask2type(bwn_dma_mask(mac)); 2527 base = bwn_dma_base(type, idx); 2528 if (type == BWN_DMA_64BIT) { 2529 ctl = BWN_READ_4(mac, base + BWN_DMA64_RXCTL); 2530 ctl &= ~BWN_DMA64_RXDIRECTFIFO; 2531 if (enable) 2532 ctl |= BWN_DMA64_RXDIRECTFIFO; 2533 BWN_WRITE_4(mac, base + BWN_DMA64_RXCTL, ctl); 2534 } else { 2535 ctl = BWN_READ_4(mac, base + BWN_DMA32_RXCTL); 2536 ctl &= ~BWN_DMA32_RXDIRECTFIFO; 2537 if (enable) 2538 ctl |= BWN_DMA32_RXDIRECTFIFO; 2539 BWN_WRITE_4(mac, base + BWN_DMA32_RXCTL, ctl); 2540 } 2541 } 2542 2543 static uint64_t 2544 bwn_dma_mask(struct bwn_mac *mac) 2545 { 2546 uint32_t tmp; 2547 uint16_t base; 2548 2549 tmp = BWN_READ_4(mac, SIBA_TGSHIGH); 2550 if (tmp & SIBA_TGSHIGH_DMA64) 2551 return (BWN_DMA_BIT_MASK(64)); 2552 base = bwn_dma_base(0, 0); 2553 BWN_WRITE_4(mac, base + BWN_DMA32_TXCTL, BWN_DMA32_TXADDREXT_MASK); 2554 tmp = BWN_READ_4(mac, base + BWN_DMA32_TXCTL); 2555 if (tmp & BWN_DMA32_TXADDREXT_MASK) 2556 return (BWN_DMA_BIT_MASK(32)); 2557 2558 return (BWN_DMA_BIT_MASK(30)); 2559 } 2560 2561 static int 2562 bwn_dma_mask2type(uint64_t dmamask) 2563 { 2564 2565 if (dmamask == BWN_DMA_BIT_MASK(30)) 2566 return (BWN_DMA_30BIT); 2567 if (dmamask == BWN_DMA_BIT_MASK(32)) 2568 return (BWN_DMA_32BIT); 2569 if (dmamask == BWN_DMA_BIT_MASK(64)) 2570 return (BWN_DMA_64BIT); 2571 KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__)); 2572 return (BWN_DMA_30BIT); 2573 } 2574 2575 static void 2576 bwn_pio_cancel_tx_packets(struct bwn_pio_txqueue *tq) 2577 { 2578 struct bwn_pio_txpkt *tp; 2579 unsigned int i; 2580 2581 for (i = 0; i < N(tq->tq_pkts); i++) { 2582 tp = &(tq->tq_pkts[i]); 2583 if (tp->tp_m) { 2584 m_freem(tp->tp_m); 2585 tp->tp_m = NULL; 2586 } 2587 } 2588 } 2589 2590 static uint16_t 2591 bwn_dma_base(int type, int controller_idx) 2592 { 2593 static const uint16_t map64[] = { 2594 BWN_DMA64_BASE0, 2595 BWN_DMA64_BASE1, 2596 BWN_DMA64_BASE2, 2597 BWN_DMA64_BASE3, 2598 BWN_DMA64_BASE4, 2599 BWN_DMA64_BASE5, 2600 }; 2601 static const uint16_t map32[] = { 2602 BWN_DMA32_BASE0, 2603 BWN_DMA32_BASE1, 2604 BWN_DMA32_BASE2, 2605 BWN_DMA32_BASE3, 2606 BWN_DMA32_BASE4, 2607 BWN_DMA32_BASE5, 2608 }; 2609 2610 if (type == BWN_DMA_64BIT) { 2611 KASSERT(controller_idx >= 0 && controller_idx < N(map64), 2612 ("%s:%d: fail", __func__, __LINE__)); 2613 return (map64[controller_idx]); 2614 } 2615 KASSERT(controller_idx >= 0 && controller_idx < N(map32), 2616 ("%s:%d: fail", __func__, __LINE__)); 2617 return (map32[controller_idx]); 2618 } 2619 2620 static void 2621 bwn_dma_init(struct bwn_mac *mac) 2622 { 2623 struct bwn_dma *dma = &mac->mac_method.dma; 2624 2625 /* setup TX DMA channels. */ 2626 bwn_dma_setup(dma->wme[WME_AC_BK]); 2627 bwn_dma_setup(dma->wme[WME_AC_BE]); 2628 bwn_dma_setup(dma->wme[WME_AC_VI]); 2629 bwn_dma_setup(dma->wme[WME_AC_VO]); 2630 bwn_dma_setup(dma->mcast); 2631 /* setup RX DMA channel. */ 2632 bwn_dma_setup(dma->rx); 2633 } 2634 2635 static struct bwn_dma_ring * 2636 bwn_dma_ringsetup(struct bwn_mac *mac, int controller_index, 2637 int for_tx, int type) 2638 { 2639 struct bwn_dma *dma = &mac->mac_method.dma; 2640 struct bwn_dma_ring *dr; 2641 struct bwn_dmadesc_generic *desc; 2642 struct bwn_dmadesc_meta *mt; 2643 struct bwn_softc *sc = mac->mac_sc; 2644 int error, i; 2645 2646 dr = malloc(sizeof(*dr), M_DEVBUF, M_NOWAIT | M_ZERO); 2647 if (dr == NULL) 2648 goto out; 2649 dr->dr_numslots = BWN_RXRING_SLOTS; 2650 if (for_tx) 2651 dr->dr_numslots = BWN_TXRING_SLOTS; 2652 2653 dr->dr_meta = malloc(dr->dr_numslots * sizeof(struct bwn_dmadesc_meta), 2654 M_DEVBUF, M_NOWAIT | M_ZERO); 2655 if (dr->dr_meta == NULL) 2656 goto fail0; 2657 2658 dr->dr_type = type; 2659 dr->dr_mac = mac; 2660 dr->dr_base = bwn_dma_base(type, controller_index); 2661 dr->dr_index = controller_index; 2662 if (type == BWN_DMA_64BIT) { 2663 dr->getdesc = bwn_dma_64_getdesc; 2664 dr->setdesc = bwn_dma_64_setdesc; 2665 dr->start_transfer = bwn_dma_64_start_transfer; 2666 dr->suspend = bwn_dma_64_suspend; 2667 dr->resume = bwn_dma_64_resume; 2668 dr->get_curslot = bwn_dma_64_get_curslot; 2669 dr->set_curslot = bwn_dma_64_set_curslot; 2670 } else { 2671 dr->getdesc = bwn_dma_32_getdesc; 2672 dr->setdesc = bwn_dma_32_setdesc; 2673 dr->start_transfer = bwn_dma_32_start_transfer; 2674 dr->suspend = bwn_dma_32_suspend; 2675 dr->resume = bwn_dma_32_resume; 2676 dr->get_curslot = bwn_dma_32_get_curslot; 2677 dr->set_curslot = bwn_dma_32_set_curslot; 2678 } 2679 if (for_tx) { 2680 dr->dr_tx = 1; 2681 dr->dr_curslot = -1; 2682 } else { 2683 if (dr->dr_index == 0) { 2684 switch (mac->mac_fw.fw_hdr_format) { 2685 case BWN_FW_HDR_351: 2686 case BWN_FW_HDR_410: 2687 dr->dr_rx_bufsize = 2688 BWN_DMA0_RX_BUFFERSIZE_FW351; 2689 dr->dr_frameoffset = 2690 BWN_DMA0_RX_FRAMEOFFSET_FW351; 2691 break; 2692 case BWN_FW_HDR_598: 2693 dr->dr_rx_bufsize = 2694 BWN_DMA0_RX_BUFFERSIZE_FW598; 2695 dr->dr_frameoffset = 2696 BWN_DMA0_RX_FRAMEOFFSET_FW598; 2697 break; 2698 } 2699 } else 2700 KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__)); 2701 } 2702 2703 error = bwn_dma_allocringmemory(dr); 2704 if (error) 2705 goto fail2; 2706 2707 if (for_tx) { 2708 /* 2709 * Assumption: BWN_TXRING_SLOTS can be divided by 2710 * BWN_TX_SLOTS_PER_FRAME 2711 */ 2712 KASSERT(BWN_TXRING_SLOTS % BWN_TX_SLOTS_PER_FRAME == 0, 2713 ("%s:%d: fail", __func__, __LINE__)); 2714 2715 dr->dr_txhdr_cache = contigmalloc( 2716 (dr->dr_numslots / BWN_TX_SLOTS_PER_FRAME) * 2717 BWN_MAXTXHDRSIZE, M_DEVBUF, M_ZERO, 2718 0, BUS_SPACE_MAXADDR, 8, 0); 2719 if (dr->dr_txhdr_cache == NULL) { 2720 device_printf(sc->sc_dev, 2721 "can't allocate TX header DMA memory\n"); 2722 goto fail1; 2723 } 2724 2725 /* 2726 * Create TX ring DMA stuffs 2727 */ 2728 error = bus_dma_tag_create(dma->parent_dtag, 2729 BWN_ALIGN, 0, 2730 BUS_SPACE_MAXADDR, 2731 BUS_SPACE_MAXADDR, 2732 NULL, NULL, 2733 BWN_HDRSIZE(mac), 2734 1, 2735 BUS_SPACE_MAXSIZE_32BIT, 2736 0, 2737 NULL, NULL, 2738 &dr->dr_txring_dtag); 2739 if (error) { 2740 device_printf(sc->sc_dev, 2741 "can't create TX ring DMA tag: TODO frees\n"); 2742 goto fail2; 2743 } 2744 2745 for (i = 0; i < dr->dr_numslots; i += 2) { 2746 dr->getdesc(dr, i, &desc, &mt); 2747 2748 mt->mt_txtype = BWN_DMADESC_METATYPE_HEADER; 2749 mt->mt_m = NULL; 2750 mt->mt_ni = NULL; 2751 mt->mt_islast = 0; 2752 error = bus_dmamap_create(dr->dr_txring_dtag, 0, 2753 &mt->mt_dmap); 2754 if (error) { 2755 device_printf(sc->sc_dev, 2756 "can't create RX buf DMA map\n"); 2757 goto fail2; 2758 } 2759 2760 dr->getdesc(dr, i + 1, &desc, &mt); 2761 2762 mt->mt_txtype = BWN_DMADESC_METATYPE_BODY; 2763 mt->mt_m = NULL; 2764 mt->mt_ni = NULL; 2765 mt->mt_islast = 1; 2766 error = bus_dmamap_create(dma->txbuf_dtag, 0, 2767 &mt->mt_dmap); 2768 if (error) { 2769 device_printf(sc->sc_dev, 2770 "can't create RX buf DMA map\n"); 2771 goto fail2; 2772 } 2773 } 2774 } else { 2775 error = bus_dmamap_create(dma->rxbuf_dtag, 0, 2776 &dr->dr_spare_dmap); 2777 if (error) { 2778 device_printf(sc->sc_dev, 2779 "can't create RX buf DMA map\n"); 2780 goto out; /* XXX wrong! */ 2781 } 2782 2783 for (i = 0; i < dr->dr_numslots; i++) { 2784 dr->getdesc(dr, i, &desc, &mt); 2785 2786 error = bus_dmamap_create(dma->rxbuf_dtag, 0, 2787 &mt->mt_dmap); 2788 if (error) { 2789 device_printf(sc->sc_dev, 2790 "can't create RX buf DMA map\n"); 2791 goto out; /* XXX wrong! */ 2792 } 2793 error = bwn_dma_newbuf(dr, desc, mt, 1); 2794 if (error) { 2795 device_printf(sc->sc_dev, 2796 "failed to allocate RX buf\n"); 2797 goto out; /* XXX wrong! */ 2798 } 2799 } 2800 2801 bus_dmamap_sync(dr->dr_ring_dtag, dr->dr_ring_dmap, 2802 BUS_DMASYNC_PREWRITE); 2803 2804 dr->dr_usedslot = dr->dr_numslots; 2805 } 2806 2807 out: 2808 return (dr); 2809 2810 fail2: 2811 if (dr->dr_txhdr_cache != NULL) { 2812 contigfree(dr->dr_txhdr_cache, 2813 (dr->dr_numslots / BWN_TX_SLOTS_PER_FRAME) * 2814 BWN_MAXTXHDRSIZE, M_DEVBUF); 2815 } 2816 fail1: 2817 free(dr->dr_meta, M_DEVBUF); 2818 fail0: 2819 free(dr, M_DEVBUF); 2820 return (NULL); 2821 } 2822 2823 static void 2824 bwn_dma_ringfree(struct bwn_dma_ring **dr) 2825 { 2826 2827 if (dr == NULL) 2828 return; 2829 2830 bwn_dma_free_descbufs(*dr); 2831 bwn_dma_free_ringmemory(*dr); 2832 2833 if ((*dr)->dr_txhdr_cache != NULL) { 2834 contigfree((*dr)->dr_txhdr_cache, 2835 ((*dr)->dr_numslots / BWN_TX_SLOTS_PER_FRAME) * 2836 BWN_MAXTXHDRSIZE, M_DEVBUF); 2837 } 2838 free((*dr)->dr_meta, M_DEVBUF); 2839 free(*dr, M_DEVBUF); 2840 2841 *dr = NULL; 2842 } 2843 2844 static void 2845 bwn_dma_32_getdesc(struct bwn_dma_ring *dr, int slot, 2846 struct bwn_dmadesc_generic **gdesc, struct bwn_dmadesc_meta **meta) 2847 { 2848 struct bwn_dmadesc32 *desc; 2849 2850 *meta = &(dr->dr_meta[slot]); 2851 desc = dr->dr_ring_descbase; 2852 desc = &(desc[slot]); 2853 2854 *gdesc = (struct bwn_dmadesc_generic *)desc; 2855 } 2856 2857 static void 2858 bwn_dma_32_setdesc(struct bwn_dma_ring *dr, 2859 struct bwn_dmadesc_generic *desc, bus_addr_t dmaaddr, uint16_t bufsize, 2860 int start, int end, int irq) 2861 { 2862 struct bwn_dmadesc32 *descbase = dr->dr_ring_descbase; 2863 struct bwn_softc *sc = dr->dr_mac->mac_sc; 2864 uint32_t addr, addrext, ctl; 2865 int slot; 2866 2867 slot = (int)(&(desc->dma.dma32) - descbase); 2868 KASSERT(slot >= 0 && slot < dr->dr_numslots, 2869 ("%s:%d: fail", __func__, __LINE__)); 2870 2871 addr = (uint32_t) (dmaaddr & ~SIBA_DMA_TRANSLATION_MASK); 2872 addrext = (uint32_t) (dmaaddr & SIBA_DMA_TRANSLATION_MASK) >> 30; 2873 addr |= siba_dma_translation(sc->sc_dev); 2874 ctl = bufsize & BWN_DMA32_DCTL_BYTECNT; 2875 if (slot == dr->dr_numslots - 1) 2876 ctl |= BWN_DMA32_DCTL_DTABLEEND; 2877 if (start) 2878 ctl |= BWN_DMA32_DCTL_FRAMESTART; 2879 if (end) 2880 ctl |= BWN_DMA32_DCTL_FRAMEEND; 2881 if (irq) 2882 ctl |= BWN_DMA32_DCTL_IRQ; 2883 ctl |= (addrext << BWN_DMA32_DCTL_ADDREXT_SHIFT) 2884 & BWN_DMA32_DCTL_ADDREXT_MASK; 2885 2886 desc->dma.dma32.control = htole32(ctl); 2887 desc->dma.dma32.address = htole32(addr); 2888 } 2889 2890 static void 2891 bwn_dma_32_start_transfer(struct bwn_dma_ring *dr, int slot) 2892 { 2893 2894 BWN_DMA_WRITE(dr, BWN_DMA32_TXINDEX, 2895 (uint32_t)(slot * sizeof(struct bwn_dmadesc32))); 2896 } 2897 2898 static void 2899 bwn_dma_32_suspend(struct bwn_dma_ring *dr) 2900 { 2901 2902 BWN_DMA_WRITE(dr, BWN_DMA32_TXCTL, 2903 BWN_DMA_READ(dr, BWN_DMA32_TXCTL) | BWN_DMA32_TXSUSPEND); 2904 } 2905 2906 static void 2907 bwn_dma_32_resume(struct bwn_dma_ring *dr) 2908 { 2909 2910 BWN_DMA_WRITE(dr, BWN_DMA32_TXCTL, 2911 BWN_DMA_READ(dr, BWN_DMA32_TXCTL) & ~BWN_DMA32_TXSUSPEND); 2912 } 2913 2914 static int 2915 bwn_dma_32_get_curslot(struct bwn_dma_ring *dr) 2916 { 2917 uint32_t val; 2918 2919 val = BWN_DMA_READ(dr, BWN_DMA32_RXSTATUS); 2920 val &= BWN_DMA32_RXDPTR; 2921 2922 return (val / sizeof(struct bwn_dmadesc32)); 2923 } 2924 2925 static void 2926 bwn_dma_32_set_curslot(struct bwn_dma_ring *dr, int slot) 2927 { 2928 2929 BWN_DMA_WRITE(dr, BWN_DMA32_RXINDEX, 2930 (uint32_t) (slot * sizeof(struct bwn_dmadesc32))); 2931 } 2932 2933 static void 2934 bwn_dma_64_getdesc(struct bwn_dma_ring *dr, int slot, 2935 struct bwn_dmadesc_generic **gdesc, struct bwn_dmadesc_meta **meta) 2936 { 2937 struct bwn_dmadesc64 *desc; 2938 2939 *meta = &(dr->dr_meta[slot]); 2940 desc = dr->dr_ring_descbase; 2941 desc = &(desc[slot]); 2942 2943 *gdesc = (struct bwn_dmadesc_generic *)desc; 2944 } 2945 2946 static void 2947 bwn_dma_64_setdesc(struct bwn_dma_ring *dr, 2948 struct bwn_dmadesc_generic *desc, bus_addr_t dmaaddr, uint16_t bufsize, 2949 int start, int end, int irq) 2950 { 2951 struct bwn_dmadesc64 *descbase = dr->dr_ring_descbase; 2952 struct bwn_softc *sc = dr->dr_mac->mac_sc; 2953 int slot; 2954 uint32_t ctl0 = 0, ctl1 = 0; 2955 uint32_t addrlo, addrhi; 2956 uint32_t addrext; 2957 2958 slot = (int)(&(desc->dma.dma64) - descbase); 2959 KASSERT(slot >= 0 && slot < dr->dr_numslots, 2960 ("%s:%d: fail", __func__, __LINE__)); 2961 2962 addrlo = (uint32_t) (dmaaddr & 0xffffffff); 2963 addrhi = (((uint64_t) dmaaddr >> 32) & ~SIBA_DMA_TRANSLATION_MASK); 2964 addrext = (((uint64_t) dmaaddr >> 32) & SIBA_DMA_TRANSLATION_MASK) >> 2965 30; 2966 addrhi |= (siba_dma_translation(sc->sc_dev) << 1); 2967 if (slot == dr->dr_numslots - 1) 2968 ctl0 |= BWN_DMA64_DCTL0_DTABLEEND; 2969 if (start) 2970 ctl0 |= BWN_DMA64_DCTL0_FRAMESTART; 2971 if (end) 2972 ctl0 |= BWN_DMA64_DCTL0_FRAMEEND; 2973 if (irq) 2974 ctl0 |= BWN_DMA64_DCTL0_IRQ; 2975 ctl1 |= bufsize & BWN_DMA64_DCTL1_BYTECNT; 2976 ctl1 |= (addrext << BWN_DMA64_DCTL1_ADDREXT_SHIFT) 2977 & BWN_DMA64_DCTL1_ADDREXT_MASK; 2978 2979 desc->dma.dma64.control0 = htole32(ctl0); 2980 desc->dma.dma64.control1 = htole32(ctl1); 2981 desc->dma.dma64.address_low = htole32(addrlo); 2982 desc->dma.dma64.address_high = htole32(addrhi); 2983 } 2984 2985 static void 2986 bwn_dma_64_start_transfer(struct bwn_dma_ring *dr, int slot) 2987 { 2988 2989 BWN_DMA_WRITE(dr, BWN_DMA64_TXINDEX, 2990 (uint32_t)(slot * sizeof(struct bwn_dmadesc64))); 2991 } 2992 2993 static void 2994 bwn_dma_64_suspend(struct bwn_dma_ring *dr) 2995 { 2996 2997 BWN_DMA_WRITE(dr, BWN_DMA64_TXCTL, 2998 BWN_DMA_READ(dr, BWN_DMA64_TXCTL) | BWN_DMA64_TXSUSPEND); 2999 } 3000 3001 static void 3002 bwn_dma_64_resume(struct bwn_dma_ring *dr) 3003 { 3004 3005 BWN_DMA_WRITE(dr, BWN_DMA64_TXCTL, 3006 BWN_DMA_READ(dr, BWN_DMA64_TXCTL) & ~BWN_DMA64_TXSUSPEND); 3007 } 3008 3009 static int 3010 bwn_dma_64_get_curslot(struct bwn_dma_ring *dr) 3011 { 3012 uint32_t val; 3013 3014 val = BWN_DMA_READ(dr, BWN_DMA64_RXSTATUS); 3015 val &= BWN_DMA64_RXSTATDPTR; 3016 3017 return (val / sizeof(struct bwn_dmadesc64)); 3018 } 3019 3020 static void 3021 bwn_dma_64_set_curslot(struct bwn_dma_ring *dr, int slot) 3022 { 3023 3024 BWN_DMA_WRITE(dr, BWN_DMA64_RXINDEX, 3025 (uint32_t)(slot * sizeof(struct bwn_dmadesc64))); 3026 } 3027 3028 static int 3029 bwn_dma_allocringmemory(struct bwn_dma_ring *dr) 3030 { 3031 struct bwn_mac *mac = dr->dr_mac; 3032 struct bwn_dma *dma = &mac->mac_method.dma; 3033 struct bwn_softc *sc = mac->mac_sc; 3034 int error; 3035 3036 error = bus_dma_tag_create(dma->parent_dtag, 3037 BWN_ALIGN, 0, 3038 BUS_SPACE_MAXADDR, 3039 BUS_SPACE_MAXADDR, 3040 NULL, NULL, 3041 BWN_DMA_RINGMEMSIZE, 3042 1, 3043 BUS_SPACE_MAXSIZE_32BIT, 3044 0, 3045 NULL, NULL, 3046 &dr->dr_ring_dtag); 3047 if (error) { 3048 device_printf(sc->sc_dev, 3049 "can't create TX ring DMA tag: TODO frees\n"); 3050 return (-1); 3051 } 3052 3053 error = bus_dmamem_alloc(dr->dr_ring_dtag, 3054 &dr->dr_ring_descbase, BUS_DMA_WAITOK | BUS_DMA_ZERO, 3055 &dr->dr_ring_dmap); 3056 if (error) { 3057 device_printf(sc->sc_dev, 3058 "can't allocate DMA mem: TODO frees\n"); 3059 return (-1); 3060 } 3061 error = bus_dmamap_load(dr->dr_ring_dtag, dr->dr_ring_dmap, 3062 dr->dr_ring_descbase, BWN_DMA_RINGMEMSIZE, 3063 bwn_dma_ring_addr, &dr->dr_ring_dmabase, BUS_DMA_NOWAIT); 3064 if (error) { 3065 device_printf(sc->sc_dev, 3066 "can't load DMA mem: TODO free\n"); 3067 return (-1); 3068 } 3069 3070 return (0); 3071 } 3072 3073 static void 3074 bwn_dma_setup(struct bwn_dma_ring *dr) 3075 { 3076 struct bwn_softc *sc = dr->dr_mac->mac_sc; 3077 uint64_t ring64; 3078 uint32_t addrext, ring32, value; 3079 uint32_t trans = siba_dma_translation(sc->sc_dev); 3080 3081 if (dr->dr_tx) { 3082 dr->dr_curslot = -1; 3083 3084 if (dr->dr_type == BWN_DMA_64BIT) { 3085 ring64 = (uint64_t)(dr->dr_ring_dmabase); 3086 addrext = ((ring64 >> 32) & SIBA_DMA_TRANSLATION_MASK) 3087 >> 30; 3088 value = BWN_DMA64_TXENABLE; 3089 value |= (addrext << BWN_DMA64_TXADDREXT_SHIFT) 3090 & BWN_DMA64_TXADDREXT_MASK; 3091 BWN_DMA_WRITE(dr, BWN_DMA64_TXCTL, value); 3092 BWN_DMA_WRITE(dr, BWN_DMA64_TXRINGLO, 3093 (ring64 & 0xffffffff)); 3094 BWN_DMA_WRITE(dr, BWN_DMA64_TXRINGHI, 3095 ((ring64 >> 32) & 3096 ~SIBA_DMA_TRANSLATION_MASK) | (trans << 1)); 3097 } else { 3098 ring32 = (uint32_t)(dr->dr_ring_dmabase); 3099 addrext = (ring32 & SIBA_DMA_TRANSLATION_MASK) >> 30; 3100 value = BWN_DMA32_TXENABLE; 3101 value |= (addrext << BWN_DMA32_TXADDREXT_SHIFT) 3102 & BWN_DMA32_TXADDREXT_MASK; 3103 BWN_DMA_WRITE(dr, BWN_DMA32_TXCTL, value); 3104 BWN_DMA_WRITE(dr, BWN_DMA32_TXRING, 3105 (ring32 & ~SIBA_DMA_TRANSLATION_MASK) | trans); 3106 } 3107 return; 3108 } 3109 3110 /* 3111 * set for RX 3112 */ 3113 dr->dr_usedslot = dr->dr_numslots; 3114 3115 if (dr->dr_type == BWN_DMA_64BIT) { 3116 ring64 = (uint64_t)(dr->dr_ring_dmabase); 3117 addrext = ((ring64 >> 32) & SIBA_DMA_TRANSLATION_MASK) >> 30; 3118 value = (dr->dr_frameoffset << BWN_DMA64_RXFROFF_SHIFT); 3119 value |= BWN_DMA64_RXENABLE; 3120 value |= (addrext << BWN_DMA64_RXADDREXT_SHIFT) 3121 & BWN_DMA64_RXADDREXT_MASK; 3122 BWN_DMA_WRITE(dr, BWN_DMA64_RXCTL, value); 3123 BWN_DMA_WRITE(dr, BWN_DMA64_RXRINGLO, (ring64 & 0xffffffff)); 3124 BWN_DMA_WRITE(dr, BWN_DMA64_RXRINGHI, 3125 ((ring64 >> 32) & ~SIBA_DMA_TRANSLATION_MASK) 3126 | (trans << 1)); 3127 BWN_DMA_WRITE(dr, BWN_DMA64_RXINDEX, dr->dr_numslots * 3128 sizeof(struct bwn_dmadesc64)); 3129 } else { 3130 ring32 = (uint32_t)(dr->dr_ring_dmabase); 3131 addrext = (ring32 & SIBA_DMA_TRANSLATION_MASK) >> 30; 3132 value = (dr->dr_frameoffset << BWN_DMA32_RXFROFF_SHIFT); 3133 value |= BWN_DMA32_RXENABLE; 3134 value |= (addrext << BWN_DMA32_RXADDREXT_SHIFT) 3135 & BWN_DMA32_RXADDREXT_MASK; 3136 BWN_DMA_WRITE(dr, BWN_DMA32_RXCTL, value); 3137 BWN_DMA_WRITE(dr, BWN_DMA32_RXRING, 3138 (ring32 & ~SIBA_DMA_TRANSLATION_MASK) | trans); 3139 BWN_DMA_WRITE(dr, BWN_DMA32_RXINDEX, dr->dr_numslots * 3140 sizeof(struct bwn_dmadesc32)); 3141 } 3142 } 3143 3144 static void 3145 bwn_dma_free_ringmemory(struct bwn_dma_ring *dr) 3146 { 3147 3148 bus_dmamap_unload(dr->dr_ring_dtag, dr->dr_ring_dmap); 3149 bus_dmamem_free(dr->dr_ring_dtag, dr->dr_ring_descbase, 3150 dr->dr_ring_dmap); 3151 } 3152 3153 static void 3154 bwn_dma_cleanup(struct bwn_dma_ring *dr) 3155 { 3156 3157 if (dr->dr_tx) { 3158 bwn_dma_tx_reset(dr->dr_mac, dr->dr_base, dr->dr_type); 3159 if (dr->dr_type == BWN_DMA_64BIT) { 3160 BWN_DMA_WRITE(dr, BWN_DMA64_TXRINGLO, 0); 3161 BWN_DMA_WRITE(dr, BWN_DMA64_TXRINGHI, 0); 3162 } else 3163 BWN_DMA_WRITE(dr, BWN_DMA32_TXRING, 0); 3164 } else { 3165 bwn_dma_rx_reset(dr->dr_mac, dr->dr_base, dr->dr_type); 3166 if (dr->dr_type == BWN_DMA_64BIT) { 3167 BWN_DMA_WRITE(dr, BWN_DMA64_RXRINGLO, 0); 3168 BWN_DMA_WRITE(dr, BWN_DMA64_RXRINGHI, 0); 3169 } else 3170 BWN_DMA_WRITE(dr, BWN_DMA32_RXRING, 0); 3171 } 3172 } 3173 3174 static void 3175 bwn_dma_free_descbufs(struct bwn_dma_ring *dr) 3176 { 3177 struct bwn_dmadesc_generic *desc; 3178 struct bwn_dmadesc_meta *meta; 3179 struct bwn_mac *mac = dr->dr_mac; 3180 struct bwn_dma *dma = &mac->mac_method.dma; 3181 struct bwn_softc *sc = mac->mac_sc; 3182 int i; 3183 3184 if (!dr->dr_usedslot) 3185 return; 3186 for (i = 0; i < dr->dr_numslots; i++) { 3187 dr->getdesc(dr, i, &desc, &meta); 3188 3189 if (meta->mt_m == NULL) { 3190 if (!dr->dr_tx) 3191 device_printf(sc->sc_dev, "%s: not TX?\n", 3192 __func__); 3193 continue; 3194 } 3195 if (dr->dr_tx) { 3196 if (meta->mt_txtype == BWN_DMADESC_METATYPE_HEADER) 3197 bus_dmamap_unload(dr->dr_txring_dtag, 3198 meta->mt_dmap); 3199 else if (meta->mt_txtype == BWN_DMADESC_METATYPE_BODY) 3200 bus_dmamap_unload(dma->txbuf_dtag, 3201 meta->mt_dmap); 3202 } else 3203 bus_dmamap_unload(dma->rxbuf_dtag, meta->mt_dmap); 3204 bwn_dma_free_descbuf(dr, meta); 3205 } 3206 } 3207 3208 static int 3209 bwn_dma_tx_reset(struct bwn_mac *mac, uint16_t base, 3210 int type) 3211 { 3212 struct bwn_softc *sc = mac->mac_sc; 3213 uint32_t value; 3214 int i; 3215 uint16_t offset; 3216 3217 for (i = 0; i < 10; i++) { 3218 offset = (type == BWN_DMA_64BIT) ? BWN_DMA64_TXSTATUS : 3219 BWN_DMA32_TXSTATUS; 3220 value = BWN_READ_4(mac, base + offset); 3221 if (type == BWN_DMA_64BIT) { 3222 value &= BWN_DMA64_TXSTAT; 3223 if (value == BWN_DMA64_TXSTAT_DISABLED || 3224 value == BWN_DMA64_TXSTAT_IDLEWAIT || 3225 value == BWN_DMA64_TXSTAT_STOPPED) 3226 break; 3227 } else { 3228 value &= BWN_DMA32_TXSTATE; 3229 if (value == BWN_DMA32_TXSTAT_DISABLED || 3230 value == BWN_DMA32_TXSTAT_IDLEWAIT || 3231 value == BWN_DMA32_TXSTAT_STOPPED) 3232 break; 3233 } 3234 DELAY(1000); 3235 } 3236 offset = (type == BWN_DMA_64BIT) ? BWN_DMA64_TXCTL : BWN_DMA32_TXCTL; 3237 BWN_WRITE_4(mac, base + offset, 0); 3238 for (i = 0; i < 10; i++) { 3239 offset = (type == BWN_DMA_64BIT) ? BWN_DMA64_TXSTATUS : 3240 BWN_DMA32_TXSTATUS; 3241 value = BWN_READ_4(mac, base + offset); 3242 if (type == BWN_DMA_64BIT) { 3243 value &= BWN_DMA64_TXSTAT; 3244 if (value == BWN_DMA64_TXSTAT_DISABLED) { 3245 i = -1; 3246 break; 3247 } 3248 } else { 3249 value &= BWN_DMA32_TXSTATE; 3250 if (value == BWN_DMA32_TXSTAT_DISABLED) { 3251 i = -1; 3252 break; 3253 } 3254 } 3255 DELAY(1000); 3256 } 3257 if (i != -1) { 3258 device_printf(sc->sc_dev, "%s: timed out\n", __func__); 3259 return (ENODEV); 3260 } 3261 DELAY(1000); 3262 3263 return (0); 3264 } 3265 3266 static int 3267 bwn_dma_rx_reset(struct bwn_mac *mac, uint16_t base, 3268 int type) 3269 { 3270 struct bwn_softc *sc = mac->mac_sc; 3271 uint32_t value; 3272 int i; 3273 uint16_t offset; 3274 3275 offset = (type == BWN_DMA_64BIT) ? BWN_DMA64_RXCTL : BWN_DMA32_RXCTL; 3276 BWN_WRITE_4(mac, base + offset, 0); 3277 for (i = 0; i < 10; i++) { 3278 offset = (type == BWN_DMA_64BIT) ? BWN_DMA64_RXSTATUS : 3279 BWN_DMA32_RXSTATUS; 3280 value = BWN_READ_4(mac, base + offset); 3281 if (type == BWN_DMA_64BIT) { 3282 value &= BWN_DMA64_RXSTAT; 3283 if (value == BWN_DMA64_RXSTAT_DISABLED) { 3284 i = -1; 3285 break; 3286 } 3287 } else { 3288 value &= BWN_DMA32_RXSTATE; 3289 if (value == BWN_DMA32_RXSTAT_DISABLED) { 3290 i = -1; 3291 break; 3292 } 3293 } 3294 DELAY(1000); 3295 } 3296 if (i != -1) { 3297 device_printf(sc->sc_dev, "%s: timed out\n", __func__); 3298 return (ENODEV); 3299 } 3300 3301 return (0); 3302 } 3303 3304 static void 3305 bwn_dma_free_descbuf(struct bwn_dma_ring *dr, 3306 struct bwn_dmadesc_meta *meta) 3307 { 3308 3309 if (meta->mt_m != NULL) { 3310 m_freem(meta->mt_m); 3311 meta->mt_m = NULL; 3312 } 3313 if (meta->mt_ni != NULL) { 3314 ieee80211_free_node(meta->mt_ni); 3315 meta->mt_ni = NULL; 3316 } 3317 } 3318 3319 static void 3320 bwn_dma_set_redzone(struct bwn_dma_ring *dr, struct mbuf *m) 3321 { 3322 struct bwn_rxhdr4 *rxhdr; 3323 unsigned char *frame; 3324 3325 rxhdr = mtod(m, struct bwn_rxhdr4 *); 3326 rxhdr->frame_len = 0; 3327 3328 KASSERT(dr->dr_rx_bufsize >= dr->dr_frameoffset + 3329 sizeof(struct bwn_plcp6) + 2, 3330 ("%s:%d: fail", __func__, __LINE__)); 3331 frame = mtod(m, char *) + dr->dr_frameoffset; 3332 memset(frame, 0xff, sizeof(struct bwn_plcp6) + 2 /* padding */); 3333 } 3334 3335 static uint8_t 3336 bwn_dma_check_redzone(struct bwn_dma_ring *dr, struct mbuf *m) 3337 { 3338 unsigned char *f = mtod(m, char *) + dr->dr_frameoffset; 3339 3340 return ((f[0] & f[1] & f[2] & f[3] & f[4] & f[5] & f[6] & f[7]) 3341 == 0xff); 3342 } 3343 3344 static void 3345 bwn_wme_init(struct bwn_mac *mac) 3346 { 3347 3348 bwn_wme_load(mac); 3349 3350 /* enable WME support. */ 3351 bwn_hf_write(mac, bwn_hf_read(mac) | BWN_HF_EDCF); 3352 BWN_WRITE_2(mac, BWN_IFSCTL, BWN_READ_2(mac, BWN_IFSCTL) | 3353 BWN_IFSCTL_USE_EDCF); 3354 } 3355 3356 static void 3357 bwn_spu_setdelay(struct bwn_mac *mac, int idle) 3358 { 3359 struct bwn_softc *sc = mac->mac_sc; 3360 struct ieee80211com *ic = &sc->sc_ic; 3361 uint16_t delay; /* microsec */ 3362 3363 delay = (mac->mac_phy.type == BWN_PHYTYPE_A) ? 3700 : 1050; 3364 if (ic->ic_opmode == IEEE80211_M_IBSS || idle) 3365 delay = 500; 3366 if ((mac->mac_phy.rf_ver == 0x2050) && (mac->mac_phy.rf_rev == 8)) 3367 delay = max(delay, (uint16_t)2400); 3368 3369 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_SPU_WAKEUP, delay); 3370 } 3371 3372 static void 3373 bwn_bt_enable(struct bwn_mac *mac) 3374 { 3375 struct bwn_softc *sc = mac->mac_sc; 3376 uint64_t hf; 3377 3378 if (bwn_bluetooth == 0) 3379 return; 3380 if ((siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_BTCOEXIST) == 0) 3381 return; 3382 if (mac->mac_phy.type != BWN_PHYTYPE_B && !mac->mac_phy.gmode) 3383 return; 3384 3385 hf = bwn_hf_read(mac); 3386 if (siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_BTCMOD) 3387 hf |= BWN_HF_BT_COEXISTALT; 3388 else 3389 hf |= BWN_HF_BT_COEXIST; 3390 bwn_hf_write(mac, hf); 3391 } 3392 3393 static void 3394 bwn_set_macaddr(struct bwn_mac *mac) 3395 { 3396 3397 bwn_mac_write_bssid(mac); 3398 bwn_mac_setfilter(mac, BWN_MACFILTER_SELF, 3399 mac->mac_sc->sc_ic.ic_macaddr); 3400 } 3401 3402 static void 3403 bwn_clear_keys(struct bwn_mac *mac) 3404 { 3405 int i; 3406 3407 for (i = 0; i < mac->mac_max_nr_keys; i++) { 3408 KASSERT(i >= 0 && i < mac->mac_max_nr_keys, 3409 ("%s:%d: fail", __func__, __LINE__)); 3410 3411 bwn_key_dowrite(mac, i, BWN_SEC_ALGO_NONE, 3412 NULL, BWN_SEC_KEYSIZE, NULL); 3413 if ((i <= 3) && !BWN_SEC_NEWAPI(mac)) { 3414 bwn_key_dowrite(mac, i + 4, BWN_SEC_ALGO_NONE, 3415 NULL, BWN_SEC_KEYSIZE, NULL); 3416 } 3417 mac->mac_key[i].keyconf = NULL; 3418 } 3419 } 3420 3421 static void 3422 bwn_crypt_init(struct bwn_mac *mac) 3423 { 3424 struct bwn_softc *sc = mac->mac_sc; 3425 3426 mac->mac_max_nr_keys = (siba_get_revid(sc->sc_dev) >= 5) ? 58 : 20; 3427 KASSERT(mac->mac_max_nr_keys <= N(mac->mac_key), 3428 ("%s:%d: fail", __func__, __LINE__)); 3429 mac->mac_ktp = bwn_shm_read_2(mac, BWN_SHARED, BWN_SHARED_KEY_TABLEP); 3430 mac->mac_ktp *= 2; 3431 if (siba_get_revid(sc->sc_dev) >= 5) 3432 BWN_WRITE_2(mac, BWN_RCMTA_COUNT, mac->mac_max_nr_keys - 8); 3433 bwn_clear_keys(mac); 3434 } 3435 3436 static void 3437 bwn_chip_exit(struct bwn_mac *mac) 3438 { 3439 struct bwn_softc *sc = mac->mac_sc; 3440 3441 bwn_phy_exit(mac); 3442 siba_gpio_set(sc->sc_dev, 0); 3443 } 3444 3445 static int 3446 bwn_fw_fillinfo(struct bwn_mac *mac) 3447 { 3448 int error; 3449 3450 error = bwn_fw_gets(mac, BWN_FWTYPE_DEFAULT); 3451 if (error == 0) 3452 return (0); 3453 error = bwn_fw_gets(mac, BWN_FWTYPE_OPENSOURCE); 3454 if (error == 0) 3455 return (0); 3456 return (error); 3457 } 3458 3459 static int 3460 bwn_gpio_init(struct bwn_mac *mac) 3461 { 3462 struct bwn_softc *sc = mac->mac_sc; 3463 uint32_t mask = 0x1f, set = 0xf, value; 3464 3465 BWN_WRITE_4(mac, BWN_MACCTL, 3466 BWN_READ_4(mac, BWN_MACCTL) & ~BWN_MACCTL_GPOUT_MASK); 3467 BWN_WRITE_2(mac, BWN_GPIO_MASK, 3468 BWN_READ_2(mac, BWN_GPIO_MASK) | 0x000f); 3469 3470 if (siba_get_chipid(sc->sc_dev) == 0x4301) { 3471 mask |= 0x0060; 3472 set |= 0x0060; 3473 } 3474 if (siba_sprom_get_bf_lo(sc->sc_dev) & BWN_BFL_PACTRL) { 3475 BWN_WRITE_2(mac, BWN_GPIO_MASK, 3476 BWN_READ_2(mac, BWN_GPIO_MASK) | 0x0200); 3477 mask |= 0x0200; 3478 set |= 0x0200; 3479 } 3480 if (siba_get_revid(sc->sc_dev) >= 2) 3481 mask |= 0x0010; 3482 3483 value = siba_gpio_get(sc->sc_dev); 3484 if (value == -1) 3485 return (0); 3486 siba_gpio_set(sc->sc_dev, (value & mask) | set); 3487 3488 return (0); 3489 } 3490 3491 static int 3492 bwn_fw_loadinitvals(struct bwn_mac *mac) 3493 { 3494 #define GETFWOFFSET(fwp, offset) \ 3495 ((const struct bwn_fwinitvals *)((const char *)fwp.fw->data + offset)) 3496 const size_t hdr_len = sizeof(struct bwn_fwhdr); 3497 const struct bwn_fwhdr *hdr; 3498 struct bwn_fw *fw = &mac->mac_fw; 3499 int error; 3500 3501 hdr = (const struct bwn_fwhdr *)(fw->initvals.fw->data); 3502 error = bwn_fwinitvals_write(mac, GETFWOFFSET(fw->initvals, hdr_len), 3503 be32toh(hdr->size), fw->initvals.fw->datasize - hdr_len); 3504 if (error) 3505 return (error); 3506 if (fw->initvals_band.fw) { 3507 hdr = (const struct bwn_fwhdr *)(fw->initvals_band.fw->data); 3508 error = bwn_fwinitvals_write(mac, 3509 GETFWOFFSET(fw->initvals_band, hdr_len), 3510 be32toh(hdr->size), 3511 fw->initvals_band.fw->datasize - hdr_len); 3512 } 3513 return (error); 3514 #undef GETFWOFFSET 3515 } 3516 3517 static int 3518 bwn_phy_init(struct bwn_mac *mac) 3519 { 3520 struct bwn_softc *sc = mac->mac_sc; 3521 int error; 3522 3523 mac->mac_phy.chan = mac->mac_phy.get_default_chan(mac); 3524 mac->mac_phy.rf_onoff(mac, 1); 3525 error = mac->mac_phy.init(mac); 3526 if (error) { 3527 device_printf(sc->sc_dev, "PHY init failed\n"); 3528 goto fail0; 3529 } 3530 error = bwn_switch_channel(mac, 3531 mac->mac_phy.get_default_chan(mac)); 3532 if (error) { 3533 device_printf(sc->sc_dev, 3534 "failed to switch default channel\n"); 3535 goto fail1; 3536 } 3537 return (0); 3538 fail1: 3539 if (mac->mac_phy.exit) 3540 mac->mac_phy.exit(mac); 3541 fail0: 3542 mac->mac_phy.rf_onoff(mac, 0); 3543 3544 return (error); 3545 } 3546 3547 static void 3548 bwn_set_txantenna(struct bwn_mac *mac, int antenna) 3549 { 3550 uint16_t ant; 3551 uint16_t tmp; 3552 3553 ant = bwn_ant2phy(antenna); 3554 3555 /* For ACK/CTS */ 3556 tmp = bwn_shm_read_2(mac, BWN_SHARED, BWN_SHARED_ACKCTS_PHYCTL); 3557 tmp = (tmp & ~BWN_TX_PHY_ANT) | ant; 3558 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_ACKCTS_PHYCTL, tmp); 3559 /* For Probe Resposes */ 3560 tmp = bwn_shm_read_2(mac, BWN_SHARED, BWN_SHARED_PROBE_RESP_PHYCTL); 3561 tmp = (tmp & ~BWN_TX_PHY_ANT) | ant; 3562 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_PROBE_RESP_PHYCTL, tmp); 3563 } 3564 3565 static void 3566 bwn_set_opmode(struct bwn_mac *mac) 3567 { 3568 struct bwn_softc *sc = mac->mac_sc; 3569 struct ieee80211com *ic = &sc->sc_ic; 3570 uint32_t ctl; 3571 uint16_t cfp_pretbtt; 3572 3573 ctl = BWN_READ_4(mac, BWN_MACCTL); 3574 ctl &= ~(BWN_MACCTL_HOSTAP | BWN_MACCTL_PASS_CTL | 3575 BWN_MACCTL_PASS_BADPLCP | BWN_MACCTL_PASS_BADFCS | 3576 BWN_MACCTL_PROMISC | BWN_MACCTL_BEACON_PROMISC); 3577 ctl |= BWN_MACCTL_STA; 3578 3579 if (ic->ic_opmode == IEEE80211_M_HOSTAP || 3580 ic->ic_opmode == IEEE80211_M_MBSS) 3581 ctl |= BWN_MACCTL_HOSTAP; 3582 else if (ic->ic_opmode == IEEE80211_M_IBSS) 3583 ctl &= ~BWN_MACCTL_STA; 3584 ctl |= sc->sc_filters; 3585 3586 if (siba_get_revid(sc->sc_dev) <= 4) 3587 ctl |= BWN_MACCTL_PROMISC; 3588 3589 BWN_WRITE_4(mac, BWN_MACCTL, ctl); 3590 3591 cfp_pretbtt = 2; 3592 if ((ctl & BWN_MACCTL_STA) && !(ctl & BWN_MACCTL_HOSTAP)) { 3593 if (siba_get_chipid(sc->sc_dev) == 0x4306 && 3594 siba_get_chiprev(sc->sc_dev) == 3) 3595 cfp_pretbtt = 100; 3596 else 3597 cfp_pretbtt = 50; 3598 } 3599 BWN_WRITE_2(mac, 0x612, cfp_pretbtt); 3600 } 3601 3602 static int 3603 bwn_dma_gettype(struct bwn_mac *mac) 3604 { 3605 uint32_t tmp; 3606 uint16_t base; 3607 3608 tmp = BWN_READ_4(mac, SIBA_TGSHIGH); 3609 if (tmp & SIBA_TGSHIGH_DMA64) 3610 return (BWN_DMA_64BIT); 3611 base = bwn_dma_base(0, 0); 3612 BWN_WRITE_4(mac, base + BWN_DMA32_TXCTL, BWN_DMA32_TXADDREXT_MASK); 3613 tmp = BWN_READ_4(mac, base + BWN_DMA32_TXCTL); 3614 if (tmp & BWN_DMA32_TXADDREXT_MASK) 3615 return (BWN_DMA_32BIT); 3616 3617 return (BWN_DMA_30BIT); 3618 } 3619 3620 static void 3621 bwn_dma_ring_addr(void *arg, bus_dma_segment_t *seg, int nseg, int error) 3622 { 3623 if (!error) { 3624 KASSERT(nseg == 1, ("too many segments(%d)\n", nseg)); 3625 *((bus_addr_t *)arg) = seg->ds_addr; 3626 } 3627 } 3628 3629 void 3630 bwn_dummy_transmission(struct bwn_mac *mac, int ofdm, int paon) 3631 { 3632 struct bwn_phy *phy = &mac->mac_phy; 3633 struct bwn_softc *sc = mac->mac_sc; 3634 unsigned int i, max_loop; 3635 uint16_t value; 3636 uint32_t buffer[5] = { 3637 0x00000000, 0x00d40000, 0x00000000, 0x01000000, 0x00000000 3638 }; 3639 3640 if (ofdm) { 3641 max_loop = 0x1e; 3642 buffer[0] = 0x000201cc; 3643 } else { 3644 max_loop = 0xfa; 3645 buffer[0] = 0x000b846e; 3646 } 3647 3648 BWN_ASSERT_LOCKED(mac->mac_sc); 3649 3650 for (i = 0; i < 5; i++) 3651 bwn_ram_write(mac, i * 4, buffer[i]); 3652 3653 BWN_WRITE_2(mac, 0x0568, 0x0000); 3654 BWN_WRITE_2(mac, 0x07c0, 3655 (siba_get_revid(sc->sc_dev) < 11) ? 0x0000 : 0x0100); 3656 3657 value = (ofdm ? 0x41 : 0x40); 3658 BWN_WRITE_2(mac, 0x050c, value); 3659 3660 if (phy->type == BWN_PHYTYPE_N || phy->type == BWN_PHYTYPE_LP || 3661 phy->type == BWN_PHYTYPE_LCN) 3662 BWN_WRITE_2(mac, 0x0514, 0x1a02); 3663 BWN_WRITE_2(mac, 0x0508, 0x0000); 3664 BWN_WRITE_2(mac, 0x050a, 0x0000); 3665 BWN_WRITE_2(mac, 0x054c, 0x0000); 3666 BWN_WRITE_2(mac, 0x056a, 0x0014); 3667 BWN_WRITE_2(mac, 0x0568, 0x0826); 3668 BWN_WRITE_2(mac, 0x0500, 0x0000); 3669 3670 /* XXX TODO: n phy pa override? */ 3671 3672 switch (phy->type) { 3673 case BWN_PHYTYPE_N: 3674 case BWN_PHYTYPE_LCN: 3675 BWN_WRITE_2(mac, 0x0502, 0x00d0); 3676 break; 3677 case BWN_PHYTYPE_LP: 3678 BWN_WRITE_2(mac, 0x0502, 0x0050); 3679 break; 3680 default: 3681 BWN_WRITE_2(mac, 0x0502, 0x0030); 3682 break; 3683 } 3684 3685 /* flush */ 3686 BWN_READ_2(mac, 0x0502); 3687 3688 if (phy->rf_ver == 0x2050 && phy->rf_rev <= 0x5) 3689 BWN_RF_WRITE(mac, 0x0051, 0x0017); 3690 for (i = 0x00; i < max_loop; i++) { 3691 value = BWN_READ_2(mac, 0x050e); 3692 if (value & 0x0080) 3693 break; 3694 DELAY(10); 3695 } 3696 for (i = 0x00; i < 0x0a; i++) { 3697 value = BWN_READ_2(mac, 0x050e); 3698 if (value & 0x0400) 3699 break; 3700 DELAY(10); 3701 } 3702 for (i = 0x00; i < 0x19; i++) { 3703 value = BWN_READ_2(mac, 0x0690); 3704 if (!(value & 0x0100)) 3705 break; 3706 DELAY(10); 3707 } 3708 if (phy->rf_ver == 0x2050 && phy->rf_rev <= 0x5) 3709 BWN_RF_WRITE(mac, 0x0051, 0x0037); 3710 } 3711 3712 void 3713 bwn_ram_write(struct bwn_mac *mac, uint16_t offset, uint32_t val) 3714 { 3715 uint32_t macctl; 3716 3717 KASSERT(offset % 4 == 0, ("%s:%d: fail", __func__, __LINE__)); 3718 3719 macctl = BWN_READ_4(mac, BWN_MACCTL); 3720 if (macctl & BWN_MACCTL_BIGENDIAN) 3721 printf("TODO: need swap\n"); 3722 3723 BWN_WRITE_4(mac, BWN_RAM_CONTROL, offset); 3724 BWN_BARRIER(mac, BUS_SPACE_BARRIER_WRITE); 3725 BWN_WRITE_4(mac, BWN_RAM_DATA, val); 3726 } 3727 3728 void 3729 bwn_mac_suspend(struct bwn_mac *mac) 3730 { 3731 struct bwn_softc *sc = mac->mac_sc; 3732 int i; 3733 uint32_t tmp; 3734 3735 KASSERT(mac->mac_suspended >= 0, 3736 ("%s:%d: fail", __func__, __LINE__)); 3737 3738 DPRINTF(mac->mac_sc, BWN_DEBUG_RESET, "%s: suspended=%d\n", 3739 __func__, mac->mac_suspended); 3740 3741 if (mac->mac_suspended == 0) { 3742 bwn_psctl(mac, BWN_PS_AWAKE); 3743 BWN_WRITE_4(mac, BWN_MACCTL, 3744 BWN_READ_4(mac, BWN_MACCTL) 3745 & ~BWN_MACCTL_ON); 3746 BWN_READ_4(mac, BWN_MACCTL); 3747 for (i = 35; i; i--) { 3748 tmp = BWN_READ_4(mac, BWN_INTR_REASON); 3749 if (tmp & BWN_INTR_MAC_SUSPENDED) 3750 goto out; 3751 DELAY(10); 3752 } 3753 for (i = 40; i; i--) { 3754 tmp = BWN_READ_4(mac, BWN_INTR_REASON); 3755 if (tmp & BWN_INTR_MAC_SUSPENDED) 3756 goto out; 3757 DELAY(1000); 3758 } 3759 device_printf(sc->sc_dev, "MAC suspend failed\n"); 3760 } 3761 out: 3762 mac->mac_suspended++; 3763 } 3764 3765 void 3766 bwn_mac_enable(struct bwn_mac *mac) 3767 { 3768 struct bwn_softc *sc = mac->mac_sc; 3769 uint16_t state; 3770 3771 DPRINTF(mac->mac_sc, BWN_DEBUG_RESET, "%s: suspended=%d\n", 3772 __func__, mac->mac_suspended); 3773 3774 state = bwn_shm_read_2(mac, BWN_SHARED, 3775 BWN_SHARED_UCODESTAT); 3776 if (state != BWN_SHARED_UCODESTAT_SUSPEND && 3777 state != BWN_SHARED_UCODESTAT_SLEEP) { 3778 DPRINTF(sc, BWN_DEBUG_FW, 3779 "%s: warn: firmware state (%d)\n", 3780 __func__, state); 3781 } 3782 3783 mac->mac_suspended--; 3784 KASSERT(mac->mac_suspended >= 0, 3785 ("%s:%d: fail", __func__, __LINE__)); 3786 if (mac->mac_suspended == 0) { 3787 BWN_WRITE_4(mac, BWN_MACCTL, 3788 BWN_READ_4(mac, BWN_MACCTL) | BWN_MACCTL_ON); 3789 BWN_WRITE_4(mac, BWN_INTR_REASON, BWN_INTR_MAC_SUSPENDED); 3790 BWN_READ_4(mac, BWN_MACCTL); 3791 BWN_READ_4(mac, BWN_INTR_REASON); 3792 bwn_psctl(mac, 0); 3793 } 3794 } 3795 3796 void 3797 bwn_psctl(struct bwn_mac *mac, uint32_t flags) 3798 { 3799 struct bwn_softc *sc = mac->mac_sc; 3800 int i; 3801 uint16_t ucstat; 3802 3803 KASSERT(!((flags & BWN_PS_ON) && (flags & BWN_PS_OFF)), 3804 ("%s:%d: fail", __func__, __LINE__)); 3805 KASSERT(!((flags & BWN_PS_AWAKE) && (flags & BWN_PS_ASLEEP)), 3806 ("%s:%d: fail", __func__, __LINE__)); 3807 3808 /* XXX forcibly awake and hwps-off */ 3809 3810 BWN_WRITE_4(mac, BWN_MACCTL, 3811 (BWN_READ_4(mac, BWN_MACCTL) | BWN_MACCTL_AWAKE) & 3812 ~BWN_MACCTL_HWPS); 3813 BWN_READ_4(mac, BWN_MACCTL); 3814 if (siba_get_revid(sc->sc_dev) >= 5) { 3815 for (i = 0; i < 100; i++) { 3816 ucstat = bwn_shm_read_2(mac, BWN_SHARED, 3817 BWN_SHARED_UCODESTAT); 3818 if (ucstat != BWN_SHARED_UCODESTAT_SLEEP) 3819 break; 3820 DELAY(10); 3821 } 3822 } 3823 DPRINTF(mac->mac_sc, BWN_DEBUG_RESET, "%s: ucstat=%d\n", __func__, 3824 ucstat); 3825 } 3826 3827 static int 3828 bwn_fw_gets(struct bwn_mac *mac, enum bwn_fwtype type) 3829 { 3830 struct bwn_softc *sc = mac->mac_sc; 3831 struct bwn_fw *fw = &mac->mac_fw; 3832 const uint8_t rev = siba_get_revid(sc->sc_dev); 3833 const char *filename; 3834 uint32_t high; 3835 int error; 3836 3837 /* microcode */ 3838 filename = NULL; 3839 switch (rev) { 3840 case 42: 3841 if (mac->mac_phy.type == BWN_PHYTYPE_AC) 3842 filename = "ucode42"; 3843 break; 3844 case 40: 3845 if (mac->mac_phy.type == BWN_PHYTYPE_AC) 3846 filename = "ucode40"; 3847 break; 3848 case 33: 3849 if (mac->mac_phy.type == BWN_PHYTYPE_LCN40) 3850 filename = "ucode33_lcn40"; 3851 break; 3852 case 30: 3853 if (mac->mac_phy.type == BWN_PHYTYPE_N) 3854 filename = "ucode30_mimo"; 3855 break; 3856 case 29: 3857 if (mac->mac_phy.type == BWN_PHYTYPE_HT) 3858 filename = "ucode29_mimo"; 3859 break; 3860 case 26: 3861 if (mac->mac_phy.type == BWN_PHYTYPE_HT) 3862 filename = "ucode26_mimo"; 3863 break; 3864 case 28: 3865 case 25: 3866 if (mac->mac_phy.type == BWN_PHYTYPE_N) 3867 filename = "ucode25_mimo"; 3868 else if (mac->mac_phy.type == BWN_PHYTYPE_LCN) 3869 filename = "ucode25_lcn"; 3870 break; 3871 case 24: 3872 if (mac->mac_phy.type == BWN_PHYTYPE_LCN) 3873 filename = "ucode24_lcn"; 3874 break; 3875 case 23: 3876 if (mac->mac_phy.type == BWN_PHYTYPE_N) 3877 filename = "ucode16_mimo"; 3878 break; 3879 case 16: 3880 case 17: 3881 case 18: 3882 case 19: 3883 if (mac->mac_phy.type == BWN_PHYTYPE_N) 3884 filename = "ucode16_mimo"; 3885 else if (mac->mac_phy.type == BWN_PHYTYPE_LP) 3886 filename = "ucode16_lp"; 3887 break; 3888 case 15: 3889 filename = "ucode15"; 3890 break; 3891 case 14: 3892 filename = "ucode14"; 3893 break; 3894 case 13: 3895 filename = "ucode13"; 3896 break; 3897 case 12: 3898 case 11: 3899 filename = "ucode11"; 3900 break; 3901 case 10: 3902 case 9: 3903 case 8: 3904 case 7: 3905 case 6: 3906 case 5: 3907 filename = "ucode5"; 3908 break; 3909 default: 3910 device_printf(sc->sc_dev, "no ucode for rev %d\n", rev); 3911 bwn_release_firmware(mac); 3912 return (EOPNOTSUPP); 3913 } 3914 3915 device_printf(sc->sc_dev, "ucode fw: %s\n", filename); 3916 error = bwn_fw_get(mac, type, filename, &fw->ucode); 3917 if (error) { 3918 bwn_release_firmware(mac); 3919 return (error); 3920 } 3921 3922 /* PCM */ 3923 KASSERT(fw->no_pcmfile == 0, ("%s:%d fail", __func__, __LINE__)); 3924 if (rev >= 5 && rev <= 10) { 3925 error = bwn_fw_get(mac, type, "pcm5", &fw->pcm); 3926 if (error == ENOENT) 3927 fw->no_pcmfile = 1; 3928 else if (error) { 3929 bwn_release_firmware(mac); 3930 return (error); 3931 } 3932 } else if (rev < 11) { 3933 device_printf(sc->sc_dev, "no PCM for rev %d\n", rev); 3934 return (EOPNOTSUPP); 3935 } 3936 3937 /* initvals */ 3938 high = siba_read_4(sc->sc_dev, SIBA_TGSHIGH); 3939 switch (mac->mac_phy.type) { 3940 case BWN_PHYTYPE_A: 3941 if (rev < 5 || rev > 10) 3942 goto fail1; 3943 if (high & BWN_TGSHIGH_HAVE_2GHZ) 3944 filename = "a0g1initvals5"; 3945 else 3946 filename = "a0g0initvals5"; 3947 break; 3948 case BWN_PHYTYPE_G: 3949 if (rev >= 5 && rev <= 10) 3950 filename = "b0g0initvals5"; 3951 else if (rev >= 13) 3952 filename = "b0g0initvals13"; 3953 else 3954 goto fail1; 3955 break; 3956 case BWN_PHYTYPE_LP: 3957 if (rev == 13) 3958 filename = "lp0initvals13"; 3959 else if (rev == 14) 3960 filename = "lp0initvals14"; 3961 else if (rev >= 15) 3962 filename = "lp0initvals15"; 3963 else 3964 goto fail1; 3965 break; 3966 case BWN_PHYTYPE_N: 3967 if (rev == 30) 3968 filename = "n16initvals30"; 3969 else if (rev == 28 || rev == 25) 3970 filename = "n0initvals25"; 3971 else if (rev == 24) 3972 filename = "n0initvals24"; 3973 else if (rev == 23) 3974 filename = "n0initvals16"; 3975 else if (rev >= 16 && rev <= 18) 3976 filename = "n0initvals16"; 3977 else if (rev >= 11 && rev <= 12) 3978 filename = "n0initvals11"; 3979 else 3980 goto fail1; 3981 break; 3982 default: 3983 goto fail1; 3984 } 3985 error = bwn_fw_get(mac, type, filename, &fw->initvals); 3986 if (error) { 3987 bwn_release_firmware(mac); 3988 return (error); 3989 } 3990 3991 /* bandswitch initvals */ 3992 switch (mac->mac_phy.type) { 3993 case BWN_PHYTYPE_A: 3994 if (rev >= 5 && rev <= 10) { 3995 if (high & BWN_TGSHIGH_HAVE_2GHZ) 3996 filename = "a0g1bsinitvals5"; 3997 else 3998 filename = "a0g0bsinitvals5"; 3999 } else if (rev >= 11) 4000 filename = NULL; 4001 else 4002 goto fail1; 4003 break; 4004 case BWN_PHYTYPE_G: 4005 if (rev >= 5 && rev <= 10) 4006 filename = "b0g0bsinitvals5"; 4007 else if (rev >= 11) 4008 filename = NULL; 4009 else 4010 goto fail1; 4011 break; 4012 case BWN_PHYTYPE_LP: 4013 if (rev == 13) 4014 filename = "lp0bsinitvals13"; 4015 else if (rev == 14) 4016 filename = "lp0bsinitvals14"; 4017 else if (rev >= 15) 4018 filename = "lp0bsinitvals15"; 4019 else 4020 goto fail1; 4021 break; 4022 case BWN_PHYTYPE_N: 4023 if (rev == 30) 4024 filename = "n16bsinitvals30"; 4025 else if (rev == 28 || rev == 25) 4026 filename = "n0bsinitvals25"; 4027 else if (rev == 24) 4028 filename = "n0bsinitvals24"; 4029 else if (rev == 23) 4030 filename = "n0bsinitvals16"; 4031 else if (rev >= 16 && rev <= 18) 4032 filename = "n0bsinitvals16"; 4033 else if (rev >= 11 && rev <= 12) 4034 filename = "n0bsinitvals11"; 4035 else 4036 goto fail1; 4037 break; 4038 default: 4039 device_printf(sc->sc_dev, "unknown phy (%d)\n", 4040 mac->mac_phy.type); 4041 goto fail1; 4042 } 4043 error = bwn_fw_get(mac, type, filename, &fw->initvals_band); 4044 if (error) { 4045 bwn_release_firmware(mac); 4046 return (error); 4047 } 4048 return (0); 4049 fail1: 4050 device_printf(sc->sc_dev, "no INITVALS for rev %d, phy.type %d\n", 4051 rev, mac->mac_phy.type); 4052 bwn_release_firmware(mac); 4053 return (EOPNOTSUPP); 4054 } 4055 4056 static int 4057 bwn_fw_get(struct bwn_mac *mac, enum bwn_fwtype type, 4058 const char *name, struct bwn_fwfile *bfw) 4059 { 4060 const struct bwn_fwhdr *hdr; 4061 struct bwn_softc *sc = mac->mac_sc; 4062 const struct firmware *fw; 4063 char namebuf[64]; 4064 4065 if (name == NULL) { 4066 bwn_do_release_fw(bfw); 4067 return (0); 4068 } 4069 if (bfw->filename != NULL) { 4070 if (bfw->type == type && (strcmp(bfw->filename, name) == 0)) 4071 return (0); 4072 bwn_do_release_fw(bfw); 4073 } 4074 4075 snprintf(namebuf, sizeof(namebuf), "bwn%s_v4_%s%s", 4076 (type == BWN_FWTYPE_OPENSOURCE) ? "-open" : "", 4077 (mac->mac_phy.type == BWN_PHYTYPE_LP) ? "lp_" : "", name); 4078 /* XXX Sleeping on "fwload" with the non-sleepable locks held */ 4079 fw = firmware_get(namebuf); 4080 if (fw == NULL) { 4081 device_printf(sc->sc_dev, "the fw file(%s) not found\n", 4082 namebuf); 4083 return (ENOENT); 4084 } 4085 if (fw->datasize < sizeof(struct bwn_fwhdr)) 4086 goto fail; 4087 hdr = (const struct bwn_fwhdr *)(fw->data); 4088 switch (hdr->type) { 4089 case BWN_FWTYPE_UCODE: 4090 case BWN_FWTYPE_PCM: 4091 if (be32toh(hdr->size) != 4092 (fw->datasize - sizeof(struct bwn_fwhdr))) 4093 goto fail; 4094 /* FALLTHROUGH */ 4095 case BWN_FWTYPE_IV: 4096 if (hdr->ver != 1) 4097 goto fail; 4098 break; 4099 default: 4100 goto fail; 4101 } 4102 bfw->filename = name; 4103 bfw->fw = fw; 4104 bfw->type = type; 4105 return (0); 4106 fail: 4107 device_printf(sc->sc_dev, "the fw file(%s) format error\n", namebuf); 4108 if (fw != NULL) 4109 firmware_put(fw, FIRMWARE_UNLOAD); 4110 return (EPROTO); 4111 } 4112 4113 static void 4114 bwn_release_firmware(struct bwn_mac *mac) 4115 { 4116 4117 bwn_do_release_fw(&mac->mac_fw.ucode); 4118 bwn_do_release_fw(&mac->mac_fw.pcm); 4119 bwn_do_release_fw(&mac->mac_fw.initvals); 4120 bwn_do_release_fw(&mac->mac_fw.initvals_band); 4121 } 4122 4123 static void 4124 bwn_do_release_fw(struct bwn_fwfile *bfw) 4125 { 4126 4127 if (bfw->fw != NULL) 4128 firmware_put(bfw->fw, FIRMWARE_UNLOAD); 4129 bfw->fw = NULL; 4130 bfw->filename = NULL; 4131 } 4132 4133 static int 4134 bwn_fw_loaducode(struct bwn_mac *mac) 4135 { 4136 #define GETFWOFFSET(fwp, offset) \ 4137 ((const uint32_t *)((const char *)fwp.fw->data + offset)) 4138 #define GETFWSIZE(fwp, offset) \ 4139 ((fwp.fw->datasize - offset) / sizeof(uint32_t)) 4140 struct bwn_softc *sc = mac->mac_sc; 4141 const uint32_t *data; 4142 unsigned int i; 4143 uint32_t ctl; 4144 uint16_t date, fwcaps, time; 4145 int error = 0; 4146 4147 ctl = BWN_READ_4(mac, BWN_MACCTL); 4148 ctl |= BWN_MACCTL_MCODE_JMP0; 4149 KASSERT(!(ctl & BWN_MACCTL_MCODE_RUN), ("%s:%d: fail", __func__, 4150 __LINE__)); 4151 BWN_WRITE_4(mac, BWN_MACCTL, ctl); 4152 for (i = 0; i < 64; i++) 4153 bwn_shm_write_2(mac, BWN_SCRATCH, i, 0); 4154 for (i = 0; i < 4096; i += 2) 4155 bwn_shm_write_2(mac, BWN_SHARED, i, 0); 4156 4157 data = GETFWOFFSET(mac->mac_fw.ucode, sizeof(struct bwn_fwhdr)); 4158 bwn_shm_ctlword(mac, BWN_UCODE | BWN_SHARED_AUTOINC, 0x0000); 4159 for (i = 0; i < GETFWSIZE(mac->mac_fw.ucode, sizeof(struct bwn_fwhdr)); 4160 i++) { 4161 BWN_WRITE_4(mac, BWN_SHM_DATA, be32toh(data[i])); 4162 DELAY(10); 4163 } 4164 4165 if (mac->mac_fw.pcm.fw) { 4166 data = GETFWOFFSET(mac->mac_fw.pcm, sizeof(struct bwn_fwhdr)); 4167 bwn_shm_ctlword(mac, BWN_HW, 0x01ea); 4168 BWN_WRITE_4(mac, BWN_SHM_DATA, 0x00004000); 4169 bwn_shm_ctlword(mac, BWN_HW, 0x01eb); 4170 for (i = 0; i < GETFWSIZE(mac->mac_fw.pcm, 4171 sizeof(struct bwn_fwhdr)); i++) { 4172 BWN_WRITE_4(mac, BWN_SHM_DATA, be32toh(data[i])); 4173 DELAY(10); 4174 } 4175 } 4176 4177 BWN_WRITE_4(mac, BWN_INTR_REASON, BWN_INTR_ALL); 4178 BWN_WRITE_4(mac, BWN_MACCTL, 4179 (BWN_READ_4(mac, BWN_MACCTL) & ~BWN_MACCTL_MCODE_JMP0) | 4180 BWN_MACCTL_MCODE_RUN); 4181 4182 for (i = 0; i < 21; i++) { 4183 if (BWN_READ_4(mac, BWN_INTR_REASON) == BWN_INTR_MAC_SUSPENDED) 4184 break; 4185 if (i >= 20) { 4186 device_printf(sc->sc_dev, "ucode timeout\n"); 4187 error = ENXIO; 4188 goto error; 4189 } 4190 DELAY(50000); 4191 } 4192 BWN_READ_4(mac, BWN_INTR_REASON); 4193 4194 mac->mac_fw.rev = bwn_shm_read_2(mac, BWN_SHARED, BWN_SHARED_UCODE_REV); 4195 if (mac->mac_fw.rev <= 0x128) { 4196 device_printf(sc->sc_dev, "the firmware is too old\n"); 4197 error = EOPNOTSUPP; 4198 goto error; 4199 } 4200 4201 /* 4202 * Determine firmware header version; needed for TX/RX packet 4203 * handling. 4204 */ 4205 if (mac->mac_fw.rev >= 598) 4206 mac->mac_fw.fw_hdr_format = BWN_FW_HDR_598; 4207 else if (mac->mac_fw.rev >= 410) 4208 mac->mac_fw.fw_hdr_format = BWN_FW_HDR_410; 4209 else 4210 mac->mac_fw.fw_hdr_format = BWN_FW_HDR_351; 4211 4212 /* 4213 * We don't support rev 598 or later; that requires 4214 * another round of changes to the TX/RX descriptor 4215 * and status layout. 4216 * 4217 * So, complain this is the case and exit out, rather 4218 * than attaching and then failing. 4219 */ 4220 #if 0 4221 if (mac->mac_fw.fw_hdr_format == BWN_FW_HDR_598) { 4222 device_printf(sc->sc_dev, 4223 "firmware is too new (>=598); not supported\n"); 4224 error = EOPNOTSUPP; 4225 goto error; 4226 } 4227 #endif 4228 4229 mac->mac_fw.patch = bwn_shm_read_2(mac, BWN_SHARED, 4230 BWN_SHARED_UCODE_PATCH); 4231 date = bwn_shm_read_2(mac, BWN_SHARED, BWN_SHARED_UCODE_DATE); 4232 mac->mac_fw.opensource = (date == 0xffff); 4233 if (bwn_wme != 0) 4234 mac->mac_flags |= BWN_MAC_FLAG_WME; 4235 mac->mac_flags |= BWN_MAC_FLAG_HWCRYPTO; 4236 4237 time = bwn_shm_read_2(mac, BWN_SHARED, BWN_SHARED_UCODE_TIME); 4238 if (mac->mac_fw.opensource == 0) { 4239 device_printf(sc->sc_dev, 4240 "firmware version (rev %u patch %u date %#x time %#x)\n", 4241 mac->mac_fw.rev, mac->mac_fw.patch, date, time); 4242 if (mac->mac_fw.no_pcmfile) 4243 device_printf(sc->sc_dev, 4244 "no HW crypto acceleration due to pcm5\n"); 4245 } else { 4246 mac->mac_fw.patch = time; 4247 fwcaps = bwn_fwcaps_read(mac); 4248 if (!(fwcaps & BWN_FWCAPS_HWCRYPTO) || mac->mac_fw.no_pcmfile) { 4249 device_printf(sc->sc_dev, 4250 "disabling HW crypto acceleration\n"); 4251 mac->mac_flags &= ~BWN_MAC_FLAG_HWCRYPTO; 4252 } 4253 if (!(fwcaps & BWN_FWCAPS_WME)) { 4254 device_printf(sc->sc_dev, "disabling WME support\n"); 4255 mac->mac_flags &= ~BWN_MAC_FLAG_WME; 4256 } 4257 } 4258 4259 if (BWN_ISOLDFMT(mac)) 4260 device_printf(sc->sc_dev, "using old firmware image\n"); 4261 4262 return (0); 4263 4264 error: 4265 BWN_WRITE_4(mac, BWN_MACCTL, 4266 (BWN_READ_4(mac, BWN_MACCTL) & ~BWN_MACCTL_MCODE_RUN) | 4267 BWN_MACCTL_MCODE_JMP0); 4268 4269 return (error); 4270 #undef GETFWSIZE 4271 #undef GETFWOFFSET 4272 } 4273 4274 /* OpenFirmware only */ 4275 static uint16_t 4276 bwn_fwcaps_read(struct bwn_mac *mac) 4277 { 4278 4279 KASSERT(mac->mac_fw.opensource == 1, 4280 ("%s:%d: fail", __func__, __LINE__)); 4281 return (bwn_shm_read_2(mac, BWN_SHARED, BWN_SHARED_FWCAPS)); 4282 } 4283 4284 static int 4285 bwn_fwinitvals_write(struct bwn_mac *mac, const struct bwn_fwinitvals *ivals, 4286 size_t count, size_t array_size) 4287 { 4288 #define GET_NEXTIV16(iv) \ 4289 ((const struct bwn_fwinitvals *)((const uint8_t *)(iv) + \ 4290 sizeof(uint16_t) + sizeof(uint16_t))) 4291 #define GET_NEXTIV32(iv) \ 4292 ((const struct bwn_fwinitvals *)((const uint8_t *)(iv) + \ 4293 sizeof(uint16_t) + sizeof(uint32_t))) 4294 struct bwn_softc *sc = mac->mac_sc; 4295 const struct bwn_fwinitvals *iv; 4296 uint16_t offset; 4297 size_t i; 4298 uint8_t bit32; 4299 4300 KASSERT(sizeof(struct bwn_fwinitvals) == 6, 4301 ("%s:%d: fail", __func__, __LINE__)); 4302 iv = ivals; 4303 for (i = 0; i < count; i++) { 4304 if (array_size < sizeof(iv->offset_size)) 4305 goto fail; 4306 array_size -= sizeof(iv->offset_size); 4307 offset = be16toh(iv->offset_size); 4308 bit32 = (offset & BWN_FWINITVALS_32BIT) ? 1 : 0; 4309 offset &= BWN_FWINITVALS_OFFSET_MASK; 4310 if (offset >= 0x1000) 4311 goto fail; 4312 if (bit32) { 4313 if (array_size < sizeof(iv->data.d32)) 4314 goto fail; 4315 array_size -= sizeof(iv->data.d32); 4316 BWN_WRITE_4(mac, offset, be32toh(iv->data.d32)); 4317 iv = GET_NEXTIV32(iv); 4318 } else { 4319 4320 if (array_size < sizeof(iv->data.d16)) 4321 goto fail; 4322 array_size -= sizeof(iv->data.d16); 4323 BWN_WRITE_2(mac, offset, be16toh(iv->data.d16)); 4324 4325 iv = GET_NEXTIV16(iv); 4326 } 4327 } 4328 if (array_size != 0) 4329 goto fail; 4330 return (0); 4331 fail: 4332 device_printf(sc->sc_dev, "initvals: invalid format\n"); 4333 return (EPROTO); 4334 #undef GET_NEXTIV16 4335 #undef GET_NEXTIV32 4336 } 4337 4338 int 4339 bwn_switch_channel(struct bwn_mac *mac, int chan) 4340 { 4341 struct bwn_phy *phy = &(mac->mac_phy); 4342 struct bwn_softc *sc = mac->mac_sc; 4343 struct ieee80211com *ic = &sc->sc_ic; 4344 uint16_t channelcookie, savedcookie; 4345 int error; 4346 4347 if (chan == 0xffff) 4348 chan = phy->get_default_chan(mac); 4349 4350 channelcookie = chan; 4351 if (IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan)) 4352 channelcookie |= 0x100; 4353 savedcookie = bwn_shm_read_2(mac, BWN_SHARED, BWN_SHARED_CHAN); 4354 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_CHAN, channelcookie); 4355 error = phy->switch_channel(mac, chan); 4356 if (error) 4357 goto fail; 4358 4359 mac->mac_phy.chan = chan; 4360 DELAY(8000); 4361 return (0); 4362 fail: 4363 device_printf(sc->sc_dev, "failed to switch channel\n"); 4364 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_CHAN, savedcookie); 4365 return (error); 4366 } 4367 4368 static uint16_t 4369 bwn_ant2phy(int antenna) 4370 { 4371 4372 switch (antenna) { 4373 case BWN_ANT0: 4374 return (BWN_TX_PHY_ANT0); 4375 case BWN_ANT1: 4376 return (BWN_TX_PHY_ANT1); 4377 case BWN_ANT2: 4378 return (BWN_TX_PHY_ANT2); 4379 case BWN_ANT3: 4380 return (BWN_TX_PHY_ANT3); 4381 case BWN_ANTAUTO: 4382 return (BWN_TX_PHY_ANT01AUTO); 4383 } 4384 KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__)); 4385 return (0); 4386 } 4387 4388 static void 4389 bwn_wme_load(struct bwn_mac *mac) 4390 { 4391 struct bwn_softc *sc = mac->mac_sc; 4392 int i; 4393 4394 KASSERT(N(bwn_wme_shm_offsets) == N(sc->sc_wmeParams), 4395 ("%s:%d: fail", __func__, __LINE__)); 4396 4397 bwn_mac_suspend(mac); 4398 for (i = 0; i < N(sc->sc_wmeParams); i++) 4399 bwn_wme_loadparams(mac, &(sc->sc_wmeParams[i]), 4400 bwn_wme_shm_offsets[i]); 4401 bwn_mac_enable(mac); 4402 } 4403 4404 static void 4405 bwn_wme_loadparams(struct bwn_mac *mac, 4406 const struct wmeParams *p, uint16_t shm_offset) 4407 { 4408 #define SM(_v, _f) (((_v) << _f##_S) & _f) 4409 struct bwn_softc *sc = mac->mac_sc; 4410 uint16_t params[BWN_NR_WMEPARAMS]; 4411 int slot, tmp; 4412 unsigned int i; 4413 4414 slot = BWN_READ_2(mac, BWN_RNG) & 4415 SM(p->wmep_logcwmin, WME_PARAM_LOGCWMIN); 4416 4417 memset(¶ms, 0, sizeof(params)); 4418 4419 DPRINTF(sc, BWN_DEBUG_WME, "wmep_txopLimit %d wmep_logcwmin %d " 4420 "wmep_logcwmax %d wmep_aifsn %d\n", p->wmep_txopLimit, 4421 p->wmep_logcwmin, p->wmep_logcwmax, p->wmep_aifsn); 4422 4423 params[BWN_WMEPARAM_TXOP] = p->wmep_txopLimit * 32; 4424 params[BWN_WMEPARAM_CWMIN] = SM(p->wmep_logcwmin, WME_PARAM_LOGCWMIN); 4425 params[BWN_WMEPARAM_CWMAX] = SM(p->wmep_logcwmax, WME_PARAM_LOGCWMAX); 4426 params[BWN_WMEPARAM_CWCUR] = SM(p->wmep_logcwmin, WME_PARAM_LOGCWMIN); 4427 params[BWN_WMEPARAM_AIFS] = p->wmep_aifsn; 4428 params[BWN_WMEPARAM_BSLOTS] = slot; 4429 params[BWN_WMEPARAM_REGGAP] = slot + p->wmep_aifsn; 4430 4431 for (i = 0; i < N(params); i++) { 4432 if (i == BWN_WMEPARAM_STATUS) { 4433 tmp = bwn_shm_read_2(mac, BWN_SHARED, 4434 shm_offset + (i * 2)); 4435 tmp |= 0x100; 4436 bwn_shm_write_2(mac, BWN_SHARED, shm_offset + (i * 2), 4437 tmp); 4438 } else { 4439 bwn_shm_write_2(mac, BWN_SHARED, shm_offset + (i * 2), 4440 params[i]); 4441 } 4442 } 4443 } 4444 4445 static void 4446 bwn_mac_write_bssid(struct bwn_mac *mac) 4447 { 4448 struct bwn_softc *sc = mac->mac_sc; 4449 uint32_t tmp; 4450 int i; 4451 uint8_t mac_bssid[IEEE80211_ADDR_LEN * 2]; 4452 4453 bwn_mac_setfilter(mac, BWN_MACFILTER_BSSID, sc->sc_bssid); 4454 memcpy(mac_bssid, sc->sc_ic.ic_macaddr, IEEE80211_ADDR_LEN); 4455 memcpy(mac_bssid + IEEE80211_ADDR_LEN, sc->sc_bssid, 4456 IEEE80211_ADDR_LEN); 4457 4458 for (i = 0; i < N(mac_bssid); i += sizeof(uint32_t)) { 4459 tmp = (uint32_t) (mac_bssid[i + 0]); 4460 tmp |= (uint32_t) (mac_bssid[i + 1]) << 8; 4461 tmp |= (uint32_t) (mac_bssid[i + 2]) << 16; 4462 tmp |= (uint32_t) (mac_bssid[i + 3]) << 24; 4463 bwn_ram_write(mac, 0x20 + i, tmp); 4464 } 4465 } 4466 4467 static void 4468 bwn_mac_setfilter(struct bwn_mac *mac, uint16_t offset, 4469 const uint8_t *macaddr) 4470 { 4471 static const uint8_t zero[IEEE80211_ADDR_LEN] = { 0 }; 4472 uint16_t data; 4473 4474 if (!mac) 4475 macaddr = zero; 4476 4477 offset |= 0x0020; 4478 BWN_WRITE_2(mac, BWN_MACFILTER_CONTROL, offset); 4479 4480 data = macaddr[0]; 4481 data |= macaddr[1] << 8; 4482 BWN_WRITE_2(mac, BWN_MACFILTER_DATA, data); 4483 data = macaddr[2]; 4484 data |= macaddr[3] << 8; 4485 BWN_WRITE_2(mac, BWN_MACFILTER_DATA, data); 4486 data = macaddr[4]; 4487 data |= macaddr[5] << 8; 4488 BWN_WRITE_2(mac, BWN_MACFILTER_DATA, data); 4489 } 4490 4491 static void 4492 bwn_key_dowrite(struct bwn_mac *mac, uint8_t index, uint8_t algorithm, 4493 const uint8_t *key, size_t key_len, const uint8_t *mac_addr) 4494 { 4495 uint8_t buf[BWN_SEC_KEYSIZE] = { 0, }; 4496 uint8_t per_sta_keys_start = 8; 4497 4498 if (BWN_SEC_NEWAPI(mac)) 4499 per_sta_keys_start = 4; 4500 4501 KASSERT(index < mac->mac_max_nr_keys, 4502 ("%s:%d: fail", __func__, __LINE__)); 4503 KASSERT(key_len <= BWN_SEC_KEYSIZE, 4504 ("%s:%d: fail", __func__, __LINE__)); 4505 4506 if (index >= per_sta_keys_start) 4507 bwn_key_macwrite(mac, index, NULL); 4508 if (key) 4509 memcpy(buf, key, key_len); 4510 bwn_key_write(mac, index, algorithm, buf); 4511 if (index >= per_sta_keys_start) 4512 bwn_key_macwrite(mac, index, mac_addr); 4513 4514 mac->mac_key[index].algorithm = algorithm; 4515 } 4516 4517 static void 4518 bwn_key_macwrite(struct bwn_mac *mac, uint8_t index, const uint8_t *addr) 4519 { 4520 struct bwn_softc *sc = mac->mac_sc; 4521 uint32_t addrtmp[2] = { 0, 0 }; 4522 uint8_t start = 8; 4523 4524 if (BWN_SEC_NEWAPI(mac)) 4525 start = 4; 4526 4527 KASSERT(index >= start, 4528 ("%s:%d: fail", __func__, __LINE__)); 4529 index -= start; 4530 4531 if (addr) { 4532 addrtmp[0] = addr[0]; 4533 addrtmp[0] |= ((uint32_t) (addr[1]) << 8); 4534 addrtmp[0] |= ((uint32_t) (addr[2]) << 16); 4535 addrtmp[0] |= ((uint32_t) (addr[3]) << 24); 4536 addrtmp[1] = addr[4]; 4537 addrtmp[1] |= ((uint32_t) (addr[5]) << 8); 4538 } 4539 4540 if (siba_get_revid(sc->sc_dev) >= 5) { 4541 bwn_shm_write_4(mac, BWN_RCMTA, (index * 2) + 0, addrtmp[0]); 4542 bwn_shm_write_2(mac, BWN_RCMTA, (index * 2) + 1, addrtmp[1]); 4543 } else { 4544 if (index >= 8) { 4545 bwn_shm_write_4(mac, BWN_SHARED, 4546 BWN_SHARED_PSM + (index * 6) + 0, addrtmp[0]); 4547 bwn_shm_write_2(mac, BWN_SHARED, 4548 BWN_SHARED_PSM + (index * 6) + 4, addrtmp[1]); 4549 } 4550 } 4551 } 4552 4553 static void 4554 bwn_key_write(struct bwn_mac *mac, uint8_t index, uint8_t algorithm, 4555 const uint8_t *key) 4556 { 4557 unsigned int i; 4558 uint32_t offset; 4559 uint16_t kidx, value; 4560 4561 kidx = BWN_SEC_KEY2FW(mac, index); 4562 bwn_shm_write_2(mac, BWN_SHARED, 4563 BWN_SHARED_KEYIDX_BLOCK + (kidx * 2), (kidx << 4) | algorithm); 4564 4565 offset = mac->mac_ktp + (index * BWN_SEC_KEYSIZE); 4566 for (i = 0; i < BWN_SEC_KEYSIZE; i += 2) { 4567 value = key[i]; 4568 value |= (uint16_t)(key[i + 1]) << 8; 4569 bwn_shm_write_2(mac, BWN_SHARED, offset + i, value); 4570 } 4571 } 4572 4573 static void 4574 bwn_phy_exit(struct bwn_mac *mac) 4575 { 4576 4577 mac->mac_phy.rf_onoff(mac, 0); 4578 if (mac->mac_phy.exit != NULL) 4579 mac->mac_phy.exit(mac); 4580 } 4581 4582 static void 4583 bwn_dma_free(struct bwn_mac *mac) 4584 { 4585 struct bwn_dma *dma; 4586 4587 if ((mac->mac_flags & BWN_MAC_FLAG_DMA) == 0) 4588 return; 4589 dma = &mac->mac_method.dma; 4590 4591 bwn_dma_ringfree(&dma->rx); 4592 bwn_dma_ringfree(&dma->wme[WME_AC_BK]); 4593 bwn_dma_ringfree(&dma->wme[WME_AC_BE]); 4594 bwn_dma_ringfree(&dma->wme[WME_AC_VI]); 4595 bwn_dma_ringfree(&dma->wme[WME_AC_VO]); 4596 bwn_dma_ringfree(&dma->mcast); 4597 } 4598 4599 static void 4600 bwn_core_stop(struct bwn_mac *mac) 4601 { 4602 struct bwn_softc *sc = mac->mac_sc; 4603 4604 BWN_ASSERT_LOCKED(sc); 4605 4606 if (mac->mac_status < BWN_MAC_STATUS_STARTED) 4607 return; 4608 4609 callout_stop(&sc->sc_rfswitch_ch); 4610 callout_stop(&sc->sc_task_ch); 4611 callout_stop(&sc->sc_watchdog_ch); 4612 sc->sc_watchdog_timer = 0; 4613 BWN_WRITE_4(mac, BWN_INTR_MASK, 0); 4614 BWN_READ_4(mac, BWN_INTR_MASK); 4615 bwn_mac_suspend(mac); 4616 4617 mac->mac_status = BWN_MAC_STATUS_INITED; 4618 } 4619 4620 static int 4621 bwn_switch_band(struct bwn_softc *sc, struct ieee80211_channel *chan) 4622 { 4623 struct bwn_mac *up_dev = NULL; 4624 struct bwn_mac *down_dev; 4625 struct bwn_mac *mac; 4626 int err, status; 4627 uint8_t gmode; 4628 4629 BWN_ASSERT_LOCKED(sc); 4630 4631 TAILQ_FOREACH(mac, &sc->sc_maclist, mac_list) { 4632 if (IEEE80211_IS_CHAN_2GHZ(chan) && 4633 mac->mac_phy.supports_2ghz) { 4634 up_dev = mac; 4635 gmode = 1; 4636 } else if (IEEE80211_IS_CHAN_5GHZ(chan) && 4637 mac->mac_phy.supports_5ghz) { 4638 up_dev = mac; 4639 gmode = 0; 4640 } else { 4641 KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__)); 4642 return (EINVAL); 4643 } 4644 if (up_dev != NULL) 4645 break; 4646 } 4647 if (up_dev == NULL) { 4648 device_printf(sc->sc_dev, "Could not find a device\n"); 4649 return (ENODEV); 4650 } 4651 if (up_dev == sc->sc_curmac && sc->sc_curmac->mac_phy.gmode == gmode) 4652 return (0); 4653 4654 DPRINTF(sc, BWN_DEBUG_RF | BWN_DEBUG_PHY | BWN_DEBUG_RESET, 4655 "switching to %s-GHz band\n", 4656 IEEE80211_IS_CHAN_2GHZ(chan) ? "2" : "5"); 4657 4658 down_dev = sc->sc_curmac; 4659 status = down_dev->mac_status; 4660 if (status >= BWN_MAC_STATUS_STARTED) 4661 bwn_core_stop(down_dev); 4662 if (status >= BWN_MAC_STATUS_INITED) 4663 bwn_core_exit(down_dev); 4664 4665 if (down_dev != up_dev) 4666 bwn_phy_reset(down_dev); 4667 4668 up_dev->mac_phy.gmode = gmode; 4669 if (status >= BWN_MAC_STATUS_INITED) { 4670 err = bwn_core_init(up_dev); 4671 if (err) { 4672 device_printf(sc->sc_dev, 4673 "fatal: failed to initialize for %s-GHz\n", 4674 IEEE80211_IS_CHAN_2GHZ(chan) ? "2" : "5"); 4675 goto fail; 4676 } 4677 } 4678 if (status >= BWN_MAC_STATUS_STARTED) 4679 bwn_core_start(up_dev); 4680 KASSERT(up_dev->mac_status == status, ("%s: fail", __func__)); 4681 sc->sc_curmac = up_dev; 4682 4683 return (0); 4684 fail: 4685 sc->sc_curmac = NULL; 4686 return (err); 4687 } 4688 4689 static void 4690 bwn_rf_turnon(struct bwn_mac *mac) 4691 { 4692 4693 DPRINTF(mac->mac_sc, BWN_DEBUG_RESET, "%s: called\n", __func__); 4694 4695 bwn_mac_suspend(mac); 4696 mac->mac_phy.rf_onoff(mac, 1); 4697 mac->mac_phy.rf_on = 1; 4698 bwn_mac_enable(mac); 4699 } 4700 4701 static void 4702 bwn_rf_turnoff(struct bwn_mac *mac) 4703 { 4704 4705 DPRINTF(mac->mac_sc, BWN_DEBUG_RESET, "%s: called\n", __func__); 4706 4707 bwn_mac_suspend(mac); 4708 mac->mac_phy.rf_onoff(mac, 0); 4709 mac->mac_phy.rf_on = 0; 4710 bwn_mac_enable(mac); 4711 } 4712 4713 /* 4714 * SSB PHY reset. 4715 * 4716 * XXX TODO: BCMA PHY reset. 4717 */ 4718 static void 4719 bwn_phy_reset(struct bwn_mac *mac) 4720 { 4721 struct bwn_softc *sc = mac->mac_sc; 4722 4723 siba_write_4(sc->sc_dev, SIBA_TGSLOW, 4724 ((siba_read_4(sc->sc_dev, SIBA_TGSLOW) & ~BWN_TGSLOW_SUPPORT_G) | 4725 BWN_TGSLOW_PHYRESET) | SIBA_TGSLOW_FGC); 4726 DELAY(1000); 4727 siba_write_4(sc->sc_dev, SIBA_TGSLOW, 4728 (siba_read_4(sc->sc_dev, SIBA_TGSLOW) & ~SIBA_TGSLOW_FGC)); 4729 DELAY(1000); 4730 } 4731 4732 static int 4733 bwn_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 4734 { 4735 struct bwn_vap *bvp = BWN_VAP(vap); 4736 struct ieee80211com *ic= vap->iv_ic; 4737 enum ieee80211_state ostate = vap->iv_state; 4738 struct bwn_softc *sc = ic->ic_softc; 4739 struct bwn_mac *mac = sc->sc_curmac; 4740 int error; 4741 4742 DPRINTF(sc, BWN_DEBUG_STATE, "%s: %s -> %s\n", __func__, 4743 ieee80211_state_name[vap->iv_state], 4744 ieee80211_state_name[nstate]); 4745 4746 error = bvp->bv_newstate(vap, nstate, arg); 4747 if (error != 0) 4748 return (error); 4749 4750 BWN_LOCK(sc); 4751 4752 bwn_led_newstate(mac, nstate); 4753 4754 /* 4755 * Clear the BSSID when we stop a STA 4756 */ 4757 if (vap->iv_opmode == IEEE80211_M_STA) { 4758 if (ostate == IEEE80211_S_RUN && nstate != IEEE80211_S_RUN) { 4759 /* 4760 * Clear out the BSSID. If we reassociate to 4761 * the same AP, this will reinialize things 4762 * correctly... 4763 */ 4764 if (ic->ic_opmode == IEEE80211_M_STA && 4765 (sc->sc_flags & BWN_FLAG_INVALID) == 0) { 4766 memset(sc->sc_bssid, 0, IEEE80211_ADDR_LEN); 4767 bwn_set_macaddr(mac); 4768 } 4769 } 4770 } 4771 4772 if (vap->iv_opmode == IEEE80211_M_MONITOR || 4773 vap->iv_opmode == IEEE80211_M_AHDEMO) { 4774 /* XXX nothing to do? */ 4775 } else if (nstate == IEEE80211_S_RUN) { 4776 memcpy(sc->sc_bssid, vap->iv_bss->ni_bssid, IEEE80211_ADDR_LEN); 4777 bwn_set_opmode(mac); 4778 bwn_set_pretbtt(mac); 4779 bwn_spu_setdelay(mac, 0); 4780 bwn_set_macaddr(mac); 4781 } 4782 4783 BWN_UNLOCK(sc); 4784 4785 return (error); 4786 } 4787 4788 static void 4789 bwn_set_pretbtt(struct bwn_mac *mac) 4790 { 4791 struct bwn_softc *sc = mac->mac_sc; 4792 struct ieee80211com *ic = &sc->sc_ic; 4793 uint16_t pretbtt; 4794 4795 if (ic->ic_opmode == IEEE80211_M_IBSS) 4796 pretbtt = 2; 4797 else 4798 pretbtt = (mac->mac_phy.type == BWN_PHYTYPE_A) ? 120 : 250; 4799 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_PRETBTT, pretbtt); 4800 BWN_WRITE_2(mac, BWN_TSF_CFP_PRETBTT, pretbtt); 4801 } 4802 4803 static int 4804 bwn_intr(void *arg) 4805 { 4806 struct bwn_mac *mac = arg; 4807 struct bwn_softc *sc = mac->mac_sc; 4808 uint32_t reason; 4809 4810 if (mac->mac_status < BWN_MAC_STATUS_STARTED || 4811 (sc->sc_flags & BWN_FLAG_INVALID)) 4812 return (FILTER_STRAY); 4813 4814 DPRINTF(sc, BWN_DEBUG_INTR, "%s: called\n", __func__); 4815 4816 reason = BWN_READ_4(mac, BWN_INTR_REASON); 4817 if (reason == 0xffffffff) /* shared IRQ */ 4818 return (FILTER_STRAY); 4819 reason &= mac->mac_intr_mask; 4820 if (reason == 0) 4821 return (FILTER_HANDLED); 4822 DPRINTF(sc, BWN_DEBUG_INTR, "%s: reason=0x%08x\n", __func__, reason); 4823 4824 mac->mac_reason[0] = BWN_READ_4(mac, BWN_DMA0_REASON) & 0x0001dc00; 4825 mac->mac_reason[1] = BWN_READ_4(mac, BWN_DMA1_REASON) & 0x0000dc00; 4826 mac->mac_reason[2] = BWN_READ_4(mac, BWN_DMA2_REASON) & 0x0000dc00; 4827 mac->mac_reason[3] = BWN_READ_4(mac, BWN_DMA3_REASON) & 0x0001dc00; 4828 mac->mac_reason[4] = BWN_READ_4(mac, BWN_DMA4_REASON) & 0x0000dc00; 4829 BWN_WRITE_4(mac, BWN_INTR_REASON, reason); 4830 BWN_WRITE_4(mac, BWN_DMA0_REASON, mac->mac_reason[0]); 4831 BWN_WRITE_4(mac, BWN_DMA1_REASON, mac->mac_reason[1]); 4832 BWN_WRITE_4(mac, BWN_DMA2_REASON, mac->mac_reason[2]); 4833 BWN_WRITE_4(mac, BWN_DMA3_REASON, mac->mac_reason[3]); 4834 BWN_WRITE_4(mac, BWN_DMA4_REASON, mac->mac_reason[4]); 4835 4836 /* Disable interrupts. */ 4837 BWN_WRITE_4(mac, BWN_INTR_MASK, 0); 4838 4839 mac->mac_reason_intr = reason; 4840 4841 BWN_BARRIER(mac, BUS_SPACE_BARRIER_READ); 4842 BWN_BARRIER(mac, BUS_SPACE_BARRIER_WRITE); 4843 4844 taskqueue_enqueue(sc->sc_tq, &mac->mac_intrtask); 4845 return (FILTER_HANDLED); 4846 } 4847 4848 static void 4849 bwn_intrtask(void *arg, int npending) 4850 { 4851 struct bwn_mac *mac = arg; 4852 struct bwn_softc *sc = mac->mac_sc; 4853 uint32_t merged = 0; 4854 int i, tx = 0, rx = 0; 4855 4856 BWN_LOCK(sc); 4857 if (mac->mac_status < BWN_MAC_STATUS_STARTED || 4858 (sc->sc_flags & BWN_FLAG_INVALID)) { 4859 BWN_UNLOCK(sc); 4860 return; 4861 } 4862 4863 for (i = 0; i < N(mac->mac_reason); i++) 4864 merged |= mac->mac_reason[i]; 4865 4866 if (mac->mac_reason_intr & BWN_INTR_MAC_TXERR) 4867 device_printf(sc->sc_dev, "MAC trans error\n"); 4868 4869 if (mac->mac_reason_intr & BWN_INTR_PHY_TXERR) { 4870 DPRINTF(sc, BWN_DEBUG_INTR, "%s: PHY trans error\n", __func__); 4871 mac->mac_phy.txerrors--; 4872 if (mac->mac_phy.txerrors == 0) { 4873 mac->mac_phy.txerrors = BWN_TXERROR_MAX; 4874 bwn_restart(mac, "PHY TX errors"); 4875 } 4876 } 4877 4878 if (merged & (BWN_DMAINTR_FATALMASK | BWN_DMAINTR_NONFATALMASK)) { 4879 if (merged & BWN_DMAINTR_FATALMASK) { 4880 device_printf(sc->sc_dev, 4881 "Fatal DMA error: %#x %#x %#x %#x %#x %#x\n", 4882 mac->mac_reason[0], mac->mac_reason[1], 4883 mac->mac_reason[2], mac->mac_reason[3], 4884 mac->mac_reason[4], mac->mac_reason[5]); 4885 bwn_restart(mac, "DMA error"); 4886 BWN_UNLOCK(sc); 4887 return; 4888 } 4889 if (merged & BWN_DMAINTR_NONFATALMASK) { 4890 device_printf(sc->sc_dev, 4891 "DMA error: %#x %#x %#x %#x %#x %#x\n", 4892 mac->mac_reason[0], mac->mac_reason[1], 4893 mac->mac_reason[2], mac->mac_reason[3], 4894 mac->mac_reason[4], mac->mac_reason[5]); 4895 } 4896 } 4897 4898 if (mac->mac_reason_intr & BWN_INTR_UCODE_DEBUG) 4899 bwn_intr_ucode_debug(mac); 4900 if (mac->mac_reason_intr & BWN_INTR_TBTT_INDI) 4901 bwn_intr_tbtt_indication(mac); 4902 if (mac->mac_reason_intr & BWN_INTR_ATIM_END) 4903 bwn_intr_atim_end(mac); 4904 if (mac->mac_reason_intr & BWN_INTR_BEACON) 4905 bwn_intr_beacon(mac); 4906 if (mac->mac_reason_intr & BWN_INTR_PMQ) 4907 bwn_intr_pmq(mac); 4908 if (mac->mac_reason_intr & BWN_INTR_NOISESAMPLE_OK) 4909 bwn_intr_noise(mac); 4910 4911 if (mac->mac_flags & BWN_MAC_FLAG_DMA) { 4912 if (mac->mac_reason[0] & BWN_DMAINTR_RX_DONE) { 4913 bwn_dma_rx(mac->mac_method.dma.rx); 4914 rx = 1; 4915 } 4916 } else 4917 rx = bwn_pio_rx(&mac->mac_method.pio.rx); 4918 4919 KASSERT(!(mac->mac_reason[1] & BWN_DMAINTR_RX_DONE), ("%s", __func__)); 4920 KASSERT(!(mac->mac_reason[2] & BWN_DMAINTR_RX_DONE), ("%s", __func__)); 4921 KASSERT(!(mac->mac_reason[3] & BWN_DMAINTR_RX_DONE), ("%s", __func__)); 4922 KASSERT(!(mac->mac_reason[4] & BWN_DMAINTR_RX_DONE), ("%s", __func__)); 4923 KASSERT(!(mac->mac_reason[5] & BWN_DMAINTR_RX_DONE), ("%s", __func__)); 4924 4925 if (mac->mac_reason_intr & BWN_INTR_TX_OK) { 4926 bwn_intr_txeof(mac); 4927 tx = 1; 4928 } 4929 4930 BWN_WRITE_4(mac, BWN_INTR_MASK, mac->mac_intr_mask); 4931 4932 if (sc->sc_blink_led != NULL && sc->sc_led_blink) { 4933 int evt = BWN_LED_EVENT_NONE; 4934 4935 if (tx && rx) { 4936 if (sc->sc_rx_rate > sc->sc_tx_rate) 4937 evt = BWN_LED_EVENT_RX; 4938 else 4939 evt = BWN_LED_EVENT_TX; 4940 } else if (tx) { 4941 evt = BWN_LED_EVENT_TX; 4942 } else if (rx) { 4943 evt = BWN_LED_EVENT_RX; 4944 } else if (rx == 0) { 4945 evt = BWN_LED_EVENT_POLL; 4946 } 4947 4948 if (evt != BWN_LED_EVENT_NONE) 4949 bwn_led_event(mac, evt); 4950 } 4951 4952 if (mbufq_first(&sc->sc_snd) != NULL) 4953 bwn_start(sc); 4954 4955 BWN_BARRIER(mac, BUS_SPACE_BARRIER_READ); 4956 BWN_BARRIER(mac, BUS_SPACE_BARRIER_WRITE); 4957 4958 BWN_UNLOCK(sc); 4959 } 4960 4961 static void 4962 bwn_restart(struct bwn_mac *mac, const char *msg) 4963 { 4964 struct bwn_softc *sc = mac->mac_sc; 4965 struct ieee80211com *ic = &sc->sc_ic; 4966 4967 if (mac->mac_status < BWN_MAC_STATUS_INITED) 4968 return; 4969 4970 device_printf(sc->sc_dev, "HW reset: %s\n", msg); 4971 ieee80211_runtask(ic, &mac->mac_hwreset); 4972 } 4973 4974 static void 4975 bwn_intr_ucode_debug(struct bwn_mac *mac) 4976 { 4977 struct bwn_softc *sc = mac->mac_sc; 4978 uint16_t reason; 4979 4980 if (mac->mac_fw.opensource == 0) 4981 return; 4982 4983 reason = bwn_shm_read_2(mac, BWN_SCRATCH, BWN_DEBUGINTR_REASON_REG); 4984 switch (reason) { 4985 case BWN_DEBUGINTR_PANIC: 4986 bwn_handle_fwpanic(mac); 4987 break; 4988 case BWN_DEBUGINTR_DUMP_SHM: 4989 device_printf(sc->sc_dev, "BWN_DEBUGINTR_DUMP_SHM\n"); 4990 break; 4991 case BWN_DEBUGINTR_DUMP_REGS: 4992 device_printf(sc->sc_dev, "BWN_DEBUGINTR_DUMP_REGS\n"); 4993 break; 4994 case BWN_DEBUGINTR_MARKER: 4995 device_printf(sc->sc_dev, "BWN_DEBUGINTR_MARKER\n"); 4996 break; 4997 default: 4998 device_printf(sc->sc_dev, 4999 "ucode debug unknown reason: %#x\n", reason); 5000 } 5001 5002 bwn_shm_write_2(mac, BWN_SCRATCH, BWN_DEBUGINTR_REASON_REG, 5003 BWN_DEBUGINTR_ACK); 5004 } 5005 5006 static void 5007 bwn_intr_tbtt_indication(struct bwn_mac *mac) 5008 { 5009 struct bwn_softc *sc = mac->mac_sc; 5010 struct ieee80211com *ic = &sc->sc_ic; 5011 5012 if (ic->ic_opmode != IEEE80211_M_HOSTAP) 5013 bwn_psctl(mac, 0); 5014 if (ic->ic_opmode == IEEE80211_M_IBSS) 5015 mac->mac_flags |= BWN_MAC_FLAG_DFQVALID; 5016 } 5017 5018 static void 5019 bwn_intr_atim_end(struct bwn_mac *mac) 5020 { 5021 5022 if (mac->mac_flags & BWN_MAC_FLAG_DFQVALID) { 5023 BWN_WRITE_4(mac, BWN_MACCMD, 5024 BWN_READ_4(mac, BWN_MACCMD) | BWN_MACCMD_DFQ_VALID); 5025 mac->mac_flags &= ~BWN_MAC_FLAG_DFQVALID; 5026 } 5027 } 5028 5029 static void 5030 bwn_intr_beacon(struct bwn_mac *mac) 5031 { 5032 struct bwn_softc *sc = mac->mac_sc; 5033 struct ieee80211com *ic = &sc->sc_ic; 5034 uint32_t cmd, beacon0, beacon1; 5035 5036 if (ic->ic_opmode == IEEE80211_M_HOSTAP || 5037 ic->ic_opmode == IEEE80211_M_MBSS) 5038 return; 5039 5040 mac->mac_intr_mask &= ~BWN_INTR_BEACON; 5041 5042 cmd = BWN_READ_4(mac, BWN_MACCMD); 5043 beacon0 = (cmd & BWN_MACCMD_BEACON0_VALID); 5044 beacon1 = (cmd & BWN_MACCMD_BEACON1_VALID); 5045 5046 if (beacon0 && beacon1) { 5047 BWN_WRITE_4(mac, BWN_INTR_REASON, BWN_INTR_BEACON); 5048 mac->mac_intr_mask |= BWN_INTR_BEACON; 5049 return; 5050 } 5051 5052 if (sc->sc_flags & BWN_FLAG_NEED_BEACON_TP) { 5053 sc->sc_flags &= ~BWN_FLAG_NEED_BEACON_TP; 5054 bwn_load_beacon0(mac); 5055 bwn_load_beacon1(mac); 5056 cmd = BWN_READ_4(mac, BWN_MACCMD); 5057 cmd |= BWN_MACCMD_BEACON0_VALID; 5058 BWN_WRITE_4(mac, BWN_MACCMD, cmd); 5059 } else { 5060 if (!beacon0) { 5061 bwn_load_beacon0(mac); 5062 cmd = BWN_READ_4(mac, BWN_MACCMD); 5063 cmd |= BWN_MACCMD_BEACON0_VALID; 5064 BWN_WRITE_4(mac, BWN_MACCMD, cmd); 5065 } else if (!beacon1) { 5066 bwn_load_beacon1(mac); 5067 cmd = BWN_READ_4(mac, BWN_MACCMD); 5068 cmd |= BWN_MACCMD_BEACON1_VALID; 5069 BWN_WRITE_4(mac, BWN_MACCMD, cmd); 5070 } 5071 } 5072 } 5073 5074 static void 5075 bwn_intr_pmq(struct bwn_mac *mac) 5076 { 5077 uint32_t tmp; 5078 5079 while (1) { 5080 tmp = BWN_READ_4(mac, BWN_PS_STATUS); 5081 if (!(tmp & 0x00000008)) 5082 break; 5083 } 5084 BWN_WRITE_2(mac, BWN_PS_STATUS, 0x0002); 5085 } 5086 5087 static void 5088 bwn_intr_noise(struct bwn_mac *mac) 5089 { 5090 struct bwn_phy_g *pg = &mac->mac_phy.phy_g; 5091 uint16_t tmp; 5092 uint8_t noise[4]; 5093 uint8_t i, j; 5094 int32_t average; 5095 5096 if (mac->mac_phy.type != BWN_PHYTYPE_G) 5097 return; 5098 5099 KASSERT(mac->mac_noise.noi_running, ("%s: fail", __func__)); 5100 *((uint32_t *)noise) = htole32(bwn_jssi_read(mac)); 5101 if (noise[0] == 0x7f || noise[1] == 0x7f || noise[2] == 0x7f || 5102 noise[3] == 0x7f) 5103 goto new; 5104 5105 KASSERT(mac->mac_noise.noi_nsamples < 8, 5106 ("%s:%d: fail", __func__, __LINE__)); 5107 i = mac->mac_noise.noi_nsamples; 5108 noise[0] = MIN(MAX(noise[0], 0), N(pg->pg_nrssi_lt) - 1); 5109 noise[1] = MIN(MAX(noise[1], 0), N(pg->pg_nrssi_lt) - 1); 5110 noise[2] = MIN(MAX(noise[2], 0), N(pg->pg_nrssi_lt) - 1); 5111 noise[3] = MIN(MAX(noise[3], 0), N(pg->pg_nrssi_lt) - 1); 5112 mac->mac_noise.noi_samples[i][0] = pg->pg_nrssi_lt[noise[0]]; 5113 mac->mac_noise.noi_samples[i][1] = pg->pg_nrssi_lt[noise[1]]; 5114 mac->mac_noise.noi_samples[i][2] = pg->pg_nrssi_lt[noise[2]]; 5115 mac->mac_noise.noi_samples[i][3] = pg->pg_nrssi_lt[noise[3]]; 5116 mac->mac_noise.noi_nsamples++; 5117 if (mac->mac_noise.noi_nsamples == 8) { 5118 average = 0; 5119 for (i = 0; i < 8; i++) { 5120 for (j = 0; j < 4; j++) 5121 average += mac->mac_noise.noi_samples[i][j]; 5122 } 5123 average = (((average / 32) * 125) + 64) / 128; 5124 tmp = (bwn_shm_read_2(mac, BWN_SHARED, 0x40c) / 128) & 0x1f; 5125 if (tmp >= 8) 5126 average += 2; 5127 else 5128 average -= 25; 5129 average -= (tmp == 8) ? 72 : 48; 5130 5131 mac->mac_stats.link_noise = average; 5132 mac->mac_noise.noi_running = 0; 5133 return; 5134 } 5135 new: 5136 bwn_noise_gensample(mac); 5137 } 5138 5139 static int 5140 bwn_pio_rx(struct bwn_pio_rxqueue *prq) 5141 { 5142 struct bwn_mac *mac = prq->prq_mac; 5143 struct bwn_softc *sc = mac->mac_sc; 5144 unsigned int i; 5145 5146 BWN_ASSERT_LOCKED(sc); 5147 5148 if (mac->mac_status < BWN_MAC_STATUS_STARTED) 5149 return (0); 5150 5151 for (i = 0; i < 5000; i++) { 5152 if (bwn_pio_rxeof(prq) == 0) 5153 break; 5154 } 5155 if (i >= 5000) 5156 device_printf(sc->sc_dev, "too many RX frames in PIO mode\n"); 5157 return ((i > 0) ? 1 : 0); 5158 } 5159 5160 static void 5161 bwn_dma_rx(struct bwn_dma_ring *dr) 5162 { 5163 int slot, curslot; 5164 5165 KASSERT(!dr->dr_tx, ("%s:%d: fail", __func__, __LINE__)); 5166 curslot = dr->get_curslot(dr); 5167 KASSERT(curslot >= 0 && curslot < dr->dr_numslots, 5168 ("%s:%d: fail", __func__, __LINE__)); 5169 5170 slot = dr->dr_curslot; 5171 for (; slot != curslot; slot = bwn_dma_nextslot(dr, slot)) 5172 bwn_dma_rxeof(dr, &slot); 5173 5174 bus_dmamap_sync(dr->dr_ring_dtag, dr->dr_ring_dmap, 5175 BUS_DMASYNC_PREWRITE); 5176 5177 dr->set_curslot(dr, slot); 5178 dr->dr_curslot = slot; 5179 } 5180 5181 static void 5182 bwn_intr_txeof(struct bwn_mac *mac) 5183 { 5184 struct bwn_txstatus stat; 5185 uint32_t stat0, stat1; 5186 uint16_t tmp; 5187 5188 BWN_ASSERT_LOCKED(mac->mac_sc); 5189 5190 while (1) { 5191 stat0 = BWN_READ_4(mac, BWN_XMITSTAT_0); 5192 if (!(stat0 & 0x00000001)) 5193 break; 5194 stat1 = BWN_READ_4(mac, BWN_XMITSTAT_1); 5195 5196 DPRINTF(mac->mac_sc, BWN_DEBUG_XMIT, 5197 "%s: stat0=0x%08x, stat1=0x%08x\n", 5198 __func__, 5199 stat0, 5200 stat1); 5201 5202 stat.cookie = (stat0 >> 16); 5203 stat.seq = (stat1 & 0x0000ffff); 5204 stat.phy_stat = ((stat1 & 0x00ff0000) >> 16); 5205 tmp = (stat0 & 0x0000ffff); 5206 stat.framecnt = ((tmp & 0xf000) >> 12); 5207 stat.rtscnt = ((tmp & 0x0f00) >> 8); 5208 stat.sreason = ((tmp & 0x001c) >> 2); 5209 stat.pm = (tmp & 0x0080) ? 1 : 0; 5210 stat.im = (tmp & 0x0040) ? 1 : 0; 5211 stat.ampdu = (tmp & 0x0020) ? 1 : 0; 5212 stat.ack = (tmp & 0x0002) ? 1 : 0; 5213 5214 DPRINTF(mac->mac_sc, BWN_DEBUG_XMIT, 5215 "%s: cookie=%d, seq=%d, phystat=0x%02x, framecnt=%d, " 5216 "rtscnt=%d, sreason=%d, pm=%d, im=%d, ampdu=%d, ack=%d\n", 5217 __func__, 5218 stat.cookie, 5219 stat.seq, 5220 stat.phy_stat, 5221 stat.framecnt, 5222 stat.rtscnt, 5223 stat.sreason, 5224 stat.pm, 5225 stat.im, 5226 stat.ampdu, 5227 stat.ack); 5228 5229 bwn_handle_txeof(mac, &stat); 5230 } 5231 } 5232 5233 static void 5234 bwn_hwreset(void *arg, int npending) 5235 { 5236 struct bwn_mac *mac = arg; 5237 struct bwn_softc *sc = mac->mac_sc; 5238 int error = 0; 5239 int prev_status; 5240 5241 BWN_LOCK(sc); 5242 5243 prev_status = mac->mac_status; 5244 if (prev_status >= BWN_MAC_STATUS_STARTED) 5245 bwn_core_stop(mac); 5246 if (prev_status >= BWN_MAC_STATUS_INITED) 5247 bwn_core_exit(mac); 5248 5249 if (prev_status >= BWN_MAC_STATUS_INITED) { 5250 error = bwn_core_init(mac); 5251 if (error) 5252 goto out; 5253 } 5254 if (prev_status >= BWN_MAC_STATUS_STARTED) 5255 bwn_core_start(mac); 5256 out: 5257 if (error) { 5258 device_printf(sc->sc_dev, "%s: failed (%d)\n", __func__, error); 5259 sc->sc_curmac = NULL; 5260 } 5261 BWN_UNLOCK(sc); 5262 } 5263 5264 static void 5265 bwn_handle_fwpanic(struct bwn_mac *mac) 5266 { 5267 struct bwn_softc *sc = mac->mac_sc; 5268 uint16_t reason; 5269 5270 reason = bwn_shm_read_2(mac, BWN_SCRATCH, BWN_FWPANIC_REASON_REG); 5271 device_printf(sc->sc_dev,"fw panic (%u)\n", reason); 5272 5273 if (reason == BWN_FWPANIC_RESTART) 5274 bwn_restart(mac, "ucode panic"); 5275 } 5276 5277 static void 5278 bwn_load_beacon0(struct bwn_mac *mac) 5279 { 5280 5281 KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__)); 5282 } 5283 5284 static void 5285 bwn_load_beacon1(struct bwn_mac *mac) 5286 { 5287 5288 KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__)); 5289 } 5290 5291 static uint32_t 5292 bwn_jssi_read(struct bwn_mac *mac) 5293 { 5294 uint32_t val = 0; 5295 5296 val = bwn_shm_read_2(mac, BWN_SHARED, 0x08a); 5297 val <<= 16; 5298 val |= bwn_shm_read_2(mac, BWN_SHARED, 0x088); 5299 5300 return (val); 5301 } 5302 5303 static void 5304 bwn_noise_gensample(struct bwn_mac *mac) 5305 { 5306 uint32_t jssi = 0x7f7f7f7f; 5307 5308 bwn_shm_write_2(mac, BWN_SHARED, 0x088, (jssi & 0x0000ffff)); 5309 bwn_shm_write_2(mac, BWN_SHARED, 0x08a, (jssi & 0xffff0000) >> 16); 5310 BWN_WRITE_4(mac, BWN_MACCMD, 5311 BWN_READ_4(mac, BWN_MACCMD) | BWN_MACCMD_BGNOISE); 5312 } 5313 5314 static int 5315 bwn_dma_freeslot(struct bwn_dma_ring *dr) 5316 { 5317 BWN_ASSERT_LOCKED(dr->dr_mac->mac_sc); 5318 5319 return (dr->dr_numslots - dr->dr_usedslot); 5320 } 5321 5322 static int 5323 bwn_dma_nextslot(struct bwn_dma_ring *dr, int slot) 5324 { 5325 BWN_ASSERT_LOCKED(dr->dr_mac->mac_sc); 5326 5327 KASSERT(slot >= -1 && slot <= dr->dr_numslots - 1, 5328 ("%s:%d: fail", __func__, __LINE__)); 5329 if (slot == dr->dr_numslots - 1) 5330 return (0); 5331 return (slot + 1); 5332 } 5333 5334 static void 5335 bwn_dma_rxeof(struct bwn_dma_ring *dr, int *slot) 5336 { 5337 struct bwn_mac *mac = dr->dr_mac; 5338 struct bwn_softc *sc = mac->mac_sc; 5339 struct bwn_dma *dma = &mac->mac_method.dma; 5340 struct bwn_dmadesc_generic *desc; 5341 struct bwn_dmadesc_meta *meta; 5342 struct bwn_rxhdr4 *rxhdr; 5343 struct mbuf *m; 5344 uint32_t macstat; 5345 int32_t tmp; 5346 int cnt = 0; 5347 uint16_t len; 5348 5349 dr->getdesc(dr, *slot, &desc, &meta); 5350 5351 bus_dmamap_sync(dma->rxbuf_dtag, meta->mt_dmap, BUS_DMASYNC_POSTREAD); 5352 m = meta->mt_m; 5353 5354 if (bwn_dma_newbuf(dr, desc, meta, 0)) { 5355 counter_u64_add(sc->sc_ic.ic_ierrors, 1); 5356 return; 5357 } 5358 5359 rxhdr = mtod(m, struct bwn_rxhdr4 *); 5360 len = le16toh(rxhdr->frame_len); 5361 if (len <= 0) { 5362 counter_u64_add(sc->sc_ic.ic_ierrors, 1); 5363 return; 5364 } 5365 if (bwn_dma_check_redzone(dr, m)) { 5366 device_printf(sc->sc_dev, "redzone error.\n"); 5367 bwn_dma_set_redzone(dr, m); 5368 bus_dmamap_sync(dma->rxbuf_dtag, meta->mt_dmap, 5369 BUS_DMASYNC_PREWRITE); 5370 return; 5371 } 5372 if (len > dr->dr_rx_bufsize) { 5373 tmp = len; 5374 while (1) { 5375 dr->getdesc(dr, *slot, &desc, &meta); 5376 bwn_dma_set_redzone(dr, meta->mt_m); 5377 bus_dmamap_sync(dma->rxbuf_dtag, meta->mt_dmap, 5378 BUS_DMASYNC_PREWRITE); 5379 *slot = bwn_dma_nextslot(dr, *slot); 5380 cnt++; 5381 tmp -= dr->dr_rx_bufsize; 5382 if (tmp <= 0) 5383 break; 5384 } 5385 device_printf(sc->sc_dev, "too small buffer " 5386 "(len %u buffer %u dropped %d)\n", 5387 len, dr->dr_rx_bufsize, cnt); 5388 return; 5389 } 5390 5391 switch (mac->mac_fw.fw_hdr_format) { 5392 case BWN_FW_HDR_351: 5393 case BWN_FW_HDR_410: 5394 macstat = le32toh(rxhdr->ps4.r351.mac_status); 5395 break; 5396 case BWN_FW_HDR_598: 5397 macstat = le32toh(rxhdr->ps4.r598.mac_status); 5398 break; 5399 } 5400 5401 if (macstat & BWN_RX_MAC_FCSERR) { 5402 if (!(mac->mac_sc->sc_filters & BWN_MACCTL_PASS_BADFCS)) { 5403 device_printf(sc->sc_dev, "RX drop\n"); 5404 return; 5405 } 5406 } 5407 5408 m->m_len = m->m_pkthdr.len = len + dr->dr_frameoffset; 5409 m_adj(m, dr->dr_frameoffset); 5410 5411 bwn_rxeof(dr->dr_mac, m, rxhdr); 5412 } 5413 5414 static void 5415 bwn_handle_txeof(struct bwn_mac *mac, const struct bwn_txstatus *status) 5416 { 5417 struct bwn_softc *sc = mac->mac_sc; 5418 struct bwn_stats *stats = &mac->mac_stats; 5419 5420 BWN_ASSERT_LOCKED(mac->mac_sc); 5421 5422 if (status->im) 5423 device_printf(sc->sc_dev, "TODO: STATUS IM\n"); 5424 if (status->ampdu) 5425 device_printf(sc->sc_dev, "TODO: STATUS AMPDU\n"); 5426 if (status->rtscnt) { 5427 if (status->rtscnt == 0xf) 5428 stats->rtsfail++; 5429 else 5430 stats->rts++; 5431 } 5432 5433 if (mac->mac_flags & BWN_MAC_FLAG_DMA) { 5434 bwn_dma_handle_txeof(mac, status); 5435 } else { 5436 bwn_pio_handle_txeof(mac, status); 5437 } 5438 5439 bwn_phy_txpower_check(mac, 0); 5440 } 5441 5442 static uint8_t 5443 bwn_pio_rxeof(struct bwn_pio_rxqueue *prq) 5444 { 5445 struct bwn_mac *mac = prq->prq_mac; 5446 struct bwn_softc *sc = mac->mac_sc; 5447 struct bwn_rxhdr4 rxhdr; 5448 struct mbuf *m; 5449 uint32_t ctl32, macstat, v32; 5450 unsigned int i, padding; 5451 uint16_t ctl16, len, totlen, v16; 5452 unsigned char *mp; 5453 char *data; 5454 5455 memset(&rxhdr, 0, sizeof(rxhdr)); 5456 5457 if (prq->prq_rev >= 8) { 5458 ctl32 = bwn_pio_rx_read_4(prq, BWN_PIO8_RXCTL); 5459 if (!(ctl32 & BWN_PIO8_RXCTL_FRAMEREADY)) 5460 return (0); 5461 bwn_pio_rx_write_4(prq, BWN_PIO8_RXCTL, 5462 BWN_PIO8_RXCTL_FRAMEREADY); 5463 for (i = 0; i < 10; i++) { 5464 ctl32 = bwn_pio_rx_read_4(prq, BWN_PIO8_RXCTL); 5465 if (ctl32 & BWN_PIO8_RXCTL_DATAREADY) 5466 goto ready; 5467 DELAY(10); 5468 } 5469 } else { 5470 ctl16 = bwn_pio_rx_read_2(prq, BWN_PIO_RXCTL); 5471 if (!(ctl16 & BWN_PIO_RXCTL_FRAMEREADY)) 5472 return (0); 5473 bwn_pio_rx_write_2(prq, BWN_PIO_RXCTL, 5474 BWN_PIO_RXCTL_FRAMEREADY); 5475 for (i = 0; i < 10; i++) { 5476 ctl16 = bwn_pio_rx_read_2(prq, BWN_PIO_RXCTL); 5477 if (ctl16 & BWN_PIO_RXCTL_DATAREADY) 5478 goto ready; 5479 DELAY(10); 5480 } 5481 } 5482 device_printf(sc->sc_dev, "%s: timed out\n", __func__); 5483 return (1); 5484 ready: 5485 if (prq->prq_rev >= 8) 5486 siba_read_multi_4(sc->sc_dev, &rxhdr, sizeof(rxhdr), 5487 prq->prq_base + BWN_PIO8_RXDATA); 5488 else 5489 siba_read_multi_2(sc->sc_dev, &rxhdr, sizeof(rxhdr), 5490 prq->prq_base + BWN_PIO_RXDATA); 5491 len = le16toh(rxhdr.frame_len); 5492 if (len > 0x700) { 5493 device_printf(sc->sc_dev, "%s: len is too big\n", __func__); 5494 goto error; 5495 } 5496 if (len == 0) { 5497 device_printf(sc->sc_dev, "%s: len is 0\n", __func__); 5498 goto error; 5499 } 5500 5501 switch (mac->mac_fw.fw_hdr_format) { 5502 case BWN_FW_HDR_351: 5503 case BWN_FW_HDR_410: 5504 macstat = le32toh(rxhdr.ps4.r351.mac_status); 5505 break; 5506 case BWN_FW_HDR_598: 5507 macstat = le32toh(rxhdr.ps4.r598.mac_status); 5508 break; 5509 } 5510 5511 if (macstat & BWN_RX_MAC_FCSERR) { 5512 if (!(mac->mac_sc->sc_filters & BWN_MACCTL_PASS_BADFCS)) { 5513 device_printf(sc->sc_dev, "%s: FCS error", __func__); 5514 goto error; 5515 } 5516 } 5517 5518 padding = (macstat & BWN_RX_MAC_PADDING) ? 2 : 0; 5519 totlen = len + padding; 5520 KASSERT(totlen <= MCLBYTES, ("too big..\n")); 5521 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 5522 if (m == NULL) { 5523 device_printf(sc->sc_dev, "%s: out of memory", __func__); 5524 goto error; 5525 } 5526 mp = mtod(m, unsigned char *); 5527 if (prq->prq_rev >= 8) { 5528 siba_read_multi_4(sc->sc_dev, mp, (totlen & ~3), 5529 prq->prq_base + BWN_PIO8_RXDATA); 5530 if (totlen & 3) { 5531 v32 = bwn_pio_rx_read_4(prq, BWN_PIO8_RXDATA); 5532 data = &(mp[totlen - 1]); 5533 switch (totlen & 3) { 5534 case 3: 5535 *data = (v32 >> 16); 5536 data--; 5537 case 2: 5538 *data = (v32 >> 8); 5539 data--; 5540 case 1: 5541 *data = v32; 5542 } 5543 } 5544 } else { 5545 siba_read_multi_2(sc->sc_dev, mp, (totlen & ~1), 5546 prq->prq_base + BWN_PIO_RXDATA); 5547 if (totlen & 1) { 5548 v16 = bwn_pio_rx_read_2(prq, BWN_PIO_RXDATA); 5549 mp[totlen - 1] = v16; 5550 } 5551 } 5552 5553 m->m_len = m->m_pkthdr.len = totlen; 5554 5555 bwn_rxeof(prq->prq_mac, m, &rxhdr); 5556 5557 return (1); 5558 error: 5559 if (prq->prq_rev >= 8) 5560 bwn_pio_rx_write_4(prq, BWN_PIO8_RXCTL, 5561 BWN_PIO8_RXCTL_DATAREADY); 5562 else 5563 bwn_pio_rx_write_2(prq, BWN_PIO_RXCTL, BWN_PIO_RXCTL_DATAREADY); 5564 return (1); 5565 } 5566 5567 static int 5568 bwn_dma_newbuf(struct bwn_dma_ring *dr, struct bwn_dmadesc_generic *desc, 5569 struct bwn_dmadesc_meta *meta, int init) 5570 { 5571 struct bwn_mac *mac = dr->dr_mac; 5572 struct bwn_dma *dma = &mac->mac_method.dma; 5573 struct bwn_rxhdr4 *hdr; 5574 bus_dmamap_t map; 5575 bus_addr_t paddr; 5576 struct mbuf *m; 5577 int error; 5578 5579 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 5580 if (m == NULL) { 5581 error = ENOBUFS; 5582 5583 /* 5584 * If the NIC is up and running, we need to: 5585 * - Clear RX buffer's header. 5586 * - Restore RX descriptor settings. 5587 */ 5588 if (init) 5589 return (error); 5590 else 5591 goto back; 5592 } 5593 m->m_len = m->m_pkthdr.len = MCLBYTES; 5594 5595 bwn_dma_set_redzone(dr, m); 5596 5597 /* 5598 * Try to load RX buf into temporary DMA map 5599 */ 5600 error = bus_dmamap_load_mbuf(dma->rxbuf_dtag, dr->dr_spare_dmap, m, 5601 bwn_dma_buf_addr, &paddr, BUS_DMA_NOWAIT); 5602 if (error) { 5603 m_freem(m); 5604 5605 /* 5606 * See the comment above 5607 */ 5608 if (init) 5609 return (error); 5610 else 5611 goto back; 5612 } 5613 5614 if (!init) 5615 bus_dmamap_unload(dma->rxbuf_dtag, meta->mt_dmap); 5616 meta->mt_m = m; 5617 meta->mt_paddr = paddr; 5618 5619 /* 5620 * Swap RX buf's DMA map with the loaded temporary one 5621 */ 5622 map = meta->mt_dmap; 5623 meta->mt_dmap = dr->dr_spare_dmap; 5624 dr->dr_spare_dmap = map; 5625 5626 back: 5627 /* 5628 * Clear RX buf header 5629 */ 5630 hdr = mtod(meta->mt_m, struct bwn_rxhdr4 *); 5631 bzero(hdr, sizeof(*hdr)); 5632 bus_dmamap_sync(dma->rxbuf_dtag, meta->mt_dmap, 5633 BUS_DMASYNC_PREWRITE); 5634 5635 /* 5636 * Setup RX buf descriptor 5637 */ 5638 dr->setdesc(dr, desc, meta->mt_paddr, meta->mt_m->m_len - 5639 sizeof(*hdr), 0, 0, 0); 5640 return (error); 5641 } 5642 5643 static void 5644 bwn_dma_buf_addr(void *arg, bus_dma_segment_t *seg, int nseg, 5645 bus_size_t mapsz __unused, int error) 5646 { 5647 5648 if (!error) { 5649 KASSERT(nseg == 1, ("too many segments(%d)\n", nseg)); 5650 *((bus_addr_t *)arg) = seg->ds_addr; 5651 } 5652 } 5653 5654 static int 5655 bwn_hwrate2ieeerate(int rate) 5656 { 5657 5658 switch (rate) { 5659 case BWN_CCK_RATE_1MB: 5660 return (2); 5661 case BWN_CCK_RATE_2MB: 5662 return (4); 5663 case BWN_CCK_RATE_5MB: 5664 return (11); 5665 case BWN_CCK_RATE_11MB: 5666 return (22); 5667 case BWN_OFDM_RATE_6MB: 5668 return (12); 5669 case BWN_OFDM_RATE_9MB: 5670 return (18); 5671 case BWN_OFDM_RATE_12MB: 5672 return (24); 5673 case BWN_OFDM_RATE_18MB: 5674 return (36); 5675 case BWN_OFDM_RATE_24MB: 5676 return (48); 5677 case BWN_OFDM_RATE_36MB: 5678 return (72); 5679 case BWN_OFDM_RATE_48MB: 5680 return (96); 5681 case BWN_OFDM_RATE_54MB: 5682 return (108); 5683 default: 5684 printf("Ooops\n"); 5685 return (0); 5686 } 5687 } 5688 5689 /* 5690 * Post process the RX provided RSSI. 5691 * 5692 * Valid for A, B, G, LP PHYs. 5693 */ 5694 static int8_t 5695 bwn_rx_rssi_calc(struct bwn_mac *mac, uint8_t in_rssi, 5696 int ofdm, int adjust_2053, int adjust_2050) 5697 { 5698 struct bwn_phy *phy = &mac->mac_phy; 5699 struct bwn_phy_g *gphy = &phy->phy_g; 5700 int tmp; 5701 5702 switch (phy->rf_ver) { 5703 case 0x2050: 5704 if (ofdm) { 5705 tmp = in_rssi; 5706 if (tmp > 127) 5707 tmp -= 256; 5708 tmp = tmp * 73 / 64; 5709 if (adjust_2050) 5710 tmp += 25; 5711 else 5712 tmp -= 3; 5713 } else { 5714 if (siba_sprom_get_bf_lo(mac->mac_sc->sc_dev) 5715 & BWN_BFL_RSSI) { 5716 if (in_rssi > 63) 5717 in_rssi = 63; 5718 tmp = gphy->pg_nrssi_lt[in_rssi]; 5719 tmp = (31 - tmp) * -131 / 128 - 57; 5720 } else { 5721 tmp = in_rssi; 5722 tmp = (31 - tmp) * -149 / 128 - 68; 5723 } 5724 if (phy->type == BWN_PHYTYPE_G && adjust_2050) 5725 tmp += 25; 5726 } 5727 break; 5728 case 0x2060: 5729 if (in_rssi > 127) 5730 tmp = in_rssi - 256; 5731 else 5732 tmp = in_rssi; 5733 break; 5734 default: 5735 tmp = in_rssi; 5736 tmp = (tmp - 11) * 103 / 64; 5737 if (adjust_2053) 5738 tmp -= 109; 5739 else 5740 tmp -= 83; 5741 } 5742 5743 return (tmp); 5744 } 5745 5746 static void 5747 bwn_rxeof(struct bwn_mac *mac, struct mbuf *m, const void *_rxhdr) 5748 { 5749 const struct bwn_rxhdr4 *rxhdr = _rxhdr; 5750 struct bwn_plcp6 *plcp; 5751 struct bwn_softc *sc = mac->mac_sc; 5752 struct ieee80211_frame_min *wh; 5753 struct ieee80211_node *ni; 5754 struct ieee80211com *ic = &sc->sc_ic; 5755 uint32_t macstat; 5756 int padding, rate, rssi = 0, noise = 0, type; 5757 uint16_t phytype, phystat0, phystat3, chanstat; 5758 unsigned char *mp = mtod(m, unsigned char *); 5759 static int rx_mac_dec_rpt = 0; 5760 5761 BWN_ASSERT_LOCKED(sc); 5762 5763 phystat0 = le16toh(rxhdr->phy_status0); 5764 5765 /* 5766 * XXX Note: phy_status3 doesn't exist for HT-PHY; it's only 5767 * used for LP-PHY. 5768 */ 5769 phystat3 = le16toh(rxhdr->ps3.lp.phy_status3); 5770 5771 switch (mac->mac_fw.fw_hdr_format) { 5772 case BWN_FW_HDR_351: 5773 case BWN_FW_HDR_410: 5774 macstat = le32toh(rxhdr->ps4.r351.mac_status); 5775 chanstat = le16toh(rxhdr->ps4.r351.channel); 5776 break; 5777 case BWN_FW_HDR_598: 5778 macstat = le32toh(rxhdr->ps4.r598.mac_status); 5779 chanstat = le16toh(rxhdr->ps4.r598.channel); 5780 break; 5781 } 5782 5783 5784 phytype = chanstat & BWN_RX_CHAN_PHYTYPE; 5785 5786 if (macstat & BWN_RX_MAC_FCSERR) 5787 device_printf(sc->sc_dev, "TODO RX: RX_FLAG_FAILED_FCS_CRC\n"); 5788 if (phystat0 & (BWN_RX_PHYST0_PLCPHCF | BWN_RX_PHYST0_PLCPFV)) 5789 device_printf(sc->sc_dev, "TODO RX: RX_FLAG_FAILED_PLCP_CRC\n"); 5790 if (macstat & BWN_RX_MAC_DECERR) 5791 goto drop; 5792 5793 padding = (macstat & BWN_RX_MAC_PADDING) ? 2 : 0; 5794 if (m->m_pkthdr.len < (sizeof(struct bwn_plcp6) + padding)) { 5795 device_printf(sc->sc_dev, "frame too short (length=%d)\n", 5796 m->m_pkthdr.len); 5797 goto drop; 5798 } 5799 plcp = (struct bwn_plcp6 *)(mp + padding); 5800 m_adj(m, sizeof(struct bwn_plcp6) + padding); 5801 if (m->m_pkthdr.len < IEEE80211_MIN_LEN) { 5802 device_printf(sc->sc_dev, "frame too short (length=%d)\n", 5803 m->m_pkthdr.len); 5804 goto drop; 5805 } 5806 wh = mtod(m, struct ieee80211_frame_min *); 5807 5808 if (macstat & BWN_RX_MAC_DEC && rx_mac_dec_rpt++ < 50) 5809 device_printf(sc->sc_dev, 5810 "RX decryption attempted (old %d keyidx %#x)\n", 5811 BWN_ISOLDFMT(mac), 5812 (macstat & BWN_RX_MAC_KEYIDX) >> BWN_RX_MAC_KEYIDX_SHIFT); 5813 5814 if (phystat0 & BWN_RX_PHYST0_OFDM) 5815 rate = bwn_plcp_get_ofdmrate(mac, plcp, 5816 phytype == BWN_PHYTYPE_A); 5817 else 5818 rate = bwn_plcp_get_cckrate(mac, plcp); 5819 if (rate == -1) { 5820 if (!(mac->mac_sc->sc_filters & BWN_MACCTL_PASS_BADPLCP)) 5821 goto drop; 5822 } 5823 sc->sc_rx_rate = bwn_hwrate2ieeerate(rate); 5824 5825 /* rssi/noise */ 5826 switch (phytype) { 5827 case BWN_PHYTYPE_A: 5828 case BWN_PHYTYPE_B: 5829 case BWN_PHYTYPE_G: 5830 case BWN_PHYTYPE_LP: 5831 rssi = bwn_rx_rssi_calc(mac, rxhdr->phy.abg.rssi, 5832 !! (phystat0 & BWN_RX_PHYST0_OFDM), 5833 !! (phystat0 & BWN_RX_PHYST0_GAINCTL), 5834 !! (phystat3 & BWN_RX_PHYST3_TRSTATE)); 5835 break; 5836 case BWN_PHYTYPE_N: 5837 /* Broadcom has code for min/avg, but always used max */ 5838 if (rxhdr->phy.n.power0 == 16 || rxhdr->phy.n.power0 == 32) 5839 rssi = max(rxhdr->phy.n.power1, rxhdr->ps2.n.power2); 5840 else 5841 rssi = max(rxhdr->phy.n.power0, rxhdr->phy.n.power1); 5842 #if 0 5843 DPRINTF(mac->mac_sc, BWN_DEBUG_RECV, 5844 "%s: power0=%d, power1=%d, power2=%d\n", 5845 __func__, 5846 rxhdr->phy.n.power0, 5847 rxhdr->phy.n.power1, 5848 rxhdr->ps2.n.power2); 5849 #endif 5850 break; 5851 default: 5852 /* XXX TODO: implement rssi for other PHYs */ 5853 break; 5854 } 5855 5856 /* 5857 * RSSI here is absolute, not relative to the noise floor. 5858 */ 5859 noise = mac->mac_stats.link_noise; 5860 rssi = rssi - noise; 5861 5862 /* RX radio tap */ 5863 if (ieee80211_radiotap_active(ic)) 5864 bwn_rx_radiotap(mac, m, rxhdr, plcp, rate, rssi, noise); 5865 m_adj(m, -IEEE80211_CRC_LEN); 5866 5867 BWN_UNLOCK(sc); 5868 5869 ni = ieee80211_find_rxnode(ic, wh); 5870 if (ni != NULL) { 5871 type = ieee80211_input(ni, m, rssi, noise); 5872 ieee80211_free_node(ni); 5873 } else 5874 type = ieee80211_input_all(ic, m, rssi, noise); 5875 5876 BWN_LOCK(sc); 5877 return; 5878 drop: 5879 device_printf(sc->sc_dev, "%s: dropped\n", __func__); 5880 } 5881 5882 static void 5883 bwn_dma_handle_txeof(struct bwn_mac *mac, 5884 const struct bwn_txstatus *status) 5885 { 5886 struct bwn_dma *dma = &mac->mac_method.dma; 5887 struct bwn_dma_ring *dr; 5888 struct bwn_dmadesc_generic *desc; 5889 struct bwn_dmadesc_meta *meta; 5890 struct bwn_softc *sc = mac->mac_sc; 5891 int slot; 5892 int retrycnt = 0; 5893 5894 BWN_ASSERT_LOCKED(sc); 5895 5896 dr = bwn_dma_parse_cookie(mac, status, status->cookie, &slot); 5897 if (dr == NULL) { 5898 device_printf(sc->sc_dev, "failed to parse cookie\n"); 5899 return; 5900 } 5901 KASSERT(dr->dr_tx, ("%s:%d: fail", __func__, __LINE__)); 5902 5903 while (1) { 5904 KASSERT(slot >= 0 && slot < dr->dr_numslots, 5905 ("%s:%d: fail", __func__, __LINE__)); 5906 dr->getdesc(dr, slot, &desc, &meta); 5907 5908 if (meta->mt_txtype == BWN_DMADESC_METATYPE_HEADER) 5909 bus_dmamap_unload(dr->dr_txring_dtag, meta->mt_dmap); 5910 else if (meta->mt_txtype == BWN_DMADESC_METATYPE_BODY) 5911 bus_dmamap_unload(dma->txbuf_dtag, meta->mt_dmap); 5912 5913 if (meta->mt_islast) { 5914 KASSERT(meta->mt_m != NULL, 5915 ("%s:%d: fail", __func__, __LINE__)); 5916 5917 /* 5918 * If we don't get an ACK, then we should log the 5919 * full framecnt. That may be 0 if it's a PHY 5920 * failure, so ensure that gets logged as some 5921 * retry attempt. 5922 */ 5923 if (status->ack) { 5924 retrycnt = status->framecnt - 1; 5925 } else { 5926 retrycnt = status->framecnt; 5927 if (retrycnt == 0) 5928 retrycnt = 1; 5929 } 5930 ieee80211_ratectl_tx_complete(meta->mt_ni->ni_vap, meta->mt_ni, 5931 status->ack ? 5932 IEEE80211_RATECTL_TX_SUCCESS : 5933 IEEE80211_RATECTL_TX_FAILURE, 5934 &retrycnt, 0); 5935 ieee80211_tx_complete(meta->mt_ni, meta->mt_m, 0); 5936 meta->mt_ni = NULL; 5937 meta->mt_m = NULL; 5938 } else 5939 KASSERT(meta->mt_m == NULL, 5940 ("%s:%d: fail", __func__, __LINE__)); 5941 5942 dr->dr_usedslot--; 5943 if (meta->mt_islast) 5944 break; 5945 slot = bwn_dma_nextslot(dr, slot); 5946 } 5947 sc->sc_watchdog_timer = 0; 5948 if (dr->dr_stop) { 5949 KASSERT(bwn_dma_freeslot(dr) >= BWN_TX_SLOTS_PER_FRAME, 5950 ("%s:%d: fail", __func__, __LINE__)); 5951 dr->dr_stop = 0; 5952 } 5953 } 5954 5955 static void 5956 bwn_pio_handle_txeof(struct bwn_mac *mac, 5957 const struct bwn_txstatus *status) 5958 { 5959 struct bwn_pio_txqueue *tq; 5960 struct bwn_pio_txpkt *tp = NULL; 5961 struct bwn_softc *sc = mac->mac_sc; 5962 int retrycnt = 0; 5963 5964 BWN_ASSERT_LOCKED(sc); 5965 5966 tq = bwn_pio_parse_cookie(mac, status->cookie, &tp); 5967 if (tq == NULL) 5968 return; 5969 5970 tq->tq_used -= roundup(tp->tp_m->m_pkthdr.len + BWN_HDRSIZE(mac), 4); 5971 tq->tq_free++; 5972 5973 if (tp->tp_ni != NULL) { 5974 /* 5975 * Do any tx complete callback. Note this must 5976 * be done before releasing the node reference. 5977 */ 5978 5979 /* 5980 * If we don't get an ACK, then we should log the 5981 * full framecnt. That may be 0 if it's a PHY 5982 * failure, so ensure that gets logged as some 5983 * retry attempt. 5984 */ 5985 if (status->ack) { 5986 retrycnt = status->framecnt - 1; 5987 } else { 5988 retrycnt = status->framecnt; 5989 if (retrycnt == 0) 5990 retrycnt = 1; 5991 } 5992 ieee80211_ratectl_tx_complete(tp->tp_ni->ni_vap, tp->tp_ni, 5993 status->ack ? 5994 IEEE80211_RATECTL_TX_SUCCESS : 5995 IEEE80211_RATECTL_TX_FAILURE, 5996 &retrycnt, 0); 5997 5998 if (tp->tp_m->m_flags & M_TXCB) 5999 ieee80211_process_callback(tp->tp_ni, tp->tp_m, 0); 6000 ieee80211_free_node(tp->tp_ni); 6001 tp->tp_ni = NULL; 6002 } 6003 m_freem(tp->tp_m); 6004 tp->tp_m = NULL; 6005 TAILQ_INSERT_TAIL(&tq->tq_pktlist, tp, tp_list); 6006 6007 sc->sc_watchdog_timer = 0; 6008 } 6009 6010 static void 6011 bwn_phy_txpower_check(struct bwn_mac *mac, uint32_t flags) 6012 { 6013 struct bwn_softc *sc = mac->mac_sc; 6014 struct bwn_phy *phy = &mac->mac_phy; 6015 struct ieee80211com *ic = &sc->sc_ic; 6016 unsigned long now; 6017 bwn_txpwr_result_t result; 6018 6019 BWN_GETTIME(now); 6020 6021 if (!(flags & BWN_TXPWR_IGNORE_TIME) && ieee80211_time_before(now, phy->nexttime)) 6022 return; 6023 phy->nexttime = now + 2 * 1000; 6024 6025 if (siba_get_pci_subvendor(sc->sc_dev) == SIBA_BOARDVENDOR_BCM && 6026 siba_get_pci_subdevice(sc->sc_dev) == SIBA_BOARD_BU4306) 6027 return; 6028 6029 if (phy->recalc_txpwr != NULL) { 6030 result = phy->recalc_txpwr(mac, 6031 (flags & BWN_TXPWR_IGNORE_TSSI) ? 1 : 0); 6032 if (result == BWN_TXPWR_RES_DONE) 6033 return; 6034 KASSERT(result == BWN_TXPWR_RES_NEED_ADJUST, 6035 ("%s: fail", __func__)); 6036 KASSERT(phy->set_txpwr != NULL, ("%s: fail", __func__)); 6037 6038 ieee80211_runtask(ic, &mac->mac_txpower); 6039 } 6040 } 6041 6042 static uint16_t 6043 bwn_pio_rx_read_2(struct bwn_pio_rxqueue *prq, uint16_t offset) 6044 { 6045 6046 return (BWN_READ_2(prq->prq_mac, prq->prq_base + offset)); 6047 } 6048 6049 static uint32_t 6050 bwn_pio_rx_read_4(struct bwn_pio_rxqueue *prq, uint16_t offset) 6051 { 6052 6053 return (BWN_READ_4(prq->prq_mac, prq->prq_base + offset)); 6054 } 6055 6056 static void 6057 bwn_pio_rx_write_2(struct bwn_pio_rxqueue *prq, uint16_t offset, uint16_t value) 6058 { 6059 6060 BWN_WRITE_2(prq->prq_mac, prq->prq_base + offset, value); 6061 } 6062 6063 static void 6064 bwn_pio_rx_write_4(struct bwn_pio_rxqueue *prq, uint16_t offset, uint32_t value) 6065 { 6066 6067 BWN_WRITE_4(prq->prq_mac, prq->prq_base + offset, value); 6068 } 6069 6070 static int 6071 bwn_ieeerate2hwrate(struct bwn_softc *sc, int rate) 6072 { 6073 6074 switch (rate) { 6075 /* OFDM rates (cf IEEE Std 802.11a-1999, pp. 14 Table 80) */ 6076 case 12: 6077 return (BWN_OFDM_RATE_6MB); 6078 case 18: 6079 return (BWN_OFDM_RATE_9MB); 6080 case 24: 6081 return (BWN_OFDM_RATE_12MB); 6082 case 36: 6083 return (BWN_OFDM_RATE_18MB); 6084 case 48: 6085 return (BWN_OFDM_RATE_24MB); 6086 case 72: 6087 return (BWN_OFDM_RATE_36MB); 6088 case 96: 6089 return (BWN_OFDM_RATE_48MB); 6090 case 108: 6091 return (BWN_OFDM_RATE_54MB); 6092 /* CCK rates (NB: not IEEE std, device-specific) */ 6093 case 2: 6094 return (BWN_CCK_RATE_1MB); 6095 case 4: 6096 return (BWN_CCK_RATE_2MB); 6097 case 11: 6098 return (BWN_CCK_RATE_5MB); 6099 case 22: 6100 return (BWN_CCK_RATE_11MB); 6101 } 6102 6103 device_printf(sc->sc_dev, "unsupported rate %d\n", rate); 6104 return (BWN_CCK_RATE_1MB); 6105 } 6106 6107 static uint16_t 6108 bwn_set_txhdr_phyctl1(struct bwn_mac *mac, uint8_t bitrate) 6109 { 6110 struct bwn_phy *phy = &mac->mac_phy; 6111 uint16_t control = 0; 6112 uint16_t bw; 6113 6114 /* XXX TODO: this is for LP phy, what about N-PHY, etc? */ 6115 bw = BWN_TXH_PHY1_BW_20; 6116 6117 if (BWN_ISCCKRATE(bitrate) && phy->type != BWN_PHYTYPE_LP) { 6118 control = bw; 6119 } else { 6120 control = bw; 6121 /* Figure out coding rate and modulation */ 6122 /* XXX TODO: table-ize, for MCS transmit */ 6123 /* Note: this is BWN_*_RATE values */ 6124 switch (bitrate) { 6125 case BWN_CCK_RATE_1MB: 6126 control |= 0; 6127 break; 6128 case BWN_CCK_RATE_2MB: 6129 control |= 1; 6130 break; 6131 case BWN_CCK_RATE_5MB: 6132 control |= 2; 6133 break; 6134 case BWN_CCK_RATE_11MB: 6135 control |= 3; 6136 break; 6137 case BWN_OFDM_RATE_6MB: 6138 control |= BWN_TXH_PHY1_CRATE_1_2; 6139 control |= BWN_TXH_PHY1_MODUL_BPSK; 6140 break; 6141 case BWN_OFDM_RATE_9MB: 6142 control |= BWN_TXH_PHY1_CRATE_3_4; 6143 control |= BWN_TXH_PHY1_MODUL_BPSK; 6144 break; 6145 case BWN_OFDM_RATE_12MB: 6146 control |= BWN_TXH_PHY1_CRATE_1_2; 6147 control |= BWN_TXH_PHY1_MODUL_QPSK; 6148 break; 6149 case BWN_OFDM_RATE_18MB: 6150 control |= BWN_TXH_PHY1_CRATE_3_4; 6151 control |= BWN_TXH_PHY1_MODUL_QPSK; 6152 break; 6153 case BWN_OFDM_RATE_24MB: 6154 control |= BWN_TXH_PHY1_CRATE_1_2; 6155 control |= BWN_TXH_PHY1_MODUL_QAM16; 6156 break; 6157 case BWN_OFDM_RATE_36MB: 6158 control |= BWN_TXH_PHY1_CRATE_3_4; 6159 control |= BWN_TXH_PHY1_MODUL_QAM16; 6160 break; 6161 case BWN_OFDM_RATE_48MB: 6162 control |= BWN_TXH_PHY1_CRATE_1_2; 6163 control |= BWN_TXH_PHY1_MODUL_QAM64; 6164 break; 6165 case BWN_OFDM_RATE_54MB: 6166 control |= BWN_TXH_PHY1_CRATE_3_4; 6167 control |= BWN_TXH_PHY1_MODUL_QAM64; 6168 break; 6169 default: 6170 break; 6171 } 6172 control |= BWN_TXH_PHY1_MODE_SISO; 6173 } 6174 6175 return control; 6176 } 6177 6178 static int 6179 bwn_set_txhdr(struct bwn_mac *mac, struct ieee80211_node *ni, 6180 struct mbuf *m, struct bwn_txhdr *txhdr, uint16_t cookie) 6181 { 6182 const struct bwn_phy *phy = &mac->mac_phy; 6183 struct bwn_softc *sc = mac->mac_sc; 6184 struct ieee80211_frame *wh; 6185 struct ieee80211_frame *protwh; 6186 struct ieee80211_frame_cts *cts; 6187 struct ieee80211_frame_rts *rts; 6188 const struct ieee80211_txparam *tp; 6189 struct ieee80211vap *vap = ni->ni_vap; 6190 struct ieee80211com *ic = &sc->sc_ic; 6191 struct mbuf *mprot; 6192 unsigned int len; 6193 uint32_t macctl = 0; 6194 int protdur, rts_rate, rts_rate_fb, ismcast, isshort, rix, type; 6195 uint16_t phyctl = 0; 6196 uint8_t rate, rate_fb; 6197 int fill_phy_ctl1 = 0; 6198 6199 wh = mtod(m, struct ieee80211_frame *); 6200 memset(txhdr, 0, sizeof(*txhdr)); 6201 6202 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 6203 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 6204 isshort = (ic->ic_flags & IEEE80211_F_SHPREAMBLE) != 0; 6205 6206 if ((phy->type == BWN_PHYTYPE_N) || (phy->type == BWN_PHYTYPE_LP) 6207 || (phy->type == BWN_PHYTYPE_HT)) 6208 fill_phy_ctl1 = 1; 6209 6210 /* 6211 * Find TX rate 6212 */ 6213 tp = &vap->iv_txparms[ieee80211_chan2mode(ic->ic_curchan)]; 6214 if (type != IEEE80211_FC0_TYPE_DATA || (m->m_flags & M_EAPOL)) 6215 rate = rate_fb = tp->mgmtrate; 6216 else if (ismcast) 6217 rate = rate_fb = tp->mcastrate; 6218 else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) 6219 rate = rate_fb = tp->ucastrate; 6220 else { 6221 /* XXX TODO: don't fall back to CCK rates for OFDM */ 6222 rix = ieee80211_ratectl_rate(ni, NULL, 0); 6223 rate = ni->ni_txrate; 6224 6225 if (rix > 0) 6226 rate_fb = ni->ni_rates.rs_rates[rix - 1] & 6227 IEEE80211_RATE_VAL; 6228 else 6229 rate_fb = rate; 6230 } 6231 6232 sc->sc_tx_rate = rate; 6233 6234 /* Note: this maps the select ieee80211 rate to hardware rate */ 6235 rate = bwn_ieeerate2hwrate(sc, rate); 6236 rate_fb = bwn_ieeerate2hwrate(sc, rate_fb); 6237 6238 txhdr->phyrate = (BWN_ISOFDMRATE(rate)) ? bwn_plcp_getofdm(rate) : 6239 bwn_plcp_getcck(rate); 6240 bcopy(wh->i_fc, txhdr->macfc, sizeof(txhdr->macfc)); 6241 bcopy(wh->i_addr1, txhdr->addr1, IEEE80211_ADDR_LEN); 6242 6243 /* XXX rate/rate_fb is the hardware rate */ 6244 if ((rate_fb == rate) || 6245 (*(u_int16_t *)wh->i_dur & htole16(0x8000)) || 6246 (*(u_int16_t *)wh->i_dur == htole16(0))) 6247 txhdr->dur_fb = *(u_int16_t *)wh->i_dur; 6248 else 6249 txhdr->dur_fb = ieee80211_compute_duration(ic->ic_rt, 6250 m->m_pkthdr.len, rate, isshort); 6251 6252 /* XXX TX encryption */ 6253 6254 switch (mac->mac_fw.fw_hdr_format) { 6255 case BWN_FW_HDR_351: 6256 bwn_plcp_genhdr((struct bwn_plcp4 *)(&txhdr->body.r351.plcp), 6257 m->m_pkthdr.len + IEEE80211_CRC_LEN, rate); 6258 break; 6259 case BWN_FW_HDR_410: 6260 bwn_plcp_genhdr((struct bwn_plcp4 *)(&txhdr->body.r410.plcp), 6261 m->m_pkthdr.len + IEEE80211_CRC_LEN, rate); 6262 break; 6263 case BWN_FW_HDR_598: 6264 bwn_plcp_genhdr((struct bwn_plcp4 *)(&txhdr->body.r598.plcp), 6265 m->m_pkthdr.len + IEEE80211_CRC_LEN, rate); 6266 break; 6267 } 6268 6269 bwn_plcp_genhdr((struct bwn_plcp4 *)(&txhdr->plcp_fb), 6270 m->m_pkthdr.len + IEEE80211_CRC_LEN, rate_fb); 6271 6272 txhdr->eftypes |= (BWN_ISOFDMRATE(rate_fb)) ? BWN_TX_EFT_FB_OFDM : 6273 BWN_TX_EFT_FB_CCK; 6274 txhdr->chan = phy->chan; 6275 phyctl |= (BWN_ISOFDMRATE(rate)) ? BWN_TX_PHY_ENC_OFDM : 6276 BWN_TX_PHY_ENC_CCK; 6277 /* XXX preamble? obey net80211 */ 6278 if (isshort && (rate == BWN_CCK_RATE_2MB || rate == BWN_CCK_RATE_5MB || 6279 rate == BWN_CCK_RATE_11MB)) 6280 phyctl |= BWN_TX_PHY_SHORTPRMBL; 6281 6282 if (! phy->gmode) 6283 macctl |= BWN_TX_MAC_5GHZ; 6284 6285 /* XXX TX antenna selection */ 6286 6287 switch (bwn_antenna_sanitize(mac, 0)) { 6288 case 0: 6289 phyctl |= BWN_TX_PHY_ANT01AUTO; 6290 break; 6291 case 1: 6292 phyctl |= BWN_TX_PHY_ANT0; 6293 break; 6294 case 2: 6295 phyctl |= BWN_TX_PHY_ANT1; 6296 break; 6297 case 3: 6298 phyctl |= BWN_TX_PHY_ANT2; 6299 break; 6300 case 4: 6301 phyctl |= BWN_TX_PHY_ANT3; 6302 break; 6303 default: 6304 KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__)); 6305 } 6306 6307 if (!ismcast) 6308 macctl |= BWN_TX_MAC_ACK; 6309 6310 macctl |= (BWN_TX_MAC_HWSEQ | BWN_TX_MAC_START_MSDU); 6311 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 6312 m->m_pkthdr.len + IEEE80211_CRC_LEN > vap->iv_rtsthreshold) 6313 macctl |= BWN_TX_MAC_LONGFRAME; 6314 6315 if (ic->ic_flags & IEEE80211_F_USEPROT) { 6316 /* XXX RTS rate is always 1MB??? */ 6317 /* XXX TODO: don't fall back to CCK rates for OFDM */ 6318 rts_rate = BWN_CCK_RATE_1MB; 6319 rts_rate_fb = bwn_get_fbrate(rts_rate); 6320 6321 /* XXX 'rate' here is hardware rate now, not the net80211 rate */ 6322 protdur = ieee80211_compute_duration(ic->ic_rt, 6323 m->m_pkthdr.len, rate, isshort) + 6324 + ieee80211_ack_duration(ic->ic_rt, rate, isshort); 6325 6326 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) { 6327 6328 switch (mac->mac_fw.fw_hdr_format) { 6329 case BWN_FW_HDR_351: 6330 cts = (struct ieee80211_frame_cts *) 6331 txhdr->body.r351.rts_frame; 6332 break; 6333 case BWN_FW_HDR_410: 6334 cts = (struct ieee80211_frame_cts *) 6335 txhdr->body.r410.rts_frame; 6336 break; 6337 case BWN_FW_HDR_598: 6338 cts = (struct ieee80211_frame_cts *) 6339 txhdr->body.r598.rts_frame; 6340 break; 6341 } 6342 6343 mprot = ieee80211_alloc_cts(ic, ni->ni_vap->iv_myaddr, 6344 protdur); 6345 KASSERT(mprot != NULL, ("failed to alloc mbuf\n")); 6346 bcopy(mtod(mprot, uint8_t *), (uint8_t *)cts, 6347 mprot->m_pkthdr.len); 6348 m_freem(mprot); 6349 macctl |= BWN_TX_MAC_SEND_CTSTOSELF; 6350 len = sizeof(struct ieee80211_frame_cts); 6351 } else { 6352 switch (mac->mac_fw.fw_hdr_format) { 6353 case BWN_FW_HDR_351: 6354 rts = (struct ieee80211_frame_rts *) 6355 txhdr->body.r351.rts_frame; 6356 break; 6357 case BWN_FW_HDR_410: 6358 rts = (struct ieee80211_frame_rts *) 6359 txhdr->body.r410.rts_frame; 6360 break; 6361 case BWN_FW_HDR_598: 6362 rts = (struct ieee80211_frame_rts *) 6363 txhdr->body.r598.rts_frame; 6364 break; 6365 } 6366 6367 /* XXX rate/rate_fb is the hardware rate */ 6368 protdur += ieee80211_ack_duration(ic->ic_rt, rate, 6369 isshort); 6370 mprot = ieee80211_alloc_rts(ic, wh->i_addr1, 6371 wh->i_addr2, protdur); 6372 KASSERT(mprot != NULL, ("failed to alloc mbuf\n")); 6373 bcopy(mtod(mprot, uint8_t *), (uint8_t *)rts, 6374 mprot->m_pkthdr.len); 6375 m_freem(mprot); 6376 macctl |= BWN_TX_MAC_SEND_RTSCTS; 6377 len = sizeof(struct ieee80211_frame_rts); 6378 } 6379 len += IEEE80211_CRC_LEN; 6380 6381 switch (mac->mac_fw.fw_hdr_format) { 6382 case BWN_FW_HDR_351: 6383 bwn_plcp_genhdr((struct bwn_plcp4 *) 6384 &txhdr->body.r351.rts_plcp, len, rts_rate); 6385 break; 6386 case BWN_FW_HDR_410: 6387 bwn_plcp_genhdr((struct bwn_plcp4 *) 6388 &txhdr->body.r410.rts_plcp, len, rts_rate); 6389 break; 6390 case BWN_FW_HDR_598: 6391 bwn_plcp_genhdr((struct bwn_plcp4 *) 6392 &txhdr->body.r598.rts_plcp, len, rts_rate); 6393 break; 6394 } 6395 6396 bwn_plcp_genhdr((struct bwn_plcp4 *)&txhdr->rts_plcp_fb, len, 6397 rts_rate_fb); 6398 6399 switch (mac->mac_fw.fw_hdr_format) { 6400 case BWN_FW_HDR_351: 6401 protwh = (struct ieee80211_frame *) 6402 &txhdr->body.r351.rts_frame; 6403 break; 6404 case BWN_FW_HDR_410: 6405 protwh = (struct ieee80211_frame *) 6406 &txhdr->body.r410.rts_frame; 6407 break; 6408 case BWN_FW_HDR_598: 6409 protwh = (struct ieee80211_frame *) 6410 &txhdr->body.r598.rts_frame; 6411 break; 6412 } 6413 6414 txhdr->rts_dur_fb = *(u_int16_t *)protwh->i_dur; 6415 6416 if (BWN_ISOFDMRATE(rts_rate)) { 6417 txhdr->eftypes |= BWN_TX_EFT_RTS_OFDM; 6418 txhdr->phyrate_rts = bwn_plcp_getofdm(rts_rate); 6419 } else { 6420 txhdr->eftypes |= BWN_TX_EFT_RTS_CCK; 6421 txhdr->phyrate_rts = bwn_plcp_getcck(rts_rate); 6422 } 6423 txhdr->eftypes |= (BWN_ISOFDMRATE(rts_rate_fb)) ? 6424 BWN_TX_EFT_RTS_FBOFDM : BWN_TX_EFT_RTS_FBCCK; 6425 6426 if (fill_phy_ctl1) { 6427 txhdr->phyctl_1rts = htole16(bwn_set_txhdr_phyctl1(mac, rts_rate)); 6428 txhdr->phyctl_1rtsfb = htole16(bwn_set_txhdr_phyctl1(mac, rts_rate_fb)); 6429 } 6430 } 6431 6432 if (fill_phy_ctl1) { 6433 txhdr->phyctl_1 = htole16(bwn_set_txhdr_phyctl1(mac, rate)); 6434 txhdr->phyctl_1fb = htole16(bwn_set_txhdr_phyctl1(mac, rate_fb)); 6435 } 6436 6437 switch (mac->mac_fw.fw_hdr_format) { 6438 case BWN_FW_HDR_351: 6439 txhdr->body.r351.cookie = htole16(cookie); 6440 break; 6441 case BWN_FW_HDR_410: 6442 txhdr->body.r410.cookie = htole16(cookie); 6443 break; 6444 case BWN_FW_HDR_598: 6445 txhdr->body.r598.cookie = htole16(cookie); 6446 break; 6447 } 6448 6449 txhdr->macctl = htole32(macctl); 6450 txhdr->phyctl = htole16(phyctl); 6451 6452 /* 6453 * TX radio tap 6454 */ 6455 if (ieee80211_radiotap_active_vap(vap)) { 6456 sc->sc_tx_th.wt_flags = 0; 6457 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) 6458 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP; 6459 if (isshort && 6460 (rate == BWN_CCK_RATE_2MB || rate == BWN_CCK_RATE_5MB || 6461 rate == BWN_CCK_RATE_11MB)) 6462 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 6463 sc->sc_tx_th.wt_rate = rate; 6464 6465 ieee80211_radiotap_tx(vap, m); 6466 } 6467 6468 return (0); 6469 } 6470 6471 static void 6472 bwn_plcp_genhdr(struct bwn_plcp4 *plcp, const uint16_t octets, 6473 const uint8_t rate) 6474 { 6475 uint32_t d, plen; 6476 uint8_t *raw = plcp->o.raw; 6477 6478 if (BWN_ISOFDMRATE(rate)) { 6479 d = bwn_plcp_getofdm(rate); 6480 KASSERT(!(octets & 0xf000), 6481 ("%s:%d: fail", __func__, __LINE__)); 6482 d |= (octets << 5); 6483 plcp->o.data = htole32(d); 6484 } else { 6485 plen = octets * 16 / rate; 6486 if ((octets * 16 % rate) > 0) { 6487 plen++; 6488 if ((rate == BWN_CCK_RATE_11MB) 6489 && ((octets * 8 % 11) < 4)) { 6490 raw[1] = 0x84; 6491 } else 6492 raw[1] = 0x04; 6493 } else 6494 raw[1] = 0x04; 6495 plcp->o.data |= htole32(plen << 16); 6496 raw[0] = bwn_plcp_getcck(rate); 6497 } 6498 } 6499 6500 static uint8_t 6501 bwn_antenna_sanitize(struct bwn_mac *mac, uint8_t n) 6502 { 6503 struct bwn_softc *sc = mac->mac_sc; 6504 uint8_t mask; 6505 6506 if (n == 0) 6507 return (0); 6508 if (mac->mac_phy.gmode) 6509 mask = siba_sprom_get_ant_bg(sc->sc_dev); 6510 else 6511 mask = siba_sprom_get_ant_a(sc->sc_dev); 6512 if (!(mask & (1 << (n - 1)))) 6513 return (0); 6514 return (n); 6515 } 6516 6517 /* 6518 * Return a fallback rate for the given rate. 6519 * 6520 * Note: Don't fall back from OFDM to CCK. 6521 */ 6522 static uint8_t 6523 bwn_get_fbrate(uint8_t bitrate) 6524 { 6525 switch (bitrate) { 6526 /* CCK */ 6527 case BWN_CCK_RATE_1MB: 6528 return (BWN_CCK_RATE_1MB); 6529 case BWN_CCK_RATE_2MB: 6530 return (BWN_CCK_RATE_1MB); 6531 case BWN_CCK_RATE_5MB: 6532 return (BWN_CCK_RATE_2MB); 6533 case BWN_CCK_RATE_11MB: 6534 return (BWN_CCK_RATE_5MB); 6535 6536 /* OFDM */ 6537 case BWN_OFDM_RATE_6MB: 6538 return (BWN_OFDM_RATE_6MB); 6539 case BWN_OFDM_RATE_9MB: 6540 return (BWN_OFDM_RATE_6MB); 6541 case BWN_OFDM_RATE_12MB: 6542 return (BWN_OFDM_RATE_9MB); 6543 case BWN_OFDM_RATE_18MB: 6544 return (BWN_OFDM_RATE_12MB); 6545 case BWN_OFDM_RATE_24MB: 6546 return (BWN_OFDM_RATE_18MB); 6547 case BWN_OFDM_RATE_36MB: 6548 return (BWN_OFDM_RATE_24MB); 6549 case BWN_OFDM_RATE_48MB: 6550 return (BWN_OFDM_RATE_36MB); 6551 case BWN_OFDM_RATE_54MB: 6552 return (BWN_OFDM_RATE_48MB); 6553 } 6554 KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__)); 6555 return (0); 6556 } 6557 6558 static uint32_t 6559 bwn_pio_write_multi_4(struct bwn_mac *mac, struct bwn_pio_txqueue *tq, 6560 uint32_t ctl, const void *_data, int len) 6561 { 6562 struct bwn_softc *sc = mac->mac_sc; 6563 uint32_t value = 0; 6564 const uint8_t *data = _data; 6565 6566 ctl |= BWN_PIO8_TXCTL_0_7 | BWN_PIO8_TXCTL_8_15 | 6567 BWN_PIO8_TXCTL_16_23 | BWN_PIO8_TXCTL_24_31; 6568 bwn_pio_write_4(mac, tq, BWN_PIO8_TXCTL, ctl); 6569 6570 siba_write_multi_4(sc->sc_dev, data, (len & ~3), 6571 tq->tq_base + BWN_PIO8_TXDATA); 6572 if (len & 3) { 6573 ctl &= ~(BWN_PIO8_TXCTL_8_15 | BWN_PIO8_TXCTL_16_23 | 6574 BWN_PIO8_TXCTL_24_31); 6575 data = &(data[len - 1]); 6576 switch (len & 3) { 6577 case 3: 6578 ctl |= BWN_PIO8_TXCTL_16_23; 6579 value |= (uint32_t)(*data) << 16; 6580 data--; 6581 case 2: 6582 ctl |= BWN_PIO8_TXCTL_8_15; 6583 value |= (uint32_t)(*data) << 8; 6584 data--; 6585 case 1: 6586 value |= (uint32_t)(*data); 6587 } 6588 bwn_pio_write_4(mac, tq, BWN_PIO8_TXCTL, ctl); 6589 bwn_pio_write_4(mac, tq, BWN_PIO8_TXDATA, value); 6590 } 6591 6592 return (ctl); 6593 } 6594 6595 static void 6596 bwn_pio_write_4(struct bwn_mac *mac, struct bwn_pio_txqueue *tq, 6597 uint16_t offset, uint32_t value) 6598 { 6599 6600 BWN_WRITE_4(mac, tq->tq_base + offset, value); 6601 } 6602 6603 static uint16_t 6604 bwn_pio_write_multi_2(struct bwn_mac *mac, struct bwn_pio_txqueue *tq, 6605 uint16_t ctl, const void *_data, int len) 6606 { 6607 struct bwn_softc *sc = mac->mac_sc; 6608 const uint8_t *data = _data; 6609 6610 ctl |= BWN_PIO_TXCTL_WRITELO | BWN_PIO_TXCTL_WRITEHI; 6611 BWN_PIO_WRITE_2(mac, tq, BWN_PIO_TXCTL, ctl); 6612 6613 siba_write_multi_2(sc->sc_dev, data, (len & ~1), 6614 tq->tq_base + BWN_PIO_TXDATA); 6615 if (len & 1) { 6616 ctl &= ~BWN_PIO_TXCTL_WRITEHI; 6617 BWN_PIO_WRITE_2(mac, tq, BWN_PIO_TXCTL, ctl); 6618 BWN_PIO_WRITE_2(mac, tq, BWN_PIO_TXDATA, data[len - 1]); 6619 } 6620 6621 return (ctl); 6622 } 6623 6624 static uint16_t 6625 bwn_pio_write_mbuf_2(struct bwn_mac *mac, struct bwn_pio_txqueue *tq, 6626 uint16_t ctl, struct mbuf *m0) 6627 { 6628 int i, j = 0; 6629 uint16_t data = 0; 6630 const uint8_t *buf; 6631 struct mbuf *m = m0; 6632 6633 ctl |= BWN_PIO_TXCTL_WRITELO | BWN_PIO_TXCTL_WRITEHI; 6634 BWN_PIO_WRITE_2(mac, tq, BWN_PIO_TXCTL, ctl); 6635 6636 for (; m != NULL; m = m->m_next) { 6637 buf = mtod(m, const uint8_t *); 6638 for (i = 0; i < m->m_len; i++) { 6639 if (!((j++) % 2)) 6640 data |= buf[i]; 6641 else { 6642 data |= (buf[i] << 8); 6643 BWN_PIO_WRITE_2(mac, tq, BWN_PIO_TXDATA, data); 6644 data = 0; 6645 } 6646 } 6647 } 6648 if (m0->m_pkthdr.len % 2) { 6649 ctl &= ~BWN_PIO_TXCTL_WRITEHI; 6650 BWN_PIO_WRITE_2(mac, tq, BWN_PIO_TXCTL, ctl); 6651 BWN_PIO_WRITE_2(mac, tq, BWN_PIO_TXDATA, data); 6652 } 6653 6654 return (ctl); 6655 } 6656 6657 static void 6658 bwn_set_slot_time(struct bwn_mac *mac, uint16_t time) 6659 { 6660 6661 /* XXX should exit if 5GHz band .. */ 6662 if (mac->mac_phy.type != BWN_PHYTYPE_G) 6663 return; 6664 6665 BWN_WRITE_2(mac, 0x684, 510 + time); 6666 /* Disabled in Linux b43, can adversely effect performance */ 6667 #if 0 6668 bwn_shm_write_2(mac, BWN_SHARED, 0x0010, time); 6669 #endif 6670 } 6671 6672 static struct bwn_dma_ring * 6673 bwn_dma_select(struct bwn_mac *mac, uint8_t prio) 6674 { 6675 6676 if ((mac->mac_flags & BWN_MAC_FLAG_WME) == 0) 6677 return (mac->mac_method.dma.wme[WME_AC_BE]); 6678 6679 switch (prio) { 6680 case 3: 6681 return (mac->mac_method.dma.wme[WME_AC_VO]); 6682 case 2: 6683 return (mac->mac_method.dma.wme[WME_AC_VI]); 6684 case 0: 6685 return (mac->mac_method.dma.wme[WME_AC_BE]); 6686 case 1: 6687 return (mac->mac_method.dma.wme[WME_AC_BK]); 6688 } 6689 KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__)); 6690 return (NULL); 6691 } 6692 6693 static int 6694 bwn_dma_getslot(struct bwn_dma_ring *dr) 6695 { 6696 int slot; 6697 6698 BWN_ASSERT_LOCKED(dr->dr_mac->mac_sc); 6699 6700 KASSERT(dr->dr_tx, ("%s:%d: fail", __func__, __LINE__)); 6701 KASSERT(!(dr->dr_stop), ("%s:%d: fail", __func__, __LINE__)); 6702 KASSERT(bwn_dma_freeslot(dr) != 0, ("%s:%d: fail", __func__, __LINE__)); 6703 6704 slot = bwn_dma_nextslot(dr, dr->dr_curslot); 6705 KASSERT(!(slot & ~0x0fff), ("%s:%d: fail", __func__, __LINE__)); 6706 dr->dr_curslot = slot; 6707 dr->dr_usedslot++; 6708 6709 return (slot); 6710 } 6711 6712 static struct bwn_pio_txqueue * 6713 bwn_pio_parse_cookie(struct bwn_mac *mac, uint16_t cookie, 6714 struct bwn_pio_txpkt **pack) 6715 { 6716 struct bwn_pio *pio = &mac->mac_method.pio; 6717 struct bwn_pio_txqueue *tq = NULL; 6718 unsigned int index; 6719 6720 switch (cookie & 0xf000) { 6721 case 0x1000: 6722 tq = &pio->wme[WME_AC_BK]; 6723 break; 6724 case 0x2000: 6725 tq = &pio->wme[WME_AC_BE]; 6726 break; 6727 case 0x3000: 6728 tq = &pio->wme[WME_AC_VI]; 6729 break; 6730 case 0x4000: 6731 tq = &pio->wme[WME_AC_VO]; 6732 break; 6733 case 0x5000: 6734 tq = &pio->mcast; 6735 break; 6736 } 6737 KASSERT(tq != NULL, ("%s:%d: fail", __func__, __LINE__)); 6738 if (tq == NULL) 6739 return (NULL); 6740 index = (cookie & 0x0fff); 6741 KASSERT(index < N(tq->tq_pkts), ("%s:%d: fail", __func__, __LINE__)); 6742 if (index >= N(tq->tq_pkts)) 6743 return (NULL); 6744 *pack = &tq->tq_pkts[index]; 6745 KASSERT(*pack != NULL, ("%s:%d: fail", __func__, __LINE__)); 6746 return (tq); 6747 } 6748 6749 static void 6750 bwn_txpwr(void *arg, int npending) 6751 { 6752 struct bwn_mac *mac = arg; 6753 struct bwn_softc *sc = mac->mac_sc; 6754 6755 BWN_LOCK(sc); 6756 if (mac && mac->mac_status >= BWN_MAC_STATUS_STARTED && 6757 mac->mac_phy.set_txpwr != NULL) 6758 mac->mac_phy.set_txpwr(mac); 6759 BWN_UNLOCK(sc); 6760 } 6761 6762 static void 6763 bwn_task_15s(struct bwn_mac *mac) 6764 { 6765 uint16_t reg; 6766 6767 if (mac->mac_fw.opensource) { 6768 reg = bwn_shm_read_2(mac, BWN_SCRATCH, BWN_WATCHDOG_REG); 6769 if (reg) { 6770 bwn_restart(mac, "fw watchdog"); 6771 return; 6772 } 6773 bwn_shm_write_2(mac, BWN_SCRATCH, BWN_WATCHDOG_REG, 1); 6774 } 6775 if (mac->mac_phy.task_15s) 6776 mac->mac_phy.task_15s(mac); 6777 6778 mac->mac_phy.txerrors = BWN_TXERROR_MAX; 6779 } 6780 6781 static void 6782 bwn_task_30s(struct bwn_mac *mac) 6783 { 6784 6785 if (mac->mac_phy.type != BWN_PHYTYPE_G || mac->mac_noise.noi_running) 6786 return; 6787 mac->mac_noise.noi_running = 1; 6788 mac->mac_noise.noi_nsamples = 0; 6789 6790 bwn_noise_gensample(mac); 6791 } 6792 6793 static void 6794 bwn_task_60s(struct bwn_mac *mac) 6795 { 6796 6797 if (mac->mac_phy.task_60s) 6798 mac->mac_phy.task_60s(mac); 6799 bwn_phy_txpower_check(mac, BWN_TXPWR_IGNORE_TIME); 6800 } 6801 6802 static void 6803 bwn_tasks(void *arg) 6804 { 6805 struct bwn_mac *mac = arg; 6806 struct bwn_softc *sc = mac->mac_sc; 6807 6808 BWN_ASSERT_LOCKED(sc); 6809 if (mac->mac_status != BWN_MAC_STATUS_STARTED) 6810 return; 6811 6812 if (mac->mac_task_state % 4 == 0) 6813 bwn_task_60s(mac); 6814 if (mac->mac_task_state % 2 == 0) 6815 bwn_task_30s(mac); 6816 bwn_task_15s(mac); 6817 6818 mac->mac_task_state++; 6819 callout_reset(&sc->sc_task_ch, hz * 15, bwn_tasks, mac); 6820 } 6821 6822 static int 6823 bwn_plcp_get_ofdmrate(struct bwn_mac *mac, struct bwn_plcp6 *plcp, uint8_t a) 6824 { 6825 struct bwn_softc *sc = mac->mac_sc; 6826 6827 KASSERT(a == 0, ("not support APHY\n")); 6828 6829 switch (plcp->o.raw[0] & 0xf) { 6830 case 0xb: 6831 return (BWN_OFDM_RATE_6MB); 6832 case 0xf: 6833 return (BWN_OFDM_RATE_9MB); 6834 case 0xa: 6835 return (BWN_OFDM_RATE_12MB); 6836 case 0xe: 6837 return (BWN_OFDM_RATE_18MB); 6838 case 0x9: 6839 return (BWN_OFDM_RATE_24MB); 6840 case 0xd: 6841 return (BWN_OFDM_RATE_36MB); 6842 case 0x8: 6843 return (BWN_OFDM_RATE_48MB); 6844 case 0xc: 6845 return (BWN_OFDM_RATE_54MB); 6846 } 6847 device_printf(sc->sc_dev, "incorrect OFDM rate %d\n", 6848 plcp->o.raw[0] & 0xf); 6849 return (-1); 6850 } 6851 6852 static int 6853 bwn_plcp_get_cckrate(struct bwn_mac *mac, struct bwn_plcp6 *plcp) 6854 { 6855 struct bwn_softc *sc = mac->mac_sc; 6856 6857 switch (plcp->o.raw[0]) { 6858 case 0x0a: 6859 return (BWN_CCK_RATE_1MB); 6860 case 0x14: 6861 return (BWN_CCK_RATE_2MB); 6862 case 0x37: 6863 return (BWN_CCK_RATE_5MB); 6864 case 0x6e: 6865 return (BWN_CCK_RATE_11MB); 6866 } 6867 device_printf(sc->sc_dev, "incorrect CCK rate %d\n", plcp->o.raw[0]); 6868 return (-1); 6869 } 6870 6871 static void 6872 bwn_rx_radiotap(struct bwn_mac *mac, struct mbuf *m, 6873 const struct bwn_rxhdr4 *rxhdr, struct bwn_plcp6 *plcp, int rate, 6874 int rssi, int noise) 6875 { 6876 struct bwn_softc *sc = mac->mac_sc; 6877 const struct ieee80211_frame_min *wh; 6878 uint64_t tsf; 6879 uint16_t low_mactime_now; 6880 uint16_t mt; 6881 6882 if (htole16(rxhdr->phy_status0) & BWN_RX_PHYST0_SHORTPRMBL) 6883 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 6884 6885 wh = mtod(m, const struct ieee80211_frame_min *); 6886 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) 6887 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_WEP; 6888 6889 bwn_tsf_read(mac, &tsf); 6890 low_mactime_now = tsf; 6891 tsf = tsf & ~0xffffULL; 6892 6893 switch (mac->mac_fw.fw_hdr_format) { 6894 case BWN_FW_HDR_351: 6895 case BWN_FW_HDR_410: 6896 mt = le16toh(rxhdr->ps4.r351.mac_time); 6897 break; 6898 case BWN_FW_HDR_598: 6899 mt = le16toh(rxhdr->ps4.r598.mac_time); 6900 break; 6901 } 6902 6903 tsf += mt; 6904 if (low_mactime_now < mt) 6905 tsf -= 0x10000; 6906 6907 sc->sc_rx_th.wr_tsf = tsf; 6908 sc->sc_rx_th.wr_rate = rate; 6909 sc->sc_rx_th.wr_antsignal = rssi; 6910 sc->sc_rx_th.wr_antnoise = noise; 6911 } 6912 6913 static void 6914 bwn_tsf_read(struct bwn_mac *mac, uint64_t *tsf) 6915 { 6916 uint32_t low, high; 6917 6918 KASSERT(siba_get_revid(mac->mac_sc->sc_dev) >= 3, 6919 ("%s:%d: fail", __func__, __LINE__)); 6920 6921 low = BWN_READ_4(mac, BWN_REV3PLUS_TSF_LOW); 6922 high = BWN_READ_4(mac, BWN_REV3PLUS_TSF_HIGH); 6923 *tsf = high; 6924 *tsf <<= 32; 6925 *tsf |= low; 6926 } 6927 6928 static int 6929 bwn_dma_attach(struct bwn_mac *mac) 6930 { 6931 struct bwn_dma *dma = &mac->mac_method.dma; 6932 struct bwn_softc *sc = mac->mac_sc; 6933 bus_addr_t lowaddr = 0; 6934 int error; 6935 6936 if (siba_get_type(sc->sc_dev) == SIBA_TYPE_PCMCIA || bwn_usedma == 0) 6937 return (0); 6938 6939 KASSERT(siba_get_revid(sc->sc_dev) >= 5, ("%s: fail", __func__)); 6940 6941 mac->mac_flags |= BWN_MAC_FLAG_DMA; 6942 6943 dma->dmatype = bwn_dma_gettype(mac); 6944 if (dma->dmatype == BWN_DMA_30BIT) 6945 lowaddr = BWN_BUS_SPACE_MAXADDR_30BIT; 6946 else if (dma->dmatype == BWN_DMA_32BIT) 6947 lowaddr = BUS_SPACE_MAXADDR_32BIT; 6948 else 6949 lowaddr = BUS_SPACE_MAXADDR; 6950 6951 /* 6952 * Create top level DMA tag 6953 */ 6954 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), /* parent */ 6955 BWN_ALIGN, 0, /* alignment, bounds */ 6956 lowaddr, /* lowaddr */ 6957 BUS_SPACE_MAXADDR, /* highaddr */ 6958 NULL, NULL, /* filter, filterarg */ 6959 BUS_SPACE_MAXSIZE, /* maxsize */ 6960 BUS_SPACE_UNRESTRICTED, /* nsegments */ 6961 BUS_SPACE_MAXSIZE, /* maxsegsize */ 6962 0, /* flags */ 6963 NULL, NULL, /* lockfunc, lockarg */ 6964 &dma->parent_dtag); 6965 if (error) { 6966 device_printf(sc->sc_dev, "can't create parent DMA tag\n"); 6967 return (error); 6968 } 6969 6970 /* 6971 * Create TX/RX mbuf DMA tag 6972 */ 6973 error = bus_dma_tag_create(dma->parent_dtag, 6974 1, 6975 0, 6976 BUS_SPACE_MAXADDR, 6977 BUS_SPACE_MAXADDR, 6978 NULL, NULL, 6979 MCLBYTES, 6980 1, 6981 BUS_SPACE_MAXSIZE_32BIT, 6982 0, 6983 NULL, NULL, 6984 &dma->rxbuf_dtag); 6985 if (error) { 6986 device_printf(sc->sc_dev, "can't create mbuf DMA tag\n"); 6987 goto fail0; 6988 } 6989 error = bus_dma_tag_create(dma->parent_dtag, 6990 1, 6991 0, 6992 BUS_SPACE_MAXADDR, 6993 BUS_SPACE_MAXADDR, 6994 NULL, NULL, 6995 MCLBYTES, 6996 1, 6997 BUS_SPACE_MAXSIZE_32BIT, 6998 0, 6999 NULL, NULL, 7000 &dma->txbuf_dtag); 7001 if (error) { 7002 device_printf(sc->sc_dev, "can't create mbuf DMA tag\n"); 7003 goto fail1; 7004 } 7005 7006 dma->wme[WME_AC_BK] = bwn_dma_ringsetup(mac, 0, 1, dma->dmatype); 7007 if (!dma->wme[WME_AC_BK]) 7008 goto fail2; 7009 7010 dma->wme[WME_AC_BE] = bwn_dma_ringsetup(mac, 1, 1, dma->dmatype); 7011 if (!dma->wme[WME_AC_BE]) 7012 goto fail3; 7013 7014 dma->wme[WME_AC_VI] = bwn_dma_ringsetup(mac, 2, 1, dma->dmatype); 7015 if (!dma->wme[WME_AC_VI]) 7016 goto fail4; 7017 7018 dma->wme[WME_AC_VO] = bwn_dma_ringsetup(mac, 3, 1, dma->dmatype); 7019 if (!dma->wme[WME_AC_VO]) 7020 goto fail5; 7021 7022 dma->mcast = bwn_dma_ringsetup(mac, 4, 1, dma->dmatype); 7023 if (!dma->mcast) 7024 goto fail6; 7025 dma->rx = bwn_dma_ringsetup(mac, 0, 0, dma->dmatype); 7026 if (!dma->rx) 7027 goto fail7; 7028 7029 return (error); 7030 7031 fail7: bwn_dma_ringfree(&dma->mcast); 7032 fail6: bwn_dma_ringfree(&dma->wme[WME_AC_VO]); 7033 fail5: bwn_dma_ringfree(&dma->wme[WME_AC_VI]); 7034 fail4: bwn_dma_ringfree(&dma->wme[WME_AC_BE]); 7035 fail3: bwn_dma_ringfree(&dma->wme[WME_AC_BK]); 7036 fail2: bus_dma_tag_destroy(dma->txbuf_dtag); 7037 fail1: bus_dma_tag_destroy(dma->rxbuf_dtag); 7038 fail0: bus_dma_tag_destroy(dma->parent_dtag); 7039 return (error); 7040 } 7041 7042 static struct bwn_dma_ring * 7043 bwn_dma_parse_cookie(struct bwn_mac *mac, const struct bwn_txstatus *status, 7044 uint16_t cookie, int *slot) 7045 { 7046 struct bwn_dma *dma = &mac->mac_method.dma; 7047 struct bwn_dma_ring *dr; 7048 struct bwn_softc *sc = mac->mac_sc; 7049 7050 BWN_ASSERT_LOCKED(mac->mac_sc); 7051 7052 switch (cookie & 0xf000) { 7053 case 0x1000: 7054 dr = dma->wme[WME_AC_BK]; 7055 break; 7056 case 0x2000: 7057 dr = dma->wme[WME_AC_BE]; 7058 break; 7059 case 0x3000: 7060 dr = dma->wme[WME_AC_VI]; 7061 break; 7062 case 0x4000: 7063 dr = dma->wme[WME_AC_VO]; 7064 break; 7065 case 0x5000: 7066 dr = dma->mcast; 7067 break; 7068 default: 7069 dr = NULL; 7070 KASSERT(0 == 1, 7071 ("invalid cookie value %d", cookie & 0xf000)); 7072 } 7073 *slot = (cookie & 0x0fff); 7074 if (*slot < 0 || *slot >= dr->dr_numslots) { 7075 /* 7076 * XXX FIXME: sometimes H/W returns TX DONE events duplicately 7077 * that it occurs events which have same H/W sequence numbers. 7078 * When it's occurred just prints a WARNING msgs and ignores. 7079 */ 7080 KASSERT(status->seq == dma->lastseq, 7081 ("%s:%d: fail", __func__, __LINE__)); 7082 device_printf(sc->sc_dev, 7083 "out of slot ranges (0 < %d < %d)\n", *slot, 7084 dr->dr_numslots); 7085 return (NULL); 7086 } 7087 dma->lastseq = status->seq; 7088 return (dr); 7089 } 7090 7091 static void 7092 bwn_dma_stop(struct bwn_mac *mac) 7093 { 7094 struct bwn_dma *dma; 7095 7096 if ((mac->mac_flags & BWN_MAC_FLAG_DMA) == 0) 7097 return; 7098 dma = &mac->mac_method.dma; 7099 7100 bwn_dma_ringstop(&dma->rx); 7101 bwn_dma_ringstop(&dma->wme[WME_AC_BK]); 7102 bwn_dma_ringstop(&dma->wme[WME_AC_BE]); 7103 bwn_dma_ringstop(&dma->wme[WME_AC_VI]); 7104 bwn_dma_ringstop(&dma->wme[WME_AC_VO]); 7105 bwn_dma_ringstop(&dma->mcast); 7106 } 7107 7108 static void 7109 bwn_dma_ringstop(struct bwn_dma_ring **dr) 7110 { 7111 7112 if (dr == NULL) 7113 return; 7114 7115 bwn_dma_cleanup(*dr); 7116 } 7117 7118 static void 7119 bwn_pio_stop(struct bwn_mac *mac) 7120 { 7121 struct bwn_pio *pio; 7122 7123 if (mac->mac_flags & BWN_MAC_FLAG_DMA) 7124 return; 7125 pio = &mac->mac_method.pio; 7126 7127 bwn_destroy_queue_tx(&pio->mcast); 7128 bwn_destroy_queue_tx(&pio->wme[WME_AC_VO]); 7129 bwn_destroy_queue_tx(&pio->wme[WME_AC_VI]); 7130 bwn_destroy_queue_tx(&pio->wme[WME_AC_BE]); 7131 bwn_destroy_queue_tx(&pio->wme[WME_AC_BK]); 7132 } 7133 7134 static void 7135 bwn_led_attach(struct bwn_mac *mac) 7136 { 7137 struct bwn_softc *sc = mac->mac_sc; 7138 const uint8_t *led_act = NULL; 7139 uint16_t val[BWN_LED_MAX]; 7140 int i; 7141 7142 sc->sc_led_idle = (2350 * hz) / 1000; 7143 sc->sc_led_blink = 1; 7144 7145 for (i = 0; i < N(bwn_vendor_led_act); ++i) { 7146 if (siba_get_pci_subvendor(sc->sc_dev) == 7147 bwn_vendor_led_act[i].vid) { 7148 led_act = bwn_vendor_led_act[i].led_act; 7149 break; 7150 } 7151 } 7152 if (led_act == NULL) 7153 led_act = bwn_default_led_act; 7154 7155 val[0] = siba_sprom_get_gpio0(sc->sc_dev); 7156 val[1] = siba_sprom_get_gpio1(sc->sc_dev); 7157 val[2] = siba_sprom_get_gpio2(sc->sc_dev); 7158 val[3] = siba_sprom_get_gpio3(sc->sc_dev); 7159 7160 for (i = 0; i < BWN_LED_MAX; ++i) { 7161 struct bwn_led *led = &sc->sc_leds[i]; 7162 7163 if (val[i] == 0xff) { 7164 led->led_act = led_act[i]; 7165 } else { 7166 if (val[i] & BWN_LED_ACT_LOW) 7167 led->led_flags |= BWN_LED_F_ACTLOW; 7168 led->led_act = val[i] & BWN_LED_ACT_MASK; 7169 } 7170 led->led_mask = (1 << i); 7171 7172 if (led->led_act == BWN_LED_ACT_BLINK_SLOW || 7173 led->led_act == BWN_LED_ACT_BLINK_POLL || 7174 led->led_act == BWN_LED_ACT_BLINK) { 7175 led->led_flags |= BWN_LED_F_BLINK; 7176 if (led->led_act == BWN_LED_ACT_BLINK_POLL) 7177 led->led_flags |= BWN_LED_F_POLLABLE; 7178 else if (led->led_act == BWN_LED_ACT_BLINK_SLOW) 7179 led->led_flags |= BWN_LED_F_SLOW; 7180 7181 if (sc->sc_blink_led == NULL) { 7182 sc->sc_blink_led = led; 7183 if (led->led_flags & BWN_LED_F_SLOW) 7184 BWN_LED_SLOWDOWN(sc->sc_led_idle); 7185 } 7186 } 7187 7188 DPRINTF(sc, BWN_DEBUG_LED, 7189 "%dth led, act %d, lowact %d\n", i, 7190 led->led_act, led->led_flags & BWN_LED_F_ACTLOW); 7191 } 7192 callout_init_mtx(&sc->sc_led_blink_ch, &sc->sc_mtx, 0); 7193 } 7194 7195 static __inline uint16_t 7196 bwn_led_onoff(const struct bwn_led *led, uint16_t val, int on) 7197 { 7198 7199 if (led->led_flags & BWN_LED_F_ACTLOW) 7200 on = !on; 7201 if (on) 7202 val |= led->led_mask; 7203 else 7204 val &= ~led->led_mask; 7205 return val; 7206 } 7207 7208 static void 7209 bwn_led_newstate(struct bwn_mac *mac, enum ieee80211_state nstate) 7210 { 7211 struct bwn_softc *sc = mac->mac_sc; 7212 struct ieee80211com *ic = &sc->sc_ic; 7213 uint16_t val; 7214 int i; 7215 7216 if (nstate == IEEE80211_S_INIT) { 7217 callout_stop(&sc->sc_led_blink_ch); 7218 sc->sc_led_blinking = 0; 7219 } 7220 7221 if ((sc->sc_flags & BWN_FLAG_RUNNING) == 0) 7222 return; 7223 7224 val = BWN_READ_2(mac, BWN_GPIO_CONTROL); 7225 for (i = 0; i < BWN_LED_MAX; ++i) { 7226 struct bwn_led *led = &sc->sc_leds[i]; 7227 int on; 7228 7229 if (led->led_act == BWN_LED_ACT_UNKN || 7230 led->led_act == BWN_LED_ACT_NULL) 7231 continue; 7232 7233 if ((led->led_flags & BWN_LED_F_BLINK) && 7234 nstate != IEEE80211_S_INIT) 7235 continue; 7236 7237 switch (led->led_act) { 7238 case BWN_LED_ACT_ON: /* Always on */ 7239 on = 1; 7240 break; 7241 case BWN_LED_ACT_OFF: /* Always off */ 7242 case BWN_LED_ACT_5GHZ: /* TODO: 11A */ 7243 on = 0; 7244 break; 7245 default: 7246 on = 1; 7247 switch (nstate) { 7248 case IEEE80211_S_INIT: 7249 on = 0; 7250 break; 7251 case IEEE80211_S_RUN: 7252 if (led->led_act == BWN_LED_ACT_11G && 7253 ic->ic_curmode != IEEE80211_MODE_11G) 7254 on = 0; 7255 break; 7256 default: 7257 if (led->led_act == BWN_LED_ACT_ASSOC) 7258 on = 0; 7259 break; 7260 } 7261 break; 7262 } 7263 7264 val = bwn_led_onoff(led, val, on); 7265 } 7266 BWN_WRITE_2(mac, BWN_GPIO_CONTROL, val); 7267 } 7268 7269 static void 7270 bwn_led_event(struct bwn_mac *mac, int event) 7271 { 7272 struct bwn_softc *sc = mac->mac_sc; 7273 struct bwn_led *led = sc->sc_blink_led; 7274 int rate; 7275 7276 if (event == BWN_LED_EVENT_POLL) { 7277 if ((led->led_flags & BWN_LED_F_POLLABLE) == 0) 7278 return; 7279 if (ticks - sc->sc_led_ticks < sc->sc_led_idle) 7280 return; 7281 } 7282 7283 sc->sc_led_ticks = ticks; 7284 if (sc->sc_led_blinking) 7285 return; 7286 7287 switch (event) { 7288 case BWN_LED_EVENT_RX: 7289 rate = sc->sc_rx_rate; 7290 break; 7291 case BWN_LED_EVENT_TX: 7292 rate = sc->sc_tx_rate; 7293 break; 7294 case BWN_LED_EVENT_POLL: 7295 rate = 0; 7296 break; 7297 default: 7298 panic("unknown LED event %d\n", event); 7299 break; 7300 } 7301 bwn_led_blink_start(mac, bwn_led_duration[rate].on_dur, 7302 bwn_led_duration[rate].off_dur); 7303 } 7304 7305 static void 7306 bwn_led_blink_start(struct bwn_mac *mac, int on_dur, int off_dur) 7307 { 7308 struct bwn_softc *sc = mac->mac_sc; 7309 struct bwn_led *led = sc->sc_blink_led; 7310 uint16_t val; 7311 7312 val = BWN_READ_2(mac, BWN_GPIO_CONTROL); 7313 val = bwn_led_onoff(led, val, 1); 7314 BWN_WRITE_2(mac, BWN_GPIO_CONTROL, val); 7315 7316 if (led->led_flags & BWN_LED_F_SLOW) { 7317 BWN_LED_SLOWDOWN(on_dur); 7318 BWN_LED_SLOWDOWN(off_dur); 7319 } 7320 7321 sc->sc_led_blinking = 1; 7322 sc->sc_led_blink_offdur = off_dur; 7323 7324 callout_reset(&sc->sc_led_blink_ch, on_dur, bwn_led_blink_next, mac); 7325 } 7326 7327 static void 7328 bwn_led_blink_next(void *arg) 7329 { 7330 struct bwn_mac *mac = arg; 7331 struct bwn_softc *sc = mac->mac_sc; 7332 uint16_t val; 7333 7334 val = BWN_READ_2(mac, BWN_GPIO_CONTROL); 7335 val = bwn_led_onoff(sc->sc_blink_led, val, 0); 7336 BWN_WRITE_2(mac, BWN_GPIO_CONTROL, val); 7337 7338 callout_reset(&sc->sc_led_blink_ch, sc->sc_led_blink_offdur, 7339 bwn_led_blink_end, mac); 7340 } 7341 7342 static void 7343 bwn_led_blink_end(void *arg) 7344 { 7345 struct bwn_mac *mac = arg; 7346 struct bwn_softc *sc = mac->mac_sc; 7347 7348 sc->sc_led_blinking = 0; 7349 } 7350 7351 static int 7352 bwn_suspend(device_t dev) 7353 { 7354 struct bwn_softc *sc = device_get_softc(dev); 7355 7356 BWN_LOCK(sc); 7357 bwn_stop(sc); 7358 BWN_UNLOCK(sc); 7359 return (0); 7360 } 7361 7362 static int 7363 bwn_resume(device_t dev) 7364 { 7365 struct bwn_softc *sc = device_get_softc(dev); 7366 int error = EDOOFUS; 7367 7368 BWN_LOCK(sc); 7369 if (sc->sc_ic.ic_nrunning > 0) 7370 error = bwn_init(sc); 7371 BWN_UNLOCK(sc); 7372 if (error == 0) 7373 ieee80211_start_all(&sc->sc_ic); 7374 return (0); 7375 } 7376 7377 static void 7378 bwn_rfswitch(void *arg) 7379 { 7380 struct bwn_softc *sc = arg; 7381 struct bwn_mac *mac = sc->sc_curmac; 7382 int cur = 0, prev = 0; 7383 7384 KASSERT(mac->mac_status >= BWN_MAC_STATUS_STARTED, 7385 ("%s: invalid MAC status %d", __func__, mac->mac_status)); 7386 7387 if (mac->mac_phy.rev >= 3 || mac->mac_phy.type == BWN_PHYTYPE_LP 7388 || mac->mac_phy.type == BWN_PHYTYPE_N) { 7389 if (!(BWN_READ_4(mac, BWN_RF_HWENABLED_HI) 7390 & BWN_RF_HWENABLED_HI_MASK)) 7391 cur = 1; 7392 } else { 7393 if (BWN_READ_2(mac, BWN_RF_HWENABLED_LO) 7394 & BWN_RF_HWENABLED_LO_MASK) 7395 cur = 1; 7396 } 7397 7398 if (mac->mac_flags & BWN_MAC_FLAG_RADIO_ON) 7399 prev = 1; 7400 7401 DPRINTF(sc, BWN_DEBUG_RESET, "%s: called; cur=%d, prev=%d\n", 7402 __func__, cur, prev); 7403 7404 if (cur != prev) { 7405 if (cur) 7406 mac->mac_flags |= BWN_MAC_FLAG_RADIO_ON; 7407 else 7408 mac->mac_flags &= ~BWN_MAC_FLAG_RADIO_ON; 7409 7410 device_printf(sc->sc_dev, 7411 "status of RF switch is changed to %s\n", 7412 cur ? "ON" : "OFF"); 7413 if (cur != mac->mac_phy.rf_on) { 7414 if (cur) 7415 bwn_rf_turnon(mac); 7416 else 7417 bwn_rf_turnoff(mac); 7418 } 7419 } 7420 7421 callout_schedule(&sc->sc_rfswitch_ch, hz); 7422 } 7423 7424 static void 7425 bwn_sysctl_node(struct bwn_softc *sc) 7426 { 7427 device_t dev = sc->sc_dev; 7428 struct bwn_mac *mac; 7429 struct bwn_stats *stats; 7430 7431 /* XXX assume that count of MAC is only 1. */ 7432 7433 if ((mac = sc->sc_curmac) == NULL) 7434 return; 7435 stats = &mac->mac_stats; 7436 7437 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 7438 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 7439 "linknoise", CTLFLAG_RW, &stats->rts, 0, "Noise level"); 7440 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 7441 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 7442 "rts", CTLFLAG_RW, &stats->rts, 0, "RTS"); 7443 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 7444 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 7445 "rtsfail", CTLFLAG_RW, &stats->rtsfail, 0, "RTS failed to send"); 7446 7447 #ifdef BWN_DEBUG 7448 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), 7449 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 7450 "debug", CTLFLAG_RW, &sc->sc_debug, 0, "Debug flags"); 7451 #endif 7452 } 7453 7454 static device_method_t bwn_methods[] = { 7455 /* Device interface */ 7456 DEVMETHOD(device_probe, bwn_probe), 7457 DEVMETHOD(device_attach, bwn_attach), 7458 DEVMETHOD(device_detach, bwn_detach), 7459 DEVMETHOD(device_suspend, bwn_suspend), 7460 DEVMETHOD(device_resume, bwn_resume), 7461 DEVMETHOD_END 7462 }; 7463 static driver_t bwn_driver = { 7464 "bwn", 7465 bwn_methods, 7466 sizeof(struct bwn_softc) 7467 }; 7468 static devclass_t bwn_devclass; 7469 DRIVER_MODULE(bwn, siba_bwn, bwn_driver, bwn_devclass, 0, 0); 7470 MODULE_DEPEND(bwn, siba_bwn, 1, 1, 1); 7471 MODULE_DEPEND(bwn, wlan, 1, 1, 1); /* 802.11 media layer */ 7472 MODULE_DEPEND(bwn, firmware, 1, 1, 1); /* firmware support */ 7473 MODULE_DEPEND(bwn, wlan_amrr, 1, 1, 1); 7474 MODULE_VERSION(bwn, 1); 7475