1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2009-2010 Weongyo Jeong <weongyo@freebsd.org> 5 * Copyright (c) 2016 Landon Fuller <landonf@FreeBSD.org> 6 * Copyright (c) 2017 The FreeBSD Foundation 7 * All rights reserved. 8 * 9 * Portions of this software were developed by Landon Fuller 10 * under sponsorship from the FreeBSD Foundation. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer, 17 * without modification. 18 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 19 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 20 * redistribution must be conditioned upon including a substantially 21 * similar Disclaimer requirement for further binary redistribution. 22 * 23 * NO WARRANTY 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 27 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 28 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 29 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 32 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 34 * THE POSSIBILITY OF SUCH DAMAGES. 35 */ 36 37 #include <sys/cdefs.h> 38 __FBSDID("$FreeBSD$"); 39 40 /* 41 * The Broadcom Wireless LAN controller driver. 42 */ 43 44 #include "opt_bwn.h" 45 #include "opt_wlan.h" 46 47 #include <sys/param.h> 48 #include <sys/systm.h> 49 #include <sys/kernel.h> 50 #include <sys/gpio.h> 51 #include <sys/malloc.h> 52 #include <sys/module.h> 53 #include <sys/endian.h> 54 #include <sys/errno.h> 55 #include <sys/firmware.h> 56 #include <sys/lock.h> 57 #include <sys/mutex.h> 58 #include <machine/bus.h> 59 #include <machine/resource.h> 60 #include <sys/bus.h> 61 #include <sys/rman.h> 62 #include <sys/socket.h> 63 #include <sys/sockio.h> 64 65 #include <net/ethernet.h> 66 #include <net/if.h> 67 #include <net/if_var.h> 68 #include <net/if_arp.h> 69 #include <net/if_dl.h> 70 #include <net/if_llc.h> 71 #include <net/if_media.h> 72 #include <net/if_types.h> 73 74 #include <net80211/ieee80211_var.h> 75 #include <net80211/ieee80211_radiotap.h> 76 #include <net80211/ieee80211_regdomain.h> 77 #include <net80211/ieee80211_phy.h> 78 #include <net80211/ieee80211_ratectl.h> 79 80 #include <dev/bhnd/bhnd.h> 81 #include <dev/bhnd/bhnd_ids.h> 82 83 #include <dev/bhnd/cores/chipc/chipc.h> 84 #include <dev/bhnd/cores/pmu/bhnd_pmu.h> 85 86 #include <dev/bwn/if_bwnreg.h> 87 #include <dev/bwn/if_bwnvar.h> 88 89 #include <dev/bwn/if_bwn_debug.h> 90 #include <dev/bwn/if_bwn_misc.h> 91 #include <dev/bwn/if_bwn_util.h> 92 #include <dev/bwn/if_bwn_phy_common.h> 93 #include <dev/bwn/if_bwn_phy_g.h> 94 #include <dev/bwn/if_bwn_phy_lp.h> 95 #include <dev/bwn/if_bwn_phy_n.h> 96 97 #include "bhnd_nvram_map.h" 98 99 #include "gpio_if.h" 100 101 static SYSCTL_NODE(_hw, OID_AUTO, bwn, CTLFLAG_RD | CTLFLAG_MPSAFE, 0, 102 "Broadcom driver parameters"); 103 104 /* 105 * Tunable & sysctl variables. 106 */ 107 108 #ifdef BWN_DEBUG 109 static int bwn_debug = 0; 110 SYSCTL_INT(_hw_bwn, OID_AUTO, debug, CTLFLAG_RWTUN, &bwn_debug, 0, 111 "Broadcom debugging printfs"); 112 #endif 113 114 static int bwn_bfp = 0; /* use "Bad Frames Preemption" */ 115 SYSCTL_INT(_hw_bwn, OID_AUTO, bfp, CTLFLAG_RW, &bwn_bfp, 0, 116 "uses Bad Frames Preemption"); 117 static int bwn_bluetooth = 1; 118 SYSCTL_INT(_hw_bwn, OID_AUTO, bluetooth, CTLFLAG_RW, &bwn_bluetooth, 0, 119 "turns on Bluetooth Coexistence"); 120 static int bwn_hwpctl = 0; 121 SYSCTL_INT(_hw_bwn, OID_AUTO, hwpctl, CTLFLAG_RW, &bwn_hwpctl, 0, 122 "uses H/W power control"); 123 static int bwn_usedma = 1; 124 SYSCTL_INT(_hw_bwn, OID_AUTO, usedma, CTLFLAG_RD, &bwn_usedma, 0, 125 "uses DMA"); 126 TUNABLE_INT("hw.bwn.usedma", &bwn_usedma); 127 static int bwn_wme = 1; 128 SYSCTL_INT(_hw_bwn, OID_AUTO, wme, CTLFLAG_RW, &bwn_wme, 0, 129 "uses WME support"); 130 131 static void bwn_attach_pre(struct bwn_softc *); 132 static int bwn_attach_post(struct bwn_softc *); 133 static int bwn_retain_bus_providers(struct bwn_softc *sc); 134 static void bwn_release_bus_providers(struct bwn_softc *sc); 135 static void bwn_sprom_bugfixes(device_t); 136 static int bwn_init(struct bwn_softc *); 137 static void bwn_parent(struct ieee80211com *); 138 static void bwn_start(struct bwn_softc *); 139 static int bwn_transmit(struct ieee80211com *, struct mbuf *); 140 static int bwn_attach_core(struct bwn_mac *); 141 static int bwn_phy_getinfo(struct bwn_mac *, int); 142 static int bwn_chiptest(struct bwn_mac *); 143 static int bwn_setup_channels(struct bwn_mac *, int, int); 144 static void bwn_shm_ctlword(struct bwn_mac *, uint16_t, 145 uint16_t); 146 static void bwn_addchannels(struct ieee80211_channel [], int, int *, 147 const struct bwn_channelinfo *, const uint8_t []); 148 static int bwn_raw_xmit(struct ieee80211_node *, struct mbuf *, 149 const struct ieee80211_bpf_params *); 150 static void bwn_updateslot(struct ieee80211com *); 151 static void bwn_update_promisc(struct ieee80211com *); 152 static void bwn_wme_init(struct bwn_mac *); 153 static int bwn_wme_update(struct ieee80211com *); 154 static void bwn_wme_clear(struct bwn_softc *); 155 static void bwn_wme_load(struct bwn_mac *); 156 static void bwn_wme_loadparams(struct bwn_mac *, 157 const struct wmeParams *, uint16_t); 158 static void bwn_scan_start(struct ieee80211com *); 159 static void bwn_scan_end(struct ieee80211com *); 160 static void bwn_set_channel(struct ieee80211com *); 161 static struct ieee80211vap *bwn_vap_create(struct ieee80211com *, 162 const char [IFNAMSIZ], int, enum ieee80211_opmode, int, 163 const uint8_t [IEEE80211_ADDR_LEN], 164 const uint8_t [IEEE80211_ADDR_LEN]); 165 static void bwn_vap_delete(struct ieee80211vap *); 166 static void bwn_stop(struct bwn_softc *); 167 static int bwn_core_forceclk(struct bwn_mac *, bool); 168 static int bwn_core_init(struct bwn_mac *); 169 static void bwn_core_start(struct bwn_mac *); 170 static void bwn_core_exit(struct bwn_mac *); 171 static void bwn_bt_disable(struct bwn_mac *); 172 static int bwn_chip_init(struct bwn_mac *); 173 static void bwn_set_txretry(struct bwn_mac *, int, int); 174 static void bwn_rate_init(struct bwn_mac *); 175 static void bwn_set_phytxctl(struct bwn_mac *); 176 static void bwn_spu_setdelay(struct bwn_mac *, int); 177 static void bwn_bt_enable(struct bwn_mac *); 178 static void bwn_set_macaddr(struct bwn_mac *); 179 static void bwn_crypt_init(struct bwn_mac *); 180 static void bwn_chip_exit(struct bwn_mac *); 181 static int bwn_fw_fillinfo(struct bwn_mac *); 182 static int bwn_fw_loaducode(struct bwn_mac *); 183 static int bwn_gpio_init(struct bwn_mac *); 184 static int bwn_fw_loadinitvals(struct bwn_mac *); 185 static int bwn_phy_init(struct bwn_mac *); 186 static void bwn_set_txantenna(struct bwn_mac *, int); 187 static void bwn_set_opmode(struct bwn_mac *); 188 static void bwn_rate_write(struct bwn_mac *, uint16_t, int); 189 static uint8_t bwn_plcp_getcck(const uint8_t); 190 static uint8_t bwn_plcp_getofdm(const uint8_t); 191 static void bwn_pio_init(struct bwn_mac *); 192 static uint16_t bwn_pio_idx2base(struct bwn_mac *, int); 193 static void bwn_pio_set_txqueue(struct bwn_mac *, struct bwn_pio_txqueue *, 194 int); 195 static void bwn_pio_setupqueue_rx(struct bwn_mac *, 196 struct bwn_pio_rxqueue *, int); 197 static void bwn_destroy_queue_tx(struct bwn_pio_txqueue *); 198 static uint16_t bwn_pio_read_2(struct bwn_mac *, struct bwn_pio_txqueue *, 199 uint16_t); 200 static void bwn_pio_cancel_tx_packets(struct bwn_pio_txqueue *); 201 static int bwn_pio_rx(struct bwn_pio_rxqueue *); 202 static uint8_t bwn_pio_rxeof(struct bwn_pio_rxqueue *); 203 static void bwn_pio_handle_txeof(struct bwn_mac *, 204 const struct bwn_txstatus *); 205 static uint16_t bwn_pio_rx_read_2(struct bwn_pio_rxqueue *, uint16_t); 206 static uint32_t bwn_pio_rx_read_4(struct bwn_pio_rxqueue *, uint16_t); 207 static void bwn_pio_rx_write_2(struct bwn_pio_rxqueue *, uint16_t, 208 uint16_t); 209 static void bwn_pio_rx_write_4(struct bwn_pio_rxqueue *, uint16_t, 210 uint32_t); 211 static int bwn_pio_tx_start(struct bwn_mac *, struct ieee80211_node *, 212 struct mbuf **); 213 static struct bwn_pio_txqueue *bwn_pio_select(struct bwn_mac *, uint8_t); 214 static uint32_t bwn_pio_write_multi_4(struct bwn_mac *, 215 struct bwn_pio_txqueue *, uint32_t, const void *, int); 216 static void bwn_pio_write_4(struct bwn_mac *, struct bwn_pio_txqueue *, 217 uint16_t, uint32_t); 218 static uint16_t bwn_pio_write_multi_2(struct bwn_mac *, 219 struct bwn_pio_txqueue *, uint16_t, const void *, int); 220 static uint16_t bwn_pio_write_mbuf_2(struct bwn_mac *, 221 struct bwn_pio_txqueue *, uint16_t, struct mbuf *); 222 static struct bwn_pio_txqueue *bwn_pio_parse_cookie(struct bwn_mac *, 223 uint16_t, struct bwn_pio_txpkt **); 224 static void bwn_dma_init(struct bwn_mac *); 225 static void bwn_dma_rxdirectfifo(struct bwn_mac *, int, uint8_t); 226 static uint16_t bwn_dma_base(int, int); 227 static void bwn_dma_ringfree(struct bwn_dma_ring **); 228 static void bwn_dma_32_getdesc(struct bwn_dma_ring *, 229 int, struct bwn_dmadesc_generic **, 230 struct bwn_dmadesc_meta **); 231 static void bwn_dma_32_setdesc(struct bwn_dma_ring *, 232 struct bwn_dmadesc_generic *, bus_addr_t, uint16_t, int, 233 int, int); 234 static void bwn_dma_32_start_transfer(struct bwn_dma_ring *, int); 235 static void bwn_dma_32_suspend(struct bwn_dma_ring *); 236 static void bwn_dma_32_resume(struct bwn_dma_ring *); 237 static int bwn_dma_32_get_curslot(struct bwn_dma_ring *); 238 static void bwn_dma_32_set_curslot(struct bwn_dma_ring *, int); 239 static void bwn_dma_64_getdesc(struct bwn_dma_ring *, 240 int, struct bwn_dmadesc_generic **, 241 struct bwn_dmadesc_meta **); 242 static void bwn_dma_64_setdesc(struct bwn_dma_ring *, 243 struct bwn_dmadesc_generic *, bus_addr_t, uint16_t, int, 244 int, int); 245 static void bwn_dma_64_start_transfer(struct bwn_dma_ring *, int); 246 static void bwn_dma_64_suspend(struct bwn_dma_ring *); 247 static void bwn_dma_64_resume(struct bwn_dma_ring *); 248 static int bwn_dma_64_get_curslot(struct bwn_dma_ring *); 249 static void bwn_dma_64_set_curslot(struct bwn_dma_ring *, int); 250 static int bwn_dma_allocringmemory(struct bwn_dma_ring *); 251 static void bwn_dma_setup(struct bwn_dma_ring *); 252 static void bwn_dma_free_ringmemory(struct bwn_dma_ring *); 253 static void bwn_dma_cleanup(struct bwn_dma_ring *); 254 static void bwn_dma_free_descbufs(struct bwn_dma_ring *); 255 static int bwn_dma_tx_reset(struct bwn_mac *, uint16_t, int); 256 static void bwn_dma_rx(struct bwn_dma_ring *); 257 static int bwn_dma_rx_reset(struct bwn_mac *, uint16_t, int); 258 static void bwn_dma_free_descbuf(struct bwn_dma_ring *, 259 struct bwn_dmadesc_meta *); 260 static void bwn_dma_set_redzone(struct bwn_dma_ring *, struct mbuf *); 261 static void bwn_dma_ring_addr(void *, bus_dma_segment_t *, int, int); 262 static int bwn_dma_freeslot(struct bwn_dma_ring *); 263 static int bwn_dma_nextslot(struct bwn_dma_ring *, int); 264 static void bwn_dma_rxeof(struct bwn_dma_ring *, int *); 265 static int bwn_dma_newbuf(struct bwn_dma_ring *, 266 struct bwn_dmadesc_generic *, struct bwn_dmadesc_meta *, 267 int); 268 static void bwn_dma_buf_addr(void *, bus_dma_segment_t *, int, 269 bus_size_t, int); 270 static uint8_t bwn_dma_check_redzone(struct bwn_dma_ring *, struct mbuf *); 271 static void bwn_ratectl_tx_complete(const struct ieee80211_node *, 272 const struct bwn_txstatus *); 273 static void bwn_dma_handle_txeof(struct bwn_mac *, 274 const struct bwn_txstatus *); 275 static int bwn_dma_tx_start(struct bwn_mac *, struct ieee80211_node *, 276 struct mbuf **); 277 static int bwn_dma_getslot(struct bwn_dma_ring *); 278 static struct bwn_dma_ring *bwn_dma_select(struct bwn_mac *, 279 uint8_t); 280 static int bwn_dma_attach(struct bwn_mac *); 281 static struct bwn_dma_ring *bwn_dma_ringsetup(struct bwn_mac *, 282 int, int); 283 static struct bwn_dma_ring *bwn_dma_parse_cookie(struct bwn_mac *, 284 const struct bwn_txstatus *, uint16_t, int *); 285 static void bwn_dma_free(struct bwn_mac *); 286 static int bwn_fw_gets(struct bwn_mac *, enum bwn_fwtype); 287 static int bwn_fw_get(struct bwn_mac *, enum bwn_fwtype, 288 const char *, struct bwn_fwfile *); 289 static void bwn_release_firmware(struct bwn_mac *); 290 static void bwn_do_release_fw(struct bwn_fwfile *); 291 static uint16_t bwn_fwcaps_read(struct bwn_mac *); 292 static int bwn_fwinitvals_write(struct bwn_mac *, 293 const struct bwn_fwinitvals *, size_t, size_t); 294 static uint16_t bwn_ant2phy(int); 295 static void bwn_mac_write_bssid(struct bwn_mac *); 296 static void bwn_mac_setfilter(struct bwn_mac *, uint16_t, 297 const uint8_t *); 298 static void bwn_key_dowrite(struct bwn_mac *, uint8_t, uint8_t, 299 const uint8_t *, size_t, const uint8_t *); 300 static void bwn_key_macwrite(struct bwn_mac *, uint8_t, 301 const uint8_t *); 302 static void bwn_key_write(struct bwn_mac *, uint8_t, uint8_t, 303 const uint8_t *); 304 static void bwn_phy_exit(struct bwn_mac *); 305 static void bwn_core_stop(struct bwn_mac *); 306 static int bwn_switch_band(struct bwn_softc *, 307 struct ieee80211_channel *); 308 static int bwn_phy_reset(struct bwn_mac *); 309 static int bwn_newstate(struct ieee80211vap *, enum ieee80211_state, int); 310 static void bwn_set_pretbtt(struct bwn_mac *); 311 static int bwn_intr(void *); 312 static void bwn_intrtask(void *, int); 313 static void bwn_restart(struct bwn_mac *, const char *); 314 static void bwn_intr_ucode_debug(struct bwn_mac *); 315 static void bwn_intr_tbtt_indication(struct bwn_mac *); 316 static void bwn_intr_atim_end(struct bwn_mac *); 317 static void bwn_intr_beacon(struct bwn_mac *); 318 static void bwn_intr_pmq(struct bwn_mac *); 319 static void bwn_intr_noise(struct bwn_mac *); 320 static void bwn_intr_txeof(struct bwn_mac *); 321 static void bwn_hwreset(void *, int); 322 static void bwn_handle_fwpanic(struct bwn_mac *); 323 static void bwn_load_beacon0(struct bwn_mac *); 324 static void bwn_load_beacon1(struct bwn_mac *); 325 static uint32_t bwn_jssi_read(struct bwn_mac *); 326 static void bwn_noise_gensample(struct bwn_mac *); 327 static void bwn_handle_txeof(struct bwn_mac *, 328 const struct bwn_txstatus *); 329 static void bwn_rxeof(struct bwn_mac *, struct mbuf *, const void *); 330 static void bwn_phy_txpower_check(struct bwn_mac *, uint32_t); 331 static int bwn_tx_start(struct bwn_softc *, struct ieee80211_node *, 332 struct mbuf *); 333 static int bwn_tx_isfull(struct bwn_softc *, struct mbuf *); 334 static int bwn_set_txhdr(struct bwn_mac *, 335 struct ieee80211_node *, struct mbuf *, struct bwn_txhdr *, 336 uint16_t); 337 static void bwn_plcp_genhdr(struct bwn_plcp4 *, const uint16_t, 338 const uint8_t); 339 static uint8_t bwn_antenna_sanitize(struct bwn_mac *, uint8_t); 340 static uint8_t bwn_get_fbrate(uint8_t); 341 static void bwn_txpwr(void *, int); 342 static void bwn_tasks(void *); 343 static void bwn_task_15s(struct bwn_mac *); 344 static void bwn_task_30s(struct bwn_mac *); 345 static void bwn_task_60s(struct bwn_mac *); 346 static int bwn_plcp_get_ofdmrate(struct bwn_mac *, struct bwn_plcp6 *, 347 uint8_t); 348 static int bwn_plcp_get_cckrate(struct bwn_mac *, struct bwn_plcp6 *); 349 static void bwn_rx_radiotap(struct bwn_mac *, struct mbuf *, 350 const struct bwn_rxhdr4 *, struct bwn_plcp6 *, int, 351 int, int); 352 static void bwn_tsf_read(struct bwn_mac *, uint64_t *); 353 static void bwn_set_slot_time(struct bwn_mac *, uint16_t); 354 static void bwn_watchdog(void *); 355 static void bwn_dma_stop(struct bwn_mac *); 356 static void bwn_pio_stop(struct bwn_mac *); 357 static void bwn_dma_ringstop(struct bwn_dma_ring **); 358 static int bwn_led_attach(struct bwn_mac *); 359 static void bwn_led_newstate(struct bwn_mac *, enum ieee80211_state); 360 static void bwn_led_event(struct bwn_mac *, int); 361 static void bwn_led_blink_start(struct bwn_mac *, int, int); 362 static void bwn_led_blink_next(void *); 363 static void bwn_led_blink_end(void *); 364 static void bwn_rfswitch(void *); 365 static void bwn_rf_turnon(struct bwn_mac *); 366 static void bwn_rf_turnoff(struct bwn_mac *); 367 static void bwn_sysctl_node(struct bwn_softc *); 368 369 static const struct bwn_channelinfo bwn_chantable_bg = { 370 .channels = { 371 { 2412, 1, 30 }, { 2417, 2, 30 }, { 2422, 3, 30 }, 372 { 2427, 4, 30 }, { 2432, 5, 30 }, { 2437, 6, 30 }, 373 { 2442, 7, 30 }, { 2447, 8, 30 }, { 2452, 9, 30 }, 374 { 2457, 10, 30 }, { 2462, 11, 30 }, { 2467, 12, 30 }, 375 { 2472, 13, 30 }, { 2484, 14, 30 } }, 376 .nchannels = 14 377 }; 378 379 static const struct bwn_channelinfo bwn_chantable_a = { 380 .channels = { 381 { 5170, 34, 30 }, { 5180, 36, 30 }, { 5190, 38, 30 }, 382 { 5200, 40, 30 }, { 5210, 42, 30 }, { 5220, 44, 30 }, 383 { 5230, 46, 30 }, { 5240, 48, 30 }, { 5260, 52, 30 }, 384 { 5280, 56, 30 }, { 5300, 60, 30 }, { 5320, 64, 30 }, 385 { 5500, 100, 30 }, { 5520, 104, 30 }, { 5540, 108, 30 }, 386 { 5560, 112, 30 }, { 5580, 116, 30 }, { 5600, 120, 30 }, 387 { 5620, 124, 30 }, { 5640, 128, 30 }, { 5660, 132, 30 }, 388 { 5680, 136, 30 }, { 5700, 140, 30 }, { 5745, 149, 30 }, 389 { 5765, 153, 30 }, { 5785, 157, 30 }, { 5805, 161, 30 }, 390 { 5825, 165, 30 }, { 5920, 184, 30 }, { 5940, 188, 30 }, 391 { 5960, 192, 30 }, { 5980, 196, 30 }, { 6000, 200, 30 }, 392 { 6020, 204, 30 }, { 6040, 208, 30 }, { 6060, 212, 30 }, 393 { 6080, 216, 30 } }, 394 .nchannels = 37 395 }; 396 397 #if 0 398 static const struct bwn_channelinfo bwn_chantable_n = { 399 .channels = { 400 { 5160, 32, 30 }, { 5170, 34, 30 }, { 5180, 36, 30 }, 401 { 5190, 38, 30 }, { 5200, 40, 30 }, { 5210, 42, 30 }, 402 { 5220, 44, 30 }, { 5230, 46, 30 }, { 5240, 48, 30 }, 403 { 5250, 50, 30 }, { 5260, 52, 30 }, { 5270, 54, 30 }, 404 { 5280, 56, 30 }, { 5290, 58, 30 }, { 5300, 60, 30 }, 405 { 5310, 62, 30 }, { 5320, 64, 30 }, { 5330, 66, 30 }, 406 { 5340, 68, 30 }, { 5350, 70, 30 }, { 5360, 72, 30 }, 407 { 5370, 74, 30 }, { 5380, 76, 30 }, { 5390, 78, 30 }, 408 { 5400, 80, 30 }, { 5410, 82, 30 }, { 5420, 84, 30 }, 409 { 5430, 86, 30 }, { 5440, 88, 30 }, { 5450, 90, 30 }, 410 { 5460, 92, 30 }, { 5470, 94, 30 }, { 5480, 96, 30 }, 411 { 5490, 98, 30 }, { 5500, 100, 30 }, { 5510, 102, 30 }, 412 { 5520, 104, 30 }, { 5530, 106, 30 }, { 5540, 108, 30 }, 413 { 5550, 110, 30 }, { 5560, 112, 30 }, { 5570, 114, 30 }, 414 { 5580, 116, 30 }, { 5590, 118, 30 }, { 5600, 120, 30 }, 415 { 5610, 122, 30 }, { 5620, 124, 30 }, { 5630, 126, 30 }, 416 { 5640, 128, 30 }, { 5650, 130, 30 }, { 5660, 132, 30 }, 417 { 5670, 134, 30 }, { 5680, 136, 30 }, { 5690, 138, 30 }, 418 { 5700, 140, 30 }, { 5710, 142, 30 }, { 5720, 144, 30 }, 419 { 5725, 145, 30 }, { 5730, 146, 30 }, { 5735, 147, 30 }, 420 { 5740, 148, 30 }, { 5745, 149, 30 }, { 5750, 150, 30 }, 421 { 5755, 151, 30 }, { 5760, 152, 30 }, { 5765, 153, 30 }, 422 { 5770, 154, 30 }, { 5775, 155, 30 }, { 5780, 156, 30 }, 423 { 5785, 157, 30 }, { 5790, 158, 30 }, { 5795, 159, 30 }, 424 { 5800, 160, 30 }, { 5805, 161, 30 }, { 5810, 162, 30 }, 425 { 5815, 163, 30 }, { 5820, 164, 30 }, { 5825, 165, 30 }, 426 { 5830, 166, 30 }, { 5840, 168, 30 }, { 5850, 170, 30 }, 427 { 5860, 172, 30 }, { 5870, 174, 30 }, { 5880, 176, 30 }, 428 { 5890, 178, 30 }, { 5900, 180, 30 }, { 5910, 182, 30 }, 429 { 5920, 184, 30 }, { 5930, 186, 30 }, { 5940, 188, 30 }, 430 { 5950, 190, 30 }, { 5960, 192, 30 }, { 5970, 194, 30 }, 431 { 5980, 196, 30 }, { 5990, 198, 30 }, { 6000, 200, 30 }, 432 { 6010, 202, 30 }, { 6020, 204, 30 }, { 6030, 206, 30 }, 433 { 6040, 208, 30 }, { 6050, 210, 30 }, { 6060, 212, 30 }, 434 { 6070, 214, 30 }, { 6080, 216, 30 }, { 6090, 218, 30 }, 435 { 6100, 220, 30 }, { 6110, 222, 30 }, { 6120, 224, 30 }, 436 { 6130, 226, 30 }, { 6140, 228, 30 } }, 437 .nchannels = 110 438 }; 439 #endif 440 441 #define VENDOR_LED_ACT(vendor) \ 442 { \ 443 .vid = PCI_VENDOR_##vendor, \ 444 .led_act = { BWN_VENDOR_LED_ACT_##vendor } \ 445 } 446 447 static const struct { 448 uint16_t vid; 449 uint8_t led_act[BWN_LED_MAX]; 450 } bwn_vendor_led_act[] = { 451 VENDOR_LED_ACT(HP_COMPAQ), 452 VENDOR_LED_ACT(ASUSTEK) 453 }; 454 455 static const uint8_t bwn_default_led_act[BWN_LED_MAX] = 456 { BWN_VENDOR_LED_ACT_DEFAULT }; 457 458 #undef VENDOR_LED_ACT 459 460 static const char *bwn_led_vars[] = { 461 BHND_NVAR_LEDBH0, 462 BHND_NVAR_LEDBH1, 463 BHND_NVAR_LEDBH2, 464 BHND_NVAR_LEDBH3 465 }; 466 467 static const struct { 468 int on_dur; 469 int off_dur; 470 } bwn_led_duration[109] = { 471 [0] = { 400, 100 }, 472 [2] = { 150, 75 }, 473 [4] = { 90, 45 }, 474 [11] = { 66, 34 }, 475 [12] = { 53, 26 }, 476 [18] = { 42, 21 }, 477 [22] = { 35, 17 }, 478 [24] = { 32, 16 }, 479 [36] = { 21, 10 }, 480 [48] = { 16, 8 }, 481 [72] = { 11, 5 }, 482 [96] = { 9, 4 }, 483 [108] = { 7, 3 } 484 }; 485 486 static const uint16_t bwn_wme_shm_offsets[] = { 487 [0] = BWN_WME_BESTEFFORT, 488 [1] = BWN_WME_BACKGROUND, 489 [2] = BWN_WME_VOICE, 490 [3] = BWN_WME_VIDEO, 491 }; 492 493 /* Supported D11 core revisions */ 494 #define BWN_DEV(_hwrev) {{ \ 495 BHND_MATCH_CORE(BHND_MFGID_BCM, BHND_COREID_D11), \ 496 BHND_MATCH_CORE_REV(_hwrev), \ 497 }} 498 static const struct bhnd_device bwn_devices[] = { 499 BWN_DEV(HWREV_RANGE(5, 16)), 500 BWN_DEV(HWREV_EQ(23)), 501 BHND_DEVICE_END 502 }; 503 504 /* D11 quirks when bridged via a PCI host bridge core */ 505 static const struct bhnd_device_quirk pci_bridge_quirks[] = { 506 BHND_CORE_QUIRK (HWREV_LTE(10), BWN_QUIRK_UCODE_SLOWCLOCK_WAR), 507 BHND_DEVICE_QUIRK_END 508 }; 509 510 /* D11 quirks when bridged via a PCMCIA host bridge core */ 511 static const struct bhnd_device_quirk pcmcia_bridge_quirks[] = { 512 BHND_CORE_QUIRK (HWREV_ANY, BWN_QUIRK_NODMA), 513 BHND_DEVICE_QUIRK_END 514 }; 515 516 /* Host bridge cores for which D11 quirk flags should be applied */ 517 static const struct bhnd_device bridge_devices[] = { 518 BHND_DEVICE(BCM, PCI, NULL, pci_bridge_quirks), 519 BHND_DEVICE(BCM, PCMCIA, NULL, pcmcia_bridge_quirks), 520 BHND_DEVICE_END 521 }; 522 523 static int 524 bwn_probe(device_t dev) 525 { 526 const struct bhnd_device *id; 527 528 id = bhnd_device_lookup(dev, bwn_devices, sizeof(bwn_devices[0])); 529 if (id == NULL) 530 return (ENXIO); 531 532 bhnd_set_default_core_desc(dev); 533 return (BUS_PROBE_DEFAULT); 534 } 535 536 static int 537 bwn_attach(device_t dev) 538 { 539 struct bwn_mac *mac; 540 struct bwn_softc *sc; 541 device_t parent, hostb; 542 char chip_name[BHND_CHIPID_MAX_NAMELEN]; 543 int error; 544 545 sc = device_get_softc(dev); 546 sc->sc_dev = dev; 547 #ifdef BWN_DEBUG 548 sc->sc_debug = bwn_debug; 549 #endif 550 551 mac = NULL; 552 553 /* Determine the driver quirks applicable to this device, including any 554 * quirks specific to the bus host bridge core (if any) */ 555 sc->sc_quirks = bhnd_device_quirks(dev, bwn_devices, 556 sizeof(bwn_devices[0])); 557 558 parent = device_get_parent(dev); 559 if ((hostb = bhnd_bus_find_hostb_device(parent)) != NULL) { 560 sc->sc_quirks |= bhnd_device_quirks(hostb, bridge_devices, 561 sizeof(bridge_devices[0])); 562 } 563 564 /* DMA explicitly disabled? */ 565 if (!bwn_usedma) 566 sc->sc_quirks |= BWN_QUIRK_NODMA; 567 568 /* Fetch our chip identification and board info */ 569 sc->sc_cid = *bhnd_get_chipid(dev); 570 if ((error = bhnd_read_board_info(dev, &sc->sc_board_info))) { 571 device_printf(sc->sc_dev, "couldn't read board info\n"); 572 return (error); 573 } 574 575 /* Allocate our D11 register block and PMU state */ 576 sc->sc_mem_rid = 0; 577 sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 578 &sc->sc_mem_rid, RF_ACTIVE); 579 if (sc->sc_mem_res == NULL) { 580 device_printf(sc->sc_dev, "couldn't allocate registers\n"); 581 return (error); 582 } 583 584 if ((error = bhnd_alloc_pmu(sc->sc_dev))) { 585 bus_release_resource(sc->sc_dev, SYS_RES_MEMORY, 586 sc->sc_mem_rid, sc->sc_mem_res); 587 return (error); 588 } 589 590 /* Retain references to all required bus service providers */ 591 if ((error = bwn_retain_bus_providers(sc))) 592 goto fail; 593 594 /* Fetch mask of available antennas */ 595 error = bhnd_nvram_getvar_uint8(sc->sc_dev, BHND_NVAR_AA2G, 596 &sc->sc_ant2g); 597 if (error) { 598 device_printf(sc->sc_dev, "error determining 2GHz antenna " 599 "availability from NVRAM: %d\n", error); 600 goto fail; 601 } 602 603 error = bhnd_nvram_getvar_uint8(sc->sc_dev, BHND_NVAR_AA5G, 604 &sc->sc_ant5g); 605 if (error) { 606 device_printf(sc->sc_dev, "error determining 5GHz antenna " 607 "availability from NVRAM: %d\n", error); 608 goto fail; 609 } 610 611 if ((sc->sc_flags & BWN_FLAG_ATTACHED) == 0) { 612 bwn_attach_pre(sc); 613 bwn_sprom_bugfixes(dev); 614 sc->sc_flags |= BWN_FLAG_ATTACHED; 615 } 616 617 mac = malloc(sizeof(*mac), M_DEVBUF, M_WAITOK | M_ZERO); 618 mac->mac_sc = sc; 619 mac->mac_status = BWN_MAC_STATUS_UNINIT; 620 if (bwn_bfp != 0) 621 mac->mac_flags |= BWN_MAC_FLAG_BADFRAME_PREEMP; 622 623 TASK_INIT(&mac->mac_hwreset, 0, bwn_hwreset, mac); 624 NET_TASK_INIT(&mac->mac_intrtask, 0, bwn_intrtask, mac); 625 TASK_INIT(&mac->mac_txpower, 0, bwn_txpwr, mac); 626 627 error = bwn_attach_core(mac); 628 if (error) 629 goto fail; 630 error = bwn_led_attach(mac); 631 if (error) 632 goto fail; 633 634 bhnd_format_chip_id(chip_name, sizeof(chip_name), sc->sc_cid.chip_id); 635 device_printf(sc->sc_dev, "WLAN (%s rev %u sromrev %u) " 636 "PHY (analog %d type %d rev %d) RADIO (manuf %#x ver %#x rev %d)\n", 637 chip_name, bhnd_get_hwrev(sc->sc_dev), 638 sc->sc_board_info.board_srom_rev, mac->mac_phy.analog, 639 mac->mac_phy.type, mac->mac_phy.rev, mac->mac_phy.rf_manuf, 640 mac->mac_phy.rf_ver, mac->mac_phy.rf_rev); 641 if (mac->mac_flags & BWN_MAC_FLAG_DMA) 642 device_printf(sc->sc_dev, "DMA (%d bits)\n", mac->mac_dmatype); 643 else 644 device_printf(sc->sc_dev, "PIO\n"); 645 646 #ifdef BWN_GPL_PHY 647 device_printf(sc->sc_dev, 648 "Note: compiled with BWN_GPL_PHY; includes GPLv2 code\n"); 649 #endif 650 651 mac->mac_rid_irq = 0; 652 mac->mac_res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, 653 &mac->mac_rid_irq, RF_ACTIVE | RF_SHAREABLE); 654 655 if (mac->mac_res_irq == NULL) { 656 device_printf(sc->sc_dev, "couldn't allocate IRQ resource\n"); 657 error = ENXIO; 658 goto fail; 659 } 660 661 error = bus_setup_intr(dev, mac->mac_res_irq, 662 INTR_TYPE_NET | INTR_MPSAFE, bwn_intr, NULL, mac, 663 &mac->mac_intrhand); 664 if (error != 0) { 665 device_printf(sc->sc_dev, "couldn't setup interrupt (%d)\n", 666 error); 667 goto fail; 668 } 669 670 TAILQ_INSERT_TAIL(&sc->sc_maclist, mac, mac_list); 671 672 /* 673 * calls attach-post routine 674 */ 675 if ((sc->sc_flags & BWN_FLAG_ATTACHED) != 0) 676 bwn_attach_post(sc); 677 678 return (0); 679 fail: 680 if (mac != NULL && mac->mac_res_irq != NULL) { 681 bus_release_resource(dev, SYS_RES_IRQ, mac->mac_rid_irq, 682 mac->mac_res_irq); 683 } 684 685 free(mac, M_DEVBUF); 686 bhnd_release_pmu(dev); 687 bwn_release_bus_providers(sc); 688 689 if (sc->sc_mem_res != NULL) { 690 bus_release_resource(sc->sc_dev, SYS_RES_MEMORY, 691 sc->sc_mem_rid, sc->sc_mem_res); 692 } 693 694 return (error); 695 } 696 697 static int 698 bwn_retain_bus_providers(struct bwn_softc *sc) 699 { 700 struct chipc_caps *ccaps; 701 702 sc->sc_chipc = bhnd_retain_provider(sc->sc_dev, BHND_SERVICE_CHIPC); 703 if (sc->sc_chipc == NULL) { 704 device_printf(sc->sc_dev, "ChipCommon device not found\n"); 705 goto failed; 706 } 707 708 ccaps = BHND_CHIPC_GET_CAPS(sc->sc_chipc); 709 710 sc->sc_gpio = bhnd_retain_provider(sc->sc_dev, BHND_SERVICE_GPIO); 711 if (sc->sc_gpio == NULL) { 712 device_printf(sc->sc_dev, "GPIO device not found\n"); 713 goto failed; 714 } 715 716 if (ccaps->pmu) { 717 sc->sc_pmu = bhnd_retain_provider(sc->sc_dev, BHND_SERVICE_PMU); 718 if (sc->sc_pmu == NULL) { 719 device_printf(sc->sc_dev, "PMU device not found\n"); 720 goto failed; 721 } 722 } 723 724 return (0); 725 726 failed: 727 bwn_release_bus_providers(sc); 728 return (ENXIO); 729 } 730 731 static void 732 bwn_release_bus_providers(struct bwn_softc *sc) 733 { 734 #define BWN_RELEASE_PROV(_sc, _prov, _service) do { \ 735 if ((_sc)-> _prov != NULL) { \ 736 bhnd_release_provider((_sc)->sc_dev, (_sc)-> _prov, \ 737 (_service)); \ 738 (_sc)-> _prov = NULL; \ 739 } \ 740 } while (0) 741 742 BWN_RELEASE_PROV(sc, sc_chipc, BHND_SERVICE_CHIPC); 743 BWN_RELEASE_PROV(sc, sc_gpio, BHND_SERVICE_GPIO); 744 BWN_RELEASE_PROV(sc, sc_pmu, BHND_SERVICE_PMU); 745 746 #undef BWN_RELEASE_PROV 747 } 748 749 static int 750 bwn_attach_post(struct bwn_softc *sc) 751 { 752 struct ieee80211com *ic; 753 const char *mac_varname; 754 u_int core_unit; 755 int error; 756 757 ic = &sc->sc_ic; 758 759 ic->ic_softc = sc; 760 ic->ic_name = device_get_nameunit(sc->sc_dev); 761 /* XXX not right but it's not used anywhere important */ 762 ic->ic_phytype = IEEE80211_T_OFDM; 763 ic->ic_opmode = IEEE80211_M_STA; 764 ic->ic_caps = 765 IEEE80211_C_STA /* station mode supported */ 766 | IEEE80211_C_MONITOR /* monitor mode */ 767 | IEEE80211_C_AHDEMO /* adhoc demo mode */ 768 | IEEE80211_C_SHPREAMBLE /* short preamble supported */ 769 | IEEE80211_C_SHSLOT /* short slot time supported */ 770 | IEEE80211_C_WME /* WME/WMM supported */ 771 | IEEE80211_C_WPA /* capable of WPA1+WPA2 */ 772 #if 0 773 | IEEE80211_C_BGSCAN /* capable of bg scanning */ 774 #endif 775 | IEEE80211_C_TXPMGT /* capable of txpow mgt */ 776 ; 777 778 ic->ic_flags_ext |= IEEE80211_FEXT_SWBMISS; /* s/w bmiss */ 779 780 /* Determine the NVRAM variable containing our MAC address */ 781 core_unit = bhnd_get_core_unit(sc->sc_dev); 782 mac_varname = NULL; 783 if (sc->sc_board_info.board_srom_rev <= 2) { 784 if (core_unit == 0) { 785 mac_varname = BHND_NVAR_IL0MACADDR; 786 } else if (core_unit == 1) { 787 mac_varname = BHND_NVAR_ET1MACADDR; 788 } 789 } else { 790 if (core_unit == 0) { 791 mac_varname = BHND_NVAR_MACADDR; 792 } 793 } 794 795 if (mac_varname == NULL) { 796 device_printf(sc->sc_dev, "missing MAC address variable for " 797 "D11 core %u", core_unit); 798 return (ENXIO); 799 } 800 801 /* Read the MAC address from NVRAM */ 802 error = bhnd_nvram_getvar_array(sc->sc_dev, mac_varname, ic->ic_macaddr, 803 sizeof(ic->ic_macaddr), BHND_NVRAM_TYPE_UINT8_ARRAY); 804 if (error) { 805 device_printf(sc->sc_dev, "error reading %s: %d\n", mac_varname, 806 error); 807 return (error); 808 } 809 810 /* call MI attach routine. */ 811 ieee80211_ifattach(ic); 812 813 ic->ic_headroom = sizeof(struct bwn_txhdr); 814 815 /* override default methods */ 816 ic->ic_raw_xmit = bwn_raw_xmit; 817 ic->ic_updateslot = bwn_updateslot; 818 ic->ic_update_promisc = bwn_update_promisc; 819 ic->ic_wme.wme_update = bwn_wme_update; 820 ic->ic_scan_start = bwn_scan_start; 821 ic->ic_scan_end = bwn_scan_end; 822 ic->ic_set_channel = bwn_set_channel; 823 ic->ic_vap_create = bwn_vap_create; 824 ic->ic_vap_delete = bwn_vap_delete; 825 ic->ic_transmit = bwn_transmit; 826 ic->ic_parent = bwn_parent; 827 828 ieee80211_radiotap_attach(ic, 829 &sc->sc_tx_th.wt_ihdr, sizeof(sc->sc_tx_th), 830 BWN_TX_RADIOTAP_PRESENT, 831 &sc->sc_rx_th.wr_ihdr, sizeof(sc->sc_rx_th), 832 BWN_RX_RADIOTAP_PRESENT); 833 834 bwn_sysctl_node(sc); 835 836 if (bootverbose) 837 ieee80211_announce(ic); 838 return (0); 839 } 840 841 static void 842 bwn_phy_detach(struct bwn_mac *mac) 843 { 844 845 if (mac->mac_phy.detach != NULL) 846 mac->mac_phy.detach(mac); 847 } 848 849 static int 850 bwn_detach(device_t dev) 851 { 852 struct bwn_softc *sc = device_get_softc(dev); 853 struct bwn_mac *mac = sc->sc_curmac; 854 struct ieee80211com *ic = &sc->sc_ic; 855 856 sc->sc_flags |= BWN_FLAG_INVALID; 857 858 if (device_is_attached(sc->sc_dev)) { 859 BWN_LOCK(sc); 860 bwn_stop(sc); 861 BWN_UNLOCK(sc); 862 bwn_dma_free(mac); 863 callout_drain(&sc->sc_led_blink_ch); 864 callout_drain(&sc->sc_rfswitch_ch); 865 callout_drain(&sc->sc_task_ch); 866 callout_drain(&sc->sc_watchdog_ch); 867 bwn_phy_detach(mac); 868 ieee80211_draintask(ic, &mac->mac_hwreset); 869 ieee80211_draintask(ic, &mac->mac_txpower); 870 ieee80211_ifdetach(ic); 871 } 872 taskqueue_drain(sc->sc_tq, &mac->mac_intrtask); 873 taskqueue_free(sc->sc_tq); 874 875 if (mac->mac_intrhand != NULL) { 876 bus_teardown_intr(dev, mac->mac_res_irq, mac->mac_intrhand); 877 mac->mac_intrhand = NULL; 878 } 879 880 bhnd_release_pmu(dev); 881 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_mem_rid, 882 sc->sc_mem_res); 883 bus_release_resource(dev, SYS_RES_IRQ, mac->mac_rid_irq, 884 mac->mac_res_irq); 885 mbufq_drain(&sc->sc_snd); 886 bwn_release_firmware(mac); 887 BWN_LOCK_DESTROY(sc); 888 889 bwn_release_bus_providers(sc); 890 891 return (0); 892 } 893 894 static void 895 bwn_attach_pre(struct bwn_softc *sc) 896 { 897 898 BWN_LOCK_INIT(sc); 899 TAILQ_INIT(&sc->sc_maclist); 900 callout_init_mtx(&sc->sc_rfswitch_ch, &sc->sc_mtx, 0); 901 callout_init_mtx(&sc->sc_task_ch, &sc->sc_mtx, 0); 902 callout_init_mtx(&sc->sc_watchdog_ch, &sc->sc_mtx, 0); 903 mbufq_init(&sc->sc_snd, ifqmaxlen); 904 sc->sc_tq = taskqueue_create_fast("bwn_taskq", M_NOWAIT, 905 taskqueue_thread_enqueue, &sc->sc_tq); 906 taskqueue_start_threads(&sc->sc_tq, 1, PI_NET, 907 "%s taskq", device_get_nameunit(sc->sc_dev)); 908 } 909 910 static void 911 bwn_sprom_bugfixes(device_t dev) 912 { 913 struct bwn_softc *sc = device_get_softc(dev); 914 915 #define BWN_ISDEV(_device, _subvendor, _subdevice) \ 916 ((sc->sc_board_info.board_devid == PCI_DEVID_##_device) && \ 917 (sc->sc_board_info.board_vendor == PCI_VENDOR_##_subvendor) && \ 918 (sc->sc_board_info.board_type == _subdevice)) 919 920 /* A subset of Apple Airport Extreme (BCM4306 rev 2) devices 921 * were programmed with a missing PACTRL boardflag */ 922 if (sc->sc_board_info.board_vendor == PCI_VENDOR_APPLE && 923 sc->sc_board_info.board_type == 0x4e && 924 sc->sc_board_info.board_rev > 0x40) 925 sc->sc_board_info.board_flags |= BHND_BFL_PACTRL; 926 927 if (BWN_ISDEV(BCM4318_D11G, ASUSTEK, 0x100f) || 928 BWN_ISDEV(BCM4306_D11G, DELL, 0x0003) || 929 BWN_ISDEV(BCM4306_D11G, HP, 0x12f8) || 930 BWN_ISDEV(BCM4306_D11G, LINKSYS, 0x0013) || 931 BWN_ISDEV(BCM4306_D11G, LINKSYS, 0x0014) || 932 BWN_ISDEV(BCM4306_D11G, LINKSYS, 0x0015) || 933 BWN_ISDEV(BCM4306_D11G, MOTOROLA, 0x7010)) 934 sc->sc_board_info.board_flags &= ~BHND_BFL_BTCOEX; 935 #undef BWN_ISDEV 936 } 937 938 static void 939 bwn_parent(struct ieee80211com *ic) 940 { 941 struct bwn_softc *sc = ic->ic_softc; 942 int startall = 0; 943 944 BWN_LOCK(sc); 945 if (ic->ic_nrunning > 0) { 946 if ((sc->sc_flags & BWN_FLAG_RUNNING) == 0) { 947 bwn_init(sc); 948 startall = 1; 949 } else 950 bwn_update_promisc(ic); 951 } else if (sc->sc_flags & BWN_FLAG_RUNNING) 952 bwn_stop(sc); 953 BWN_UNLOCK(sc); 954 955 if (startall) 956 ieee80211_start_all(ic); 957 } 958 959 static int 960 bwn_transmit(struct ieee80211com *ic, struct mbuf *m) 961 { 962 struct bwn_softc *sc = ic->ic_softc; 963 int error; 964 965 BWN_LOCK(sc); 966 if ((sc->sc_flags & BWN_FLAG_RUNNING) == 0) { 967 BWN_UNLOCK(sc); 968 return (ENXIO); 969 } 970 error = mbufq_enqueue(&sc->sc_snd, m); 971 if (error) { 972 BWN_UNLOCK(sc); 973 return (error); 974 } 975 bwn_start(sc); 976 BWN_UNLOCK(sc); 977 return (0); 978 } 979 980 static void 981 bwn_start(struct bwn_softc *sc) 982 { 983 struct bwn_mac *mac = sc->sc_curmac; 984 struct ieee80211_frame *wh; 985 struct ieee80211_node *ni; 986 struct ieee80211_key *k; 987 struct mbuf *m; 988 989 BWN_ASSERT_LOCKED(sc); 990 991 if ((sc->sc_flags & BWN_FLAG_RUNNING) == 0 || mac == NULL || 992 mac->mac_status < BWN_MAC_STATUS_STARTED) 993 return; 994 995 while ((m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 996 if (bwn_tx_isfull(sc, m)) 997 break; 998 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif; 999 if (ni == NULL) { 1000 device_printf(sc->sc_dev, "unexpected NULL ni\n"); 1001 m_freem(m); 1002 counter_u64_add(sc->sc_ic.ic_oerrors, 1); 1003 continue; 1004 } 1005 wh = mtod(m, struct ieee80211_frame *); 1006 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1007 k = ieee80211_crypto_encap(ni, m); 1008 if (k == NULL) { 1009 if_inc_counter(ni->ni_vap->iv_ifp, 1010 IFCOUNTER_OERRORS, 1); 1011 ieee80211_free_node(ni); 1012 m_freem(m); 1013 continue; 1014 } 1015 } 1016 wh = NULL; /* Catch any invalid use */ 1017 if (bwn_tx_start(sc, ni, m) != 0) { 1018 if (ni != NULL) { 1019 if_inc_counter(ni->ni_vap->iv_ifp, 1020 IFCOUNTER_OERRORS, 1); 1021 ieee80211_free_node(ni); 1022 } 1023 continue; 1024 } 1025 sc->sc_watchdog_timer = 5; 1026 } 1027 } 1028 1029 static int 1030 bwn_tx_isfull(struct bwn_softc *sc, struct mbuf *m) 1031 { 1032 struct bwn_dma_ring *dr; 1033 struct bwn_mac *mac = sc->sc_curmac; 1034 struct bwn_pio_txqueue *tq; 1035 int pktlen = roundup(m->m_pkthdr.len + BWN_HDRSIZE(mac), 4); 1036 1037 BWN_ASSERT_LOCKED(sc); 1038 1039 if (mac->mac_flags & BWN_MAC_FLAG_DMA) { 1040 dr = bwn_dma_select(mac, M_WME_GETAC(m)); 1041 if (dr->dr_stop == 1 || 1042 bwn_dma_freeslot(dr) < BWN_TX_SLOTS_PER_FRAME) { 1043 dr->dr_stop = 1; 1044 goto full; 1045 } 1046 } else { 1047 tq = bwn_pio_select(mac, M_WME_GETAC(m)); 1048 if (tq->tq_free == 0 || pktlen > tq->tq_size || 1049 pktlen > (tq->tq_size - tq->tq_used)) 1050 goto full; 1051 } 1052 return (0); 1053 full: 1054 mbufq_prepend(&sc->sc_snd, m); 1055 return (1); 1056 } 1057 1058 static int 1059 bwn_tx_start(struct bwn_softc *sc, struct ieee80211_node *ni, struct mbuf *m) 1060 { 1061 struct bwn_mac *mac = sc->sc_curmac; 1062 int error; 1063 1064 BWN_ASSERT_LOCKED(sc); 1065 1066 if (m->m_pkthdr.len < IEEE80211_MIN_LEN || mac == NULL) { 1067 m_freem(m); 1068 return (ENXIO); 1069 } 1070 1071 error = (mac->mac_flags & BWN_MAC_FLAG_DMA) ? 1072 bwn_dma_tx_start(mac, ni, &m) : bwn_pio_tx_start(mac, ni, &m); 1073 if (error) { 1074 m_freem(m); 1075 return (error); 1076 } 1077 return (0); 1078 } 1079 1080 static int 1081 bwn_pio_tx_start(struct bwn_mac *mac, struct ieee80211_node *ni, 1082 struct mbuf **mp) 1083 { 1084 struct bwn_pio_txpkt *tp; 1085 struct bwn_pio_txqueue *tq; 1086 struct bwn_softc *sc = mac->mac_sc; 1087 struct bwn_txhdr txhdr; 1088 struct mbuf *m, *m_new; 1089 uint32_t ctl32; 1090 int error; 1091 uint16_t ctl16; 1092 1093 BWN_ASSERT_LOCKED(sc); 1094 1095 /* XXX TODO send packets after DTIM */ 1096 1097 m = *mp; 1098 tq = bwn_pio_select(mac, M_WME_GETAC(m)); 1099 KASSERT(!TAILQ_EMPTY(&tq->tq_pktlist), ("%s: fail", __func__)); 1100 tp = TAILQ_FIRST(&tq->tq_pktlist); 1101 tp->tp_ni = ni; 1102 tp->tp_m = m; 1103 1104 error = bwn_set_txhdr(mac, ni, m, &txhdr, BWN_PIO_COOKIE(tq, tp)); 1105 if (error) { 1106 device_printf(sc->sc_dev, "tx fail\n"); 1107 return (error); 1108 } 1109 1110 TAILQ_REMOVE(&tq->tq_pktlist, tp, tp_list); 1111 tq->tq_used += roundup(m->m_pkthdr.len + BWN_HDRSIZE(mac), 4); 1112 tq->tq_free--; 1113 1114 if (bhnd_get_hwrev(sc->sc_dev) >= 8) { 1115 /* 1116 * XXX please removes m_defrag(9) 1117 */ 1118 m_new = m_defrag(*mp, M_NOWAIT); 1119 if (m_new == NULL) { 1120 device_printf(sc->sc_dev, 1121 "%s: can't defrag TX buffer\n", 1122 __func__); 1123 return (ENOBUFS); 1124 } 1125 *mp = m_new; 1126 if (m_new->m_next != NULL) 1127 device_printf(sc->sc_dev, 1128 "TODO: fragmented packets for PIO\n"); 1129 tp->tp_m = m_new; 1130 1131 /* send HEADER */ 1132 ctl32 = bwn_pio_write_multi_4(mac, tq, 1133 (BWN_PIO_READ_4(mac, tq, BWN_PIO8_TXCTL) | 1134 BWN_PIO8_TXCTL_FRAMEREADY) & ~BWN_PIO8_TXCTL_EOF, 1135 (const uint8_t *)&txhdr, BWN_HDRSIZE(mac)); 1136 /* send BODY */ 1137 ctl32 = bwn_pio_write_multi_4(mac, tq, ctl32, 1138 mtod(m_new, const void *), m_new->m_pkthdr.len); 1139 bwn_pio_write_4(mac, tq, BWN_PIO_TXCTL, 1140 ctl32 | BWN_PIO8_TXCTL_EOF); 1141 } else { 1142 ctl16 = bwn_pio_write_multi_2(mac, tq, 1143 (bwn_pio_read_2(mac, tq, BWN_PIO_TXCTL) | 1144 BWN_PIO_TXCTL_FRAMEREADY) & ~BWN_PIO_TXCTL_EOF, 1145 (const uint8_t *)&txhdr, BWN_HDRSIZE(mac)); 1146 ctl16 = bwn_pio_write_mbuf_2(mac, tq, ctl16, m); 1147 BWN_PIO_WRITE_2(mac, tq, BWN_PIO_TXCTL, 1148 ctl16 | BWN_PIO_TXCTL_EOF); 1149 } 1150 1151 return (0); 1152 } 1153 1154 static struct bwn_pio_txqueue * 1155 bwn_pio_select(struct bwn_mac *mac, uint8_t prio) 1156 { 1157 1158 if ((mac->mac_flags & BWN_MAC_FLAG_WME) == 0) 1159 return (&mac->mac_method.pio.wme[WME_AC_BE]); 1160 1161 switch (prio) { 1162 case 0: 1163 return (&mac->mac_method.pio.wme[WME_AC_BE]); 1164 case 1: 1165 return (&mac->mac_method.pio.wme[WME_AC_BK]); 1166 case 2: 1167 return (&mac->mac_method.pio.wme[WME_AC_VI]); 1168 case 3: 1169 return (&mac->mac_method.pio.wme[WME_AC_VO]); 1170 } 1171 KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__)); 1172 return (NULL); 1173 } 1174 1175 static int 1176 bwn_dma_tx_start(struct bwn_mac *mac, struct ieee80211_node *ni, 1177 struct mbuf **mp) 1178 { 1179 #define BWN_GET_TXHDRCACHE(slot) \ 1180 &(txhdr_cache[(slot / BWN_TX_SLOTS_PER_FRAME) * BWN_HDRSIZE(mac)]) 1181 struct bwn_dma *dma = &mac->mac_method.dma; 1182 struct bwn_dma_ring *dr = bwn_dma_select(mac, M_WME_GETAC(*mp)); 1183 struct bwn_dmadesc_generic *desc; 1184 struct bwn_dmadesc_meta *mt; 1185 struct bwn_softc *sc = mac->mac_sc; 1186 struct mbuf *m; 1187 uint8_t *txhdr_cache = (uint8_t *)dr->dr_txhdr_cache; 1188 int error, slot, backup[2] = { dr->dr_curslot, dr->dr_usedslot }; 1189 1190 BWN_ASSERT_LOCKED(sc); 1191 KASSERT(!dr->dr_stop, ("%s:%d: fail", __func__, __LINE__)); 1192 1193 /* XXX send after DTIM */ 1194 1195 m = *mp; 1196 slot = bwn_dma_getslot(dr); 1197 dr->getdesc(dr, slot, &desc, &mt); 1198 KASSERT(mt->mt_txtype == BWN_DMADESC_METATYPE_HEADER, 1199 ("%s:%d: fail", __func__, __LINE__)); 1200 1201 error = bwn_set_txhdr(dr->dr_mac, ni, m, 1202 (struct bwn_txhdr *)BWN_GET_TXHDRCACHE(slot), 1203 BWN_DMA_COOKIE(dr, slot)); 1204 if (error) 1205 goto fail; 1206 error = bus_dmamap_load(dr->dr_txring_dtag, mt->mt_dmap, 1207 BWN_GET_TXHDRCACHE(slot), BWN_HDRSIZE(mac), bwn_dma_ring_addr, 1208 &mt->mt_paddr, BUS_DMA_NOWAIT); 1209 if (error) { 1210 device_printf(sc->sc_dev, "%s: can't load TX buffer (1) %d\n", 1211 __func__, error); 1212 goto fail; 1213 } 1214 bus_dmamap_sync(dr->dr_txring_dtag, mt->mt_dmap, 1215 BUS_DMASYNC_PREWRITE); 1216 dr->setdesc(dr, desc, mt->mt_paddr, BWN_HDRSIZE(mac), 1, 0, 0); 1217 bus_dmamap_sync(dr->dr_ring_dtag, dr->dr_ring_dmap, 1218 BUS_DMASYNC_PREWRITE); 1219 1220 slot = bwn_dma_getslot(dr); 1221 dr->getdesc(dr, slot, &desc, &mt); 1222 KASSERT(mt->mt_txtype == BWN_DMADESC_METATYPE_BODY && 1223 mt->mt_islast == 1, ("%s:%d: fail", __func__, __LINE__)); 1224 mt->mt_m = m; 1225 mt->mt_ni = ni; 1226 1227 error = bus_dmamap_load_mbuf(dma->txbuf_dtag, mt->mt_dmap, m, 1228 bwn_dma_buf_addr, &mt->mt_paddr, BUS_DMA_NOWAIT); 1229 if (error && error != EFBIG) { 1230 device_printf(sc->sc_dev, "%s: can't load TX buffer (1) %d\n", 1231 __func__, error); 1232 goto fail; 1233 } 1234 if (error) { /* error == EFBIG */ 1235 struct mbuf *m_new; 1236 1237 m_new = m_defrag(m, M_NOWAIT); 1238 if (m_new == NULL) { 1239 device_printf(sc->sc_dev, 1240 "%s: can't defrag TX buffer\n", 1241 __func__); 1242 error = ENOBUFS; 1243 goto fail; 1244 } 1245 *mp = m = m_new; 1246 1247 mt->mt_m = m; 1248 error = bus_dmamap_load_mbuf(dma->txbuf_dtag, mt->mt_dmap, 1249 m, bwn_dma_buf_addr, &mt->mt_paddr, BUS_DMA_NOWAIT); 1250 if (error) { 1251 device_printf(sc->sc_dev, 1252 "%s: can't load TX buffer (2) %d\n", 1253 __func__, error); 1254 goto fail; 1255 } 1256 } 1257 bus_dmamap_sync(dma->txbuf_dtag, mt->mt_dmap, BUS_DMASYNC_PREWRITE); 1258 dr->setdesc(dr, desc, mt->mt_paddr, m->m_pkthdr.len, 0, 1, 1); 1259 bus_dmamap_sync(dr->dr_ring_dtag, dr->dr_ring_dmap, 1260 BUS_DMASYNC_PREWRITE); 1261 1262 /* XXX send after DTIM */ 1263 1264 dr->start_transfer(dr, bwn_dma_nextslot(dr, slot)); 1265 return (0); 1266 fail: 1267 dr->dr_curslot = backup[0]; 1268 dr->dr_usedslot = backup[1]; 1269 return (error); 1270 #undef BWN_GET_TXHDRCACHE 1271 } 1272 1273 static void 1274 bwn_watchdog(void *arg) 1275 { 1276 struct bwn_softc *sc = arg; 1277 1278 if (sc->sc_watchdog_timer != 0 && --sc->sc_watchdog_timer == 0) { 1279 device_printf(sc->sc_dev, "device timeout\n"); 1280 counter_u64_add(sc->sc_ic.ic_oerrors, 1); 1281 } 1282 callout_schedule(&sc->sc_watchdog_ch, hz); 1283 } 1284 1285 static int 1286 bwn_attach_core(struct bwn_mac *mac) 1287 { 1288 struct bwn_softc *sc = mac->mac_sc; 1289 int error, have_bg = 0, have_a = 0; 1290 uint16_t iost; 1291 1292 KASSERT(bhnd_get_hwrev(sc->sc_dev) >= 5, 1293 ("unsupported revision %d", bhnd_get_hwrev(sc->sc_dev))); 1294 1295 if ((error = bwn_core_forceclk(mac, true))) 1296 return (error); 1297 1298 if ((error = bhnd_read_iost(sc->sc_dev, &iost))) { 1299 device_printf(sc->sc_dev, "error reading I/O status flags: " 1300 "%d\n", error); 1301 return (error); 1302 } 1303 1304 have_a = (iost & BWN_IOST_HAVE_5GHZ) ? 1 : 0; 1305 have_bg = (iost & BWN_IOST_HAVE_2GHZ) ? 1 : 0; 1306 if (iost & BWN_IOST_DUALPHY) { 1307 have_bg = 1; 1308 have_a = 1; 1309 } 1310 1311 #if 0 1312 device_printf(sc->sc_dev, "%s: iost=0x%04hx, have_a=%d, have_bg=%d," 1313 " deviceid=0x%04x, siba_deviceid=0x%04x\n", 1314 __func__, 1315 iost, 1316 have_a, 1317 have_bg, 1318 sc->sc_board_info.board_devid, 1319 sc->sc_cid.chip_id); 1320 #endif 1321 1322 /* 1323 * Guess at whether it has A-PHY or G-PHY. 1324 * This is just used for resetting the core to probe things; 1325 * we will re-guess once it's all up and working. 1326 */ 1327 error = bwn_reset_core(mac, have_bg); 1328 if (error) 1329 goto fail; 1330 1331 /* 1332 * Determine the DMA engine type 1333 */ 1334 if (iost & BHND_IOST_DMA64) { 1335 mac->mac_dmatype = BHND_DMA_ADDR_64BIT; 1336 } else { 1337 uint32_t tmp; 1338 uint16_t base; 1339 1340 base = bwn_dma_base(0, 0); 1341 BWN_WRITE_4(mac, base + BWN_DMA32_TXCTL, 1342 BWN_DMA32_TXADDREXT_MASK); 1343 tmp = BWN_READ_4(mac, base + BWN_DMA32_TXCTL); 1344 if (tmp & BWN_DMA32_TXADDREXT_MASK) { 1345 mac->mac_dmatype = BHND_DMA_ADDR_32BIT; 1346 } else { 1347 mac->mac_dmatype = BHND_DMA_ADDR_30BIT; 1348 } 1349 } 1350 1351 /* 1352 * Get the PHY version. 1353 */ 1354 error = bwn_phy_getinfo(mac, have_bg); 1355 if (error) 1356 goto fail; 1357 1358 /* 1359 * This is the whitelist of devices which we "believe" 1360 * the SPROM PHY config from. The rest are "guessed". 1361 */ 1362 if (sc->sc_board_info.board_devid != PCI_DEVID_BCM4311_D11DUAL && 1363 sc->sc_board_info.board_devid != PCI_DEVID_BCM4328_D11G && 1364 sc->sc_board_info.board_devid != PCI_DEVID_BCM4318_D11DUAL && 1365 sc->sc_board_info.board_devid != PCI_DEVID_BCM4306_D11DUAL && 1366 sc->sc_board_info.board_devid != PCI_DEVID_BCM4321_D11N && 1367 sc->sc_board_info.board_devid != PCI_DEVID_BCM4322_D11N) { 1368 have_a = have_bg = 0; 1369 if (mac->mac_phy.type == BWN_PHYTYPE_A) 1370 have_a = 1; 1371 else if (mac->mac_phy.type == BWN_PHYTYPE_G || 1372 mac->mac_phy.type == BWN_PHYTYPE_N || 1373 mac->mac_phy.type == BWN_PHYTYPE_LP) 1374 have_bg = 1; 1375 else 1376 KASSERT(0 == 1, ("%s: unknown phy type (%d)", __func__, 1377 mac->mac_phy.type)); 1378 } 1379 1380 /* 1381 * XXX The PHY-G support doesn't do 5GHz operation. 1382 */ 1383 if (mac->mac_phy.type != BWN_PHYTYPE_LP && 1384 mac->mac_phy.type != BWN_PHYTYPE_N) { 1385 device_printf(sc->sc_dev, 1386 "%s: forcing 2GHz only; no dual-band support for PHY\n", 1387 __func__); 1388 have_a = 0; 1389 have_bg = 1; 1390 } 1391 1392 mac->mac_phy.phy_n = NULL; 1393 1394 if (mac->mac_phy.type == BWN_PHYTYPE_G) { 1395 mac->mac_phy.attach = bwn_phy_g_attach; 1396 mac->mac_phy.detach = bwn_phy_g_detach; 1397 mac->mac_phy.prepare_hw = bwn_phy_g_prepare_hw; 1398 mac->mac_phy.init_pre = bwn_phy_g_init_pre; 1399 mac->mac_phy.init = bwn_phy_g_init; 1400 mac->mac_phy.exit = bwn_phy_g_exit; 1401 mac->mac_phy.phy_read = bwn_phy_g_read; 1402 mac->mac_phy.phy_write = bwn_phy_g_write; 1403 mac->mac_phy.rf_read = bwn_phy_g_rf_read; 1404 mac->mac_phy.rf_write = bwn_phy_g_rf_write; 1405 mac->mac_phy.use_hwpctl = bwn_phy_g_hwpctl; 1406 mac->mac_phy.rf_onoff = bwn_phy_g_rf_onoff; 1407 mac->mac_phy.switch_analog = bwn_phy_switch_analog; 1408 mac->mac_phy.switch_channel = bwn_phy_g_switch_channel; 1409 mac->mac_phy.get_default_chan = bwn_phy_g_get_default_chan; 1410 mac->mac_phy.set_antenna = bwn_phy_g_set_antenna; 1411 mac->mac_phy.set_im = bwn_phy_g_im; 1412 mac->mac_phy.recalc_txpwr = bwn_phy_g_recalc_txpwr; 1413 mac->mac_phy.set_txpwr = bwn_phy_g_set_txpwr; 1414 mac->mac_phy.task_15s = bwn_phy_g_task_15s; 1415 mac->mac_phy.task_60s = bwn_phy_g_task_60s; 1416 } else if (mac->mac_phy.type == BWN_PHYTYPE_LP) { 1417 mac->mac_phy.init_pre = bwn_phy_lp_init_pre; 1418 mac->mac_phy.init = bwn_phy_lp_init; 1419 mac->mac_phy.phy_read = bwn_phy_lp_read; 1420 mac->mac_phy.phy_write = bwn_phy_lp_write; 1421 mac->mac_phy.phy_maskset = bwn_phy_lp_maskset; 1422 mac->mac_phy.rf_read = bwn_phy_lp_rf_read; 1423 mac->mac_phy.rf_write = bwn_phy_lp_rf_write; 1424 mac->mac_phy.rf_onoff = bwn_phy_lp_rf_onoff; 1425 mac->mac_phy.switch_analog = bwn_phy_lp_switch_analog; 1426 mac->mac_phy.switch_channel = bwn_phy_lp_switch_channel; 1427 mac->mac_phy.get_default_chan = bwn_phy_lp_get_default_chan; 1428 mac->mac_phy.set_antenna = bwn_phy_lp_set_antenna; 1429 mac->mac_phy.task_60s = bwn_phy_lp_task_60s; 1430 } else if (mac->mac_phy.type == BWN_PHYTYPE_N) { 1431 mac->mac_phy.attach = bwn_phy_n_attach; 1432 mac->mac_phy.detach = bwn_phy_n_detach; 1433 mac->mac_phy.prepare_hw = bwn_phy_n_prepare_hw; 1434 mac->mac_phy.init_pre = bwn_phy_n_init_pre; 1435 mac->mac_phy.init = bwn_phy_n_init; 1436 mac->mac_phy.exit = bwn_phy_n_exit; 1437 mac->mac_phy.phy_read = bwn_phy_n_read; 1438 mac->mac_phy.phy_write = bwn_phy_n_write; 1439 mac->mac_phy.rf_read = bwn_phy_n_rf_read; 1440 mac->mac_phy.rf_write = bwn_phy_n_rf_write; 1441 mac->mac_phy.use_hwpctl = bwn_phy_n_hwpctl; 1442 mac->mac_phy.rf_onoff = bwn_phy_n_rf_onoff; 1443 mac->mac_phy.switch_analog = bwn_phy_n_switch_analog; 1444 mac->mac_phy.switch_channel = bwn_phy_n_switch_channel; 1445 mac->mac_phy.get_default_chan = bwn_phy_n_get_default_chan; 1446 mac->mac_phy.set_antenna = bwn_phy_n_set_antenna; 1447 mac->mac_phy.set_im = bwn_phy_n_im; 1448 mac->mac_phy.recalc_txpwr = bwn_phy_n_recalc_txpwr; 1449 mac->mac_phy.set_txpwr = bwn_phy_n_set_txpwr; 1450 mac->mac_phy.task_15s = bwn_phy_n_task_15s; 1451 mac->mac_phy.task_60s = bwn_phy_n_task_60s; 1452 } else { 1453 device_printf(sc->sc_dev, "unsupported PHY type (%d)\n", 1454 mac->mac_phy.type); 1455 error = ENXIO; 1456 goto fail; 1457 } 1458 1459 mac->mac_phy.gmode = have_bg; 1460 if (mac->mac_phy.attach != NULL) { 1461 error = mac->mac_phy.attach(mac); 1462 if (error) { 1463 device_printf(sc->sc_dev, "failed\n"); 1464 goto fail; 1465 } 1466 } 1467 1468 error = bwn_reset_core(mac, have_bg); 1469 if (error) 1470 goto fail; 1471 1472 error = bwn_chiptest(mac); 1473 if (error) 1474 goto fail; 1475 error = bwn_setup_channels(mac, have_bg, have_a); 1476 if (error) { 1477 device_printf(sc->sc_dev, "failed to setup channels\n"); 1478 goto fail; 1479 } 1480 1481 if (sc->sc_curmac == NULL) 1482 sc->sc_curmac = mac; 1483 1484 error = bwn_dma_attach(mac); 1485 if (error != 0) { 1486 device_printf(sc->sc_dev, "failed to initialize DMA\n"); 1487 goto fail; 1488 } 1489 1490 mac->mac_phy.switch_analog(mac, 0); 1491 1492 fail: 1493 bhnd_suspend_hw(sc->sc_dev, 0); 1494 bwn_release_firmware(mac); 1495 return (error); 1496 } 1497 1498 /* 1499 * Reset 1500 */ 1501 int 1502 bwn_reset_core(struct bwn_mac *mac, int g_mode) 1503 { 1504 struct bwn_softc *sc; 1505 uint32_t ctl; 1506 uint16_t ioctl, ioctl_mask; 1507 int error; 1508 1509 sc = mac->mac_sc; 1510 1511 DPRINTF(sc, BWN_DEBUG_RESET, "%s: g_mode=%d\n", __func__, g_mode); 1512 1513 /* Reset core */ 1514 ioctl = (BWN_IOCTL_PHYCLOCK_ENABLE | BWN_IOCTL_PHYRESET); 1515 if (g_mode) 1516 ioctl |= BWN_IOCTL_SUPPORT_G; 1517 1518 /* XXX N-PHY only; and hard-code to 20MHz for now */ 1519 if (mac->mac_phy.type == BWN_PHYTYPE_N) 1520 ioctl |= BWN_IOCTL_PHY_BANDWIDTH_20MHZ; 1521 1522 if ((error = bhnd_reset_hw(sc->sc_dev, ioctl, ioctl))) { 1523 device_printf(sc->sc_dev, "core reset failed: %d", error); 1524 return (error); 1525 } 1526 1527 DELAY(2000); 1528 1529 /* Take PHY out of reset */ 1530 ioctl = BHND_IOCTL_CLK_FORCE; 1531 ioctl_mask = BHND_IOCTL_CLK_FORCE | 1532 BWN_IOCTL_PHYRESET | 1533 BWN_IOCTL_PHYCLOCK_ENABLE; 1534 1535 if ((error = bhnd_write_ioctl(sc->sc_dev, ioctl, ioctl_mask))) { 1536 device_printf(sc->sc_dev, "failed to set core ioctl flags: " 1537 "%d\n", error); 1538 return (error); 1539 } 1540 1541 DELAY(2000); 1542 1543 ioctl = BWN_IOCTL_PHYCLOCK_ENABLE; 1544 if ((error = bhnd_write_ioctl(sc->sc_dev, ioctl, ioctl_mask))) { 1545 device_printf(sc->sc_dev, "failed to set core ioctl flags: " 1546 "%d\n", error); 1547 return (error); 1548 } 1549 1550 DELAY(2000); 1551 1552 if (mac->mac_phy.switch_analog != NULL) 1553 mac->mac_phy.switch_analog(mac, 1); 1554 1555 ctl = BWN_READ_4(mac, BWN_MACCTL) & ~BWN_MACCTL_GMODE; 1556 if (g_mode) 1557 ctl |= BWN_MACCTL_GMODE; 1558 BWN_WRITE_4(mac, BWN_MACCTL, ctl | BWN_MACCTL_IHR_ON); 1559 1560 return (0); 1561 } 1562 1563 static int 1564 bwn_phy_getinfo(struct bwn_mac *mac, int gmode) 1565 { 1566 struct bwn_phy *phy = &mac->mac_phy; 1567 struct bwn_softc *sc = mac->mac_sc; 1568 uint32_t tmp; 1569 1570 /* PHY */ 1571 tmp = BWN_READ_2(mac, BWN_PHYVER); 1572 phy->gmode = gmode; 1573 phy->rf_on = 1; 1574 phy->analog = (tmp & BWN_PHYVER_ANALOG) >> 12; 1575 phy->type = (tmp & BWN_PHYVER_TYPE) >> 8; 1576 phy->rev = (tmp & BWN_PHYVER_VERSION); 1577 if ((phy->type == BWN_PHYTYPE_A && phy->rev >= 4) || 1578 (phy->type == BWN_PHYTYPE_B && phy->rev != 2 && 1579 phy->rev != 4 && phy->rev != 6 && phy->rev != 7) || 1580 (phy->type == BWN_PHYTYPE_G && phy->rev > 9) || 1581 (phy->type == BWN_PHYTYPE_N && phy->rev > 6) || 1582 (phy->type == BWN_PHYTYPE_LP && phy->rev > 2)) 1583 goto unsupphy; 1584 1585 /* RADIO */ 1586 BWN_WRITE_2(mac, BWN_RFCTL, BWN_RFCTL_ID); 1587 tmp = BWN_READ_2(mac, BWN_RFDATALO); 1588 BWN_WRITE_2(mac, BWN_RFCTL, BWN_RFCTL_ID); 1589 tmp |= (uint32_t)BWN_READ_2(mac, BWN_RFDATAHI) << 16; 1590 1591 phy->rf_rev = (tmp & 0xf0000000) >> 28; 1592 phy->rf_ver = (tmp & 0x0ffff000) >> 12; 1593 phy->rf_manuf = (tmp & 0x00000fff); 1594 1595 /* 1596 * For now, just always do full init (ie, what bwn has traditionally 1597 * done) 1598 */ 1599 phy->phy_do_full_init = 1; 1600 1601 if (phy->rf_manuf != 0x17f) /* 0x17f is broadcom */ 1602 goto unsupradio; 1603 if ((phy->type == BWN_PHYTYPE_A && (phy->rf_ver != 0x2060 || 1604 phy->rf_rev != 1 || phy->rf_manuf != 0x17f)) || 1605 (phy->type == BWN_PHYTYPE_B && (phy->rf_ver & 0xfff0) != 0x2050) || 1606 (phy->type == BWN_PHYTYPE_G && phy->rf_ver != 0x2050) || 1607 (phy->type == BWN_PHYTYPE_N && 1608 phy->rf_ver != 0x2055 && phy->rf_ver != 0x2056) || 1609 (phy->type == BWN_PHYTYPE_LP && 1610 phy->rf_ver != 0x2062 && phy->rf_ver != 0x2063)) 1611 goto unsupradio; 1612 1613 return (0); 1614 unsupphy: 1615 device_printf(sc->sc_dev, "unsupported PHY (type %#x, rev %#x, " 1616 "analog %#x)\n", 1617 phy->type, phy->rev, phy->analog); 1618 return (ENXIO); 1619 unsupradio: 1620 device_printf(sc->sc_dev, "unsupported radio (manuf %#x, ver %#x, " 1621 "rev %#x)\n", 1622 phy->rf_manuf, phy->rf_ver, phy->rf_rev); 1623 return (ENXIO); 1624 } 1625 1626 static int 1627 bwn_chiptest(struct bwn_mac *mac) 1628 { 1629 #define TESTVAL0 0x55aaaa55 1630 #define TESTVAL1 0xaa5555aa 1631 struct bwn_softc *sc = mac->mac_sc; 1632 uint32_t v, backup; 1633 1634 BWN_LOCK(sc); 1635 1636 backup = bwn_shm_read_4(mac, BWN_SHARED, 0); 1637 1638 bwn_shm_write_4(mac, BWN_SHARED, 0, TESTVAL0); 1639 if (bwn_shm_read_4(mac, BWN_SHARED, 0) != TESTVAL0) 1640 goto error; 1641 bwn_shm_write_4(mac, BWN_SHARED, 0, TESTVAL1); 1642 if (bwn_shm_read_4(mac, BWN_SHARED, 0) != TESTVAL1) 1643 goto error; 1644 1645 bwn_shm_write_4(mac, BWN_SHARED, 0, backup); 1646 1647 if ((bhnd_get_hwrev(sc->sc_dev) >= 3) && 1648 (bhnd_get_hwrev(sc->sc_dev) <= 10)) { 1649 BWN_WRITE_2(mac, BWN_TSF_CFP_START, 0xaaaa); 1650 BWN_WRITE_4(mac, BWN_TSF_CFP_START, 0xccccbbbb); 1651 if (BWN_READ_2(mac, BWN_TSF_CFP_START_LOW) != 0xbbbb) 1652 goto error; 1653 if (BWN_READ_2(mac, BWN_TSF_CFP_START_HIGH) != 0xcccc) 1654 goto error; 1655 } 1656 BWN_WRITE_4(mac, BWN_TSF_CFP_START, 0); 1657 1658 v = BWN_READ_4(mac, BWN_MACCTL) | BWN_MACCTL_GMODE; 1659 if (v != (BWN_MACCTL_GMODE | BWN_MACCTL_IHR_ON)) 1660 goto error; 1661 1662 BWN_UNLOCK(sc); 1663 return (0); 1664 error: 1665 BWN_UNLOCK(sc); 1666 device_printf(sc->sc_dev, "failed to validate the chipaccess\n"); 1667 return (ENODEV); 1668 } 1669 1670 static int 1671 bwn_setup_channels(struct bwn_mac *mac, int have_bg, int have_a) 1672 { 1673 struct bwn_softc *sc = mac->mac_sc; 1674 struct ieee80211com *ic = &sc->sc_ic; 1675 uint8_t bands[IEEE80211_MODE_BYTES]; 1676 1677 memset(ic->ic_channels, 0, sizeof(ic->ic_channels)); 1678 ic->ic_nchans = 0; 1679 1680 DPRINTF(sc, BWN_DEBUG_EEPROM, "%s: called; bg=%d, a=%d\n", 1681 __func__, 1682 have_bg, 1683 have_a); 1684 1685 if (have_bg) { 1686 memset(bands, 0, sizeof(bands)); 1687 setbit(bands, IEEE80211_MODE_11B); 1688 setbit(bands, IEEE80211_MODE_11G); 1689 bwn_addchannels(ic->ic_channels, IEEE80211_CHAN_MAX, 1690 &ic->ic_nchans, &bwn_chantable_bg, bands); 1691 } 1692 1693 if (have_a) { 1694 memset(bands, 0, sizeof(bands)); 1695 setbit(bands, IEEE80211_MODE_11A); 1696 bwn_addchannels(ic->ic_channels, IEEE80211_CHAN_MAX, 1697 &ic->ic_nchans, &bwn_chantable_a, bands); 1698 } 1699 1700 mac->mac_phy.supports_2ghz = have_bg; 1701 mac->mac_phy.supports_5ghz = have_a; 1702 1703 return (ic->ic_nchans == 0 ? ENXIO : 0); 1704 } 1705 1706 uint32_t 1707 bwn_shm_read_4(struct bwn_mac *mac, uint16_t way, uint16_t offset) 1708 { 1709 uint32_t ret; 1710 1711 BWN_ASSERT_LOCKED(mac->mac_sc); 1712 1713 if (way == BWN_SHARED) { 1714 KASSERT((offset & 0x0001) == 0, 1715 ("%s:%d warn", __func__, __LINE__)); 1716 if (offset & 0x0003) { 1717 bwn_shm_ctlword(mac, way, offset >> 2); 1718 ret = BWN_READ_2(mac, BWN_SHM_DATA_UNALIGNED); 1719 ret <<= 16; 1720 bwn_shm_ctlword(mac, way, (offset >> 2) + 1); 1721 ret |= BWN_READ_2(mac, BWN_SHM_DATA); 1722 goto out; 1723 } 1724 offset >>= 2; 1725 } 1726 bwn_shm_ctlword(mac, way, offset); 1727 ret = BWN_READ_4(mac, BWN_SHM_DATA); 1728 out: 1729 return (ret); 1730 } 1731 1732 uint16_t 1733 bwn_shm_read_2(struct bwn_mac *mac, uint16_t way, uint16_t offset) 1734 { 1735 uint16_t ret; 1736 1737 BWN_ASSERT_LOCKED(mac->mac_sc); 1738 1739 if (way == BWN_SHARED) { 1740 KASSERT((offset & 0x0001) == 0, 1741 ("%s:%d warn", __func__, __LINE__)); 1742 if (offset & 0x0003) { 1743 bwn_shm_ctlword(mac, way, offset >> 2); 1744 ret = BWN_READ_2(mac, BWN_SHM_DATA_UNALIGNED); 1745 goto out; 1746 } 1747 offset >>= 2; 1748 } 1749 bwn_shm_ctlword(mac, way, offset); 1750 ret = BWN_READ_2(mac, BWN_SHM_DATA); 1751 out: 1752 1753 return (ret); 1754 } 1755 1756 static void 1757 bwn_shm_ctlword(struct bwn_mac *mac, uint16_t way, 1758 uint16_t offset) 1759 { 1760 uint32_t control; 1761 1762 control = way; 1763 control <<= 16; 1764 control |= offset; 1765 BWN_WRITE_4(mac, BWN_SHM_CONTROL, control); 1766 } 1767 1768 void 1769 bwn_shm_write_4(struct bwn_mac *mac, uint16_t way, uint16_t offset, 1770 uint32_t value) 1771 { 1772 BWN_ASSERT_LOCKED(mac->mac_sc); 1773 1774 if (way == BWN_SHARED) { 1775 KASSERT((offset & 0x0001) == 0, 1776 ("%s:%d warn", __func__, __LINE__)); 1777 if (offset & 0x0003) { 1778 bwn_shm_ctlword(mac, way, offset >> 2); 1779 BWN_WRITE_2(mac, BWN_SHM_DATA_UNALIGNED, 1780 (value >> 16) & 0xffff); 1781 bwn_shm_ctlword(mac, way, (offset >> 2) + 1); 1782 BWN_WRITE_2(mac, BWN_SHM_DATA, value & 0xffff); 1783 return; 1784 } 1785 offset >>= 2; 1786 } 1787 bwn_shm_ctlword(mac, way, offset); 1788 BWN_WRITE_4(mac, BWN_SHM_DATA, value); 1789 } 1790 1791 void 1792 bwn_shm_write_2(struct bwn_mac *mac, uint16_t way, uint16_t offset, 1793 uint16_t value) 1794 { 1795 BWN_ASSERT_LOCKED(mac->mac_sc); 1796 1797 if (way == BWN_SHARED) { 1798 KASSERT((offset & 0x0001) == 0, 1799 ("%s:%d warn", __func__, __LINE__)); 1800 if (offset & 0x0003) { 1801 bwn_shm_ctlword(mac, way, offset >> 2); 1802 BWN_WRITE_2(mac, BWN_SHM_DATA_UNALIGNED, value); 1803 return; 1804 } 1805 offset >>= 2; 1806 } 1807 bwn_shm_ctlword(mac, way, offset); 1808 BWN_WRITE_2(mac, BWN_SHM_DATA, value); 1809 } 1810 1811 static void 1812 bwn_addchannels(struct ieee80211_channel chans[], int maxchans, int *nchans, 1813 const struct bwn_channelinfo *ci, const uint8_t bands[]) 1814 { 1815 int i, error; 1816 1817 for (i = 0, error = 0; i < ci->nchannels && error == 0; i++) { 1818 const struct bwn_channel *hc = &ci->channels[i]; 1819 1820 error = ieee80211_add_channel(chans, maxchans, nchans, 1821 hc->ieee, hc->freq, hc->maxTxPow, 0, bands); 1822 } 1823 } 1824 1825 static int 1826 bwn_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 1827 const struct ieee80211_bpf_params *params) 1828 { 1829 struct ieee80211com *ic = ni->ni_ic; 1830 struct bwn_softc *sc = ic->ic_softc; 1831 struct bwn_mac *mac = sc->sc_curmac; 1832 int error; 1833 1834 if ((sc->sc_flags & BWN_FLAG_RUNNING) == 0 || 1835 mac->mac_status < BWN_MAC_STATUS_STARTED) { 1836 m_freem(m); 1837 return (ENETDOWN); 1838 } 1839 1840 BWN_LOCK(sc); 1841 if (bwn_tx_isfull(sc, m)) { 1842 m_freem(m); 1843 BWN_UNLOCK(sc); 1844 return (ENOBUFS); 1845 } 1846 1847 error = bwn_tx_start(sc, ni, m); 1848 if (error == 0) 1849 sc->sc_watchdog_timer = 5; 1850 BWN_UNLOCK(sc); 1851 return (error); 1852 } 1853 1854 /* 1855 * Callback from the 802.11 layer to update the slot time 1856 * based on the current setting. We use it to notify the 1857 * firmware of ERP changes and the f/w takes care of things 1858 * like slot time and preamble. 1859 */ 1860 static void 1861 bwn_updateslot(struct ieee80211com *ic) 1862 { 1863 struct bwn_softc *sc = ic->ic_softc; 1864 struct bwn_mac *mac; 1865 1866 BWN_LOCK(sc); 1867 if (sc->sc_flags & BWN_FLAG_RUNNING) { 1868 mac = (struct bwn_mac *)sc->sc_curmac; 1869 bwn_set_slot_time(mac, IEEE80211_GET_SLOTTIME(ic)); 1870 } 1871 BWN_UNLOCK(sc); 1872 } 1873 1874 /* 1875 * Callback from the 802.11 layer after a promiscuous mode change. 1876 * Note this interface does not check the operating mode as this 1877 * is an internal callback and we are expected to honor the current 1878 * state (e.g. this is used for setting the interface in promiscuous 1879 * mode when operating in hostap mode to do ACS). 1880 */ 1881 static void 1882 bwn_update_promisc(struct ieee80211com *ic) 1883 { 1884 struct bwn_softc *sc = ic->ic_softc; 1885 struct bwn_mac *mac = sc->sc_curmac; 1886 1887 BWN_LOCK(sc); 1888 mac = sc->sc_curmac; 1889 if (mac != NULL && mac->mac_status >= BWN_MAC_STATUS_INITED) { 1890 if (ic->ic_promisc > 0) 1891 sc->sc_filters |= BWN_MACCTL_PROMISC; 1892 else 1893 sc->sc_filters &= ~BWN_MACCTL_PROMISC; 1894 bwn_set_opmode(mac); 1895 } 1896 BWN_UNLOCK(sc); 1897 } 1898 1899 /* 1900 * Callback from the 802.11 layer to update WME parameters. 1901 */ 1902 static int 1903 bwn_wme_update(struct ieee80211com *ic) 1904 { 1905 struct bwn_softc *sc = ic->ic_softc; 1906 struct bwn_mac *mac = sc->sc_curmac; 1907 struct chanAccParams chp; 1908 struct wmeParams *wmep; 1909 int i; 1910 1911 ieee80211_wme_ic_getparams(ic, &chp); 1912 1913 BWN_LOCK(sc); 1914 mac = sc->sc_curmac; 1915 if (mac != NULL && mac->mac_status >= BWN_MAC_STATUS_INITED) { 1916 bwn_mac_suspend(mac); 1917 for (i = 0; i < N(sc->sc_wmeParams); i++) { 1918 wmep = &chp.cap_wmeParams[i]; 1919 bwn_wme_loadparams(mac, wmep, bwn_wme_shm_offsets[i]); 1920 } 1921 bwn_mac_enable(mac); 1922 } 1923 BWN_UNLOCK(sc); 1924 return (0); 1925 } 1926 1927 static void 1928 bwn_scan_start(struct ieee80211com *ic) 1929 { 1930 struct bwn_softc *sc = ic->ic_softc; 1931 struct bwn_mac *mac; 1932 1933 BWN_LOCK(sc); 1934 mac = sc->sc_curmac; 1935 if (mac != NULL && mac->mac_status >= BWN_MAC_STATUS_INITED) { 1936 sc->sc_filters |= BWN_MACCTL_BEACON_PROMISC; 1937 bwn_set_opmode(mac); 1938 /* disable CFP update during scan */ 1939 bwn_hf_write(mac, bwn_hf_read(mac) | BWN_HF_SKIP_CFP_UPDATE); 1940 } 1941 BWN_UNLOCK(sc); 1942 } 1943 1944 static void 1945 bwn_scan_end(struct ieee80211com *ic) 1946 { 1947 struct bwn_softc *sc = ic->ic_softc; 1948 struct bwn_mac *mac; 1949 1950 BWN_LOCK(sc); 1951 mac = sc->sc_curmac; 1952 if (mac != NULL && mac->mac_status >= BWN_MAC_STATUS_INITED) { 1953 sc->sc_filters &= ~BWN_MACCTL_BEACON_PROMISC; 1954 bwn_set_opmode(mac); 1955 bwn_hf_write(mac, bwn_hf_read(mac) & ~BWN_HF_SKIP_CFP_UPDATE); 1956 } 1957 BWN_UNLOCK(sc); 1958 } 1959 1960 static void 1961 bwn_set_channel(struct ieee80211com *ic) 1962 { 1963 struct bwn_softc *sc = ic->ic_softc; 1964 struct bwn_mac *mac = sc->sc_curmac; 1965 struct bwn_phy *phy = &mac->mac_phy; 1966 int chan, error; 1967 1968 BWN_LOCK(sc); 1969 1970 error = bwn_switch_band(sc, ic->ic_curchan); 1971 if (error) 1972 goto fail; 1973 bwn_mac_suspend(mac); 1974 bwn_set_txretry(mac, BWN_RETRY_SHORT, BWN_RETRY_LONG); 1975 chan = ieee80211_chan2ieee(ic, ic->ic_curchan); 1976 if (chan != phy->chan) 1977 bwn_switch_channel(mac, chan); 1978 1979 /* TX power level */ 1980 if (ic->ic_curchan->ic_maxpower != 0 && 1981 ic->ic_curchan->ic_maxpower != phy->txpower) { 1982 phy->txpower = ic->ic_curchan->ic_maxpower / 2; 1983 bwn_phy_txpower_check(mac, BWN_TXPWR_IGNORE_TIME | 1984 BWN_TXPWR_IGNORE_TSSI); 1985 } 1986 1987 bwn_set_txantenna(mac, BWN_ANT_DEFAULT); 1988 if (phy->set_antenna) 1989 phy->set_antenna(mac, BWN_ANT_DEFAULT); 1990 1991 if (sc->sc_rf_enabled != phy->rf_on) { 1992 if (sc->sc_rf_enabled) { 1993 bwn_rf_turnon(mac); 1994 if (!(mac->mac_flags & BWN_MAC_FLAG_RADIO_ON)) 1995 device_printf(sc->sc_dev, 1996 "please turn on the RF switch\n"); 1997 } else 1998 bwn_rf_turnoff(mac); 1999 } 2000 2001 bwn_mac_enable(mac); 2002 2003 fail: 2004 BWN_UNLOCK(sc); 2005 } 2006 2007 static struct ieee80211vap * 2008 bwn_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 2009 enum ieee80211_opmode opmode, int flags, 2010 const uint8_t bssid[IEEE80211_ADDR_LEN], 2011 const uint8_t mac[IEEE80211_ADDR_LEN]) 2012 { 2013 struct ieee80211vap *vap; 2014 struct bwn_vap *bvp; 2015 2016 switch (opmode) { 2017 case IEEE80211_M_HOSTAP: 2018 case IEEE80211_M_MBSS: 2019 case IEEE80211_M_STA: 2020 case IEEE80211_M_WDS: 2021 case IEEE80211_M_MONITOR: 2022 case IEEE80211_M_IBSS: 2023 case IEEE80211_M_AHDEMO: 2024 break; 2025 default: 2026 return (NULL); 2027 } 2028 2029 bvp = malloc(sizeof(struct bwn_vap), M_80211_VAP, M_WAITOK | M_ZERO); 2030 vap = &bvp->bv_vap; 2031 ieee80211_vap_setup(ic, vap, name, unit, opmode, flags, bssid); 2032 /* override with driver methods */ 2033 bvp->bv_newstate = vap->iv_newstate; 2034 vap->iv_newstate = bwn_newstate; 2035 2036 /* override max aid so sta's cannot assoc when we're out of sta id's */ 2037 vap->iv_max_aid = BWN_STAID_MAX; 2038 2039 ieee80211_ratectl_init(vap); 2040 2041 /* complete setup */ 2042 ieee80211_vap_attach(vap, ieee80211_media_change, 2043 ieee80211_media_status, mac); 2044 return (vap); 2045 } 2046 2047 static void 2048 bwn_vap_delete(struct ieee80211vap *vap) 2049 { 2050 struct bwn_vap *bvp = BWN_VAP(vap); 2051 2052 ieee80211_ratectl_deinit(vap); 2053 ieee80211_vap_detach(vap); 2054 free(bvp, M_80211_VAP); 2055 } 2056 2057 static int 2058 bwn_init(struct bwn_softc *sc) 2059 { 2060 struct bwn_mac *mac; 2061 int error; 2062 2063 BWN_ASSERT_LOCKED(sc); 2064 2065 DPRINTF(sc, BWN_DEBUG_RESET, "%s: called\n", __func__); 2066 2067 bzero(sc->sc_bssid, IEEE80211_ADDR_LEN); 2068 sc->sc_flags |= BWN_FLAG_NEED_BEACON_TP; 2069 sc->sc_filters = 0; 2070 bwn_wme_clear(sc); 2071 sc->sc_beacons[0] = sc->sc_beacons[1] = 0; 2072 sc->sc_rf_enabled = 1; 2073 2074 mac = sc->sc_curmac; 2075 if (mac->mac_status == BWN_MAC_STATUS_UNINIT) { 2076 error = bwn_core_init(mac); 2077 if (error != 0) 2078 return (error); 2079 } 2080 if (mac->mac_status == BWN_MAC_STATUS_INITED) 2081 bwn_core_start(mac); 2082 2083 bwn_set_opmode(mac); 2084 bwn_set_pretbtt(mac); 2085 bwn_spu_setdelay(mac, 0); 2086 bwn_set_macaddr(mac); 2087 2088 sc->sc_flags |= BWN_FLAG_RUNNING; 2089 callout_reset(&sc->sc_rfswitch_ch, hz, bwn_rfswitch, sc); 2090 callout_reset(&sc->sc_watchdog_ch, hz, bwn_watchdog, sc); 2091 2092 return (0); 2093 } 2094 2095 static void 2096 bwn_stop(struct bwn_softc *sc) 2097 { 2098 struct bwn_mac *mac = sc->sc_curmac; 2099 2100 BWN_ASSERT_LOCKED(sc); 2101 2102 DPRINTF(sc, BWN_DEBUG_RESET, "%s: called\n", __func__); 2103 2104 if (mac->mac_status >= BWN_MAC_STATUS_INITED) { 2105 /* XXX FIXME opmode not based on VAP */ 2106 bwn_set_opmode(mac); 2107 bwn_set_macaddr(mac); 2108 } 2109 2110 if (mac->mac_status >= BWN_MAC_STATUS_STARTED) 2111 bwn_core_stop(mac); 2112 2113 callout_stop(&sc->sc_led_blink_ch); 2114 sc->sc_led_blinking = 0; 2115 2116 bwn_core_exit(mac); 2117 sc->sc_rf_enabled = 0; 2118 2119 sc->sc_flags &= ~BWN_FLAG_RUNNING; 2120 } 2121 2122 static void 2123 bwn_wme_clear(struct bwn_softc *sc) 2124 { 2125 #define MS(_v, _f) (((_v) & _f) >> _f##_S) 2126 struct wmeParams *p; 2127 unsigned int i; 2128 2129 KASSERT(N(bwn_wme_shm_offsets) == N(sc->sc_wmeParams), 2130 ("%s:%d: fail", __func__, __LINE__)); 2131 2132 for (i = 0; i < N(sc->sc_wmeParams); i++) { 2133 p = &(sc->sc_wmeParams[i]); 2134 2135 switch (bwn_wme_shm_offsets[i]) { 2136 case BWN_WME_VOICE: 2137 p->wmep_txopLimit = 0; 2138 p->wmep_aifsn = 2; 2139 /* XXX FIXME: log2(cwmin) */ 2140 p->wmep_logcwmin = MS(0x0001, WME_PARAM_LOGCWMIN); 2141 p->wmep_logcwmax = MS(0x0001, WME_PARAM_LOGCWMAX); 2142 break; 2143 case BWN_WME_VIDEO: 2144 p->wmep_txopLimit = 0; 2145 p->wmep_aifsn = 2; 2146 /* XXX FIXME: log2(cwmin) */ 2147 p->wmep_logcwmin = MS(0x0001, WME_PARAM_LOGCWMIN); 2148 p->wmep_logcwmax = MS(0x0001, WME_PARAM_LOGCWMAX); 2149 break; 2150 case BWN_WME_BESTEFFORT: 2151 p->wmep_txopLimit = 0; 2152 p->wmep_aifsn = 3; 2153 /* XXX FIXME: log2(cwmin) */ 2154 p->wmep_logcwmin = MS(0x0001, WME_PARAM_LOGCWMIN); 2155 p->wmep_logcwmax = MS(0x03ff, WME_PARAM_LOGCWMAX); 2156 break; 2157 case BWN_WME_BACKGROUND: 2158 p->wmep_txopLimit = 0; 2159 p->wmep_aifsn = 7; 2160 /* XXX FIXME: log2(cwmin) */ 2161 p->wmep_logcwmin = MS(0x0001, WME_PARAM_LOGCWMIN); 2162 p->wmep_logcwmax = MS(0x03ff, WME_PARAM_LOGCWMAX); 2163 break; 2164 default: 2165 KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__)); 2166 } 2167 } 2168 } 2169 2170 static int 2171 bwn_core_forceclk(struct bwn_mac *mac, bool force) 2172 { 2173 struct bwn_softc *sc; 2174 bhnd_clock clock; 2175 int error; 2176 2177 sc = mac->mac_sc; 2178 2179 /* On PMU equipped devices, we do not need to force the HT clock */ 2180 if (sc->sc_pmu != NULL) 2181 return (0); 2182 2183 /* Issue a PMU clock request */ 2184 if (force) 2185 clock = BHND_CLOCK_HT; 2186 else 2187 clock = BHND_CLOCK_DYN; 2188 2189 if ((error = bhnd_request_clock(sc->sc_dev, clock))) { 2190 device_printf(sc->sc_dev, "%d clock request failed: %d\n", 2191 clock, error); 2192 return (error); 2193 } 2194 2195 return (0); 2196 } 2197 2198 static int 2199 bwn_core_init(struct bwn_mac *mac) 2200 { 2201 struct bwn_softc *sc = mac->mac_sc; 2202 uint64_t hf; 2203 int error; 2204 2205 KASSERT(mac->mac_status == BWN_MAC_STATUS_UNINIT, 2206 ("%s:%d: fail", __func__, __LINE__)); 2207 2208 DPRINTF(mac->mac_sc, BWN_DEBUG_RESET, "%s: called\n", __func__); 2209 2210 if ((error = bwn_core_forceclk(mac, true))) 2211 return (error); 2212 2213 if (bhnd_is_hw_suspended(sc->sc_dev)) { 2214 if ((error = bwn_reset_core(mac, mac->mac_phy.gmode))) 2215 goto fail0; 2216 } 2217 2218 mac->mac_flags &= ~BWN_MAC_FLAG_DFQVALID; 2219 mac->mac_flags |= BWN_MAC_FLAG_RADIO_ON; 2220 mac->mac_phy.hwpctl = (bwn_hwpctl) ? 1 : 0; 2221 BWN_GETTIME(mac->mac_phy.nexttime); 2222 mac->mac_phy.txerrors = BWN_TXERROR_MAX; 2223 bzero(&mac->mac_stats, sizeof(mac->mac_stats)); 2224 mac->mac_stats.link_noise = -95; 2225 mac->mac_reason_intr = 0; 2226 bzero(mac->mac_reason, sizeof(mac->mac_reason)); 2227 mac->mac_intr_mask = BWN_INTR_MASKTEMPLATE; 2228 #ifdef BWN_DEBUG 2229 if (sc->sc_debug & BWN_DEBUG_XMIT) 2230 mac->mac_intr_mask &= ~BWN_INTR_PHY_TXERR; 2231 #endif 2232 mac->mac_suspended = 1; 2233 mac->mac_task_state = 0; 2234 memset(&mac->mac_noise, 0, sizeof(mac->mac_noise)); 2235 2236 mac->mac_phy.init_pre(mac); 2237 2238 bwn_bt_disable(mac); 2239 if (mac->mac_phy.prepare_hw) { 2240 error = mac->mac_phy.prepare_hw(mac); 2241 if (error) 2242 goto fail0; 2243 } 2244 DPRINTF(mac->mac_sc, BWN_DEBUG_RESET, "%s: chip_init\n", __func__); 2245 error = bwn_chip_init(mac); 2246 if (error) 2247 goto fail0; 2248 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_COREREV, 2249 bhnd_get_hwrev(sc->sc_dev)); 2250 hf = bwn_hf_read(mac); 2251 if (mac->mac_phy.type == BWN_PHYTYPE_G) { 2252 hf |= BWN_HF_GPHY_SYM_WORKAROUND; 2253 if (sc->sc_board_info.board_flags & BHND_BFL_PACTRL) 2254 hf |= BWN_HF_PAGAINBOOST_OFDM_ON; 2255 if (mac->mac_phy.rev == 1) 2256 hf |= BWN_HF_GPHY_DC_CANCELFILTER; 2257 } 2258 if (mac->mac_phy.rf_ver == 0x2050) { 2259 if (mac->mac_phy.rf_rev < 6) 2260 hf |= BWN_HF_FORCE_VCO_RECALC; 2261 if (mac->mac_phy.rf_rev == 6) 2262 hf |= BWN_HF_4318_TSSI; 2263 } 2264 if (sc->sc_board_info.board_flags & BHND_BFL_NOPLLDOWN) 2265 hf |= BWN_HF_SLOWCLOCK_REQ_OFF; 2266 if (sc->sc_quirks & BWN_QUIRK_UCODE_SLOWCLOCK_WAR) 2267 hf |= BWN_HF_PCI_SLOWCLOCK_WORKAROUND; 2268 hf &= ~BWN_HF_SKIP_CFP_UPDATE; 2269 bwn_hf_write(mac, hf); 2270 2271 /* Tell the firmware about the MAC capabilities */ 2272 if (bhnd_get_hwrev(sc->sc_dev) >= 13) { 2273 uint32_t cap; 2274 cap = BWN_READ_4(mac, BWN_MAC_HW_CAP); 2275 DPRINTF(sc, BWN_DEBUG_RESET, 2276 "%s: hw capabilities: 0x%08x\n", 2277 __func__, cap); 2278 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_MACHW_L, 2279 cap & 0xffff); 2280 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_MACHW_H, 2281 (cap >> 16) & 0xffff); 2282 } 2283 2284 bwn_set_txretry(mac, BWN_RETRY_SHORT, BWN_RETRY_LONG); 2285 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_SHORT_RETRY_FALLBACK, 3); 2286 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_LONG_RETRY_FALLBACK, 2); 2287 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_PROBE_RESP_MAXTIME, 1); 2288 2289 bwn_rate_init(mac); 2290 bwn_set_phytxctl(mac); 2291 2292 bwn_shm_write_2(mac, BWN_SCRATCH, BWN_SCRATCH_CONT_MIN, 2293 (mac->mac_phy.type == BWN_PHYTYPE_B) ? 0x1f : 0xf); 2294 bwn_shm_write_2(mac, BWN_SCRATCH, BWN_SCRATCH_CONT_MAX, 0x3ff); 2295 2296 if (sc->sc_quirks & BWN_QUIRK_NODMA) 2297 bwn_pio_init(mac); 2298 else 2299 bwn_dma_init(mac); 2300 bwn_wme_init(mac); 2301 bwn_spu_setdelay(mac, 1); 2302 bwn_bt_enable(mac); 2303 2304 DPRINTF(mac->mac_sc, BWN_DEBUG_RESET, "%s: powerup\n", __func__); 2305 if (sc->sc_board_info.board_flags & BHND_BFL_NOPLLDOWN) 2306 bwn_core_forceclk(mac, true); 2307 else 2308 bwn_core_forceclk(mac, false); 2309 2310 bwn_set_macaddr(mac); 2311 bwn_crypt_init(mac); 2312 2313 /* XXX LED initializatin */ 2314 2315 mac->mac_status = BWN_MAC_STATUS_INITED; 2316 2317 DPRINTF(mac->mac_sc, BWN_DEBUG_RESET, "%s: done\n", __func__); 2318 return (error); 2319 2320 fail0: 2321 bhnd_suspend_hw(sc->sc_dev, 0); 2322 KASSERT(mac->mac_status == BWN_MAC_STATUS_UNINIT, 2323 ("%s:%d: fail", __func__, __LINE__)); 2324 DPRINTF(mac->mac_sc, BWN_DEBUG_RESET, "%s: fail\n", __func__); 2325 return (error); 2326 } 2327 2328 static void 2329 bwn_core_start(struct bwn_mac *mac) 2330 { 2331 struct bwn_softc *sc = mac->mac_sc; 2332 uint32_t tmp; 2333 2334 KASSERT(mac->mac_status == BWN_MAC_STATUS_INITED, 2335 ("%s:%d: fail", __func__, __LINE__)); 2336 2337 if (bhnd_get_hwrev(sc->sc_dev) < 5) 2338 return; 2339 2340 while (1) { 2341 tmp = BWN_READ_4(mac, BWN_XMITSTAT_0); 2342 if (!(tmp & 0x00000001)) 2343 break; 2344 tmp = BWN_READ_4(mac, BWN_XMITSTAT_1); 2345 } 2346 2347 bwn_mac_enable(mac); 2348 BWN_WRITE_4(mac, BWN_INTR_MASK, mac->mac_intr_mask); 2349 callout_reset(&sc->sc_task_ch, hz * 15, bwn_tasks, mac); 2350 2351 mac->mac_status = BWN_MAC_STATUS_STARTED; 2352 } 2353 2354 static void 2355 bwn_core_exit(struct bwn_mac *mac) 2356 { 2357 struct bwn_softc *sc = mac->mac_sc; 2358 uint32_t macctl; 2359 2360 BWN_ASSERT_LOCKED(mac->mac_sc); 2361 2362 KASSERT(mac->mac_status <= BWN_MAC_STATUS_INITED, 2363 ("%s:%d: fail", __func__, __LINE__)); 2364 2365 if (mac->mac_status != BWN_MAC_STATUS_INITED) 2366 return; 2367 mac->mac_status = BWN_MAC_STATUS_UNINIT; 2368 2369 macctl = BWN_READ_4(mac, BWN_MACCTL); 2370 macctl &= ~BWN_MACCTL_MCODE_RUN; 2371 macctl |= BWN_MACCTL_MCODE_JMP0; 2372 BWN_WRITE_4(mac, BWN_MACCTL, macctl); 2373 2374 bwn_dma_stop(mac); 2375 bwn_pio_stop(mac); 2376 bwn_chip_exit(mac); 2377 mac->mac_phy.switch_analog(mac, 0); 2378 bhnd_suspend_hw(sc->sc_dev, 0); 2379 } 2380 2381 static void 2382 bwn_bt_disable(struct bwn_mac *mac) 2383 { 2384 struct bwn_softc *sc = mac->mac_sc; 2385 2386 (void)sc; 2387 /* XXX do nothing yet */ 2388 } 2389 2390 static int 2391 bwn_chip_init(struct bwn_mac *mac) 2392 { 2393 struct bwn_softc *sc = mac->mac_sc; 2394 struct bwn_phy *phy = &mac->mac_phy; 2395 uint32_t macctl; 2396 u_int delay; 2397 int error; 2398 2399 macctl = BWN_MACCTL_IHR_ON | BWN_MACCTL_SHM_ON | BWN_MACCTL_STA; 2400 if (phy->gmode) 2401 macctl |= BWN_MACCTL_GMODE; 2402 BWN_WRITE_4(mac, BWN_MACCTL, macctl); 2403 2404 error = bwn_fw_fillinfo(mac); 2405 if (error) 2406 return (error); 2407 error = bwn_fw_loaducode(mac); 2408 if (error) 2409 return (error); 2410 2411 error = bwn_gpio_init(mac); 2412 if (error) 2413 return (error); 2414 2415 error = bwn_fw_loadinitvals(mac); 2416 if (error) 2417 return (error); 2418 2419 phy->switch_analog(mac, 1); 2420 error = bwn_phy_init(mac); 2421 if (error) 2422 return (error); 2423 2424 if (phy->set_im) 2425 phy->set_im(mac, BWN_IMMODE_NONE); 2426 if (phy->set_antenna) 2427 phy->set_antenna(mac, BWN_ANT_DEFAULT); 2428 bwn_set_txantenna(mac, BWN_ANT_DEFAULT); 2429 2430 if (phy->type == BWN_PHYTYPE_B) 2431 BWN_WRITE_2(mac, 0x005e, BWN_READ_2(mac, 0x005e) | 0x0004); 2432 BWN_WRITE_4(mac, 0x0100, 0x01000000); 2433 if (bhnd_get_hwrev(sc->sc_dev) < 5) 2434 BWN_WRITE_4(mac, 0x010c, 0x01000000); 2435 2436 BWN_WRITE_4(mac, BWN_MACCTL, 2437 BWN_READ_4(mac, BWN_MACCTL) & ~BWN_MACCTL_STA); 2438 BWN_WRITE_4(mac, BWN_MACCTL, 2439 BWN_READ_4(mac, BWN_MACCTL) | BWN_MACCTL_STA); 2440 bwn_shm_write_2(mac, BWN_SHARED, 0x0074, 0x0000); 2441 2442 bwn_set_opmode(mac); 2443 if (bhnd_get_hwrev(sc->sc_dev) < 3) { 2444 BWN_WRITE_2(mac, 0x060e, 0x0000); 2445 BWN_WRITE_2(mac, 0x0610, 0x8000); 2446 BWN_WRITE_2(mac, 0x0604, 0x0000); 2447 BWN_WRITE_2(mac, 0x0606, 0x0200); 2448 } else { 2449 BWN_WRITE_4(mac, 0x0188, 0x80000000); 2450 BWN_WRITE_4(mac, 0x018c, 0x02000000); 2451 } 2452 BWN_WRITE_4(mac, BWN_INTR_REASON, 0x00004000); 2453 BWN_WRITE_4(mac, BWN_DMA0_INTR_MASK, 0x0001dc00); 2454 BWN_WRITE_4(mac, BWN_DMA1_INTR_MASK, 0x0000dc00); 2455 BWN_WRITE_4(mac, BWN_DMA2_INTR_MASK, 0x0000dc00); 2456 BWN_WRITE_4(mac, BWN_DMA3_INTR_MASK, 0x0001dc00); 2457 BWN_WRITE_4(mac, BWN_DMA4_INTR_MASK, 0x0000dc00); 2458 BWN_WRITE_4(mac, BWN_DMA5_INTR_MASK, 0x0000dc00); 2459 2460 bwn_mac_phy_clock_set(mac, true); 2461 2462 /* Provide the HT clock transition latency to the MAC core */ 2463 error = bhnd_get_clock_latency(sc->sc_dev, BHND_CLOCK_HT, &delay); 2464 if (error) { 2465 device_printf(sc->sc_dev, "failed to fetch HT clock latency: " 2466 "%d\n", error); 2467 return (error); 2468 } 2469 2470 if (delay > UINT16_MAX) { 2471 device_printf(sc->sc_dev, "invalid HT clock latency: %u\n", 2472 delay); 2473 return (ENXIO); 2474 } 2475 2476 BWN_WRITE_2(mac, BWN_POWERUP_DELAY, delay); 2477 return (0); 2478 } 2479 2480 /* read hostflags */ 2481 uint64_t 2482 bwn_hf_read(struct bwn_mac *mac) 2483 { 2484 uint64_t ret; 2485 2486 ret = bwn_shm_read_2(mac, BWN_SHARED, BWN_SHARED_HFHI); 2487 ret <<= 16; 2488 ret |= bwn_shm_read_2(mac, BWN_SHARED, BWN_SHARED_HFMI); 2489 ret <<= 16; 2490 ret |= bwn_shm_read_2(mac, BWN_SHARED, BWN_SHARED_HFLO); 2491 return (ret); 2492 } 2493 2494 void 2495 bwn_hf_write(struct bwn_mac *mac, uint64_t value) 2496 { 2497 2498 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_HFLO, 2499 (value & 0x00000000ffffull)); 2500 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_HFMI, 2501 (value & 0x0000ffff0000ull) >> 16); 2502 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_HFHI, 2503 (value & 0xffff00000000ULL) >> 32); 2504 } 2505 2506 static void 2507 bwn_set_txretry(struct bwn_mac *mac, int s, int l) 2508 { 2509 2510 bwn_shm_write_2(mac, BWN_SCRATCH, BWN_SCRATCH_SHORT_RETRY, MIN(s, 0xf)); 2511 bwn_shm_write_2(mac, BWN_SCRATCH, BWN_SCRATCH_LONG_RETRY, MIN(l, 0xf)); 2512 } 2513 2514 static void 2515 bwn_rate_init(struct bwn_mac *mac) 2516 { 2517 2518 switch (mac->mac_phy.type) { 2519 case BWN_PHYTYPE_A: 2520 case BWN_PHYTYPE_G: 2521 case BWN_PHYTYPE_LP: 2522 case BWN_PHYTYPE_N: 2523 bwn_rate_write(mac, BWN_OFDM_RATE_6MB, 1); 2524 bwn_rate_write(mac, BWN_OFDM_RATE_12MB, 1); 2525 bwn_rate_write(mac, BWN_OFDM_RATE_18MB, 1); 2526 bwn_rate_write(mac, BWN_OFDM_RATE_24MB, 1); 2527 bwn_rate_write(mac, BWN_OFDM_RATE_36MB, 1); 2528 bwn_rate_write(mac, BWN_OFDM_RATE_48MB, 1); 2529 bwn_rate_write(mac, BWN_OFDM_RATE_54MB, 1); 2530 if (mac->mac_phy.type == BWN_PHYTYPE_A) 2531 break; 2532 /* FALLTHROUGH */ 2533 case BWN_PHYTYPE_B: 2534 bwn_rate_write(mac, BWN_CCK_RATE_1MB, 0); 2535 bwn_rate_write(mac, BWN_CCK_RATE_2MB, 0); 2536 bwn_rate_write(mac, BWN_CCK_RATE_5MB, 0); 2537 bwn_rate_write(mac, BWN_CCK_RATE_11MB, 0); 2538 break; 2539 default: 2540 KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__)); 2541 } 2542 } 2543 2544 static void 2545 bwn_rate_write(struct bwn_mac *mac, uint16_t rate, int ofdm) 2546 { 2547 uint16_t offset; 2548 2549 if (ofdm) { 2550 offset = 0x480; 2551 offset += (bwn_plcp_getofdm(rate) & 0x000f) * 2; 2552 } else { 2553 offset = 0x4c0; 2554 offset += (bwn_plcp_getcck(rate) & 0x000f) * 2; 2555 } 2556 bwn_shm_write_2(mac, BWN_SHARED, offset + 0x20, 2557 bwn_shm_read_2(mac, BWN_SHARED, offset)); 2558 } 2559 2560 static uint8_t 2561 bwn_plcp_getcck(const uint8_t bitrate) 2562 { 2563 2564 switch (bitrate) { 2565 case BWN_CCK_RATE_1MB: 2566 return (0x0a); 2567 case BWN_CCK_RATE_2MB: 2568 return (0x14); 2569 case BWN_CCK_RATE_5MB: 2570 return (0x37); 2571 case BWN_CCK_RATE_11MB: 2572 return (0x6e); 2573 } 2574 KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__)); 2575 return (0); 2576 } 2577 2578 static uint8_t 2579 bwn_plcp_getofdm(const uint8_t bitrate) 2580 { 2581 2582 switch (bitrate) { 2583 case BWN_OFDM_RATE_6MB: 2584 return (0xb); 2585 case BWN_OFDM_RATE_9MB: 2586 return (0xf); 2587 case BWN_OFDM_RATE_12MB: 2588 return (0xa); 2589 case BWN_OFDM_RATE_18MB: 2590 return (0xe); 2591 case BWN_OFDM_RATE_24MB: 2592 return (0x9); 2593 case BWN_OFDM_RATE_36MB: 2594 return (0xd); 2595 case BWN_OFDM_RATE_48MB: 2596 return (0x8); 2597 case BWN_OFDM_RATE_54MB: 2598 return (0xc); 2599 } 2600 KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__)); 2601 return (0); 2602 } 2603 2604 static void 2605 bwn_set_phytxctl(struct bwn_mac *mac) 2606 { 2607 uint16_t ctl; 2608 2609 ctl = (BWN_TX_PHY_ENC_CCK | BWN_TX_PHY_ANT01AUTO | 2610 BWN_TX_PHY_TXPWR); 2611 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_BEACON_PHYCTL, ctl); 2612 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_ACKCTS_PHYCTL, ctl); 2613 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_PROBE_RESP_PHYCTL, ctl); 2614 } 2615 2616 static void 2617 bwn_pio_init(struct bwn_mac *mac) 2618 { 2619 struct bwn_pio *pio = &mac->mac_method.pio; 2620 2621 BWN_WRITE_4(mac, BWN_MACCTL, BWN_READ_4(mac, BWN_MACCTL) 2622 & ~BWN_MACCTL_BIGENDIAN); 2623 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_RX_PADOFFSET, 0); 2624 2625 bwn_pio_set_txqueue(mac, &pio->wme[WME_AC_BK], 0); 2626 bwn_pio_set_txqueue(mac, &pio->wme[WME_AC_BE], 1); 2627 bwn_pio_set_txqueue(mac, &pio->wme[WME_AC_VI], 2); 2628 bwn_pio_set_txqueue(mac, &pio->wme[WME_AC_VO], 3); 2629 bwn_pio_set_txqueue(mac, &pio->mcast, 4); 2630 bwn_pio_setupqueue_rx(mac, &pio->rx, 0); 2631 } 2632 2633 static void 2634 bwn_pio_set_txqueue(struct bwn_mac *mac, struct bwn_pio_txqueue *tq, 2635 int index) 2636 { 2637 struct bwn_pio_txpkt *tp; 2638 struct bwn_softc *sc = mac->mac_sc; 2639 unsigned int i; 2640 2641 tq->tq_base = bwn_pio_idx2base(mac, index) + BWN_PIO_TXQOFFSET(mac); 2642 tq->tq_index = index; 2643 2644 tq->tq_free = BWN_PIO_MAX_TXPACKETS; 2645 if (bhnd_get_hwrev(sc->sc_dev) >= 8) 2646 tq->tq_size = 1920; 2647 else { 2648 tq->tq_size = bwn_pio_read_2(mac, tq, BWN_PIO_TXQBUFSIZE); 2649 tq->tq_size -= 80; 2650 } 2651 2652 TAILQ_INIT(&tq->tq_pktlist); 2653 for (i = 0; i < N(tq->tq_pkts); i++) { 2654 tp = &(tq->tq_pkts[i]); 2655 tp->tp_index = i; 2656 tp->tp_queue = tq; 2657 TAILQ_INSERT_TAIL(&tq->tq_pktlist, tp, tp_list); 2658 } 2659 } 2660 2661 static uint16_t 2662 bwn_pio_idx2base(struct bwn_mac *mac, int index) 2663 { 2664 struct bwn_softc *sc = mac->mac_sc; 2665 static const uint16_t bases[] = { 2666 BWN_PIO_BASE0, 2667 BWN_PIO_BASE1, 2668 BWN_PIO_BASE2, 2669 BWN_PIO_BASE3, 2670 BWN_PIO_BASE4, 2671 BWN_PIO_BASE5, 2672 BWN_PIO_BASE6, 2673 BWN_PIO_BASE7, 2674 }; 2675 static const uint16_t bases_rev11[] = { 2676 BWN_PIO11_BASE0, 2677 BWN_PIO11_BASE1, 2678 BWN_PIO11_BASE2, 2679 BWN_PIO11_BASE3, 2680 BWN_PIO11_BASE4, 2681 BWN_PIO11_BASE5, 2682 }; 2683 2684 if (bhnd_get_hwrev(sc->sc_dev) >= 11) { 2685 if (index >= N(bases_rev11)) 2686 device_printf(sc->sc_dev, "%s: warning\n", __func__); 2687 return (bases_rev11[index]); 2688 } 2689 if (index >= N(bases)) 2690 device_printf(sc->sc_dev, "%s: warning\n", __func__); 2691 return (bases[index]); 2692 } 2693 2694 static void 2695 bwn_pio_setupqueue_rx(struct bwn_mac *mac, struct bwn_pio_rxqueue *prq, 2696 int index) 2697 { 2698 struct bwn_softc *sc = mac->mac_sc; 2699 2700 prq->prq_mac = mac; 2701 prq->prq_rev = bhnd_get_hwrev(sc->sc_dev); 2702 prq->prq_base = bwn_pio_idx2base(mac, index) + BWN_PIO_RXQOFFSET(mac); 2703 bwn_dma_rxdirectfifo(mac, index, 1); 2704 } 2705 2706 static void 2707 bwn_destroy_pioqueue_tx(struct bwn_pio_txqueue *tq) 2708 { 2709 if (tq == NULL) 2710 return; 2711 bwn_pio_cancel_tx_packets(tq); 2712 } 2713 2714 static void 2715 bwn_destroy_queue_tx(struct bwn_pio_txqueue *pio) 2716 { 2717 2718 bwn_destroy_pioqueue_tx(pio); 2719 } 2720 2721 static uint16_t 2722 bwn_pio_read_2(struct bwn_mac *mac, struct bwn_pio_txqueue *tq, 2723 uint16_t offset) 2724 { 2725 2726 return (BWN_READ_2(mac, tq->tq_base + offset)); 2727 } 2728 2729 static void 2730 bwn_dma_rxdirectfifo(struct bwn_mac *mac, int idx, uint8_t enable) 2731 { 2732 uint32_t ctl; 2733 uint16_t base; 2734 2735 base = bwn_dma_base(mac->mac_dmatype, idx); 2736 if (mac->mac_dmatype == BHND_DMA_ADDR_64BIT) { 2737 ctl = BWN_READ_4(mac, base + BWN_DMA64_RXCTL); 2738 ctl &= ~BWN_DMA64_RXDIRECTFIFO; 2739 if (enable) 2740 ctl |= BWN_DMA64_RXDIRECTFIFO; 2741 BWN_WRITE_4(mac, base + BWN_DMA64_RXCTL, ctl); 2742 } else { 2743 ctl = BWN_READ_4(mac, base + BWN_DMA32_RXCTL); 2744 ctl &= ~BWN_DMA32_RXDIRECTFIFO; 2745 if (enable) 2746 ctl |= BWN_DMA32_RXDIRECTFIFO; 2747 BWN_WRITE_4(mac, base + BWN_DMA32_RXCTL, ctl); 2748 } 2749 } 2750 2751 static void 2752 bwn_pio_cancel_tx_packets(struct bwn_pio_txqueue *tq) 2753 { 2754 struct bwn_pio_txpkt *tp; 2755 unsigned int i; 2756 2757 for (i = 0; i < N(tq->tq_pkts); i++) { 2758 tp = &(tq->tq_pkts[i]); 2759 if (tp->tp_m) { 2760 m_freem(tp->tp_m); 2761 tp->tp_m = NULL; 2762 } 2763 } 2764 } 2765 2766 static uint16_t 2767 bwn_dma_base(int type, int controller_idx) 2768 { 2769 static const uint16_t map64[] = { 2770 BWN_DMA64_BASE0, 2771 BWN_DMA64_BASE1, 2772 BWN_DMA64_BASE2, 2773 BWN_DMA64_BASE3, 2774 BWN_DMA64_BASE4, 2775 BWN_DMA64_BASE5, 2776 }; 2777 static const uint16_t map32[] = { 2778 BWN_DMA32_BASE0, 2779 BWN_DMA32_BASE1, 2780 BWN_DMA32_BASE2, 2781 BWN_DMA32_BASE3, 2782 BWN_DMA32_BASE4, 2783 BWN_DMA32_BASE5, 2784 }; 2785 2786 if (type == BHND_DMA_ADDR_64BIT) { 2787 KASSERT(controller_idx >= 0 && controller_idx < N(map64), 2788 ("%s:%d: fail", __func__, __LINE__)); 2789 return (map64[controller_idx]); 2790 } 2791 KASSERT(controller_idx >= 0 && controller_idx < N(map32), 2792 ("%s:%d: fail", __func__, __LINE__)); 2793 return (map32[controller_idx]); 2794 } 2795 2796 static void 2797 bwn_dma_init(struct bwn_mac *mac) 2798 { 2799 struct bwn_dma *dma = &mac->mac_method.dma; 2800 2801 /* setup TX DMA channels. */ 2802 bwn_dma_setup(dma->wme[WME_AC_BK]); 2803 bwn_dma_setup(dma->wme[WME_AC_BE]); 2804 bwn_dma_setup(dma->wme[WME_AC_VI]); 2805 bwn_dma_setup(dma->wme[WME_AC_VO]); 2806 bwn_dma_setup(dma->mcast); 2807 /* setup RX DMA channel. */ 2808 bwn_dma_setup(dma->rx); 2809 } 2810 2811 static struct bwn_dma_ring * 2812 bwn_dma_ringsetup(struct bwn_mac *mac, int controller_index, 2813 int for_tx) 2814 { 2815 struct bwn_dma *dma = &mac->mac_method.dma; 2816 struct bwn_dma_ring *dr; 2817 struct bwn_dmadesc_generic *desc; 2818 struct bwn_dmadesc_meta *mt; 2819 struct bwn_softc *sc = mac->mac_sc; 2820 int error, i; 2821 2822 dr = malloc(sizeof(*dr), M_DEVBUF, M_NOWAIT | M_ZERO); 2823 if (dr == NULL) 2824 goto out; 2825 dr->dr_numslots = BWN_RXRING_SLOTS; 2826 if (for_tx) 2827 dr->dr_numslots = BWN_TXRING_SLOTS; 2828 2829 dr->dr_meta = malloc(dr->dr_numslots * sizeof(struct bwn_dmadesc_meta), 2830 M_DEVBUF, M_NOWAIT | M_ZERO); 2831 if (dr->dr_meta == NULL) 2832 goto fail0; 2833 2834 dr->dr_type = mac->mac_dmatype; 2835 dr->dr_mac = mac; 2836 dr->dr_base = bwn_dma_base(dr->dr_type, controller_index); 2837 dr->dr_index = controller_index; 2838 if (dr->dr_type == BHND_DMA_ADDR_64BIT) { 2839 dr->getdesc = bwn_dma_64_getdesc; 2840 dr->setdesc = bwn_dma_64_setdesc; 2841 dr->start_transfer = bwn_dma_64_start_transfer; 2842 dr->suspend = bwn_dma_64_suspend; 2843 dr->resume = bwn_dma_64_resume; 2844 dr->get_curslot = bwn_dma_64_get_curslot; 2845 dr->set_curslot = bwn_dma_64_set_curslot; 2846 } else { 2847 dr->getdesc = bwn_dma_32_getdesc; 2848 dr->setdesc = bwn_dma_32_setdesc; 2849 dr->start_transfer = bwn_dma_32_start_transfer; 2850 dr->suspend = bwn_dma_32_suspend; 2851 dr->resume = bwn_dma_32_resume; 2852 dr->get_curslot = bwn_dma_32_get_curslot; 2853 dr->set_curslot = bwn_dma_32_set_curslot; 2854 } 2855 if (for_tx) { 2856 dr->dr_tx = 1; 2857 dr->dr_curslot = -1; 2858 } else { 2859 if (dr->dr_index == 0) { 2860 switch (mac->mac_fw.fw_hdr_format) { 2861 case BWN_FW_HDR_351: 2862 case BWN_FW_HDR_410: 2863 dr->dr_rx_bufsize = 2864 BWN_DMA0_RX_BUFFERSIZE_FW351; 2865 dr->dr_frameoffset = 2866 BWN_DMA0_RX_FRAMEOFFSET_FW351; 2867 break; 2868 case BWN_FW_HDR_598: 2869 dr->dr_rx_bufsize = 2870 BWN_DMA0_RX_BUFFERSIZE_FW598; 2871 dr->dr_frameoffset = 2872 BWN_DMA0_RX_FRAMEOFFSET_FW598; 2873 break; 2874 } 2875 } else 2876 KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__)); 2877 } 2878 2879 error = bwn_dma_allocringmemory(dr); 2880 if (error) 2881 goto fail2; 2882 2883 if (for_tx) { 2884 /* 2885 * Assumption: BWN_TXRING_SLOTS can be divided by 2886 * BWN_TX_SLOTS_PER_FRAME 2887 */ 2888 KASSERT(BWN_TXRING_SLOTS % BWN_TX_SLOTS_PER_FRAME == 0, 2889 ("%s:%d: fail", __func__, __LINE__)); 2890 2891 dr->dr_txhdr_cache = contigmalloc( 2892 (dr->dr_numslots / BWN_TX_SLOTS_PER_FRAME) * 2893 BWN_MAXTXHDRSIZE, M_DEVBUF, M_ZERO, 2894 0, BUS_SPACE_MAXADDR, 8, 0); 2895 if (dr->dr_txhdr_cache == NULL) { 2896 device_printf(sc->sc_dev, 2897 "can't allocate TX header DMA memory\n"); 2898 goto fail1; 2899 } 2900 2901 /* 2902 * Create TX ring DMA stuffs 2903 */ 2904 error = bus_dma_tag_create(dma->parent_dtag, 2905 BWN_ALIGN, 0, 2906 BUS_SPACE_MAXADDR, 2907 BUS_SPACE_MAXADDR, 2908 NULL, NULL, 2909 BWN_HDRSIZE(mac), 2910 1, 2911 BUS_SPACE_MAXSIZE_32BIT, 2912 0, 2913 NULL, NULL, 2914 &dr->dr_txring_dtag); 2915 if (error) { 2916 device_printf(sc->sc_dev, 2917 "can't create TX ring DMA tag: TODO frees\n"); 2918 goto fail2; 2919 } 2920 2921 for (i = 0; i < dr->dr_numslots; i += 2) { 2922 dr->getdesc(dr, i, &desc, &mt); 2923 2924 mt->mt_txtype = BWN_DMADESC_METATYPE_HEADER; 2925 mt->mt_m = NULL; 2926 mt->mt_ni = NULL; 2927 mt->mt_islast = 0; 2928 error = bus_dmamap_create(dr->dr_txring_dtag, 0, 2929 &mt->mt_dmap); 2930 if (error) { 2931 device_printf(sc->sc_dev, 2932 "can't create RX buf DMA map\n"); 2933 goto fail2; 2934 } 2935 2936 dr->getdesc(dr, i + 1, &desc, &mt); 2937 2938 mt->mt_txtype = BWN_DMADESC_METATYPE_BODY; 2939 mt->mt_m = NULL; 2940 mt->mt_ni = NULL; 2941 mt->mt_islast = 1; 2942 error = bus_dmamap_create(dma->txbuf_dtag, 0, 2943 &mt->mt_dmap); 2944 if (error) { 2945 device_printf(sc->sc_dev, 2946 "can't create RX buf DMA map\n"); 2947 goto fail2; 2948 } 2949 } 2950 } else { 2951 error = bus_dmamap_create(dma->rxbuf_dtag, 0, 2952 &dr->dr_spare_dmap); 2953 if (error) { 2954 device_printf(sc->sc_dev, 2955 "can't create RX buf DMA map\n"); 2956 goto out; /* XXX wrong! */ 2957 } 2958 2959 for (i = 0; i < dr->dr_numslots; i++) { 2960 dr->getdesc(dr, i, &desc, &mt); 2961 2962 error = bus_dmamap_create(dma->rxbuf_dtag, 0, 2963 &mt->mt_dmap); 2964 if (error) { 2965 device_printf(sc->sc_dev, 2966 "can't create RX buf DMA map\n"); 2967 goto out; /* XXX wrong! */ 2968 } 2969 error = bwn_dma_newbuf(dr, desc, mt, 1); 2970 if (error) { 2971 device_printf(sc->sc_dev, 2972 "failed to allocate RX buf\n"); 2973 goto out; /* XXX wrong! */ 2974 } 2975 } 2976 2977 bus_dmamap_sync(dr->dr_ring_dtag, dr->dr_ring_dmap, 2978 BUS_DMASYNC_PREWRITE); 2979 2980 dr->dr_usedslot = dr->dr_numslots; 2981 } 2982 2983 out: 2984 return (dr); 2985 2986 fail2: 2987 if (dr->dr_txhdr_cache != NULL) { 2988 contigfree(dr->dr_txhdr_cache, 2989 (dr->dr_numslots / BWN_TX_SLOTS_PER_FRAME) * 2990 BWN_MAXTXHDRSIZE, M_DEVBUF); 2991 } 2992 fail1: 2993 free(dr->dr_meta, M_DEVBUF); 2994 fail0: 2995 free(dr, M_DEVBUF); 2996 return (NULL); 2997 } 2998 2999 static void 3000 bwn_dma_ringfree(struct bwn_dma_ring **dr) 3001 { 3002 3003 if (dr == NULL) 3004 return; 3005 3006 bwn_dma_free_descbufs(*dr); 3007 bwn_dma_free_ringmemory(*dr); 3008 3009 if ((*dr)->dr_txhdr_cache != NULL) { 3010 contigfree((*dr)->dr_txhdr_cache, 3011 ((*dr)->dr_numslots / BWN_TX_SLOTS_PER_FRAME) * 3012 BWN_MAXTXHDRSIZE, M_DEVBUF); 3013 } 3014 free((*dr)->dr_meta, M_DEVBUF); 3015 free(*dr, M_DEVBUF); 3016 3017 *dr = NULL; 3018 } 3019 3020 static void 3021 bwn_dma_32_getdesc(struct bwn_dma_ring *dr, int slot, 3022 struct bwn_dmadesc_generic **gdesc, struct bwn_dmadesc_meta **meta) 3023 { 3024 struct bwn_dmadesc32 *desc; 3025 3026 *meta = &(dr->dr_meta[slot]); 3027 desc = dr->dr_ring_descbase; 3028 desc = &(desc[slot]); 3029 3030 *gdesc = (struct bwn_dmadesc_generic *)desc; 3031 } 3032 3033 static void 3034 bwn_dma_32_setdesc(struct bwn_dma_ring *dr, 3035 struct bwn_dmadesc_generic *desc, bus_addr_t dmaaddr, uint16_t bufsize, 3036 int start, int end, int irq) 3037 { 3038 struct bwn_dmadesc32 *descbase; 3039 struct bwn_dma *dma; 3040 struct bhnd_dma_translation *dt; 3041 uint32_t addr, addrext, ctl; 3042 int slot; 3043 3044 descbase = dr->dr_ring_descbase; 3045 dma = &dr->dr_mac->mac_method.dma; 3046 dt = &dma->translation; 3047 3048 slot = (int)(&(desc->dma.dma32) - descbase); 3049 KASSERT(slot >= 0 && slot < dr->dr_numslots, 3050 ("%s:%d: fail", __func__, __LINE__)); 3051 3052 addr = (dmaaddr & dt->addr_mask) | dt->base_addr; 3053 addrext = ((dmaaddr & dt->addrext_mask) >> dma->addrext_shift); 3054 ctl = bufsize & BWN_DMA32_DCTL_BYTECNT; 3055 if (slot == dr->dr_numslots - 1) 3056 ctl |= BWN_DMA32_DCTL_DTABLEEND; 3057 if (start) 3058 ctl |= BWN_DMA32_DCTL_FRAMESTART; 3059 if (end) 3060 ctl |= BWN_DMA32_DCTL_FRAMEEND; 3061 if (irq) 3062 ctl |= BWN_DMA32_DCTL_IRQ; 3063 ctl |= (addrext << BWN_DMA32_DCTL_ADDREXT_SHIFT) 3064 & BWN_DMA32_DCTL_ADDREXT_MASK; 3065 3066 desc->dma.dma32.control = htole32(ctl); 3067 desc->dma.dma32.address = htole32(addr); 3068 } 3069 3070 static void 3071 bwn_dma_32_start_transfer(struct bwn_dma_ring *dr, int slot) 3072 { 3073 3074 BWN_DMA_WRITE(dr, BWN_DMA32_TXINDEX, 3075 (uint32_t)(slot * sizeof(struct bwn_dmadesc32))); 3076 } 3077 3078 static void 3079 bwn_dma_32_suspend(struct bwn_dma_ring *dr) 3080 { 3081 3082 BWN_DMA_WRITE(dr, BWN_DMA32_TXCTL, 3083 BWN_DMA_READ(dr, BWN_DMA32_TXCTL) | BWN_DMA32_TXSUSPEND); 3084 } 3085 3086 static void 3087 bwn_dma_32_resume(struct bwn_dma_ring *dr) 3088 { 3089 3090 BWN_DMA_WRITE(dr, BWN_DMA32_TXCTL, 3091 BWN_DMA_READ(dr, BWN_DMA32_TXCTL) & ~BWN_DMA32_TXSUSPEND); 3092 } 3093 3094 static int 3095 bwn_dma_32_get_curslot(struct bwn_dma_ring *dr) 3096 { 3097 uint32_t val; 3098 3099 val = BWN_DMA_READ(dr, BWN_DMA32_RXSTATUS); 3100 val &= BWN_DMA32_RXDPTR; 3101 3102 return (val / sizeof(struct bwn_dmadesc32)); 3103 } 3104 3105 static void 3106 bwn_dma_32_set_curslot(struct bwn_dma_ring *dr, int slot) 3107 { 3108 3109 BWN_DMA_WRITE(dr, BWN_DMA32_RXINDEX, 3110 (uint32_t) (slot * sizeof(struct bwn_dmadesc32))); 3111 } 3112 3113 static void 3114 bwn_dma_64_getdesc(struct bwn_dma_ring *dr, int slot, 3115 struct bwn_dmadesc_generic **gdesc, struct bwn_dmadesc_meta **meta) 3116 { 3117 struct bwn_dmadesc64 *desc; 3118 3119 *meta = &(dr->dr_meta[slot]); 3120 desc = dr->dr_ring_descbase; 3121 desc = &(desc[slot]); 3122 3123 *gdesc = (struct bwn_dmadesc_generic *)desc; 3124 } 3125 3126 static void 3127 bwn_dma_64_setdesc(struct bwn_dma_ring *dr, 3128 struct bwn_dmadesc_generic *desc, bus_addr_t dmaaddr, uint16_t bufsize, 3129 int start, int end, int irq) 3130 { 3131 struct bwn_dmadesc64 *descbase; 3132 struct bwn_dma *dma; 3133 struct bhnd_dma_translation *dt; 3134 bhnd_addr_t addr; 3135 uint32_t addrhi, addrlo; 3136 uint32_t addrext; 3137 uint32_t ctl0, ctl1; 3138 int slot; 3139 3140 descbase = dr->dr_ring_descbase; 3141 dma = &dr->dr_mac->mac_method.dma; 3142 dt = &dma->translation; 3143 3144 slot = (int)(&(desc->dma.dma64) - descbase); 3145 KASSERT(slot >= 0 && slot < dr->dr_numslots, 3146 ("%s:%d: fail", __func__, __LINE__)); 3147 3148 addr = (dmaaddr & dt->addr_mask) | dt->base_addr; 3149 addrhi = (addr >> 32); 3150 addrlo = (addr & UINT32_MAX); 3151 addrext = ((dmaaddr & dt->addrext_mask) >> dma->addrext_shift); 3152 3153 ctl0 = 0; 3154 if (slot == dr->dr_numslots - 1) 3155 ctl0 |= BWN_DMA64_DCTL0_DTABLEEND; 3156 if (start) 3157 ctl0 |= BWN_DMA64_DCTL0_FRAMESTART; 3158 if (end) 3159 ctl0 |= BWN_DMA64_DCTL0_FRAMEEND; 3160 if (irq) 3161 ctl0 |= BWN_DMA64_DCTL0_IRQ; 3162 3163 ctl1 = 0; 3164 ctl1 |= bufsize & BWN_DMA64_DCTL1_BYTECNT; 3165 ctl1 |= (addrext << BWN_DMA64_DCTL1_ADDREXT_SHIFT) 3166 & BWN_DMA64_DCTL1_ADDREXT_MASK; 3167 3168 desc->dma.dma64.control0 = htole32(ctl0); 3169 desc->dma.dma64.control1 = htole32(ctl1); 3170 desc->dma.dma64.address_low = htole32(addrlo); 3171 desc->dma.dma64.address_high = htole32(addrhi); 3172 } 3173 3174 static void 3175 bwn_dma_64_start_transfer(struct bwn_dma_ring *dr, int slot) 3176 { 3177 3178 BWN_DMA_WRITE(dr, BWN_DMA64_TXINDEX, 3179 (uint32_t)(slot * sizeof(struct bwn_dmadesc64))); 3180 } 3181 3182 static void 3183 bwn_dma_64_suspend(struct bwn_dma_ring *dr) 3184 { 3185 3186 BWN_DMA_WRITE(dr, BWN_DMA64_TXCTL, 3187 BWN_DMA_READ(dr, BWN_DMA64_TXCTL) | BWN_DMA64_TXSUSPEND); 3188 } 3189 3190 static void 3191 bwn_dma_64_resume(struct bwn_dma_ring *dr) 3192 { 3193 3194 BWN_DMA_WRITE(dr, BWN_DMA64_TXCTL, 3195 BWN_DMA_READ(dr, BWN_DMA64_TXCTL) & ~BWN_DMA64_TXSUSPEND); 3196 } 3197 3198 static int 3199 bwn_dma_64_get_curslot(struct bwn_dma_ring *dr) 3200 { 3201 uint32_t val; 3202 3203 val = BWN_DMA_READ(dr, BWN_DMA64_RXSTATUS); 3204 val &= BWN_DMA64_RXSTATDPTR; 3205 3206 return (val / sizeof(struct bwn_dmadesc64)); 3207 } 3208 3209 static void 3210 bwn_dma_64_set_curslot(struct bwn_dma_ring *dr, int slot) 3211 { 3212 3213 BWN_DMA_WRITE(dr, BWN_DMA64_RXINDEX, 3214 (uint32_t)(slot * sizeof(struct bwn_dmadesc64))); 3215 } 3216 3217 static int 3218 bwn_dma_allocringmemory(struct bwn_dma_ring *dr) 3219 { 3220 struct bwn_mac *mac = dr->dr_mac; 3221 struct bwn_dma *dma = &mac->mac_method.dma; 3222 struct bwn_softc *sc = mac->mac_sc; 3223 int error; 3224 3225 error = bus_dma_tag_create(dma->parent_dtag, 3226 BWN_ALIGN, 0, 3227 BUS_SPACE_MAXADDR, 3228 BUS_SPACE_MAXADDR, 3229 NULL, NULL, 3230 BWN_DMA_RINGMEMSIZE, 3231 1, 3232 BUS_SPACE_MAXSIZE_32BIT, 3233 0, 3234 NULL, NULL, 3235 &dr->dr_ring_dtag); 3236 if (error) { 3237 device_printf(sc->sc_dev, 3238 "can't create TX ring DMA tag: TODO frees\n"); 3239 return (-1); 3240 } 3241 3242 error = bus_dmamem_alloc(dr->dr_ring_dtag, 3243 &dr->dr_ring_descbase, BUS_DMA_WAITOK | BUS_DMA_ZERO, 3244 &dr->dr_ring_dmap); 3245 if (error) { 3246 device_printf(sc->sc_dev, 3247 "can't allocate DMA mem: TODO frees\n"); 3248 return (-1); 3249 } 3250 error = bus_dmamap_load(dr->dr_ring_dtag, dr->dr_ring_dmap, 3251 dr->dr_ring_descbase, BWN_DMA_RINGMEMSIZE, 3252 bwn_dma_ring_addr, &dr->dr_ring_dmabase, BUS_DMA_NOWAIT); 3253 if (error) { 3254 device_printf(sc->sc_dev, 3255 "can't load DMA mem: TODO free\n"); 3256 return (-1); 3257 } 3258 3259 return (0); 3260 } 3261 3262 static void 3263 bwn_dma_setup(struct bwn_dma_ring *dr) 3264 { 3265 struct bwn_mac *mac; 3266 struct bwn_dma *dma; 3267 struct bhnd_dma_translation *dt; 3268 bhnd_addr_t addr, paddr; 3269 uint32_t addrhi, addrlo, addrext, value; 3270 3271 mac = dr->dr_mac; 3272 dma = &mac->mac_method.dma; 3273 dt = &dma->translation; 3274 3275 paddr = dr->dr_ring_dmabase; 3276 addr = (paddr & dt->addr_mask) | dt->base_addr; 3277 addrhi = (addr >> 32); 3278 addrlo = (addr & UINT32_MAX); 3279 addrext = ((paddr & dt->addrext_mask) >> dma->addrext_shift); 3280 3281 if (dr->dr_tx) { 3282 dr->dr_curslot = -1; 3283 3284 if (dr->dr_type == BHND_DMA_ADDR_64BIT) { 3285 value = BWN_DMA64_TXENABLE; 3286 value |= BWN_DMA64_TXPARITY_DISABLE; 3287 value |= (addrext << BWN_DMA64_TXADDREXT_SHIFT) 3288 & BWN_DMA64_TXADDREXT_MASK; 3289 BWN_DMA_WRITE(dr, BWN_DMA64_TXCTL, value); 3290 BWN_DMA_WRITE(dr, BWN_DMA64_TXRINGLO, addrlo); 3291 BWN_DMA_WRITE(dr, BWN_DMA64_TXRINGHI, addrhi); 3292 } else { 3293 value = BWN_DMA32_TXENABLE; 3294 value |= BWN_DMA32_TXPARITY_DISABLE; 3295 value |= (addrext << BWN_DMA32_TXADDREXT_SHIFT) 3296 & BWN_DMA32_TXADDREXT_MASK; 3297 BWN_DMA_WRITE(dr, BWN_DMA32_TXCTL, value); 3298 BWN_DMA_WRITE(dr, BWN_DMA32_TXRING, addrlo); 3299 } 3300 return; 3301 } 3302 3303 /* 3304 * set for RX 3305 */ 3306 dr->dr_usedslot = dr->dr_numslots; 3307 3308 if (dr->dr_type == BHND_DMA_ADDR_64BIT) { 3309 value = (dr->dr_frameoffset << BWN_DMA64_RXFROFF_SHIFT); 3310 value |= BWN_DMA64_RXENABLE; 3311 value |= BWN_DMA64_RXPARITY_DISABLE; 3312 value |= (addrext << BWN_DMA64_RXADDREXT_SHIFT) 3313 & BWN_DMA64_RXADDREXT_MASK; 3314 BWN_DMA_WRITE(dr, BWN_DMA64_RXCTL, value); 3315 BWN_DMA_WRITE(dr, BWN_DMA64_RXRINGLO, addrlo); 3316 BWN_DMA_WRITE(dr, BWN_DMA64_RXRINGHI, addrhi); 3317 BWN_DMA_WRITE(dr, BWN_DMA64_RXINDEX, dr->dr_numslots * 3318 sizeof(struct bwn_dmadesc64)); 3319 } else { 3320 value = (dr->dr_frameoffset << BWN_DMA32_RXFROFF_SHIFT); 3321 value |= BWN_DMA32_RXENABLE; 3322 value |= BWN_DMA32_RXPARITY_DISABLE; 3323 value |= (addrext << BWN_DMA32_RXADDREXT_SHIFT) 3324 & BWN_DMA32_RXADDREXT_MASK; 3325 BWN_DMA_WRITE(dr, BWN_DMA32_RXCTL, value); 3326 BWN_DMA_WRITE(dr, BWN_DMA32_RXRING, addrlo); 3327 BWN_DMA_WRITE(dr, BWN_DMA32_RXINDEX, dr->dr_numslots * 3328 sizeof(struct bwn_dmadesc32)); 3329 } 3330 } 3331 3332 static void 3333 bwn_dma_free_ringmemory(struct bwn_dma_ring *dr) 3334 { 3335 3336 bus_dmamap_unload(dr->dr_ring_dtag, dr->dr_ring_dmap); 3337 bus_dmamem_free(dr->dr_ring_dtag, dr->dr_ring_descbase, 3338 dr->dr_ring_dmap); 3339 } 3340 3341 static void 3342 bwn_dma_cleanup(struct bwn_dma_ring *dr) 3343 { 3344 3345 if (dr->dr_tx) { 3346 bwn_dma_tx_reset(dr->dr_mac, dr->dr_base, dr->dr_type); 3347 if (dr->dr_type == BHND_DMA_ADDR_64BIT) { 3348 BWN_DMA_WRITE(dr, BWN_DMA64_TXRINGLO, 0); 3349 BWN_DMA_WRITE(dr, BWN_DMA64_TXRINGHI, 0); 3350 } else 3351 BWN_DMA_WRITE(dr, BWN_DMA32_TXRING, 0); 3352 } else { 3353 bwn_dma_rx_reset(dr->dr_mac, dr->dr_base, dr->dr_type); 3354 if (dr->dr_type == BHND_DMA_ADDR_64BIT) { 3355 BWN_DMA_WRITE(dr, BWN_DMA64_RXRINGLO, 0); 3356 BWN_DMA_WRITE(dr, BWN_DMA64_RXRINGHI, 0); 3357 } else 3358 BWN_DMA_WRITE(dr, BWN_DMA32_RXRING, 0); 3359 } 3360 } 3361 3362 static void 3363 bwn_dma_free_descbufs(struct bwn_dma_ring *dr) 3364 { 3365 struct bwn_dmadesc_generic *desc; 3366 struct bwn_dmadesc_meta *meta; 3367 struct bwn_mac *mac = dr->dr_mac; 3368 struct bwn_dma *dma = &mac->mac_method.dma; 3369 struct bwn_softc *sc = mac->mac_sc; 3370 int i; 3371 3372 if (!dr->dr_usedslot) 3373 return; 3374 for (i = 0; i < dr->dr_numslots; i++) { 3375 dr->getdesc(dr, i, &desc, &meta); 3376 3377 if (meta->mt_m == NULL) { 3378 if (!dr->dr_tx) 3379 device_printf(sc->sc_dev, "%s: not TX?\n", 3380 __func__); 3381 continue; 3382 } 3383 if (dr->dr_tx) { 3384 if (meta->mt_txtype == BWN_DMADESC_METATYPE_HEADER) 3385 bus_dmamap_unload(dr->dr_txring_dtag, 3386 meta->mt_dmap); 3387 else if (meta->mt_txtype == BWN_DMADESC_METATYPE_BODY) 3388 bus_dmamap_unload(dma->txbuf_dtag, 3389 meta->mt_dmap); 3390 } else 3391 bus_dmamap_unload(dma->rxbuf_dtag, meta->mt_dmap); 3392 bwn_dma_free_descbuf(dr, meta); 3393 } 3394 } 3395 3396 static int 3397 bwn_dma_tx_reset(struct bwn_mac *mac, uint16_t base, 3398 int type) 3399 { 3400 struct bwn_softc *sc = mac->mac_sc; 3401 uint32_t value; 3402 int i; 3403 uint16_t offset; 3404 3405 for (i = 0; i < 10; i++) { 3406 offset = (type == BHND_DMA_ADDR_64BIT) ? BWN_DMA64_TXSTATUS : 3407 BWN_DMA32_TXSTATUS; 3408 value = BWN_READ_4(mac, base + offset); 3409 if (type == BHND_DMA_ADDR_64BIT) { 3410 value &= BWN_DMA64_TXSTAT; 3411 if (value == BWN_DMA64_TXSTAT_DISABLED || 3412 value == BWN_DMA64_TXSTAT_IDLEWAIT || 3413 value == BWN_DMA64_TXSTAT_STOPPED) 3414 break; 3415 } else { 3416 value &= BWN_DMA32_TXSTATE; 3417 if (value == BWN_DMA32_TXSTAT_DISABLED || 3418 value == BWN_DMA32_TXSTAT_IDLEWAIT || 3419 value == BWN_DMA32_TXSTAT_STOPPED) 3420 break; 3421 } 3422 DELAY(1000); 3423 } 3424 offset = (type == BHND_DMA_ADDR_64BIT) ? BWN_DMA64_TXCTL : 3425 BWN_DMA32_TXCTL; 3426 BWN_WRITE_4(mac, base + offset, 0); 3427 for (i = 0; i < 10; i++) { 3428 offset = (type == BHND_DMA_ADDR_64BIT) ? BWN_DMA64_TXSTATUS : 3429 BWN_DMA32_TXSTATUS; 3430 value = BWN_READ_4(mac, base + offset); 3431 if (type == BHND_DMA_ADDR_64BIT) { 3432 value &= BWN_DMA64_TXSTAT; 3433 if (value == BWN_DMA64_TXSTAT_DISABLED) { 3434 i = -1; 3435 break; 3436 } 3437 } else { 3438 value &= BWN_DMA32_TXSTATE; 3439 if (value == BWN_DMA32_TXSTAT_DISABLED) { 3440 i = -1; 3441 break; 3442 } 3443 } 3444 DELAY(1000); 3445 } 3446 if (i != -1) { 3447 device_printf(sc->sc_dev, "%s: timed out\n", __func__); 3448 return (ENODEV); 3449 } 3450 DELAY(1000); 3451 3452 return (0); 3453 } 3454 3455 static int 3456 bwn_dma_rx_reset(struct bwn_mac *mac, uint16_t base, 3457 int type) 3458 { 3459 struct bwn_softc *sc = mac->mac_sc; 3460 uint32_t value; 3461 int i; 3462 uint16_t offset; 3463 3464 offset = (type == BHND_DMA_ADDR_64BIT) ? BWN_DMA64_RXCTL : 3465 BWN_DMA32_RXCTL; 3466 BWN_WRITE_4(mac, base + offset, 0); 3467 for (i = 0; i < 10; i++) { 3468 offset = (type == BHND_DMA_ADDR_64BIT) ? BWN_DMA64_RXSTATUS : 3469 BWN_DMA32_RXSTATUS; 3470 value = BWN_READ_4(mac, base + offset); 3471 if (type == BHND_DMA_ADDR_64BIT) { 3472 value &= BWN_DMA64_RXSTAT; 3473 if (value == BWN_DMA64_RXSTAT_DISABLED) { 3474 i = -1; 3475 break; 3476 } 3477 } else { 3478 value &= BWN_DMA32_RXSTATE; 3479 if (value == BWN_DMA32_RXSTAT_DISABLED) { 3480 i = -1; 3481 break; 3482 } 3483 } 3484 DELAY(1000); 3485 } 3486 if (i != -1) { 3487 device_printf(sc->sc_dev, "%s: timed out\n", __func__); 3488 return (ENODEV); 3489 } 3490 3491 return (0); 3492 } 3493 3494 static void 3495 bwn_dma_free_descbuf(struct bwn_dma_ring *dr, 3496 struct bwn_dmadesc_meta *meta) 3497 { 3498 3499 if (meta->mt_m != NULL) { 3500 m_freem(meta->mt_m); 3501 meta->mt_m = NULL; 3502 } 3503 if (meta->mt_ni != NULL) { 3504 ieee80211_free_node(meta->mt_ni); 3505 meta->mt_ni = NULL; 3506 } 3507 } 3508 3509 static void 3510 bwn_dma_set_redzone(struct bwn_dma_ring *dr, struct mbuf *m) 3511 { 3512 struct bwn_rxhdr4 *rxhdr; 3513 unsigned char *frame; 3514 3515 rxhdr = mtod(m, struct bwn_rxhdr4 *); 3516 rxhdr->frame_len = 0; 3517 3518 KASSERT(dr->dr_rx_bufsize >= dr->dr_frameoffset + 3519 sizeof(struct bwn_plcp6) + 2, 3520 ("%s:%d: fail", __func__, __LINE__)); 3521 frame = mtod(m, char *) + dr->dr_frameoffset; 3522 memset(frame, 0xff, sizeof(struct bwn_plcp6) + 2 /* padding */); 3523 } 3524 3525 static uint8_t 3526 bwn_dma_check_redzone(struct bwn_dma_ring *dr, struct mbuf *m) 3527 { 3528 unsigned char *f = mtod(m, char *) + dr->dr_frameoffset; 3529 3530 return ((f[0] & f[1] & f[2] & f[3] & f[4] & f[5] & f[6] & f[7]) 3531 == 0xff); 3532 } 3533 3534 static void 3535 bwn_wme_init(struct bwn_mac *mac) 3536 { 3537 3538 bwn_wme_load(mac); 3539 3540 /* enable WME support. */ 3541 bwn_hf_write(mac, bwn_hf_read(mac) | BWN_HF_EDCF); 3542 BWN_WRITE_2(mac, BWN_IFSCTL, BWN_READ_2(mac, BWN_IFSCTL) | 3543 BWN_IFSCTL_USE_EDCF); 3544 } 3545 3546 static void 3547 bwn_spu_setdelay(struct bwn_mac *mac, int idle) 3548 { 3549 struct bwn_softc *sc = mac->mac_sc; 3550 struct ieee80211com *ic = &sc->sc_ic; 3551 uint16_t delay; /* microsec */ 3552 3553 delay = (mac->mac_phy.type == BWN_PHYTYPE_A) ? 3700 : 1050; 3554 if (ic->ic_opmode == IEEE80211_M_IBSS || idle) 3555 delay = 500; 3556 if ((mac->mac_phy.rf_ver == 0x2050) && (mac->mac_phy.rf_rev == 8)) 3557 delay = max(delay, (uint16_t)2400); 3558 3559 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_SPU_WAKEUP, delay); 3560 } 3561 3562 static void 3563 bwn_bt_enable(struct bwn_mac *mac) 3564 { 3565 struct bwn_softc *sc = mac->mac_sc; 3566 uint64_t hf; 3567 3568 if (bwn_bluetooth == 0) 3569 return; 3570 if ((sc->sc_board_info.board_flags & BHND_BFL_BTCOEX) == 0) 3571 return; 3572 if (mac->mac_phy.type != BWN_PHYTYPE_B && !mac->mac_phy.gmode) 3573 return; 3574 3575 hf = bwn_hf_read(mac); 3576 if (sc->sc_board_info.board_flags & BHND_BFL_BTC2WIRE_ALTGPIO) 3577 hf |= BWN_HF_BT_COEXISTALT; 3578 else 3579 hf |= BWN_HF_BT_COEXIST; 3580 bwn_hf_write(mac, hf); 3581 } 3582 3583 static void 3584 bwn_set_macaddr(struct bwn_mac *mac) 3585 { 3586 3587 bwn_mac_write_bssid(mac); 3588 bwn_mac_setfilter(mac, BWN_MACFILTER_SELF, 3589 mac->mac_sc->sc_ic.ic_macaddr); 3590 } 3591 3592 static void 3593 bwn_clear_keys(struct bwn_mac *mac) 3594 { 3595 int i; 3596 3597 for (i = 0; i < mac->mac_max_nr_keys; i++) { 3598 KASSERT(i >= 0 && i < mac->mac_max_nr_keys, 3599 ("%s:%d: fail", __func__, __LINE__)); 3600 3601 bwn_key_dowrite(mac, i, BWN_SEC_ALGO_NONE, 3602 NULL, BWN_SEC_KEYSIZE, NULL); 3603 if ((i <= 3) && !BWN_SEC_NEWAPI(mac)) { 3604 bwn_key_dowrite(mac, i + 4, BWN_SEC_ALGO_NONE, 3605 NULL, BWN_SEC_KEYSIZE, NULL); 3606 } 3607 mac->mac_key[i].keyconf = NULL; 3608 } 3609 } 3610 3611 static void 3612 bwn_crypt_init(struct bwn_mac *mac) 3613 { 3614 struct bwn_softc *sc = mac->mac_sc; 3615 3616 mac->mac_max_nr_keys = (bhnd_get_hwrev(sc->sc_dev) >= 5) ? 58 : 20; 3617 KASSERT(mac->mac_max_nr_keys <= N(mac->mac_key), 3618 ("%s:%d: fail", __func__, __LINE__)); 3619 mac->mac_ktp = bwn_shm_read_2(mac, BWN_SHARED, BWN_SHARED_KEY_TABLEP); 3620 mac->mac_ktp *= 2; 3621 if (bhnd_get_hwrev(sc->sc_dev) >= 5) 3622 BWN_WRITE_2(mac, BWN_RCMTA_COUNT, mac->mac_max_nr_keys - 8); 3623 bwn_clear_keys(mac); 3624 } 3625 3626 static void 3627 bwn_chip_exit(struct bwn_mac *mac) 3628 { 3629 bwn_phy_exit(mac); 3630 } 3631 3632 static int 3633 bwn_fw_fillinfo(struct bwn_mac *mac) 3634 { 3635 int error; 3636 3637 error = bwn_fw_gets(mac, BWN_FWTYPE_DEFAULT); 3638 if (error == 0) 3639 return (0); 3640 error = bwn_fw_gets(mac, BWN_FWTYPE_OPENSOURCE); 3641 if (error == 0) 3642 return (0); 3643 return (error); 3644 } 3645 3646 /** 3647 * Request that the GPIO controller tristate all pins set in @p mask, granting 3648 * the MAC core control over the pins. 3649 * 3650 * @param mac bwn MAC state. 3651 * @param pins If the bit position for a pin number is set to one, tristate the 3652 * pin. 3653 */ 3654 int 3655 bwn_gpio_control(struct bwn_mac *mac, uint32_t pins) 3656 { 3657 struct bwn_softc *sc; 3658 uint32_t flags[32]; 3659 int error; 3660 3661 sc = mac->mac_sc; 3662 3663 /* Determine desired pin flags */ 3664 for (size_t pin = 0; pin < nitems(flags); pin++) { 3665 uint32_t pinbit = (1 << pin); 3666 3667 if (pins & pinbit) { 3668 /* Tristate output */ 3669 flags[pin] = GPIO_PIN_OUTPUT|GPIO_PIN_TRISTATE; 3670 } else { 3671 /* Leave unmodified */ 3672 flags[pin] = 0; 3673 } 3674 } 3675 3676 /* Configure all pins */ 3677 error = GPIO_PIN_CONFIG_32(sc->sc_gpio, 0, nitems(flags), flags); 3678 if (error) { 3679 device_printf(sc->sc_dev, "error configuring %s pin flags: " 3680 "%d\n", device_get_nameunit(sc->sc_gpio), error); 3681 return (error); 3682 } 3683 3684 return (0); 3685 } 3686 3687 static int 3688 bwn_gpio_init(struct bwn_mac *mac) 3689 { 3690 struct bwn_softc *sc; 3691 uint32_t pins; 3692 3693 sc = mac->mac_sc; 3694 3695 pins = 0xF; 3696 3697 BWN_WRITE_4(mac, BWN_MACCTL, 3698 BWN_READ_4(mac, BWN_MACCTL) & ~BWN_MACCTL_GPOUT_MASK); 3699 BWN_WRITE_2(mac, BWN_GPIO_MASK, 3700 BWN_READ_2(mac, BWN_GPIO_MASK) | pins); 3701 3702 if (sc->sc_board_info.board_flags & BHND_BFL_PACTRL) { 3703 /* MAC core is responsible for toggling PAREF via gpio9 */ 3704 BWN_WRITE_2(mac, BWN_GPIO_MASK, 3705 BWN_READ_2(mac, BWN_GPIO_MASK) | BHND_GPIO_BOARD_PACTRL); 3706 3707 pins |= BHND_GPIO_BOARD_PACTRL; 3708 } 3709 3710 return (bwn_gpio_control(mac, pins)); 3711 } 3712 3713 static int 3714 bwn_fw_loadinitvals(struct bwn_mac *mac) 3715 { 3716 #define GETFWOFFSET(fwp, offset) \ 3717 ((const struct bwn_fwinitvals *)((const char *)fwp.fw->data + offset)) 3718 const size_t hdr_len = sizeof(struct bwn_fwhdr); 3719 const struct bwn_fwhdr *hdr; 3720 struct bwn_fw *fw = &mac->mac_fw; 3721 int error; 3722 3723 hdr = (const struct bwn_fwhdr *)(fw->initvals.fw->data); 3724 error = bwn_fwinitvals_write(mac, GETFWOFFSET(fw->initvals, hdr_len), 3725 be32toh(hdr->size), fw->initvals.fw->datasize - hdr_len); 3726 if (error) 3727 return (error); 3728 if (fw->initvals_band.fw) { 3729 hdr = (const struct bwn_fwhdr *)(fw->initvals_band.fw->data); 3730 error = bwn_fwinitvals_write(mac, 3731 GETFWOFFSET(fw->initvals_band, hdr_len), 3732 be32toh(hdr->size), 3733 fw->initvals_band.fw->datasize - hdr_len); 3734 } 3735 return (error); 3736 #undef GETFWOFFSET 3737 } 3738 3739 static int 3740 bwn_phy_init(struct bwn_mac *mac) 3741 { 3742 struct bwn_softc *sc = mac->mac_sc; 3743 int error; 3744 3745 mac->mac_phy.chan = mac->mac_phy.get_default_chan(mac); 3746 mac->mac_phy.rf_onoff(mac, 1); 3747 error = mac->mac_phy.init(mac); 3748 if (error) { 3749 device_printf(sc->sc_dev, "PHY init failed\n"); 3750 goto fail0; 3751 } 3752 error = bwn_switch_channel(mac, 3753 mac->mac_phy.get_default_chan(mac)); 3754 if (error) { 3755 device_printf(sc->sc_dev, 3756 "failed to switch default channel\n"); 3757 goto fail1; 3758 } 3759 return (0); 3760 fail1: 3761 if (mac->mac_phy.exit) 3762 mac->mac_phy.exit(mac); 3763 fail0: 3764 mac->mac_phy.rf_onoff(mac, 0); 3765 3766 return (error); 3767 } 3768 3769 static void 3770 bwn_set_txantenna(struct bwn_mac *mac, int antenna) 3771 { 3772 uint16_t ant; 3773 uint16_t tmp; 3774 3775 ant = bwn_ant2phy(antenna); 3776 3777 /* For ACK/CTS */ 3778 tmp = bwn_shm_read_2(mac, BWN_SHARED, BWN_SHARED_ACKCTS_PHYCTL); 3779 tmp = (tmp & ~BWN_TX_PHY_ANT) | ant; 3780 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_ACKCTS_PHYCTL, tmp); 3781 /* For Probe Resposes */ 3782 tmp = bwn_shm_read_2(mac, BWN_SHARED, BWN_SHARED_PROBE_RESP_PHYCTL); 3783 tmp = (tmp & ~BWN_TX_PHY_ANT) | ant; 3784 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_PROBE_RESP_PHYCTL, tmp); 3785 } 3786 3787 static void 3788 bwn_set_opmode(struct bwn_mac *mac) 3789 { 3790 struct bwn_softc *sc = mac->mac_sc; 3791 struct ieee80211com *ic = &sc->sc_ic; 3792 uint32_t ctl; 3793 uint16_t cfp_pretbtt; 3794 3795 ctl = BWN_READ_4(mac, BWN_MACCTL); 3796 ctl &= ~(BWN_MACCTL_HOSTAP | BWN_MACCTL_PASS_CTL | 3797 BWN_MACCTL_PASS_BADPLCP | BWN_MACCTL_PASS_BADFCS | 3798 BWN_MACCTL_PROMISC | BWN_MACCTL_BEACON_PROMISC); 3799 ctl |= BWN_MACCTL_STA; 3800 3801 if (ic->ic_opmode == IEEE80211_M_HOSTAP || 3802 ic->ic_opmode == IEEE80211_M_MBSS) 3803 ctl |= BWN_MACCTL_HOSTAP; 3804 else if (ic->ic_opmode == IEEE80211_M_IBSS) 3805 ctl &= ~BWN_MACCTL_STA; 3806 ctl |= sc->sc_filters; 3807 3808 if (bhnd_get_hwrev(sc->sc_dev) <= 4) 3809 ctl |= BWN_MACCTL_PROMISC; 3810 3811 BWN_WRITE_4(mac, BWN_MACCTL, ctl); 3812 3813 cfp_pretbtt = 2; 3814 if ((ctl & BWN_MACCTL_STA) && !(ctl & BWN_MACCTL_HOSTAP)) { 3815 if (sc->sc_cid.chip_id == BHND_CHIPID_BCM4306 && 3816 sc->sc_cid.chip_rev == 3) 3817 cfp_pretbtt = 100; 3818 else 3819 cfp_pretbtt = 50; 3820 } 3821 BWN_WRITE_2(mac, 0x612, cfp_pretbtt); 3822 } 3823 3824 static void 3825 bwn_dma_ring_addr(void *arg, bus_dma_segment_t *seg, int nseg, int error) 3826 { 3827 if (!error) { 3828 KASSERT(nseg == 1, ("too many segments(%d)\n", nseg)); 3829 *((bus_addr_t *)arg) = seg->ds_addr; 3830 } 3831 } 3832 3833 void 3834 bwn_dummy_transmission(struct bwn_mac *mac, int ofdm, int paon) 3835 { 3836 struct bwn_phy *phy = &mac->mac_phy; 3837 struct bwn_softc *sc = mac->mac_sc; 3838 unsigned int i, max_loop; 3839 uint16_t value; 3840 uint32_t buffer[5] = { 3841 0x00000000, 0x00d40000, 0x00000000, 0x01000000, 0x00000000 3842 }; 3843 3844 if (ofdm) { 3845 max_loop = 0x1e; 3846 buffer[0] = 0x000201cc; 3847 } else { 3848 max_loop = 0xfa; 3849 buffer[0] = 0x000b846e; 3850 } 3851 3852 BWN_ASSERT_LOCKED(mac->mac_sc); 3853 3854 for (i = 0; i < 5; i++) 3855 bwn_ram_write(mac, i * 4, buffer[i]); 3856 3857 BWN_WRITE_2(mac, 0x0568, 0x0000); 3858 BWN_WRITE_2(mac, 0x07c0, 3859 (bhnd_get_hwrev(sc->sc_dev) < 11) ? 0x0000 : 0x0100); 3860 3861 value = (ofdm ? 0x41 : 0x40); 3862 BWN_WRITE_2(mac, 0x050c, value); 3863 3864 if (phy->type == BWN_PHYTYPE_N || phy->type == BWN_PHYTYPE_LP || 3865 phy->type == BWN_PHYTYPE_LCN) 3866 BWN_WRITE_2(mac, 0x0514, 0x1a02); 3867 BWN_WRITE_2(mac, 0x0508, 0x0000); 3868 BWN_WRITE_2(mac, 0x050a, 0x0000); 3869 BWN_WRITE_2(mac, 0x054c, 0x0000); 3870 BWN_WRITE_2(mac, 0x056a, 0x0014); 3871 BWN_WRITE_2(mac, 0x0568, 0x0826); 3872 BWN_WRITE_2(mac, 0x0500, 0x0000); 3873 3874 /* XXX TODO: n phy pa override? */ 3875 3876 switch (phy->type) { 3877 case BWN_PHYTYPE_N: 3878 case BWN_PHYTYPE_LCN: 3879 BWN_WRITE_2(mac, 0x0502, 0x00d0); 3880 break; 3881 case BWN_PHYTYPE_LP: 3882 BWN_WRITE_2(mac, 0x0502, 0x0050); 3883 break; 3884 default: 3885 BWN_WRITE_2(mac, 0x0502, 0x0030); 3886 break; 3887 } 3888 3889 /* flush */ 3890 BWN_READ_2(mac, 0x0502); 3891 3892 if (phy->rf_ver == 0x2050 && phy->rf_rev <= 0x5) 3893 BWN_RF_WRITE(mac, 0x0051, 0x0017); 3894 for (i = 0x00; i < max_loop; i++) { 3895 value = BWN_READ_2(mac, 0x050e); 3896 if (value & 0x0080) 3897 break; 3898 DELAY(10); 3899 } 3900 for (i = 0x00; i < 0x0a; i++) { 3901 value = BWN_READ_2(mac, 0x050e); 3902 if (value & 0x0400) 3903 break; 3904 DELAY(10); 3905 } 3906 for (i = 0x00; i < 0x19; i++) { 3907 value = BWN_READ_2(mac, 0x0690); 3908 if (!(value & 0x0100)) 3909 break; 3910 DELAY(10); 3911 } 3912 if (phy->rf_ver == 0x2050 && phy->rf_rev <= 0x5) 3913 BWN_RF_WRITE(mac, 0x0051, 0x0037); 3914 } 3915 3916 void 3917 bwn_ram_write(struct bwn_mac *mac, uint16_t offset, uint32_t val) 3918 { 3919 uint32_t macctl; 3920 3921 KASSERT(offset % 4 == 0, ("%s:%d: fail", __func__, __LINE__)); 3922 3923 macctl = BWN_READ_4(mac, BWN_MACCTL); 3924 if (macctl & BWN_MACCTL_BIGENDIAN) 3925 printf("TODO: need swap\n"); 3926 3927 BWN_WRITE_4(mac, BWN_RAM_CONTROL, offset); 3928 BWN_BARRIER(mac, BWN_RAM_CONTROL, 4, BUS_SPACE_BARRIER_WRITE); 3929 BWN_WRITE_4(mac, BWN_RAM_DATA, val); 3930 } 3931 3932 void 3933 bwn_mac_suspend(struct bwn_mac *mac) 3934 { 3935 struct bwn_softc *sc = mac->mac_sc; 3936 int i; 3937 uint32_t tmp; 3938 3939 KASSERT(mac->mac_suspended >= 0, 3940 ("%s:%d: fail", __func__, __LINE__)); 3941 3942 DPRINTF(mac->mac_sc, BWN_DEBUG_RESET, "%s: suspended=%d\n", 3943 __func__, mac->mac_suspended); 3944 3945 if (mac->mac_suspended == 0) { 3946 bwn_psctl(mac, BWN_PS_AWAKE); 3947 BWN_WRITE_4(mac, BWN_MACCTL, 3948 BWN_READ_4(mac, BWN_MACCTL) 3949 & ~BWN_MACCTL_ON); 3950 BWN_READ_4(mac, BWN_MACCTL); 3951 for (i = 35; i; i--) { 3952 tmp = BWN_READ_4(mac, BWN_INTR_REASON); 3953 if (tmp & BWN_INTR_MAC_SUSPENDED) 3954 goto out; 3955 DELAY(10); 3956 } 3957 for (i = 40; i; i--) { 3958 tmp = BWN_READ_4(mac, BWN_INTR_REASON); 3959 if (tmp & BWN_INTR_MAC_SUSPENDED) 3960 goto out; 3961 DELAY(1000); 3962 } 3963 device_printf(sc->sc_dev, "MAC suspend failed\n"); 3964 } 3965 out: 3966 mac->mac_suspended++; 3967 } 3968 3969 void 3970 bwn_mac_enable(struct bwn_mac *mac) 3971 { 3972 struct bwn_softc *sc = mac->mac_sc; 3973 uint16_t state; 3974 3975 DPRINTF(mac->mac_sc, BWN_DEBUG_RESET, "%s: suspended=%d\n", 3976 __func__, mac->mac_suspended); 3977 3978 state = bwn_shm_read_2(mac, BWN_SHARED, 3979 BWN_SHARED_UCODESTAT); 3980 if (state != BWN_SHARED_UCODESTAT_SUSPEND && 3981 state != BWN_SHARED_UCODESTAT_SLEEP) { 3982 DPRINTF(sc, BWN_DEBUG_FW, 3983 "%s: warn: firmware state (%d)\n", 3984 __func__, state); 3985 } 3986 3987 mac->mac_suspended--; 3988 KASSERT(mac->mac_suspended >= 0, 3989 ("%s:%d: fail", __func__, __LINE__)); 3990 if (mac->mac_suspended == 0) { 3991 BWN_WRITE_4(mac, BWN_MACCTL, 3992 BWN_READ_4(mac, BWN_MACCTL) | BWN_MACCTL_ON); 3993 BWN_WRITE_4(mac, BWN_INTR_REASON, BWN_INTR_MAC_SUSPENDED); 3994 BWN_READ_4(mac, BWN_MACCTL); 3995 BWN_READ_4(mac, BWN_INTR_REASON); 3996 bwn_psctl(mac, 0); 3997 } 3998 } 3999 4000 void 4001 bwn_psctl(struct bwn_mac *mac, uint32_t flags) 4002 { 4003 struct bwn_softc *sc = mac->mac_sc; 4004 int i; 4005 uint16_t ucstat; 4006 4007 KASSERT(!((flags & BWN_PS_ON) && (flags & BWN_PS_OFF)), 4008 ("%s:%d: fail", __func__, __LINE__)); 4009 KASSERT(!((flags & BWN_PS_AWAKE) && (flags & BWN_PS_ASLEEP)), 4010 ("%s:%d: fail", __func__, __LINE__)); 4011 4012 /* XXX forcibly awake and hwps-off */ 4013 4014 BWN_WRITE_4(mac, BWN_MACCTL, 4015 (BWN_READ_4(mac, BWN_MACCTL) | BWN_MACCTL_AWAKE) & 4016 ~BWN_MACCTL_HWPS); 4017 BWN_READ_4(mac, BWN_MACCTL); 4018 if (bhnd_get_hwrev(sc->sc_dev) >= 5) { 4019 for (i = 0; i < 100; i++) { 4020 ucstat = bwn_shm_read_2(mac, BWN_SHARED, 4021 BWN_SHARED_UCODESTAT); 4022 if (ucstat != BWN_SHARED_UCODESTAT_SLEEP) 4023 break; 4024 DELAY(10); 4025 } 4026 } 4027 DPRINTF(mac->mac_sc, BWN_DEBUG_RESET, "%s: ucstat=%d\n", __func__, 4028 ucstat); 4029 } 4030 4031 static int 4032 bwn_fw_gets(struct bwn_mac *mac, enum bwn_fwtype type) 4033 { 4034 struct bwn_softc *sc = mac->mac_sc; 4035 struct bwn_fw *fw = &mac->mac_fw; 4036 const uint8_t rev = bhnd_get_hwrev(sc->sc_dev); 4037 const char *filename; 4038 uint16_t iost; 4039 int error; 4040 4041 /* microcode */ 4042 filename = NULL; 4043 switch (rev) { 4044 case 42: 4045 if (mac->mac_phy.type == BWN_PHYTYPE_AC) 4046 filename = "ucode42"; 4047 break; 4048 case 40: 4049 if (mac->mac_phy.type == BWN_PHYTYPE_AC) 4050 filename = "ucode40"; 4051 break; 4052 case 33: 4053 if (mac->mac_phy.type == BWN_PHYTYPE_LCN40) 4054 filename = "ucode33_lcn40"; 4055 break; 4056 case 30: 4057 if (mac->mac_phy.type == BWN_PHYTYPE_N) 4058 filename = "ucode30_mimo"; 4059 break; 4060 case 29: 4061 if (mac->mac_phy.type == BWN_PHYTYPE_HT) 4062 filename = "ucode29_mimo"; 4063 break; 4064 case 26: 4065 if (mac->mac_phy.type == BWN_PHYTYPE_HT) 4066 filename = "ucode26_mimo"; 4067 break; 4068 case 28: 4069 case 25: 4070 if (mac->mac_phy.type == BWN_PHYTYPE_N) 4071 filename = "ucode25_mimo"; 4072 else if (mac->mac_phy.type == BWN_PHYTYPE_LCN) 4073 filename = "ucode25_lcn"; 4074 break; 4075 case 24: 4076 if (mac->mac_phy.type == BWN_PHYTYPE_LCN) 4077 filename = "ucode24_lcn"; 4078 break; 4079 case 23: 4080 if (mac->mac_phy.type == BWN_PHYTYPE_N) 4081 filename = "ucode16_mimo"; 4082 break; 4083 case 16: 4084 case 17: 4085 case 18: 4086 case 19: 4087 if (mac->mac_phy.type == BWN_PHYTYPE_N) 4088 filename = "ucode16_mimo"; 4089 else if (mac->mac_phy.type == BWN_PHYTYPE_LP) 4090 filename = "ucode16_lp"; 4091 break; 4092 case 15: 4093 filename = "ucode15"; 4094 break; 4095 case 14: 4096 filename = "ucode14"; 4097 break; 4098 case 13: 4099 filename = "ucode13"; 4100 break; 4101 case 12: 4102 case 11: 4103 filename = "ucode11"; 4104 break; 4105 case 10: 4106 case 9: 4107 case 8: 4108 case 7: 4109 case 6: 4110 case 5: 4111 filename = "ucode5"; 4112 break; 4113 default: 4114 device_printf(sc->sc_dev, "no ucode for rev %d\n", rev); 4115 bwn_release_firmware(mac); 4116 return (EOPNOTSUPP); 4117 } 4118 4119 device_printf(sc->sc_dev, "ucode fw: %s\n", filename); 4120 error = bwn_fw_get(mac, type, filename, &fw->ucode); 4121 if (error) { 4122 bwn_release_firmware(mac); 4123 return (error); 4124 } 4125 4126 /* PCM */ 4127 KASSERT(fw->no_pcmfile == 0, ("%s:%d fail", __func__, __LINE__)); 4128 if (rev >= 5 && rev <= 10) { 4129 error = bwn_fw_get(mac, type, "pcm5", &fw->pcm); 4130 if (error == ENOENT) 4131 fw->no_pcmfile = 1; 4132 else if (error) { 4133 bwn_release_firmware(mac); 4134 return (error); 4135 } 4136 } else if (rev < 11) { 4137 device_printf(sc->sc_dev, "no PCM for rev %d\n", rev); 4138 bwn_release_firmware(mac); 4139 return (EOPNOTSUPP); 4140 } 4141 4142 /* initvals */ 4143 error = bhnd_read_iost(sc->sc_dev, &iost); 4144 if (error) 4145 goto fail1; 4146 4147 switch (mac->mac_phy.type) { 4148 case BWN_PHYTYPE_A: 4149 if (rev < 5 || rev > 10) 4150 goto fail1; 4151 if (iost & BWN_IOST_HAVE_2GHZ) 4152 filename = "a0g1initvals5"; 4153 else 4154 filename = "a0g0initvals5"; 4155 break; 4156 case BWN_PHYTYPE_G: 4157 if (rev >= 5 && rev <= 10) 4158 filename = "b0g0initvals5"; 4159 else if (rev >= 13) 4160 filename = "b0g0initvals13"; 4161 else 4162 goto fail1; 4163 break; 4164 case BWN_PHYTYPE_LP: 4165 if (rev == 13) 4166 filename = "lp0initvals13"; 4167 else if (rev == 14) 4168 filename = "lp0initvals14"; 4169 else if (rev >= 15) 4170 filename = "lp0initvals15"; 4171 else 4172 goto fail1; 4173 break; 4174 case BWN_PHYTYPE_N: 4175 if (rev == 30) 4176 filename = "n16initvals30"; 4177 else if (rev == 28 || rev == 25) 4178 filename = "n0initvals25"; 4179 else if (rev == 24) 4180 filename = "n0initvals24"; 4181 else if (rev == 23) 4182 filename = "n0initvals16"; 4183 else if (rev >= 16 && rev <= 18) 4184 filename = "n0initvals16"; 4185 else if (rev >= 11 && rev <= 12) 4186 filename = "n0initvals11"; 4187 else 4188 goto fail1; 4189 break; 4190 default: 4191 goto fail1; 4192 } 4193 error = bwn_fw_get(mac, type, filename, &fw->initvals); 4194 if (error) { 4195 bwn_release_firmware(mac); 4196 return (error); 4197 } 4198 4199 /* bandswitch initvals */ 4200 switch (mac->mac_phy.type) { 4201 case BWN_PHYTYPE_A: 4202 if (rev >= 5 && rev <= 10) { 4203 if (iost & BWN_IOST_HAVE_2GHZ) 4204 filename = "a0g1bsinitvals5"; 4205 else 4206 filename = "a0g0bsinitvals5"; 4207 } else if (rev >= 11) 4208 filename = NULL; 4209 else 4210 goto fail1; 4211 break; 4212 case BWN_PHYTYPE_G: 4213 if (rev >= 5 && rev <= 10) 4214 filename = "b0g0bsinitvals5"; 4215 else if (rev >= 11) 4216 filename = NULL; 4217 else 4218 goto fail1; 4219 break; 4220 case BWN_PHYTYPE_LP: 4221 if (rev == 13) 4222 filename = "lp0bsinitvals13"; 4223 else if (rev == 14) 4224 filename = "lp0bsinitvals14"; 4225 else if (rev >= 15) 4226 filename = "lp0bsinitvals15"; 4227 else 4228 goto fail1; 4229 break; 4230 case BWN_PHYTYPE_N: 4231 if (rev == 30) 4232 filename = "n16bsinitvals30"; 4233 else if (rev == 28 || rev == 25) 4234 filename = "n0bsinitvals25"; 4235 else if (rev == 24) 4236 filename = "n0bsinitvals24"; 4237 else if (rev == 23) 4238 filename = "n0bsinitvals16"; 4239 else if (rev >= 16 && rev <= 18) 4240 filename = "n0bsinitvals16"; 4241 else if (rev >= 11 && rev <= 12) 4242 filename = "n0bsinitvals11"; 4243 else 4244 goto fail1; 4245 break; 4246 default: 4247 device_printf(sc->sc_dev, "unknown phy (%d)\n", 4248 mac->mac_phy.type); 4249 goto fail1; 4250 } 4251 error = bwn_fw_get(mac, type, filename, &fw->initvals_band); 4252 if (error) { 4253 bwn_release_firmware(mac); 4254 return (error); 4255 } 4256 return (0); 4257 fail1: 4258 device_printf(sc->sc_dev, "no INITVALS for rev %d, phy.type %d\n", 4259 rev, mac->mac_phy.type); 4260 bwn_release_firmware(mac); 4261 return (EOPNOTSUPP); 4262 } 4263 4264 static int 4265 bwn_fw_get(struct bwn_mac *mac, enum bwn_fwtype type, 4266 const char *name, struct bwn_fwfile *bfw) 4267 { 4268 const struct bwn_fwhdr *hdr; 4269 struct bwn_softc *sc = mac->mac_sc; 4270 const struct firmware *fw; 4271 char namebuf[64]; 4272 4273 if (name == NULL) { 4274 bwn_do_release_fw(bfw); 4275 return (0); 4276 } 4277 if (bfw->filename != NULL) { 4278 if (bfw->type == type && (strcmp(bfw->filename, name) == 0)) 4279 return (0); 4280 bwn_do_release_fw(bfw); 4281 } 4282 4283 snprintf(namebuf, sizeof(namebuf), "bwn%s_v4_%s%s", 4284 (type == BWN_FWTYPE_OPENSOURCE) ? "-open" : "", 4285 (mac->mac_phy.type == BWN_PHYTYPE_LP) ? "lp_" : "", name); 4286 /* XXX Sleeping on "fwload" with the non-sleepable locks held */ 4287 fw = firmware_get(namebuf); 4288 if (fw == NULL) { 4289 device_printf(sc->sc_dev, "the fw file(%s) not found\n", 4290 namebuf); 4291 return (ENOENT); 4292 } 4293 if (fw->datasize < sizeof(struct bwn_fwhdr)) 4294 goto fail; 4295 hdr = (const struct bwn_fwhdr *)(fw->data); 4296 switch (hdr->type) { 4297 case BWN_FWTYPE_UCODE: 4298 case BWN_FWTYPE_PCM: 4299 if (be32toh(hdr->size) != 4300 (fw->datasize - sizeof(struct bwn_fwhdr))) 4301 goto fail; 4302 /* FALLTHROUGH */ 4303 case BWN_FWTYPE_IV: 4304 if (hdr->ver != 1) 4305 goto fail; 4306 break; 4307 default: 4308 goto fail; 4309 } 4310 bfw->filename = name; 4311 bfw->fw = fw; 4312 bfw->type = type; 4313 return (0); 4314 fail: 4315 device_printf(sc->sc_dev, "the fw file(%s) format error\n", namebuf); 4316 if (fw != NULL) 4317 firmware_put(fw, FIRMWARE_UNLOAD); 4318 return (EPROTO); 4319 } 4320 4321 static void 4322 bwn_release_firmware(struct bwn_mac *mac) 4323 { 4324 4325 bwn_do_release_fw(&mac->mac_fw.ucode); 4326 bwn_do_release_fw(&mac->mac_fw.pcm); 4327 bwn_do_release_fw(&mac->mac_fw.initvals); 4328 bwn_do_release_fw(&mac->mac_fw.initvals_band); 4329 } 4330 4331 static void 4332 bwn_do_release_fw(struct bwn_fwfile *bfw) 4333 { 4334 4335 if (bfw->fw != NULL) 4336 firmware_put(bfw->fw, FIRMWARE_UNLOAD); 4337 bfw->fw = NULL; 4338 bfw->filename = NULL; 4339 } 4340 4341 static int 4342 bwn_fw_loaducode(struct bwn_mac *mac) 4343 { 4344 #define GETFWOFFSET(fwp, offset) \ 4345 ((const uint32_t *)((const char *)fwp.fw->data + offset)) 4346 #define GETFWSIZE(fwp, offset) \ 4347 ((fwp.fw->datasize - offset) / sizeof(uint32_t)) 4348 struct bwn_softc *sc = mac->mac_sc; 4349 const uint32_t *data; 4350 unsigned int i; 4351 uint32_t ctl; 4352 uint16_t date, fwcaps, time; 4353 int error = 0; 4354 4355 ctl = BWN_READ_4(mac, BWN_MACCTL); 4356 ctl |= BWN_MACCTL_MCODE_JMP0; 4357 KASSERT(!(ctl & BWN_MACCTL_MCODE_RUN), ("%s:%d: fail", __func__, 4358 __LINE__)); 4359 BWN_WRITE_4(mac, BWN_MACCTL, ctl); 4360 for (i = 0; i < 64; i++) 4361 bwn_shm_write_2(mac, BWN_SCRATCH, i, 0); 4362 for (i = 0; i < 4096; i += 2) 4363 bwn_shm_write_2(mac, BWN_SHARED, i, 0); 4364 4365 data = GETFWOFFSET(mac->mac_fw.ucode, sizeof(struct bwn_fwhdr)); 4366 bwn_shm_ctlword(mac, BWN_UCODE | BWN_SHARED_AUTOINC, 0x0000); 4367 for (i = 0; i < GETFWSIZE(mac->mac_fw.ucode, sizeof(struct bwn_fwhdr)); 4368 i++) { 4369 BWN_WRITE_4(mac, BWN_SHM_DATA, be32toh(data[i])); 4370 DELAY(10); 4371 } 4372 4373 if (mac->mac_fw.pcm.fw) { 4374 data = GETFWOFFSET(mac->mac_fw.pcm, sizeof(struct bwn_fwhdr)); 4375 bwn_shm_ctlword(mac, BWN_HW, 0x01ea); 4376 BWN_WRITE_4(mac, BWN_SHM_DATA, 0x00004000); 4377 bwn_shm_ctlword(mac, BWN_HW, 0x01eb); 4378 for (i = 0; i < GETFWSIZE(mac->mac_fw.pcm, 4379 sizeof(struct bwn_fwhdr)); i++) { 4380 BWN_WRITE_4(mac, BWN_SHM_DATA, be32toh(data[i])); 4381 DELAY(10); 4382 } 4383 } 4384 4385 BWN_WRITE_4(mac, BWN_INTR_REASON, BWN_INTR_ALL); 4386 BWN_WRITE_4(mac, BWN_MACCTL, 4387 (BWN_READ_4(mac, BWN_MACCTL) & ~BWN_MACCTL_MCODE_JMP0) | 4388 BWN_MACCTL_MCODE_RUN); 4389 4390 for (i = 0; i < 21; i++) { 4391 if (BWN_READ_4(mac, BWN_INTR_REASON) == BWN_INTR_MAC_SUSPENDED) 4392 break; 4393 if (i >= 20) { 4394 device_printf(sc->sc_dev, "ucode timeout\n"); 4395 error = ENXIO; 4396 goto error; 4397 } 4398 DELAY(50000); 4399 } 4400 BWN_READ_4(mac, BWN_INTR_REASON); 4401 4402 mac->mac_fw.rev = bwn_shm_read_2(mac, BWN_SHARED, BWN_SHARED_UCODE_REV); 4403 if (mac->mac_fw.rev <= 0x128) { 4404 device_printf(sc->sc_dev, "the firmware is too old\n"); 4405 error = EOPNOTSUPP; 4406 goto error; 4407 } 4408 4409 /* 4410 * Determine firmware header version; needed for TX/RX packet 4411 * handling. 4412 */ 4413 if (mac->mac_fw.rev >= 598) 4414 mac->mac_fw.fw_hdr_format = BWN_FW_HDR_598; 4415 else if (mac->mac_fw.rev >= 410) 4416 mac->mac_fw.fw_hdr_format = BWN_FW_HDR_410; 4417 else 4418 mac->mac_fw.fw_hdr_format = BWN_FW_HDR_351; 4419 4420 /* 4421 * We don't support rev 598 or later; that requires 4422 * another round of changes to the TX/RX descriptor 4423 * and status layout. 4424 * 4425 * So, complain this is the case and exit out, rather 4426 * than attaching and then failing. 4427 */ 4428 #if 0 4429 if (mac->mac_fw.fw_hdr_format == BWN_FW_HDR_598) { 4430 device_printf(sc->sc_dev, 4431 "firmware is too new (>=598); not supported\n"); 4432 error = EOPNOTSUPP; 4433 goto error; 4434 } 4435 #endif 4436 4437 mac->mac_fw.patch = bwn_shm_read_2(mac, BWN_SHARED, 4438 BWN_SHARED_UCODE_PATCH); 4439 date = bwn_shm_read_2(mac, BWN_SHARED, BWN_SHARED_UCODE_DATE); 4440 mac->mac_fw.opensource = (date == 0xffff); 4441 if (bwn_wme != 0) 4442 mac->mac_flags |= BWN_MAC_FLAG_WME; 4443 mac->mac_flags |= BWN_MAC_FLAG_HWCRYPTO; 4444 4445 time = bwn_shm_read_2(mac, BWN_SHARED, BWN_SHARED_UCODE_TIME); 4446 if (mac->mac_fw.opensource == 0) { 4447 device_printf(sc->sc_dev, 4448 "firmware version (rev %u patch %u date %#x time %#x)\n", 4449 mac->mac_fw.rev, mac->mac_fw.patch, date, time); 4450 if (mac->mac_fw.no_pcmfile) 4451 device_printf(sc->sc_dev, 4452 "no HW crypto acceleration due to pcm5\n"); 4453 } else { 4454 mac->mac_fw.patch = time; 4455 fwcaps = bwn_fwcaps_read(mac); 4456 if (!(fwcaps & BWN_FWCAPS_HWCRYPTO) || mac->mac_fw.no_pcmfile) { 4457 device_printf(sc->sc_dev, 4458 "disabling HW crypto acceleration\n"); 4459 mac->mac_flags &= ~BWN_MAC_FLAG_HWCRYPTO; 4460 } 4461 if (!(fwcaps & BWN_FWCAPS_WME)) { 4462 device_printf(sc->sc_dev, "disabling WME support\n"); 4463 mac->mac_flags &= ~BWN_MAC_FLAG_WME; 4464 } 4465 } 4466 4467 if (BWN_ISOLDFMT(mac)) 4468 device_printf(sc->sc_dev, "using old firmware image\n"); 4469 4470 return (0); 4471 4472 error: 4473 BWN_WRITE_4(mac, BWN_MACCTL, 4474 (BWN_READ_4(mac, BWN_MACCTL) & ~BWN_MACCTL_MCODE_RUN) | 4475 BWN_MACCTL_MCODE_JMP0); 4476 4477 return (error); 4478 #undef GETFWSIZE 4479 #undef GETFWOFFSET 4480 } 4481 4482 /* OpenFirmware only */ 4483 static uint16_t 4484 bwn_fwcaps_read(struct bwn_mac *mac) 4485 { 4486 4487 KASSERT(mac->mac_fw.opensource == 1, 4488 ("%s:%d: fail", __func__, __LINE__)); 4489 return (bwn_shm_read_2(mac, BWN_SHARED, BWN_SHARED_FWCAPS)); 4490 } 4491 4492 static int 4493 bwn_fwinitvals_write(struct bwn_mac *mac, const struct bwn_fwinitvals *ivals, 4494 size_t count, size_t array_size) 4495 { 4496 #define GET_NEXTIV16(iv) \ 4497 ((const struct bwn_fwinitvals *)((const uint8_t *)(iv) + \ 4498 sizeof(uint16_t) + sizeof(uint16_t))) 4499 #define GET_NEXTIV32(iv) \ 4500 ((const struct bwn_fwinitvals *)((const uint8_t *)(iv) + \ 4501 sizeof(uint16_t) + sizeof(uint32_t))) 4502 struct bwn_softc *sc = mac->mac_sc; 4503 const struct bwn_fwinitvals *iv; 4504 uint16_t offset; 4505 size_t i; 4506 uint8_t bit32; 4507 4508 KASSERT(sizeof(struct bwn_fwinitvals) == 6, 4509 ("%s:%d: fail", __func__, __LINE__)); 4510 iv = ivals; 4511 for (i = 0; i < count; i++) { 4512 if (array_size < sizeof(iv->offset_size)) 4513 goto fail; 4514 array_size -= sizeof(iv->offset_size); 4515 offset = be16toh(iv->offset_size); 4516 bit32 = (offset & BWN_FWINITVALS_32BIT) ? 1 : 0; 4517 offset &= BWN_FWINITVALS_OFFSET_MASK; 4518 if (offset >= 0x1000) 4519 goto fail; 4520 if (bit32) { 4521 if (array_size < sizeof(iv->data.d32)) 4522 goto fail; 4523 array_size -= sizeof(iv->data.d32); 4524 BWN_WRITE_4(mac, offset, be32toh(iv->data.d32)); 4525 iv = GET_NEXTIV32(iv); 4526 } else { 4527 if (array_size < sizeof(iv->data.d16)) 4528 goto fail; 4529 array_size -= sizeof(iv->data.d16); 4530 BWN_WRITE_2(mac, offset, be16toh(iv->data.d16)); 4531 4532 iv = GET_NEXTIV16(iv); 4533 } 4534 } 4535 if (array_size != 0) 4536 goto fail; 4537 return (0); 4538 fail: 4539 device_printf(sc->sc_dev, "initvals: invalid format\n"); 4540 return (EPROTO); 4541 #undef GET_NEXTIV16 4542 #undef GET_NEXTIV32 4543 } 4544 4545 int 4546 bwn_switch_channel(struct bwn_mac *mac, int chan) 4547 { 4548 struct bwn_phy *phy = &(mac->mac_phy); 4549 struct bwn_softc *sc = mac->mac_sc; 4550 struct ieee80211com *ic = &sc->sc_ic; 4551 uint16_t channelcookie, savedcookie; 4552 int error; 4553 4554 if (chan == 0xffff) 4555 chan = phy->get_default_chan(mac); 4556 4557 channelcookie = chan; 4558 if (IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan)) 4559 channelcookie |= 0x100; 4560 savedcookie = bwn_shm_read_2(mac, BWN_SHARED, BWN_SHARED_CHAN); 4561 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_CHAN, channelcookie); 4562 error = phy->switch_channel(mac, chan); 4563 if (error) 4564 goto fail; 4565 4566 mac->mac_phy.chan = chan; 4567 DELAY(8000); 4568 return (0); 4569 fail: 4570 device_printf(sc->sc_dev, "failed to switch channel\n"); 4571 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_CHAN, savedcookie); 4572 return (error); 4573 } 4574 4575 static uint16_t 4576 bwn_ant2phy(int antenna) 4577 { 4578 4579 switch (antenna) { 4580 case BWN_ANT0: 4581 return (BWN_TX_PHY_ANT0); 4582 case BWN_ANT1: 4583 return (BWN_TX_PHY_ANT1); 4584 case BWN_ANT2: 4585 return (BWN_TX_PHY_ANT2); 4586 case BWN_ANT3: 4587 return (BWN_TX_PHY_ANT3); 4588 case BWN_ANTAUTO: 4589 return (BWN_TX_PHY_ANT01AUTO); 4590 } 4591 KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__)); 4592 return (0); 4593 } 4594 4595 static void 4596 bwn_wme_load(struct bwn_mac *mac) 4597 { 4598 struct bwn_softc *sc = mac->mac_sc; 4599 int i; 4600 4601 KASSERT(N(bwn_wme_shm_offsets) == N(sc->sc_wmeParams), 4602 ("%s:%d: fail", __func__, __LINE__)); 4603 4604 bwn_mac_suspend(mac); 4605 for (i = 0; i < N(sc->sc_wmeParams); i++) 4606 bwn_wme_loadparams(mac, &(sc->sc_wmeParams[i]), 4607 bwn_wme_shm_offsets[i]); 4608 bwn_mac_enable(mac); 4609 } 4610 4611 static void 4612 bwn_wme_loadparams(struct bwn_mac *mac, 4613 const struct wmeParams *p, uint16_t shm_offset) 4614 { 4615 #define SM(_v, _f) (((_v) << _f##_S) & _f) 4616 struct bwn_softc *sc = mac->mac_sc; 4617 uint16_t params[BWN_NR_WMEPARAMS]; 4618 int slot, tmp; 4619 unsigned int i; 4620 4621 slot = BWN_READ_2(mac, BWN_RNG) & 4622 SM(p->wmep_logcwmin, WME_PARAM_LOGCWMIN); 4623 4624 memset(¶ms, 0, sizeof(params)); 4625 4626 DPRINTF(sc, BWN_DEBUG_WME, "wmep_txopLimit %d wmep_logcwmin %d " 4627 "wmep_logcwmax %d wmep_aifsn %d\n", p->wmep_txopLimit, 4628 p->wmep_logcwmin, p->wmep_logcwmax, p->wmep_aifsn); 4629 4630 params[BWN_WMEPARAM_TXOP] = p->wmep_txopLimit * 32; 4631 params[BWN_WMEPARAM_CWMIN] = SM(p->wmep_logcwmin, WME_PARAM_LOGCWMIN); 4632 params[BWN_WMEPARAM_CWMAX] = SM(p->wmep_logcwmax, WME_PARAM_LOGCWMAX); 4633 params[BWN_WMEPARAM_CWCUR] = SM(p->wmep_logcwmin, WME_PARAM_LOGCWMIN); 4634 params[BWN_WMEPARAM_AIFS] = p->wmep_aifsn; 4635 params[BWN_WMEPARAM_BSLOTS] = slot; 4636 params[BWN_WMEPARAM_REGGAP] = slot + p->wmep_aifsn; 4637 4638 for (i = 0; i < N(params); i++) { 4639 if (i == BWN_WMEPARAM_STATUS) { 4640 tmp = bwn_shm_read_2(mac, BWN_SHARED, 4641 shm_offset + (i * 2)); 4642 tmp |= 0x100; 4643 bwn_shm_write_2(mac, BWN_SHARED, shm_offset + (i * 2), 4644 tmp); 4645 } else { 4646 bwn_shm_write_2(mac, BWN_SHARED, shm_offset + (i * 2), 4647 params[i]); 4648 } 4649 } 4650 } 4651 4652 static void 4653 bwn_mac_write_bssid(struct bwn_mac *mac) 4654 { 4655 struct bwn_softc *sc = mac->mac_sc; 4656 uint32_t tmp; 4657 int i; 4658 uint8_t mac_bssid[IEEE80211_ADDR_LEN * 2]; 4659 4660 bwn_mac_setfilter(mac, BWN_MACFILTER_BSSID, sc->sc_bssid); 4661 memcpy(mac_bssid, sc->sc_ic.ic_macaddr, IEEE80211_ADDR_LEN); 4662 memcpy(mac_bssid + IEEE80211_ADDR_LEN, sc->sc_bssid, 4663 IEEE80211_ADDR_LEN); 4664 4665 for (i = 0; i < N(mac_bssid); i += sizeof(uint32_t)) { 4666 tmp = (uint32_t) (mac_bssid[i + 0]); 4667 tmp |= (uint32_t) (mac_bssid[i + 1]) << 8; 4668 tmp |= (uint32_t) (mac_bssid[i + 2]) << 16; 4669 tmp |= (uint32_t) (mac_bssid[i + 3]) << 24; 4670 bwn_ram_write(mac, 0x20 + i, tmp); 4671 } 4672 } 4673 4674 static void 4675 bwn_mac_setfilter(struct bwn_mac *mac, uint16_t offset, 4676 const uint8_t *macaddr) 4677 { 4678 static const uint8_t zero[IEEE80211_ADDR_LEN] = { 0 }; 4679 uint16_t data; 4680 4681 if (!mac) 4682 macaddr = zero; 4683 4684 offset |= 0x0020; 4685 BWN_WRITE_2(mac, BWN_MACFILTER_CONTROL, offset); 4686 4687 data = macaddr[0]; 4688 data |= macaddr[1] << 8; 4689 BWN_WRITE_2(mac, BWN_MACFILTER_DATA, data); 4690 data = macaddr[2]; 4691 data |= macaddr[3] << 8; 4692 BWN_WRITE_2(mac, BWN_MACFILTER_DATA, data); 4693 data = macaddr[4]; 4694 data |= macaddr[5] << 8; 4695 BWN_WRITE_2(mac, BWN_MACFILTER_DATA, data); 4696 } 4697 4698 static void 4699 bwn_key_dowrite(struct bwn_mac *mac, uint8_t index, uint8_t algorithm, 4700 const uint8_t *key, size_t key_len, const uint8_t *mac_addr) 4701 { 4702 uint8_t buf[BWN_SEC_KEYSIZE] = { 0, }; 4703 uint8_t per_sta_keys_start = 8; 4704 4705 if (BWN_SEC_NEWAPI(mac)) 4706 per_sta_keys_start = 4; 4707 4708 KASSERT(index < mac->mac_max_nr_keys, 4709 ("%s:%d: fail", __func__, __LINE__)); 4710 KASSERT(key_len <= BWN_SEC_KEYSIZE, 4711 ("%s:%d: fail", __func__, __LINE__)); 4712 4713 if (index >= per_sta_keys_start) 4714 bwn_key_macwrite(mac, index, NULL); 4715 if (key) 4716 memcpy(buf, key, key_len); 4717 bwn_key_write(mac, index, algorithm, buf); 4718 if (index >= per_sta_keys_start) 4719 bwn_key_macwrite(mac, index, mac_addr); 4720 4721 mac->mac_key[index].algorithm = algorithm; 4722 } 4723 4724 static void 4725 bwn_key_macwrite(struct bwn_mac *mac, uint8_t index, const uint8_t *addr) 4726 { 4727 struct bwn_softc *sc = mac->mac_sc; 4728 uint32_t addrtmp[2] = { 0, 0 }; 4729 uint8_t start = 8; 4730 4731 if (BWN_SEC_NEWAPI(mac)) 4732 start = 4; 4733 4734 KASSERT(index >= start, 4735 ("%s:%d: fail", __func__, __LINE__)); 4736 index -= start; 4737 4738 if (addr) { 4739 addrtmp[0] = addr[0]; 4740 addrtmp[0] |= ((uint32_t) (addr[1]) << 8); 4741 addrtmp[0] |= ((uint32_t) (addr[2]) << 16); 4742 addrtmp[0] |= ((uint32_t) (addr[3]) << 24); 4743 addrtmp[1] = addr[4]; 4744 addrtmp[1] |= ((uint32_t) (addr[5]) << 8); 4745 } 4746 4747 if (bhnd_get_hwrev(sc->sc_dev) >= 5) { 4748 bwn_shm_write_4(mac, BWN_RCMTA, (index * 2) + 0, addrtmp[0]); 4749 bwn_shm_write_2(mac, BWN_RCMTA, (index * 2) + 1, addrtmp[1]); 4750 } else { 4751 if (index >= 8) { 4752 bwn_shm_write_4(mac, BWN_SHARED, 4753 BWN_SHARED_PSM + (index * 6) + 0, addrtmp[0]); 4754 bwn_shm_write_2(mac, BWN_SHARED, 4755 BWN_SHARED_PSM + (index * 6) + 4, addrtmp[1]); 4756 } 4757 } 4758 } 4759 4760 static void 4761 bwn_key_write(struct bwn_mac *mac, uint8_t index, uint8_t algorithm, 4762 const uint8_t *key) 4763 { 4764 unsigned int i; 4765 uint32_t offset; 4766 uint16_t kidx, value; 4767 4768 kidx = BWN_SEC_KEY2FW(mac, index); 4769 bwn_shm_write_2(mac, BWN_SHARED, 4770 BWN_SHARED_KEYIDX_BLOCK + (kidx * 2), (kidx << 4) | algorithm); 4771 4772 offset = mac->mac_ktp + (index * BWN_SEC_KEYSIZE); 4773 for (i = 0; i < BWN_SEC_KEYSIZE; i += 2) { 4774 value = key[i]; 4775 value |= (uint16_t)(key[i + 1]) << 8; 4776 bwn_shm_write_2(mac, BWN_SHARED, offset + i, value); 4777 } 4778 } 4779 4780 static void 4781 bwn_phy_exit(struct bwn_mac *mac) 4782 { 4783 4784 mac->mac_phy.rf_onoff(mac, 0); 4785 if (mac->mac_phy.exit != NULL) 4786 mac->mac_phy.exit(mac); 4787 } 4788 4789 static void 4790 bwn_dma_free(struct bwn_mac *mac) 4791 { 4792 struct bwn_dma *dma; 4793 4794 if ((mac->mac_flags & BWN_MAC_FLAG_DMA) == 0) 4795 return; 4796 dma = &mac->mac_method.dma; 4797 4798 bwn_dma_ringfree(&dma->rx); 4799 bwn_dma_ringfree(&dma->wme[WME_AC_BK]); 4800 bwn_dma_ringfree(&dma->wme[WME_AC_BE]); 4801 bwn_dma_ringfree(&dma->wme[WME_AC_VI]); 4802 bwn_dma_ringfree(&dma->wme[WME_AC_VO]); 4803 bwn_dma_ringfree(&dma->mcast); 4804 } 4805 4806 static void 4807 bwn_core_stop(struct bwn_mac *mac) 4808 { 4809 struct bwn_softc *sc = mac->mac_sc; 4810 4811 BWN_ASSERT_LOCKED(sc); 4812 4813 if (mac->mac_status < BWN_MAC_STATUS_STARTED) 4814 return; 4815 4816 callout_stop(&sc->sc_rfswitch_ch); 4817 callout_stop(&sc->sc_task_ch); 4818 callout_stop(&sc->sc_watchdog_ch); 4819 sc->sc_watchdog_timer = 0; 4820 BWN_WRITE_4(mac, BWN_INTR_MASK, 0); 4821 BWN_READ_4(mac, BWN_INTR_MASK); 4822 bwn_mac_suspend(mac); 4823 4824 mac->mac_status = BWN_MAC_STATUS_INITED; 4825 } 4826 4827 static int 4828 bwn_switch_band(struct bwn_softc *sc, struct ieee80211_channel *chan) 4829 { 4830 struct bwn_mac *up_dev = NULL; 4831 struct bwn_mac *down_dev; 4832 struct bwn_mac *mac; 4833 int err, status; 4834 uint8_t gmode; 4835 4836 BWN_ASSERT_LOCKED(sc); 4837 4838 TAILQ_FOREACH(mac, &sc->sc_maclist, mac_list) { 4839 if (IEEE80211_IS_CHAN_2GHZ(chan) && 4840 mac->mac_phy.supports_2ghz) { 4841 up_dev = mac; 4842 gmode = 1; 4843 } else if (IEEE80211_IS_CHAN_5GHZ(chan) && 4844 mac->mac_phy.supports_5ghz) { 4845 up_dev = mac; 4846 gmode = 0; 4847 } else { 4848 KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__)); 4849 return (EINVAL); 4850 } 4851 if (up_dev != NULL) 4852 break; 4853 } 4854 if (up_dev == NULL) { 4855 device_printf(sc->sc_dev, "Could not find a device\n"); 4856 return (ENODEV); 4857 } 4858 if (up_dev == sc->sc_curmac && sc->sc_curmac->mac_phy.gmode == gmode) 4859 return (0); 4860 4861 DPRINTF(sc, BWN_DEBUG_RF | BWN_DEBUG_PHY | BWN_DEBUG_RESET, 4862 "switching to %s-GHz band\n", 4863 IEEE80211_IS_CHAN_2GHZ(chan) ? "2" : "5"); 4864 4865 down_dev = sc->sc_curmac; 4866 status = down_dev->mac_status; 4867 if (status >= BWN_MAC_STATUS_STARTED) 4868 bwn_core_stop(down_dev); 4869 if (status >= BWN_MAC_STATUS_INITED) 4870 bwn_core_exit(down_dev); 4871 4872 if (down_dev != up_dev) { 4873 err = bwn_phy_reset(down_dev); 4874 if (err) 4875 goto fail; 4876 } 4877 4878 up_dev->mac_phy.gmode = gmode; 4879 if (status >= BWN_MAC_STATUS_INITED) { 4880 err = bwn_core_init(up_dev); 4881 if (err) { 4882 device_printf(sc->sc_dev, 4883 "fatal: failed to initialize for %s-GHz\n", 4884 IEEE80211_IS_CHAN_2GHZ(chan) ? "2" : "5"); 4885 goto fail; 4886 } 4887 } 4888 if (status >= BWN_MAC_STATUS_STARTED) 4889 bwn_core_start(up_dev); 4890 KASSERT(up_dev->mac_status == status, ("%s: fail", __func__)); 4891 sc->sc_curmac = up_dev; 4892 4893 return (0); 4894 fail: 4895 sc->sc_curmac = NULL; 4896 return (err); 4897 } 4898 4899 static void 4900 bwn_rf_turnon(struct bwn_mac *mac) 4901 { 4902 4903 DPRINTF(mac->mac_sc, BWN_DEBUG_RESET, "%s: called\n", __func__); 4904 4905 bwn_mac_suspend(mac); 4906 mac->mac_phy.rf_onoff(mac, 1); 4907 mac->mac_phy.rf_on = 1; 4908 bwn_mac_enable(mac); 4909 } 4910 4911 static void 4912 bwn_rf_turnoff(struct bwn_mac *mac) 4913 { 4914 4915 DPRINTF(mac->mac_sc, BWN_DEBUG_RESET, "%s: called\n", __func__); 4916 4917 bwn_mac_suspend(mac); 4918 mac->mac_phy.rf_onoff(mac, 0); 4919 mac->mac_phy.rf_on = 0; 4920 bwn_mac_enable(mac); 4921 } 4922 4923 /* 4924 * PHY reset. 4925 */ 4926 static int 4927 bwn_phy_reset(struct bwn_mac *mac) 4928 { 4929 struct bwn_softc *sc; 4930 uint16_t iost, mask; 4931 int error; 4932 4933 sc = mac->mac_sc; 4934 4935 iost = BWN_IOCTL_PHYRESET | BHND_IOCTL_CLK_FORCE; 4936 mask = iost | BWN_IOCTL_SUPPORT_G; 4937 4938 if ((error = bhnd_write_ioctl(sc->sc_dev, iost, mask))) 4939 return (error); 4940 4941 DELAY(1000); 4942 4943 iost &= ~BHND_IOCTL_CLK_FORCE; 4944 4945 if ((error = bhnd_write_ioctl(sc->sc_dev, iost, mask))) 4946 return (error); 4947 4948 DELAY(1000); 4949 4950 return (0); 4951 } 4952 4953 static int 4954 bwn_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 4955 { 4956 struct bwn_vap *bvp = BWN_VAP(vap); 4957 struct ieee80211com *ic= vap->iv_ic; 4958 enum ieee80211_state ostate = vap->iv_state; 4959 struct bwn_softc *sc = ic->ic_softc; 4960 struct bwn_mac *mac = sc->sc_curmac; 4961 int error; 4962 4963 DPRINTF(sc, BWN_DEBUG_STATE, "%s: %s -> %s\n", __func__, 4964 ieee80211_state_name[vap->iv_state], 4965 ieee80211_state_name[nstate]); 4966 4967 error = bvp->bv_newstate(vap, nstate, arg); 4968 if (error != 0) 4969 return (error); 4970 4971 BWN_LOCK(sc); 4972 4973 bwn_led_newstate(mac, nstate); 4974 4975 /* 4976 * Clear the BSSID when we stop a STA 4977 */ 4978 if (vap->iv_opmode == IEEE80211_M_STA) { 4979 if (ostate == IEEE80211_S_RUN && nstate != IEEE80211_S_RUN) { 4980 /* 4981 * Clear out the BSSID. If we reassociate to 4982 * the same AP, this will reinialize things 4983 * correctly... 4984 */ 4985 if (ic->ic_opmode == IEEE80211_M_STA && 4986 (sc->sc_flags & BWN_FLAG_INVALID) == 0) { 4987 memset(sc->sc_bssid, 0, IEEE80211_ADDR_LEN); 4988 bwn_set_macaddr(mac); 4989 } 4990 } 4991 } 4992 4993 if (vap->iv_opmode == IEEE80211_M_MONITOR || 4994 vap->iv_opmode == IEEE80211_M_AHDEMO) { 4995 /* XXX nothing to do? */ 4996 } else if (nstate == IEEE80211_S_RUN) { 4997 memcpy(sc->sc_bssid, vap->iv_bss->ni_bssid, IEEE80211_ADDR_LEN); 4998 bwn_set_opmode(mac); 4999 bwn_set_pretbtt(mac); 5000 bwn_spu_setdelay(mac, 0); 5001 bwn_set_macaddr(mac); 5002 } 5003 5004 BWN_UNLOCK(sc); 5005 5006 return (error); 5007 } 5008 5009 static void 5010 bwn_set_pretbtt(struct bwn_mac *mac) 5011 { 5012 struct bwn_softc *sc = mac->mac_sc; 5013 struct ieee80211com *ic = &sc->sc_ic; 5014 uint16_t pretbtt; 5015 5016 if (ic->ic_opmode == IEEE80211_M_IBSS) 5017 pretbtt = 2; 5018 else 5019 pretbtt = (mac->mac_phy.type == BWN_PHYTYPE_A) ? 120 : 250; 5020 bwn_shm_write_2(mac, BWN_SHARED, BWN_SHARED_PRETBTT, pretbtt); 5021 BWN_WRITE_2(mac, BWN_TSF_CFP_PRETBTT, pretbtt); 5022 } 5023 5024 static int 5025 bwn_intr(void *arg) 5026 { 5027 struct bwn_mac *mac = arg; 5028 struct bwn_softc *sc = mac->mac_sc; 5029 uint32_t reason; 5030 5031 if (mac->mac_status < BWN_MAC_STATUS_STARTED || 5032 (sc->sc_flags & BWN_FLAG_INVALID)) 5033 return (FILTER_STRAY); 5034 5035 DPRINTF(sc, BWN_DEBUG_INTR, "%s: called\n", __func__); 5036 5037 reason = BWN_READ_4(mac, BWN_INTR_REASON); 5038 if (reason == 0xffffffff) /* shared IRQ */ 5039 return (FILTER_STRAY); 5040 reason &= mac->mac_intr_mask; 5041 if (reason == 0) 5042 return (FILTER_HANDLED); 5043 DPRINTF(sc, BWN_DEBUG_INTR, "%s: reason=0x%08x\n", __func__, reason); 5044 5045 mac->mac_reason[0] = BWN_READ_4(mac, BWN_DMA0_REASON) & 0x0001dc00; 5046 mac->mac_reason[1] = BWN_READ_4(mac, BWN_DMA1_REASON) & 0x0000dc00; 5047 mac->mac_reason[2] = BWN_READ_4(mac, BWN_DMA2_REASON) & 0x0000dc00; 5048 mac->mac_reason[3] = BWN_READ_4(mac, BWN_DMA3_REASON) & 0x0001dc00; 5049 mac->mac_reason[4] = BWN_READ_4(mac, BWN_DMA4_REASON) & 0x0000dc00; 5050 BWN_WRITE_4(mac, BWN_INTR_REASON, reason); 5051 BWN_WRITE_4(mac, BWN_DMA0_REASON, mac->mac_reason[0]); 5052 BWN_WRITE_4(mac, BWN_DMA1_REASON, mac->mac_reason[1]); 5053 BWN_WRITE_4(mac, BWN_DMA2_REASON, mac->mac_reason[2]); 5054 BWN_WRITE_4(mac, BWN_DMA3_REASON, mac->mac_reason[3]); 5055 BWN_WRITE_4(mac, BWN_DMA4_REASON, mac->mac_reason[4]); 5056 5057 /* Disable interrupts. */ 5058 BWN_WRITE_4(mac, BWN_INTR_MASK, 0); 5059 5060 mac->mac_reason_intr = reason; 5061 5062 BWN_BARRIER(mac, 0, 0, BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE); 5063 5064 taskqueue_enqueue(sc->sc_tq, &mac->mac_intrtask); 5065 return (FILTER_HANDLED); 5066 } 5067 5068 static void 5069 bwn_intrtask(void *arg, int npending) 5070 { 5071 struct epoch_tracker et; 5072 struct bwn_mac *mac = arg; 5073 struct bwn_softc *sc = mac->mac_sc; 5074 uint32_t merged = 0; 5075 int i, tx = 0, rx = 0; 5076 5077 BWN_LOCK(sc); 5078 if (mac->mac_status < BWN_MAC_STATUS_STARTED || 5079 (sc->sc_flags & BWN_FLAG_INVALID)) { 5080 BWN_UNLOCK(sc); 5081 return; 5082 } 5083 5084 for (i = 0; i < N(mac->mac_reason); i++) 5085 merged |= mac->mac_reason[i]; 5086 5087 if (mac->mac_reason_intr & BWN_INTR_MAC_TXERR) 5088 device_printf(sc->sc_dev, "MAC trans error\n"); 5089 5090 if (mac->mac_reason_intr & BWN_INTR_PHY_TXERR) { 5091 DPRINTF(sc, BWN_DEBUG_INTR, "%s: PHY trans error\n", __func__); 5092 mac->mac_phy.txerrors--; 5093 if (mac->mac_phy.txerrors == 0) { 5094 mac->mac_phy.txerrors = BWN_TXERROR_MAX; 5095 bwn_restart(mac, "PHY TX errors"); 5096 } 5097 } 5098 5099 if (merged & (BWN_DMAINTR_FATALMASK | BWN_DMAINTR_NONFATALMASK)) { 5100 if (merged & BWN_DMAINTR_FATALMASK) { 5101 device_printf(sc->sc_dev, 5102 "Fatal DMA error: %#x %#x %#x %#x %#x %#x\n", 5103 mac->mac_reason[0], mac->mac_reason[1], 5104 mac->mac_reason[2], mac->mac_reason[3], 5105 mac->mac_reason[4], mac->mac_reason[5]); 5106 bwn_restart(mac, "DMA error"); 5107 BWN_UNLOCK(sc); 5108 return; 5109 } 5110 if (merged & BWN_DMAINTR_NONFATALMASK) { 5111 device_printf(sc->sc_dev, 5112 "DMA error: %#x %#x %#x %#x %#x %#x\n", 5113 mac->mac_reason[0], mac->mac_reason[1], 5114 mac->mac_reason[2], mac->mac_reason[3], 5115 mac->mac_reason[4], mac->mac_reason[5]); 5116 } 5117 } 5118 5119 if (mac->mac_reason_intr & BWN_INTR_UCODE_DEBUG) 5120 bwn_intr_ucode_debug(mac); 5121 if (mac->mac_reason_intr & BWN_INTR_TBTT_INDI) 5122 bwn_intr_tbtt_indication(mac); 5123 if (mac->mac_reason_intr & BWN_INTR_ATIM_END) 5124 bwn_intr_atim_end(mac); 5125 if (mac->mac_reason_intr & BWN_INTR_BEACON) 5126 bwn_intr_beacon(mac); 5127 if (mac->mac_reason_intr & BWN_INTR_PMQ) 5128 bwn_intr_pmq(mac); 5129 if (mac->mac_reason_intr & BWN_INTR_NOISESAMPLE_OK) 5130 bwn_intr_noise(mac); 5131 5132 NET_EPOCH_ENTER(et); 5133 if (mac->mac_flags & BWN_MAC_FLAG_DMA) { 5134 if (mac->mac_reason[0] & BWN_DMAINTR_RX_DONE) { 5135 bwn_dma_rx(mac->mac_method.dma.rx); 5136 rx = 1; 5137 } 5138 } else 5139 rx = bwn_pio_rx(&mac->mac_method.pio.rx); 5140 NET_EPOCH_EXIT(et); 5141 5142 KASSERT(!(mac->mac_reason[1] & BWN_DMAINTR_RX_DONE), ("%s", __func__)); 5143 KASSERT(!(mac->mac_reason[2] & BWN_DMAINTR_RX_DONE), ("%s", __func__)); 5144 KASSERT(!(mac->mac_reason[3] & BWN_DMAINTR_RX_DONE), ("%s", __func__)); 5145 KASSERT(!(mac->mac_reason[4] & BWN_DMAINTR_RX_DONE), ("%s", __func__)); 5146 KASSERT(!(mac->mac_reason[5] & BWN_DMAINTR_RX_DONE), ("%s", __func__)); 5147 5148 if (mac->mac_reason_intr & BWN_INTR_TX_OK) { 5149 bwn_intr_txeof(mac); 5150 tx = 1; 5151 } 5152 5153 BWN_WRITE_4(mac, BWN_INTR_MASK, mac->mac_intr_mask); 5154 5155 if (sc->sc_blink_led != NULL && sc->sc_led_blink) { 5156 int evt = BWN_LED_EVENT_NONE; 5157 5158 if (tx && rx) { 5159 if (sc->sc_rx_rate > sc->sc_tx_rate) 5160 evt = BWN_LED_EVENT_RX; 5161 else 5162 evt = BWN_LED_EVENT_TX; 5163 } else if (tx) { 5164 evt = BWN_LED_EVENT_TX; 5165 } else if (rx) { 5166 evt = BWN_LED_EVENT_RX; 5167 } else if (rx == 0) { 5168 evt = BWN_LED_EVENT_POLL; 5169 } 5170 5171 if (evt != BWN_LED_EVENT_NONE) 5172 bwn_led_event(mac, evt); 5173 } 5174 5175 if (mbufq_first(&sc->sc_snd) != NULL) 5176 bwn_start(sc); 5177 5178 BWN_BARRIER(mac, 0, 0, BUS_SPACE_BARRIER_READ|BUS_SPACE_BARRIER_WRITE); 5179 5180 BWN_UNLOCK(sc); 5181 } 5182 5183 static void 5184 bwn_restart(struct bwn_mac *mac, const char *msg) 5185 { 5186 struct bwn_softc *sc = mac->mac_sc; 5187 struct ieee80211com *ic = &sc->sc_ic; 5188 5189 if (mac->mac_status < BWN_MAC_STATUS_INITED) 5190 return; 5191 5192 device_printf(sc->sc_dev, "HW reset: %s\n", msg); 5193 ieee80211_runtask(ic, &mac->mac_hwreset); 5194 } 5195 5196 static void 5197 bwn_intr_ucode_debug(struct bwn_mac *mac) 5198 { 5199 struct bwn_softc *sc = mac->mac_sc; 5200 uint16_t reason; 5201 5202 if (mac->mac_fw.opensource == 0) 5203 return; 5204 5205 reason = bwn_shm_read_2(mac, BWN_SCRATCH, BWN_DEBUGINTR_REASON_REG); 5206 switch (reason) { 5207 case BWN_DEBUGINTR_PANIC: 5208 bwn_handle_fwpanic(mac); 5209 break; 5210 case BWN_DEBUGINTR_DUMP_SHM: 5211 device_printf(sc->sc_dev, "BWN_DEBUGINTR_DUMP_SHM\n"); 5212 break; 5213 case BWN_DEBUGINTR_DUMP_REGS: 5214 device_printf(sc->sc_dev, "BWN_DEBUGINTR_DUMP_REGS\n"); 5215 break; 5216 case BWN_DEBUGINTR_MARKER: 5217 device_printf(sc->sc_dev, "BWN_DEBUGINTR_MARKER\n"); 5218 break; 5219 default: 5220 device_printf(sc->sc_dev, 5221 "ucode debug unknown reason: %#x\n", reason); 5222 } 5223 5224 bwn_shm_write_2(mac, BWN_SCRATCH, BWN_DEBUGINTR_REASON_REG, 5225 BWN_DEBUGINTR_ACK); 5226 } 5227 5228 static void 5229 bwn_intr_tbtt_indication(struct bwn_mac *mac) 5230 { 5231 struct bwn_softc *sc = mac->mac_sc; 5232 struct ieee80211com *ic = &sc->sc_ic; 5233 5234 if (ic->ic_opmode != IEEE80211_M_HOSTAP) 5235 bwn_psctl(mac, 0); 5236 if (ic->ic_opmode == IEEE80211_M_IBSS) 5237 mac->mac_flags |= BWN_MAC_FLAG_DFQVALID; 5238 } 5239 5240 static void 5241 bwn_intr_atim_end(struct bwn_mac *mac) 5242 { 5243 5244 if (mac->mac_flags & BWN_MAC_FLAG_DFQVALID) { 5245 BWN_WRITE_4(mac, BWN_MACCMD, 5246 BWN_READ_4(mac, BWN_MACCMD) | BWN_MACCMD_DFQ_VALID); 5247 mac->mac_flags &= ~BWN_MAC_FLAG_DFQVALID; 5248 } 5249 } 5250 5251 static void 5252 bwn_intr_beacon(struct bwn_mac *mac) 5253 { 5254 struct bwn_softc *sc = mac->mac_sc; 5255 struct ieee80211com *ic = &sc->sc_ic; 5256 uint32_t cmd, beacon0, beacon1; 5257 5258 if (ic->ic_opmode == IEEE80211_M_HOSTAP || 5259 ic->ic_opmode == IEEE80211_M_MBSS) 5260 return; 5261 5262 mac->mac_intr_mask &= ~BWN_INTR_BEACON; 5263 5264 cmd = BWN_READ_4(mac, BWN_MACCMD); 5265 beacon0 = (cmd & BWN_MACCMD_BEACON0_VALID); 5266 beacon1 = (cmd & BWN_MACCMD_BEACON1_VALID); 5267 5268 if (beacon0 && beacon1) { 5269 BWN_WRITE_4(mac, BWN_INTR_REASON, BWN_INTR_BEACON); 5270 mac->mac_intr_mask |= BWN_INTR_BEACON; 5271 return; 5272 } 5273 5274 if (sc->sc_flags & BWN_FLAG_NEED_BEACON_TP) { 5275 sc->sc_flags &= ~BWN_FLAG_NEED_BEACON_TP; 5276 bwn_load_beacon0(mac); 5277 bwn_load_beacon1(mac); 5278 cmd = BWN_READ_4(mac, BWN_MACCMD); 5279 cmd |= BWN_MACCMD_BEACON0_VALID; 5280 BWN_WRITE_4(mac, BWN_MACCMD, cmd); 5281 } else { 5282 if (!beacon0) { 5283 bwn_load_beacon0(mac); 5284 cmd = BWN_READ_4(mac, BWN_MACCMD); 5285 cmd |= BWN_MACCMD_BEACON0_VALID; 5286 BWN_WRITE_4(mac, BWN_MACCMD, cmd); 5287 } else if (!beacon1) { 5288 bwn_load_beacon1(mac); 5289 cmd = BWN_READ_4(mac, BWN_MACCMD); 5290 cmd |= BWN_MACCMD_BEACON1_VALID; 5291 BWN_WRITE_4(mac, BWN_MACCMD, cmd); 5292 } 5293 } 5294 } 5295 5296 static void 5297 bwn_intr_pmq(struct bwn_mac *mac) 5298 { 5299 uint32_t tmp; 5300 5301 while (1) { 5302 tmp = BWN_READ_4(mac, BWN_PS_STATUS); 5303 if (!(tmp & 0x00000008)) 5304 break; 5305 } 5306 BWN_WRITE_2(mac, BWN_PS_STATUS, 0x0002); 5307 } 5308 5309 static void 5310 bwn_intr_noise(struct bwn_mac *mac) 5311 { 5312 struct bwn_phy_g *pg = &mac->mac_phy.phy_g; 5313 uint16_t tmp; 5314 uint8_t noise[4]; 5315 uint8_t i, j; 5316 int32_t average; 5317 5318 if (mac->mac_phy.type != BWN_PHYTYPE_G) 5319 return; 5320 5321 KASSERT(mac->mac_noise.noi_running, ("%s: fail", __func__)); 5322 *((uint32_t *)noise) = htole32(bwn_jssi_read(mac)); 5323 if (noise[0] == 0x7f || noise[1] == 0x7f || noise[2] == 0x7f || 5324 noise[3] == 0x7f) 5325 goto new; 5326 5327 KASSERT(mac->mac_noise.noi_nsamples < 8, 5328 ("%s:%d: fail", __func__, __LINE__)); 5329 i = mac->mac_noise.noi_nsamples; 5330 noise[0] = MIN(MAX(noise[0], 0), N(pg->pg_nrssi_lt) - 1); 5331 noise[1] = MIN(MAX(noise[1], 0), N(pg->pg_nrssi_lt) - 1); 5332 noise[2] = MIN(MAX(noise[2], 0), N(pg->pg_nrssi_lt) - 1); 5333 noise[3] = MIN(MAX(noise[3], 0), N(pg->pg_nrssi_lt) - 1); 5334 mac->mac_noise.noi_samples[i][0] = pg->pg_nrssi_lt[noise[0]]; 5335 mac->mac_noise.noi_samples[i][1] = pg->pg_nrssi_lt[noise[1]]; 5336 mac->mac_noise.noi_samples[i][2] = pg->pg_nrssi_lt[noise[2]]; 5337 mac->mac_noise.noi_samples[i][3] = pg->pg_nrssi_lt[noise[3]]; 5338 mac->mac_noise.noi_nsamples++; 5339 if (mac->mac_noise.noi_nsamples == 8) { 5340 average = 0; 5341 for (i = 0; i < 8; i++) { 5342 for (j = 0; j < 4; j++) 5343 average += mac->mac_noise.noi_samples[i][j]; 5344 } 5345 average = (((average / 32) * 125) + 64) / 128; 5346 tmp = (bwn_shm_read_2(mac, BWN_SHARED, 0x40c) / 128) & 0x1f; 5347 if (tmp >= 8) 5348 average += 2; 5349 else 5350 average -= 25; 5351 average -= (tmp == 8) ? 72 : 48; 5352 5353 mac->mac_stats.link_noise = average; 5354 mac->mac_noise.noi_running = 0; 5355 return; 5356 } 5357 new: 5358 bwn_noise_gensample(mac); 5359 } 5360 5361 static int 5362 bwn_pio_rx(struct bwn_pio_rxqueue *prq) 5363 { 5364 struct bwn_mac *mac = prq->prq_mac; 5365 struct bwn_softc *sc = mac->mac_sc; 5366 unsigned int i; 5367 5368 BWN_ASSERT_LOCKED(sc); 5369 5370 if (mac->mac_status < BWN_MAC_STATUS_STARTED) 5371 return (0); 5372 5373 for (i = 0; i < 5000; i++) { 5374 if (bwn_pio_rxeof(prq) == 0) 5375 break; 5376 } 5377 if (i >= 5000) 5378 device_printf(sc->sc_dev, "too many RX frames in PIO mode\n"); 5379 return ((i > 0) ? 1 : 0); 5380 } 5381 5382 static void 5383 bwn_dma_rx(struct bwn_dma_ring *dr) 5384 { 5385 int slot, curslot; 5386 5387 KASSERT(!dr->dr_tx, ("%s:%d: fail", __func__, __LINE__)); 5388 curslot = dr->get_curslot(dr); 5389 KASSERT(curslot >= 0 && curslot < dr->dr_numslots, 5390 ("%s:%d: fail", __func__, __LINE__)); 5391 5392 slot = dr->dr_curslot; 5393 for (; slot != curslot; slot = bwn_dma_nextslot(dr, slot)) 5394 bwn_dma_rxeof(dr, &slot); 5395 5396 bus_dmamap_sync(dr->dr_ring_dtag, dr->dr_ring_dmap, 5397 BUS_DMASYNC_PREWRITE); 5398 5399 dr->set_curslot(dr, slot); 5400 dr->dr_curslot = slot; 5401 } 5402 5403 static void 5404 bwn_intr_txeof(struct bwn_mac *mac) 5405 { 5406 struct bwn_txstatus stat; 5407 uint32_t stat0, stat1; 5408 uint16_t tmp; 5409 5410 BWN_ASSERT_LOCKED(mac->mac_sc); 5411 5412 while (1) { 5413 stat0 = BWN_READ_4(mac, BWN_XMITSTAT_0); 5414 if (!(stat0 & 0x00000001)) 5415 break; 5416 stat1 = BWN_READ_4(mac, BWN_XMITSTAT_1); 5417 5418 DPRINTF(mac->mac_sc, BWN_DEBUG_XMIT, 5419 "%s: stat0=0x%08x, stat1=0x%08x\n", 5420 __func__, 5421 stat0, 5422 stat1); 5423 5424 stat.cookie = (stat0 >> 16); 5425 stat.seq = (stat1 & 0x0000ffff); 5426 stat.phy_stat = ((stat1 & 0x00ff0000) >> 16); 5427 tmp = (stat0 & 0x0000ffff); 5428 stat.framecnt = ((tmp & 0xf000) >> 12); 5429 stat.rtscnt = ((tmp & 0x0f00) >> 8); 5430 stat.sreason = ((tmp & 0x001c) >> 2); 5431 stat.pm = (tmp & 0x0080) ? 1 : 0; 5432 stat.im = (tmp & 0x0040) ? 1 : 0; 5433 stat.ampdu = (tmp & 0x0020) ? 1 : 0; 5434 stat.ack = (tmp & 0x0002) ? 1 : 0; 5435 5436 DPRINTF(mac->mac_sc, BWN_DEBUG_XMIT, 5437 "%s: cookie=%d, seq=%d, phystat=0x%02x, framecnt=%d, " 5438 "rtscnt=%d, sreason=%d, pm=%d, im=%d, ampdu=%d, ack=%d\n", 5439 __func__, 5440 stat.cookie, 5441 stat.seq, 5442 stat.phy_stat, 5443 stat.framecnt, 5444 stat.rtscnt, 5445 stat.sreason, 5446 stat.pm, 5447 stat.im, 5448 stat.ampdu, 5449 stat.ack); 5450 5451 bwn_handle_txeof(mac, &stat); 5452 } 5453 } 5454 5455 static void 5456 bwn_hwreset(void *arg, int npending) 5457 { 5458 struct bwn_mac *mac = arg; 5459 struct bwn_softc *sc = mac->mac_sc; 5460 int error = 0; 5461 int prev_status; 5462 5463 BWN_LOCK(sc); 5464 5465 prev_status = mac->mac_status; 5466 if (prev_status >= BWN_MAC_STATUS_STARTED) 5467 bwn_core_stop(mac); 5468 if (prev_status >= BWN_MAC_STATUS_INITED) 5469 bwn_core_exit(mac); 5470 5471 if (prev_status >= BWN_MAC_STATUS_INITED) { 5472 error = bwn_core_init(mac); 5473 if (error) 5474 goto out; 5475 } 5476 if (prev_status >= BWN_MAC_STATUS_STARTED) 5477 bwn_core_start(mac); 5478 out: 5479 if (error) { 5480 device_printf(sc->sc_dev, "%s: failed (%d)\n", __func__, error); 5481 sc->sc_curmac = NULL; 5482 } 5483 BWN_UNLOCK(sc); 5484 } 5485 5486 static void 5487 bwn_handle_fwpanic(struct bwn_mac *mac) 5488 { 5489 struct bwn_softc *sc = mac->mac_sc; 5490 uint16_t reason; 5491 5492 reason = bwn_shm_read_2(mac, BWN_SCRATCH, BWN_FWPANIC_REASON_REG); 5493 device_printf(sc->sc_dev,"fw panic (%u)\n", reason); 5494 5495 if (reason == BWN_FWPANIC_RESTART) 5496 bwn_restart(mac, "ucode panic"); 5497 } 5498 5499 static void 5500 bwn_load_beacon0(struct bwn_mac *mac) 5501 { 5502 5503 KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__)); 5504 } 5505 5506 static void 5507 bwn_load_beacon1(struct bwn_mac *mac) 5508 { 5509 5510 KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__)); 5511 } 5512 5513 static uint32_t 5514 bwn_jssi_read(struct bwn_mac *mac) 5515 { 5516 uint32_t val = 0; 5517 5518 val = bwn_shm_read_2(mac, BWN_SHARED, 0x08a); 5519 val <<= 16; 5520 val |= bwn_shm_read_2(mac, BWN_SHARED, 0x088); 5521 5522 return (val); 5523 } 5524 5525 static void 5526 bwn_noise_gensample(struct bwn_mac *mac) 5527 { 5528 uint32_t jssi = 0x7f7f7f7f; 5529 5530 bwn_shm_write_2(mac, BWN_SHARED, 0x088, (jssi & 0x0000ffff)); 5531 bwn_shm_write_2(mac, BWN_SHARED, 0x08a, (jssi & 0xffff0000) >> 16); 5532 BWN_WRITE_4(mac, BWN_MACCMD, 5533 BWN_READ_4(mac, BWN_MACCMD) | BWN_MACCMD_BGNOISE); 5534 } 5535 5536 static int 5537 bwn_dma_freeslot(struct bwn_dma_ring *dr) 5538 { 5539 BWN_ASSERT_LOCKED(dr->dr_mac->mac_sc); 5540 5541 return (dr->dr_numslots - dr->dr_usedslot); 5542 } 5543 5544 static int 5545 bwn_dma_nextslot(struct bwn_dma_ring *dr, int slot) 5546 { 5547 BWN_ASSERT_LOCKED(dr->dr_mac->mac_sc); 5548 5549 KASSERT(slot >= -1 && slot <= dr->dr_numslots - 1, 5550 ("%s:%d: fail", __func__, __LINE__)); 5551 if (slot == dr->dr_numslots - 1) 5552 return (0); 5553 return (slot + 1); 5554 } 5555 5556 static void 5557 bwn_dma_rxeof(struct bwn_dma_ring *dr, int *slot) 5558 { 5559 struct bwn_mac *mac = dr->dr_mac; 5560 struct bwn_softc *sc = mac->mac_sc; 5561 struct bwn_dma *dma = &mac->mac_method.dma; 5562 struct bwn_dmadesc_generic *desc; 5563 struct bwn_dmadesc_meta *meta; 5564 struct bwn_rxhdr4 *rxhdr; 5565 struct mbuf *m; 5566 uint32_t macstat; 5567 int32_t tmp; 5568 int cnt = 0; 5569 uint16_t len; 5570 5571 dr->getdesc(dr, *slot, &desc, &meta); 5572 5573 bus_dmamap_sync(dma->rxbuf_dtag, meta->mt_dmap, BUS_DMASYNC_POSTREAD); 5574 m = meta->mt_m; 5575 5576 if (bwn_dma_newbuf(dr, desc, meta, 0)) { 5577 counter_u64_add(sc->sc_ic.ic_ierrors, 1); 5578 return; 5579 } 5580 5581 rxhdr = mtod(m, struct bwn_rxhdr4 *); 5582 len = le16toh(rxhdr->frame_len); 5583 if (len <= 0) { 5584 counter_u64_add(sc->sc_ic.ic_ierrors, 1); 5585 return; 5586 } 5587 if (bwn_dma_check_redzone(dr, m)) { 5588 device_printf(sc->sc_dev, "redzone error.\n"); 5589 bwn_dma_set_redzone(dr, m); 5590 bus_dmamap_sync(dma->rxbuf_dtag, meta->mt_dmap, 5591 BUS_DMASYNC_PREWRITE); 5592 return; 5593 } 5594 if (len > dr->dr_rx_bufsize) { 5595 tmp = len; 5596 while (1) { 5597 dr->getdesc(dr, *slot, &desc, &meta); 5598 bwn_dma_set_redzone(dr, meta->mt_m); 5599 bus_dmamap_sync(dma->rxbuf_dtag, meta->mt_dmap, 5600 BUS_DMASYNC_PREWRITE); 5601 *slot = bwn_dma_nextslot(dr, *slot); 5602 cnt++; 5603 tmp -= dr->dr_rx_bufsize; 5604 if (tmp <= 0) 5605 break; 5606 } 5607 device_printf(sc->sc_dev, "too small buffer " 5608 "(len %u buffer %u dropped %d)\n", 5609 len, dr->dr_rx_bufsize, cnt); 5610 return; 5611 } 5612 5613 switch (mac->mac_fw.fw_hdr_format) { 5614 case BWN_FW_HDR_351: 5615 case BWN_FW_HDR_410: 5616 macstat = le32toh(rxhdr->ps4.r351.mac_status); 5617 break; 5618 case BWN_FW_HDR_598: 5619 macstat = le32toh(rxhdr->ps4.r598.mac_status); 5620 break; 5621 } 5622 5623 if (macstat & BWN_RX_MAC_FCSERR) { 5624 if (!(mac->mac_sc->sc_filters & BWN_MACCTL_PASS_BADFCS)) { 5625 device_printf(sc->sc_dev, "RX drop\n"); 5626 return; 5627 } 5628 } 5629 5630 m->m_len = m->m_pkthdr.len = len + dr->dr_frameoffset; 5631 m_adj(m, dr->dr_frameoffset); 5632 5633 bwn_rxeof(dr->dr_mac, m, rxhdr); 5634 } 5635 5636 static void 5637 bwn_handle_txeof(struct bwn_mac *mac, const struct bwn_txstatus *status) 5638 { 5639 struct bwn_softc *sc = mac->mac_sc; 5640 struct bwn_stats *stats = &mac->mac_stats; 5641 5642 BWN_ASSERT_LOCKED(mac->mac_sc); 5643 5644 if (status->im) 5645 device_printf(sc->sc_dev, "TODO: STATUS IM\n"); 5646 if (status->ampdu) 5647 device_printf(sc->sc_dev, "TODO: STATUS AMPDU\n"); 5648 if (status->rtscnt) { 5649 if (status->rtscnt == 0xf) 5650 stats->rtsfail++; 5651 else 5652 stats->rts++; 5653 } 5654 5655 if (mac->mac_flags & BWN_MAC_FLAG_DMA) { 5656 bwn_dma_handle_txeof(mac, status); 5657 } else { 5658 bwn_pio_handle_txeof(mac, status); 5659 } 5660 5661 bwn_phy_txpower_check(mac, 0); 5662 } 5663 5664 static uint8_t 5665 bwn_pio_rxeof(struct bwn_pio_rxqueue *prq) 5666 { 5667 struct bwn_mac *mac = prq->prq_mac; 5668 struct bwn_softc *sc = mac->mac_sc; 5669 struct bwn_rxhdr4 rxhdr; 5670 struct mbuf *m; 5671 uint32_t ctl32, macstat, v32; 5672 unsigned int i, padding; 5673 uint16_t ctl16, len, totlen, v16; 5674 unsigned char *mp; 5675 char *data; 5676 5677 memset(&rxhdr, 0, sizeof(rxhdr)); 5678 5679 if (prq->prq_rev >= 8) { 5680 ctl32 = bwn_pio_rx_read_4(prq, BWN_PIO8_RXCTL); 5681 if (!(ctl32 & BWN_PIO8_RXCTL_FRAMEREADY)) 5682 return (0); 5683 bwn_pio_rx_write_4(prq, BWN_PIO8_RXCTL, 5684 BWN_PIO8_RXCTL_FRAMEREADY); 5685 for (i = 0; i < 10; i++) { 5686 ctl32 = bwn_pio_rx_read_4(prq, BWN_PIO8_RXCTL); 5687 if (ctl32 & BWN_PIO8_RXCTL_DATAREADY) 5688 goto ready; 5689 DELAY(10); 5690 } 5691 } else { 5692 ctl16 = bwn_pio_rx_read_2(prq, BWN_PIO_RXCTL); 5693 if (!(ctl16 & BWN_PIO_RXCTL_FRAMEREADY)) 5694 return (0); 5695 bwn_pio_rx_write_2(prq, BWN_PIO_RXCTL, 5696 BWN_PIO_RXCTL_FRAMEREADY); 5697 for (i = 0; i < 10; i++) { 5698 ctl16 = bwn_pio_rx_read_2(prq, BWN_PIO_RXCTL); 5699 if (ctl16 & BWN_PIO_RXCTL_DATAREADY) 5700 goto ready; 5701 DELAY(10); 5702 } 5703 } 5704 device_printf(sc->sc_dev, "%s: timed out\n", __func__); 5705 return (1); 5706 ready: 5707 if (prq->prq_rev >= 8) { 5708 bus_read_multi_4(sc->sc_mem_res, 5709 prq->prq_base + BWN_PIO8_RXDATA, (void *)&rxhdr, 5710 sizeof(rxhdr)); 5711 } else { 5712 bus_read_multi_2(sc->sc_mem_res, 5713 prq->prq_base + BWN_PIO_RXDATA, (void *)&rxhdr, 5714 sizeof(rxhdr)); 5715 } 5716 len = le16toh(rxhdr.frame_len); 5717 if (len > 0x700) { 5718 device_printf(sc->sc_dev, "%s: len is too big\n", __func__); 5719 goto error; 5720 } 5721 if (len == 0) { 5722 device_printf(sc->sc_dev, "%s: len is 0\n", __func__); 5723 goto error; 5724 } 5725 5726 switch (mac->mac_fw.fw_hdr_format) { 5727 case BWN_FW_HDR_351: 5728 case BWN_FW_HDR_410: 5729 macstat = le32toh(rxhdr.ps4.r351.mac_status); 5730 break; 5731 case BWN_FW_HDR_598: 5732 macstat = le32toh(rxhdr.ps4.r598.mac_status); 5733 break; 5734 } 5735 5736 if (macstat & BWN_RX_MAC_FCSERR) { 5737 if (!(mac->mac_sc->sc_filters & BWN_MACCTL_PASS_BADFCS)) { 5738 device_printf(sc->sc_dev, "%s: FCS error", __func__); 5739 goto error; 5740 } 5741 } 5742 5743 padding = (macstat & BWN_RX_MAC_PADDING) ? 2 : 0; 5744 totlen = len + padding; 5745 KASSERT(totlen <= MCLBYTES, ("too big..\n")); 5746 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 5747 if (m == NULL) { 5748 device_printf(sc->sc_dev, "%s: out of memory", __func__); 5749 goto error; 5750 } 5751 mp = mtod(m, unsigned char *); 5752 if (prq->prq_rev >= 8) { 5753 bus_read_multi_4(sc->sc_mem_res, 5754 prq->prq_base + BWN_PIO8_RXDATA, (void *)mp, (totlen & ~3)); 5755 if (totlen & 3) { 5756 v32 = bwn_pio_rx_read_4(prq, BWN_PIO8_RXDATA); 5757 data = &(mp[totlen - 1]); 5758 switch (totlen & 3) { 5759 case 3: 5760 *data = (v32 >> 16); 5761 data--; 5762 case 2: 5763 *data = (v32 >> 8); 5764 data--; 5765 case 1: 5766 *data = v32; 5767 } 5768 } 5769 } else { 5770 bus_read_multi_2(sc->sc_mem_res, 5771 prq->prq_base + BWN_PIO_RXDATA, (void *)mp, (totlen & ~1)); 5772 if (totlen & 1) { 5773 v16 = bwn_pio_rx_read_2(prq, BWN_PIO_RXDATA); 5774 mp[totlen - 1] = v16; 5775 } 5776 } 5777 5778 m->m_len = m->m_pkthdr.len = totlen; 5779 5780 bwn_rxeof(prq->prq_mac, m, &rxhdr); 5781 5782 return (1); 5783 error: 5784 if (prq->prq_rev >= 8) 5785 bwn_pio_rx_write_4(prq, BWN_PIO8_RXCTL, 5786 BWN_PIO8_RXCTL_DATAREADY); 5787 else 5788 bwn_pio_rx_write_2(prq, BWN_PIO_RXCTL, BWN_PIO_RXCTL_DATAREADY); 5789 return (1); 5790 } 5791 5792 static int 5793 bwn_dma_newbuf(struct bwn_dma_ring *dr, struct bwn_dmadesc_generic *desc, 5794 struct bwn_dmadesc_meta *meta, int init) 5795 { 5796 struct bwn_mac *mac = dr->dr_mac; 5797 struct bwn_dma *dma = &mac->mac_method.dma; 5798 struct bwn_rxhdr4 *hdr; 5799 bus_dmamap_t map; 5800 bus_addr_t paddr; 5801 struct mbuf *m; 5802 int error; 5803 5804 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 5805 if (m == NULL) { 5806 error = ENOBUFS; 5807 5808 /* 5809 * If the NIC is up and running, we need to: 5810 * - Clear RX buffer's header. 5811 * - Restore RX descriptor settings. 5812 */ 5813 if (init) 5814 return (error); 5815 else 5816 goto back; 5817 } 5818 m->m_len = m->m_pkthdr.len = MCLBYTES; 5819 5820 bwn_dma_set_redzone(dr, m); 5821 5822 /* 5823 * Try to load RX buf into temporary DMA map 5824 */ 5825 error = bus_dmamap_load_mbuf(dma->rxbuf_dtag, dr->dr_spare_dmap, m, 5826 bwn_dma_buf_addr, &paddr, BUS_DMA_NOWAIT); 5827 if (error) { 5828 m_freem(m); 5829 5830 /* 5831 * See the comment above 5832 */ 5833 if (init) 5834 return (error); 5835 else 5836 goto back; 5837 } 5838 5839 if (!init) 5840 bus_dmamap_unload(dma->rxbuf_dtag, meta->mt_dmap); 5841 meta->mt_m = m; 5842 meta->mt_paddr = paddr; 5843 5844 /* 5845 * Swap RX buf's DMA map with the loaded temporary one 5846 */ 5847 map = meta->mt_dmap; 5848 meta->mt_dmap = dr->dr_spare_dmap; 5849 dr->dr_spare_dmap = map; 5850 5851 back: 5852 /* 5853 * Clear RX buf header 5854 */ 5855 hdr = mtod(meta->mt_m, struct bwn_rxhdr4 *); 5856 bzero(hdr, sizeof(*hdr)); 5857 bus_dmamap_sync(dma->rxbuf_dtag, meta->mt_dmap, 5858 BUS_DMASYNC_PREWRITE); 5859 5860 /* 5861 * Setup RX buf descriptor 5862 */ 5863 dr->setdesc(dr, desc, meta->mt_paddr, meta->mt_m->m_len - 5864 sizeof(*hdr), 0, 0, 0); 5865 return (error); 5866 } 5867 5868 static void 5869 bwn_dma_buf_addr(void *arg, bus_dma_segment_t *seg, int nseg, 5870 bus_size_t mapsz __unused, int error) 5871 { 5872 5873 if (!error) { 5874 KASSERT(nseg == 1, ("too many segments(%d)\n", nseg)); 5875 *((bus_addr_t *)arg) = seg->ds_addr; 5876 } 5877 } 5878 5879 static int 5880 bwn_hwrate2ieeerate(int rate) 5881 { 5882 5883 switch (rate) { 5884 case BWN_CCK_RATE_1MB: 5885 return (2); 5886 case BWN_CCK_RATE_2MB: 5887 return (4); 5888 case BWN_CCK_RATE_5MB: 5889 return (11); 5890 case BWN_CCK_RATE_11MB: 5891 return (22); 5892 case BWN_OFDM_RATE_6MB: 5893 return (12); 5894 case BWN_OFDM_RATE_9MB: 5895 return (18); 5896 case BWN_OFDM_RATE_12MB: 5897 return (24); 5898 case BWN_OFDM_RATE_18MB: 5899 return (36); 5900 case BWN_OFDM_RATE_24MB: 5901 return (48); 5902 case BWN_OFDM_RATE_36MB: 5903 return (72); 5904 case BWN_OFDM_RATE_48MB: 5905 return (96); 5906 case BWN_OFDM_RATE_54MB: 5907 return (108); 5908 default: 5909 printf("Ooops\n"); 5910 return (0); 5911 } 5912 } 5913 5914 /* 5915 * Post process the RX provided RSSI. 5916 * 5917 * Valid for A, B, G, LP PHYs. 5918 */ 5919 static int8_t 5920 bwn_rx_rssi_calc(struct bwn_mac *mac, uint8_t in_rssi, 5921 int ofdm, int adjust_2053, int adjust_2050) 5922 { 5923 struct bwn_phy *phy = &mac->mac_phy; 5924 struct bwn_phy_g *gphy = &phy->phy_g; 5925 int tmp; 5926 5927 switch (phy->rf_ver) { 5928 case 0x2050: 5929 if (ofdm) { 5930 tmp = in_rssi; 5931 if (tmp > 127) 5932 tmp -= 256; 5933 tmp = tmp * 73 / 64; 5934 if (adjust_2050) 5935 tmp += 25; 5936 else 5937 tmp -= 3; 5938 } else { 5939 if (mac->mac_sc->sc_board_info.board_flags 5940 & BHND_BFL_ADCDIV) { 5941 if (in_rssi > 63) 5942 in_rssi = 63; 5943 tmp = gphy->pg_nrssi_lt[in_rssi]; 5944 tmp = (31 - tmp) * -131 / 128 - 57; 5945 } else { 5946 tmp = in_rssi; 5947 tmp = (31 - tmp) * -149 / 128 - 68; 5948 } 5949 if (phy->type == BWN_PHYTYPE_G && adjust_2050) 5950 tmp += 25; 5951 } 5952 break; 5953 case 0x2060: 5954 if (in_rssi > 127) 5955 tmp = in_rssi - 256; 5956 else 5957 tmp = in_rssi; 5958 break; 5959 default: 5960 tmp = in_rssi; 5961 tmp = (tmp - 11) * 103 / 64; 5962 if (adjust_2053) 5963 tmp -= 109; 5964 else 5965 tmp -= 83; 5966 } 5967 5968 return (tmp); 5969 } 5970 5971 static void 5972 bwn_rxeof(struct bwn_mac *mac, struct mbuf *m, const void *_rxhdr) 5973 { 5974 const struct bwn_rxhdr4 *rxhdr = _rxhdr; 5975 struct bwn_plcp6 *plcp; 5976 struct bwn_softc *sc = mac->mac_sc; 5977 struct ieee80211_frame_min *wh; 5978 struct ieee80211_node *ni; 5979 struct ieee80211com *ic = &sc->sc_ic; 5980 uint32_t macstat; 5981 int padding, rate, rssi = 0, noise = 0, type; 5982 uint16_t phytype, phystat0, phystat3, chanstat; 5983 unsigned char *mp = mtod(m, unsigned char *); 5984 5985 BWN_ASSERT_LOCKED(sc); 5986 5987 phystat0 = le16toh(rxhdr->phy_status0); 5988 5989 /* 5990 * XXX Note: phy_status3 doesn't exist for HT-PHY; it's only 5991 * used for LP-PHY. 5992 */ 5993 phystat3 = le16toh(rxhdr->ps3.lp.phy_status3); 5994 5995 switch (mac->mac_fw.fw_hdr_format) { 5996 case BWN_FW_HDR_351: 5997 case BWN_FW_HDR_410: 5998 macstat = le32toh(rxhdr->ps4.r351.mac_status); 5999 chanstat = le16toh(rxhdr->ps4.r351.channel); 6000 break; 6001 case BWN_FW_HDR_598: 6002 macstat = le32toh(rxhdr->ps4.r598.mac_status); 6003 chanstat = le16toh(rxhdr->ps4.r598.channel); 6004 break; 6005 } 6006 6007 phytype = chanstat & BWN_RX_CHAN_PHYTYPE; 6008 6009 if (macstat & BWN_RX_MAC_FCSERR) 6010 device_printf(sc->sc_dev, "TODO RX: RX_FLAG_FAILED_FCS_CRC\n"); 6011 if (phystat0 & (BWN_RX_PHYST0_PLCPHCF | BWN_RX_PHYST0_PLCPFV)) 6012 device_printf(sc->sc_dev, "TODO RX: RX_FLAG_FAILED_PLCP_CRC\n"); 6013 if (macstat & BWN_RX_MAC_DECERR) 6014 goto drop; 6015 6016 padding = (macstat & BWN_RX_MAC_PADDING) ? 2 : 0; 6017 if (m->m_pkthdr.len < (sizeof(struct bwn_plcp6) + padding)) { 6018 device_printf(sc->sc_dev, "frame too short (length=%d)\n", 6019 m->m_pkthdr.len); 6020 goto drop; 6021 } 6022 plcp = (struct bwn_plcp6 *)(mp + padding); 6023 m_adj(m, sizeof(struct bwn_plcp6) + padding); 6024 if (m->m_pkthdr.len < IEEE80211_MIN_LEN) { 6025 device_printf(sc->sc_dev, "frame too short (length=%d)\n", 6026 m->m_pkthdr.len); 6027 goto drop; 6028 } 6029 wh = mtod(m, struct ieee80211_frame_min *); 6030 6031 if (macstat & BWN_RX_MAC_DEC) { 6032 DPRINTF(sc, BWN_DEBUG_HWCRYPTO, 6033 "RX decryption attempted (old %d keyidx %#x)\n", 6034 BWN_ISOLDFMT(mac), 6035 (macstat & BWN_RX_MAC_KEYIDX) >> BWN_RX_MAC_KEYIDX_SHIFT); 6036 } 6037 6038 if (phystat0 & BWN_RX_PHYST0_OFDM) 6039 rate = bwn_plcp_get_ofdmrate(mac, plcp, 6040 phytype == BWN_PHYTYPE_A); 6041 else 6042 rate = bwn_plcp_get_cckrate(mac, plcp); 6043 if (rate == -1) { 6044 if (!(mac->mac_sc->sc_filters & BWN_MACCTL_PASS_BADPLCP)) 6045 goto drop; 6046 } 6047 sc->sc_rx_rate = bwn_hwrate2ieeerate(rate); 6048 6049 /* rssi/noise */ 6050 switch (phytype) { 6051 case BWN_PHYTYPE_A: 6052 case BWN_PHYTYPE_B: 6053 case BWN_PHYTYPE_G: 6054 case BWN_PHYTYPE_LP: 6055 rssi = bwn_rx_rssi_calc(mac, rxhdr->phy.abg.rssi, 6056 !! (phystat0 & BWN_RX_PHYST0_OFDM), 6057 !! (phystat0 & BWN_RX_PHYST0_GAINCTL), 6058 !! (phystat3 & BWN_RX_PHYST3_TRSTATE)); 6059 break; 6060 case BWN_PHYTYPE_N: 6061 /* Broadcom has code for min/avg, but always used max */ 6062 if (rxhdr->phy.n.power0 == 16 || rxhdr->phy.n.power0 == 32) 6063 rssi = max(rxhdr->phy.n.power1, rxhdr->ps2.n.power2); 6064 else 6065 rssi = max(rxhdr->phy.n.power0, rxhdr->phy.n.power1); 6066 #if 0 6067 DPRINTF(mac->mac_sc, BWN_DEBUG_RECV, 6068 "%s: power0=%d, power1=%d, power2=%d\n", 6069 __func__, 6070 rxhdr->phy.n.power0, 6071 rxhdr->phy.n.power1, 6072 rxhdr->ps2.n.power2); 6073 #endif 6074 break; 6075 default: 6076 /* XXX TODO: implement rssi for other PHYs */ 6077 break; 6078 } 6079 6080 /* 6081 * RSSI here is absolute, not relative to the noise floor. 6082 */ 6083 noise = mac->mac_stats.link_noise; 6084 rssi = rssi - noise; 6085 6086 /* RX radio tap */ 6087 if (ieee80211_radiotap_active(ic)) 6088 bwn_rx_radiotap(mac, m, rxhdr, plcp, rate, rssi, noise); 6089 m_adj(m, -IEEE80211_CRC_LEN); 6090 6091 BWN_UNLOCK(sc); 6092 6093 ni = ieee80211_find_rxnode(ic, wh); 6094 if (ni != NULL) { 6095 type = ieee80211_input(ni, m, rssi, noise); 6096 ieee80211_free_node(ni); 6097 } else 6098 type = ieee80211_input_all(ic, m, rssi, noise); 6099 6100 BWN_LOCK(sc); 6101 return; 6102 drop: 6103 device_printf(sc->sc_dev, "%s: dropped\n", __func__); 6104 } 6105 6106 static void 6107 bwn_ratectl_tx_complete(const struct ieee80211_node *ni, 6108 const struct bwn_txstatus *status) 6109 { 6110 struct ieee80211_ratectl_tx_status txs; 6111 int retrycnt = 0; 6112 6113 /* 6114 * If we don't get an ACK, then we should log the 6115 * full framecnt. That may be 0 if it's a PHY 6116 * failure, so ensure that gets logged as some 6117 * retry attempt. 6118 */ 6119 txs.flags = IEEE80211_RATECTL_STATUS_LONG_RETRY; 6120 if (status->ack) { 6121 txs.status = IEEE80211_RATECTL_TX_SUCCESS; 6122 retrycnt = status->framecnt - 1; 6123 } else { 6124 txs.status = IEEE80211_RATECTL_TX_FAIL_UNSPECIFIED; 6125 retrycnt = status->framecnt; 6126 if (retrycnt == 0) 6127 retrycnt = 1; 6128 } 6129 txs.long_retries = retrycnt; 6130 ieee80211_ratectl_tx_complete(ni, &txs); 6131 } 6132 6133 static void 6134 bwn_dma_handle_txeof(struct bwn_mac *mac, 6135 const struct bwn_txstatus *status) 6136 { 6137 struct bwn_dma *dma = &mac->mac_method.dma; 6138 struct bwn_dma_ring *dr; 6139 struct bwn_dmadesc_generic *desc; 6140 struct bwn_dmadesc_meta *meta; 6141 struct bwn_softc *sc = mac->mac_sc; 6142 int slot; 6143 6144 BWN_ASSERT_LOCKED(sc); 6145 6146 dr = bwn_dma_parse_cookie(mac, status, status->cookie, &slot); 6147 if (dr == NULL) { 6148 device_printf(sc->sc_dev, "failed to parse cookie\n"); 6149 return; 6150 } 6151 KASSERT(dr->dr_tx, ("%s:%d: fail", __func__, __LINE__)); 6152 6153 while (1) { 6154 KASSERT(slot >= 0 && slot < dr->dr_numslots, 6155 ("%s:%d: fail", __func__, __LINE__)); 6156 dr->getdesc(dr, slot, &desc, &meta); 6157 6158 if (meta->mt_txtype == BWN_DMADESC_METATYPE_HEADER) 6159 bus_dmamap_unload(dr->dr_txring_dtag, meta->mt_dmap); 6160 else if (meta->mt_txtype == BWN_DMADESC_METATYPE_BODY) 6161 bus_dmamap_unload(dma->txbuf_dtag, meta->mt_dmap); 6162 6163 if (meta->mt_islast) { 6164 KASSERT(meta->mt_m != NULL, 6165 ("%s:%d: fail", __func__, __LINE__)); 6166 6167 bwn_ratectl_tx_complete(meta->mt_ni, status); 6168 ieee80211_tx_complete(meta->mt_ni, meta->mt_m, 0); 6169 meta->mt_ni = NULL; 6170 meta->mt_m = NULL; 6171 } else 6172 KASSERT(meta->mt_m == NULL, 6173 ("%s:%d: fail", __func__, __LINE__)); 6174 6175 dr->dr_usedslot--; 6176 if (meta->mt_islast) 6177 break; 6178 slot = bwn_dma_nextslot(dr, slot); 6179 } 6180 sc->sc_watchdog_timer = 0; 6181 if (dr->dr_stop) { 6182 KASSERT(bwn_dma_freeslot(dr) >= BWN_TX_SLOTS_PER_FRAME, 6183 ("%s:%d: fail", __func__, __LINE__)); 6184 dr->dr_stop = 0; 6185 } 6186 } 6187 6188 static void 6189 bwn_pio_handle_txeof(struct bwn_mac *mac, 6190 const struct bwn_txstatus *status) 6191 { 6192 struct bwn_pio_txqueue *tq; 6193 struct bwn_pio_txpkt *tp = NULL; 6194 struct bwn_softc *sc = mac->mac_sc; 6195 6196 BWN_ASSERT_LOCKED(sc); 6197 6198 tq = bwn_pio_parse_cookie(mac, status->cookie, &tp); 6199 if (tq == NULL) 6200 return; 6201 6202 tq->tq_used -= roundup(tp->tp_m->m_pkthdr.len + BWN_HDRSIZE(mac), 4); 6203 tq->tq_free++; 6204 6205 if (tp->tp_ni != NULL) { 6206 /* 6207 * Do any tx complete callback. Note this must 6208 * be done before releasing the node reference. 6209 */ 6210 bwn_ratectl_tx_complete(tp->tp_ni, status); 6211 } 6212 ieee80211_tx_complete(tp->tp_ni, tp->tp_m, 0); 6213 tp->tp_ni = NULL; 6214 tp->tp_m = NULL; 6215 TAILQ_INSERT_TAIL(&tq->tq_pktlist, tp, tp_list); 6216 6217 sc->sc_watchdog_timer = 0; 6218 } 6219 6220 static void 6221 bwn_phy_txpower_check(struct bwn_mac *mac, uint32_t flags) 6222 { 6223 struct bwn_softc *sc = mac->mac_sc; 6224 struct bwn_phy *phy = &mac->mac_phy; 6225 struct ieee80211com *ic = &sc->sc_ic; 6226 unsigned long now; 6227 bwn_txpwr_result_t result; 6228 6229 BWN_GETTIME(now); 6230 6231 if (!(flags & BWN_TXPWR_IGNORE_TIME) && ieee80211_time_before(now, phy->nexttime)) 6232 return; 6233 phy->nexttime = now + 2 * 1000; 6234 6235 if (sc->sc_board_info.board_vendor == PCI_VENDOR_BROADCOM && 6236 sc->sc_board_info.board_type == BHND_BOARD_BU4306) 6237 return; 6238 6239 if (phy->recalc_txpwr != NULL) { 6240 result = phy->recalc_txpwr(mac, 6241 (flags & BWN_TXPWR_IGNORE_TSSI) ? 1 : 0); 6242 if (result == BWN_TXPWR_RES_DONE) 6243 return; 6244 KASSERT(result == BWN_TXPWR_RES_NEED_ADJUST, 6245 ("%s: fail", __func__)); 6246 KASSERT(phy->set_txpwr != NULL, ("%s: fail", __func__)); 6247 6248 ieee80211_runtask(ic, &mac->mac_txpower); 6249 } 6250 } 6251 6252 static uint16_t 6253 bwn_pio_rx_read_2(struct bwn_pio_rxqueue *prq, uint16_t offset) 6254 { 6255 6256 return (BWN_READ_2(prq->prq_mac, prq->prq_base + offset)); 6257 } 6258 6259 static uint32_t 6260 bwn_pio_rx_read_4(struct bwn_pio_rxqueue *prq, uint16_t offset) 6261 { 6262 6263 return (BWN_READ_4(prq->prq_mac, prq->prq_base + offset)); 6264 } 6265 6266 static void 6267 bwn_pio_rx_write_2(struct bwn_pio_rxqueue *prq, uint16_t offset, uint16_t value) 6268 { 6269 6270 BWN_WRITE_2(prq->prq_mac, prq->prq_base + offset, value); 6271 } 6272 6273 static void 6274 bwn_pio_rx_write_4(struct bwn_pio_rxqueue *prq, uint16_t offset, uint32_t value) 6275 { 6276 6277 BWN_WRITE_4(prq->prq_mac, prq->prq_base + offset, value); 6278 } 6279 6280 static int 6281 bwn_ieeerate2hwrate(struct bwn_softc *sc, int rate) 6282 { 6283 6284 switch (rate) { 6285 /* OFDM rates (cf IEEE Std 802.11a-1999, pp. 14 Table 80) */ 6286 case 12: 6287 return (BWN_OFDM_RATE_6MB); 6288 case 18: 6289 return (BWN_OFDM_RATE_9MB); 6290 case 24: 6291 return (BWN_OFDM_RATE_12MB); 6292 case 36: 6293 return (BWN_OFDM_RATE_18MB); 6294 case 48: 6295 return (BWN_OFDM_RATE_24MB); 6296 case 72: 6297 return (BWN_OFDM_RATE_36MB); 6298 case 96: 6299 return (BWN_OFDM_RATE_48MB); 6300 case 108: 6301 return (BWN_OFDM_RATE_54MB); 6302 /* CCK rates (NB: not IEEE std, device-specific) */ 6303 case 2: 6304 return (BWN_CCK_RATE_1MB); 6305 case 4: 6306 return (BWN_CCK_RATE_2MB); 6307 case 11: 6308 return (BWN_CCK_RATE_5MB); 6309 case 22: 6310 return (BWN_CCK_RATE_11MB); 6311 } 6312 6313 device_printf(sc->sc_dev, "unsupported rate %d\n", rate); 6314 return (BWN_CCK_RATE_1MB); 6315 } 6316 6317 static uint16_t 6318 bwn_set_txhdr_phyctl1(struct bwn_mac *mac, uint8_t bitrate) 6319 { 6320 struct bwn_phy *phy = &mac->mac_phy; 6321 uint16_t control = 0; 6322 uint16_t bw; 6323 6324 /* XXX TODO: this is for LP phy, what about N-PHY, etc? */ 6325 bw = BWN_TXH_PHY1_BW_20; 6326 6327 if (BWN_ISCCKRATE(bitrate) && phy->type != BWN_PHYTYPE_LP) { 6328 control = bw; 6329 } else { 6330 control = bw; 6331 /* Figure out coding rate and modulation */ 6332 /* XXX TODO: table-ize, for MCS transmit */ 6333 /* Note: this is BWN_*_RATE values */ 6334 switch (bitrate) { 6335 case BWN_CCK_RATE_1MB: 6336 control |= 0; 6337 break; 6338 case BWN_CCK_RATE_2MB: 6339 control |= 1; 6340 break; 6341 case BWN_CCK_RATE_5MB: 6342 control |= 2; 6343 break; 6344 case BWN_CCK_RATE_11MB: 6345 control |= 3; 6346 break; 6347 case BWN_OFDM_RATE_6MB: 6348 control |= BWN_TXH_PHY1_CRATE_1_2; 6349 control |= BWN_TXH_PHY1_MODUL_BPSK; 6350 break; 6351 case BWN_OFDM_RATE_9MB: 6352 control |= BWN_TXH_PHY1_CRATE_3_4; 6353 control |= BWN_TXH_PHY1_MODUL_BPSK; 6354 break; 6355 case BWN_OFDM_RATE_12MB: 6356 control |= BWN_TXH_PHY1_CRATE_1_2; 6357 control |= BWN_TXH_PHY1_MODUL_QPSK; 6358 break; 6359 case BWN_OFDM_RATE_18MB: 6360 control |= BWN_TXH_PHY1_CRATE_3_4; 6361 control |= BWN_TXH_PHY1_MODUL_QPSK; 6362 break; 6363 case BWN_OFDM_RATE_24MB: 6364 control |= BWN_TXH_PHY1_CRATE_1_2; 6365 control |= BWN_TXH_PHY1_MODUL_QAM16; 6366 break; 6367 case BWN_OFDM_RATE_36MB: 6368 control |= BWN_TXH_PHY1_CRATE_3_4; 6369 control |= BWN_TXH_PHY1_MODUL_QAM16; 6370 break; 6371 case BWN_OFDM_RATE_48MB: 6372 control |= BWN_TXH_PHY1_CRATE_1_2; 6373 control |= BWN_TXH_PHY1_MODUL_QAM64; 6374 break; 6375 case BWN_OFDM_RATE_54MB: 6376 control |= BWN_TXH_PHY1_CRATE_3_4; 6377 control |= BWN_TXH_PHY1_MODUL_QAM64; 6378 break; 6379 default: 6380 break; 6381 } 6382 control |= BWN_TXH_PHY1_MODE_SISO; 6383 } 6384 6385 return control; 6386 } 6387 6388 static int 6389 bwn_set_txhdr(struct bwn_mac *mac, struct ieee80211_node *ni, 6390 struct mbuf *m, struct bwn_txhdr *txhdr, uint16_t cookie) 6391 { 6392 const struct bwn_phy *phy = &mac->mac_phy; 6393 struct bwn_softc *sc = mac->mac_sc; 6394 struct ieee80211_frame *wh; 6395 struct ieee80211_frame *protwh; 6396 const struct ieee80211_txparam *tp = ni->ni_txparms; 6397 struct ieee80211vap *vap = ni->ni_vap; 6398 struct ieee80211com *ic = &sc->sc_ic; 6399 struct mbuf *mprot; 6400 uint8_t *prot_ptr; 6401 unsigned int len; 6402 uint32_t macctl = 0; 6403 int rts_rate, rts_rate_fb, ismcast, isshort, rix, type; 6404 uint16_t phyctl = 0; 6405 uint8_t rate, rate_fb; 6406 int fill_phy_ctl1 = 0; 6407 6408 wh = mtod(m, struct ieee80211_frame *); 6409 memset(txhdr, 0, sizeof(*txhdr)); 6410 6411 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 6412 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 6413 isshort = (ic->ic_flags & IEEE80211_F_SHPREAMBLE) != 0; 6414 6415 if ((phy->type == BWN_PHYTYPE_N) || (phy->type == BWN_PHYTYPE_LP) 6416 || (phy->type == BWN_PHYTYPE_HT)) 6417 fill_phy_ctl1 = 1; 6418 6419 /* 6420 * Find TX rate 6421 */ 6422 if (type != IEEE80211_FC0_TYPE_DATA || (m->m_flags & M_EAPOL)) 6423 rate = rate_fb = tp->mgmtrate; 6424 else if (ismcast) 6425 rate = rate_fb = tp->mcastrate; 6426 else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) 6427 rate = rate_fb = tp->ucastrate; 6428 else { 6429 rix = ieee80211_ratectl_rate(ni, NULL, 0); 6430 rate = ni->ni_txrate; 6431 6432 if (rix > 0) 6433 rate_fb = ni->ni_rates.rs_rates[rix - 1] & 6434 IEEE80211_RATE_VAL; 6435 else 6436 rate_fb = rate; 6437 } 6438 6439 sc->sc_tx_rate = rate; 6440 6441 /* Note: this maps the select ieee80211 rate to hardware rate */ 6442 rate = bwn_ieeerate2hwrate(sc, rate); 6443 rate_fb = bwn_ieeerate2hwrate(sc, rate_fb); 6444 6445 txhdr->phyrate = (BWN_ISOFDMRATE(rate)) ? bwn_plcp_getofdm(rate) : 6446 bwn_plcp_getcck(rate); 6447 bcopy(wh->i_fc, txhdr->macfc, sizeof(txhdr->macfc)); 6448 bcopy(wh->i_addr1, txhdr->addr1, IEEE80211_ADDR_LEN); 6449 6450 /* XXX rate/rate_fb is the hardware rate */ 6451 if ((rate_fb == rate) || 6452 (*(u_int16_t *)wh->i_dur & htole16(0x8000)) || 6453 (*(u_int16_t *)wh->i_dur == htole16(0))) 6454 txhdr->dur_fb = *(u_int16_t *)wh->i_dur; 6455 else 6456 txhdr->dur_fb = ieee80211_compute_duration(ic->ic_rt, 6457 m->m_pkthdr.len, rate, isshort); 6458 6459 /* XXX TX encryption */ 6460 6461 switch (mac->mac_fw.fw_hdr_format) { 6462 case BWN_FW_HDR_351: 6463 bwn_plcp_genhdr((struct bwn_plcp4 *)(&txhdr->body.r351.plcp), 6464 m->m_pkthdr.len + IEEE80211_CRC_LEN, rate); 6465 break; 6466 case BWN_FW_HDR_410: 6467 bwn_plcp_genhdr((struct bwn_plcp4 *)(&txhdr->body.r410.plcp), 6468 m->m_pkthdr.len + IEEE80211_CRC_LEN, rate); 6469 break; 6470 case BWN_FW_HDR_598: 6471 bwn_plcp_genhdr((struct bwn_plcp4 *)(&txhdr->body.r598.plcp), 6472 m->m_pkthdr.len + IEEE80211_CRC_LEN, rate); 6473 break; 6474 } 6475 6476 bwn_plcp_genhdr((struct bwn_plcp4 *)(&txhdr->plcp_fb), 6477 m->m_pkthdr.len + IEEE80211_CRC_LEN, rate_fb); 6478 6479 txhdr->eftypes |= (BWN_ISOFDMRATE(rate_fb)) ? BWN_TX_EFT_FB_OFDM : 6480 BWN_TX_EFT_FB_CCK; 6481 txhdr->chan = phy->chan; 6482 phyctl |= (BWN_ISOFDMRATE(rate)) ? BWN_TX_PHY_ENC_OFDM : 6483 BWN_TX_PHY_ENC_CCK; 6484 /* XXX preamble? obey net80211 */ 6485 if (isshort && (rate == BWN_CCK_RATE_2MB || rate == BWN_CCK_RATE_5MB || 6486 rate == BWN_CCK_RATE_11MB)) 6487 phyctl |= BWN_TX_PHY_SHORTPRMBL; 6488 6489 if (! phy->gmode) 6490 macctl |= BWN_TX_MAC_5GHZ; 6491 6492 /* XXX TX antenna selection */ 6493 6494 switch (bwn_antenna_sanitize(mac, 0)) { 6495 case 0: 6496 phyctl |= BWN_TX_PHY_ANT01AUTO; 6497 break; 6498 case 1: 6499 phyctl |= BWN_TX_PHY_ANT0; 6500 break; 6501 case 2: 6502 phyctl |= BWN_TX_PHY_ANT1; 6503 break; 6504 case 3: 6505 phyctl |= BWN_TX_PHY_ANT2; 6506 break; 6507 case 4: 6508 phyctl |= BWN_TX_PHY_ANT3; 6509 break; 6510 default: 6511 KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__)); 6512 } 6513 6514 if (!ismcast) 6515 macctl |= BWN_TX_MAC_ACK; 6516 6517 macctl |= (BWN_TX_MAC_HWSEQ | BWN_TX_MAC_START_MSDU); 6518 if (!IEEE80211_IS_MULTICAST(wh->i_addr1) && 6519 m->m_pkthdr.len + IEEE80211_CRC_LEN > vap->iv_rtsthreshold) 6520 macctl |= BWN_TX_MAC_LONGFRAME; 6521 6522 if ((ic->ic_flags & IEEE80211_F_USEPROT) && 6523 ic->ic_protmode != IEEE80211_PROT_NONE) { 6524 /* Note: don't fall back to CCK rates for 5G */ 6525 if (phy->gmode) 6526 rts_rate = BWN_CCK_RATE_1MB; 6527 else 6528 rts_rate = BWN_OFDM_RATE_6MB; 6529 rts_rate_fb = bwn_get_fbrate(rts_rate); 6530 6531 /* XXX 'rate' here is hardware rate now, not the net80211 rate */ 6532 mprot = ieee80211_alloc_prot(ni, m, rate, ic->ic_protmode); 6533 if (mprot == NULL) { 6534 if_inc_counter(vap->iv_ifp, IFCOUNTER_OERRORS, 1); 6535 device_printf(sc->sc_dev, 6536 "could not allocate mbuf for protection mode %d\n", 6537 ic->ic_protmode); 6538 return (ENOBUFS); 6539 } 6540 6541 switch (mac->mac_fw.fw_hdr_format) { 6542 case BWN_FW_HDR_351: 6543 prot_ptr = txhdr->body.r351.rts_frame; 6544 break; 6545 case BWN_FW_HDR_410: 6546 prot_ptr = txhdr->body.r410.rts_frame; 6547 break; 6548 case BWN_FW_HDR_598: 6549 prot_ptr = txhdr->body.r598.rts_frame; 6550 break; 6551 } 6552 6553 bcopy(mtod(mprot, uint8_t *), prot_ptr, mprot->m_pkthdr.len); 6554 m_freem(mprot); 6555 6556 if (ic->ic_protmode == IEEE80211_PROT_CTSONLY) { 6557 macctl |= BWN_TX_MAC_SEND_CTSTOSELF; 6558 len = sizeof(struct ieee80211_frame_cts); 6559 } else { 6560 macctl |= BWN_TX_MAC_SEND_RTSCTS; 6561 len = sizeof(struct ieee80211_frame_rts); 6562 } 6563 len += IEEE80211_CRC_LEN; 6564 6565 switch (mac->mac_fw.fw_hdr_format) { 6566 case BWN_FW_HDR_351: 6567 bwn_plcp_genhdr((struct bwn_plcp4 *) 6568 &txhdr->body.r351.rts_plcp, len, rts_rate); 6569 break; 6570 case BWN_FW_HDR_410: 6571 bwn_plcp_genhdr((struct bwn_plcp4 *) 6572 &txhdr->body.r410.rts_plcp, len, rts_rate); 6573 break; 6574 case BWN_FW_HDR_598: 6575 bwn_plcp_genhdr((struct bwn_plcp4 *) 6576 &txhdr->body.r598.rts_plcp, len, rts_rate); 6577 break; 6578 } 6579 6580 bwn_plcp_genhdr((struct bwn_plcp4 *)&txhdr->rts_plcp_fb, len, 6581 rts_rate_fb); 6582 6583 switch (mac->mac_fw.fw_hdr_format) { 6584 case BWN_FW_HDR_351: 6585 protwh = (struct ieee80211_frame *) 6586 &txhdr->body.r351.rts_frame; 6587 break; 6588 case BWN_FW_HDR_410: 6589 protwh = (struct ieee80211_frame *) 6590 &txhdr->body.r410.rts_frame; 6591 break; 6592 case BWN_FW_HDR_598: 6593 protwh = (struct ieee80211_frame *) 6594 &txhdr->body.r598.rts_frame; 6595 break; 6596 } 6597 6598 txhdr->rts_dur_fb = *(u_int16_t *)protwh->i_dur; 6599 6600 if (BWN_ISOFDMRATE(rts_rate)) { 6601 txhdr->eftypes |= BWN_TX_EFT_RTS_OFDM; 6602 txhdr->phyrate_rts = bwn_plcp_getofdm(rts_rate); 6603 } else { 6604 txhdr->eftypes |= BWN_TX_EFT_RTS_CCK; 6605 txhdr->phyrate_rts = bwn_plcp_getcck(rts_rate); 6606 } 6607 txhdr->eftypes |= (BWN_ISOFDMRATE(rts_rate_fb)) ? 6608 BWN_TX_EFT_RTS_FBOFDM : BWN_TX_EFT_RTS_FBCCK; 6609 6610 if (fill_phy_ctl1) { 6611 txhdr->phyctl_1rts = htole16(bwn_set_txhdr_phyctl1(mac, rts_rate)); 6612 txhdr->phyctl_1rtsfb = htole16(bwn_set_txhdr_phyctl1(mac, rts_rate_fb)); 6613 } 6614 } 6615 6616 if (fill_phy_ctl1) { 6617 txhdr->phyctl_1 = htole16(bwn_set_txhdr_phyctl1(mac, rate)); 6618 txhdr->phyctl_1fb = htole16(bwn_set_txhdr_phyctl1(mac, rate_fb)); 6619 } 6620 6621 switch (mac->mac_fw.fw_hdr_format) { 6622 case BWN_FW_HDR_351: 6623 txhdr->body.r351.cookie = htole16(cookie); 6624 break; 6625 case BWN_FW_HDR_410: 6626 txhdr->body.r410.cookie = htole16(cookie); 6627 break; 6628 case BWN_FW_HDR_598: 6629 txhdr->body.r598.cookie = htole16(cookie); 6630 break; 6631 } 6632 6633 txhdr->macctl = htole32(macctl); 6634 txhdr->phyctl = htole16(phyctl); 6635 6636 /* 6637 * TX radio tap 6638 */ 6639 if (ieee80211_radiotap_active_vap(vap)) { 6640 sc->sc_tx_th.wt_flags = 0; 6641 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) 6642 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP; 6643 if (isshort && 6644 (rate == BWN_CCK_RATE_2MB || rate == BWN_CCK_RATE_5MB || 6645 rate == BWN_CCK_RATE_11MB)) 6646 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 6647 sc->sc_tx_th.wt_rate = rate; 6648 6649 ieee80211_radiotap_tx(vap, m); 6650 } 6651 6652 return (0); 6653 } 6654 6655 static void 6656 bwn_plcp_genhdr(struct bwn_plcp4 *plcp, const uint16_t octets, 6657 const uint8_t rate) 6658 { 6659 uint32_t d, plen; 6660 uint8_t *raw = plcp->o.raw; 6661 6662 if (BWN_ISOFDMRATE(rate)) { 6663 d = bwn_plcp_getofdm(rate); 6664 KASSERT(!(octets & 0xf000), 6665 ("%s:%d: fail", __func__, __LINE__)); 6666 d |= (octets << 5); 6667 plcp->o.data = htole32(d); 6668 } else { 6669 plen = octets * 16 / rate; 6670 if ((octets * 16 % rate) > 0) { 6671 plen++; 6672 if ((rate == BWN_CCK_RATE_11MB) 6673 && ((octets * 8 % 11) < 4)) { 6674 raw[1] = 0x84; 6675 } else 6676 raw[1] = 0x04; 6677 } else 6678 raw[1] = 0x04; 6679 plcp->o.data |= htole32(plen << 16); 6680 raw[0] = bwn_plcp_getcck(rate); 6681 } 6682 } 6683 6684 static uint8_t 6685 bwn_antenna_sanitize(struct bwn_mac *mac, uint8_t n) 6686 { 6687 struct bwn_softc *sc = mac->mac_sc; 6688 uint8_t mask; 6689 6690 if (n == 0) 6691 return (0); 6692 if (mac->mac_phy.gmode) 6693 mask = sc->sc_ant2g; 6694 else 6695 mask = sc->sc_ant5g; 6696 if (!(mask & (1 << (n - 1)))) 6697 return (0); 6698 return (n); 6699 } 6700 6701 /* 6702 * Return a fallback rate for the given rate. 6703 * 6704 * Note: Don't fall back from OFDM to CCK. 6705 */ 6706 static uint8_t 6707 bwn_get_fbrate(uint8_t bitrate) 6708 { 6709 switch (bitrate) { 6710 /* CCK */ 6711 case BWN_CCK_RATE_1MB: 6712 return (BWN_CCK_RATE_1MB); 6713 case BWN_CCK_RATE_2MB: 6714 return (BWN_CCK_RATE_1MB); 6715 case BWN_CCK_RATE_5MB: 6716 return (BWN_CCK_RATE_2MB); 6717 case BWN_CCK_RATE_11MB: 6718 return (BWN_CCK_RATE_5MB); 6719 6720 /* OFDM */ 6721 case BWN_OFDM_RATE_6MB: 6722 return (BWN_OFDM_RATE_6MB); 6723 case BWN_OFDM_RATE_9MB: 6724 return (BWN_OFDM_RATE_6MB); 6725 case BWN_OFDM_RATE_12MB: 6726 return (BWN_OFDM_RATE_9MB); 6727 case BWN_OFDM_RATE_18MB: 6728 return (BWN_OFDM_RATE_12MB); 6729 case BWN_OFDM_RATE_24MB: 6730 return (BWN_OFDM_RATE_18MB); 6731 case BWN_OFDM_RATE_36MB: 6732 return (BWN_OFDM_RATE_24MB); 6733 case BWN_OFDM_RATE_48MB: 6734 return (BWN_OFDM_RATE_36MB); 6735 case BWN_OFDM_RATE_54MB: 6736 return (BWN_OFDM_RATE_48MB); 6737 } 6738 KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__)); 6739 return (0); 6740 } 6741 6742 static uint32_t 6743 bwn_pio_write_multi_4(struct bwn_mac *mac, struct bwn_pio_txqueue *tq, 6744 uint32_t ctl, const void *_data, int len) 6745 { 6746 struct bwn_softc *sc = mac->mac_sc; 6747 uint32_t value = 0; 6748 const uint8_t *data = _data; 6749 6750 ctl |= BWN_PIO8_TXCTL_0_7 | BWN_PIO8_TXCTL_8_15 | 6751 BWN_PIO8_TXCTL_16_23 | BWN_PIO8_TXCTL_24_31; 6752 bwn_pio_write_4(mac, tq, BWN_PIO8_TXCTL, ctl); 6753 6754 bus_write_multi_4(sc->sc_mem_res, tq->tq_base + BWN_PIO8_TXDATA, 6755 __DECONST(void *, data), (len & ~3)); 6756 if (len & 3) { 6757 ctl &= ~(BWN_PIO8_TXCTL_8_15 | BWN_PIO8_TXCTL_16_23 | 6758 BWN_PIO8_TXCTL_24_31); 6759 data = &(data[len - 1]); 6760 switch (len & 3) { 6761 case 3: 6762 ctl |= BWN_PIO8_TXCTL_16_23; 6763 value |= (uint32_t)(*data) << 16; 6764 data--; 6765 case 2: 6766 ctl |= BWN_PIO8_TXCTL_8_15; 6767 value |= (uint32_t)(*data) << 8; 6768 data--; 6769 case 1: 6770 value |= (uint32_t)(*data); 6771 } 6772 bwn_pio_write_4(mac, tq, BWN_PIO8_TXCTL, ctl); 6773 bwn_pio_write_4(mac, tq, BWN_PIO8_TXDATA, value); 6774 } 6775 6776 return (ctl); 6777 } 6778 6779 static void 6780 bwn_pio_write_4(struct bwn_mac *mac, struct bwn_pio_txqueue *tq, 6781 uint16_t offset, uint32_t value) 6782 { 6783 6784 BWN_WRITE_4(mac, tq->tq_base + offset, value); 6785 } 6786 6787 static uint16_t 6788 bwn_pio_write_multi_2(struct bwn_mac *mac, struct bwn_pio_txqueue *tq, 6789 uint16_t ctl, const void *_data, int len) 6790 { 6791 struct bwn_softc *sc = mac->mac_sc; 6792 const uint8_t *data = _data; 6793 6794 ctl |= BWN_PIO_TXCTL_WRITELO | BWN_PIO_TXCTL_WRITEHI; 6795 BWN_PIO_WRITE_2(mac, tq, BWN_PIO_TXCTL, ctl); 6796 6797 bus_write_multi_2(sc->sc_mem_res, tq->tq_base + BWN_PIO_TXDATA, 6798 __DECONST(void *, data), (len & ~1)); 6799 if (len & 1) { 6800 ctl &= ~BWN_PIO_TXCTL_WRITEHI; 6801 BWN_PIO_WRITE_2(mac, tq, BWN_PIO_TXCTL, ctl); 6802 BWN_PIO_WRITE_2(mac, tq, BWN_PIO_TXDATA, data[len - 1]); 6803 } 6804 6805 return (ctl); 6806 } 6807 6808 static uint16_t 6809 bwn_pio_write_mbuf_2(struct bwn_mac *mac, struct bwn_pio_txqueue *tq, 6810 uint16_t ctl, struct mbuf *m0) 6811 { 6812 int i, j = 0; 6813 uint16_t data = 0; 6814 const uint8_t *buf; 6815 struct mbuf *m = m0; 6816 6817 ctl |= BWN_PIO_TXCTL_WRITELO | BWN_PIO_TXCTL_WRITEHI; 6818 BWN_PIO_WRITE_2(mac, tq, BWN_PIO_TXCTL, ctl); 6819 6820 for (; m != NULL; m = m->m_next) { 6821 buf = mtod(m, const uint8_t *); 6822 for (i = 0; i < m->m_len; i++) { 6823 if (!((j++) % 2)) 6824 data |= buf[i]; 6825 else { 6826 data |= (buf[i] << 8); 6827 BWN_PIO_WRITE_2(mac, tq, BWN_PIO_TXDATA, data); 6828 data = 0; 6829 } 6830 } 6831 } 6832 if (m0->m_pkthdr.len % 2) { 6833 ctl &= ~BWN_PIO_TXCTL_WRITEHI; 6834 BWN_PIO_WRITE_2(mac, tq, BWN_PIO_TXCTL, ctl); 6835 BWN_PIO_WRITE_2(mac, tq, BWN_PIO_TXDATA, data); 6836 } 6837 6838 return (ctl); 6839 } 6840 6841 static void 6842 bwn_set_slot_time(struct bwn_mac *mac, uint16_t time) 6843 { 6844 6845 /* XXX should exit if 5GHz band .. */ 6846 if (mac->mac_phy.type != BWN_PHYTYPE_G) 6847 return; 6848 6849 BWN_WRITE_2(mac, 0x684, 510 + time); 6850 /* Disabled in Linux b43, can adversely effect performance */ 6851 #if 0 6852 bwn_shm_write_2(mac, BWN_SHARED, 0x0010, time); 6853 #endif 6854 } 6855 6856 static struct bwn_dma_ring * 6857 bwn_dma_select(struct bwn_mac *mac, uint8_t prio) 6858 { 6859 6860 if ((mac->mac_flags & BWN_MAC_FLAG_WME) == 0) 6861 return (mac->mac_method.dma.wme[WME_AC_BE]); 6862 6863 switch (prio) { 6864 case 3: 6865 return (mac->mac_method.dma.wme[WME_AC_VO]); 6866 case 2: 6867 return (mac->mac_method.dma.wme[WME_AC_VI]); 6868 case 0: 6869 return (mac->mac_method.dma.wme[WME_AC_BE]); 6870 case 1: 6871 return (mac->mac_method.dma.wme[WME_AC_BK]); 6872 } 6873 KASSERT(0 == 1, ("%s:%d: fail", __func__, __LINE__)); 6874 return (NULL); 6875 } 6876 6877 static int 6878 bwn_dma_getslot(struct bwn_dma_ring *dr) 6879 { 6880 int slot; 6881 6882 BWN_ASSERT_LOCKED(dr->dr_mac->mac_sc); 6883 6884 KASSERT(dr->dr_tx, ("%s:%d: fail", __func__, __LINE__)); 6885 KASSERT(!(dr->dr_stop), ("%s:%d: fail", __func__, __LINE__)); 6886 KASSERT(bwn_dma_freeslot(dr) != 0, ("%s:%d: fail", __func__, __LINE__)); 6887 6888 slot = bwn_dma_nextslot(dr, dr->dr_curslot); 6889 KASSERT(!(slot & ~0x0fff), ("%s:%d: fail", __func__, __LINE__)); 6890 dr->dr_curslot = slot; 6891 dr->dr_usedslot++; 6892 6893 return (slot); 6894 } 6895 6896 static struct bwn_pio_txqueue * 6897 bwn_pio_parse_cookie(struct bwn_mac *mac, uint16_t cookie, 6898 struct bwn_pio_txpkt **pack) 6899 { 6900 struct bwn_pio *pio = &mac->mac_method.pio; 6901 struct bwn_pio_txqueue *tq = NULL; 6902 unsigned int index; 6903 6904 switch (cookie & 0xf000) { 6905 case 0x1000: 6906 tq = &pio->wme[WME_AC_BK]; 6907 break; 6908 case 0x2000: 6909 tq = &pio->wme[WME_AC_BE]; 6910 break; 6911 case 0x3000: 6912 tq = &pio->wme[WME_AC_VI]; 6913 break; 6914 case 0x4000: 6915 tq = &pio->wme[WME_AC_VO]; 6916 break; 6917 case 0x5000: 6918 tq = &pio->mcast; 6919 break; 6920 } 6921 KASSERT(tq != NULL, ("%s:%d: fail", __func__, __LINE__)); 6922 if (tq == NULL) 6923 return (NULL); 6924 index = (cookie & 0x0fff); 6925 KASSERT(index < N(tq->tq_pkts), ("%s:%d: fail", __func__, __LINE__)); 6926 if (index >= N(tq->tq_pkts)) 6927 return (NULL); 6928 *pack = &tq->tq_pkts[index]; 6929 KASSERT(*pack != NULL, ("%s:%d: fail", __func__, __LINE__)); 6930 return (tq); 6931 } 6932 6933 static void 6934 bwn_txpwr(void *arg, int npending) 6935 { 6936 struct bwn_mac *mac = arg; 6937 struct bwn_softc *sc; 6938 6939 if (mac == NULL) 6940 return; 6941 6942 sc = mac->mac_sc; 6943 6944 BWN_LOCK(sc); 6945 if (mac->mac_status >= BWN_MAC_STATUS_STARTED && 6946 mac->mac_phy.set_txpwr != NULL) 6947 mac->mac_phy.set_txpwr(mac); 6948 BWN_UNLOCK(sc); 6949 } 6950 6951 static void 6952 bwn_task_15s(struct bwn_mac *mac) 6953 { 6954 uint16_t reg; 6955 6956 if (mac->mac_fw.opensource) { 6957 reg = bwn_shm_read_2(mac, BWN_SCRATCH, BWN_WATCHDOG_REG); 6958 if (reg) { 6959 bwn_restart(mac, "fw watchdog"); 6960 return; 6961 } 6962 bwn_shm_write_2(mac, BWN_SCRATCH, BWN_WATCHDOG_REG, 1); 6963 } 6964 if (mac->mac_phy.task_15s) 6965 mac->mac_phy.task_15s(mac); 6966 6967 mac->mac_phy.txerrors = BWN_TXERROR_MAX; 6968 } 6969 6970 static void 6971 bwn_task_30s(struct bwn_mac *mac) 6972 { 6973 6974 if (mac->mac_phy.type != BWN_PHYTYPE_G || mac->mac_noise.noi_running) 6975 return; 6976 mac->mac_noise.noi_running = 1; 6977 mac->mac_noise.noi_nsamples = 0; 6978 6979 bwn_noise_gensample(mac); 6980 } 6981 6982 static void 6983 bwn_task_60s(struct bwn_mac *mac) 6984 { 6985 6986 if (mac->mac_phy.task_60s) 6987 mac->mac_phy.task_60s(mac); 6988 bwn_phy_txpower_check(mac, BWN_TXPWR_IGNORE_TIME); 6989 } 6990 6991 static void 6992 bwn_tasks(void *arg) 6993 { 6994 struct bwn_mac *mac = arg; 6995 struct bwn_softc *sc = mac->mac_sc; 6996 6997 BWN_ASSERT_LOCKED(sc); 6998 if (mac->mac_status != BWN_MAC_STATUS_STARTED) 6999 return; 7000 7001 if (mac->mac_task_state % 4 == 0) 7002 bwn_task_60s(mac); 7003 if (mac->mac_task_state % 2 == 0) 7004 bwn_task_30s(mac); 7005 bwn_task_15s(mac); 7006 7007 mac->mac_task_state++; 7008 callout_reset(&sc->sc_task_ch, hz * 15, bwn_tasks, mac); 7009 } 7010 7011 static int 7012 bwn_plcp_get_ofdmrate(struct bwn_mac *mac, struct bwn_plcp6 *plcp, uint8_t a) 7013 { 7014 struct bwn_softc *sc = mac->mac_sc; 7015 7016 KASSERT(a == 0, ("not support APHY\n")); 7017 7018 switch (plcp->o.raw[0] & 0xf) { 7019 case 0xb: 7020 return (BWN_OFDM_RATE_6MB); 7021 case 0xf: 7022 return (BWN_OFDM_RATE_9MB); 7023 case 0xa: 7024 return (BWN_OFDM_RATE_12MB); 7025 case 0xe: 7026 return (BWN_OFDM_RATE_18MB); 7027 case 0x9: 7028 return (BWN_OFDM_RATE_24MB); 7029 case 0xd: 7030 return (BWN_OFDM_RATE_36MB); 7031 case 0x8: 7032 return (BWN_OFDM_RATE_48MB); 7033 case 0xc: 7034 return (BWN_OFDM_RATE_54MB); 7035 } 7036 device_printf(sc->sc_dev, "incorrect OFDM rate %d\n", 7037 plcp->o.raw[0] & 0xf); 7038 return (-1); 7039 } 7040 7041 static int 7042 bwn_plcp_get_cckrate(struct bwn_mac *mac, struct bwn_plcp6 *plcp) 7043 { 7044 struct bwn_softc *sc = mac->mac_sc; 7045 7046 switch (plcp->o.raw[0]) { 7047 case 0x0a: 7048 return (BWN_CCK_RATE_1MB); 7049 case 0x14: 7050 return (BWN_CCK_RATE_2MB); 7051 case 0x37: 7052 return (BWN_CCK_RATE_5MB); 7053 case 0x6e: 7054 return (BWN_CCK_RATE_11MB); 7055 } 7056 device_printf(sc->sc_dev, "incorrect CCK rate %d\n", plcp->o.raw[0]); 7057 return (-1); 7058 } 7059 7060 static void 7061 bwn_rx_radiotap(struct bwn_mac *mac, struct mbuf *m, 7062 const struct bwn_rxhdr4 *rxhdr, struct bwn_plcp6 *plcp, int rate, 7063 int rssi, int noise) 7064 { 7065 struct bwn_softc *sc = mac->mac_sc; 7066 const struct ieee80211_frame_min *wh; 7067 uint64_t tsf; 7068 uint16_t low_mactime_now; 7069 uint16_t mt; 7070 7071 if (htole16(rxhdr->phy_status0) & BWN_RX_PHYST0_SHORTPRMBL) 7072 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 7073 7074 wh = mtod(m, const struct ieee80211_frame_min *); 7075 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) 7076 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_WEP; 7077 7078 bwn_tsf_read(mac, &tsf); 7079 low_mactime_now = tsf; 7080 tsf = tsf & ~0xffffULL; 7081 7082 switch (mac->mac_fw.fw_hdr_format) { 7083 case BWN_FW_HDR_351: 7084 case BWN_FW_HDR_410: 7085 mt = le16toh(rxhdr->ps4.r351.mac_time); 7086 break; 7087 case BWN_FW_HDR_598: 7088 mt = le16toh(rxhdr->ps4.r598.mac_time); 7089 break; 7090 } 7091 7092 tsf += mt; 7093 if (low_mactime_now < mt) 7094 tsf -= 0x10000; 7095 7096 sc->sc_rx_th.wr_tsf = tsf; 7097 sc->sc_rx_th.wr_rate = rate; 7098 sc->sc_rx_th.wr_antsignal = rssi; 7099 sc->sc_rx_th.wr_antnoise = noise; 7100 } 7101 7102 static void 7103 bwn_tsf_read(struct bwn_mac *mac, uint64_t *tsf) 7104 { 7105 uint32_t low, high; 7106 7107 KASSERT(bhnd_get_hwrev(mac->mac_sc->sc_dev) >= 3, 7108 ("%s:%d: fail", __func__, __LINE__)); 7109 7110 low = BWN_READ_4(mac, BWN_REV3PLUS_TSF_LOW); 7111 high = BWN_READ_4(mac, BWN_REV3PLUS_TSF_HIGH); 7112 *tsf = high; 7113 *tsf <<= 32; 7114 *tsf |= low; 7115 } 7116 7117 static int 7118 bwn_dma_attach(struct bwn_mac *mac) 7119 { 7120 struct bwn_dma *dma; 7121 struct bwn_softc *sc; 7122 struct bhnd_dma_translation *dt, dma_translation; 7123 bhnd_addr_t addrext_req; 7124 bus_dma_tag_t dmat; 7125 bus_addr_t lowaddr; 7126 u_int addrext_shift, addr_width; 7127 int error; 7128 7129 dma = &mac->mac_method.dma; 7130 sc = mac->mac_sc; 7131 dt = NULL; 7132 7133 if (sc->sc_quirks & BWN_QUIRK_NODMA) 7134 return (0); 7135 7136 KASSERT(bhnd_get_hwrev(sc->sc_dev) >= 5, ("%s: fail", __func__)); 7137 7138 /* Use the DMA engine's maximum host address width to determine the 7139 * addrext constraints, and supported device address width. */ 7140 switch (mac->mac_dmatype) { 7141 case BHND_DMA_ADDR_30BIT: 7142 /* 32-bit engine without addrext support */ 7143 addrext_req = 0x0; 7144 addrext_shift = 0; 7145 7146 /* We can address the full 32-bit device address space */ 7147 addr_width = BHND_DMA_ADDR_32BIT; 7148 break; 7149 7150 case BHND_DMA_ADDR_32BIT: 7151 /* 32-bit engine with addrext support */ 7152 addrext_req = BWN_DMA32_ADDREXT_MASK; 7153 addrext_shift = BWN_DMA32_ADDREXT_SHIFT; 7154 addr_width = BHND_DMA_ADDR_32BIT; 7155 break; 7156 7157 case BHND_DMA_ADDR_64BIT: 7158 /* 64-bit engine with addrext support */ 7159 addrext_req = BWN_DMA64_ADDREXT_MASK; 7160 addrext_shift = BWN_DMA64_ADDREXT_SHIFT; 7161 addr_width = BHND_DMA_ADDR_64BIT; 7162 break; 7163 7164 default: 7165 device_printf(sc->sc_dev, "unsupported DMA address width: %d\n", 7166 mac->mac_dmatype); 7167 return (ENXIO); 7168 } 7169 7170 /* Fetch our device->host DMA translation and tag */ 7171 error = bhnd_get_dma_translation(sc->sc_dev, addr_width, 0, &dmat, 7172 &dma_translation); 7173 if (error) { 7174 device_printf(sc->sc_dev, "error fetching DMA translation: " 7175 "%d\n", error); 7176 return (error); 7177 } 7178 7179 /* Verify that our DMA engine's addrext constraints are compatible with 7180 * our DMA translation */ 7181 if (addrext_req != 0x0 && 7182 (dma_translation.addrext_mask & addrext_req) != addrext_req) 7183 { 7184 device_printf(sc->sc_dev, "bus addrext mask %#jx incompatible " 7185 "with device addrext mask %#jx, disabling extended address " 7186 "support\n", (uintmax_t)dma_translation.addrext_mask, 7187 (uintmax_t)addrext_req); 7188 7189 addrext_req = 0x0; 7190 addrext_shift = 0; 7191 } 7192 7193 /* Apply our addrext translation constraint */ 7194 dma_translation.addrext_mask = addrext_req; 7195 7196 /* Initialize our DMA engine configuration */ 7197 mac->mac_flags |= BWN_MAC_FLAG_DMA; 7198 7199 dma->addrext_shift = addrext_shift; 7200 dma->translation = dma_translation; 7201 7202 dt = &dma->translation; 7203 7204 /* Dermine our translation's maximum supported address */ 7205 lowaddr = MIN((dt->addr_mask | dt->addrext_mask), BUS_SPACE_MAXADDR); 7206 7207 /* 7208 * Create top level DMA tag 7209 */ 7210 error = bus_dma_tag_create(dmat, /* parent */ 7211 BWN_ALIGN, 0, /* alignment, bounds */ 7212 lowaddr, /* lowaddr */ 7213 BUS_SPACE_MAXADDR, /* highaddr */ 7214 NULL, NULL, /* filter, filterarg */ 7215 BUS_SPACE_MAXSIZE, /* maxsize */ 7216 BUS_SPACE_UNRESTRICTED, /* nsegments */ 7217 BUS_SPACE_MAXSIZE, /* maxsegsize */ 7218 0, /* flags */ 7219 NULL, NULL, /* lockfunc, lockarg */ 7220 &dma->parent_dtag); 7221 if (error) { 7222 device_printf(sc->sc_dev, "can't create parent DMA tag\n"); 7223 return (error); 7224 } 7225 7226 /* 7227 * Create TX/RX mbuf DMA tag 7228 */ 7229 error = bus_dma_tag_create(dma->parent_dtag, 7230 1, 7231 0, 7232 BUS_SPACE_MAXADDR, 7233 BUS_SPACE_MAXADDR, 7234 NULL, NULL, 7235 MCLBYTES, 7236 1, 7237 BUS_SPACE_MAXSIZE_32BIT, 7238 0, 7239 NULL, NULL, 7240 &dma->rxbuf_dtag); 7241 if (error) { 7242 device_printf(sc->sc_dev, "can't create mbuf DMA tag\n"); 7243 goto fail0; 7244 } 7245 error = bus_dma_tag_create(dma->parent_dtag, 7246 1, 7247 0, 7248 BUS_SPACE_MAXADDR, 7249 BUS_SPACE_MAXADDR, 7250 NULL, NULL, 7251 MCLBYTES, 7252 1, 7253 BUS_SPACE_MAXSIZE_32BIT, 7254 0, 7255 NULL, NULL, 7256 &dma->txbuf_dtag); 7257 if (error) { 7258 device_printf(sc->sc_dev, "can't create mbuf DMA tag\n"); 7259 goto fail1; 7260 } 7261 7262 dma->wme[WME_AC_BK] = bwn_dma_ringsetup(mac, 0, 1); 7263 if (!dma->wme[WME_AC_BK]) 7264 goto fail2; 7265 7266 dma->wme[WME_AC_BE] = bwn_dma_ringsetup(mac, 1, 1); 7267 if (!dma->wme[WME_AC_BE]) 7268 goto fail3; 7269 7270 dma->wme[WME_AC_VI] = bwn_dma_ringsetup(mac, 2, 1); 7271 if (!dma->wme[WME_AC_VI]) 7272 goto fail4; 7273 7274 dma->wme[WME_AC_VO] = bwn_dma_ringsetup(mac, 3, 1); 7275 if (!dma->wme[WME_AC_VO]) 7276 goto fail5; 7277 7278 dma->mcast = bwn_dma_ringsetup(mac, 4, 1); 7279 if (!dma->mcast) 7280 goto fail6; 7281 dma->rx = bwn_dma_ringsetup(mac, 0, 0); 7282 if (!dma->rx) 7283 goto fail7; 7284 7285 return (error); 7286 7287 fail7: bwn_dma_ringfree(&dma->mcast); 7288 fail6: bwn_dma_ringfree(&dma->wme[WME_AC_VO]); 7289 fail5: bwn_dma_ringfree(&dma->wme[WME_AC_VI]); 7290 fail4: bwn_dma_ringfree(&dma->wme[WME_AC_BE]); 7291 fail3: bwn_dma_ringfree(&dma->wme[WME_AC_BK]); 7292 fail2: bus_dma_tag_destroy(dma->txbuf_dtag); 7293 fail1: bus_dma_tag_destroy(dma->rxbuf_dtag); 7294 fail0: bus_dma_tag_destroy(dma->parent_dtag); 7295 return (error); 7296 } 7297 7298 static struct bwn_dma_ring * 7299 bwn_dma_parse_cookie(struct bwn_mac *mac, const struct bwn_txstatus *status, 7300 uint16_t cookie, int *slot) 7301 { 7302 struct bwn_dma *dma = &mac->mac_method.dma; 7303 struct bwn_dma_ring *dr; 7304 struct bwn_softc *sc = mac->mac_sc; 7305 7306 BWN_ASSERT_LOCKED(mac->mac_sc); 7307 7308 switch (cookie & 0xf000) { 7309 case 0x1000: 7310 dr = dma->wme[WME_AC_BK]; 7311 break; 7312 case 0x2000: 7313 dr = dma->wme[WME_AC_BE]; 7314 break; 7315 case 0x3000: 7316 dr = dma->wme[WME_AC_VI]; 7317 break; 7318 case 0x4000: 7319 dr = dma->wme[WME_AC_VO]; 7320 break; 7321 case 0x5000: 7322 dr = dma->mcast; 7323 break; 7324 default: 7325 dr = NULL; 7326 KASSERT(0 == 1, 7327 ("invalid cookie value %d", cookie & 0xf000)); 7328 } 7329 *slot = (cookie & 0x0fff); 7330 if (*slot < 0 || *slot >= dr->dr_numslots) { 7331 /* 7332 * XXX FIXME: sometimes H/W returns TX DONE events duplicately 7333 * that it occurs events which have same H/W sequence numbers. 7334 * When it's occurred just prints a WARNING msgs and ignores. 7335 */ 7336 KASSERT(status->seq == dma->lastseq, 7337 ("%s:%d: fail", __func__, __LINE__)); 7338 device_printf(sc->sc_dev, 7339 "out of slot ranges (0 < %d < %d)\n", *slot, 7340 dr->dr_numslots); 7341 return (NULL); 7342 } 7343 dma->lastseq = status->seq; 7344 return (dr); 7345 } 7346 7347 static void 7348 bwn_dma_stop(struct bwn_mac *mac) 7349 { 7350 struct bwn_dma *dma; 7351 7352 if ((mac->mac_flags & BWN_MAC_FLAG_DMA) == 0) 7353 return; 7354 dma = &mac->mac_method.dma; 7355 7356 bwn_dma_ringstop(&dma->rx); 7357 bwn_dma_ringstop(&dma->wme[WME_AC_BK]); 7358 bwn_dma_ringstop(&dma->wme[WME_AC_BE]); 7359 bwn_dma_ringstop(&dma->wme[WME_AC_VI]); 7360 bwn_dma_ringstop(&dma->wme[WME_AC_VO]); 7361 bwn_dma_ringstop(&dma->mcast); 7362 } 7363 7364 static void 7365 bwn_dma_ringstop(struct bwn_dma_ring **dr) 7366 { 7367 7368 if (dr == NULL) 7369 return; 7370 7371 bwn_dma_cleanup(*dr); 7372 } 7373 7374 static void 7375 bwn_pio_stop(struct bwn_mac *mac) 7376 { 7377 struct bwn_pio *pio; 7378 7379 if (mac->mac_flags & BWN_MAC_FLAG_DMA) 7380 return; 7381 pio = &mac->mac_method.pio; 7382 7383 bwn_destroy_queue_tx(&pio->mcast); 7384 bwn_destroy_queue_tx(&pio->wme[WME_AC_VO]); 7385 bwn_destroy_queue_tx(&pio->wme[WME_AC_VI]); 7386 bwn_destroy_queue_tx(&pio->wme[WME_AC_BE]); 7387 bwn_destroy_queue_tx(&pio->wme[WME_AC_BK]); 7388 } 7389 7390 static int 7391 bwn_led_attach(struct bwn_mac *mac) 7392 { 7393 struct bwn_softc *sc = mac->mac_sc; 7394 const uint8_t *led_act = NULL; 7395 int error; 7396 int i; 7397 7398 sc->sc_led_idle = (2350 * hz) / 1000; 7399 sc->sc_led_blink = 1; 7400 7401 for (i = 0; i < N(bwn_vendor_led_act); ++i) { 7402 if (sc->sc_board_info.board_vendor == 7403 bwn_vendor_led_act[i].vid) { 7404 led_act = bwn_vendor_led_act[i].led_act; 7405 break; 7406 } 7407 } 7408 if (led_act == NULL) 7409 led_act = bwn_default_led_act; 7410 7411 _Static_assert(nitems(bwn_led_vars) == BWN_LED_MAX, 7412 "invalid NVRAM variable name array"); 7413 7414 for (i = 0; i < BWN_LED_MAX; ++i) { 7415 struct bwn_led *led; 7416 uint8_t val; 7417 7418 led = &sc->sc_leds[i]; 7419 7420 KASSERT(i < nitems(bwn_led_vars), ("unknown LED index")); 7421 error = bhnd_nvram_getvar_uint8(sc->sc_dev, bwn_led_vars[i], 7422 &val); 7423 if (error) { 7424 if (error != ENOENT) { 7425 device_printf(sc->sc_dev, "NVRAM variable %s " 7426 "unreadable: %d", bwn_led_vars[i], error); 7427 return (error); 7428 } 7429 7430 /* Not found; use default */ 7431 led->led_act = led_act[i]; 7432 } else { 7433 if (val & BWN_LED_ACT_LOW) 7434 led->led_flags |= BWN_LED_F_ACTLOW; 7435 led->led_act = val & BWN_LED_ACT_MASK; 7436 } 7437 led->led_mask = (1 << i); 7438 7439 if (led->led_act == BWN_LED_ACT_BLINK_SLOW || 7440 led->led_act == BWN_LED_ACT_BLINK_POLL || 7441 led->led_act == BWN_LED_ACT_BLINK) { 7442 led->led_flags |= BWN_LED_F_BLINK; 7443 if (led->led_act == BWN_LED_ACT_BLINK_POLL) 7444 led->led_flags |= BWN_LED_F_POLLABLE; 7445 else if (led->led_act == BWN_LED_ACT_BLINK_SLOW) 7446 led->led_flags |= BWN_LED_F_SLOW; 7447 7448 if (sc->sc_blink_led == NULL) { 7449 sc->sc_blink_led = led; 7450 if (led->led_flags & BWN_LED_F_SLOW) 7451 BWN_LED_SLOWDOWN(sc->sc_led_idle); 7452 } 7453 } 7454 7455 DPRINTF(sc, BWN_DEBUG_LED, 7456 "%dth led, act %d, lowact %d\n", i, 7457 led->led_act, led->led_flags & BWN_LED_F_ACTLOW); 7458 } 7459 callout_init_mtx(&sc->sc_led_blink_ch, &sc->sc_mtx, 0); 7460 7461 return (0); 7462 } 7463 7464 static __inline uint16_t 7465 bwn_led_onoff(const struct bwn_led *led, uint16_t val, int on) 7466 { 7467 7468 if (led->led_flags & BWN_LED_F_ACTLOW) 7469 on = !on; 7470 if (on) 7471 val |= led->led_mask; 7472 else 7473 val &= ~led->led_mask; 7474 return val; 7475 } 7476 7477 static void 7478 bwn_led_newstate(struct bwn_mac *mac, enum ieee80211_state nstate) 7479 { 7480 struct bwn_softc *sc = mac->mac_sc; 7481 struct ieee80211com *ic = &sc->sc_ic; 7482 uint16_t val; 7483 int i; 7484 7485 if (nstate == IEEE80211_S_INIT) { 7486 callout_stop(&sc->sc_led_blink_ch); 7487 sc->sc_led_blinking = 0; 7488 } 7489 7490 if ((sc->sc_flags & BWN_FLAG_RUNNING) == 0) 7491 return; 7492 7493 val = BWN_READ_2(mac, BWN_GPIO_CONTROL); 7494 for (i = 0; i < BWN_LED_MAX; ++i) { 7495 struct bwn_led *led = &sc->sc_leds[i]; 7496 int on; 7497 7498 if (led->led_act == BWN_LED_ACT_UNKN || 7499 led->led_act == BWN_LED_ACT_NULL) 7500 continue; 7501 7502 if ((led->led_flags & BWN_LED_F_BLINK) && 7503 nstate != IEEE80211_S_INIT) 7504 continue; 7505 7506 switch (led->led_act) { 7507 case BWN_LED_ACT_ON: /* Always on */ 7508 on = 1; 7509 break; 7510 case BWN_LED_ACT_OFF: /* Always off */ 7511 case BWN_LED_ACT_5GHZ: /* TODO: 11A */ 7512 on = 0; 7513 break; 7514 default: 7515 on = 1; 7516 switch (nstate) { 7517 case IEEE80211_S_INIT: 7518 on = 0; 7519 break; 7520 case IEEE80211_S_RUN: 7521 if (led->led_act == BWN_LED_ACT_11G && 7522 ic->ic_curmode != IEEE80211_MODE_11G) 7523 on = 0; 7524 break; 7525 default: 7526 if (led->led_act == BWN_LED_ACT_ASSOC) 7527 on = 0; 7528 break; 7529 } 7530 break; 7531 } 7532 7533 val = bwn_led_onoff(led, val, on); 7534 } 7535 BWN_WRITE_2(mac, BWN_GPIO_CONTROL, val); 7536 } 7537 7538 static void 7539 bwn_led_event(struct bwn_mac *mac, int event) 7540 { 7541 struct bwn_softc *sc = mac->mac_sc; 7542 struct bwn_led *led = sc->sc_blink_led; 7543 int rate; 7544 7545 if (event == BWN_LED_EVENT_POLL) { 7546 if ((led->led_flags & BWN_LED_F_POLLABLE) == 0) 7547 return; 7548 if (ticks - sc->sc_led_ticks < sc->sc_led_idle) 7549 return; 7550 } 7551 7552 sc->sc_led_ticks = ticks; 7553 if (sc->sc_led_blinking) 7554 return; 7555 7556 switch (event) { 7557 case BWN_LED_EVENT_RX: 7558 rate = sc->sc_rx_rate; 7559 break; 7560 case BWN_LED_EVENT_TX: 7561 rate = sc->sc_tx_rate; 7562 break; 7563 case BWN_LED_EVENT_POLL: 7564 rate = 0; 7565 break; 7566 default: 7567 panic("unknown LED event %d\n", event); 7568 break; 7569 } 7570 bwn_led_blink_start(mac, bwn_led_duration[rate].on_dur, 7571 bwn_led_duration[rate].off_dur); 7572 } 7573 7574 static void 7575 bwn_led_blink_start(struct bwn_mac *mac, int on_dur, int off_dur) 7576 { 7577 struct bwn_softc *sc = mac->mac_sc; 7578 struct bwn_led *led = sc->sc_blink_led; 7579 uint16_t val; 7580 7581 val = BWN_READ_2(mac, BWN_GPIO_CONTROL); 7582 val = bwn_led_onoff(led, val, 1); 7583 BWN_WRITE_2(mac, BWN_GPIO_CONTROL, val); 7584 7585 if (led->led_flags & BWN_LED_F_SLOW) { 7586 BWN_LED_SLOWDOWN(on_dur); 7587 BWN_LED_SLOWDOWN(off_dur); 7588 } 7589 7590 sc->sc_led_blinking = 1; 7591 sc->sc_led_blink_offdur = off_dur; 7592 7593 callout_reset(&sc->sc_led_blink_ch, on_dur, bwn_led_blink_next, mac); 7594 } 7595 7596 static void 7597 bwn_led_blink_next(void *arg) 7598 { 7599 struct bwn_mac *mac = arg; 7600 struct bwn_softc *sc = mac->mac_sc; 7601 uint16_t val; 7602 7603 val = BWN_READ_2(mac, BWN_GPIO_CONTROL); 7604 val = bwn_led_onoff(sc->sc_blink_led, val, 0); 7605 BWN_WRITE_2(mac, BWN_GPIO_CONTROL, val); 7606 7607 callout_reset(&sc->sc_led_blink_ch, sc->sc_led_blink_offdur, 7608 bwn_led_blink_end, mac); 7609 } 7610 7611 static void 7612 bwn_led_blink_end(void *arg) 7613 { 7614 struct bwn_mac *mac = arg; 7615 struct bwn_softc *sc = mac->mac_sc; 7616 7617 sc->sc_led_blinking = 0; 7618 } 7619 7620 static int 7621 bwn_suspend(device_t dev) 7622 { 7623 struct bwn_softc *sc = device_get_softc(dev); 7624 7625 BWN_LOCK(sc); 7626 bwn_stop(sc); 7627 BWN_UNLOCK(sc); 7628 return (0); 7629 } 7630 7631 static int 7632 bwn_resume(device_t dev) 7633 { 7634 struct bwn_softc *sc = device_get_softc(dev); 7635 int error = EDOOFUS; 7636 7637 BWN_LOCK(sc); 7638 if (sc->sc_ic.ic_nrunning > 0) 7639 error = bwn_init(sc); 7640 BWN_UNLOCK(sc); 7641 if (error == 0) 7642 ieee80211_start_all(&sc->sc_ic); 7643 return (0); 7644 } 7645 7646 static void 7647 bwn_rfswitch(void *arg) 7648 { 7649 struct bwn_softc *sc = arg; 7650 struct bwn_mac *mac = sc->sc_curmac; 7651 int cur = 0, prev = 0; 7652 7653 KASSERT(mac->mac_status >= BWN_MAC_STATUS_STARTED, 7654 ("%s: invalid MAC status %d", __func__, mac->mac_status)); 7655 7656 if (mac->mac_phy.rev >= 3 || mac->mac_phy.type == BWN_PHYTYPE_LP 7657 || mac->mac_phy.type == BWN_PHYTYPE_N) { 7658 if (!(BWN_READ_4(mac, BWN_RF_HWENABLED_HI) 7659 & BWN_RF_HWENABLED_HI_MASK)) 7660 cur = 1; 7661 } else { 7662 if (BWN_READ_2(mac, BWN_RF_HWENABLED_LO) 7663 & BWN_RF_HWENABLED_LO_MASK) 7664 cur = 1; 7665 } 7666 7667 if (mac->mac_flags & BWN_MAC_FLAG_RADIO_ON) 7668 prev = 1; 7669 7670 DPRINTF(sc, BWN_DEBUG_RESET, "%s: called; cur=%d, prev=%d\n", 7671 __func__, cur, prev); 7672 7673 if (cur != prev) { 7674 if (cur) 7675 mac->mac_flags |= BWN_MAC_FLAG_RADIO_ON; 7676 else 7677 mac->mac_flags &= ~BWN_MAC_FLAG_RADIO_ON; 7678 7679 device_printf(sc->sc_dev, 7680 "status of RF switch is changed to %s\n", 7681 cur ? "ON" : "OFF"); 7682 if (cur != mac->mac_phy.rf_on) { 7683 if (cur) 7684 bwn_rf_turnon(mac); 7685 else 7686 bwn_rf_turnoff(mac); 7687 } 7688 } 7689 7690 callout_schedule(&sc->sc_rfswitch_ch, hz); 7691 } 7692 7693 static void 7694 bwn_sysctl_node(struct bwn_softc *sc) 7695 { 7696 device_t dev = sc->sc_dev; 7697 struct bwn_mac *mac; 7698 struct bwn_stats *stats; 7699 7700 /* XXX assume that count of MAC is only 1. */ 7701 7702 if ((mac = sc->sc_curmac) == NULL) 7703 return; 7704 stats = &mac->mac_stats; 7705 7706 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 7707 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 7708 "linknoise", CTLFLAG_RW, &stats->rts, 0, "Noise level"); 7709 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 7710 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 7711 "rts", CTLFLAG_RW, &stats->rts, 0, "RTS"); 7712 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 7713 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 7714 "rtsfail", CTLFLAG_RW, &stats->rtsfail, 0, "RTS failed to send"); 7715 7716 #ifdef BWN_DEBUG 7717 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), 7718 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 7719 "debug", CTLFLAG_RW, &sc->sc_debug, 0, "Debug flags"); 7720 #endif 7721 } 7722 7723 static device_method_t bwn_methods[] = { 7724 /* Device interface */ 7725 DEVMETHOD(device_probe, bwn_probe), 7726 DEVMETHOD(device_attach, bwn_attach), 7727 DEVMETHOD(device_detach, bwn_detach), 7728 DEVMETHOD(device_suspend, bwn_suspend), 7729 DEVMETHOD(device_resume, bwn_resume), 7730 DEVMETHOD_END 7731 }; 7732 static driver_t bwn_driver = { 7733 "bwn", 7734 bwn_methods, 7735 sizeof(struct bwn_softc) 7736 }; 7737 static devclass_t bwn_devclass; 7738 DRIVER_MODULE(bwn, bhnd, bwn_driver, bwn_devclass, 0, 0); 7739 MODULE_DEPEND(bwn, bhnd, 1, 1, 1); 7740 MODULE_DEPEND(bwn, gpiobus, 1, 1, 1); 7741 MODULE_DEPEND(bwn, wlan, 1, 1, 1); /* 802.11 media layer */ 7742 MODULE_DEPEND(bwn, firmware, 1, 1, 1); /* firmware support */ 7743 MODULE_DEPEND(bwn, wlan_amrr, 1, 1, 1); 7744 MODULE_VERSION(bwn, 1); 7745