1 /* 2 * Copyright (c) 2007 The DragonFly Project. All rights reserved. 3 * 4 * This code is derived from software contributed to The DragonFly Project 5 * by Sepherosa Ziehau <sepherosa@gmail.com> 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * 3. Neither the name of The DragonFly Project nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific, prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 24 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 25 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 27 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 29 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * $DragonFly: src/sys/dev/netif/bwi/if_bwireg.h,v 1.4 2007/10/19 14:27:04 sephe Exp $ 35 * $FreeBSD$ 36 */ 37 38 #ifndef _IF_BWIREG_H 39 #define _IF_BWIREG_H 40 41 /* 42 * Registers for all of the register windows 43 */ 44 #define BWI_FLAGS 0xf18 45 #define BWI_FLAGS_INTR_MASK __BITS(5, 0) 46 47 #define BWI_IMSTATE 0xf90 48 #define BWI_IMSTATE_INBAND_ERR __BIT(17) 49 #define BWI_IMSTATE_TIMEOUT __BIT(18) 50 51 #define BWI_INTRVEC 0xf94 52 53 #define BWI_STATE_LO 0xf98 54 #define BWI_STATE_LO_RESET __BIT(0) 55 #define BWI_STATE_LO_DISABLE1 __BIT(1) 56 #define BWI_STATE_LO_DISABLE2 __BIT(2) 57 #define BWI_STATE_LO_CLOCK __BIT(16) 58 #define BWI_STATE_LO_GATED_CLOCK __BIT(17) 59 #define BWI_STATE_LO_FLAG_PHYCLKEN __BIT(0) 60 #define BWI_STATE_LO_FLAG_PHYRST __BIT(1) 61 #define BWI_STATE_LO_FLAG_PHYLNK __BIT(11) 62 #define BWI_STATE_LO_FLAGS_MASK __BITS(29, 18) 63 64 #define BWI_STATE_HI 0xf9c 65 #define BWI_STATE_HI_SERROR __BIT(0) 66 #define BWI_STATE_HI_BUSY __BIT(2) 67 #define BWI_STATE_HI_FLAG_MAGIC1 0x1 68 #define BWI_STATE_HI_FLAG_MAGIC2 0x2 69 #define BWI_STATE_HI_FLAG_64BIT 0x1000 70 #define BWI_STATE_HI_FLAGS_MASK __BITS(28, 16) 71 72 #define BWI_CONF_LO 0xfa8 73 #define BWI_CONF_LO_SERVTO_MASK __BITS(2, 0) /* service timeout */ 74 #define BWI_CONF_LO_SERVTO 2 75 #define BWI_CONF_LO_REQTO_MASK __BITS(6, 4) /* request timeout */ 76 #define BWI_CONF_LO_REQTO 3 77 78 79 #define BWI_ID_LO 0xff8 80 #define BWI_ID_LO_BUSREV_MASK __BITS(31, 28) 81 /* Bus revision */ 82 #define BWI_BUSREV_0 0 83 #define BWI_BUSREV_1 1 84 85 #define BWI_ID_HI 0xffc 86 #define BWI_ID_HI_REGWIN_REV(v) (((v) & 0xf) | (((v) & 0x7000) >> 8)) 87 #define BWI_ID_HI_REGWIN_TYPE(v) (((v) & 0x8ff0) >> 4) 88 #define BWI_ID_HI_REGWIN_VENDOR_MASK __BITS(31, 16) 89 90 /* 91 * Registers for common register window 92 */ 93 #define BWI_INFO 0x0 94 #define BWI_INFO_BBPID_MASK __BITS(15, 0) 95 #define BWI_INFO_BBPREV_MASK __BITS(19, 16) 96 #define BWI_INFO_BBPPKG_MASK __BITS(23, 20) 97 #define BWI_INFO_NREGWIN_MASK __BITS(27, 24) 98 99 #define BWI_CAPABILITY 0x4 100 #define BWI_CAP_CLKMODE __BIT(18) 101 102 #define BWI_CONTROL 0x28 103 #define BWI_CONTROL_MAGIC0 0x3a4 104 #define BWI_CONTROL_MAGIC1 0xa4 105 #define BWI_PLL_ON_DELAY 0xb0 106 #define BWI_FREQ_SEL_DELAY 0xb4 107 108 #define BWI_CLOCK_CTRL 0xb8 109 #define BWI_CLOCK_CTRL_CLKSRC __BITS(2, 0) 110 #define BWI_CLOCK_CTRL_SLOW __BIT(11) 111 #define BWI_CLOCK_CTRL_IGNPLL __BIT(12) 112 #define BWI_CLOCK_CTRL_NODYN __BIT(13) 113 #define BWI_CLOCK_CTRL_FDIV __BITS(31, 16) /* freq divisor */ 114 115 /* Possible values for BWI_CLOCK_CTRL_CLKSRC */ 116 #define BWI_CLKSRC_LP_OSC 0 /* Low power oscillator */ 117 #define BWI_CLKSRC_CS_OSC 1 /* Crystal oscillator */ 118 #define BWI_CLKSRC_PCI 2 119 #define BWI_CLKSRC_MAX 3 /* Maximum of clock source */ 120 /* Min/Max frequency for given clock source */ 121 #define BWI_CLKSRC_LP_OSC_FMIN 25000 122 #define BWI_CLKSRC_LP_OSC_FMAX 43000 123 #define BWI_CLKSRC_CS_OSC_FMIN 19800000 124 #define BWI_CLKSRC_CS_OSC_FMAX 20200000 125 #define BWI_CLKSRC_PCI_FMIN 25000000 126 #define BWI_CLKSRC_PCI_FMAX 34000000 127 128 #define BWI_CLOCK_INFO 0xc0 129 #define BWI_CLOCK_INFO_FDIV __BITS(31, 16) /* freq divisor */ 130 131 /* 132 * Registers for bus register window 133 */ 134 #define BWI_BUS_ADDR 0x50 135 #define BWI_BUS_ADDR_MAGIC 0xfd8 136 137 #define BWI_BUS_DATA 0x54 138 139 #define BWI_BUS_CONFIG 0x108 140 #define BWI_BUS_CONFIG_PREFETCH __BIT(2) 141 #define BWI_BUS_CONFIG_BURST __BIT(3) 142 #define BWI_BUS_CONFIG_MRM __BIT(5) 143 144 /* 145 * Register for MAC 146 */ 147 #define BWI_TXRX_INTR_STATUS_BASE 0x20 148 #define BWI_TXRX_INTR_MASK_BASE 0x24 149 #define BWI_TXRX_INTR_STATUS(i) (BWI_TXRX_INTR_STATUS_BASE + ((i) * 8)) 150 #define BWI_TXRX_INTR_MASK(i) (BWI_TXRX_INTR_MASK_BASE + ((i) * 8)) 151 152 #define BWI_MAC_STATUS 0x120 153 #define BWI_MAC_STATUS_ENABLE __BIT(0) 154 #define BWI_MAC_STATUS_UCODE_START __BIT(1) 155 #define BWI_MAC_STATUS_UCODE_JUMP0 __BIT(2) 156 #define BWI_MAC_STATUS_IHREN __BIT(10) 157 #define BWI_MAC_STATUS_GPOSEL_MASK __BITS(15, 14) 158 #define BWI_MAC_STATUS_BSWAP __BIT(16) 159 #define BWI_MAC_STATUS_INFRA __BIT(17) 160 #define BWI_MAC_STATUS_OPMODE_HOSTAP __BIT(18) 161 #define BWI_MAC_STATUS_RFLOCK __BIT(19) 162 #define BWI_MAC_STATUS_PASS_BCN __BIT(20) 163 #define BWI_MAC_STATUS_PASS_BADPLCP __BIT(21) 164 #define BWI_MAC_STATUS_PASS_CTL __BIT(22) 165 #define BWI_MAC_STATUS_PASS_BADFCS __BIT(23) 166 #define BWI_MAC_STATUS_PROMISC __BIT(24) 167 #define BWI_MAC_STATUS_HW_PS __BIT(25) 168 #define BWI_MAC_STATUS_WAKEUP __BIT(26) 169 #define BWI_MAC_STATUS_PHYLNK __BIT(31) 170 171 #define BWI_MAC_INTR_STATUS 0x128 172 #define BWI_MAC_INTR_MASK 0x12c 173 174 #define BWI_MAC_TMPLT_CTRL 0x130 175 #define BWI_MAC_TMPLT_DATA 0x134 176 177 #define BWI_MAC_PS_STATUS 0x140 178 179 #define BWI_MOBJ_CTRL 0x160 180 #define BWI_MOBJ_CTRL_VAL(objid, ofs) ((objid) << 16 | (ofs)) 181 #define BWI_MOBJ_DATA 0x164 182 #define BWI_MOBJ_DATA_UNALIGN 0x166 183 /* 184 * Memory object IDs 185 */ 186 #define BWI_WR_MOBJ_AUTOINC 0x100 /* Auto-increment wr */ 187 #define BWI_RD_MOBJ_AUTOINC 0x200 /* Auto-increment rd */ 188 /* Firmware ucode object */ 189 #define BWI_FW_UCODE_MOBJ 0x0 190 /* Common object */ 191 #define BWI_COMM_MOBJ 0x1 192 #define BWI_COMM_MOBJ_FWREV 0x0 193 #define BWI_COMM_MOBJ_FWPATCHLV 0x2 194 #define BWI_COMM_MOBJ_SLOTTIME 0x10 195 #define BWI_COMM_MOBJ_MACREV 0x16 196 #define BWI_COMM_MOBJ_TX_ACK 0x22 197 #define BWI_COMM_MOBJ_UCODE_STATE 0x40 198 #define BWI_COMM_MOBJ_SHRETRY_FB 0x44 199 #define BWI_COMM_MOBJ_LGRETEY_FB 0x46 200 #define BWI_COMM_MOBJ_TX_BEACON 0x54 201 #define BWI_COMM_MOBJ_KEYTABLE_OFS 0x56 202 #define BWI_COMM_MOBJ_TSSI_DS 0x58 203 #define BWI_COMM_MOBJ_HFLAGS_LO 0x5e 204 #define BWI_COMM_MOBJ_HFLAGS_MI 0x60 205 #define BWI_COMM_MOBJ_HFLAGS_HI 0x62 206 #define BWI_COMM_MOBJ_RF_ATTEN 0x64 207 #define BWI_COMM_MOBJ_RF_NOISE 0x6e 208 #define BWI_COMM_MOBJ_TSSI_OFDM 0x70 209 #define BWI_COMM_MOBJ_PROBE_RESP_TO 0x74 210 #define BWI_COMM_MOBJ_CHAN 0xa0 211 #define BWI_COMM_MOBJ_KEY_ALGO 0x100 212 #define BWI_COMM_MOBJ_TX_PROBE_RESP 0x188 213 #define BWI_HFLAG_AUTO_ANTDIV 0x1ULL 214 #define BWI_HFLAG_SYM_WA 0x2ULL /* ??? SYM work around */ 215 #define BWI_HFLAG_PWR_BOOST_DS 0x8ULL 216 #define BWI_HFLAG_GDC_WA 0x20ULL /* ??? GDC work around */ 217 #define BWI_HFLAG_OFDM_PA 0x40ULL 218 #define BWI_HFLAG_NOT_JAPAN 0x80ULL 219 #define BWI_HFLAG_MAGIC1 0x200ULL 220 #define BWI_UCODE_STATE_PS 4 221 #define BWI_LO_TSSI_MASK __BITS(7, 0) 222 #define BWI_HI_TSSI_MASK __BITS(15, 8) 223 #define BWI_INVALID_TSSI 0x7f 224 /* 802.11 object */ 225 #define BWI_80211_MOBJ 0x2 226 #define BWI_80211_MOBJ_CWMIN 0xc 227 #define BWI_80211_MOBJ_CWMAX 0x10 228 #define BWI_80211_MOBJ_SHRETRY 0x18 229 #define BWI_80211_MOBJ_LGRETRY 0x1c 230 /* Firmware PCM object */ 231 #define BWI_FW_PCM_MOBJ 0x3 232 /* MAC address of pairwise keys */ 233 #define BWI_PKEY_ADDR_MOBJ 0x4 234 235 #define BWI_TXSTATUS0 0x170 236 #define BWI_TXSTATUS0_VALID __BIT(0) 237 #define BWI_TXSTATUS0_ACKED __BIT(1) 238 #define BWI_TXSTATUS0_FREASON_MASK __BITS(4, 2) /* Failure reason */ 239 #define BWI_TXSTATUS0_AMPDU __BIT(5) 240 #define BWI_TXSTATUS0_PENDING __BIT(6) 241 #define BWI_TXSTATUS0_PM __BIT(7) 242 #define BWI_TXSTATUS0_RTS_TXCNT_MASK __BITS(11, 8) 243 #define BWI_TXSTATUS0_DATA_TXCNT_MASK __BITS(15, 12) 244 #define BWI_TXSTATUS0_TXID_MASK __BITS(31, 16) 245 #define BWI_TXSTATUS1 0x174 246 247 #define BWI_TXRX_CTRL_BASE 0x200 248 #define BWI_TX32_CTRL 0x0 249 #define BWI_TX32_RINGINFO 0x4 250 #define BWI_TX32_INDEX 0x8 251 #define BWI_TX32_STATUS 0xc 252 #define BWI_TX32_STATUS_STATE_MASK __BITS(15, 12) 253 #define BWI_TX32_STATUS_STATE_DISABLED 0 254 #define BWI_TX32_STATUS_STATE_IDLE 2 255 #define BWI_TX32_STATUS_STATE_STOPPED 3 256 #define BWI_RX32_CTRL 0x10 257 #define BWI_RX32_CTRL_HDRSZ_MASK __BITS(7, 1) 258 #define BWI_RX32_RINGINFO 0x14 259 #define BWI_RX32_INDEX 0x18 260 #define BWI_RX32_STATUS 0x1c 261 #define BWI_RX32_STATUS_INDEX_MASK __BITS(11, 0) 262 #define BWI_RX32_STATUS_STATE_MASK __BITS(15, 12) 263 #define BWI_RX32_STATUS_STATE_DISABLED 0 264 /* Shared by 32bit TX/RX CTRL */ 265 #define BWI_TXRX32_CTRL_ENABLE __BIT(0) 266 #define BWI_TXRX32_CTRL_ADDRHI_MASK __BITS(17, 16) 267 /* Shared by 32bit TX/RX RINGINFO */ 268 #define BWI_TXRX32_RINGINFO_FUNC_TXRX 0x1 269 #define BWI_TXRX32_RINGINFO_FUNC_MASK __BITS(31, 30) 270 #define BWI_TXRX32_RINGINFO_ADDR_MASK __BITS(29, 0) 271 272 #define BWI_PHYINFO 0x3e0 273 #define BWI_PHYINFO_REV_MASK __BITS(3, 0) 274 #define BWI_PHYINFO_TYPE_MASK __BITS(11, 8) 275 #define BWI_PHYINFO_TYPE_11A 0 276 #define BWI_PHYINFO_TYPE_11B 1 277 #define BWI_PHYINFO_TYPE_11G 2 278 #define BWI_PHYINFO_TYPE_11N 4 279 #define BWI_PHYINFO_TYPE_11LP 5 280 #define BWI_PHYINFO_VER_MASK __BITS(15, 12) 281 282 #define BWI_RF_ANTDIV 0x3e2 /* Antenna Diversity?? */ 283 284 #define BWI_PHY_MAGIC_REG1 0x3e4 285 #define BWI_PHY_MAGIC_REG1_VAL1 0x3000 286 #define BWI_PHY_MAGIC_REG1_VAL2 0x9 287 288 #define BWI_BBP_ATTEN 0x3e6 289 #define BWI_BBP_ATTEN_MAGIC 0xf4 290 #define BWI_BBP_ATTEN_MAGIC2 0x8140 291 292 #define BWI_BPHY_CTRL 0x3ec 293 #define BWI_BPHY_CTRL_INIT 0x3f22 294 295 #define BWI_RF_CHAN 0x3f0 296 #define BWI_RF_CHAN_EX 0x3f4 297 298 #define BWI_RF_CTRL 0x3f6 299 /* Register values for BWI_RF_CTRL */ 300 #define BWI_RF_CTRL_RFINFO 0x1 301 /* XXX extra bits for reading from radio */ 302 #define BWI_RF_CTRL_RD_11A 0x40 303 #define BWI_RF_CTRL_RD_11BG 0x80 304 #define BWI_RF_DATA_HI 0x3f8 305 #define BWI_RF_DATA_LO 0x3fa 306 /* Values read from BWI_RF_DATA_{HI,LO} after BWI_RF_CTRL_RFINFO */ 307 #define BWI_RFINFO_MANUFACT_MASK __BITS(11, 0) 308 #define BWI_RF_MANUFACT_BCM 0x17f /* XXX */ 309 #define BWI_RFINFO_TYPE_MASK __BITS(27, 12) 310 #define BWI_RF_T_BCM2050 0x2050 311 #define BWI_RF_T_BCM2053 0x2053 312 #define BWI_RF_T_BCM2060 0x2060 313 #define BWI_RFINFO_REV_MASK __BITS(31, 28) 314 315 #define BWI_PHY_CTRL 0x3fc 316 #define BWI_PHY_DATA 0x3fe 317 318 #define BWI_ADDR_FILTER_CTRL 0x420 319 #define BWI_ADDR_FILTER_CTRL_SET 0x20 320 #define BWI_ADDR_FILTER_MYADDR 0 321 #define BWI_ADDR_FILTER_BSSID 3 322 #define BWI_ADDR_FILTER_DATA 0x422 323 324 #define BWI_MAC_GPIO_CTRL 0x49c 325 #define BWI_MAC_GPIO_MASK 0x49e 326 #define BWI_MAC_PRE_TBTT 0x612 327 #define BWI_MAC_SLOTTIME 0x684 328 #define BWI_MAC_SLOTTIME_ADJUST 510 329 #define BWI_MAC_POWERUP_DELAY 0x6a8 330 331 /* 332 * Special registers 333 */ 334 /* 335 * GPIO control 336 * If common regwin exists, then it is within common regwin, 337 * else it is in bus regwin. 338 */ 339 #define BWI_GPIO_CTRL 0x6c 340 341 #define PCI_VENDOR_BROADCOM 0x14e4 /* Broadcom */ 342 #define PCI_PRODUCT_BROADCOM_BCM4309 0x4324 343 344 /* 345 * Extended PCI registers 346 */ 347 #define BWI_PCIR_BAR PCIR_BAR(0) 348 #define BWI_PCIR_SEL_REGWIN 0x80 349 /* Register value for BWI_PCIR_SEL_REGWIN */ 350 #define BWI_PCIM_REGWIN(id) (((id) * 0x1000) + 0x18000000) 351 #define BWI_PCIR_GPIO_IN 0xb0 352 #define BWI_PCIR_GPIO_OUT 0xb4 353 #define BWI_PCIM_GPIO_OUT_CLKSRC __BIT(4) 354 #define BWI_PCIR_GPIO_ENABLE 0xb8 355 /* Register values for BWI_PCIR_GPIO_{IN,OUT,ENABLE} */ 356 #define BWI_PCIM_GPIO_PWR_ON __BIT(6) 357 #define BWI_PCIM_GPIO_PLL_PWR_OFF __BIT(7) 358 #define BWI_PCIR_INTCTL 0x94 359 360 /* 361 * PCI subdevice IDs 362 */ 363 #define BWI_PCI_SUBDEVICE_BU4306 0x416 364 #define BWI_PCI_SUBDEVICE_BCM4309G 0x421 365 366 #define BWI_IS_BRCM_BU4306(sc) \ 367 ((sc)->sc_pci_subvid == PCI_VENDOR_BROADCOM && \ 368 (sc)->sc_pci_subdid == BWI_PCI_SUBDEVICE_BU4306) 369 #define BWI_IS_BRCM_BCM4309G(sc) \ 370 ((sc)->sc_pci_subvid == PCI_VENDOR_BROADCOM && \ 371 (sc)->sc_pci_subdid == BWI_PCI_SUBDEVICE_BCM4309G) 372 373 /* 374 * EEPROM start address 375 */ 376 #define BWI_SPROM_START 0x1000 377 #define BWI_SPROM_11BG_EADDR 0x48 378 #define BWI_SPROM_11A_EADDR 0x54 379 #define BWI_SPROM_CARD_INFO 0x5c 380 #define BWI_SPROM_CARD_INFO_LOCALE __BITS(11, 8) 381 #define BWI_SPROM_LOCALE_JAPAN 5 382 #define BWI_SPROM_PA_PARAM_11BG 0x5e 383 #define BWI_SPROM_GPIO01 0x64 384 #define BWI_SPROM_GPIO_0 __BITS(7, 0) 385 #define BWI_SPROM_GPIO_1 __BITS(15, 8) 386 #define BWI_SPROM_GPIO23 0x66 387 #define BWI_SPROM_GPIO_2 __BITS(7, 0) 388 #define BWI_SPROM_GPIO_3 __BITS(15, 8) 389 #define BWI_SPROM_MAX_TXPWR 0x68 390 #define BWI_SPROM_MAX_TXPWR_MASK_11BG __BITS(7, 0) /* XXX */ 391 #define BWI_SPROM_MAX_TXPWR_MASK_11A __BITS(15, 8) /* XXX */ 392 #define BWI_SPROM_PA_PARAM_11A 0x6a 393 #define BWI_SPROM_IDLE_TSSI 0x70 394 #define BWI_SPROM_IDLE_TSSI_MASK_11BG __BITS(7, 0) /* XXX */ 395 #define BWI_SPROM_IDLE_TSSI_MASK_11A __BITS(15, 8) /* XXX */ 396 #define BWI_SPROM_CARD_FLAGS 0x72 397 #define BWI_SPROM_ANT_GAIN 0x74 398 #define BWI_SPROM_ANT_GAIN_MASK_11A __BITS(7, 0) 399 #define BWI_SPROM_ANT_GAIN_MASK_11BG __BITS(15, 8) 400 401 /* 402 * SPROM card flags 403 */ 404 #define BWI_CARD_F_BT_COEXIST __BIT(0) /* Bluetooth coexist */ 405 #define BWI_CARD_F_PA_GPIO9 __BIT(1) /* GPIO 9 controls PA */ 406 #define BWI_CARD_F_SW_NRSSI __BIT(3) 407 #define BWI_CARD_F_NO_SLOWCLK __BIT(5) /* no slow clock */ 408 #define BWI_CARD_F_EXT_LNA __BIT(12) /* external LNA */ 409 #define BWI_CARD_F_ALT_IQ __BIT(15) /* alternate I/Q */ 410 411 /* 412 * SPROM GPIO 413 */ 414 #define BWI_LED_ACT_LOW __BIT(7) 415 #define BWI_LED_ACT_MASK __BITS(6, 0) 416 #define BWI_LED_ACT_OFF 0 417 #define BWI_LED_ACT_ON 1 418 #define BWI_LED_ACT_BLINK 2 419 #define BWI_LED_ACT_RF_ENABLED 3 420 #define BWI_LED_ACT_5GHZ 4 421 #define BWI_LED_ACT_2GHZ 5 422 #define BWI_LED_ACT_11G 6 423 #define BWI_LED_ACT_BLINK_SLOW 7 424 #define BWI_LED_ACT_BLINK_POLL 8 425 #define BWI_LED_ACT_UNKN 9 426 #define BWI_LED_ACT_ASSOC 10 427 #define BWI_LED_ACT_NULL 11 428 429 #define BWI_VENDOR_LED_ACT_COMPAQ \ 430 BWI_LED_ACT_RF_ENABLED, \ 431 BWI_LED_ACT_2GHZ, \ 432 BWI_LED_ACT_5GHZ, \ 433 BWI_LED_ACT_OFF 434 435 #define BWI_VENDOR_LED_ACT_LINKSYS \ 436 BWI_LED_ACT_ASSOC, \ 437 BWI_LED_ACT_2GHZ, \ 438 BWI_LED_ACT_5GHZ, \ 439 BWI_LED_ACT_OFF 440 441 #define BWI_VENDOR_LED_ACT_DEFAULT \ 442 BWI_LED_ACT_BLINK, \ 443 BWI_LED_ACT_2GHZ, \ 444 BWI_LED_ACT_5GHZ, \ 445 BWI_LED_ACT_OFF 446 447 /* 448 * BBP IDs 449 */ 450 #define BWI_BBPID_BCM4301 0x4301 451 #define BWI_BBPID_BCM4306 0x4306 452 #define BWI_BBPID_BCM4317 0x4317 453 #define BWI_BBPID_BCM4320 0x4320 454 #define BWI_BBPID_BCM4321 0x4321 455 456 /* 457 * Register window types 458 */ 459 #define BWI_REGWIN_T_COM 0x800 460 #define BWI_REGWIN_T_BUSPCI 0x804 461 #define BWI_REGWIN_T_MAC 0x812 462 #define BWI_REGWIN_T_BUSPCIE 0x820 463 464 /* 465 * MAC interrupts 466 */ 467 #define BWI_INTR_READY __BIT(0) 468 #define BWI_INTR_BEACON __BIT(1) 469 #define BWI_INTR_TBTT __BIT(2) 470 #define BWI_INTR_EO_ATIM __BIT(5) /* End of ATIM */ 471 #define BWI_INTR_PMQ __BIT(6) /* XXX?? */ 472 #define BWI_INTR_MAC_TXERR __BIT(9) 473 #define BWI_INTR_PHY_TXERR __BIT(11) 474 #define BWI_INTR_TIMER1 __BIT(14) 475 #define BWI_INTR_RX_DONE __BIT(15) 476 #define BWI_INTR_TX_FIFO __BIT(16) /* XXX?? */ 477 #define BWI_INTR_NOISE __BIT(18) 478 #define BWI_INTR_RF_DISABLED __BIT(28) 479 #define BWI_INTR_TX_DONE __BIT(29) 480 481 #define BWI_INIT_INTRS \ 482 (BWI_INTR_READY | BWI_INTR_BEACON | BWI_INTR_TBTT | \ 483 BWI_INTR_EO_ATIM | BWI_INTR_PMQ | BWI_INTR_MAC_TXERR | \ 484 BWI_INTR_PHY_TXERR | BWI_INTR_RX_DONE | BWI_INTR_TX_FIFO | \ 485 BWI_INTR_NOISE | BWI_INTR_RF_DISABLED | BWI_INTR_TX_DONE) 486 #define BWI_ALL_INTRS 0xffffffff 487 488 /* 489 * TX/RX interrupts 490 */ 491 #define BWI_TXRX_INTR_ERROR (__BIT(15) | __BIT(14) | __BITS(12, 10)) 492 #define BWI_TXRX_INTR_RX __BIT(16) 493 #define BWI_TXRX_TX_INTRS BWI_TXRX_INTR_ERROR 494 #define BWI_TXRX_RX_INTRS (BWI_TXRX_INTR_ERROR | BWI_TXRX_INTR_RX) 495 #define BWI_TXRX_IS_RX(i) ((i) % 3 == 0) 496 497 #endif /* !_IF_BWIREG_H */ 498