1 /*- 2 * SPDX-License-Identifier: BSD-3-Clause 3 * 4 * Copyright (c) 2007 The DragonFly Project. All rights reserved. 5 * 6 * This code is derived from software contributed to The DragonFly Project 7 * by Sepherosa Ziehau <sepherosa@gmail.com> 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in 17 * the documentation and/or other materials provided with the 18 * distribution. 19 * 3. Neither the name of The DragonFly Project nor the names of its 20 * contributors may be used to endorse or promote products derived 21 * from this software without specific, prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 24 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 25 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 26 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 27 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 28 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 29 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 30 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 31 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 33 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34 * SUCH DAMAGE. 35 * 36 * $DragonFly: src/sys/dev/netif/bwi/if_bwi.c,v 1.19 2008/02/15 11:15:38 sephe Exp $ 37 */ 38 39 #include <sys/cdefs.h> 40 __FBSDID("$FreeBSD$"); 41 42 #include "opt_inet.h" 43 #include "opt_bwi.h" 44 #include "opt_wlan.h" 45 46 #include <sys/param.h> 47 #include <sys/endian.h> 48 #include <sys/kernel.h> 49 #include <sys/bus.h> 50 #include <sys/malloc.h> 51 #include <sys/proc.h> 52 #include <sys/rman.h> 53 #include <sys/socket.h> 54 #include <sys/sockio.h> 55 #include <sys/sysctl.h> 56 #include <sys/systm.h> 57 #include <sys/taskqueue.h> 58 59 #include <net/if.h> 60 #include <net/if_var.h> 61 #include <net/if_dl.h> 62 #include <net/if_media.h> 63 #include <net/if_types.h> 64 #include <net/if_arp.h> 65 #include <net/ethernet.h> 66 #include <net/if_llc.h> 67 68 #include <net80211/ieee80211_var.h> 69 #include <net80211/ieee80211_radiotap.h> 70 #include <net80211/ieee80211_regdomain.h> 71 #include <net80211/ieee80211_phy.h> 72 #include <net80211/ieee80211_ratectl.h> 73 74 #include <net/bpf.h> 75 76 #ifdef INET 77 #include <netinet/in.h> 78 #include <netinet/if_ether.h> 79 #endif 80 81 #include <machine/bus.h> 82 83 #include <dev/pci/pcivar.h> 84 #include <dev/pci/pcireg.h> 85 86 #include <dev/bwi/bitops.h> 87 #include <dev/bwi/if_bwireg.h> 88 #include <dev/bwi/if_bwivar.h> 89 #include <dev/bwi/bwimac.h> 90 #include <dev/bwi/bwirf.h> 91 92 struct bwi_clock_freq { 93 u_int clkfreq_min; 94 u_int clkfreq_max; 95 }; 96 97 struct bwi_myaddr_bssid { 98 uint8_t myaddr[IEEE80211_ADDR_LEN]; 99 uint8_t bssid[IEEE80211_ADDR_LEN]; 100 } __packed; 101 102 static struct ieee80211vap *bwi_vap_create(struct ieee80211com *, 103 const char [IFNAMSIZ], int, enum ieee80211_opmode, int, 104 const uint8_t [IEEE80211_ADDR_LEN], 105 const uint8_t [IEEE80211_ADDR_LEN]); 106 static void bwi_vap_delete(struct ieee80211vap *); 107 static void bwi_init(struct bwi_softc *); 108 static void bwi_parent(struct ieee80211com *); 109 static int bwi_transmit(struct ieee80211com *, struct mbuf *); 110 static void bwi_start_locked(struct bwi_softc *); 111 static int bwi_raw_xmit(struct ieee80211_node *, struct mbuf *, 112 const struct ieee80211_bpf_params *); 113 static void bwi_watchdog(void *); 114 static void bwi_scan_start(struct ieee80211com *); 115 static void bwi_getradiocaps(struct ieee80211com *, int, int *, 116 struct ieee80211_channel[]); 117 static void bwi_set_channel(struct ieee80211com *); 118 static void bwi_scan_end(struct ieee80211com *); 119 static int bwi_newstate(struct ieee80211vap *, enum ieee80211_state, int); 120 static void bwi_updateslot(struct ieee80211com *); 121 static int bwi_media_change(struct ifnet *); 122 123 static void bwi_calibrate(void *); 124 125 static int bwi_calc_rssi(struct bwi_softc *, const struct bwi_rxbuf_hdr *); 126 static int bwi_calc_noise(struct bwi_softc *); 127 static __inline uint8_t bwi_plcp2rate(uint32_t, enum ieee80211_phytype); 128 static void bwi_rx_radiotap(struct bwi_softc *, struct mbuf *, 129 struct bwi_rxbuf_hdr *, const void *, int, int, int); 130 131 static void bwi_restart(void *, int); 132 static void bwi_init_statechg(struct bwi_softc *, int); 133 static void bwi_stop(struct bwi_softc *, int); 134 static void bwi_stop_locked(struct bwi_softc *, int); 135 static int bwi_newbuf(struct bwi_softc *, int, int); 136 static int bwi_encap(struct bwi_softc *, int, struct mbuf *, 137 struct ieee80211_node *); 138 static int bwi_encap_raw(struct bwi_softc *, int, struct mbuf *, 139 struct ieee80211_node *, 140 const struct ieee80211_bpf_params *); 141 142 static void bwi_init_rxdesc_ring32(struct bwi_softc *, uint32_t, 143 bus_addr_t, int, int); 144 static void bwi_reset_rx_ring32(struct bwi_softc *, uint32_t); 145 146 static int bwi_init_tx_ring32(struct bwi_softc *, int); 147 static int bwi_init_rx_ring32(struct bwi_softc *); 148 static int bwi_init_txstats32(struct bwi_softc *); 149 static void bwi_free_tx_ring32(struct bwi_softc *, int); 150 static void bwi_free_rx_ring32(struct bwi_softc *); 151 static void bwi_free_txstats32(struct bwi_softc *); 152 static void bwi_setup_rx_desc32(struct bwi_softc *, int, bus_addr_t, int); 153 static void bwi_setup_tx_desc32(struct bwi_softc *, struct bwi_ring_data *, 154 int, bus_addr_t, int); 155 static int bwi_rxeof32(struct bwi_softc *); 156 static void bwi_start_tx32(struct bwi_softc *, uint32_t, int); 157 static void bwi_txeof_status32(struct bwi_softc *); 158 159 static int bwi_init_tx_ring64(struct bwi_softc *, int); 160 static int bwi_init_rx_ring64(struct bwi_softc *); 161 static int bwi_init_txstats64(struct bwi_softc *); 162 static void bwi_free_tx_ring64(struct bwi_softc *, int); 163 static void bwi_free_rx_ring64(struct bwi_softc *); 164 static void bwi_free_txstats64(struct bwi_softc *); 165 static void bwi_setup_rx_desc64(struct bwi_softc *, int, bus_addr_t, int); 166 static void bwi_setup_tx_desc64(struct bwi_softc *, struct bwi_ring_data *, 167 int, bus_addr_t, int); 168 static int bwi_rxeof64(struct bwi_softc *); 169 static void bwi_start_tx64(struct bwi_softc *, uint32_t, int); 170 static void bwi_txeof_status64(struct bwi_softc *); 171 172 static int bwi_rxeof(struct bwi_softc *, int); 173 static void _bwi_txeof(struct bwi_softc *, uint16_t, int, int); 174 static void bwi_txeof(struct bwi_softc *); 175 static void bwi_txeof_status(struct bwi_softc *, int); 176 static void bwi_enable_intrs(struct bwi_softc *, uint32_t); 177 static void bwi_disable_intrs(struct bwi_softc *, uint32_t); 178 179 static int bwi_dma_alloc(struct bwi_softc *); 180 static void bwi_dma_free(struct bwi_softc *); 181 static int bwi_dma_ring_alloc(struct bwi_softc *, bus_dma_tag_t, 182 struct bwi_ring_data *, bus_size_t, 183 uint32_t); 184 static int bwi_dma_mbuf_create(struct bwi_softc *); 185 static void bwi_dma_mbuf_destroy(struct bwi_softc *, int, int); 186 static int bwi_dma_txstats_alloc(struct bwi_softc *, uint32_t, bus_size_t); 187 static void bwi_dma_txstats_free(struct bwi_softc *); 188 static void bwi_dma_ring_addr(void *, bus_dma_segment_t *, int, int); 189 static void bwi_dma_buf_addr(void *, bus_dma_segment_t *, int, 190 bus_size_t, int); 191 192 static void bwi_power_on(struct bwi_softc *, int); 193 static int bwi_power_off(struct bwi_softc *, int); 194 static int bwi_set_clock_mode(struct bwi_softc *, enum bwi_clock_mode); 195 static int bwi_set_clock_delay(struct bwi_softc *); 196 static void bwi_get_clock_freq(struct bwi_softc *, struct bwi_clock_freq *); 197 static int bwi_get_pwron_delay(struct bwi_softc *sc); 198 static void bwi_set_addr_filter(struct bwi_softc *, uint16_t, 199 const uint8_t *); 200 static void bwi_set_bssid(struct bwi_softc *, const uint8_t *); 201 202 static void bwi_get_card_flags(struct bwi_softc *); 203 static void bwi_get_eaddr(struct bwi_softc *, uint16_t, uint8_t *); 204 205 static int bwi_bus_attach(struct bwi_softc *); 206 static int bwi_bbp_attach(struct bwi_softc *); 207 static int bwi_bbp_power_on(struct bwi_softc *, enum bwi_clock_mode); 208 static void bwi_bbp_power_off(struct bwi_softc *); 209 210 static const char *bwi_regwin_name(const struct bwi_regwin *); 211 static uint32_t bwi_regwin_disable_bits(struct bwi_softc *); 212 static void bwi_regwin_info(struct bwi_softc *, uint16_t *, uint8_t *); 213 static int bwi_regwin_select(struct bwi_softc *, int); 214 215 static void bwi_led_attach(struct bwi_softc *); 216 static void bwi_led_newstate(struct bwi_softc *, enum ieee80211_state); 217 static void bwi_led_event(struct bwi_softc *, int); 218 static void bwi_led_blink_start(struct bwi_softc *, int, int); 219 static void bwi_led_blink_next(void *); 220 static void bwi_led_blink_end(void *); 221 222 static const struct { 223 uint16_t did_min; 224 uint16_t did_max; 225 uint16_t bbp_id; 226 } bwi_bbpid_map[] = { 227 { 0x4301, 0x4301, 0x4301 }, 228 { 0x4305, 0x4307, 0x4307 }, 229 { 0x4402, 0x4403, 0x4402 }, 230 { 0x4610, 0x4615, 0x4610 }, 231 { 0x4710, 0x4715, 0x4710 }, 232 { 0x4720, 0x4725, 0x4309 } 233 }; 234 235 static const struct { 236 uint16_t bbp_id; 237 int nregwin; 238 } bwi_regwin_count[] = { 239 { 0x4301, 5 }, 240 { 0x4306, 6 }, 241 { 0x4307, 5 }, 242 { 0x4310, 8 }, 243 { 0x4401, 3 }, 244 { 0x4402, 3 }, 245 { 0x4610, 9 }, 246 { 0x4704, 9 }, 247 { 0x4710, 9 }, 248 { 0x5365, 7 } 249 }; 250 251 #define CLKSRC(src) \ 252 [BWI_CLKSRC_ ## src] = { \ 253 .freq_min = BWI_CLKSRC_ ##src## _FMIN, \ 254 .freq_max = BWI_CLKSRC_ ##src## _FMAX \ 255 } 256 257 static const struct { 258 u_int freq_min; 259 u_int freq_max; 260 } bwi_clkfreq[BWI_CLKSRC_MAX] = { 261 CLKSRC(LP_OSC), 262 CLKSRC(CS_OSC), 263 CLKSRC(PCI) 264 }; 265 266 #undef CLKSRC 267 268 #define VENDOR_LED_ACT(vendor) \ 269 { \ 270 .vid = PCI_VENDOR_##vendor, \ 271 .led_act = { BWI_VENDOR_LED_ACT_##vendor } \ 272 } 273 274 static const struct { 275 #define PCI_VENDOR_COMPAQ 0x0e11 276 #define PCI_VENDOR_LINKSYS 0x1737 277 uint16_t vid; 278 uint8_t led_act[BWI_LED_MAX]; 279 } bwi_vendor_led_act[] = { 280 VENDOR_LED_ACT(COMPAQ), 281 VENDOR_LED_ACT(LINKSYS) 282 #undef PCI_VENDOR_LINKSYS 283 #undef PCI_VENDOR_COMPAQ 284 }; 285 286 static const uint8_t bwi_default_led_act[BWI_LED_MAX] = 287 { BWI_VENDOR_LED_ACT_DEFAULT }; 288 289 #undef VENDOR_LED_ACT 290 291 static const struct { 292 int on_dur; 293 int off_dur; 294 } bwi_led_duration[109] = { 295 [0] = { 400, 100 }, 296 [2] = { 150, 75 }, 297 [4] = { 90, 45 }, 298 [11] = { 66, 34 }, 299 [12] = { 53, 26 }, 300 [18] = { 42, 21 }, 301 [22] = { 35, 17 }, 302 [24] = { 32, 16 }, 303 [36] = { 21, 10 }, 304 [48] = { 16, 8 }, 305 [72] = { 11, 5 }, 306 [96] = { 9, 4 }, 307 [108] = { 7, 3 } 308 }; 309 310 #ifdef BWI_DEBUG 311 #ifdef BWI_DEBUG_VERBOSE 312 static uint32_t bwi_debug = BWI_DBG_ATTACH | BWI_DBG_INIT | BWI_DBG_TXPOWER; 313 #else 314 static uint32_t bwi_debug; 315 #endif 316 TUNABLE_INT("hw.bwi.debug", (int *)&bwi_debug); 317 #endif /* BWI_DEBUG */ 318 319 static const uint8_t bwi_zero_addr[IEEE80211_ADDR_LEN]; 320 321 uint16_t 322 bwi_read_sprom(struct bwi_softc *sc, uint16_t ofs) 323 { 324 return CSR_READ_2(sc, ofs + BWI_SPROM_START); 325 } 326 327 static __inline void 328 bwi_setup_desc32(struct bwi_softc *sc, struct bwi_desc32 *desc_array, 329 int ndesc, int desc_idx, bus_addr_t paddr, int buf_len, 330 int tx) 331 { 332 struct bwi_desc32 *desc = &desc_array[desc_idx]; 333 uint32_t ctrl, addr, addr_hi, addr_lo; 334 335 addr_lo = __SHIFTOUT(paddr, BWI_DESC32_A_ADDR_MASK); 336 addr_hi = __SHIFTOUT(paddr, BWI_DESC32_A_FUNC_MASK); 337 338 addr = __SHIFTIN(addr_lo, BWI_DESC32_A_ADDR_MASK) | 339 __SHIFTIN(BWI_DESC32_A_FUNC_TXRX, BWI_DESC32_A_FUNC_MASK); 340 341 ctrl = __SHIFTIN(buf_len, BWI_DESC32_C_BUFLEN_MASK) | 342 __SHIFTIN(addr_hi, BWI_DESC32_C_ADDRHI_MASK); 343 if (desc_idx == ndesc - 1) 344 ctrl |= BWI_DESC32_C_EOR; 345 if (tx) { 346 /* XXX */ 347 ctrl |= BWI_DESC32_C_FRAME_START | 348 BWI_DESC32_C_FRAME_END | 349 BWI_DESC32_C_INTR; 350 } 351 352 desc->addr = htole32(addr); 353 desc->ctrl = htole32(ctrl); 354 } 355 356 int 357 bwi_attach(struct bwi_softc *sc) 358 { 359 struct ieee80211com *ic = &sc->sc_ic; 360 device_t dev = sc->sc_dev; 361 struct bwi_mac *mac; 362 struct bwi_phy *phy; 363 int i, error; 364 365 BWI_LOCK_INIT(sc); 366 367 /* 368 * Initialize taskq and various tasks 369 */ 370 sc->sc_tq = taskqueue_create("bwi_taskq", M_NOWAIT | M_ZERO, 371 taskqueue_thread_enqueue, &sc->sc_tq); 372 taskqueue_start_threads(&sc->sc_tq, 1, PI_NET, "%s taskq", 373 device_get_nameunit(dev)); 374 TASK_INIT(&sc->sc_restart_task, 0, bwi_restart, sc); 375 callout_init_mtx(&sc->sc_calib_ch, &sc->sc_mtx, 0); 376 mbufq_init(&sc->sc_snd, ifqmaxlen); 377 378 /* 379 * Initialize sysctl variables 380 */ 381 sc->sc_fw_version = BWI_FW_VERSION3; 382 sc->sc_led_idle = (2350 * hz) / 1000; 383 sc->sc_led_ticks = ticks - sc->sc_led_idle; 384 sc->sc_led_blink = 1; 385 sc->sc_txpwr_calib = 1; 386 #ifdef BWI_DEBUG 387 sc->sc_debug = bwi_debug; 388 #endif 389 bwi_power_on(sc, 1); 390 391 error = bwi_bbp_attach(sc); 392 if (error) 393 goto fail; 394 395 error = bwi_bbp_power_on(sc, BWI_CLOCK_MODE_FAST); 396 if (error) 397 goto fail; 398 399 if (BWI_REGWIN_EXIST(&sc->sc_com_regwin)) { 400 error = bwi_set_clock_delay(sc); 401 if (error) 402 goto fail; 403 404 error = bwi_set_clock_mode(sc, BWI_CLOCK_MODE_FAST); 405 if (error) 406 goto fail; 407 408 error = bwi_get_pwron_delay(sc); 409 if (error) 410 goto fail; 411 } 412 413 error = bwi_bus_attach(sc); 414 if (error) 415 goto fail; 416 417 bwi_get_card_flags(sc); 418 419 bwi_led_attach(sc); 420 421 for (i = 0; i < sc->sc_nmac; ++i) { 422 struct bwi_regwin *old; 423 424 mac = &sc->sc_mac[i]; 425 error = bwi_regwin_switch(sc, &mac->mac_regwin, &old); 426 if (error) 427 goto fail; 428 429 error = bwi_mac_lateattach(mac); 430 if (error) 431 goto fail; 432 433 error = bwi_regwin_switch(sc, old, NULL); 434 if (error) 435 goto fail; 436 } 437 438 /* 439 * XXX First MAC is known to exist 440 * TODO2 441 */ 442 mac = &sc->sc_mac[0]; 443 phy = &mac->mac_phy; 444 445 bwi_bbp_power_off(sc); 446 447 error = bwi_dma_alloc(sc); 448 if (error) 449 goto fail; 450 451 error = bwi_mac_fw_alloc(mac); 452 if (error) 453 goto fail; 454 455 callout_init_mtx(&sc->sc_watchdog_timer, &sc->sc_mtx, 0); 456 457 /* 458 * Setup ratesets, phytype, channels and get MAC address 459 */ 460 if (phy->phy_mode == IEEE80211_MODE_11B || 461 phy->phy_mode == IEEE80211_MODE_11G) { 462 if (phy->phy_mode == IEEE80211_MODE_11B) { 463 ic->ic_phytype = IEEE80211_T_DS; 464 } else { 465 ic->ic_phytype = IEEE80211_T_OFDM; 466 } 467 468 bwi_get_eaddr(sc, BWI_SPROM_11BG_EADDR, ic->ic_macaddr); 469 if (IEEE80211_IS_MULTICAST(ic->ic_macaddr)) { 470 bwi_get_eaddr(sc, BWI_SPROM_11A_EADDR, ic->ic_macaddr); 471 if (IEEE80211_IS_MULTICAST(ic->ic_macaddr)) { 472 device_printf(dev, 473 "invalid MAC address: %6D\n", 474 ic->ic_macaddr, ":"); 475 } 476 } 477 } else if (phy->phy_mode == IEEE80211_MODE_11A) { 478 /* TODO:11A */ 479 error = ENXIO; 480 goto fail; 481 } else { 482 panic("unknown phymode %d\n", phy->phy_mode); 483 } 484 485 /* Get locale */ 486 sc->sc_locale = __SHIFTOUT(bwi_read_sprom(sc, BWI_SPROM_CARD_INFO), 487 BWI_SPROM_CARD_INFO_LOCALE); 488 DPRINTF(sc, BWI_DBG_ATTACH, "locale: %d\n", sc->sc_locale); 489 /* XXX use locale */ 490 491 ic->ic_softc = sc; 492 493 bwi_getradiocaps(ic, IEEE80211_CHAN_MAX, &ic->ic_nchans, 494 ic->ic_channels); 495 496 ic->ic_name = device_get_nameunit(dev); 497 ic->ic_caps = IEEE80211_C_STA | 498 IEEE80211_C_SHSLOT | 499 IEEE80211_C_SHPREAMBLE | 500 IEEE80211_C_WPA | 501 IEEE80211_C_BGSCAN | 502 IEEE80211_C_MONITOR; 503 ic->ic_opmode = IEEE80211_M_STA; 504 ieee80211_ifattach(ic); 505 506 ic->ic_headroom = sizeof(struct bwi_txbuf_hdr); 507 508 /* override default methods */ 509 ic->ic_vap_create = bwi_vap_create; 510 ic->ic_vap_delete = bwi_vap_delete; 511 ic->ic_raw_xmit = bwi_raw_xmit; 512 ic->ic_updateslot = bwi_updateslot; 513 ic->ic_scan_start = bwi_scan_start; 514 ic->ic_scan_end = bwi_scan_end; 515 ic->ic_getradiocaps = bwi_getradiocaps; 516 ic->ic_set_channel = bwi_set_channel; 517 ic->ic_transmit = bwi_transmit; 518 ic->ic_parent = bwi_parent; 519 520 sc->sc_rates = ieee80211_get_ratetable(ic->ic_curchan); 521 522 ieee80211_radiotap_attach(ic, 523 &sc->sc_tx_th.wt_ihdr, sizeof(sc->sc_tx_th), 524 BWI_TX_RADIOTAP_PRESENT, 525 &sc->sc_rx_th.wr_ihdr, sizeof(sc->sc_rx_th), 526 BWI_RX_RADIOTAP_PRESENT); 527 528 /* 529 * Add sysctl nodes 530 */ 531 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 532 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 533 "fw_version", CTLFLAG_RD, &sc->sc_fw_version, 0, 534 "Firmware version"); 535 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 536 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 537 "led_idle", CTLFLAG_RW, &sc->sc_led_idle, 0, 538 "# ticks before LED enters idle state"); 539 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 540 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 541 "led_blink", CTLFLAG_RW, &sc->sc_led_blink, 0, 542 "Allow LED to blink"); 543 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 544 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 545 "txpwr_calib", CTLFLAG_RW, &sc->sc_txpwr_calib, 0, 546 "Enable software TX power calibration"); 547 #ifdef BWI_DEBUG 548 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), 549 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 550 "debug", CTLFLAG_RW, &sc->sc_debug, 0, "Debug flags"); 551 #endif 552 if (bootverbose) 553 ieee80211_announce(ic); 554 555 return (0); 556 fail: 557 BWI_LOCK_DESTROY(sc); 558 return (error); 559 } 560 561 int 562 bwi_detach(struct bwi_softc *sc) 563 { 564 struct ieee80211com *ic = &sc->sc_ic; 565 int i; 566 567 bwi_stop(sc, 1); 568 callout_drain(&sc->sc_led_blink_ch); 569 callout_drain(&sc->sc_calib_ch); 570 callout_drain(&sc->sc_watchdog_timer); 571 ieee80211_ifdetach(ic); 572 573 for (i = 0; i < sc->sc_nmac; ++i) 574 bwi_mac_detach(&sc->sc_mac[i]); 575 bwi_dma_free(sc); 576 taskqueue_free(sc->sc_tq); 577 mbufq_drain(&sc->sc_snd); 578 579 BWI_LOCK_DESTROY(sc); 580 581 return (0); 582 } 583 584 static struct ieee80211vap * 585 bwi_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 586 enum ieee80211_opmode opmode, int flags, 587 const uint8_t bssid[IEEE80211_ADDR_LEN], 588 const uint8_t mac[IEEE80211_ADDR_LEN]) 589 { 590 struct bwi_vap *bvp; 591 struct ieee80211vap *vap; 592 593 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */ 594 return NULL; 595 bvp = malloc(sizeof(struct bwi_vap), M_80211_VAP, M_WAITOK | M_ZERO); 596 vap = &bvp->bv_vap; 597 /* enable s/w bmiss handling for sta mode */ 598 ieee80211_vap_setup(ic, vap, name, unit, opmode, 599 flags | IEEE80211_CLONE_NOBEACONS, bssid); 600 601 /* override default methods */ 602 bvp->bv_newstate = vap->iv_newstate; 603 vap->iv_newstate = bwi_newstate; 604 #if 0 605 vap->iv_update_beacon = bwi_beacon_update; 606 #endif 607 ieee80211_ratectl_init(vap); 608 609 /* complete setup */ 610 ieee80211_vap_attach(vap, bwi_media_change, ieee80211_media_status, 611 mac); 612 ic->ic_opmode = opmode; 613 return vap; 614 } 615 616 static void 617 bwi_vap_delete(struct ieee80211vap *vap) 618 { 619 struct bwi_vap *bvp = BWI_VAP(vap); 620 621 ieee80211_ratectl_deinit(vap); 622 ieee80211_vap_detach(vap); 623 free(bvp, M_80211_VAP); 624 } 625 626 void 627 bwi_suspend(struct bwi_softc *sc) 628 { 629 bwi_stop(sc, 1); 630 } 631 632 void 633 bwi_resume(struct bwi_softc *sc) 634 { 635 636 if (sc->sc_ic.ic_nrunning > 0) 637 bwi_init(sc); 638 } 639 640 int 641 bwi_shutdown(struct bwi_softc *sc) 642 { 643 bwi_stop(sc, 1); 644 return 0; 645 } 646 647 static void 648 bwi_power_on(struct bwi_softc *sc, int with_pll) 649 { 650 uint32_t gpio_in, gpio_out, gpio_en; 651 uint16_t status; 652 653 gpio_in = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_IN, 4); 654 if (gpio_in & BWI_PCIM_GPIO_PWR_ON) 655 goto back; 656 657 gpio_out = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, 4); 658 gpio_en = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, 4); 659 660 gpio_out |= BWI_PCIM_GPIO_PWR_ON; 661 gpio_en |= BWI_PCIM_GPIO_PWR_ON; 662 if (with_pll) { 663 /* Turn off PLL first */ 664 gpio_out |= BWI_PCIM_GPIO_PLL_PWR_OFF; 665 gpio_en |= BWI_PCIM_GPIO_PLL_PWR_OFF; 666 } 667 668 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, gpio_out, 4); 669 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, gpio_en, 4); 670 DELAY(1000); 671 672 if (with_pll) { 673 /* Turn on PLL */ 674 gpio_out &= ~BWI_PCIM_GPIO_PLL_PWR_OFF; 675 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, gpio_out, 4); 676 DELAY(5000); 677 } 678 679 back: 680 /* Clear "Signaled Target Abort" */ 681 status = pci_read_config(sc->sc_dev, PCIR_STATUS, 2); 682 status &= ~PCIM_STATUS_STABORT; 683 pci_write_config(sc->sc_dev, PCIR_STATUS, status, 2); 684 } 685 686 static int 687 bwi_power_off(struct bwi_softc *sc, int with_pll) 688 { 689 uint32_t gpio_out, gpio_en; 690 691 pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_IN, 4); /* dummy read */ 692 gpio_out = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, 4); 693 gpio_en = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, 4); 694 695 gpio_out &= ~BWI_PCIM_GPIO_PWR_ON; 696 gpio_en |= BWI_PCIM_GPIO_PWR_ON; 697 if (with_pll) { 698 gpio_out |= BWI_PCIM_GPIO_PLL_PWR_OFF; 699 gpio_en |= BWI_PCIM_GPIO_PLL_PWR_OFF; 700 } 701 702 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, gpio_out, 4); 703 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, gpio_en, 4); 704 return 0; 705 } 706 707 int 708 bwi_regwin_switch(struct bwi_softc *sc, struct bwi_regwin *rw, 709 struct bwi_regwin **old_rw) 710 { 711 int error; 712 713 if (old_rw != NULL) 714 *old_rw = NULL; 715 716 if (!BWI_REGWIN_EXIST(rw)) 717 return EINVAL; 718 719 if (sc->sc_cur_regwin != rw) { 720 error = bwi_regwin_select(sc, rw->rw_id); 721 if (error) { 722 device_printf(sc->sc_dev, "can't select regwin %d\n", 723 rw->rw_id); 724 return error; 725 } 726 } 727 728 if (old_rw != NULL) 729 *old_rw = sc->sc_cur_regwin; 730 sc->sc_cur_regwin = rw; 731 return 0; 732 } 733 734 static int 735 bwi_regwin_select(struct bwi_softc *sc, int id) 736 { 737 uint32_t win = BWI_PCIM_REGWIN(id); 738 int i; 739 740 #define RETRY_MAX 50 741 for (i = 0; i < RETRY_MAX; ++i) { 742 pci_write_config(sc->sc_dev, BWI_PCIR_SEL_REGWIN, win, 4); 743 if (pci_read_config(sc->sc_dev, BWI_PCIR_SEL_REGWIN, 4) == win) 744 return 0; 745 DELAY(10); 746 } 747 #undef RETRY_MAX 748 749 return ENXIO; 750 } 751 752 static void 753 bwi_regwin_info(struct bwi_softc *sc, uint16_t *type, uint8_t *rev) 754 { 755 uint32_t val; 756 757 val = CSR_READ_4(sc, BWI_ID_HI); 758 *type = BWI_ID_HI_REGWIN_TYPE(val); 759 *rev = BWI_ID_HI_REGWIN_REV(val); 760 761 DPRINTF(sc, BWI_DBG_ATTACH, "regwin: type 0x%03x, rev %d, " 762 "vendor 0x%04x\n", *type, *rev, 763 __SHIFTOUT(val, BWI_ID_HI_REGWIN_VENDOR_MASK)); 764 } 765 766 static int 767 bwi_bbp_attach(struct bwi_softc *sc) 768 { 769 uint16_t bbp_id, rw_type; 770 uint8_t rw_rev; 771 uint32_t info; 772 int error, nregwin, i; 773 774 /* 775 * Get 0th regwin information 776 * NOTE: 0th regwin should exist 777 */ 778 error = bwi_regwin_select(sc, 0); 779 if (error) { 780 device_printf(sc->sc_dev, "can't select regwin 0\n"); 781 return error; 782 } 783 bwi_regwin_info(sc, &rw_type, &rw_rev); 784 785 /* 786 * Find out BBP id 787 */ 788 bbp_id = 0; 789 info = 0; 790 if (rw_type == BWI_REGWIN_T_COM) { 791 info = CSR_READ_4(sc, BWI_INFO); 792 bbp_id = __SHIFTOUT(info, BWI_INFO_BBPID_MASK); 793 794 BWI_CREATE_REGWIN(&sc->sc_com_regwin, 0, rw_type, rw_rev); 795 796 sc->sc_cap = CSR_READ_4(sc, BWI_CAPABILITY); 797 } else { 798 for (i = 0; i < nitems(bwi_bbpid_map); ++i) { 799 if (sc->sc_pci_did >= bwi_bbpid_map[i].did_min && 800 sc->sc_pci_did <= bwi_bbpid_map[i].did_max) { 801 bbp_id = bwi_bbpid_map[i].bbp_id; 802 break; 803 } 804 } 805 if (bbp_id == 0) { 806 device_printf(sc->sc_dev, "no BBP id for device id " 807 "0x%04x\n", sc->sc_pci_did); 808 return ENXIO; 809 } 810 811 info = __SHIFTIN(sc->sc_pci_revid, BWI_INFO_BBPREV_MASK) | 812 __SHIFTIN(0, BWI_INFO_BBPPKG_MASK); 813 } 814 815 /* 816 * Find out number of regwins 817 */ 818 nregwin = 0; 819 if (rw_type == BWI_REGWIN_T_COM && rw_rev >= 4) { 820 nregwin = __SHIFTOUT(info, BWI_INFO_NREGWIN_MASK); 821 } else { 822 for (i = 0; i < nitems(bwi_regwin_count); ++i) { 823 if (bwi_regwin_count[i].bbp_id == bbp_id) { 824 nregwin = bwi_regwin_count[i].nregwin; 825 break; 826 } 827 } 828 if (nregwin == 0) { 829 device_printf(sc->sc_dev, "no number of win for " 830 "BBP id 0x%04x\n", bbp_id); 831 return ENXIO; 832 } 833 } 834 835 /* Record BBP id/rev for later using */ 836 sc->sc_bbp_id = bbp_id; 837 sc->sc_bbp_rev = __SHIFTOUT(info, BWI_INFO_BBPREV_MASK); 838 sc->sc_bbp_pkg = __SHIFTOUT(info, BWI_INFO_BBPPKG_MASK); 839 device_printf(sc->sc_dev, "BBP: id 0x%04x, rev 0x%x, pkg %d\n", 840 sc->sc_bbp_id, sc->sc_bbp_rev, sc->sc_bbp_pkg); 841 842 DPRINTF(sc, BWI_DBG_ATTACH, "nregwin %d, cap 0x%08x\n", 843 nregwin, sc->sc_cap); 844 845 /* 846 * Create rest of the regwins 847 */ 848 849 /* Don't re-create common regwin, if it is already created */ 850 i = BWI_REGWIN_EXIST(&sc->sc_com_regwin) ? 1 : 0; 851 852 for (; i < nregwin; ++i) { 853 /* 854 * Get regwin information 855 */ 856 error = bwi_regwin_select(sc, i); 857 if (error) { 858 device_printf(sc->sc_dev, 859 "can't select regwin %d\n", i); 860 return error; 861 } 862 bwi_regwin_info(sc, &rw_type, &rw_rev); 863 864 /* 865 * Try attach: 866 * 1) Bus (PCI/PCIE) regwin 867 * 2) MAC regwin 868 * Ignore rest types of regwin 869 */ 870 if (rw_type == BWI_REGWIN_T_BUSPCI || 871 rw_type == BWI_REGWIN_T_BUSPCIE) { 872 if (BWI_REGWIN_EXIST(&sc->sc_bus_regwin)) { 873 device_printf(sc->sc_dev, 874 "bus regwin already exists\n"); 875 } else { 876 BWI_CREATE_REGWIN(&sc->sc_bus_regwin, i, 877 rw_type, rw_rev); 878 } 879 } else if (rw_type == BWI_REGWIN_T_MAC) { 880 /* XXX ignore return value */ 881 bwi_mac_attach(sc, i, rw_rev); 882 } 883 } 884 885 /* At least one MAC shold exist */ 886 if (!BWI_REGWIN_EXIST(&sc->sc_mac[0].mac_regwin)) { 887 device_printf(sc->sc_dev, "no MAC was found\n"); 888 return ENXIO; 889 } 890 KASSERT(sc->sc_nmac > 0, ("no mac's")); 891 892 /* Bus regwin must exist */ 893 if (!BWI_REGWIN_EXIST(&sc->sc_bus_regwin)) { 894 device_printf(sc->sc_dev, "no bus regwin was found\n"); 895 return ENXIO; 896 } 897 898 /* Start with first MAC */ 899 error = bwi_regwin_switch(sc, &sc->sc_mac[0].mac_regwin, NULL); 900 if (error) 901 return error; 902 903 return 0; 904 } 905 906 int 907 bwi_bus_init(struct bwi_softc *sc, struct bwi_mac *mac) 908 { 909 struct bwi_regwin *old, *bus; 910 uint32_t val; 911 int error; 912 913 bus = &sc->sc_bus_regwin; 914 KASSERT(sc->sc_cur_regwin == &mac->mac_regwin, ("not cur regwin")); 915 916 /* 917 * Tell bus to generate requested interrupts 918 */ 919 if (bus->rw_rev < 6 && bus->rw_type == BWI_REGWIN_T_BUSPCI) { 920 /* 921 * NOTE: Read BWI_FLAGS from MAC regwin 922 */ 923 val = CSR_READ_4(sc, BWI_FLAGS); 924 925 error = bwi_regwin_switch(sc, bus, &old); 926 if (error) 927 return error; 928 929 CSR_SETBITS_4(sc, BWI_INTRVEC, (val & BWI_FLAGS_INTR_MASK)); 930 } else { 931 uint32_t mac_mask; 932 933 mac_mask = 1 << mac->mac_id; 934 935 error = bwi_regwin_switch(sc, bus, &old); 936 if (error) 937 return error; 938 939 val = pci_read_config(sc->sc_dev, BWI_PCIR_INTCTL, 4); 940 val |= mac_mask << 8; 941 pci_write_config(sc->sc_dev, BWI_PCIR_INTCTL, val, 4); 942 } 943 944 if (sc->sc_flags & BWI_F_BUS_INITED) 945 goto back; 946 947 if (bus->rw_type == BWI_REGWIN_T_BUSPCI) { 948 /* 949 * Enable prefetch and burst 950 */ 951 CSR_SETBITS_4(sc, BWI_BUS_CONFIG, 952 BWI_BUS_CONFIG_PREFETCH | BWI_BUS_CONFIG_BURST); 953 954 if (bus->rw_rev < 5) { 955 struct bwi_regwin *com = &sc->sc_com_regwin; 956 957 /* 958 * Configure timeouts for bus operation 959 */ 960 961 /* 962 * Set service timeout and request timeout 963 */ 964 CSR_SETBITS_4(sc, BWI_CONF_LO, 965 __SHIFTIN(BWI_CONF_LO_SERVTO, BWI_CONF_LO_SERVTO_MASK) | 966 __SHIFTIN(BWI_CONF_LO_REQTO, BWI_CONF_LO_REQTO_MASK)); 967 968 /* 969 * If there is common regwin, we switch to that regwin 970 * and switch back to bus regwin once we have done. 971 */ 972 if (BWI_REGWIN_EXIST(com)) { 973 error = bwi_regwin_switch(sc, com, NULL); 974 if (error) 975 return error; 976 } 977 978 /* Let bus know what we have changed */ 979 CSR_WRITE_4(sc, BWI_BUS_ADDR, BWI_BUS_ADDR_MAGIC); 980 CSR_READ_4(sc, BWI_BUS_ADDR); /* Flush */ 981 CSR_WRITE_4(sc, BWI_BUS_DATA, 0); 982 CSR_READ_4(sc, BWI_BUS_DATA); /* Flush */ 983 984 if (BWI_REGWIN_EXIST(com)) { 985 error = bwi_regwin_switch(sc, bus, NULL); 986 if (error) 987 return error; 988 } 989 } else if (bus->rw_rev >= 11) { 990 /* 991 * Enable memory read multiple 992 */ 993 CSR_SETBITS_4(sc, BWI_BUS_CONFIG, BWI_BUS_CONFIG_MRM); 994 } 995 } else { 996 /* TODO:PCIE */ 997 } 998 999 sc->sc_flags |= BWI_F_BUS_INITED; 1000 back: 1001 return bwi_regwin_switch(sc, old, NULL); 1002 } 1003 1004 static void 1005 bwi_get_card_flags(struct bwi_softc *sc) 1006 { 1007 #define PCI_VENDOR_APPLE 0x106b 1008 #define PCI_VENDOR_DELL 0x1028 1009 sc->sc_card_flags = bwi_read_sprom(sc, BWI_SPROM_CARD_FLAGS); 1010 if (sc->sc_card_flags == 0xffff) 1011 sc->sc_card_flags = 0; 1012 1013 if (sc->sc_pci_subvid == PCI_VENDOR_DELL && 1014 sc->sc_bbp_id == BWI_BBPID_BCM4301 && 1015 sc->sc_pci_revid == 0x74) 1016 sc->sc_card_flags |= BWI_CARD_F_BT_COEXIST; 1017 1018 if (sc->sc_pci_subvid == PCI_VENDOR_APPLE && 1019 sc->sc_pci_subdid == 0x4e && /* XXX */ 1020 sc->sc_pci_revid > 0x40) 1021 sc->sc_card_flags |= BWI_CARD_F_PA_GPIO9; 1022 1023 DPRINTF(sc, BWI_DBG_ATTACH, "card flags 0x%04x\n", sc->sc_card_flags); 1024 #undef PCI_VENDOR_DELL 1025 #undef PCI_VENDOR_APPLE 1026 } 1027 1028 static void 1029 bwi_get_eaddr(struct bwi_softc *sc, uint16_t eaddr_ofs, uint8_t *eaddr) 1030 { 1031 int i; 1032 1033 for (i = 0; i < 3; ++i) { 1034 *((uint16_t *)eaddr + i) = 1035 htobe16(bwi_read_sprom(sc, eaddr_ofs + 2 * i)); 1036 } 1037 } 1038 1039 static void 1040 bwi_get_clock_freq(struct bwi_softc *sc, struct bwi_clock_freq *freq) 1041 { 1042 struct bwi_regwin *com; 1043 uint32_t val; 1044 u_int div; 1045 int src; 1046 1047 bzero(freq, sizeof(*freq)); 1048 com = &sc->sc_com_regwin; 1049 1050 KASSERT(BWI_REGWIN_EXIST(com), ("regwin does not exist")); 1051 KASSERT(sc->sc_cur_regwin == com, ("wrong regwin")); 1052 KASSERT(sc->sc_cap & BWI_CAP_CLKMODE, ("wrong clock mode")); 1053 1054 /* 1055 * Calculate clock frequency 1056 */ 1057 src = -1; 1058 div = 0; 1059 if (com->rw_rev < 6) { 1060 val = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, 4); 1061 if (val & BWI_PCIM_GPIO_OUT_CLKSRC) { 1062 src = BWI_CLKSRC_PCI; 1063 div = 64; 1064 } else { 1065 src = BWI_CLKSRC_CS_OSC; 1066 div = 32; 1067 } 1068 } else if (com->rw_rev < 10) { 1069 val = CSR_READ_4(sc, BWI_CLOCK_CTRL); 1070 1071 src = __SHIFTOUT(val, BWI_CLOCK_CTRL_CLKSRC); 1072 if (src == BWI_CLKSRC_LP_OSC) { 1073 div = 1; 1074 } else { 1075 div = (__SHIFTOUT(val, BWI_CLOCK_CTRL_FDIV) + 1) << 2; 1076 1077 /* Unknown source */ 1078 if (src >= BWI_CLKSRC_MAX) 1079 src = BWI_CLKSRC_CS_OSC; 1080 } 1081 } else { 1082 val = CSR_READ_4(sc, BWI_CLOCK_INFO); 1083 1084 src = BWI_CLKSRC_CS_OSC; 1085 div = (__SHIFTOUT(val, BWI_CLOCK_INFO_FDIV) + 1) << 2; 1086 } 1087 1088 KASSERT(src >= 0 && src < BWI_CLKSRC_MAX, ("bad src %d", src)); 1089 KASSERT(div != 0, ("div zero")); 1090 1091 DPRINTF(sc, BWI_DBG_ATTACH, "clksrc %s\n", 1092 src == BWI_CLKSRC_PCI ? "PCI" : 1093 (src == BWI_CLKSRC_LP_OSC ? "LP_OSC" : "CS_OSC")); 1094 1095 freq->clkfreq_min = bwi_clkfreq[src].freq_min / div; 1096 freq->clkfreq_max = bwi_clkfreq[src].freq_max / div; 1097 1098 DPRINTF(sc, BWI_DBG_ATTACH, "clkfreq min %u, max %u\n", 1099 freq->clkfreq_min, freq->clkfreq_max); 1100 } 1101 1102 static int 1103 bwi_set_clock_mode(struct bwi_softc *sc, enum bwi_clock_mode clk_mode) 1104 { 1105 struct bwi_regwin *old, *com; 1106 uint32_t clk_ctrl, clk_src; 1107 int error, pwr_off = 0; 1108 1109 com = &sc->sc_com_regwin; 1110 if (!BWI_REGWIN_EXIST(com)) 1111 return 0; 1112 1113 if (com->rw_rev >= 10 || com->rw_rev < 6) 1114 return 0; 1115 1116 /* 1117 * For common regwin whose rev is [6, 10), the chip 1118 * must be capable to change clock mode. 1119 */ 1120 if ((sc->sc_cap & BWI_CAP_CLKMODE) == 0) 1121 return 0; 1122 1123 error = bwi_regwin_switch(sc, com, &old); 1124 if (error) 1125 return error; 1126 1127 if (clk_mode == BWI_CLOCK_MODE_FAST) 1128 bwi_power_on(sc, 0); /* Don't turn on PLL */ 1129 1130 clk_ctrl = CSR_READ_4(sc, BWI_CLOCK_CTRL); 1131 clk_src = __SHIFTOUT(clk_ctrl, BWI_CLOCK_CTRL_CLKSRC); 1132 1133 switch (clk_mode) { 1134 case BWI_CLOCK_MODE_FAST: 1135 clk_ctrl &= ~BWI_CLOCK_CTRL_SLOW; 1136 clk_ctrl |= BWI_CLOCK_CTRL_IGNPLL; 1137 break; 1138 case BWI_CLOCK_MODE_SLOW: 1139 clk_ctrl |= BWI_CLOCK_CTRL_SLOW; 1140 break; 1141 case BWI_CLOCK_MODE_DYN: 1142 clk_ctrl &= ~(BWI_CLOCK_CTRL_SLOW | 1143 BWI_CLOCK_CTRL_IGNPLL | 1144 BWI_CLOCK_CTRL_NODYN); 1145 if (clk_src != BWI_CLKSRC_CS_OSC) { 1146 clk_ctrl |= BWI_CLOCK_CTRL_NODYN; 1147 pwr_off = 1; 1148 } 1149 break; 1150 } 1151 CSR_WRITE_4(sc, BWI_CLOCK_CTRL, clk_ctrl); 1152 1153 if (pwr_off) 1154 bwi_power_off(sc, 0); /* Leave PLL as it is */ 1155 1156 return bwi_regwin_switch(sc, old, NULL); 1157 } 1158 1159 static int 1160 bwi_set_clock_delay(struct bwi_softc *sc) 1161 { 1162 struct bwi_regwin *old, *com; 1163 int error; 1164 1165 com = &sc->sc_com_regwin; 1166 if (!BWI_REGWIN_EXIST(com)) 1167 return 0; 1168 1169 error = bwi_regwin_switch(sc, com, &old); 1170 if (error) 1171 return error; 1172 1173 if (sc->sc_bbp_id == BWI_BBPID_BCM4321) { 1174 if (sc->sc_bbp_rev == 0) 1175 CSR_WRITE_4(sc, BWI_CONTROL, BWI_CONTROL_MAGIC0); 1176 else if (sc->sc_bbp_rev == 1) 1177 CSR_WRITE_4(sc, BWI_CONTROL, BWI_CONTROL_MAGIC1); 1178 } 1179 1180 if (sc->sc_cap & BWI_CAP_CLKMODE) { 1181 if (com->rw_rev >= 10) { 1182 CSR_FILT_SETBITS_4(sc, BWI_CLOCK_INFO, 0xffff, 0x40000); 1183 } else { 1184 struct bwi_clock_freq freq; 1185 1186 bwi_get_clock_freq(sc, &freq); 1187 CSR_WRITE_4(sc, BWI_PLL_ON_DELAY, 1188 howmany(freq.clkfreq_max * 150, 1000000)); 1189 CSR_WRITE_4(sc, BWI_FREQ_SEL_DELAY, 1190 howmany(freq.clkfreq_max * 15, 1000000)); 1191 } 1192 } 1193 1194 return bwi_regwin_switch(sc, old, NULL); 1195 } 1196 1197 static void 1198 bwi_init(struct bwi_softc *sc) 1199 { 1200 struct ieee80211com *ic = &sc->sc_ic; 1201 1202 BWI_LOCK(sc); 1203 bwi_init_statechg(sc, 1); 1204 BWI_UNLOCK(sc); 1205 1206 if (sc->sc_flags & BWI_F_RUNNING) 1207 ieee80211_start_all(ic); /* start all vap's */ 1208 } 1209 1210 static void 1211 bwi_init_statechg(struct bwi_softc *sc, int statechg) 1212 { 1213 struct bwi_mac *mac; 1214 int error; 1215 1216 BWI_ASSERT_LOCKED(sc); 1217 1218 bwi_stop_locked(sc, statechg); 1219 1220 bwi_bbp_power_on(sc, BWI_CLOCK_MODE_FAST); 1221 1222 /* TODO: 2 MAC */ 1223 1224 mac = &sc->sc_mac[0]; 1225 error = bwi_regwin_switch(sc, &mac->mac_regwin, NULL); 1226 if (error) { 1227 device_printf(sc->sc_dev, "%s: error %d on regwin switch\n", 1228 __func__, error); 1229 goto bad; 1230 } 1231 error = bwi_mac_init(mac); 1232 if (error) { 1233 device_printf(sc->sc_dev, "%s: error %d on MAC init\n", 1234 __func__, error); 1235 goto bad; 1236 } 1237 1238 bwi_bbp_power_on(sc, BWI_CLOCK_MODE_DYN); 1239 1240 bwi_set_bssid(sc, bwi_zero_addr); /* Clear BSSID */ 1241 bwi_set_addr_filter(sc, BWI_ADDR_FILTER_MYADDR, sc->sc_ic.ic_macaddr); 1242 1243 bwi_mac_reset_hwkeys(mac); 1244 1245 if ((mac->mac_flags & BWI_MAC_F_HAS_TXSTATS) == 0) { 1246 int i; 1247 1248 #define NRETRY 1000 1249 /* 1250 * Drain any possible pending TX status 1251 */ 1252 for (i = 0; i < NRETRY; ++i) { 1253 if ((CSR_READ_4(sc, BWI_TXSTATUS0) & 1254 BWI_TXSTATUS0_VALID) == 0) 1255 break; 1256 CSR_READ_4(sc, BWI_TXSTATUS1); 1257 } 1258 if (i == NRETRY) 1259 device_printf(sc->sc_dev, 1260 "%s: can't drain TX status\n", __func__); 1261 #undef NRETRY 1262 } 1263 1264 if (mac->mac_phy.phy_mode == IEEE80211_MODE_11G) 1265 bwi_mac_updateslot(mac, 1); 1266 1267 /* Start MAC */ 1268 error = bwi_mac_start(mac); 1269 if (error) { 1270 device_printf(sc->sc_dev, "%s: error %d starting MAC\n", 1271 __func__, error); 1272 goto bad; 1273 } 1274 1275 /* Clear stop flag before enabling interrupt */ 1276 sc->sc_flags &= ~BWI_F_STOP; 1277 sc->sc_flags |= BWI_F_RUNNING; 1278 callout_reset(&sc->sc_watchdog_timer, hz, bwi_watchdog, sc); 1279 1280 /* Enable intrs */ 1281 bwi_enable_intrs(sc, BWI_INIT_INTRS); 1282 return; 1283 bad: 1284 bwi_stop_locked(sc, 1); 1285 } 1286 1287 static void 1288 bwi_parent(struct ieee80211com *ic) 1289 { 1290 struct bwi_softc *sc = ic->ic_softc; 1291 int startall = 0; 1292 1293 BWI_LOCK(sc); 1294 if (ic->ic_nrunning > 0) { 1295 struct bwi_mac *mac; 1296 int promisc = -1; 1297 1298 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 1299 ("current regwin type %d", 1300 sc->sc_cur_regwin->rw_type)); 1301 mac = (struct bwi_mac *)sc->sc_cur_regwin; 1302 1303 if (ic->ic_promisc > 0 && (sc->sc_flags & BWI_F_PROMISC) == 0) { 1304 promisc = 1; 1305 sc->sc_flags |= BWI_F_PROMISC; 1306 } else if (ic->ic_promisc == 0 && 1307 (sc->sc_flags & BWI_F_PROMISC) != 0) { 1308 promisc = 0; 1309 sc->sc_flags &= ~BWI_F_PROMISC; 1310 } 1311 1312 if (promisc >= 0) 1313 bwi_mac_set_promisc(mac, promisc); 1314 } 1315 if (ic->ic_nrunning > 0) { 1316 if ((sc->sc_flags & BWI_F_RUNNING) == 0) { 1317 bwi_init_statechg(sc, 1); 1318 startall = 1; 1319 } 1320 } else if (sc->sc_flags & BWI_F_RUNNING) 1321 bwi_stop_locked(sc, 1); 1322 BWI_UNLOCK(sc); 1323 if (startall) 1324 ieee80211_start_all(ic); 1325 } 1326 1327 static int 1328 bwi_transmit(struct ieee80211com *ic, struct mbuf *m) 1329 { 1330 struct bwi_softc *sc = ic->ic_softc; 1331 int error; 1332 1333 BWI_LOCK(sc); 1334 if ((sc->sc_flags & BWI_F_RUNNING) == 0) { 1335 BWI_UNLOCK(sc); 1336 return (ENXIO); 1337 } 1338 error = mbufq_enqueue(&sc->sc_snd, m); 1339 if (error) { 1340 BWI_UNLOCK(sc); 1341 return (error); 1342 } 1343 bwi_start_locked(sc); 1344 BWI_UNLOCK(sc); 1345 return (0); 1346 } 1347 1348 static void 1349 bwi_start_locked(struct bwi_softc *sc) 1350 { 1351 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING]; 1352 struct ieee80211_frame *wh; 1353 struct ieee80211_node *ni; 1354 struct mbuf *m; 1355 int trans, idx; 1356 1357 BWI_ASSERT_LOCKED(sc); 1358 1359 trans = 0; 1360 idx = tbd->tbd_idx; 1361 1362 while (tbd->tbd_buf[idx].tb_mbuf == NULL && 1363 tbd->tbd_used + BWI_TX_NSPRDESC < BWI_TX_NDESC && 1364 (m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 1365 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif; 1366 wh = mtod(m, struct ieee80211_frame *); 1367 if ((wh->i_fc[1] & IEEE80211_FC1_PROTECTED) != 0 && 1368 ieee80211_crypto_encap(ni, m) == NULL) { 1369 if_inc_counter(ni->ni_vap->iv_ifp, 1370 IFCOUNTER_OERRORS, 1); 1371 ieee80211_free_node(ni); 1372 m_freem(m); 1373 continue; 1374 } 1375 if (bwi_encap(sc, idx, m, ni) != 0) { 1376 /* 'm' is freed in bwi_encap() if we reach here */ 1377 if (ni != NULL) { 1378 if_inc_counter(ni->ni_vap->iv_ifp, 1379 IFCOUNTER_OERRORS, 1); 1380 ieee80211_free_node(ni); 1381 } else 1382 counter_u64_add(sc->sc_ic.ic_oerrors, 1); 1383 continue; 1384 } 1385 trans = 1; 1386 tbd->tbd_used++; 1387 idx = (idx + 1) % BWI_TX_NDESC; 1388 } 1389 1390 tbd->tbd_idx = idx; 1391 if (trans) 1392 sc->sc_tx_timer = 5; 1393 } 1394 1395 static int 1396 bwi_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 1397 const struct ieee80211_bpf_params *params) 1398 { 1399 struct ieee80211com *ic = ni->ni_ic; 1400 struct bwi_softc *sc = ic->ic_softc; 1401 /* XXX wme? */ 1402 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING]; 1403 int idx, error; 1404 1405 if ((sc->sc_flags & BWI_F_RUNNING) == 0) { 1406 m_freem(m); 1407 return ENETDOWN; 1408 } 1409 1410 BWI_LOCK(sc); 1411 idx = tbd->tbd_idx; 1412 KASSERT(tbd->tbd_buf[idx].tb_mbuf == NULL, ("slot %d not empty", idx)); 1413 if (params == NULL) { 1414 /* 1415 * Legacy path; interpret frame contents to decide 1416 * precisely how to send the frame. 1417 */ 1418 error = bwi_encap(sc, idx, m, ni); 1419 } else { 1420 /* 1421 * Caller supplied explicit parameters to use in 1422 * sending the frame. 1423 */ 1424 error = bwi_encap_raw(sc, idx, m, ni, params); 1425 } 1426 if (error == 0) { 1427 tbd->tbd_used++; 1428 tbd->tbd_idx = (idx + 1) % BWI_TX_NDESC; 1429 sc->sc_tx_timer = 5; 1430 } 1431 BWI_UNLOCK(sc); 1432 return error; 1433 } 1434 1435 static void 1436 bwi_watchdog(void *arg) 1437 { 1438 struct bwi_softc *sc; 1439 1440 sc = arg; 1441 BWI_ASSERT_LOCKED(sc); 1442 if (sc->sc_tx_timer != 0 && --sc->sc_tx_timer == 0) { 1443 device_printf(sc->sc_dev, "watchdog timeout\n"); 1444 counter_u64_add(sc->sc_ic.ic_oerrors, 1); 1445 taskqueue_enqueue(sc->sc_tq, &sc->sc_restart_task); 1446 } 1447 callout_reset(&sc->sc_watchdog_timer, hz, bwi_watchdog, sc); 1448 } 1449 1450 static void 1451 bwi_stop(struct bwi_softc *sc, int statechg) 1452 { 1453 BWI_LOCK(sc); 1454 bwi_stop_locked(sc, statechg); 1455 BWI_UNLOCK(sc); 1456 } 1457 1458 static void 1459 bwi_stop_locked(struct bwi_softc *sc, int statechg) 1460 { 1461 struct bwi_mac *mac; 1462 int i, error, pwr_off = 0; 1463 1464 BWI_ASSERT_LOCKED(sc); 1465 1466 callout_stop(&sc->sc_calib_ch); 1467 callout_stop(&sc->sc_led_blink_ch); 1468 sc->sc_led_blinking = 0; 1469 sc->sc_flags |= BWI_F_STOP; 1470 1471 if (sc->sc_flags & BWI_F_RUNNING) { 1472 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 1473 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 1474 mac = (struct bwi_mac *)sc->sc_cur_regwin; 1475 1476 bwi_disable_intrs(sc, BWI_ALL_INTRS); 1477 CSR_READ_4(sc, BWI_MAC_INTR_MASK); 1478 bwi_mac_stop(mac); 1479 } 1480 1481 for (i = 0; i < sc->sc_nmac; ++i) { 1482 struct bwi_regwin *old_rw; 1483 1484 mac = &sc->sc_mac[i]; 1485 if ((mac->mac_flags & BWI_MAC_F_INITED) == 0) 1486 continue; 1487 1488 error = bwi_regwin_switch(sc, &mac->mac_regwin, &old_rw); 1489 if (error) 1490 continue; 1491 1492 bwi_mac_shutdown(mac); 1493 pwr_off = 1; 1494 1495 bwi_regwin_switch(sc, old_rw, NULL); 1496 } 1497 1498 if (pwr_off) 1499 bwi_bbp_power_off(sc); 1500 1501 sc->sc_tx_timer = 0; 1502 callout_stop(&sc->sc_watchdog_timer); 1503 sc->sc_flags &= ~BWI_F_RUNNING; 1504 } 1505 1506 void 1507 bwi_intr(void *xsc) 1508 { 1509 struct epoch_tracker et; 1510 struct bwi_softc *sc = xsc; 1511 struct bwi_mac *mac; 1512 uint32_t intr_status; 1513 uint32_t txrx_intr_status[BWI_TXRX_NRING]; 1514 int i, txrx_error, tx = 0, rx_data = -1; 1515 1516 BWI_LOCK(sc); 1517 1518 if ((sc->sc_flags & BWI_F_RUNNING) == 0 || 1519 (sc->sc_flags & BWI_F_STOP)) { 1520 BWI_UNLOCK(sc); 1521 return; 1522 } 1523 /* 1524 * Get interrupt status 1525 */ 1526 intr_status = CSR_READ_4(sc, BWI_MAC_INTR_STATUS); 1527 if (intr_status == 0xffffffff) { /* Not for us */ 1528 BWI_UNLOCK(sc); 1529 return; 1530 } 1531 1532 DPRINTF(sc, BWI_DBG_INTR, "intr status 0x%08x\n", intr_status); 1533 1534 intr_status &= CSR_READ_4(sc, BWI_MAC_INTR_MASK); 1535 if (intr_status == 0) { /* Nothing is interesting */ 1536 BWI_UNLOCK(sc); 1537 return; 1538 } 1539 1540 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 1541 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 1542 mac = (struct bwi_mac *)sc->sc_cur_regwin; 1543 1544 txrx_error = 0; 1545 DPRINTF(sc, BWI_DBG_INTR, "%s\n", "TX/RX intr"); 1546 for (i = 0; i < BWI_TXRX_NRING; ++i) { 1547 uint32_t mask; 1548 1549 if (BWI_TXRX_IS_RX(i)) 1550 mask = BWI_TXRX_RX_INTRS; 1551 else 1552 mask = BWI_TXRX_TX_INTRS; 1553 1554 txrx_intr_status[i] = 1555 CSR_READ_4(sc, BWI_TXRX_INTR_STATUS(i)) & mask; 1556 1557 _DPRINTF(sc, BWI_DBG_INTR, ", %d 0x%08x", 1558 i, txrx_intr_status[i]); 1559 1560 if (txrx_intr_status[i] & BWI_TXRX_INTR_ERROR) { 1561 device_printf(sc->sc_dev, 1562 "%s: intr fatal TX/RX (%d) error 0x%08x\n", 1563 __func__, i, txrx_intr_status[i]); 1564 txrx_error = 1; 1565 } 1566 } 1567 _DPRINTF(sc, BWI_DBG_INTR, "%s\n", ""); 1568 1569 /* 1570 * Acknowledge interrupt 1571 */ 1572 CSR_WRITE_4(sc, BWI_MAC_INTR_STATUS, intr_status); 1573 1574 for (i = 0; i < BWI_TXRX_NRING; ++i) 1575 CSR_WRITE_4(sc, BWI_TXRX_INTR_STATUS(i), txrx_intr_status[i]); 1576 1577 /* Disable all interrupts */ 1578 bwi_disable_intrs(sc, BWI_ALL_INTRS); 1579 1580 /* 1581 * http://bcm-specs.sipsolutions.net/Interrupts 1582 * Says for this bit (0x800): 1583 * "Fatal Error 1584 * 1585 * We got this one while testing things when by accident the 1586 * template ram wasn't set to big endian when it should have 1587 * been after writing the initial values. It keeps on being 1588 * triggered, the only way to stop it seems to shut down the 1589 * chip." 1590 * 1591 * Suggesting that we should never get it and if we do we're not 1592 * feeding TX packets into the MAC correctly if we do... Apparently, 1593 * it is valid only on mac version 5 and higher, but I couldn't 1594 * find a reference for that... Since I see them from time to time 1595 * on my card, this suggests an error in the tx path still... 1596 */ 1597 if (intr_status & BWI_INTR_PHY_TXERR) { 1598 if (mac->mac_flags & BWI_MAC_F_PHYE_RESET) { 1599 device_printf(sc->sc_dev, "%s: intr PHY TX error\n", 1600 __func__); 1601 taskqueue_enqueue(sc->sc_tq, &sc->sc_restart_task); 1602 BWI_UNLOCK(sc); 1603 return; 1604 } 1605 } 1606 1607 if (txrx_error) { 1608 /* TODO: reset device */ 1609 } 1610 1611 if (intr_status & BWI_INTR_TBTT) 1612 bwi_mac_config_ps(mac); 1613 1614 if (intr_status & BWI_INTR_EO_ATIM) 1615 device_printf(sc->sc_dev, "EO_ATIM\n"); 1616 1617 if (intr_status & BWI_INTR_PMQ) { 1618 for (;;) { 1619 if ((CSR_READ_4(sc, BWI_MAC_PS_STATUS) & 0x8) == 0) 1620 break; 1621 } 1622 CSR_WRITE_2(sc, BWI_MAC_PS_STATUS, 0x2); 1623 } 1624 1625 if (intr_status & BWI_INTR_NOISE) 1626 device_printf(sc->sc_dev, "intr noise\n"); 1627 1628 if (txrx_intr_status[0] & BWI_TXRX_INTR_RX) { 1629 NET_EPOCH_ENTER(et); 1630 rx_data = sc->sc_rxeof(sc); 1631 NET_EPOCH_EXIT(et); 1632 if (sc->sc_flags & BWI_F_STOP) { 1633 BWI_UNLOCK(sc); 1634 return; 1635 } 1636 } 1637 1638 if (txrx_intr_status[3] & BWI_TXRX_INTR_RX) { 1639 sc->sc_txeof_status(sc); 1640 tx = 1; 1641 } 1642 1643 if (intr_status & BWI_INTR_TX_DONE) { 1644 bwi_txeof(sc); 1645 tx = 1; 1646 } 1647 1648 /* Re-enable interrupts */ 1649 bwi_enable_intrs(sc, BWI_INIT_INTRS); 1650 1651 if (sc->sc_blink_led != NULL && sc->sc_led_blink) { 1652 int evt = BWI_LED_EVENT_NONE; 1653 1654 if (tx && rx_data > 0) { 1655 if (sc->sc_rx_rate > sc->sc_tx_rate) 1656 evt = BWI_LED_EVENT_RX; 1657 else 1658 evt = BWI_LED_EVENT_TX; 1659 } else if (tx) { 1660 evt = BWI_LED_EVENT_TX; 1661 } else if (rx_data > 0) { 1662 evt = BWI_LED_EVENT_RX; 1663 } else if (rx_data == 0) { 1664 evt = BWI_LED_EVENT_POLL; 1665 } 1666 1667 if (evt != BWI_LED_EVENT_NONE) 1668 bwi_led_event(sc, evt); 1669 } 1670 1671 BWI_UNLOCK(sc); 1672 } 1673 1674 static void 1675 bwi_scan_start(struct ieee80211com *ic) 1676 { 1677 struct bwi_softc *sc = ic->ic_softc; 1678 1679 BWI_LOCK(sc); 1680 /* Enable MAC beacon promiscuity */ 1681 CSR_SETBITS_4(sc, BWI_MAC_STATUS, BWI_MAC_STATUS_PASS_BCN); 1682 BWI_UNLOCK(sc); 1683 } 1684 1685 static void 1686 bwi_getradiocaps(struct ieee80211com *ic, 1687 int maxchans, int *nchans, struct ieee80211_channel chans[]) 1688 { 1689 struct bwi_softc *sc = ic->ic_softc; 1690 struct bwi_mac *mac; 1691 struct bwi_phy *phy; 1692 uint8_t bands[IEEE80211_MODE_BYTES]; 1693 1694 /* 1695 * XXX First MAC is known to exist 1696 * TODO2 1697 */ 1698 mac = &sc->sc_mac[0]; 1699 phy = &mac->mac_phy; 1700 1701 memset(bands, 0, sizeof(bands)); 1702 switch (phy->phy_mode) { 1703 case IEEE80211_MODE_11G: 1704 setbit(bands, IEEE80211_MODE_11G); 1705 /* FALLTHROUGH */ 1706 case IEEE80211_MODE_11B: 1707 setbit(bands, IEEE80211_MODE_11B); 1708 break; 1709 case IEEE80211_MODE_11A: 1710 /* TODO:11A */ 1711 setbit(bands, IEEE80211_MODE_11A); 1712 device_printf(sc->sc_dev, "no 11a support\n"); 1713 return; 1714 default: 1715 panic("unknown phymode %d\n", phy->phy_mode); 1716 } 1717 1718 ieee80211_add_channels_default_2ghz(chans, maxchans, nchans, bands, 0); 1719 } 1720 1721 static void 1722 bwi_set_channel(struct ieee80211com *ic) 1723 { 1724 struct bwi_softc *sc = ic->ic_softc; 1725 struct ieee80211_channel *c = ic->ic_curchan; 1726 struct bwi_mac *mac; 1727 1728 BWI_LOCK(sc); 1729 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 1730 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 1731 mac = (struct bwi_mac *)sc->sc_cur_regwin; 1732 bwi_rf_set_chan(mac, ieee80211_chan2ieee(ic, c), 0); 1733 1734 sc->sc_rates = ieee80211_get_ratetable(c); 1735 BWI_UNLOCK(sc); 1736 } 1737 1738 static void 1739 bwi_scan_end(struct ieee80211com *ic) 1740 { 1741 struct bwi_softc *sc = ic->ic_softc; 1742 1743 BWI_LOCK(sc); 1744 CSR_CLRBITS_4(sc, BWI_MAC_STATUS, BWI_MAC_STATUS_PASS_BCN); 1745 BWI_UNLOCK(sc); 1746 } 1747 1748 static int 1749 bwi_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 1750 { 1751 struct bwi_vap *bvp = BWI_VAP(vap); 1752 struct ieee80211com *ic= vap->iv_ic; 1753 struct bwi_softc *sc = ic->ic_softc; 1754 enum ieee80211_state ostate = vap->iv_state; 1755 struct bwi_mac *mac; 1756 int error; 1757 1758 BWI_LOCK(sc); 1759 1760 callout_stop(&sc->sc_calib_ch); 1761 1762 if (nstate == IEEE80211_S_INIT) 1763 sc->sc_txpwrcb_type = BWI_TXPWR_INIT; 1764 1765 bwi_led_newstate(sc, nstate); 1766 1767 error = bvp->bv_newstate(vap, nstate, arg); 1768 if (error != 0) 1769 goto back; 1770 1771 /* 1772 * Clear the BSSID when we stop a STA 1773 */ 1774 if (vap->iv_opmode == IEEE80211_M_STA) { 1775 if (ostate == IEEE80211_S_RUN && nstate != IEEE80211_S_RUN) { 1776 /* 1777 * Clear out the BSSID. If we reassociate to 1778 * the same AP, this will reinialize things 1779 * correctly... 1780 */ 1781 if (ic->ic_opmode == IEEE80211_M_STA && 1782 !(sc->sc_flags & BWI_F_STOP)) 1783 bwi_set_bssid(sc, bwi_zero_addr); 1784 } 1785 } 1786 1787 if (vap->iv_opmode == IEEE80211_M_MONITOR) { 1788 /* Nothing to do */ 1789 } else if (nstate == IEEE80211_S_RUN) { 1790 bwi_set_bssid(sc, vap->iv_bss->ni_bssid); 1791 1792 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 1793 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 1794 mac = (struct bwi_mac *)sc->sc_cur_regwin; 1795 1796 /* Initial TX power calibration */ 1797 bwi_mac_calibrate_txpower(mac, BWI_TXPWR_INIT); 1798 #ifdef notyet 1799 sc->sc_txpwrcb_type = BWI_TXPWR_FORCE; 1800 #else 1801 sc->sc_txpwrcb_type = BWI_TXPWR_CALIB; 1802 #endif 1803 1804 callout_reset(&sc->sc_calib_ch, hz, bwi_calibrate, sc); 1805 } 1806 back: 1807 BWI_UNLOCK(sc); 1808 1809 return error; 1810 } 1811 1812 static int 1813 bwi_media_change(struct ifnet *ifp) 1814 { 1815 int error = ieee80211_media_change(ifp); 1816 /* NB: only the fixed rate can change and that doesn't need a reset */ 1817 return (error == ENETRESET ? 0 : error); 1818 } 1819 1820 static int 1821 bwi_dma_alloc(struct bwi_softc *sc) 1822 { 1823 int error, i, has_txstats; 1824 bus_addr_t lowaddr = 0; 1825 bus_size_t tx_ring_sz, rx_ring_sz, desc_sz = 0; 1826 uint32_t txrx_ctrl_step = 0; 1827 1828 has_txstats = 0; 1829 for (i = 0; i < sc->sc_nmac; ++i) { 1830 if (sc->sc_mac[i].mac_flags & BWI_MAC_F_HAS_TXSTATS) { 1831 has_txstats = 1; 1832 break; 1833 } 1834 } 1835 1836 switch (sc->sc_bus_space) { 1837 case BWI_BUS_SPACE_30BIT: 1838 case BWI_BUS_SPACE_32BIT: 1839 if (sc->sc_bus_space == BWI_BUS_SPACE_30BIT) 1840 lowaddr = BWI_BUS_SPACE_MAXADDR; 1841 else 1842 lowaddr = BUS_SPACE_MAXADDR_32BIT; 1843 desc_sz = sizeof(struct bwi_desc32); 1844 txrx_ctrl_step = 0x20; 1845 1846 sc->sc_init_tx_ring = bwi_init_tx_ring32; 1847 sc->sc_free_tx_ring = bwi_free_tx_ring32; 1848 sc->sc_init_rx_ring = bwi_init_rx_ring32; 1849 sc->sc_free_rx_ring = bwi_free_rx_ring32; 1850 sc->sc_setup_rxdesc = bwi_setup_rx_desc32; 1851 sc->sc_setup_txdesc = bwi_setup_tx_desc32; 1852 sc->sc_rxeof = bwi_rxeof32; 1853 sc->sc_start_tx = bwi_start_tx32; 1854 if (has_txstats) { 1855 sc->sc_init_txstats = bwi_init_txstats32; 1856 sc->sc_free_txstats = bwi_free_txstats32; 1857 sc->sc_txeof_status = bwi_txeof_status32; 1858 } 1859 break; 1860 1861 case BWI_BUS_SPACE_64BIT: 1862 lowaddr = BUS_SPACE_MAXADDR; /* XXX */ 1863 desc_sz = sizeof(struct bwi_desc64); 1864 txrx_ctrl_step = 0x40; 1865 1866 sc->sc_init_tx_ring = bwi_init_tx_ring64; 1867 sc->sc_free_tx_ring = bwi_free_tx_ring64; 1868 sc->sc_init_rx_ring = bwi_init_rx_ring64; 1869 sc->sc_free_rx_ring = bwi_free_rx_ring64; 1870 sc->sc_setup_rxdesc = bwi_setup_rx_desc64; 1871 sc->sc_setup_txdesc = bwi_setup_tx_desc64; 1872 sc->sc_rxeof = bwi_rxeof64; 1873 sc->sc_start_tx = bwi_start_tx64; 1874 if (has_txstats) { 1875 sc->sc_init_txstats = bwi_init_txstats64; 1876 sc->sc_free_txstats = bwi_free_txstats64; 1877 sc->sc_txeof_status = bwi_txeof_status64; 1878 } 1879 break; 1880 } 1881 1882 KASSERT(lowaddr != 0, ("lowaddr zero")); 1883 KASSERT(desc_sz != 0, ("desc_sz zero")); 1884 KASSERT(txrx_ctrl_step != 0, ("txrx_ctrl_step zero")); 1885 1886 tx_ring_sz = roundup(desc_sz * BWI_TX_NDESC, BWI_RING_ALIGN); 1887 rx_ring_sz = roundup(desc_sz * BWI_RX_NDESC, BWI_RING_ALIGN); 1888 1889 /* 1890 * Create top level DMA tag 1891 */ 1892 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), /* parent */ 1893 BWI_ALIGN, 0, /* alignment, bounds */ 1894 lowaddr, /* lowaddr */ 1895 BUS_SPACE_MAXADDR, /* highaddr */ 1896 NULL, NULL, /* filter, filterarg */ 1897 BUS_SPACE_MAXSIZE, /* maxsize */ 1898 BUS_SPACE_UNRESTRICTED, /* nsegments */ 1899 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1900 0, /* flags */ 1901 NULL, NULL, /* lockfunc, lockarg */ 1902 &sc->sc_parent_dtag); 1903 if (error) { 1904 device_printf(sc->sc_dev, "can't create parent DMA tag\n"); 1905 return error; 1906 } 1907 1908 #define TXRX_CTRL(idx) (BWI_TXRX_CTRL_BASE + (idx) * txrx_ctrl_step) 1909 1910 /* 1911 * Create TX ring DMA stuffs 1912 */ 1913 error = bus_dma_tag_create(sc->sc_parent_dtag, 1914 BWI_RING_ALIGN, 0, 1915 BUS_SPACE_MAXADDR, 1916 BUS_SPACE_MAXADDR, 1917 NULL, NULL, 1918 tx_ring_sz, 1919 1, 1920 tx_ring_sz, 1921 0, 1922 NULL, NULL, 1923 &sc->sc_txring_dtag); 1924 if (error) { 1925 device_printf(sc->sc_dev, "can't create TX ring DMA tag\n"); 1926 return error; 1927 } 1928 1929 for (i = 0; i < BWI_TX_NRING; ++i) { 1930 error = bwi_dma_ring_alloc(sc, sc->sc_txring_dtag, 1931 &sc->sc_tx_rdata[i], tx_ring_sz, 1932 TXRX_CTRL(i)); 1933 if (error) { 1934 device_printf(sc->sc_dev, "%dth TX ring " 1935 "DMA alloc failed\n", i); 1936 return error; 1937 } 1938 } 1939 1940 /* 1941 * Create RX ring DMA stuffs 1942 */ 1943 error = bus_dma_tag_create(sc->sc_parent_dtag, 1944 BWI_RING_ALIGN, 0, 1945 BUS_SPACE_MAXADDR, 1946 BUS_SPACE_MAXADDR, 1947 NULL, NULL, 1948 rx_ring_sz, 1949 1, 1950 rx_ring_sz, 1951 0, 1952 NULL, NULL, 1953 &sc->sc_rxring_dtag); 1954 if (error) { 1955 device_printf(sc->sc_dev, "can't create RX ring DMA tag\n"); 1956 return error; 1957 } 1958 1959 error = bwi_dma_ring_alloc(sc, sc->sc_rxring_dtag, &sc->sc_rx_rdata, 1960 rx_ring_sz, TXRX_CTRL(0)); 1961 if (error) { 1962 device_printf(sc->sc_dev, "RX ring DMA alloc failed\n"); 1963 return error; 1964 } 1965 1966 if (has_txstats) { 1967 error = bwi_dma_txstats_alloc(sc, TXRX_CTRL(3), desc_sz); 1968 if (error) { 1969 device_printf(sc->sc_dev, 1970 "TX stats DMA alloc failed\n"); 1971 return error; 1972 } 1973 } 1974 1975 #undef TXRX_CTRL 1976 1977 return bwi_dma_mbuf_create(sc); 1978 } 1979 1980 static void 1981 bwi_dma_free(struct bwi_softc *sc) 1982 { 1983 if (sc->sc_txring_dtag != NULL) { 1984 int i; 1985 1986 for (i = 0; i < BWI_TX_NRING; ++i) { 1987 struct bwi_ring_data *rd = &sc->sc_tx_rdata[i]; 1988 1989 if (rd->rdata_desc != NULL) { 1990 bus_dmamap_unload(sc->sc_txring_dtag, 1991 rd->rdata_dmap); 1992 bus_dmamem_free(sc->sc_txring_dtag, 1993 rd->rdata_desc, 1994 rd->rdata_dmap); 1995 } 1996 } 1997 bus_dma_tag_destroy(sc->sc_txring_dtag); 1998 } 1999 2000 if (sc->sc_rxring_dtag != NULL) { 2001 struct bwi_ring_data *rd = &sc->sc_rx_rdata; 2002 2003 if (rd->rdata_desc != NULL) { 2004 bus_dmamap_unload(sc->sc_rxring_dtag, rd->rdata_dmap); 2005 bus_dmamem_free(sc->sc_rxring_dtag, rd->rdata_desc, 2006 rd->rdata_dmap); 2007 } 2008 bus_dma_tag_destroy(sc->sc_rxring_dtag); 2009 } 2010 2011 bwi_dma_txstats_free(sc); 2012 bwi_dma_mbuf_destroy(sc, BWI_TX_NRING, 1); 2013 2014 if (sc->sc_parent_dtag != NULL) 2015 bus_dma_tag_destroy(sc->sc_parent_dtag); 2016 } 2017 2018 static int 2019 bwi_dma_ring_alloc(struct bwi_softc *sc, bus_dma_tag_t dtag, 2020 struct bwi_ring_data *rd, bus_size_t size, 2021 uint32_t txrx_ctrl) 2022 { 2023 int error; 2024 2025 error = bus_dmamem_alloc(dtag, &rd->rdata_desc, 2026 BUS_DMA_WAITOK | BUS_DMA_ZERO, 2027 &rd->rdata_dmap); 2028 if (error) { 2029 device_printf(sc->sc_dev, "can't allocate DMA mem\n"); 2030 return error; 2031 } 2032 2033 error = bus_dmamap_load(dtag, rd->rdata_dmap, rd->rdata_desc, size, 2034 bwi_dma_ring_addr, &rd->rdata_paddr, 2035 BUS_DMA_NOWAIT); 2036 if (error) { 2037 device_printf(sc->sc_dev, "can't load DMA mem\n"); 2038 bus_dmamem_free(dtag, rd->rdata_desc, rd->rdata_dmap); 2039 rd->rdata_desc = NULL; 2040 return error; 2041 } 2042 2043 rd->rdata_txrx_ctrl = txrx_ctrl; 2044 return 0; 2045 } 2046 2047 static int 2048 bwi_dma_txstats_alloc(struct bwi_softc *sc, uint32_t ctrl_base, 2049 bus_size_t desc_sz) 2050 { 2051 struct bwi_txstats_data *st; 2052 bus_size_t dma_size; 2053 int error; 2054 2055 st = malloc(sizeof(*st), M_DEVBUF, M_NOWAIT | M_ZERO); 2056 if (st == NULL) { 2057 device_printf(sc->sc_dev, "can't allocate txstats data\n"); 2058 return ENOMEM; 2059 } 2060 sc->sc_txstats = st; 2061 2062 /* 2063 * Create TX stats descriptor DMA stuffs 2064 */ 2065 dma_size = roundup(desc_sz * BWI_TXSTATS_NDESC, BWI_RING_ALIGN); 2066 2067 error = bus_dma_tag_create(sc->sc_parent_dtag, 2068 BWI_RING_ALIGN, 2069 0, 2070 BUS_SPACE_MAXADDR, 2071 BUS_SPACE_MAXADDR, 2072 NULL, NULL, 2073 dma_size, 2074 1, 2075 dma_size, 2076 0, 2077 NULL, NULL, 2078 &st->stats_ring_dtag); 2079 if (error) { 2080 device_printf(sc->sc_dev, "can't create txstats ring " 2081 "DMA tag\n"); 2082 return error; 2083 } 2084 2085 error = bus_dmamem_alloc(st->stats_ring_dtag, &st->stats_ring, 2086 BUS_DMA_WAITOK | BUS_DMA_ZERO, 2087 &st->stats_ring_dmap); 2088 if (error) { 2089 device_printf(sc->sc_dev, "can't allocate txstats ring " 2090 "DMA mem\n"); 2091 bus_dma_tag_destroy(st->stats_ring_dtag); 2092 st->stats_ring_dtag = NULL; 2093 return error; 2094 } 2095 2096 error = bus_dmamap_load(st->stats_ring_dtag, st->stats_ring_dmap, 2097 st->stats_ring, dma_size, 2098 bwi_dma_ring_addr, &st->stats_ring_paddr, 2099 BUS_DMA_NOWAIT); 2100 if (error) { 2101 device_printf(sc->sc_dev, "can't load txstats ring DMA mem\n"); 2102 bus_dmamem_free(st->stats_ring_dtag, st->stats_ring, 2103 st->stats_ring_dmap); 2104 bus_dma_tag_destroy(st->stats_ring_dtag); 2105 st->stats_ring_dtag = NULL; 2106 return error; 2107 } 2108 2109 /* 2110 * Create TX stats DMA stuffs 2111 */ 2112 dma_size = roundup(sizeof(struct bwi_txstats) * BWI_TXSTATS_NDESC, 2113 BWI_ALIGN); 2114 2115 error = bus_dma_tag_create(sc->sc_parent_dtag, 2116 BWI_ALIGN, 2117 0, 2118 BUS_SPACE_MAXADDR, 2119 BUS_SPACE_MAXADDR, 2120 NULL, NULL, 2121 dma_size, 2122 1, 2123 dma_size, 2124 0, 2125 NULL, NULL, 2126 &st->stats_dtag); 2127 if (error) { 2128 device_printf(sc->sc_dev, "can't create txstats DMA tag\n"); 2129 return error; 2130 } 2131 2132 error = bus_dmamem_alloc(st->stats_dtag, (void **)&st->stats, 2133 BUS_DMA_WAITOK | BUS_DMA_ZERO, 2134 &st->stats_dmap); 2135 if (error) { 2136 device_printf(sc->sc_dev, "can't allocate txstats DMA mem\n"); 2137 bus_dma_tag_destroy(st->stats_dtag); 2138 st->stats_dtag = NULL; 2139 return error; 2140 } 2141 2142 error = bus_dmamap_load(st->stats_dtag, st->stats_dmap, st->stats, 2143 dma_size, bwi_dma_ring_addr, &st->stats_paddr, 2144 BUS_DMA_NOWAIT); 2145 if (error) { 2146 device_printf(sc->sc_dev, "can't load txstats DMA mem\n"); 2147 bus_dmamem_free(st->stats_dtag, st->stats, st->stats_dmap); 2148 bus_dma_tag_destroy(st->stats_dtag); 2149 st->stats_dtag = NULL; 2150 return error; 2151 } 2152 2153 st->stats_ctrl_base = ctrl_base; 2154 return 0; 2155 } 2156 2157 static void 2158 bwi_dma_txstats_free(struct bwi_softc *sc) 2159 { 2160 struct bwi_txstats_data *st; 2161 2162 if (sc->sc_txstats == NULL) 2163 return; 2164 st = sc->sc_txstats; 2165 2166 if (st->stats_ring_dtag != NULL) { 2167 bus_dmamap_unload(st->stats_ring_dtag, st->stats_ring_dmap); 2168 bus_dmamem_free(st->stats_ring_dtag, st->stats_ring, 2169 st->stats_ring_dmap); 2170 bus_dma_tag_destroy(st->stats_ring_dtag); 2171 } 2172 2173 if (st->stats_dtag != NULL) { 2174 bus_dmamap_unload(st->stats_dtag, st->stats_dmap); 2175 bus_dmamem_free(st->stats_dtag, st->stats, st->stats_dmap); 2176 bus_dma_tag_destroy(st->stats_dtag); 2177 } 2178 2179 free(st, M_DEVBUF); 2180 } 2181 2182 static void 2183 bwi_dma_ring_addr(void *arg, bus_dma_segment_t *seg, int nseg, int error) 2184 { 2185 KASSERT(nseg == 1, ("too many segments\n")); 2186 *((bus_addr_t *)arg) = seg->ds_addr; 2187 } 2188 2189 static int 2190 bwi_dma_mbuf_create(struct bwi_softc *sc) 2191 { 2192 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata; 2193 int i, j, k, ntx, error; 2194 2195 /* 2196 * Create TX/RX mbuf DMA tag 2197 */ 2198 error = bus_dma_tag_create(sc->sc_parent_dtag, 2199 1, 2200 0, 2201 BUS_SPACE_MAXADDR, 2202 BUS_SPACE_MAXADDR, 2203 NULL, NULL, 2204 MCLBYTES, 2205 1, 2206 MCLBYTES, 2207 BUS_DMA_ALLOCNOW, 2208 NULL, NULL, 2209 &sc->sc_buf_dtag); 2210 if (error) { 2211 device_printf(sc->sc_dev, "can't create mbuf DMA tag\n"); 2212 return error; 2213 } 2214 2215 ntx = 0; 2216 2217 /* 2218 * Create TX mbuf DMA map 2219 */ 2220 for (i = 0; i < BWI_TX_NRING; ++i) { 2221 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[i]; 2222 2223 for (j = 0; j < BWI_TX_NDESC; ++j) { 2224 error = bus_dmamap_create(sc->sc_buf_dtag, 0, 2225 &tbd->tbd_buf[j].tb_dmap); 2226 if (error) { 2227 device_printf(sc->sc_dev, "can't create " 2228 "%dth tbd, %dth DMA map\n", i, j); 2229 2230 ntx = i; 2231 for (k = 0; k < j; ++k) { 2232 bus_dmamap_destroy(sc->sc_buf_dtag, 2233 tbd->tbd_buf[k].tb_dmap); 2234 } 2235 goto fail; 2236 } 2237 } 2238 } 2239 ntx = BWI_TX_NRING; 2240 2241 /* 2242 * Create RX mbuf DMA map and a spare DMA map 2243 */ 2244 error = bus_dmamap_create(sc->sc_buf_dtag, 0, 2245 &rbd->rbd_tmp_dmap); 2246 if (error) { 2247 device_printf(sc->sc_dev, 2248 "can't create spare RX buf DMA map\n"); 2249 goto fail; 2250 } 2251 2252 for (j = 0; j < BWI_RX_NDESC; ++j) { 2253 error = bus_dmamap_create(sc->sc_buf_dtag, 0, 2254 &rbd->rbd_buf[j].rb_dmap); 2255 if (error) { 2256 device_printf(sc->sc_dev, "can't create %dth " 2257 "RX buf DMA map\n", j); 2258 2259 for (k = 0; k < j; ++k) { 2260 bus_dmamap_destroy(sc->sc_buf_dtag, 2261 rbd->rbd_buf[j].rb_dmap); 2262 } 2263 bus_dmamap_destroy(sc->sc_buf_dtag, 2264 rbd->rbd_tmp_dmap); 2265 goto fail; 2266 } 2267 } 2268 2269 return 0; 2270 fail: 2271 bwi_dma_mbuf_destroy(sc, ntx, 0); 2272 return error; 2273 } 2274 2275 static void 2276 bwi_dma_mbuf_destroy(struct bwi_softc *sc, int ntx, int nrx) 2277 { 2278 int i, j; 2279 2280 if (sc->sc_buf_dtag == NULL) 2281 return; 2282 2283 for (i = 0; i < ntx; ++i) { 2284 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[i]; 2285 2286 for (j = 0; j < BWI_TX_NDESC; ++j) { 2287 struct bwi_txbuf *tb = &tbd->tbd_buf[j]; 2288 2289 if (tb->tb_mbuf != NULL) { 2290 bus_dmamap_unload(sc->sc_buf_dtag, 2291 tb->tb_dmap); 2292 m_freem(tb->tb_mbuf); 2293 } 2294 if (tb->tb_ni != NULL) 2295 ieee80211_free_node(tb->tb_ni); 2296 bus_dmamap_destroy(sc->sc_buf_dtag, tb->tb_dmap); 2297 } 2298 } 2299 2300 if (nrx) { 2301 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata; 2302 2303 bus_dmamap_destroy(sc->sc_buf_dtag, rbd->rbd_tmp_dmap); 2304 for (j = 0; j < BWI_RX_NDESC; ++j) { 2305 struct bwi_rxbuf *rb = &rbd->rbd_buf[j]; 2306 2307 if (rb->rb_mbuf != NULL) { 2308 bus_dmamap_unload(sc->sc_buf_dtag, 2309 rb->rb_dmap); 2310 m_freem(rb->rb_mbuf); 2311 } 2312 bus_dmamap_destroy(sc->sc_buf_dtag, rb->rb_dmap); 2313 } 2314 } 2315 2316 bus_dma_tag_destroy(sc->sc_buf_dtag); 2317 sc->sc_buf_dtag = NULL; 2318 } 2319 2320 static void 2321 bwi_enable_intrs(struct bwi_softc *sc, uint32_t enable_intrs) 2322 { 2323 CSR_SETBITS_4(sc, BWI_MAC_INTR_MASK, enable_intrs); 2324 } 2325 2326 static void 2327 bwi_disable_intrs(struct bwi_softc *sc, uint32_t disable_intrs) 2328 { 2329 CSR_CLRBITS_4(sc, BWI_MAC_INTR_MASK, disable_intrs); 2330 } 2331 2332 static int 2333 bwi_init_tx_ring32(struct bwi_softc *sc, int ring_idx) 2334 { 2335 struct bwi_ring_data *rd; 2336 struct bwi_txbuf_data *tbd; 2337 uint32_t val, addr_hi, addr_lo; 2338 2339 KASSERT(ring_idx < BWI_TX_NRING, ("ring_idx %d", ring_idx)); 2340 rd = &sc->sc_tx_rdata[ring_idx]; 2341 tbd = &sc->sc_tx_bdata[ring_idx]; 2342 2343 tbd->tbd_idx = 0; 2344 tbd->tbd_used = 0; 2345 2346 bzero(rd->rdata_desc, sizeof(struct bwi_desc32) * BWI_TX_NDESC); 2347 bus_dmamap_sync(sc->sc_txring_dtag, rd->rdata_dmap, 2348 BUS_DMASYNC_PREWRITE); 2349 2350 addr_lo = __SHIFTOUT(rd->rdata_paddr, BWI_TXRX32_RINGINFO_ADDR_MASK); 2351 addr_hi = __SHIFTOUT(rd->rdata_paddr, BWI_TXRX32_RINGINFO_FUNC_MASK); 2352 2353 val = __SHIFTIN(addr_lo, BWI_TXRX32_RINGINFO_ADDR_MASK) | 2354 __SHIFTIN(BWI_TXRX32_RINGINFO_FUNC_TXRX, 2355 BWI_TXRX32_RINGINFO_FUNC_MASK); 2356 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_RINGINFO, val); 2357 2358 val = __SHIFTIN(addr_hi, BWI_TXRX32_CTRL_ADDRHI_MASK) | 2359 BWI_TXRX32_CTRL_ENABLE; 2360 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_CTRL, val); 2361 2362 return 0; 2363 } 2364 2365 static void 2366 bwi_init_rxdesc_ring32(struct bwi_softc *sc, uint32_t ctrl_base, 2367 bus_addr_t paddr, int hdr_size, int ndesc) 2368 { 2369 uint32_t val, addr_hi, addr_lo; 2370 2371 addr_lo = __SHIFTOUT(paddr, BWI_TXRX32_RINGINFO_ADDR_MASK); 2372 addr_hi = __SHIFTOUT(paddr, BWI_TXRX32_RINGINFO_FUNC_MASK); 2373 2374 val = __SHIFTIN(addr_lo, BWI_TXRX32_RINGINFO_ADDR_MASK) | 2375 __SHIFTIN(BWI_TXRX32_RINGINFO_FUNC_TXRX, 2376 BWI_TXRX32_RINGINFO_FUNC_MASK); 2377 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_RINGINFO, val); 2378 2379 val = __SHIFTIN(hdr_size, BWI_RX32_CTRL_HDRSZ_MASK) | 2380 __SHIFTIN(addr_hi, BWI_TXRX32_CTRL_ADDRHI_MASK) | 2381 BWI_TXRX32_CTRL_ENABLE; 2382 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_CTRL, val); 2383 2384 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_INDEX, 2385 (ndesc - 1) * sizeof(struct bwi_desc32)); 2386 } 2387 2388 static int 2389 bwi_init_rx_ring32(struct bwi_softc *sc) 2390 { 2391 struct bwi_ring_data *rd = &sc->sc_rx_rdata; 2392 int i, error; 2393 2394 sc->sc_rx_bdata.rbd_idx = 0; 2395 2396 for (i = 0; i < BWI_RX_NDESC; ++i) { 2397 error = bwi_newbuf(sc, i, 1); 2398 if (error) { 2399 device_printf(sc->sc_dev, 2400 "can't allocate %dth RX buffer\n", i); 2401 return error; 2402 } 2403 } 2404 bus_dmamap_sync(sc->sc_rxring_dtag, rd->rdata_dmap, 2405 BUS_DMASYNC_PREWRITE); 2406 2407 bwi_init_rxdesc_ring32(sc, rd->rdata_txrx_ctrl, rd->rdata_paddr, 2408 sizeof(struct bwi_rxbuf_hdr), BWI_RX_NDESC); 2409 return 0; 2410 } 2411 2412 static int 2413 bwi_init_txstats32(struct bwi_softc *sc) 2414 { 2415 struct bwi_txstats_data *st = sc->sc_txstats; 2416 bus_addr_t stats_paddr; 2417 int i; 2418 2419 bzero(st->stats, BWI_TXSTATS_NDESC * sizeof(struct bwi_txstats)); 2420 bus_dmamap_sync(st->stats_dtag, st->stats_dmap, BUS_DMASYNC_PREWRITE); 2421 2422 st->stats_idx = 0; 2423 2424 stats_paddr = st->stats_paddr; 2425 for (i = 0; i < BWI_TXSTATS_NDESC; ++i) { 2426 bwi_setup_desc32(sc, st->stats_ring, BWI_TXSTATS_NDESC, i, 2427 stats_paddr, sizeof(struct bwi_txstats), 0); 2428 stats_paddr += sizeof(struct bwi_txstats); 2429 } 2430 bus_dmamap_sync(st->stats_ring_dtag, st->stats_ring_dmap, 2431 BUS_DMASYNC_PREWRITE); 2432 2433 bwi_init_rxdesc_ring32(sc, st->stats_ctrl_base, 2434 st->stats_ring_paddr, 0, BWI_TXSTATS_NDESC); 2435 return 0; 2436 } 2437 2438 static void 2439 bwi_setup_rx_desc32(struct bwi_softc *sc, int buf_idx, bus_addr_t paddr, 2440 int buf_len) 2441 { 2442 struct bwi_ring_data *rd = &sc->sc_rx_rdata; 2443 2444 KASSERT(buf_idx < BWI_RX_NDESC, ("buf_idx %d", buf_idx)); 2445 bwi_setup_desc32(sc, rd->rdata_desc, BWI_RX_NDESC, buf_idx, 2446 paddr, buf_len, 0); 2447 } 2448 2449 static void 2450 bwi_setup_tx_desc32(struct bwi_softc *sc, struct bwi_ring_data *rd, 2451 int buf_idx, bus_addr_t paddr, int buf_len) 2452 { 2453 KASSERT(buf_idx < BWI_TX_NDESC, ("buf_idx %d", buf_idx)); 2454 bwi_setup_desc32(sc, rd->rdata_desc, BWI_TX_NDESC, buf_idx, 2455 paddr, buf_len, 1); 2456 } 2457 2458 static int 2459 bwi_init_tx_ring64(struct bwi_softc *sc, int ring_idx) 2460 { 2461 /* TODO:64 */ 2462 return EOPNOTSUPP; 2463 } 2464 2465 static int 2466 bwi_init_rx_ring64(struct bwi_softc *sc) 2467 { 2468 /* TODO:64 */ 2469 return EOPNOTSUPP; 2470 } 2471 2472 static int 2473 bwi_init_txstats64(struct bwi_softc *sc) 2474 { 2475 /* TODO:64 */ 2476 return EOPNOTSUPP; 2477 } 2478 2479 static void 2480 bwi_setup_rx_desc64(struct bwi_softc *sc, int buf_idx, bus_addr_t paddr, 2481 int buf_len) 2482 { 2483 /* TODO:64 */ 2484 } 2485 2486 static void 2487 bwi_setup_tx_desc64(struct bwi_softc *sc, struct bwi_ring_data *rd, 2488 int buf_idx, bus_addr_t paddr, int buf_len) 2489 { 2490 /* TODO:64 */ 2491 } 2492 2493 static void 2494 bwi_dma_buf_addr(void *arg, bus_dma_segment_t *seg, int nseg, 2495 bus_size_t mapsz __unused, int error) 2496 { 2497 if (!error) { 2498 KASSERT(nseg == 1, ("too many segments(%d)\n", nseg)); 2499 *((bus_addr_t *)arg) = seg->ds_addr; 2500 } 2501 } 2502 2503 static int 2504 bwi_newbuf(struct bwi_softc *sc, int buf_idx, int init) 2505 { 2506 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata; 2507 struct bwi_rxbuf *rxbuf = &rbd->rbd_buf[buf_idx]; 2508 struct bwi_rxbuf_hdr *hdr; 2509 bus_dmamap_t map; 2510 bus_addr_t paddr; 2511 struct mbuf *m; 2512 int error; 2513 2514 KASSERT(buf_idx < BWI_RX_NDESC, ("buf_idx %d", buf_idx)); 2515 2516 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 2517 if (m == NULL) { 2518 error = ENOBUFS; 2519 2520 /* 2521 * If the NIC is up and running, we need to: 2522 * - Clear RX buffer's header. 2523 * - Restore RX descriptor settings. 2524 */ 2525 if (init) 2526 return error; 2527 else 2528 goto back; 2529 } 2530 m->m_len = m->m_pkthdr.len = MCLBYTES; 2531 2532 /* 2533 * Try to load RX buf into temporary DMA map 2534 */ 2535 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, rbd->rbd_tmp_dmap, m, 2536 bwi_dma_buf_addr, &paddr, BUS_DMA_NOWAIT); 2537 if (error) { 2538 m_freem(m); 2539 2540 /* 2541 * See the comment above 2542 */ 2543 if (init) 2544 return error; 2545 else 2546 goto back; 2547 } 2548 2549 if (!init) 2550 bus_dmamap_unload(sc->sc_buf_dtag, rxbuf->rb_dmap); 2551 rxbuf->rb_mbuf = m; 2552 rxbuf->rb_paddr = paddr; 2553 2554 /* 2555 * Swap RX buf's DMA map with the loaded temporary one 2556 */ 2557 map = rxbuf->rb_dmap; 2558 rxbuf->rb_dmap = rbd->rbd_tmp_dmap; 2559 rbd->rbd_tmp_dmap = map; 2560 2561 back: 2562 /* 2563 * Clear RX buf header 2564 */ 2565 hdr = mtod(rxbuf->rb_mbuf, struct bwi_rxbuf_hdr *); 2566 bzero(hdr, sizeof(*hdr)); 2567 bus_dmamap_sync(sc->sc_buf_dtag, rxbuf->rb_dmap, BUS_DMASYNC_PREWRITE); 2568 2569 /* 2570 * Setup RX buf descriptor 2571 */ 2572 sc->sc_setup_rxdesc(sc, buf_idx, rxbuf->rb_paddr, 2573 rxbuf->rb_mbuf->m_len - sizeof(*hdr)); 2574 return error; 2575 } 2576 2577 static void 2578 bwi_set_addr_filter(struct bwi_softc *sc, uint16_t addr_ofs, 2579 const uint8_t *addr) 2580 { 2581 int i; 2582 2583 CSR_WRITE_2(sc, BWI_ADDR_FILTER_CTRL, 2584 BWI_ADDR_FILTER_CTRL_SET | addr_ofs); 2585 2586 for (i = 0; i < (IEEE80211_ADDR_LEN / 2); ++i) { 2587 uint16_t addr_val; 2588 2589 addr_val = (uint16_t)addr[i * 2] | 2590 (((uint16_t)addr[(i * 2) + 1]) << 8); 2591 CSR_WRITE_2(sc, BWI_ADDR_FILTER_DATA, addr_val); 2592 } 2593 } 2594 2595 static int 2596 bwi_rxeof(struct bwi_softc *sc, int end_idx) 2597 { 2598 struct bwi_ring_data *rd = &sc->sc_rx_rdata; 2599 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata; 2600 struct ieee80211com *ic = &sc->sc_ic; 2601 int idx, rx_data = 0; 2602 2603 idx = rbd->rbd_idx; 2604 while (idx != end_idx) { 2605 struct bwi_rxbuf *rb = &rbd->rbd_buf[idx]; 2606 struct bwi_rxbuf_hdr *hdr; 2607 struct ieee80211_frame_min *wh; 2608 struct ieee80211_node *ni; 2609 struct mbuf *m; 2610 uint32_t plcp; 2611 uint16_t flags2; 2612 int buflen, wh_ofs, hdr_extra, rssi, noise, type, rate; 2613 2614 m = rb->rb_mbuf; 2615 bus_dmamap_sync(sc->sc_buf_dtag, rb->rb_dmap, 2616 BUS_DMASYNC_POSTREAD); 2617 2618 if (bwi_newbuf(sc, idx, 0)) { 2619 counter_u64_add(ic->ic_ierrors, 1); 2620 goto next; 2621 } 2622 2623 hdr = mtod(m, struct bwi_rxbuf_hdr *); 2624 flags2 = le16toh(hdr->rxh_flags2); 2625 2626 hdr_extra = 0; 2627 if (flags2 & BWI_RXH_F2_TYPE2FRAME) 2628 hdr_extra = 2; 2629 wh_ofs = hdr_extra + 6; /* XXX magic number */ 2630 2631 buflen = le16toh(hdr->rxh_buflen); 2632 if (buflen < BWI_FRAME_MIN_LEN(wh_ofs)) { 2633 device_printf(sc->sc_dev, 2634 "%s: zero length data, hdr_extra %d\n", 2635 __func__, hdr_extra); 2636 counter_u64_add(ic->ic_ierrors, 1); 2637 m_freem(m); 2638 goto next; 2639 } 2640 2641 bcopy((uint8_t *)(hdr + 1) + hdr_extra, &plcp, sizeof(plcp)); 2642 rssi = bwi_calc_rssi(sc, hdr); 2643 noise = bwi_calc_noise(sc); 2644 2645 m->m_len = m->m_pkthdr.len = buflen + sizeof(*hdr); 2646 m_adj(m, sizeof(*hdr) + wh_ofs); 2647 2648 if (htole16(hdr->rxh_flags1) & BWI_RXH_F1_OFDM) 2649 rate = bwi_plcp2rate(plcp, IEEE80211_T_OFDM); 2650 else 2651 rate = bwi_plcp2rate(plcp, IEEE80211_T_CCK); 2652 2653 /* RX radio tap */ 2654 if (ieee80211_radiotap_active(ic)) 2655 bwi_rx_radiotap(sc, m, hdr, &plcp, rate, rssi, noise); 2656 2657 m_adj(m, -IEEE80211_CRC_LEN); 2658 2659 BWI_UNLOCK(sc); 2660 2661 wh = mtod(m, struct ieee80211_frame_min *); 2662 ni = ieee80211_find_rxnode(ic, wh); 2663 if (ni != NULL) { 2664 type = ieee80211_input(ni, m, rssi - noise, noise); 2665 ieee80211_free_node(ni); 2666 } else 2667 type = ieee80211_input_all(ic, m, rssi - noise, noise); 2668 if (type == IEEE80211_FC0_TYPE_DATA) { 2669 rx_data = 1; 2670 sc->sc_rx_rate = rate; 2671 } 2672 2673 BWI_LOCK(sc); 2674 next: 2675 idx = (idx + 1) % BWI_RX_NDESC; 2676 2677 if (sc->sc_flags & BWI_F_STOP) { 2678 /* 2679 * Take the fast lane, don't do 2680 * any damage to softc 2681 */ 2682 return -1; 2683 } 2684 } 2685 2686 rbd->rbd_idx = idx; 2687 bus_dmamap_sync(sc->sc_rxring_dtag, rd->rdata_dmap, 2688 BUS_DMASYNC_PREWRITE); 2689 2690 return rx_data; 2691 } 2692 2693 static int 2694 bwi_rxeof32(struct bwi_softc *sc) 2695 { 2696 uint32_t val, rx_ctrl; 2697 int end_idx, rx_data; 2698 2699 rx_ctrl = sc->sc_rx_rdata.rdata_txrx_ctrl; 2700 2701 val = CSR_READ_4(sc, rx_ctrl + BWI_RX32_STATUS); 2702 end_idx = __SHIFTOUT(val, BWI_RX32_STATUS_INDEX_MASK) / 2703 sizeof(struct bwi_desc32); 2704 2705 rx_data = bwi_rxeof(sc, end_idx); 2706 if (rx_data >= 0) { 2707 CSR_WRITE_4(sc, rx_ctrl + BWI_RX32_INDEX, 2708 end_idx * sizeof(struct bwi_desc32)); 2709 } 2710 return rx_data; 2711 } 2712 2713 static int 2714 bwi_rxeof64(struct bwi_softc *sc) 2715 { 2716 /* TODO:64 */ 2717 return 0; 2718 } 2719 2720 static void 2721 bwi_reset_rx_ring32(struct bwi_softc *sc, uint32_t rx_ctrl) 2722 { 2723 int i; 2724 2725 CSR_WRITE_4(sc, rx_ctrl + BWI_RX32_CTRL, 0); 2726 2727 #define NRETRY 10 2728 2729 for (i = 0; i < NRETRY; ++i) { 2730 uint32_t status; 2731 2732 status = CSR_READ_4(sc, rx_ctrl + BWI_RX32_STATUS); 2733 if (__SHIFTOUT(status, BWI_RX32_STATUS_STATE_MASK) == 2734 BWI_RX32_STATUS_STATE_DISABLED) 2735 break; 2736 2737 DELAY(1000); 2738 } 2739 if (i == NRETRY) 2740 device_printf(sc->sc_dev, "reset rx ring timedout\n"); 2741 2742 #undef NRETRY 2743 2744 CSR_WRITE_4(sc, rx_ctrl + BWI_RX32_RINGINFO, 0); 2745 } 2746 2747 static void 2748 bwi_free_txstats32(struct bwi_softc *sc) 2749 { 2750 bwi_reset_rx_ring32(sc, sc->sc_txstats->stats_ctrl_base); 2751 } 2752 2753 static void 2754 bwi_free_rx_ring32(struct bwi_softc *sc) 2755 { 2756 struct bwi_ring_data *rd = &sc->sc_rx_rdata; 2757 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata; 2758 int i; 2759 2760 bwi_reset_rx_ring32(sc, rd->rdata_txrx_ctrl); 2761 2762 for (i = 0; i < BWI_RX_NDESC; ++i) { 2763 struct bwi_rxbuf *rb = &rbd->rbd_buf[i]; 2764 2765 if (rb->rb_mbuf != NULL) { 2766 bus_dmamap_unload(sc->sc_buf_dtag, rb->rb_dmap); 2767 m_freem(rb->rb_mbuf); 2768 rb->rb_mbuf = NULL; 2769 } 2770 } 2771 } 2772 2773 static void 2774 bwi_free_tx_ring32(struct bwi_softc *sc, int ring_idx) 2775 { 2776 struct bwi_ring_data *rd; 2777 struct bwi_txbuf_data *tbd; 2778 uint32_t state, val; 2779 int i; 2780 2781 KASSERT(ring_idx < BWI_TX_NRING, ("ring_idx %d", ring_idx)); 2782 rd = &sc->sc_tx_rdata[ring_idx]; 2783 tbd = &sc->sc_tx_bdata[ring_idx]; 2784 2785 #define NRETRY 10 2786 2787 for (i = 0; i < NRETRY; ++i) { 2788 val = CSR_READ_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_STATUS); 2789 state = __SHIFTOUT(val, BWI_TX32_STATUS_STATE_MASK); 2790 if (state == BWI_TX32_STATUS_STATE_DISABLED || 2791 state == BWI_TX32_STATUS_STATE_IDLE || 2792 state == BWI_TX32_STATUS_STATE_STOPPED) 2793 break; 2794 2795 DELAY(1000); 2796 } 2797 if (i == NRETRY) { 2798 device_printf(sc->sc_dev, 2799 "%s: wait for TX ring(%d) stable timed out\n", 2800 __func__, ring_idx); 2801 } 2802 2803 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_CTRL, 0); 2804 for (i = 0; i < NRETRY; ++i) { 2805 val = CSR_READ_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_STATUS); 2806 state = __SHIFTOUT(val, BWI_TX32_STATUS_STATE_MASK); 2807 if (state == BWI_TX32_STATUS_STATE_DISABLED) 2808 break; 2809 2810 DELAY(1000); 2811 } 2812 if (i == NRETRY) 2813 device_printf(sc->sc_dev, "%s: reset TX ring (%d) timed out\n", 2814 __func__, ring_idx); 2815 2816 #undef NRETRY 2817 2818 DELAY(1000); 2819 2820 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_RINGINFO, 0); 2821 2822 for (i = 0; i < BWI_TX_NDESC; ++i) { 2823 struct bwi_txbuf *tb = &tbd->tbd_buf[i]; 2824 2825 if (tb->tb_mbuf != NULL) { 2826 bus_dmamap_unload(sc->sc_buf_dtag, tb->tb_dmap); 2827 m_freem(tb->tb_mbuf); 2828 tb->tb_mbuf = NULL; 2829 } 2830 if (tb->tb_ni != NULL) { 2831 ieee80211_free_node(tb->tb_ni); 2832 tb->tb_ni = NULL; 2833 } 2834 } 2835 } 2836 2837 static void 2838 bwi_free_txstats64(struct bwi_softc *sc) 2839 { 2840 /* TODO:64 */ 2841 } 2842 2843 static void 2844 bwi_free_rx_ring64(struct bwi_softc *sc) 2845 { 2846 /* TODO:64 */ 2847 } 2848 2849 static void 2850 bwi_free_tx_ring64(struct bwi_softc *sc, int ring_idx) 2851 { 2852 /* TODO:64 */ 2853 } 2854 2855 /* XXX does not belong here */ 2856 #define IEEE80211_OFDM_PLCP_RATE_MASK __BITS(3, 0) 2857 #define IEEE80211_OFDM_PLCP_LEN_MASK __BITS(16, 5) 2858 2859 static __inline void 2860 bwi_ofdm_plcp_header(uint32_t *plcp0, int pkt_len, uint8_t rate) 2861 { 2862 uint32_t plcp; 2863 2864 plcp = __SHIFTIN(ieee80211_rate2plcp(rate, IEEE80211_T_OFDM), 2865 IEEE80211_OFDM_PLCP_RATE_MASK) | 2866 __SHIFTIN(pkt_len, IEEE80211_OFDM_PLCP_LEN_MASK); 2867 *plcp0 = htole32(plcp); 2868 } 2869 2870 static __inline void 2871 bwi_ds_plcp_header(struct ieee80211_ds_plcp_hdr *plcp, int pkt_len, 2872 uint8_t rate) 2873 { 2874 int len, service, pkt_bitlen; 2875 2876 pkt_bitlen = pkt_len * NBBY; 2877 len = howmany(pkt_bitlen * 2, rate); 2878 2879 service = IEEE80211_PLCP_SERVICE_LOCKED; 2880 if (rate == (11 * 2)) { 2881 int pkt_bitlen1; 2882 2883 /* 2884 * PLCP service field needs to be adjusted, 2885 * if TX rate is 11Mbytes/s 2886 */ 2887 pkt_bitlen1 = len * 11; 2888 if (pkt_bitlen1 - pkt_bitlen >= NBBY) 2889 service |= IEEE80211_PLCP_SERVICE_LENEXT7; 2890 } 2891 2892 plcp->i_signal = ieee80211_rate2plcp(rate, IEEE80211_T_CCK); 2893 plcp->i_service = service; 2894 plcp->i_length = htole16(len); 2895 /* NOTE: do NOT touch i_crc */ 2896 } 2897 2898 static __inline void 2899 bwi_plcp_header(const struct ieee80211_rate_table *rt, 2900 void *plcp, int pkt_len, uint8_t rate) 2901 { 2902 enum ieee80211_phytype modtype; 2903 2904 /* 2905 * Assume caller has zeroed 'plcp' 2906 */ 2907 modtype = ieee80211_rate2phytype(rt, rate); 2908 if (modtype == IEEE80211_T_OFDM) 2909 bwi_ofdm_plcp_header(plcp, pkt_len, rate); 2910 else if (modtype == IEEE80211_T_DS) 2911 bwi_ds_plcp_header(plcp, pkt_len, rate); 2912 else 2913 panic("unsupport modulation type %u\n", modtype); 2914 } 2915 2916 static int 2917 bwi_encap(struct bwi_softc *sc, int idx, struct mbuf *m, 2918 struct ieee80211_node *ni) 2919 { 2920 struct ieee80211vap *vap = ni->ni_vap; 2921 struct ieee80211com *ic = &sc->sc_ic; 2922 struct bwi_ring_data *rd = &sc->sc_tx_rdata[BWI_TX_DATA_RING]; 2923 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING]; 2924 struct bwi_txbuf *tb = &tbd->tbd_buf[idx]; 2925 struct bwi_mac *mac; 2926 struct bwi_txbuf_hdr *hdr; 2927 struct ieee80211_frame *wh; 2928 const struct ieee80211_txparam *tp = ni->ni_txparms; 2929 uint8_t rate, rate_fb; 2930 uint32_t mac_ctrl; 2931 uint16_t phy_ctrl; 2932 bus_addr_t paddr; 2933 int type, ismcast, pkt_len, error, rix; 2934 #if 0 2935 const uint8_t *p; 2936 int i; 2937 #endif 2938 2939 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 2940 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 2941 mac = (struct bwi_mac *)sc->sc_cur_regwin; 2942 2943 wh = mtod(m, struct ieee80211_frame *); 2944 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2945 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 2946 2947 /* Get 802.11 frame len before prepending TX header */ 2948 pkt_len = m->m_pkthdr.len + IEEE80211_CRC_LEN; 2949 2950 /* 2951 * Find TX rate 2952 */ 2953 if (type != IEEE80211_FC0_TYPE_DATA || (m->m_flags & M_EAPOL)) { 2954 rate = rate_fb = tp->mgmtrate; 2955 } else if (ismcast) { 2956 rate = rate_fb = tp->mcastrate; 2957 } else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) { 2958 rate = rate_fb = tp->ucastrate; 2959 } else { 2960 rix = ieee80211_ratectl_rate(ni, NULL, pkt_len); 2961 rate = ni->ni_txrate; 2962 2963 if (rix > 0) { 2964 rate_fb = ni->ni_rates.rs_rates[rix-1] & 2965 IEEE80211_RATE_VAL; 2966 } else { 2967 rate_fb = rate; 2968 } 2969 } 2970 tb->tb_rate[0] = rate; 2971 tb->tb_rate[1] = rate_fb; 2972 sc->sc_tx_rate = rate; 2973 2974 /* 2975 * TX radio tap 2976 */ 2977 if (ieee80211_radiotap_active_vap(vap)) { 2978 sc->sc_tx_th.wt_flags = 0; 2979 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) 2980 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP; 2981 if (ieee80211_rate2phytype(sc->sc_rates, rate) == IEEE80211_T_DS && 2982 (ic->ic_flags & IEEE80211_F_SHPREAMBLE) && 2983 rate != (1 * 2)) { 2984 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 2985 } 2986 sc->sc_tx_th.wt_rate = rate; 2987 2988 ieee80211_radiotap_tx(vap, m); 2989 } 2990 2991 /* 2992 * Setup the embedded TX header 2993 */ 2994 M_PREPEND(m, sizeof(*hdr), M_NOWAIT); 2995 if (m == NULL) { 2996 device_printf(sc->sc_dev, "%s: prepend TX header failed\n", 2997 __func__); 2998 return ENOBUFS; 2999 } 3000 hdr = mtod(m, struct bwi_txbuf_hdr *); 3001 3002 bzero(hdr, sizeof(*hdr)); 3003 3004 bcopy(wh->i_fc, hdr->txh_fc, sizeof(hdr->txh_fc)); 3005 bcopy(wh->i_addr1, hdr->txh_addr1, sizeof(hdr->txh_addr1)); 3006 3007 if (!ismcast) { 3008 uint16_t dur; 3009 3010 dur = ieee80211_ack_duration(sc->sc_rates, rate, 3011 ic->ic_flags & ~IEEE80211_F_SHPREAMBLE); 3012 3013 hdr->txh_fb_duration = htole16(dur); 3014 } 3015 3016 hdr->txh_id = __SHIFTIN(BWI_TX_DATA_RING, BWI_TXH_ID_RING_MASK) | 3017 __SHIFTIN(idx, BWI_TXH_ID_IDX_MASK); 3018 3019 bwi_plcp_header(sc->sc_rates, hdr->txh_plcp, pkt_len, rate); 3020 bwi_plcp_header(sc->sc_rates, hdr->txh_fb_plcp, pkt_len, rate_fb); 3021 3022 phy_ctrl = __SHIFTIN(mac->mac_rf.rf_ant_mode, 3023 BWI_TXH_PHY_C_ANTMODE_MASK); 3024 if (ieee80211_rate2phytype(sc->sc_rates, rate) == IEEE80211_T_OFDM) 3025 phy_ctrl |= BWI_TXH_PHY_C_OFDM; 3026 else if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && rate != (2 * 1)) 3027 phy_ctrl |= BWI_TXH_PHY_C_SHPREAMBLE; 3028 3029 mac_ctrl = BWI_TXH_MAC_C_HWSEQ | BWI_TXH_MAC_C_FIRST_FRAG; 3030 if (!ismcast) 3031 mac_ctrl |= BWI_TXH_MAC_C_ACK; 3032 if (ieee80211_rate2phytype(sc->sc_rates, rate_fb) == IEEE80211_T_OFDM) 3033 mac_ctrl |= BWI_TXH_MAC_C_FB_OFDM; 3034 3035 hdr->txh_mac_ctrl = htole32(mac_ctrl); 3036 hdr->txh_phy_ctrl = htole16(phy_ctrl); 3037 3038 /* Catch any further usage */ 3039 hdr = NULL; 3040 wh = NULL; 3041 3042 /* DMA load */ 3043 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m, 3044 bwi_dma_buf_addr, &paddr, BUS_DMA_NOWAIT); 3045 if (error && error != EFBIG) { 3046 device_printf(sc->sc_dev, "%s: can't load TX buffer (1) %d\n", 3047 __func__, error); 3048 goto back; 3049 } 3050 3051 if (error) { /* error == EFBIG */ 3052 struct mbuf *m_new; 3053 3054 m_new = m_defrag(m, M_NOWAIT); 3055 if (m_new == NULL) { 3056 device_printf(sc->sc_dev, 3057 "%s: can't defrag TX buffer\n", __func__); 3058 error = ENOBUFS; 3059 goto back; 3060 } else { 3061 m = m_new; 3062 } 3063 3064 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m, 3065 bwi_dma_buf_addr, &paddr, 3066 BUS_DMA_NOWAIT); 3067 if (error) { 3068 device_printf(sc->sc_dev, 3069 "%s: can't load TX buffer (2) %d\n", 3070 __func__, error); 3071 goto back; 3072 } 3073 } 3074 error = 0; 3075 3076 bus_dmamap_sync(sc->sc_buf_dtag, tb->tb_dmap, BUS_DMASYNC_PREWRITE); 3077 3078 tb->tb_mbuf = m; 3079 tb->tb_ni = ni; 3080 3081 #if 0 3082 p = mtod(m, const uint8_t *); 3083 for (i = 0; i < m->m_pkthdr.len; ++i) { 3084 if (i != 0 && i % 8 == 0) 3085 printf("\n"); 3086 printf("%02x ", p[i]); 3087 } 3088 printf("\n"); 3089 #endif 3090 DPRINTF(sc, BWI_DBG_TX, "idx %d, pkt_len %d, buflen %d\n", 3091 idx, pkt_len, m->m_pkthdr.len); 3092 3093 /* Setup TX descriptor */ 3094 sc->sc_setup_txdesc(sc, rd, idx, paddr, m->m_pkthdr.len); 3095 bus_dmamap_sync(sc->sc_txring_dtag, rd->rdata_dmap, 3096 BUS_DMASYNC_PREWRITE); 3097 3098 /* Kick start */ 3099 sc->sc_start_tx(sc, rd->rdata_txrx_ctrl, idx); 3100 3101 back: 3102 if (error) 3103 m_freem(m); 3104 return error; 3105 } 3106 3107 static int 3108 bwi_encap_raw(struct bwi_softc *sc, int idx, struct mbuf *m, 3109 struct ieee80211_node *ni, const struct ieee80211_bpf_params *params) 3110 { 3111 struct ieee80211vap *vap = ni->ni_vap; 3112 struct ieee80211com *ic = ni->ni_ic; 3113 struct bwi_ring_data *rd = &sc->sc_tx_rdata[BWI_TX_DATA_RING]; 3114 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING]; 3115 struct bwi_txbuf *tb = &tbd->tbd_buf[idx]; 3116 struct bwi_mac *mac; 3117 struct bwi_txbuf_hdr *hdr; 3118 struct ieee80211_frame *wh; 3119 uint8_t rate, rate_fb; 3120 uint32_t mac_ctrl; 3121 uint16_t phy_ctrl; 3122 bus_addr_t paddr; 3123 int ismcast, pkt_len, error; 3124 3125 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 3126 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 3127 mac = (struct bwi_mac *)sc->sc_cur_regwin; 3128 3129 wh = mtod(m, struct ieee80211_frame *); 3130 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 3131 3132 /* Get 802.11 frame len before prepending TX header */ 3133 pkt_len = m->m_pkthdr.len + IEEE80211_CRC_LEN; 3134 3135 /* 3136 * Find TX rate 3137 */ 3138 rate = params->ibp_rate0; 3139 if (!ieee80211_isratevalid(ic->ic_rt, rate)) { 3140 /* XXX fall back to mcast/mgmt rate? */ 3141 m_freem(m); 3142 return EINVAL; 3143 } 3144 if (params->ibp_try1 != 0) { 3145 rate_fb = params->ibp_rate1; 3146 if (!ieee80211_isratevalid(ic->ic_rt, rate_fb)) { 3147 /* XXX fall back to rate0? */ 3148 m_freem(m); 3149 return EINVAL; 3150 } 3151 } else 3152 rate_fb = rate; 3153 tb->tb_rate[0] = rate; 3154 tb->tb_rate[1] = rate_fb; 3155 sc->sc_tx_rate = rate; 3156 3157 /* 3158 * TX radio tap 3159 */ 3160 if (ieee80211_radiotap_active_vap(vap)) { 3161 sc->sc_tx_th.wt_flags = 0; 3162 /* XXX IEEE80211_BPF_CRYPTO */ 3163 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) 3164 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP; 3165 if (params->ibp_flags & IEEE80211_BPF_SHORTPRE) 3166 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 3167 sc->sc_tx_th.wt_rate = rate; 3168 3169 ieee80211_radiotap_tx(vap, m); 3170 } 3171 3172 /* 3173 * Setup the embedded TX header 3174 */ 3175 M_PREPEND(m, sizeof(*hdr), M_NOWAIT); 3176 if (m == NULL) { 3177 device_printf(sc->sc_dev, "%s: prepend TX header failed\n", 3178 __func__); 3179 return ENOBUFS; 3180 } 3181 hdr = mtod(m, struct bwi_txbuf_hdr *); 3182 3183 bzero(hdr, sizeof(*hdr)); 3184 3185 bcopy(wh->i_fc, hdr->txh_fc, sizeof(hdr->txh_fc)); 3186 bcopy(wh->i_addr1, hdr->txh_addr1, sizeof(hdr->txh_addr1)); 3187 3188 mac_ctrl = BWI_TXH_MAC_C_HWSEQ | BWI_TXH_MAC_C_FIRST_FRAG; 3189 if (!ismcast && (params->ibp_flags & IEEE80211_BPF_NOACK) == 0) { 3190 uint16_t dur; 3191 3192 dur = ieee80211_ack_duration(sc->sc_rates, rate_fb, 0); 3193 3194 hdr->txh_fb_duration = htole16(dur); 3195 mac_ctrl |= BWI_TXH_MAC_C_ACK; 3196 } 3197 3198 hdr->txh_id = __SHIFTIN(BWI_TX_DATA_RING, BWI_TXH_ID_RING_MASK) | 3199 __SHIFTIN(idx, BWI_TXH_ID_IDX_MASK); 3200 3201 bwi_plcp_header(sc->sc_rates, hdr->txh_plcp, pkt_len, rate); 3202 bwi_plcp_header(sc->sc_rates, hdr->txh_fb_plcp, pkt_len, rate_fb); 3203 3204 phy_ctrl = __SHIFTIN(mac->mac_rf.rf_ant_mode, 3205 BWI_TXH_PHY_C_ANTMODE_MASK); 3206 if (ieee80211_rate2phytype(sc->sc_rates, rate) == IEEE80211_T_OFDM) { 3207 phy_ctrl |= BWI_TXH_PHY_C_OFDM; 3208 mac_ctrl |= BWI_TXH_MAC_C_FB_OFDM; 3209 } else if (params->ibp_flags & IEEE80211_BPF_SHORTPRE) 3210 phy_ctrl |= BWI_TXH_PHY_C_SHPREAMBLE; 3211 3212 hdr->txh_mac_ctrl = htole32(mac_ctrl); 3213 hdr->txh_phy_ctrl = htole16(phy_ctrl); 3214 3215 /* Catch any further usage */ 3216 hdr = NULL; 3217 wh = NULL; 3218 3219 /* DMA load */ 3220 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m, 3221 bwi_dma_buf_addr, &paddr, BUS_DMA_NOWAIT); 3222 if (error != 0) { 3223 struct mbuf *m_new; 3224 3225 if (error != EFBIG) { 3226 device_printf(sc->sc_dev, 3227 "%s: can't load TX buffer (1) %d\n", 3228 __func__, error); 3229 goto back; 3230 } 3231 m_new = m_defrag(m, M_NOWAIT); 3232 if (m_new == NULL) { 3233 device_printf(sc->sc_dev, 3234 "%s: can't defrag TX buffer\n", __func__); 3235 error = ENOBUFS; 3236 goto back; 3237 } 3238 m = m_new; 3239 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m, 3240 bwi_dma_buf_addr, &paddr, 3241 BUS_DMA_NOWAIT); 3242 if (error) { 3243 device_printf(sc->sc_dev, 3244 "%s: can't load TX buffer (2) %d\n", 3245 __func__, error); 3246 goto back; 3247 } 3248 } 3249 3250 bus_dmamap_sync(sc->sc_buf_dtag, tb->tb_dmap, BUS_DMASYNC_PREWRITE); 3251 3252 tb->tb_mbuf = m; 3253 tb->tb_ni = ni; 3254 3255 DPRINTF(sc, BWI_DBG_TX, "idx %d, pkt_len %d, buflen %d\n", 3256 idx, pkt_len, m->m_pkthdr.len); 3257 3258 /* Setup TX descriptor */ 3259 sc->sc_setup_txdesc(sc, rd, idx, paddr, m->m_pkthdr.len); 3260 bus_dmamap_sync(sc->sc_txring_dtag, rd->rdata_dmap, 3261 BUS_DMASYNC_PREWRITE); 3262 3263 /* Kick start */ 3264 sc->sc_start_tx(sc, rd->rdata_txrx_ctrl, idx); 3265 back: 3266 if (error) 3267 m_freem(m); 3268 return error; 3269 } 3270 3271 static void 3272 bwi_start_tx32(struct bwi_softc *sc, uint32_t tx_ctrl, int idx) 3273 { 3274 idx = (idx + 1) % BWI_TX_NDESC; 3275 CSR_WRITE_4(sc, tx_ctrl + BWI_TX32_INDEX, 3276 idx * sizeof(struct bwi_desc32)); 3277 } 3278 3279 static void 3280 bwi_start_tx64(struct bwi_softc *sc, uint32_t tx_ctrl, int idx) 3281 { 3282 /* TODO:64 */ 3283 } 3284 3285 static void 3286 bwi_txeof_status32(struct bwi_softc *sc) 3287 { 3288 uint32_t val, ctrl_base; 3289 int end_idx; 3290 3291 ctrl_base = sc->sc_txstats->stats_ctrl_base; 3292 3293 val = CSR_READ_4(sc, ctrl_base + BWI_RX32_STATUS); 3294 end_idx = __SHIFTOUT(val, BWI_RX32_STATUS_INDEX_MASK) / 3295 sizeof(struct bwi_desc32); 3296 3297 bwi_txeof_status(sc, end_idx); 3298 3299 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_INDEX, 3300 end_idx * sizeof(struct bwi_desc32)); 3301 3302 bwi_start_locked(sc); 3303 } 3304 3305 static void 3306 bwi_txeof_status64(struct bwi_softc *sc) 3307 { 3308 /* TODO:64 */ 3309 } 3310 3311 static void 3312 _bwi_txeof(struct bwi_softc *sc, uint16_t tx_id, int acked, int data_txcnt) 3313 { 3314 struct bwi_txbuf_data *tbd; 3315 struct bwi_txbuf *tb; 3316 int ring_idx, buf_idx; 3317 struct ieee80211_node *ni; 3318 3319 if (tx_id == 0) { 3320 device_printf(sc->sc_dev, "%s: zero tx id\n", __func__); 3321 return; 3322 } 3323 3324 ring_idx = __SHIFTOUT(tx_id, BWI_TXH_ID_RING_MASK); 3325 buf_idx = __SHIFTOUT(tx_id, BWI_TXH_ID_IDX_MASK); 3326 3327 KASSERT(ring_idx == BWI_TX_DATA_RING, ("ring_idx %d", ring_idx)); 3328 KASSERT(buf_idx < BWI_TX_NDESC, ("buf_idx %d", buf_idx)); 3329 3330 tbd = &sc->sc_tx_bdata[ring_idx]; 3331 KASSERT(tbd->tbd_used > 0, ("tbd_used %d", tbd->tbd_used)); 3332 tbd->tbd_used--; 3333 3334 tb = &tbd->tbd_buf[buf_idx]; 3335 DPRINTF(sc, BWI_DBG_TXEOF, "txeof idx %d, " 3336 "acked %d, data_txcnt %d, ni %p\n", 3337 buf_idx, acked, data_txcnt, tb->tb_ni); 3338 3339 bus_dmamap_unload(sc->sc_buf_dtag, tb->tb_dmap); 3340 3341 if ((ni = tb->tb_ni) != NULL) { 3342 const struct bwi_txbuf_hdr *hdr = 3343 mtod(tb->tb_mbuf, const struct bwi_txbuf_hdr *); 3344 struct ieee80211_ratectl_tx_status txs; 3345 3346 /* NB: update rate control only for unicast frames */ 3347 if (hdr->txh_mac_ctrl & htole32(BWI_TXH_MAC_C_ACK)) { 3348 /* 3349 * Feed back 'acked and data_txcnt'. Note that the 3350 * generic AMRR code only understands one tx rate 3351 * and the estimator doesn't handle real retry counts 3352 * well so to avoid over-aggressive downshifting we 3353 * treat any number of retries as "1". 3354 */ 3355 txs.flags = IEEE80211_RATECTL_STATUS_LONG_RETRY; 3356 txs.long_retries = acked; 3357 if (data_txcnt > 1) 3358 txs.status = IEEE80211_RATECTL_TX_SUCCESS; 3359 else { 3360 txs.status = 3361 IEEE80211_RATECTL_TX_FAIL_UNSPECIFIED; 3362 } 3363 ieee80211_ratectl_tx_complete(ni, &txs); 3364 } 3365 ieee80211_tx_complete(ni, tb->tb_mbuf, !acked); 3366 tb->tb_ni = NULL; 3367 } else 3368 m_freem(tb->tb_mbuf); 3369 tb->tb_mbuf = NULL; 3370 3371 if (tbd->tbd_used == 0) 3372 sc->sc_tx_timer = 0; 3373 } 3374 3375 static void 3376 bwi_txeof_status(struct bwi_softc *sc, int end_idx) 3377 { 3378 struct bwi_txstats_data *st = sc->sc_txstats; 3379 int idx; 3380 3381 bus_dmamap_sync(st->stats_dtag, st->stats_dmap, BUS_DMASYNC_POSTREAD); 3382 3383 idx = st->stats_idx; 3384 while (idx != end_idx) { 3385 const struct bwi_txstats *stats = &st->stats[idx]; 3386 3387 if ((stats->txs_flags & BWI_TXS_F_PENDING) == 0) { 3388 int data_txcnt; 3389 3390 data_txcnt = __SHIFTOUT(stats->txs_txcnt, 3391 BWI_TXS_TXCNT_DATA); 3392 _bwi_txeof(sc, le16toh(stats->txs_id), 3393 stats->txs_flags & BWI_TXS_F_ACKED, 3394 data_txcnt); 3395 } 3396 idx = (idx + 1) % BWI_TXSTATS_NDESC; 3397 } 3398 st->stats_idx = idx; 3399 } 3400 3401 static void 3402 bwi_txeof(struct bwi_softc *sc) 3403 { 3404 3405 for (;;) { 3406 uint32_t tx_status0, tx_status1; 3407 uint16_t tx_id; 3408 int data_txcnt; 3409 3410 tx_status0 = CSR_READ_4(sc, BWI_TXSTATUS0); 3411 if ((tx_status0 & BWI_TXSTATUS0_VALID) == 0) 3412 break; 3413 tx_status1 = CSR_READ_4(sc, BWI_TXSTATUS1); 3414 3415 tx_id = __SHIFTOUT(tx_status0, BWI_TXSTATUS0_TXID_MASK); 3416 data_txcnt = __SHIFTOUT(tx_status0, 3417 BWI_TXSTATUS0_DATA_TXCNT_MASK); 3418 3419 if (tx_status0 & (BWI_TXSTATUS0_AMPDU | BWI_TXSTATUS0_PENDING)) 3420 continue; 3421 3422 _bwi_txeof(sc, le16toh(tx_id), tx_status0 & BWI_TXSTATUS0_ACKED, 3423 data_txcnt); 3424 } 3425 3426 bwi_start_locked(sc); 3427 } 3428 3429 static int 3430 bwi_bbp_power_on(struct bwi_softc *sc, enum bwi_clock_mode clk_mode) 3431 { 3432 bwi_power_on(sc, 1); 3433 return bwi_set_clock_mode(sc, clk_mode); 3434 } 3435 3436 static void 3437 bwi_bbp_power_off(struct bwi_softc *sc) 3438 { 3439 bwi_set_clock_mode(sc, BWI_CLOCK_MODE_SLOW); 3440 bwi_power_off(sc, 1); 3441 } 3442 3443 static int 3444 bwi_get_pwron_delay(struct bwi_softc *sc) 3445 { 3446 struct bwi_regwin *com, *old; 3447 struct bwi_clock_freq freq; 3448 uint32_t val; 3449 int error; 3450 3451 com = &sc->sc_com_regwin; 3452 KASSERT(BWI_REGWIN_EXIST(com), ("no regwin")); 3453 3454 if ((sc->sc_cap & BWI_CAP_CLKMODE) == 0) 3455 return 0; 3456 3457 error = bwi_regwin_switch(sc, com, &old); 3458 if (error) 3459 return error; 3460 3461 bwi_get_clock_freq(sc, &freq); 3462 3463 val = CSR_READ_4(sc, BWI_PLL_ON_DELAY); 3464 sc->sc_pwron_delay = howmany((val + 2) * 1000000, freq.clkfreq_min); 3465 DPRINTF(sc, BWI_DBG_ATTACH, "power on delay %u\n", sc->sc_pwron_delay); 3466 3467 return bwi_regwin_switch(sc, old, NULL); 3468 } 3469 3470 static int 3471 bwi_bus_attach(struct bwi_softc *sc) 3472 { 3473 struct bwi_regwin *bus, *old; 3474 int error; 3475 3476 bus = &sc->sc_bus_regwin; 3477 3478 error = bwi_regwin_switch(sc, bus, &old); 3479 if (error) 3480 return error; 3481 3482 if (!bwi_regwin_is_enabled(sc, bus)) 3483 bwi_regwin_enable(sc, bus, 0); 3484 3485 /* Disable interripts */ 3486 CSR_WRITE_4(sc, BWI_INTRVEC, 0); 3487 3488 return bwi_regwin_switch(sc, old, NULL); 3489 } 3490 3491 static const char * 3492 bwi_regwin_name(const struct bwi_regwin *rw) 3493 { 3494 switch (rw->rw_type) { 3495 case BWI_REGWIN_T_COM: 3496 return "COM"; 3497 case BWI_REGWIN_T_BUSPCI: 3498 return "PCI"; 3499 case BWI_REGWIN_T_MAC: 3500 return "MAC"; 3501 case BWI_REGWIN_T_BUSPCIE: 3502 return "PCIE"; 3503 } 3504 panic("unknown regwin type 0x%04x\n", rw->rw_type); 3505 return NULL; 3506 } 3507 3508 static uint32_t 3509 bwi_regwin_disable_bits(struct bwi_softc *sc) 3510 { 3511 uint32_t busrev; 3512 3513 /* XXX cache this */ 3514 busrev = __SHIFTOUT(CSR_READ_4(sc, BWI_ID_LO), BWI_ID_LO_BUSREV_MASK); 3515 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT | BWI_DBG_MISC, 3516 "bus rev %u\n", busrev); 3517 3518 if (busrev == BWI_BUSREV_0) 3519 return BWI_STATE_LO_DISABLE1; 3520 else if (busrev == BWI_BUSREV_1) 3521 return BWI_STATE_LO_DISABLE2; 3522 else 3523 return (BWI_STATE_LO_DISABLE1 | BWI_STATE_LO_DISABLE2); 3524 } 3525 3526 int 3527 bwi_regwin_is_enabled(struct bwi_softc *sc, struct bwi_regwin *rw) 3528 { 3529 uint32_t val, disable_bits; 3530 3531 disable_bits = bwi_regwin_disable_bits(sc); 3532 val = CSR_READ_4(sc, BWI_STATE_LO); 3533 3534 if ((val & (BWI_STATE_LO_CLOCK | 3535 BWI_STATE_LO_RESET | 3536 disable_bits)) == BWI_STATE_LO_CLOCK) { 3537 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT, "%s is enabled\n", 3538 bwi_regwin_name(rw)); 3539 return 1; 3540 } else { 3541 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT, "%s is disabled\n", 3542 bwi_regwin_name(rw)); 3543 return 0; 3544 } 3545 } 3546 3547 void 3548 bwi_regwin_disable(struct bwi_softc *sc, struct bwi_regwin *rw, uint32_t flags) 3549 { 3550 uint32_t state_lo, disable_bits; 3551 int i; 3552 3553 state_lo = CSR_READ_4(sc, BWI_STATE_LO); 3554 3555 /* 3556 * If current regwin is in 'reset' state, it was already disabled. 3557 */ 3558 if (state_lo & BWI_STATE_LO_RESET) { 3559 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT, 3560 "%s was already disabled\n", bwi_regwin_name(rw)); 3561 return; 3562 } 3563 3564 disable_bits = bwi_regwin_disable_bits(sc); 3565 3566 /* 3567 * Disable normal clock 3568 */ 3569 state_lo = BWI_STATE_LO_CLOCK | disable_bits; 3570 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo); 3571 3572 /* 3573 * Wait until normal clock is disabled 3574 */ 3575 #define NRETRY 1000 3576 for (i = 0; i < NRETRY; ++i) { 3577 state_lo = CSR_READ_4(sc, BWI_STATE_LO); 3578 if (state_lo & disable_bits) 3579 break; 3580 DELAY(10); 3581 } 3582 if (i == NRETRY) { 3583 device_printf(sc->sc_dev, "%s disable clock timeout\n", 3584 bwi_regwin_name(rw)); 3585 } 3586 3587 for (i = 0; i < NRETRY; ++i) { 3588 uint32_t state_hi; 3589 3590 state_hi = CSR_READ_4(sc, BWI_STATE_HI); 3591 if ((state_hi & BWI_STATE_HI_BUSY) == 0) 3592 break; 3593 DELAY(10); 3594 } 3595 if (i == NRETRY) { 3596 device_printf(sc->sc_dev, "%s wait BUSY unset timeout\n", 3597 bwi_regwin_name(rw)); 3598 } 3599 #undef NRETRY 3600 3601 /* 3602 * Reset and disable regwin with gated clock 3603 */ 3604 state_lo = BWI_STATE_LO_RESET | disable_bits | 3605 BWI_STATE_LO_CLOCK | BWI_STATE_LO_GATED_CLOCK | 3606 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK); 3607 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo); 3608 3609 /* Flush pending bus write */ 3610 CSR_READ_4(sc, BWI_STATE_LO); 3611 DELAY(1); 3612 3613 /* Reset and disable regwin */ 3614 state_lo = BWI_STATE_LO_RESET | disable_bits | 3615 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK); 3616 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo); 3617 3618 /* Flush pending bus write */ 3619 CSR_READ_4(sc, BWI_STATE_LO); 3620 DELAY(1); 3621 } 3622 3623 void 3624 bwi_regwin_enable(struct bwi_softc *sc, struct bwi_regwin *rw, uint32_t flags) 3625 { 3626 uint32_t state_lo, state_hi, imstate; 3627 3628 bwi_regwin_disable(sc, rw, flags); 3629 3630 /* Reset regwin with gated clock */ 3631 state_lo = BWI_STATE_LO_RESET | 3632 BWI_STATE_LO_CLOCK | 3633 BWI_STATE_LO_GATED_CLOCK | 3634 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK); 3635 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo); 3636 3637 /* Flush pending bus write */ 3638 CSR_READ_4(sc, BWI_STATE_LO); 3639 DELAY(1); 3640 3641 state_hi = CSR_READ_4(sc, BWI_STATE_HI); 3642 if (state_hi & BWI_STATE_HI_SERROR) 3643 CSR_WRITE_4(sc, BWI_STATE_HI, 0); 3644 3645 imstate = CSR_READ_4(sc, BWI_IMSTATE); 3646 if (imstate & (BWI_IMSTATE_INBAND_ERR | BWI_IMSTATE_TIMEOUT)) { 3647 imstate &= ~(BWI_IMSTATE_INBAND_ERR | BWI_IMSTATE_TIMEOUT); 3648 CSR_WRITE_4(sc, BWI_IMSTATE, imstate); 3649 } 3650 3651 /* Enable regwin with gated clock */ 3652 state_lo = BWI_STATE_LO_CLOCK | 3653 BWI_STATE_LO_GATED_CLOCK | 3654 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK); 3655 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo); 3656 3657 /* Flush pending bus write */ 3658 CSR_READ_4(sc, BWI_STATE_LO); 3659 DELAY(1); 3660 3661 /* Enable regwin with normal clock */ 3662 state_lo = BWI_STATE_LO_CLOCK | 3663 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK); 3664 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo); 3665 3666 /* Flush pending bus write */ 3667 CSR_READ_4(sc, BWI_STATE_LO); 3668 DELAY(1); 3669 } 3670 3671 static void 3672 bwi_set_bssid(struct bwi_softc *sc, const uint8_t *bssid) 3673 { 3674 struct bwi_mac *mac; 3675 struct bwi_myaddr_bssid buf; 3676 const uint8_t *p; 3677 uint32_t val; 3678 int n, i; 3679 3680 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 3681 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 3682 mac = (struct bwi_mac *)sc->sc_cur_regwin; 3683 3684 bwi_set_addr_filter(sc, BWI_ADDR_FILTER_BSSID, bssid); 3685 3686 bcopy(sc->sc_ic.ic_macaddr, buf.myaddr, sizeof(buf.myaddr)); 3687 bcopy(bssid, buf.bssid, sizeof(buf.bssid)); 3688 3689 n = sizeof(buf) / sizeof(val); 3690 p = (const uint8_t *)&buf; 3691 for (i = 0; i < n; ++i) { 3692 int j; 3693 3694 val = 0; 3695 for (j = 0; j < sizeof(val); ++j) 3696 val |= ((uint32_t)(*p++)) << (j * 8); 3697 3698 TMPLT_WRITE_4(mac, 0x20 + (i * sizeof(val)), val); 3699 } 3700 } 3701 3702 static void 3703 bwi_updateslot(struct ieee80211com *ic) 3704 { 3705 struct bwi_softc *sc = ic->ic_softc; 3706 struct bwi_mac *mac; 3707 3708 BWI_LOCK(sc); 3709 if (sc->sc_flags & BWI_F_RUNNING) { 3710 DPRINTF(sc, BWI_DBG_80211, "%s\n", __func__); 3711 3712 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 3713 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 3714 mac = (struct bwi_mac *)sc->sc_cur_regwin; 3715 3716 bwi_mac_updateslot(mac, (ic->ic_flags & IEEE80211_F_SHSLOT)); 3717 } 3718 BWI_UNLOCK(sc); 3719 } 3720 3721 static void 3722 bwi_calibrate(void *xsc) 3723 { 3724 struct bwi_softc *sc = xsc; 3725 struct bwi_mac *mac; 3726 3727 BWI_ASSERT_LOCKED(sc); 3728 3729 KASSERT(sc->sc_ic.ic_opmode != IEEE80211_M_MONITOR, 3730 ("opmode %d", sc->sc_ic.ic_opmode)); 3731 3732 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 3733 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 3734 mac = (struct bwi_mac *)sc->sc_cur_regwin; 3735 3736 bwi_mac_calibrate_txpower(mac, sc->sc_txpwrcb_type); 3737 sc->sc_txpwrcb_type = BWI_TXPWR_CALIB; 3738 3739 /* XXX 15 seconds */ 3740 callout_reset(&sc->sc_calib_ch, hz * 15, bwi_calibrate, sc); 3741 } 3742 3743 static int 3744 bwi_calc_rssi(struct bwi_softc *sc, const struct bwi_rxbuf_hdr *hdr) 3745 { 3746 struct bwi_mac *mac; 3747 3748 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 3749 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 3750 mac = (struct bwi_mac *)sc->sc_cur_regwin; 3751 3752 return bwi_rf_calc_rssi(mac, hdr); 3753 } 3754 3755 static int 3756 bwi_calc_noise(struct bwi_softc *sc) 3757 { 3758 struct bwi_mac *mac; 3759 3760 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 3761 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 3762 mac = (struct bwi_mac *)sc->sc_cur_regwin; 3763 3764 return bwi_rf_calc_noise(mac); 3765 } 3766 3767 static __inline uint8_t 3768 bwi_plcp2rate(const uint32_t plcp0, enum ieee80211_phytype type) 3769 { 3770 uint32_t plcp = le32toh(plcp0) & IEEE80211_OFDM_PLCP_RATE_MASK; 3771 return (ieee80211_plcp2rate(plcp, type)); 3772 } 3773 3774 static void 3775 bwi_rx_radiotap(struct bwi_softc *sc, struct mbuf *m, 3776 struct bwi_rxbuf_hdr *hdr, const void *plcp, int rate, int rssi, int noise) 3777 { 3778 const struct ieee80211_frame_min *wh; 3779 3780 sc->sc_rx_th.wr_flags = IEEE80211_RADIOTAP_F_FCS; 3781 if (htole16(hdr->rxh_flags1) & BWI_RXH_F1_SHPREAMBLE) 3782 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 3783 3784 wh = mtod(m, const struct ieee80211_frame_min *); 3785 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) 3786 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_WEP; 3787 3788 sc->sc_rx_th.wr_tsf = hdr->rxh_tsf; /* No endian conversion */ 3789 sc->sc_rx_th.wr_rate = rate; 3790 sc->sc_rx_th.wr_antsignal = rssi; 3791 sc->sc_rx_th.wr_antnoise = noise; 3792 } 3793 3794 static void 3795 bwi_led_attach(struct bwi_softc *sc) 3796 { 3797 const uint8_t *led_act = NULL; 3798 uint16_t gpio, val[BWI_LED_MAX]; 3799 int i; 3800 3801 for (i = 0; i < nitems(bwi_vendor_led_act); ++i) { 3802 if (sc->sc_pci_subvid == bwi_vendor_led_act[i].vid) { 3803 led_act = bwi_vendor_led_act[i].led_act; 3804 break; 3805 } 3806 } 3807 if (led_act == NULL) 3808 led_act = bwi_default_led_act; 3809 3810 gpio = bwi_read_sprom(sc, BWI_SPROM_GPIO01); 3811 val[0] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_0); 3812 val[1] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_1); 3813 3814 gpio = bwi_read_sprom(sc, BWI_SPROM_GPIO23); 3815 val[2] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_2); 3816 val[3] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_3); 3817 3818 for (i = 0; i < BWI_LED_MAX; ++i) { 3819 struct bwi_led *led = &sc->sc_leds[i]; 3820 3821 if (val[i] == 0xff) { 3822 led->l_act = led_act[i]; 3823 } else { 3824 if (val[i] & BWI_LED_ACT_LOW) 3825 led->l_flags |= BWI_LED_F_ACTLOW; 3826 led->l_act = __SHIFTOUT(val[i], BWI_LED_ACT_MASK); 3827 } 3828 led->l_mask = (1 << i); 3829 3830 if (led->l_act == BWI_LED_ACT_BLINK_SLOW || 3831 led->l_act == BWI_LED_ACT_BLINK_POLL || 3832 led->l_act == BWI_LED_ACT_BLINK) { 3833 led->l_flags |= BWI_LED_F_BLINK; 3834 if (led->l_act == BWI_LED_ACT_BLINK_POLL) 3835 led->l_flags |= BWI_LED_F_POLLABLE; 3836 else if (led->l_act == BWI_LED_ACT_BLINK_SLOW) 3837 led->l_flags |= BWI_LED_F_SLOW; 3838 3839 if (sc->sc_blink_led == NULL) { 3840 sc->sc_blink_led = led; 3841 if (led->l_flags & BWI_LED_F_SLOW) 3842 BWI_LED_SLOWDOWN(sc->sc_led_idle); 3843 } 3844 } 3845 3846 DPRINTF(sc, BWI_DBG_LED | BWI_DBG_ATTACH, 3847 "%dth led, act %d, lowact %d\n", i, 3848 led->l_act, led->l_flags & BWI_LED_F_ACTLOW); 3849 } 3850 callout_init_mtx(&sc->sc_led_blink_ch, &sc->sc_mtx, 0); 3851 } 3852 3853 static __inline uint16_t 3854 bwi_led_onoff(const struct bwi_led *led, uint16_t val, int on) 3855 { 3856 if (led->l_flags & BWI_LED_F_ACTLOW) 3857 on = !on; 3858 if (on) 3859 val |= led->l_mask; 3860 else 3861 val &= ~led->l_mask; 3862 return val; 3863 } 3864 3865 static void 3866 bwi_led_newstate(struct bwi_softc *sc, enum ieee80211_state nstate) 3867 { 3868 struct ieee80211com *ic = &sc->sc_ic; 3869 uint16_t val; 3870 int i; 3871 3872 if (nstate == IEEE80211_S_INIT) { 3873 callout_stop(&sc->sc_led_blink_ch); 3874 sc->sc_led_blinking = 0; 3875 } 3876 3877 if ((sc->sc_flags & BWI_F_RUNNING) == 0) 3878 return; 3879 3880 val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL); 3881 for (i = 0; i < BWI_LED_MAX; ++i) { 3882 struct bwi_led *led = &sc->sc_leds[i]; 3883 int on; 3884 3885 if (led->l_act == BWI_LED_ACT_UNKN || 3886 led->l_act == BWI_LED_ACT_NULL) 3887 continue; 3888 3889 if ((led->l_flags & BWI_LED_F_BLINK) && 3890 nstate != IEEE80211_S_INIT) 3891 continue; 3892 3893 switch (led->l_act) { 3894 case BWI_LED_ACT_ON: /* Always on */ 3895 on = 1; 3896 break; 3897 case BWI_LED_ACT_OFF: /* Always off */ 3898 case BWI_LED_ACT_5GHZ: /* TODO: 11A */ 3899 on = 0; 3900 break; 3901 default: 3902 on = 1; 3903 switch (nstate) { 3904 case IEEE80211_S_INIT: 3905 on = 0; 3906 break; 3907 case IEEE80211_S_RUN: 3908 if (led->l_act == BWI_LED_ACT_11G && 3909 ic->ic_curmode != IEEE80211_MODE_11G) 3910 on = 0; 3911 break; 3912 default: 3913 if (led->l_act == BWI_LED_ACT_ASSOC) 3914 on = 0; 3915 break; 3916 } 3917 break; 3918 } 3919 3920 val = bwi_led_onoff(led, val, on); 3921 } 3922 CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val); 3923 } 3924 static void 3925 bwi_led_event(struct bwi_softc *sc, int event) 3926 { 3927 struct bwi_led *led = sc->sc_blink_led; 3928 int rate; 3929 3930 if (event == BWI_LED_EVENT_POLL) { 3931 if ((led->l_flags & BWI_LED_F_POLLABLE) == 0) 3932 return; 3933 if (ticks - sc->sc_led_ticks < sc->sc_led_idle) 3934 return; 3935 } 3936 3937 sc->sc_led_ticks = ticks; 3938 if (sc->sc_led_blinking) 3939 return; 3940 3941 switch (event) { 3942 case BWI_LED_EVENT_RX: 3943 rate = sc->sc_rx_rate; 3944 break; 3945 case BWI_LED_EVENT_TX: 3946 rate = sc->sc_tx_rate; 3947 break; 3948 case BWI_LED_EVENT_POLL: 3949 rate = 0; 3950 break; 3951 default: 3952 panic("unknown LED event %d\n", event); 3953 break; 3954 } 3955 bwi_led_blink_start(sc, bwi_led_duration[rate].on_dur, 3956 bwi_led_duration[rate].off_dur); 3957 } 3958 3959 static void 3960 bwi_led_blink_start(struct bwi_softc *sc, int on_dur, int off_dur) 3961 { 3962 struct bwi_led *led = sc->sc_blink_led; 3963 uint16_t val; 3964 3965 val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL); 3966 val = bwi_led_onoff(led, val, 1); 3967 CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val); 3968 3969 if (led->l_flags & BWI_LED_F_SLOW) { 3970 BWI_LED_SLOWDOWN(on_dur); 3971 BWI_LED_SLOWDOWN(off_dur); 3972 } 3973 3974 sc->sc_led_blinking = 1; 3975 sc->sc_led_blink_offdur = off_dur; 3976 3977 callout_reset(&sc->sc_led_blink_ch, on_dur, bwi_led_blink_next, sc); 3978 } 3979 3980 static void 3981 bwi_led_blink_next(void *xsc) 3982 { 3983 struct bwi_softc *sc = xsc; 3984 uint16_t val; 3985 3986 val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL); 3987 val = bwi_led_onoff(sc->sc_blink_led, val, 0); 3988 CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val); 3989 3990 callout_reset(&sc->sc_led_blink_ch, sc->sc_led_blink_offdur, 3991 bwi_led_blink_end, sc); 3992 } 3993 3994 static void 3995 bwi_led_blink_end(void *xsc) 3996 { 3997 struct bwi_softc *sc = xsc; 3998 sc->sc_led_blinking = 0; 3999 } 4000 4001 static void 4002 bwi_restart(void *xsc, int pending) 4003 { 4004 struct bwi_softc *sc = xsc; 4005 4006 device_printf(sc->sc_dev, "%s begin, help!\n", __func__); 4007 BWI_LOCK(sc); 4008 bwi_init_statechg(sc, 0); 4009 #if 0 4010 bwi_start_locked(sc); 4011 #endif 4012 BWI_UNLOCK(sc); 4013 } 4014