1 /* 2 * Copyright (c) 2007 The DragonFly Project. All rights reserved. 3 * 4 * This code is derived from software contributed to The DragonFly Project 5 * by Sepherosa Ziehau <sepherosa@gmail.com> 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * 3. Neither the name of The DragonFly Project nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific, prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 24 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 25 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 27 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 29 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * $DragonFly: src/sys/dev/netif/bwi/if_bwi.c,v 1.19 2008/02/15 11:15:38 sephe Exp $ 35 */ 36 37 #include <sys/cdefs.h> 38 __FBSDID("$FreeBSD$"); 39 40 #include "opt_inet.h" 41 #include "opt_bwi.h" 42 #include "opt_wlan.h" 43 44 #include <sys/param.h> 45 #include <sys/endian.h> 46 #include <sys/kernel.h> 47 #include <sys/bus.h> 48 #include <sys/malloc.h> 49 #include <sys/proc.h> 50 #include <sys/rman.h> 51 #include <sys/socket.h> 52 #include <sys/sockio.h> 53 #include <sys/sysctl.h> 54 #include <sys/systm.h> 55 #include <sys/taskqueue.h> 56 57 #include <net/if.h> 58 #include <net/if_var.h> 59 #include <net/if_dl.h> 60 #include <net/if_media.h> 61 #include <net/if_types.h> 62 #include <net/if_arp.h> 63 #include <net/ethernet.h> 64 #include <net/if_llc.h> 65 66 #include <net80211/ieee80211_var.h> 67 #include <net80211/ieee80211_radiotap.h> 68 #include <net80211/ieee80211_regdomain.h> 69 #include <net80211/ieee80211_phy.h> 70 #include <net80211/ieee80211_ratectl.h> 71 72 #include <net/bpf.h> 73 74 #ifdef INET 75 #include <netinet/in.h> 76 #include <netinet/if_ether.h> 77 #endif 78 79 #include <machine/bus.h> 80 81 #include <dev/pci/pcivar.h> 82 #include <dev/pci/pcireg.h> 83 84 #include <dev/bwi/bitops.h> 85 #include <dev/bwi/if_bwireg.h> 86 #include <dev/bwi/if_bwivar.h> 87 #include <dev/bwi/bwimac.h> 88 #include <dev/bwi/bwirf.h> 89 90 struct bwi_clock_freq { 91 u_int clkfreq_min; 92 u_int clkfreq_max; 93 }; 94 95 struct bwi_myaddr_bssid { 96 uint8_t myaddr[IEEE80211_ADDR_LEN]; 97 uint8_t bssid[IEEE80211_ADDR_LEN]; 98 } __packed; 99 100 static struct ieee80211vap *bwi_vap_create(struct ieee80211com *, 101 const char [IFNAMSIZ], int, enum ieee80211_opmode, int, 102 const uint8_t [IEEE80211_ADDR_LEN], 103 const uint8_t [IEEE80211_ADDR_LEN]); 104 static void bwi_vap_delete(struct ieee80211vap *); 105 static void bwi_init(void *); 106 static int bwi_ioctl(struct ifnet *, u_long, caddr_t); 107 static void bwi_start(struct ifnet *); 108 static void bwi_start_locked(struct ifnet *); 109 static int bwi_raw_xmit(struct ieee80211_node *, struct mbuf *, 110 const struct ieee80211_bpf_params *); 111 static void bwi_watchdog(void *); 112 static void bwi_scan_start(struct ieee80211com *); 113 static void bwi_set_channel(struct ieee80211com *); 114 static void bwi_scan_end(struct ieee80211com *); 115 static int bwi_newstate(struct ieee80211vap *, enum ieee80211_state, int); 116 static void bwi_updateslot(struct ieee80211com *); 117 static int bwi_media_change(struct ifnet *); 118 119 static void bwi_calibrate(void *); 120 121 static int bwi_calc_rssi(struct bwi_softc *, const struct bwi_rxbuf_hdr *); 122 static int bwi_calc_noise(struct bwi_softc *); 123 static __inline uint8_t bwi_plcp2rate(uint32_t, enum ieee80211_phytype); 124 static void bwi_rx_radiotap(struct bwi_softc *, struct mbuf *, 125 struct bwi_rxbuf_hdr *, const void *, int, int, int); 126 127 static void bwi_restart(void *, int); 128 static void bwi_init_statechg(struct bwi_softc *, int); 129 static void bwi_stop(struct bwi_softc *, int); 130 static void bwi_stop_locked(struct bwi_softc *, int); 131 static int bwi_newbuf(struct bwi_softc *, int, int); 132 static int bwi_encap(struct bwi_softc *, int, struct mbuf *, 133 struct ieee80211_node *); 134 static int bwi_encap_raw(struct bwi_softc *, int, struct mbuf *, 135 struct ieee80211_node *, 136 const struct ieee80211_bpf_params *); 137 138 static void bwi_init_rxdesc_ring32(struct bwi_softc *, uint32_t, 139 bus_addr_t, int, int); 140 static void bwi_reset_rx_ring32(struct bwi_softc *, uint32_t); 141 142 static int bwi_init_tx_ring32(struct bwi_softc *, int); 143 static int bwi_init_rx_ring32(struct bwi_softc *); 144 static int bwi_init_txstats32(struct bwi_softc *); 145 static void bwi_free_tx_ring32(struct bwi_softc *, int); 146 static void bwi_free_rx_ring32(struct bwi_softc *); 147 static void bwi_free_txstats32(struct bwi_softc *); 148 static void bwi_setup_rx_desc32(struct bwi_softc *, int, bus_addr_t, int); 149 static void bwi_setup_tx_desc32(struct bwi_softc *, struct bwi_ring_data *, 150 int, bus_addr_t, int); 151 static int bwi_rxeof32(struct bwi_softc *); 152 static void bwi_start_tx32(struct bwi_softc *, uint32_t, int); 153 static void bwi_txeof_status32(struct bwi_softc *); 154 155 static int bwi_init_tx_ring64(struct bwi_softc *, int); 156 static int bwi_init_rx_ring64(struct bwi_softc *); 157 static int bwi_init_txstats64(struct bwi_softc *); 158 static void bwi_free_tx_ring64(struct bwi_softc *, int); 159 static void bwi_free_rx_ring64(struct bwi_softc *); 160 static void bwi_free_txstats64(struct bwi_softc *); 161 static void bwi_setup_rx_desc64(struct bwi_softc *, int, bus_addr_t, int); 162 static void bwi_setup_tx_desc64(struct bwi_softc *, struct bwi_ring_data *, 163 int, bus_addr_t, int); 164 static int bwi_rxeof64(struct bwi_softc *); 165 static void bwi_start_tx64(struct bwi_softc *, uint32_t, int); 166 static void bwi_txeof_status64(struct bwi_softc *); 167 168 static int bwi_rxeof(struct bwi_softc *, int); 169 static void _bwi_txeof(struct bwi_softc *, uint16_t, int, int); 170 static void bwi_txeof(struct bwi_softc *); 171 static void bwi_txeof_status(struct bwi_softc *, int); 172 static void bwi_enable_intrs(struct bwi_softc *, uint32_t); 173 static void bwi_disable_intrs(struct bwi_softc *, uint32_t); 174 175 static int bwi_dma_alloc(struct bwi_softc *); 176 static void bwi_dma_free(struct bwi_softc *); 177 static int bwi_dma_ring_alloc(struct bwi_softc *, bus_dma_tag_t, 178 struct bwi_ring_data *, bus_size_t, 179 uint32_t); 180 static int bwi_dma_mbuf_create(struct bwi_softc *); 181 static void bwi_dma_mbuf_destroy(struct bwi_softc *, int, int); 182 static int bwi_dma_txstats_alloc(struct bwi_softc *, uint32_t, bus_size_t); 183 static void bwi_dma_txstats_free(struct bwi_softc *); 184 static void bwi_dma_ring_addr(void *, bus_dma_segment_t *, int, int); 185 static void bwi_dma_buf_addr(void *, bus_dma_segment_t *, int, 186 bus_size_t, int); 187 188 static void bwi_power_on(struct bwi_softc *, int); 189 static int bwi_power_off(struct bwi_softc *, int); 190 static int bwi_set_clock_mode(struct bwi_softc *, enum bwi_clock_mode); 191 static int bwi_set_clock_delay(struct bwi_softc *); 192 static void bwi_get_clock_freq(struct bwi_softc *, struct bwi_clock_freq *); 193 static int bwi_get_pwron_delay(struct bwi_softc *sc); 194 static void bwi_set_addr_filter(struct bwi_softc *, uint16_t, 195 const uint8_t *); 196 static void bwi_set_bssid(struct bwi_softc *, const uint8_t *); 197 198 static void bwi_get_card_flags(struct bwi_softc *); 199 static void bwi_get_eaddr(struct bwi_softc *, uint16_t, uint8_t *); 200 201 static int bwi_bus_attach(struct bwi_softc *); 202 static int bwi_bbp_attach(struct bwi_softc *); 203 static int bwi_bbp_power_on(struct bwi_softc *, enum bwi_clock_mode); 204 static void bwi_bbp_power_off(struct bwi_softc *); 205 206 static const char *bwi_regwin_name(const struct bwi_regwin *); 207 static uint32_t bwi_regwin_disable_bits(struct bwi_softc *); 208 static void bwi_regwin_info(struct bwi_softc *, uint16_t *, uint8_t *); 209 static int bwi_regwin_select(struct bwi_softc *, int); 210 211 static void bwi_led_attach(struct bwi_softc *); 212 static void bwi_led_newstate(struct bwi_softc *, enum ieee80211_state); 213 static void bwi_led_event(struct bwi_softc *, int); 214 static void bwi_led_blink_start(struct bwi_softc *, int, int); 215 static void bwi_led_blink_next(void *); 216 static void bwi_led_blink_end(void *); 217 218 static const struct { 219 uint16_t did_min; 220 uint16_t did_max; 221 uint16_t bbp_id; 222 } bwi_bbpid_map[] = { 223 { 0x4301, 0x4301, 0x4301 }, 224 { 0x4305, 0x4307, 0x4307 }, 225 { 0x4402, 0x4403, 0x4402 }, 226 { 0x4610, 0x4615, 0x4610 }, 227 { 0x4710, 0x4715, 0x4710 }, 228 { 0x4720, 0x4725, 0x4309 } 229 }; 230 231 static const struct { 232 uint16_t bbp_id; 233 int nregwin; 234 } bwi_regwin_count[] = { 235 { 0x4301, 5 }, 236 { 0x4306, 6 }, 237 { 0x4307, 5 }, 238 { 0x4310, 8 }, 239 { 0x4401, 3 }, 240 { 0x4402, 3 }, 241 { 0x4610, 9 }, 242 { 0x4704, 9 }, 243 { 0x4710, 9 }, 244 { 0x5365, 7 } 245 }; 246 247 #define CLKSRC(src) \ 248 [BWI_CLKSRC_ ## src] = { \ 249 .freq_min = BWI_CLKSRC_ ##src## _FMIN, \ 250 .freq_max = BWI_CLKSRC_ ##src## _FMAX \ 251 } 252 253 static const struct { 254 u_int freq_min; 255 u_int freq_max; 256 } bwi_clkfreq[BWI_CLKSRC_MAX] = { 257 CLKSRC(LP_OSC), 258 CLKSRC(CS_OSC), 259 CLKSRC(PCI) 260 }; 261 262 #undef CLKSRC 263 264 #define VENDOR_LED_ACT(vendor) \ 265 { \ 266 .vid = PCI_VENDOR_##vendor, \ 267 .led_act = { BWI_VENDOR_LED_ACT_##vendor } \ 268 } 269 270 static const struct { 271 #define PCI_VENDOR_COMPAQ 0x0e11 272 #define PCI_VENDOR_LINKSYS 0x1737 273 uint16_t vid; 274 uint8_t led_act[BWI_LED_MAX]; 275 } bwi_vendor_led_act[] = { 276 VENDOR_LED_ACT(COMPAQ), 277 VENDOR_LED_ACT(LINKSYS) 278 #undef PCI_VENDOR_LINKSYS 279 #undef PCI_VENDOR_COMPAQ 280 }; 281 282 static const uint8_t bwi_default_led_act[BWI_LED_MAX] = 283 { BWI_VENDOR_LED_ACT_DEFAULT }; 284 285 #undef VENDOR_LED_ACT 286 287 static const struct { 288 int on_dur; 289 int off_dur; 290 } bwi_led_duration[109] = { 291 [0] = { 400, 100 }, 292 [2] = { 150, 75 }, 293 [4] = { 90, 45 }, 294 [11] = { 66, 34 }, 295 [12] = { 53, 26 }, 296 [18] = { 42, 21 }, 297 [22] = { 35, 17 }, 298 [24] = { 32, 16 }, 299 [36] = { 21, 10 }, 300 [48] = { 16, 8 }, 301 [72] = { 11, 5 }, 302 [96] = { 9, 4 }, 303 [108] = { 7, 3 } 304 }; 305 306 #ifdef BWI_DEBUG 307 #ifdef BWI_DEBUG_VERBOSE 308 static uint32_t bwi_debug = BWI_DBG_ATTACH | BWI_DBG_INIT | BWI_DBG_TXPOWER; 309 #else 310 static uint32_t bwi_debug; 311 #endif 312 TUNABLE_INT("hw.bwi.debug", (int *)&bwi_debug); 313 #endif /* BWI_DEBUG */ 314 315 static const uint8_t bwi_zero_addr[IEEE80211_ADDR_LEN]; 316 317 uint16_t 318 bwi_read_sprom(struct bwi_softc *sc, uint16_t ofs) 319 { 320 return CSR_READ_2(sc, ofs + BWI_SPROM_START); 321 } 322 323 static __inline void 324 bwi_setup_desc32(struct bwi_softc *sc, struct bwi_desc32 *desc_array, 325 int ndesc, int desc_idx, bus_addr_t paddr, int buf_len, 326 int tx) 327 { 328 struct bwi_desc32 *desc = &desc_array[desc_idx]; 329 uint32_t ctrl, addr, addr_hi, addr_lo; 330 331 addr_lo = __SHIFTOUT(paddr, BWI_DESC32_A_ADDR_MASK); 332 addr_hi = __SHIFTOUT(paddr, BWI_DESC32_A_FUNC_MASK); 333 334 addr = __SHIFTIN(addr_lo, BWI_DESC32_A_ADDR_MASK) | 335 __SHIFTIN(BWI_DESC32_A_FUNC_TXRX, BWI_DESC32_A_FUNC_MASK); 336 337 ctrl = __SHIFTIN(buf_len, BWI_DESC32_C_BUFLEN_MASK) | 338 __SHIFTIN(addr_hi, BWI_DESC32_C_ADDRHI_MASK); 339 if (desc_idx == ndesc - 1) 340 ctrl |= BWI_DESC32_C_EOR; 341 if (tx) { 342 /* XXX */ 343 ctrl |= BWI_DESC32_C_FRAME_START | 344 BWI_DESC32_C_FRAME_END | 345 BWI_DESC32_C_INTR; 346 } 347 348 desc->addr = htole32(addr); 349 desc->ctrl = htole32(ctrl); 350 } 351 352 int 353 bwi_attach(struct bwi_softc *sc) 354 { 355 struct ieee80211com *ic; 356 device_t dev = sc->sc_dev; 357 struct ifnet *ifp; 358 struct bwi_mac *mac; 359 struct bwi_phy *phy; 360 int i, error; 361 uint8_t bands; 362 uint8_t macaddr[IEEE80211_ADDR_LEN]; 363 364 BWI_LOCK_INIT(sc); 365 366 /* 367 * Initialize taskq and various tasks 368 */ 369 sc->sc_tq = taskqueue_create("bwi_taskq", M_NOWAIT | M_ZERO, 370 taskqueue_thread_enqueue, &sc->sc_tq); 371 taskqueue_start_threads(&sc->sc_tq, 1, PI_NET, "%s taskq", 372 device_get_nameunit(dev)); 373 TASK_INIT(&sc->sc_restart_task, 0, bwi_restart, sc); 374 375 callout_init_mtx(&sc->sc_calib_ch, &sc->sc_mtx, 0); 376 377 /* 378 * Initialize sysctl variables 379 */ 380 sc->sc_fw_version = BWI_FW_VERSION3; 381 sc->sc_led_idle = (2350 * hz) / 1000; 382 sc->sc_led_blink = 1; 383 sc->sc_txpwr_calib = 1; 384 #ifdef BWI_DEBUG 385 sc->sc_debug = bwi_debug; 386 #endif 387 bwi_power_on(sc, 1); 388 389 error = bwi_bbp_attach(sc); 390 if (error) 391 goto fail; 392 393 error = bwi_bbp_power_on(sc, BWI_CLOCK_MODE_FAST); 394 if (error) 395 goto fail; 396 397 if (BWI_REGWIN_EXIST(&sc->sc_com_regwin)) { 398 error = bwi_set_clock_delay(sc); 399 if (error) 400 goto fail; 401 402 error = bwi_set_clock_mode(sc, BWI_CLOCK_MODE_FAST); 403 if (error) 404 goto fail; 405 406 error = bwi_get_pwron_delay(sc); 407 if (error) 408 goto fail; 409 } 410 411 error = bwi_bus_attach(sc); 412 if (error) 413 goto fail; 414 415 bwi_get_card_flags(sc); 416 417 bwi_led_attach(sc); 418 419 for (i = 0; i < sc->sc_nmac; ++i) { 420 struct bwi_regwin *old; 421 422 mac = &sc->sc_mac[i]; 423 error = bwi_regwin_switch(sc, &mac->mac_regwin, &old); 424 if (error) 425 goto fail; 426 427 error = bwi_mac_lateattach(mac); 428 if (error) 429 goto fail; 430 431 error = bwi_regwin_switch(sc, old, NULL); 432 if (error) 433 goto fail; 434 } 435 436 /* 437 * XXX First MAC is known to exist 438 * TODO2 439 */ 440 mac = &sc->sc_mac[0]; 441 phy = &mac->mac_phy; 442 443 bwi_bbp_power_off(sc); 444 445 error = bwi_dma_alloc(sc); 446 if (error) 447 goto fail; 448 449 error = bwi_mac_fw_alloc(mac); 450 if (error) 451 goto fail; 452 453 ifp = sc->sc_ifp = if_alloc(IFT_IEEE80211); 454 if (ifp == NULL) { 455 device_printf(dev, "can not if_alloc()\n"); 456 error = ENOSPC; 457 goto fail; 458 } 459 ic = ifp->if_l2com; 460 461 /* set these up early for if_printf use */ 462 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 463 464 ifp->if_softc = sc; 465 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 466 ifp->if_init = bwi_init; 467 ifp->if_ioctl = bwi_ioctl; 468 ifp->if_start = bwi_start; 469 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen); 470 ifp->if_snd.ifq_drv_maxlen = ifqmaxlen; 471 IFQ_SET_READY(&ifp->if_snd); 472 callout_init_mtx(&sc->sc_watchdog_timer, &sc->sc_mtx, 0); 473 474 /* 475 * Setup ratesets, phytype, channels and get MAC address 476 */ 477 bands = 0; 478 if (phy->phy_mode == IEEE80211_MODE_11B || 479 phy->phy_mode == IEEE80211_MODE_11G) { 480 setbit(&bands, IEEE80211_MODE_11B); 481 if (phy->phy_mode == IEEE80211_MODE_11B) { 482 ic->ic_phytype = IEEE80211_T_DS; 483 } else { 484 ic->ic_phytype = IEEE80211_T_OFDM; 485 setbit(&bands, IEEE80211_MODE_11G); 486 } 487 488 bwi_get_eaddr(sc, BWI_SPROM_11BG_EADDR, macaddr); 489 if (IEEE80211_IS_MULTICAST(macaddr)) { 490 bwi_get_eaddr(sc, BWI_SPROM_11A_EADDR, macaddr); 491 if (IEEE80211_IS_MULTICAST(macaddr)) { 492 device_printf(dev, 493 "invalid MAC address: %6D\n", 494 macaddr, ":"); 495 } 496 } 497 } else if (phy->phy_mode == IEEE80211_MODE_11A) { 498 /* TODO:11A */ 499 setbit(&bands, IEEE80211_MODE_11A); 500 error = ENXIO; 501 goto fail; 502 } else { 503 panic("unknown phymode %d\n", phy->phy_mode); 504 } 505 506 /* Get locale */ 507 sc->sc_locale = __SHIFTOUT(bwi_read_sprom(sc, BWI_SPROM_CARD_INFO), 508 BWI_SPROM_CARD_INFO_LOCALE); 509 DPRINTF(sc, BWI_DBG_ATTACH, "locale: %d\n", sc->sc_locale); 510 /* XXX use locale */ 511 ieee80211_init_channels(ic, NULL, &bands); 512 513 ic->ic_ifp = ifp; 514 ic->ic_softc = sc; 515 ic->ic_name = device_get_nameunit(dev); 516 ic->ic_caps = IEEE80211_C_STA | 517 IEEE80211_C_SHSLOT | 518 IEEE80211_C_SHPREAMBLE | 519 IEEE80211_C_WPA | 520 IEEE80211_C_BGSCAN | 521 IEEE80211_C_MONITOR; 522 ic->ic_opmode = IEEE80211_M_STA; 523 ieee80211_ifattach(ic, macaddr); 524 525 ic->ic_headroom = sizeof(struct bwi_txbuf_hdr); 526 527 /* override default methods */ 528 ic->ic_vap_create = bwi_vap_create; 529 ic->ic_vap_delete = bwi_vap_delete; 530 ic->ic_raw_xmit = bwi_raw_xmit; 531 ic->ic_updateslot = bwi_updateslot; 532 ic->ic_scan_start = bwi_scan_start; 533 ic->ic_scan_end = bwi_scan_end; 534 ic->ic_set_channel = bwi_set_channel; 535 536 sc->sc_rates = ieee80211_get_ratetable(ic->ic_curchan); 537 538 ieee80211_radiotap_attach(ic, 539 &sc->sc_tx_th.wt_ihdr, sizeof(sc->sc_tx_th), 540 BWI_TX_RADIOTAP_PRESENT, 541 &sc->sc_rx_th.wr_ihdr, sizeof(sc->sc_rx_th), 542 BWI_RX_RADIOTAP_PRESENT); 543 544 /* 545 * Add sysctl nodes 546 */ 547 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 548 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 549 "fw_version", CTLFLAG_RD, &sc->sc_fw_version, 0, 550 "Firmware version"); 551 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 552 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 553 "led_idle", CTLFLAG_RW, &sc->sc_led_idle, 0, 554 "# ticks before LED enters idle state"); 555 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 556 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 557 "led_blink", CTLFLAG_RW, &sc->sc_led_blink, 0, 558 "Allow LED to blink"); 559 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 560 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 561 "txpwr_calib", CTLFLAG_RW, &sc->sc_txpwr_calib, 0, 562 "Enable software TX power calibration"); 563 #ifdef BWI_DEBUG 564 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), 565 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 566 "debug", CTLFLAG_RW, &sc->sc_debug, 0, "Debug flags"); 567 #endif 568 if (bootverbose) 569 ieee80211_announce(ic); 570 571 return (0); 572 fail: 573 BWI_LOCK_DESTROY(sc); 574 return (error); 575 } 576 577 int 578 bwi_detach(struct bwi_softc *sc) 579 { 580 struct ifnet *ifp = sc->sc_ifp; 581 struct ieee80211com *ic = ifp->if_l2com; 582 int i; 583 584 bwi_stop(sc, 1); 585 callout_drain(&sc->sc_led_blink_ch); 586 callout_drain(&sc->sc_calib_ch); 587 callout_drain(&sc->sc_watchdog_timer); 588 ieee80211_ifdetach(ic); 589 590 for (i = 0; i < sc->sc_nmac; ++i) 591 bwi_mac_detach(&sc->sc_mac[i]); 592 bwi_dma_free(sc); 593 if_free(ifp); 594 taskqueue_free(sc->sc_tq); 595 596 BWI_LOCK_DESTROY(sc); 597 598 return (0); 599 } 600 601 static struct ieee80211vap * 602 bwi_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 603 enum ieee80211_opmode opmode, int flags, 604 const uint8_t bssid[IEEE80211_ADDR_LEN], 605 const uint8_t mac[IEEE80211_ADDR_LEN]) 606 { 607 struct bwi_vap *bvp; 608 struct ieee80211vap *vap; 609 610 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */ 611 return NULL; 612 bvp = (struct bwi_vap *) malloc(sizeof(struct bwi_vap), 613 M_80211_VAP, M_WAITOK | M_ZERO); 614 if (bvp == NULL) 615 return NULL; 616 vap = &bvp->bv_vap; 617 /* enable s/w bmiss handling for sta mode */ 618 ieee80211_vap_setup(ic, vap, name, unit, opmode, 619 flags | IEEE80211_CLONE_NOBEACONS, bssid, mac); 620 621 /* override default methods */ 622 bvp->bv_newstate = vap->iv_newstate; 623 vap->iv_newstate = bwi_newstate; 624 #if 0 625 vap->iv_update_beacon = bwi_beacon_update; 626 #endif 627 ieee80211_ratectl_init(vap); 628 629 /* complete setup */ 630 ieee80211_vap_attach(vap, bwi_media_change, ieee80211_media_status); 631 ic->ic_opmode = opmode; 632 return vap; 633 } 634 635 static void 636 bwi_vap_delete(struct ieee80211vap *vap) 637 { 638 struct bwi_vap *bvp = BWI_VAP(vap); 639 640 ieee80211_ratectl_deinit(vap); 641 ieee80211_vap_detach(vap); 642 free(bvp, M_80211_VAP); 643 } 644 645 void 646 bwi_suspend(struct bwi_softc *sc) 647 { 648 bwi_stop(sc, 1); 649 } 650 651 void 652 bwi_resume(struct bwi_softc *sc) 653 { 654 struct ifnet *ifp = sc->sc_ifp; 655 656 if (ifp->if_flags & IFF_UP) 657 bwi_init(sc); 658 } 659 660 int 661 bwi_shutdown(struct bwi_softc *sc) 662 { 663 bwi_stop(sc, 1); 664 return 0; 665 } 666 667 static void 668 bwi_power_on(struct bwi_softc *sc, int with_pll) 669 { 670 uint32_t gpio_in, gpio_out, gpio_en; 671 uint16_t status; 672 673 gpio_in = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_IN, 4); 674 if (gpio_in & BWI_PCIM_GPIO_PWR_ON) 675 goto back; 676 677 gpio_out = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, 4); 678 gpio_en = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, 4); 679 680 gpio_out |= BWI_PCIM_GPIO_PWR_ON; 681 gpio_en |= BWI_PCIM_GPIO_PWR_ON; 682 if (with_pll) { 683 /* Turn off PLL first */ 684 gpio_out |= BWI_PCIM_GPIO_PLL_PWR_OFF; 685 gpio_en |= BWI_PCIM_GPIO_PLL_PWR_OFF; 686 } 687 688 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, gpio_out, 4); 689 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, gpio_en, 4); 690 DELAY(1000); 691 692 if (with_pll) { 693 /* Turn on PLL */ 694 gpio_out &= ~BWI_PCIM_GPIO_PLL_PWR_OFF; 695 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, gpio_out, 4); 696 DELAY(5000); 697 } 698 699 back: 700 /* Clear "Signaled Target Abort" */ 701 status = pci_read_config(sc->sc_dev, PCIR_STATUS, 2); 702 status &= ~PCIM_STATUS_STABORT; 703 pci_write_config(sc->sc_dev, PCIR_STATUS, status, 2); 704 } 705 706 static int 707 bwi_power_off(struct bwi_softc *sc, int with_pll) 708 { 709 uint32_t gpio_out, gpio_en; 710 711 pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_IN, 4); /* dummy read */ 712 gpio_out = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, 4); 713 gpio_en = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, 4); 714 715 gpio_out &= ~BWI_PCIM_GPIO_PWR_ON; 716 gpio_en |= BWI_PCIM_GPIO_PWR_ON; 717 if (with_pll) { 718 gpio_out |= BWI_PCIM_GPIO_PLL_PWR_OFF; 719 gpio_en |= BWI_PCIM_GPIO_PLL_PWR_OFF; 720 } 721 722 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, gpio_out, 4); 723 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, gpio_en, 4); 724 return 0; 725 } 726 727 int 728 bwi_regwin_switch(struct bwi_softc *sc, struct bwi_regwin *rw, 729 struct bwi_regwin **old_rw) 730 { 731 int error; 732 733 if (old_rw != NULL) 734 *old_rw = NULL; 735 736 if (!BWI_REGWIN_EXIST(rw)) 737 return EINVAL; 738 739 if (sc->sc_cur_regwin != rw) { 740 error = bwi_regwin_select(sc, rw->rw_id); 741 if (error) { 742 device_printf(sc->sc_dev, "can't select regwin %d\n", 743 rw->rw_id); 744 return error; 745 } 746 } 747 748 if (old_rw != NULL) 749 *old_rw = sc->sc_cur_regwin; 750 sc->sc_cur_regwin = rw; 751 return 0; 752 } 753 754 static int 755 bwi_regwin_select(struct bwi_softc *sc, int id) 756 { 757 uint32_t win = BWI_PCIM_REGWIN(id); 758 int i; 759 760 #define RETRY_MAX 50 761 for (i = 0; i < RETRY_MAX; ++i) { 762 pci_write_config(sc->sc_dev, BWI_PCIR_SEL_REGWIN, win, 4); 763 if (pci_read_config(sc->sc_dev, BWI_PCIR_SEL_REGWIN, 4) == win) 764 return 0; 765 DELAY(10); 766 } 767 #undef RETRY_MAX 768 769 return ENXIO; 770 } 771 772 static void 773 bwi_regwin_info(struct bwi_softc *sc, uint16_t *type, uint8_t *rev) 774 { 775 uint32_t val; 776 777 val = CSR_READ_4(sc, BWI_ID_HI); 778 *type = BWI_ID_HI_REGWIN_TYPE(val); 779 *rev = BWI_ID_HI_REGWIN_REV(val); 780 781 DPRINTF(sc, BWI_DBG_ATTACH, "regwin: type 0x%03x, rev %d, " 782 "vendor 0x%04x\n", *type, *rev, 783 __SHIFTOUT(val, BWI_ID_HI_REGWIN_VENDOR_MASK)); 784 } 785 786 static int 787 bwi_bbp_attach(struct bwi_softc *sc) 788 { 789 #define N(arr) (int)(sizeof(arr) / sizeof(arr[0])) 790 uint16_t bbp_id, rw_type; 791 uint8_t rw_rev; 792 uint32_t info; 793 int error, nregwin, i; 794 795 /* 796 * Get 0th regwin information 797 * NOTE: 0th regwin should exist 798 */ 799 error = bwi_regwin_select(sc, 0); 800 if (error) { 801 device_printf(sc->sc_dev, "can't select regwin 0\n"); 802 return error; 803 } 804 bwi_regwin_info(sc, &rw_type, &rw_rev); 805 806 /* 807 * Find out BBP id 808 */ 809 bbp_id = 0; 810 info = 0; 811 if (rw_type == BWI_REGWIN_T_COM) { 812 info = CSR_READ_4(sc, BWI_INFO); 813 bbp_id = __SHIFTOUT(info, BWI_INFO_BBPID_MASK); 814 815 BWI_CREATE_REGWIN(&sc->sc_com_regwin, 0, rw_type, rw_rev); 816 817 sc->sc_cap = CSR_READ_4(sc, BWI_CAPABILITY); 818 } else { 819 for (i = 0; i < N(bwi_bbpid_map); ++i) { 820 if (sc->sc_pci_did >= bwi_bbpid_map[i].did_min && 821 sc->sc_pci_did <= bwi_bbpid_map[i].did_max) { 822 bbp_id = bwi_bbpid_map[i].bbp_id; 823 break; 824 } 825 } 826 if (bbp_id == 0) { 827 device_printf(sc->sc_dev, "no BBP id for device id " 828 "0x%04x\n", sc->sc_pci_did); 829 return ENXIO; 830 } 831 832 info = __SHIFTIN(sc->sc_pci_revid, BWI_INFO_BBPREV_MASK) | 833 __SHIFTIN(0, BWI_INFO_BBPPKG_MASK); 834 } 835 836 /* 837 * Find out number of regwins 838 */ 839 nregwin = 0; 840 if (rw_type == BWI_REGWIN_T_COM && rw_rev >= 4) { 841 nregwin = __SHIFTOUT(info, BWI_INFO_NREGWIN_MASK); 842 } else { 843 for (i = 0; i < N(bwi_regwin_count); ++i) { 844 if (bwi_regwin_count[i].bbp_id == bbp_id) { 845 nregwin = bwi_regwin_count[i].nregwin; 846 break; 847 } 848 } 849 if (nregwin == 0) { 850 device_printf(sc->sc_dev, "no number of win for " 851 "BBP id 0x%04x\n", bbp_id); 852 return ENXIO; 853 } 854 } 855 856 /* Record BBP id/rev for later using */ 857 sc->sc_bbp_id = bbp_id; 858 sc->sc_bbp_rev = __SHIFTOUT(info, BWI_INFO_BBPREV_MASK); 859 sc->sc_bbp_pkg = __SHIFTOUT(info, BWI_INFO_BBPPKG_MASK); 860 device_printf(sc->sc_dev, "BBP: id 0x%04x, rev 0x%x, pkg %d\n", 861 sc->sc_bbp_id, sc->sc_bbp_rev, sc->sc_bbp_pkg); 862 863 DPRINTF(sc, BWI_DBG_ATTACH, "nregwin %d, cap 0x%08x\n", 864 nregwin, sc->sc_cap); 865 866 /* 867 * Create rest of the regwins 868 */ 869 870 /* Don't re-create common regwin, if it is already created */ 871 i = BWI_REGWIN_EXIST(&sc->sc_com_regwin) ? 1 : 0; 872 873 for (; i < nregwin; ++i) { 874 /* 875 * Get regwin information 876 */ 877 error = bwi_regwin_select(sc, i); 878 if (error) { 879 device_printf(sc->sc_dev, 880 "can't select regwin %d\n", i); 881 return error; 882 } 883 bwi_regwin_info(sc, &rw_type, &rw_rev); 884 885 /* 886 * Try attach: 887 * 1) Bus (PCI/PCIE) regwin 888 * 2) MAC regwin 889 * Ignore rest types of regwin 890 */ 891 if (rw_type == BWI_REGWIN_T_BUSPCI || 892 rw_type == BWI_REGWIN_T_BUSPCIE) { 893 if (BWI_REGWIN_EXIST(&sc->sc_bus_regwin)) { 894 device_printf(sc->sc_dev, 895 "bus regwin already exists\n"); 896 } else { 897 BWI_CREATE_REGWIN(&sc->sc_bus_regwin, i, 898 rw_type, rw_rev); 899 } 900 } else if (rw_type == BWI_REGWIN_T_MAC) { 901 /* XXX ignore return value */ 902 bwi_mac_attach(sc, i, rw_rev); 903 } 904 } 905 906 /* At least one MAC shold exist */ 907 if (!BWI_REGWIN_EXIST(&sc->sc_mac[0].mac_regwin)) { 908 device_printf(sc->sc_dev, "no MAC was found\n"); 909 return ENXIO; 910 } 911 KASSERT(sc->sc_nmac > 0, ("no mac's")); 912 913 /* Bus regwin must exist */ 914 if (!BWI_REGWIN_EXIST(&sc->sc_bus_regwin)) { 915 device_printf(sc->sc_dev, "no bus regwin was found\n"); 916 return ENXIO; 917 } 918 919 /* Start with first MAC */ 920 error = bwi_regwin_switch(sc, &sc->sc_mac[0].mac_regwin, NULL); 921 if (error) 922 return error; 923 924 return 0; 925 #undef N 926 } 927 928 int 929 bwi_bus_init(struct bwi_softc *sc, struct bwi_mac *mac) 930 { 931 struct bwi_regwin *old, *bus; 932 uint32_t val; 933 int error; 934 935 bus = &sc->sc_bus_regwin; 936 KASSERT(sc->sc_cur_regwin == &mac->mac_regwin, ("not cur regwin")); 937 938 /* 939 * Tell bus to generate requested interrupts 940 */ 941 if (bus->rw_rev < 6 && bus->rw_type == BWI_REGWIN_T_BUSPCI) { 942 /* 943 * NOTE: Read BWI_FLAGS from MAC regwin 944 */ 945 val = CSR_READ_4(sc, BWI_FLAGS); 946 947 error = bwi_regwin_switch(sc, bus, &old); 948 if (error) 949 return error; 950 951 CSR_SETBITS_4(sc, BWI_INTRVEC, (val & BWI_FLAGS_INTR_MASK)); 952 } else { 953 uint32_t mac_mask; 954 955 mac_mask = 1 << mac->mac_id; 956 957 error = bwi_regwin_switch(sc, bus, &old); 958 if (error) 959 return error; 960 961 val = pci_read_config(sc->sc_dev, BWI_PCIR_INTCTL, 4); 962 val |= mac_mask << 8; 963 pci_write_config(sc->sc_dev, BWI_PCIR_INTCTL, val, 4); 964 } 965 966 if (sc->sc_flags & BWI_F_BUS_INITED) 967 goto back; 968 969 if (bus->rw_type == BWI_REGWIN_T_BUSPCI) { 970 /* 971 * Enable prefetch and burst 972 */ 973 CSR_SETBITS_4(sc, BWI_BUS_CONFIG, 974 BWI_BUS_CONFIG_PREFETCH | BWI_BUS_CONFIG_BURST); 975 976 if (bus->rw_rev < 5) { 977 struct bwi_regwin *com = &sc->sc_com_regwin; 978 979 /* 980 * Configure timeouts for bus operation 981 */ 982 983 /* 984 * Set service timeout and request timeout 985 */ 986 CSR_SETBITS_4(sc, BWI_CONF_LO, 987 __SHIFTIN(BWI_CONF_LO_SERVTO, BWI_CONF_LO_SERVTO_MASK) | 988 __SHIFTIN(BWI_CONF_LO_REQTO, BWI_CONF_LO_REQTO_MASK)); 989 990 /* 991 * If there is common regwin, we switch to that regwin 992 * and switch back to bus regwin once we have done. 993 */ 994 if (BWI_REGWIN_EXIST(com)) { 995 error = bwi_regwin_switch(sc, com, NULL); 996 if (error) 997 return error; 998 } 999 1000 /* Let bus know what we have changed */ 1001 CSR_WRITE_4(sc, BWI_BUS_ADDR, BWI_BUS_ADDR_MAGIC); 1002 CSR_READ_4(sc, BWI_BUS_ADDR); /* Flush */ 1003 CSR_WRITE_4(sc, BWI_BUS_DATA, 0); 1004 CSR_READ_4(sc, BWI_BUS_DATA); /* Flush */ 1005 1006 if (BWI_REGWIN_EXIST(com)) { 1007 error = bwi_regwin_switch(sc, bus, NULL); 1008 if (error) 1009 return error; 1010 } 1011 } else if (bus->rw_rev >= 11) { 1012 /* 1013 * Enable memory read multiple 1014 */ 1015 CSR_SETBITS_4(sc, BWI_BUS_CONFIG, BWI_BUS_CONFIG_MRM); 1016 } 1017 } else { 1018 /* TODO:PCIE */ 1019 } 1020 1021 sc->sc_flags |= BWI_F_BUS_INITED; 1022 back: 1023 return bwi_regwin_switch(sc, old, NULL); 1024 } 1025 1026 static void 1027 bwi_get_card_flags(struct bwi_softc *sc) 1028 { 1029 #define PCI_VENDOR_APPLE 0x106b 1030 #define PCI_VENDOR_DELL 0x1028 1031 sc->sc_card_flags = bwi_read_sprom(sc, BWI_SPROM_CARD_FLAGS); 1032 if (sc->sc_card_flags == 0xffff) 1033 sc->sc_card_flags = 0; 1034 1035 if (sc->sc_pci_subvid == PCI_VENDOR_DELL && 1036 sc->sc_bbp_id == BWI_BBPID_BCM4301 && 1037 sc->sc_pci_revid == 0x74) 1038 sc->sc_card_flags |= BWI_CARD_F_BT_COEXIST; 1039 1040 if (sc->sc_pci_subvid == PCI_VENDOR_APPLE && 1041 sc->sc_pci_subdid == 0x4e && /* XXX */ 1042 sc->sc_pci_revid > 0x40) 1043 sc->sc_card_flags |= BWI_CARD_F_PA_GPIO9; 1044 1045 DPRINTF(sc, BWI_DBG_ATTACH, "card flags 0x%04x\n", sc->sc_card_flags); 1046 #undef PCI_VENDOR_DELL 1047 #undef PCI_VENDOR_APPLE 1048 } 1049 1050 static void 1051 bwi_get_eaddr(struct bwi_softc *sc, uint16_t eaddr_ofs, uint8_t *eaddr) 1052 { 1053 int i; 1054 1055 for (i = 0; i < 3; ++i) { 1056 *((uint16_t *)eaddr + i) = 1057 htobe16(bwi_read_sprom(sc, eaddr_ofs + 2 * i)); 1058 } 1059 } 1060 1061 static void 1062 bwi_get_clock_freq(struct bwi_softc *sc, struct bwi_clock_freq *freq) 1063 { 1064 struct bwi_regwin *com; 1065 uint32_t val; 1066 u_int div; 1067 int src; 1068 1069 bzero(freq, sizeof(*freq)); 1070 com = &sc->sc_com_regwin; 1071 1072 KASSERT(BWI_REGWIN_EXIST(com), ("regwin does not exist")); 1073 KASSERT(sc->sc_cur_regwin == com, ("wrong regwin")); 1074 KASSERT(sc->sc_cap & BWI_CAP_CLKMODE, ("wrong clock mode")); 1075 1076 /* 1077 * Calculate clock frequency 1078 */ 1079 src = -1; 1080 div = 0; 1081 if (com->rw_rev < 6) { 1082 val = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, 4); 1083 if (val & BWI_PCIM_GPIO_OUT_CLKSRC) { 1084 src = BWI_CLKSRC_PCI; 1085 div = 64; 1086 } else { 1087 src = BWI_CLKSRC_CS_OSC; 1088 div = 32; 1089 } 1090 } else if (com->rw_rev < 10) { 1091 val = CSR_READ_4(sc, BWI_CLOCK_CTRL); 1092 1093 src = __SHIFTOUT(val, BWI_CLOCK_CTRL_CLKSRC); 1094 if (src == BWI_CLKSRC_LP_OSC) { 1095 div = 1; 1096 } else { 1097 div = (__SHIFTOUT(val, BWI_CLOCK_CTRL_FDIV) + 1) << 2; 1098 1099 /* Unknown source */ 1100 if (src >= BWI_CLKSRC_MAX) 1101 src = BWI_CLKSRC_CS_OSC; 1102 } 1103 } else { 1104 val = CSR_READ_4(sc, BWI_CLOCK_INFO); 1105 1106 src = BWI_CLKSRC_CS_OSC; 1107 div = (__SHIFTOUT(val, BWI_CLOCK_INFO_FDIV) + 1) << 2; 1108 } 1109 1110 KASSERT(src >= 0 && src < BWI_CLKSRC_MAX, ("bad src %d", src)); 1111 KASSERT(div != 0, ("div zero")); 1112 1113 DPRINTF(sc, BWI_DBG_ATTACH, "clksrc %s\n", 1114 src == BWI_CLKSRC_PCI ? "PCI" : 1115 (src == BWI_CLKSRC_LP_OSC ? "LP_OSC" : "CS_OSC")); 1116 1117 freq->clkfreq_min = bwi_clkfreq[src].freq_min / div; 1118 freq->clkfreq_max = bwi_clkfreq[src].freq_max / div; 1119 1120 DPRINTF(sc, BWI_DBG_ATTACH, "clkfreq min %u, max %u\n", 1121 freq->clkfreq_min, freq->clkfreq_max); 1122 } 1123 1124 static int 1125 bwi_set_clock_mode(struct bwi_softc *sc, enum bwi_clock_mode clk_mode) 1126 { 1127 struct bwi_regwin *old, *com; 1128 uint32_t clk_ctrl, clk_src; 1129 int error, pwr_off = 0; 1130 1131 com = &sc->sc_com_regwin; 1132 if (!BWI_REGWIN_EXIST(com)) 1133 return 0; 1134 1135 if (com->rw_rev >= 10 || com->rw_rev < 6) 1136 return 0; 1137 1138 /* 1139 * For common regwin whose rev is [6, 10), the chip 1140 * must be capable to change clock mode. 1141 */ 1142 if ((sc->sc_cap & BWI_CAP_CLKMODE) == 0) 1143 return 0; 1144 1145 error = bwi_regwin_switch(sc, com, &old); 1146 if (error) 1147 return error; 1148 1149 if (clk_mode == BWI_CLOCK_MODE_FAST) 1150 bwi_power_on(sc, 0); /* Don't turn on PLL */ 1151 1152 clk_ctrl = CSR_READ_4(sc, BWI_CLOCK_CTRL); 1153 clk_src = __SHIFTOUT(clk_ctrl, BWI_CLOCK_CTRL_CLKSRC); 1154 1155 switch (clk_mode) { 1156 case BWI_CLOCK_MODE_FAST: 1157 clk_ctrl &= ~BWI_CLOCK_CTRL_SLOW; 1158 clk_ctrl |= BWI_CLOCK_CTRL_IGNPLL; 1159 break; 1160 case BWI_CLOCK_MODE_SLOW: 1161 clk_ctrl |= BWI_CLOCK_CTRL_SLOW; 1162 break; 1163 case BWI_CLOCK_MODE_DYN: 1164 clk_ctrl &= ~(BWI_CLOCK_CTRL_SLOW | 1165 BWI_CLOCK_CTRL_IGNPLL | 1166 BWI_CLOCK_CTRL_NODYN); 1167 if (clk_src != BWI_CLKSRC_CS_OSC) { 1168 clk_ctrl |= BWI_CLOCK_CTRL_NODYN; 1169 pwr_off = 1; 1170 } 1171 break; 1172 } 1173 CSR_WRITE_4(sc, BWI_CLOCK_CTRL, clk_ctrl); 1174 1175 if (pwr_off) 1176 bwi_power_off(sc, 0); /* Leave PLL as it is */ 1177 1178 return bwi_regwin_switch(sc, old, NULL); 1179 } 1180 1181 static int 1182 bwi_set_clock_delay(struct bwi_softc *sc) 1183 { 1184 struct bwi_regwin *old, *com; 1185 int error; 1186 1187 com = &sc->sc_com_regwin; 1188 if (!BWI_REGWIN_EXIST(com)) 1189 return 0; 1190 1191 error = bwi_regwin_switch(sc, com, &old); 1192 if (error) 1193 return error; 1194 1195 if (sc->sc_bbp_id == BWI_BBPID_BCM4321) { 1196 if (sc->sc_bbp_rev == 0) 1197 CSR_WRITE_4(sc, BWI_CONTROL, BWI_CONTROL_MAGIC0); 1198 else if (sc->sc_bbp_rev == 1) 1199 CSR_WRITE_4(sc, BWI_CONTROL, BWI_CONTROL_MAGIC1); 1200 } 1201 1202 if (sc->sc_cap & BWI_CAP_CLKMODE) { 1203 if (com->rw_rev >= 10) { 1204 CSR_FILT_SETBITS_4(sc, BWI_CLOCK_INFO, 0xffff, 0x40000); 1205 } else { 1206 struct bwi_clock_freq freq; 1207 1208 bwi_get_clock_freq(sc, &freq); 1209 CSR_WRITE_4(sc, BWI_PLL_ON_DELAY, 1210 howmany(freq.clkfreq_max * 150, 1000000)); 1211 CSR_WRITE_4(sc, BWI_FREQ_SEL_DELAY, 1212 howmany(freq.clkfreq_max * 15, 1000000)); 1213 } 1214 } 1215 1216 return bwi_regwin_switch(sc, old, NULL); 1217 } 1218 1219 static void 1220 bwi_init(void *xsc) 1221 { 1222 struct bwi_softc *sc = xsc; 1223 struct ifnet *ifp = sc->sc_ifp; 1224 struct ieee80211com *ic = ifp->if_l2com; 1225 1226 BWI_LOCK(sc); 1227 bwi_init_statechg(sc, 1); 1228 BWI_UNLOCK(sc); 1229 1230 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1231 ieee80211_start_all(ic); /* start all vap's */ 1232 } 1233 1234 static void 1235 bwi_init_statechg(struct bwi_softc *sc, int statechg) 1236 { 1237 struct ifnet *ifp = sc->sc_ifp; 1238 struct bwi_mac *mac; 1239 int error; 1240 1241 bwi_stop_locked(sc, statechg); 1242 1243 bwi_bbp_power_on(sc, BWI_CLOCK_MODE_FAST); 1244 1245 /* TODO: 2 MAC */ 1246 1247 mac = &sc->sc_mac[0]; 1248 error = bwi_regwin_switch(sc, &mac->mac_regwin, NULL); 1249 if (error) { 1250 if_printf(ifp, "%s: error %d on regwin switch\n", 1251 __func__, error); 1252 goto bad; 1253 } 1254 error = bwi_mac_init(mac); 1255 if (error) { 1256 if_printf(ifp, "%s: error %d on MAC init\n", __func__, error); 1257 goto bad; 1258 } 1259 1260 bwi_bbp_power_on(sc, BWI_CLOCK_MODE_DYN); 1261 1262 bwi_set_bssid(sc, bwi_zero_addr); /* Clear BSSID */ 1263 bwi_set_addr_filter(sc, BWI_ADDR_FILTER_MYADDR, IF_LLADDR(ifp)); 1264 1265 bwi_mac_reset_hwkeys(mac); 1266 1267 if ((mac->mac_flags & BWI_MAC_F_HAS_TXSTATS) == 0) { 1268 int i; 1269 1270 #define NRETRY 1000 1271 /* 1272 * Drain any possible pending TX status 1273 */ 1274 for (i = 0; i < NRETRY; ++i) { 1275 if ((CSR_READ_4(sc, BWI_TXSTATUS0) & 1276 BWI_TXSTATUS0_VALID) == 0) 1277 break; 1278 CSR_READ_4(sc, BWI_TXSTATUS1); 1279 } 1280 if (i == NRETRY) 1281 if_printf(ifp, "%s: can't drain TX status\n", __func__); 1282 #undef NRETRY 1283 } 1284 1285 if (mac->mac_phy.phy_mode == IEEE80211_MODE_11G) 1286 bwi_mac_updateslot(mac, 1); 1287 1288 /* Start MAC */ 1289 error = bwi_mac_start(mac); 1290 if (error) { 1291 if_printf(ifp, "%s: error %d starting MAC\n", __func__, error); 1292 goto bad; 1293 } 1294 1295 /* Clear stop flag before enabling interrupt */ 1296 sc->sc_flags &= ~BWI_F_STOP; 1297 1298 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1299 callout_reset(&sc->sc_watchdog_timer, hz, bwi_watchdog, sc); 1300 1301 /* Enable intrs */ 1302 bwi_enable_intrs(sc, BWI_INIT_INTRS); 1303 return; 1304 bad: 1305 bwi_stop_locked(sc, 1); 1306 } 1307 1308 static int 1309 bwi_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1310 { 1311 #define IS_RUNNING(ifp) \ 1312 ((ifp->if_flags & IFF_UP) && (ifp->if_drv_flags & IFF_DRV_RUNNING)) 1313 struct bwi_softc *sc = ifp->if_softc; 1314 struct ieee80211com *ic = ifp->if_l2com; 1315 struct ifreq *ifr = (struct ifreq *) data; 1316 int error = 0, startall = 0; 1317 1318 switch (cmd) { 1319 case SIOCSIFFLAGS: 1320 BWI_LOCK(sc); 1321 if (IS_RUNNING(ifp)) { 1322 struct bwi_mac *mac; 1323 int promisc = -1; 1324 1325 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 1326 ("current regwin type %d", 1327 sc->sc_cur_regwin->rw_type)); 1328 mac = (struct bwi_mac *)sc->sc_cur_regwin; 1329 1330 if ((ifp->if_flags & IFF_PROMISC) && 1331 (sc->sc_flags & BWI_F_PROMISC) == 0) { 1332 promisc = 1; 1333 sc->sc_flags |= BWI_F_PROMISC; 1334 } else if ((ifp->if_flags & IFF_PROMISC) == 0 && 1335 (sc->sc_flags & BWI_F_PROMISC)) { 1336 promisc = 0; 1337 sc->sc_flags &= ~BWI_F_PROMISC; 1338 } 1339 1340 if (promisc >= 0) 1341 bwi_mac_set_promisc(mac, promisc); 1342 } 1343 1344 if (ifp->if_flags & IFF_UP) { 1345 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 1346 bwi_init_statechg(sc, 1); 1347 startall = 1; 1348 } 1349 } else { 1350 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1351 bwi_stop_locked(sc, 1); 1352 } 1353 BWI_UNLOCK(sc); 1354 if (startall) 1355 ieee80211_start_all(ic); 1356 break; 1357 case SIOCGIFMEDIA: 1358 error = ifmedia_ioctl(ifp, ifr, &ic->ic_media, cmd); 1359 break; 1360 case SIOCGIFADDR: 1361 error = ether_ioctl(ifp, cmd, data); 1362 break; 1363 default: 1364 error = EINVAL; 1365 break; 1366 } 1367 return error; 1368 #undef IS_RUNNING 1369 } 1370 1371 static void 1372 bwi_start(struct ifnet *ifp) 1373 { 1374 struct bwi_softc *sc = ifp->if_softc; 1375 1376 BWI_LOCK(sc); 1377 bwi_start_locked(ifp); 1378 BWI_UNLOCK(sc); 1379 } 1380 1381 static void 1382 bwi_start_locked(struct ifnet *ifp) 1383 { 1384 struct bwi_softc *sc = ifp->if_softc; 1385 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING]; 1386 struct ieee80211_frame *wh; 1387 struct ieee80211_node *ni; 1388 struct ieee80211_key *k; 1389 struct mbuf *m; 1390 int trans, idx; 1391 1392 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 1393 return; 1394 1395 trans = 0; 1396 idx = tbd->tbd_idx; 1397 1398 while (tbd->tbd_buf[idx].tb_mbuf == NULL) { 1399 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); /* XXX: LOCK */ 1400 if (m == NULL) 1401 break; 1402 1403 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif; 1404 wh = mtod(m, struct ieee80211_frame *); 1405 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) { 1406 k = ieee80211_crypto_encap(ni, m); 1407 if (k == NULL) { 1408 ieee80211_free_node(ni); 1409 m_freem(m); 1410 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1411 continue; 1412 } 1413 } 1414 wh = NULL; /* Catch any invalid use */ 1415 1416 if (bwi_encap(sc, idx, m, ni) != 0) { 1417 /* 'm' is freed in bwi_encap() if we reach here */ 1418 if (ni != NULL) 1419 ieee80211_free_node(ni); 1420 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1421 continue; 1422 } 1423 1424 trans = 1; 1425 tbd->tbd_used++; 1426 idx = (idx + 1) % BWI_TX_NDESC; 1427 1428 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 1429 1430 if (tbd->tbd_used + BWI_TX_NSPRDESC >= BWI_TX_NDESC) { 1431 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1432 break; 1433 } 1434 } 1435 tbd->tbd_idx = idx; 1436 1437 if (trans) 1438 sc->sc_tx_timer = 5; 1439 } 1440 1441 static int 1442 bwi_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 1443 const struct ieee80211_bpf_params *params) 1444 { 1445 struct ieee80211com *ic = ni->ni_ic; 1446 struct ifnet *ifp = ic->ic_ifp; 1447 struct bwi_softc *sc = ic->ic_softc; 1448 /* XXX wme? */ 1449 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING]; 1450 int idx, error; 1451 1452 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 1453 ieee80211_free_node(ni); 1454 m_freem(m); 1455 return ENETDOWN; 1456 } 1457 1458 BWI_LOCK(sc); 1459 idx = tbd->tbd_idx; 1460 KASSERT(tbd->tbd_buf[idx].tb_mbuf == NULL, ("slot %d not empty", idx)); 1461 if (params == NULL) { 1462 /* 1463 * Legacy path; interpret frame contents to decide 1464 * precisely how to send the frame. 1465 */ 1466 error = bwi_encap(sc, idx, m, ni); 1467 } else { 1468 /* 1469 * Caller supplied explicit parameters to use in 1470 * sending the frame. 1471 */ 1472 error = bwi_encap_raw(sc, idx, m, ni, params); 1473 } 1474 if (error == 0) { 1475 if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1); 1476 if (++tbd->tbd_used + BWI_TX_NSPRDESC >= BWI_TX_NDESC) 1477 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1478 tbd->tbd_idx = (idx + 1) % BWI_TX_NDESC; 1479 sc->sc_tx_timer = 5; 1480 } else { 1481 /* NB: m is reclaimed on encap failure */ 1482 ieee80211_free_node(ni); 1483 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1484 } 1485 BWI_UNLOCK(sc); 1486 return error; 1487 } 1488 1489 static void 1490 bwi_watchdog(void *arg) 1491 { 1492 struct bwi_softc *sc; 1493 struct ifnet *ifp; 1494 1495 sc = arg; 1496 ifp = sc->sc_ifp; 1497 BWI_ASSERT_LOCKED(sc); 1498 if (sc->sc_tx_timer != 0 && --sc->sc_tx_timer == 0) { 1499 if_printf(ifp, "watchdog timeout\n"); 1500 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1501 taskqueue_enqueue(sc->sc_tq, &sc->sc_restart_task); 1502 } 1503 callout_reset(&sc->sc_watchdog_timer, hz, bwi_watchdog, sc); 1504 } 1505 1506 static void 1507 bwi_stop(struct bwi_softc *sc, int statechg) 1508 { 1509 BWI_LOCK(sc); 1510 bwi_stop_locked(sc, statechg); 1511 BWI_UNLOCK(sc); 1512 } 1513 1514 static void 1515 bwi_stop_locked(struct bwi_softc *sc, int statechg) 1516 { 1517 struct ifnet *ifp = sc->sc_ifp; 1518 struct bwi_mac *mac; 1519 int i, error, pwr_off = 0; 1520 1521 BWI_ASSERT_LOCKED(sc); 1522 1523 callout_stop(&sc->sc_calib_ch); 1524 callout_stop(&sc->sc_led_blink_ch); 1525 sc->sc_led_blinking = 0; 1526 sc->sc_flags |= BWI_F_STOP; 1527 1528 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1529 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 1530 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 1531 mac = (struct bwi_mac *)sc->sc_cur_regwin; 1532 1533 bwi_disable_intrs(sc, BWI_ALL_INTRS); 1534 CSR_READ_4(sc, BWI_MAC_INTR_MASK); 1535 bwi_mac_stop(mac); 1536 } 1537 1538 for (i = 0; i < sc->sc_nmac; ++i) { 1539 struct bwi_regwin *old_rw; 1540 1541 mac = &sc->sc_mac[i]; 1542 if ((mac->mac_flags & BWI_MAC_F_INITED) == 0) 1543 continue; 1544 1545 error = bwi_regwin_switch(sc, &mac->mac_regwin, &old_rw); 1546 if (error) 1547 continue; 1548 1549 bwi_mac_shutdown(mac); 1550 pwr_off = 1; 1551 1552 bwi_regwin_switch(sc, old_rw, NULL); 1553 } 1554 1555 if (pwr_off) 1556 bwi_bbp_power_off(sc); 1557 1558 sc->sc_tx_timer = 0; 1559 callout_stop(&sc->sc_watchdog_timer); 1560 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1561 } 1562 1563 void 1564 bwi_intr(void *xsc) 1565 { 1566 struct bwi_softc *sc = xsc; 1567 struct ifnet *ifp = sc->sc_ifp; 1568 struct bwi_mac *mac; 1569 uint32_t intr_status; 1570 uint32_t txrx_intr_status[BWI_TXRX_NRING]; 1571 int i, txrx_error, tx = 0, rx_data = -1; 1572 1573 BWI_LOCK(sc); 1574 1575 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || 1576 (sc->sc_flags & BWI_F_STOP)) { 1577 BWI_UNLOCK(sc); 1578 return; 1579 } 1580 /* 1581 * Get interrupt status 1582 */ 1583 intr_status = CSR_READ_4(sc, BWI_MAC_INTR_STATUS); 1584 if (intr_status == 0xffffffff) { /* Not for us */ 1585 BWI_UNLOCK(sc); 1586 return; 1587 } 1588 1589 DPRINTF(sc, BWI_DBG_INTR, "intr status 0x%08x\n", intr_status); 1590 1591 intr_status &= CSR_READ_4(sc, BWI_MAC_INTR_MASK); 1592 if (intr_status == 0) { /* Nothing is interesting */ 1593 BWI_UNLOCK(sc); 1594 return; 1595 } 1596 1597 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 1598 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 1599 mac = (struct bwi_mac *)sc->sc_cur_regwin; 1600 1601 txrx_error = 0; 1602 DPRINTF(sc, BWI_DBG_INTR, "%s\n", "TX/RX intr"); 1603 for (i = 0; i < BWI_TXRX_NRING; ++i) { 1604 uint32_t mask; 1605 1606 if (BWI_TXRX_IS_RX(i)) 1607 mask = BWI_TXRX_RX_INTRS; 1608 else 1609 mask = BWI_TXRX_TX_INTRS; 1610 1611 txrx_intr_status[i] = 1612 CSR_READ_4(sc, BWI_TXRX_INTR_STATUS(i)) & mask; 1613 1614 _DPRINTF(sc, BWI_DBG_INTR, ", %d 0x%08x", 1615 i, txrx_intr_status[i]); 1616 1617 if (txrx_intr_status[i] & BWI_TXRX_INTR_ERROR) { 1618 if_printf(ifp, 1619 "%s: intr fatal TX/RX (%d) error 0x%08x\n", 1620 __func__, i, txrx_intr_status[i]); 1621 txrx_error = 1; 1622 } 1623 } 1624 _DPRINTF(sc, BWI_DBG_INTR, "%s\n", ""); 1625 1626 /* 1627 * Acknowledge interrupt 1628 */ 1629 CSR_WRITE_4(sc, BWI_MAC_INTR_STATUS, intr_status); 1630 1631 for (i = 0; i < BWI_TXRX_NRING; ++i) 1632 CSR_WRITE_4(sc, BWI_TXRX_INTR_STATUS(i), txrx_intr_status[i]); 1633 1634 /* Disable all interrupts */ 1635 bwi_disable_intrs(sc, BWI_ALL_INTRS); 1636 1637 /* 1638 * http://bcm-specs.sipsolutions.net/Interrupts 1639 * Says for this bit (0x800): 1640 * "Fatal Error 1641 * 1642 * We got this one while testing things when by accident the 1643 * template ram wasn't set to big endian when it should have 1644 * been after writing the initial values. It keeps on being 1645 * triggered, the only way to stop it seems to shut down the 1646 * chip." 1647 * 1648 * Suggesting that we should never get it and if we do we're not 1649 * feeding TX packets into the MAC correctly if we do... Apparently, 1650 * it is valid only on mac version 5 and higher, but I couldn't 1651 * find a reference for that... Since I see them from time to time 1652 * on my card, this suggests an error in the tx path still... 1653 */ 1654 if (intr_status & BWI_INTR_PHY_TXERR) { 1655 if (mac->mac_flags & BWI_MAC_F_PHYE_RESET) { 1656 if_printf(ifp, "%s: intr PHY TX error\n", __func__); 1657 taskqueue_enqueue(sc->sc_tq, &sc->sc_restart_task); 1658 BWI_UNLOCK(sc); 1659 return; 1660 } 1661 } 1662 1663 if (txrx_error) { 1664 /* TODO: reset device */ 1665 } 1666 1667 if (intr_status & BWI_INTR_TBTT) 1668 bwi_mac_config_ps(mac); 1669 1670 if (intr_status & BWI_INTR_EO_ATIM) 1671 if_printf(ifp, "EO_ATIM\n"); 1672 1673 if (intr_status & BWI_INTR_PMQ) { 1674 for (;;) { 1675 if ((CSR_READ_4(sc, BWI_MAC_PS_STATUS) & 0x8) == 0) 1676 break; 1677 } 1678 CSR_WRITE_2(sc, BWI_MAC_PS_STATUS, 0x2); 1679 } 1680 1681 if (intr_status & BWI_INTR_NOISE) 1682 if_printf(ifp, "intr noise\n"); 1683 1684 if (txrx_intr_status[0] & BWI_TXRX_INTR_RX) { 1685 rx_data = sc->sc_rxeof(sc); 1686 if (sc->sc_flags & BWI_F_STOP) { 1687 BWI_UNLOCK(sc); 1688 return; 1689 } 1690 } 1691 1692 if (txrx_intr_status[3] & BWI_TXRX_INTR_RX) { 1693 sc->sc_txeof_status(sc); 1694 tx = 1; 1695 } 1696 1697 if (intr_status & BWI_INTR_TX_DONE) { 1698 bwi_txeof(sc); 1699 tx = 1; 1700 } 1701 1702 /* Re-enable interrupts */ 1703 bwi_enable_intrs(sc, BWI_INIT_INTRS); 1704 1705 if (sc->sc_blink_led != NULL && sc->sc_led_blink) { 1706 int evt = BWI_LED_EVENT_NONE; 1707 1708 if (tx && rx_data > 0) { 1709 if (sc->sc_rx_rate > sc->sc_tx_rate) 1710 evt = BWI_LED_EVENT_RX; 1711 else 1712 evt = BWI_LED_EVENT_TX; 1713 } else if (tx) { 1714 evt = BWI_LED_EVENT_TX; 1715 } else if (rx_data > 0) { 1716 evt = BWI_LED_EVENT_RX; 1717 } else if (rx_data == 0) { 1718 evt = BWI_LED_EVENT_POLL; 1719 } 1720 1721 if (evt != BWI_LED_EVENT_NONE) 1722 bwi_led_event(sc, evt); 1723 } 1724 1725 BWI_UNLOCK(sc); 1726 } 1727 1728 static void 1729 bwi_scan_start(struct ieee80211com *ic) 1730 { 1731 struct bwi_softc *sc = ic->ic_softc; 1732 1733 BWI_LOCK(sc); 1734 /* Enable MAC beacon promiscuity */ 1735 CSR_SETBITS_4(sc, BWI_MAC_STATUS, BWI_MAC_STATUS_PASS_BCN); 1736 BWI_UNLOCK(sc); 1737 } 1738 1739 static void 1740 bwi_set_channel(struct ieee80211com *ic) 1741 { 1742 struct bwi_softc *sc = ic->ic_softc; 1743 struct ieee80211_channel *c = ic->ic_curchan; 1744 struct bwi_mac *mac; 1745 1746 BWI_LOCK(sc); 1747 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 1748 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 1749 mac = (struct bwi_mac *)sc->sc_cur_regwin; 1750 bwi_rf_set_chan(mac, ieee80211_chan2ieee(ic, c), 0); 1751 1752 sc->sc_rates = ieee80211_get_ratetable(c); 1753 1754 /* 1755 * Setup radio tap channel freq and flags 1756 */ 1757 sc->sc_tx_th.wt_chan_freq = sc->sc_rx_th.wr_chan_freq = 1758 htole16(c->ic_freq); 1759 sc->sc_tx_th.wt_chan_flags = sc->sc_rx_th.wr_chan_flags = 1760 htole16(c->ic_flags & 0xffff); 1761 1762 BWI_UNLOCK(sc); 1763 } 1764 1765 static void 1766 bwi_scan_end(struct ieee80211com *ic) 1767 { 1768 struct bwi_softc *sc = ic->ic_softc; 1769 1770 BWI_LOCK(sc); 1771 CSR_CLRBITS_4(sc, BWI_MAC_STATUS, BWI_MAC_STATUS_PASS_BCN); 1772 BWI_UNLOCK(sc); 1773 } 1774 1775 static int 1776 bwi_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 1777 { 1778 struct bwi_vap *bvp = BWI_VAP(vap); 1779 struct ieee80211com *ic = vap->iv_ic; 1780 enum ieee80211_state ostate = vap->iv_state; 1781 struct bwi_softc *sc = ic->ic_softc; 1782 struct bwi_mac *mac; 1783 int error; 1784 1785 BWI_LOCK(sc); 1786 1787 callout_stop(&sc->sc_calib_ch); 1788 1789 if (nstate == IEEE80211_S_INIT) 1790 sc->sc_txpwrcb_type = BWI_TXPWR_INIT; 1791 1792 bwi_led_newstate(sc, nstate); 1793 1794 error = bvp->bv_newstate(vap, nstate, arg); 1795 if (error != 0) 1796 goto back; 1797 1798 /* 1799 * Clear the BSSID when we stop a STA 1800 */ 1801 if (vap->iv_opmode == IEEE80211_M_STA) { 1802 if (ostate == IEEE80211_S_RUN && nstate != IEEE80211_S_RUN) { 1803 /* 1804 * Clear out the BSSID. If we reassociate to 1805 * the same AP, this will reinialize things 1806 * correctly... 1807 */ 1808 if (ic->ic_opmode == IEEE80211_M_STA && 1809 !(sc->sc_flags & BWI_F_STOP)) 1810 bwi_set_bssid(sc, bwi_zero_addr); 1811 } 1812 } 1813 1814 if (vap->iv_opmode == IEEE80211_M_MONITOR) { 1815 /* Nothing to do */ 1816 } else if (nstate == IEEE80211_S_RUN) { 1817 bwi_set_bssid(sc, vap->iv_bss->ni_bssid); 1818 1819 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 1820 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 1821 mac = (struct bwi_mac *)sc->sc_cur_regwin; 1822 1823 /* Initial TX power calibration */ 1824 bwi_mac_calibrate_txpower(mac, BWI_TXPWR_INIT); 1825 #ifdef notyet 1826 sc->sc_txpwrcb_type = BWI_TXPWR_FORCE; 1827 #else 1828 sc->sc_txpwrcb_type = BWI_TXPWR_CALIB; 1829 #endif 1830 1831 callout_reset(&sc->sc_calib_ch, hz, bwi_calibrate, sc); 1832 } 1833 back: 1834 BWI_UNLOCK(sc); 1835 1836 return error; 1837 } 1838 1839 static int 1840 bwi_media_change(struct ifnet *ifp) 1841 { 1842 int error = ieee80211_media_change(ifp); 1843 /* NB: only the fixed rate can change and that doesn't need a reset */ 1844 return (error == ENETRESET ? 0 : error); 1845 } 1846 1847 static int 1848 bwi_dma_alloc(struct bwi_softc *sc) 1849 { 1850 int error, i, has_txstats; 1851 bus_addr_t lowaddr = 0; 1852 bus_size_t tx_ring_sz, rx_ring_sz, desc_sz = 0; 1853 uint32_t txrx_ctrl_step = 0; 1854 1855 has_txstats = 0; 1856 for (i = 0; i < sc->sc_nmac; ++i) { 1857 if (sc->sc_mac[i].mac_flags & BWI_MAC_F_HAS_TXSTATS) { 1858 has_txstats = 1; 1859 break; 1860 } 1861 } 1862 1863 switch (sc->sc_bus_space) { 1864 case BWI_BUS_SPACE_30BIT: 1865 case BWI_BUS_SPACE_32BIT: 1866 if (sc->sc_bus_space == BWI_BUS_SPACE_30BIT) 1867 lowaddr = BWI_BUS_SPACE_MAXADDR; 1868 else 1869 lowaddr = BUS_SPACE_MAXADDR_32BIT; 1870 desc_sz = sizeof(struct bwi_desc32); 1871 txrx_ctrl_step = 0x20; 1872 1873 sc->sc_init_tx_ring = bwi_init_tx_ring32; 1874 sc->sc_free_tx_ring = bwi_free_tx_ring32; 1875 sc->sc_init_rx_ring = bwi_init_rx_ring32; 1876 sc->sc_free_rx_ring = bwi_free_rx_ring32; 1877 sc->sc_setup_rxdesc = bwi_setup_rx_desc32; 1878 sc->sc_setup_txdesc = bwi_setup_tx_desc32; 1879 sc->sc_rxeof = bwi_rxeof32; 1880 sc->sc_start_tx = bwi_start_tx32; 1881 if (has_txstats) { 1882 sc->sc_init_txstats = bwi_init_txstats32; 1883 sc->sc_free_txstats = bwi_free_txstats32; 1884 sc->sc_txeof_status = bwi_txeof_status32; 1885 } 1886 break; 1887 1888 case BWI_BUS_SPACE_64BIT: 1889 lowaddr = BUS_SPACE_MAXADDR; /* XXX */ 1890 desc_sz = sizeof(struct bwi_desc64); 1891 txrx_ctrl_step = 0x40; 1892 1893 sc->sc_init_tx_ring = bwi_init_tx_ring64; 1894 sc->sc_free_tx_ring = bwi_free_tx_ring64; 1895 sc->sc_init_rx_ring = bwi_init_rx_ring64; 1896 sc->sc_free_rx_ring = bwi_free_rx_ring64; 1897 sc->sc_setup_rxdesc = bwi_setup_rx_desc64; 1898 sc->sc_setup_txdesc = bwi_setup_tx_desc64; 1899 sc->sc_rxeof = bwi_rxeof64; 1900 sc->sc_start_tx = bwi_start_tx64; 1901 if (has_txstats) { 1902 sc->sc_init_txstats = bwi_init_txstats64; 1903 sc->sc_free_txstats = bwi_free_txstats64; 1904 sc->sc_txeof_status = bwi_txeof_status64; 1905 } 1906 break; 1907 } 1908 1909 KASSERT(lowaddr != 0, ("lowaddr zero")); 1910 KASSERT(desc_sz != 0, ("desc_sz zero")); 1911 KASSERT(txrx_ctrl_step != 0, ("txrx_ctrl_step zero")); 1912 1913 tx_ring_sz = roundup(desc_sz * BWI_TX_NDESC, BWI_RING_ALIGN); 1914 rx_ring_sz = roundup(desc_sz * BWI_RX_NDESC, BWI_RING_ALIGN); 1915 1916 /* 1917 * Create top level DMA tag 1918 */ 1919 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), /* parent */ 1920 BWI_ALIGN, 0, /* alignment, bounds */ 1921 lowaddr, /* lowaddr */ 1922 BUS_SPACE_MAXADDR, /* highaddr */ 1923 NULL, NULL, /* filter, filterarg */ 1924 BUS_SPACE_MAXSIZE, /* maxsize */ 1925 BUS_SPACE_UNRESTRICTED, /* nsegments */ 1926 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1927 0, /* flags */ 1928 NULL, NULL, /* lockfunc, lockarg */ 1929 &sc->sc_parent_dtag); 1930 if (error) { 1931 device_printf(sc->sc_dev, "can't create parent DMA tag\n"); 1932 return error; 1933 } 1934 1935 #define TXRX_CTRL(idx) (BWI_TXRX_CTRL_BASE + (idx) * txrx_ctrl_step) 1936 1937 /* 1938 * Create TX ring DMA stuffs 1939 */ 1940 error = bus_dma_tag_create(sc->sc_parent_dtag, 1941 BWI_RING_ALIGN, 0, 1942 BUS_SPACE_MAXADDR, 1943 BUS_SPACE_MAXADDR, 1944 NULL, NULL, 1945 tx_ring_sz, 1946 1, 1947 tx_ring_sz, 1948 0, 1949 NULL, NULL, 1950 &sc->sc_txring_dtag); 1951 if (error) { 1952 device_printf(sc->sc_dev, "can't create TX ring DMA tag\n"); 1953 return error; 1954 } 1955 1956 for (i = 0; i < BWI_TX_NRING; ++i) { 1957 error = bwi_dma_ring_alloc(sc, sc->sc_txring_dtag, 1958 &sc->sc_tx_rdata[i], tx_ring_sz, 1959 TXRX_CTRL(i)); 1960 if (error) { 1961 device_printf(sc->sc_dev, "%dth TX ring " 1962 "DMA alloc failed\n", i); 1963 return error; 1964 } 1965 } 1966 1967 /* 1968 * Create RX ring DMA stuffs 1969 */ 1970 error = bus_dma_tag_create(sc->sc_parent_dtag, 1971 BWI_RING_ALIGN, 0, 1972 BUS_SPACE_MAXADDR, 1973 BUS_SPACE_MAXADDR, 1974 NULL, NULL, 1975 rx_ring_sz, 1976 1, 1977 rx_ring_sz, 1978 0, 1979 NULL, NULL, 1980 &sc->sc_rxring_dtag); 1981 if (error) { 1982 device_printf(sc->sc_dev, "can't create RX ring DMA tag\n"); 1983 return error; 1984 } 1985 1986 error = bwi_dma_ring_alloc(sc, sc->sc_rxring_dtag, &sc->sc_rx_rdata, 1987 rx_ring_sz, TXRX_CTRL(0)); 1988 if (error) { 1989 device_printf(sc->sc_dev, "RX ring DMA alloc failed\n"); 1990 return error; 1991 } 1992 1993 if (has_txstats) { 1994 error = bwi_dma_txstats_alloc(sc, TXRX_CTRL(3), desc_sz); 1995 if (error) { 1996 device_printf(sc->sc_dev, 1997 "TX stats DMA alloc failed\n"); 1998 return error; 1999 } 2000 } 2001 2002 #undef TXRX_CTRL 2003 2004 return bwi_dma_mbuf_create(sc); 2005 } 2006 2007 static void 2008 bwi_dma_free(struct bwi_softc *sc) 2009 { 2010 if (sc->sc_txring_dtag != NULL) { 2011 int i; 2012 2013 for (i = 0; i < BWI_TX_NRING; ++i) { 2014 struct bwi_ring_data *rd = &sc->sc_tx_rdata[i]; 2015 2016 if (rd->rdata_desc != NULL) { 2017 bus_dmamap_unload(sc->sc_txring_dtag, 2018 rd->rdata_dmap); 2019 bus_dmamem_free(sc->sc_txring_dtag, 2020 rd->rdata_desc, 2021 rd->rdata_dmap); 2022 } 2023 } 2024 bus_dma_tag_destroy(sc->sc_txring_dtag); 2025 } 2026 2027 if (sc->sc_rxring_dtag != NULL) { 2028 struct bwi_ring_data *rd = &sc->sc_rx_rdata; 2029 2030 if (rd->rdata_desc != NULL) { 2031 bus_dmamap_unload(sc->sc_rxring_dtag, rd->rdata_dmap); 2032 bus_dmamem_free(sc->sc_rxring_dtag, rd->rdata_desc, 2033 rd->rdata_dmap); 2034 } 2035 bus_dma_tag_destroy(sc->sc_rxring_dtag); 2036 } 2037 2038 bwi_dma_txstats_free(sc); 2039 bwi_dma_mbuf_destroy(sc, BWI_TX_NRING, 1); 2040 2041 if (sc->sc_parent_dtag != NULL) 2042 bus_dma_tag_destroy(sc->sc_parent_dtag); 2043 } 2044 2045 static int 2046 bwi_dma_ring_alloc(struct bwi_softc *sc, bus_dma_tag_t dtag, 2047 struct bwi_ring_data *rd, bus_size_t size, 2048 uint32_t txrx_ctrl) 2049 { 2050 int error; 2051 2052 error = bus_dmamem_alloc(dtag, &rd->rdata_desc, 2053 BUS_DMA_WAITOK | BUS_DMA_ZERO, 2054 &rd->rdata_dmap); 2055 if (error) { 2056 device_printf(sc->sc_dev, "can't allocate DMA mem\n"); 2057 return error; 2058 } 2059 2060 error = bus_dmamap_load(dtag, rd->rdata_dmap, rd->rdata_desc, size, 2061 bwi_dma_ring_addr, &rd->rdata_paddr, 2062 BUS_DMA_NOWAIT); 2063 if (error) { 2064 device_printf(sc->sc_dev, "can't load DMA mem\n"); 2065 bus_dmamem_free(dtag, rd->rdata_desc, rd->rdata_dmap); 2066 rd->rdata_desc = NULL; 2067 return error; 2068 } 2069 2070 rd->rdata_txrx_ctrl = txrx_ctrl; 2071 return 0; 2072 } 2073 2074 static int 2075 bwi_dma_txstats_alloc(struct bwi_softc *sc, uint32_t ctrl_base, 2076 bus_size_t desc_sz) 2077 { 2078 struct bwi_txstats_data *st; 2079 bus_size_t dma_size; 2080 int error; 2081 2082 st = malloc(sizeof(*st), M_DEVBUF, M_NOWAIT | M_ZERO); 2083 if (st == NULL) { 2084 device_printf(sc->sc_dev, "can't allocate txstats data\n"); 2085 return ENOMEM; 2086 } 2087 sc->sc_txstats = st; 2088 2089 /* 2090 * Create TX stats descriptor DMA stuffs 2091 */ 2092 dma_size = roundup(desc_sz * BWI_TXSTATS_NDESC, BWI_RING_ALIGN); 2093 2094 error = bus_dma_tag_create(sc->sc_parent_dtag, 2095 BWI_RING_ALIGN, 2096 0, 2097 BUS_SPACE_MAXADDR, 2098 BUS_SPACE_MAXADDR, 2099 NULL, NULL, 2100 dma_size, 2101 1, 2102 dma_size, 2103 0, 2104 NULL, NULL, 2105 &st->stats_ring_dtag); 2106 if (error) { 2107 device_printf(sc->sc_dev, "can't create txstats ring " 2108 "DMA tag\n"); 2109 return error; 2110 } 2111 2112 error = bus_dmamem_alloc(st->stats_ring_dtag, &st->stats_ring, 2113 BUS_DMA_WAITOK | BUS_DMA_ZERO, 2114 &st->stats_ring_dmap); 2115 if (error) { 2116 device_printf(sc->sc_dev, "can't allocate txstats ring " 2117 "DMA mem\n"); 2118 bus_dma_tag_destroy(st->stats_ring_dtag); 2119 st->stats_ring_dtag = NULL; 2120 return error; 2121 } 2122 2123 error = bus_dmamap_load(st->stats_ring_dtag, st->stats_ring_dmap, 2124 st->stats_ring, dma_size, 2125 bwi_dma_ring_addr, &st->stats_ring_paddr, 2126 BUS_DMA_NOWAIT); 2127 if (error) { 2128 device_printf(sc->sc_dev, "can't load txstats ring DMA mem\n"); 2129 bus_dmamem_free(st->stats_ring_dtag, st->stats_ring, 2130 st->stats_ring_dmap); 2131 bus_dma_tag_destroy(st->stats_ring_dtag); 2132 st->stats_ring_dtag = NULL; 2133 return error; 2134 } 2135 2136 /* 2137 * Create TX stats DMA stuffs 2138 */ 2139 dma_size = roundup(sizeof(struct bwi_txstats) * BWI_TXSTATS_NDESC, 2140 BWI_ALIGN); 2141 2142 error = bus_dma_tag_create(sc->sc_parent_dtag, 2143 BWI_ALIGN, 2144 0, 2145 BUS_SPACE_MAXADDR, 2146 BUS_SPACE_MAXADDR, 2147 NULL, NULL, 2148 dma_size, 2149 1, 2150 dma_size, 2151 0, 2152 NULL, NULL, 2153 &st->stats_dtag); 2154 if (error) { 2155 device_printf(sc->sc_dev, "can't create txstats DMA tag\n"); 2156 return error; 2157 } 2158 2159 error = bus_dmamem_alloc(st->stats_dtag, (void **)&st->stats, 2160 BUS_DMA_WAITOK | BUS_DMA_ZERO, 2161 &st->stats_dmap); 2162 if (error) { 2163 device_printf(sc->sc_dev, "can't allocate txstats DMA mem\n"); 2164 bus_dma_tag_destroy(st->stats_dtag); 2165 st->stats_dtag = NULL; 2166 return error; 2167 } 2168 2169 error = bus_dmamap_load(st->stats_dtag, st->stats_dmap, st->stats, 2170 dma_size, bwi_dma_ring_addr, &st->stats_paddr, 2171 BUS_DMA_NOWAIT); 2172 if (error) { 2173 device_printf(sc->sc_dev, "can't load txstats DMA mem\n"); 2174 bus_dmamem_free(st->stats_dtag, st->stats, st->stats_dmap); 2175 bus_dma_tag_destroy(st->stats_dtag); 2176 st->stats_dtag = NULL; 2177 return error; 2178 } 2179 2180 st->stats_ctrl_base = ctrl_base; 2181 return 0; 2182 } 2183 2184 static void 2185 bwi_dma_txstats_free(struct bwi_softc *sc) 2186 { 2187 struct bwi_txstats_data *st; 2188 2189 if (sc->sc_txstats == NULL) 2190 return; 2191 st = sc->sc_txstats; 2192 2193 if (st->stats_ring_dtag != NULL) { 2194 bus_dmamap_unload(st->stats_ring_dtag, st->stats_ring_dmap); 2195 bus_dmamem_free(st->stats_ring_dtag, st->stats_ring, 2196 st->stats_ring_dmap); 2197 bus_dma_tag_destroy(st->stats_ring_dtag); 2198 } 2199 2200 if (st->stats_dtag != NULL) { 2201 bus_dmamap_unload(st->stats_dtag, st->stats_dmap); 2202 bus_dmamem_free(st->stats_dtag, st->stats, st->stats_dmap); 2203 bus_dma_tag_destroy(st->stats_dtag); 2204 } 2205 2206 free(st, M_DEVBUF); 2207 } 2208 2209 static void 2210 bwi_dma_ring_addr(void *arg, bus_dma_segment_t *seg, int nseg, int error) 2211 { 2212 KASSERT(nseg == 1, ("too many segments\n")); 2213 *((bus_addr_t *)arg) = seg->ds_addr; 2214 } 2215 2216 static int 2217 bwi_dma_mbuf_create(struct bwi_softc *sc) 2218 { 2219 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata; 2220 int i, j, k, ntx, error; 2221 2222 /* 2223 * Create TX/RX mbuf DMA tag 2224 */ 2225 error = bus_dma_tag_create(sc->sc_parent_dtag, 2226 1, 2227 0, 2228 BUS_SPACE_MAXADDR, 2229 BUS_SPACE_MAXADDR, 2230 NULL, NULL, 2231 MCLBYTES, 2232 1, 2233 MCLBYTES, 2234 BUS_DMA_ALLOCNOW, 2235 NULL, NULL, 2236 &sc->sc_buf_dtag); 2237 if (error) { 2238 device_printf(sc->sc_dev, "can't create mbuf DMA tag\n"); 2239 return error; 2240 } 2241 2242 ntx = 0; 2243 2244 /* 2245 * Create TX mbuf DMA map 2246 */ 2247 for (i = 0; i < BWI_TX_NRING; ++i) { 2248 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[i]; 2249 2250 for (j = 0; j < BWI_TX_NDESC; ++j) { 2251 error = bus_dmamap_create(sc->sc_buf_dtag, 0, 2252 &tbd->tbd_buf[j].tb_dmap); 2253 if (error) { 2254 device_printf(sc->sc_dev, "can't create " 2255 "%dth tbd, %dth DMA map\n", i, j); 2256 2257 ntx = i; 2258 for (k = 0; k < j; ++k) { 2259 bus_dmamap_destroy(sc->sc_buf_dtag, 2260 tbd->tbd_buf[k].tb_dmap); 2261 } 2262 goto fail; 2263 } 2264 } 2265 } 2266 ntx = BWI_TX_NRING; 2267 2268 /* 2269 * Create RX mbuf DMA map and a spare DMA map 2270 */ 2271 error = bus_dmamap_create(sc->sc_buf_dtag, 0, 2272 &rbd->rbd_tmp_dmap); 2273 if (error) { 2274 device_printf(sc->sc_dev, 2275 "can't create spare RX buf DMA map\n"); 2276 goto fail; 2277 } 2278 2279 for (j = 0; j < BWI_RX_NDESC; ++j) { 2280 error = bus_dmamap_create(sc->sc_buf_dtag, 0, 2281 &rbd->rbd_buf[j].rb_dmap); 2282 if (error) { 2283 device_printf(sc->sc_dev, "can't create %dth " 2284 "RX buf DMA map\n", j); 2285 2286 for (k = 0; k < j; ++k) { 2287 bus_dmamap_destroy(sc->sc_buf_dtag, 2288 rbd->rbd_buf[j].rb_dmap); 2289 } 2290 bus_dmamap_destroy(sc->sc_buf_dtag, 2291 rbd->rbd_tmp_dmap); 2292 goto fail; 2293 } 2294 } 2295 2296 return 0; 2297 fail: 2298 bwi_dma_mbuf_destroy(sc, ntx, 0); 2299 return error; 2300 } 2301 2302 static void 2303 bwi_dma_mbuf_destroy(struct bwi_softc *sc, int ntx, int nrx) 2304 { 2305 int i, j; 2306 2307 if (sc->sc_buf_dtag == NULL) 2308 return; 2309 2310 for (i = 0; i < ntx; ++i) { 2311 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[i]; 2312 2313 for (j = 0; j < BWI_TX_NDESC; ++j) { 2314 struct bwi_txbuf *tb = &tbd->tbd_buf[j]; 2315 2316 if (tb->tb_mbuf != NULL) { 2317 bus_dmamap_unload(sc->sc_buf_dtag, 2318 tb->tb_dmap); 2319 m_freem(tb->tb_mbuf); 2320 } 2321 if (tb->tb_ni != NULL) 2322 ieee80211_free_node(tb->tb_ni); 2323 bus_dmamap_destroy(sc->sc_buf_dtag, tb->tb_dmap); 2324 } 2325 } 2326 2327 if (nrx) { 2328 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata; 2329 2330 bus_dmamap_destroy(sc->sc_buf_dtag, rbd->rbd_tmp_dmap); 2331 for (j = 0; j < BWI_RX_NDESC; ++j) { 2332 struct bwi_rxbuf *rb = &rbd->rbd_buf[j]; 2333 2334 if (rb->rb_mbuf != NULL) { 2335 bus_dmamap_unload(sc->sc_buf_dtag, 2336 rb->rb_dmap); 2337 m_freem(rb->rb_mbuf); 2338 } 2339 bus_dmamap_destroy(sc->sc_buf_dtag, rb->rb_dmap); 2340 } 2341 } 2342 2343 bus_dma_tag_destroy(sc->sc_buf_dtag); 2344 sc->sc_buf_dtag = NULL; 2345 } 2346 2347 static void 2348 bwi_enable_intrs(struct bwi_softc *sc, uint32_t enable_intrs) 2349 { 2350 CSR_SETBITS_4(sc, BWI_MAC_INTR_MASK, enable_intrs); 2351 } 2352 2353 static void 2354 bwi_disable_intrs(struct bwi_softc *sc, uint32_t disable_intrs) 2355 { 2356 CSR_CLRBITS_4(sc, BWI_MAC_INTR_MASK, disable_intrs); 2357 } 2358 2359 static int 2360 bwi_init_tx_ring32(struct bwi_softc *sc, int ring_idx) 2361 { 2362 struct bwi_ring_data *rd; 2363 struct bwi_txbuf_data *tbd; 2364 uint32_t val, addr_hi, addr_lo; 2365 2366 KASSERT(ring_idx < BWI_TX_NRING, ("ring_idx %d", ring_idx)); 2367 rd = &sc->sc_tx_rdata[ring_idx]; 2368 tbd = &sc->sc_tx_bdata[ring_idx]; 2369 2370 tbd->tbd_idx = 0; 2371 tbd->tbd_used = 0; 2372 2373 bzero(rd->rdata_desc, sizeof(struct bwi_desc32) * BWI_TX_NDESC); 2374 bus_dmamap_sync(sc->sc_txring_dtag, rd->rdata_dmap, 2375 BUS_DMASYNC_PREWRITE); 2376 2377 addr_lo = __SHIFTOUT(rd->rdata_paddr, BWI_TXRX32_RINGINFO_ADDR_MASK); 2378 addr_hi = __SHIFTOUT(rd->rdata_paddr, BWI_TXRX32_RINGINFO_FUNC_MASK); 2379 2380 val = __SHIFTIN(addr_lo, BWI_TXRX32_RINGINFO_ADDR_MASK) | 2381 __SHIFTIN(BWI_TXRX32_RINGINFO_FUNC_TXRX, 2382 BWI_TXRX32_RINGINFO_FUNC_MASK); 2383 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_RINGINFO, val); 2384 2385 val = __SHIFTIN(addr_hi, BWI_TXRX32_CTRL_ADDRHI_MASK) | 2386 BWI_TXRX32_CTRL_ENABLE; 2387 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_CTRL, val); 2388 2389 return 0; 2390 } 2391 2392 static void 2393 bwi_init_rxdesc_ring32(struct bwi_softc *sc, uint32_t ctrl_base, 2394 bus_addr_t paddr, int hdr_size, int ndesc) 2395 { 2396 uint32_t val, addr_hi, addr_lo; 2397 2398 addr_lo = __SHIFTOUT(paddr, BWI_TXRX32_RINGINFO_ADDR_MASK); 2399 addr_hi = __SHIFTOUT(paddr, BWI_TXRX32_RINGINFO_FUNC_MASK); 2400 2401 val = __SHIFTIN(addr_lo, BWI_TXRX32_RINGINFO_ADDR_MASK) | 2402 __SHIFTIN(BWI_TXRX32_RINGINFO_FUNC_TXRX, 2403 BWI_TXRX32_RINGINFO_FUNC_MASK); 2404 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_RINGINFO, val); 2405 2406 val = __SHIFTIN(hdr_size, BWI_RX32_CTRL_HDRSZ_MASK) | 2407 __SHIFTIN(addr_hi, BWI_TXRX32_CTRL_ADDRHI_MASK) | 2408 BWI_TXRX32_CTRL_ENABLE; 2409 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_CTRL, val); 2410 2411 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_INDEX, 2412 (ndesc - 1) * sizeof(struct bwi_desc32)); 2413 } 2414 2415 static int 2416 bwi_init_rx_ring32(struct bwi_softc *sc) 2417 { 2418 struct bwi_ring_data *rd = &sc->sc_rx_rdata; 2419 int i, error; 2420 2421 sc->sc_rx_bdata.rbd_idx = 0; 2422 2423 for (i = 0; i < BWI_RX_NDESC; ++i) { 2424 error = bwi_newbuf(sc, i, 1); 2425 if (error) { 2426 device_printf(sc->sc_dev, 2427 "can't allocate %dth RX buffer\n", i); 2428 return error; 2429 } 2430 } 2431 bus_dmamap_sync(sc->sc_rxring_dtag, rd->rdata_dmap, 2432 BUS_DMASYNC_PREWRITE); 2433 2434 bwi_init_rxdesc_ring32(sc, rd->rdata_txrx_ctrl, rd->rdata_paddr, 2435 sizeof(struct bwi_rxbuf_hdr), BWI_RX_NDESC); 2436 return 0; 2437 } 2438 2439 static int 2440 bwi_init_txstats32(struct bwi_softc *sc) 2441 { 2442 struct bwi_txstats_data *st = sc->sc_txstats; 2443 bus_addr_t stats_paddr; 2444 int i; 2445 2446 bzero(st->stats, BWI_TXSTATS_NDESC * sizeof(struct bwi_txstats)); 2447 bus_dmamap_sync(st->stats_dtag, st->stats_dmap, BUS_DMASYNC_PREWRITE); 2448 2449 st->stats_idx = 0; 2450 2451 stats_paddr = st->stats_paddr; 2452 for (i = 0; i < BWI_TXSTATS_NDESC; ++i) { 2453 bwi_setup_desc32(sc, st->stats_ring, BWI_TXSTATS_NDESC, i, 2454 stats_paddr, sizeof(struct bwi_txstats), 0); 2455 stats_paddr += sizeof(struct bwi_txstats); 2456 } 2457 bus_dmamap_sync(st->stats_ring_dtag, st->stats_ring_dmap, 2458 BUS_DMASYNC_PREWRITE); 2459 2460 bwi_init_rxdesc_ring32(sc, st->stats_ctrl_base, 2461 st->stats_ring_paddr, 0, BWI_TXSTATS_NDESC); 2462 return 0; 2463 } 2464 2465 static void 2466 bwi_setup_rx_desc32(struct bwi_softc *sc, int buf_idx, bus_addr_t paddr, 2467 int buf_len) 2468 { 2469 struct bwi_ring_data *rd = &sc->sc_rx_rdata; 2470 2471 KASSERT(buf_idx < BWI_RX_NDESC, ("buf_idx %d", buf_idx)); 2472 bwi_setup_desc32(sc, rd->rdata_desc, BWI_RX_NDESC, buf_idx, 2473 paddr, buf_len, 0); 2474 } 2475 2476 static void 2477 bwi_setup_tx_desc32(struct bwi_softc *sc, struct bwi_ring_data *rd, 2478 int buf_idx, bus_addr_t paddr, int buf_len) 2479 { 2480 KASSERT(buf_idx < BWI_TX_NDESC, ("buf_idx %d", buf_idx)); 2481 bwi_setup_desc32(sc, rd->rdata_desc, BWI_TX_NDESC, buf_idx, 2482 paddr, buf_len, 1); 2483 } 2484 2485 static int 2486 bwi_init_tx_ring64(struct bwi_softc *sc, int ring_idx) 2487 { 2488 /* TODO:64 */ 2489 return EOPNOTSUPP; 2490 } 2491 2492 static int 2493 bwi_init_rx_ring64(struct bwi_softc *sc) 2494 { 2495 /* TODO:64 */ 2496 return EOPNOTSUPP; 2497 } 2498 2499 static int 2500 bwi_init_txstats64(struct bwi_softc *sc) 2501 { 2502 /* TODO:64 */ 2503 return EOPNOTSUPP; 2504 } 2505 2506 static void 2507 bwi_setup_rx_desc64(struct bwi_softc *sc, int buf_idx, bus_addr_t paddr, 2508 int buf_len) 2509 { 2510 /* TODO:64 */ 2511 } 2512 2513 static void 2514 bwi_setup_tx_desc64(struct bwi_softc *sc, struct bwi_ring_data *rd, 2515 int buf_idx, bus_addr_t paddr, int buf_len) 2516 { 2517 /* TODO:64 */ 2518 } 2519 2520 static void 2521 bwi_dma_buf_addr(void *arg, bus_dma_segment_t *seg, int nseg, 2522 bus_size_t mapsz __unused, int error) 2523 { 2524 if (!error) { 2525 KASSERT(nseg == 1, ("too many segments(%d)\n", nseg)); 2526 *((bus_addr_t *)arg) = seg->ds_addr; 2527 } 2528 } 2529 2530 static int 2531 bwi_newbuf(struct bwi_softc *sc, int buf_idx, int init) 2532 { 2533 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata; 2534 struct bwi_rxbuf *rxbuf = &rbd->rbd_buf[buf_idx]; 2535 struct bwi_rxbuf_hdr *hdr; 2536 bus_dmamap_t map; 2537 bus_addr_t paddr; 2538 struct mbuf *m; 2539 int error; 2540 2541 KASSERT(buf_idx < BWI_RX_NDESC, ("buf_idx %d", buf_idx)); 2542 2543 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 2544 if (m == NULL) { 2545 error = ENOBUFS; 2546 2547 /* 2548 * If the NIC is up and running, we need to: 2549 * - Clear RX buffer's header. 2550 * - Restore RX descriptor settings. 2551 */ 2552 if (init) 2553 return error; 2554 else 2555 goto back; 2556 } 2557 m->m_len = m->m_pkthdr.len = MCLBYTES; 2558 2559 /* 2560 * Try to load RX buf into temporary DMA map 2561 */ 2562 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, rbd->rbd_tmp_dmap, m, 2563 bwi_dma_buf_addr, &paddr, BUS_DMA_NOWAIT); 2564 if (error) { 2565 m_freem(m); 2566 2567 /* 2568 * See the comment above 2569 */ 2570 if (init) 2571 return error; 2572 else 2573 goto back; 2574 } 2575 2576 if (!init) 2577 bus_dmamap_unload(sc->sc_buf_dtag, rxbuf->rb_dmap); 2578 rxbuf->rb_mbuf = m; 2579 rxbuf->rb_paddr = paddr; 2580 2581 /* 2582 * Swap RX buf's DMA map with the loaded temporary one 2583 */ 2584 map = rxbuf->rb_dmap; 2585 rxbuf->rb_dmap = rbd->rbd_tmp_dmap; 2586 rbd->rbd_tmp_dmap = map; 2587 2588 back: 2589 /* 2590 * Clear RX buf header 2591 */ 2592 hdr = mtod(rxbuf->rb_mbuf, struct bwi_rxbuf_hdr *); 2593 bzero(hdr, sizeof(*hdr)); 2594 bus_dmamap_sync(sc->sc_buf_dtag, rxbuf->rb_dmap, BUS_DMASYNC_PREWRITE); 2595 2596 /* 2597 * Setup RX buf descriptor 2598 */ 2599 sc->sc_setup_rxdesc(sc, buf_idx, rxbuf->rb_paddr, 2600 rxbuf->rb_mbuf->m_len - sizeof(*hdr)); 2601 return error; 2602 } 2603 2604 static void 2605 bwi_set_addr_filter(struct bwi_softc *sc, uint16_t addr_ofs, 2606 const uint8_t *addr) 2607 { 2608 int i; 2609 2610 CSR_WRITE_2(sc, BWI_ADDR_FILTER_CTRL, 2611 BWI_ADDR_FILTER_CTRL_SET | addr_ofs); 2612 2613 for (i = 0; i < (IEEE80211_ADDR_LEN / 2); ++i) { 2614 uint16_t addr_val; 2615 2616 addr_val = (uint16_t)addr[i * 2] | 2617 (((uint16_t)addr[(i * 2) + 1]) << 8); 2618 CSR_WRITE_2(sc, BWI_ADDR_FILTER_DATA, addr_val); 2619 } 2620 } 2621 2622 static int 2623 bwi_rxeof(struct bwi_softc *sc, int end_idx) 2624 { 2625 struct bwi_ring_data *rd = &sc->sc_rx_rdata; 2626 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata; 2627 struct ifnet *ifp = sc->sc_ifp; 2628 struct ieee80211com *ic = ifp->if_l2com; 2629 int idx, rx_data = 0; 2630 2631 idx = rbd->rbd_idx; 2632 while (idx != end_idx) { 2633 struct bwi_rxbuf *rb = &rbd->rbd_buf[idx]; 2634 struct bwi_rxbuf_hdr *hdr; 2635 struct ieee80211_frame_min *wh; 2636 struct ieee80211_node *ni; 2637 struct mbuf *m; 2638 uint32_t plcp; 2639 uint16_t flags2; 2640 int buflen, wh_ofs, hdr_extra, rssi, noise, type, rate; 2641 2642 m = rb->rb_mbuf; 2643 bus_dmamap_sync(sc->sc_buf_dtag, rb->rb_dmap, 2644 BUS_DMASYNC_POSTREAD); 2645 2646 if (bwi_newbuf(sc, idx, 0)) { 2647 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 2648 goto next; 2649 } 2650 2651 hdr = mtod(m, struct bwi_rxbuf_hdr *); 2652 flags2 = le16toh(hdr->rxh_flags2); 2653 2654 hdr_extra = 0; 2655 if (flags2 & BWI_RXH_F2_TYPE2FRAME) 2656 hdr_extra = 2; 2657 wh_ofs = hdr_extra + 6; /* XXX magic number */ 2658 2659 buflen = le16toh(hdr->rxh_buflen); 2660 if (buflen < BWI_FRAME_MIN_LEN(wh_ofs)) { 2661 if_printf(ifp, "%s: zero length data, hdr_extra %d\n", 2662 __func__, hdr_extra); 2663 if_inc_counter(ifp, IFCOUNTER_IERRORS, 1); 2664 m_freem(m); 2665 goto next; 2666 } 2667 2668 bcopy((uint8_t *)(hdr + 1) + hdr_extra, &plcp, sizeof(plcp)); 2669 rssi = bwi_calc_rssi(sc, hdr); 2670 noise = bwi_calc_noise(sc); 2671 2672 m->m_pkthdr.rcvif = ifp; 2673 m->m_len = m->m_pkthdr.len = buflen + sizeof(*hdr); 2674 m_adj(m, sizeof(*hdr) + wh_ofs); 2675 2676 if (htole16(hdr->rxh_flags1) & BWI_RXH_F1_OFDM) 2677 rate = bwi_plcp2rate(plcp, IEEE80211_T_OFDM); 2678 else 2679 rate = bwi_plcp2rate(plcp, IEEE80211_T_CCK); 2680 2681 /* RX radio tap */ 2682 if (ieee80211_radiotap_active(ic)) 2683 bwi_rx_radiotap(sc, m, hdr, &plcp, rate, rssi, noise); 2684 2685 m_adj(m, -IEEE80211_CRC_LEN); 2686 2687 BWI_UNLOCK(sc); 2688 2689 wh = mtod(m, struct ieee80211_frame_min *); 2690 ni = ieee80211_find_rxnode(ic, wh); 2691 if (ni != NULL) { 2692 type = ieee80211_input(ni, m, rssi - noise, noise); 2693 ieee80211_free_node(ni); 2694 } else 2695 type = ieee80211_input_all(ic, m, rssi - noise, noise); 2696 if (type == IEEE80211_FC0_TYPE_DATA) { 2697 rx_data = 1; 2698 sc->sc_rx_rate = rate; 2699 } 2700 2701 BWI_LOCK(sc); 2702 next: 2703 idx = (idx + 1) % BWI_RX_NDESC; 2704 2705 if (sc->sc_flags & BWI_F_STOP) { 2706 /* 2707 * Take the fast lane, don't do 2708 * any damage to softc 2709 */ 2710 return -1; 2711 } 2712 } 2713 2714 rbd->rbd_idx = idx; 2715 bus_dmamap_sync(sc->sc_rxring_dtag, rd->rdata_dmap, 2716 BUS_DMASYNC_PREWRITE); 2717 2718 return rx_data; 2719 } 2720 2721 static int 2722 bwi_rxeof32(struct bwi_softc *sc) 2723 { 2724 uint32_t val, rx_ctrl; 2725 int end_idx, rx_data; 2726 2727 rx_ctrl = sc->sc_rx_rdata.rdata_txrx_ctrl; 2728 2729 val = CSR_READ_4(sc, rx_ctrl + BWI_RX32_STATUS); 2730 end_idx = __SHIFTOUT(val, BWI_RX32_STATUS_INDEX_MASK) / 2731 sizeof(struct bwi_desc32); 2732 2733 rx_data = bwi_rxeof(sc, end_idx); 2734 if (rx_data >= 0) { 2735 CSR_WRITE_4(sc, rx_ctrl + BWI_RX32_INDEX, 2736 end_idx * sizeof(struct bwi_desc32)); 2737 } 2738 return rx_data; 2739 } 2740 2741 static int 2742 bwi_rxeof64(struct bwi_softc *sc) 2743 { 2744 /* TODO:64 */ 2745 return 0; 2746 } 2747 2748 static void 2749 bwi_reset_rx_ring32(struct bwi_softc *sc, uint32_t rx_ctrl) 2750 { 2751 int i; 2752 2753 CSR_WRITE_4(sc, rx_ctrl + BWI_RX32_CTRL, 0); 2754 2755 #define NRETRY 10 2756 2757 for (i = 0; i < NRETRY; ++i) { 2758 uint32_t status; 2759 2760 status = CSR_READ_4(sc, rx_ctrl + BWI_RX32_STATUS); 2761 if (__SHIFTOUT(status, BWI_RX32_STATUS_STATE_MASK) == 2762 BWI_RX32_STATUS_STATE_DISABLED) 2763 break; 2764 2765 DELAY(1000); 2766 } 2767 if (i == NRETRY) 2768 device_printf(sc->sc_dev, "reset rx ring timedout\n"); 2769 2770 #undef NRETRY 2771 2772 CSR_WRITE_4(sc, rx_ctrl + BWI_RX32_RINGINFO, 0); 2773 } 2774 2775 static void 2776 bwi_free_txstats32(struct bwi_softc *sc) 2777 { 2778 bwi_reset_rx_ring32(sc, sc->sc_txstats->stats_ctrl_base); 2779 } 2780 2781 static void 2782 bwi_free_rx_ring32(struct bwi_softc *sc) 2783 { 2784 struct bwi_ring_data *rd = &sc->sc_rx_rdata; 2785 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata; 2786 int i; 2787 2788 bwi_reset_rx_ring32(sc, rd->rdata_txrx_ctrl); 2789 2790 for (i = 0; i < BWI_RX_NDESC; ++i) { 2791 struct bwi_rxbuf *rb = &rbd->rbd_buf[i]; 2792 2793 if (rb->rb_mbuf != NULL) { 2794 bus_dmamap_unload(sc->sc_buf_dtag, rb->rb_dmap); 2795 m_freem(rb->rb_mbuf); 2796 rb->rb_mbuf = NULL; 2797 } 2798 } 2799 } 2800 2801 static void 2802 bwi_free_tx_ring32(struct bwi_softc *sc, int ring_idx) 2803 { 2804 struct bwi_ring_data *rd; 2805 struct bwi_txbuf_data *tbd; 2806 struct ifnet *ifp = sc->sc_ifp; 2807 uint32_t state, val; 2808 int i; 2809 2810 KASSERT(ring_idx < BWI_TX_NRING, ("ring_idx %d", ring_idx)); 2811 rd = &sc->sc_tx_rdata[ring_idx]; 2812 tbd = &sc->sc_tx_bdata[ring_idx]; 2813 2814 #define NRETRY 10 2815 2816 for (i = 0; i < NRETRY; ++i) { 2817 val = CSR_READ_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_STATUS); 2818 state = __SHIFTOUT(val, BWI_TX32_STATUS_STATE_MASK); 2819 if (state == BWI_TX32_STATUS_STATE_DISABLED || 2820 state == BWI_TX32_STATUS_STATE_IDLE || 2821 state == BWI_TX32_STATUS_STATE_STOPPED) 2822 break; 2823 2824 DELAY(1000); 2825 } 2826 if (i == NRETRY) { 2827 if_printf(ifp, "%s: wait for TX ring(%d) stable timed out\n", 2828 __func__, ring_idx); 2829 } 2830 2831 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_CTRL, 0); 2832 for (i = 0; i < NRETRY; ++i) { 2833 val = CSR_READ_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_STATUS); 2834 state = __SHIFTOUT(val, BWI_TX32_STATUS_STATE_MASK); 2835 if (state == BWI_TX32_STATUS_STATE_DISABLED) 2836 break; 2837 2838 DELAY(1000); 2839 } 2840 if (i == NRETRY) 2841 if_printf(ifp, "%s: reset TX ring (%d) timed out\n", 2842 __func__, ring_idx); 2843 2844 #undef NRETRY 2845 2846 DELAY(1000); 2847 2848 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_RINGINFO, 0); 2849 2850 for (i = 0; i < BWI_TX_NDESC; ++i) { 2851 struct bwi_txbuf *tb = &tbd->tbd_buf[i]; 2852 2853 if (tb->tb_mbuf != NULL) { 2854 bus_dmamap_unload(sc->sc_buf_dtag, tb->tb_dmap); 2855 m_freem(tb->tb_mbuf); 2856 tb->tb_mbuf = NULL; 2857 } 2858 if (tb->tb_ni != NULL) { 2859 ieee80211_free_node(tb->tb_ni); 2860 tb->tb_ni = NULL; 2861 } 2862 } 2863 } 2864 2865 static void 2866 bwi_free_txstats64(struct bwi_softc *sc) 2867 { 2868 /* TODO:64 */ 2869 } 2870 2871 static void 2872 bwi_free_rx_ring64(struct bwi_softc *sc) 2873 { 2874 /* TODO:64 */ 2875 } 2876 2877 static void 2878 bwi_free_tx_ring64(struct bwi_softc *sc, int ring_idx) 2879 { 2880 /* TODO:64 */ 2881 } 2882 2883 /* XXX does not belong here */ 2884 #define IEEE80211_OFDM_PLCP_RATE_MASK __BITS(3, 0) 2885 #define IEEE80211_OFDM_PLCP_LEN_MASK __BITS(16, 5) 2886 2887 static __inline void 2888 bwi_ofdm_plcp_header(uint32_t *plcp0, int pkt_len, uint8_t rate) 2889 { 2890 uint32_t plcp; 2891 2892 plcp = __SHIFTIN(ieee80211_rate2plcp(rate, IEEE80211_T_OFDM), 2893 IEEE80211_OFDM_PLCP_RATE_MASK) | 2894 __SHIFTIN(pkt_len, IEEE80211_OFDM_PLCP_LEN_MASK); 2895 *plcp0 = htole32(plcp); 2896 } 2897 2898 static __inline void 2899 bwi_ds_plcp_header(struct ieee80211_ds_plcp_hdr *plcp, int pkt_len, 2900 uint8_t rate) 2901 { 2902 int len, service, pkt_bitlen; 2903 2904 pkt_bitlen = pkt_len * NBBY; 2905 len = howmany(pkt_bitlen * 2, rate); 2906 2907 service = IEEE80211_PLCP_SERVICE_LOCKED; 2908 if (rate == (11 * 2)) { 2909 int pkt_bitlen1; 2910 2911 /* 2912 * PLCP service field needs to be adjusted, 2913 * if TX rate is 11Mbytes/s 2914 */ 2915 pkt_bitlen1 = len * 11; 2916 if (pkt_bitlen1 - pkt_bitlen >= NBBY) 2917 service |= IEEE80211_PLCP_SERVICE_LENEXT7; 2918 } 2919 2920 plcp->i_signal = ieee80211_rate2plcp(rate, IEEE80211_T_CCK); 2921 plcp->i_service = service; 2922 plcp->i_length = htole16(len); 2923 /* NOTE: do NOT touch i_crc */ 2924 } 2925 2926 static __inline void 2927 bwi_plcp_header(const struct ieee80211_rate_table *rt, 2928 void *plcp, int pkt_len, uint8_t rate) 2929 { 2930 enum ieee80211_phytype modtype; 2931 2932 /* 2933 * Assume caller has zeroed 'plcp' 2934 */ 2935 modtype = ieee80211_rate2phytype(rt, rate); 2936 if (modtype == IEEE80211_T_OFDM) 2937 bwi_ofdm_plcp_header(plcp, pkt_len, rate); 2938 else if (modtype == IEEE80211_T_DS) 2939 bwi_ds_plcp_header(plcp, pkt_len, rate); 2940 else 2941 panic("unsupport modulation type %u\n", modtype); 2942 } 2943 2944 static int 2945 bwi_encap(struct bwi_softc *sc, int idx, struct mbuf *m, 2946 struct ieee80211_node *ni) 2947 { 2948 struct ieee80211vap *vap = ni->ni_vap; 2949 struct ifnet *ifp = sc->sc_ifp; 2950 struct ieee80211com *ic = ifp->if_l2com; 2951 struct bwi_ring_data *rd = &sc->sc_tx_rdata[BWI_TX_DATA_RING]; 2952 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING]; 2953 struct bwi_txbuf *tb = &tbd->tbd_buf[idx]; 2954 struct bwi_mac *mac; 2955 struct bwi_txbuf_hdr *hdr; 2956 struct ieee80211_frame *wh; 2957 const struct ieee80211_txparam *tp; 2958 uint8_t rate, rate_fb; 2959 uint32_t mac_ctrl; 2960 uint16_t phy_ctrl; 2961 bus_addr_t paddr; 2962 int type, ismcast, pkt_len, error, rix; 2963 #if 0 2964 const uint8_t *p; 2965 int i; 2966 #endif 2967 2968 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 2969 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 2970 mac = (struct bwi_mac *)sc->sc_cur_regwin; 2971 2972 wh = mtod(m, struct ieee80211_frame *); 2973 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2974 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 2975 2976 /* Get 802.11 frame len before prepending TX header */ 2977 pkt_len = m->m_pkthdr.len + IEEE80211_CRC_LEN; 2978 2979 /* 2980 * Find TX rate 2981 */ 2982 tp = &vap->iv_txparms[ieee80211_chan2mode(ic->ic_curchan)]; 2983 if (type != IEEE80211_FC0_TYPE_DATA || (m->m_flags & M_EAPOL)) { 2984 rate = rate_fb = tp->mgmtrate; 2985 } else if (ismcast) { 2986 rate = rate_fb = tp->mcastrate; 2987 } else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) { 2988 rate = rate_fb = tp->ucastrate; 2989 } else { 2990 rix = ieee80211_ratectl_rate(ni, NULL, pkt_len); 2991 rate = ni->ni_txrate; 2992 2993 if (rix > 0) { 2994 rate_fb = ni->ni_rates.rs_rates[rix-1] & 2995 IEEE80211_RATE_VAL; 2996 } else { 2997 rate_fb = rate; 2998 } 2999 } 3000 tb->tb_rate[0] = rate; 3001 tb->tb_rate[1] = rate_fb; 3002 sc->sc_tx_rate = rate; 3003 3004 /* 3005 * TX radio tap 3006 */ 3007 if (ieee80211_radiotap_active_vap(vap)) { 3008 sc->sc_tx_th.wt_flags = 0; 3009 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) 3010 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP; 3011 if (ieee80211_rate2phytype(sc->sc_rates, rate) == IEEE80211_T_DS && 3012 (ic->ic_flags & IEEE80211_F_SHPREAMBLE) && 3013 rate != (1 * 2)) { 3014 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 3015 } 3016 sc->sc_tx_th.wt_rate = rate; 3017 3018 ieee80211_radiotap_tx(vap, m); 3019 } 3020 3021 /* 3022 * Setup the embedded TX header 3023 */ 3024 M_PREPEND(m, sizeof(*hdr), M_NOWAIT); 3025 if (m == NULL) { 3026 if_printf(ifp, "%s: prepend TX header failed\n", __func__); 3027 return ENOBUFS; 3028 } 3029 hdr = mtod(m, struct bwi_txbuf_hdr *); 3030 3031 bzero(hdr, sizeof(*hdr)); 3032 3033 bcopy(wh->i_fc, hdr->txh_fc, sizeof(hdr->txh_fc)); 3034 bcopy(wh->i_addr1, hdr->txh_addr1, sizeof(hdr->txh_addr1)); 3035 3036 if (!ismcast) { 3037 uint16_t dur; 3038 3039 dur = ieee80211_ack_duration(sc->sc_rates, rate, 3040 ic->ic_flags & ~IEEE80211_F_SHPREAMBLE); 3041 3042 hdr->txh_fb_duration = htole16(dur); 3043 } 3044 3045 hdr->txh_id = __SHIFTIN(BWI_TX_DATA_RING, BWI_TXH_ID_RING_MASK) | 3046 __SHIFTIN(idx, BWI_TXH_ID_IDX_MASK); 3047 3048 bwi_plcp_header(sc->sc_rates, hdr->txh_plcp, pkt_len, rate); 3049 bwi_plcp_header(sc->sc_rates, hdr->txh_fb_plcp, pkt_len, rate_fb); 3050 3051 phy_ctrl = __SHIFTIN(mac->mac_rf.rf_ant_mode, 3052 BWI_TXH_PHY_C_ANTMODE_MASK); 3053 if (ieee80211_rate2phytype(sc->sc_rates, rate) == IEEE80211_T_OFDM) 3054 phy_ctrl |= BWI_TXH_PHY_C_OFDM; 3055 else if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && rate != (2 * 1)) 3056 phy_ctrl |= BWI_TXH_PHY_C_SHPREAMBLE; 3057 3058 mac_ctrl = BWI_TXH_MAC_C_HWSEQ | BWI_TXH_MAC_C_FIRST_FRAG; 3059 if (!ismcast) 3060 mac_ctrl |= BWI_TXH_MAC_C_ACK; 3061 if (ieee80211_rate2phytype(sc->sc_rates, rate_fb) == IEEE80211_T_OFDM) 3062 mac_ctrl |= BWI_TXH_MAC_C_FB_OFDM; 3063 3064 hdr->txh_mac_ctrl = htole32(mac_ctrl); 3065 hdr->txh_phy_ctrl = htole16(phy_ctrl); 3066 3067 /* Catch any further usage */ 3068 hdr = NULL; 3069 wh = NULL; 3070 3071 /* DMA load */ 3072 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m, 3073 bwi_dma_buf_addr, &paddr, BUS_DMA_NOWAIT); 3074 if (error && error != EFBIG) { 3075 if_printf(ifp, "%s: can't load TX buffer (1) %d\n", 3076 __func__, error); 3077 goto back; 3078 } 3079 3080 if (error) { /* error == EFBIG */ 3081 struct mbuf *m_new; 3082 3083 m_new = m_defrag(m, M_NOWAIT); 3084 if (m_new == NULL) { 3085 if_printf(ifp, "%s: can't defrag TX buffer\n", 3086 __func__); 3087 error = ENOBUFS; 3088 goto back; 3089 } else { 3090 m = m_new; 3091 } 3092 3093 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m, 3094 bwi_dma_buf_addr, &paddr, 3095 BUS_DMA_NOWAIT); 3096 if (error) { 3097 if_printf(ifp, "%s: can't load TX buffer (2) %d\n", 3098 __func__, error); 3099 goto back; 3100 } 3101 } 3102 error = 0; 3103 3104 bus_dmamap_sync(sc->sc_buf_dtag, tb->tb_dmap, BUS_DMASYNC_PREWRITE); 3105 3106 tb->tb_mbuf = m; 3107 tb->tb_ni = ni; 3108 3109 #if 0 3110 p = mtod(m, const uint8_t *); 3111 for (i = 0; i < m->m_pkthdr.len; ++i) { 3112 if (i != 0 && i % 8 == 0) 3113 printf("\n"); 3114 printf("%02x ", p[i]); 3115 } 3116 printf("\n"); 3117 #endif 3118 DPRINTF(sc, BWI_DBG_TX, "idx %d, pkt_len %d, buflen %d\n", 3119 idx, pkt_len, m->m_pkthdr.len); 3120 3121 /* Setup TX descriptor */ 3122 sc->sc_setup_txdesc(sc, rd, idx, paddr, m->m_pkthdr.len); 3123 bus_dmamap_sync(sc->sc_txring_dtag, rd->rdata_dmap, 3124 BUS_DMASYNC_PREWRITE); 3125 3126 /* Kick start */ 3127 sc->sc_start_tx(sc, rd->rdata_txrx_ctrl, idx); 3128 3129 back: 3130 if (error) 3131 m_freem(m); 3132 return error; 3133 } 3134 3135 static int 3136 bwi_encap_raw(struct bwi_softc *sc, int idx, struct mbuf *m, 3137 struct ieee80211_node *ni, const struct ieee80211_bpf_params *params) 3138 { 3139 struct ifnet *ifp = sc->sc_ifp; 3140 struct ieee80211vap *vap = ni->ni_vap; 3141 struct ieee80211com *ic = ni->ni_ic; 3142 struct bwi_ring_data *rd = &sc->sc_tx_rdata[BWI_TX_DATA_RING]; 3143 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING]; 3144 struct bwi_txbuf *tb = &tbd->tbd_buf[idx]; 3145 struct bwi_mac *mac; 3146 struct bwi_txbuf_hdr *hdr; 3147 struct ieee80211_frame *wh; 3148 uint8_t rate, rate_fb; 3149 uint32_t mac_ctrl; 3150 uint16_t phy_ctrl; 3151 bus_addr_t paddr; 3152 int ismcast, pkt_len, error; 3153 3154 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 3155 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 3156 mac = (struct bwi_mac *)sc->sc_cur_regwin; 3157 3158 wh = mtod(m, struct ieee80211_frame *); 3159 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 3160 3161 /* Get 802.11 frame len before prepending TX header */ 3162 pkt_len = m->m_pkthdr.len + IEEE80211_CRC_LEN; 3163 3164 /* 3165 * Find TX rate 3166 */ 3167 rate = params->ibp_rate0; 3168 if (!ieee80211_isratevalid(ic->ic_rt, rate)) { 3169 /* XXX fall back to mcast/mgmt rate? */ 3170 m_freem(m); 3171 return EINVAL; 3172 } 3173 if (params->ibp_try1 != 0) { 3174 rate_fb = params->ibp_rate1; 3175 if (!ieee80211_isratevalid(ic->ic_rt, rate_fb)) { 3176 /* XXX fall back to rate0? */ 3177 m_freem(m); 3178 return EINVAL; 3179 } 3180 } else 3181 rate_fb = rate; 3182 tb->tb_rate[0] = rate; 3183 tb->tb_rate[1] = rate_fb; 3184 sc->sc_tx_rate = rate; 3185 3186 /* 3187 * TX radio tap 3188 */ 3189 if (ieee80211_radiotap_active_vap(vap)) { 3190 sc->sc_tx_th.wt_flags = 0; 3191 /* XXX IEEE80211_BPF_CRYPTO */ 3192 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) 3193 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP; 3194 if (params->ibp_flags & IEEE80211_BPF_SHORTPRE) 3195 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 3196 sc->sc_tx_th.wt_rate = rate; 3197 3198 ieee80211_radiotap_tx(vap, m); 3199 } 3200 3201 /* 3202 * Setup the embedded TX header 3203 */ 3204 M_PREPEND(m, sizeof(*hdr), M_NOWAIT); 3205 if (m == NULL) { 3206 if_printf(ifp, "%s: prepend TX header failed\n", __func__); 3207 return ENOBUFS; 3208 } 3209 hdr = mtod(m, struct bwi_txbuf_hdr *); 3210 3211 bzero(hdr, sizeof(*hdr)); 3212 3213 bcopy(wh->i_fc, hdr->txh_fc, sizeof(hdr->txh_fc)); 3214 bcopy(wh->i_addr1, hdr->txh_addr1, sizeof(hdr->txh_addr1)); 3215 3216 mac_ctrl = BWI_TXH_MAC_C_HWSEQ | BWI_TXH_MAC_C_FIRST_FRAG; 3217 if (!ismcast && (params->ibp_flags & IEEE80211_BPF_NOACK) == 0) { 3218 uint16_t dur; 3219 3220 dur = ieee80211_ack_duration(sc->sc_rates, rate_fb, 0); 3221 3222 hdr->txh_fb_duration = htole16(dur); 3223 mac_ctrl |= BWI_TXH_MAC_C_ACK; 3224 } 3225 3226 hdr->txh_id = __SHIFTIN(BWI_TX_DATA_RING, BWI_TXH_ID_RING_MASK) | 3227 __SHIFTIN(idx, BWI_TXH_ID_IDX_MASK); 3228 3229 bwi_plcp_header(sc->sc_rates, hdr->txh_plcp, pkt_len, rate); 3230 bwi_plcp_header(sc->sc_rates, hdr->txh_fb_plcp, pkt_len, rate_fb); 3231 3232 phy_ctrl = __SHIFTIN(mac->mac_rf.rf_ant_mode, 3233 BWI_TXH_PHY_C_ANTMODE_MASK); 3234 if (ieee80211_rate2phytype(sc->sc_rates, rate) == IEEE80211_T_OFDM) { 3235 phy_ctrl |= BWI_TXH_PHY_C_OFDM; 3236 mac_ctrl |= BWI_TXH_MAC_C_FB_OFDM; 3237 } else if (params->ibp_flags & IEEE80211_BPF_SHORTPRE) 3238 phy_ctrl |= BWI_TXH_PHY_C_SHPREAMBLE; 3239 3240 hdr->txh_mac_ctrl = htole32(mac_ctrl); 3241 hdr->txh_phy_ctrl = htole16(phy_ctrl); 3242 3243 /* Catch any further usage */ 3244 hdr = NULL; 3245 wh = NULL; 3246 3247 /* DMA load */ 3248 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m, 3249 bwi_dma_buf_addr, &paddr, BUS_DMA_NOWAIT); 3250 if (error != 0) { 3251 struct mbuf *m_new; 3252 3253 if (error != EFBIG) { 3254 if_printf(ifp, "%s: can't load TX buffer (1) %d\n", 3255 __func__, error); 3256 goto back; 3257 } 3258 m_new = m_defrag(m, M_NOWAIT); 3259 if (m_new == NULL) { 3260 if_printf(ifp, "%s: can't defrag TX buffer\n", 3261 __func__); 3262 error = ENOBUFS; 3263 goto back; 3264 } 3265 m = m_new; 3266 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m, 3267 bwi_dma_buf_addr, &paddr, 3268 BUS_DMA_NOWAIT); 3269 if (error) { 3270 if_printf(ifp, "%s: can't load TX buffer (2) %d\n", 3271 __func__, error); 3272 goto back; 3273 } 3274 } 3275 3276 bus_dmamap_sync(sc->sc_buf_dtag, tb->tb_dmap, BUS_DMASYNC_PREWRITE); 3277 3278 tb->tb_mbuf = m; 3279 tb->tb_ni = ni; 3280 3281 DPRINTF(sc, BWI_DBG_TX, "idx %d, pkt_len %d, buflen %d\n", 3282 idx, pkt_len, m->m_pkthdr.len); 3283 3284 /* Setup TX descriptor */ 3285 sc->sc_setup_txdesc(sc, rd, idx, paddr, m->m_pkthdr.len); 3286 bus_dmamap_sync(sc->sc_txring_dtag, rd->rdata_dmap, 3287 BUS_DMASYNC_PREWRITE); 3288 3289 /* Kick start */ 3290 sc->sc_start_tx(sc, rd->rdata_txrx_ctrl, idx); 3291 back: 3292 if (error) 3293 m_freem(m); 3294 return error; 3295 } 3296 3297 static void 3298 bwi_start_tx32(struct bwi_softc *sc, uint32_t tx_ctrl, int idx) 3299 { 3300 idx = (idx + 1) % BWI_TX_NDESC; 3301 CSR_WRITE_4(sc, tx_ctrl + BWI_TX32_INDEX, 3302 idx * sizeof(struct bwi_desc32)); 3303 } 3304 3305 static void 3306 bwi_start_tx64(struct bwi_softc *sc, uint32_t tx_ctrl, int idx) 3307 { 3308 /* TODO:64 */ 3309 } 3310 3311 static void 3312 bwi_txeof_status32(struct bwi_softc *sc) 3313 { 3314 struct ifnet *ifp = sc->sc_ifp; 3315 uint32_t val, ctrl_base; 3316 int end_idx; 3317 3318 ctrl_base = sc->sc_txstats->stats_ctrl_base; 3319 3320 val = CSR_READ_4(sc, ctrl_base + BWI_RX32_STATUS); 3321 end_idx = __SHIFTOUT(val, BWI_RX32_STATUS_INDEX_MASK) / 3322 sizeof(struct bwi_desc32); 3323 3324 bwi_txeof_status(sc, end_idx); 3325 3326 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_INDEX, 3327 end_idx * sizeof(struct bwi_desc32)); 3328 3329 if ((ifp->if_drv_flags & IFF_DRV_OACTIVE) == 0) 3330 ifp->if_start(ifp); 3331 } 3332 3333 static void 3334 bwi_txeof_status64(struct bwi_softc *sc) 3335 { 3336 /* TODO:64 */ 3337 } 3338 3339 static void 3340 _bwi_txeof(struct bwi_softc *sc, uint16_t tx_id, int acked, int data_txcnt) 3341 { 3342 struct ifnet *ifp = sc->sc_ifp; 3343 struct bwi_txbuf_data *tbd; 3344 struct bwi_txbuf *tb; 3345 int ring_idx, buf_idx; 3346 struct ieee80211_node *ni; 3347 struct ieee80211vap *vap; 3348 3349 if (tx_id == 0) { 3350 if_printf(ifp, "%s: zero tx id\n", __func__); 3351 return; 3352 } 3353 3354 ring_idx = __SHIFTOUT(tx_id, BWI_TXH_ID_RING_MASK); 3355 buf_idx = __SHIFTOUT(tx_id, BWI_TXH_ID_IDX_MASK); 3356 3357 KASSERT(ring_idx == BWI_TX_DATA_RING, ("ring_idx %d", ring_idx)); 3358 KASSERT(buf_idx < BWI_TX_NDESC, ("buf_idx %d", buf_idx)); 3359 3360 tbd = &sc->sc_tx_bdata[ring_idx]; 3361 KASSERT(tbd->tbd_used > 0, ("tbd_used %d", tbd->tbd_used)); 3362 tbd->tbd_used--; 3363 3364 tb = &tbd->tbd_buf[buf_idx]; 3365 DPRINTF(sc, BWI_DBG_TXEOF, "txeof idx %d, " 3366 "acked %d, data_txcnt %d, ni %p\n", 3367 buf_idx, acked, data_txcnt, tb->tb_ni); 3368 3369 bus_dmamap_unload(sc->sc_buf_dtag, tb->tb_dmap); 3370 3371 ni = tb->tb_ni; 3372 if (tb->tb_ni != NULL) { 3373 const struct bwi_txbuf_hdr *hdr = 3374 mtod(tb->tb_mbuf, const struct bwi_txbuf_hdr *); 3375 vap = ni->ni_vap; 3376 3377 /* NB: update rate control only for unicast frames */ 3378 if (hdr->txh_mac_ctrl & htole32(BWI_TXH_MAC_C_ACK)) { 3379 /* 3380 * Feed back 'acked and data_txcnt'. Note that the 3381 * generic AMRR code only understands one tx rate 3382 * and the estimator doesn't handle real retry counts 3383 * well so to avoid over-aggressive downshifting we 3384 * treat any number of retries as "1". 3385 */ 3386 ieee80211_ratectl_tx_complete(vap, ni, 3387 (data_txcnt > 1) ? IEEE80211_RATECTL_TX_SUCCESS : 3388 IEEE80211_RATECTL_TX_FAILURE, &acked, NULL); 3389 } 3390 3391 /* 3392 * Do any tx complete callback. Note this must 3393 * be done before releasing the node reference. 3394 */ 3395 if (tb->tb_mbuf->m_flags & M_TXCB) 3396 ieee80211_process_callback(ni, tb->tb_mbuf, !acked); 3397 3398 ieee80211_free_node(tb->tb_ni); 3399 tb->tb_ni = NULL; 3400 } 3401 m_freem(tb->tb_mbuf); 3402 tb->tb_mbuf = NULL; 3403 3404 if (tbd->tbd_used == 0) 3405 sc->sc_tx_timer = 0; 3406 3407 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3408 } 3409 3410 static void 3411 bwi_txeof_status(struct bwi_softc *sc, int end_idx) 3412 { 3413 struct bwi_txstats_data *st = sc->sc_txstats; 3414 int idx; 3415 3416 bus_dmamap_sync(st->stats_dtag, st->stats_dmap, BUS_DMASYNC_POSTREAD); 3417 3418 idx = st->stats_idx; 3419 while (idx != end_idx) { 3420 const struct bwi_txstats *stats = &st->stats[idx]; 3421 3422 if ((stats->txs_flags & BWI_TXS_F_PENDING) == 0) { 3423 int data_txcnt; 3424 3425 data_txcnt = __SHIFTOUT(stats->txs_txcnt, 3426 BWI_TXS_TXCNT_DATA); 3427 _bwi_txeof(sc, le16toh(stats->txs_id), 3428 stats->txs_flags & BWI_TXS_F_ACKED, 3429 data_txcnt); 3430 } 3431 idx = (idx + 1) % BWI_TXSTATS_NDESC; 3432 } 3433 st->stats_idx = idx; 3434 } 3435 3436 static void 3437 bwi_txeof(struct bwi_softc *sc) 3438 { 3439 struct ifnet *ifp = sc->sc_ifp; 3440 3441 for (;;) { 3442 uint32_t tx_status0, tx_status1; 3443 uint16_t tx_id; 3444 int data_txcnt; 3445 3446 tx_status0 = CSR_READ_4(sc, BWI_TXSTATUS0); 3447 if ((tx_status0 & BWI_TXSTATUS0_VALID) == 0) 3448 break; 3449 tx_status1 = CSR_READ_4(sc, BWI_TXSTATUS1); 3450 3451 tx_id = __SHIFTOUT(tx_status0, BWI_TXSTATUS0_TXID_MASK); 3452 data_txcnt = __SHIFTOUT(tx_status0, 3453 BWI_TXSTATUS0_DATA_TXCNT_MASK); 3454 3455 if (tx_status0 & (BWI_TXSTATUS0_AMPDU | BWI_TXSTATUS0_PENDING)) 3456 continue; 3457 3458 _bwi_txeof(sc, le16toh(tx_id), tx_status0 & BWI_TXSTATUS0_ACKED, 3459 data_txcnt); 3460 } 3461 3462 if ((ifp->if_drv_flags & IFF_DRV_OACTIVE) == 0) 3463 ifp->if_start(ifp); 3464 } 3465 3466 static int 3467 bwi_bbp_power_on(struct bwi_softc *sc, enum bwi_clock_mode clk_mode) 3468 { 3469 bwi_power_on(sc, 1); 3470 return bwi_set_clock_mode(sc, clk_mode); 3471 } 3472 3473 static void 3474 bwi_bbp_power_off(struct bwi_softc *sc) 3475 { 3476 bwi_set_clock_mode(sc, BWI_CLOCK_MODE_SLOW); 3477 bwi_power_off(sc, 1); 3478 } 3479 3480 static int 3481 bwi_get_pwron_delay(struct bwi_softc *sc) 3482 { 3483 struct bwi_regwin *com, *old; 3484 struct bwi_clock_freq freq; 3485 uint32_t val; 3486 int error; 3487 3488 com = &sc->sc_com_regwin; 3489 KASSERT(BWI_REGWIN_EXIST(com), ("no regwin")); 3490 3491 if ((sc->sc_cap & BWI_CAP_CLKMODE) == 0) 3492 return 0; 3493 3494 error = bwi_regwin_switch(sc, com, &old); 3495 if (error) 3496 return error; 3497 3498 bwi_get_clock_freq(sc, &freq); 3499 3500 val = CSR_READ_4(sc, BWI_PLL_ON_DELAY); 3501 sc->sc_pwron_delay = howmany((val + 2) * 1000000, freq.clkfreq_min); 3502 DPRINTF(sc, BWI_DBG_ATTACH, "power on delay %u\n", sc->sc_pwron_delay); 3503 3504 return bwi_regwin_switch(sc, old, NULL); 3505 } 3506 3507 static int 3508 bwi_bus_attach(struct bwi_softc *sc) 3509 { 3510 struct bwi_regwin *bus, *old; 3511 int error; 3512 3513 bus = &sc->sc_bus_regwin; 3514 3515 error = bwi_regwin_switch(sc, bus, &old); 3516 if (error) 3517 return error; 3518 3519 if (!bwi_regwin_is_enabled(sc, bus)) 3520 bwi_regwin_enable(sc, bus, 0); 3521 3522 /* Disable interripts */ 3523 CSR_WRITE_4(sc, BWI_INTRVEC, 0); 3524 3525 return bwi_regwin_switch(sc, old, NULL); 3526 } 3527 3528 static const char * 3529 bwi_regwin_name(const struct bwi_regwin *rw) 3530 { 3531 switch (rw->rw_type) { 3532 case BWI_REGWIN_T_COM: 3533 return "COM"; 3534 case BWI_REGWIN_T_BUSPCI: 3535 return "PCI"; 3536 case BWI_REGWIN_T_MAC: 3537 return "MAC"; 3538 case BWI_REGWIN_T_BUSPCIE: 3539 return "PCIE"; 3540 } 3541 panic("unknown regwin type 0x%04x\n", rw->rw_type); 3542 return NULL; 3543 } 3544 3545 static uint32_t 3546 bwi_regwin_disable_bits(struct bwi_softc *sc) 3547 { 3548 uint32_t busrev; 3549 3550 /* XXX cache this */ 3551 busrev = __SHIFTOUT(CSR_READ_4(sc, BWI_ID_LO), BWI_ID_LO_BUSREV_MASK); 3552 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT | BWI_DBG_MISC, 3553 "bus rev %u\n", busrev); 3554 3555 if (busrev == BWI_BUSREV_0) 3556 return BWI_STATE_LO_DISABLE1; 3557 else if (busrev == BWI_BUSREV_1) 3558 return BWI_STATE_LO_DISABLE2; 3559 else 3560 return (BWI_STATE_LO_DISABLE1 | BWI_STATE_LO_DISABLE2); 3561 } 3562 3563 int 3564 bwi_regwin_is_enabled(struct bwi_softc *sc, struct bwi_regwin *rw) 3565 { 3566 uint32_t val, disable_bits; 3567 3568 disable_bits = bwi_regwin_disable_bits(sc); 3569 val = CSR_READ_4(sc, BWI_STATE_LO); 3570 3571 if ((val & (BWI_STATE_LO_CLOCK | 3572 BWI_STATE_LO_RESET | 3573 disable_bits)) == BWI_STATE_LO_CLOCK) { 3574 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT, "%s is enabled\n", 3575 bwi_regwin_name(rw)); 3576 return 1; 3577 } else { 3578 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT, "%s is disabled\n", 3579 bwi_regwin_name(rw)); 3580 return 0; 3581 } 3582 } 3583 3584 void 3585 bwi_regwin_disable(struct bwi_softc *sc, struct bwi_regwin *rw, uint32_t flags) 3586 { 3587 uint32_t state_lo, disable_bits; 3588 int i; 3589 3590 state_lo = CSR_READ_4(sc, BWI_STATE_LO); 3591 3592 /* 3593 * If current regwin is in 'reset' state, it was already disabled. 3594 */ 3595 if (state_lo & BWI_STATE_LO_RESET) { 3596 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT, 3597 "%s was already disabled\n", bwi_regwin_name(rw)); 3598 return; 3599 } 3600 3601 disable_bits = bwi_regwin_disable_bits(sc); 3602 3603 /* 3604 * Disable normal clock 3605 */ 3606 state_lo = BWI_STATE_LO_CLOCK | disable_bits; 3607 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo); 3608 3609 /* 3610 * Wait until normal clock is disabled 3611 */ 3612 #define NRETRY 1000 3613 for (i = 0; i < NRETRY; ++i) { 3614 state_lo = CSR_READ_4(sc, BWI_STATE_LO); 3615 if (state_lo & disable_bits) 3616 break; 3617 DELAY(10); 3618 } 3619 if (i == NRETRY) { 3620 device_printf(sc->sc_dev, "%s disable clock timeout\n", 3621 bwi_regwin_name(rw)); 3622 } 3623 3624 for (i = 0; i < NRETRY; ++i) { 3625 uint32_t state_hi; 3626 3627 state_hi = CSR_READ_4(sc, BWI_STATE_HI); 3628 if ((state_hi & BWI_STATE_HI_BUSY) == 0) 3629 break; 3630 DELAY(10); 3631 } 3632 if (i == NRETRY) { 3633 device_printf(sc->sc_dev, "%s wait BUSY unset timeout\n", 3634 bwi_regwin_name(rw)); 3635 } 3636 #undef NRETRY 3637 3638 /* 3639 * Reset and disable regwin with gated clock 3640 */ 3641 state_lo = BWI_STATE_LO_RESET | disable_bits | 3642 BWI_STATE_LO_CLOCK | BWI_STATE_LO_GATED_CLOCK | 3643 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK); 3644 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo); 3645 3646 /* Flush pending bus write */ 3647 CSR_READ_4(sc, BWI_STATE_LO); 3648 DELAY(1); 3649 3650 /* Reset and disable regwin */ 3651 state_lo = BWI_STATE_LO_RESET | disable_bits | 3652 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK); 3653 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo); 3654 3655 /* Flush pending bus write */ 3656 CSR_READ_4(sc, BWI_STATE_LO); 3657 DELAY(1); 3658 } 3659 3660 void 3661 bwi_regwin_enable(struct bwi_softc *sc, struct bwi_regwin *rw, uint32_t flags) 3662 { 3663 uint32_t state_lo, state_hi, imstate; 3664 3665 bwi_regwin_disable(sc, rw, flags); 3666 3667 /* Reset regwin with gated clock */ 3668 state_lo = BWI_STATE_LO_RESET | 3669 BWI_STATE_LO_CLOCK | 3670 BWI_STATE_LO_GATED_CLOCK | 3671 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK); 3672 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo); 3673 3674 /* Flush pending bus write */ 3675 CSR_READ_4(sc, BWI_STATE_LO); 3676 DELAY(1); 3677 3678 state_hi = CSR_READ_4(sc, BWI_STATE_HI); 3679 if (state_hi & BWI_STATE_HI_SERROR) 3680 CSR_WRITE_4(sc, BWI_STATE_HI, 0); 3681 3682 imstate = CSR_READ_4(sc, BWI_IMSTATE); 3683 if (imstate & (BWI_IMSTATE_INBAND_ERR | BWI_IMSTATE_TIMEOUT)) { 3684 imstate &= ~(BWI_IMSTATE_INBAND_ERR | BWI_IMSTATE_TIMEOUT); 3685 CSR_WRITE_4(sc, BWI_IMSTATE, imstate); 3686 } 3687 3688 /* Enable regwin with gated clock */ 3689 state_lo = BWI_STATE_LO_CLOCK | 3690 BWI_STATE_LO_GATED_CLOCK | 3691 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK); 3692 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo); 3693 3694 /* Flush pending bus write */ 3695 CSR_READ_4(sc, BWI_STATE_LO); 3696 DELAY(1); 3697 3698 /* Enable regwin with normal clock */ 3699 state_lo = BWI_STATE_LO_CLOCK | 3700 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK); 3701 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo); 3702 3703 /* Flush pending bus write */ 3704 CSR_READ_4(sc, BWI_STATE_LO); 3705 DELAY(1); 3706 } 3707 3708 static void 3709 bwi_set_bssid(struct bwi_softc *sc, const uint8_t *bssid) 3710 { 3711 struct ifnet *ifp = sc->sc_ifp; 3712 struct bwi_mac *mac; 3713 struct bwi_myaddr_bssid buf; 3714 const uint8_t *p; 3715 uint32_t val; 3716 int n, i; 3717 3718 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 3719 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 3720 mac = (struct bwi_mac *)sc->sc_cur_regwin; 3721 3722 bwi_set_addr_filter(sc, BWI_ADDR_FILTER_BSSID, bssid); 3723 3724 bcopy(IF_LLADDR(ifp), buf.myaddr, sizeof(buf.myaddr)); 3725 bcopy(bssid, buf.bssid, sizeof(buf.bssid)); 3726 3727 n = sizeof(buf) / sizeof(val); 3728 p = (const uint8_t *)&buf; 3729 for (i = 0; i < n; ++i) { 3730 int j; 3731 3732 val = 0; 3733 for (j = 0; j < sizeof(val); ++j) 3734 val |= ((uint32_t)(*p++)) << (j * 8); 3735 3736 TMPLT_WRITE_4(mac, 0x20 + (i * sizeof(val)), val); 3737 } 3738 } 3739 3740 static void 3741 bwi_updateslot(struct ieee80211com *ic) 3742 { 3743 struct bwi_softc *sc = ic->ic_softc; 3744 struct bwi_mac *mac; 3745 3746 BWI_LOCK(sc); 3747 if (ic->ic_ifp->if_drv_flags & IFF_DRV_RUNNING) { 3748 DPRINTF(sc, BWI_DBG_80211, "%s\n", __func__); 3749 3750 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 3751 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 3752 mac = (struct bwi_mac *)sc->sc_cur_regwin; 3753 3754 bwi_mac_updateslot(mac, (ic->ic_flags & IEEE80211_F_SHSLOT)); 3755 } 3756 BWI_UNLOCK(sc); 3757 } 3758 3759 static void 3760 bwi_calibrate(void *xsc) 3761 { 3762 struct bwi_softc *sc = xsc; 3763 #ifdef INVARIANTS 3764 struct ifnet *ifp = sc->sc_ifp; 3765 struct ieee80211com *ic = ifp->if_l2com; 3766 #endif 3767 struct bwi_mac *mac; 3768 3769 BWI_ASSERT_LOCKED(sc); 3770 3771 KASSERT(ic->ic_opmode != IEEE80211_M_MONITOR, 3772 ("opmode %d", ic->ic_opmode)); 3773 3774 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 3775 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 3776 mac = (struct bwi_mac *)sc->sc_cur_regwin; 3777 3778 bwi_mac_calibrate_txpower(mac, sc->sc_txpwrcb_type); 3779 sc->sc_txpwrcb_type = BWI_TXPWR_CALIB; 3780 3781 /* XXX 15 seconds */ 3782 callout_reset(&sc->sc_calib_ch, hz * 15, bwi_calibrate, sc); 3783 } 3784 3785 static int 3786 bwi_calc_rssi(struct bwi_softc *sc, const struct bwi_rxbuf_hdr *hdr) 3787 { 3788 struct bwi_mac *mac; 3789 3790 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 3791 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 3792 mac = (struct bwi_mac *)sc->sc_cur_regwin; 3793 3794 return bwi_rf_calc_rssi(mac, hdr); 3795 } 3796 3797 static int 3798 bwi_calc_noise(struct bwi_softc *sc) 3799 { 3800 struct bwi_mac *mac; 3801 3802 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 3803 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 3804 mac = (struct bwi_mac *)sc->sc_cur_regwin; 3805 3806 return bwi_rf_calc_noise(mac); 3807 } 3808 3809 static __inline uint8_t 3810 bwi_plcp2rate(const uint32_t plcp0, enum ieee80211_phytype type) 3811 { 3812 uint32_t plcp = le32toh(plcp0) & IEEE80211_OFDM_PLCP_RATE_MASK; 3813 return (ieee80211_plcp2rate(plcp, type)); 3814 } 3815 3816 static void 3817 bwi_rx_radiotap(struct bwi_softc *sc, struct mbuf *m, 3818 struct bwi_rxbuf_hdr *hdr, const void *plcp, int rate, int rssi, int noise) 3819 { 3820 const struct ieee80211_frame_min *wh; 3821 3822 sc->sc_rx_th.wr_flags = IEEE80211_RADIOTAP_F_FCS; 3823 if (htole16(hdr->rxh_flags1) & BWI_RXH_F1_SHPREAMBLE) 3824 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 3825 3826 wh = mtod(m, const struct ieee80211_frame_min *); 3827 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) 3828 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_WEP; 3829 3830 sc->sc_rx_th.wr_tsf = hdr->rxh_tsf; /* No endian convertion */ 3831 sc->sc_rx_th.wr_rate = rate; 3832 sc->sc_rx_th.wr_antsignal = rssi; 3833 sc->sc_rx_th.wr_antnoise = noise; 3834 } 3835 3836 static void 3837 bwi_led_attach(struct bwi_softc *sc) 3838 { 3839 const uint8_t *led_act = NULL; 3840 uint16_t gpio, val[BWI_LED_MAX]; 3841 int i; 3842 3843 #define N(arr) (int)(sizeof(arr) / sizeof(arr[0])) 3844 3845 for (i = 0; i < N(bwi_vendor_led_act); ++i) { 3846 if (sc->sc_pci_subvid == bwi_vendor_led_act[i].vid) { 3847 led_act = bwi_vendor_led_act[i].led_act; 3848 break; 3849 } 3850 } 3851 if (led_act == NULL) 3852 led_act = bwi_default_led_act; 3853 3854 #undef N 3855 3856 gpio = bwi_read_sprom(sc, BWI_SPROM_GPIO01); 3857 val[0] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_0); 3858 val[1] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_1); 3859 3860 gpio = bwi_read_sprom(sc, BWI_SPROM_GPIO23); 3861 val[2] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_2); 3862 val[3] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_3); 3863 3864 for (i = 0; i < BWI_LED_MAX; ++i) { 3865 struct bwi_led *led = &sc->sc_leds[i]; 3866 3867 if (val[i] == 0xff) { 3868 led->l_act = led_act[i]; 3869 } else { 3870 if (val[i] & BWI_LED_ACT_LOW) 3871 led->l_flags |= BWI_LED_F_ACTLOW; 3872 led->l_act = __SHIFTOUT(val[i], BWI_LED_ACT_MASK); 3873 } 3874 led->l_mask = (1 << i); 3875 3876 if (led->l_act == BWI_LED_ACT_BLINK_SLOW || 3877 led->l_act == BWI_LED_ACT_BLINK_POLL || 3878 led->l_act == BWI_LED_ACT_BLINK) { 3879 led->l_flags |= BWI_LED_F_BLINK; 3880 if (led->l_act == BWI_LED_ACT_BLINK_POLL) 3881 led->l_flags |= BWI_LED_F_POLLABLE; 3882 else if (led->l_act == BWI_LED_ACT_BLINK_SLOW) 3883 led->l_flags |= BWI_LED_F_SLOW; 3884 3885 if (sc->sc_blink_led == NULL) { 3886 sc->sc_blink_led = led; 3887 if (led->l_flags & BWI_LED_F_SLOW) 3888 BWI_LED_SLOWDOWN(sc->sc_led_idle); 3889 } 3890 } 3891 3892 DPRINTF(sc, BWI_DBG_LED | BWI_DBG_ATTACH, 3893 "%dth led, act %d, lowact %d\n", i, 3894 led->l_act, led->l_flags & BWI_LED_F_ACTLOW); 3895 } 3896 callout_init_mtx(&sc->sc_led_blink_ch, &sc->sc_mtx, 0); 3897 } 3898 3899 static __inline uint16_t 3900 bwi_led_onoff(const struct bwi_led *led, uint16_t val, int on) 3901 { 3902 if (led->l_flags & BWI_LED_F_ACTLOW) 3903 on = !on; 3904 if (on) 3905 val |= led->l_mask; 3906 else 3907 val &= ~led->l_mask; 3908 return val; 3909 } 3910 3911 static void 3912 bwi_led_newstate(struct bwi_softc *sc, enum ieee80211_state nstate) 3913 { 3914 struct ifnet *ifp = sc->sc_ifp; 3915 struct ieee80211com *ic = ifp->if_l2com; 3916 uint16_t val; 3917 int i; 3918 3919 if (nstate == IEEE80211_S_INIT) { 3920 callout_stop(&sc->sc_led_blink_ch); 3921 sc->sc_led_blinking = 0; 3922 } 3923 3924 if ((ic->ic_ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 3925 return; 3926 3927 val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL); 3928 for (i = 0; i < BWI_LED_MAX; ++i) { 3929 struct bwi_led *led = &sc->sc_leds[i]; 3930 int on; 3931 3932 if (led->l_act == BWI_LED_ACT_UNKN || 3933 led->l_act == BWI_LED_ACT_NULL) 3934 continue; 3935 3936 if ((led->l_flags & BWI_LED_F_BLINK) && 3937 nstate != IEEE80211_S_INIT) 3938 continue; 3939 3940 switch (led->l_act) { 3941 case BWI_LED_ACT_ON: /* Always on */ 3942 on = 1; 3943 break; 3944 case BWI_LED_ACT_OFF: /* Always off */ 3945 case BWI_LED_ACT_5GHZ: /* TODO: 11A */ 3946 on = 0; 3947 break; 3948 default: 3949 on = 1; 3950 switch (nstate) { 3951 case IEEE80211_S_INIT: 3952 on = 0; 3953 break; 3954 case IEEE80211_S_RUN: 3955 if (led->l_act == BWI_LED_ACT_11G && 3956 ic->ic_curmode != IEEE80211_MODE_11G) 3957 on = 0; 3958 break; 3959 default: 3960 if (led->l_act == BWI_LED_ACT_ASSOC) 3961 on = 0; 3962 break; 3963 } 3964 break; 3965 } 3966 3967 val = bwi_led_onoff(led, val, on); 3968 } 3969 CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val); 3970 } 3971 static void 3972 bwi_led_event(struct bwi_softc *sc, int event) 3973 { 3974 struct bwi_led *led = sc->sc_blink_led; 3975 int rate; 3976 3977 if (event == BWI_LED_EVENT_POLL) { 3978 if ((led->l_flags & BWI_LED_F_POLLABLE) == 0) 3979 return; 3980 if (ticks - sc->sc_led_ticks < sc->sc_led_idle) 3981 return; 3982 } 3983 3984 sc->sc_led_ticks = ticks; 3985 if (sc->sc_led_blinking) 3986 return; 3987 3988 switch (event) { 3989 case BWI_LED_EVENT_RX: 3990 rate = sc->sc_rx_rate; 3991 break; 3992 case BWI_LED_EVENT_TX: 3993 rate = sc->sc_tx_rate; 3994 break; 3995 case BWI_LED_EVENT_POLL: 3996 rate = 0; 3997 break; 3998 default: 3999 panic("unknown LED event %d\n", event); 4000 break; 4001 } 4002 bwi_led_blink_start(sc, bwi_led_duration[rate].on_dur, 4003 bwi_led_duration[rate].off_dur); 4004 } 4005 4006 static void 4007 bwi_led_blink_start(struct bwi_softc *sc, int on_dur, int off_dur) 4008 { 4009 struct bwi_led *led = sc->sc_blink_led; 4010 uint16_t val; 4011 4012 val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL); 4013 val = bwi_led_onoff(led, val, 1); 4014 CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val); 4015 4016 if (led->l_flags & BWI_LED_F_SLOW) { 4017 BWI_LED_SLOWDOWN(on_dur); 4018 BWI_LED_SLOWDOWN(off_dur); 4019 } 4020 4021 sc->sc_led_blinking = 1; 4022 sc->sc_led_blink_offdur = off_dur; 4023 4024 callout_reset(&sc->sc_led_blink_ch, on_dur, bwi_led_blink_next, sc); 4025 } 4026 4027 static void 4028 bwi_led_blink_next(void *xsc) 4029 { 4030 struct bwi_softc *sc = xsc; 4031 uint16_t val; 4032 4033 val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL); 4034 val = bwi_led_onoff(sc->sc_blink_led, val, 0); 4035 CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val); 4036 4037 callout_reset(&sc->sc_led_blink_ch, sc->sc_led_blink_offdur, 4038 bwi_led_blink_end, sc); 4039 } 4040 4041 static void 4042 bwi_led_blink_end(void *xsc) 4043 { 4044 struct bwi_softc *sc = xsc; 4045 sc->sc_led_blinking = 0; 4046 } 4047 4048 static void 4049 bwi_restart(void *xsc, int pending) 4050 { 4051 struct bwi_softc *sc = xsc; 4052 struct ifnet *ifp = sc->sc_ifp; 4053 4054 if_printf(ifp, "%s begin, help!\n", __func__); 4055 BWI_LOCK(sc); 4056 bwi_init_statechg(xsc, 0); 4057 #if 0 4058 bwi_start_locked(ifp); 4059 #endif 4060 BWI_UNLOCK(sc); 4061 } 4062