1 /* 2 * Copyright (c) 2007 The DragonFly Project. All rights reserved. 3 * 4 * This code is derived from software contributed to The DragonFly Project 5 * by Sepherosa Ziehau <sepherosa@gmail.com> 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * 3. Neither the name of The DragonFly Project nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific, prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 24 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 25 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 27 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 29 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * $DragonFly: src/sys/dev/netif/bwi/if_bwi.c,v 1.19 2008/02/15 11:15:38 sephe Exp $ 35 */ 36 37 #include <sys/cdefs.h> 38 __FBSDID("$FreeBSD$"); 39 40 #include "opt_inet.h" 41 #include "opt_bwi.h" 42 43 #include <sys/param.h> 44 #include <sys/endian.h> 45 #include <sys/kernel.h> 46 #include <sys/bus.h> 47 #include <sys/malloc.h> 48 #include <sys/proc.h> 49 #include <sys/rman.h> 50 #include <sys/socket.h> 51 #include <sys/sockio.h> 52 #include <sys/sysctl.h> 53 #include <sys/systm.h> 54 #include <sys/taskqueue.h> 55 56 #include <net/if.h> 57 #include <net/if_dl.h> 58 #include <net/if_media.h> 59 #include <net/if_types.h> 60 #include <net/if_arp.h> 61 #include <net/ethernet.h> 62 #include <net/if_llc.h> 63 64 #include <net80211/ieee80211_var.h> 65 #include <net80211/ieee80211_radiotap.h> 66 #include <net80211/ieee80211_regdomain.h> 67 #include <net80211/ieee80211_amrr.h> 68 #include <net80211/ieee80211_phy.h> 69 70 #include <net/bpf.h> 71 72 #ifdef INET 73 #include <netinet/in.h> 74 #include <netinet/if_ether.h> 75 #endif 76 77 #include <machine/bus.h> 78 79 #include <dev/pci/pcivar.h> 80 #include <dev/pci/pcireg.h> 81 82 #include <dev/bwi/bitops.h> 83 #include <dev/bwi/if_bwireg.h> 84 #include <dev/bwi/if_bwivar.h> 85 #include <dev/bwi/bwimac.h> 86 #include <dev/bwi/bwirf.h> 87 88 struct bwi_clock_freq { 89 u_int clkfreq_min; 90 u_int clkfreq_max; 91 }; 92 93 struct bwi_myaddr_bssid { 94 uint8_t myaddr[IEEE80211_ADDR_LEN]; 95 uint8_t bssid[IEEE80211_ADDR_LEN]; 96 } __packed; 97 98 static struct ieee80211vap *bwi_vap_create(struct ieee80211com *, 99 const char [IFNAMSIZ], int, int, int, 100 const uint8_t [IEEE80211_ADDR_LEN], 101 const uint8_t [IEEE80211_ADDR_LEN]); 102 static void bwi_vap_delete(struct ieee80211vap *); 103 static void bwi_init(void *); 104 static int bwi_ioctl(struct ifnet *, u_long, caddr_t); 105 static void bwi_start(struct ifnet *); 106 static void bwi_start_locked(struct ifnet *); 107 static int bwi_raw_xmit(struct ieee80211_node *, struct mbuf *, 108 const struct ieee80211_bpf_params *); 109 static void bwi_watchdog(struct ifnet *); 110 static void bwi_scan_start(struct ieee80211com *); 111 static void bwi_set_channel(struct ieee80211com *); 112 static void bwi_scan_end(struct ieee80211com *); 113 static int bwi_newstate(struct ieee80211vap *, enum ieee80211_state, int); 114 static void bwi_updateslot(struct ifnet *); 115 static struct ieee80211_node *bwi_node_alloc(struct ieee80211vap *, 116 const uint8_t [IEEE80211_ADDR_LEN]); 117 static void bwi_newassoc(struct ieee80211_node *, int); 118 static int bwi_media_change(struct ifnet *); 119 120 static void bwi_calibrate(void *); 121 122 static int bwi_calc_rssi(struct bwi_softc *, const struct bwi_rxbuf_hdr *); 123 static int bwi_calc_noise(struct bwi_softc *); 124 static __inline uint8_t bwi_ofdm_plcp2rate(const uint32_t *); 125 static __inline uint8_t bwi_ds_plcp2rate(const struct ieee80211_ds_plcp_hdr *); 126 static void bwi_rx_radiotap(struct bwi_softc *, struct mbuf *, 127 struct bwi_rxbuf_hdr *, const void *, int, int, int); 128 129 static void bwi_restart(void *, int); 130 static void bwi_init_statechg(struct bwi_softc *, int); 131 static void bwi_stop(struct bwi_softc *, int); 132 static void bwi_stop_locked(struct bwi_softc *, int); 133 static int bwi_newbuf(struct bwi_softc *, int, int); 134 static int bwi_encap(struct bwi_softc *, int, struct mbuf *, 135 struct ieee80211_node *); 136 static int bwi_encap_raw(struct bwi_softc *, int, struct mbuf *, 137 struct ieee80211_node *, 138 const struct ieee80211_bpf_params *); 139 140 static void bwi_init_rxdesc_ring32(struct bwi_softc *, uint32_t, 141 bus_addr_t, int, int); 142 static void bwi_reset_rx_ring32(struct bwi_softc *, uint32_t); 143 144 static int bwi_init_tx_ring32(struct bwi_softc *, int); 145 static int bwi_init_rx_ring32(struct bwi_softc *); 146 static int bwi_init_txstats32(struct bwi_softc *); 147 static void bwi_free_tx_ring32(struct bwi_softc *, int); 148 static void bwi_free_rx_ring32(struct bwi_softc *); 149 static void bwi_free_txstats32(struct bwi_softc *); 150 static void bwi_setup_rx_desc32(struct bwi_softc *, int, bus_addr_t, int); 151 static void bwi_setup_tx_desc32(struct bwi_softc *, struct bwi_ring_data *, 152 int, bus_addr_t, int); 153 static int bwi_rxeof32(struct bwi_softc *); 154 static void bwi_start_tx32(struct bwi_softc *, uint32_t, int); 155 static void bwi_txeof_status32(struct bwi_softc *); 156 157 static int bwi_init_tx_ring64(struct bwi_softc *, int); 158 static int bwi_init_rx_ring64(struct bwi_softc *); 159 static int bwi_init_txstats64(struct bwi_softc *); 160 static void bwi_free_tx_ring64(struct bwi_softc *, int); 161 static void bwi_free_rx_ring64(struct bwi_softc *); 162 static void bwi_free_txstats64(struct bwi_softc *); 163 static void bwi_setup_rx_desc64(struct bwi_softc *, int, bus_addr_t, int); 164 static void bwi_setup_tx_desc64(struct bwi_softc *, struct bwi_ring_data *, 165 int, bus_addr_t, int); 166 static int bwi_rxeof64(struct bwi_softc *); 167 static void bwi_start_tx64(struct bwi_softc *, uint32_t, int); 168 static void bwi_txeof_status64(struct bwi_softc *); 169 170 static int bwi_rxeof(struct bwi_softc *, int); 171 static void _bwi_txeof(struct bwi_softc *, uint16_t, int, int); 172 static void bwi_txeof(struct bwi_softc *); 173 static void bwi_txeof_status(struct bwi_softc *, int); 174 static void bwi_enable_intrs(struct bwi_softc *, uint32_t); 175 static void bwi_disable_intrs(struct bwi_softc *, uint32_t); 176 177 static int bwi_dma_alloc(struct bwi_softc *); 178 static void bwi_dma_free(struct bwi_softc *); 179 static int bwi_dma_ring_alloc(struct bwi_softc *, bus_dma_tag_t, 180 struct bwi_ring_data *, bus_size_t, 181 uint32_t); 182 static int bwi_dma_mbuf_create(struct bwi_softc *); 183 static void bwi_dma_mbuf_destroy(struct bwi_softc *, int, int); 184 static int bwi_dma_txstats_alloc(struct bwi_softc *, uint32_t, bus_size_t); 185 static void bwi_dma_txstats_free(struct bwi_softc *); 186 static void bwi_dma_ring_addr(void *, bus_dma_segment_t *, int, int); 187 static void bwi_dma_buf_addr(void *, bus_dma_segment_t *, int, 188 bus_size_t, int); 189 190 static void bwi_power_on(struct bwi_softc *, int); 191 static int bwi_power_off(struct bwi_softc *, int); 192 static int bwi_set_clock_mode(struct bwi_softc *, enum bwi_clock_mode); 193 static int bwi_set_clock_delay(struct bwi_softc *); 194 static void bwi_get_clock_freq(struct bwi_softc *, struct bwi_clock_freq *); 195 static int bwi_get_pwron_delay(struct bwi_softc *sc); 196 static void bwi_set_addr_filter(struct bwi_softc *, uint16_t, 197 const uint8_t *); 198 static void bwi_set_bssid(struct bwi_softc *, const uint8_t *); 199 200 static void bwi_get_card_flags(struct bwi_softc *); 201 static void bwi_get_eaddr(struct bwi_softc *, uint16_t, uint8_t *); 202 203 static int bwi_bus_attach(struct bwi_softc *); 204 static int bwi_bbp_attach(struct bwi_softc *); 205 static int bwi_bbp_power_on(struct bwi_softc *, enum bwi_clock_mode); 206 static void bwi_bbp_power_off(struct bwi_softc *); 207 208 static const char *bwi_regwin_name(const struct bwi_regwin *); 209 static uint32_t bwi_regwin_disable_bits(struct bwi_softc *); 210 static void bwi_regwin_info(struct bwi_softc *, uint16_t *, uint8_t *); 211 static int bwi_regwin_select(struct bwi_softc *, int); 212 213 static void bwi_led_attach(struct bwi_softc *); 214 static void bwi_led_newstate(struct bwi_softc *, enum ieee80211_state); 215 static void bwi_led_event(struct bwi_softc *, int); 216 static void bwi_led_blink_start(struct bwi_softc *, int, int); 217 static void bwi_led_blink_next(void *); 218 static void bwi_led_blink_end(void *); 219 220 static const struct { 221 uint16_t did_min; 222 uint16_t did_max; 223 uint16_t bbp_id; 224 } bwi_bbpid_map[] = { 225 { 0x4301, 0x4301, 0x4301 }, 226 { 0x4305, 0x4307, 0x4307 }, 227 { 0x4403, 0x4403, 0x4402 }, 228 { 0x4610, 0x4615, 0x4610 }, 229 { 0x4710, 0x4715, 0x4710 }, 230 { 0x4720, 0x4725, 0x4309 } 231 }; 232 233 static const struct { 234 uint16_t bbp_id; 235 int nregwin; 236 } bwi_regwin_count[] = { 237 { 0x4301, 5 }, 238 { 0x4306, 6 }, 239 { 0x4307, 5 }, 240 { 0x4310, 8 }, 241 { 0x4401, 3 }, 242 { 0x4402, 3 }, 243 { 0x4610, 9 }, 244 { 0x4704, 9 }, 245 { 0x4710, 9 }, 246 { 0x5365, 7 } 247 }; 248 249 #define CLKSRC(src) \ 250 [BWI_CLKSRC_ ## src] = { \ 251 .freq_min = BWI_CLKSRC_ ##src## _FMIN, \ 252 .freq_max = BWI_CLKSRC_ ##src## _FMAX \ 253 } 254 255 static const struct { 256 u_int freq_min; 257 u_int freq_max; 258 } bwi_clkfreq[BWI_CLKSRC_MAX] = { 259 CLKSRC(LP_OSC), 260 CLKSRC(CS_OSC), 261 CLKSRC(PCI) 262 }; 263 264 #undef CLKSRC 265 266 #define VENDOR_LED_ACT(vendor) \ 267 { \ 268 .vid = PCI_VENDOR_##vendor, \ 269 .led_act = { BWI_VENDOR_LED_ACT_##vendor } \ 270 } 271 272 static const struct { 273 #define PCI_VENDOR_COMPAQ 0x0e11 274 #define PCI_VENDOR_LINKSYS 0x1737 275 uint16_t vid; 276 uint8_t led_act[BWI_LED_MAX]; 277 } bwi_vendor_led_act[] = { 278 VENDOR_LED_ACT(COMPAQ), 279 VENDOR_LED_ACT(LINKSYS) 280 #undef PCI_VENDOR_LINKSYS 281 #undef PCI_VENDOR_COMPAQ 282 }; 283 284 static const uint8_t bwi_default_led_act[BWI_LED_MAX] = 285 { BWI_VENDOR_LED_ACT_DEFAULT }; 286 287 #undef VENDOR_LED_ACT 288 289 static const struct { 290 int on_dur; 291 int off_dur; 292 } bwi_led_duration[109] = { 293 [0] = { 400, 100 }, 294 [2] = { 150, 75 }, 295 [4] = { 90, 45 }, 296 [11] = { 66, 34 }, 297 [12] = { 53, 26 }, 298 [18] = { 42, 21 }, 299 [22] = { 35, 17 }, 300 [24] = { 32, 16 }, 301 [36] = { 21, 10 }, 302 [48] = { 16, 8 }, 303 [72] = { 11, 5 }, 304 [96] = { 9, 4 }, 305 [108] = { 7, 3 } 306 }; 307 308 #ifdef BWI_DEBUG 309 #ifdef BWI_DEBUG_VERBOSE 310 static uint32_t bwi_debug = BWI_DBG_ATTACH | BWI_DBG_INIT | BWI_DBG_TXPOWER; 311 #else 312 static uint32_t bwi_debug; 313 #endif 314 TUNABLE_INT("hw.bwi.debug", (int *)&bwi_debug); 315 #endif /* BWI_DEBUG */ 316 317 static const uint8_t bwi_zero_addr[IEEE80211_ADDR_LEN]; 318 319 uint16_t 320 bwi_read_sprom(struct bwi_softc *sc, uint16_t ofs) 321 { 322 return CSR_READ_2(sc, ofs + BWI_SPROM_START); 323 } 324 325 static __inline void 326 bwi_setup_desc32(struct bwi_softc *sc, struct bwi_desc32 *desc_array, 327 int ndesc, int desc_idx, bus_addr_t paddr, int buf_len, 328 int tx) 329 { 330 struct bwi_desc32 *desc = &desc_array[desc_idx]; 331 uint32_t ctrl, addr, addr_hi, addr_lo; 332 333 addr_lo = __SHIFTOUT(paddr, BWI_DESC32_A_ADDR_MASK); 334 addr_hi = __SHIFTOUT(paddr, BWI_DESC32_A_FUNC_MASK); 335 336 addr = __SHIFTIN(addr_lo, BWI_DESC32_A_ADDR_MASK) | 337 __SHIFTIN(BWI_DESC32_A_FUNC_TXRX, BWI_DESC32_A_FUNC_MASK); 338 339 ctrl = __SHIFTIN(buf_len, BWI_DESC32_C_BUFLEN_MASK) | 340 __SHIFTIN(addr_hi, BWI_DESC32_C_ADDRHI_MASK); 341 if (desc_idx == ndesc - 1) 342 ctrl |= BWI_DESC32_C_EOR; 343 if (tx) { 344 /* XXX */ 345 ctrl |= BWI_DESC32_C_FRAME_START | 346 BWI_DESC32_C_FRAME_END | 347 BWI_DESC32_C_INTR; 348 } 349 350 desc->addr = htole32(addr); 351 desc->ctrl = htole32(ctrl); 352 } 353 354 int 355 bwi_attach(struct bwi_softc *sc) 356 { 357 struct ieee80211com *ic; 358 device_t dev = sc->sc_dev; 359 struct ifnet *ifp; 360 struct bwi_mac *mac; 361 struct bwi_phy *phy; 362 int i, error; 363 uint8_t bands; 364 uint8_t macaddr[IEEE80211_ADDR_LEN]; 365 366 BWI_LOCK_INIT(sc); 367 368 /* 369 * Initialize taskq and various tasks 370 */ 371 sc->sc_tq = taskqueue_create("bwi_taskq", M_NOWAIT | M_ZERO, 372 taskqueue_thread_enqueue, &sc->sc_tq); 373 taskqueue_start_threads(&sc->sc_tq, 1, PI_NET, "%s taskq", 374 device_get_nameunit(dev)); 375 TASK_INIT(&sc->sc_restart_task, 0, bwi_restart, sc); 376 377 callout_init_mtx(&sc->sc_calib_ch, &sc->sc_mtx, 0); 378 379 /* 380 * Initialize sysctl variables 381 */ 382 sc->sc_fw_version = BWI_FW_VERSION3; 383 sc->sc_led_idle = (2350 * hz) / 1000; 384 sc->sc_led_blink = 1; 385 sc->sc_txpwr_calib = 1; 386 #ifdef BWI_DEBUG 387 sc->sc_debug = bwi_debug; 388 #endif 389 bwi_power_on(sc, 1); 390 391 error = bwi_bbp_attach(sc); 392 if (error) 393 goto fail; 394 395 error = bwi_bbp_power_on(sc, BWI_CLOCK_MODE_FAST); 396 if (error) 397 goto fail; 398 399 if (BWI_REGWIN_EXIST(&sc->sc_com_regwin)) { 400 error = bwi_set_clock_delay(sc); 401 if (error) 402 goto fail; 403 404 error = bwi_set_clock_mode(sc, BWI_CLOCK_MODE_FAST); 405 if (error) 406 goto fail; 407 408 error = bwi_get_pwron_delay(sc); 409 if (error) 410 goto fail; 411 } 412 413 error = bwi_bus_attach(sc); 414 if (error) 415 goto fail; 416 417 bwi_get_card_flags(sc); 418 419 bwi_led_attach(sc); 420 421 for (i = 0; i < sc->sc_nmac; ++i) { 422 struct bwi_regwin *old; 423 424 mac = &sc->sc_mac[i]; 425 error = bwi_regwin_switch(sc, &mac->mac_regwin, &old); 426 if (error) 427 goto fail; 428 429 error = bwi_mac_lateattach(mac); 430 if (error) 431 goto fail; 432 433 error = bwi_regwin_switch(sc, old, NULL); 434 if (error) 435 goto fail; 436 } 437 438 /* 439 * XXX First MAC is known to exist 440 * TODO2 441 */ 442 mac = &sc->sc_mac[0]; 443 phy = &mac->mac_phy; 444 445 bwi_bbp_power_off(sc); 446 447 error = bwi_dma_alloc(sc); 448 if (error) 449 goto fail; 450 451 ifp = sc->sc_ifp = if_alloc(IFT_IEEE80211); 452 if (ifp == NULL) { 453 device_printf(dev, "can not if_alloc()\n"); 454 error = ENOSPC; 455 goto fail; 456 } 457 ic = ifp->if_l2com; 458 459 /* set these up early for if_printf use */ 460 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 461 462 ifp->if_softc = sc; 463 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 464 ifp->if_init = bwi_init; 465 ifp->if_ioctl = bwi_ioctl; 466 ifp->if_start = bwi_start; 467 ifp->if_watchdog = bwi_watchdog; 468 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); 469 ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN; 470 IFQ_SET_READY(&ifp->if_snd); 471 472 /* 473 * Setup ratesets, phytype, channels and get MAC address 474 */ 475 bands = 0; 476 if (phy->phy_mode == IEEE80211_MODE_11B || 477 phy->phy_mode == IEEE80211_MODE_11G) { 478 setbit(&bands, IEEE80211_MODE_11B); 479 if (phy->phy_mode == IEEE80211_MODE_11B) { 480 ic->ic_phytype = IEEE80211_T_DS; 481 } else { 482 ic->ic_phytype = IEEE80211_T_OFDM; 483 setbit(&bands, IEEE80211_MODE_11G); 484 } 485 486 bwi_get_eaddr(sc, BWI_SPROM_11BG_EADDR, macaddr); 487 if (IEEE80211_IS_MULTICAST(macaddr)) { 488 bwi_get_eaddr(sc, BWI_SPROM_11A_EADDR, macaddr); 489 if (IEEE80211_IS_MULTICAST(macaddr)) { 490 device_printf(dev, 491 "invalid MAC address: %6D\n", 492 macaddr, ":"); 493 } 494 } 495 } else if (phy->phy_mode == IEEE80211_MODE_11A) { 496 /* TODO:11A */ 497 setbit(&bands, IEEE80211_MODE_11A); 498 error = ENXIO; 499 goto fail; 500 } else { 501 panic("unknown phymode %d\n", phy->phy_mode); 502 } 503 504 /* Get locale */ 505 sc->sc_locale = __SHIFTOUT(bwi_read_sprom(sc, BWI_SPROM_CARD_INFO), 506 BWI_SPROM_CARD_INFO_LOCALE); 507 DPRINTF(sc, BWI_DBG_ATTACH, "locale: %d\n", sc->sc_locale); 508 /* XXX use locale */ 509 ieee80211_init_channels(ic, NULL, &bands); 510 511 ic->ic_ifp = ifp; 512 ic->ic_caps = IEEE80211_C_STA | 513 IEEE80211_C_SHSLOT | 514 IEEE80211_C_SHPREAMBLE | 515 IEEE80211_C_WPA | 516 IEEE80211_C_BGSCAN | 517 IEEE80211_C_MONITOR; 518 ic->ic_opmode = IEEE80211_M_STA; 519 ieee80211_ifattach(ic, macaddr); 520 521 ic->ic_headroom = sizeof(struct bwi_txbuf_hdr); 522 523 /* override default methods */ 524 ic->ic_vap_create = bwi_vap_create; 525 ic->ic_vap_delete = bwi_vap_delete; 526 ic->ic_raw_xmit = bwi_raw_xmit; 527 ic->ic_updateslot = bwi_updateslot; 528 ic->ic_node_alloc = bwi_node_alloc; 529 ic->ic_scan_start = bwi_scan_start; 530 ic->ic_scan_end = bwi_scan_end; 531 ic->ic_set_channel = bwi_set_channel; 532 533 sc->sc_rates = ieee80211_get_ratetable(ic->ic_curchan); 534 535 ieee80211_radiotap_attach(ic, 536 &sc->sc_tx_th.wt_ihdr, sizeof(sc->sc_tx_th), 537 BWI_TX_RADIOTAP_PRESENT, 538 &sc->sc_rx_th.wr_ihdr, sizeof(sc->sc_rx_th), 539 BWI_RX_RADIOTAP_PRESENT); 540 541 /* 542 * Add sysctl nodes 543 */ 544 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), 545 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 546 "fw_version", CTLFLAG_RD, &sc->sc_fw_version, 0, 547 "Firmware version"); 548 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), 549 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 550 "led_idle", CTLFLAG_RW, &sc->sc_led_idle, 0, 551 "# ticks before LED enters idle state"); 552 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 553 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 554 "led_blink", CTLFLAG_RW, &sc->sc_led_blink, 0, 555 "Allow LED to blink"); 556 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 557 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 558 "txpwr_calib", CTLFLAG_RW, &sc->sc_txpwr_calib, 0, 559 "Enable software TX power calibration"); 560 #ifdef BWI_DEBUG 561 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), 562 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 563 "debug", CTLFLAG_RW, &sc->sc_debug, 0, "Debug flags"); 564 #endif 565 if (bootverbose) 566 ieee80211_announce(ic); 567 568 return (0); 569 fail: 570 BWI_LOCK_DESTROY(sc); 571 return (error); 572 } 573 574 int 575 bwi_detach(struct bwi_softc *sc) 576 { 577 struct ifnet *ifp = sc->sc_ifp; 578 struct ieee80211com *ic = ifp->if_l2com; 579 int i; 580 581 bwi_stop(sc, 1); 582 callout_drain(&sc->sc_led_blink_ch); 583 callout_drain(&sc->sc_calib_ch); 584 ieee80211_ifdetach(ic); 585 586 for (i = 0; i < sc->sc_nmac; ++i) 587 bwi_mac_detach(&sc->sc_mac[i]); 588 bwi_dma_free(sc); 589 if_free(ifp); 590 taskqueue_free(sc->sc_tq); 591 592 BWI_LOCK_DESTROY(sc); 593 594 return (0); 595 } 596 597 static struct ieee80211vap * 598 bwi_vap_create(struct ieee80211com *ic, 599 const char name[IFNAMSIZ], int unit, int opmode, int flags, 600 const uint8_t bssid[IEEE80211_ADDR_LEN], 601 const uint8_t mac[IEEE80211_ADDR_LEN]) 602 { 603 struct bwi_vap *bvp; 604 struct ieee80211vap *vap; 605 606 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */ 607 return NULL; 608 bvp = (struct bwi_vap *) malloc(sizeof(struct bwi_vap), 609 M_80211_VAP, M_WAITOK | M_ZERO); 610 if (bvp == NULL) 611 return NULL; 612 vap = &bvp->bv_vap; 613 /* enable s/w bmiss handling for sta mode */ 614 ieee80211_vap_setup(ic, vap, name, unit, opmode, 615 flags | IEEE80211_CLONE_NOBEACONS, bssid, mac); 616 617 /* override default methods */ 618 bvp->bv_newstate = vap->iv_newstate; 619 vap->iv_newstate = bwi_newstate; 620 #if 0 621 vap->iv_update_beacon = bwi_beacon_update; 622 #endif 623 ieee80211_amrr_init(&bvp->bv_amrr, vap, 624 IEEE80211_AMRR_MIN_SUCCESS_THRESHOLD, 625 IEEE80211_AMRR_MAX_SUCCESS_THRESHOLD, 626 500 /*ms*/); 627 628 /* complete setup */ 629 ieee80211_vap_attach(vap, bwi_media_change, ieee80211_media_status); 630 ic->ic_opmode = opmode; 631 return vap; 632 } 633 634 static void 635 bwi_vap_delete(struct ieee80211vap *vap) 636 { 637 struct bwi_vap *bvp = BWI_VAP(vap); 638 639 ieee80211_amrr_cleanup(&bvp->bv_amrr); 640 ieee80211_vap_detach(vap); 641 free(bvp, M_80211_VAP); 642 } 643 644 void 645 bwi_suspend(struct bwi_softc *sc) 646 { 647 bwi_stop(sc, 1); 648 } 649 650 void 651 bwi_resume(struct bwi_softc *sc) 652 { 653 struct ifnet *ifp = sc->sc_ifp; 654 655 if (ifp->if_flags & IFF_UP) 656 bwi_init(sc); 657 } 658 659 int 660 bwi_shutdown(struct bwi_softc *sc) 661 { 662 bwi_stop(sc, 1); 663 return 0; 664 } 665 666 static void 667 bwi_power_on(struct bwi_softc *sc, int with_pll) 668 { 669 uint32_t gpio_in, gpio_out, gpio_en; 670 uint16_t status; 671 672 gpio_in = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_IN, 4); 673 if (gpio_in & BWI_PCIM_GPIO_PWR_ON) 674 goto back; 675 676 gpio_out = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, 4); 677 gpio_en = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, 4); 678 679 gpio_out |= BWI_PCIM_GPIO_PWR_ON; 680 gpio_en |= BWI_PCIM_GPIO_PWR_ON; 681 if (with_pll) { 682 /* Turn off PLL first */ 683 gpio_out |= BWI_PCIM_GPIO_PLL_PWR_OFF; 684 gpio_en |= BWI_PCIM_GPIO_PLL_PWR_OFF; 685 } 686 687 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, gpio_out, 4); 688 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, gpio_en, 4); 689 DELAY(1000); 690 691 if (with_pll) { 692 /* Turn on PLL */ 693 gpio_out &= ~BWI_PCIM_GPIO_PLL_PWR_OFF; 694 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, gpio_out, 4); 695 DELAY(5000); 696 } 697 698 back: 699 /* Clear "Signaled Target Abort" */ 700 status = pci_read_config(sc->sc_dev, PCIR_STATUS, 2); 701 status &= ~PCIM_STATUS_STABORT; 702 pci_write_config(sc->sc_dev, PCIR_STATUS, status, 2); 703 } 704 705 static int 706 bwi_power_off(struct bwi_softc *sc, int with_pll) 707 { 708 uint32_t gpio_out, gpio_en; 709 710 pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_IN, 4); /* dummy read */ 711 gpio_out = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, 4); 712 gpio_en = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, 4); 713 714 gpio_out &= ~BWI_PCIM_GPIO_PWR_ON; 715 gpio_en |= BWI_PCIM_GPIO_PWR_ON; 716 if (with_pll) { 717 gpio_out |= BWI_PCIM_GPIO_PLL_PWR_OFF; 718 gpio_en |= BWI_PCIM_GPIO_PLL_PWR_OFF; 719 } 720 721 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, gpio_out, 4); 722 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, gpio_en, 4); 723 return 0; 724 } 725 726 int 727 bwi_regwin_switch(struct bwi_softc *sc, struct bwi_regwin *rw, 728 struct bwi_regwin **old_rw) 729 { 730 int error; 731 732 if (old_rw != NULL) 733 *old_rw = NULL; 734 735 if (!BWI_REGWIN_EXIST(rw)) 736 return EINVAL; 737 738 if (sc->sc_cur_regwin != rw) { 739 error = bwi_regwin_select(sc, rw->rw_id); 740 if (error) { 741 device_printf(sc->sc_dev, "can't select regwin %d\n", 742 rw->rw_id); 743 return error; 744 } 745 } 746 747 if (old_rw != NULL) 748 *old_rw = sc->sc_cur_regwin; 749 sc->sc_cur_regwin = rw; 750 return 0; 751 } 752 753 static int 754 bwi_regwin_select(struct bwi_softc *sc, int id) 755 { 756 uint32_t win = BWI_PCIM_REGWIN(id); 757 int i; 758 759 #define RETRY_MAX 50 760 for (i = 0; i < RETRY_MAX; ++i) { 761 pci_write_config(sc->sc_dev, BWI_PCIR_SEL_REGWIN, win, 4); 762 if (pci_read_config(sc->sc_dev, BWI_PCIR_SEL_REGWIN, 4) == win) 763 return 0; 764 DELAY(10); 765 } 766 #undef RETRY_MAX 767 768 return ENXIO; 769 } 770 771 static void 772 bwi_regwin_info(struct bwi_softc *sc, uint16_t *type, uint8_t *rev) 773 { 774 uint32_t val; 775 776 val = CSR_READ_4(sc, BWI_ID_HI); 777 *type = BWI_ID_HI_REGWIN_TYPE(val); 778 *rev = BWI_ID_HI_REGWIN_REV(val); 779 780 DPRINTF(sc, BWI_DBG_ATTACH, "regwin: type 0x%03x, rev %d, " 781 "vendor 0x%04x\n", *type, *rev, 782 __SHIFTOUT(val, BWI_ID_HI_REGWIN_VENDOR_MASK)); 783 } 784 785 static int 786 bwi_bbp_attach(struct bwi_softc *sc) 787 { 788 #define N(arr) (int)(sizeof(arr) / sizeof(arr[0])) 789 uint16_t bbp_id, rw_type; 790 uint8_t rw_rev; 791 uint32_t info; 792 int error, nregwin, i; 793 794 /* 795 * Get 0th regwin information 796 * NOTE: 0th regwin should exist 797 */ 798 error = bwi_regwin_select(sc, 0); 799 if (error) { 800 device_printf(sc->sc_dev, "can't select regwin 0\n"); 801 return error; 802 } 803 bwi_regwin_info(sc, &rw_type, &rw_rev); 804 805 /* 806 * Find out BBP id 807 */ 808 bbp_id = 0; 809 info = 0; 810 if (rw_type == BWI_REGWIN_T_COM) { 811 info = CSR_READ_4(sc, BWI_INFO); 812 bbp_id = __SHIFTOUT(info, BWI_INFO_BBPID_MASK); 813 814 BWI_CREATE_REGWIN(&sc->sc_com_regwin, 0, rw_type, rw_rev); 815 816 sc->sc_cap = CSR_READ_4(sc, BWI_CAPABILITY); 817 } else { 818 for (i = 0; i < N(bwi_bbpid_map); ++i) { 819 if (sc->sc_pci_did >= bwi_bbpid_map[i].did_min && 820 sc->sc_pci_did <= bwi_bbpid_map[i].did_max) { 821 bbp_id = bwi_bbpid_map[i].bbp_id; 822 break; 823 } 824 } 825 if (bbp_id == 0) { 826 device_printf(sc->sc_dev, "no BBP id for device id " 827 "0x%04x\n", sc->sc_pci_did); 828 return ENXIO; 829 } 830 831 info = __SHIFTIN(sc->sc_pci_revid, BWI_INFO_BBPREV_MASK) | 832 __SHIFTIN(0, BWI_INFO_BBPPKG_MASK); 833 } 834 835 /* 836 * Find out number of regwins 837 */ 838 nregwin = 0; 839 if (rw_type == BWI_REGWIN_T_COM && rw_rev >= 4) { 840 nregwin = __SHIFTOUT(info, BWI_INFO_NREGWIN_MASK); 841 } else { 842 for (i = 0; i < N(bwi_regwin_count); ++i) { 843 if (bwi_regwin_count[i].bbp_id == bbp_id) { 844 nregwin = bwi_regwin_count[i].nregwin; 845 break; 846 } 847 } 848 if (nregwin == 0) { 849 device_printf(sc->sc_dev, "no number of win for " 850 "BBP id 0x%04x\n", bbp_id); 851 return ENXIO; 852 } 853 } 854 855 /* Record BBP id/rev for later using */ 856 sc->sc_bbp_id = bbp_id; 857 sc->sc_bbp_rev = __SHIFTOUT(info, BWI_INFO_BBPREV_MASK); 858 sc->sc_bbp_pkg = __SHIFTOUT(info, BWI_INFO_BBPPKG_MASK); 859 device_printf(sc->sc_dev, "BBP: id 0x%04x, rev 0x%x, pkg %d\n", 860 sc->sc_bbp_id, sc->sc_bbp_rev, sc->sc_bbp_pkg); 861 862 DPRINTF(sc, BWI_DBG_ATTACH, "nregwin %d, cap 0x%08x\n", 863 nregwin, sc->sc_cap); 864 865 /* 866 * Create rest of the regwins 867 */ 868 869 /* Don't re-create common regwin, if it is already created */ 870 i = BWI_REGWIN_EXIST(&sc->sc_com_regwin) ? 1 : 0; 871 872 for (; i < nregwin; ++i) { 873 /* 874 * Get regwin information 875 */ 876 error = bwi_regwin_select(sc, i); 877 if (error) { 878 device_printf(sc->sc_dev, 879 "can't select regwin %d\n", i); 880 return error; 881 } 882 bwi_regwin_info(sc, &rw_type, &rw_rev); 883 884 /* 885 * Try attach: 886 * 1) Bus (PCI/PCIE) regwin 887 * 2) MAC regwin 888 * Ignore rest types of regwin 889 */ 890 if (rw_type == BWI_REGWIN_T_BUSPCI || 891 rw_type == BWI_REGWIN_T_BUSPCIE) { 892 if (BWI_REGWIN_EXIST(&sc->sc_bus_regwin)) { 893 device_printf(sc->sc_dev, 894 "bus regwin already exists\n"); 895 } else { 896 BWI_CREATE_REGWIN(&sc->sc_bus_regwin, i, 897 rw_type, rw_rev); 898 } 899 } else if (rw_type == BWI_REGWIN_T_MAC) { 900 /* XXX ignore return value */ 901 bwi_mac_attach(sc, i, rw_rev); 902 } 903 } 904 905 /* At least one MAC shold exist */ 906 if (!BWI_REGWIN_EXIST(&sc->sc_mac[0].mac_regwin)) { 907 device_printf(sc->sc_dev, "no MAC was found\n"); 908 return ENXIO; 909 } 910 KASSERT(sc->sc_nmac > 0, ("no mac's")); 911 912 /* Bus regwin must exist */ 913 if (!BWI_REGWIN_EXIST(&sc->sc_bus_regwin)) { 914 device_printf(sc->sc_dev, "no bus regwin was found\n"); 915 return ENXIO; 916 } 917 918 /* Start with first MAC */ 919 error = bwi_regwin_switch(sc, &sc->sc_mac[0].mac_regwin, NULL); 920 if (error) 921 return error; 922 923 return 0; 924 #undef N 925 } 926 927 int 928 bwi_bus_init(struct bwi_softc *sc, struct bwi_mac *mac) 929 { 930 struct bwi_regwin *old, *bus; 931 uint32_t val; 932 int error; 933 934 bus = &sc->sc_bus_regwin; 935 KASSERT(sc->sc_cur_regwin == &mac->mac_regwin, ("not cur regwin")); 936 937 /* 938 * Tell bus to generate requested interrupts 939 */ 940 if (bus->rw_rev < 6 && bus->rw_type == BWI_REGWIN_T_BUSPCI) { 941 /* 942 * NOTE: Read BWI_FLAGS from MAC regwin 943 */ 944 val = CSR_READ_4(sc, BWI_FLAGS); 945 946 error = bwi_regwin_switch(sc, bus, &old); 947 if (error) 948 return error; 949 950 CSR_SETBITS_4(sc, BWI_INTRVEC, (val & BWI_FLAGS_INTR_MASK)); 951 } else { 952 uint32_t mac_mask; 953 954 mac_mask = 1 << mac->mac_id; 955 956 error = bwi_regwin_switch(sc, bus, &old); 957 if (error) 958 return error; 959 960 val = pci_read_config(sc->sc_dev, BWI_PCIR_INTCTL, 4); 961 val |= mac_mask << 8; 962 pci_write_config(sc->sc_dev, BWI_PCIR_INTCTL, val, 4); 963 } 964 965 if (sc->sc_flags & BWI_F_BUS_INITED) 966 goto back; 967 968 if (bus->rw_type == BWI_REGWIN_T_BUSPCI) { 969 /* 970 * Enable prefetch and burst 971 */ 972 CSR_SETBITS_4(sc, BWI_BUS_CONFIG, 973 BWI_BUS_CONFIG_PREFETCH | BWI_BUS_CONFIG_BURST); 974 975 if (bus->rw_rev < 5) { 976 struct bwi_regwin *com = &sc->sc_com_regwin; 977 978 /* 979 * Configure timeouts for bus operation 980 */ 981 982 /* 983 * Set service timeout and request timeout 984 */ 985 CSR_SETBITS_4(sc, BWI_CONF_LO, 986 __SHIFTIN(BWI_CONF_LO_SERVTO, BWI_CONF_LO_SERVTO_MASK) | 987 __SHIFTIN(BWI_CONF_LO_REQTO, BWI_CONF_LO_REQTO_MASK)); 988 989 /* 990 * If there is common regwin, we switch to that regwin 991 * and switch back to bus regwin once we have done. 992 */ 993 if (BWI_REGWIN_EXIST(com)) { 994 error = bwi_regwin_switch(sc, com, NULL); 995 if (error) 996 return error; 997 } 998 999 /* Let bus know what we have changed */ 1000 CSR_WRITE_4(sc, BWI_BUS_ADDR, BWI_BUS_ADDR_MAGIC); 1001 CSR_READ_4(sc, BWI_BUS_ADDR); /* Flush */ 1002 CSR_WRITE_4(sc, BWI_BUS_DATA, 0); 1003 CSR_READ_4(sc, BWI_BUS_DATA); /* Flush */ 1004 1005 if (BWI_REGWIN_EXIST(com)) { 1006 error = bwi_regwin_switch(sc, bus, NULL); 1007 if (error) 1008 return error; 1009 } 1010 } else if (bus->rw_rev >= 11) { 1011 /* 1012 * Enable memory read multiple 1013 */ 1014 CSR_SETBITS_4(sc, BWI_BUS_CONFIG, BWI_BUS_CONFIG_MRM); 1015 } 1016 } else { 1017 /* TODO:PCIE */ 1018 } 1019 1020 sc->sc_flags |= BWI_F_BUS_INITED; 1021 back: 1022 return bwi_regwin_switch(sc, old, NULL); 1023 } 1024 1025 static void 1026 bwi_get_card_flags(struct bwi_softc *sc) 1027 { 1028 #define PCI_VENDOR_APPLE 0x106b 1029 #define PCI_VENDOR_DELL 0x1028 1030 sc->sc_card_flags = bwi_read_sprom(sc, BWI_SPROM_CARD_FLAGS); 1031 if (sc->sc_card_flags == 0xffff) 1032 sc->sc_card_flags = 0; 1033 1034 if (sc->sc_pci_subvid == PCI_VENDOR_DELL && 1035 sc->sc_bbp_id == BWI_BBPID_BCM4301 && 1036 sc->sc_pci_revid == 0x74) 1037 sc->sc_card_flags |= BWI_CARD_F_BT_COEXIST; 1038 1039 if (sc->sc_pci_subvid == PCI_VENDOR_APPLE && 1040 sc->sc_pci_subdid == 0x4e && /* XXX */ 1041 sc->sc_pci_revid > 0x40) 1042 sc->sc_card_flags |= BWI_CARD_F_PA_GPIO9; 1043 1044 DPRINTF(sc, BWI_DBG_ATTACH, "card flags 0x%04x\n", sc->sc_card_flags); 1045 #undef PCI_VENDOR_DELL 1046 #undef PCI_VENDOR_APPLE 1047 } 1048 1049 static void 1050 bwi_get_eaddr(struct bwi_softc *sc, uint16_t eaddr_ofs, uint8_t *eaddr) 1051 { 1052 int i; 1053 1054 for (i = 0; i < 3; ++i) { 1055 *((uint16_t *)eaddr + i) = 1056 htobe16(bwi_read_sprom(sc, eaddr_ofs + 2 * i)); 1057 } 1058 } 1059 1060 static void 1061 bwi_get_clock_freq(struct bwi_softc *sc, struct bwi_clock_freq *freq) 1062 { 1063 struct bwi_regwin *com; 1064 uint32_t val; 1065 u_int div; 1066 int src; 1067 1068 bzero(freq, sizeof(*freq)); 1069 com = &sc->sc_com_regwin; 1070 1071 KASSERT(BWI_REGWIN_EXIST(com), ("regwin does not exist")); 1072 KASSERT(sc->sc_cur_regwin == com, ("wrong regwin")); 1073 KASSERT(sc->sc_cap & BWI_CAP_CLKMODE, ("wrong clock mode")); 1074 1075 /* 1076 * Calculate clock frequency 1077 */ 1078 src = -1; 1079 div = 0; 1080 if (com->rw_rev < 6) { 1081 val = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, 4); 1082 if (val & BWI_PCIM_GPIO_OUT_CLKSRC) { 1083 src = BWI_CLKSRC_PCI; 1084 div = 64; 1085 } else { 1086 src = BWI_CLKSRC_CS_OSC; 1087 div = 32; 1088 } 1089 } else if (com->rw_rev < 10) { 1090 val = CSR_READ_4(sc, BWI_CLOCK_CTRL); 1091 1092 src = __SHIFTOUT(val, BWI_CLOCK_CTRL_CLKSRC); 1093 if (src == BWI_CLKSRC_LP_OSC) { 1094 div = 1; 1095 } else { 1096 div = (__SHIFTOUT(val, BWI_CLOCK_CTRL_FDIV) + 1) << 2; 1097 1098 /* Unknown source */ 1099 if (src >= BWI_CLKSRC_MAX) 1100 src = BWI_CLKSRC_CS_OSC; 1101 } 1102 } else { 1103 val = CSR_READ_4(sc, BWI_CLOCK_INFO); 1104 1105 src = BWI_CLKSRC_CS_OSC; 1106 div = (__SHIFTOUT(val, BWI_CLOCK_INFO_FDIV) + 1) << 2; 1107 } 1108 1109 KASSERT(src >= 0 && src < BWI_CLKSRC_MAX, ("bad src %d", src)); 1110 KASSERT(div != 0, ("div zero")); 1111 1112 DPRINTF(sc, BWI_DBG_ATTACH, "clksrc %s\n", 1113 src == BWI_CLKSRC_PCI ? "PCI" : 1114 (src == BWI_CLKSRC_LP_OSC ? "LP_OSC" : "CS_OSC")); 1115 1116 freq->clkfreq_min = bwi_clkfreq[src].freq_min / div; 1117 freq->clkfreq_max = bwi_clkfreq[src].freq_max / div; 1118 1119 DPRINTF(sc, BWI_DBG_ATTACH, "clkfreq min %u, max %u\n", 1120 freq->clkfreq_min, freq->clkfreq_max); 1121 } 1122 1123 static int 1124 bwi_set_clock_mode(struct bwi_softc *sc, enum bwi_clock_mode clk_mode) 1125 { 1126 struct bwi_regwin *old, *com; 1127 uint32_t clk_ctrl, clk_src; 1128 int error, pwr_off = 0; 1129 1130 com = &sc->sc_com_regwin; 1131 if (!BWI_REGWIN_EXIST(com)) 1132 return 0; 1133 1134 if (com->rw_rev >= 10 || com->rw_rev < 6) 1135 return 0; 1136 1137 /* 1138 * For common regwin whose rev is [6, 10), the chip 1139 * must be capable to change clock mode. 1140 */ 1141 if ((sc->sc_cap & BWI_CAP_CLKMODE) == 0) 1142 return 0; 1143 1144 error = bwi_regwin_switch(sc, com, &old); 1145 if (error) 1146 return error; 1147 1148 if (clk_mode == BWI_CLOCK_MODE_FAST) 1149 bwi_power_on(sc, 0); /* Don't turn on PLL */ 1150 1151 clk_ctrl = CSR_READ_4(sc, BWI_CLOCK_CTRL); 1152 clk_src = __SHIFTOUT(clk_ctrl, BWI_CLOCK_CTRL_CLKSRC); 1153 1154 switch (clk_mode) { 1155 case BWI_CLOCK_MODE_FAST: 1156 clk_ctrl &= ~BWI_CLOCK_CTRL_SLOW; 1157 clk_ctrl |= BWI_CLOCK_CTRL_IGNPLL; 1158 break; 1159 case BWI_CLOCK_MODE_SLOW: 1160 clk_ctrl |= BWI_CLOCK_CTRL_SLOW; 1161 break; 1162 case BWI_CLOCK_MODE_DYN: 1163 clk_ctrl &= ~(BWI_CLOCK_CTRL_SLOW | 1164 BWI_CLOCK_CTRL_IGNPLL | 1165 BWI_CLOCK_CTRL_NODYN); 1166 if (clk_src != BWI_CLKSRC_CS_OSC) { 1167 clk_ctrl |= BWI_CLOCK_CTRL_NODYN; 1168 pwr_off = 1; 1169 } 1170 break; 1171 } 1172 CSR_WRITE_4(sc, BWI_CLOCK_CTRL, clk_ctrl); 1173 1174 if (pwr_off) 1175 bwi_power_off(sc, 0); /* Leave PLL as it is */ 1176 1177 return bwi_regwin_switch(sc, old, NULL); 1178 } 1179 1180 static int 1181 bwi_set_clock_delay(struct bwi_softc *sc) 1182 { 1183 struct bwi_regwin *old, *com; 1184 int error; 1185 1186 com = &sc->sc_com_regwin; 1187 if (!BWI_REGWIN_EXIST(com)) 1188 return 0; 1189 1190 error = bwi_regwin_switch(sc, com, &old); 1191 if (error) 1192 return error; 1193 1194 if (sc->sc_bbp_id == BWI_BBPID_BCM4321) { 1195 if (sc->sc_bbp_rev == 0) 1196 CSR_WRITE_4(sc, BWI_CONTROL, BWI_CONTROL_MAGIC0); 1197 else if (sc->sc_bbp_rev == 1) 1198 CSR_WRITE_4(sc, BWI_CONTROL, BWI_CONTROL_MAGIC1); 1199 } 1200 1201 if (sc->sc_cap & BWI_CAP_CLKMODE) { 1202 if (com->rw_rev >= 10) { 1203 CSR_FILT_SETBITS_4(sc, BWI_CLOCK_INFO, 0xffff, 0x40000); 1204 } else { 1205 struct bwi_clock_freq freq; 1206 1207 bwi_get_clock_freq(sc, &freq); 1208 CSR_WRITE_4(sc, BWI_PLL_ON_DELAY, 1209 howmany(freq.clkfreq_max * 150, 1000000)); 1210 CSR_WRITE_4(sc, BWI_FREQ_SEL_DELAY, 1211 howmany(freq.clkfreq_max * 15, 1000000)); 1212 } 1213 } 1214 1215 return bwi_regwin_switch(sc, old, NULL); 1216 } 1217 1218 static void 1219 bwi_init(void *xsc) 1220 { 1221 struct bwi_softc *sc = xsc; 1222 struct ifnet *ifp = sc->sc_ifp; 1223 struct ieee80211com *ic = ifp->if_l2com; 1224 1225 BWI_LOCK(sc); 1226 bwi_init_statechg(sc, 1); 1227 BWI_UNLOCK(sc); 1228 1229 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1230 ieee80211_start_all(ic); /* start all vap's */ 1231 } 1232 1233 static void 1234 bwi_init_statechg(struct bwi_softc *sc, int statechg) 1235 { 1236 struct ifnet *ifp = sc->sc_ifp; 1237 struct bwi_mac *mac; 1238 int error; 1239 1240 bwi_stop_locked(sc, statechg); 1241 1242 bwi_bbp_power_on(sc, BWI_CLOCK_MODE_FAST); 1243 1244 /* TODO: 2 MAC */ 1245 1246 mac = &sc->sc_mac[0]; 1247 error = bwi_regwin_switch(sc, &mac->mac_regwin, NULL); 1248 if (error) { 1249 if_printf(ifp, "%s: error %d on regwin switch\n", 1250 __func__, error); 1251 goto bad; 1252 } 1253 error = bwi_mac_init(mac); 1254 if (error) { 1255 if_printf(ifp, "%s: error %d on MAC init\n", __func__, error); 1256 goto bad; 1257 } 1258 1259 bwi_bbp_power_on(sc, BWI_CLOCK_MODE_DYN); 1260 1261 bwi_set_bssid(sc, bwi_zero_addr); /* Clear BSSID */ 1262 bwi_set_addr_filter(sc, BWI_ADDR_FILTER_MYADDR, IF_LLADDR(ifp)); 1263 1264 bwi_mac_reset_hwkeys(mac); 1265 1266 if ((mac->mac_flags & BWI_MAC_F_HAS_TXSTATS) == 0) { 1267 int i; 1268 1269 #define NRETRY 1000 1270 /* 1271 * Drain any possible pending TX status 1272 */ 1273 for (i = 0; i < NRETRY; ++i) { 1274 if ((CSR_READ_4(sc, BWI_TXSTATUS0) & 1275 BWI_TXSTATUS0_VALID) == 0) 1276 break; 1277 CSR_READ_4(sc, BWI_TXSTATUS1); 1278 } 1279 if (i == NRETRY) 1280 if_printf(ifp, "%s: can't drain TX status\n", __func__); 1281 #undef NRETRY 1282 } 1283 1284 if (mac->mac_phy.phy_mode == IEEE80211_MODE_11G) 1285 bwi_mac_updateslot(mac, 1); 1286 1287 /* Start MAC */ 1288 error = bwi_mac_start(mac); 1289 if (error) { 1290 if_printf(ifp, "%s: error %d starting MAC\n", __func__, error); 1291 goto bad; 1292 } 1293 1294 /* Clear stop flag before enabling interrupt */ 1295 sc->sc_flags &= ~BWI_F_STOP; 1296 1297 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1298 1299 /* Enable intrs */ 1300 bwi_enable_intrs(sc, BWI_INIT_INTRS); 1301 return; 1302 bad: 1303 bwi_stop_locked(sc, 1); 1304 } 1305 1306 static int 1307 bwi_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1308 { 1309 #define IS_RUNNING(ifp) \ 1310 ((ifp->if_flags & IFF_UP) && (ifp->if_drv_flags & IFF_DRV_RUNNING)) 1311 struct bwi_softc *sc = ifp->if_softc; 1312 struct ieee80211com *ic = ifp->if_l2com; 1313 struct ifreq *ifr = (struct ifreq *) data; 1314 int error = 0, startall = 0; 1315 1316 switch (cmd) { 1317 case SIOCSIFFLAGS: 1318 BWI_LOCK(sc); 1319 if (IS_RUNNING(ifp)) { 1320 struct bwi_mac *mac; 1321 int promisc = -1; 1322 1323 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 1324 ("current regwin type %d", 1325 sc->sc_cur_regwin->rw_type)); 1326 mac = (struct bwi_mac *)sc->sc_cur_regwin; 1327 1328 if ((ifp->if_flags & IFF_PROMISC) && 1329 (sc->sc_flags & BWI_F_PROMISC) == 0) { 1330 promisc = 1; 1331 sc->sc_flags |= BWI_F_PROMISC; 1332 } else if ((ifp->if_flags & IFF_PROMISC) == 0 && 1333 (sc->sc_flags & BWI_F_PROMISC)) { 1334 promisc = 0; 1335 sc->sc_flags &= ~BWI_F_PROMISC; 1336 } 1337 1338 if (promisc >= 0) 1339 bwi_mac_set_promisc(mac, promisc); 1340 } 1341 1342 if (ifp->if_flags & IFF_UP) { 1343 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 1344 bwi_init_statechg(sc, 1); 1345 startall = 1; 1346 } 1347 } else { 1348 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1349 bwi_stop_locked(sc, 1); 1350 } 1351 BWI_UNLOCK(sc); 1352 if (startall) 1353 ieee80211_start_all(ic); 1354 break; 1355 case SIOCGIFMEDIA: 1356 error = ifmedia_ioctl(ifp, ifr, &ic->ic_media, cmd); 1357 break; 1358 case SIOCGIFADDR: 1359 error = ether_ioctl(ifp, cmd, data); 1360 break; 1361 default: 1362 error = EINVAL; 1363 break; 1364 } 1365 return error; 1366 #undef IS_RUNNING 1367 } 1368 1369 static void 1370 bwi_start(struct ifnet *ifp) 1371 { 1372 struct bwi_softc *sc = ifp->if_softc; 1373 1374 BWI_LOCK(sc); 1375 bwi_start_locked(ifp); 1376 BWI_UNLOCK(sc); 1377 } 1378 1379 static void 1380 bwi_start_locked(struct ifnet *ifp) 1381 { 1382 struct bwi_softc *sc = ifp->if_softc; 1383 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING]; 1384 struct ieee80211_frame *wh; 1385 struct ieee80211_node *ni; 1386 struct ieee80211_key *k; 1387 struct mbuf *m; 1388 int trans, idx; 1389 1390 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 1391 return; 1392 1393 trans = 0; 1394 idx = tbd->tbd_idx; 1395 1396 while (tbd->tbd_buf[idx].tb_mbuf == NULL) { 1397 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); /* XXX: LOCK */ 1398 if (m == NULL) 1399 break; 1400 1401 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif; 1402 wh = mtod(m, struct ieee80211_frame *); 1403 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1404 k = ieee80211_crypto_encap(ni, m); 1405 if (k == NULL) { 1406 ieee80211_free_node(ni); 1407 m_freem(m); 1408 ifp->if_oerrors++; 1409 continue; 1410 } 1411 } 1412 wh = NULL; /* Catch any invalid use */ 1413 1414 if (bwi_encap(sc, idx, m, ni) != 0) { 1415 /* 'm' is freed in bwi_encap() if we reach here */ 1416 if (ni != NULL) 1417 ieee80211_free_node(ni); 1418 ifp->if_oerrors++; 1419 continue; 1420 } 1421 1422 trans = 1; 1423 tbd->tbd_used++; 1424 idx = (idx + 1) % BWI_TX_NDESC; 1425 1426 ifp->if_opackets++; 1427 1428 if (tbd->tbd_used + BWI_TX_NSPRDESC >= BWI_TX_NDESC) { 1429 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1430 break; 1431 } 1432 } 1433 tbd->tbd_idx = idx; 1434 1435 if (trans) 1436 ifp->if_timer = 5; 1437 } 1438 1439 static int 1440 bwi_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 1441 const struct ieee80211_bpf_params *params) 1442 { 1443 struct ieee80211com *ic = ni->ni_ic; 1444 struct ifnet *ifp = ic->ic_ifp; 1445 struct bwi_softc *sc = ifp->if_softc; 1446 /* XXX wme? */ 1447 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING]; 1448 int idx, error; 1449 1450 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 1451 ieee80211_free_node(ni); 1452 m_freem(m); 1453 return ENETDOWN; 1454 } 1455 1456 BWI_LOCK(sc); 1457 idx = tbd->tbd_idx; 1458 KASSERT(tbd->tbd_buf[idx].tb_mbuf == NULL, ("slot %d not empty", idx)); 1459 if (params == NULL) { 1460 /* 1461 * Legacy path; interpret frame contents to decide 1462 * precisely how to send the frame. 1463 */ 1464 error = bwi_encap(sc, idx, m, ni); 1465 } else { 1466 /* 1467 * Caller supplied explicit parameters to use in 1468 * sending the frame. 1469 */ 1470 error = bwi_encap_raw(sc, idx, m, ni, params); 1471 } 1472 if (error == 0) { 1473 ifp->if_opackets++; 1474 if (++tbd->tbd_used + BWI_TX_NSPRDESC >= BWI_TX_NDESC) 1475 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1476 tbd->tbd_idx = (idx + 1) % BWI_TX_NDESC; 1477 ifp->if_timer = 5; 1478 } else { 1479 /* NB: m is reclaimed on encap failure */ 1480 ieee80211_free_node(ni); 1481 ifp->if_oerrors++; 1482 } 1483 BWI_UNLOCK(sc); 1484 return error; 1485 } 1486 1487 static void 1488 bwi_watchdog(struct ifnet *ifp) 1489 { 1490 struct bwi_softc *sc = ifp->if_softc; 1491 1492 BWI_LOCK(sc); 1493 if ((ifp->if_drv_flags & IFF_DRV_RUNNING)) { 1494 if_printf(ifp, "watchdog timeout\n"); 1495 ifp->if_oerrors++; 1496 taskqueue_enqueue(sc->sc_tq, &sc->sc_restart_task); 1497 } 1498 BWI_UNLOCK(sc); 1499 } 1500 1501 static void 1502 bwi_stop(struct bwi_softc *sc, int statechg) 1503 { 1504 BWI_LOCK(sc); 1505 bwi_stop_locked(sc, statechg); 1506 BWI_UNLOCK(sc); 1507 } 1508 1509 static void 1510 bwi_stop_locked(struct bwi_softc *sc, int statechg) 1511 { 1512 struct ifnet *ifp = sc->sc_ifp; 1513 struct bwi_mac *mac; 1514 int i, error, pwr_off = 0; 1515 1516 BWI_ASSERT_LOCKED(sc); 1517 1518 callout_stop(&sc->sc_calib_ch); 1519 callout_stop(&sc->sc_led_blink_ch); 1520 sc->sc_led_blinking = 0; 1521 sc->sc_flags |= BWI_F_STOP; 1522 1523 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1524 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 1525 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 1526 mac = (struct bwi_mac *)sc->sc_cur_regwin; 1527 1528 bwi_disable_intrs(sc, BWI_ALL_INTRS); 1529 CSR_READ_4(sc, BWI_MAC_INTR_MASK); 1530 bwi_mac_stop(mac); 1531 } 1532 1533 for (i = 0; i < sc->sc_nmac; ++i) { 1534 struct bwi_regwin *old_rw; 1535 1536 mac = &sc->sc_mac[i]; 1537 if ((mac->mac_flags & BWI_MAC_F_INITED) == 0) 1538 continue; 1539 1540 error = bwi_regwin_switch(sc, &mac->mac_regwin, &old_rw); 1541 if (error) 1542 continue; 1543 1544 bwi_mac_shutdown(mac); 1545 pwr_off = 1; 1546 1547 bwi_regwin_switch(sc, old_rw, NULL); 1548 } 1549 1550 if (pwr_off) 1551 bwi_bbp_power_off(sc); 1552 1553 sc->sc_tx_timer = 0; 1554 ifp->if_timer = 0; 1555 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1556 } 1557 1558 void 1559 bwi_intr(void *xsc) 1560 { 1561 struct bwi_softc *sc = xsc; 1562 struct ifnet *ifp = sc->sc_ifp; 1563 struct bwi_mac *mac; 1564 uint32_t intr_status; 1565 uint32_t txrx_intr_status[BWI_TXRX_NRING]; 1566 int i, txrx_error, tx = 0, rx_data = -1; 1567 1568 BWI_LOCK(sc); 1569 1570 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || 1571 (sc->sc_flags & BWI_F_STOP)) { 1572 BWI_UNLOCK(sc); 1573 return; 1574 } 1575 /* 1576 * Get interrupt status 1577 */ 1578 intr_status = CSR_READ_4(sc, BWI_MAC_INTR_STATUS); 1579 if (intr_status == 0xffffffff) { /* Not for us */ 1580 BWI_UNLOCK(sc); 1581 return; 1582 } 1583 1584 DPRINTF(sc, BWI_DBG_INTR, "intr status 0x%08x\n", intr_status); 1585 1586 intr_status &= CSR_READ_4(sc, BWI_MAC_INTR_MASK); 1587 if (intr_status == 0) { /* Nothing is interesting */ 1588 BWI_UNLOCK(sc); 1589 return; 1590 } 1591 1592 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 1593 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 1594 mac = (struct bwi_mac *)sc->sc_cur_regwin; 1595 1596 txrx_error = 0; 1597 DPRINTF(sc, BWI_DBG_INTR, "%s\n", "TX/RX intr"); 1598 for (i = 0; i < BWI_TXRX_NRING; ++i) { 1599 uint32_t mask; 1600 1601 if (BWI_TXRX_IS_RX(i)) 1602 mask = BWI_TXRX_RX_INTRS; 1603 else 1604 mask = BWI_TXRX_TX_INTRS; 1605 1606 txrx_intr_status[i] = 1607 CSR_READ_4(sc, BWI_TXRX_INTR_STATUS(i)) & mask; 1608 1609 _DPRINTF(sc, BWI_DBG_INTR, ", %d 0x%08x", 1610 i, txrx_intr_status[i]); 1611 1612 if (txrx_intr_status[i] & BWI_TXRX_INTR_ERROR) { 1613 if_printf(ifp, 1614 "%s: intr fatal TX/RX (%d) error 0x%08x\n", 1615 __func__, i, txrx_intr_status[i]); 1616 txrx_error = 1; 1617 } 1618 } 1619 _DPRINTF(sc, BWI_DBG_INTR, "%s\n", ""); 1620 1621 /* 1622 * Acknowledge interrupt 1623 */ 1624 CSR_WRITE_4(sc, BWI_MAC_INTR_STATUS, intr_status); 1625 1626 for (i = 0; i < BWI_TXRX_NRING; ++i) 1627 CSR_WRITE_4(sc, BWI_TXRX_INTR_STATUS(i), txrx_intr_status[i]); 1628 1629 /* Disable all interrupts */ 1630 bwi_disable_intrs(sc, BWI_ALL_INTRS); 1631 1632 /* 1633 * http://bcm-specs.sipsolutions.net/Interrupts 1634 * Says for this bit (0x800): 1635 * "Fatal Error 1636 * 1637 * We got this one while testing things when by accident the 1638 * template ram wasn't set to big endian when it should have 1639 * been after writing the initial values. It keeps on being 1640 * triggered, the only way to stop it seems to shut down the 1641 * chip." 1642 * 1643 * Suggesting that we should never get it and if we do we're not 1644 * feeding TX packets into the MAC correctly if we do... Apparently, 1645 * it is valid only on mac version 5 and higher, but I couldn't 1646 * find a reference for that... Since I see them from time to time 1647 * on my card, this suggests an error in the tx path still... 1648 */ 1649 if (intr_status & BWI_INTR_PHY_TXERR) { 1650 if (mac->mac_flags & BWI_MAC_F_PHYE_RESET) { 1651 if_printf(ifp, "%s: intr PHY TX error\n", __func__); 1652 taskqueue_enqueue(sc->sc_tq, &sc->sc_restart_task); 1653 BWI_UNLOCK(sc); 1654 return; 1655 } 1656 } 1657 1658 if (txrx_error) { 1659 /* TODO: reset device */ 1660 } 1661 1662 if (intr_status & BWI_INTR_TBTT) 1663 bwi_mac_config_ps(mac); 1664 1665 if (intr_status & BWI_INTR_EO_ATIM) 1666 if_printf(ifp, "EO_ATIM\n"); 1667 1668 if (intr_status & BWI_INTR_PMQ) { 1669 for (;;) { 1670 if ((CSR_READ_4(sc, BWI_MAC_PS_STATUS) & 0x8) == 0) 1671 break; 1672 } 1673 CSR_WRITE_2(sc, BWI_MAC_PS_STATUS, 0x2); 1674 } 1675 1676 if (intr_status & BWI_INTR_NOISE) 1677 if_printf(ifp, "intr noise\n"); 1678 1679 if (txrx_intr_status[0] & BWI_TXRX_INTR_RX) { 1680 rx_data = sc->sc_rxeof(sc); 1681 if (sc->sc_flags & BWI_F_STOP) { 1682 BWI_UNLOCK(sc); 1683 return; 1684 } 1685 } 1686 1687 if (txrx_intr_status[3] & BWI_TXRX_INTR_RX) { 1688 sc->sc_txeof_status(sc); 1689 tx = 1; 1690 } 1691 1692 if (intr_status & BWI_INTR_TX_DONE) { 1693 bwi_txeof(sc); 1694 tx = 1; 1695 } 1696 1697 /* Re-enable interrupts */ 1698 bwi_enable_intrs(sc, BWI_INIT_INTRS); 1699 1700 if (sc->sc_blink_led != NULL && sc->sc_led_blink) { 1701 int evt = BWI_LED_EVENT_NONE; 1702 1703 if (tx && rx_data > 0) { 1704 if (sc->sc_rx_rate > sc->sc_tx_rate) 1705 evt = BWI_LED_EVENT_RX; 1706 else 1707 evt = BWI_LED_EVENT_TX; 1708 } else if (tx) { 1709 evt = BWI_LED_EVENT_TX; 1710 } else if (rx_data > 0) { 1711 evt = BWI_LED_EVENT_RX; 1712 } else if (rx_data == 0) { 1713 evt = BWI_LED_EVENT_POLL; 1714 } 1715 1716 if (evt != BWI_LED_EVENT_NONE) 1717 bwi_led_event(sc, evt); 1718 } 1719 1720 BWI_UNLOCK(sc); 1721 } 1722 1723 static void 1724 bwi_scan_start(struct ieee80211com *ic) 1725 { 1726 struct bwi_softc *sc = ic->ic_ifp->if_softc; 1727 1728 BWI_LOCK(sc); 1729 /* Enable MAC beacon promiscuity */ 1730 CSR_SETBITS_4(sc, BWI_MAC_STATUS, BWI_MAC_STATUS_PASS_BCN); 1731 BWI_UNLOCK(sc); 1732 } 1733 1734 static void 1735 bwi_set_channel(struct ieee80211com *ic) 1736 { 1737 struct bwi_softc *sc = ic->ic_ifp->if_softc; 1738 struct ieee80211_channel *c = ic->ic_curchan; 1739 struct bwi_mac *mac; 1740 1741 BWI_LOCK(sc); 1742 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 1743 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 1744 mac = (struct bwi_mac *)sc->sc_cur_regwin; 1745 bwi_rf_set_chan(mac, ieee80211_chan2ieee(ic, c), 0); 1746 1747 sc->sc_rates = ieee80211_get_ratetable(c); 1748 1749 /* 1750 * Setup radio tap channel freq and flags 1751 */ 1752 sc->sc_tx_th.wt_chan_freq = sc->sc_rx_th.wr_chan_freq = 1753 htole16(c->ic_freq); 1754 sc->sc_tx_th.wt_chan_flags = sc->sc_rx_th.wr_chan_flags = 1755 htole16(c->ic_flags & 0xffff); 1756 1757 BWI_UNLOCK(sc); 1758 } 1759 1760 static void 1761 bwi_scan_end(struct ieee80211com *ic) 1762 { 1763 struct bwi_softc *sc = ic->ic_ifp->if_softc; 1764 1765 BWI_LOCK(sc); 1766 CSR_CLRBITS_4(sc, BWI_MAC_STATUS, BWI_MAC_STATUS_PASS_BCN); 1767 BWI_UNLOCK(sc); 1768 } 1769 1770 static int 1771 bwi_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 1772 { 1773 struct bwi_vap *bvp = BWI_VAP(vap); 1774 struct ifnet *ifp = vap->iv_ic->ic_ifp; 1775 struct bwi_softc *sc = ifp->if_softc; 1776 struct bwi_mac *mac; 1777 struct ieee80211_node *ni; 1778 int error; 1779 1780 BWI_LOCK(sc); 1781 1782 callout_stop(&sc->sc_calib_ch); 1783 1784 if (nstate == IEEE80211_S_INIT) 1785 sc->sc_txpwrcb_type = BWI_TXPWR_INIT; 1786 1787 bwi_led_newstate(sc, nstate); 1788 1789 error = bvp->bv_newstate(vap, nstate, arg); 1790 if (error != 0) 1791 goto back; 1792 1793 if (vap->iv_opmode == IEEE80211_M_MONITOR) { 1794 /* Nothing to do */ 1795 } else if (nstate == IEEE80211_S_RUN) { 1796 ni = vap->iv_bss; 1797 1798 bwi_set_bssid(sc, vap->iv_bss->ni_bssid); 1799 1800 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 1801 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 1802 mac = (struct bwi_mac *)sc->sc_cur_regwin; 1803 1804 /* Initial TX power calibration */ 1805 bwi_mac_calibrate_txpower(mac, BWI_TXPWR_INIT); 1806 #ifdef notyet 1807 sc->sc_txpwrcb_type = BWI_TXPWR_FORCE; 1808 #else 1809 sc->sc_txpwrcb_type = BWI_TXPWR_CALIB; 1810 #endif 1811 if (vap->iv_opmode == IEEE80211_M_STA) { 1812 /* fake a join to init the tx rate */ 1813 bwi_newassoc(ni, 1); 1814 } 1815 1816 callout_reset(&sc->sc_calib_ch, hz, bwi_calibrate, sc); 1817 } else { 1818 bwi_set_bssid(sc, bwi_zero_addr); 1819 } 1820 back: 1821 BWI_UNLOCK(sc); 1822 1823 return error; 1824 } 1825 1826 /* ARGUSED */ 1827 static struct ieee80211_node * 1828 bwi_node_alloc(struct ieee80211vap *vap, const uint8_t mac[IEEE80211_ADDR_LEN]) 1829 { 1830 struct bwi_node *bn; 1831 1832 bn = malloc(sizeof(struct bwi_node), M_80211_NODE, M_NOWAIT | M_ZERO); 1833 return bn != NULL ? &bn->ni : NULL; 1834 } 1835 1836 static void 1837 bwi_newassoc(struct ieee80211_node *ni, int isnew) 1838 { 1839 struct ieee80211vap *vap = ni->ni_vap; 1840 1841 ieee80211_amrr_node_init(&BWI_VAP(vap)->bv_amrr, 1842 &BWI_NODE(ni)->amn, ni); 1843 } 1844 1845 static int 1846 bwi_media_change(struct ifnet *ifp) 1847 { 1848 int error = ieee80211_media_change(ifp); 1849 /* NB: only the fixed rate can change and that doesn't need a reset */ 1850 return (error == ENETRESET ? 0 : error); 1851 } 1852 1853 static int 1854 bwi_dma_alloc(struct bwi_softc *sc) 1855 { 1856 int error, i, has_txstats; 1857 bus_addr_t lowaddr = 0; 1858 bus_size_t tx_ring_sz, rx_ring_sz, desc_sz = 0; 1859 uint32_t txrx_ctrl_step = 0; 1860 1861 has_txstats = 0; 1862 for (i = 0; i < sc->sc_nmac; ++i) { 1863 if (sc->sc_mac[i].mac_flags & BWI_MAC_F_HAS_TXSTATS) { 1864 has_txstats = 1; 1865 break; 1866 } 1867 } 1868 1869 switch (sc->sc_bus_space) { 1870 case BWI_BUS_SPACE_30BIT: 1871 case BWI_BUS_SPACE_32BIT: 1872 if (sc->sc_bus_space == BWI_BUS_SPACE_30BIT) 1873 lowaddr = BWI_BUS_SPACE_MAXADDR; 1874 else 1875 lowaddr = BUS_SPACE_MAXADDR_32BIT; 1876 desc_sz = sizeof(struct bwi_desc32); 1877 txrx_ctrl_step = 0x20; 1878 1879 sc->sc_init_tx_ring = bwi_init_tx_ring32; 1880 sc->sc_free_tx_ring = bwi_free_tx_ring32; 1881 sc->sc_init_rx_ring = bwi_init_rx_ring32; 1882 sc->sc_free_rx_ring = bwi_free_rx_ring32; 1883 sc->sc_setup_rxdesc = bwi_setup_rx_desc32; 1884 sc->sc_setup_txdesc = bwi_setup_tx_desc32; 1885 sc->sc_rxeof = bwi_rxeof32; 1886 sc->sc_start_tx = bwi_start_tx32; 1887 if (has_txstats) { 1888 sc->sc_init_txstats = bwi_init_txstats32; 1889 sc->sc_free_txstats = bwi_free_txstats32; 1890 sc->sc_txeof_status = bwi_txeof_status32; 1891 } 1892 break; 1893 1894 case BWI_BUS_SPACE_64BIT: 1895 lowaddr = BUS_SPACE_MAXADDR; /* XXX */ 1896 desc_sz = sizeof(struct bwi_desc64); 1897 txrx_ctrl_step = 0x40; 1898 1899 sc->sc_init_tx_ring = bwi_init_tx_ring64; 1900 sc->sc_free_tx_ring = bwi_free_tx_ring64; 1901 sc->sc_init_rx_ring = bwi_init_rx_ring64; 1902 sc->sc_free_rx_ring = bwi_free_rx_ring64; 1903 sc->sc_setup_rxdesc = bwi_setup_rx_desc64; 1904 sc->sc_setup_txdesc = bwi_setup_tx_desc64; 1905 sc->sc_rxeof = bwi_rxeof64; 1906 sc->sc_start_tx = bwi_start_tx64; 1907 if (has_txstats) { 1908 sc->sc_init_txstats = bwi_init_txstats64; 1909 sc->sc_free_txstats = bwi_free_txstats64; 1910 sc->sc_txeof_status = bwi_txeof_status64; 1911 } 1912 break; 1913 } 1914 1915 KASSERT(lowaddr != 0, ("lowaddr zero")); 1916 KASSERT(desc_sz != 0, ("desc_sz zero")); 1917 KASSERT(txrx_ctrl_step != 0, ("txrx_ctrl_step zero")); 1918 1919 tx_ring_sz = roundup(desc_sz * BWI_TX_NDESC, BWI_RING_ALIGN); 1920 rx_ring_sz = roundup(desc_sz * BWI_RX_NDESC, BWI_RING_ALIGN); 1921 1922 /* 1923 * Create top level DMA tag 1924 */ 1925 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), /* parent */ 1926 BWI_ALIGN, 0, /* alignment, bounds */ 1927 lowaddr, /* lowaddr */ 1928 BUS_SPACE_MAXADDR, /* highaddr */ 1929 NULL, NULL, /* filter, filterarg */ 1930 MAXBSIZE, /* maxsize */ 1931 BUS_SPACE_UNRESTRICTED, /* nsegments */ 1932 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1933 BUS_DMA_ALLOCNOW, /* flags */ 1934 NULL, NULL, /* lockfunc, lockarg */ 1935 &sc->sc_parent_dtag); 1936 if (error) { 1937 device_printf(sc->sc_dev, "can't create parent DMA tag\n"); 1938 return error; 1939 } 1940 1941 #define TXRX_CTRL(idx) (BWI_TXRX_CTRL_BASE + (idx) * txrx_ctrl_step) 1942 1943 /* 1944 * Create TX ring DMA stuffs 1945 */ 1946 error = bus_dma_tag_create(sc->sc_parent_dtag, 1947 BWI_RING_ALIGN, 0, 1948 BUS_SPACE_MAXADDR, 1949 BUS_SPACE_MAXADDR, 1950 NULL, NULL, 1951 tx_ring_sz, 1952 1, 1953 BUS_SPACE_MAXSIZE_32BIT, 1954 BUS_DMA_ALLOCNOW, 1955 NULL, NULL, 1956 &sc->sc_txring_dtag); 1957 if (error) { 1958 device_printf(sc->sc_dev, "can't create TX ring DMA tag\n"); 1959 return error; 1960 } 1961 1962 for (i = 0; i < BWI_TX_NRING; ++i) { 1963 error = bwi_dma_ring_alloc(sc, sc->sc_txring_dtag, 1964 &sc->sc_tx_rdata[i], tx_ring_sz, 1965 TXRX_CTRL(i)); 1966 if (error) { 1967 device_printf(sc->sc_dev, "%dth TX ring " 1968 "DMA alloc failed\n", i); 1969 return error; 1970 } 1971 } 1972 1973 /* 1974 * Create RX ring DMA stuffs 1975 */ 1976 error = bus_dma_tag_create(sc->sc_parent_dtag, 1977 BWI_RING_ALIGN, 0, 1978 BUS_SPACE_MAXADDR, 1979 BUS_SPACE_MAXADDR, 1980 NULL, NULL, 1981 rx_ring_sz, 1982 1, 1983 BUS_SPACE_MAXSIZE_32BIT, 1984 BUS_DMA_ALLOCNOW, 1985 NULL, NULL, 1986 &sc->sc_rxring_dtag); 1987 if (error) { 1988 device_printf(sc->sc_dev, "can't create RX ring DMA tag\n"); 1989 return error; 1990 } 1991 1992 error = bwi_dma_ring_alloc(sc, sc->sc_rxring_dtag, &sc->sc_rx_rdata, 1993 rx_ring_sz, TXRX_CTRL(0)); 1994 if (error) { 1995 device_printf(sc->sc_dev, "RX ring DMA alloc failed\n"); 1996 return error; 1997 } 1998 1999 if (has_txstats) { 2000 error = bwi_dma_txstats_alloc(sc, TXRX_CTRL(3), desc_sz); 2001 if (error) { 2002 device_printf(sc->sc_dev, 2003 "TX stats DMA alloc failed\n"); 2004 return error; 2005 } 2006 } 2007 2008 #undef TXRX_CTRL 2009 2010 return bwi_dma_mbuf_create(sc); 2011 } 2012 2013 static void 2014 bwi_dma_free(struct bwi_softc *sc) 2015 { 2016 if (sc->sc_txring_dtag != NULL) { 2017 int i; 2018 2019 for (i = 0; i < BWI_TX_NRING; ++i) { 2020 struct bwi_ring_data *rd = &sc->sc_tx_rdata[i]; 2021 2022 if (rd->rdata_desc != NULL) { 2023 bus_dmamap_unload(sc->sc_txring_dtag, 2024 rd->rdata_dmap); 2025 bus_dmamem_free(sc->sc_txring_dtag, 2026 rd->rdata_desc, 2027 rd->rdata_dmap); 2028 } 2029 } 2030 bus_dma_tag_destroy(sc->sc_txring_dtag); 2031 } 2032 2033 if (sc->sc_rxring_dtag != NULL) { 2034 struct bwi_ring_data *rd = &sc->sc_rx_rdata; 2035 2036 if (rd->rdata_desc != NULL) { 2037 bus_dmamap_unload(sc->sc_rxring_dtag, rd->rdata_dmap); 2038 bus_dmamem_free(sc->sc_rxring_dtag, rd->rdata_desc, 2039 rd->rdata_dmap); 2040 } 2041 bus_dma_tag_destroy(sc->sc_rxring_dtag); 2042 } 2043 2044 bwi_dma_txstats_free(sc); 2045 bwi_dma_mbuf_destroy(sc, BWI_TX_NRING, 1); 2046 2047 if (sc->sc_parent_dtag != NULL) 2048 bus_dma_tag_destroy(sc->sc_parent_dtag); 2049 } 2050 2051 static int 2052 bwi_dma_ring_alloc(struct bwi_softc *sc, bus_dma_tag_t dtag, 2053 struct bwi_ring_data *rd, bus_size_t size, 2054 uint32_t txrx_ctrl) 2055 { 2056 int error; 2057 2058 error = bus_dmamem_alloc(dtag, &rd->rdata_desc, 2059 BUS_DMA_WAITOK | BUS_DMA_ZERO, 2060 &rd->rdata_dmap); 2061 if (error) { 2062 device_printf(sc->sc_dev, "can't allocate DMA mem\n"); 2063 return error; 2064 } 2065 2066 error = bus_dmamap_load(dtag, rd->rdata_dmap, rd->rdata_desc, size, 2067 bwi_dma_ring_addr, &rd->rdata_paddr, 2068 BUS_DMA_NOWAIT); 2069 if (error) { 2070 device_printf(sc->sc_dev, "can't load DMA mem\n"); 2071 bus_dmamem_free(dtag, rd->rdata_desc, rd->rdata_dmap); 2072 rd->rdata_desc = NULL; 2073 return error; 2074 } 2075 2076 rd->rdata_txrx_ctrl = txrx_ctrl; 2077 return 0; 2078 } 2079 2080 static int 2081 bwi_dma_txstats_alloc(struct bwi_softc *sc, uint32_t ctrl_base, 2082 bus_size_t desc_sz) 2083 { 2084 struct bwi_txstats_data *st; 2085 bus_size_t dma_size; 2086 int error; 2087 2088 st = malloc(sizeof(*st), M_DEVBUF, M_NOWAIT | M_ZERO); 2089 if (st == NULL) { 2090 device_printf(sc->sc_dev, "can't allocate txstats data\n"); 2091 return ENOMEM; 2092 } 2093 sc->sc_txstats = st; 2094 2095 /* 2096 * Create TX stats descriptor DMA stuffs 2097 */ 2098 dma_size = roundup(desc_sz * BWI_TXSTATS_NDESC, BWI_RING_ALIGN); 2099 2100 error = bus_dma_tag_create(sc->sc_parent_dtag, 2101 BWI_RING_ALIGN, 2102 0, 2103 BUS_SPACE_MAXADDR, 2104 BUS_SPACE_MAXADDR, 2105 NULL, NULL, 2106 dma_size, 2107 1, 2108 BUS_SPACE_MAXSIZE_32BIT, 2109 BUS_DMA_ALLOCNOW, 2110 NULL, NULL, 2111 &st->stats_ring_dtag); 2112 if (error) { 2113 device_printf(sc->sc_dev, "can't create txstats ring " 2114 "DMA tag\n"); 2115 return error; 2116 } 2117 2118 error = bus_dmamem_alloc(st->stats_ring_dtag, &st->stats_ring, 2119 BUS_DMA_WAITOK | BUS_DMA_ZERO, 2120 &st->stats_ring_dmap); 2121 if (error) { 2122 device_printf(sc->sc_dev, "can't allocate txstats ring " 2123 "DMA mem\n"); 2124 bus_dma_tag_destroy(st->stats_ring_dtag); 2125 st->stats_ring_dtag = NULL; 2126 return error; 2127 } 2128 2129 error = bus_dmamap_load(st->stats_ring_dtag, st->stats_ring_dmap, 2130 st->stats_ring, dma_size, 2131 bwi_dma_ring_addr, &st->stats_ring_paddr, 2132 BUS_DMA_NOWAIT); 2133 if (error) { 2134 device_printf(sc->sc_dev, "can't load txstats ring DMA mem\n"); 2135 bus_dmamem_free(st->stats_ring_dtag, st->stats_ring, 2136 st->stats_ring_dmap); 2137 bus_dma_tag_destroy(st->stats_ring_dtag); 2138 st->stats_ring_dtag = NULL; 2139 return error; 2140 } 2141 2142 /* 2143 * Create TX stats DMA stuffs 2144 */ 2145 dma_size = roundup(sizeof(struct bwi_txstats) * BWI_TXSTATS_NDESC, 2146 BWI_ALIGN); 2147 2148 error = bus_dma_tag_create(sc->sc_parent_dtag, 2149 BWI_ALIGN, 2150 0, 2151 BUS_SPACE_MAXADDR, 2152 BUS_SPACE_MAXADDR, 2153 NULL, NULL, 2154 dma_size, 2155 1, 2156 BUS_SPACE_MAXSIZE_32BIT, 2157 BUS_DMA_ALLOCNOW, 2158 NULL, NULL, 2159 &st->stats_dtag); 2160 if (error) { 2161 device_printf(sc->sc_dev, "can't create txstats DMA tag\n"); 2162 return error; 2163 } 2164 2165 error = bus_dmamem_alloc(st->stats_dtag, (void **)&st->stats, 2166 BUS_DMA_WAITOK | BUS_DMA_ZERO, 2167 &st->stats_dmap); 2168 if (error) { 2169 device_printf(sc->sc_dev, "can't allocate txstats DMA mem\n"); 2170 bus_dma_tag_destroy(st->stats_dtag); 2171 st->stats_dtag = NULL; 2172 return error; 2173 } 2174 2175 error = bus_dmamap_load(st->stats_dtag, st->stats_dmap, st->stats, 2176 dma_size, bwi_dma_ring_addr, &st->stats_paddr, 2177 BUS_DMA_NOWAIT); 2178 if (error) { 2179 device_printf(sc->sc_dev, "can't load txstats DMA mem\n"); 2180 bus_dmamem_free(st->stats_dtag, st->stats, st->stats_dmap); 2181 bus_dma_tag_destroy(st->stats_dtag); 2182 st->stats_dtag = NULL; 2183 return error; 2184 } 2185 2186 st->stats_ctrl_base = ctrl_base; 2187 return 0; 2188 } 2189 2190 static void 2191 bwi_dma_txstats_free(struct bwi_softc *sc) 2192 { 2193 struct bwi_txstats_data *st; 2194 2195 if (sc->sc_txstats == NULL) 2196 return; 2197 st = sc->sc_txstats; 2198 2199 if (st->stats_ring_dtag != NULL) { 2200 bus_dmamap_unload(st->stats_ring_dtag, st->stats_ring_dmap); 2201 bus_dmamem_free(st->stats_ring_dtag, st->stats_ring, 2202 st->stats_ring_dmap); 2203 bus_dma_tag_destroy(st->stats_ring_dtag); 2204 } 2205 2206 if (st->stats_dtag != NULL) { 2207 bus_dmamap_unload(st->stats_dtag, st->stats_dmap); 2208 bus_dmamem_free(st->stats_dtag, st->stats, st->stats_dmap); 2209 bus_dma_tag_destroy(st->stats_dtag); 2210 } 2211 2212 free(st, M_DEVBUF); 2213 } 2214 2215 static void 2216 bwi_dma_ring_addr(void *arg, bus_dma_segment_t *seg, int nseg, int error) 2217 { 2218 KASSERT(nseg == 1, ("too many segments\n")); 2219 *((bus_addr_t *)arg) = seg->ds_addr; 2220 } 2221 2222 static int 2223 bwi_dma_mbuf_create(struct bwi_softc *sc) 2224 { 2225 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata; 2226 int i, j, k, ntx, error; 2227 2228 /* 2229 * Create TX/RX mbuf DMA tag 2230 */ 2231 error = bus_dma_tag_create(sc->sc_parent_dtag, 2232 1, 2233 0, 2234 BUS_SPACE_MAXADDR, 2235 BUS_SPACE_MAXADDR, 2236 NULL, NULL, 2237 MCLBYTES, 2238 1, 2239 BUS_SPACE_MAXSIZE_32BIT, 2240 BUS_DMA_ALLOCNOW, 2241 NULL, NULL, 2242 &sc->sc_buf_dtag); 2243 if (error) { 2244 device_printf(sc->sc_dev, "can't create mbuf DMA tag\n"); 2245 return error; 2246 } 2247 2248 ntx = 0; 2249 2250 /* 2251 * Create TX mbuf DMA map 2252 */ 2253 for (i = 0; i < BWI_TX_NRING; ++i) { 2254 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[i]; 2255 2256 for (j = 0; j < BWI_TX_NDESC; ++j) { 2257 error = bus_dmamap_create(sc->sc_buf_dtag, 0, 2258 &tbd->tbd_buf[j].tb_dmap); 2259 if (error) { 2260 device_printf(sc->sc_dev, "can't create " 2261 "%dth tbd, %dth DMA map\n", i, j); 2262 2263 ntx = i; 2264 for (k = 0; k < j; ++k) { 2265 bus_dmamap_destroy(sc->sc_buf_dtag, 2266 tbd->tbd_buf[k].tb_dmap); 2267 } 2268 goto fail; 2269 } 2270 } 2271 } 2272 ntx = BWI_TX_NRING; 2273 2274 /* 2275 * Create RX mbuf DMA map and a spare DMA map 2276 */ 2277 error = bus_dmamap_create(sc->sc_buf_dtag, 0, 2278 &rbd->rbd_tmp_dmap); 2279 if (error) { 2280 device_printf(sc->sc_dev, 2281 "can't create spare RX buf DMA map\n"); 2282 goto fail; 2283 } 2284 2285 for (j = 0; j < BWI_RX_NDESC; ++j) { 2286 error = bus_dmamap_create(sc->sc_buf_dtag, 0, 2287 &rbd->rbd_buf[j].rb_dmap); 2288 if (error) { 2289 device_printf(sc->sc_dev, "can't create %dth " 2290 "RX buf DMA map\n", j); 2291 2292 for (k = 0; k < j; ++k) { 2293 bus_dmamap_destroy(sc->sc_buf_dtag, 2294 rbd->rbd_buf[j].rb_dmap); 2295 } 2296 bus_dmamap_destroy(sc->sc_buf_dtag, 2297 rbd->rbd_tmp_dmap); 2298 goto fail; 2299 } 2300 } 2301 2302 return 0; 2303 fail: 2304 bwi_dma_mbuf_destroy(sc, ntx, 0); 2305 return error; 2306 } 2307 2308 static void 2309 bwi_dma_mbuf_destroy(struct bwi_softc *sc, int ntx, int nrx) 2310 { 2311 int i, j; 2312 2313 if (sc->sc_buf_dtag == NULL) 2314 return; 2315 2316 for (i = 0; i < ntx; ++i) { 2317 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[i]; 2318 2319 for (j = 0; j < BWI_TX_NDESC; ++j) { 2320 struct bwi_txbuf *tb = &tbd->tbd_buf[j]; 2321 2322 if (tb->tb_mbuf != NULL) { 2323 bus_dmamap_unload(sc->sc_buf_dtag, 2324 tb->tb_dmap); 2325 m_freem(tb->tb_mbuf); 2326 } 2327 if (tb->tb_ni != NULL) 2328 ieee80211_free_node(tb->tb_ni); 2329 bus_dmamap_destroy(sc->sc_buf_dtag, tb->tb_dmap); 2330 } 2331 } 2332 2333 if (nrx) { 2334 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata; 2335 2336 bus_dmamap_destroy(sc->sc_buf_dtag, rbd->rbd_tmp_dmap); 2337 for (j = 0; j < BWI_RX_NDESC; ++j) { 2338 struct bwi_rxbuf *rb = &rbd->rbd_buf[j]; 2339 2340 if (rb->rb_mbuf != NULL) { 2341 bus_dmamap_unload(sc->sc_buf_dtag, 2342 rb->rb_dmap); 2343 m_freem(rb->rb_mbuf); 2344 } 2345 bus_dmamap_destroy(sc->sc_buf_dtag, rb->rb_dmap); 2346 } 2347 } 2348 2349 bus_dma_tag_destroy(sc->sc_buf_dtag); 2350 sc->sc_buf_dtag = NULL; 2351 } 2352 2353 static void 2354 bwi_enable_intrs(struct bwi_softc *sc, uint32_t enable_intrs) 2355 { 2356 CSR_SETBITS_4(sc, BWI_MAC_INTR_MASK, enable_intrs); 2357 } 2358 2359 static void 2360 bwi_disable_intrs(struct bwi_softc *sc, uint32_t disable_intrs) 2361 { 2362 CSR_CLRBITS_4(sc, BWI_MAC_INTR_MASK, disable_intrs); 2363 } 2364 2365 static int 2366 bwi_init_tx_ring32(struct bwi_softc *sc, int ring_idx) 2367 { 2368 struct bwi_ring_data *rd; 2369 struct bwi_txbuf_data *tbd; 2370 uint32_t val, addr_hi, addr_lo; 2371 2372 KASSERT(ring_idx < BWI_TX_NRING, ("ring_idx %d", ring_idx)); 2373 rd = &sc->sc_tx_rdata[ring_idx]; 2374 tbd = &sc->sc_tx_bdata[ring_idx]; 2375 2376 tbd->tbd_idx = 0; 2377 tbd->tbd_used = 0; 2378 2379 bzero(rd->rdata_desc, sizeof(struct bwi_desc32) * BWI_TX_NDESC); 2380 bus_dmamap_sync(sc->sc_txring_dtag, rd->rdata_dmap, 2381 BUS_DMASYNC_PREWRITE); 2382 2383 addr_lo = __SHIFTOUT(rd->rdata_paddr, BWI_TXRX32_RINGINFO_ADDR_MASK); 2384 addr_hi = __SHIFTOUT(rd->rdata_paddr, BWI_TXRX32_RINGINFO_FUNC_MASK); 2385 2386 val = __SHIFTIN(addr_lo, BWI_TXRX32_RINGINFO_ADDR_MASK) | 2387 __SHIFTIN(BWI_TXRX32_RINGINFO_FUNC_TXRX, 2388 BWI_TXRX32_RINGINFO_FUNC_MASK); 2389 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_RINGINFO, val); 2390 2391 val = __SHIFTIN(addr_hi, BWI_TXRX32_CTRL_ADDRHI_MASK) | 2392 BWI_TXRX32_CTRL_ENABLE; 2393 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_CTRL, val); 2394 2395 return 0; 2396 } 2397 2398 static void 2399 bwi_init_rxdesc_ring32(struct bwi_softc *sc, uint32_t ctrl_base, 2400 bus_addr_t paddr, int hdr_size, int ndesc) 2401 { 2402 uint32_t val, addr_hi, addr_lo; 2403 2404 addr_lo = __SHIFTOUT(paddr, BWI_TXRX32_RINGINFO_ADDR_MASK); 2405 addr_hi = __SHIFTOUT(paddr, BWI_TXRX32_RINGINFO_FUNC_MASK); 2406 2407 val = __SHIFTIN(addr_lo, BWI_TXRX32_RINGINFO_ADDR_MASK) | 2408 __SHIFTIN(BWI_TXRX32_RINGINFO_FUNC_TXRX, 2409 BWI_TXRX32_RINGINFO_FUNC_MASK); 2410 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_RINGINFO, val); 2411 2412 val = __SHIFTIN(hdr_size, BWI_RX32_CTRL_HDRSZ_MASK) | 2413 __SHIFTIN(addr_hi, BWI_TXRX32_CTRL_ADDRHI_MASK) | 2414 BWI_TXRX32_CTRL_ENABLE; 2415 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_CTRL, val); 2416 2417 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_INDEX, 2418 (ndesc - 1) * sizeof(struct bwi_desc32)); 2419 } 2420 2421 static int 2422 bwi_init_rx_ring32(struct bwi_softc *sc) 2423 { 2424 struct bwi_ring_data *rd = &sc->sc_rx_rdata; 2425 int i, error; 2426 2427 sc->sc_rx_bdata.rbd_idx = 0; 2428 2429 for (i = 0; i < BWI_RX_NDESC; ++i) { 2430 error = bwi_newbuf(sc, i, 1); 2431 if (error) { 2432 device_printf(sc->sc_dev, 2433 "can't allocate %dth RX buffer\n", i); 2434 return error; 2435 } 2436 } 2437 bus_dmamap_sync(sc->sc_rxring_dtag, rd->rdata_dmap, 2438 BUS_DMASYNC_PREWRITE); 2439 2440 bwi_init_rxdesc_ring32(sc, rd->rdata_txrx_ctrl, rd->rdata_paddr, 2441 sizeof(struct bwi_rxbuf_hdr), BWI_RX_NDESC); 2442 return 0; 2443 } 2444 2445 static int 2446 bwi_init_txstats32(struct bwi_softc *sc) 2447 { 2448 struct bwi_txstats_data *st = sc->sc_txstats; 2449 bus_addr_t stats_paddr; 2450 int i; 2451 2452 bzero(st->stats, BWI_TXSTATS_NDESC * sizeof(struct bwi_txstats)); 2453 bus_dmamap_sync(st->stats_dtag, st->stats_dmap, BUS_DMASYNC_PREWRITE); 2454 2455 st->stats_idx = 0; 2456 2457 stats_paddr = st->stats_paddr; 2458 for (i = 0; i < BWI_TXSTATS_NDESC; ++i) { 2459 bwi_setup_desc32(sc, st->stats_ring, BWI_TXSTATS_NDESC, i, 2460 stats_paddr, sizeof(struct bwi_txstats), 0); 2461 stats_paddr += sizeof(struct bwi_txstats); 2462 } 2463 bus_dmamap_sync(st->stats_ring_dtag, st->stats_ring_dmap, 2464 BUS_DMASYNC_PREWRITE); 2465 2466 bwi_init_rxdesc_ring32(sc, st->stats_ctrl_base, 2467 st->stats_ring_paddr, 0, BWI_TXSTATS_NDESC); 2468 return 0; 2469 } 2470 2471 static void 2472 bwi_setup_rx_desc32(struct bwi_softc *sc, int buf_idx, bus_addr_t paddr, 2473 int buf_len) 2474 { 2475 struct bwi_ring_data *rd = &sc->sc_rx_rdata; 2476 2477 KASSERT(buf_idx < BWI_RX_NDESC, ("buf_idx %d", buf_idx)); 2478 bwi_setup_desc32(sc, rd->rdata_desc, BWI_RX_NDESC, buf_idx, 2479 paddr, buf_len, 0); 2480 } 2481 2482 static void 2483 bwi_setup_tx_desc32(struct bwi_softc *sc, struct bwi_ring_data *rd, 2484 int buf_idx, bus_addr_t paddr, int buf_len) 2485 { 2486 KASSERT(buf_idx < BWI_TX_NDESC, ("buf_idx %d", buf_idx)); 2487 bwi_setup_desc32(sc, rd->rdata_desc, BWI_TX_NDESC, buf_idx, 2488 paddr, buf_len, 1); 2489 } 2490 2491 static int 2492 bwi_init_tx_ring64(struct bwi_softc *sc, int ring_idx) 2493 { 2494 /* TODO:64 */ 2495 return EOPNOTSUPP; 2496 } 2497 2498 static int 2499 bwi_init_rx_ring64(struct bwi_softc *sc) 2500 { 2501 /* TODO:64 */ 2502 return EOPNOTSUPP; 2503 } 2504 2505 static int 2506 bwi_init_txstats64(struct bwi_softc *sc) 2507 { 2508 /* TODO:64 */ 2509 return EOPNOTSUPP; 2510 } 2511 2512 static void 2513 bwi_setup_rx_desc64(struct bwi_softc *sc, int buf_idx, bus_addr_t paddr, 2514 int buf_len) 2515 { 2516 /* TODO:64 */ 2517 } 2518 2519 static void 2520 bwi_setup_tx_desc64(struct bwi_softc *sc, struct bwi_ring_data *rd, 2521 int buf_idx, bus_addr_t paddr, int buf_len) 2522 { 2523 /* TODO:64 */ 2524 } 2525 2526 static void 2527 bwi_dma_buf_addr(void *arg, bus_dma_segment_t *seg, int nseg, 2528 bus_size_t mapsz __unused, int error) 2529 { 2530 if (!error) { 2531 KASSERT(nseg == 1, ("too many segments(%d)\n", nseg)); 2532 *((bus_addr_t *)arg) = seg->ds_addr; 2533 } 2534 } 2535 2536 static int 2537 bwi_newbuf(struct bwi_softc *sc, int buf_idx, int init) 2538 { 2539 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata; 2540 struct bwi_rxbuf *rxbuf = &rbd->rbd_buf[buf_idx]; 2541 struct bwi_rxbuf_hdr *hdr; 2542 bus_dmamap_t map; 2543 bus_addr_t paddr; 2544 struct mbuf *m; 2545 int error; 2546 2547 KASSERT(buf_idx < BWI_RX_NDESC, ("buf_idx %d", buf_idx)); 2548 2549 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2550 if (m == NULL) { 2551 error = ENOBUFS; 2552 2553 /* 2554 * If the NIC is up and running, we need to: 2555 * - Clear RX buffer's header. 2556 * - Restore RX descriptor settings. 2557 */ 2558 if (init) 2559 return error; 2560 else 2561 goto back; 2562 } 2563 m->m_len = m->m_pkthdr.len = MCLBYTES; 2564 2565 /* 2566 * Try to load RX buf into temporary DMA map 2567 */ 2568 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, rbd->rbd_tmp_dmap, m, 2569 bwi_dma_buf_addr, &paddr, BUS_DMA_NOWAIT); 2570 if (error) { 2571 m_freem(m); 2572 2573 /* 2574 * See the comment above 2575 */ 2576 if (init) 2577 return error; 2578 else 2579 goto back; 2580 } 2581 2582 if (!init) 2583 bus_dmamap_unload(sc->sc_buf_dtag, rxbuf->rb_dmap); 2584 rxbuf->rb_mbuf = m; 2585 rxbuf->rb_paddr = paddr; 2586 2587 /* 2588 * Swap RX buf's DMA map with the loaded temporary one 2589 */ 2590 map = rxbuf->rb_dmap; 2591 rxbuf->rb_dmap = rbd->rbd_tmp_dmap; 2592 rbd->rbd_tmp_dmap = map; 2593 2594 back: 2595 /* 2596 * Clear RX buf header 2597 */ 2598 hdr = mtod(rxbuf->rb_mbuf, struct bwi_rxbuf_hdr *); 2599 bzero(hdr, sizeof(*hdr)); 2600 bus_dmamap_sync(sc->sc_buf_dtag, rxbuf->rb_dmap, BUS_DMASYNC_PREWRITE); 2601 2602 /* 2603 * Setup RX buf descriptor 2604 */ 2605 sc->sc_setup_rxdesc(sc, buf_idx, rxbuf->rb_paddr, 2606 rxbuf->rb_mbuf->m_len - sizeof(*hdr)); 2607 return error; 2608 } 2609 2610 static void 2611 bwi_set_addr_filter(struct bwi_softc *sc, uint16_t addr_ofs, 2612 const uint8_t *addr) 2613 { 2614 int i; 2615 2616 CSR_WRITE_2(sc, BWI_ADDR_FILTER_CTRL, 2617 BWI_ADDR_FILTER_CTRL_SET | addr_ofs); 2618 2619 for (i = 0; i < (IEEE80211_ADDR_LEN / 2); ++i) { 2620 uint16_t addr_val; 2621 2622 addr_val = (uint16_t)addr[i * 2] | 2623 (((uint16_t)addr[(i * 2) + 1]) << 8); 2624 CSR_WRITE_2(sc, BWI_ADDR_FILTER_DATA, addr_val); 2625 } 2626 } 2627 2628 static int 2629 bwi_rxeof(struct bwi_softc *sc, int end_idx) 2630 { 2631 struct bwi_ring_data *rd = &sc->sc_rx_rdata; 2632 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata; 2633 struct ifnet *ifp = sc->sc_ifp; 2634 struct ieee80211com *ic = ifp->if_l2com; 2635 int idx, rx_data = 0; 2636 2637 idx = rbd->rbd_idx; 2638 while (idx != end_idx) { 2639 struct bwi_rxbuf *rb = &rbd->rbd_buf[idx]; 2640 struct bwi_rxbuf_hdr *hdr; 2641 struct ieee80211_frame_min *wh; 2642 struct ieee80211_node *ni; 2643 struct mbuf *m; 2644 const void *plcp; 2645 uint16_t flags2; 2646 int buflen, wh_ofs, hdr_extra, rssi, noise, type, rate; 2647 2648 m = rb->rb_mbuf; 2649 bus_dmamap_sync(sc->sc_buf_dtag, rb->rb_dmap, 2650 BUS_DMASYNC_POSTREAD); 2651 2652 if (bwi_newbuf(sc, idx, 0)) { 2653 ifp->if_ierrors++; 2654 goto next; 2655 } 2656 2657 hdr = mtod(m, struct bwi_rxbuf_hdr *); 2658 flags2 = le16toh(hdr->rxh_flags2); 2659 2660 hdr_extra = 0; 2661 if (flags2 & BWI_RXH_F2_TYPE2FRAME) 2662 hdr_extra = 2; 2663 wh_ofs = hdr_extra + 6; /* XXX magic number */ 2664 2665 buflen = le16toh(hdr->rxh_buflen); 2666 if (buflen < BWI_FRAME_MIN_LEN(wh_ofs)) { 2667 if_printf(ifp, "%s: zero length data, hdr_extra %d\n", 2668 __func__, hdr_extra); 2669 ifp->if_ierrors++; 2670 m_freem(m); 2671 goto next; 2672 } 2673 2674 plcp = ((const uint8_t *)(hdr + 1) + hdr_extra); 2675 rssi = bwi_calc_rssi(sc, hdr); 2676 noise = bwi_calc_noise(sc); 2677 2678 m->m_pkthdr.rcvif = ifp; 2679 m->m_len = m->m_pkthdr.len = buflen + sizeof(*hdr); 2680 m_adj(m, sizeof(*hdr) + wh_ofs); 2681 2682 if (htole16(hdr->rxh_flags1) & BWI_RXH_F1_OFDM) 2683 rate = bwi_ofdm_plcp2rate(plcp); 2684 else 2685 rate = bwi_ds_plcp2rate(plcp); 2686 2687 /* RX radio tap */ 2688 if (ieee80211_radiotap_active(ic)) 2689 bwi_rx_radiotap(sc, m, hdr, plcp, rate, rssi, noise); 2690 2691 m_adj(m, -IEEE80211_CRC_LEN); 2692 2693 BWI_UNLOCK(sc); 2694 2695 wh = mtod(m, struct ieee80211_frame_min *); 2696 ni = ieee80211_find_rxnode(ic, wh); 2697 if (ni != NULL) { 2698 type = ieee80211_input(ni, m, rssi - noise, noise); 2699 ieee80211_free_node(ni); 2700 } else 2701 type = ieee80211_input_all(ic, m, rssi - noise, noise); 2702 if (type == IEEE80211_FC0_TYPE_DATA) { 2703 rx_data = 1; 2704 sc->sc_rx_rate = rate; 2705 } 2706 2707 BWI_LOCK(sc); 2708 next: 2709 idx = (idx + 1) % BWI_RX_NDESC; 2710 2711 if (sc->sc_flags & BWI_F_STOP) { 2712 /* 2713 * Take the fast lane, don't do 2714 * any damage to softc 2715 */ 2716 return -1; 2717 } 2718 } 2719 2720 rbd->rbd_idx = idx; 2721 bus_dmamap_sync(sc->sc_rxring_dtag, rd->rdata_dmap, 2722 BUS_DMASYNC_PREWRITE); 2723 2724 return rx_data; 2725 } 2726 2727 static int 2728 bwi_rxeof32(struct bwi_softc *sc) 2729 { 2730 uint32_t val, rx_ctrl; 2731 int end_idx, rx_data; 2732 2733 rx_ctrl = sc->sc_rx_rdata.rdata_txrx_ctrl; 2734 2735 val = CSR_READ_4(sc, rx_ctrl + BWI_RX32_STATUS); 2736 end_idx = __SHIFTOUT(val, BWI_RX32_STATUS_INDEX_MASK) / 2737 sizeof(struct bwi_desc32); 2738 2739 rx_data = bwi_rxeof(sc, end_idx); 2740 if (rx_data >= 0) { 2741 CSR_WRITE_4(sc, rx_ctrl + BWI_RX32_INDEX, 2742 end_idx * sizeof(struct bwi_desc32)); 2743 } 2744 return rx_data; 2745 } 2746 2747 static int 2748 bwi_rxeof64(struct bwi_softc *sc) 2749 { 2750 /* TODO:64 */ 2751 return 0; 2752 } 2753 2754 static void 2755 bwi_reset_rx_ring32(struct bwi_softc *sc, uint32_t rx_ctrl) 2756 { 2757 int i; 2758 2759 CSR_WRITE_4(sc, rx_ctrl + BWI_RX32_CTRL, 0); 2760 2761 #define NRETRY 10 2762 2763 for (i = 0; i < NRETRY; ++i) { 2764 uint32_t status; 2765 2766 status = CSR_READ_4(sc, rx_ctrl + BWI_RX32_STATUS); 2767 if (__SHIFTOUT(status, BWI_RX32_STATUS_STATE_MASK) == 2768 BWI_RX32_STATUS_STATE_DISABLED) 2769 break; 2770 2771 DELAY(1000); 2772 } 2773 if (i == NRETRY) 2774 device_printf(sc->sc_dev, "reset rx ring timedout\n"); 2775 2776 #undef NRETRY 2777 2778 CSR_WRITE_4(sc, rx_ctrl + BWI_RX32_RINGINFO, 0); 2779 } 2780 2781 static void 2782 bwi_free_txstats32(struct bwi_softc *sc) 2783 { 2784 bwi_reset_rx_ring32(sc, sc->sc_txstats->stats_ctrl_base); 2785 } 2786 2787 static void 2788 bwi_free_rx_ring32(struct bwi_softc *sc) 2789 { 2790 struct bwi_ring_data *rd = &sc->sc_rx_rdata; 2791 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata; 2792 int i; 2793 2794 bwi_reset_rx_ring32(sc, rd->rdata_txrx_ctrl); 2795 2796 for (i = 0; i < BWI_RX_NDESC; ++i) { 2797 struct bwi_rxbuf *rb = &rbd->rbd_buf[i]; 2798 2799 if (rb->rb_mbuf != NULL) { 2800 bus_dmamap_unload(sc->sc_buf_dtag, rb->rb_dmap); 2801 m_freem(rb->rb_mbuf); 2802 rb->rb_mbuf = NULL; 2803 } 2804 } 2805 } 2806 2807 static void 2808 bwi_free_tx_ring32(struct bwi_softc *sc, int ring_idx) 2809 { 2810 struct bwi_ring_data *rd; 2811 struct bwi_txbuf_data *tbd; 2812 struct ifnet *ifp = sc->sc_ifp; 2813 uint32_t state, val; 2814 int i; 2815 2816 KASSERT(ring_idx < BWI_TX_NRING, ("ring_idx %d", ring_idx)); 2817 rd = &sc->sc_tx_rdata[ring_idx]; 2818 tbd = &sc->sc_tx_bdata[ring_idx]; 2819 2820 #define NRETRY 10 2821 2822 for (i = 0; i < NRETRY; ++i) { 2823 val = CSR_READ_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_STATUS); 2824 state = __SHIFTOUT(val, BWI_TX32_STATUS_STATE_MASK); 2825 if (state == BWI_TX32_STATUS_STATE_DISABLED || 2826 state == BWI_TX32_STATUS_STATE_IDLE || 2827 state == BWI_TX32_STATUS_STATE_STOPPED) 2828 break; 2829 2830 DELAY(1000); 2831 } 2832 if (i == NRETRY) { 2833 if_printf(ifp, "%s: wait for TX ring(%d) stable timed out\n", 2834 __func__, ring_idx); 2835 } 2836 2837 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_CTRL, 0); 2838 for (i = 0; i < NRETRY; ++i) { 2839 val = CSR_READ_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_STATUS); 2840 state = __SHIFTOUT(val, BWI_TX32_STATUS_STATE_MASK); 2841 if (state == BWI_TX32_STATUS_STATE_DISABLED) 2842 break; 2843 2844 DELAY(1000); 2845 } 2846 if (i == NRETRY) 2847 if_printf(ifp, "%s: reset TX ring (%d) timed out\n", 2848 __func__, ring_idx); 2849 2850 #undef NRETRY 2851 2852 DELAY(1000); 2853 2854 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_RINGINFO, 0); 2855 2856 for (i = 0; i < BWI_TX_NDESC; ++i) { 2857 struct bwi_txbuf *tb = &tbd->tbd_buf[i]; 2858 2859 if (tb->tb_mbuf != NULL) { 2860 bus_dmamap_unload(sc->sc_buf_dtag, tb->tb_dmap); 2861 m_freem(tb->tb_mbuf); 2862 tb->tb_mbuf = NULL; 2863 } 2864 if (tb->tb_ni != NULL) { 2865 ieee80211_free_node(tb->tb_ni); 2866 tb->tb_ni = NULL; 2867 } 2868 } 2869 } 2870 2871 static void 2872 bwi_free_txstats64(struct bwi_softc *sc) 2873 { 2874 /* TODO:64 */ 2875 } 2876 2877 static void 2878 bwi_free_rx_ring64(struct bwi_softc *sc) 2879 { 2880 /* TODO:64 */ 2881 } 2882 2883 static void 2884 bwi_free_tx_ring64(struct bwi_softc *sc, int ring_idx) 2885 { 2886 /* TODO:64 */ 2887 } 2888 2889 /* XXX does not belong here */ 2890 #define IEEE80211_OFDM_PLCP_RATE_MASK __BITS(3, 0) 2891 #define IEEE80211_OFDM_PLCP_LEN_MASK __BITS(16, 5) 2892 2893 static __inline void 2894 bwi_ofdm_plcp_header(uint32_t *plcp0, int pkt_len, uint8_t rate) 2895 { 2896 uint32_t plcp; 2897 2898 plcp = __SHIFTIN(ieee80211_rate2plcp(rate, IEEE80211_T_OFDM), 2899 IEEE80211_OFDM_PLCP_RATE_MASK) | 2900 __SHIFTIN(pkt_len, IEEE80211_OFDM_PLCP_LEN_MASK); 2901 *plcp0 = htole32(plcp); 2902 } 2903 2904 static __inline void 2905 bwi_ds_plcp_header(struct ieee80211_ds_plcp_hdr *plcp, int pkt_len, 2906 uint8_t rate) 2907 { 2908 int len, service, pkt_bitlen; 2909 2910 pkt_bitlen = pkt_len * NBBY; 2911 len = howmany(pkt_bitlen * 2, rate); 2912 2913 service = IEEE80211_PLCP_SERVICE_LOCKED; 2914 if (rate == (11 * 2)) { 2915 int pkt_bitlen1; 2916 2917 /* 2918 * PLCP service field needs to be adjusted, 2919 * if TX rate is 11Mbytes/s 2920 */ 2921 pkt_bitlen1 = len * 11; 2922 if (pkt_bitlen1 - pkt_bitlen >= NBBY) 2923 service |= IEEE80211_PLCP_SERVICE_LENEXT7; 2924 } 2925 2926 plcp->i_signal = ieee80211_rate2plcp(rate, IEEE80211_T_CCK); 2927 plcp->i_service = service; 2928 plcp->i_length = htole16(len); 2929 /* NOTE: do NOT touch i_crc */ 2930 } 2931 2932 static __inline void 2933 bwi_plcp_header(const struct ieee80211_rate_table *rt, 2934 void *plcp, int pkt_len, uint8_t rate) 2935 { 2936 enum ieee80211_phytype modtype; 2937 2938 /* 2939 * Assume caller has zeroed 'plcp' 2940 */ 2941 modtype = ieee80211_rate2phytype(rt, rate); 2942 if (modtype == IEEE80211_T_OFDM) 2943 bwi_ofdm_plcp_header(plcp, pkt_len, rate); 2944 else if (modtype == IEEE80211_T_DS) 2945 bwi_ds_plcp_header(plcp, pkt_len, rate); 2946 else 2947 panic("unsupport modulation type %u\n", modtype); 2948 } 2949 2950 static int 2951 bwi_encap(struct bwi_softc *sc, int idx, struct mbuf *m, 2952 struct ieee80211_node *ni) 2953 { 2954 struct ieee80211vap *vap = ni->ni_vap; 2955 struct ifnet *ifp = sc->sc_ifp; 2956 struct ieee80211com *ic = ifp->if_l2com; 2957 struct bwi_ring_data *rd = &sc->sc_tx_rdata[BWI_TX_DATA_RING]; 2958 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING]; 2959 struct bwi_txbuf *tb = &tbd->tbd_buf[idx]; 2960 struct bwi_mac *mac; 2961 struct bwi_txbuf_hdr *hdr; 2962 struct ieee80211_frame *wh; 2963 const struct ieee80211_txparam *tp; 2964 uint8_t rate, rate_fb; 2965 uint32_t mac_ctrl; 2966 uint16_t phy_ctrl; 2967 bus_addr_t paddr; 2968 int type, ismcast, pkt_len, error, rix; 2969 #if 0 2970 const uint8_t *p; 2971 int i; 2972 #endif 2973 2974 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 2975 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 2976 mac = (struct bwi_mac *)sc->sc_cur_regwin; 2977 2978 wh = mtod(m, struct ieee80211_frame *); 2979 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2980 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 2981 2982 /* Get 802.11 frame len before prepending TX header */ 2983 pkt_len = m->m_pkthdr.len + IEEE80211_CRC_LEN; 2984 2985 /* 2986 * Find TX rate 2987 */ 2988 tp = &vap->iv_txparms[ieee80211_chan2mode(ic->ic_curchan)]; 2989 if (type != IEEE80211_FC0_TYPE_DATA || (m->m_flags & M_EAPOL)) { 2990 rate = rate_fb = tp->mgmtrate; 2991 } else if (ismcast) { 2992 rate = rate_fb = tp->mcastrate; 2993 } else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) { 2994 rate = rate_fb = tp->ucastrate; 2995 } else { 2996 rix = ieee80211_amrr_choose(ni, &BWI_NODE(ni)->amn); 2997 rate = ni->ni_txrate; 2998 2999 if (rix > 0) { 3000 rate_fb = ni->ni_rates.rs_rates[rix-1] & 3001 IEEE80211_RATE_VAL; 3002 } else { 3003 rate_fb = rate; 3004 } 3005 } 3006 tb->tb_rate[0] = rate; 3007 tb->tb_rate[1] = rate_fb; 3008 sc->sc_tx_rate = rate; 3009 3010 /* 3011 * TX radio tap 3012 */ 3013 if (ieee80211_radiotap_active_vap(vap)) { 3014 sc->sc_tx_th.wt_flags = 0; 3015 if (wh->i_fc[1] & IEEE80211_FC1_WEP) 3016 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP; 3017 if (ieee80211_rate2phytype(sc->sc_rates, rate) == IEEE80211_T_DS && 3018 (ic->ic_flags & IEEE80211_F_SHPREAMBLE) && 3019 rate != (1 * 2)) { 3020 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 3021 } 3022 sc->sc_tx_th.wt_rate = rate; 3023 3024 ieee80211_radiotap_tx(vap, m); 3025 } 3026 3027 /* 3028 * Setup the embedded TX header 3029 */ 3030 M_PREPEND(m, sizeof(*hdr), M_DONTWAIT); 3031 if (m == NULL) { 3032 if_printf(ifp, "%s: prepend TX header failed\n", __func__); 3033 return ENOBUFS; 3034 } 3035 hdr = mtod(m, struct bwi_txbuf_hdr *); 3036 3037 bzero(hdr, sizeof(*hdr)); 3038 3039 bcopy(wh->i_fc, hdr->txh_fc, sizeof(hdr->txh_fc)); 3040 bcopy(wh->i_addr1, hdr->txh_addr1, sizeof(hdr->txh_addr1)); 3041 3042 if (!ismcast) { 3043 uint16_t dur; 3044 3045 dur = ieee80211_ack_duration(sc->sc_rates, rate, 3046 ic->ic_flags & ~IEEE80211_F_SHPREAMBLE); 3047 3048 hdr->txh_fb_duration = htole16(dur); 3049 } 3050 3051 hdr->txh_id = __SHIFTIN(BWI_TX_DATA_RING, BWI_TXH_ID_RING_MASK) | 3052 __SHIFTIN(idx, BWI_TXH_ID_IDX_MASK); 3053 3054 bwi_plcp_header(sc->sc_rates, hdr->txh_plcp, pkt_len, rate); 3055 bwi_plcp_header(sc->sc_rates, hdr->txh_fb_plcp, pkt_len, rate_fb); 3056 3057 phy_ctrl = __SHIFTIN(mac->mac_rf.rf_ant_mode, 3058 BWI_TXH_PHY_C_ANTMODE_MASK); 3059 if (ieee80211_rate2phytype(sc->sc_rates, rate) == IEEE80211_T_OFDM) 3060 phy_ctrl |= BWI_TXH_PHY_C_OFDM; 3061 else if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && rate != (2 * 1)) 3062 phy_ctrl |= BWI_TXH_PHY_C_SHPREAMBLE; 3063 3064 mac_ctrl = BWI_TXH_MAC_C_HWSEQ | BWI_TXH_MAC_C_FIRST_FRAG; 3065 if (!ismcast) 3066 mac_ctrl |= BWI_TXH_MAC_C_ACK; 3067 if (ieee80211_rate2phytype(sc->sc_rates, rate_fb) == IEEE80211_T_OFDM) 3068 mac_ctrl |= BWI_TXH_MAC_C_FB_OFDM; 3069 3070 hdr->txh_mac_ctrl = htole32(mac_ctrl); 3071 hdr->txh_phy_ctrl = htole16(phy_ctrl); 3072 3073 /* Catch any further usage */ 3074 hdr = NULL; 3075 wh = NULL; 3076 3077 /* DMA load */ 3078 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m, 3079 bwi_dma_buf_addr, &paddr, BUS_DMA_NOWAIT); 3080 if (error && error != EFBIG) { 3081 if_printf(ifp, "%s: can't load TX buffer (1) %d\n", 3082 __func__, error); 3083 goto back; 3084 } 3085 3086 if (error) { /* error == EFBIG */ 3087 struct mbuf *m_new; 3088 3089 m_new = m_defrag(m, M_DONTWAIT); 3090 if (m_new == NULL) { 3091 if_printf(ifp, "%s: can't defrag TX buffer\n", 3092 __func__); 3093 error = ENOBUFS; 3094 goto back; 3095 } else { 3096 m = m_new; 3097 } 3098 3099 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m, 3100 bwi_dma_buf_addr, &paddr, 3101 BUS_DMA_NOWAIT); 3102 if (error) { 3103 if_printf(ifp, "%s: can't load TX buffer (2) %d\n", 3104 __func__, error); 3105 goto back; 3106 } 3107 } 3108 error = 0; 3109 3110 bus_dmamap_sync(sc->sc_buf_dtag, tb->tb_dmap, BUS_DMASYNC_PREWRITE); 3111 3112 tb->tb_mbuf = m; 3113 tb->tb_ni = ni; 3114 3115 #if 0 3116 p = mtod(m, const uint8_t *); 3117 for (i = 0; i < m->m_pkthdr.len; ++i) { 3118 if (i != 0 && i % 8 == 0) 3119 printf("\n"); 3120 printf("%02x ", p[i]); 3121 } 3122 printf("\n"); 3123 #endif 3124 DPRINTF(sc, BWI_DBG_TX, "idx %d, pkt_len %d, buflen %d\n", 3125 idx, pkt_len, m->m_pkthdr.len); 3126 3127 /* Setup TX descriptor */ 3128 sc->sc_setup_txdesc(sc, rd, idx, paddr, m->m_pkthdr.len); 3129 bus_dmamap_sync(sc->sc_txring_dtag, rd->rdata_dmap, 3130 BUS_DMASYNC_PREWRITE); 3131 3132 /* Kick start */ 3133 sc->sc_start_tx(sc, rd->rdata_txrx_ctrl, idx); 3134 3135 back: 3136 if (error) 3137 m_freem(m); 3138 return error; 3139 } 3140 3141 static int 3142 bwi_encap_raw(struct bwi_softc *sc, int idx, struct mbuf *m, 3143 struct ieee80211_node *ni, const struct ieee80211_bpf_params *params) 3144 { 3145 struct ifnet *ifp = sc->sc_ifp; 3146 struct ieee80211vap *vap = ni->ni_vap; 3147 struct ieee80211com *ic = ni->ni_ic; 3148 struct bwi_ring_data *rd = &sc->sc_tx_rdata[BWI_TX_DATA_RING]; 3149 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING]; 3150 struct bwi_txbuf *tb = &tbd->tbd_buf[idx]; 3151 struct bwi_mac *mac; 3152 struct bwi_txbuf_hdr *hdr; 3153 struct ieee80211_frame *wh; 3154 uint8_t rate, rate_fb; 3155 uint32_t mac_ctrl; 3156 uint16_t phy_ctrl; 3157 bus_addr_t paddr; 3158 int ismcast, pkt_len, error; 3159 3160 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 3161 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 3162 mac = (struct bwi_mac *)sc->sc_cur_regwin; 3163 3164 wh = mtod(m, struct ieee80211_frame *); 3165 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 3166 3167 /* Get 802.11 frame len before prepending TX header */ 3168 pkt_len = m->m_pkthdr.len + IEEE80211_CRC_LEN; 3169 3170 /* 3171 * Find TX rate 3172 */ 3173 rate = params->ibp_rate0; 3174 if (!ieee80211_isratevalid(ic->ic_rt, rate)) { 3175 /* XXX fall back to mcast/mgmt rate? */ 3176 m_freem(m); 3177 return EINVAL; 3178 } 3179 if (params->ibp_try1 != 0) { 3180 rate_fb = params->ibp_rate1; 3181 if (!ieee80211_isratevalid(ic->ic_rt, rate_fb)) { 3182 /* XXX fall back to rate0? */ 3183 m_freem(m); 3184 return EINVAL; 3185 } 3186 } else 3187 rate_fb = rate; 3188 tb->tb_rate[0] = rate; 3189 tb->tb_rate[1] = rate_fb; 3190 sc->sc_tx_rate = rate; 3191 3192 /* 3193 * TX radio tap 3194 */ 3195 if (ieee80211_radiotap_active_vap(vap)) { 3196 sc->sc_tx_th.wt_flags = 0; 3197 /* XXX IEEE80211_BPF_CRYPTO */ 3198 if (wh->i_fc[1] & IEEE80211_FC1_WEP) 3199 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP; 3200 if (params->ibp_flags & IEEE80211_BPF_SHORTPRE) 3201 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 3202 sc->sc_tx_th.wt_rate = rate; 3203 3204 ieee80211_radiotap_tx(vap, m); 3205 } 3206 3207 /* 3208 * Setup the embedded TX header 3209 */ 3210 M_PREPEND(m, sizeof(*hdr), M_DONTWAIT); 3211 if (m == NULL) { 3212 if_printf(ifp, "%s: prepend TX header failed\n", __func__); 3213 return ENOBUFS; 3214 } 3215 hdr = mtod(m, struct bwi_txbuf_hdr *); 3216 3217 bzero(hdr, sizeof(*hdr)); 3218 3219 bcopy(wh->i_fc, hdr->txh_fc, sizeof(hdr->txh_fc)); 3220 bcopy(wh->i_addr1, hdr->txh_addr1, sizeof(hdr->txh_addr1)); 3221 3222 mac_ctrl = BWI_TXH_MAC_C_HWSEQ | BWI_TXH_MAC_C_FIRST_FRAG; 3223 if (!ismcast && (params->ibp_flags & IEEE80211_BPF_NOACK) == 0) { 3224 uint16_t dur; 3225 3226 dur = ieee80211_ack_duration(sc->sc_rates, rate_fb, 0); 3227 3228 hdr->txh_fb_duration = htole16(dur); 3229 mac_ctrl |= BWI_TXH_MAC_C_ACK; 3230 } 3231 3232 hdr->txh_id = __SHIFTIN(BWI_TX_DATA_RING, BWI_TXH_ID_RING_MASK) | 3233 __SHIFTIN(idx, BWI_TXH_ID_IDX_MASK); 3234 3235 bwi_plcp_header(sc->sc_rates, hdr->txh_plcp, pkt_len, rate); 3236 bwi_plcp_header(sc->sc_rates, hdr->txh_fb_plcp, pkt_len, rate_fb); 3237 3238 phy_ctrl = __SHIFTIN(mac->mac_rf.rf_ant_mode, 3239 BWI_TXH_PHY_C_ANTMODE_MASK); 3240 if (ieee80211_rate2phytype(sc->sc_rates, rate) == IEEE80211_T_OFDM) { 3241 phy_ctrl |= BWI_TXH_PHY_C_OFDM; 3242 mac_ctrl |= BWI_TXH_MAC_C_FB_OFDM; 3243 } else if (params->ibp_flags & IEEE80211_BPF_SHORTPRE) 3244 phy_ctrl |= BWI_TXH_PHY_C_SHPREAMBLE; 3245 3246 hdr->txh_mac_ctrl = htole32(mac_ctrl); 3247 hdr->txh_phy_ctrl = htole16(phy_ctrl); 3248 3249 /* Catch any further usage */ 3250 hdr = NULL; 3251 wh = NULL; 3252 3253 /* DMA load */ 3254 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m, 3255 bwi_dma_buf_addr, &paddr, BUS_DMA_NOWAIT); 3256 if (error != 0) { 3257 struct mbuf *m_new; 3258 3259 if (error != EFBIG) { 3260 if_printf(ifp, "%s: can't load TX buffer (1) %d\n", 3261 __func__, error); 3262 goto back; 3263 } 3264 m_new = m_defrag(m, M_DONTWAIT); 3265 if (m_new == NULL) { 3266 if_printf(ifp, "%s: can't defrag TX buffer\n", 3267 __func__); 3268 error = ENOBUFS; 3269 goto back; 3270 } 3271 m = m_new; 3272 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m, 3273 bwi_dma_buf_addr, &paddr, 3274 BUS_DMA_NOWAIT); 3275 if (error) { 3276 if_printf(ifp, "%s: can't load TX buffer (2) %d\n", 3277 __func__, error); 3278 goto back; 3279 } 3280 } 3281 3282 bus_dmamap_sync(sc->sc_buf_dtag, tb->tb_dmap, BUS_DMASYNC_PREWRITE); 3283 3284 tb->tb_mbuf = m; 3285 tb->tb_ni = ni; 3286 3287 DPRINTF(sc, BWI_DBG_TX, "idx %d, pkt_len %d, buflen %d\n", 3288 idx, pkt_len, m->m_pkthdr.len); 3289 3290 /* Setup TX descriptor */ 3291 sc->sc_setup_txdesc(sc, rd, idx, paddr, m->m_pkthdr.len); 3292 bus_dmamap_sync(sc->sc_txring_dtag, rd->rdata_dmap, 3293 BUS_DMASYNC_PREWRITE); 3294 3295 /* Kick start */ 3296 sc->sc_start_tx(sc, rd->rdata_txrx_ctrl, idx); 3297 back: 3298 if (error) 3299 m_freem(m); 3300 return error; 3301 } 3302 3303 static void 3304 bwi_start_tx32(struct bwi_softc *sc, uint32_t tx_ctrl, int idx) 3305 { 3306 idx = (idx + 1) % BWI_TX_NDESC; 3307 CSR_WRITE_4(sc, tx_ctrl + BWI_TX32_INDEX, 3308 idx * sizeof(struct bwi_desc32)); 3309 } 3310 3311 static void 3312 bwi_start_tx64(struct bwi_softc *sc, uint32_t tx_ctrl, int idx) 3313 { 3314 /* TODO:64 */ 3315 } 3316 3317 static void 3318 bwi_txeof_status32(struct bwi_softc *sc) 3319 { 3320 struct ifnet *ifp = sc->sc_ifp; 3321 uint32_t val, ctrl_base; 3322 int end_idx; 3323 3324 ctrl_base = sc->sc_txstats->stats_ctrl_base; 3325 3326 val = CSR_READ_4(sc, ctrl_base + BWI_RX32_STATUS); 3327 end_idx = __SHIFTOUT(val, BWI_RX32_STATUS_INDEX_MASK) / 3328 sizeof(struct bwi_desc32); 3329 3330 bwi_txeof_status(sc, end_idx); 3331 3332 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_INDEX, 3333 end_idx * sizeof(struct bwi_desc32)); 3334 3335 if ((ifp->if_drv_flags & IFF_DRV_OACTIVE) == 0) 3336 ifp->if_start(ifp); 3337 } 3338 3339 static void 3340 bwi_txeof_status64(struct bwi_softc *sc) 3341 { 3342 /* TODO:64 */ 3343 } 3344 3345 static void 3346 _bwi_txeof(struct bwi_softc *sc, uint16_t tx_id, int acked, int data_txcnt) 3347 { 3348 struct ifnet *ifp = sc->sc_ifp; 3349 struct bwi_txbuf_data *tbd; 3350 struct bwi_txbuf *tb; 3351 int ring_idx, buf_idx; 3352 struct ieee80211_node *ni; 3353 3354 if (tx_id == 0) { 3355 if_printf(ifp, "%s: zero tx id\n", __func__); 3356 return; 3357 } 3358 3359 ring_idx = __SHIFTOUT(tx_id, BWI_TXH_ID_RING_MASK); 3360 buf_idx = __SHIFTOUT(tx_id, BWI_TXH_ID_IDX_MASK); 3361 3362 KASSERT(ring_idx == BWI_TX_DATA_RING, ("ring_idx %d", ring_idx)); 3363 KASSERT(buf_idx < BWI_TX_NDESC, ("buf_idx %d", buf_idx)); 3364 3365 tbd = &sc->sc_tx_bdata[ring_idx]; 3366 KASSERT(tbd->tbd_used > 0, ("tbd_used %d", tbd->tbd_used)); 3367 tbd->tbd_used--; 3368 3369 tb = &tbd->tbd_buf[buf_idx]; 3370 DPRINTF(sc, BWI_DBG_TXEOF, "txeof idx %d, " 3371 "acked %d, data_txcnt %d, ni %p\n", 3372 buf_idx, acked, data_txcnt, tb->tb_ni); 3373 3374 bus_dmamap_unload(sc->sc_buf_dtag, tb->tb_dmap); 3375 3376 ni = tb->tb_ni; 3377 if (tb->tb_ni != NULL) { 3378 struct bwi_node *bn = (struct bwi_node *) tb->tb_ni; 3379 const struct bwi_txbuf_hdr *hdr = 3380 mtod(tb->tb_mbuf, const struct bwi_txbuf_hdr *); 3381 3382 /* NB: update rate control only for unicast frames */ 3383 if (hdr->txh_mac_ctrl & htole32(BWI_TXH_MAC_C_ACK)) { 3384 /* 3385 * Feed back 'acked and data_txcnt'. Note that the 3386 * generic AMRR code only understands one tx rate 3387 * and the estimator doesn't handle real retry counts 3388 * well so to avoid over-aggressive downshifting we 3389 * treat any number of retries as "1". 3390 */ 3391 ieee80211_amrr_tx_complete(&bn->amn, acked, 3392 data_txcnt > 1); 3393 } 3394 3395 /* 3396 * Do any tx complete callback. Note this must 3397 * be done before releasing the node reference. 3398 */ 3399 if (tb->tb_mbuf->m_flags & M_TXCB) 3400 ieee80211_process_callback(ni, tb->tb_mbuf, !acked); 3401 3402 ieee80211_free_node(tb->tb_ni); 3403 tb->tb_ni = NULL; 3404 } 3405 m_freem(tb->tb_mbuf); 3406 tb->tb_mbuf = NULL; 3407 3408 if (tbd->tbd_used == 0) 3409 ifp->if_timer = 0; 3410 3411 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3412 } 3413 3414 static void 3415 bwi_txeof_status(struct bwi_softc *sc, int end_idx) 3416 { 3417 struct bwi_txstats_data *st = sc->sc_txstats; 3418 int idx; 3419 3420 bus_dmamap_sync(st->stats_dtag, st->stats_dmap, BUS_DMASYNC_POSTREAD); 3421 3422 idx = st->stats_idx; 3423 while (idx != end_idx) { 3424 const struct bwi_txstats *stats = &st->stats[idx]; 3425 3426 if ((stats->txs_flags & BWI_TXS_F_PENDING) == 0) { 3427 int data_txcnt; 3428 3429 data_txcnt = __SHIFTOUT(stats->txs_txcnt, 3430 BWI_TXS_TXCNT_DATA); 3431 _bwi_txeof(sc, le16toh(stats->txs_id), 3432 stats->txs_flags & BWI_TXS_F_ACKED, 3433 data_txcnt); 3434 } 3435 idx = (idx + 1) % BWI_TXSTATS_NDESC; 3436 } 3437 st->stats_idx = idx; 3438 } 3439 3440 static void 3441 bwi_txeof(struct bwi_softc *sc) 3442 { 3443 struct ifnet *ifp = sc->sc_ifp; 3444 3445 for (;;) { 3446 uint32_t tx_status0, tx_status1; 3447 uint16_t tx_id; 3448 int data_txcnt; 3449 3450 tx_status0 = CSR_READ_4(sc, BWI_TXSTATUS0); 3451 if ((tx_status0 & BWI_TXSTATUS0_VALID) == 0) 3452 break; 3453 tx_status1 = CSR_READ_4(sc, BWI_TXSTATUS1); 3454 3455 tx_id = __SHIFTOUT(tx_status0, BWI_TXSTATUS0_TXID_MASK); 3456 data_txcnt = __SHIFTOUT(tx_status0, 3457 BWI_TXSTATUS0_DATA_TXCNT_MASK); 3458 3459 if (tx_status0 & (BWI_TXSTATUS0_AMPDU | BWI_TXSTATUS0_PENDING)) 3460 continue; 3461 3462 _bwi_txeof(sc, le16toh(tx_id), tx_status0 & BWI_TXSTATUS0_ACKED, 3463 data_txcnt); 3464 } 3465 3466 if ((ifp->if_drv_flags & IFF_DRV_OACTIVE) == 0) 3467 ifp->if_start(ifp); 3468 } 3469 3470 static int 3471 bwi_bbp_power_on(struct bwi_softc *sc, enum bwi_clock_mode clk_mode) 3472 { 3473 bwi_power_on(sc, 1); 3474 return bwi_set_clock_mode(sc, clk_mode); 3475 } 3476 3477 static void 3478 bwi_bbp_power_off(struct bwi_softc *sc) 3479 { 3480 bwi_set_clock_mode(sc, BWI_CLOCK_MODE_SLOW); 3481 bwi_power_off(sc, 1); 3482 } 3483 3484 static int 3485 bwi_get_pwron_delay(struct bwi_softc *sc) 3486 { 3487 struct bwi_regwin *com, *old; 3488 struct bwi_clock_freq freq; 3489 uint32_t val; 3490 int error; 3491 3492 com = &sc->sc_com_regwin; 3493 KASSERT(BWI_REGWIN_EXIST(com), ("no regwin")); 3494 3495 if ((sc->sc_cap & BWI_CAP_CLKMODE) == 0) 3496 return 0; 3497 3498 error = bwi_regwin_switch(sc, com, &old); 3499 if (error) 3500 return error; 3501 3502 bwi_get_clock_freq(sc, &freq); 3503 3504 val = CSR_READ_4(sc, BWI_PLL_ON_DELAY); 3505 sc->sc_pwron_delay = howmany((val + 2) * 1000000, freq.clkfreq_min); 3506 DPRINTF(sc, BWI_DBG_ATTACH, "power on delay %u\n", sc->sc_pwron_delay); 3507 3508 return bwi_regwin_switch(sc, old, NULL); 3509 } 3510 3511 static int 3512 bwi_bus_attach(struct bwi_softc *sc) 3513 { 3514 struct bwi_regwin *bus, *old; 3515 int error; 3516 3517 bus = &sc->sc_bus_regwin; 3518 3519 error = bwi_regwin_switch(sc, bus, &old); 3520 if (error) 3521 return error; 3522 3523 if (!bwi_regwin_is_enabled(sc, bus)) 3524 bwi_regwin_enable(sc, bus, 0); 3525 3526 /* Disable interripts */ 3527 CSR_WRITE_4(sc, BWI_INTRVEC, 0); 3528 3529 return bwi_regwin_switch(sc, old, NULL); 3530 } 3531 3532 static const char * 3533 bwi_regwin_name(const struct bwi_regwin *rw) 3534 { 3535 switch (rw->rw_type) { 3536 case BWI_REGWIN_T_COM: 3537 return "COM"; 3538 case BWI_REGWIN_T_BUSPCI: 3539 return "PCI"; 3540 case BWI_REGWIN_T_MAC: 3541 return "MAC"; 3542 case BWI_REGWIN_T_BUSPCIE: 3543 return "PCIE"; 3544 } 3545 panic("unknown regwin type 0x%04x\n", rw->rw_type); 3546 return NULL; 3547 } 3548 3549 static uint32_t 3550 bwi_regwin_disable_bits(struct bwi_softc *sc) 3551 { 3552 uint32_t busrev; 3553 3554 /* XXX cache this */ 3555 busrev = __SHIFTOUT(CSR_READ_4(sc, BWI_ID_LO), BWI_ID_LO_BUSREV_MASK); 3556 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT | BWI_DBG_MISC, 3557 "bus rev %u\n", busrev); 3558 3559 if (busrev == BWI_BUSREV_0) 3560 return BWI_STATE_LO_DISABLE1; 3561 else if (busrev == BWI_BUSREV_1) 3562 return BWI_STATE_LO_DISABLE2; 3563 else 3564 return (BWI_STATE_LO_DISABLE1 | BWI_STATE_LO_DISABLE2); 3565 } 3566 3567 int 3568 bwi_regwin_is_enabled(struct bwi_softc *sc, struct bwi_regwin *rw) 3569 { 3570 uint32_t val, disable_bits; 3571 3572 disable_bits = bwi_regwin_disable_bits(sc); 3573 val = CSR_READ_4(sc, BWI_STATE_LO); 3574 3575 if ((val & (BWI_STATE_LO_CLOCK | 3576 BWI_STATE_LO_RESET | 3577 disable_bits)) == BWI_STATE_LO_CLOCK) { 3578 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT, "%s is enabled\n", 3579 bwi_regwin_name(rw)); 3580 return 1; 3581 } else { 3582 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT, "%s is disabled\n", 3583 bwi_regwin_name(rw)); 3584 return 0; 3585 } 3586 } 3587 3588 void 3589 bwi_regwin_disable(struct bwi_softc *sc, struct bwi_regwin *rw, uint32_t flags) 3590 { 3591 uint32_t state_lo, disable_bits; 3592 int i; 3593 3594 state_lo = CSR_READ_4(sc, BWI_STATE_LO); 3595 3596 /* 3597 * If current regwin is in 'reset' state, it was already disabled. 3598 */ 3599 if (state_lo & BWI_STATE_LO_RESET) { 3600 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT, 3601 "%s was already disabled\n", bwi_regwin_name(rw)); 3602 return; 3603 } 3604 3605 disable_bits = bwi_regwin_disable_bits(sc); 3606 3607 /* 3608 * Disable normal clock 3609 */ 3610 state_lo = BWI_STATE_LO_CLOCK | disable_bits; 3611 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo); 3612 3613 /* 3614 * Wait until normal clock is disabled 3615 */ 3616 #define NRETRY 1000 3617 for (i = 0; i < NRETRY; ++i) { 3618 state_lo = CSR_READ_4(sc, BWI_STATE_LO); 3619 if (state_lo & disable_bits) 3620 break; 3621 DELAY(10); 3622 } 3623 if (i == NRETRY) { 3624 device_printf(sc->sc_dev, "%s disable clock timeout\n", 3625 bwi_regwin_name(rw)); 3626 } 3627 3628 for (i = 0; i < NRETRY; ++i) { 3629 uint32_t state_hi; 3630 3631 state_hi = CSR_READ_4(sc, BWI_STATE_HI); 3632 if ((state_hi & BWI_STATE_HI_BUSY) == 0) 3633 break; 3634 DELAY(10); 3635 } 3636 if (i == NRETRY) { 3637 device_printf(sc->sc_dev, "%s wait BUSY unset timeout\n", 3638 bwi_regwin_name(rw)); 3639 } 3640 #undef NRETRY 3641 3642 /* 3643 * Reset and disable regwin with gated clock 3644 */ 3645 state_lo = BWI_STATE_LO_RESET | disable_bits | 3646 BWI_STATE_LO_CLOCK | BWI_STATE_LO_GATED_CLOCK | 3647 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK); 3648 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo); 3649 3650 /* Flush pending bus write */ 3651 CSR_READ_4(sc, BWI_STATE_LO); 3652 DELAY(1); 3653 3654 /* Reset and disable regwin */ 3655 state_lo = BWI_STATE_LO_RESET | disable_bits | 3656 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK); 3657 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo); 3658 3659 /* Flush pending bus write */ 3660 CSR_READ_4(sc, BWI_STATE_LO); 3661 DELAY(1); 3662 } 3663 3664 void 3665 bwi_regwin_enable(struct bwi_softc *sc, struct bwi_regwin *rw, uint32_t flags) 3666 { 3667 uint32_t state_lo, state_hi, imstate; 3668 3669 bwi_regwin_disable(sc, rw, flags); 3670 3671 /* Reset regwin with gated clock */ 3672 state_lo = BWI_STATE_LO_RESET | 3673 BWI_STATE_LO_CLOCK | 3674 BWI_STATE_LO_GATED_CLOCK | 3675 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK); 3676 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo); 3677 3678 /* Flush pending bus write */ 3679 CSR_READ_4(sc, BWI_STATE_LO); 3680 DELAY(1); 3681 3682 state_hi = CSR_READ_4(sc, BWI_STATE_HI); 3683 if (state_hi & BWI_STATE_HI_SERROR) 3684 CSR_WRITE_4(sc, BWI_STATE_HI, 0); 3685 3686 imstate = CSR_READ_4(sc, BWI_IMSTATE); 3687 if (imstate & (BWI_IMSTATE_INBAND_ERR | BWI_IMSTATE_TIMEOUT)) { 3688 imstate &= ~(BWI_IMSTATE_INBAND_ERR | BWI_IMSTATE_TIMEOUT); 3689 CSR_WRITE_4(sc, BWI_IMSTATE, imstate); 3690 } 3691 3692 /* Enable regwin with gated clock */ 3693 state_lo = BWI_STATE_LO_CLOCK | 3694 BWI_STATE_LO_GATED_CLOCK | 3695 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK); 3696 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo); 3697 3698 /* Flush pending bus write */ 3699 CSR_READ_4(sc, BWI_STATE_LO); 3700 DELAY(1); 3701 3702 /* Enable regwin with normal clock */ 3703 state_lo = BWI_STATE_LO_CLOCK | 3704 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK); 3705 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo); 3706 3707 /* Flush pending bus write */ 3708 CSR_READ_4(sc, BWI_STATE_LO); 3709 DELAY(1); 3710 } 3711 3712 static void 3713 bwi_set_bssid(struct bwi_softc *sc, const uint8_t *bssid) 3714 { 3715 struct ifnet *ifp = sc->sc_ifp; 3716 struct bwi_mac *mac; 3717 struct bwi_myaddr_bssid buf; 3718 const uint8_t *p; 3719 uint32_t val; 3720 int n, i; 3721 3722 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 3723 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 3724 mac = (struct bwi_mac *)sc->sc_cur_regwin; 3725 3726 bwi_set_addr_filter(sc, BWI_ADDR_FILTER_BSSID, bssid); 3727 3728 bcopy(IF_LLADDR(ifp), buf.myaddr, sizeof(buf.myaddr)); 3729 bcopy(bssid, buf.bssid, sizeof(buf.bssid)); 3730 3731 n = sizeof(buf) / sizeof(val); 3732 p = (const uint8_t *)&buf; 3733 for (i = 0; i < n; ++i) { 3734 int j; 3735 3736 val = 0; 3737 for (j = 0; j < sizeof(val); ++j) 3738 val |= ((uint32_t)(*p++)) << (j * 8); 3739 3740 TMPLT_WRITE_4(mac, 0x20 + (i * sizeof(val)), val); 3741 } 3742 } 3743 3744 static void 3745 bwi_updateslot(struct ifnet *ifp) 3746 { 3747 struct bwi_softc *sc = ifp->if_softc; 3748 struct ieee80211com *ic = ifp->if_l2com; 3749 struct bwi_mac *mac; 3750 3751 BWI_LOCK(sc); 3752 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3753 DPRINTF(sc, BWI_DBG_80211, "%s\n", __func__); 3754 3755 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 3756 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 3757 mac = (struct bwi_mac *)sc->sc_cur_regwin; 3758 3759 bwi_mac_updateslot(mac, (ic->ic_flags & IEEE80211_F_SHSLOT)); 3760 } 3761 BWI_UNLOCK(sc); 3762 } 3763 3764 static void 3765 bwi_calibrate(void *xsc) 3766 { 3767 struct bwi_softc *sc = xsc; 3768 #ifdef INVARIANTS 3769 struct ifnet *ifp = sc->sc_ifp; 3770 struct ieee80211com *ic = ifp->if_l2com; 3771 #endif 3772 struct bwi_mac *mac; 3773 3774 BWI_ASSERT_LOCKED(sc); 3775 3776 KASSERT(ic->ic_opmode != IEEE80211_M_MONITOR, 3777 ("opmode %d", ic->ic_opmode)); 3778 3779 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 3780 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 3781 mac = (struct bwi_mac *)sc->sc_cur_regwin; 3782 3783 bwi_mac_calibrate_txpower(mac, sc->sc_txpwrcb_type); 3784 sc->sc_txpwrcb_type = BWI_TXPWR_CALIB; 3785 3786 /* XXX 15 seconds */ 3787 callout_reset(&sc->sc_calib_ch, hz * 15, bwi_calibrate, sc); 3788 } 3789 3790 static int 3791 bwi_calc_rssi(struct bwi_softc *sc, const struct bwi_rxbuf_hdr *hdr) 3792 { 3793 struct bwi_mac *mac; 3794 3795 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 3796 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 3797 mac = (struct bwi_mac *)sc->sc_cur_regwin; 3798 3799 return bwi_rf_calc_rssi(mac, hdr); 3800 } 3801 3802 static int 3803 bwi_calc_noise(struct bwi_softc *sc) 3804 { 3805 struct bwi_mac *mac; 3806 3807 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 3808 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 3809 mac = (struct bwi_mac *)sc->sc_cur_regwin; 3810 3811 return bwi_rf_calc_noise(mac); 3812 } 3813 3814 static __inline uint8_t 3815 bwi_ofdm_plcp2rate(const uint32_t *plcp0) 3816 { 3817 uint32_t plcp; 3818 uint8_t plcp_rate; 3819 3820 plcp = le32toh(*plcp0); 3821 plcp_rate = __SHIFTOUT(plcp, IEEE80211_OFDM_PLCP_RATE_MASK); 3822 return ieee80211_plcp2rate(plcp_rate, IEEE80211_T_OFDM); 3823 } 3824 3825 static __inline uint8_t 3826 bwi_ds_plcp2rate(const struct ieee80211_ds_plcp_hdr *hdr) 3827 { 3828 return ieee80211_plcp2rate(hdr->i_signal, IEEE80211_T_DS); 3829 } 3830 3831 static void 3832 bwi_rx_radiotap(struct bwi_softc *sc, struct mbuf *m, 3833 struct bwi_rxbuf_hdr *hdr, const void *plcp, int rate, int rssi, int noise) 3834 { 3835 const struct ieee80211_frame_min *wh; 3836 3837 sc->sc_rx_th.wr_flags = IEEE80211_RADIOTAP_F_FCS; 3838 if (htole16(hdr->rxh_flags1) & BWI_RXH_F1_SHPREAMBLE) 3839 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 3840 3841 wh = mtod(m, const struct ieee80211_frame_min *); 3842 if (wh->i_fc[1] & IEEE80211_FC1_WEP) 3843 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_WEP; 3844 3845 sc->sc_rx_th.wr_tsf = hdr->rxh_tsf; /* No endian convertion */ 3846 sc->sc_rx_th.wr_rate = rate; 3847 sc->sc_rx_th.wr_antsignal = rssi; 3848 sc->sc_rx_th.wr_antnoise = noise; 3849 } 3850 3851 static void 3852 bwi_led_attach(struct bwi_softc *sc) 3853 { 3854 const uint8_t *led_act = NULL; 3855 uint16_t gpio, val[BWI_LED_MAX]; 3856 int i; 3857 3858 #define N(arr) (int)(sizeof(arr) / sizeof(arr[0])) 3859 3860 for (i = 0; i < N(bwi_vendor_led_act); ++i) { 3861 if (sc->sc_pci_subvid == bwi_vendor_led_act[i].vid) { 3862 led_act = bwi_vendor_led_act[i].led_act; 3863 break; 3864 } 3865 } 3866 if (led_act == NULL) 3867 led_act = bwi_default_led_act; 3868 3869 #undef N 3870 3871 gpio = bwi_read_sprom(sc, BWI_SPROM_GPIO01); 3872 val[0] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_0); 3873 val[1] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_1); 3874 3875 gpio = bwi_read_sprom(sc, BWI_SPROM_GPIO23); 3876 val[2] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_2); 3877 val[3] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_3); 3878 3879 for (i = 0; i < BWI_LED_MAX; ++i) { 3880 struct bwi_led *led = &sc->sc_leds[i]; 3881 3882 if (val[i] == 0xff) { 3883 led->l_act = led_act[i]; 3884 } else { 3885 if (val[i] & BWI_LED_ACT_LOW) 3886 led->l_flags |= BWI_LED_F_ACTLOW; 3887 led->l_act = __SHIFTOUT(val[i], BWI_LED_ACT_MASK); 3888 } 3889 led->l_mask = (1 << i); 3890 3891 if (led->l_act == BWI_LED_ACT_BLINK_SLOW || 3892 led->l_act == BWI_LED_ACT_BLINK_POLL || 3893 led->l_act == BWI_LED_ACT_BLINK) { 3894 led->l_flags |= BWI_LED_F_BLINK; 3895 if (led->l_act == BWI_LED_ACT_BLINK_POLL) 3896 led->l_flags |= BWI_LED_F_POLLABLE; 3897 else if (led->l_act == BWI_LED_ACT_BLINK_SLOW) 3898 led->l_flags |= BWI_LED_F_SLOW; 3899 3900 if (sc->sc_blink_led == NULL) { 3901 sc->sc_blink_led = led; 3902 if (led->l_flags & BWI_LED_F_SLOW) 3903 BWI_LED_SLOWDOWN(sc->sc_led_idle); 3904 } 3905 } 3906 3907 DPRINTF(sc, BWI_DBG_LED | BWI_DBG_ATTACH, 3908 "%dth led, act %d, lowact %d\n", i, 3909 led->l_act, led->l_flags & BWI_LED_F_ACTLOW); 3910 } 3911 callout_init(&sc->sc_led_blink_ch, CALLOUT_MPSAFE); 3912 } 3913 3914 static __inline uint16_t 3915 bwi_led_onoff(const struct bwi_led *led, uint16_t val, int on) 3916 { 3917 if (led->l_flags & BWI_LED_F_ACTLOW) 3918 on = !on; 3919 if (on) 3920 val |= led->l_mask; 3921 else 3922 val &= ~led->l_mask; 3923 return val; 3924 } 3925 3926 static void 3927 bwi_led_newstate(struct bwi_softc *sc, enum ieee80211_state nstate) 3928 { 3929 struct ifnet *ifp = sc->sc_ifp; 3930 struct ieee80211com *ic = ifp->if_l2com; 3931 uint16_t val; 3932 int i; 3933 3934 if (nstate == IEEE80211_S_INIT) { 3935 callout_stop(&sc->sc_led_blink_ch); 3936 sc->sc_led_blinking = 0; 3937 } 3938 3939 if ((ic->ic_ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 3940 return; 3941 3942 val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL); 3943 for (i = 0; i < BWI_LED_MAX; ++i) { 3944 struct bwi_led *led = &sc->sc_leds[i]; 3945 int on; 3946 3947 if (led->l_act == BWI_LED_ACT_UNKN || 3948 led->l_act == BWI_LED_ACT_NULL) 3949 continue; 3950 3951 if ((led->l_flags & BWI_LED_F_BLINK) && 3952 nstate != IEEE80211_S_INIT) 3953 continue; 3954 3955 switch (led->l_act) { 3956 case BWI_LED_ACT_ON: /* Always on */ 3957 on = 1; 3958 break; 3959 case BWI_LED_ACT_OFF: /* Always off */ 3960 case BWI_LED_ACT_5GHZ: /* TODO: 11A */ 3961 on = 0; 3962 break; 3963 default: 3964 on = 1; 3965 switch (nstate) { 3966 case IEEE80211_S_INIT: 3967 on = 0; 3968 break; 3969 case IEEE80211_S_RUN: 3970 if (led->l_act == BWI_LED_ACT_11G && 3971 ic->ic_curmode != IEEE80211_MODE_11G) 3972 on = 0; 3973 break; 3974 default: 3975 if (led->l_act == BWI_LED_ACT_ASSOC) 3976 on = 0; 3977 break; 3978 } 3979 break; 3980 } 3981 3982 val = bwi_led_onoff(led, val, on); 3983 } 3984 CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val); 3985 } 3986 static void 3987 bwi_led_event(struct bwi_softc *sc, int event) 3988 { 3989 struct bwi_led *led = sc->sc_blink_led; 3990 int rate; 3991 3992 if (event == BWI_LED_EVENT_POLL) { 3993 if ((led->l_flags & BWI_LED_F_POLLABLE) == 0) 3994 return; 3995 if (ticks - sc->sc_led_ticks < sc->sc_led_idle) 3996 return; 3997 } 3998 3999 sc->sc_led_ticks = ticks; 4000 if (sc->sc_led_blinking) 4001 return; 4002 4003 switch (event) { 4004 case BWI_LED_EVENT_RX: 4005 rate = sc->sc_rx_rate; 4006 break; 4007 case BWI_LED_EVENT_TX: 4008 rate = sc->sc_tx_rate; 4009 break; 4010 case BWI_LED_EVENT_POLL: 4011 rate = 0; 4012 break; 4013 default: 4014 panic("unknown LED event %d\n", event); 4015 break; 4016 } 4017 bwi_led_blink_start(sc, bwi_led_duration[rate].on_dur, 4018 bwi_led_duration[rate].off_dur); 4019 } 4020 4021 static void 4022 bwi_led_blink_start(struct bwi_softc *sc, int on_dur, int off_dur) 4023 { 4024 struct bwi_led *led = sc->sc_blink_led; 4025 uint16_t val; 4026 4027 val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL); 4028 val = bwi_led_onoff(led, val, 1); 4029 CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val); 4030 4031 if (led->l_flags & BWI_LED_F_SLOW) { 4032 BWI_LED_SLOWDOWN(on_dur); 4033 BWI_LED_SLOWDOWN(off_dur); 4034 } 4035 4036 sc->sc_led_blinking = 1; 4037 sc->sc_led_blink_offdur = off_dur; 4038 4039 callout_reset(&sc->sc_led_blink_ch, on_dur, bwi_led_blink_next, sc); 4040 } 4041 4042 static void 4043 bwi_led_blink_next(void *xsc) 4044 { 4045 struct bwi_softc *sc = xsc; 4046 uint16_t val; 4047 4048 val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL); 4049 val = bwi_led_onoff(sc->sc_blink_led, val, 0); 4050 CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val); 4051 4052 callout_reset(&sc->sc_led_blink_ch, sc->sc_led_blink_offdur, 4053 bwi_led_blink_end, sc); 4054 } 4055 4056 static void 4057 bwi_led_blink_end(void *xsc) 4058 { 4059 struct bwi_softc *sc = xsc; 4060 sc->sc_led_blinking = 0; 4061 } 4062 4063 static void 4064 bwi_restart(void *xsc, int pending) 4065 { 4066 struct bwi_softc *sc = xsc; 4067 struct ifnet *ifp = sc->sc_ifp; 4068 4069 if_printf(ifp, "%s begin, help!\n", __func__); 4070 BWI_LOCK(sc); 4071 bwi_init_statechg(xsc, 0); 4072 #if 0 4073 bwi_start_locked(ifp); 4074 #endif 4075 BWI_UNLOCK(sc); 4076 } 4077