1 /* 2 * Copyright (c) 2007 The DragonFly Project. All rights reserved. 3 * 4 * This code is derived from software contributed to The DragonFly Project 5 * by Sepherosa Ziehau <sepherosa@gmail.com> 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * 3. Neither the name of The DragonFly Project nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific, prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 24 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 25 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 27 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 29 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * $DragonFly: src/sys/dev/netif/bwi/if_bwi.c,v 1.19 2008/02/15 11:15:38 sephe Exp $ 35 */ 36 37 #include <sys/cdefs.h> 38 __FBSDID("$FreeBSD$"); 39 40 #include "opt_inet.h" 41 #include "opt_bwi.h" 42 #include "opt_wlan.h" 43 44 #include <sys/param.h> 45 #include <sys/endian.h> 46 #include <sys/kernel.h> 47 #include <sys/bus.h> 48 #include <sys/malloc.h> 49 #include <sys/proc.h> 50 #include <sys/rman.h> 51 #include <sys/socket.h> 52 #include <sys/sockio.h> 53 #include <sys/sysctl.h> 54 #include <sys/systm.h> 55 #include <sys/taskqueue.h> 56 57 #include <net/if.h> 58 #include <net/if_var.h> 59 #include <net/if_dl.h> 60 #include <net/if_media.h> 61 #include <net/if_types.h> 62 #include <net/if_arp.h> 63 #include <net/ethernet.h> 64 #include <net/if_llc.h> 65 66 #include <net80211/ieee80211_var.h> 67 #include <net80211/ieee80211_radiotap.h> 68 #include <net80211/ieee80211_regdomain.h> 69 #include <net80211/ieee80211_phy.h> 70 #include <net80211/ieee80211_ratectl.h> 71 72 #include <net/bpf.h> 73 74 #ifdef INET 75 #include <netinet/in.h> 76 #include <netinet/if_ether.h> 77 #endif 78 79 #include <machine/bus.h> 80 81 #include <dev/pci/pcivar.h> 82 #include <dev/pci/pcireg.h> 83 84 #include <dev/bwi/bitops.h> 85 #include <dev/bwi/if_bwireg.h> 86 #include <dev/bwi/if_bwivar.h> 87 #include <dev/bwi/bwimac.h> 88 #include <dev/bwi/bwirf.h> 89 90 struct bwi_clock_freq { 91 u_int clkfreq_min; 92 u_int clkfreq_max; 93 }; 94 95 struct bwi_myaddr_bssid { 96 uint8_t myaddr[IEEE80211_ADDR_LEN]; 97 uint8_t bssid[IEEE80211_ADDR_LEN]; 98 } __packed; 99 100 static struct ieee80211vap *bwi_vap_create(struct ieee80211com *, 101 const char [IFNAMSIZ], int, enum ieee80211_opmode, int, 102 const uint8_t [IEEE80211_ADDR_LEN], 103 const uint8_t [IEEE80211_ADDR_LEN]); 104 static void bwi_vap_delete(struct ieee80211vap *); 105 static void bwi_init(struct bwi_softc *); 106 static void bwi_parent(struct ieee80211com *); 107 static int bwi_transmit(struct ieee80211com *, struct mbuf *); 108 static void bwi_start_locked(struct bwi_softc *); 109 static int bwi_raw_xmit(struct ieee80211_node *, struct mbuf *, 110 const struct ieee80211_bpf_params *); 111 static void bwi_watchdog(void *); 112 static void bwi_scan_start(struct ieee80211com *); 113 static void bwi_set_channel(struct ieee80211com *); 114 static void bwi_scan_end(struct ieee80211com *); 115 static int bwi_newstate(struct ieee80211vap *, enum ieee80211_state, int); 116 static void bwi_updateslot(struct ieee80211com *); 117 static int bwi_media_change(struct ifnet *); 118 119 static void bwi_calibrate(void *); 120 121 static int bwi_calc_rssi(struct bwi_softc *, const struct bwi_rxbuf_hdr *); 122 static int bwi_calc_noise(struct bwi_softc *); 123 static __inline uint8_t bwi_plcp2rate(uint32_t, enum ieee80211_phytype); 124 static void bwi_rx_radiotap(struct bwi_softc *, struct mbuf *, 125 struct bwi_rxbuf_hdr *, const void *, int, int, int); 126 127 static void bwi_restart(void *, int); 128 static void bwi_init_statechg(struct bwi_softc *, int); 129 static void bwi_stop(struct bwi_softc *, int); 130 static void bwi_stop_locked(struct bwi_softc *, int); 131 static int bwi_newbuf(struct bwi_softc *, int, int); 132 static int bwi_encap(struct bwi_softc *, int, struct mbuf *, 133 struct ieee80211_node *); 134 static int bwi_encap_raw(struct bwi_softc *, int, struct mbuf *, 135 struct ieee80211_node *, 136 const struct ieee80211_bpf_params *); 137 138 static void bwi_init_rxdesc_ring32(struct bwi_softc *, uint32_t, 139 bus_addr_t, int, int); 140 static void bwi_reset_rx_ring32(struct bwi_softc *, uint32_t); 141 142 static int bwi_init_tx_ring32(struct bwi_softc *, int); 143 static int bwi_init_rx_ring32(struct bwi_softc *); 144 static int bwi_init_txstats32(struct bwi_softc *); 145 static void bwi_free_tx_ring32(struct bwi_softc *, int); 146 static void bwi_free_rx_ring32(struct bwi_softc *); 147 static void bwi_free_txstats32(struct bwi_softc *); 148 static void bwi_setup_rx_desc32(struct bwi_softc *, int, bus_addr_t, int); 149 static void bwi_setup_tx_desc32(struct bwi_softc *, struct bwi_ring_data *, 150 int, bus_addr_t, int); 151 static int bwi_rxeof32(struct bwi_softc *); 152 static void bwi_start_tx32(struct bwi_softc *, uint32_t, int); 153 static void bwi_txeof_status32(struct bwi_softc *); 154 155 static int bwi_init_tx_ring64(struct bwi_softc *, int); 156 static int bwi_init_rx_ring64(struct bwi_softc *); 157 static int bwi_init_txstats64(struct bwi_softc *); 158 static void bwi_free_tx_ring64(struct bwi_softc *, int); 159 static void bwi_free_rx_ring64(struct bwi_softc *); 160 static void bwi_free_txstats64(struct bwi_softc *); 161 static void bwi_setup_rx_desc64(struct bwi_softc *, int, bus_addr_t, int); 162 static void bwi_setup_tx_desc64(struct bwi_softc *, struct bwi_ring_data *, 163 int, bus_addr_t, int); 164 static int bwi_rxeof64(struct bwi_softc *); 165 static void bwi_start_tx64(struct bwi_softc *, uint32_t, int); 166 static void bwi_txeof_status64(struct bwi_softc *); 167 168 static int bwi_rxeof(struct bwi_softc *, int); 169 static void _bwi_txeof(struct bwi_softc *, uint16_t, int, int); 170 static void bwi_txeof(struct bwi_softc *); 171 static void bwi_txeof_status(struct bwi_softc *, int); 172 static void bwi_enable_intrs(struct bwi_softc *, uint32_t); 173 static void bwi_disable_intrs(struct bwi_softc *, uint32_t); 174 175 static int bwi_dma_alloc(struct bwi_softc *); 176 static void bwi_dma_free(struct bwi_softc *); 177 static int bwi_dma_ring_alloc(struct bwi_softc *, bus_dma_tag_t, 178 struct bwi_ring_data *, bus_size_t, 179 uint32_t); 180 static int bwi_dma_mbuf_create(struct bwi_softc *); 181 static void bwi_dma_mbuf_destroy(struct bwi_softc *, int, int); 182 static int bwi_dma_txstats_alloc(struct bwi_softc *, uint32_t, bus_size_t); 183 static void bwi_dma_txstats_free(struct bwi_softc *); 184 static void bwi_dma_ring_addr(void *, bus_dma_segment_t *, int, int); 185 static void bwi_dma_buf_addr(void *, bus_dma_segment_t *, int, 186 bus_size_t, int); 187 188 static void bwi_power_on(struct bwi_softc *, int); 189 static int bwi_power_off(struct bwi_softc *, int); 190 static int bwi_set_clock_mode(struct bwi_softc *, enum bwi_clock_mode); 191 static int bwi_set_clock_delay(struct bwi_softc *); 192 static void bwi_get_clock_freq(struct bwi_softc *, struct bwi_clock_freq *); 193 static int bwi_get_pwron_delay(struct bwi_softc *sc); 194 static void bwi_set_addr_filter(struct bwi_softc *, uint16_t, 195 const uint8_t *); 196 static void bwi_set_bssid(struct bwi_softc *, const uint8_t *); 197 198 static void bwi_get_card_flags(struct bwi_softc *); 199 static void bwi_get_eaddr(struct bwi_softc *, uint16_t, uint8_t *); 200 201 static int bwi_bus_attach(struct bwi_softc *); 202 static int bwi_bbp_attach(struct bwi_softc *); 203 static int bwi_bbp_power_on(struct bwi_softc *, enum bwi_clock_mode); 204 static void bwi_bbp_power_off(struct bwi_softc *); 205 206 static const char *bwi_regwin_name(const struct bwi_regwin *); 207 static uint32_t bwi_regwin_disable_bits(struct bwi_softc *); 208 static void bwi_regwin_info(struct bwi_softc *, uint16_t *, uint8_t *); 209 static int bwi_regwin_select(struct bwi_softc *, int); 210 211 static void bwi_led_attach(struct bwi_softc *); 212 static void bwi_led_newstate(struct bwi_softc *, enum ieee80211_state); 213 static void bwi_led_event(struct bwi_softc *, int); 214 static void bwi_led_blink_start(struct bwi_softc *, int, int); 215 static void bwi_led_blink_next(void *); 216 static void bwi_led_blink_end(void *); 217 218 static const struct { 219 uint16_t did_min; 220 uint16_t did_max; 221 uint16_t bbp_id; 222 } bwi_bbpid_map[] = { 223 { 0x4301, 0x4301, 0x4301 }, 224 { 0x4305, 0x4307, 0x4307 }, 225 { 0x4402, 0x4403, 0x4402 }, 226 { 0x4610, 0x4615, 0x4610 }, 227 { 0x4710, 0x4715, 0x4710 }, 228 { 0x4720, 0x4725, 0x4309 } 229 }; 230 231 static const struct { 232 uint16_t bbp_id; 233 int nregwin; 234 } bwi_regwin_count[] = { 235 { 0x4301, 5 }, 236 { 0x4306, 6 }, 237 { 0x4307, 5 }, 238 { 0x4310, 8 }, 239 { 0x4401, 3 }, 240 { 0x4402, 3 }, 241 { 0x4610, 9 }, 242 { 0x4704, 9 }, 243 { 0x4710, 9 }, 244 { 0x5365, 7 } 245 }; 246 247 #define CLKSRC(src) \ 248 [BWI_CLKSRC_ ## src] = { \ 249 .freq_min = BWI_CLKSRC_ ##src## _FMIN, \ 250 .freq_max = BWI_CLKSRC_ ##src## _FMAX \ 251 } 252 253 static const struct { 254 u_int freq_min; 255 u_int freq_max; 256 } bwi_clkfreq[BWI_CLKSRC_MAX] = { 257 CLKSRC(LP_OSC), 258 CLKSRC(CS_OSC), 259 CLKSRC(PCI) 260 }; 261 262 #undef CLKSRC 263 264 #define VENDOR_LED_ACT(vendor) \ 265 { \ 266 .vid = PCI_VENDOR_##vendor, \ 267 .led_act = { BWI_VENDOR_LED_ACT_##vendor } \ 268 } 269 270 static const struct { 271 #define PCI_VENDOR_COMPAQ 0x0e11 272 #define PCI_VENDOR_LINKSYS 0x1737 273 uint16_t vid; 274 uint8_t led_act[BWI_LED_MAX]; 275 } bwi_vendor_led_act[] = { 276 VENDOR_LED_ACT(COMPAQ), 277 VENDOR_LED_ACT(LINKSYS) 278 #undef PCI_VENDOR_LINKSYS 279 #undef PCI_VENDOR_COMPAQ 280 }; 281 282 static const uint8_t bwi_default_led_act[BWI_LED_MAX] = 283 { BWI_VENDOR_LED_ACT_DEFAULT }; 284 285 #undef VENDOR_LED_ACT 286 287 static const struct { 288 int on_dur; 289 int off_dur; 290 } bwi_led_duration[109] = { 291 [0] = { 400, 100 }, 292 [2] = { 150, 75 }, 293 [4] = { 90, 45 }, 294 [11] = { 66, 34 }, 295 [12] = { 53, 26 }, 296 [18] = { 42, 21 }, 297 [22] = { 35, 17 }, 298 [24] = { 32, 16 }, 299 [36] = { 21, 10 }, 300 [48] = { 16, 8 }, 301 [72] = { 11, 5 }, 302 [96] = { 9, 4 }, 303 [108] = { 7, 3 } 304 }; 305 306 #ifdef BWI_DEBUG 307 #ifdef BWI_DEBUG_VERBOSE 308 static uint32_t bwi_debug = BWI_DBG_ATTACH | BWI_DBG_INIT | BWI_DBG_TXPOWER; 309 #else 310 static uint32_t bwi_debug; 311 #endif 312 TUNABLE_INT("hw.bwi.debug", (int *)&bwi_debug); 313 #endif /* BWI_DEBUG */ 314 315 static const uint8_t bwi_zero_addr[IEEE80211_ADDR_LEN]; 316 317 uint16_t 318 bwi_read_sprom(struct bwi_softc *sc, uint16_t ofs) 319 { 320 return CSR_READ_2(sc, ofs + BWI_SPROM_START); 321 } 322 323 static __inline void 324 bwi_setup_desc32(struct bwi_softc *sc, struct bwi_desc32 *desc_array, 325 int ndesc, int desc_idx, bus_addr_t paddr, int buf_len, 326 int tx) 327 { 328 struct bwi_desc32 *desc = &desc_array[desc_idx]; 329 uint32_t ctrl, addr, addr_hi, addr_lo; 330 331 addr_lo = __SHIFTOUT(paddr, BWI_DESC32_A_ADDR_MASK); 332 addr_hi = __SHIFTOUT(paddr, BWI_DESC32_A_FUNC_MASK); 333 334 addr = __SHIFTIN(addr_lo, BWI_DESC32_A_ADDR_MASK) | 335 __SHIFTIN(BWI_DESC32_A_FUNC_TXRX, BWI_DESC32_A_FUNC_MASK); 336 337 ctrl = __SHIFTIN(buf_len, BWI_DESC32_C_BUFLEN_MASK) | 338 __SHIFTIN(addr_hi, BWI_DESC32_C_ADDRHI_MASK); 339 if (desc_idx == ndesc - 1) 340 ctrl |= BWI_DESC32_C_EOR; 341 if (tx) { 342 /* XXX */ 343 ctrl |= BWI_DESC32_C_FRAME_START | 344 BWI_DESC32_C_FRAME_END | 345 BWI_DESC32_C_INTR; 346 } 347 348 desc->addr = htole32(addr); 349 desc->ctrl = htole32(ctrl); 350 } 351 352 int 353 bwi_attach(struct bwi_softc *sc) 354 { 355 struct ieee80211com *ic = &sc->sc_ic; 356 device_t dev = sc->sc_dev; 357 struct bwi_mac *mac; 358 struct bwi_phy *phy; 359 int i, error; 360 uint8_t bands; 361 362 BWI_LOCK_INIT(sc); 363 364 /* 365 * Initialize taskq and various tasks 366 */ 367 sc->sc_tq = taskqueue_create("bwi_taskq", M_NOWAIT | M_ZERO, 368 taskqueue_thread_enqueue, &sc->sc_tq); 369 taskqueue_start_threads(&sc->sc_tq, 1, PI_NET, "%s taskq", 370 device_get_nameunit(dev)); 371 TASK_INIT(&sc->sc_restart_task, 0, bwi_restart, sc); 372 callout_init_mtx(&sc->sc_calib_ch, &sc->sc_mtx, 0); 373 mbufq_init(&sc->sc_snd, ifqmaxlen); 374 375 /* 376 * Initialize sysctl variables 377 */ 378 sc->sc_fw_version = BWI_FW_VERSION3; 379 sc->sc_led_idle = (2350 * hz) / 1000; 380 sc->sc_led_blink = 1; 381 sc->sc_txpwr_calib = 1; 382 #ifdef BWI_DEBUG 383 sc->sc_debug = bwi_debug; 384 #endif 385 bwi_power_on(sc, 1); 386 387 error = bwi_bbp_attach(sc); 388 if (error) 389 goto fail; 390 391 error = bwi_bbp_power_on(sc, BWI_CLOCK_MODE_FAST); 392 if (error) 393 goto fail; 394 395 if (BWI_REGWIN_EXIST(&sc->sc_com_regwin)) { 396 error = bwi_set_clock_delay(sc); 397 if (error) 398 goto fail; 399 400 error = bwi_set_clock_mode(sc, BWI_CLOCK_MODE_FAST); 401 if (error) 402 goto fail; 403 404 error = bwi_get_pwron_delay(sc); 405 if (error) 406 goto fail; 407 } 408 409 error = bwi_bus_attach(sc); 410 if (error) 411 goto fail; 412 413 bwi_get_card_flags(sc); 414 415 bwi_led_attach(sc); 416 417 for (i = 0; i < sc->sc_nmac; ++i) { 418 struct bwi_regwin *old; 419 420 mac = &sc->sc_mac[i]; 421 error = bwi_regwin_switch(sc, &mac->mac_regwin, &old); 422 if (error) 423 goto fail; 424 425 error = bwi_mac_lateattach(mac); 426 if (error) 427 goto fail; 428 429 error = bwi_regwin_switch(sc, old, NULL); 430 if (error) 431 goto fail; 432 } 433 434 /* 435 * XXX First MAC is known to exist 436 * TODO2 437 */ 438 mac = &sc->sc_mac[0]; 439 phy = &mac->mac_phy; 440 441 bwi_bbp_power_off(sc); 442 443 error = bwi_dma_alloc(sc); 444 if (error) 445 goto fail; 446 447 error = bwi_mac_fw_alloc(mac); 448 if (error) 449 goto fail; 450 451 callout_init_mtx(&sc->sc_watchdog_timer, &sc->sc_mtx, 0); 452 453 /* 454 * Setup ratesets, phytype, channels and get MAC address 455 */ 456 bands = 0; 457 if (phy->phy_mode == IEEE80211_MODE_11B || 458 phy->phy_mode == IEEE80211_MODE_11G) { 459 setbit(&bands, IEEE80211_MODE_11B); 460 if (phy->phy_mode == IEEE80211_MODE_11B) { 461 ic->ic_phytype = IEEE80211_T_DS; 462 } else { 463 ic->ic_phytype = IEEE80211_T_OFDM; 464 setbit(&bands, IEEE80211_MODE_11G); 465 } 466 467 bwi_get_eaddr(sc, BWI_SPROM_11BG_EADDR, ic->ic_macaddr); 468 if (IEEE80211_IS_MULTICAST(ic->ic_macaddr)) { 469 bwi_get_eaddr(sc, BWI_SPROM_11A_EADDR, ic->ic_macaddr); 470 if (IEEE80211_IS_MULTICAST(ic->ic_macaddr)) { 471 device_printf(dev, 472 "invalid MAC address: %6D\n", 473 ic->ic_macaddr, ":"); 474 } 475 } 476 } else if (phy->phy_mode == IEEE80211_MODE_11A) { 477 /* TODO:11A */ 478 setbit(&bands, IEEE80211_MODE_11A); 479 error = ENXIO; 480 goto fail; 481 } else { 482 panic("unknown phymode %d\n", phy->phy_mode); 483 } 484 485 /* Get locale */ 486 sc->sc_locale = __SHIFTOUT(bwi_read_sprom(sc, BWI_SPROM_CARD_INFO), 487 BWI_SPROM_CARD_INFO_LOCALE); 488 DPRINTF(sc, BWI_DBG_ATTACH, "locale: %d\n", sc->sc_locale); 489 /* XXX use locale */ 490 ieee80211_init_channels(ic, NULL, &bands); 491 492 ic->ic_softc = sc; 493 ic->ic_name = device_get_nameunit(dev); 494 ic->ic_caps = IEEE80211_C_STA | 495 IEEE80211_C_SHSLOT | 496 IEEE80211_C_SHPREAMBLE | 497 IEEE80211_C_WPA | 498 IEEE80211_C_BGSCAN | 499 IEEE80211_C_MONITOR; 500 ic->ic_opmode = IEEE80211_M_STA; 501 ieee80211_ifattach(ic); 502 503 ic->ic_headroom = sizeof(struct bwi_txbuf_hdr); 504 505 /* override default methods */ 506 ic->ic_vap_create = bwi_vap_create; 507 ic->ic_vap_delete = bwi_vap_delete; 508 ic->ic_raw_xmit = bwi_raw_xmit; 509 ic->ic_updateslot = bwi_updateslot; 510 ic->ic_scan_start = bwi_scan_start; 511 ic->ic_scan_end = bwi_scan_end; 512 ic->ic_set_channel = bwi_set_channel; 513 ic->ic_transmit = bwi_transmit; 514 ic->ic_parent = bwi_parent; 515 516 sc->sc_rates = ieee80211_get_ratetable(ic->ic_curchan); 517 518 ieee80211_radiotap_attach(ic, 519 &sc->sc_tx_th.wt_ihdr, sizeof(sc->sc_tx_th), 520 BWI_TX_RADIOTAP_PRESENT, 521 &sc->sc_rx_th.wr_ihdr, sizeof(sc->sc_rx_th), 522 BWI_RX_RADIOTAP_PRESENT); 523 524 /* 525 * Add sysctl nodes 526 */ 527 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 528 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 529 "fw_version", CTLFLAG_RD, &sc->sc_fw_version, 0, 530 "Firmware version"); 531 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 532 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 533 "led_idle", CTLFLAG_RW, &sc->sc_led_idle, 0, 534 "# ticks before LED enters idle state"); 535 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 536 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 537 "led_blink", CTLFLAG_RW, &sc->sc_led_blink, 0, 538 "Allow LED to blink"); 539 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 540 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 541 "txpwr_calib", CTLFLAG_RW, &sc->sc_txpwr_calib, 0, 542 "Enable software TX power calibration"); 543 #ifdef BWI_DEBUG 544 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), 545 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 546 "debug", CTLFLAG_RW, &sc->sc_debug, 0, "Debug flags"); 547 #endif 548 if (bootverbose) 549 ieee80211_announce(ic); 550 551 return (0); 552 fail: 553 BWI_LOCK_DESTROY(sc); 554 return (error); 555 } 556 557 int 558 bwi_detach(struct bwi_softc *sc) 559 { 560 struct ieee80211com *ic = &sc->sc_ic; 561 int i; 562 563 bwi_stop(sc, 1); 564 callout_drain(&sc->sc_led_blink_ch); 565 callout_drain(&sc->sc_calib_ch); 566 callout_drain(&sc->sc_watchdog_timer); 567 ieee80211_ifdetach(ic); 568 569 for (i = 0; i < sc->sc_nmac; ++i) 570 bwi_mac_detach(&sc->sc_mac[i]); 571 bwi_dma_free(sc); 572 taskqueue_free(sc->sc_tq); 573 mbufq_drain(&sc->sc_snd); 574 575 BWI_LOCK_DESTROY(sc); 576 577 return (0); 578 } 579 580 static struct ieee80211vap * 581 bwi_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit, 582 enum ieee80211_opmode opmode, int flags, 583 const uint8_t bssid[IEEE80211_ADDR_LEN], 584 const uint8_t mac[IEEE80211_ADDR_LEN]) 585 { 586 struct bwi_vap *bvp; 587 struct ieee80211vap *vap; 588 589 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */ 590 return NULL; 591 bvp = malloc(sizeof(struct bwi_vap), M_80211_VAP, M_WAITOK | M_ZERO); 592 vap = &bvp->bv_vap; 593 /* enable s/w bmiss handling for sta mode */ 594 ieee80211_vap_setup(ic, vap, name, unit, opmode, 595 flags | IEEE80211_CLONE_NOBEACONS, bssid); 596 597 /* override default methods */ 598 bvp->bv_newstate = vap->iv_newstate; 599 vap->iv_newstate = bwi_newstate; 600 #if 0 601 vap->iv_update_beacon = bwi_beacon_update; 602 #endif 603 ieee80211_ratectl_init(vap); 604 605 /* complete setup */ 606 ieee80211_vap_attach(vap, bwi_media_change, ieee80211_media_status, 607 mac); 608 ic->ic_opmode = opmode; 609 return vap; 610 } 611 612 static void 613 bwi_vap_delete(struct ieee80211vap *vap) 614 { 615 struct bwi_vap *bvp = BWI_VAP(vap); 616 617 ieee80211_ratectl_deinit(vap); 618 ieee80211_vap_detach(vap); 619 free(bvp, M_80211_VAP); 620 } 621 622 void 623 bwi_suspend(struct bwi_softc *sc) 624 { 625 bwi_stop(sc, 1); 626 } 627 628 void 629 bwi_resume(struct bwi_softc *sc) 630 { 631 632 if (sc->sc_ic.ic_nrunning > 0) 633 bwi_init(sc); 634 } 635 636 int 637 bwi_shutdown(struct bwi_softc *sc) 638 { 639 bwi_stop(sc, 1); 640 return 0; 641 } 642 643 static void 644 bwi_power_on(struct bwi_softc *sc, int with_pll) 645 { 646 uint32_t gpio_in, gpio_out, gpio_en; 647 uint16_t status; 648 649 gpio_in = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_IN, 4); 650 if (gpio_in & BWI_PCIM_GPIO_PWR_ON) 651 goto back; 652 653 gpio_out = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, 4); 654 gpio_en = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, 4); 655 656 gpio_out |= BWI_PCIM_GPIO_PWR_ON; 657 gpio_en |= BWI_PCIM_GPIO_PWR_ON; 658 if (with_pll) { 659 /* Turn off PLL first */ 660 gpio_out |= BWI_PCIM_GPIO_PLL_PWR_OFF; 661 gpio_en |= BWI_PCIM_GPIO_PLL_PWR_OFF; 662 } 663 664 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, gpio_out, 4); 665 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, gpio_en, 4); 666 DELAY(1000); 667 668 if (with_pll) { 669 /* Turn on PLL */ 670 gpio_out &= ~BWI_PCIM_GPIO_PLL_PWR_OFF; 671 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, gpio_out, 4); 672 DELAY(5000); 673 } 674 675 back: 676 /* Clear "Signaled Target Abort" */ 677 status = pci_read_config(sc->sc_dev, PCIR_STATUS, 2); 678 status &= ~PCIM_STATUS_STABORT; 679 pci_write_config(sc->sc_dev, PCIR_STATUS, status, 2); 680 } 681 682 static int 683 bwi_power_off(struct bwi_softc *sc, int with_pll) 684 { 685 uint32_t gpio_out, gpio_en; 686 687 pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_IN, 4); /* dummy read */ 688 gpio_out = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, 4); 689 gpio_en = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, 4); 690 691 gpio_out &= ~BWI_PCIM_GPIO_PWR_ON; 692 gpio_en |= BWI_PCIM_GPIO_PWR_ON; 693 if (with_pll) { 694 gpio_out |= BWI_PCIM_GPIO_PLL_PWR_OFF; 695 gpio_en |= BWI_PCIM_GPIO_PLL_PWR_OFF; 696 } 697 698 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, gpio_out, 4); 699 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, gpio_en, 4); 700 return 0; 701 } 702 703 int 704 bwi_regwin_switch(struct bwi_softc *sc, struct bwi_regwin *rw, 705 struct bwi_regwin **old_rw) 706 { 707 int error; 708 709 if (old_rw != NULL) 710 *old_rw = NULL; 711 712 if (!BWI_REGWIN_EXIST(rw)) 713 return EINVAL; 714 715 if (sc->sc_cur_regwin != rw) { 716 error = bwi_regwin_select(sc, rw->rw_id); 717 if (error) { 718 device_printf(sc->sc_dev, "can't select regwin %d\n", 719 rw->rw_id); 720 return error; 721 } 722 } 723 724 if (old_rw != NULL) 725 *old_rw = sc->sc_cur_regwin; 726 sc->sc_cur_regwin = rw; 727 return 0; 728 } 729 730 static int 731 bwi_regwin_select(struct bwi_softc *sc, int id) 732 { 733 uint32_t win = BWI_PCIM_REGWIN(id); 734 int i; 735 736 #define RETRY_MAX 50 737 for (i = 0; i < RETRY_MAX; ++i) { 738 pci_write_config(sc->sc_dev, BWI_PCIR_SEL_REGWIN, win, 4); 739 if (pci_read_config(sc->sc_dev, BWI_PCIR_SEL_REGWIN, 4) == win) 740 return 0; 741 DELAY(10); 742 } 743 #undef RETRY_MAX 744 745 return ENXIO; 746 } 747 748 static void 749 bwi_regwin_info(struct bwi_softc *sc, uint16_t *type, uint8_t *rev) 750 { 751 uint32_t val; 752 753 val = CSR_READ_4(sc, BWI_ID_HI); 754 *type = BWI_ID_HI_REGWIN_TYPE(val); 755 *rev = BWI_ID_HI_REGWIN_REV(val); 756 757 DPRINTF(sc, BWI_DBG_ATTACH, "regwin: type 0x%03x, rev %d, " 758 "vendor 0x%04x\n", *type, *rev, 759 __SHIFTOUT(val, BWI_ID_HI_REGWIN_VENDOR_MASK)); 760 } 761 762 static int 763 bwi_bbp_attach(struct bwi_softc *sc) 764 { 765 uint16_t bbp_id, rw_type; 766 uint8_t rw_rev; 767 uint32_t info; 768 int error, nregwin, i; 769 770 /* 771 * Get 0th regwin information 772 * NOTE: 0th regwin should exist 773 */ 774 error = bwi_regwin_select(sc, 0); 775 if (error) { 776 device_printf(sc->sc_dev, "can't select regwin 0\n"); 777 return error; 778 } 779 bwi_regwin_info(sc, &rw_type, &rw_rev); 780 781 /* 782 * Find out BBP id 783 */ 784 bbp_id = 0; 785 info = 0; 786 if (rw_type == BWI_REGWIN_T_COM) { 787 info = CSR_READ_4(sc, BWI_INFO); 788 bbp_id = __SHIFTOUT(info, BWI_INFO_BBPID_MASK); 789 790 BWI_CREATE_REGWIN(&sc->sc_com_regwin, 0, rw_type, rw_rev); 791 792 sc->sc_cap = CSR_READ_4(sc, BWI_CAPABILITY); 793 } else { 794 for (i = 0; i < nitems(bwi_bbpid_map); ++i) { 795 if (sc->sc_pci_did >= bwi_bbpid_map[i].did_min && 796 sc->sc_pci_did <= bwi_bbpid_map[i].did_max) { 797 bbp_id = bwi_bbpid_map[i].bbp_id; 798 break; 799 } 800 } 801 if (bbp_id == 0) { 802 device_printf(sc->sc_dev, "no BBP id for device id " 803 "0x%04x\n", sc->sc_pci_did); 804 return ENXIO; 805 } 806 807 info = __SHIFTIN(sc->sc_pci_revid, BWI_INFO_BBPREV_MASK) | 808 __SHIFTIN(0, BWI_INFO_BBPPKG_MASK); 809 } 810 811 /* 812 * Find out number of regwins 813 */ 814 nregwin = 0; 815 if (rw_type == BWI_REGWIN_T_COM && rw_rev >= 4) { 816 nregwin = __SHIFTOUT(info, BWI_INFO_NREGWIN_MASK); 817 } else { 818 for (i = 0; i < nitems(bwi_regwin_count); ++i) { 819 if (bwi_regwin_count[i].bbp_id == bbp_id) { 820 nregwin = bwi_regwin_count[i].nregwin; 821 break; 822 } 823 } 824 if (nregwin == 0) { 825 device_printf(sc->sc_dev, "no number of win for " 826 "BBP id 0x%04x\n", bbp_id); 827 return ENXIO; 828 } 829 } 830 831 /* Record BBP id/rev for later using */ 832 sc->sc_bbp_id = bbp_id; 833 sc->sc_bbp_rev = __SHIFTOUT(info, BWI_INFO_BBPREV_MASK); 834 sc->sc_bbp_pkg = __SHIFTOUT(info, BWI_INFO_BBPPKG_MASK); 835 device_printf(sc->sc_dev, "BBP: id 0x%04x, rev 0x%x, pkg %d\n", 836 sc->sc_bbp_id, sc->sc_bbp_rev, sc->sc_bbp_pkg); 837 838 DPRINTF(sc, BWI_DBG_ATTACH, "nregwin %d, cap 0x%08x\n", 839 nregwin, sc->sc_cap); 840 841 /* 842 * Create rest of the regwins 843 */ 844 845 /* Don't re-create common regwin, if it is already created */ 846 i = BWI_REGWIN_EXIST(&sc->sc_com_regwin) ? 1 : 0; 847 848 for (; i < nregwin; ++i) { 849 /* 850 * Get regwin information 851 */ 852 error = bwi_regwin_select(sc, i); 853 if (error) { 854 device_printf(sc->sc_dev, 855 "can't select regwin %d\n", i); 856 return error; 857 } 858 bwi_regwin_info(sc, &rw_type, &rw_rev); 859 860 /* 861 * Try attach: 862 * 1) Bus (PCI/PCIE) regwin 863 * 2) MAC regwin 864 * Ignore rest types of regwin 865 */ 866 if (rw_type == BWI_REGWIN_T_BUSPCI || 867 rw_type == BWI_REGWIN_T_BUSPCIE) { 868 if (BWI_REGWIN_EXIST(&sc->sc_bus_regwin)) { 869 device_printf(sc->sc_dev, 870 "bus regwin already exists\n"); 871 } else { 872 BWI_CREATE_REGWIN(&sc->sc_bus_regwin, i, 873 rw_type, rw_rev); 874 } 875 } else if (rw_type == BWI_REGWIN_T_MAC) { 876 /* XXX ignore return value */ 877 bwi_mac_attach(sc, i, rw_rev); 878 } 879 } 880 881 /* At least one MAC shold exist */ 882 if (!BWI_REGWIN_EXIST(&sc->sc_mac[0].mac_regwin)) { 883 device_printf(sc->sc_dev, "no MAC was found\n"); 884 return ENXIO; 885 } 886 KASSERT(sc->sc_nmac > 0, ("no mac's")); 887 888 /* Bus regwin must exist */ 889 if (!BWI_REGWIN_EXIST(&sc->sc_bus_regwin)) { 890 device_printf(sc->sc_dev, "no bus regwin was found\n"); 891 return ENXIO; 892 } 893 894 /* Start with first MAC */ 895 error = bwi_regwin_switch(sc, &sc->sc_mac[0].mac_regwin, NULL); 896 if (error) 897 return error; 898 899 return 0; 900 } 901 902 int 903 bwi_bus_init(struct bwi_softc *sc, struct bwi_mac *mac) 904 { 905 struct bwi_regwin *old, *bus; 906 uint32_t val; 907 int error; 908 909 bus = &sc->sc_bus_regwin; 910 KASSERT(sc->sc_cur_regwin == &mac->mac_regwin, ("not cur regwin")); 911 912 /* 913 * Tell bus to generate requested interrupts 914 */ 915 if (bus->rw_rev < 6 && bus->rw_type == BWI_REGWIN_T_BUSPCI) { 916 /* 917 * NOTE: Read BWI_FLAGS from MAC regwin 918 */ 919 val = CSR_READ_4(sc, BWI_FLAGS); 920 921 error = bwi_regwin_switch(sc, bus, &old); 922 if (error) 923 return error; 924 925 CSR_SETBITS_4(sc, BWI_INTRVEC, (val & BWI_FLAGS_INTR_MASK)); 926 } else { 927 uint32_t mac_mask; 928 929 mac_mask = 1 << mac->mac_id; 930 931 error = bwi_regwin_switch(sc, bus, &old); 932 if (error) 933 return error; 934 935 val = pci_read_config(sc->sc_dev, BWI_PCIR_INTCTL, 4); 936 val |= mac_mask << 8; 937 pci_write_config(sc->sc_dev, BWI_PCIR_INTCTL, val, 4); 938 } 939 940 if (sc->sc_flags & BWI_F_BUS_INITED) 941 goto back; 942 943 if (bus->rw_type == BWI_REGWIN_T_BUSPCI) { 944 /* 945 * Enable prefetch and burst 946 */ 947 CSR_SETBITS_4(sc, BWI_BUS_CONFIG, 948 BWI_BUS_CONFIG_PREFETCH | BWI_BUS_CONFIG_BURST); 949 950 if (bus->rw_rev < 5) { 951 struct bwi_regwin *com = &sc->sc_com_regwin; 952 953 /* 954 * Configure timeouts for bus operation 955 */ 956 957 /* 958 * Set service timeout and request timeout 959 */ 960 CSR_SETBITS_4(sc, BWI_CONF_LO, 961 __SHIFTIN(BWI_CONF_LO_SERVTO, BWI_CONF_LO_SERVTO_MASK) | 962 __SHIFTIN(BWI_CONF_LO_REQTO, BWI_CONF_LO_REQTO_MASK)); 963 964 /* 965 * If there is common regwin, we switch to that regwin 966 * and switch back to bus regwin once we have done. 967 */ 968 if (BWI_REGWIN_EXIST(com)) { 969 error = bwi_regwin_switch(sc, com, NULL); 970 if (error) 971 return error; 972 } 973 974 /* Let bus know what we have changed */ 975 CSR_WRITE_4(sc, BWI_BUS_ADDR, BWI_BUS_ADDR_MAGIC); 976 CSR_READ_4(sc, BWI_BUS_ADDR); /* Flush */ 977 CSR_WRITE_4(sc, BWI_BUS_DATA, 0); 978 CSR_READ_4(sc, BWI_BUS_DATA); /* Flush */ 979 980 if (BWI_REGWIN_EXIST(com)) { 981 error = bwi_regwin_switch(sc, bus, NULL); 982 if (error) 983 return error; 984 } 985 } else if (bus->rw_rev >= 11) { 986 /* 987 * Enable memory read multiple 988 */ 989 CSR_SETBITS_4(sc, BWI_BUS_CONFIG, BWI_BUS_CONFIG_MRM); 990 } 991 } else { 992 /* TODO:PCIE */ 993 } 994 995 sc->sc_flags |= BWI_F_BUS_INITED; 996 back: 997 return bwi_regwin_switch(sc, old, NULL); 998 } 999 1000 static void 1001 bwi_get_card_flags(struct bwi_softc *sc) 1002 { 1003 #define PCI_VENDOR_APPLE 0x106b 1004 #define PCI_VENDOR_DELL 0x1028 1005 sc->sc_card_flags = bwi_read_sprom(sc, BWI_SPROM_CARD_FLAGS); 1006 if (sc->sc_card_flags == 0xffff) 1007 sc->sc_card_flags = 0; 1008 1009 if (sc->sc_pci_subvid == PCI_VENDOR_DELL && 1010 sc->sc_bbp_id == BWI_BBPID_BCM4301 && 1011 sc->sc_pci_revid == 0x74) 1012 sc->sc_card_flags |= BWI_CARD_F_BT_COEXIST; 1013 1014 if (sc->sc_pci_subvid == PCI_VENDOR_APPLE && 1015 sc->sc_pci_subdid == 0x4e && /* XXX */ 1016 sc->sc_pci_revid > 0x40) 1017 sc->sc_card_flags |= BWI_CARD_F_PA_GPIO9; 1018 1019 DPRINTF(sc, BWI_DBG_ATTACH, "card flags 0x%04x\n", sc->sc_card_flags); 1020 #undef PCI_VENDOR_DELL 1021 #undef PCI_VENDOR_APPLE 1022 } 1023 1024 static void 1025 bwi_get_eaddr(struct bwi_softc *sc, uint16_t eaddr_ofs, uint8_t *eaddr) 1026 { 1027 int i; 1028 1029 for (i = 0; i < 3; ++i) { 1030 *((uint16_t *)eaddr + i) = 1031 htobe16(bwi_read_sprom(sc, eaddr_ofs + 2 * i)); 1032 } 1033 } 1034 1035 static void 1036 bwi_get_clock_freq(struct bwi_softc *sc, struct bwi_clock_freq *freq) 1037 { 1038 struct bwi_regwin *com; 1039 uint32_t val; 1040 u_int div; 1041 int src; 1042 1043 bzero(freq, sizeof(*freq)); 1044 com = &sc->sc_com_regwin; 1045 1046 KASSERT(BWI_REGWIN_EXIST(com), ("regwin does not exist")); 1047 KASSERT(sc->sc_cur_regwin == com, ("wrong regwin")); 1048 KASSERT(sc->sc_cap & BWI_CAP_CLKMODE, ("wrong clock mode")); 1049 1050 /* 1051 * Calculate clock frequency 1052 */ 1053 src = -1; 1054 div = 0; 1055 if (com->rw_rev < 6) { 1056 val = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, 4); 1057 if (val & BWI_PCIM_GPIO_OUT_CLKSRC) { 1058 src = BWI_CLKSRC_PCI; 1059 div = 64; 1060 } else { 1061 src = BWI_CLKSRC_CS_OSC; 1062 div = 32; 1063 } 1064 } else if (com->rw_rev < 10) { 1065 val = CSR_READ_4(sc, BWI_CLOCK_CTRL); 1066 1067 src = __SHIFTOUT(val, BWI_CLOCK_CTRL_CLKSRC); 1068 if (src == BWI_CLKSRC_LP_OSC) { 1069 div = 1; 1070 } else { 1071 div = (__SHIFTOUT(val, BWI_CLOCK_CTRL_FDIV) + 1) << 2; 1072 1073 /* Unknown source */ 1074 if (src >= BWI_CLKSRC_MAX) 1075 src = BWI_CLKSRC_CS_OSC; 1076 } 1077 } else { 1078 val = CSR_READ_4(sc, BWI_CLOCK_INFO); 1079 1080 src = BWI_CLKSRC_CS_OSC; 1081 div = (__SHIFTOUT(val, BWI_CLOCK_INFO_FDIV) + 1) << 2; 1082 } 1083 1084 KASSERT(src >= 0 && src < BWI_CLKSRC_MAX, ("bad src %d", src)); 1085 KASSERT(div != 0, ("div zero")); 1086 1087 DPRINTF(sc, BWI_DBG_ATTACH, "clksrc %s\n", 1088 src == BWI_CLKSRC_PCI ? "PCI" : 1089 (src == BWI_CLKSRC_LP_OSC ? "LP_OSC" : "CS_OSC")); 1090 1091 freq->clkfreq_min = bwi_clkfreq[src].freq_min / div; 1092 freq->clkfreq_max = bwi_clkfreq[src].freq_max / div; 1093 1094 DPRINTF(sc, BWI_DBG_ATTACH, "clkfreq min %u, max %u\n", 1095 freq->clkfreq_min, freq->clkfreq_max); 1096 } 1097 1098 static int 1099 bwi_set_clock_mode(struct bwi_softc *sc, enum bwi_clock_mode clk_mode) 1100 { 1101 struct bwi_regwin *old, *com; 1102 uint32_t clk_ctrl, clk_src; 1103 int error, pwr_off = 0; 1104 1105 com = &sc->sc_com_regwin; 1106 if (!BWI_REGWIN_EXIST(com)) 1107 return 0; 1108 1109 if (com->rw_rev >= 10 || com->rw_rev < 6) 1110 return 0; 1111 1112 /* 1113 * For common regwin whose rev is [6, 10), the chip 1114 * must be capable to change clock mode. 1115 */ 1116 if ((sc->sc_cap & BWI_CAP_CLKMODE) == 0) 1117 return 0; 1118 1119 error = bwi_regwin_switch(sc, com, &old); 1120 if (error) 1121 return error; 1122 1123 if (clk_mode == BWI_CLOCK_MODE_FAST) 1124 bwi_power_on(sc, 0); /* Don't turn on PLL */ 1125 1126 clk_ctrl = CSR_READ_4(sc, BWI_CLOCK_CTRL); 1127 clk_src = __SHIFTOUT(clk_ctrl, BWI_CLOCK_CTRL_CLKSRC); 1128 1129 switch (clk_mode) { 1130 case BWI_CLOCK_MODE_FAST: 1131 clk_ctrl &= ~BWI_CLOCK_CTRL_SLOW; 1132 clk_ctrl |= BWI_CLOCK_CTRL_IGNPLL; 1133 break; 1134 case BWI_CLOCK_MODE_SLOW: 1135 clk_ctrl |= BWI_CLOCK_CTRL_SLOW; 1136 break; 1137 case BWI_CLOCK_MODE_DYN: 1138 clk_ctrl &= ~(BWI_CLOCK_CTRL_SLOW | 1139 BWI_CLOCK_CTRL_IGNPLL | 1140 BWI_CLOCK_CTRL_NODYN); 1141 if (clk_src != BWI_CLKSRC_CS_OSC) { 1142 clk_ctrl |= BWI_CLOCK_CTRL_NODYN; 1143 pwr_off = 1; 1144 } 1145 break; 1146 } 1147 CSR_WRITE_4(sc, BWI_CLOCK_CTRL, clk_ctrl); 1148 1149 if (pwr_off) 1150 bwi_power_off(sc, 0); /* Leave PLL as it is */ 1151 1152 return bwi_regwin_switch(sc, old, NULL); 1153 } 1154 1155 static int 1156 bwi_set_clock_delay(struct bwi_softc *sc) 1157 { 1158 struct bwi_regwin *old, *com; 1159 int error; 1160 1161 com = &sc->sc_com_regwin; 1162 if (!BWI_REGWIN_EXIST(com)) 1163 return 0; 1164 1165 error = bwi_regwin_switch(sc, com, &old); 1166 if (error) 1167 return error; 1168 1169 if (sc->sc_bbp_id == BWI_BBPID_BCM4321) { 1170 if (sc->sc_bbp_rev == 0) 1171 CSR_WRITE_4(sc, BWI_CONTROL, BWI_CONTROL_MAGIC0); 1172 else if (sc->sc_bbp_rev == 1) 1173 CSR_WRITE_4(sc, BWI_CONTROL, BWI_CONTROL_MAGIC1); 1174 } 1175 1176 if (sc->sc_cap & BWI_CAP_CLKMODE) { 1177 if (com->rw_rev >= 10) { 1178 CSR_FILT_SETBITS_4(sc, BWI_CLOCK_INFO, 0xffff, 0x40000); 1179 } else { 1180 struct bwi_clock_freq freq; 1181 1182 bwi_get_clock_freq(sc, &freq); 1183 CSR_WRITE_4(sc, BWI_PLL_ON_DELAY, 1184 howmany(freq.clkfreq_max * 150, 1000000)); 1185 CSR_WRITE_4(sc, BWI_FREQ_SEL_DELAY, 1186 howmany(freq.clkfreq_max * 15, 1000000)); 1187 } 1188 } 1189 1190 return bwi_regwin_switch(sc, old, NULL); 1191 } 1192 1193 static void 1194 bwi_init(struct bwi_softc *sc) 1195 { 1196 struct ieee80211com *ic = &sc->sc_ic; 1197 1198 BWI_LOCK(sc); 1199 bwi_init_statechg(sc, 1); 1200 BWI_UNLOCK(sc); 1201 1202 if (sc->sc_flags & BWI_F_RUNNING) 1203 ieee80211_start_all(ic); /* start all vap's */ 1204 } 1205 1206 static void 1207 bwi_init_statechg(struct bwi_softc *sc, int statechg) 1208 { 1209 struct bwi_mac *mac; 1210 int error; 1211 1212 BWI_ASSERT_LOCKED(sc); 1213 1214 bwi_stop_locked(sc, statechg); 1215 1216 bwi_bbp_power_on(sc, BWI_CLOCK_MODE_FAST); 1217 1218 /* TODO: 2 MAC */ 1219 1220 mac = &sc->sc_mac[0]; 1221 error = bwi_regwin_switch(sc, &mac->mac_regwin, NULL); 1222 if (error) { 1223 device_printf(sc->sc_dev, "%s: error %d on regwin switch\n", 1224 __func__, error); 1225 goto bad; 1226 } 1227 error = bwi_mac_init(mac); 1228 if (error) { 1229 device_printf(sc->sc_dev, "%s: error %d on MAC init\n", 1230 __func__, error); 1231 goto bad; 1232 } 1233 1234 bwi_bbp_power_on(sc, BWI_CLOCK_MODE_DYN); 1235 1236 bwi_set_bssid(sc, bwi_zero_addr); /* Clear BSSID */ 1237 bwi_set_addr_filter(sc, BWI_ADDR_FILTER_MYADDR, sc->sc_ic.ic_macaddr); 1238 1239 bwi_mac_reset_hwkeys(mac); 1240 1241 if ((mac->mac_flags & BWI_MAC_F_HAS_TXSTATS) == 0) { 1242 int i; 1243 1244 #define NRETRY 1000 1245 /* 1246 * Drain any possible pending TX status 1247 */ 1248 for (i = 0; i < NRETRY; ++i) { 1249 if ((CSR_READ_4(sc, BWI_TXSTATUS0) & 1250 BWI_TXSTATUS0_VALID) == 0) 1251 break; 1252 CSR_READ_4(sc, BWI_TXSTATUS1); 1253 } 1254 if (i == NRETRY) 1255 device_printf(sc->sc_dev, 1256 "%s: can't drain TX status\n", __func__); 1257 #undef NRETRY 1258 } 1259 1260 if (mac->mac_phy.phy_mode == IEEE80211_MODE_11G) 1261 bwi_mac_updateslot(mac, 1); 1262 1263 /* Start MAC */ 1264 error = bwi_mac_start(mac); 1265 if (error) { 1266 device_printf(sc->sc_dev, "%s: error %d starting MAC\n", 1267 __func__, error); 1268 goto bad; 1269 } 1270 1271 /* Clear stop flag before enabling interrupt */ 1272 sc->sc_flags &= ~BWI_F_STOP; 1273 sc->sc_flags |= BWI_F_RUNNING; 1274 callout_reset(&sc->sc_watchdog_timer, hz, bwi_watchdog, sc); 1275 1276 /* Enable intrs */ 1277 bwi_enable_intrs(sc, BWI_INIT_INTRS); 1278 return; 1279 bad: 1280 bwi_stop_locked(sc, 1); 1281 } 1282 1283 static void 1284 bwi_parent(struct ieee80211com *ic) 1285 { 1286 struct bwi_softc *sc = ic->ic_softc; 1287 int startall = 0; 1288 1289 BWI_LOCK(sc); 1290 if (ic->ic_nrunning > 0) { 1291 struct bwi_mac *mac; 1292 int promisc = -1; 1293 1294 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 1295 ("current regwin type %d", 1296 sc->sc_cur_regwin->rw_type)); 1297 mac = (struct bwi_mac *)sc->sc_cur_regwin; 1298 1299 if (ic->ic_promisc > 0 && (sc->sc_flags & BWI_F_PROMISC) == 0) { 1300 promisc = 1; 1301 sc->sc_flags |= BWI_F_PROMISC; 1302 } else if (ic->ic_promisc == 0 && 1303 (sc->sc_flags & BWI_F_PROMISC) != 0) { 1304 promisc = 0; 1305 sc->sc_flags &= ~BWI_F_PROMISC; 1306 } 1307 1308 if (promisc >= 0) 1309 bwi_mac_set_promisc(mac, promisc); 1310 } 1311 if (ic->ic_nrunning > 0) { 1312 if ((sc->sc_flags & BWI_F_RUNNING) == 0) { 1313 bwi_init_statechg(sc, 1); 1314 startall = 1; 1315 } 1316 } else if (sc->sc_flags & BWI_F_RUNNING) 1317 bwi_stop_locked(sc, 1); 1318 BWI_UNLOCK(sc); 1319 if (startall) 1320 ieee80211_start_all(ic); 1321 } 1322 1323 static int 1324 bwi_transmit(struct ieee80211com *ic, struct mbuf *m) 1325 { 1326 struct bwi_softc *sc = ic->ic_softc; 1327 int error; 1328 1329 BWI_LOCK(sc); 1330 if ((sc->sc_flags & BWI_F_RUNNING) == 0) { 1331 BWI_UNLOCK(sc); 1332 return (ENXIO); 1333 } 1334 error = mbufq_enqueue(&sc->sc_snd, m); 1335 if (error) { 1336 BWI_UNLOCK(sc); 1337 return (error); 1338 } 1339 bwi_start_locked(sc); 1340 BWI_UNLOCK(sc); 1341 return (0); 1342 } 1343 1344 static void 1345 bwi_start_locked(struct bwi_softc *sc) 1346 { 1347 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING]; 1348 struct ieee80211_frame *wh; 1349 struct ieee80211_node *ni; 1350 struct mbuf *m; 1351 int trans, idx; 1352 1353 BWI_ASSERT_LOCKED(sc); 1354 1355 trans = 0; 1356 idx = tbd->tbd_idx; 1357 1358 while (tbd->tbd_buf[idx].tb_mbuf == NULL && 1359 tbd->tbd_used + BWI_TX_NSPRDESC < BWI_TX_NDESC && 1360 (m = mbufq_dequeue(&sc->sc_snd)) != NULL) { 1361 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif; 1362 wh = mtod(m, struct ieee80211_frame *); 1363 if ((wh->i_fc[1] & IEEE80211_FC1_PROTECTED) != 0 && 1364 ieee80211_crypto_encap(ni, m) == NULL) { 1365 if_inc_counter(ni->ni_vap->iv_ifp, 1366 IFCOUNTER_OERRORS, 1); 1367 ieee80211_free_node(ni); 1368 m_freem(m); 1369 continue; 1370 } 1371 if (bwi_encap(sc, idx, m, ni) != 0) { 1372 /* 'm' is freed in bwi_encap() if we reach here */ 1373 if (ni != NULL) { 1374 if_inc_counter(ni->ni_vap->iv_ifp, 1375 IFCOUNTER_OERRORS, 1); 1376 ieee80211_free_node(ni); 1377 } else 1378 counter_u64_add(sc->sc_ic.ic_oerrors, 1); 1379 continue; 1380 } 1381 trans = 1; 1382 tbd->tbd_used++; 1383 idx = (idx + 1) % BWI_TX_NDESC; 1384 } 1385 1386 tbd->tbd_idx = idx; 1387 if (trans) 1388 sc->sc_tx_timer = 5; 1389 } 1390 1391 static int 1392 bwi_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 1393 const struct ieee80211_bpf_params *params) 1394 { 1395 struct ieee80211com *ic = ni->ni_ic; 1396 struct bwi_softc *sc = ic->ic_softc; 1397 /* XXX wme? */ 1398 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING]; 1399 int idx, error; 1400 1401 if ((sc->sc_flags & BWI_F_RUNNING) == 0) { 1402 ieee80211_free_node(ni); 1403 m_freem(m); 1404 return ENETDOWN; 1405 } 1406 1407 BWI_LOCK(sc); 1408 idx = tbd->tbd_idx; 1409 KASSERT(tbd->tbd_buf[idx].tb_mbuf == NULL, ("slot %d not empty", idx)); 1410 if (params == NULL) { 1411 /* 1412 * Legacy path; interpret frame contents to decide 1413 * precisely how to send the frame. 1414 */ 1415 error = bwi_encap(sc, idx, m, ni); 1416 } else { 1417 /* 1418 * Caller supplied explicit parameters to use in 1419 * sending the frame. 1420 */ 1421 error = bwi_encap_raw(sc, idx, m, ni, params); 1422 } 1423 if (error == 0) { 1424 tbd->tbd_used++; 1425 tbd->tbd_idx = (idx + 1) % BWI_TX_NDESC; 1426 sc->sc_tx_timer = 5; 1427 } else 1428 /* NB: m is reclaimed on encap failure */ 1429 ieee80211_free_node(ni); 1430 BWI_UNLOCK(sc); 1431 return error; 1432 } 1433 1434 static void 1435 bwi_watchdog(void *arg) 1436 { 1437 struct bwi_softc *sc; 1438 1439 sc = arg; 1440 BWI_ASSERT_LOCKED(sc); 1441 if (sc->sc_tx_timer != 0 && --sc->sc_tx_timer == 0) { 1442 device_printf(sc->sc_dev, "watchdog timeout\n"); 1443 counter_u64_add(sc->sc_ic.ic_oerrors, 1); 1444 taskqueue_enqueue(sc->sc_tq, &sc->sc_restart_task); 1445 } 1446 callout_reset(&sc->sc_watchdog_timer, hz, bwi_watchdog, sc); 1447 } 1448 1449 static void 1450 bwi_stop(struct bwi_softc *sc, int statechg) 1451 { 1452 BWI_LOCK(sc); 1453 bwi_stop_locked(sc, statechg); 1454 BWI_UNLOCK(sc); 1455 } 1456 1457 static void 1458 bwi_stop_locked(struct bwi_softc *sc, int statechg) 1459 { 1460 struct bwi_mac *mac; 1461 int i, error, pwr_off = 0; 1462 1463 BWI_ASSERT_LOCKED(sc); 1464 1465 callout_stop(&sc->sc_calib_ch); 1466 callout_stop(&sc->sc_led_blink_ch); 1467 sc->sc_led_blinking = 0; 1468 sc->sc_flags |= BWI_F_STOP; 1469 1470 if (sc->sc_flags & BWI_F_RUNNING) { 1471 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 1472 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 1473 mac = (struct bwi_mac *)sc->sc_cur_regwin; 1474 1475 bwi_disable_intrs(sc, BWI_ALL_INTRS); 1476 CSR_READ_4(sc, BWI_MAC_INTR_MASK); 1477 bwi_mac_stop(mac); 1478 } 1479 1480 for (i = 0; i < sc->sc_nmac; ++i) { 1481 struct bwi_regwin *old_rw; 1482 1483 mac = &sc->sc_mac[i]; 1484 if ((mac->mac_flags & BWI_MAC_F_INITED) == 0) 1485 continue; 1486 1487 error = bwi_regwin_switch(sc, &mac->mac_regwin, &old_rw); 1488 if (error) 1489 continue; 1490 1491 bwi_mac_shutdown(mac); 1492 pwr_off = 1; 1493 1494 bwi_regwin_switch(sc, old_rw, NULL); 1495 } 1496 1497 if (pwr_off) 1498 bwi_bbp_power_off(sc); 1499 1500 sc->sc_tx_timer = 0; 1501 callout_stop(&sc->sc_watchdog_timer); 1502 sc->sc_flags &= ~BWI_F_RUNNING; 1503 } 1504 1505 void 1506 bwi_intr(void *xsc) 1507 { 1508 struct bwi_softc *sc = xsc; 1509 struct bwi_mac *mac; 1510 uint32_t intr_status; 1511 uint32_t txrx_intr_status[BWI_TXRX_NRING]; 1512 int i, txrx_error, tx = 0, rx_data = -1; 1513 1514 BWI_LOCK(sc); 1515 1516 if ((sc->sc_flags & BWI_F_RUNNING) == 0 || 1517 (sc->sc_flags & BWI_F_STOP)) { 1518 BWI_UNLOCK(sc); 1519 return; 1520 } 1521 /* 1522 * Get interrupt status 1523 */ 1524 intr_status = CSR_READ_4(sc, BWI_MAC_INTR_STATUS); 1525 if (intr_status == 0xffffffff) { /* Not for us */ 1526 BWI_UNLOCK(sc); 1527 return; 1528 } 1529 1530 DPRINTF(sc, BWI_DBG_INTR, "intr status 0x%08x\n", intr_status); 1531 1532 intr_status &= CSR_READ_4(sc, BWI_MAC_INTR_MASK); 1533 if (intr_status == 0) { /* Nothing is interesting */ 1534 BWI_UNLOCK(sc); 1535 return; 1536 } 1537 1538 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 1539 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 1540 mac = (struct bwi_mac *)sc->sc_cur_regwin; 1541 1542 txrx_error = 0; 1543 DPRINTF(sc, BWI_DBG_INTR, "%s\n", "TX/RX intr"); 1544 for (i = 0; i < BWI_TXRX_NRING; ++i) { 1545 uint32_t mask; 1546 1547 if (BWI_TXRX_IS_RX(i)) 1548 mask = BWI_TXRX_RX_INTRS; 1549 else 1550 mask = BWI_TXRX_TX_INTRS; 1551 1552 txrx_intr_status[i] = 1553 CSR_READ_4(sc, BWI_TXRX_INTR_STATUS(i)) & mask; 1554 1555 _DPRINTF(sc, BWI_DBG_INTR, ", %d 0x%08x", 1556 i, txrx_intr_status[i]); 1557 1558 if (txrx_intr_status[i] & BWI_TXRX_INTR_ERROR) { 1559 device_printf(sc->sc_dev, 1560 "%s: intr fatal TX/RX (%d) error 0x%08x\n", 1561 __func__, i, txrx_intr_status[i]); 1562 txrx_error = 1; 1563 } 1564 } 1565 _DPRINTF(sc, BWI_DBG_INTR, "%s\n", ""); 1566 1567 /* 1568 * Acknowledge interrupt 1569 */ 1570 CSR_WRITE_4(sc, BWI_MAC_INTR_STATUS, intr_status); 1571 1572 for (i = 0; i < BWI_TXRX_NRING; ++i) 1573 CSR_WRITE_4(sc, BWI_TXRX_INTR_STATUS(i), txrx_intr_status[i]); 1574 1575 /* Disable all interrupts */ 1576 bwi_disable_intrs(sc, BWI_ALL_INTRS); 1577 1578 /* 1579 * http://bcm-specs.sipsolutions.net/Interrupts 1580 * Says for this bit (0x800): 1581 * "Fatal Error 1582 * 1583 * We got this one while testing things when by accident the 1584 * template ram wasn't set to big endian when it should have 1585 * been after writing the initial values. It keeps on being 1586 * triggered, the only way to stop it seems to shut down the 1587 * chip." 1588 * 1589 * Suggesting that we should never get it and if we do we're not 1590 * feeding TX packets into the MAC correctly if we do... Apparently, 1591 * it is valid only on mac version 5 and higher, but I couldn't 1592 * find a reference for that... Since I see them from time to time 1593 * on my card, this suggests an error in the tx path still... 1594 */ 1595 if (intr_status & BWI_INTR_PHY_TXERR) { 1596 if (mac->mac_flags & BWI_MAC_F_PHYE_RESET) { 1597 device_printf(sc->sc_dev, "%s: intr PHY TX error\n", 1598 __func__); 1599 taskqueue_enqueue(sc->sc_tq, &sc->sc_restart_task); 1600 BWI_UNLOCK(sc); 1601 return; 1602 } 1603 } 1604 1605 if (txrx_error) { 1606 /* TODO: reset device */ 1607 } 1608 1609 if (intr_status & BWI_INTR_TBTT) 1610 bwi_mac_config_ps(mac); 1611 1612 if (intr_status & BWI_INTR_EO_ATIM) 1613 device_printf(sc->sc_dev, "EO_ATIM\n"); 1614 1615 if (intr_status & BWI_INTR_PMQ) { 1616 for (;;) { 1617 if ((CSR_READ_4(sc, BWI_MAC_PS_STATUS) & 0x8) == 0) 1618 break; 1619 } 1620 CSR_WRITE_2(sc, BWI_MAC_PS_STATUS, 0x2); 1621 } 1622 1623 if (intr_status & BWI_INTR_NOISE) 1624 device_printf(sc->sc_dev, "intr noise\n"); 1625 1626 if (txrx_intr_status[0] & BWI_TXRX_INTR_RX) { 1627 rx_data = sc->sc_rxeof(sc); 1628 if (sc->sc_flags & BWI_F_STOP) { 1629 BWI_UNLOCK(sc); 1630 return; 1631 } 1632 } 1633 1634 if (txrx_intr_status[3] & BWI_TXRX_INTR_RX) { 1635 sc->sc_txeof_status(sc); 1636 tx = 1; 1637 } 1638 1639 if (intr_status & BWI_INTR_TX_DONE) { 1640 bwi_txeof(sc); 1641 tx = 1; 1642 } 1643 1644 /* Re-enable interrupts */ 1645 bwi_enable_intrs(sc, BWI_INIT_INTRS); 1646 1647 if (sc->sc_blink_led != NULL && sc->sc_led_blink) { 1648 int evt = BWI_LED_EVENT_NONE; 1649 1650 if (tx && rx_data > 0) { 1651 if (sc->sc_rx_rate > sc->sc_tx_rate) 1652 evt = BWI_LED_EVENT_RX; 1653 else 1654 evt = BWI_LED_EVENT_TX; 1655 } else if (tx) { 1656 evt = BWI_LED_EVENT_TX; 1657 } else if (rx_data > 0) { 1658 evt = BWI_LED_EVENT_RX; 1659 } else if (rx_data == 0) { 1660 evt = BWI_LED_EVENT_POLL; 1661 } 1662 1663 if (evt != BWI_LED_EVENT_NONE) 1664 bwi_led_event(sc, evt); 1665 } 1666 1667 BWI_UNLOCK(sc); 1668 } 1669 1670 static void 1671 bwi_scan_start(struct ieee80211com *ic) 1672 { 1673 struct bwi_softc *sc = ic->ic_softc; 1674 1675 BWI_LOCK(sc); 1676 /* Enable MAC beacon promiscuity */ 1677 CSR_SETBITS_4(sc, BWI_MAC_STATUS, BWI_MAC_STATUS_PASS_BCN); 1678 BWI_UNLOCK(sc); 1679 } 1680 1681 static void 1682 bwi_set_channel(struct ieee80211com *ic) 1683 { 1684 struct bwi_softc *sc = ic->ic_softc; 1685 struct ieee80211_channel *c = ic->ic_curchan; 1686 struct bwi_mac *mac; 1687 1688 BWI_LOCK(sc); 1689 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 1690 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 1691 mac = (struct bwi_mac *)sc->sc_cur_regwin; 1692 bwi_rf_set_chan(mac, ieee80211_chan2ieee(ic, c), 0); 1693 1694 sc->sc_rates = ieee80211_get_ratetable(c); 1695 1696 /* 1697 * Setup radio tap channel freq and flags 1698 */ 1699 sc->sc_tx_th.wt_chan_freq = sc->sc_rx_th.wr_chan_freq = 1700 htole16(c->ic_freq); 1701 sc->sc_tx_th.wt_chan_flags = sc->sc_rx_th.wr_chan_flags = 1702 htole16(c->ic_flags & 0xffff); 1703 1704 BWI_UNLOCK(sc); 1705 } 1706 1707 static void 1708 bwi_scan_end(struct ieee80211com *ic) 1709 { 1710 struct bwi_softc *sc = ic->ic_softc; 1711 1712 BWI_LOCK(sc); 1713 CSR_CLRBITS_4(sc, BWI_MAC_STATUS, BWI_MAC_STATUS_PASS_BCN); 1714 BWI_UNLOCK(sc); 1715 } 1716 1717 static int 1718 bwi_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 1719 { 1720 struct bwi_vap *bvp = BWI_VAP(vap); 1721 struct ieee80211com *ic= vap->iv_ic; 1722 struct bwi_softc *sc = ic->ic_softc; 1723 enum ieee80211_state ostate = vap->iv_state; 1724 struct bwi_mac *mac; 1725 int error; 1726 1727 BWI_LOCK(sc); 1728 1729 callout_stop(&sc->sc_calib_ch); 1730 1731 if (nstate == IEEE80211_S_INIT) 1732 sc->sc_txpwrcb_type = BWI_TXPWR_INIT; 1733 1734 bwi_led_newstate(sc, nstate); 1735 1736 error = bvp->bv_newstate(vap, nstate, arg); 1737 if (error != 0) 1738 goto back; 1739 1740 /* 1741 * Clear the BSSID when we stop a STA 1742 */ 1743 if (vap->iv_opmode == IEEE80211_M_STA) { 1744 if (ostate == IEEE80211_S_RUN && nstate != IEEE80211_S_RUN) { 1745 /* 1746 * Clear out the BSSID. If we reassociate to 1747 * the same AP, this will reinialize things 1748 * correctly... 1749 */ 1750 if (ic->ic_opmode == IEEE80211_M_STA && 1751 !(sc->sc_flags & BWI_F_STOP)) 1752 bwi_set_bssid(sc, bwi_zero_addr); 1753 } 1754 } 1755 1756 if (vap->iv_opmode == IEEE80211_M_MONITOR) { 1757 /* Nothing to do */ 1758 } else if (nstate == IEEE80211_S_RUN) { 1759 bwi_set_bssid(sc, vap->iv_bss->ni_bssid); 1760 1761 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 1762 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 1763 mac = (struct bwi_mac *)sc->sc_cur_regwin; 1764 1765 /* Initial TX power calibration */ 1766 bwi_mac_calibrate_txpower(mac, BWI_TXPWR_INIT); 1767 #ifdef notyet 1768 sc->sc_txpwrcb_type = BWI_TXPWR_FORCE; 1769 #else 1770 sc->sc_txpwrcb_type = BWI_TXPWR_CALIB; 1771 #endif 1772 1773 callout_reset(&sc->sc_calib_ch, hz, bwi_calibrate, sc); 1774 } 1775 back: 1776 BWI_UNLOCK(sc); 1777 1778 return error; 1779 } 1780 1781 static int 1782 bwi_media_change(struct ifnet *ifp) 1783 { 1784 int error = ieee80211_media_change(ifp); 1785 /* NB: only the fixed rate can change and that doesn't need a reset */ 1786 return (error == ENETRESET ? 0 : error); 1787 } 1788 1789 static int 1790 bwi_dma_alloc(struct bwi_softc *sc) 1791 { 1792 int error, i, has_txstats; 1793 bus_addr_t lowaddr = 0; 1794 bus_size_t tx_ring_sz, rx_ring_sz, desc_sz = 0; 1795 uint32_t txrx_ctrl_step = 0; 1796 1797 has_txstats = 0; 1798 for (i = 0; i < sc->sc_nmac; ++i) { 1799 if (sc->sc_mac[i].mac_flags & BWI_MAC_F_HAS_TXSTATS) { 1800 has_txstats = 1; 1801 break; 1802 } 1803 } 1804 1805 switch (sc->sc_bus_space) { 1806 case BWI_BUS_SPACE_30BIT: 1807 case BWI_BUS_SPACE_32BIT: 1808 if (sc->sc_bus_space == BWI_BUS_SPACE_30BIT) 1809 lowaddr = BWI_BUS_SPACE_MAXADDR; 1810 else 1811 lowaddr = BUS_SPACE_MAXADDR_32BIT; 1812 desc_sz = sizeof(struct bwi_desc32); 1813 txrx_ctrl_step = 0x20; 1814 1815 sc->sc_init_tx_ring = bwi_init_tx_ring32; 1816 sc->sc_free_tx_ring = bwi_free_tx_ring32; 1817 sc->sc_init_rx_ring = bwi_init_rx_ring32; 1818 sc->sc_free_rx_ring = bwi_free_rx_ring32; 1819 sc->sc_setup_rxdesc = bwi_setup_rx_desc32; 1820 sc->sc_setup_txdesc = bwi_setup_tx_desc32; 1821 sc->sc_rxeof = bwi_rxeof32; 1822 sc->sc_start_tx = bwi_start_tx32; 1823 if (has_txstats) { 1824 sc->sc_init_txstats = bwi_init_txstats32; 1825 sc->sc_free_txstats = bwi_free_txstats32; 1826 sc->sc_txeof_status = bwi_txeof_status32; 1827 } 1828 break; 1829 1830 case BWI_BUS_SPACE_64BIT: 1831 lowaddr = BUS_SPACE_MAXADDR; /* XXX */ 1832 desc_sz = sizeof(struct bwi_desc64); 1833 txrx_ctrl_step = 0x40; 1834 1835 sc->sc_init_tx_ring = bwi_init_tx_ring64; 1836 sc->sc_free_tx_ring = bwi_free_tx_ring64; 1837 sc->sc_init_rx_ring = bwi_init_rx_ring64; 1838 sc->sc_free_rx_ring = bwi_free_rx_ring64; 1839 sc->sc_setup_rxdesc = bwi_setup_rx_desc64; 1840 sc->sc_setup_txdesc = bwi_setup_tx_desc64; 1841 sc->sc_rxeof = bwi_rxeof64; 1842 sc->sc_start_tx = bwi_start_tx64; 1843 if (has_txstats) { 1844 sc->sc_init_txstats = bwi_init_txstats64; 1845 sc->sc_free_txstats = bwi_free_txstats64; 1846 sc->sc_txeof_status = bwi_txeof_status64; 1847 } 1848 break; 1849 } 1850 1851 KASSERT(lowaddr != 0, ("lowaddr zero")); 1852 KASSERT(desc_sz != 0, ("desc_sz zero")); 1853 KASSERT(txrx_ctrl_step != 0, ("txrx_ctrl_step zero")); 1854 1855 tx_ring_sz = roundup(desc_sz * BWI_TX_NDESC, BWI_RING_ALIGN); 1856 rx_ring_sz = roundup(desc_sz * BWI_RX_NDESC, BWI_RING_ALIGN); 1857 1858 /* 1859 * Create top level DMA tag 1860 */ 1861 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), /* parent */ 1862 BWI_ALIGN, 0, /* alignment, bounds */ 1863 lowaddr, /* lowaddr */ 1864 BUS_SPACE_MAXADDR, /* highaddr */ 1865 NULL, NULL, /* filter, filterarg */ 1866 BUS_SPACE_MAXSIZE, /* maxsize */ 1867 BUS_SPACE_UNRESTRICTED, /* nsegments */ 1868 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1869 0, /* flags */ 1870 NULL, NULL, /* lockfunc, lockarg */ 1871 &sc->sc_parent_dtag); 1872 if (error) { 1873 device_printf(sc->sc_dev, "can't create parent DMA tag\n"); 1874 return error; 1875 } 1876 1877 #define TXRX_CTRL(idx) (BWI_TXRX_CTRL_BASE + (idx) * txrx_ctrl_step) 1878 1879 /* 1880 * Create TX ring DMA stuffs 1881 */ 1882 error = bus_dma_tag_create(sc->sc_parent_dtag, 1883 BWI_RING_ALIGN, 0, 1884 BUS_SPACE_MAXADDR, 1885 BUS_SPACE_MAXADDR, 1886 NULL, NULL, 1887 tx_ring_sz, 1888 1, 1889 tx_ring_sz, 1890 0, 1891 NULL, NULL, 1892 &sc->sc_txring_dtag); 1893 if (error) { 1894 device_printf(sc->sc_dev, "can't create TX ring DMA tag\n"); 1895 return error; 1896 } 1897 1898 for (i = 0; i < BWI_TX_NRING; ++i) { 1899 error = bwi_dma_ring_alloc(sc, sc->sc_txring_dtag, 1900 &sc->sc_tx_rdata[i], tx_ring_sz, 1901 TXRX_CTRL(i)); 1902 if (error) { 1903 device_printf(sc->sc_dev, "%dth TX ring " 1904 "DMA alloc failed\n", i); 1905 return error; 1906 } 1907 } 1908 1909 /* 1910 * Create RX ring DMA stuffs 1911 */ 1912 error = bus_dma_tag_create(sc->sc_parent_dtag, 1913 BWI_RING_ALIGN, 0, 1914 BUS_SPACE_MAXADDR, 1915 BUS_SPACE_MAXADDR, 1916 NULL, NULL, 1917 rx_ring_sz, 1918 1, 1919 rx_ring_sz, 1920 0, 1921 NULL, NULL, 1922 &sc->sc_rxring_dtag); 1923 if (error) { 1924 device_printf(sc->sc_dev, "can't create RX ring DMA tag\n"); 1925 return error; 1926 } 1927 1928 error = bwi_dma_ring_alloc(sc, sc->sc_rxring_dtag, &sc->sc_rx_rdata, 1929 rx_ring_sz, TXRX_CTRL(0)); 1930 if (error) { 1931 device_printf(sc->sc_dev, "RX ring DMA alloc failed\n"); 1932 return error; 1933 } 1934 1935 if (has_txstats) { 1936 error = bwi_dma_txstats_alloc(sc, TXRX_CTRL(3), desc_sz); 1937 if (error) { 1938 device_printf(sc->sc_dev, 1939 "TX stats DMA alloc failed\n"); 1940 return error; 1941 } 1942 } 1943 1944 #undef TXRX_CTRL 1945 1946 return bwi_dma_mbuf_create(sc); 1947 } 1948 1949 static void 1950 bwi_dma_free(struct bwi_softc *sc) 1951 { 1952 if (sc->sc_txring_dtag != NULL) { 1953 int i; 1954 1955 for (i = 0; i < BWI_TX_NRING; ++i) { 1956 struct bwi_ring_data *rd = &sc->sc_tx_rdata[i]; 1957 1958 if (rd->rdata_desc != NULL) { 1959 bus_dmamap_unload(sc->sc_txring_dtag, 1960 rd->rdata_dmap); 1961 bus_dmamem_free(sc->sc_txring_dtag, 1962 rd->rdata_desc, 1963 rd->rdata_dmap); 1964 } 1965 } 1966 bus_dma_tag_destroy(sc->sc_txring_dtag); 1967 } 1968 1969 if (sc->sc_rxring_dtag != NULL) { 1970 struct bwi_ring_data *rd = &sc->sc_rx_rdata; 1971 1972 if (rd->rdata_desc != NULL) { 1973 bus_dmamap_unload(sc->sc_rxring_dtag, rd->rdata_dmap); 1974 bus_dmamem_free(sc->sc_rxring_dtag, rd->rdata_desc, 1975 rd->rdata_dmap); 1976 } 1977 bus_dma_tag_destroy(sc->sc_rxring_dtag); 1978 } 1979 1980 bwi_dma_txstats_free(sc); 1981 bwi_dma_mbuf_destroy(sc, BWI_TX_NRING, 1); 1982 1983 if (sc->sc_parent_dtag != NULL) 1984 bus_dma_tag_destroy(sc->sc_parent_dtag); 1985 } 1986 1987 static int 1988 bwi_dma_ring_alloc(struct bwi_softc *sc, bus_dma_tag_t dtag, 1989 struct bwi_ring_data *rd, bus_size_t size, 1990 uint32_t txrx_ctrl) 1991 { 1992 int error; 1993 1994 error = bus_dmamem_alloc(dtag, &rd->rdata_desc, 1995 BUS_DMA_WAITOK | BUS_DMA_ZERO, 1996 &rd->rdata_dmap); 1997 if (error) { 1998 device_printf(sc->sc_dev, "can't allocate DMA mem\n"); 1999 return error; 2000 } 2001 2002 error = bus_dmamap_load(dtag, rd->rdata_dmap, rd->rdata_desc, size, 2003 bwi_dma_ring_addr, &rd->rdata_paddr, 2004 BUS_DMA_NOWAIT); 2005 if (error) { 2006 device_printf(sc->sc_dev, "can't load DMA mem\n"); 2007 bus_dmamem_free(dtag, rd->rdata_desc, rd->rdata_dmap); 2008 rd->rdata_desc = NULL; 2009 return error; 2010 } 2011 2012 rd->rdata_txrx_ctrl = txrx_ctrl; 2013 return 0; 2014 } 2015 2016 static int 2017 bwi_dma_txstats_alloc(struct bwi_softc *sc, uint32_t ctrl_base, 2018 bus_size_t desc_sz) 2019 { 2020 struct bwi_txstats_data *st; 2021 bus_size_t dma_size; 2022 int error; 2023 2024 st = malloc(sizeof(*st), M_DEVBUF, M_NOWAIT | M_ZERO); 2025 if (st == NULL) { 2026 device_printf(sc->sc_dev, "can't allocate txstats data\n"); 2027 return ENOMEM; 2028 } 2029 sc->sc_txstats = st; 2030 2031 /* 2032 * Create TX stats descriptor DMA stuffs 2033 */ 2034 dma_size = roundup(desc_sz * BWI_TXSTATS_NDESC, BWI_RING_ALIGN); 2035 2036 error = bus_dma_tag_create(sc->sc_parent_dtag, 2037 BWI_RING_ALIGN, 2038 0, 2039 BUS_SPACE_MAXADDR, 2040 BUS_SPACE_MAXADDR, 2041 NULL, NULL, 2042 dma_size, 2043 1, 2044 dma_size, 2045 0, 2046 NULL, NULL, 2047 &st->stats_ring_dtag); 2048 if (error) { 2049 device_printf(sc->sc_dev, "can't create txstats ring " 2050 "DMA tag\n"); 2051 return error; 2052 } 2053 2054 error = bus_dmamem_alloc(st->stats_ring_dtag, &st->stats_ring, 2055 BUS_DMA_WAITOK | BUS_DMA_ZERO, 2056 &st->stats_ring_dmap); 2057 if (error) { 2058 device_printf(sc->sc_dev, "can't allocate txstats ring " 2059 "DMA mem\n"); 2060 bus_dma_tag_destroy(st->stats_ring_dtag); 2061 st->stats_ring_dtag = NULL; 2062 return error; 2063 } 2064 2065 error = bus_dmamap_load(st->stats_ring_dtag, st->stats_ring_dmap, 2066 st->stats_ring, dma_size, 2067 bwi_dma_ring_addr, &st->stats_ring_paddr, 2068 BUS_DMA_NOWAIT); 2069 if (error) { 2070 device_printf(sc->sc_dev, "can't load txstats ring DMA mem\n"); 2071 bus_dmamem_free(st->stats_ring_dtag, st->stats_ring, 2072 st->stats_ring_dmap); 2073 bus_dma_tag_destroy(st->stats_ring_dtag); 2074 st->stats_ring_dtag = NULL; 2075 return error; 2076 } 2077 2078 /* 2079 * Create TX stats DMA stuffs 2080 */ 2081 dma_size = roundup(sizeof(struct bwi_txstats) * BWI_TXSTATS_NDESC, 2082 BWI_ALIGN); 2083 2084 error = bus_dma_tag_create(sc->sc_parent_dtag, 2085 BWI_ALIGN, 2086 0, 2087 BUS_SPACE_MAXADDR, 2088 BUS_SPACE_MAXADDR, 2089 NULL, NULL, 2090 dma_size, 2091 1, 2092 dma_size, 2093 0, 2094 NULL, NULL, 2095 &st->stats_dtag); 2096 if (error) { 2097 device_printf(sc->sc_dev, "can't create txstats DMA tag\n"); 2098 return error; 2099 } 2100 2101 error = bus_dmamem_alloc(st->stats_dtag, (void **)&st->stats, 2102 BUS_DMA_WAITOK | BUS_DMA_ZERO, 2103 &st->stats_dmap); 2104 if (error) { 2105 device_printf(sc->sc_dev, "can't allocate txstats DMA mem\n"); 2106 bus_dma_tag_destroy(st->stats_dtag); 2107 st->stats_dtag = NULL; 2108 return error; 2109 } 2110 2111 error = bus_dmamap_load(st->stats_dtag, st->stats_dmap, st->stats, 2112 dma_size, bwi_dma_ring_addr, &st->stats_paddr, 2113 BUS_DMA_NOWAIT); 2114 if (error) { 2115 device_printf(sc->sc_dev, "can't load txstats DMA mem\n"); 2116 bus_dmamem_free(st->stats_dtag, st->stats, st->stats_dmap); 2117 bus_dma_tag_destroy(st->stats_dtag); 2118 st->stats_dtag = NULL; 2119 return error; 2120 } 2121 2122 st->stats_ctrl_base = ctrl_base; 2123 return 0; 2124 } 2125 2126 static void 2127 bwi_dma_txstats_free(struct bwi_softc *sc) 2128 { 2129 struct bwi_txstats_data *st; 2130 2131 if (sc->sc_txstats == NULL) 2132 return; 2133 st = sc->sc_txstats; 2134 2135 if (st->stats_ring_dtag != NULL) { 2136 bus_dmamap_unload(st->stats_ring_dtag, st->stats_ring_dmap); 2137 bus_dmamem_free(st->stats_ring_dtag, st->stats_ring, 2138 st->stats_ring_dmap); 2139 bus_dma_tag_destroy(st->stats_ring_dtag); 2140 } 2141 2142 if (st->stats_dtag != NULL) { 2143 bus_dmamap_unload(st->stats_dtag, st->stats_dmap); 2144 bus_dmamem_free(st->stats_dtag, st->stats, st->stats_dmap); 2145 bus_dma_tag_destroy(st->stats_dtag); 2146 } 2147 2148 free(st, M_DEVBUF); 2149 } 2150 2151 static void 2152 bwi_dma_ring_addr(void *arg, bus_dma_segment_t *seg, int nseg, int error) 2153 { 2154 KASSERT(nseg == 1, ("too many segments\n")); 2155 *((bus_addr_t *)arg) = seg->ds_addr; 2156 } 2157 2158 static int 2159 bwi_dma_mbuf_create(struct bwi_softc *sc) 2160 { 2161 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata; 2162 int i, j, k, ntx, error; 2163 2164 /* 2165 * Create TX/RX mbuf DMA tag 2166 */ 2167 error = bus_dma_tag_create(sc->sc_parent_dtag, 2168 1, 2169 0, 2170 BUS_SPACE_MAXADDR, 2171 BUS_SPACE_MAXADDR, 2172 NULL, NULL, 2173 MCLBYTES, 2174 1, 2175 MCLBYTES, 2176 BUS_DMA_ALLOCNOW, 2177 NULL, NULL, 2178 &sc->sc_buf_dtag); 2179 if (error) { 2180 device_printf(sc->sc_dev, "can't create mbuf DMA tag\n"); 2181 return error; 2182 } 2183 2184 ntx = 0; 2185 2186 /* 2187 * Create TX mbuf DMA map 2188 */ 2189 for (i = 0; i < BWI_TX_NRING; ++i) { 2190 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[i]; 2191 2192 for (j = 0; j < BWI_TX_NDESC; ++j) { 2193 error = bus_dmamap_create(sc->sc_buf_dtag, 0, 2194 &tbd->tbd_buf[j].tb_dmap); 2195 if (error) { 2196 device_printf(sc->sc_dev, "can't create " 2197 "%dth tbd, %dth DMA map\n", i, j); 2198 2199 ntx = i; 2200 for (k = 0; k < j; ++k) { 2201 bus_dmamap_destroy(sc->sc_buf_dtag, 2202 tbd->tbd_buf[k].tb_dmap); 2203 } 2204 goto fail; 2205 } 2206 } 2207 } 2208 ntx = BWI_TX_NRING; 2209 2210 /* 2211 * Create RX mbuf DMA map and a spare DMA map 2212 */ 2213 error = bus_dmamap_create(sc->sc_buf_dtag, 0, 2214 &rbd->rbd_tmp_dmap); 2215 if (error) { 2216 device_printf(sc->sc_dev, 2217 "can't create spare RX buf DMA map\n"); 2218 goto fail; 2219 } 2220 2221 for (j = 0; j < BWI_RX_NDESC; ++j) { 2222 error = bus_dmamap_create(sc->sc_buf_dtag, 0, 2223 &rbd->rbd_buf[j].rb_dmap); 2224 if (error) { 2225 device_printf(sc->sc_dev, "can't create %dth " 2226 "RX buf DMA map\n", j); 2227 2228 for (k = 0; k < j; ++k) { 2229 bus_dmamap_destroy(sc->sc_buf_dtag, 2230 rbd->rbd_buf[j].rb_dmap); 2231 } 2232 bus_dmamap_destroy(sc->sc_buf_dtag, 2233 rbd->rbd_tmp_dmap); 2234 goto fail; 2235 } 2236 } 2237 2238 return 0; 2239 fail: 2240 bwi_dma_mbuf_destroy(sc, ntx, 0); 2241 return error; 2242 } 2243 2244 static void 2245 bwi_dma_mbuf_destroy(struct bwi_softc *sc, int ntx, int nrx) 2246 { 2247 int i, j; 2248 2249 if (sc->sc_buf_dtag == NULL) 2250 return; 2251 2252 for (i = 0; i < ntx; ++i) { 2253 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[i]; 2254 2255 for (j = 0; j < BWI_TX_NDESC; ++j) { 2256 struct bwi_txbuf *tb = &tbd->tbd_buf[j]; 2257 2258 if (tb->tb_mbuf != NULL) { 2259 bus_dmamap_unload(sc->sc_buf_dtag, 2260 tb->tb_dmap); 2261 m_freem(tb->tb_mbuf); 2262 } 2263 if (tb->tb_ni != NULL) 2264 ieee80211_free_node(tb->tb_ni); 2265 bus_dmamap_destroy(sc->sc_buf_dtag, tb->tb_dmap); 2266 } 2267 } 2268 2269 if (nrx) { 2270 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata; 2271 2272 bus_dmamap_destroy(sc->sc_buf_dtag, rbd->rbd_tmp_dmap); 2273 for (j = 0; j < BWI_RX_NDESC; ++j) { 2274 struct bwi_rxbuf *rb = &rbd->rbd_buf[j]; 2275 2276 if (rb->rb_mbuf != NULL) { 2277 bus_dmamap_unload(sc->sc_buf_dtag, 2278 rb->rb_dmap); 2279 m_freem(rb->rb_mbuf); 2280 } 2281 bus_dmamap_destroy(sc->sc_buf_dtag, rb->rb_dmap); 2282 } 2283 } 2284 2285 bus_dma_tag_destroy(sc->sc_buf_dtag); 2286 sc->sc_buf_dtag = NULL; 2287 } 2288 2289 static void 2290 bwi_enable_intrs(struct bwi_softc *sc, uint32_t enable_intrs) 2291 { 2292 CSR_SETBITS_4(sc, BWI_MAC_INTR_MASK, enable_intrs); 2293 } 2294 2295 static void 2296 bwi_disable_intrs(struct bwi_softc *sc, uint32_t disable_intrs) 2297 { 2298 CSR_CLRBITS_4(sc, BWI_MAC_INTR_MASK, disable_intrs); 2299 } 2300 2301 static int 2302 bwi_init_tx_ring32(struct bwi_softc *sc, int ring_idx) 2303 { 2304 struct bwi_ring_data *rd; 2305 struct bwi_txbuf_data *tbd; 2306 uint32_t val, addr_hi, addr_lo; 2307 2308 KASSERT(ring_idx < BWI_TX_NRING, ("ring_idx %d", ring_idx)); 2309 rd = &sc->sc_tx_rdata[ring_idx]; 2310 tbd = &sc->sc_tx_bdata[ring_idx]; 2311 2312 tbd->tbd_idx = 0; 2313 tbd->tbd_used = 0; 2314 2315 bzero(rd->rdata_desc, sizeof(struct bwi_desc32) * BWI_TX_NDESC); 2316 bus_dmamap_sync(sc->sc_txring_dtag, rd->rdata_dmap, 2317 BUS_DMASYNC_PREWRITE); 2318 2319 addr_lo = __SHIFTOUT(rd->rdata_paddr, BWI_TXRX32_RINGINFO_ADDR_MASK); 2320 addr_hi = __SHIFTOUT(rd->rdata_paddr, BWI_TXRX32_RINGINFO_FUNC_MASK); 2321 2322 val = __SHIFTIN(addr_lo, BWI_TXRX32_RINGINFO_ADDR_MASK) | 2323 __SHIFTIN(BWI_TXRX32_RINGINFO_FUNC_TXRX, 2324 BWI_TXRX32_RINGINFO_FUNC_MASK); 2325 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_RINGINFO, val); 2326 2327 val = __SHIFTIN(addr_hi, BWI_TXRX32_CTRL_ADDRHI_MASK) | 2328 BWI_TXRX32_CTRL_ENABLE; 2329 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_CTRL, val); 2330 2331 return 0; 2332 } 2333 2334 static void 2335 bwi_init_rxdesc_ring32(struct bwi_softc *sc, uint32_t ctrl_base, 2336 bus_addr_t paddr, int hdr_size, int ndesc) 2337 { 2338 uint32_t val, addr_hi, addr_lo; 2339 2340 addr_lo = __SHIFTOUT(paddr, BWI_TXRX32_RINGINFO_ADDR_MASK); 2341 addr_hi = __SHIFTOUT(paddr, BWI_TXRX32_RINGINFO_FUNC_MASK); 2342 2343 val = __SHIFTIN(addr_lo, BWI_TXRX32_RINGINFO_ADDR_MASK) | 2344 __SHIFTIN(BWI_TXRX32_RINGINFO_FUNC_TXRX, 2345 BWI_TXRX32_RINGINFO_FUNC_MASK); 2346 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_RINGINFO, val); 2347 2348 val = __SHIFTIN(hdr_size, BWI_RX32_CTRL_HDRSZ_MASK) | 2349 __SHIFTIN(addr_hi, BWI_TXRX32_CTRL_ADDRHI_MASK) | 2350 BWI_TXRX32_CTRL_ENABLE; 2351 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_CTRL, val); 2352 2353 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_INDEX, 2354 (ndesc - 1) * sizeof(struct bwi_desc32)); 2355 } 2356 2357 static int 2358 bwi_init_rx_ring32(struct bwi_softc *sc) 2359 { 2360 struct bwi_ring_data *rd = &sc->sc_rx_rdata; 2361 int i, error; 2362 2363 sc->sc_rx_bdata.rbd_idx = 0; 2364 2365 for (i = 0; i < BWI_RX_NDESC; ++i) { 2366 error = bwi_newbuf(sc, i, 1); 2367 if (error) { 2368 device_printf(sc->sc_dev, 2369 "can't allocate %dth RX buffer\n", i); 2370 return error; 2371 } 2372 } 2373 bus_dmamap_sync(sc->sc_rxring_dtag, rd->rdata_dmap, 2374 BUS_DMASYNC_PREWRITE); 2375 2376 bwi_init_rxdesc_ring32(sc, rd->rdata_txrx_ctrl, rd->rdata_paddr, 2377 sizeof(struct bwi_rxbuf_hdr), BWI_RX_NDESC); 2378 return 0; 2379 } 2380 2381 static int 2382 bwi_init_txstats32(struct bwi_softc *sc) 2383 { 2384 struct bwi_txstats_data *st = sc->sc_txstats; 2385 bus_addr_t stats_paddr; 2386 int i; 2387 2388 bzero(st->stats, BWI_TXSTATS_NDESC * sizeof(struct bwi_txstats)); 2389 bus_dmamap_sync(st->stats_dtag, st->stats_dmap, BUS_DMASYNC_PREWRITE); 2390 2391 st->stats_idx = 0; 2392 2393 stats_paddr = st->stats_paddr; 2394 for (i = 0; i < BWI_TXSTATS_NDESC; ++i) { 2395 bwi_setup_desc32(sc, st->stats_ring, BWI_TXSTATS_NDESC, i, 2396 stats_paddr, sizeof(struct bwi_txstats), 0); 2397 stats_paddr += sizeof(struct bwi_txstats); 2398 } 2399 bus_dmamap_sync(st->stats_ring_dtag, st->stats_ring_dmap, 2400 BUS_DMASYNC_PREWRITE); 2401 2402 bwi_init_rxdesc_ring32(sc, st->stats_ctrl_base, 2403 st->stats_ring_paddr, 0, BWI_TXSTATS_NDESC); 2404 return 0; 2405 } 2406 2407 static void 2408 bwi_setup_rx_desc32(struct bwi_softc *sc, int buf_idx, bus_addr_t paddr, 2409 int buf_len) 2410 { 2411 struct bwi_ring_data *rd = &sc->sc_rx_rdata; 2412 2413 KASSERT(buf_idx < BWI_RX_NDESC, ("buf_idx %d", buf_idx)); 2414 bwi_setup_desc32(sc, rd->rdata_desc, BWI_RX_NDESC, buf_idx, 2415 paddr, buf_len, 0); 2416 } 2417 2418 static void 2419 bwi_setup_tx_desc32(struct bwi_softc *sc, struct bwi_ring_data *rd, 2420 int buf_idx, bus_addr_t paddr, int buf_len) 2421 { 2422 KASSERT(buf_idx < BWI_TX_NDESC, ("buf_idx %d", buf_idx)); 2423 bwi_setup_desc32(sc, rd->rdata_desc, BWI_TX_NDESC, buf_idx, 2424 paddr, buf_len, 1); 2425 } 2426 2427 static int 2428 bwi_init_tx_ring64(struct bwi_softc *sc, int ring_idx) 2429 { 2430 /* TODO:64 */ 2431 return EOPNOTSUPP; 2432 } 2433 2434 static int 2435 bwi_init_rx_ring64(struct bwi_softc *sc) 2436 { 2437 /* TODO:64 */ 2438 return EOPNOTSUPP; 2439 } 2440 2441 static int 2442 bwi_init_txstats64(struct bwi_softc *sc) 2443 { 2444 /* TODO:64 */ 2445 return EOPNOTSUPP; 2446 } 2447 2448 static void 2449 bwi_setup_rx_desc64(struct bwi_softc *sc, int buf_idx, bus_addr_t paddr, 2450 int buf_len) 2451 { 2452 /* TODO:64 */ 2453 } 2454 2455 static void 2456 bwi_setup_tx_desc64(struct bwi_softc *sc, struct bwi_ring_data *rd, 2457 int buf_idx, bus_addr_t paddr, int buf_len) 2458 { 2459 /* TODO:64 */ 2460 } 2461 2462 static void 2463 bwi_dma_buf_addr(void *arg, bus_dma_segment_t *seg, int nseg, 2464 bus_size_t mapsz __unused, int error) 2465 { 2466 if (!error) { 2467 KASSERT(nseg == 1, ("too many segments(%d)\n", nseg)); 2468 *((bus_addr_t *)arg) = seg->ds_addr; 2469 } 2470 } 2471 2472 static int 2473 bwi_newbuf(struct bwi_softc *sc, int buf_idx, int init) 2474 { 2475 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata; 2476 struct bwi_rxbuf *rxbuf = &rbd->rbd_buf[buf_idx]; 2477 struct bwi_rxbuf_hdr *hdr; 2478 bus_dmamap_t map; 2479 bus_addr_t paddr; 2480 struct mbuf *m; 2481 int error; 2482 2483 KASSERT(buf_idx < BWI_RX_NDESC, ("buf_idx %d", buf_idx)); 2484 2485 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 2486 if (m == NULL) { 2487 error = ENOBUFS; 2488 2489 /* 2490 * If the NIC is up and running, we need to: 2491 * - Clear RX buffer's header. 2492 * - Restore RX descriptor settings. 2493 */ 2494 if (init) 2495 return error; 2496 else 2497 goto back; 2498 } 2499 m->m_len = m->m_pkthdr.len = MCLBYTES; 2500 2501 /* 2502 * Try to load RX buf into temporary DMA map 2503 */ 2504 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, rbd->rbd_tmp_dmap, m, 2505 bwi_dma_buf_addr, &paddr, BUS_DMA_NOWAIT); 2506 if (error) { 2507 m_freem(m); 2508 2509 /* 2510 * See the comment above 2511 */ 2512 if (init) 2513 return error; 2514 else 2515 goto back; 2516 } 2517 2518 if (!init) 2519 bus_dmamap_unload(sc->sc_buf_dtag, rxbuf->rb_dmap); 2520 rxbuf->rb_mbuf = m; 2521 rxbuf->rb_paddr = paddr; 2522 2523 /* 2524 * Swap RX buf's DMA map with the loaded temporary one 2525 */ 2526 map = rxbuf->rb_dmap; 2527 rxbuf->rb_dmap = rbd->rbd_tmp_dmap; 2528 rbd->rbd_tmp_dmap = map; 2529 2530 back: 2531 /* 2532 * Clear RX buf header 2533 */ 2534 hdr = mtod(rxbuf->rb_mbuf, struct bwi_rxbuf_hdr *); 2535 bzero(hdr, sizeof(*hdr)); 2536 bus_dmamap_sync(sc->sc_buf_dtag, rxbuf->rb_dmap, BUS_DMASYNC_PREWRITE); 2537 2538 /* 2539 * Setup RX buf descriptor 2540 */ 2541 sc->sc_setup_rxdesc(sc, buf_idx, rxbuf->rb_paddr, 2542 rxbuf->rb_mbuf->m_len - sizeof(*hdr)); 2543 return error; 2544 } 2545 2546 static void 2547 bwi_set_addr_filter(struct bwi_softc *sc, uint16_t addr_ofs, 2548 const uint8_t *addr) 2549 { 2550 int i; 2551 2552 CSR_WRITE_2(sc, BWI_ADDR_FILTER_CTRL, 2553 BWI_ADDR_FILTER_CTRL_SET | addr_ofs); 2554 2555 for (i = 0; i < (IEEE80211_ADDR_LEN / 2); ++i) { 2556 uint16_t addr_val; 2557 2558 addr_val = (uint16_t)addr[i * 2] | 2559 (((uint16_t)addr[(i * 2) + 1]) << 8); 2560 CSR_WRITE_2(sc, BWI_ADDR_FILTER_DATA, addr_val); 2561 } 2562 } 2563 2564 static int 2565 bwi_rxeof(struct bwi_softc *sc, int end_idx) 2566 { 2567 struct bwi_ring_data *rd = &sc->sc_rx_rdata; 2568 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata; 2569 struct ieee80211com *ic = &sc->sc_ic; 2570 int idx, rx_data = 0; 2571 2572 idx = rbd->rbd_idx; 2573 while (idx != end_idx) { 2574 struct bwi_rxbuf *rb = &rbd->rbd_buf[idx]; 2575 struct bwi_rxbuf_hdr *hdr; 2576 struct ieee80211_frame_min *wh; 2577 struct ieee80211_node *ni; 2578 struct mbuf *m; 2579 uint32_t plcp; 2580 uint16_t flags2; 2581 int buflen, wh_ofs, hdr_extra, rssi, noise, type, rate; 2582 2583 m = rb->rb_mbuf; 2584 bus_dmamap_sync(sc->sc_buf_dtag, rb->rb_dmap, 2585 BUS_DMASYNC_POSTREAD); 2586 2587 if (bwi_newbuf(sc, idx, 0)) { 2588 counter_u64_add(ic->ic_ierrors, 1); 2589 goto next; 2590 } 2591 2592 hdr = mtod(m, struct bwi_rxbuf_hdr *); 2593 flags2 = le16toh(hdr->rxh_flags2); 2594 2595 hdr_extra = 0; 2596 if (flags2 & BWI_RXH_F2_TYPE2FRAME) 2597 hdr_extra = 2; 2598 wh_ofs = hdr_extra + 6; /* XXX magic number */ 2599 2600 buflen = le16toh(hdr->rxh_buflen); 2601 if (buflen < BWI_FRAME_MIN_LEN(wh_ofs)) { 2602 device_printf(sc->sc_dev, 2603 "%s: zero length data, hdr_extra %d\n", 2604 __func__, hdr_extra); 2605 counter_u64_add(ic->ic_ierrors, 1); 2606 m_freem(m); 2607 goto next; 2608 } 2609 2610 bcopy((uint8_t *)(hdr + 1) + hdr_extra, &plcp, sizeof(plcp)); 2611 rssi = bwi_calc_rssi(sc, hdr); 2612 noise = bwi_calc_noise(sc); 2613 2614 m->m_len = m->m_pkthdr.len = buflen + sizeof(*hdr); 2615 m_adj(m, sizeof(*hdr) + wh_ofs); 2616 2617 if (htole16(hdr->rxh_flags1) & BWI_RXH_F1_OFDM) 2618 rate = bwi_plcp2rate(plcp, IEEE80211_T_OFDM); 2619 else 2620 rate = bwi_plcp2rate(plcp, IEEE80211_T_CCK); 2621 2622 /* RX radio tap */ 2623 if (ieee80211_radiotap_active(ic)) 2624 bwi_rx_radiotap(sc, m, hdr, &plcp, rate, rssi, noise); 2625 2626 m_adj(m, -IEEE80211_CRC_LEN); 2627 2628 BWI_UNLOCK(sc); 2629 2630 wh = mtod(m, struct ieee80211_frame_min *); 2631 ni = ieee80211_find_rxnode(ic, wh); 2632 if (ni != NULL) { 2633 type = ieee80211_input(ni, m, rssi - noise, noise); 2634 ieee80211_free_node(ni); 2635 } else 2636 type = ieee80211_input_all(ic, m, rssi - noise, noise); 2637 if (type == IEEE80211_FC0_TYPE_DATA) { 2638 rx_data = 1; 2639 sc->sc_rx_rate = rate; 2640 } 2641 2642 BWI_LOCK(sc); 2643 next: 2644 idx = (idx + 1) % BWI_RX_NDESC; 2645 2646 if (sc->sc_flags & BWI_F_STOP) { 2647 /* 2648 * Take the fast lane, don't do 2649 * any damage to softc 2650 */ 2651 return -1; 2652 } 2653 } 2654 2655 rbd->rbd_idx = idx; 2656 bus_dmamap_sync(sc->sc_rxring_dtag, rd->rdata_dmap, 2657 BUS_DMASYNC_PREWRITE); 2658 2659 return rx_data; 2660 } 2661 2662 static int 2663 bwi_rxeof32(struct bwi_softc *sc) 2664 { 2665 uint32_t val, rx_ctrl; 2666 int end_idx, rx_data; 2667 2668 rx_ctrl = sc->sc_rx_rdata.rdata_txrx_ctrl; 2669 2670 val = CSR_READ_4(sc, rx_ctrl + BWI_RX32_STATUS); 2671 end_idx = __SHIFTOUT(val, BWI_RX32_STATUS_INDEX_MASK) / 2672 sizeof(struct bwi_desc32); 2673 2674 rx_data = bwi_rxeof(sc, end_idx); 2675 if (rx_data >= 0) { 2676 CSR_WRITE_4(sc, rx_ctrl + BWI_RX32_INDEX, 2677 end_idx * sizeof(struct bwi_desc32)); 2678 } 2679 return rx_data; 2680 } 2681 2682 static int 2683 bwi_rxeof64(struct bwi_softc *sc) 2684 { 2685 /* TODO:64 */ 2686 return 0; 2687 } 2688 2689 static void 2690 bwi_reset_rx_ring32(struct bwi_softc *sc, uint32_t rx_ctrl) 2691 { 2692 int i; 2693 2694 CSR_WRITE_4(sc, rx_ctrl + BWI_RX32_CTRL, 0); 2695 2696 #define NRETRY 10 2697 2698 for (i = 0; i < NRETRY; ++i) { 2699 uint32_t status; 2700 2701 status = CSR_READ_4(sc, rx_ctrl + BWI_RX32_STATUS); 2702 if (__SHIFTOUT(status, BWI_RX32_STATUS_STATE_MASK) == 2703 BWI_RX32_STATUS_STATE_DISABLED) 2704 break; 2705 2706 DELAY(1000); 2707 } 2708 if (i == NRETRY) 2709 device_printf(sc->sc_dev, "reset rx ring timedout\n"); 2710 2711 #undef NRETRY 2712 2713 CSR_WRITE_4(sc, rx_ctrl + BWI_RX32_RINGINFO, 0); 2714 } 2715 2716 static void 2717 bwi_free_txstats32(struct bwi_softc *sc) 2718 { 2719 bwi_reset_rx_ring32(sc, sc->sc_txstats->stats_ctrl_base); 2720 } 2721 2722 static void 2723 bwi_free_rx_ring32(struct bwi_softc *sc) 2724 { 2725 struct bwi_ring_data *rd = &sc->sc_rx_rdata; 2726 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata; 2727 int i; 2728 2729 bwi_reset_rx_ring32(sc, rd->rdata_txrx_ctrl); 2730 2731 for (i = 0; i < BWI_RX_NDESC; ++i) { 2732 struct bwi_rxbuf *rb = &rbd->rbd_buf[i]; 2733 2734 if (rb->rb_mbuf != NULL) { 2735 bus_dmamap_unload(sc->sc_buf_dtag, rb->rb_dmap); 2736 m_freem(rb->rb_mbuf); 2737 rb->rb_mbuf = NULL; 2738 } 2739 } 2740 } 2741 2742 static void 2743 bwi_free_tx_ring32(struct bwi_softc *sc, int ring_idx) 2744 { 2745 struct bwi_ring_data *rd; 2746 struct bwi_txbuf_data *tbd; 2747 uint32_t state, val; 2748 int i; 2749 2750 KASSERT(ring_idx < BWI_TX_NRING, ("ring_idx %d", ring_idx)); 2751 rd = &sc->sc_tx_rdata[ring_idx]; 2752 tbd = &sc->sc_tx_bdata[ring_idx]; 2753 2754 #define NRETRY 10 2755 2756 for (i = 0; i < NRETRY; ++i) { 2757 val = CSR_READ_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_STATUS); 2758 state = __SHIFTOUT(val, BWI_TX32_STATUS_STATE_MASK); 2759 if (state == BWI_TX32_STATUS_STATE_DISABLED || 2760 state == BWI_TX32_STATUS_STATE_IDLE || 2761 state == BWI_TX32_STATUS_STATE_STOPPED) 2762 break; 2763 2764 DELAY(1000); 2765 } 2766 if (i == NRETRY) { 2767 device_printf(sc->sc_dev, 2768 "%s: wait for TX ring(%d) stable timed out\n", 2769 __func__, ring_idx); 2770 } 2771 2772 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_CTRL, 0); 2773 for (i = 0; i < NRETRY; ++i) { 2774 val = CSR_READ_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_STATUS); 2775 state = __SHIFTOUT(val, BWI_TX32_STATUS_STATE_MASK); 2776 if (state == BWI_TX32_STATUS_STATE_DISABLED) 2777 break; 2778 2779 DELAY(1000); 2780 } 2781 if (i == NRETRY) 2782 device_printf(sc->sc_dev, "%s: reset TX ring (%d) timed out\n", 2783 __func__, ring_idx); 2784 2785 #undef NRETRY 2786 2787 DELAY(1000); 2788 2789 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_RINGINFO, 0); 2790 2791 for (i = 0; i < BWI_TX_NDESC; ++i) { 2792 struct bwi_txbuf *tb = &tbd->tbd_buf[i]; 2793 2794 if (tb->tb_mbuf != NULL) { 2795 bus_dmamap_unload(sc->sc_buf_dtag, tb->tb_dmap); 2796 m_freem(tb->tb_mbuf); 2797 tb->tb_mbuf = NULL; 2798 } 2799 if (tb->tb_ni != NULL) { 2800 ieee80211_free_node(tb->tb_ni); 2801 tb->tb_ni = NULL; 2802 } 2803 } 2804 } 2805 2806 static void 2807 bwi_free_txstats64(struct bwi_softc *sc) 2808 { 2809 /* TODO:64 */ 2810 } 2811 2812 static void 2813 bwi_free_rx_ring64(struct bwi_softc *sc) 2814 { 2815 /* TODO:64 */ 2816 } 2817 2818 static void 2819 bwi_free_tx_ring64(struct bwi_softc *sc, int ring_idx) 2820 { 2821 /* TODO:64 */ 2822 } 2823 2824 /* XXX does not belong here */ 2825 #define IEEE80211_OFDM_PLCP_RATE_MASK __BITS(3, 0) 2826 #define IEEE80211_OFDM_PLCP_LEN_MASK __BITS(16, 5) 2827 2828 static __inline void 2829 bwi_ofdm_plcp_header(uint32_t *plcp0, int pkt_len, uint8_t rate) 2830 { 2831 uint32_t plcp; 2832 2833 plcp = __SHIFTIN(ieee80211_rate2plcp(rate, IEEE80211_T_OFDM), 2834 IEEE80211_OFDM_PLCP_RATE_MASK) | 2835 __SHIFTIN(pkt_len, IEEE80211_OFDM_PLCP_LEN_MASK); 2836 *plcp0 = htole32(plcp); 2837 } 2838 2839 static __inline void 2840 bwi_ds_plcp_header(struct ieee80211_ds_plcp_hdr *plcp, int pkt_len, 2841 uint8_t rate) 2842 { 2843 int len, service, pkt_bitlen; 2844 2845 pkt_bitlen = pkt_len * NBBY; 2846 len = howmany(pkt_bitlen * 2, rate); 2847 2848 service = IEEE80211_PLCP_SERVICE_LOCKED; 2849 if (rate == (11 * 2)) { 2850 int pkt_bitlen1; 2851 2852 /* 2853 * PLCP service field needs to be adjusted, 2854 * if TX rate is 11Mbytes/s 2855 */ 2856 pkt_bitlen1 = len * 11; 2857 if (pkt_bitlen1 - pkt_bitlen >= NBBY) 2858 service |= IEEE80211_PLCP_SERVICE_LENEXT7; 2859 } 2860 2861 plcp->i_signal = ieee80211_rate2plcp(rate, IEEE80211_T_CCK); 2862 plcp->i_service = service; 2863 plcp->i_length = htole16(len); 2864 /* NOTE: do NOT touch i_crc */ 2865 } 2866 2867 static __inline void 2868 bwi_plcp_header(const struct ieee80211_rate_table *rt, 2869 void *plcp, int pkt_len, uint8_t rate) 2870 { 2871 enum ieee80211_phytype modtype; 2872 2873 /* 2874 * Assume caller has zeroed 'plcp' 2875 */ 2876 modtype = ieee80211_rate2phytype(rt, rate); 2877 if (modtype == IEEE80211_T_OFDM) 2878 bwi_ofdm_plcp_header(plcp, pkt_len, rate); 2879 else if (modtype == IEEE80211_T_DS) 2880 bwi_ds_plcp_header(plcp, pkt_len, rate); 2881 else 2882 panic("unsupport modulation type %u\n", modtype); 2883 } 2884 2885 static int 2886 bwi_encap(struct bwi_softc *sc, int idx, struct mbuf *m, 2887 struct ieee80211_node *ni) 2888 { 2889 struct ieee80211vap *vap = ni->ni_vap; 2890 struct ieee80211com *ic = &sc->sc_ic; 2891 struct bwi_ring_data *rd = &sc->sc_tx_rdata[BWI_TX_DATA_RING]; 2892 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING]; 2893 struct bwi_txbuf *tb = &tbd->tbd_buf[idx]; 2894 struct bwi_mac *mac; 2895 struct bwi_txbuf_hdr *hdr; 2896 struct ieee80211_frame *wh; 2897 const struct ieee80211_txparam *tp; 2898 uint8_t rate, rate_fb; 2899 uint32_t mac_ctrl; 2900 uint16_t phy_ctrl; 2901 bus_addr_t paddr; 2902 int type, ismcast, pkt_len, error, rix; 2903 #if 0 2904 const uint8_t *p; 2905 int i; 2906 #endif 2907 2908 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 2909 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 2910 mac = (struct bwi_mac *)sc->sc_cur_regwin; 2911 2912 wh = mtod(m, struct ieee80211_frame *); 2913 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2914 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 2915 2916 /* Get 802.11 frame len before prepending TX header */ 2917 pkt_len = m->m_pkthdr.len + IEEE80211_CRC_LEN; 2918 2919 /* 2920 * Find TX rate 2921 */ 2922 tp = &vap->iv_txparms[ieee80211_chan2mode(ic->ic_curchan)]; 2923 if (type != IEEE80211_FC0_TYPE_DATA || (m->m_flags & M_EAPOL)) { 2924 rate = rate_fb = tp->mgmtrate; 2925 } else if (ismcast) { 2926 rate = rate_fb = tp->mcastrate; 2927 } else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) { 2928 rate = rate_fb = tp->ucastrate; 2929 } else { 2930 rix = ieee80211_ratectl_rate(ni, NULL, pkt_len); 2931 rate = ni->ni_txrate; 2932 2933 if (rix > 0) { 2934 rate_fb = ni->ni_rates.rs_rates[rix-1] & 2935 IEEE80211_RATE_VAL; 2936 } else { 2937 rate_fb = rate; 2938 } 2939 } 2940 tb->tb_rate[0] = rate; 2941 tb->tb_rate[1] = rate_fb; 2942 sc->sc_tx_rate = rate; 2943 2944 /* 2945 * TX radio tap 2946 */ 2947 if (ieee80211_radiotap_active_vap(vap)) { 2948 sc->sc_tx_th.wt_flags = 0; 2949 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) 2950 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP; 2951 if (ieee80211_rate2phytype(sc->sc_rates, rate) == IEEE80211_T_DS && 2952 (ic->ic_flags & IEEE80211_F_SHPREAMBLE) && 2953 rate != (1 * 2)) { 2954 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 2955 } 2956 sc->sc_tx_th.wt_rate = rate; 2957 2958 ieee80211_radiotap_tx(vap, m); 2959 } 2960 2961 /* 2962 * Setup the embedded TX header 2963 */ 2964 M_PREPEND(m, sizeof(*hdr), M_NOWAIT); 2965 if (m == NULL) { 2966 device_printf(sc->sc_dev, "%s: prepend TX header failed\n", 2967 __func__); 2968 return ENOBUFS; 2969 } 2970 hdr = mtod(m, struct bwi_txbuf_hdr *); 2971 2972 bzero(hdr, sizeof(*hdr)); 2973 2974 bcopy(wh->i_fc, hdr->txh_fc, sizeof(hdr->txh_fc)); 2975 bcopy(wh->i_addr1, hdr->txh_addr1, sizeof(hdr->txh_addr1)); 2976 2977 if (!ismcast) { 2978 uint16_t dur; 2979 2980 dur = ieee80211_ack_duration(sc->sc_rates, rate, 2981 ic->ic_flags & ~IEEE80211_F_SHPREAMBLE); 2982 2983 hdr->txh_fb_duration = htole16(dur); 2984 } 2985 2986 hdr->txh_id = __SHIFTIN(BWI_TX_DATA_RING, BWI_TXH_ID_RING_MASK) | 2987 __SHIFTIN(idx, BWI_TXH_ID_IDX_MASK); 2988 2989 bwi_plcp_header(sc->sc_rates, hdr->txh_plcp, pkt_len, rate); 2990 bwi_plcp_header(sc->sc_rates, hdr->txh_fb_plcp, pkt_len, rate_fb); 2991 2992 phy_ctrl = __SHIFTIN(mac->mac_rf.rf_ant_mode, 2993 BWI_TXH_PHY_C_ANTMODE_MASK); 2994 if (ieee80211_rate2phytype(sc->sc_rates, rate) == IEEE80211_T_OFDM) 2995 phy_ctrl |= BWI_TXH_PHY_C_OFDM; 2996 else if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && rate != (2 * 1)) 2997 phy_ctrl |= BWI_TXH_PHY_C_SHPREAMBLE; 2998 2999 mac_ctrl = BWI_TXH_MAC_C_HWSEQ | BWI_TXH_MAC_C_FIRST_FRAG; 3000 if (!ismcast) 3001 mac_ctrl |= BWI_TXH_MAC_C_ACK; 3002 if (ieee80211_rate2phytype(sc->sc_rates, rate_fb) == IEEE80211_T_OFDM) 3003 mac_ctrl |= BWI_TXH_MAC_C_FB_OFDM; 3004 3005 hdr->txh_mac_ctrl = htole32(mac_ctrl); 3006 hdr->txh_phy_ctrl = htole16(phy_ctrl); 3007 3008 /* Catch any further usage */ 3009 hdr = NULL; 3010 wh = NULL; 3011 3012 /* DMA load */ 3013 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m, 3014 bwi_dma_buf_addr, &paddr, BUS_DMA_NOWAIT); 3015 if (error && error != EFBIG) { 3016 device_printf(sc->sc_dev, "%s: can't load TX buffer (1) %d\n", 3017 __func__, error); 3018 goto back; 3019 } 3020 3021 if (error) { /* error == EFBIG */ 3022 struct mbuf *m_new; 3023 3024 m_new = m_defrag(m, M_NOWAIT); 3025 if (m_new == NULL) { 3026 device_printf(sc->sc_dev, 3027 "%s: can't defrag TX buffer\n", __func__); 3028 error = ENOBUFS; 3029 goto back; 3030 } else { 3031 m = m_new; 3032 } 3033 3034 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m, 3035 bwi_dma_buf_addr, &paddr, 3036 BUS_DMA_NOWAIT); 3037 if (error) { 3038 device_printf(sc->sc_dev, 3039 "%s: can't load TX buffer (2) %d\n", 3040 __func__, error); 3041 goto back; 3042 } 3043 } 3044 error = 0; 3045 3046 bus_dmamap_sync(sc->sc_buf_dtag, tb->tb_dmap, BUS_DMASYNC_PREWRITE); 3047 3048 tb->tb_mbuf = m; 3049 tb->tb_ni = ni; 3050 3051 #if 0 3052 p = mtod(m, const uint8_t *); 3053 for (i = 0; i < m->m_pkthdr.len; ++i) { 3054 if (i != 0 && i % 8 == 0) 3055 printf("\n"); 3056 printf("%02x ", p[i]); 3057 } 3058 printf("\n"); 3059 #endif 3060 DPRINTF(sc, BWI_DBG_TX, "idx %d, pkt_len %d, buflen %d\n", 3061 idx, pkt_len, m->m_pkthdr.len); 3062 3063 /* Setup TX descriptor */ 3064 sc->sc_setup_txdesc(sc, rd, idx, paddr, m->m_pkthdr.len); 3065 bus_dmamap_sync(sc->sc_txring_dtag, rd->rdata_dmap, 3066 BUS_DMASYNC_PREWRITE); 3067 3068 /* Kick start */ 3069 sc->sc_start_tx(sc, rd->rdata_txrx_ctrl, idx); 3070 3071 back: 3072 if (error) 3073 m_freem(m); 3074 return error; 3075 } 3076 3077 static int 3078 bwi_encap_raw(struct bwi_softc *sc, int idx, struct mbuf *m, 3079 struct ieee80211_node *ni, const struct ieee80211_bpf_params *params) 3080 { 3081 struct ieee80211vap *vap = ni->ni_vap; 3082 struct ieee80211com *ic = ni->ni_ic; 3083 struct bwi_ring_data *rd = &sc->sc_tx_rdata[BWI_TX_DATA_RING]; 3084 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING]; 3085 struct bwi_txbuf *tb = &tbd->tbd_buf[idx]; 3086 struct bwi_mac *mac; 3087 struct bwi_txbuf_hdr *hdr; 3088 struct ieee80211_frame *wh; 3089 uint8_t rate, rate_fb; 3090 uint32_t mac_ctrl; 3091 uint16_t phy_ctrl; 3092 bus_addr_t paddr; 3093 int ismcast, pkt_len, error; 3094 3095 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 3096 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 3097 mac = (struct bwi_mac *)sc->sc_cur_regwin; 3098 3099 wh = mtod(m, struct ieee80211_frame *); 3100 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 3101 3102 /* Get 802.11 frame len before prepending TX header */ 3103 pkt_len = m->m_pkthdr.len + IEEE80211_CRC_LEN; 3104 3105 /* 3106 * Find TX rate 3107 */ 3108 rate = params->ibp_rate0; 3109 if (!ieee80211_isratevalid(ic->ic_rt, rate)) { 3110 /* XXX fall back to mcast/mgmt rate? */ 3111 m_freem(m); 3112 return EINVAL; 3113 } 3114 if (params->ibp_try1 != 0) { 3115 rate_fb = params->ibp_rate1; 3116 if (!ieee80211_isratevalid(ic->ic_rt, rate_fb)) { 3117 /* XXX fall back to rate0? */ 3118 m_freem(m); 3119 return EINVAL; 3120 } 3121 } else 3122 rate_fb = rate; 3123 tb->tb_rate[0] = rate; 3124 tb->tb_rate[1] = rate_fb; 3125 sc->sc_tx_rate = rate; 3126 3127 /* 3128 * TX radio tap 3129 */ 3130 if (ieee80211_radiotap_active_vap(vap)) { 3131 sc->sc_tx_th.wt_flags = 0; 3132 /* XXX IEEE80211_BPF_CRYPTO */ 3133 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) 3134 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP; 3135 if (params->ibp_flags & IEEE80211_BPF_SHORTPRE) 3136 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 3137 sc->sc_tx_th.wt_rate = rate; 3138 3139 ieee80211_radiotap_tx(vap, m); 3140 } 3141 3142 /* 3143 * Setup the embedded TX header 3144 */ 3145 M_PREPEND(m, sizeof(*hdr), M_NOWAIT); 3146 if (m == NULL) { 3147 device_printf(sc->sc_dev, "%s: prepend TX header failed\n", 3148 __func__); 3149 return ENOBUFS; 3150 } 3151 hdr = mtod(m, struct bwi_txbuf_hdr *); 3152 3153 bzero(hdr, sizeof(*hdr)); 3154 3155 bcopy(wh->i_fc, hdr->txh_fc, sizeof(hdr->txh_fc)); 3156 bcopy(wh->i_addr1, hdr->txh_addr1, sizeof(hdr->txh_addr1)); 3157 3158 mac_ctrl = BWI_TXH_MAC_C_HWSEQ | BWI_TXH_MAC_C_FIRST_FRAG; 3159 if (!ismcast && (params->ibp_flags & IEEE80211_BPF_NOACK) == 0) { 3160 uint16_t dur; 3161 3162 dur = ieee80211_ack_duration(sc->sc_rates, rate_fb, 0); 3163 3164 hdr->txh_fb_duration = htole16(dur); 3165 mac_ctrl |= BWI_TXH_MAC_C_ACK; 3166 } 3167 3168 hdr->txh_id = __SHIFTIN(BWI_TX_DATA_RING, BWI_TXH_ID_RING_MASK) | 3169 __SHIFTIN(idx, BWI_TXH_ID_IDX_MASK); 3170 3171 bwi_plcp_header(sc->sc_rates, hdr->txh_plcp, pkt_len, rate); 3172 bwi_plcp_header(sc->sc_rates, hdr->txh_fb_plcp, pkt_len, rate_fb); 3173 3174 phy_ctrl = __SHIFTIN(mac->mac_rf.rf_ant_mode, 3175 BWI_TXH_PHY_C_ANTMODE_MASK); 3176 if (ieee80211_rate2phytype(sc->sc_rates, rate) == IEEE80211_T_OFDM) { 3177 phy_ctrl |= BWI_TXH_PHY_C_OFDM; 3178 mac_ctrl |= BWI_TXH_MAC_C_FB_OFDM; 3179 } else if (params->ibp_flags & IEEE80211_BPF_SHORTPRE) 3180 phy_ctrl |= BWI_TXH_PHY_C_SHPREAMBLE; 3181 3182 hdr->txh_mac_ctrl = htole32(mac_ctrl); 3183 hdr->txh_phy_ctrl = htole16(phy_ctrl); 3184 3185 /* Catch any further usage */ 3186 hdr = NULL; 3187 wh = NULL; 3188 3189 /* DMA load */ 3190 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m, 3191 bwi_dma_buf_addr, &paddr, BUS_DMA_NOWAIT); 3192 if (error != 0) { 3193 struct mbuf *m_new; 3194 3195 if (error != EFBIG) { 3196 device_printf(sc->sc_dev, 3197 "%s: can't load TX buffer (1) %d\n", 3198 __func__, error); 3199 goto back; 3200 } 3201 m_new = m_defrag(m, M_NOWAIT); 3202 if (m_new == NULL) { 3203 device_printf(sc->sc_dev, 3204 "%s: can't defrag TX buffer\n", __func__); 3205 error = ENOBUFS; 3206 goto back; 3207 } 3208 m = m_new; 3209 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m, 3210 bwi_dma_buf_addr, &paddr, 3211 BUS_DMA_NOWAIT); 3212 if (error) { 3213 device_printf(sc->sc_dev, 3214 "%s: can't load TX buffer (2) %d\n", 3215 __func__, error); 3216 goto back; 3217 } 3218 } 3219 3220 bus_dmamap_sync(sc->sc_buf_dtag, tb->tb_dmap, BUS_DMASYNC_PREWRITE); 3221 3222 tb->tb_mbuf = m; 3223 tb->tb_ni = ni; 3224 3225 DPRINTF(sc, BWI_DBG_TX, "idx %d, pkt_len %d, buflen %d\n", 3226 idx, pkt_len, m->m_pkthdr.len); 3227 3228 /* Setup TX descriptor */ 3229 sc->sc_setup_txdesc(sc, rd, idx, paddr, m->m_pkthdr.len); 3230 bus_dmamap_sync(sc->sc_txring_dtag, rd->rdata_dmap, 3231 BUS_DMASYNC_PREWRITE); 3232 3233 /* Kick start */ 3234 sc->sc_start_tx(sc, rd->rdata_txrx_ctrl, idx); 3235 back: 3236 if (error) 3237 m_freem(m); 3238 return error; 3239 } 3240 3241 static void 3242 bwi_start_tx32(struct bwi_softc *sc, uint32_t tx_ctrl, int idx) 3243 { 3244 idx = (idx + 1) % BWI_TX_NDESC; 3245 CSR_WRITE_4(sc, tx_ctrl + BWI_TX32_INDEX, 3246 idx * sizeof(struct bwi_desc32)); 3247 } 3248 3249 static void 3250 bwi_start_tx64(struct bwi_softc *sc, uint32_t tx_ctrl, int idx) 3251 { 3252 /* TODO:64 */ 3253 } 3254 3255 static void 3256 bwi_txeof_status32(struct bwi_softc *sc) 3257 { 3258 uint32_t val, ctrl_base; 3259 int end_idx; 3260 3261 ctrl_base = sc->sc_txstats->stats_ctrl_base; 3262 3263 val = CSR_READ_4(sc, ctrl_base + BWI_RX32_STATUS); 3264 end_idx = __SHIFTOUT(val, BWI_RX32_STATUS_INDEX_MASK) / 3265 sizeof(struct bwi_desc32); 3266 3267 bwi_txeof_status(sc, end_idx); 3268 3269 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_INDEX, 3270 end_idx * sizeof(struct bwi_desc32)); 3271 3272 bwi_start_locked(sc); 3273 } 3274 3275 static void 3276 bwi_txeof_status64(struct bwi_softc *sc) 3277 { 3278 /* TODO:64 */ 3279 } 3280 3281 static void 3282 _bwi_txeof(struct bwi_softc *sc, uint16_t tx_id, int acked, int data_txcnt) 3283 { 3284 struct bwi_txbuf_data *tbd; 3285 struct bwi_txbuf *tb; 3286 int ring_idx, buf_idx; 3287 struct ieee80211_node *ni; 3288 struct ieee80211vap *vap; 3289 3290 if (tx_id == 0) { 3291 device_printf(sc->sc_dev, "%s: zero tx id\n", __func__); 3292 return; 3293 } 3294 3295 ring_idx = __SHIFTOUT(tx_id, BWI_TXH_ID_RING_MASK); 3296 buf_idx = __SHIFTOUT(tx_id, BWI_TXH_ID_IDX_MASK); 3297 3298 KASSERT(ring_idx == BWI_TX_DATA_RING, ("ring_idx %d", ring_idx)); 3299 KASSERT(buf_idx < BWI_TX_NDESC, ("buf_idx %d", buf_idx)); 3300 3301 tbd = &sc->sc_tx_bdata[ring_idx]; 3302 KASSERT(tbd->tbd_used > 0, ("tbd_used %d", tbd->tbd_used)); 3303 tbd->tbd_used--; 3304 3305 tb = &tbd->tbd_buf[buf_idx]; 3306 DPRINTF(sc, BWI_DBG_TXEOF, "txeof idx %d, " 3307 "acked %d, data_txcnt %d, ni %p\n", 3308 buf_idx, acked, data_txcnt, tb->tb_ni); 3309 3310 bus_dmamap_unload(sc->sc_buf_dtag, tb->tb_dmap); 3311 3312 if ((ni = tb->tb_ni) != NULL) { 3313 const struct bwi_txbuf_hdr *hdr = 3314 mtod(tb->tb_mbuf, const struct bwi_txbuf_hdr *); 3315 vap = ni->ni_vap; 3316 3317 /* NB: update rate control only for unicast frames */ 3318 if (hdr->txh_mac_ctrl & htole32(BWI_TXH_MAC_C_ACK)) { 3319 /* 3320 * Feed back 'acked and data_txcnt'. Note that the 3321 * generic AMRR code only understands one tx rate 3322 * and the estimator doesn't handle real retry counts 3323 * well so to avoid over-aggressive downshifting we 3324 * treat any number of retries as "1". 3325 */ 3326 ieee80211_ratectl_tx_complete(vap, ni, 3327 (data_txcnt > 1) ? IEEE80211_RATECTL_TX_SUCCESS : 3328 IEEE80211_RATECTL_TX_FAILURE, &acked, NULL); 3329 } 3330 ieee80211_tx_complete(ni, tb->tb_mbuf, !acked); 3331 tb->tb_ni = NULL; 3332 } else 3333 m_freem(tb->tb_mbuf); 3334 tb->tb_mbuf = NULL; 3335 3336 if (tbd->tbd_used == 0) 3337 sc->sc_tx_timer = 0; 3338 } 3339 3340 static void 3341 bwi_txeof_status(struct bwi_softc *sc, int end_idx) 3342 { 3343 struct bwi_txstats_data *st = sc->sc_txstats; 3344 int idx; 3345 3346 bus_dmamap_sync(st->stats_dtag, st->stats_dmap, BUS_DMASYNC_POSTREAD); 3347 3348 idx = st->stats_idx; 3349 while (idx != end_idx) { 3350 const struct bwi_txstats *stats = &st->stats[idx]; 3351 3352 if ((stats->txs_flags & BWI_TXS_F_PENDING) == 0) { 3353 int data_txcnt; 3354 3355 data_txcnt = __SHIFTOUT(stats->txs_txcnt, 3356 BWI_TXS_TXCNT_DATA); 3357 _bwi_txeof(sc, le16toh(stats->txs_id), 3358 stats->txs_flags & BWI_TXS_F_ACKED, 3359 data_txcnt); 3360 } 3361 idx = (idx + 1) % BWI_TXSTATS_NDESC; 3362 } 3363 st->stats_idx = idx; 3364 } 3365 3366 static void 3367 bwi_txeof(struct bwi_softc *sc) 3368 { 3369 3370 for (;;) { 3371 uint32_t tx_status0, tx_status1; 3372 uint16_t tx_id; 3373 int data_txcnt; 3374 3375 tx_status0 = CSR_READ_4(sc, BWI_TXSTATUS0); 3376 if ((tx_status0 & BWI_TXSTATUS0_VALID) == 0) 3377 break; 3378 tx_status1 = CSR_READ_4(sc, BWI_TXSTATUS1); 3379 3380 tx_id = __SHIFTOUT(tx_status0, BWI_TXSTATUS0_TXID_MASK); 3381 data_txcnt = __SHIFTOUT(tx_status0, 3382 BWI_TXSTATUS0_DATA_TXCNT_MASK); 3383 3384 if (tx_status0 & (BWI_TXSTATUS0_AMPDU | BWI_TXSTATUS0_PENDING)) 3385 continue; 3386 3387 _bwi_txeof(sc, le16toh(tx_id), tx_status0 & BWI_TXSTATUS0_ACKED, 3388 data_txcnt); 3389 } 3390 3391 bwi_start_locked(sc); 3392 } 3393 3394 static int 3395 bwi_bbp_power_on(struct bwi_softc *sc, enum bwi_clock_mode clk_mode) 3396 { 3397 bwi_power_on(sc, 1); 3398 return bwi_set_clock_mode(sc, clk_mode); 3399 } 3400 3401 static void 3402 bwi_bbp_power_off(struct bwi_softc *sc) 3403 { 3404 bwi_set_clock_mode(sc, BWI_CLOCK_MODE_SLOW); 3405 bwi_power_off(sc, 1); 3406 } 3407 3408 static int 3409 bwi_get_pwron_delay(struct bwi_softc *sc) 3410 { 3411 struct bwi_regwin *com, *old; 3412 struct bwi_clock_freq freq; 3413 uint32_t val; 3414 int error; 3415 3416 com = &sc->sc_com_regwin; 3417 KASSERT(BWI_REGWIN_EXIST(com), ("no regwin")); 3418 3419 if ((sc->sc_cap & BWI_CAP_CLKMODE) == 0) 3420 return 0; 3421 3422 error = bwi_regwin_switch(sc, com, &old); 3423 if (error) 3424 return error; 3425 3426 bwi_get_clock_freq(sc, &freq); 3427 3428 val = CSR_READ_4(sc, BWI_PLL_ON_DELAY); 3429 sc->sc_pwron_delay = howmany((val + 2) * 1000000, freq.clkfreq_min); 3430 DPRINTF(sc, BWI_DBG_ATTACH, "power on delay %u\n", sc->sc_pwron_delay); 3431 3432 return bwi_regwin_switch(sc, old, NULL); 3433 } 3434 3435 static int 3436 bwi_bus_attach(struct bwi_softc *sc) 3437 { 3438 struct bwi_regwin *bus, *old; 3439 int error; 3440 3441 bus = &sc->sc_bus_regwin; 3442 3443 error = bwi_regwin_switch(sc, bus, &old); 3444 if (error) 3445 return error; 3446 3447 if (!bwi_regwin_is_enabled(sc, bus)) 3448 bwi_regwin_enable(sc, bus, 0); 3449 3450 /* Disable interripts */ 3451 CSR_WRITE_4(sc, BWI_INTRVEC, 0); 3452 3453 return bwi_regwin_switch(sc, old, NULL); 3454 } 3455 3456 static const char * 3457 bwi_regwin_name(const struct bwi_regwin *rw) 3458 { 3459 switch (rw->rw_type) { 3460 case BWI_REGWIN_T_COM: 3461 return "COM"; 3462 case BWI_REGWIN_T_BUSPCI: 3463 return "PCI"; 3464 case BWI_REGWIN_T_MAC: 3465 return "MAC"; 3466 case BWI_REGWIN_T_BUSPCIE: 3467 return "PCIE"; 3468 } 3469 panic("unknown regwin type 0x%04x\n", rw->rw_type); 3470 return NULL; 3471 } 3472 3473 static uint32_t 3474 bwi_regwin_disable_bits(struct bwi_softc *sc) 3475 { 3476 uint32_t busrev; 3477 3478 /* XXX cache this */ 3479 busrev = __SHIFTOUT(CSR_READ_4(sc, BWI_ID_LO), BWI_ID_LO_BUSREV_MASK); 3480 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT | BWI_DBG_MISC, 3481 "bus rev %u\n", busrev); 3482 3483 if (busrev == BWI_BUSREV_0) 3484 return BWI_STATE_LO_DISABLE1; 3485 else if (busrev == BWI_BUSREV_1) 3486 return BWI_STATE_LO_DISABLE2; 3487 else 3488 return (BWI_STATE_LO_DISABLE1 | BWI_STATE_LO_DISABLE2); 3489 } 3490 3491 int 3492 bwi_regwin_is_enabled(struct bwi_softc *sc, struct bwi_regwin *rw) 3493 { 3494 uint32_t val, disable_bits; 3495 3496 disable_bits = bwi_regwin_disable_bits(sc); 3497 val = CSR_READ_4(sc, BWI_STATE_LO); 3498 3499 if ((val & (BWI_STATE_LO_CLOCK | 3500 BWI_STATE_LO_RESET | 3501 disable_bits)) == BWI_STATE_LO_CLOCK) { 3502 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT, "%s is enabled\n", 3503 bwi_regwin_name(rw)); 3504 return 1; 3505 } else { 3506 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT, "%s is disabled\n", 3507 bwi_regwin_name(rw)); 3508 return 0; 3509 } 3510 } 3511 3512 void 3513 bwi_regwin_disable(struct bwi_softc *sc, struct bwi_regwin *rw, uint32_t flags) 3514 { 3515 uint32_t state_lo, disable_bits; 3516 int i; 3517 3518 state_lo = CSR_READ_4(sc, BWI_STATE_LO); 3519 3520 /* 3521 * If current regwin is in 'reset' state, it was already disabled. 3522 */ 3523 if (state_lo & BWI_STATE_LO_RESET) { 3524 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT, 3525 "%s was already disabled\n", bwi_regwin_name(rw)); 3526 return; 3527 } 3528 3529 disable_bits = bwi_regwin_disable_bits(sc); 3530 3531 /* 3532 * Disable normal clock 3533 */ 3534 state_lo = BWI_STATE_LO_CLOCK | disable_bits; 3535 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo); 3536 3537 /* 3538 * Wait until normal clock is disabled 3539 */ 3540 #define NRETRY 1000 3541 for (i = 0; i < NRETRY; ++i) { 3542 state_lo = CSR_READ_4(sc, BWI_STATE_LO); 3543 if (state_lo & disable_bits) 3544 break; 3545 DELAY(10); 3546 } 3547 if (i == NRETRY) { 3548 device_printf(sc->sc_dev, "%s disable clock timeout\n", 3549 bwi_regwin_name(rw)); 3550 } 3551 3552 for (i = 0; i < NRETRY; ++i) { 3553 uint32_t state_hi; 3554 3555 state_hi = CSR_READ_4(sc, BWI_STATE_HI); 3556 if ((state_hi & BWI_STATE_HI_BUSY) == 0) 3557 break; 3558 DELAY(10); 3559 } 3560 if (i == NRETRY) { 3561 device_printf(sc->sc_dev, "%s wait BUSY unset timeout\n", 3562 bwi_regwin_name(rw)); 3563 } 3564 #undef NRETRY 3565 3566 /* 3567 * Reset and disable regwin with gated clock 3568 */ 3569 state_lo = BWI_STATE_LO_RESET | disable_bits | 3570 BWI_STATE_LO_CLOCK | BWI_STATE_LO_GATED_CLOCK | 3571 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK); 3572 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo); 3573 3574 /* Flush pending bus write */ 3575 CSR_READ_4(sc, BWI_STATE_LO); 3576 DELAY(1); 3577 3578 /* Reset and disable regwin */ 3579 state_lo = BWI_STATE_LO_RESET | disable_bits | 3580 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK); 3581 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo); 3582 3583 /* Flush pending bus write */ 3584 CSR_READ_4(sc, BWI_STATE_LO); 3585 DELAY(1); 3586 } 3587 3588 void 3589 bwi_regwin_enable(struct bwi_softc *sc, struct bwi_regwin *rw, uint32_t flags) 3590 { 3591 uint32_t state_lo, state_hi, imstate; 3592 3593 bwi_regwin_disable(sc, rw, flags); 3594 3595 /* Reset regwin with gated clock */ 3596 state_lo = BWI_STATE_LO_RESET | 3597 BWI_STATE_LO_CLOCK | 3598 BWI_STATE_LO_GATED_CLOCK | 3599 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK); 3600 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo); 3601 3602 /* Flush pending bus write */ 3603 CSR_READ_4(sc, BWI_STATE_LO); 3604 DELAY(1); 3605 3606 state_hi = CSR_READ_4(sc, BWI_STATE_HI); 3607 if (state_hi & BWI_STATE_HI_SERROR) 3608 CSR_WRITE_4(sc, BWI_STATE_HI, 0); 3609 3610 imstate = CSR_READ_4(sc, BWI_IMSTATE); 3611 if (imstate & (BWI_IMSTATE_INBAND_ERR | BWI_IMSTATE_TIMEOUT)) { 3612 imstate &= ~(BWI_IMSTATE_INBAND_ERR | BWI_IMSTATE_TIMEOUT); 3613 CSR_WRITE_4(sc, BWI_IMSTATE, imstate); 3614 } 3615 3616 /* Enable regwin with gated clock */ 3617 state_lo = BWI_STATE_LO_CLOCK | 3618 BWI_STATE_LO_GATED_CLOCK | 3619 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK); 3620 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo); 3621 3622 /* Flush pending bus write */ 3623 CSR_READ_4(sc, BWI_STATE_LO); 3624 DELAY(1); 3625 3626 /* Enable regwin with normal clock */ 3627 state_lo = BWI_STATE_LO_CLOCK | 3628 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK); 3629 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo); 3630 3631 /* Flush pending bus write */ 3632 CSR_READ_4(sc, BWI_STATE_LO); 3633 DELAY(1); 3634 } 3635 3636 static void 3637 bwi_set_bssid(struct bwi_softc *sc, const uint8_t *bssid) 3638 { 3639 struct bwi_mac *mac; 3640 struct bwi_myaddr_bssid buf; 3641 const uint8_t *p; 3642 uint32_t val; 3643 int n, i; 3644 3645 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 3646 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 3647 mac = (struct bwi_mac *)sc->sc_cur_regwin; 3648 3649 bwi_set_addr_filter(sc, BWI_ADDR_FILTER_BSSID, bssid); 3650 3651 bcopy(sc->sc_ic.ic_macaddr, buf.myaddr, sizeof(buf.myaddr)); 3652 bcopy(bssid, buf.bssid, sizeof(buf.bssid)); 3653 3654 n = sizeof(buf) / sizeof(val); 3655 p = (const uint8_t *)&buf; 3656 for (i = 0; i < n; ++i) { 3657 int j; 3658 3659 val = 0; 3660 for (j = 0; j < sizeof(val); ++j) 3661 val |= ((uint32_t)(*p++)) << (j * 8); 3662 3663 TMPLT_WRITE_4(mac, 0x20 + (i * sizeof(val)), val); 3664 } 3665 } 3666 3667 static void 3668 bwi_updateslot(struct ieee80211com *ic) 3669 { 3670 struct bwi_softc *sc = ic->ic_softc; 3671 struct bwi_mac *mac; 3672 3673 BWI_LOCK(sc); 3674 if (sc->sc_flags & BWI_F_RUNNING) { 3675 DPRINTF(sc, BWI_DBG_80211, "%s\n", __func__); 3676 3677 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 3678 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 3679 mac = (struct bwi_mac *)sc->sc_cur_regwin; 3680 3681 bwi_mac_updateslot(mac, (ic->ic_flags & IEEE80211_F_SHSLOT)); 3682 } 3683 BWI_UNLOCK(sc); 3684 } 3685 3686 static void 3687 bwi_calibrate(void *xsc) 3688 { 3689 struct bwi_softc *sc = xsc; 3690 struct bwi_mac *mac; 3691 3692 BWI_ASSERT_LOCKED(sc); 3693 3694 KASSERT(sc->sc_ic.ic_opmode != IEEE80211_M_MONITOR, 3695 ("opmode %d", sc->sc_ic.ic_opmode)); 3696 3697 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 3698 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 3699 mac = (struct bwi_mac *)sc->sc_cur_regwin; 3700 3701 bwi_mac_calibrate_txpower(mac, sc->sc_txpwrcb_type); 3702 sc->sc_txpwrcb_type = BWI_TXPWR_CALIB; 3703 3704 /* XXX 15 seconds */ 3705 callout_reset(&sc->sc_calib_ch, hz * 15, bwi_calibrate, sc); 3706 } 3707 3708 static int 3709 bwi_calc_rssi(struct bwi_softc *sc, const struct bwi_rxbuf_hdr *hdr) 3710 { 3711 struct bwi_mac *mac; 3712 3713 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 3714 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 3715 mac = (struct bwi_mac *)sc->sc_cur_regwin; 3716 3717 return bwi_rf_calc_rssi(mac, hdr); 3718 } 3719 3720 static int 3721 bwi_calc_noise(struct bwi_softc *sc) 3722 { 3723 struct bwi_mac *mac; 3724 3725 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 3726 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 3727 mac = (struct bwi_mac *)sc->sc_cur_regwin; 3728 3729 return bwi_rf_calc_noise(mac); 3730 } 3731 3732 static __inline uint8_t 3733 bwi_plcp2rate(const uint32_t plcp0, enum ieee80211_phytype type) 3734 { 3735 uint32_t plcp = le32toh(plcp0) & IEEE80211_OFDM_PLCP_RATE_MASK; 3736 return (ieee80211_plcp2rate(plcp, type)); 3737 } 3738 3739 static void 3740 bwi_rx_radiotap(struct bwi_softc *sc, struct mbuf *m, 3741 struct bwi_rxbuf_hdr *hdr, const void *plcp, int rate, int rssi, int noise) 3742 { 3743 const struct ieee80211_frame_min *wh; 3744 3745 sc->sc_rx_th.wr_flags = IEEE80211_RADIOTAP_F_FCS; 3746 if (htole16(hdr->rxh_flags1) & BWI_RXH_F1_SHPREAMBLE) 3747 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 3748 3749 wh = mtod(m, const struct ieee80211_frame_min *); 3750 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) 3751 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_WEP; 3752 3753 sc->sc_rx_th.wr_tsf = hdr->rxh_tsf; /* No endian convertion */ 3754 sc->sc_rx_th.wr_rate = rate; 3755 sc->sc_rx_th.wr_antsignal = rssi; 3756 sc->sc_rx_th.wr_antnoise = noise; 3757 } 3758 3759 static void 3760 bwi_led_attach(struct bwi_softc *sc) 3761 { 3762 const uint8_t *led_act = NULL; 3763 uint16_t gpio, val[BWI_LED_MAX]; 3764 int i; 3765 3766 for (i = 0; i < nitems(bwi_vendor_led_act); ++i) { 3767 if (sc->sc_pci_subvid == bwi_vendor_led_act[i].vid) { 3768 led_act = bwi_vendor_led_act[i].led_act; 3769 break; 3770 } 3771 } 3772 if (led_act == NULL) 3773 led_act = bwi_default_led_act; 3774 3775 gpio = bwi_read_sprom(sc, BWI_SPROM_GPIO01); 3776 val[0] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_0); 3777 val[1] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_1); 3778 3779 gpio = bwi_read_sprom(sc, BWI_SPROM_GPIO23); 3780 val[2] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_2); 3781 val[3] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_3); 3782 3783 for (i = 0; i < BWI_LED_MAX; ++i) { 3784 struct bwi_led *led = &sc->sc_leds[i]; 3785 3786 if (val[i] == 0xff) { 3787 led->l_act = led_act[i]; 3788 } else { 3789 if (val[i] & BWI_LED_ACT_LOW) 3790 led->l_flags |= BWI_LED_F_ACTLOW; 3791 led->l_act = __SHIFTOUT(val[i], BWI_LED_ACT_MASK); 3792 } 3793 led->l_mask = (1 << i); 3794 3795 if (led->l_act == BWI_LED_ACT_BLINK_SLOW || 3796 led->l_act == BWI_LED_ACT_BLINK_POLL || 3797 led->l_act == BWI_LED_ACT_BLINK) { 3798 led->l_flags |= BWI_LED_F_BLINK; 3799 if (led->l_act == BWI_LED_ACT_BLINK_POLL) 3800 led->l_flags |= BWI_LED_F_POLLABLE; 3801 else if (led->l_act == BWI_LED_ACT_BLINK_SLOW) 3802 led->l_flags |= BWI_LED_F_SLOW; 3803 3804 if (sc->sc_blink_led == NULL) { 3805 sc->sc_blink_led = led; 3806 if (led->l_flags & BWI_LED_F_SLOW) 3807 BWI_LED_SLOWDOWN(sc->sc_led_idle); 3808 } 3809 } 3810 3811 DPRINTF(sc, BWI_DBG_LED | BWI_DBG_ATTACH, 3812 "%dth led, act %d, lowact %d\n", i, 3813 led->l_act, led->l_flags & BWI_LED_F_ACTLOW); 3814 } 3815 callout_init_mtx(&sc->sc_led_blink_ch, &sc->sc_mtx, 0); 3816 } 3817 3818 static __inline uint16_t 3819 bwi_led_onoff(const struct bwi_led *led, uint16_t val, int on) 3820 { 3821 if (led->l_flags & BWI_LED_F_ACTLOW) 3822 on = !on; 3823 if (on) 3824 val |= led->l_mask; 3825 else 3826 val &= ~led->l_mask; 3827 return val; 3828 } 3829 3830 static void 3831 bwi_led_newstate(struct bwi_softc *sc, enum ieee80211_state nstate) 3832 { 3833 struct ieee80211com *ic = &sc->sc_ic; 3834 uint16_t val; 3835 int i; 3836 3837 if (nstate == IEEE80211_S_INIT) { 3838 callout_stop(&sc->sc_led_blink_ch); 3839 sc->sc_led_blinking = 0; 3840 } 3841 3842 if ((sc->sc_flags & BWI_F_RUNNING) == 0) 3843 return; 3844 3845 val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL); 3846 for (i = 0; i < BWI_LED_MAX; ++i) { 3847 struct bwi_led *led = &sc->sc_leds[i]; 3848 int on; 3849 3850 if (led->l_act == BWI_LED_ACT_UNKN || 3851 led->l_act == BWI_LED_ACT_NULL) 3852 continue; 3853 3854 if ((led->l_flags & BWI_LED_F_BLINK) && 3855 nstate != IEEE80211_S_INIT) 3856 continue; 3857 3858 switch (led->l_act) { 3859 case BWI_LED_ACT_ON: /* Always on */ 3860 on = 1; 3861 break; 3862 case BWI_LED_ACT_OFF: /* Always off */ 3863 case BWI_LED_ACT_5GHZ: /* TODO: 11A */ 3864 on = 0; 3865 break; 3866 default: 3867 on = 1; 3868 switch (nstate) { 3869 case IEEE80211_S_INIT: 3870 on = 0; 3871 break; 3872 case IEEE80211_S_RUN: 3873 if (led->l_act == BWI_LED_ACT_11G && 3874 ic->ic_curmode != IEEE80211_MODE_11G) 3875 on = 0; 3876 break; 3877 default: 3878 if (led->l_act == BWI_LED_ACT_ASSOC) 3879 on = 0; 3880 break; 3881 } 3882 break; 3883 } 3884 3885 val = bwi_led_onoff(led, val, on); 3886 } 3887 CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val); 3888 } 3889 static void 3890 bwi_led_event(struct bwi_softc *sc, int event) 3891 { 3892 struct bwi_led *led = sc->sc_blink_led; 3893 int rate; 3894 3895 if (event == BWI_LED_EVENT_POLL) { 3896 if ((led->l_flags & BWI_LED_F_POLLABLE) == 0) 3897 return; 3898 if (ticks - sc->sc_led_ticks < sc->sc_led_idle) 3899 return; 3900 } 3901 3902 sc->sc_led_ticks = ticks; 3903 if (sc->sc_led_blinking) 3904 return; 3905 3906 switch (event) { 3907 case BWI_LED_EVENT_RX: 3908 rate = sc->sc_rx_rate; 3909 break; 3910 case BWI_LED_EVENT_TX: 3911 rate = sc->sc_tx_rate; 3912 break; 3913 case BWI_LED_EVENT_POLL: 3914 rate = 0; 3915 break; 3916 default: 3917 panic("unknown LED event %d\n", event); 3918 break; 3919 } 3920 bwi_led_blink_start(sc, bwi_led_duration[rate].on_dur, 3921 bwi_led_duration[rate].off_dur); 3922 } 3923 3924 static void 3925 bwi_led_blink_start(struct bwi_softc *sc, int on_dur, int off_dur) 3926 { 3927 struct bwi_led *led = sc->sc_blink_led; 3928 uint16_t val; 3929 3930 val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL); 3931 val = bwi_led_onoff(led, val, 1); 3932 CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val); 3933 3934 if (led->l_flags & BWI_LED_F_SLOW) { 3935 BWI_LED_SLOWDOWN(on_dur); 3936 BWI_LED_SLOWDOWN(off_dur); 3937 } 3938 3939 sc->sc_led_blinking = 1; 3940 sc->sc_led_blink_offdur = off_dur; 3941 3942 callout_reset(&sc->sc_led_blink_ch, on_dur, bwi_led_blink_next, sc); 3943 } 3944 3945 static void 3946 bwi_led_blink_next(void *xsc) 3947 { 3948 struct bwi_softc *sc = xsc; 3949 uint16_t val; 3950 3951 val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL); 3952 val = bwi_led_onoff(sc->sc_blink_led, val, 0); 3953 CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val); 3954 3955 callout_reset(&sc->sc_led_blink_ch, sc->sc_led_blink_offdur, 3956 bwi_led_blink_end, sc); 3957 } 3958 3959 static void 3960 bwi_led_blink_end(void *xsc) 3961 { 3962 struct bwi_softc *sc = xsc; 3963 sc->sc_led_blinking = 0; 3964 } 3965 3966 static void 3967 bwi_restart(void *xsc, int pending) 3968 { 3969 struct bwi_softc *sc = xsc; 3970 3971 device_printf(sc->sc_dev, "%s begin, help!\n", __func__); 3972 BWI_LOCK(sc); 3973 bwi_init_statechg(sc, 0); 3974 #if 0 3975 bwi_start_locked(sc); 3976 #endif 3977 BWI_UNLOCK(sc); 3978 } 3979