1 /* 2 * Copyright (c) 2007 The DragonFly Project. All rights reserved. 3 * 4 * This code is derived from software contributed to The DragonFly Project 5 * by Sepherosa Ziehau <sepherosa@gmail.com> 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in 15 * the documentation and/or other materials provided with the 16 * distribution. 17 * 3. Neither the name of The DragonFly Project nor the names of its 18 * contributors may be used to endorse or promote products derived 19 * from this software without specific, prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 24 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 25 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING, 27 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 29 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 32 * SUCH DAMAGE. 33 * 34 * $DragonFly: src/sys/dev/netif/bwi/if_bwi.c,v 1.19 2008/02/15 11:15:38 sephe Exp $ 35 */ 36 37 #include <sys/cdefs.h> 38 __FBSDID("$FreeBSD$"); 39 40 #include "opt_inet.h" 41 #include "opt_bwi.h" 42 43 #include <sys/param.h> 44 #include <sys/endian.h> 45 #include <sys/kernel.h> 46 #include <sys/bus.h> 47 #include <sys/malloc.h> 48 #include <sys/proc.h> 49 #include <sys/rman.h> 50 #include <sys/socket.h> 51 #include <sys/sockio.h> 52 #include <sys/sysctl.h> 53 #include <sys/systm.h> 54 #include <sys/taskqueue.h> 55 56 #include <net/if.h> 57 #include <net/if_dl.h> 58 #include <net/if_media.h> 59 #include <net/if_types.h> 60 #include <net/if_arp.h> 61 #include <net/ethernet.h> 62 #include <net/if_llc.h> 63 64 #include <net80211/ieee80211_var.h> 65 #include <net80211/ieee80211_radiotap.h> 66 #include <net80211/ieee80211_regdomain.h> 67 #include <net80211/ieee80211_amrr.h> 68 #include <net80211/ieee80211_phy.h> 69 70 #include <net/bpf.h> 71 72 #ifdef INET 73 #include <netinet/in.h> 74 #include <netinet/if_ether.h> 75 #endif 76 77 #include <machine/bus.h> 78 79 #include <dev/pci/pcivar.h> 80 #include <dev/pci/pcireg.h> 81 82 #include <dev/bwi/bitops.h> 83 #include <dev/bwi/if_bwireg.h> 84 #include <dev/bwi/if_bwivar.h> 85 #include <dev/bwi/bwimac.h> 86 #include <dev/bwi/bwirf.h> 87 88 struct bwi_clock_freq { 89 u_int clkfreq_min; 90 u_int clkfreq_max; 91 }; 92 93 struct bwi_myaddr_bssid { 94 uint8_t myaddr[IEEE80211_ADDR_LEN]; 95 uint8_t bssid[IEEE80211_ADDR_LEN]; 96 } __packed; 97 98 static struct ieee80211vap *bwi_vap_create(struct ieee80211com *, 99 const char [IFNAMSIZ], int, int, int, 100 const uint8_t [IEEE80211_ADDR_LEN], 101 const uint8_t [IEEE80211_ADDR_LEN]); 102 static void bwi_vap_delete(struct ieee80211vap *); 103 static void bwi_init(void *); 104 static int bwi_ioctl(struct ifnet *, u_long, caddr_t); 105 static void bwi_start(struct ifnet *); 106 static void bwi_start_locked(struct ifnet *); 107 static int bwi_raw_xmit(struct ieee80211_node *, struct mbuf *, 108 const struct ieee80211_bpf_params *); 109 static void bwi_watchdog(void *); 110 static void bwi_scan_start(struct ieee80211com *); 111 static void bwi_set_channel(struct ieee80211com *); 112 static void bwi_scan_end(struct ieee80211com *); 113 static int bwi_newstate(struct ieee80211vap *, enum ieee80211_state, int); 114 static void bwi_updateslot(struct ifnet *); 115 static struct ieee80211_node *bwi_node_alloc(struct ieee80211vap *, 116 const uint8_t [IEEE80211_ADDR_LEN]); 117 static void bwi_newassoc(struct ieee80211_node *, int); 118 static int bwi_media_change(struct ifnet *); 119 120 static void bwi_calibrate(void *); 121 122 static int bwi_calc_rssi(struct bwi_softc *, const struct bwi_rxbuf_hdr *); 123 static int bwi_calc_noise(struct bwi_softc *); 124 static __inline uint8_t bwi_ofdm_plcp2rate(const uint32_t *); 125 static __inline uint8_t bwi_ds_plcp2rate(const struct ieee80211_ds_plcp_hdr *); 126 static void bwi_rx_radiotap(struct bwi_softc *, struct mbuf *, 127 struct bwi_rxbuf_hdr *, const void *, int, int, int); 128 129 static void bwi_restart(void *, int); 130 static void bwi_init_statechg(struct bwi_softc *, int); 131 static void bwi_stop(struct bwi_softc *, int); 132 static void bwi_stop_locked(struct bwi_softc *, int); 133 static int bwi_newbuf(struct bwi_softc *, int, int); 134 static int bwi_encap(struct bwi_softc *, int, struct mbuf *, 135 struct ieee80211_node *); 136 static int bwi_encap_raw(struct bwi_softc *, int, struct mbuf *, 137 struct ieee80211_node *, 138 const struct ieee80211_bpf_params *); 139 140 static void bwi_init_rxdesc_ring32(struct bwi_softc *, uint32_t, 141 bus_addr_t, int, int); 142 static void bwi_reset_rx_ring32(struct bwi_softc *, uint32_t); 143 144 static int bwi_init_tx_ring32(struct bwi_softc *, int); 145 static int bwi_init_rx_ring32(struct bwi_softc *); 146 static int bwi_init_txstats32(struct bwi_softc *); 147 static void bwi_free_tx_ring32(struct bwi_softc *, int); 148 static void bwi_free_rx_ring32(struct bwi_softc *); 149 static void bwi_free_txstats32(struct bwi_softc *); 150 static void bwi_setup_rx_desc32(struct bwi_softc *, int, bus_addr_t, int); 151 static void bwi_setup_tx_desc32(struct bwi_softc *, struct bwi_ring_data *, 152 int, bus_addr_t, int); 153 static int bwi_rxeof32(struct bwi_softc *); 154 static void bwi_start_tx32(struct bwi_softc *, uint32_t, int); 155 static void bwi_txeof_status32(struct bwi_softc *); 156 157 static int bwi_init_tx_ring64(struct bwi_softc *, int); 158 static int bwi_init_rx_ring64(struct bwi_softc *); 159 static int bwi_init_txstats64(struct bwi_softc *); 160 static void bwi_free_tx_ring64(struct bwi_softc *, int); 161 static void bwi_free_rx_ring64(struct bwi_softc *); 162 static void bwi_free_txstats64(struct bwi_softc *); 163 static void bwi_setup_rx_desc64(struct bwi_softc *, int, bus_addr_t, int); 164 static void bwi_setup_tx_desc64(struct bwi_softc *, struct bwi_ring_data *, 165 int, bus_addr_t, int); 166 static int bwi_rxeof64(struct bwi_softc *); 167 static void bwi_start_tx64(struct bwi_softc *, uint32_t, int); 168 static void bwi_txeof_status64(struct bwi_softc *); 169 170 static int bwi_rxeof(struct bwi_softc *, int); 171 static void _bwi_txeof(struct bwi_softc *, uint16_t, int, int); 172 static void bwi_txeof(struct bwi_softc *); 173 static void bwi_txeof_status(struct bwi_softc *, int); 174 static void bwi_enable_intrs(struct bwi_softc *, uint32_t); 175 static void bwi_disable_intrs(struct bwi_softc *, uint32_t); 176 177 static int bwi_dma_alloc(struct bwi_softc *); 178 static void bwi_dma_free(struct bwi_softc *); 179 static int bwi_dma_ring_alloc(struct bwi_softc *, bus_dma_tag_t, 180 struct bwi_ring_data *, bus_size_t, 181 uint32_t); 182 static int bwi_dma_mbuf_create(struct bwi_softc *); 183 static void bwi_dma_mbuf_destroy(struct bwi_softc *, int, int); 184 static int bwi_dma_txstats_alloc(struct bwi_softc *, uint32_t, bus_size_t); 185 static void bwi_dma_txstats_free(struct bwi_softc *); 186 static void bwi_dma_ring_addr(void *, bus_dma_segment_t *, int, int); 187 static void bwi_dma_buf_addr(void *, bus_dma_segment_t *, int, 188 bus_size_t, int); 189 190 static void bwi_power_on(struct bwi_softc *, int); 191 static int bwi_power_off(struct bwi_softc *, int); 192 static int bwi_set_clock_mode(struct bwi_softc *, enum bwi_clock_mode); 193 static int bwi_set_clock_delay(struct bwi_softc *); 194 static void bwi_get_clock_freq(struct bwi_softc *, struct bwi_clock_freq *); 195 static int bwi_get_pwron_delay(struct bwi_softc *sc); 196 static void bwi_set_addr_filter(struct bwi_softc *, uint16_t, 197 const uint8_t *); 198 static void bwi_set_bssid(struct bwi_softc *, const uint8_t *); 199 200 static void bwi_get_card_flags(struct bwi_softc *); 201 static void bwi_get_eaddr(struct bwi_softc *, uint16_t, uint8_t *); 202 203 static int bwi_bus_attach(struct bwi_softc *); 204 static int bwi_bbp_attach(struct bwi_softc *); 205 static int bwi_bbp_power_on(struct bwi_softc *, enum bwi_clock_mode); 206 static void bwi_bbp_power_off(struct bwi_softc *); 207 208 static const char *bwi_regwin_name(const struct bwi_regwin *); 209 static uint32_t bwi_regwin_disable_bits(struct bwi_softc *); 210 static void bwi_regwin_info(struct bwi_softc *, uint16_t *, uint8_t *); 211 static int bwi_regwin_select(struct bwi_softc *, int); 212 213 static void bwi_led_attach(struct bwi_softc *); 214 static void bwi_led_newstate(struct bwi_softc *, enum ieee80211_state); 215 static void bwi_led_event(struct bwi_softc *, int); 216 static void bwi_led_blink_start(struct bwi_softc *, int, int); 217 static void bwi_led_blink_next(void *); 218 static void bwi_led_blink_end(void *); 219 220 static const struct { 221 uint16_t did_min; 222 uint16_t did_max; 223 uint16_t bbp_id; 224 } bwi_bbpid_map[] = { 225 { 0x4301, 0x4301, 0x4301 }, 226 { 0x4305, 0x4307, 0x4307 }, 227 { 0x4403, 0x4403, 0x4402 }, 228 { 0x4610, 0x4615, 0x4610 }, 229 { 0x4710, 0x4715, 0x4710 }, 230 { 0x4720, 0x4725, 0x4309 } 231 }; 232 233 static const struct { 234 uint16_t bbp_id; 235 int nregwin; 236 } bwi_regwin_count[] = { 237 { 0x4301, 5 }, 238 { 0x4306, 6 }, 239 { 0x4307, 5 }, 240 { 0x4310, 8 }, 241 { 0x4401, 3 }, 242 { 0x4402, 3 }, 243 { 0x4610, 9 }, 244 { 0x4704, 9 }, 245 { 0x4710, 9 }, 246 { 0x5365, 7 } 247 }; 248 249 #define CLKSRC(src) \ 250 [BWI_CLKSRC_ ## src] = { \ 251 .freq_min = BWI_CLKSRC_ ##src## _FMIN, \ 252 .freq_max = BWI_CLKSRC_ ##src## _FMAX \ 253 } 254 255 static const struct { 256 u_int freq_min; 257 u_int freq_max; 258 } bwi_clkfreq[BWI_CLKSRC_MAX] = { 259 CLKSRC(LP_OSC), 260 CLKSRC(CS_OSC), 261 CLKSRC(PCI) 262 }; 263 264 #undef CLKSRC 265 266 #define VENDOR_LED_ACT(vendor) \ 267 { \ 268 .vid = PCI_VENDOR_##vendor, \ 269 .led_act = { BWI_VENDOR_LED_ACT_##vendor } \ 270 } 271 272 static const struct { 273 #define PCI_VENDOR_COMPAQ 0x0e11 274 #define PCI_VENDOR_LINKSYS 0x1737 275 uint16_t vid; 276 uint8_t led_act[BWI_LED_MAX]; 277 } bwi_vendor_led_act[] = { 278 VENDOR_LED_ACT(COMPAQ), 279 VENDOR_LED_ACT(LINKSYS) 280 #undef PCI_VENDOR_LINKSYS 281 #undef PCI_VENDOR_COMPAQ 282 }; 283 284 static const uint8_t bwi_default_led_act[BWI_LED_MAX] = 285 { BWI_VENDOR_LED_ACT_DEFAULT }; 286 287 #undef VENDOR_LED_ACT 288 289 static const struct { 290 int on_dur; 291 int off_dur; 292 } bwi_led_duration[109] = { 293 [0] = { 400, 100 }, 294 [2] = { 150, 75 }, 295 [4] = { 90, 45 }, 296 [11] = { 66, 34 }, 297 [12] = { 53, 26 }, 298 [18] = { 42, 21 }, 299 [22] = { 35, 17 }, 300 [24] = { 32, 16 }, 301 [36] = { 21, 10 }, 302 [48] = { 16, 8 }, 303 [72] = { 11, 5 }, 304 [96] = { 9, 4 }, 305 [108] = { 7, 3 } 306 }; 307 308 #ifdef BWI_DEBUG 309 #ifdef BWI_DEBUG_VERBOSE 310 static uint32_t bwi_debug = BWI_DBG_ATTACH | BWI_DBG_INIT | BWI_DBG_TXPOWER; 311 #else 312 static uint32_t bwi_debug; 313 #endif 314 TUNABLE_INT("hw.bwi.debug", (int *)&bwi_debug); 315 #endif /* BWI_DEBUG */ 316 317 static const uint8_t bwi_zero_addr[IEEE80211_ADDR_LEN]; 318 319 uint16_t 320 bwi_read_sprom(struct bwi_softc *sc, uint16_t ofs) 321 { 322 return CSR_READ_2(sc, ofs + BWI_SPROM_START); 323 } 324 325 static __inline void 326 bwi_setup_desc32(struct bwi_softc *sc, struct bwi_desc32 *desc_array, 327 int ndesc, int desc_idx, bus_addr_t paddr, int buf_len, 328 int tx) 329 { 330 struct bwi_desc32 *desc = &desc_array[desc_idx]; 331 uint32_t ctrl, addr, addr_hi, addr_lo; 332 333 addr_lo = __SHIFTOUT(paddr, BWI_DESC32_A_ADDR_MASK); 334 addr_hi = __SHIFTOUT(paddr, BWI_DESC32_A_FUNC_MASK); 335 336 addr = __SHIFTIN(addr_lo, BWI_DESC32_A_ADDR_MASK) | 337 __SHIFTIN(BWI_DESC32_A_FUNC_TXRX, BWI_DESC32_A_FUNC_MASK); 338 339 ctrl = __SHIFTIN(buf_len, BWI_DESC32_C_BUFLEN_MASK) | 340 __SHIFTIN(addr_hi, BWI_DESC32_C_ADDRHI_MASK); 341 if (desc_idx == ndesc - 1) 342 ctrl |= BWI_DESC32_C_EOR; 343 if (tx) { 344 /* XXX */ 345 ctrl |= BWI_DESC32_C_FRAME_START | 346 BWI_DESC32_C_FRAME_END | 347 BWI_DESC32_C_INTR; 348 } 349 350 desc->addr = htole32(addr); 351 desc->ctrl = htole32(ctrl); 352 } 353 354 int 355 bwi_attach(struct bwi_softc *sc) 356 { 357 struct ieee80211com *ic; 358 device_t dev = sc->sc_dev; 359 struct ifnet *ifp; 360 struct bwi_mac *mac; 361 struct bwi_phy *phy; 362 int i, error; 363 uint8_t bands; 364 uint8_t macaddr[IEEE80211_ADDR_LEN]; 365 366 BWI_LOCK_INIT(sc); 367 368 /* 369 * Initialize taskq and various tasks 370 */ 371 sc->sc_tq = taskqueue_create("bwi_taskq", M_NOWAIT | M_ZERO, 372 taskqueue_thread_enqueue, &sc->sc_tq); 373 taskqueue_start_threads(&sc->sc_tq, 1, PI_NET, "%s taskq", 374 device_get_nameunit(dev)); 375 TASK_INIT(&sc->sc_restart_task, 0, bwi_restart, sc); 376 377 callout_init_mtx(&sc->sc_calib_ch, &sc->sc_mtx, 0); 378 379 /* 380 * Initialize sysctl variables 381 */ 382 sc->sc_fw_version = BWI_FW_VERSION3; 383 sc->sc_led_idle = (2350 * hz) / 1000; 384 sc->sc_led_blink = 1; 385 sc->sc_txpwr_calib = 1; 386 #ifdef BWI_DEBUG 387 sc->sc_debug = bwi_debug; 388 #endif 389 bwi_power_on(sc, 1); 390 391 error = bwi_bbp_attach(sc); 392 if (error) 393 goto fail; 394 395 error = bwi_bbp_power_on(sc, BWI_CLOCK_MODE_FAST); 396 if (error) 397 goto fail; 398 399 if (BWI_REGWIN_EXIST(&sc->sc_com_regwin)) { 400 error = bwi_set_clock_delay(sc); 401 if (error) 402 goto fail; 403 404 error = bwi_set_clock_mode(sc, BWI_CLOCK_MODE_FAST); 405 if (error) 406 goto fail; 407 408 error = bwi_get_pwron_delay(sc); 409 if (error) 410 goto fail; 411 } 412 413 error = bwi_bus_attach(sc); 414 if (error) 415 goto fail; 416 417 bwi_get_card_flags(sc); 418 419 bwi_led_attach(sc); 420 421 for (i = 0; i < sc->sc_nmac; ++i) { 422 struct bwi_regwin *old; 423 424 mac = &sc->sc_mac[i]; 425 error = bwi_regwin_switch(sc, &mac->mac_regwin, &old); 426 if (error) 427 goto fail; 428 429 error = bwi_mac_lateattach(mac); 430 if (error) 431 goto fail; 432 433 error = bwi_regwin_switch(sc, old, NULL); 434 if (error) 435 goto fail; 436 } 437 438 /* 439 * XXX First MAC is known to exist 440 * TODO2 441 */ 442 mac = &sc->sc_mac[0]; 443 phy = &mac->mac_phy; 444 445 bwi_bbp_power_off(sc); 446 447 error = bwi_dma_alloc(sc); 448 if (error) 449 goto fail; 450 451 ifp = sc->sc_ifp = if_alloc(IFT_IEEE80211); 452 if (ifp == NULL) { 453 device_printf(dev, "can not if_alloc()\n"); 454 error = ENOSPC; 455 goto fail; 456 } 457 ic = ifp->if_l2com; 458 459 /* set these up early for if_printf use */ 460 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 461 462 ifp->if_softc = sc; 463 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 464 ifp->if_init = bwi_init; 465 ifp->if_ioctl = bwi_ioctl; 466 ifp->if_start = bwi_start; 467 IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); 468 ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN; 469 IFQ_SET_READY(&ifp->if_snd); 470 callout_init_mtx(&sc->sc_watchdog_timer, &sc->sc_mtx, 0); 471 472 /* 473 * Setup ratesets, phytype, channels and get MAC address 474 */ 475 bands = 0; 476 if (phy->phy_mode == IEEE80211_MODE_11B || 477 phy->phy_mode == IEEE80211_MODE_11G) { 478 setbit(&bands, IEEE80211_MODE_11B); 479 if (phy->phy_mode == IEEE80211_MODE_11B) { 480 ic->ic_phytype = IEEE80211_T_DS; 481 } else { 482 ic->ic_phytype = IEEE80211_T_OFDM; 483 setbit(&bands, IEEE80211_MODE_11G); 484 } 485 486 bwi_get_eaddr(sc, BWI_SPROM_11BG_EADDR, macaddr); 487 if (IEEE80211_IS_MULTICAST(macaddr)) { 488 bwi_get_eaddr(sc, BWI_SPROM_11A_EADDR, macaddr); 489 if (IEEE80211_IS_MULTICAST(macaddr)) { 490 device_printf(dev, 491 "invalid MAC address: %6D\n", 492 macaddr, ":"); 493 } 494 } 495 } else if (phy->phy_mode == IEEE80211_MODE_11A) { 496 /* TODO:11A */ 497 setbit(&bands, IEEE80211_MODE_11A); 498 error = ENXIO; 499 goto fail; 500 } else { 501 panic("unknown phymode %d\n", phy->phy_mode); 502 } 503 504 /* Get locale */ 505 sc->sc_locale = __SHIFTOUT(bwi_read_sprom(sc, BWI_SPROM_CARD_INFO), 506 BWI_SPROM_CARD_INFO_LOCALE); 507 DPRINTF(sc, BWI_DBG_ATTACH, "locale: %d\n", sc->sc_locale); 508 /* XXX use locale */ 509 ieee80211_init_channels(ic, NULL, &bands); 510 511 ic->ic_ifp = ifp; 512 ic->ic_caps = IEEE80211_C_STA | 513 IEEE80211_C_SHSLOT | 514 IEEE80211_C_SHPREAMBLE | 515 IEEE80211_C_WPA | 516 IEEE80211_C_BGSCAN | 517 IEEE80211_C_MONITOR; 518 ic->ic_opmode = IEEE80211_M_STA; 519 ieee80211_ifattach(ic, macaddr); 520 521 ic->ic_headroom = sizeof(struct bwi_txbuf_hdr); 522 523 /* override default methods */ 524 ic->ic_vap_create = bwi_vap_create; 525 ic->ic_vap_delete = bwi_vap_delete; 526 ic->ic_raw_xmit = bwi_raw_xmit; 527 ic->ic_updateslot = bwi_updateslot; 528 ic->ic_node_alloc = bwi_node_alloc; 529 ic->ic_scan_start = bwi_scan_start; 530 ic->ic_scan_end = bwi_scan_end; 531 ic->ic_set_channel = bwi_set_channel; 532 533 sc->sc_rates = ieee80211_get_ratetable(ic->ic_curchan); 534 535 ieee80211_radiotap_attach(ic, 536 &sc->sc_tx_th.wt_ihdr, sizeof(sc->sc_tx_th), 537 BWI_TX_RADIOTAP_PRESENT, 538 &sc->sc_rx_th.wr_ihdr, sizeof(sc->sc_rx_th), 539 BWI_RX_RADIOTAP_PRESENT); 540 541 /* 542 * Add sysctl nodes 543 */ 544 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), 545 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 546 "fw_version", CTLFLAG_RD, &sc->sc_fw_version, 0, 547 "Firmware version"); 548 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), 549 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 550 "led_idle", CTLFLAG_RW, &sc->sc_led_idle, 0, 551 "# ticks before LED enters idle state"); 552 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 553 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 554 "led_blink", CTLFLAG_RW, &sc->sc_led_blink, 0, 555 "Allow LED to blink"); 556 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), 557 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 558 "txpwr_calib", CTLFLAG_RW, &sc->sc_txpwr_calib, 0, 559 "Enable software TX power calibration"); 560 #ifdef BWI_DEBUG 561 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev), 562 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 563 "debug", CTLFLAG_RW, &sc->sc_debug, 0, "Debug flags"); 564 #endif 565 if (bootverbose) 566 ieee80211_announce(ic); 567 568 return (0); 569 fail: 570 BWI_LOCK_DESTROY(sc); 571 return (error); 572 } 573 574 int 575 bwi_detach(struct bwi_softc *sc) 576 { 577 struct ifnet *ifp = sc->sc_ifp; 578 struct ieee80211com *ic = ifp->if_l2com; 579 int i; 580 581 bwi_stop(sc, 1); 582 callout_drain(&sc->sc_led_blink_ch); 583 callout_drain(&sc->sc_calib_ch); 584 callout_drain(&sc->sc_watchdog_timer); 585 ieee80211_ifdetach(ic); 586 587 for (i = 0; i < sc->sc_nmac; ++i) 588 bwi_mac_detach(&sc->sc_mac[i]); 589 bwi_dma_free(sc); 590 if_free(ifp); 591 taskqueue_free(sc->sc_tq); 592 593 BWI_LOCK_DESTROY(sc); 594 595 return (0); 596 } 597 598 static struct ieee80211vap * 599 bwi_vap_create(struct ieee80211com *ic, 600 const char name[IFNAMSIZ], int unit, int opmode, int flags, 601 const uint8_t bssid[IEEE80211_ADDR_LEN], 602 const uint8_t mac[IEEE80211_ADDR_LEN]) 603 { 604 struct bwi_vap *bvp; 605 struct ieee80211vap *vap; 606 607 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */ 608 return NULL; 609 bvp = (struct bwi_vap *) malloc(sizeof(struct bwi_vap), 610 M_80211_VAP, M_WAITOK | M_ZERO); 611 if (bvp == NULL) 612 return NULL; 613 vap = &bvp->bv_vap; 614 /* enable s/w bmiss handling for sta mode */ 615 ieee80211_vap_setup(ic, vap, name, unit, opmode, 616 flags | IEEE80211_CLONE_NOBEACONS, bssid, mac); 617 618 /* override default methods */ 619 bvp->bv_newstate = vap->iv_newstate; 620 vap->iv_newstate = bwi_newstate; 621 #if 0 622 vap->iv_update_beacon = bwi_beacon_update; 623 #endif 624 ieee80211_amrr_init(&bvp->bv_amrr, vap, 625 IEEE80211_AMRR_MIN_SUCCESS_THRESHOLD, 626 IEEE80211_AMRR_MAX_SUCCESS_THRESHOLD, 627 500 /*ms*/); 628 629 /* complete setup */ 630 ieee80211_vap_attach(vap, bwi_media_change, ieee80211_media_status); 631 ic->ic_opmode = opmode; 632 return vap; 633 } 634 635 static void 636 bwi_vap_delete(struct ieee80211vap *vap) 637 { 638 struct bwi_vap *bvp = BWI_VAP(vap); 639 640 ieee80211_amrr_cleanup(&bvp->bv_amrr); 641 ieee80211_vap_detach(vap); 642 free(bvp, M_80211_VAP); 643 } 644 645 void 646 bwi_suspend(struct bwi_softc *sc) 647 { 648 bwi_stop(sc, 1); 649 } 650 651 void 652 bwi_resume(struct bwi_softc *sc) 653 { 654 struct ifnet *ifp = sc->sc_ifp; 655 656 if (ifp->if_flags & IFF_UP) 657 bwi_init(sc); 658 } 659 660 int 661 bwi_shutdown(struct bwi_softc *sc) 662 { 663 bwi_stop(sc, 1); 664 return 0; 665 } 666 667 static void 668 bwi_power_on(struct bwi_softc *sc, int with_pll) 669 { 670 uint32_t gpio_in, gpio_out, gpio_en; 671 uint16_t status; 672 673 gpio_in = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_IN, 4); 674 if (gpio_in & BWI_PCIM_GPIO_PWR_ON) 675 goto back; 676 677 gpio_out = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, 4); 678 gpio_en = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, 4); 679 680 gpio_out |= BWI_PCIM_GPIO_PWR_ON; 681 gpio_en |= BWI_PCIM_GPIO_PWR_ON; 682 if (with_pll) { 683 /* Turn off PLL first */ 684 gpio_out |= BWI_PCIM_GPIO_PLL_PWR_OFF; 685 gpio_en |= BWI_PCIM_GPIO_PLL_PWR_OFF; 686 } 687 688 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, gpio_out, 4); 689 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, gpio_en, 4); 690 DELAY(1000); 691 692 if (with_pll) { 693 /* Turn on PLL */ 694 gpio_out &= ~BWI_PCIM_GPIO_PLL_PWR_OFF; 695 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, gpio_out, 4); 696 DELAY(5000); 697 } 698 699 back: 700 /* Clear "Signaled Target Abort" */ 701 status = pci_read_config(sc->sc_dev, PCIR_STATUS, 2); 702 status &= ~PCIM_STATUS_STABORT; 703 pci_write_config(sc->sc_dev, PCIR_STATUS, status, 2); 704 } 705 706 static int 707 bwi_power_off(struct bwi_softc *sc, int with_pll) 708 { 709 uint32_t gpio_out, gpio_en; 710 711 pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_IN, 4); /* dummy read */ 712 gpio_out = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, 4); 713 gpio_en = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, 4); 714 715 gpio_out &= ~BWI_PCIM_GPIO_PWR_ON; 716 gpio_en |= BWI_PCIM_GPIO_PWR_ON; 717 if (with_pll) { 718 gpio_out |= BWI_PCIM_GPIO_PLL_PWR_OFF; 719 gpio_en |= BWI_PCIM_GPIO_PLL_PWR_OFF; 720 } 721 722 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, gpio_out, 4); 723 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, gpio_en, 4); 724 return 0; 725 } 726 727 int 728 bwi_regwin_switch(struct bwi_softc *sc, struct bwi_regwin *rw, 729 struct bwi_regwin **old_rw) 730 { 731 int error; 732 733 if (old_rw != NULL) 734 *old_rw = NULL; 735 736 if (!BWI_REGWIN_EXIST(rw)) 737 return EINVAL; 738 739 if (sc->sc_cur_regwin != rw) { 740 error = bwi_regwin_select(sc, rw->rw_id); 741 if (error) { 742 device_printf(sc->sc_dev, "can't select regwin %d\n", 743 rw->rw_id); 744 return error; 745 } 746 } 747 748 if (old_rw != NULL) 749 *old_rw = sc->sc_cur_regwin; 750 sc->sc_cur_regwin = rw; 751 return 0; 752 } 753 754 static int 755 bwi_regwin_select(struct bwi_softc *sc, int id) 756 { 757 uint32_t win = BWI_PCIM_REGWIN(id); 758 int i; 759 760 #define RETRY_MAX 50 761 for (i = 0; i < RETRY_MAX; ++i) { 762 pci_write_config(sc->sc_dev, BWI_PCIR_SEL_REGWIN, win, 4); 763 if (pci_read_config(sc->sc_dev, BWI_PCIR_SEL_REGWIN, 4) == win) 764 return 0; 765 DELAY(10); 766 } 767 #undef RETRY_MAX 768 769 return ENXIO; 770 } 771 772 static void 773 bwi_regwin_info(struct bwi_softc *sc, uint16_t *type, uint8_t *rev) 774 { 775 uint32_t val; 776 777 val = CSR_READ_4(sc, BWI_ID_HI); 778 *type = BWI_ID_HI_REGWIN_TYPE(val); 779 *rev = BWI_ID_HI_REGWIN_REV(val); 780 781 DPRINTF(sc, BWI_DBG_ATTACH, "regwin: type 0x%03x, rev %d, " 782 "vendor 0x%04x\n", *type, *rev, 783 __SHIFTOUT(val, BWI_ID_HI_REGWIN_VENDOR_MASK)); 784 } 785 786 static int 787 bwi_bbp_attach(struct bwi_softc *sc) 788 { 789 #define N(arr) (int)(sizeof(arr) / sizeof(arr[0])) 790 uint16_t bbp_id, rw_type; 791 uint8_t rw_rev; 792 uint32_t info; 793 int error, nregwin, i; 794 795 /* 796 * Get 0th regwin information 797 * NOTE: 0th regwin should exist 798 */ 799 error = bwi_regwin_select(sc, 0); 800 if (error) { 801 device_printf(sc->sc_dev, "can't select regwin 0\n"); 802 return error; 803 } 804 bwi_regwin_info(sc, &rw_type, &rw_rev); 805 806 /* 807 * Find out BBP id 808 */ 809 bbp_id = 0; 810 info = 0; 811 if (rw_type == BWI_REGWIN_T_COM) { 812 info = CSR_READ_4(sc, BWI_INFO); 813 bbp_id = __SHIFTOUT(info, BWI_INFO_BBPID_MASK); 814 815 BWI_CREATE_REGWIN(&sc->sc_com_regwin, 0, rw_type, rw_rev); 816 817 sc->sc_cap = CSR_READ_4(sc, BWI_CAPABILITY); 818 } else { 819 for (i = 0; i < N(bwi_bbpid_map); ++i) { 820 if (sc->sc_pci_did >= bwi_bbpid_map[i].did_min && 821 sc->sc_pci_did <= bwi_bbpid_map[i].did_max) { 822 bbp_id = bwi_bbpid_map[i].bbp_id; 823 break; 824 } 825 } 826 if (bbp_id == 0) { 827 device_printf(sc->sc_dev, "no BBP id for device id " 828 "0x%04x\n", sc->sc_pci_did); 829 return ENXIO; 830 } 831 832 info = __SHIFTIN(sc->sc_pci_revid, BWI_INFO_BBPREV_MASK) | 833 __SHIFTIN(0, BWI_INFO_BBPPKG_MASK); 834 } 835 836 /* 837 * Find out number of regwins 838 */ 839 nregwin = 0; 840 if (rw_type == BWI_REGWIN_T_COM && rw_rev >= 4) { 841 nregwin = __SHIFTOUT(info, BWI_INFO_NREGWIN_MASK); 842 } else { 843 for (i = 0; i < N(bwi_regwin_count); ++i) { 844 if (bwi_regwin_count[i].bbp_id == bbp_id) { 845 nregwin = bwi_regwin_count[i].nregwin; 846 break; 847 } 848 } 849 if (nregwin == 0) { 850 device_printf(sc->sc_dev, "no number of win for " 851 "BBP id 0x%04x\n", bbp_id); 852 return ENXIO; 853 } 854 } 855 856 /* Record BBP id/rev for later using */ 857 sc->sc_bbp_id = bbp_id; 858 sc->sc_bbp_rev = __SHIFTOUT(info, BWI_INFO_BBPREV_MASK); 859 sc->sc_bbp_pkg = __SHIFTOUT(info, BWI_INFO_BBPPKG_MASK); 860 device_printf(sc->sc_dev, "BBP: id 0x%04x, rev 0x%x, pkg %d\n", 861 sc->sc_bbp_id, sc->sc_bbp_rev, sc->sc_bbp_pkg); 862 863 DPRINTF(sc, BWI_DBG_ATTACH, "nregwin %d, cap 0x%08x\n", 864 nregwin, sc->sc_cap); 865 866 /* 867 * Create rest of the regwins 868 */ 869 870 /* Don't re-create common regwin, if it is already created */ 871 i = BWI_REGWIN_EXIST(&sc->sc_com_regwin) ? 1 : 0; 872 873 for (; i < nregwin; ++i) { 874 /* 875 * Get regwin information 876 */ 877 error = bwi_regwin_select(sc, i); 878 if (error) { 879 device_printf(sc->sc_dev, 880 "can't select regwin %d\n", i); 881 return error; 882 } 883 bwi_regwin_info(sc, &rw_type, &rw_rev); 884 885 /* 886 * Try attach: 887 * 1) Bus (PCI/PCIE) regwin 888 * 2) MAC regwin 889 * Ignore rest types of regwin 890 */ 891 if (rw_type == BWI_REGWIN_T_BUSPCI || 892 rw_type == BWI_REGWIN_T_BUSPCIE) { 893 if (BWI_REGWIN_EXIST(&sc->sc_bus_regwin)) { 894 device_printf(sc->sc_dev, 895 "bus regwin already exists\n"); 896 } else { 897 BWI_CREATE_REGWIN(&sc->sc_bus_regwin, i, 898 rw_type, rw_rev); 899 } 900 } else if (rw_type == BWI_REGWIN_T_MAC) { 901 /* XXX ignore return value */ 902 bwi_mac_attach(sc, i, rw_rev); 903 } 904 } 905 906 /* At least one MAC shold exist */ 907 if (!BWI_REGWIN_EXIST(&sc->sc_mac[0].mac_regwin)) { 908 device_printf(sc->sc_dev, "no MAC was found\n"); 909 return ENXIO; 910 } 911 KASSERT(sc->sc_nmac > 0, ("no mac's")); 912 913 /* Bus regwin must exist */ 914 if (!BWI_REGWIN_EXIST(&sc->sc_bus_regwin)) { 915 device_printf(sc->sc_dev, "no bus regwin was found\n"); 916 return ENXIO; 917 } 918 919 /* Start with first MAC */ 920 error = bwi_regwin_switch(sc, &sc->sc_mac[0].mac_regwin, NULL); 921 if (error) 922 return error; 923 924 return 0; 925 #undef N 926 } 927 928 int 929 bwi_bus_init(struct bwi_softc *sc, struct bwi_mac *mac) 930 { 931 struct bwi_regwin *old, *bus; 932 uint32_t val; 933 int error; 934 935 bus = &sc->sc_bus_regwin; 936 KASSERT(sc->sc_cur_regwin == &mac->mac_regwin, ("not cur regwin")); 937 938 /* 939 * Tell bus to generate requested interrupts 940 */ 941 if (bus->rw_rev < 6 && bus->rw_type == BWI_REGWIN_T_BUSPCI) { 942 /* 943 * NOTE: Read BWI_FLAGS from MAC regwin 944 */ 945 val = CSR_READ_4(sc, BWI_FLAGS); 946 947 error = bwi_regwin_switch(sc, bus, &old); 948 if (error) 949 return error; 950 951 CSR_SETBITS_4(sc, BWI_INTRVEC, (val & BWI_FLAGS_INTR_MASK)); 952 } else { 953 uint32_t mac_mask; 954 955 mac_mask = 1 << mac->mac_id; 956 957 error = bwi_regwin_switch(sc, bus, &old); 958 if (error) 959 return error; 960 961 val = pci_read_config(sc->sc_dev, BWI_PCIR_INTCTL, 4); 962 val |= mac_mask << 8; 963 pci_write_config(sc->sc_dev, BWI_PCIR_INTCTL, val, 4); 964 } 965 966 if (sc->sc_flags & BWI_F_BUS_INITED) 967 goto back; 968 969 if (bus->rw_type == BWI_REGWIN_T_BUSPCI) { 970 /* 971 * Enable prefetch and burst 972 */ 973 CSR_SETBITS_4(sc, BWI_BUS_CONFIG, 974 BWI_BUS_CONFIG_PREFETCH | BWI_BUS_CONFIG_BURST); 975 976 if (bus->rw_rev < 5) { 977 struct bwi_regwin *com = &sc->sc_com_regwin; 978 979 /* 980 * Configure timeouts for bus operation 981 */ 982 983 /* 984 * Set service timeout and request timeout 985 */ 986 CSR_SETBITS_4(sc, BWI_CONF_LO, 987 __SHIFTIN(BWI_CONF_LO_SERVTO, BWI_CONF_LO_SERVTO_MASK) | 988 __SHIFTIN(BWI_CONF_LO_REQTO, BWI_CONF_LO_REQTO_MASK)); 989 990 /* 991 * If there is common regwin, we switch to that regwin 992 * and switch back to bus regwin once we have done. 993 */ 994 if (BWI_REGWIN_EXIST(com)) { 995 error = bwi_regwin_switch(sc, com, NULL); 996 if (error) 997 return error; 998 } 999 1000 /* Let bus know what we have changed */ 1001 CSR_WRITE_4(sc, BWI_BUS_ADDR, BWI_BUS_ADDR_MAGIC); 1002 CSR_READ_4(sc, BWI_BUS_ADDR); /* Flush */ 1003 CSR_WRITE_4(sc, BWI_BUS_DATA, 0); 1004 CSR_READ_4(sc, BWI_BUS_DATA); /* Flush */ 1005 1006 if (BWI_REGWIN_EXIST(com)) { 1007 error = bwi_regwin_switch(sc, bus, NULL); 1008 if (error) 1009 return error; 1010 } 1011 } else if (bus->rw_rev >= 11) { 1012 /* 1013 * Enable memory read multiple 1014 */ 1015 CSR_SETBITS_4(sc, BWI_BUS_CONFIG, BWI_BUS_CONFIG_MRM); 1016 } 1017 } else { 1018 /* TODO:PCIE */ 1019 } 1020 1021 sc->sc_flags |= BWI_F_BUS_INITED; 1022 back: 1023 return bwi_regwin_switch(sc, old, NULL); 1024 } 1025 1026 static void 1027 bwi_get_card_flags(struct bwi_softc *sc) 1028 { 1029 #define PCI_VENDOR_APPLE 0x106b 1030 #define PCI_VENDOR_DELL 0x1028 1031 sc->sc_card_flags = bwi_read_sprom(sc, BWI_SPROM_CARD_FLAGS); 1032 if (sc->sc_card_flags == 0xffff) 1033 sc->sc_card_flags = 0; 1034 1035 if (sc->sc_pci_subvid == PCI_VENDOR_DELL && 1036 sc->sc_bbp_id == BWI_BBPID_BCM4301 && 1037 sc->sc_pci_revid == 0x74) 1038 sc->sc_card_flags |= BWI_CARD_F_BT_COEXIST; 1039 1040 if (sc->sc_pci_subvid == PCI_VENDOR_APPLE && 1041 sc->sc_pci_subdid == 0x4e && /* XXX */ 1042 sc->sc_pci_revid > 0x40) 1043 sc->sc_card_flags |= BWI_CARD_F_PA_GPIO9; 1044 1045 DPRINTF(sc, BWI_DBG_ATTACH, "card flags 0x%04x\n", sc->sc_card_flags); 1046 #undef PCI_VENDOR_DELL 1047 #undef PCI_VENDOR_APPLE 1048 } 1049 1050 static void 1051 bwi_get_eaddr(struct bwi_softc *sc, uint16_t eaddr_ofs, uint8_t *eaddr) 1052 { 1053 int i; 1054 1055 for (i = 0; i < 3; ++i) { 1056 *((uint16_t *)eaddr + i) = 1057 htobe16(bwi_read_sprom(sc, eaddr_ofs + 2 * i)); 1058 } 1059 } 1060 1061 static void 1062 bwi_get_clock_freq(struct bwi_softc *sc, struct bwi_clock_freq *freq) 1063 { 1064 struct bwi_regwin *com; 1065 uint32_t val; 1066 u_int div; 1067 int src; 1068 1069 bzero(freq, sizeof(*freq)); 1070 com = &sc->sc_com_regwin; 1071 1072 KASSERT(BWI_REGWIN_EXIST(com), ("regwin does not exist")); 1073 KASSERT(sc->sc_cur_regwin == com, ("wrong regwin")); 1074 KASSERT(sc->sc_cap & BWI_CAP_CLKMODE, ("wrong clock mode")); 1075 1076 /* 1077 * Calculate clock frequency 1078 */ 1079 src = -1; 1080 div = 0; 1081 if (com->rw_rev < 6) { 1082 val = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, 4); 1083 if (val & BWI_PCIM_GPIO_OUT_CLKSRC) { 1084 src = BWI_CLKSRC_PCI; 1085 div = 64; 1086 } else { 1087 src = BWI_CLKSRC_CS_OSC; 1088 div = 32; 1089 } 1090 } else if (com->rw_rev < 10) { 1091 val = CSR_READ_4(sc, BWI_CLOCK_CTRL); 1092 1093 src = __SHIFTOUT(val, BWI_CLOCK_CTRL_CLKSRC); 1094 if (src == BWI_CLKSRC_LP_OSC) { 1095 div = 1; 1096 } else { 1097 div = (__SHIFTOUT(val, BWI_CLOCK_CTRL_FDIV) + 1) << 2; 1098 1099 /* Unknown source */ 1100 if (src >= BWI_CLKSRC_MAX) 1101 src = BWI_CLKSRC_CS_OSC; 1102 } 1103 } else { 1104 val = CSR_READ_4(sc, BWI_CLOCK_INFO); 1105 1106 src = BWI_CLKSRC_CS_OSC; 1107 div = (__SHIFTOUT(val, BWI_CLOCK_INFO_FDIV) + 1) << 2; 1108 } 1109 1110 KASSERT(src >= 0 && src < BWI_CLKSRC_MAX, ("bad src %d", src)); 1111 KASSERT(div != 0, ("div zero")); 1112 1113 DPRINTF(sc, BWI_DBG_ATTACH, "clksrc %s\n", 1114 src == BWI_CLKSRC_PCI ? "PCI" : 1115 (src == BWI_CLKSRC_LP_OSC ? "LP_OSC" : "CS_OSC")); 1116 1117 freq->clkfreq_min = bwi_clkfreq[src].freq_min / div; 1118 freq->clkfreq_max = bwi_clkfreq[src].freq_max / div; 1119 1120 DPRINTF(sc, BWI_DBG_ATTACH, "clkfreq min %u, max %u\n", 1121 freq->clkfreq_min, freq->clkfreq_max); 1122 } 1123 1124 static int 1125 bwi_set_clock_mode(struct bwi_softc *sc, enum bwi_clock_mode clk_mode) 1126 { 1127 struct bwi_regwin *old, *com; 1128 uint32_t clk_ctrl, clk_src; 1129 int error, pwr_off = 0; 1130 1131 com = &sc->sc_com_regwin; 1132 if (!BWI_REGWIN_EXIST(com)) 1133 return 0; 1134 1135 if (com->rw_rev >= 10 || com->rw_rev < 6) 1136 return 0; 1137 1138 /* 1139 * For common regwin whose rev is [6, 10), the chip 1140 * must be capable to change clock mode. 1141 */ 1142 if ((sc->sc_cap & BWI_CAP_CLKMODE) == 0) 1143 return 0; 1144 1145 error = bwi_regwin_switch(sc, com, &old); 1146 if (error) 1147 return error; 1148 1149 if (clk_mode == BWI_CLOCK_MODE_FAST) 1150 bwi_power_on(sc, 0); /* Don't turn on PLL */ 1151 1152 clk_ctrl = CSR_READ_4(sc, BWI_CLOCK_CTRL); 1153 clk_src = __SHIFTOUT(clk_ctrl, BWI_CLOCK_CTRL_CLKSRC); 1154 1155 switch (clk_mode) { 1156 case BWI_CLOCK_MODE_FAST: 1157 clk_ctrl &= ~BWI_CLOCK_CTRL_SLOW; 1158 clk_ctrl |= BWI_CLOCK_CTRL_IGNPLL; 1159 break; 1160 case BWI_CLOCK_MODE_SLOW: 1161 clk_ctrl |= BWI_CLOCK_CTRL_SLOW; 1162 break; 1163 case BWI_CLOCK_MODE_DYN: 1164 clk_ctrl &= ~(BWI_CLOCK_CTRL_SLOW | 1165 BWI_CLOCK_CTRL_IGNPLL | 1166 BWI_CLOCK_CTRL_NODYN); 1167 if (clk_src != BWI_CLKSRC_CS_OSC) { 1168 clk_ctrl |= BWI_CLOCK_CTRL_NODYN; 1169 pwr_off = 1; 1170 } 1171 break; 1172 } 1173 CSR_WRITE_4(sc, BWI_CLOCK_CTRL, clk_ctrl); 1174 1175 if (pwr_off) 1176 bwi_power_off(sc, 0); /* Leave PLL as it is */ 1177 1178 return bwi_regwin_switch(sc, old, NULL); 1179 } 1180 1181 static int 1182 bwi_set_clock_delay(struct bwi_softc *sc) 1183 { 1184 struct bwi_regwin *old, *com; 1185 int error; 1186 1187 com = &sc->sc_com_regwin; 1188 if (!BWI_REGWIN_EXIST(com)) 1189 return 0; 1190 1191 error = bwi_regwin_switch(sc, com, &old); 1192 if (error) 1193 return error; 1194 1195 if (sc->sc_bbp_id == BWI_BBPID_BCM4321) { 1196 if (sc->sc_bbp_rev == 0) 1197 CSR_WRITE_4(sc, BWI_CONTROL, BWI_CONTROL_MAGIC0); 1198 else if (sc->sc_bbp_rev == 1) 1199 CSR_WRITE_4(sc, BWI_CONTROL, BWI_CONTROL_MAGIC1); 1200 } 1201 1202 if (sc->sc_cap & BWI_CAP_CLKMODE) { 1203 if (com->rw_rev >= 10) { 1204 CSR_FILT_SETBITS_4(sc, BWI_CLOCK_INFO, 0xffff, 0x40000); 1205 } else { 1206 struct bwi_clock_freq freq; 1207 1208 bwi_get_clock_freq(sc, &freq); 1209 CSR_WRITE_4(sc, BWI_PLL_ON_DELAY, 1210 howmany(freq.clkfreq_max * 150, 1000000)); 1211 CSR_WRITE_4(sc, BWI_FREQ_SEL_DELAY, 1212 howmany(freq.clkfreq_max * 15, 1000000)); 1213 } 1214 } 1215 1216 return bwi_regwin_switch(sc, old, NULL); 1217 } 1218 1219 static void 1220 bwi_init(void *xsc) 1221 { 1222 struct bwi_softc *sc = xsc; 1223 struct ifnet *ifp = sc->sc_ifp; 1224 struct ieee80211com *ic = ifp->if_l2com; 1225 1226 BWI_LOCK(sc); 1227 bwi_init_statechg(sc, 1); 1228 BWI_UNLOCK(sc); 1229 1230 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1231 ieee80211_start_all(ic); /* start all vap's */ 1232 } 1233 1234 static void 1235 bwi_init_statechg(struct bwi_softc *sc, int statechg) 1236 { 1237 struct ifnet *ifp = sc->sc_ifp; 1238 struct bwi_mac *mac; 1239 int error; 1240 1241 bwi_stop_locked(sc, statechg); 1242 1243 bwi_bbp_power_on(sc, BWI_CLOCK_MODE_FAST); 1244 1245 /* TODO: 2 MAC */ 1246 1247 mac = &sc->sc_mac[0]; 1248 error = bwi_regwin_switch(sc, &mac->mac_regwin, NULL); 1249 if (error) { 1250 if_printf(ifp, "%s: error %d on regwin switch\n", 1251 __func__, error); 1252 goto bad; 1253 } 1254 error = bwi_mac_init(mac); 1255 if (error) { 1256 if_printf(ifp, "%s: error %d on MAC init\n", __func__, error); 1257 goto bad; 1258 } 1259 1260 bwi_bbp_power_on(sc, BWI_CLOCK_MODE_DYN); 1261 1262 bwi_set_bssid(sc, bwi_zero_addr); /* Clear BSSID */ 1263 bwi_set_addr_filter(sc, BWI_ADDR_FILTER_MYADDR, IF_LLADDR(ifp)); 1264 1265 bwi_mac_reset_hwkeys(mac); 1266 1267 if ((mac->mac_flags & BWI_MAC_F_HAS_TXSTATS) == 0) { 1268 int i; 1269 1270 #define NRETRY 1000 1271 /* 1272 * Drain any possible pending TX status 1273 */ 1274 for (i = 0; i < NRETRY; ++i) { 1275 if ((CSR_READ_4(sc, BWI_TXSTATUS0) & 1276 BWI_TXSTATUS0_VALID) == 0) 1277 break; 1278 CSR_READ_4(sc, BWI_TXSTATUS1); 1279 } 1280 if (i == NRETRY) 1281 if_printf(ifp, "%s: can't drain TX status\n", __func__); 1282 #undef NRETRY 1283 } 1284 1285 if (mac->mac_phy.phy_mode == IEEE80211_MODE_11G) 1286 bwi_mac_updateslot(mac, 1); 1287 1288 /* Start MAC */ 1289 error = bwi_mac_start(mac); 1290 if (error) { 1291 if_printf(ifp, "%s: error %d starting MAC\n", __func__, error); 1292 goto bad; 1293 } 1294 1295 /* Clear stop flag before enabling interrupt */ 1296 sc->sc_flags &= ~BWI_F_STOP; 1297 1298 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1299 callout_reset(&sc->sc_watchdog_timer, hz, bwi_watchdog, sc); 1300 1301 /* Enable intrs */ 1302 bwi_enable_intrs(sc, BWI_INIT_INTRS); 1303 return; 1304 bad: 1305 bwi_stop_locked(sc, 1); 1306 } 1307 1308 static int 1309 bwi_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1310 { 1311 #define IS_RUNNING(ifp) \ 1312 ((ifp->if_flags & IFF_UP) && (ifp->if_drv_flags & IFF_DRV_RUNNING)) 1313 struct bwi_softc *sc = ifp->if_softc; 1314 struct ieee80211com *ic = ifp->if_l2com; 1315 struct ifreq *ifr = (struct ifreq *) data; 1316 int error = 0, startall = 0; 1317 1318 switch (cmd) { 1319 case SIOCSIFFLAGS: 1320 BWI_LOCK(sc); 1321 if (IS_RUNNING(ifp)) { 1322 struct bwi_mac *mac; 1323 int promisc = -1; 1324 1325 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 1326 ("current regwin type %d", 1327 sc->sc_cur_regwin->rw_type)); 1328 mac = (struct bwi_mac *)sc->sc_cur_regwin; 1329 1330 if ((ifp->if_flags & IFF_PROMISC) && 1331 (sc->sc_flags & BWI_F_PROMISC) == 0) { 1332 promisc = 1; 1333 sc->sc_flags |= BWI_F_PROMISC; 1334 } else if ((ifp->if_flags & IFF_PROMISC) == 0 && 1335 (sc->sc_flags & BWI_F_PROMISC)) { 1336 promisc = 0; 1337 sc->sc_flags &= ~BWI_F_PROMISC; 1338 } 1339 1340 if (promisc >= 0) 1341 bwi_mac_set_promisc(mac, promisc); 1342 } 1343 1344 if (ifp->if_flags & IFF_UP) { 1345 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 1346 bwi_init_statechg(sc, 1); 1347 startall = 1; 1348 } 1349 } else { 1350 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1351 bwi_stop_locked(sc, 1); 1352 } 1353 BWI_UNLOCK(sc); 1354 if (startall) 1355 ieee80211_start_all(ic); 1356 break; 1357 case SIOCGIFMEDIA: 1358 error = ifmedia_ioctl(ifp, ifr, &ic->ic_media, cmd); 1359 break; 1360 case SIOCGIFADDR: 1361 error = ether_ioctl(ifp, cmd, data); 1362 break; 1363 default: 1364 error = EINVAL; 1365 break; 1366 } 1367 return error; 1368 #undef IS_RUNNING 1369 } 1370 1371 static void 1372 bwi_start(struct ifnet *ifp) 1373 { 1374 struct bwi_softc *sc = ifp->if_softc; 1375 1376 BWI_LOCK(sc); 1377 bwi_start_locked(ifp); 1378 BWI_UNLOCK(sc); 1379 } 1380 1381 static void 1382 bwi_start_locked(struct ifnet *ifp) 1383 { 1384 struct bwi_softc *sc = ifp->if_softc; 1385 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING]; 1386 struct ieee80211_frame *wh; 1387 struct ieee80211_node *ni; 1388 struct ieee80211_key *k; 1389 struct mbuf *m; 1390 int trans, idx; 1391 1392 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 1393 return; 1394 1395 trans = 0; 1396 idx = tbd->tbd_idx; 1397 1398 while (tbd->tbd_buf[idx].tb_mbuf == NULL) { 1399 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); /* XXX: LOCK */ 1400 if (m == NULL) 1401 break; 1402 1403 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif; 1404 wh = mtod(m, struct ieee80211_frame *); 1405 if (wh->i_fc[1] & IEEE80211_FC1_WEP) { 1406 k = ieee80211_crypto_encap(ni, m); 1407 if (k == NULL) { 1408 ieee80211_free_node(ni); 1409 m_freem(m); 1410 ifp->if_oerrors++; 1411 continue; 1412 } 1413 } 1414 wh = NULL; /* Catch any invalid use */ 1415 1416 if (bwi_encap(sc, idx, m, ni) != 0) { 1417 /* 'm' is freed in bwi_encap() if we reach here */ 1418 if (ni != NULL) 1419 ieee80211_free_node(ni); 1420 ifp->if_oerrors++; 1421 continue; 1422 } 1423 1424 trans = 1; 1425 tbd->tbd_used++; 1426 idx = (idx + 1) % BWI_TX_NDESC; 1427 1428 ifp->if_opackets++; 1429 1430 if (tbd->tbd_used + BWI_TX_NSPRDESC >= BWI_TX_NDESC) { 1431 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1432 break; 1433 } 1434 } 1435 tbd->tbd_idx = idx; 1436 1437 if (trans) 1438 sc->sc_tx_timer = 5; 1439 } 1440 1441 static int 1442 bwi_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, 1443 const struct ieee80211_bpf_params *params) 1444 { 1445 struct ieee80211com *ic = ni->ni_ic; 1446 struct ifnet *ifp = ic->ic_ifp; 1447 struct bwi_softc *sc = ifp->if_softc; 1448 /* XXX wme? */ 1449 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING]; 1450 int idx, error; 1451 1452 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 1453 ieee80211_free_node(ni); 1454 m_freem(m); 1455 return ENETDOWN; 1456 } 1457 1458 BWI_LOCK(sc); 1459 idx = tbd->tbd_idx; 1460 KASSERT(tbd->tbd_buf[idx].tb_mbuf == NULL, ("slot %d not empty", idx)); 1461 if (params == NULL) { 1462 /* 1463 * Legacy path; interpret frame contents to decide 1464 * precisely how to send the frame. 1465 */ 1466 error = bwi_encap(sc, idx, m, ni); 1467 } else { 1468 /* 1469 * Caller supplied explicit parameters to use in 1470 * sending the frame. 1471 */ 1472 error = bwi_encap_raw(sc, idx, m, ni, params); 1473 } 1474 if (error == 0) { 1475 ifp->if_opackets++; 1476 if (++tbd->tbd_used + BWI_TX_NSPRDESC >= BWI_TX_NDESC) 1477 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1478 tbd->tbd_idx = (idx + 1) % BWI_TX_NDESC; 1479 sc->sc_tx_timer = 5; 1480 } else { 1481 /* NB: m is reclaimed on encap failure */ 1482 ieee80211_free_node(ni); 1483 ifp->if_oerrors++; 1484 } 1485 BWI_UNLOCK(sc); 1486 return error; 1487 } 1488 1489 static void 1490 bwi_watchdog(void *arg) 1491 { 1492 struct bwi_softc *sc; 1493 struct ifnet *ifp; 1494 1495 sc = arg; 1496 ifp = sc->sc_ifp; 1497 BWI_ASSERT_LOCKED(sc); 1498 if (sc->sc_tx_timer != 0 && --sc->sc_tx_timer == 0) { 1499 if_printf(ifp, "watchdog timeout\n"); 1500 ifp->if_oerrors++; 1501 taskqueue_enqueue(sc->sc_tq, &sc->sc_restart_task); 1502 } 1503 callout_reset(&sc->sc_watchdog_timer, hz, bwi_watchdog, sc); 1504 } 1505 1506 static void 1507 bwi_stop(struct bwi_softc *sc, int statechg) 1508 { 1509 BWI_LOCK(sc); 1510 bwi_stop_locked(sc, statechg); 1511 BWI_UNLOCK(sc); 1512 } 1513 1514 static void 1515 bwi_stop_locked(struct bwi_softc *sc, int statechg) 1516 { 1517 struct ifnet *ifp = sc->sc_ifp; 1518 struct bwi_mac *mac; 1519 int i, error, pwr_off = 0; 1520 1521 BWI_ASSERT_LOCKED(sc); 1522 1523 callout_stop(&sc->sc_calib_ch); 1524 callout_stop(&sc->sc_led_blink_ch); 1525 sc->sc_led_blinking = 0; 1526 sc->sc_flags |= BWI_F_STOP; 1527 1528 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 1529 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 1530 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 1531 mac = (struct bwi_mac *)sc->sc_cur_regwin; 1532 1533 bwi_disable_intrs(sc, BWI_ALL_INTRS); 1534 CSR_READ_4(sc, BWI_MAC_INTR_MASK); 1535 bwi_mac_stop(mac); 1536 } 1537 1538 for (i = 0; i < sc->sc_nmac; ++i) { 1539 struct bwi_regwin *old_rw; 1540 1541 mac = &sc->sc_mac[i]; 1542 if ((mac->mac_flags & BWI_MAC_F_INITED) == 0) 1543 continue; 1544 1545 error = bwi_regwin_switch(sc, &mac->mac_regwin, &old_rw); 1546 if (error) 1547 continue; 1548 1549 bwi_mac_shutdown(mac); 1550 pwr_off = 1; 1551 1552 bwi_regwin_switch(sc, old_rw, NULL); 1553 } 1554 1555 if (pwr_off) 1556 bwi_bbp_power_off(sc); 1557 1558 sc->sc_tx_timer = 0; 1559 callout_stop(&sc->sc_watchdog_timer); 1560 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1561 } 1562 1563 void 1564 bwi_intr(void *xsc) 1565 { 1566 struct bwi_softc *sc = xsc; 1567 struct ifnet *ifp = sc->sc_ifp; 1568 struct bwi_mac *mac; 1569 uint32_t intr_status; 1570 uint32_t txrx_intr_status[BWI_TXRX_NRING]; 1571 int i, txrx_error, tx = 0, rx_data = -1; 1572 1573 BWI_LOCK(sc); 1574 1575 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 || 1576 (sc->sc_flags & BWI_F_STOP)) { 1577 BWI_UNLOCK(sc); 1578 return; 1579 } 1580 /* 1581 * Get interrupt status 1582 */ 1583 intr_status = CSR_READ_4(sc, BWI_MAC_INTR_STATUS); 1584 if (intr_status == 0xffffffff) { /* Not for us */ 1585 BWI_UNLOCK(sc); 1586 return; 1587 } 1588 1589 DPRINTF(sc, BWI_DBG_INTR, "intr status 0x%08x\n", intr_status); 1590 1591 intr_status &= CSR_READ_4(sc, BWI_MAC_INTR_MASK); 1592 if (intr_status == 0) { /* Nothing is interesting */ 1593 BWI_UNLOCK(sc); 1594 return; 1595 } 1596 1597 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 1598 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 1599 mac = (struct bwi_mac *)sc->sc_cur_regwin; 1600 1601 txrx_error = 0; 1602 DPRINTF(sc, BWI_DBG_INTR, "%s\n", "TX/RX intr"); 1603 for (i = 0; i < BWI_TXRX_NRING; ++i) { 1604 uint32_t mask; 1605 1606 if (BWI_TXRX_IS_RX(i)) 1607 mask = BWI_TXRX_RX_INTRS; 1608 else 1609 mask = BWI_TXRX_TX_INTRS; 1610 1611 txrx_intr_status[i] = 1612 CSR_READ_4(sc, BWI_TXRX_INTR_STATUS(i)) & mask; 1613 1614 _DPRINTF(sc, BWI_DBG_INTR, ", %d 0x%08x", 1615 i, txrx_intr_status[i]); 1616 1617 if (txrx_intr_status[i] & BWI_TXRX_INTR_ERROR) { 1618 if_printf(ifp, 1619 "%s: intr fatal TX/RX (%d) error 0x%08x\n", 1620 __func__, i, txrx_intr_status[i]); 1621 txrx_error = 1; 1622 } 1623 } 1624 _DPRINTF(sc, BWI_DBG_INTR, "%s\n", ""); 1625 1626 /* 1627 * Acknowledge interrupt 1628 */ 1629 CSR_WRITE_4(sc, BWI_MAC_INTR_STATUS, intr_status); 1630 1631 for (i = 0; i < BWI_TXRX_NRING; ++i) 1632 CSR_WRITE_4(sc, BWI_TXRX_INTR_STATUS(i), txrx_intr_status[i]); 1633 1634 /* Disable all interrupts */ 1635 bwi_disable_intrs(sc, BWI_ALL_INTRS); 1636 1637 /* 1638 * http://bcm-specs.sipsolutions.net/Interrupts 1639 * Says for this bit (0x800): 1640 * "Fatal Error 1641 * 1642 * We got this one while testing things when by accident the 1643 * template ram wasn't set to big endian when it should have 1644 * been after writing the initial values. It keeps on being 1645 * triggered, the only way to stop it seems to shut down the 1646 * chip." 1647 * 1648 * Suggesting that we should never get it and if we do we're not 1649 * feeding TX packets into the MAC correctly if we do... Apparently, 1650 * it is valid only on mac version 5 and higher, but I couldn't 1651 * find a reference for that... Since I see them from time to time 1652 * on my card, this suggests an error in the tx path still... 1653 */ 1654 if (intr_status & BWI_INTR_PHY_TXERR) { 1655 if (mac->mac_flags & BWI_MAC_F_PHYE_RESET) { 1656 if_printf(ifp, "%s: intr PHY TX error\n", __func__); 1657 taskqueue_enqueue(sc->sc_tq, &sc->sc_restart_task); 1658 BWI_UNLOCK(sc); 1659 return; 1660 } 1661 } 1662 1663 if (txrx_error) { 1664 /* TODO: reset device */ 1665 } 1666 1667 if (intr_status & BWI_INTR_TBTT) 1668 bwi_mac_config_ps(mac); 1669 1670 if (intr_status & BWI_INTR_EO_ATIM) 1671 if_printf(ifp, "EO_ATIM\n"); 1672 1673 if (intr_status & BWI_INTR_PMQ) { 1674 for (;;) { 1675 if ((CSR_READ_4(sc, BWI_MAC_PS_STATUS) & 0x8) == 0) 1676 break; 1677 } 1678 CSR_WRITE_2(sc, BWI_MAC_PS_STATUS, 0x2); 1679 } 1680 1681 if (intr_status & BWI_INTR_NOISE) 1682 if_printf(ifp, "intr noise\n"); 1683 1684 if (txrx_intr_status[0] & BWI_TXRX_INTR_RX) { 1685 rx_data = sc->sc_rxeof(sc); 1686 if (sc->sc_flags & BWI_F_STOP) { 1687 BWI_UNLOCK(sc); 1688 return; 1689 } 1690 } 1691 1692 if (txrx_intr_status[3] & BWI_TXRX_INTR_RX) { 1693 sc->sc_txeof_status(sc); 1694 tx = 1; 1695 } 1696 1697 if (intr_status & BWI_INTR_TX_DONE) { 1698 bwi_txeof(sc); 1699 tx = 1; 1700 } 1701 1702 /* Re-enable interrupts */ 1703 bwi_enable_intrs(sc, BWI_INIT_INTRS); 1704 1705 if (sc->sc_blink_led != NULL && sc->sc_led_blink) { 1706 int evt = BWI_LED_EVENT_NONE; 1707 1708 if (tx && rx_data > 0) { 1709 if (sc->sc_rx_rate > sc->sc_tx_rate) 1710 evt = BWI_LED_EVENT_RX; 1711 else 1712 evt = BWI_LED_EVENT_TX; 1713 } else if (tx) { 1714 evt = BWI_LED_EVENT_TX; 1715 } else if (rx_data > 0) { 1716 evt = BWI_LED_EVENT_RX; 1717 } else if (rx_data == 0) { 1718 evt = BWI_LED_EVENT_POLL; 1719 } 1720 1721 if (evt != BWI_LED_EVENT_NONE) 1722 bwi_led_event(sc, evt); 1723 } 1724 1725 BWI_UNLOCK(sc); 1726 } 1727 1728 static void 1729 bwi_scan_start(struct ieee80211com *ic) 1730 { 1731 struct bwi_softc *sc = ic->ic_ifp->if_softc; 1732 1733 BWI_LOCK(sc); 1734 /* Enable MAC beacon promiscuity */ 1735 CSR_SETBITS_4(sc, BWI_MAC_STATUS, BWI_MAC_STATUS_PASS_BCN); 1736 BWI_UNLOCK(sc); 1737 } 1738 1739 static void 1740 bwi_set_channel(struct ieee80211com *ic) 1741 { 1742 struct bwi_softc *sc = ic->ic_ifp->if_softc; 1743 struct ieee80211_channel *c = ic->ic_curchan; 1744 struct bwi_mac *mac; 1745 1746 BWI_LOCK(sc); 1747 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 1748 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 1749 mac = (struct bwi_mac *)sc->sc_cur_regwin; 1750 bwi_rf_set_chan(mac, ieee80211_chan2ieee(ic, c), 0); 1751 1752 sc->sc_rates = ieee80211_get_ratetable(c); 1753 1754 /* 1755 * Setup radio tap channel freq and flags 1756 */ 1757 sc->sc_tx_th.wt_chan_freq = sc->sc_rx_th.wr_chan_freq = 1758 htole16(c->ic_freq); 1759 sc->sc_tx_th.wt_chan_flags = sc->sc_rx_th.wr_chan_flags = 1760 htole16(c->ic_flags & 0xffff); 1761 1762 BWI_UNLOCK(sc); 1763 } 1764 1765 static void 1766 bwi_scan_end(struct ieee80211com *ic) 1767 { 1768 struct bwi_softc *sc = ic->ic_ifp->if_softc; 1769 1770 BWI_LOCK(sc); 1771 CSR_CLRBITS_4(sc, BWI_MAC_STATUS, BWI_MAC_STATUS_PASS_BCN); 1772 BWI_UNLOCK(sc); 1773 } 1774 1775 static int 1776 bwi_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) 1777 { 1778 struct bwi_vap *bvp = BWI_VAP(vap); 1779 struct ieee80211com *ic= vap->iv_ic; 1780 struct ifnet *ifp = ic->ic_ifp; 1781 enum ieee80211_state ostate = vap->iv_state; 1782 struct bwi_softc *sc = ifp->if_softc; 1783 struct bwi_mac *mac; 1784 struct ieee80211_node *ni = vap->iv_bss; 1785 int error; 1786 1787 BWI_LOCK(sc); 1788 1789 callout_stop(&sc->sc_calib_ch); 1790 1791 if (nstate == IEEE80211_S_INIT) 1792 sc->sc_txpwrcb_type = BWI_TXPWR_INIT; 1793 1794 bwi_led_newstate(sc, nstate); 1795 1796 error = bvp->bv_newstate(vap, nstate, arg); 1797 if (error != 0) 1798 goto back; 1799 1800 /* 1801 * Clear the BSSID when we stop a STA 1802 */ 1803 if (vap->iv_opmode == IEEE80211_M_STA) { 1804 if (ostate == IEEE80211_S_RUN && nstate != IEEE80211_S_RUN) { 1805 /* 1806 * Clear out the BSSID. If we reassociate to 1807 * the same AP, this will reinialize things 1808 * correctly... 1809 */ 1810 if (ic->ic_opmode == IEEE80211_M_STA && 1811 !(sc->sc_flags & BWI_F_STOP)) 1812 bwi_set_bssid(sc, bwi_zero_addr); 1813 } 1814 } 1815 1816 if (vap->iv_opmode == IEEE80211_M_MONITOR) { 1817 /* Nothing to do */ 1818 } else if (nstate == IEEE80211_S_RUN) { 1819 bwi_set_bssid(sc, vap->iv_bss->ni_bssid); 1820 1821 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 1822 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 1823 mac = (struct bwi_mac *)sc->sc_cur_regwin; 1824 1825 /* Initial TX power calibration */ 1826 bwi_mac_calibrate_txpower(mac, BWI_TXPWR_INIT); 1827 #ifdef notyet 1828 sc->sc_txpwrcb_type = BWI_TXPWR_FORCE; 1829 #else 1830 sc->sc_txpwrcb_type = BWI_TXPWR_CALIB; 1831 #endif 1832 if (vap->iv_opmode == IEEE80211_M_STA) { 1833 /* fake a join to init the tx rate */ 1834 bwi_newassoc(ni, 1); 1835 } 1836 1837 callout_reset(&sc->sc_calib_ch, hz, bwi_calibrate, sc); 1838 } 1839 back: 1840 BWI_UNLOCK(sc); 1841 1842 return error; 1843 } 1844 1845 /* ARGUSED */ 1846 static struct ieee80211_node * 1847 bwi_node_alloc(struct ieee80211vap *vap, const uint8_t mac[IEEE80211_ADDR_LEN]) 1848 { 1849 struct bwi_node *bn; 1850 1851 bn = malloc(sizeof(struct bwi_node), M_80211_NODE, M_NOWAIT | M_ZERO); 1852 return bn != NULL ? &bn->ni : NULL; 1853 } 1854 1855 static void 1856 bwi_newassoc(struct ieee80211_node *ni, int isnew) 1857 { 1858 struct ieee80211vap *vap = ni->ni_vap; 1859 1860 ieee80211_amrr_node_init(&BWI_VAP(vap)->bv_amrr, 1861 &BWI_NODE(ni)->amn, ni); 1862 } 1863 1864 static int 1865 bwi_media_change(struct ifnet *ifp) 1866 { 1867 int error = ieee80211_media_change(ifp); 1868 /* NB: only the fixed rate can change and that doesn't need a reset */ 1869 return (error == ENETRESET ? 0 : error); 1870 } 1871 1872 static int 1873 bwi_dma_alloc(struct bwi_softc *sc) 1874 { 1875 int error, i, has_txstats; 1876 bus_addr_t lowaddr = 0; 1877 bus_size_t tx_ring_sz, rx_ring_sz, desc_sz = 0; 1878 uint32_t txrx_ctrl_step = 0; 1879 1880 has_txstats = 0; 1881 for (i = 0; i < sc->sc_nmac; ++i) { 1882 if (sc->sc_mac[i].mac_flags & BWI_MAC_F_HAS_TXSTATS) { 1883 has_txstats = 1; 1884 break; 1885 } 1886 } 1887 1888 switch (sc->sc_bus_space) { 1889 case BWI_BUS_SPACE_30BIT: 1890 case BWI_BUS_SPACE_32BIT: 1891 if (sc->sc_bus_space == BWI_BUS_SPACE_30BIT) 1892 lowaddr = BWI_BUS_SPACE_MAXADDR; 1893 else 1894 lowaddr = BUS_SPACE_MAXADDR_32BIT; 1895 desc_sz = sizeof(struct bwi_desc32); 1896 txrx_ctrl_step = 0x20; 1897 1898 sc->sc_init_tx_ring = bwi_init_tx_ring32; 1899 sc->sc_free_tx_ring = bwi_free_tx_ring32; 1900 sc->sc_init_rx_ring = bwi_init_rx_ring32; 1901 sc->sc_free_rx_ring = bwi_free_rx_ring32; 1902 sc->sc_setup_rxdesc = bwi_setup_rx_desc32; 1903 sc->sc_setup_txdesc = bwi_setup_tx_desc32; 1904 sc->sc_rxeof = bwi_rxeof32; 1905 sc->sc_start_tx = bwi_start_tx32; 1906 if (has_txstats) { 1907 sc->sc_init_txstats = bwi_init_txstats32; 1908 sc->sc_free_txstats = bwi_free_txstats32; 1909 sc->sc_txeof_status = bwi_txeof_status32; 1910 } 1911 break; 1912 1913 case BWI_BUS_SPACE_64BIT: 1914 lowaddr = BUS_SPACE_MAXADDR; /* XXX */ 1915 desc_sz = sizeof(struct bwi_desc64); 1916 txrx_ctrl_step = 0x40; 1917 1918 sc->sc_init_tx_ring = bwi_init_tx_ring64; 1919 sc->sc_free_tx_ring = bwi_free_tx_ring64; 1920 sc->sc_init_rx_ring = bwi_init_rx_ring64; 1921 sc->sc_free_rx_ring = bwi_free_rx_ring64; 1922 sc->sc_setup_rxdesc = bwi_setup_rx_desc64; 1923 sc->sc_setup_txdesc = bwi_setup_tx_desc64; 1924 sc->sc_rxeof = bwi_rxeof64; 1925 sc->sc_start_tx = bwi_start_tx64; 1926 if (has_txstats) { 1927 sc->sc_init_txstats = bwi_init_txstats64; 1928 sc->sc_free_txstats = bwi_free_txstats64; 1929 sc->sc_txeof_status = bwi_txeof_status64; 1930 } 1931 break; 1932 } 1933 1934 KASSERT(lowaddr != 0, ("lowaddr zero")); 1935 KASSERT(desc_sz != 0, ("desc_sz zero")); 1936 KASSERT(txrx_ctrl_step != 0, ("txrx_ctrl_step zero")); 1937 1938 tx_ring_sz = roundup(desc_sz * BWI_TX_NDESC, BWI_RING_ALIGN); 1939 rx_ring_sz = roundup(desc_sz * BWI_RX_NDESC, BWI_RING_ALIGN); 1940 1941 /* 1942 * Create top level DMA tag 1943 */ 1944 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), /* parent */ 1945 BWI_ALIGN, 0, /* alignment, bounds */ 1946 lowaddr, /* lowaddr */ 1947 BUS_SPACE_MAXADDR, /* highaddr */ 1948 NULL, NULL, /* filter, filterarg */ 1949 MAXBSIZE, /* maxsize */ 1950 BUS_SPACE_UNRESTRICTED, /* nsegments */ 1951 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1952 BUS_DMA_ALLOCNOW, /* flags */ 1953 NULL, NULL, /* lockfunc, lockarg */ 1954 &sc->sc_parent_dtag); 1955 if (error) { 1956 device_printf(sc->sc_dev, "can't create parent DMA tag\n"); 1957 return error; 1958 } 1959 1960 #define TXRX_CTRL(idx) (BWI_TXRX_CTRL_BASE + (idx) * txrx_ctrl_step) 1961 1962 /* 1963 * Create TX ring DMA stuffs 1964 */ 1965 error = bus_dma_tag_create(sc->sc_parent_dtag, 1966 BWI_RING_ALIGN, 0, 1967 BUS_SPACE_MAXADDR, 1968 BUS_SPACE_MAXADDR, 1969 NULL, NULL, 1970 tx_ring_sz, 1971 1, 1972 BUS_SPACE_MAXSIZE_32BIT, 1973 BUS_DMA_ALLOCNOW, 1974 NULL, NULL, 1975 &sc->sc_txring_dtag); 1976 if (error) { 1977 device_printf(sc->sc_dev, "can't create TX ring DMA tag\n"); 1978 return error; 1979 } 1980 1981 for (i = 0; i < BWI_TX_NRING; ++i) { 1982 error = bwi_dma_ring_alloc(sc, sc->sc_txring_dtag, 1983 &sc->sc_tx_rdata[i], tx_ring_sz, 1984 TXRX_CTRL(i)); 1985 if (error) { 1986 device_printf(sc->sc_dev, "%dth TX ring " 1987 "DMA alloc failed\n", i); 1988 return error; 1989 } 1990 } 1991 1992 /* 1993 * Create RX ring DMA stuffs 1994 */ 1995 error = bus_dma_tag_create(sc->sc_parent_dtag, 1996 BWI_RING_ALIGN, 0, 1997 BUS_SPACE_MAXADDR, 1998 BUS_SPACE_MAXADDR, 1999 NULL, NULL, 2000 rx_ring_sz, 2001 1, 2002 BUS_SPACE_MAXSIZE_32BIT, 2003 BUS_DMA_ALLOCNOW, 2004 NULL, NULL, 2005 &sc->sc_rxring_dtag); 2006 if (error) { 2007 device_printf(sc->sc_dev, "can't create RX ring DMA tag\n"); 2008 return error; 2009 } 2010 2011 error = bwi_dma_ring_alloc(sc, sc->sc_rxring_dtag, &sc->sc_rx_rdata, 2012 rx_ring_sz, TXRX_CTRL(0)); 2013 if (error) { 2014 device_printf(sc->sc_dev, "RX ring DMA alloc failed\n"); 2015 return error; 2016 } 2017 2018 if (has_txstats) { 2019 error = bwi_dma_txstats_alloc(sc, TXRX_CTRL(3), desc_sz); 2020 if (error) { 2021 device_printf(sc->sc_dev, 2022 "TX stats DMA alloc failed\n"); 2023 return error; 2024 } 2025 } 2026 2027 #undef TXRX_CTRL 2028 2029 return bwi_dma_mbuf_create(sc); 2030 } 2031 2032 static void 2033 bwi_dma_free(struct bwi_softc *sc) 2034 { 2035 if (sc->sc_txring_dtag != NULL) { 2036 int i; 2037 2038 for (i = 0; i < BWI_TX_NRING; ++i) { 2039 struct bwi_ring_data *rd = &sc->sc_tx_rdata[i]; 2040 2041 if (rd->rdata_desc != NULL) { 2042 bus_dmamap_unload(sc->sc_txring_dtag, 2043 rd->rdata_dmap); 2044 bus_dmamem_free(sc->sc_txring_dtag, 2045 rd->rdata_desc, 2046 rd->rdata_dmap); 2047 } 2048 } 2049 bus_dma_tag_destroy(sc->sc_txring_dtag); 2050 } 2051 2052 if (sc->sc_rxring_dtag != NULL) { 2053 struct bwi_ring_data *rd = &sc->sc_rx_rdata; 2054 2055 if (rd->rdata_desc != NULL) { 2056 bus_dmamap_unload(sc->sc_rxring_dtag, rd->rdata_dmap); 2057 bus_dmamem_free(sc->sc_rxring_dtag, rd->rdata_desc, 2058 rd->rdata_dmap); 2059 } 2060 bus_dma_tag_destroy(sc->sc_rxring_dtag); 2061 } 2062 2063 bwi_dma_txstats_free(sc); 2064 bwi_dma_mbuf_destroy(sc, BWI_TX_NRING, 1); 2065 2066 if (sc->sc_parent_dtag != NULL) 2067 bus_dma_tag_destroy(sc->sc_parent_dtag); 2068 } 2069 2070 static int 2071 bwi_dma_ring_alloc(struct bwi_softc *sc, bus_dma_tag_t dtag, 2072 struct bwi_ring_data *rd, bus_size_t size, 2073 uint32_t txrx_ctrl) 2074 { 2075 int error; 2076 2077 error = bus_dmamem_alloc(dtag, &rd->rdata_desc, 2078 BUS_DMA_WAITOK | BUS_DMA_ZERO, 2079 &rd->rdata_dmap); 2080 if (error) { 2081 device_printf(sc->sc_dev, "can't allocate DMA mem\n"); 2082 return error; 2083 } 2084 2085 error = bus_dmamap_load(dtag, rd->rdata_dmap, rd->rdata_desc, size, 2086 bwi_dma_ring_addr, &rd->rdata_paddr, 2087 BUS_DMA_NOWAIT); 2088 if (error) { 2089 device_printf(sc->sc_dev, "can't load DMA mem\n"); 2090 bus_dmamem_free(dtag, rd->rdata_desc, rd->rdata_dmap); 2091 rd->rdata_desc = NULL; 2092 return error; 2093 } 2094 2095 rd->rdata_txrx_ctrl = txrx_ctrl; 2096 return 0; 2097 } 2098 2099 static int 2100 bwi_dma_txstats_alloc(struct bwi_softc *sc, uint32_t ctrl_base, 2101 bus_size_t desc_sz) 2102 { 2103 struct bwi_txstats_data *st; 2104 bus_size_t dma_size; 2105 int error; 2106 2107 st = malloc(sizeof(*st), M_DEVBUF, M_NOWAIT | M_ZERO); 2108 if (st == NULL) { 2109 device_printf(sc->sc_dev, "can't allocate txstats data\n"); 2110 return ENOMEM; 2111 } 2112 sc->sc_txstats = st; 2113 2114 /* 2115 * Create TX stats descriptor DMA stuffs 2116 */ 2117 dma_size = roundup(desc_sz * BWI_TXSTATS_NDESC, BWI_RING_ALIGN); 2118 2119 error = bus_dma_tag_create(sc->sc_parent_dtag, 2120 BWI_RING_ALIGN, 2121 0, 2122 BUS_SPACE_MAXADDR, 2123 BUS_SPACE_MAXADDR, 2124 NULL, NULL, 2125 dma_size, 2126 1, 2127 BUS_SPACE_MAXSIZE_32BIT, 2128 BUS_DMA_ALLOCNOW, 2129 NULL, NULL, 2130 &st->stats_ring_dtag); 2131 if (error) { 2132 device_printf(sc->sc_dev, "can't create txstats ring " 2133 "DMA tag\n"); 2134 return error; 2135 } 2136 2137 error = bus_dmamem_alloc(st->stats_ring_dtag, &st->stats_ring, 2138 BUS_DMA_WAITOK | BUS_DMA_ZERO, 2139 &st->stats_ring_dmap); 2140 if (error) { 2141 device_printf(sc->sc_dev, "can't allocate txstats ring " 2142 "DMA mem\n"); 2143 bus_dma_tag_destroy(st->stats_ring_dtag); 2144 st->stats_ring_dtag = NULL; 2145 return error; 2146 } 2147 2148 error = bus_dmamap_load(st->stats_ring_dtag, st->stats_ring_dmap, 2149 st->stats_ring, dma_size, 2150 bwi_dma_ring_addr, &st->stats_ring_paddr, 2151 BUS_DMA_NOWAIT); 2152 if (error) { 2153 device_printf(sc->sc_dev, "can't load txstats ring DMA mem\n"); 2154 bus_dmamem_free(st->stats_ring_dtag, st->stats_ring, 2155 st->stats_ring_dmap); 2156 bus_dma_tag_destroy(st->stats_ring_dtag); 2157 st->stats_ring_dtag = NULL; 2158 return error; 2159 } 2160 2161 /* 2162 * Create TX stats DMA stuffs 2163 */ 2164 dma_size = roundup(sizeof(struct bwi_txstats) * BWI_TXSTATS_NDESC, 2165 BWI_ALIGN); 2166 2167 error = bus_dma_tag_create(sc->sc_parent_dtag, 2168 BWI_ALIGN, 2169 0, 2170 BUS_SPACE_MAXADDR, 2171 BUS_SPACE_MAXADDR, 2172 NULL, NULL, 2173 dma_size, 2174 1, 2175 BUS_SPACE_MAXSIZE_32BIT, 2176 BUS_DMA_ALLOCNOW, 2177 NULL, NULL, 2178 &st->stats_dtag); 2179 if (error) { 2180 device_printf(sc->sc_dev, "can't create txstats DMA tag\n"); 2181 return error; 2182 } 2183 2184 error = bus_dmamem_alloc(st->stats_dtag, (void **)&st->stats, 2185 BUS_DMA_WAITOK | BUS_DMA_ZERO, 2186 &st->stats_dmap); 2187 if (error) { 2188 device_printf(sc->sc_dev, "can't allocate txstats DMA mem\n"); 2189 bus_dma_tag_destroy(st->stats_dtag); 2190 st->stats_dtag = NULL; 2191 return error; 2192 } 2193 2194 error = bus_dmamap_load(st->stats_dtag, st->stats_dmap, st->stats, 2195 dma_size, bwi_dma_ring_addr, &st->stats_paddr, 2196 BUS_DMA_NOWAIT); 2197 if (error) { 2198 device_printf(sc->sc_dev, "can't load txstats DMA mem\n"); 2199 bus_dmamem_free(st->stats_dtag, st->stats, st->stats_dmap); 2200 bus_dma_tag_destroy(st->stats_dtag); 2201 st->stats_dtag = NULL; 2202 return error; 2203 } 2204 2205 st->stats_ctrl_base = ctrl_base; 2206 return 0; 2207 } 2208 2209 static void 2210 bwi_dma_txstats_free(struct bwi_softc *sc) 2211 { 2212 struct bwi_txstats_data *st; 2213 2214 if (sc->sc_txstats == NULL) 2215 return; 2216 st = sc->sc_txstats; 2217 2218 if (st->stats_ring_dtag != NULL) { 2219 bus_dmamap_unload(st->stats_ring_dtag, st->stats_ring_dmap); 2220 bus_dmamem_free(st->stats_ring_dtag, st->stats_ring, 2221 st->stats_ring_dmap); 2222 bus_dma_tag_destroy(st->stats_ring_dtag); 2223 } 2224 2225 if (st->stats_dtag != NULL) { 2226 bus_dmamap_unload(st->stats_dtag, st->stats_dmap); 2227 bus_dmamem_free(st->stats_dtag, st->stats, st->stats_dmap); 2228 bus_dma_tag_destroy(st->stats_dtag); 2229 } 2230 2231 free(st, M_DEVBUF); 2232 } 2233 2234 static void 2235 bwi_dma_ring_addr(void *arg, bus_dma_segment_t *seg, int nseg, int error) 2236 { 2237 KASSERT(nseg == 1, ("too many segments\n")); 2238 *((bus_addr_t *)arg) = seg->ds_addr; 2239 } 2240 2241 static int 2242 bwi_dma_mbuf_create(struct bwi_softc *sc) 2243 { 2244 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata; 2245 int i, j, k, ntx, error; 2246 2247 /* 2248 * Create TX/RX mbuf DMA tag 2249 */ 2250 error = bus_dma_tag_create(sc->sc_parent_dtag, 2251 1, 2252 0, 2253 BUS_SPACE_MAXADDR, 2254 BUS_SPACE_MAXADDR, 2255 NULL, NULL, 2256 MCLBYTES, 2257 1, 2258 BUS_SPACE_MAXSIZE_32BIT, 2259 BUS_DMA_ALLOCNOW, 2260 NULL, NULL, 2261 &sc->sc_buf_dtag); 2262 if (error) { 2263 device_printf(sc->sc_dev, "can't create mbuf DMA tag\n"); 2264 return error; 2265 } 2266 2267 ntx = 0; 2268 2269 /* 2270 * Create TX mbuf DMA map 2271 */ 2272 for (i = 0; i < BWI_TX_NRING; ++i) { 2273 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[i]; 2274 2275 for (j = 0; j < BWI_TX_NDESC; ++j) { 2276 error = bus_dmamap_create(sc->sc_buf_dtag, 0, 2277 &tbd->tbd_buf[j].tb_dmap); 2278 if (error) { 2279 device_printf(sc->sc_dev, "can't create " 2280 "%dth tbd, %dth DMA map\n", i, j); 2281 2282 ntx = i; 2283 for (k = 0; k < j; ++k) { 2284 bus_dmamap_destroy(sc->sc_buf_dtag, 2285 tbd->tbd_buf[k].tb_dmap); 2286 } 2287 goto fail; 2288 } 2289 } 2290 } 2291 ntx = BWI_TX_NRING; 2292 2293 /* 2294 * Create RX mbuf DMA map and a spare DMA map 2295 */ 2296 error = bus_dmamap_create(sc->sc_buf_dtag, 0, 2297 &rbd->rbd_tmp_dmap); 2298 if (error) { 2299 device_printf(sc->sc_dev, 2300 "can't create spare RX buf DMA map\n"); 2301 goto fail; 2302 } 2303 2304 for (j = 0; j < BWI_RX_NDESC; ++j) { 2305 error = bus_dmamap_create(sc->sc_buf_dtag, 0, 2306 &rbd->rbd_buf[j].rb_dmap); 2307 if (error) { 2308 device_printf(sc->sc_dev, "can't create %dth " 2309 "RX buf DMA map\n", j); 2310 2311 for (k = 0; k < j; ++k) { 2312 bus_dmamap_destroy(sc->sc_buf_dtag, 2313 rbd->rbd_buf[j].rb_dmap); 2314 } 2315 bus_dmamap_destroy(sc->sc_buf_dtag, 2316 rbd->rbd_tmp_dmap); 2317 goto fail; 2318 } 2319 } 2320 2321 return 0; 2322 fail: 2323 bwi_dma_mbuf_destroy(sc, ntx, 0); 2324 return error; 2325 } 2326 2327 static void 2328 bwi_dma_mbuf_destroy(struct bwi_softc *sc, int ntx, int nrx) 2329 { 2330 int i, j; 2331 2332 if (sc->sc_buf_dtag == NULL) 2333 return; 2334 2335 for (i = 0; i < ntx; ++i) { 2336 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[i]; 2337 2338 for (j = 0; j < BWI_TX_NDESC; ++j) { 2339 struct bwi_txbuf *tb = &tbd->tbd_buf[j]; 2340 2341 if (tb->tb_mbuf != NULL) { 2342 bus_dmamap_unload(sc->sc_buf_dtag, 2343 tb->tb_dmap); 2344 m_freem(tb->tb_mbuf); 2345 } 2346 if (tb->tb_ni != NULL) 2347 ieee80211_free_node(tb->tb_ni); 2348 bus_dmamap_destroy(sc->sc_buf_dtag, tb->tb_dmap); 2349 } 2350 } 2351 2352 if (nrx) { 2353 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata; 2354 2355 bus_dmamap_destroy(sc->sc_buf_dtag, rbd->rbd_tmp_dmap); 2356 for (j = 0; j < BWI_RX_NDESC; ++j) { 2357 struct bwi_rxbuf *rb = &rbd->rbd_buf[j]; 2358 2359 if (rb->rb_mbuf != NULL) { 2360 bus_dmamap_unload(sc->sc_buf_dtag, 2361 rb->rb_dmap); 2362 m_freem(rb->rb_mbuf); 2363 } 2364 bus_dmamap_destroy(sc->sc_buf_dtag, rb->rb_dmap); 2365 } 2366 } 2367 2368 bus_dma_tag_destroy(sc->sc_buf_dtag); 2369 sc->sc_buf_dtag = NULL; 2370 } 2371 2372 static void 2373 bwi_enable_intrs(struct bwi_softc *sc, uint32_t enable_intrs) 2374 { 2375 CSR_SETBITS_4(sc, BWI_MAC_INTR_MASK, enable_intrs); 2376 } 2377 2378 static void 2379 bwi_disable_intrs(struct bwi_softc *sc, uint32_t disable_intrs) 2380 { 2381 CSR_CLRBITS_4(sc, BWI_MAC_INTR_MASK, disable_intrs); 2382 } 2383 2384 static int 2385 bwi_init_tx_ring32(struct bwi_softc *sc, int ring_idx) 2386 { 2387 struct bwi_ring_data *rd; 2388 struct bwi_txbuf_data *tbd; 2389 uint32_t val, addr_hi, addr_lo; 2390 2391 KASSERT(ring_idx < BWI_TX_NRING, ("ring_idx %d", ring_idx)); 2392 rd = &sc->sc_tx_rdata[ring_idx]; 2393 tbd = &sc->sc_tx_bdata[ring_idx]; 2394 2395 tbd->tbd_idx = 0; 2396 tbd->tbd_used = 0; 2397 2398 bzero(rd->rdata_desc, sizeof(struct bwi_desc32) * BWI_TX_NDESC); 2399 bus_dmamap_sync(sc->sc_txring_dtag, rd->rdata_dmap, 2400 BUS_DMASYNC_PREWRITE); 2401 2402 addr_lo = __SHIFTOUT(rd->rdata_paddr, BWI_TXRX32_RINGINFO_ADDR_MASK); 2403 addr_hi = __SHIFTOUT(rd->rdata_paddr, BWI_TXRX32_RINGINFO_FUNC_MASK); 2404 2405 val = __SHIFTIN(addr_lo, BWI_TXRX32_RINGINFO_ADDR_MASK) | 2406 __SHIFTIN(BWI_TXRX32_RINGINFO_FUNC_TXRX, 2407 BWI_TXRX32_RINGINFO_FUNC_MASK); 2408 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_RINGINFO, val); 2409 2410 val = __SHIFTIN(addr_hi, BWI_TXRX32_CTRL_ADDRHI_MASK) | 2411 BWI_TXRX32_CTRL_ENABLE; 2412 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_CTRL, val); 2413 2414 return 0; 2415 } 2416 2417 static void 2418 bwi_init_rxdesc_ring32(struct bwi_softc *sc, uint32_t ctrl_base, 2419 bus_addr_t paddr, int hdr_size, int ndesc) 2420 { 2421 uint32_t val, addr_hi, addr_lo; 2422 2423 addr_lo = __SHIFTOUT(paddr, BWI_TXRX32_RINGINFO_ADDR_MASK); 2424 addr_hi = __SHIFTOUT(paddr, BWI_TXRX32_RINGINFO_FUNC_MASK); 2425 2426 val = __SHIFTIN(addr_lo, BWI_TXRX32_RINGINFO_ADDR_MASK) | 2427 __SHIFTIN(BWI_TXRX32_RINGINFO_FUNC_TXRX, 2428 BWI_TXRX32_RINGINFO_FUNC_MASK); 2429 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_RINGINFO, val); 2430 2431 val = __SHIFTIN(hdr_size, BWI_RX32_CTRL_HDRSZ_MASK) | 2432 __SHIFTIN(addr_hi, BWI_TXRX32_CTRL_ADDRHI_MASK) | 2433 BWI_TXRX32_CTRL_ENABLE; 2434 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_CTRL, val); 2435 2436 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_INDEX, 2437 (ndesc - 1) * sizeof(struct bwi_desc32)); 2438 } 2439 2440 static int 2441 bwi_init_rx_ring32(struct bwi_softc *sc) 2442 { 2443 struct bwi_ring_data *rd = &sc->sc_rx_rdata; 2444 int i, error; 2445 2446 sc->sc_rx_bdata.rbd_idx = 0; 2447 2448 for (i = 0; i < BWI_RX_NDESC; ++i) { 2449 error = bwi_newbuf(sc, i, 1); 2450 if (error) { 2451 device_printf(sc->sc_dev, 2452 "can't allocate %dth RX buffer\n", i); 2453 return error; 2454 } 2455 } 2456 bus_dmamap_sync(sc->sc_rxring_dtag, rd->rdata_dmap, 2457 BUS_DMASYNC_PREWRITE); 2458 2459 bwi_init_rxdesc_ring32(sc, rd->rdata_txrx_ctrl, rd->rdata_paddr, 2460 sizeof(struct bwi_rxbuf_hdr), BWI_RX_NDESC); 2461 return 0; 2462 } 2463 2464 static int 2465 bwi_init_txstats32(struct bwi_softc *sc) 2466 { 2467 struct bwi_txstats_data *st = sc->sc_txstats; 2468 bus_addr_t stats_paddr; 2469 int i; 2470 2471 bzero(st->stats, BWI_TXSTATS_NDESC * sizeof(struct bwi_txstats)); 2472 bus_dmamap_sync(st->stats_dtag, st->stats_dmap, BUS_DMASYNC_PREWRITE); 2473 2474 st->stats_idx = 0; 2475 2476 stats_paddr = st->stats_paddr; 2477 for (i = 0; i < BWI_TXSTATS_NDESC; ++i) { 2478 bwi_setup_desc32(sc, st->stats_ring, BWI_TXSTATS_NDESC, i, 2479 stats_paddr, sizeof(struct bwi_txstats), 0); 2480 stats_paddr += sizeof(struct bwi_txstats); 2481 } 2482 bus_dmamap_sync(st->stats_ring_dtag, st->stats_ring_dmap, 2483 BUS_DMASYNC_PREWRITE); 2484 2485 bwi_init_rxdesc_ring32(sc, st->stats_ctrl_base, 2486 st->stats_ring_paddr, 0, BWI_TXSTATS_NDESC); 2487 return 0; 2488 } 2489 2490 static void 2491 bwi_setup_rx_desc32(struct bwi_softc *sc, int buf_idx, bus_addr_t paddr, 2492 int buf_len) 2493 { 2494 struct bwi_ring_data *rd = &sc->sc_rx_rdata; 2495 2496 KASSERT(buf_idx < BWI_RX_NDESC, ("buf_idx %d", buf_idx)); 2497 bwi_setup_desc32(sc, rd->rdata_desc, BWI_RX_NDESC, buf_idx, 2498 paddr, buf_len, 0); 2499 } 2500 2501 static void 2502 bwi_setup_tx_desc32(struct bwi_softc *sc, struct bwi_ring_data *rd, 2503 int buf_idx, bus_addr_t paddr, int buf_len) 2504 { 2505 KASSERT(buf_idx < BWI_TX_NDESC, ("buf_idx %d", buf_idx)); 2506 bwi_setup_desc32(sc, rd->rdata_desc, BWI_TX_NDESC, buf_idx, 2507 paddr, buf_len, 1); 2508 } 2509 2510 static int 2511 bwi_init_tx_ring64(struct bwi_softc *sc, int ring_idx) 2512 { 2513 /* TODO:64 */ 2514 return EOPNOTSUPP; 2515 } 2516 2517 static int 2518 bwi_init_rx_ring64(struct bwi_softc *sc) 2519 { 2520 /* TODO:64 */ 2521 return EOPNOTSUPP; 2522 } 2523 2524 static int 2525 bwi_init_txstats64(struct bwi_softc *sc) 2526 { 2527 /* TODO:64 */ 2528 return EOPNOTSUPP; 2529 } 2530 2531 static void 2532 bwi_setup_rx_desc64(struct bwi_softc *sc, int buf_idx, bus_addr_t paddr, 2533 int buf_len) 2534 { 2535 /* TODO:64 */ 2536 } 2537 2538 static void 2539 bwi_setup_tx_desc64(struct bwi_softc *sc, struct bwi_ring_data *rd, 2540 int buf_idx, bus_addr_t paddr, int buf_len) 2541 { 2542 /* TODO:64 */ 2543 } 2544 2545 static void 2546 bwi_dma_buf_addr(void *arg, bus_dma_segment_t *seg, int nseg, 2547 bus_size_t mapsz __unused, int error) 2548 { 2549 if (!error) { 2550 KASSERT(nseg == 1, ("too many segments(%d)\n", nseg)); 2551 *((bus_addr_t *)arg) = seg->ds_addr; 2552 } 2553 } 2554 2555 static int 2556 bwi_newbuf(struct bwi_softc *sc, int buf_idx, int init) 2557 { 2558 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata; 2559 struct bwi_rxbuf *rxbuf = &rbd->rbd_buf[buf_idx]; 2560 struct bwi_rxbuf_hdr *hdr; 2561 bus_dmamap_t map; 2562 bus_addr_t paddr; 2563 struct mbuf *m; 2564 int error; 2565 2566 KASSERT(buf_idx < BWI_RX_NDESC, ("buf_idx %d", buf_idx)); 2567 2568 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 2569 if (m == NULL) { 2570 error = ENOBUFS; 2571 2572 /* 2573 * If the NIC is up and running, we need to: 2574 * - Clear RX buffer's header. 2575 * - Restore RX descriptor settings. 2576 */ 2577 if (init) 2578 return error; 2579 else 2580 goto back; 2581 } 2582 m->m_len = m->m_pkthdr.len = MCLBYTES; 2583 2584 /* 2585 * Try to load RX buf into temporary DMA map 2586 */ 2587 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, rbd->rbd_tmp_dmap, m, 2588 bwi_dma_buf_addr, &paddr, BUS_DMA_NOWAIT); 2589 if (error) { 2590 m_freem(m); 2591 2592 /* 2593 * See the comment above 2594 */ 2595 if (init) 2596 return error; 2597 else 2598 goto back; 2599 } 2600 2601 if (!init) 2602 bus_dmamap_unload(sc->sc_buf_dtag, rxbuf->rb_dmap); 2603 rxbuf->rb_mbuf = m; 2604 rxbuf->rb_paddr = paddr; 2605 2606 /* 2607 * Swap RX buf's DMA map with the loaded temporary one 2608 */ 2609 map = rxbuf->rb_dmap; 2610 rxbuf->rb_dmap = rbd->rbd_tmp_dmap; 2611 rbd->rbd_tmp_dmap = map; 2612 2613 back: 2614 /* 2615 * Clear RX buf header 2616 */ 2617 hdr = mtod(rxbuf->rb_mbuf, struct bwi_rxbuf_hdr *); 2618 bzero(hdr, sizeof(*hdr)); 2619 bus_dmamap_sync(sc->sc_buf_dtag, rxbuf->rb_dmap, BUS_DMASYNC_PREWRITE); 2620 2621 /* 2622 * Setup RX buf descriptor 2623 */ 2624 sc->sc_setup_rxdesc(sc, buf_idx, rxbuf->rb_paddr, 2625 rxbuf->rb_mbuf->m_len - sizeof(*hdr)); 2626 return error; 2627 } 2628 2629 static void 2630 bwi_set_addr_filter(struct bwi_softc *sc, uint16_t addr_ofs, 2631 const uint8_t *addr) 2632 { 2633 int i; 2634 2635 CSR_WRITE_2(sc, BWI_ADDR_FILTER_CTRL, 2636 BWI_ADDR_FILTER_CTRL_SET | addr_ofs); 2637 2638 for (i = 0; i < (IEEE80211_ADDR_LEN / 2); ++i) { 2639 uint16_t addr_val; 2640 2641 addr_val = (uint16_t)addr[i * 2] | 2642 (((uint16_t)addr[(i * 2) + 1]) << 8); 2643 CSR_WRITE_2(sc, BWI_ADDR_FILTER_DATA, addr_val); 2644 } 2645 } 2646 2647 static int 2648 bwi_rxeof(struct bwi_softc *sc, int end_idx) 2649 { 2650 struct bwi_ring_data *rd = &sc->sc_rx_rdata; 2651 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata; 2652 struct ifnet *ifp = sc->sc_ifp; 2653 struct ieee80211com *ic = ifp->if_l2com; 2654 int idx, rx_data = 0; 2655 2656 idx = rbd->rbd_idx; 2657 while (idx != end_idx) { 2658 struct bwi_rxbuf *rb = &rbd->rbd_buf[idx]; 2659 struct bwi_rxbuf_hdr *hdr; 2660 struct ieee80211_frame_min *wh; 2661 struct ieee80211_node *ni; 2662 struct mbuf *m; 2663 const void *plcp; 2664 uint16_t flags2; 2665 int buflen, wh_ofs, hdr_extra, rssi, noise, type, rate; 2666 2667 m = rb->rb_mbuf; 2668 bus_dmamap_sync(sc->sc_buf_dtag, rb->rb_dmap, 2669 BUS_DMASYNC_POSTREAD); 2670 2671 if (bwi_newbuf(sc, idx, 0)) { 2672 ifp->if_ierrors++; 2673 goto next; 2674 } 2675 2676 hdr = mtod(m, struct bwi_rxbuf_hdr *); 2677 flags2 = le16toh(hdr->rxh_flags2); 2678 2679 hdr_extra = 0; 2680 if (flags2 & BWI_RXH_F2_TYPE2FRAME) 2681 hdr_extra = 2; 2682 wh_ofs = hdr_extra + 6; /* XXX magic number */ 2683 2684 buflen = le16toh(hdr->rxh_buflen); 2685 if (buflen < BWI_FRAME_MIN_LEN(wh_ofs)) { 2686 if_printf(ifp, "%s: zero length data, hdr_extra %d\n", 2687 __func__, hdr_extra); 2688 ifp->if_ierrors++; 2689 m_freem(m); 2690 goto next; 2691 } 2692 2693 plcp = ((const uint8_t *)(hdr + 1) + hdr_extra); 2694 rssi = bwi_calc_rssi(sc, hdr); 2695 noise = bwi_calc_noise(sc); 2696 2697 m->m_pkthdr.rcvif = ifp; 2698 m->m_len = m->m_pkthdr.len = buflen + sizeof(*hdr); 2699 m_adj(m, sizeof(*hdr) + wh_ofs); 2700 2701 if (htole16(hdr->rxh_flags1) & BWI_RXH_F1_OFDM) 2702 rate = bwi_ofdm_plcp2rate(plcp); 2703 else 2704 rate = bwi_ds_plcp2rate(plcp); 2705 2706 /* RX radio tap */ 2707 if (ieee80211_radiotap_active(ic)) 2708 bwi_rx_radiotap(sc, m, hdr, plcp, rate, rssi, noise); 2709 2710 m_adj(m, -IEEE80211_CRC_LEN); 2711 2712 BWI_UNLOCK(sc); 2713 2714 wh = mtod(m, struct ieee80211_frame_min *); 2715 ni = ieee80211_find_rxnode(ic, wh); 2716 if (ni != NULL) { 2717 type = ieee80211_input(ni, m, rssi - noise, noise); 2718 ieee80211_free_node(ni); 2719 } else 2720 type = ieee80211_input_all(ic, m, rssi - noise, noise); 2721 if (type == IEEE80211_FC0_TYPE_DATA) { 2722 rx_data = 1; 2723 sc->sc_rx_rate = rate; 2724 } 2725 2726 BWI_LOCK(sc); 2727 next: 2728 idx = (idx + 1) % BWI_RX_NDESC; 2729 2730 if (sc->sc_flags & BWI_F_STOP) { 2731 /* 2732 * Take the fast lane, don't do 2733 * any damage to softc 2734 */ 2735 return -1; 2736 } 2737 } 2738 2739 rbd->rbd_idx = idx; 2740 bus_dmamap_sync(sc->sc_rxring_dtag, rd->rdata_dmap, 2741 BUS_DMASYNC_PREWRITE); 2742 2743 return rx_data; 2744 } 2745 2746 static int 2747 bwi_rxeof32(struct bwi_softc *sc) 2748 { 2749 uint32_t val, rx_ctrl; 2750 int end_idx, rx_data; 2751 2752 rx_ctrl = sc->sc_rx_rdata.rdata_txrx_ctrl; 2753 2754 val = CSR_READ_4(sc, rx_ctrl + BWI_RX32_STATUS); 2755 end_idx = __SHIFTOUT(val, BWI_RX32_STATUS_INDEX_MASK) / 2756 sizeof(struct bwi_desc32); 2757 2758 rx_data = bwi_rxeof(sc, end_idx); 2759 if (rx_data >= 0) { 2760 CSR_WRITE_4(sc, rx_ctrl + BWI_RX32_INDEX, 2761 end_idx * sizeof(struct bwi_desc32)); 2762 } 2763 return rx_data; 2764 } 2765 2766 static int 2767 bwi_rxeof64(struct bwi_softc *sc) 2768 { 2769 /* TODO:64 */ 2770 return 0; 2771 } 2772 2773 static void 2774 bwi_reset_rx_ring32(struct bwi_softc *sc, uint32_t rx_ctrl) 2775 { 2776 int i; 2777 2778 CSR_WRITE_4(sc, rx_ctrl + BWI_RX32_CTRL, 0); 2779 2780 #define NRETRY 10 2781 2782 for (i = 0; i < NRETRY; ++i) { 2783 uint32_t status; 2784 2785 status = CSR_READ_4(sc, rx_ctrl + BWI_RX32_STATUS); 2786 if (__SHIFTOUT(status, BWI_RX32_STATUS_STATE_MASK) == 2787 BWI_RX32_STATUS_STATE_DISABLED) 2788 break; 2789 2790 DELAY(1000); 2791 } 2792 if (i == NRETRY) 2793 device_printf(sc->sc_dev, "reset rx ring timedout\n"); 2794 2795 #undef NRETRY 2796 2797 CSR_WRITE_4(sc, rx_ctrl + BWI_RX32_RINGINFO, 0); 2798 } 2799 2800 static void 2801 bwi_free_txstats32(struct bwi_softc *sc) 2802 { 2803 bwi_reset_rx_ring32(sc, sc->sc_txstats->stats_ctrl_base); 2804 } 2805 2806 static void 2807 bwi_free_rx_ring32(struct bwi_softc *sc) 2808 { 2809 struct bwi_ring_data *rd = &sc->sc_rx_rdata; 2810 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata; 2811 int i; 2812 2813 bwi_reset_rx_ring32(sc, rd->rdata_txrx_ctrl); 2814 2815 for (i = 0; i < BWI_RX_NDESC; ++i) { 2816 struct bwi_rxbuf *rb = &rbd->rbd_buf[i]; 2817 2818 if (rb->rb_mbuf != NULL) { 2819 bus_dmamap_unload(sc->sc_buf_dtag, rb->rb_dmap); 2820 m_freem(rb->rb_mbuf); 2821 rb->rb_mbuf = NULL; 2822 } 2823 } 2824 } 2825 2826 static void 2827 bwi_free_tx_ring32(struct bwi_softc *sc, int ring_idx) 2828 { 2829 struct bwi_ring_data *rd; 2830 struct bwi_txbuf_data *tbd; 2831 struct ifnet *ifp = sc->sc_ifp; 2832 uint32_t state, val; 2833 int i; 2834 2835 KASSERT(ring_idx < BWI_TX_NRING, ("ring_idx %d", ring_idx)); 2836 rd = &sc->sc_tx_rdata[ring_idx]; 2837 tbd = &sc->sc_tx_bdata[ring_idx]; 2838 2839 #define NRETRY 10 2840 2841 for (i = 0; i < NRETRY; ++i) { 2842 val = CSR_READ_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_STATUS); 2843 state = __SHIFTOUT(val, BWI_TX32_STATUS_STATE_MASK); 2844 if (state == BWI_TX32_STATUS_STATE_DISABLED || 2845 state == BWI_TX32_STATUS_STATE_IDLE || 2846 state == BWI_TX32_STATUS_STATE_STOPPED) 2847 break; 2848 2849 DELAY(1000); 2850 } 2851 if (i == NRETRY) { 2852 if_printf(ifp, "%s: wait for TX ring(%d) stable timed out\n", 2853 __func__, ring_idx); 2854 } 2855 2856 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_CTRL, 0); 2857 for (i = 0; i < NRETRY; ++i) { 2858 val = CSR_READ_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_STATUS); 2859 state = __SHIFTOUT(val, BWI_TX32_STATUS_STATE_MASK); 2860 if (state == BWI_TX32_STATUS_STATE_DISABLED) 2861 break; 2862 2863 DELAY(1000); 2864 } 2865 if (i == NRETRY) 2866 if_printf(ifp, "%s: reset TX ring (%d) timed out\n", 2867 __func__, ring_idx); 2868 2869 #undef NRETRY 2870 2871 DELAY(1000); 2872 2873 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_RINGINFO, 0); 2874 2875 for (i = 0; i < BWI_TX_NDESC; ++i) { 2876 struct bwi_txbuf *tb = &tbd->tbd_buf[i]; 2877 2878 if (tb->tb_mbuf != NULL) { 2879 bus_dmamap_unload(sc->sc_buf_dtag, tb->tb_dmap); 2880 m_freem(tb->tb_mbuf); 2881 tb->tb_mbuf = NULL; 2882 } 2883 if (tb->tb_ni != NULL) { 2884 ieee80211_free_node(tb->tb_ni); 2885 tb->tb_ni = NULL; 2886 } 2887 } 2888 } 2889 2890 static void 2891 bwi_free_txstats64(struct bwi_softc *sc) 2892 { 2893 /* TODO:64 */ 2894 } 2895 2896 static void 2897 bwi_free_rx_ring64(struct bwi_softc *sc) 2898 { 2899 /* TODO:64 */ 2900 } 2901 2902 static void 2903 bwi_free_tx_ring64(struct bwi_softc *sc, int ring_idx) 2904 { 2905 /* TODO:64 */ 2906 } 2907 2908 /* XXX does not belong here */ 2909 #define IEEE80211_OFDM_PLCP_RATE_MASK __BITS(3, 0) 2910 #define IEEE80211_OFDM_PLCP_LEN_MASK __BITS(16, 5) 2911 2912 static __inline void 2913 bwi_ofdm_plcp_header(uint32_t *plcp0, int pkt_len, uint8_t rate) 2914 { 2915 uint32_t plcp; 2916 2917 plcp = __SHIFTIN(ieee80211_rate2plcp(rate, IEEE80211_T_OFDM), 2918 IEEE80211_OFDM_PLCP_RATE_MASK) | 2919 __SHIFTIN(pkt_len, IEEE80211_OFDM_PLCP_LEN_MASK); 2920 *plcp0 = htole32(plcp); 2921 } 2922 2923 static __inline void 2924 bwi_ds_plcp_header(struct ieee80211_ds_plcp_hdr *plcp, int pkt_len, 2925 uint8_t rate) 2926 { 2927 int len, service, pkt_bitlen; 2928 2929 pkt_bitlen = pkt_len * NBBY; 2930 len = howmany(pkt_bitlen * 2, rate); 2931 2932 service = IEEE80211_PLCP_SERVICE_LOCKED; 2933 if (rate == (11 * 2)) { 2934 int pkt_bitlen1; 2935 2936 /* 2937 * PLCP service field needs to be adjusted, 2938 * if TX rate is 11Mbytes/s 2939 */ 2940 pkt_bitlen1 = len * 11; 2941 if (pkt_bitlen1 - pkt_bitlen >= NBBY) 2942 service |= IEEE80211_PLCP_SERVICE_LENEXT7; 2943 } 2944 2945 plcp->i_signal = ieee80211_rate2plcp(rate, IEEE80211_T_CCK); 2946 plcp->i_service = service; 2947 plcp->i_length = htole16(len); 2948 /* NOTE: do NOT touch i_crc */ 2949 } 2950 2951 static __inline void 2952 bwi_plcp_header(const struct ieee80211_rate_table *rt, 2953 void *plcp, int pkt_len, uint8_t rate) 2954 { 2955 enum ieee80211_phytype modtype; 2956 2957 /* 2958 * Assume caller has zeroed 'plcp' 2959 */ 2960 modtype = ieee80211_rate2phytype(rt, rate); 2961 if (modtype == IEEE80211_T_OFDM) 2962 bwi_ofdm_plcp_header(plcp, pkt_len, rate); 2963 else if (modtype == IEEE80211_T_DS) 2964 bwi_ds_plcp_header(plcp, pkt_len, rate); 2965 else 2966 panic("unsupport modulation type %u\n", modtype); 2967 } 2968 2969 static int 2970 bwi_encap(struct bwi_softc *sc, int idx, struct mbuf *m, 2971 struct ieee80211_node *ni) 2972 { 2973 struct ieee80211vap *vap = ni->ni_vap; 2974 struct ifnet *ifp = sc->sc_ifp; 2975 struct ieee80211com *ic = ifp->if_l2com; 2976 struct bwi_ring_data *rd = &sc->sc_tx_rdata[BWI_TX_DATA_RING]; 2977 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING]; 2978 struct bwi_txbuf *tb = &tbd->tbd_buf[idx]; 2979 struct bwi_mac *mac; 2980 struct bwi_txbuf_hdr *hdr; 2981 struct ieee80211_frame *wh; 2982 const struct ieee80211_txparam *tp; 2983 uint8_t rate, rate_fb; 2984 uint32_t mac_ctrl; 2985 uint16_t phy_ctrl; 2986 bus_addr_t paddr; 2987 int type, ismcast, pkt_len, error, rix; 2988 #if 0 2989 const uint8_t *p; 2990 int i; 2991 #endif 2992 2993 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 2994 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 2995 mac = (struct bwi_mac *)sc->sc_cur_regwin; 2996 2997 wh = mtod(m, struct ieee80211_frame *); 2998 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK; 2999 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 3000 3001 /* Get 802.11 frame len before prepending TX header */ 3002 pkt_len = m->m_pkthdr.len + IEEE80211_CRC_LEN; 3003 3004 /* 3005 * Find TX rate 3006 */ 3007 tp = &vap->iv_txparms[ieee80211_chan2mode(ic->ic_curchan)]; 3008 if (type != IEEE80211_FC0_TYPE_DATA || (m->m_flags & M_EAPOL)) { 3009 rate = rate_fb = tp->mgmtrate; 3010 } else if (ismcast) { 3011 rate = rate_fb = tp->mcastrate; 3012 } else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) { 3013 rate = rate_fb = tp->ucastrate; 3014 } else { 3015 rix = ieee80211_amrr_choose(ni, &BWI_NODE(ni)->amn); 3016 rate = ni->ni_txrate; 3017 3018 if (rix > 0) { 3019 rate_fb = ni->ni_rates.rs_rates[rix-1] & 3020 IEEE80211_RATE_VAL; 3021 } else { 3022 rate_fb = rate; 3023 } 3024 } 3025 tb->tb_rate[0] = rate; 3026 tb->tb_rate[1] = rate_fb; 3027 sc->sc_tx_rate = rate; 3028 3029 /* 3030 * TX radio tap 3031 */ 3032 if (ieee80211_radiotap_active_vap(vap)) { 3033 sc->sc_tx_th.wt_flags = 0; 3034 if (wh->i_fc[1] & IEEE80211_FC1_WEP) 3035 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP; 3036 if (ieee80211_rate2phytype(sc->sc_rates, rate) == IEEE80211_T_DS && 3037 (ic->ic_flags & IEEE80211_F_SHPREAMBLE) && 3038 rate != (1 * 2)) { 3039 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 3040 } 3041 sc->sc_tx_th.wt_rate = rate; 3042 3043 ieee80211_radiotap_tx(vap, m); 3044 } 3045 3046 /* 3047 * Setup the embedded TX header 3048 */ 3049 M_PREPEND(m, sizeof(*hdr), M_DONTWAIT); 3050 if (m == NULL) { 3051 if_printf(ifp, "%s: prepend TX header failed\n", __func__); 3052 return ENOBUFS; 3053 } 3054 hdr = mtod(m, struct bwi_txbuf_hdr *); 3055 3056 bzero(hdr, sizeof(*hdr)); 3057 3058 bcopy(wh->i_fc, hdr->txh_fc, sizeof(hdr->txh_fc)); 3059 bcopy(wh->i_addr1, hdr->txh_addr1, sizeof(hdr->txh_addr1)); 3060 3061 if (!ismcast) { 3062 uint16_t dur; 3063 3064 dur = ieee80211_ack_duration(sc->sc_rates, rate, 3065 ic->ic_flags & ~IEEE80211_F_SHPREAMBLE); 3066 3067 hdr->txh_fb_duration = htole16(dur); 3068 } 3069 3070 hdr->txh_id = __SHIFTIN(BWI_TX_DATA_RING, BWI_TXH_ID_RING_MASK) | 3071 __SHIFTIN(idx, BWI_TXH_ID_IDX_MASK); 3072 3073 bwi_plcp_header(sc->sc_rates, hdr->txh_plcp, pkt_len, rate); 3074 bwi_plcp_header(sc->sc_rates, hdr->txh_fb_plcp, pkt_len, rate_fb); 3075 3076 phy_ctrl = __SHIFTIN(mac->mac_rf.rf_ant_mode, 3077 BWI_TXH_PHY_C_ANTMODE_MASK); 3078 if (ieee80211_rate2phytype(sc->sc_rates, rate) == IEEE80211_T_OFDM) 3079 phy_ctrl |= BWI_TXH_PHY_C_OFDM; 3080 else if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && rate != (2 * 1)) 3081 phy_ctrl |= BWI_TXH_PHY_C_SHPREAMBLE; 3082 3083 mac_ctrl = BWI_TXH_MAC_C_HWSEQ | BWI_TXH_MAC_C_FIRST_FRAG; 3084 if (!ismcast) 3085 mac_ctrl |= BWI_TXH_MAC_C_ACK; 3086 if (ieee80211_rate2phytype(sc->sc_rates, rate_fb) == IEEE80211_T_OFDM) 3087 mac_ctrl |= BWI_TXH_MAC_C_FB_OFDM; 3088 3089 hdr->txh_mac_ctrl = htole32(mac_ctrl); 3090 hdr->txh_phy_ctrl = htole16(phy_ctrl); 3091 3092 /* Catch any further usage */ 3093 hdr = NULL; 3094 wh = NULL; 3095 3096 /* DMA load */ 3097 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m, 3098 bwi_dma_buf_addr, &paddr, BUS_DMA_NOWAIT); 3099 if (error && error != EFBIG) { 3100 if_printf(ifp, "%s: can't load TX buffer (1) %d\n", 3101 __func__, error); 3102 goto back; 3103 } 3104 3105 if (error) { /* error == EFBIG */ 3106 struct mbuf *m_new; 3107 3108 m_new = m_defrag(m, M_DONTWAIT); 3109 if (m_new == NULL) { 3110 if_printf(ifp, "%s: can't defrag TX buffer\n", 3111 __func__); 3112 error = ENOBUFS; 3113 goto back; 3114 } else { 3115 m = m_new; 3116 } 3117 3118 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m, 3119 bwi_dma_buf_addr, &paddr, 3120 BUS_DMA_NOWAIT); 3121 if (error) { 3122 if_printf(ifp, "%s: can't load TX buffer (2) %d\n", 3123 __func__, error); 3124 goto back; 3125 } 3126 } 3127 error = 0; 3128 3129 bus_dmamap_sync(sc->sc_buf_dtag, tb->tb_dmap, BUS_DMASYNC_PREWRITE); 3130 3131 tb->tb_mbuf = m; 3132 tb->tb_ni = ni; 3133 3134 #if 0 3135 p = mtod(m, const uint8_t *); 3136 for (i = 0; i < m->m_pkthdr.len; ++i) { 3137 if (i != 0 && i % 8 == 0) 3138 printf("\n"); 3139 printf("%02x ", p[i]); 3140 } 3141 printf("\n"); 3142 #endif 3143 DPRINTF(sc, BWI_DBG_TX, "idx %d, pkt_len %d, buflen %d\n", 3144 idx, pkt_len, m->m_pkthdr.len); 3145 3146 /* Setup TX descriptor */ 3147 sc->sc_setup_txdesc(sc, rd, idx, paddr, m->m_pkthdr.len); 3148 bus_dmamap_sync(sc->sc_txring_dtag, rd->rdata_dmap, 3149 BUS_DMASYNC_PREWRITE); 3150 3151 /* Kick start */ 3152 sc->sc_start_tx(sc, rd->rdata_txrx_ctrl, idx); 3153 3154 back: 3155 if (error) 3156 m_freem(m); 3157 return error; 3158 } 3159 3160 static int 3161 bwi_encap_raw(struct bwi_softc *sc, int idx, struct mbuf *m, 3162 struct ieee80211_node *ni, const struct ieee80211_bpf_params *params) 3163 { 3164 struct ifnet *ifp = sc->sc_ifp; 3165 struct ieee80211vap *vap = ni->ni_vap; 3166 struct ieee80211com *ic = ni->ni_ic; 3167 struct bwi_ring_data *rd = &sc->sc_tx_rdata[BWI_TX_DATA_RING]; 3168 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING]; 3169 struct bwi_txbuf *tb = &tbd->tbd_buf[idx]; 3170 struct bwi_mac *mac; 3171 struct bwi_txbuf_hdr *hdr; 3172 struct ieee80211_frame *wh; 3173 uint8_t rate, rate_fb; 3174 uint32_t mac_ctrl; 3175 uint16_t phy_ctrl; 3176 bus_addr_t paddr; 3177 int ismcast, pkt_len, error; 3178 3179 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 3180 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 3181 mac = (struct bwi_mac *)sc->sc_cur_regwin; 3182 3183 wh = mtod(m, struct ieee80211_frame *); 3184 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1); 3185 3186 /* Get 802.11 frame len before prepending TX header */ 3187 pkt_len = m->m_pkthdr.len + IEEE80211_CRC_LEN; 3188 3189 /* 3190 * Find TX rate 3191 */ 3192 rate = params->ibp_rate0; 3193 if (!ieee80211_isratevalid(ic->ic_rt, rate)) { 3194 /* XXX fall back to mcast/mgmt rate? */ 3195 m_freem(m); 3196 return EINVAL; 3197 } 3198 if (params->ibp_try1 != 0) { 3199 rate_fb = params->ibp_rate1; 3200 if (!ieee80211_isratevalid(ic->ic_rt, rate_fb)) { 3201 /* XXX fall back to rate0? */ 3202 m_freem(m); 3203 return EINVAL; 3204 } 3205 } else 3206 rate_fb = rate; 3207 tb->tb_rate[0] = rate; 3208 tb->tb_rate[1] = rate_fb; 3209 sc->sc_tx_rate = rate; 3210 3211 /* 3212 * TX radio tap 3213 */ 3214 if (ieee80211_radiotap_active_vap(vap)) { 3215 sc->sc_tx_th.wt_flags = 0; 3216 /* XXX IEEE80211_BPF_CRYPTO */ 3217 if (wh->i_fc[1] & IEEE80211_FC1_WEP) 3218 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP; 3219 if (params->ibp_flags & IEEE80211_BPF_SHORTPRE) 3220 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 3221 sc->sc_tx_th.wt_rate = rate; 3222 3223 ieee80211_radiotap_tx(vap, m); 3224 } 3225 3226 /* 3227 * Setup the embedded TX header 3228 */ 3229 M_PREPEND(m, sizeof(*hdr), M_DONTWAIT); 3230 if (m == NULL) { 3231 if_printf(ifp, "%s: prepend TX header failed\n", __func__); 3232 return ENOBUFS; 3233 } 3234 hdr = mtod(m, struct bwi_txbuf_hdr *); 3235 3236 bzero(hdr, sizeof(*hdr)); 3237 3238 bcopy(wh->i_fc, hdr->txh_fc, sizeof(hdr->txh_fc)); 3239 bcopy(wh->i_addr1, hdr->txh_addr1, sizeof(hdr->txh_addr1)); 3240 3241 mac_ctrl = BWI_TXH_MAC_C_HWSEQ | BWI_TXH_MAC_C_FIRST_FRAG; 3242 if (!ismcast && (params->ibp_flags & IEEE80211_BPF_NOACK) == 0) { 3243 uint16_t dur; 3244 3245 dur = ieee80211_ack_duration(sc->sc_rates, rate_fb, 0); 3246 3247 hdr->txh_fb_duration = htole16(dur); 3248 mac_ctrl |= BWI_TXH_MAC_C_ACK; 3249 } 3250 3251 hdr->txh_id = __SHIFTIN(BWI_TX_DATA_RING, BWI_TXH_ID_RING_MASK) | 3252 __SHIFTIN(idx, BWI_TXH_ID_IDX_MASK); 3253 3254 bwi_plcp_header(sc->sc_rates, hdr->txh_plcp, pkt_len, rate); 3255 bwi_plcp_header(sc->sc_rates, hdr->txh_fb_plcp, pkt_len, rate_fb); 3256 3257 phy_ctrl = __SHIFTIN(mac->mac_rf.rf_ant_mode, 3258 BWI_TXH_PHY_C_ANTMODE_MASK); 3259 if (ieee80211_rate2phytype(sc->sc_rates, rate) == IEEE80211_T_OFDM) { 3260 phy_ctrl |= BWI_TXH_PHY_C_OFDM; 3261 mac_ctrl |= BWI_TXH_MAC_C_FB_OFDM; 3262 } else if (params->ibp_flags & IEEE80211_BPF_SHORTPRE) 3263 phy_ctrl |= BWI_TXH_PHY_C_SHPREAMBLE; 3264 3265 hdr->txh_mac_ctrl = htole32(mac_ctrl); 3266 hdr->txh_phy_ctrl = htole16(phy_ctrl); 3267 3268 /* Catch any further usage */ 3269 hdr = NULL; 3270 wh = NULL; 3271 3272 /* DMA load */ 3273 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m, 3274 bwi_dma_buf_addr, &paddr, BUS_DMA_NOWAIT); 3275 if (error != 0) { 3276 struct mbuf *m_new; 3277 3278 if (error != EFBIG) { 3279 if_printf(ifp, "%s: can't load TX buffer (1) %d\n", 3280 __func__, error); 3281 goto back; 3282 } 3283 m_new = m_defrag(m, M_DONTWAIT); 3284 if (m_new == NULL) { 3285 if_printf(ifp, "%s: can't defrag TX buffer\n", 3286 __func__); 3287 error = ENOBUFS; 3288 goto back; 3289 } 3290 m = m_new; 3291 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m, 3292 bwi_dma_buf_addr, &paddr, 3293 BUS_DMA_NOWAIT); 3294 if (error) { 3295 if_printf(ifp, "%s: can't load TX buffer (2) %d\n", 3296 __func__, error); 3297 goto back; 3298 } 3299 } 3300 3301 bus_dmamap_sync(sc->sc_buf_dtag, tb->tb_dmap, BUS_DMASYNC_PREWRITE); 3302 3303 tb->tb_mbuf = m; 3304 tb->tb_ni = ni; 3305 3306 DPRINTF(sc, BWI_DBG_TX, "idx %d, pkt_len %d, buflen %d\n", 3307 idx, pkt_len, m->m_pkthdr.len); 3308 3309 /* Setup TX descriptor */ 3310 sc->sc_setup_txdesc(sc, rd, idx, paddr, m->m_pkthdr.len); 3311 bus_dmamap_sync(sc->sc_txring_dtag, rd->rdata_dmap, 3312 BUS_DMASYNC_PREWRITE); 3313 3314 /* Kick start */ 3315 sc->sc_start_tx(sc, rd->rdata_txrx_ctrl, idx); 3316 back: 3317 if (error) 3318 m_freem(m); 3319 return error; 3320 } 3321 3322 static void 3323 bwi_start_tx32(struct bwi_softc *sc, uint32_t tx_ctrl, int idx) 3324 { 3325 idx = (idx + 1) % BWI_TX_NDESC; 3326 CSR_WRITE_4(sc, tx_ctrl + BWI_TX32_INDEX, 3327 idx * sizeof(struct bwi_desc32)); 3328 } 3329 3330 static void 3331 bwi_start_tx64(struct bwi_softc *sc, uint32_t tx_ctrl, int idx) 3332 { 3333 /* TODO:64 */ 3334 } 3335 3336 static void 3337 bwi_txeof_status32(struct bwi_softc *sc) 3338 { 3339 struct ifnet *ifp = sc->sc_ifp; 3340 uint32_t val, ctrl_base; 3341 int end_idx; 3342 3343 ctrl_base = sc->sc_txstats->stats_ctrl_base; 3344 3345 val = CSR_READ_4(sc, ctrl_base + BWI_RX32_STATUS); 3346 end_idx = __SHIFTOUT(val, BWI_RX32_STATUS_INDEX_MASK) / 3347 sizeof(struct bwi_desc32); 3348 3349 bwi_txeof_status(sc, end_idx); 3350 3351 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_INDEX, 3352 end_idx * sizeof(struct bwi_desc32)); 3353 3354 if ((ifp->if_drv_flags & IFF_DRV_OACTIVE) == 0) 3355 ifp->if_start(ifp); 3356 } 3357 3358 static void 3359 bwi_txeof_status64(struct bwi_softc *sc) 3360 { 3361 /* TODO:64 */ 3362 } 3363 3364 static void 3365 _bwi_txeof(struct bwi_softc *sc, uint16_t tx_id, int acked, int data_txcnt) 3366 { 3367 struct ifnet *ifp = sc->sc_ifp; 3368 struct bwi_txbuf_data *tbd; 3369 struct bwi_txbuf *tb; 3370 int ring_idx, buf_idx; 3371 struct ieee80211_node *ni; 3372 3373 if (tx_id == 0) { 3374 if_printf(ifp, "%s: zero tx id\n", __func__); 3375 return; 3376 } 3377 3378 ring_idx = __SHIFTOUT(tx_id, BWI_TXH_ID_RING_MASK); 3379 buf_idx = __SHIFTOUT(tx_id, BWI_TXH_ID_IDX_MASK); 3380 3381 KASSERT(ring_idx == BWI_TX_DATA_RING, ("ring_idx %d", ring_idx)); 3382 KASSERT(buf_idx < BWI_TX_NDESC, ("buf_idx %d", buf_idx)); 3383 3384 tbd = &sc->sc_tx_bdata[ring_idx]; 3385 KASSERT(tbd->tbd_used > 0, ("tbd_used %d", tbd->tbd_used)); 3386 tbd->tbd_used--; 3387 3388 tb = &tbd->tbd_buf[buf_idx]; 3389 DPRINTF(sc, BWI_DBG_TXEOF, "txeof idx %d, " 3390 "acked %d, data_txcnt %d, ni %p\n", 3391 buf_idx, acked, data_txcnt, tb->tb_ni); 3392 3393 bus_dmamap_unload(sc->sc_buf_dtag, tb->tb_dmap); 3394 3395 ni = tb->tb_ni; 3396 if (tb->tb_ni != NULL) { 3397 struct bwi_node *bn = (struct bwi_node *) tb->tb_ni; 3398 const struct bwi_txbuf_hdr *hdr = 3399 mtod(tb->tb_mbuf, const struct bwi_txbuf_hdr *); 3400 3401 /* NB: update rate control only for unicast frames */ 3402 if (hdr->txh_mac_ctrl & htole32(BWI_TXH_MAC_C_ACK)) { 3403 /* 3404 * Feed back 'acked and data_txcnt'. Note that the 3405 * generic AMRR code only understands one tx rate 3406 * and the estimator doesn't handle real retry counts 3407 * well so to avoid over-aggressive downshifting we 3408 * treat any number of retries as "1". 3409 */ 3410 ieee80211_amrr_tx_complete(&bn->amn, acked, 3411 data_txcnt > 1); 3412 } 3413 3414 /* 3415 * Do any tx complete callback. Note this must 3416 * be done before releasing the node reference. 3417 */ 3418 if (tb->tb_mbuf->m_flags & M_TXCB) 3419 ieee80211_process_callback(ni, tb->tb_mbuf, !acked); 3420 3421 ieee80211_free_node(tb->tb_ni); 3422 tb->tb_ni = NULL; 3423 } 3424 m_freem(tb->tb_mbuf); 3425 tb->tb_mbuf = NULL; 3426 3427 if (tbd->tbd_used == 0) 3428 sc->sc_tx_timer = 0; 3429 3430 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3431 } 3432 3433 static void 3434 bwi_txeof_status(struct bwi_softc *sc, int end_idx) 3435 { 3436 struct bwi_txstats_data *st = sc->sc_txstats; 3437 int idx; 3438 3439 bus_dmamap_sync(st->stats_dtag, st->stats_dmap, BUS_DMASYNC_POSTREAD); 3440 3441 idx = st->stats_idx; 3442 while (idx != end_idx) { 3443 const struct bwi_txstats *stats = &st->stats[idx]; 3444 3445 if ((stats->txs_flags & BWI_TXS_F_PENDING) == 0) { 3446 int data_txcnt; 3447 3448 data_txcnt = __SHIFTOUT(stats->txs_txcnt, 3449 BWI_TXS_TXCNT_DATA); 3450 _bwi_txeof(sc, le16toh(stats->txs_id), 3451 stats->txs_flags & BWI_TXS_F_ACKED, 3452 data_txcnt); 3453 } 3454 idx = (idx + 1) % BWI_TXSTATS_NDESC; 3455 } 3456 st->stats_idx = idx; 3457 } 3458 3459 static void 3460 bwi_txeof(struct bwi_softc *sc) 3461 { 3462 struct ifnet *ifp = sc->sc_ifp; 3463 3464 for (;;) { 3465 uint32_t tx_status0, tx_status1; 3466 uint16_t tx_id; 3467 int data_txcnt; 3468 3469 tx_status0 = CSR_READ_4(sc, BWI_TXSTATUS0); 3470 if ((tx_status0 & BWI_TXSTATUS0_VALID) == 0) 3471 break; 3472 tx_status1 = CSR_READ_4(sc, BWI_TXSTATUS1); 3473 3474 tx_id = __SHIFTOUT(tx_status0, BWI_TXSTATUS0_TXID_MASK); 3475 data_txcnt = __SHIFTOUT(tx_status0, 3476 BWI_TXSTATUS0_DATA_TXCNT_MASK); 3477 3478 if (tx_status0 & (BWI_TXSTATUS0_AMPDU | BWI_TXSTATUS0_PENDING)) 3479 continue; 3480 3481 _bwi_txeof(sc, le16toh(tx_id), tx_status0 & BWI_TXSTATUS0_ACKED, 3482 data_txcnt); 3483 } 3484 3485 if ((ifp->if_drv_flags & IFF_DRV_OACTIVE) == 0) 3486 ifp->if_start(ifp); 3487 } 3488 3489 static int 3490 bwi_bbp_power_on(struct bwi_softc *sc, enum bwi_clock_mode clk_mode) 3491 { 3492 bwi_power_on(sc, 1); 3493 return bwi_set_clock_mode(sc, clk_mode); 3494 } 3495 3496 static void 3497 bwi_bbp_power_off(struct bwi_softc *sc) 3498 { 3499 bwi_set_clock_mode(sc, BWI_CLOCK_MODE_SLOW); 3500 bwi_power_off(sc, 1); 3501 } 3502 3503 static int 3504 bwi_get_pwron_delay(struct bwi_softc *sc) 3505 { 3506 struct bwi_regwin *com, *old; 3507 struct bwi_clock_freq freq; 3508 uint32_t val; 3509 int error; 3510 3511 com = &sc->sc_com_regwin; 3512 KASSERT(BWI_REGWIN_EXIST(com), ("no regwin")); 3513 3514 if ((sc->sc_cap & BWI_CAP_CLKMODE) == 0) 3515 return 0; 3516 3517 error = bwi_regwin_switch(sc, com, &old); 3518 if (error) 3519 return error; 3520 3521 bwi_get_clock_freq(sc, &freq); 3522 3523 val = CSR_READ_4(sc, BWI_PLL_ON_DELAY); 3524 sc->sc_pwron_delay = howmany((val + 2) * 1000000, freq.clkfreq_min); 3525 DPRINTF(sc, BWI_DBG_ATTACH, "power on delay %u\n", sc->sc_pwron_delay); 3526 3527 return bwi_regwin_switch(sc, old, NULL); 3528 } 3529 3530 static int 3531 bwi_bus_attach(struct bwi_softc *sc) 3532 { 3533 struct bwi_regwin *bus, *old; 3534 int error; 3535 3536 bus = &sc->sc_bus_regwin; 3537 3538 error = bwi_regwin_switch(sc, bus, &old); 3539 if (error) 3540 return error; 3541 3542 if (!bwi_regwin_is_enabled(sc, bus)) 3543 bwi_regwin_enable(sc, bus, 0); 3544 3545 /* Disable interripts */ 3546 CSR_WRITE_4(sc, BWI_INTRVEC, 0); 3547 3548 return bwi_regwin_switch(sc, old, NULL); 3549 } 3550 3551 static const char * 3552 bwi_regwin_name(const struct bwi_regwin *rw) 3553 { 3554 switch (rw->rw_type) { 3555 case BWI_REGWIN_T_COM: 3556 return "COM"; 3557 case BWI_REGWIN_T_BUSPCI: 3558 return "PCI"; 3559 case BWI_REGWIN_T_MAC: 3560 return "MAC"; 3561 case BWI_REGWIN_T_BUSPCIE: 3562 return "PCIE"; 3563 } 3564 panic("unknown regwin type 0x%04x\n", rw->rw_type); 3565 return NULL; 3566 } 3567 3568 static uint32_t 3569 bwi_regwin_disable_bits(struct bwi_softc *sc) 3570 { 3571 uint32_t busrev; 3572 3573 /* XXX cache this */ 3574 busrev = __SHIFTOUT(CSR_READ_4(sc, BWI_ID_LO), BWI_ID_LO_BUSREV_MASK); 3575 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT | BWI_DBG_MISC, 3576 "bus rev %u\n", busrev); 3577 3578 if (busrev == BWI_BUSREV_0) 3579 return BWI_STATE_LO_DISABLE1; 3580 else if (busrev == BWI_BUSREV_1) 3581 return BWI_STATE_LO_DISABLE2; 3582 else 3583 return (BWI_STATE_LO_DISABLE1 | BWI_STATE_LO_DISABLE2); 3584 } 3585 3586 int 3587 bwi_regwin_is_enabled(struct bwi_softc *sc, struct bwi_regwin *rw) 3588 { 3589 uint32_t val, disable_bits; 3590 3591 disable_bits = bwi_regwin_disable_bits(sc); 3592 val = CSR_READ_4(sc, BWI_STATE_LO); 3593 3594 if ((val & (BWI_STATE_LO_CLOCK | 3595 BWI_STATE_LO_RESET | 3596 disable_bits)) == BWI_STATE_LO_CLOCK) { 3597 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT, "%s is enabled\n", 3598 bwi_regwin_name(rw)); 3599 return 1; 3600 } else { 3601 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT, "%s is disabled\n", 3602 bwi_regwin_name(rw)); 3603 return 0; 3604 } 3605 } 3606 3607 void 3608 bwi_regwin_disable(struct bwi_softc *sc, struct bwi_regwin *rw, uint32_t flags) 3609 { 3610 uint32_t state_lo, disable_bits; 3611 int i; 3612 3613 state_lo = CSR_READ_4(sc, BWI_STATE_LO); 3614 3615 /* 3616 * If current regwin is in 'reset' state, it was already disabled. 3617 */ 3618 if (state_lo & BWI_STATE_LO_RESET) { 3619 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT, 3620 "%s was already disabled\n", bwi_regwin_name(rw)); 3621 return; 3622 } 3623 3624 disable_bits = bwi_regwin_disable_bits(sc); 3625 3626 /* 3627 * Disable normal clock 3628 */ 3629 state_lo = BWI_STATE_LO_CLOCK | disable_bits; 3630 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo); 3631 3632 /* 3633 * Wait until normal clock is disabled 3634 */ 3635 #define NRETRY 1000 3636 for (i = 0; i < NRETRY; ++i) { 3637 state_lo = CSR_READ_4(sc, BWI_STATE_LO); 3638 if (state_lo & disable_bits) 3639 break; 3640 DELAY(10); 3641 } 3642 if (i == NRETRY) { 3643 device_printf(sc->sc_dev, "%s disable clock timeout\n", 3644 bwi_regwin_name(rw)); 3645 } 3646 3647 for (i = 0; i < NRETRY; ++i) { 3648 uint32_t state_hi; 3649 3650 state_hi = CSR_READ_4(sc, BWI_STATE_HI); 3651 if ((state_hi & BWI_STATE_HI_BUSY) == 0) 3652 break; 3653 DELAY(10); 3654 } 3655 if (i == NRETRY) { 3656 device_printf(sc->sc_dev, "%s wait BUSY unset timeout\n", 3657 bwi_regwin_name(rw)); 3658 } 3659 #undef NRETRY 3660 3661 /* 3662 * Reset and disable regwin with gated clock 3663 */ 3664 state_lo = BWI_STATE_LO_RESET | disable_bits | 3665 BWI_STATE_LO_CLOCK | BWI_STATE_LO_GATED_CLOCK | 3666 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK); 3667 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo); 3668 3669 /* Flush pending bus write */ 3670 CSR_READ_4(sc, BWI_STATE_LO); 3671 DELAY(1); 3672 3673 /* Reset and disable regwin */ 3674 state_lo = BWI_STATE_LO_RESET | disable_bits | 3675 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK); 3676 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo); 3677 3678 /* Flush pending bus write */ 3679 CSR_READ_4(sc, BWI_STATE_LO); 3680 DELAY(1); 3681 } 3682 3683 void 3684 bwi_regwin_enable(struct bwi_softc *sc, struct bwi_regwin *rw, uint32_t flags) 3685 { 3686 uint32_t state_lo, state_hi, imstate; 3687 3688 bwi_regwin_disable(sc, rw, flags); 3689 3690 /* Reset regwin with gated clock */ 3691 state_lo = BWI_STATE_LO_RESET | 3692 BWI_STATE_LO_CLOCK | 3693 BWI_STATE_LO_GATED_CLOCK | 3694 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK); 3695 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo); 3696 3697 /* Flush pending bus write */ 3698 CSR_READ_4(sc, BWI_STATE_LO); 3699 DELAY(1); 3700 3701 state_hi = CSR_READ_4(sc, BWI_STATE_HI); 3702 if (state_hi & BWI_STATE_HI_SERROR) 3703 CSR_WRITE_4(sc, BWI_STATE_HI, 0); 3704 3705 imstate = CSR_READ_4(sc, BWI_IMSTATE); 3706 if (imstate & (BWI_IMSTATE_INBAND_ERR | BWI_IMSTATE_TIMEOUT)) { 3707 imstate &= ~(BWI_IMSTATE_INBAND_ERR | BWI_IMSTATE_TIMEOUT); 3708 CSR_WRITE_4(sc, BWI_IMSTATE, imstate); 3709 } 3710 3711 /* Enable regwin with gated clock */ 3712 state_lo = BWI_STATE_LO_CLOCK | 3713 BWI_STATE_LO_GATED_CLOCK | 3714 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK); 3715 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo); 3716 3717 /* Flush pending bus write */ 3718 CSR_READ_4(sc, BWI_STATE_LO); 3719 DELAY(1); 3720 3721 /* Enable regwin with normal clock */ 3722 state_lo = BWI_STATE_LO_CLOCK | 3723 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK); 3724 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo); 3725 3726 /* Flush pending bus write */ 3727 CSR_READ_4(sc, BWI_STATE_LO); 3728 DELAY(1); 3729 } 3730 3731 static void 3732 bwi_set_bssid(struct bwi_softc *sc, const uint8_t *bssid) 3733 { 3734 struct ifnet *ifp = sc->sc_ifp; 3735 struct bwi_mac *mac; 3736 struct bwi_myaddr_bssid buf; 3737 const uint8_t *p; 3738 uint32_t val; 3739 int n, i; 3740 3741 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 3742 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 3743 mac = (struct bwi_mac *)sc->sc_cur_regwin; 3744 3745 bwi_set_addr_filter(sc, BWI_ADDR_FILTER_BSSID, bssid); 3746 3747 bcopy(IF_LLADDR(ifp), buf.myaddr, sizeof(buf.myaddr)); 3748 bcopy(bssid, buf.bssid, sizeof(buf.bssid)); 3749 3750 n = sizeof(buf) / sizeof(val); 3751 p = (const uint8_t *)&buf; 3752 for (i = 0; i < n; ++i) { 3753 int j; 3754 3755 val = 0; 3756 for (j = 0; j < sizeof(val); ++j) 3757 val |= ((uint32_t)(*p++)) << (j * 8); 3758 3759 TMPLT_WRITE_4(mac, 0x20 + (i * sizeof(val)), val); 3760 } 3761 } 3762 3763 static void 3764 bwi_updateslot(struct ifnet *ifp) 3765 { 3766 struct bwi_softc *sc = ifp->if_softc; 3767 struct ieee80211com *ic = ifp->if_l2com; 3768 struct bwi_mac *mac; 3769 3770 BWI_LOCK(sc); 3771 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 3772 DPRINTF(sc, BWI_DBG_80211, "%s\n", __func__); 3773 3774 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 3775 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 3776 mac = (struct bwi_mac *)sc->sc_cur_regwin; 3777 3778 bwi_mac_updateslot(mac, (ic->ic_flags & IEEE80211_F_SHSLOT)); 3779 } 3780 BWI_UNLOCK(sc); 3781 } 3782 3783 static void 3784 bwi_calibrate(void *xsc) 3785 { 3786 struct bwi_softc *sc = xsc; 3787 #ifdef INVARIANTS 3788 struct ifnet *ifp = sc->sc_ifp; 3789 struct ieee80211com *ic = ifp->if_l2com; 3790 #endif 3791 struct bwi_mac *mac; 3792 3793 BWI_ASSERT_LOCKED(sc); 3794 3795 KASSERT(ic->ic_opmode != IEEE80211_M_MONITOR, 3796 ("opmode %d", ic->ic_opmode)); 3797 3798 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 3799 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 3800 mac = (struct bwi_mac *)sc->sc_cur_regwin; 3801 3802 bwi_mac_calibrate_txpower(mac, sc->sc_txpwrcb_type); 3803 sc->sc_txpwrcb_type = BWI_TXPWR_CALIB; 3804 3805 /* XXX 15 seconds */ 3806 callout_reset(&sc->sc_calib_ch, hz * 15, bwi_calibrate, sc); 3807 } 3808 3809 static int 3810 bwi_calc_rssi(struct bwi_softc *sc, const struct bwi_rxbuf_hdr *hdr) 3811 { 3812 struct bwi_mac *mac; 3813 3814 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 3815 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 3816 mac = (struct bwi_mac *)sc->sc_cur_regwin; 3817 3818 return bwi_rf_calc_rssi(mac, hdr); 3819 } 3820 3821 static int 3822 bwi_calc_noise(struct bwi_softc *sc) 3823 { 3824 struct bwi_mac *mac; 3825 3826 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC, 3827 ("current regwin type %d", sc->sc_cur_regwin->rw_type)); 3828 mac = (struct bwi_mac *)sc->sc_cur_regwin; 3829 3830 return bwi_rf_calc_noise(mac); 3831 } 3832 3833 static __inline uint8_t 3834 bwi_ofdm_plcp2rate(const uint32_t *plcp0) 3835 { 3836 uint32_t plcp; 3837 uint8_t plcp_rate; 3838 3839 plcp = le32toh(*plcp0); 3840 plcp_rate = __SHIFTOUT(plcp, IEEE80211_OFDM_PLCP_RATE_MASK); 3841 return ieee80211_plcp2rate(plcp_rate, IEEE80211_T_OFDM); 3842 } 3843 3844 static __inline uint8_t 3845 bwi_ds_plcp2rate(const struct ieee80211_ds_plcp_hdr *hdr) 3846 { 3847 return ieee80211_plcp2rate(hdr->i_signal, IEEE80211_T_DS); 3848 } 3849 3850 static void 3851 bwi_rx_radiotap(struct bwi_softc *sc, struct mbuf *m, 3852 struct bwi_rxbuf_hdr *hdr, const void *plcp, int rate, int rssi, int noise) 3853 { 3854 const struct ieee80211_frame_min *wh; 3855 3856 sc->sc_rx_th.wr_flags = IEEE80211_RADIOTAP_F_FCS; 3857 if (htole16(hdr->rxh_flags1) & BWI_RXH_F1_SHPREAMBLE) 3858 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE; 3859 3860 wh = mtod(m, const struct ieee80211_frame_min *); 3861 if (wh->i_fc[1] & IEEE80211_FC1_WEP) 3862 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_WEP; 3863 3864 sc->sc_rx_th.wr_tsf = hdr->rxh_tsf; /* No endian convertion */ 3865 sc->sc_rx_th.wr_rate = rate; 3866 sc->sc_rx_th.wr_antsignal = rssi; 3867 sc->sc_rx_th.wr_antnoise = noise; 3868 } 3869 3870 static void 3871 bwi_led_attach(struct bwi_softc *sc) 3872 { 3873 const uint8_t *led_act = NULL; 3874 uint16_t gpio, val[BWI_LED_MAX]; 3875 int i; 3876 3877 #define N(arr) (int)(sizeof(arr) / sizeof(arr[0])) 3878 3879 for (i = 0; i < N(bwi_vendor_led_act); ++i) { 3880 if (sc->sc_pci_subvid == bwi_vendor_led_act[i].vid) { 3881 led_act = bwi_vendor_led_act[i].led_act; 3882 break; 3883 } 3884 } 3885 if (led_act == NULL) 3886 led_act = bwi_default_led_act; 3887 3888 #undef N 3889 3890 gpio = bwi_read_sprom(sc, BWI_SPROM_GPIO01); 3891 val[0] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_0); 3892 val[1] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_1); 3893 3894 gpio = bwi_read_sprom(sc, BWI_SPROM_GPIO23); 3895 val[2] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_2); 3896 val[3] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_3); 3897 3898 for (i = 0; i < BWI_LED_MAX; ++i) { 3899 struct bwi_led *led = &sc->sc_leds[i]; 3900 3901 if (val[i] == 0xff) { 3902 led->l_act = led_act[i]; 3903 } else { 3904 if (val[i] & BWI_LED_ACT_LOW) 3905 led->l_flags |= BWI_LED_F_ACTLOW; 3906 led->l_act = __SHIFTOUT(val[i], BWI_LED_ACT_MASK); 3907 } 3908 led->l_mask = (1 << i); 3909 3910 if (led->l_act == BWI_LED_ACT_BLINK_SLOW || 3911 led->l_act == BWI_LED_ACT_BLINK_POLL || 3912 led->l_act == BWI_LED_ACT_BLINK) { 3913 led->l_flags |= BWI_LED_F_BLINK; 3914 if (led->l_act == BWI_LED_ACT_BLINK_POLL) 3915 led->l_flags |= BWI_LED_F_POLLABLE; 3916 else if (led->l_act == BWI_LED_ACT_BLINK_SLOW) 3917 led->l_flags |= BWI_LED_F_SLOW; 3918 3919 if (sc->sc_blink_led == NULL) { 3920 sc->sc_blink_led = led; 3921 if (led->l_flags & BWI_LED_F_SLOW) 3922 BWI_LED_SLOWDOWN(sc->sc_led_idle); 3923 } 3924 } 3925 3926 DPRINTF(sc, BWI_DBG_LED | BWI_DBG_ATTACH, 3927 "%dth led, act %d, lowact %d\n", i, 3928 led->l_act, led->l_flags & BWI_LED_F_ACTLOW); 3929 } 3930 callout_init_mtx(&sc->sc_led_blink_ch, &sc->sc_mtx, 0); 3931 } 3932 3933 static __inline uint16_t 3934 bwi_led_onoff(const struct bwi_led *led, uint16_t val, int on) 3935 { 3936 if (led->l_flags & BWI_LED_F_ACTLOW) 3937 on = !on; 3938 if (on) 3939 val |= led->l_mask; 3940 else 3941 val &= ~led->l_mask; 3942 return val; 3943 } 3944 3945 static void 3946 bwi_led_newstate(struct bwi_softc *sc, enum ieee80211_state nstate) 3947 { 3948 struct ifnet *ifp = sc->sc_ifp; 3949 struct ieee80211com *ic = ifp->if_l2com; 3950 uint16_t val; 3951 int i; 3952 3953 if (nstate == IEEE80211_S_INIT) { 3954 callout_stop(&sc->sc_led_blink_ch); 3955 sc->sc_led_blinking = 0; 3956 } 3957 3958 if ((ic->ic_ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 3959 return; 3960 3961 val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL); 3962 for (i = 0; i < BWI_LED_MAX; ++i) { 3963 struct bwi_led *led = &sc->sc_leds[i]; 3964 int on; 3965 3966 if (led->l_act == BWI_LED_ACT_UNKN || 3967 led->l_act == BWI_LED_ACT_NULL) 3968 continue; 3969 3970 if ((led->l_flags & BWI_LED_F_BLINK) && 3971 nstate != IEEE80211_S_INIT) 3972 continue; 3973 3974 switch (led->l_act) { 3975 case BWI_LED_ACT_ON: /* Always on */ 3976 on = 1; 3977 break; 3978 case BWI_LED_ACT_OFF: /* Always off */ 3979 case BWI_LED_ACT_5GHZ: /* TODO: 11A */ 3980 on = 0; 3981 break; 3982 default: 3983 on = 1; 3984 switch (nstate) { 3985 case IEEE80211_S_INIT: 3986 on = 0; 3987 break; 3988 case IEEE80211_S_RUN: 3989 if (led->l_act == BWI_LED_ACT_11G && 3990 ic->ic_curmode != IEEE80211_MODE_11G) 3991 on = 0; 3992 break; 3993 default: 3994 if (led->l_act == BWI_LED_ACT_ASSOC) 3995 on = 0; 3996 break; 3997 } 3998 break; 3999 } 4000 4001 val = bwi_led_onoff(led, val, on); 4002 } 4003 CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val); 4004 } 4005 static void 4006 bwi_led_event(struct bwi_softc *sc, int event) 4007 { 4008 struct bwi_led *led = sc->sc_blink_led; 4009 int rate; 4010 4011 if (event == BWI_LED_EVENT_POLL) { 4012 if ((led->l_flags & BWI_LED_F_POLLABLE) == 0) 4013 return; 4014 if (ticks - sc->sc_led_ticks < sc->sc_led_idle) 4015 return; 4016 } 4017 4018 sc->sc_led_ticks = ticks; 4019 if (sc->sc_led_blinking) 4020 return; 4021 4022 switch (event) { 4023 case BWI_LED_EVENT_RX: 4024 rate = sc->sc_rx_rate; 4025 break; 4026 case BWI_LED_EVENT_TX: 4027 rate = sc->sc_tx_rate; 4028 break; 4029 case BWI_LED_EVENT_POLL: 4030 rate = 0; 4031 break; 4032 default: 4033 panic("unknown LED event %d\n", event); 4034 break; 4035 } 4036 bwi_led_blink_start(sc, bwi_led_duration[rate].on_dur, 4037 bwi_led_duration[rate].off_dur); 4038 } 4039 4040 static void 4041 bwi_led_blink_start(struct bwi_softc *sc, int on_dur, int off_dur) 4042 { 4043 struct bwi_led *led = sc->sc_blink_led; 4044 uint16_t val; 4045 4046 val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL); 4047 val = bwi_led_onoff(led, val, 1); 4048 CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val); 4049 4050 if (led->l_flags & BWI_LED_F_SLOW) { 4051 BWI_LED_SLOWDOWN(on_dur); 4052 BWI_LED_SLOWDOWN(off_dur); 4053 } 4054 4055 sc->sc_led_blinking = 1; 4056 sc->sc_led_blink_offdur = off_dur; 4057 4058 callout_reset(&sc->sc_led_blink_ch, on_dur, bwi_led_blink_next, sc); 4059 } 4060 4061 static void 4062 bwi_led_blink_next(void *xsc) 4063 { 4064 struct bwi_softc *sc = xsc; 4065 uint16_t val; 4066 4067 val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL); 4068 val = bwi_led_onoff(sc->sc_blink_led, val, 0); 4069 CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val); 4070 4071 callout_reset(&sc->sc_led_blink_ch, sc->sc_led_blink_offdur, 4072 bwi_led_blink_end, sc); 4073 } 4074 4075 static void 4076 bwi_led_blink_end(void *xsc) 4077 { 4078 struct bwi_softc *sc = xsc; 4079 sc->sc_led_blinking = 0; 4080 } 4081 4082 static void 4083 bwi_restart(void *xsc, int pending) 4084 { 4085 struct bwi_softc *sc = xsc; 4086 struct ifnet *ifp = sc->sc_ifp; 4087 4088 if_printf(ifp, "%s begin, help!\n", __func__); 4089 BWI_LOCK(sc); 4090 bwi_init_statechg(xsc, 0); 4091 #if 0 4092 bwi_start_locked(ifp); 4093 #endif 4094 BWI_UNLOCK(sc); 4095 } 4096